Re: Hardware instrumentation presentation
Someone from IBM sent me a couple of presentations, some of which I had contributed to. It covers things like *instruction decode, address generate, execute, put away*; parallelism. How L R4,VALUE L R5,0(R4) this has to wait until the previous load has finished, but other instructions can be processed in parallel. Data from the L1 cache is faster than data from a different book. Dont have 2 threads running concurrently sharing the same cache block for private data. All good stuff Colin On Wed, 1 Mar 2023 at 17:59, Colin Paice wrote: > I've been asked to give a talk on performance to a University Computing > department. > > I know the z hardware has in builtin instrumentation which allows you to > see where the delays were for a particular instruction. For example this > load instruction got data from the L3 cache and it took x nano seconds. > > Is there a presentation on this? > > I remember seeing a presentation (it may have been IBM confidential) > showing that a Load could be slow, if the data was in a the cache in a book > 3 ft away, compared to it being in the cache on the chip. > Also the second time round a loop is faster than the first time because > the instructions are in the instruction cache. > > This was all mind blowing stuff! > > Colin > -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Hardware instrumentation presentation
Colin, you looking for a presentation on performance (to whatever level) or on hardware instrumentation service (the z/OS name - feature name: measurement and counter) There are a few I have seen/attended. So there are not IBM confidential and should be locatable on the net. About HIS I have not seen anything. But there is Phoenix which has a product that explores/utilises/extents HIS. Martin -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Hardware instrumentation presentation
Even better, try John Burg of the 'Washington Systems Center '. He used to have presentations on the TechDoc website and also presented at SHARE. Sent from Outlook for Android<https://aka.ms/AAb9ysg> From: IBM Mainframe Discussion List on behalf of Lennie Dymoke-Bradshaw <032fff1be9b4-dmarc-requ...@listserv.ua.edu> Sent: Thursday, March 2, 2023 1:10:47 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Hardware instrumentation presentation I recommend you speak to Martin Packer at IBM. Lennie -Original Message- From: IBM Mainframe Discussion List On Behalf Of Colin Paice Sent: 01 March 2023 18:00 To: IBM-MAIN@LISTSERV.UA.EDU Subject: Hardware instrumentation presentation I've been asked to give a talk on performance to a University Computing department. I know the z hardware has in builtin instrumentation which allows you to see where the delays were for a particular instruction. For example this load instruction got data from the L3 cache and it took x nano seconds. Is there a presentation on this? I remember seeing a presentation (it may have been IBM confidential) showing that a Load could be slow, if the data was in a the cache in a book 3 ft away, compared to it being in the cache on the chip. Also the second time round a loop is faster than the first time because the instructions are in the instruction cache. This was all mind blowing stuff! Colin -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Hardware instrumentation presentation
I recommend you speak to Martin Packer at IBM. Lennie -Original Message- From: IBM Mainframe Discussion List On Behalf Of Colin Paice Sent: 01 March 2023 18:00 To: IBM-MAIN@LISTSERV.UA.EDU Subject: Hardware instrumentation presentation I've been asked to give a talk on performance to a University Computing department. I know the z hardware has in builtin instrumentation which allows you to see where the delays were for a particular instruction. For example this load instruction got data from the L3 cache and it took x nano seconds. Is there a presentation on this? I remember seeing a presentation (it may have been IBM confidential) showing that a Load could be slow, if the data was in a the cache in a book 3 ft away, compared to it being in the cache on the chip. Also the second time round a loop is faster than the first time because the instructions are in the instruction cache. This was all mind blowing stuff! Colin -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Hardware instrumentation presentation
I've been asked to give a talk on performance to a University Computing department. I know the z hardware has in builtin instrumentation which allows you to see where the delays were for a particular instruction. For example this load instruction got data from the L3 cache and it took x nano seconds. Is there a presentation on this? I remember seeing a presentation (it may have been IBM confidential) showing that a Load could be slow, if the data was in a the cache in a book 3 ft away, compared to it being in the cache on the chip. Also the second time round a loop is faster than the first time because the instructions are in the instruction cache. This was all mind blowing stuff! Colin -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
