Re: [Intel-gfx] [ANNOUNCE] xf86-video-intel 2.16.902
On Mon, Nov 14, 2011 at 08:16:35 +0100, tino.keitel+x...@tikei.de wrote: On Sun, Nov 13, 2011 at 11:27:29 +, Chris Wilson wrote: This is the second release candidate in preparation for the upcoming 2.17.0 release. We will appreciate any feedback we can get from Hi, this does not show up in git://anongit.freedesktop.org/git/xorg/driver/xf86-video-intel yet. Is this the correct repository? Oops, I checked the wrong remote in my git tree. Sorry for the noise. Regards, Tino ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Mon, 14 Nov 2011 13:01:36 +0800, Zhigang Gong
zhigang.g...@linux.intel.com wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Friday, November 11, 2011 9:13 PM
To: Zhigang Gong; intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Fri, 11 Nov 2011 18:52:11 +0800, Zhigang Gong
zhigang.g...@linux.intel.com wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Friday, November 11, 2011 5:12 PM
To: Zhigang Gong; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Fri, 11 Nov 2011 16:31:20 +0800, Zhigang Gong
zhigang.g...@linux.intel.com wrote:
@@ -965,6 +969,9 @@ void
intel_uxa_block_handler(intel_screen_private *intel)
* framebuffer until significantly later.
*/
intel_flush_rendering(intel);
+#ifdef GLAMOR
+ intel_glamor_block_handler(intel);
+#endif
}
I suspect this is the wrong way around as we are not flushing the
render cache of glamor's rendering to the scanout until the next block
handler.
I don't understand here. Would you please explain more detail? Thanks.
Whenever we render, the data ends up in the Render Cache and needs to
be flushed out to memory before it is coherent with the CPU or in this
case the Display Engine (i.e. scanout).
intel_flush_rendering() does two tasks. The first is to submit any pending
batch, and the second is to flush the Render Cache so that the
modifications land on the scanout in a timely manner. It is probably best
if
those two tasks were separated so that we do:
intel_uxa_block_handler(intel); // flush the UXA batch
intel_glamor_block_handler(intel); // flush the GL batch
intel_flush_rendering(intel); // flush the RenderCache to scanout
However, you can simply rearrange the code and achieve it with the
existing functions:
intel_glamor_block_handler(intel); // mark the front bo as dirty as
needbe
intel_flush_rendering(intel); // flush UXA batch along with RenderCache
Thanks for the explanation here. But I still don't think the original code
is wrong
regard to this cache flushing issue. Here is my analysis:
intel_glamor_block_handler calls to glFlush(), and glFlush is similar with
the
intel_flush_rendering, it calls intel_flush to flush the batch buffers and
then
call intel_flush_frontbuffer to flush the frontbuffer which flushes the scan
out
buffer. So when the screen pixmap is accessed by glamor, and after we call
intel_glamor_block_handler, the Display Engine should see the correct data
Right?
No.
glFlush() does call intel_flush_front(). However that in turn calls
dri2-flushFrontBuffer which is implemented for EGL with
static void
dri2_flush_front_buffer(__DRIdrawable * driDrawable, void *loaderPrivate)
{
/* FIXME: Does EGL support front buffer rendering at all? */
}
Neither does it perform the intended action via GLX (except that
flushing the scanout is handled by the DDX as a normal part of its
operation).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
At Sat, 12 Nov 2011 10:27:26 +0800, Wu Fengguang wrote: (snip) And I'm not sure whether HDMI audio is played while DPMS is off. I haven't tested it. It will go silence on DPMS. I noticed this while doing long term HDMI audio playback tests. This should better be fixed in future on the graphics side. Hm, but I wonder what could be done alternatively. Hopefully there is a register for video-only control... There may be some mode that can keep video off while still keep minimal signals to play HDMI sound? Let's hope :) Looks very possible, here is the clue of hardware support: TRANS_DP_CTL - Transcoder DisplayPort Control bit 26: Transcoder DP Audio Only Mode Good to know! But what about HDMI? thanks, Takashi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Monday, November 14, 2011 5:07 PM
To: Zhigang Gong; intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Mon, 14 Nov 2011 13:01:36 +0800, Zhigang Gong
zhigang.g...@linux.intel.com wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Friday, November 11, 2011 9:13 PM
To: Zhigang Gong; intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Fri, 11 Nov 2011 18:52:11 +0800, Zhigang Gong
zhigang.g...@linux.intel.com wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Friday, November 11, 2011 5:12 PM
To: Zhigang Gong; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Fri, 11 Nov 2011 16:31:20 +0800, Zhigang Gong
zhigang.g...@linux.intel.com wrote:
@@ -965,6 +969,9 @@ void
intel_uxa_block_handler(intel_screen_private *intel)
* framebuffer until significantly later.
*/
intel_flush_rendering(intel);
+#ifdef GLAMOR
+ intel_glamor_block_handler(intel);
+#endif
}
I suspect this is the wrong way around as we are not flushing
the render cache of glamor's rendering to the scanout until the
next block
handler.
I don't understand here. Would you please explain more detail?
Thanks.
Whenever we render, the data ends up in the Render Cache and
needs
to be flushed out to memory before it is coherent with the CPU or in
this case the Display Engine (i.e. scanout).
intel_flush_rendering() does two tasks. The first is to submit any
pending batch, and the second is to flush the Render Cache so that
the modifications land on the scanout in a timely manner. It is
probably best
if
those two tasks were separated so that we do:
intel_uxa_block_handler(intel); // flush the UXA batch
intel_glamor_block_handler(intel); // flush the GL batch
intel_flush_rendering(intel); // flush the RenderCache to scanout
However, you can simply rearrange the code and achieve it with the
existing functions:
intel_glamor_block_handler(intel); // mark the front bo as dirty
as needbe
intel_flush_rendering(intel); // flush UXA batch along with
RenderCache
Thanks for the explanation here. But I still don't think the original
code is wrong regard to this cache flushing issue. Here is my
analysis:
intel_glamor_block_handler calls to glFlush(), and glFlush is similar
with the intel_flush_rendering, it calls intel_flush to flush the
batch buffers and then call intel_flush_frontbuffer to flush the
frontbuffer which flushes the scan out buffer. So when the screen
pixmap is accessed by glamor, and after we call
intel_glamor_block_handler, the Display Engine should see the correct
data
Right?
No.
glFlush() does call intel_flush_front(). However that in turn calls
dri2-flushFrontBuffer which is implemented for EGL with
static void
dri2_flush_front_buffer(__DRIdrawable * driDrawable, void
*loaderPrivate) {
/* FIXME: Does EGL support front buffer rendering at all? */ }
Neither does it perform the intended action via GLX (except that flushing
the scanout is handled by the DDX as a normal part of its operation).
You are right. EGL layer will not do a really front buffer flushing. We have
to
let it be done in DDX layer. In my version 2 patch set, I already rearrange
the
code sequence as you suggested please review it again. The remaining work
for this issue is that I need to add new code to set the needs_flush
according
to the access type of glamor. Will do that soon.
Thanks.
-Chris
--
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[Intel-gfx] [PATCH 1/4] glamor: Added flags to indicate whether to use glamor in UXA.
Added two new flags UXA_USE_GLAMOR and UXA_USE_GLAMOR_ONLY.
When UXA_USE_GLAMOR or UXA_USE_GLAMOR_ONLY is set, then it
will use GLAMOR to perform rendering operations by default.
If GLAMOR failed to accelerate the operation and UXA_USE_GLAMOR
is set, it then continue to the normal UXA code path to do
the rendering. If the UXA_USE_GLAMOR_ONLY is set, it then
jump to fallback path directly and avoid the UXA acceleration
code.
Signed-off-by: Zhigang Gong zhigang.g...@linux.intel.com
---
uxa/uxa.h | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/uxa/uxa.h b/uxa/uxa.h
index e001c53..21e6f2a 100644
--- a/uxa/uxa.h
+++ b/uxa/uxa.h
@@ -543,6 +543,22 @@ typedef struct _UxaDriver {
*/
#define UXA_TWO_BITBLT_DIRECTIONS (1 2)
+/**
+ * UXA_USE_GLAMOR indicates to use glamor acceleration to perform rendering
+ * as first choice. And if glamor fail to accelerate the rendering, then goto
+ * normal path to do the rendering.
+ */
+#define UXA_USE_GLAMOR (1 3)
+
+/**
+ * UXA_USE_GLAMOR_ONLY indicates to use glamor acceleration to perform
rendering.
+ * And if glamor fail to accelerate the rendering, then goto fallback to
+ * use CPU to do the rendering.
+ */
+#define UXA_USE_GLAMOR_ONLY(1 4)
+
+#define UXA_GLAMOR_FLAGS (UXA_USE_GLAMOR | UXA_USE_GLAMOR_ONLY)
+
/** @} */
/** @name UXA CreatePixmap hint flags
--
1.7.4.4
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[Intel-gfx] [PATCH 2/4] glamor: Added new data element to track uxa flags in intel structure.
As uxa_driver may be released before the last call to freeScreen
and destroy the last pixmap, we have to introduce a new flag in
intel structure to indicate whether we are using GLAMOR. This
intel-uxa_flag is a clone of intel-uxa_driver-flags element.
Signed-off-by: Zhigang Gong zhigang.g...@linux.intel.com
---
src/intel.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/intel.h b/src/intel.h
index 3b3f87d..b24aa02 100644
--- a/src/intel.h
+++ b/src/intel.h
@@ -318,6 +318,7 @@ typedef struct intel_screen_private {
void (*batch_commit_notify) (struct intel_screen_private *intel);
uxa_driver_t *uxa_driver;
+ int uxa_flags;
Bool need_sync;
int accel_pixmap_offset_alignment;
int accel_max_x;
--
1.7.4.4
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[Intel-gfx] [PATCH 3/4] glamor: check a flag to indicate whether enable GLAMOR.
According to Chris's comments, this commit try to
elminate #ifdef from the body of the code if possible.
We check the flags to determine whether enable GLAMOR
at runtime, rather than check the MACRO during the compile
time.
Signed-off-by: Zhigang Gong zhigang.g...@linux.intel.com
---
src/intel_driver.c | 12 ++--
src/intel_uxa.c| 38 --
uxa/uxa-accel.c| 16 ++--
3 files changed, 40 insertions(+), 26 deletions(-)
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 63f83e7..bd57694 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -1127,9 +1127,10 @@ static void I830FreeScreen(int scrnIndex, int flags)
{
ScrnInfoPtr scrn = xf86Screens[scrnIndex];
intel_screen_private *intel = intel_get_screen_private(scrn);
-#ifdef GLAMOR
- intel_glamor_free_screen(scrnIndex, flags);
-#endif
+
+ if (intel-uxa_flags UXA_GLAMOR_FLAGS)
+ intel_glamor_free_screen(scrnIndex, flags);
+
if (intel) {
intel_mode_fini(intel);
intel_close_drm_master(intel);
@@ -1209,9 +1210,8 @@ static Bool I830CloseScreen(int scrnIndex, ScreenPtr
screen)
DeleteCallback(FlushCallback, intel_flush_callback, scrn);
-#ifdef GLAMOR
- intel_glamor_close_screen(screen);
-#endif
+ if (intel-uxa_flags UXA_GLAMOR_FLAGS)
+ intel_glamor_close_screen(screen);
if (intel-uxa_driver) {
uxa_driver_fini(screen);
diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index 3bbe531..a069980 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -968,9 +968,8 @@ void intel_uxa_block_handler(intel_screen_private *intel)
* and beyond rendering results may not hit the
* framebuffer until significantly later.
*/
-#ifdef GLAMOR
- intel_glamor_block_handler(intel);
-#endif
+ if (intel-uxa_flags UXA_GLAMOR_FLAGS)
+ intel_glamor_block_handler(intel);
intel_flush_rendering(intel);
}
@@ -1102,10 +1101,11 @@ intel_uxa_create_pixmap(ScreenPtr screen, int w, int h,
int depth,
list_init(priv-batch);
list_init(priv-flush);
intel_set_pixmap_private(pixmap, priv);
-#ifdef GLAMOR
- priv-pinned = 1;
- intel_glamor_create_textured_pixmap(pixmap);
-#endif
+
+ if (intel-uxa_flags UXA_GLAMOR_FLAGS) {
+ priv-pinned = 1;
+ intel_glamor_create_textured_pixmap(pixmap);
+ }
}
return pixmap;
@@ -1113,10 +1113,11 @@ intel_uxa_create_pixmap(ScreenPtr screen, int w, int h,
int depth,
static Bool intel_uxa_destroy_pixmap(PixmapPtr pixmap)
{
+ ScrnInfoPtr scrn = xf86Screens[pixmap-drawable.pScreen-myNum];
+ intel_screen_private *intel = intel_get_screen_private(scrn);
if (pixmap-refcnt == 1) {
-#ifdef GLAMOR
- intel_glamor_destroy_pixmap(pixmap);
-#endif
+ if (intel-uxa_flags UXA_GLAMOR_FLAGS)
+ intel_glamor_destroy_pixmap(pixmap);
intel_set_pixmap_bo(pixmap, NULL);
}
fbDestroyPixmap(pixmap);
@@ -1149,10 +1150,10 @@ Bool intel_uxa_create_screen_resources(ScreenPtr screen)
scrn-displayWidth = intel-front_pitch / intel-cpp;
}
-#ifdef GLAMOR
- if (!intel_glamor_create_screen_resources(screen))
+ if ((intel-uxa_flags UXA_GLAMOR_FLAGS)
+!intel_glamor_create_screen_resources(screen))
return FALSE;
-#endif
+
return TRUE;
}
@@ -1315,7 +1316,16 @@ Bool intel_uxa_init(ScreenPtr screen)
uxa_set_fallback_debug(screen, intel-fallback_debug);
uxa_set_force_fallback(screen, intel-force_fallback);
#ifdef GLAMOR
- intel_glamor_init(screen);
+ if (intel_glamor_init(screen)) {
+ xf86DrvMsg(scrn-scrnIndex, X_INFO,
+ Intel GLAMOR initialization successfully.\n);
+ intel-uxa_driver-flags |= UXA_USE_GLAMOR;
+ intel-uxa_flags = intel-uxa_driver-flags;
+ } else {
+ xf86DrvMsg(scrn-scrnIndex, X_WARNING,
+ Intel GLAMOR initialization failed,
+ change to use standard UXA.\n);
+ }
#endif
return TRUE;
}
diff --git a/uxa/uxa-accel.c b/uxa/uxa-accel.c
index 18fa63b..b2e5347 100644
--- a/uxa/uxa-accel.c
+++ b/uxa/uxa-accel.c
@@ -52,10 +52,12 @@ uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n,
int nbox;
int x1, x2, y;
int off_x, off_y;
-#ifdef GLAMOR
- if (glamor_fill_spans_nf(pDrawable, pGC, n, ppt, pwidth, fSorted))
+
+ if ((uxa_screen-info-flags UXA_GLAMOR_FLAGS)
+(glamor_fill_spans_nf(pDrawable, pGC, n, ppt, pwidth, fSorted)))
return;
-#endif
+ else if(uxa_screen-info-flags UXA_USE_GLAMOR_ONLY)
+ goto fallback;
if
[Intel-gfx] [PATCH 4/4] glamor: Silence compilation warnings.
As we removed those #ifdef from the body of the code, some
functions are referenced even we haven't defined the GLAMOR
though those functions are never be called at run time. We
still need to inclue those prototypes or make a fake function
to silcent the compilation warnings.
Signed-off-by: Zhigang Gong zhigang.g...@linux.intel.com
---
src/intel_driver.c |2 --
src/intel_uxa.c|2 --
uxa/uxa-accel.c|5 -
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/intel_driver.c b/src/intel_driver.c
index bd57694..0f528f3 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -75,9 +75,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include i915_drm.h
#include xf86drmMode.h
-#ifdef GLAMOR
#include intel_glamor.h
-#endif
/* *INDENT-OFF* */
/*
diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index a069980..81d5ec0 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -40,9 +40,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include string.h
#include errno.h
-#ifdef GLAMOR
#include intel_glamor.h
-#endif
static const int I830CopyROP[16] = {
ROP_0, /* GXclear */
diff --git a/uxa/uxa-accel.c b/uxa/uxa-accel.c
index b2e5347..5b27aaa 100644
--- a/uxa/uxa-accel.c
+++ b/uxa/uxa-accel.c
@@ -38,7 +38,10 @@
#ifdef GLAMOR
#include glamor.h
-#endif
+#else
+#define glamor_fill_spans_nf(...) FALSE
+#define glamor_poly_fill_rect_nf(...) FALSE
+#endif
static void
uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n,
--
1.7.4.4
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Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
On Mon, Nov 14, 2011 at 05:45:12PM +0800, Takashi Iwai wrote: At Sat, 12 Nov 2011 10:27:26 +0800, Wu Fengguang wrote: (snip) And I'm not sure whether HDMI audio is played while DPMS is off. I haven't tested it. It will go silence on DPMS. I noticed this while doing long term HDMI audio playback tests. This should better be fixed in future on the graphics side. Hm, but I wonder what could be done alternatively. Hopefully there is a register for video-only control... There may be some mode that can keep video off while still keep minimal signals to play HDMI sound? Let's hope :) Looks very possible, here is the clue of hardware support: TRANS_DP_CTL - Transcoder DisplayPort Control bit 26: Transcoder DP Audio Only Mode Good to know! But what about HDMI? I'm not sure.. There are no corresponding TRANS_HDMI_CTL registers... Thanks, Fengguang ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] glamor: check a flag to indicate whether enable GLAMOR.
On Mon, 14 Nov 2011 20:09:03 +0800, Zhigang Gong zhigang.g...@linux.intel.com wrote: According to Chris's comments, this commit try to elminate #ifdef from the body of the code if possible. We check the flags to determine whether enable GLAMOR at runtime, rather than check the MACRO during the compile time. I was thinking more along the lines of pushing the actual check out of I830CloseScreen (and friends) and into the intel_glamor routines. That way the interface to glamor is fairly self-contained and the existing code can be gradually whittled away until it is simply a call into intel_glamor, at which point we can remove the existing layer. Inside uxa, the inline checks are indeed better as this layer should be tightly integrated with the available acceleration methods. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: track sprite coverage and disable primary plane if possible
To save power when the sprite is full screen, we can disable the primary
plane on the same pipe. Track the sprite status and enable/disable the
primary opportunistically.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_drv.h|3 ++
drivers/gpu/drm/i915/intel_sprite.c | 67 +++
2 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 68ef060..4ea3f68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -180,6 +180,7 @@ struct intel_plane {
struct drm_plane base;
enum pipe pipe;
struct drm_i915_gem_object *obj;
+ bool primary_disabled;
int max_downscale;
u32 lut_r[1024], lut_g[1024], lut_b[1024];
void (*update_plane)(struct drm_plane *plane,
@@ -192,6 +193,8 @@ struct intel_plane {
void (*disable_plane)(struct drm_plane *plane);
int (*update_destkey)(struct drm_plane *plane, u32 value);
u32 (*get_destkey)(struct drm_plane *plane);
+ void (*enable_primary)(struct drm_crtc *crtc);
+ void (*disable_primary)(struct drm_crtc *crtc);
};
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index b470e9b..f63e2a3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -49,6 +49,28 @@
*/
static void
+ivb_enable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
+}
+
+static void
+ivb_disable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) ~DISPLAY_PLANE_ENABLE);
+}
+
+static void
ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
@@ -181,6 +203,28 @@ ivb_get_destkey(struct drm_plane *plane)
}
static void
+snb_enable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
+}
+
+static void
+snb_disable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) ~DISPLAY_PLANE_ENABLE);
+}
+
+static void
snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
@@ -394,9 +438,23 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_plane-obj = obj;
+ /*
+* Be sure to re-enable the primary before the sprite is no longer
+* covering it fully.
+*/
+ if (!disable_primary intel_plane-primary_disabled) {
+ intel_plane-enable_primary(crtc);
+ intel_plane-primary_disabled = false;
+ }
+
intel_plane-update_plane(plane, fb, obj, crtc_x, crtc_y,
crtc_w, crtc_h, x, y, src_w, src_h);
+ if (disable_primary) {
+ intel_plane-disable_primary(crtc);
+ intel_plane-primary_disabled = true;
+ }
+
/* Unpin old obj after new one is active to avoid ugliness */
if (old_obj) {
/*
@@ -427,6 +485,11 @@ intel_disable_plane(struct drm_plane *plane)
struct intel_plane *intel_plane = to_intel_plane(plane);
int ret = 0;
+ if (intel_plane-primary_disabled) {
+ intel_plane-enable_primary(plane-crtc);
+ intel_plane-primary_disabled = false;
+ }
+
intel_plane-disable_plane(plane);
if (!intel_plane-obj)
@@ -550,12 +613,16 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
intel_plane-disable_plane = snb_disable_plane;
intel_plane-update_destkey = snb_update_destkey;
intel_plane-get_destkey = snb_get_destkey;
+ intel_plane-enable_primary = ivb_enable_primary;
+ intel_plane-disable_primary = ivb_disable_primary;
} else
[Intel-gfx] [PATCH 1/3] drm/i915: add SNB and IVB video sprite support v2
The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core sprite support functions. v2: use drm specific fourcc header and defines v3: address Daniel's comments: - don't take struct mutex around register access (only needed for regs in the GT power well) - don't hold struct mutex across vblank waits - fix up update_plane API (pass obj instead of GTT offset) - add interlaced defines for sprite regs - drop unnecessary 'reg' variables - comment double buffered reg flushing Also fix w/h confusion when writing the scaling reg. For this version, I tested DPMS since it came up in the last review; DPMS off/on works ok when a video player is working under X, but for power saving we'll probably want to do something smarter. I'll leave that for a separate patch on top. Likewise with the refcounting/fb layer handling, which are really separate cleanups. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/i915_reg.h | 127 ++ drivers/gpu/drm/i915/intel_display.c | 45 +++-- drivers/gpu/drm/i915/intel_drv.h | 23 ++ drivers/gpu/drm/i915/intel_fb.c |6 + drivers/gpu/drm/i915/intel_sprite.c | 425 ++ 6 files changed, 609 insertions(+), 18 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_sprite.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 0ae6a7c..808b255 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ intel_dvo.o \ intel_ringbuffer.o \ intel_overlay.o \ + intel_sprite.o \ intel_opregion.o \ dvo_ch7xxx.o \ dvo_ch7017.o \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5a09416..7929a55 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2450,6 +2450,8 @@ #define WM3_LP_ILK 0x45110 #define WM3_LP_EN (131) #define WM1S_LP_ILK0x45120 +#define WM2S_LP_IVB0x45124 +#define WM3S_LP_IVB0x45128 #define WM1S_LP_EN(131) /* Memory latency timer register */ @@ -2666,6 +2668,131 @@ #define _DSPBSURF 0x7119C #define _DSPBTILEOFF 0x711A4 +/* Sprite A control */ +#define _DVSACNTR 0x72180 +#define DVS_ENABLE (131) +#define DVS_GAMMA_ENABLE (130) +#define DVS_PIXFORMAT_MASK (325) +#define DVS_FORMAT_YUV422(025) +#define DVS_FORMAT_RGBX101010(125) +#define DVS_FORMAT_RGBX888 (225) +#define DVS_FORMAT_RGBX161616(325) +#define DVS_SOURCE_KEY (122) +#define DVS_RGB_ORDER_RGBX (120) +#define DVS_YUV_BYTE_ORDER_MASK (316) +#define DVS_YUV_ORDER_YUYV (016) +#define DVS_YUV_ORDER_UYVY (116) +#define DVS_YUV_ORDER_YVYU (216) +#define DVS_YUV_ORDER_VYUY (316) +#define DVS_DEST_KEY (12) +#define DVS_TRICKLE_FEED_DISABLE (114) +#define DVS_TILED(110) +#define _DVSASTRIDE0x72188 +#define _DVSAPOS 0x7218c +#define _DVSASIZE 0x72190 +#define _DVSAKEYVAL0x72194 +#define _DVSAKEYMSK0x72198 +#define _DVSASURF 0x7219c +#define _DVSAKEYMAXVAL 0x721a0 +#define _DVSATILEOFF 0x721a4 +#define _DVSASURFLIVE 0x721ac +#define _DVSASCALE 0x72204 +#define DVS_SCALE_ENABLE (131) +#define DVS_FILTER_MASK (329) +#define DVS_FILTER_MEDIUM(029) +#define DVS_FILTER_ENHANCING (129) +#define DVS_FILTER_SOFTENING (229) +#define DVS_VERTICAL_OFFSET_HALF (128) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (127) +#define _DVSAGAMC 0x72300 + +#define _DVSBCNTR 0x73180 +#define _DVSBSTRIDE0x73188 +#define _DVSBPOS 0x7318c +#define _DVSBSIZE 0x73190 +#define _DVSBKEYVAL0x73194 +#define _DVSBKEYMSK0x73198 +#define _DVSBSURF 0x7319c +#define _DVSBKEYMAXVAL 0x731a0 +#define _DVSBTILEOFF 0x731a4 +#define _DVSBSURFLIVE 0x731ac +#define _DVSBSCALE 0x73204 +#define _DVSBGAMC 0x73300 + +#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) +#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) +#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) +#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) +#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) +#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) +#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) + +#define _SPRA_CTL 0x70280 +#define SPRITE_ENABLE(131) +#define SPRITE_GAMMA_ENABLE
[Intel-gfx] [PATCH 2/3] drm/i915: add destination color key support
Add new ioctls for getting and setting the current destination color
key. This allows for simple overlay display control by matching a color
key value in the primary plane before blending the overlay on top.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c |2 +
drivers/gpu/drm/i915/i915_reg.h |2 +
drivers/gpu/drm/i915/intel_drv.h|8 ++
drivers/gpu/drm/i915/intel_sprite.c | 146 +++
include/drm/i915_drm.h | 16
5 files changed, 174 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2eac955..0385a27 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2294,6 +2294,8 @@ struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl,
DRM_UNLOCKED),
DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+ DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_DESTKEY, intel_sprite_set_destkey,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+ DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_DESTKEY, intel_sprite_get_destkey,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
};
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7929a55..d486bab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2726,6 +2726,8 @@
#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
#define _SPRA_CTL 0x70280
#define SPRITE_ENABLE(131)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f91de00..68ef060 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -190,6 +190,8 @@ struct intel_plane {
uint32_t x, uint32_t y,
uint32_t src_w, uint32_t src_h);
void (*disable_plane)(struct drm_plane *plane);
+ int (*update_destkey)(struct drm_plane *plane, u32 value);
+ u32 (*get_destkey)(struct drm_plane *plane);
};
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
@@ -407,4 +409,10 @@ extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
+extern int intel_sprite_set_destkey(struct drm_device *dev, void *data,
+struct drm_file *file_priv);
+extern int intel_sprite_get_destkey(struct drm_device *dev, void *data,
+struct drm_file *file_priv);
+
+
#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index d8ae3e4..b470e9b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -99,6 +99,7 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
/* must disable */
sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
sprctl |= SPRITE_ENABLE;
+ sprctl |= SPRITE_DEST_KEY;
/* Sizes are 0 based */
src_w--;
@@ -140,6 +141,45 @@ ivb_disable_plane(struct drm_plane *plane)
POSTING_READ(SPRSURF(pipe));
}
+static int
+ivb_update_destkey(struct drm_plane *plane, u32 value)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_plane *intel_plane;
+ int ret = 0;
+
+ if (value 0xff)
+ return -EINVAL;
+
+ intel_plane = to_intel_plane(plane);
+
+ mutex_lock(dev-struct_mutex);
+ I915_WRITE(SPRKEYVAL(intel_plane-pipe), value);
+ I915_WRITE(SPRKEYMSK(intel_plane-pipe), 0xff);
+ POSTING_READ(SPRKEYMSK(intel_plane-pipe));
+ mutex_unlock(dev-struct_mutex);
+
+ return ret;
+}
+
+static u32
+ivb_get_destkey(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_plane *intel_plane;
+ u32 value;
+
+ intel_plane = to_intel_plane(plane);
+
+ mutex_lock(dev-struct_mutex);
+ value = I915_READ(SPRKEYVAL(intel_plane-pipe));
+ mutex_unlock(dev-struct_mutex);
+
+ return value;
+}
+
static void
snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
@@ -228,6
[Intel-gfx] [PATCH 2/3] drm/i915: add destination color key support
Add new ioctls for getting and setting the current destination color
key. This allows for simple overlay display control by matching a color
key value in the primary plane before blending the overlay on top.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c |2 +
drivers/gpu/drm/i915/i915_reg.h |2 +
drivers/gpu/drm/i915/intel_drv.h|8 ++
drivers/gpu/drm/i915/intel_sprite.c | 146 +++
include/drm/i915_drm.h | 16
5 files changed, 174 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2eac955..0385a27 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2294,6 +2294,8 @@ struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl,
DRM_UNLOCKED),
DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+ DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_DESTKEY, intel_sprite_set_destkey,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+ DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_DESTKEY, intel_sprite_get_destkey,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
};
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7929a55..d486bab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2726,6 +2726,8 @@
#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
#define _SPRA_CTL 0x70280
#define SPRITE_ENABLE(131)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f91de00..68ef060 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -190,6 +190,8 @@ struct intel_plane {
uint32_t x, uint32_t y,
uint32_t src_w, uint32_t src_h);
void (*disable_plane)(struct drm_plane *plane);
+ int (*update_destkey)(struct drm_plane *plane, u32 value);
+ u32 (*get_destkey)(struct drm_plane *plane);
};
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
@@ -407,4 +409,10 @@ extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
+extern int intel_sprite_set_destkey(struct drm_device *dev, void *data,
+struct drm_file *file_priv);
+extern int intel_sprite_get_destkey(struct drm_device *dev, void *data,
+struct drm_file *file_priv);
+
+
#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index d8ae3e4..b470e9b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -99,6 +99,7 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
/* must disable */
sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
sprctl |= SPRITE_ENABLE;
+ sprctl |= SPRITE_DEST_KEY;
/* Sizes are 0 based */
src_w--;
@@ -140,6 +141,45 @@ ivb_disable_plane(struct drm_plane *plane)
POSTING_READ(SPRSURF(pipe));
}
+static int
+ivb_update_destkey(struct drm_plane *plane, u32 value)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_plane *intel_plane;
+ int ret = 0;
+
+ if (value 0xff)
+ return -EINVAL;
+
+ intel_plane = to_intel_plane(plane);
+
+ mutex_lock(dev-struct_mutex);
+ I915_WRITE(SPRKEYVAL(intel_plane-pipe), value);
+ I915_WRITE(SPRKEYMSK(intel_plane-pipe), 0xff);
+ POSTING_READ(SPRKEYMSK(intel_plane-pipe));
+ mutex_unlock(dev-struct_mutex);
+
+ return ret;
+}
+
+static u32
+ivb_get_destkey(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_plane *intel_plane;
+ u32 value;
+
+ intel_plane = to_intel_plane(plane);
+
+ mutex_lock(dev-struct_mutex);
+ value = I915_READ(SPRKEYVAL(intel_plane-pipe));
+ mutex_unlock(dev-struct_mutex);
+
+ return value;
+}
+
static void
snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
@@ -228,6
[Intel-gfx] [PATCH 3/3] drm/i915: track sprite coverage and disable primary plane if possible
To save power when the sprite is full screen, we can disable the primary
plane on the same pipe. Track the sprite status and enable/disable the
primary opportunistically.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_drv.h|3 ++
drivers/gpu/drm/i915/intel_sprite.c | 67 +++
2 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 68ef060..4ea3f68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -180,6 +180,7 @@ struct intel_plane {
struct drm_plane base;
enum pipe pipe;
struct drm_i915_gem_object *obj;
+ bool primary_disabled;
int max_downscale;
u32 lut_r[1024], lut_g[1024], lut_b[1024];
void (*update_plane)(struct drm_plane *plane,
@@ -192,6 +193,8 @@ struct intel_plane {
void (*disable_plane)(struct drm_plane *plane);
int (*update_destkey)(struct drm_plane *plane, u32 value);
u32 (*get_destkey)(struct drm_plane *plane);
+ void (*enable_primary)(struct drm_crtc *crtc);
+ void (*disable_primary)(struct drm_crtc *crtc);
};
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index b470e9b..f63e2a3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -49,6 +49,28 @@
*/
static void
+ivb_enable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
+}
+
+static void
+ivb_disable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) ~DISPLAY_PLANE_ENABLE);
+}
+
+static void
ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
@@ -181,6 +203,28 @@ ivb_get_destkey(struct drm_plane *plane)
}
static void
+snb_enable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
+}
+
+static void
+snb_disable_primary(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = DSPCNTR(intel_crtc-plane);
+
+ I915_WRITE(reg, I915_READ(reg) ~DISPLAY_PLANE_ENABLE);
+}
+
+static void
snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
@@ -394,9 +438,23 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_plane-obj = obj;
+ /*
+* Be sure to re-enable the primary before the sprite is no longer
+* covering it fully.
+*/
+ if (!disable_primary intel_plane-primary_disabled) {
+ intel_plane-enable_primary(crtc);
+ intel_plane-primary_disabled = false;
+ }
+
intel_plane-update_plane(plane, fb, obj, crtc_x, crtc_y,
crtc_w, crtc_h, x, y, src_w, src_h);
+ if (disable_primary) {
+ intel_plane-disable_primary(crtc);
+ intel_plane-primary_disabled = true;
+ }
+
/* Unpin old obj after new one is active to avoid ugliness */
if (old_obj) {
/*
@@ -427,6 +485,11 @@ intel_disable_plane(struct drm_plane *plane)
struct intel_plane *intel_plane = to_intel_plane(plane);
int ret = 0;
+ if (intel_plane-primary_disabled) {
+ intel_plane-enable_primary(plane-crtc);
+ intel_plane-primary_disabled = false;
+ }
+
intel_plane-disable_plane(plane);
if (!intel_plane-obj)
@@ -550,12 +613,16 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
intel_plane-disable_plane = snb_disable_plane;
intel_plane-update_destkey = snb_update_destkey;
intel_plane-get_destkey = snb_get_destkey;
+ intel_plane-enable_primary = ivb_enable_primary;
+ intel_plane-disable_primary = ivb_disable_primary;
} else
[Intel-gfx] [PATCH 1/3] drm/i915: add SNB and IVB video sprite support v2
The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core sprite support functions. v2: use drm specific fourcc header and defines v3: address Daniel's comments: - don't take struct mutex around register access (only needed for regs in the GT power well) - don't hold struct mutex across vblank waits - fix up update_plane API (pass obj instead of GTT offset) - add interlaced defines for sprite regs - drop unnecessary 'reg' variables - comment double buffered reg flushing Also fix w/h confusion when writing the scaling reg. For this version, I tested DPMS since it came up in the last review; DPMS off/on works ok when a video player is working under X, but for power saving we'll probably want to do something smarter. I'll leave that for a separate patch on top. Likewise with the refcounting/fb layer handling, which are really separate cleanups. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/i915_reg.h | 127 ++ drivers/gpu/drm/i915/intel_display.c | 29 ++- drivers/gpu/drm/i915/intel_drv.h | 23 ++ drivers/gpu/drm/i915/intel_fb.c |6 + drivers/gpu/drm/i915/intel_sprite.c | 425 ++ 6 files changed, 601 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_sprite.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 0ae6a7c..808b255 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ intel_dvo.o \ intel_ringbuffer.o \ intel_overlay.o \ + intel_sprite.o \ intel_opregion.o \ dvo_ch7xxx.o \ dvo_ch7017.o \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5a09416..7929a55 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2450,6 +2450,8 @@ #define WM3_LP_ILK 0x45110 #define WM3_LP_EN (131) #define WM1S_LP_ILK0x45120 +#define WM2S_LP_IVB0x45124 +#define WM3S_LP_IVB0x45128 #define WM1S_LP_EN(131) /* Memory latency timer register */ @@ -2666,6 +2668,131 @@ #define _DSPBSURF 0x7119C #define _DSPBTILEOFF 0x711A4 +/* Sprite A control */ +#define _DVSACNTR 0x72180 +#define DVS_ENABLE (131) +#define DVS_GAMMA_ENABLE (130) +#define DVS_PIXFORMAT_MASK (325) +#define DVS_FORMAT_YUV422(025) +#define DVS_FORMAT_RGBX101010(125) +#define DVS_FORMAT_RGBX888 (225) +#define DVS_FORMAT_RGBX161616(325) +#define DVS_SOURCE_KEY (122) +#define DVS_RGB_ORDER_RGBX (120) +#define DVS_YUV_BYTE_ORDER_MASK (316) +#define DVS_YUV_ORDER_YUYV (016) +#define DVS_YUV_ORDER_UYVY (116) +#define DVS_YUV_ORDER_YVYU (216) +#define DVS_YUV_ORDER_VYUY (316) +#define DVS_DEST_KEY (12) +#define DVS_TRICKLE_FEED_DISABLE (114) +#define DVS_TILED(110) +#define _DVSASTRIDE0x72188 +#define _DVSAPOS 0x7218c +#define _DVSASIZE 0x72190 +#define _DVSAKEYVAL0x72194 +#define _DVSAKEYMSK0x72198 +#define _DVSASURF 0x7219c +#define _DVSAKEYMAXVAL 0x721a0 +#define _DVSATILEOFF 0x721a4 +#define _DVSASURFLIVE 0x721ac +#define _DVSASCALE 0x72204 +#define DVS_SCALE_ENABLE (131) +#define DVS_FILTER_MASK (329) +#define DVS_FILTER_MEDIUM(029) +#define DVS_FILTER_ENHANCING (129) +#define DVS_FILTER_SOFTENING (229) +#define DVS_VERTICAL_OFFSET_HALF (128) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (127) +#define _DVSAGAMC 0x72300 + +#define _DVSBCNTR 0x73180 +#define _DVSBSTRIDE0x73188 +#define _DVSBPOS 0x7318c +#define _DVSBSIZE 0x73190 +#define _DVSBKEYVAL0x73194 +#define _DVSBKEYMSK0x73198 +#define _DVSBSURF 0x7319c +#define _DVSBKEYMAXVAL 0x731a0 +#define _DVSBTILEOFF 0x731a4 +#define _DVSBSURFLIVE 0x731ac +#define _DVSBSCALE 0x73204 +#define _DVSBGAMC 0x73300 + +#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) +#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) +#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) +#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) +#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) +#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) +#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) + +#define _SPRA_CTL 0x70280 +#define SPRITE_ENABLE(131) +#define SPRITE_GAMMA_ENABLE
[Intel-gfx] [PATCH 1/2] drm/i915: re-enable semaphores by default
Semaphores seem to fix most of the hangs on SNB and IVB, and do not cause any known regressions as of now. Let's re-enable them by default to provide a wider testing and coverage. Acked-by: Keith Packard kei...@keithp.com CC: Jesse Barnes jbar...@virtuousgeek.org CC: Daniel Vetter daniel.vet...@ffwll.ch Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42696 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40564 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38862 Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com --- drivers/gpu/drm/i915/i915_drv.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index cc531bb..71f887a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -58,10 +58,10 @@ module_param_named(powersave, i915_powersave, int, 0600); MODULE_PARM_DESC(powersave, Enable powersavings, fbc, downclocking, etc. (default: true)); -unsigned int i915_semaphores __read_mostly = 0; +unsigned int i915_semaphores __read_mostly = 1; module_param_named(semaphores, i915_semaphores, int, 0600); MODULE_PARM_DESC(semaphores, - Use semaphores for inter-ring sync (default: false)); + Use semaphores for inter-ring sync (default: true)); unsigned int i915_enable_rc6 __read_mostly = 0; module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); -- 1.7.7.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: re-enable rc6 by default
On Mon, 14 Nov 2011 18:39:15 -0200 Eugeni Dodonov eugeni.dodo...@intel.com wrote: Most of the rc6-related hangs and major issues were addressed for the past months. Let's re-enable it by default to provide a more wider testing, and catch the remaining problems. According to tests, enablement of rc6 results in up to +50% improvements in power usage and battery life, so it certainly would be a nice feature to have enabled by default. Also, most of the issues related to rc6 seem to came from VTd, so if you are experiencing any problems with it, try disabling VTd in bios or using intel_iommu=off kernel parameter to investigate whether it solves the issue. Yes please. Acked-by: Jesse Barnes jbar...@virtuousgeek.org -- Jesse Barnes, Intel Open Source Technology Center signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: re-enable semaphores by default
On Mon, 14 Nov 2011 18:39:14 -0200 Eugeni Dodonov eugeni.dodo...@intel.com wrote: Semaphores seem to fix most of the hangs on SNB and IVB, and do not cause any known regressions as of now. Let's re-enable them by default to provide a wider testing and coverage. Acked-by: Keith Packard kei...@keithp.com CC: Jesse Barnes jbar...@virtuousgeek.org CC: Daniel Vetter daniel.vet...@ffwll.ch Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42696 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40564 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38862 Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com --- drivers/gpu/drm/i915/i915_drv.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index cc531bb..71f887a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -58,10 +58,10 @@ module_param_named(powersave, i915_powersave, int, 0600); MODULE_PARM_DESC(powersave, Enable powersavings, fbc, downclocking, etc. (default: true)); -unsigned int i915_semaphores __read_mostly = 0; +unsigned int i915_semaphores __read_mostly = 1; module_param_named(semaphores, i915_semaphores, int, 0600); MODULE_PARM_DESC(semaphores, - Use semaphores for inter-ring sync (default: false)); + Use semaphores for inter-ring sync (default: true)); unsigned int i915_enable_rc6 __read_mostly = 0; module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); I think we should keep them enabled; if one or two fat cats in the 1% still have issues we can debug those without bringing down performance for the other 99%. Acked-by: Jesse Barnes jbar...@virtuousgeek.org -- Jesse Barnes, Intel Open Source Technology Center signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: re-enable rc6 by default
Hi, On Mon, Nov 14, 2011 at 06:39:15PM -0200, Eugeni Dodonov wrote: Most of the rc6-related hangs and major issues were addressed for the past months. which commits should I try to check whether rc6 issue is gone? As of 3.1 kernel, I'm still getting huge screen corruption. -- Lukáš Hejtmánek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: re-enable rc6 by default
2011/11/14 Lukas Hejtmanek xhejt...@ics.muni.cz Hi, On Mon, Nov 14, 2011 at 06:39:15PM -0200, Eugeni Dodonov wrote: Most of the rc6-related hangs and major issues were addressed for the past months. which commits should I try to check whether rc6 issue is gone? As of 3.1 kernel, I'm still getting huge screen corruption. The rc6 issue which are gone are the ones which was causing hard system hangs and gpu hangs. Corruptions are still out there, if they don't go away when using intel_iommu=off then we'll have to investigate them more in-depth. I am unable to reproduce any rc6-related corruptions on my machine(s) though. So it looks like this is yet another case in which we'll need to use Sherlock Holmes methods to get to them... -- Eugeni Dodonov http://eugeni.dodonov.net/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: re-enable rc6 by default
2011/11/14 Lukas Hejtmanek xhejt...@ics.muni.cz I am unable to reproduce any rc6-related corruptions on my machine(s) though. So it looks like this is yet another case in which we'll need to use Sherlock Holmes methods to get to them... are you using SNA? I do on my SNB system. Are the issues SNA-specific, or they happen with UXA as well? I do use both SNA and UXA actually (thanks to http://cgit.freedesktop.org/~eugeni/xf86-video-intel/ :)). -- Eugeni Dodonov http://eugeni.dodonov.net/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: re-enable rc6 by default
On Mon, Nov 14, 2011 at 09:04:37PM -0200, Eugeni Dodonov wrote: The rc6 issue which are gone are the ones which was causing hard system hangs and gpu hangs. Corruptions are still out there, if they don't go away when using intel_iommu=off then we'll have to investigate them more in-depth. I disabled iommu in BIOS, so I guess it is not an issue here. I am unable to reproduce any rc6-related corruptions on my machine(s) though. So it looks like this is yet another case in which we'll need to use Sherlock Holmes methods to get to them... are you using SNA? I do on my SNB system. -- Lukáš Hejtmánek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: re-enable rc6 by default
On Mon, Nov 14, 2011 at 09:17:39PM -0200, Eugeni Dodonov wrote: Are the issues SNA-specific, or they happen with UXA as well? I do use both SNA and UXA actually (thanks to http://cgit.freedesktop.org/~eugeni/xf86-video-intel/ :)). I believe they happen with both but with SNA I got regular corruption while with UXA I got accidental corruption. I.e., with SNA I got corrupted window in few minutes, with UXA maybe one corruption per few hours. But I did not try those Eric's gating patches with UXA. I got also X server segfaults related to XV video (moving window, resing window with video crashes the X server randomly). Didn't investigate this (getting core file, e.g.) I have X server 1.10, I think there are some fixes around 1.12. -- Lukáš Hejtmánek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
