Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Wake up pending_flip_queue as part of reset handling
On Fri, Feb 15, 2013 at 11:53:14PM +, Chris Wilson wrote: On Fri, Feb 15, 2013 at 05:07:44PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Someone may be waiting for a flip that will never complete due to a GPU reset. Wake up all such waiters after the GPU reset processing has finished. v2: Dropped the wake_up_all() from i915_handle_error() since we no longer wait for pending flips with struct_mutex held. Isn't the wake_up(pending_flip_queue) superseded by performing the explicit do_intel_finish_page_flip() in patch 3? Yes that's correct. But I actually forgot to remove the wake_up patch from my tree when I tested this. I'll run a few more tests just to make sure it still works. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Update primary planes after a GPU reset
On Fri, Feb 15, 2013 at 11:47:52PM +, Chris Wilson wrote:
On Fri, Feb 15, 2013 at 06:56:03PM +0200, Ville Syrjälä wrote:
On Fri, Feb 15, 2013 at 03:28:33PM +, Chris Wilson wrote:
On Fri, Feb 15, 2013 at 05:07:46PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
GPU reset will drop all flips that are still in the ring. So after the
reset, call update_plane() for all CRTCs to make sure the primary
planes are scanning out from the correct buffer.
The base address update will also generate a FLIP_DONE interrupt, which
will complete any pending flips. That means user space will get its
page flip events and won't get stuck waiting for them.
Not for all generations.
Hmm OK those seem to be the ones with the pending flip status bit
(Gen4 and older?).
Yes. Also notably the ones unlikely to survive the GPU reset :)
But can someone explain why on those platforms we also check the
vblank interrupt status bit before handling the page flip interrupt?
For those generations, we are meant to detect the transition of pending
flip status from 1 - 0. That transition of course doesn't generate an
interrupt (rather it stops generating one), so the nearest I could come
up with was in anticipating the vblank after we saw the pending flip
status was close enough. In the case of a pending vblank raising an
interrupt just as the pending flip status is asserted, shouldn't MSI
prevent the pending flip from being asserted as we process the IIR for
the vblank. Of course not all of those chipsets even have MSI. I'm not
even sure if we can close that race.
This is what I *think* gen2-gen4 Bspec are telling me:
1. CS executes MI_DISPLAY_FLIP
- ISR:flip bit 0 - 1
2. Flip completes
- ISR:flip bit 1 - 0
- IIR:flip bit 0 - 1
- interrupt generated
But unfortuntely I have no hardware to test that.
But if I'm reading the BSpec incorrectly (or if it's inaccurate), then
I think we can close the race with this code:
i965_irq_handler()
{
...
if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
intel_prepare_page_flip();
if (iir PIPE_START_VBLANK_INTERRUPT_STATUS
(I915_READ(ISR) I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) == 0)
intel_finish_page_flip();
...
}
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Update primary planes after a GPU reset
On Mon, Feb 18, 2013 at 12:15:34PM +0200, Ville Syrjälä wrote: On Fri, Feb 15, 2013 at 11:47:52PM +, Chris Wilson wrote: On Fri, Feb 15, 2013 at 06:56:03PM +0200, Ville Syrjälä wrote: On Fri, Feb 15, 2013 at 03:28:33PM +, Chris Wilson wrote: On Fri, Feb 15, 2013 at 05:07:46PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com GPU reset will drop all flips that are still in the ring. So after the reset, call update_plane() for all CRTCs to make sure the primary planes are scanning out from the correct buffer. The base address update will also generate a FLIP_DONE interrupt, which will complete any pending flips. That means user space will get its page flip events and won't get stuck waiting for them. Not for all generations. Hmm OK those seem to be the ones with the pending flip status bit (Gen4 and older?). Yes. Also notably the ones unlikely to survive the GPU reset :) But can someone explain why on those platforms we also check the vblank interrupt status bit before handling the page flip interrupt? For those generations, we are meant to detect the transition of pending flip status from 1 - 0. That transition of course doesn't generate an interrupt (rather it stops generating one), so the nearest I could come up with was in anticipating the vblank after we saw the pending flip status was close enough. In the case of a pending vblank raising an interrupt just as the pending flip status is asserted, shouldn't MSI prevent the pending flip from being asserted as we process the IIR for the vblank. Of course not all of those chipsets even have MSI. I'm not even sure if we can close that race. This is what I *think* gen2-gen4 Bspec are telling me: 1. CS executes MI_DISPLAY_FLIP - ISR:flip bit 0 - 1 2. Flip completes - ISR:flip bit 1 - 0 - IIR:flip bit 0 - 1 - interrupt generated Ah, no. The IIR mirrors the ISR and it really does continually generate the PendingFlip interrupt on gen2/3. It wasn't until midway through the gen3 cycle, that they introduced the behaviour you describe (which is what the pending flip is actually flip done bit in ECOSKPD is about). But since we already have to try and handle gen2/3, I didn't think it was worth a second gen3 code path with the revised behaviour. Can you send that as a patch for gen4? As I have a few people hitting pageflip system hangs, but only on gen4 afaict. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Update primary planes after a GPU reset
On Mon, Feb 18, 2013 at 10:47:37AM +, Chris Wilson wrote: On Mon, Feb 18, 2013 at 12:15:34PM +0200, Ville Syrjälä wrote: On Fri, Feb 15, 2013 at 11:47:52PM +, Chris Wilson wrote: On Fri, Feb 15, 2013 at 06:56:03PM +0200, Ville Syrjälä wrote: On Fri, Feb 15, 2013 at 03:28:33PM +, Chris Wilson wrote: On Fri, Feb 15, 2013 at 05:07:46PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com GPU reset will drop all flips that are still in the ring. So after the reset, call update_plane() for all CRTCs to make sure the primary planes are scanning out from the correct buffer. The base address update will also generate a FLIP_DONE interrupt, which will complete any pending flips. That means user space will get its page flip events and won't get stuck waiting for them. Not for all generations. Hmm OK those seem to be the ones with the pending flip status bit (Gen4 and older?). Yes. Also notably the ones unlikely to survive the GPU reset :) But can someone explain why on those platforms we also check the vblank interrupt status bit before handling the page flip interrupt? For those generations, we are meant to detect the transition of pending flip status from 1 - 0. That transition of course doesn't generate an interrupt (rather it stops generating one), so the nearest I could come up with was in anticipating the vblank after we saw the pending flip status was close enough. In the case of a pending vblank raising an interrupt just as the pending flip status is asserted, shouldn't MSI prevent the pending flip from being asserted as we process the IIR for the vblank. Of course not all of those chipsets even have MSI. I'm not even sure if we can close that race. This is what I *think* gen2-gen4 Bspec are telling me: 1. CS executes MI_DISPLAY_FLIP - ISR:flip bit 0 - 1 2. Flip completes - ISR:flip bit 1 - 0 - IIR:flip bit 0 - 1 - interrupt generated Ah, no. The IIR mirrors the ISR and it really does continually generate the PendingFlip interrupt on gen2/3. Continually? Oh that's nasty, but makes sense if it's just a level interrupt. It wasn't until midway through the gen3 cycle, that they introduced the behaviour you describe (which is what the pending flip is actually flip done bit in ECOSKPD is about). But since we already have to try and handle gen2/3, I didn't think it was worth a second gen3 code path with the revised behaviour. Ok. I see we never actually enable the pending flip interrupt on gen2/3 due to this. The same race exists there as well then. I can try to make a patch for that too. And we turn off the bit in ECOSKPD on gen3 to make sure we always behave the same way. Makes sense. Can you send that as a patch for gen4? As I have a few people hitting pageflip system hangs, but only on gen4 afaict. I must admit that I'm confused now. Which model does Gen4 actually follow, pending flip or flip done? -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the interrupt handler were to process a previous vblank interrupt and
the following flip pending interrupt at the same time, the page flip
would be complete too soon.
To eliminate this race check the live pending flip status from the ISR
register before finishing the page flip.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9fde49a..3de570c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2284,8 +2284,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 0)) {
if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 0);
- intel_finish_page_flip(dev, 0);
- flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 0);
+ flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2293,8 +2296,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 1)) {
if (iir I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 1);
- intel_finish_page_flip(dev, 1);
- flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 1);
+ flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2491,8 +2497,11 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, pipe)) {
if (iir flip[plane]) {
intel_prepare_page_flip(dev, plane);
- intel_finish_page_flip(dev, pipe);
- flip_mask = ~flip[plane];
+
+ if ((I915_READ(ISR) flip[plane]) ==
0) {
+ intel_finish_page_flip(dev,
pipe);
+ flip_mask = ~flip[plane];
+ }
}
}
--
1.7.12.4
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Re: [Intel-gfx] [PATCH] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
Am Montag, den 18.02.2013, 13:57 +0200 schrieb ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the interrupt handler were to process a previous vblank interrupt and
the following flip pending interrupt at the same time, the page flip
would be complete too soon.
»would complete« or »would be complete*d*«
To eliminate this race check the live pending flip status from the ISR
register before finishing the page flip.
Could this be tested somehow? Could a test case be written for this?
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9fde49a..3de570c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2284,8 +2284,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 0)) {
if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 0);
- intel_finish_page_flip(dev, 0);
- flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 0);
+ flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2293,8 +2296,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 1)) {
if (iir I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 1);
- intel_finish_page_flip(dev, 1);
- flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 1);
+ flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2491,8 +2497,11 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, pipe)) {
if (iir flip[plane]) {
intel_prepare_page_flip(dev, plane);
- intel_finish_page_flip(dev, pipe);
- flip_mask = ~flip[plane];
+
+ if ((I915_READ(ISR) flip[plane]) ==
0) {
Why not `I915_READ16`?
+ intel_finish_page_flip(dev,
pipe);
+ flip_mask = ~flip[plane];
+ }
}
}
Thanks,
Paul
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Update primary planes after a GPU reset
On Mon, Feb 18, 2013 at 01:50:26PM +0200, Ville Syrjälä wrote: Can you send that as a patch for gen4? As I have a few people hitting pageflip system hangs, but only on gen4 afaict. I must admit that I'm confused now. Which model does Gen4 actually follow, pending flip or flip done? The original bspec for gen4 doesn't mention FlipDone and the description of PendingFlip reads very similar to the earlier gen2/gen3 implementation. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
On Mon, Feb 18, 2013 at 01:57:51PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com If the interrupt handler were to process a previous vblank interrupt and the following flip pending interrupt at the same time, the page flip would be complete too soon. To eliminate this race check the live pending flip status from the ISR register before finishing the page flip. Ok, that makes a lot of sense. /* We detect FlipDone by looking for the change in PendingFlip from '1' * to '0' on the following vblank, i.e. IIR has the Pendingflip * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence * the flip is completed (no longer pending). Since this doesn't raise an * interrupt per-se, we watch for the change at vblank. */ Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Reviewed-by: Chris Wilson chris@chris-wils Time to give it a quick test and make sure it doesn't break a ton of assumptions... :) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
On Mon, Feb 18, 2013 at 01:07:53PM +0100, Paul Menzel wrote:
Am Montag, den 18.02.2013, 13:57 +0200 schrieb ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the interrupt handler were to process a previous vblank interrupt and
the following flip pending interrupt at the same time, the page flip
would be complete too soon.
»would complete« or »would be complete*d*«
The second on is what I meant. Will fix.
To eliminate this race check the live pending flip status from the ISR
register before finishing the page flip.
Could this be tested somehow? Could a test case be written for this?
It shouldn't be too difficult to force it from within the kernel. Just
turn off interrupts before vblank start, wait until vblank start is
passed, execute the MI_DISPLAY_FLIP, and finally turn the interrupts
back on again.
Given the timing constraints I'm not sure we can come up with anything
that would realiably hit it otherwise.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c
index 9fde49a..3de570c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2284,8 +2284,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void
*arg)
drm_handle_vblank(dev, 0)) {
if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 0);
- intel_finish_page_flip(dev, 0);
- flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 0);
+ flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2293,8 +2296,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void
*arg)
drm_handle_vblank(dev, 1)) {
if (iir I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 1);
- intel_finish_page_flip(dev, 1);
- flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 1);
+ flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2491,8 +2497,11 @@ static irqreturn_t i915_irq_handler(int irq, void
*arg)
drm_handle_vblank(dev, pipe)) {
if (iir flip[plane]) {
intel_prepare_page_flip(dev, plane);
- intel_finish_page_flip(dev, pipe);
- flip_mask = ~flip[plane];
+
+ if ((I915_READ(ISR) flip[plane]) ==
0) {
Why not `I915_READ16`?
It matches the rest if i915_irq_handler(). I suppose the interrupt
registers were 16 bit on gen2 and 32 bit on gen3+.
+ intel_finish_page_flip(dev,
pipe);
+ flip_mask = ~flip[plane];
+ }
}
}
Thanks,
Paul
--
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Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
On Mon, Feb 18, 2013 at 12:16:09PM +, Chris Wilson wrote: On Mon, Feb 18, 2013 at 01:57:51PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com If the interrupt handler were to process a previous vblank interrupt and the following flip pending interrupt at the same time, the page flip would be complete too soon. To eliminate this race check the live pending flip status from the ISR register before finishing the page flip. Ok, that makes a lot of sense. /* We detect FlipDone by looking for the change in PendingFlip from '1' * to '0' on the following vblank, i.e. IIR has the Pendingflip * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence * the flip is completed (no longer pending). Since this doesn't raise an * interrupt per-se, we watch for the change at vblank. */ You want me to include that comment somewhere in the code? Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Reviewed-by: Chris Wilson chris@chris-wils Time to give it a quick test and make sure it doesn't break a ton of assumptions... :) -Chris -- Chris Wilson, Intel Open Source Technology Centre -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Wake up pending_flip_queue as part of reset handling
On Mon, Feb 18, 2013 at 11:58:23AM +0200, Ville Syrjälä wrote: On Fri, Feb 15, 2013 at 11:53:14PM +, Chris Wilson wrote: On Fri, Feb 15, 2013 at 05:07:44PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Someone may be waiting for a flip that will never complete due to a GPU reset. Wake up all such waiters after the GPU reset processing has finished. v2: Dropped the wake_up_all() from i915_handle_error() since we no longer wait for pending flips with struct_mutex held. Isn't the wake_up(pending_flip_queue) superseded by performing the explicit do_intel_finish_page_flip() in patch 3? Yes that's correct. But I actually forgot to remove the wake_up patch from my tree when I tested this. I'll run a few more tests just to make sure it still works. I just tried it w/o the wake_up_all() and unfortunately it hung :( Need to think about it a bit more I suppose. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
On Mon, Feb 18, 2013 at 02:27:24PM +0200, Ville Syrjälä wrote: On Mon, Feb 18, 2013 at 12:16:09PM +, Chris Wilson wrote: /* We detect FlipDone by looking for the change in PendingFlip from '1' * to '0' on the following vblank, i.e. IIR has the Pendingflip * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence * the flip is completed (no longer pending). Since this doesn't raise an * interrupt per-se, we watch for the change at vblank. */ You want me to include that comment somewhere in the code? Please, would be useful for future archaeologists. I'd pick the gen3 location as it is more compact. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] render/gen7: Don't use a message register to store vl
On Thu, Feb 14, 2013 at 08:52:16AM -0800, Kenneth Graunke wrote:
On 02/14/2013 06:20 AM, Damien Lespiau wrote:
Turns out the new assembler that uses mesa's opcode emission hits the
path that automatically transforms MRF registers into GRF ones in the
exa_wm_src_projective shader.
The diff with the new assembler is:
$ intel-gen4disasm -g7 -
- { 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x2e8077bd, 0x008d03c0, 0x008d0180 },
mul(8) m41F g308,8,1F g128,8,1F { align1 };
mul(8) g1161Fg308,8,1F g128,8,1F { align1 };
Of course, message registers are no more in gen7, so the shader is
trying to do something shaddy (ahem!).
Instead of using m4, let's make exa_wm_src_projective use g68 for v (aka
vl) which makes sense since:
1/ vh is g69
2/ exa_wm_src_affine uses g68 for vl already
This commit changes the generated assembly, here's the decoded diff:
$ intel-gen4disasm -g7 -
- { 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x288077bd, 0x008d03c0, 0x008d0180 },
mul(8) m41F g308,8,1F g128,8,1F { align1 };
mul(8) g681F g308,8,1F g128,8,1F { align1 };
Cc: Kenneth Graunke kenn...@whitecape.org
Reported-by: Xiang, Haihao haihao.xi...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
If I recall correctly, the only actual changes between the Gen6 and
Gen7 render assembly was converting MRFs to GRFs, and I arbitrarily
picked something in the 60s rather than 112+. If you want, I think
you could actually just delete all the Gen7 custom assembly and let
gen7_convert_mrf_to_grf do it for you.
But this looks okay to me, if you'd rather continue doing everything
explicitly...
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Thanks for the patch and review, pushed.
-Chris
--
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[Intel-gfx] [PATCH v2] drm/i915: Eliminate race from gen2/3 page flip interrupt handling
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the interrupt handler were to process a previous vblank interrupt and
the following flip pending interrupt at the same time, the page flip
would be completed too soon.
To eliminate this race, check the live pending flip status from the ISR
register before finishing the page flip.
v2: Added a comment explaining the logic (by Chris Wilson)
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Tested-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_irq.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9fde49a..2aea737 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2284,8 +2284,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 0)) {
if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 0);
- intel_finish_page_flip(dev, 0);
- flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 0);
+ flip_mask =
~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2293,8 +2296,11 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, 1)) {
if (iir I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
intel_prepare_page_flip(dev, 1);
- intel_finish_page_flip(dev, 1);
- flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+
+ if ((I915_READ16(ISR)
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) == 0) {
+ intel_finish_page_flip(dev, 1);
+ flip_mask =
~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+ }
}
}
@@ -2491,8 +2497,17 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
drm_handle_vblank(dev, pipe)) {
if (iir flip[plane]) {
intel_prepare_page_flip(dev, plane);
- intel_finish_page_flip(dev, pipe);
- flip_mask = ~flip[plane];
+
+ /* We detect FlipDone by looking for
the change in PendingFlip from '1'
+* to '0' on the following vblank, i.e.
IIR has the Pendingflip
+* asserted following the
MI_DISPLAY_FLIP, but ISR is deasserted, hence
+* the flip is completed (no longer
pending). Since this doesn't raise an
+* interrupt per-se, we watch for the
change at vblank.
+*/
+ if ((I915_READ(ISR) flip[plane]) ==
0) {
+ intel_finish_page_flip(dev,
pipe);
+ flip_mask = ~flip[plane];
+ }
}
}
--
1.7.12.4
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[Intel-gfx] [RFC][PATCH] drm/i915: Fix races in gen4 page flip interrupt handling
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use the gen3 logic for handling page flip interrupts on gen4.
Unfortuantely this kills the stall_check since that looks like it can
easily trigger too early. With the current logic the stall check would
kick in on the first vblank after the flip has been submitted to the
ring. If the CS takes longer than that to process the commands in the
ring, the stall check will cause the page flip to be complete too
early. That doesn't sound like a very good idea. Something better
should be deviced if we still need the stall check.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2aea737..1347940 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2684,6 +2684,13 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
unsigned long irqflags;
int irq_received;
int ret = IRQ_NONE, pipe;
+ u32 flip[2] = {
+ I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
+ I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
+ };
+ u32 flip_mask =
+ I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
+ I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
atomic_inc(dev_priv-irq_received);
@@ -2692,7 +2699,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
for (;;) {
bool blc_event = false;
- irq_received = iir != 0;
+ irq_received = (iir ~flip_mask) != 0;
/* Can't rely on pipestat interrupt bit in iir as it might
* have been cleared after the pipestat interrupt was received.
@@ -2739,7 +2746,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
I915_READ(PORT_HOTPLUG_STAT);
}
- I915_WRITE(IIR, iir);
+ I915_WRITE(IIR, iir ~flip_mask);
new_iir = I915_READ(IIR); /* Flush posted writes */
if (iir I915_USER_INTERRUPT)
@@ -2747,17 +2754,17 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
if (iir I915_BSD_USER_INTERRUPT)
notify_ring(dev, dev_priv-ring[VCS]);
- if (iir I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
- intel_prepare_page_flip(dev, 0);
-
- if (iir I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
- intel_prepare_page_flip(dev, 1);
-
for_each_pipe(pipe) {
if (pipe_stats[pipe]
PIPE_START_VBLANK_INTERRUPT_STATUS
drm_handle_vblank(dev, pipe)) {
- i915_pageflip_stall_check(dev, pipe);
- intel_finish_page_flip(dev, pipe);
+ if (iir flip[pipe]) {
+ intel_prepare_page_flip(dev, pipe);
+
+ if ((I915_READ(ISR) flip[pipe]) == 0)
{
+ intel_finish_page_flip(dev,
pipe);
+ flip_mask = ~flip[pipe];
+ }
+ }
}
if (pipe_stats[pipe] PIPE_LEGACY_BLC_EVENT_STATUS)
--
1.7.12.4
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Wake up pending_flip_queue as part of reset handling
On Mon, Feb 18, 2013 at 05:31:14PM +0200, Ville Syrjälä wrote: On Mon, Feb 18, 2013 at 02:41:00PM +0200, Ville Syrjälä wrote: On Mon, Feb 18, 2013 at 11:58:23AM +0200, Ville Syrjälä wrote: On Fri, Feb 15, 2013 at 11:53:14PM +, Chris Wilson wrote: On Fri, Feb 15, 2013 at 05:07:44PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Someone may be waiting for a flip that will never complete due to a GPU reset. Wake up all such waiters after the GPU reset processing has finished. v2: Dropped the wake_up_all() from i915_handle_error() since we no longer wait for pending flips with struct_mutex held. Isn't the wake_up(pending_flip_queue) superseded by performing the explicit do_intel_finish_page_flip() in patch 3? Yes that's correct. But I actually forgot to remove the wake_up patch from my tree when I tested this. I'll run a few more tests just to make sure it still works. I just tried it w/o the wake_up_all() and unfortunately it hung :( Need to think about it a bit more I suppose. Well after a bit more though I think I know what happened: 1. page flip submitted on crtc which is not the first crtc in the list 2. mode set operation on any crtc (will grab all crtc locks) 3. reset handling loops over crtcs 3.1 first crtc doesn't have a pending flip, so pending_flip_queue is not woken up 3.2 code tries to grab first crtc mutex to update the base address - deadlock So either I need to keep the wake_up_all() call in the reset handling, or I need to do two loops over the crtcs, first loop would complete all page flips, and second loop would update the base address registers. I don't really care which way we go. Anyone else have a preference? I'd vote for the second approach of first waking everyone up, and then doing the modeset updates. I guess you could even use drm_modeset_lock_all, not really worth optimizing things here imo. Also please add a comment to explain this ordering constraint in the reset code. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915: Really wait for pending flips when panning
From: Ville Syrjälä ville.syrj...@linux.intel.com
Since obj-pending_flips was never set, intel_pipe_set_base() never
actually waited for pending page flips to complete.
We really do want to wait for the pending flips, because otherwise the
mmio surface base address update could overtake the flip, and you
could end up with an old frame on the screen once the flip really
completes.
Just call intel_crtc_wait_pending_flips() prior to calling
intel_pipe_set_base() instead of calling just intel_finish_fb()
from intel_pipe_set_base(). Moving the call outside of
intel_pipe_set_base() avoids calling it twice from the full
modeset path.
v2: Wait for pending flips w/o holding struct_mutex
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6337196..fd37d8b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2301,9 +2301,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
return ret;
}
- if (crtc-fb)
- intel_finish_fb(crtc-fb);
-
ret = dev_priv-display.update_plane(crtc, fb, x, y);
if (ret) {
intel_unpin_fb_obj(to_intel_framebuffer(fb)-obj);
@@ -8111,6 +8108,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
goto fail;
}
} else if (config-fb_changed) {
+ intel_crtc_wait_for_pending_flips(set-crtc);
+
ret = intel_pipe_set_base(set-crtc,
set-x, set-y, set-fb);
}
--
1.7.12.4
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[Intel-gfx] [PATCH v3 2/2] drm/i915: Finish page flips and update primary planes after a GPU reset
From: Ville Syrjälä ville.syrj...@linux.intel.com
GPU reset will drop all flips that are still in the ring. So after the
reset, call update_plane() for all CRTCs to make sure the primary
planes are scanning out from the correct buffer.
Also finish all pending flips. That means user space will get its
page flip events and won't get stuck waiting for them.
v2: Explicitly finish page flips instead of relying on FLIP_DONE
interrupt being generated by the base address update.
v3: Make two loops over crtcs to avoid deadlocks with the crtc mutex
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
drivers/gpu/drm/i915/intel_display.c | 37
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2cd97d1..9fde49a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -915,6 +915,8 @@ static void i915_error_work_func(struct work_struct *work)
for_each_ring(ring, dev_priv, i)
wake_up_all(ring-irq_queue);
+ intel_display_handle_reset(dev);
+
wake_up_all(dev_priv-gpu_error.reset_queue);
}
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fd37d8b..892f04b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2218,6 +2218,43 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct
drm_framebuffer *fb,
return dev_priv-display.update_plane(crtc, fb, x, y);
}
+void intel_display_handle_reset(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_crtc *crtc;
+
+ /*
+* Flips in the rings have been nuked by the reset,
+* so complete all pending flips so that user space
+* will get its events and not get stuck.
+*
+* Also update the base address of all primary
+* planes to the the last fb to make sure we're
+* showing the correct fb after a reset.
+*
+* Need to make two loops over the crtcs so that we
+* don't try to grab a crtc mutex before the
+* pending_flip_queue really got woken up.
+*/
+
+ list_for_each_entry(crtc, dev-mode_config.crtc_list, head) {
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ enum plane plane = intel_crtc-plane;
+
+ intel_prepare_page_flip(dev, plane);
+ intel_finish_page_flip_plane(dev, plane);
+ }
+
+ list_for_each_entry(crtc, dev-mode_config.crtc_list, head) {
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ mutex_lock(crtc-mutex);
+ if (intel_crtc-active)
+ dev_priv-display.update_plane(crtc, crtc-fb, crtc-x,
crtc-y);
+ mutex_unlock(crtc-mutex);
+ }
+}
+
static int
intel_finish_fb(struct drm_framebuffer *old_fb)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d282052..0dc14c2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -694,4 +694,6 @@ extern bool
intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
+extern void intel_display_handle_reset(struct drm_device *dev);
+
#endif /* __INTEL_DRV_H__ */
--
1.7.12.4
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: add sprite restore function v2
On Fri, Feb 15, 2013 at 01:23:10PM -0800, Jesse Barnes wrote:
To be used to restore sprite state on resume.
v2: move sprite tracking bits up so we don't track modified sprite state
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_drv.h|5 +
drivers/gpu/drm/i915/intel_sprite.c | 23 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index 005a91f..1b548e0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -247,6 +247,10 @@ struct intel_plane {
bool can_scale;
int max_downscale;
u32 lut_r[1024], lut_g[1024], lut_b[1024];
+ int crtc_x, crtc_y;
+ unsigned int crtc_w, crtc_h;
+ uint32_t x, y;
Can we call just them src_x/src_y instead?
+ uint32_t src_w, src_h;
void (*update_plane)(struct drm_plane *plane,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
@@ -532,6 +536,7 @@ extern bool intel_encoder_check_is_cloned(struct
intel_encoder *encoder);
extern void intel_connector_dpms(struct drm_connector *, int mode);
extern bool intel_connector_get_hw_state(struct intel_connector *connector);
extern void intel_modeset_check_state(struct drm_device *dev);
+extern void intel_plane_restore(struct drm_plane *plane);
static inline struct intel_encoder *intel_attached_encoder(struct
drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 03cfd62..ca171af 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -438,6 +438,15 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
old_obj = intel_plane-obj;
+ intel_plane-crtc_x = crtc_x;
+ intel_plane-crtc_y = crtc_y;
+ intel_plane-crtc_w = crtc_w;
+ intel_plane-crtc_h = crtc_h;
+ intel_plane-x = x;
+ intel_plane-y = y;
x and y are not fixed point numbers. They just contain the integer parts
of src_x and src_y. So you need to use src_x and src_y here instead.
+ intel_plane-src_w = src_w;
+ intel_plane-src_h = src_h;
+
src_w = src_w 16;
src_h = src_h 16;
@@ -644,6 +653,20 @@ out_unlock:
return ret;
}
+void intel_plane_restore(struct drm_plane *plane)
+{
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+
+ if (!plane-crtc || !plane-fb)
+ return;
+
+ intel_update_plane(plane, plane-crtc, plane-fb,
+intel_plane-crtc_x, intel_plane-crtc_y,
+intel_plane-crtc_w, intel_plane-crtc_h,
+intel_plane-x, intel_plane-y,
+intel_plane-src_w, intel_plane-src_h);
+}
+
static const struct drm_plane_funcs intel_plane_funcs = {
.update_plane = intel_update_plane,
.disable_plane = intel_disable_plane,
--
1.7.9.5
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--
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Intel OTC
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[Intel-gfx] [PATCH v2 0/4] drm/i915: handle compact dma scatter lists
This series adds support for handling compact dma scatter lists to the i915 driver. This is a dependency for the related upcoming change in the PRIME interface: http://www.spinics.net/lists/dri-devel/msg33917.html v2: - Add the sg_for_each_page macro to /lib/scatterlist instead of drivers/drm. This is a separate patchset being merged through the -mm tree. - Use the sg_for_each_page macro in the gtt pte setup code too. Imre Deak (4): drm: handle compact dma scatter lists in drm_clflush_sg() drm/i915: handle walking compact dma scatter lists drm/i915: create compact dma scatter lists for gem objects drm/i915: use for_each_sg_page for setting up the gtt ptes drivers/gpu/drm/drm_cache.c|7 ++-- drivers/gpu/drm/i915/i915_drv.h| 17 +++- drivers/gpu/drm/i915/i915_gem.c| 55 ++ drivers/gpu/drm/i915/i915_gem_dmabuf.c | 13 --- drivers/gpu/drm/i915/i915_gem_gtt.c| 67 drivers/gpu/drm/i915/i915_gem_tiling.c | 18 + 6 files changed, 80 insertions(+), 97 deletions(-) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/4] drm/i915: create compact dma scatter lists for gem objects
So far we created a sparse dma scatter list for gem objects, where each
scatter list entry represented only a single page. In the future we'll
have to handle compact scatter lists too where each entry can consist of
multiple pages, for example for objects imported through PRIME.
The previous patches have already fixed up all other places where the
i915 driver _walked_ these lists. Here we have the corresponding fix to
_create_ compact lists. It's not a performance or memory footprint
improvement, but it helps to better exercise the new logic.
Reference: http://www.spinics.net/lists/dri-devel/msg33917.html
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 03037cf..ec2f11f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1625,9 +1625,8 @@ i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj)
static void
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
{
- int page_count = obj-base.size / PAGE_SIZE;
- struct scatterlist *sg;
- int ret, i;
+ struct sg_page_iter sg_iter;
+ int ret;
BUG_ON(obj-madv == __I915_MADV_PURGED);
@@ -1647,8 +1646,8 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj)
if (obj-madv == I915_MADV_DONTNEED)
obj-dirty = 0;
- for_each_sg(obj-pages-sgl, sg, page_count, i) {
- struct page *page = sg_page(sg);
+ for_each_sg_page(obj-pages-sgl, sg_iter, obj-pages-nents, 0) {
+ struct page *page = sg_iter.page;
if (obj-dirty)
set_page_dirty(page);
@@ -1749,7 +1748,9 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj)
struct address_space *mapping;
struct sg_table *st;
struct scatterlist *sg;
+ struct sg_page_iter sg_iter;
struct page *page;
+ unsigned long last_pfn = 0; /* suppress gcc warning */
gfp_t gfp;
/* Assert that the object is not currently in any GPU domain. As it
@@ -1779,7 +1780,9 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj)
gfp = mapping_gfp_mask(mapping);
gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
gfp = ~(__GFP_IO | __GFP_WAIT);
- for_each_sg(st-sgl, sg, page_count, i) {
+ sg = st-sgl;
+ st-nents = 0;
+ for (i = 0; i page_count; i++) {
page = shmem_read_mapping_page_gfp(mapping, i, gfp);
if (IS_ERR(page)) {
i915_gem_purge(dev_priv, page_count);
@@ -1802,9 +1805,18 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj)
gfp = ~(__GFP_IO | __GFP_WAIT);
}
- sg_set_page(sg, page, PAGE_SIZE, 0);
+ if (!i || page_to_pfn(page) != last_pfn + 1) {
+ if (i)
+ sg = sg_next(sg);
+ st-nents++;
+ sg_set_page(sg, page, PAGE_SIZE, 0);
+ } else {
+ sg-length += PAGE_SIZE;
+ }
+ last_pfn = page_to_pfn(page);
}
+ sg_mark_end(sg);
obj-pages = st;
if (i915_gem_object_needs_bit17_swizzle(obj))
@@ -1813,8 +1825,9 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj)
return 0;
err_pages:
- for_each_sg(st-sgl, sg, i, page_count)
- page_cache_release(sg_page(sg));
+ sg_mark_end(sg);
+ for_each_sg_page(st-sgl, sg_iter, st-nents, 0)
+ page_cache_release(sg_iter.page);
sg_free_table(st);
kfree(st);
return PTR_ERR(page);
--
1.7.10.4
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[Intel-gfx] [PATCH v2 4/4] drm/i915: use for_each_sg_page for setting up the gtt ptes
The existing gtt setup code is correct - and so doesn't need to be fixed to
handle compact dma scatter lists similarly to the previous patches. Still,
take the for_each_sg_page macro into use, to get somewhat simpler code.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +--
1 file changed, 24 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 926a1e2..0c32054 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -116,41 +116,26 @@ static void gen6_ppgtt_insert_entries(struct
i915_hw_ppgtt *ppgtt,
{
gtt_pte_t *pt_vaddr;
unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
- unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
- unsigned i, j, m, segment_len;
- dma_addr_t page_addr;
- struct scatterlist *sg;
-
- /* init sg walking */
- sg = pages-sgl;
- i = 0;
- segment_len = sg_dma_len(sg) PAGE_SHIFT;
- m = 0;
-
- while (i pages-nents) {
- pt_vaddr = kmap_atomic(ppgtt-pt_pages[act_pd]);
-
- for (j = first_pte; j I915_PPGTT_PT_ENTRIES; j++) {
- page_addr = sg_dma_address(sg) + (m PAGE_SHIFT);
- pt_vaddr[j] = gen6_pte_encode(ppgtt-dev, page_addr,
- cache_level);
-
- /* grab the next page */
- if (++m == segment_len) {
- if (++i == pages-nents)
- break;
+ unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
+ struct sg_page_iter sg_iter;
+
+ pt_vaddr = kmap_atomic(ppgtt-pt_pages[act_pd]);
+ for_each_sg_page(pages-sgl, sg_iter, pages-nents, 0) {
+ dma_addr_t page_addr;
+
+ page_addr = sg_dma_address(sg_iter.sg) +
+ (sg_iter.sg_pgoffset PAGE_SHIFT);
+ pt_vaddr[act_pte] = gen6_pte_encode(ppgtt-dev, page_addr,
+ cache_level);
+ if (++act_pte == I915_PPGTT_PT_ENTRIES) {
+ kunmap_atomic(pt_vaddr);
+ act_pd++;
+ pt_vaddr = kmap_atomic(ppgtt-pt_pages[act_pd]);
+ act_pte = 0;
- sg = sg_next(sg);
- segment_len = sg_dma_len(sg) PAGE_SHIFT;
- m = 0;
- }
}
-
- kunmap_atomic(pt_vaddr);
-
- first_pte = 0;
- act_pd++;
}
+ kunmap_atomic(pt_vaddr);
}
static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
@@ -432,21 +417,17 @@ static void gen6_ggtt_insert_entries(struct drm_device
*dev,
enum i915_cache_level level)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- struct scatterlist *sg = st-sgl;
gtt_pte_t __iomem *gtt_entries =
(gtt_pte_t __iomem *)dev_priv-gtt.gsm + first_entry;
- int unused, i = 0;
- unsigned int len, m = 0;
+ int i = 0;
+ struct sg_page_iter sg_iter;
dma_addr_t addr;
- for_each_sg(st-sgl, sg, st-nents, unused) {
- len = sg_dma_len(sg) PAGE_SHIFT;
- for (m = 0; m len; m++) {
- addr = sg_dma_address(sg) + (m PAGE_SHIFT);
- iowrite32(gen6_pte_encode(dev, addr, level),
- gtt_entries[i]);
- i++;
- }
+ for_each_sg_page(st-sgl, sg_iter, st-nents, 0) {
+ addr = sg_dma_address(sg_iter.sg) +
+ (sg_iter.sg_pgoffset PAGE_SHIFT);
+ iowrite32(gen6_pte_encode(dev, addr, level), gtt_entries[i]);
+ i++;
}
/* XXX: This serves as a posting read to make sure that the PTE has
--
1.7.10.4
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Re: [Intel-gfx] [PATCH] drm/i915: Remove platforms in the preliminary_hw_support description
On Mon, Feb 18, 2013 at 04:47:42PM +, Damien Lespiau wrote: We already managed to get it out of sync (Haswell has been promoted out of this option), so let's remove all mentions to platforms. Signed-off-by: Damien Lespiau damien.lesp...@intel.com Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] drm/i915: drm/i915: create macros for the unclaimed register checks
On Fri, Feb 08, 2013 at 05:35:12PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
This avoids polluting i915_write##x and also allows us to reuse code
on i915_read##x.
v2: Rebase
Reviewed-by: Ben Widawsky b...@bwidawsk.net (v1)
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Checkpatch complained about the macro parameters not being enclosed in
(reg) params. I tend to agree, so maybe just extract the entire thing into
a static inline function while at it?
-Daniel
---
drivers/gpu/drm/i915/i915_drv.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c5b8c81..e24c337 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,6 +1131,20 @@ ilk_dummy_write(struct drm_i915_private *dev_priv)
I915_WRITE_NOTRACE(MI_MODE, 0);
}
+#define UNCLAIMED_REG_CLEAR(dev_priv, reg) \
+ if (IS_HASWELL(dev_priv-dev) \
+ (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) { \
+ DRM_ERROR(Unknown unclaimed register before writing to %x\n,
reg); \
+ I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
+ }
+
+#define UNCLAIMED_REG_CHECK(dev_priv, reg) \
+ if (IS_HASWELL(dev_priv-dev) \
+ (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) { \
+ DRM_ERROR(Unclaimed write to %x\n, reg); \
+ writel(ERR_INT_MMIO_UNCLAIMED, dev_priv-regs + GEN7_ERR_INT); \
+ }
+
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
u##x val = 0; \
@@ -1167,18 +1181,12 @@ void i915_write##x(struct drm_i915_private *dev_priv,
u32 reg, u##x val) { \
} \
if (IS_GEN5(dev_priv-dev)) \
ilk_dummy_write(dev_priv); \
- if (IS_HASWELL(dev_priv-dev) (I915_READ_NOTRACE(GEN7_ERR_INT)
ERR_INT_MMIO_UNCLAIMED)) { \
- DRM_ERROR(Unknown unclaimed register before writing to %x\n,
reg); \
- I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
- } \
+ UNCLAIMED_REG_CLEAR(dev_priv, reg); \
write##y(val, dev_priv-regs + reg); \
if (unlikely(__fifo_ret)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
- if (IS_HASWELL(dev_priv-dev) (I915_READ_NOTRACE(GEN7_ERR_INT)
ERR_INT_MMIO_UNCLAIMED)) { \
- DRM_ERROR(Unclaimed write to %x\n, reg); \
- writel(ERR_INT_MMIO_UNCLAIMED, dev_priv-regs + GEN7_ERR_INT);
\
- } \
+ UNCLAIMED_REG_CHECK(dev_priv, reg); \
}
__i915_write(8, b)
__i915_write(16, w)
--
1.7.10.4
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] [PATCH i-g-t/libdrm] Massasge intel_chipset.h
The main thing here is to make the macros a bit safer by wrapping the macro argument evaluations in parens. Since that already touching huge portion of the file, I went a bit further and make the whitespace style uniform throughout the file. The other two small patches just unify the i-g-t and libdrm copies of the file a bit more. The diff between them is now just a few macros existing in only one copy, some whitespace/word difference in the license text, and different copyright holders :) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] intel_chipset: Use parens around macro arguments
From: Ville Syrjälä ville.syrj...@linux.intel.com Protect the macro argument evaluations with parens. This is already touching most lines, so while at it, fix up all white space to uniform style throughout the file. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- lib/intel_chipset.h | 308 ++-- 1 file changed, 154 insertions(+), 154 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 456e367..6b4fab3 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -49,26 +49,26 @@ #define PCI_CHIP_IGD_GM0xA011 #define PCI_CHIP_IGD_G 0xA001 -#define IS_IGDGM(devid)(devid == PCI_CHIP_IGD_GM) -#define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G) -#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) +#define IS_IGDGM(devid)((devid) == PCI_CHIP_IGD_GM) +#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) +#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) #define PCI_CHIP_I965_G0x29A2 #define PCI_CHIP_I965_Q0x2992 #define PCI_CHIP_I965_G_1 0x2982 #define PCI_CHIP_I946_GZ 0x2972 -#define PCI_CHIP_I965_GM0x2A02 -#define PCI_CHIP_I965_GME 0x2A12 +#define PCI_CHIP_I965_GM 0x2A02 +#define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_GM45_GM0x2A42 +#define PCI_CHIP_GM45_GM 0x2A42 -#define PCI_CHIP_IGD_E_G0x2E02 -#define PCI_CHIP_Q45_G 0x2E12 -#define PCI_CHIP_G45_G 0x2E22 -#define PCI_CHIP_G41_G 0x2E32 +#define PCI_CHIP_IGD_E_G 0x2E02 +#define PCI_CHIP_Q45_G 0x2E12 +#define PCI_CHIP_G45_G 0x2E22 +#define PCI_CHIP_G41_G 0x2E32 -#define PCI_CHIP_ILD_G 0x0042 -#define PCI_CHIP_ILM_G 0x0046 +#define PCI_CHIP_ILD_G 0x0042 +#define PCI_CHIP_ILM_G 0x0046 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 @@ -85,164 +85,164 @@ #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ -#define PCI_CHIP_HASWELL_GT10x0402 /* Desktop */ -#define PCI_CHIP_HASWELL_GT20x0412 -#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 -#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ -#define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 -#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ -#define PCI_CHIP_HASWELL_S_GT2 0x041A -#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A -#define PCI_CHIP_HASWELL_SDV_GT10x0C02 /* Desktop */ -#define PCI_CHIP_HASWELL_SDV_GT20x0C12 -#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 -#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ -#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 -#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 -#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ -#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A -#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A -#define PCI_CHIP_HASWELL_ULT_GT10x0A02 /* Desktop */ -#define PCI_CHIP_HASWELL_ULT_GT20x0A12 -#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 -#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ -#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 -#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 -#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ -#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A -#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_GT10x0D12 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT20x0D22 -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ +#define PCI_CHIP_HASWELL_GT2 0x0412 +#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 +#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ +#define PCI_CHIP_HASWELL_M_GT2 0x0416 +#define PCI_CHIP_HASWELL_M_GT2_PLUS0x0426 +#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ +#define PCI_CHIP_HASWELL_S_GT2 0x041A +#define PCI_CHIP_HASWELL_S_GT2_PLUS0x042A +#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ +#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +#define
[Intel-gfx] [PATCH i-g-t 2/2] intel_chipset: Add multiple inclusion guards into intel_chipset.h
From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- lib/intel_chipset.h | 5 + 1 file changed, 5 insertions(+) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 6b4fab3..f703239 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -25,6 +25,9 @@ * */ +#ifndef _INTEL_CHIPSET_H +#define _INTEL_CHIPSET_H + #define PCI_CHIP_I810 0x7121 #define PCI_CHIP_I810_DC1000x7123 #define PCI_CHIP_I810_E0x7125 @@ -274,3 +277,5 @@ #define IS_CRESTLINE(devid)((devid) == PCI_CHIP_I965_GM || \ (devid) == PCI_CHIP_I965_GME) + +#endif /* _INTEL_CHIPSET_H */ -- 1.7.12.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH libdrm 1/2] intel_chipset: Use parens around macro arguments
From: Ville Syrjälä ville.syrj...@linux.intel.com Protect the macro argument evaluations with parens. This is already touching most lines, so while at it, fix up all white space to uniform style throughout the file. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- intel/intel_chipset.h | 310 +- 1 file changed, 155 insertions(+), 155 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3123a90..8af5acf 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -52,26 +52,26 @@ #define PCI_CHIP_IGD_GM0xA011 #define PCI_CHIP_IGD_G 0xA001 -#define IS_IGDGM(devid)(devid == PCI_CHIP_IGD_GM) -#define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G) -#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) +#define IS_IGDGM(devid)((devid) == PCI_CHIP_IGD_GM) +#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) +#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) #define PCI_CHIP_I965_G0x29A2 #define PCI_CHIP_I965_Q0x2992 #define PCI_CHIP_I965_G_1 0x2982 #define PCI_CHIP_I946_GZ 0x2972 -#define PCI_CHIP_I965_GM0x2A02 -#define PCI_CHIP_I965_GME 0x2A12 +#define PCI_CHIP_I965_GM 0x2A02 +#define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_GM45_GM0x2A42 +#define PCI_CHIP_GM45_GM 0x2A42 -#define PCI_CHIP_IGD_E_G0x2E02 -#define PCI_CHIP_Q45_G 0x2E12 -#define PCI_CHIP_G45_G 0x2E22 -#define PCI_CHIP_G41_G 0x2E32 +#define PCI_CHIP_IGD_E_G 0x2E02 +#define PCI_CHIP_Q45_G 0x2E12 +#define PCI_CHIP_G45_G 0x2E22 +#define PCI_CHIP_G41_G 0x2E32 -#define PCI_CHIP_ILD_G 0x0042 -#define PCI_CHIP_ILM_G 0x0046 +#define PCI_CHIP_ILD_G 0x0042 +#define PCI_CHIP_ILM_G 0x0046 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 @@ -88,169 +88,169 @@ #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ -#define PCI_CHIP_HASWELL_GT10x0402 /* Desktop */ -#define PCI_CHIP_HASWELL_GT20x0412 -#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 -#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ -#define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 -#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ -#define PCI_CHIP_HASWELL_S_GT2 0x041A -#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A -#define PCI_CHIP_HASWELL_SDV_GT10x0C02 /* Desktop */ -#define PCI_CHIP_HASWELL_SDV_GT20x0C12 -#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 -#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ -#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 -#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 -#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ -#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A -#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A -#define PCI_CHIP_HASWELL_ULT_GT10x0A02 /* Desktop */ -#define PCI_CHIP_HASWELL_ULT_GT20x0A12 -#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 -#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ -#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 -#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 -#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ -#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A -#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_GT10x0D12 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT20x0D22 -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ +#define PCI_CHIP_HASWELL_GT2 0x0412 +#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 +#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ +#define PCI_CHIP_HASWELL_M_GT2 0x0416 +#define PCI_CHIP_HASWELL_M_GT2_PLUS0x0426 +#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ +#define PCI_CHIP_HASWELL_S_GT2 0x041A +#define PCI_CHIP_HASWELL_S_GT2_PLUS0x042A +#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ +#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +#define
[Intel-gfx] [PATCH libdrm 2/2] intel_chipset: Fix up VLV confusion
From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- intel/intel_chipset.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 8af5acf..2760dc8 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -192,15 +192,15 @@ (devid) == PCI_CHIP_SANDYBRIDGE_S) #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ -IS_HASWELL(devid)) +IS_HASWELL(devid) || \ +IS_VALLEYVIEW(devid)) #define IS_IVYBRIDGE(devid)((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \ (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \ (devid) == PCI_CHIP_IVYBRIDGE_S || \ -(devid) == PCI_CHIP_IVYBRIDGE_S_GT2 || \ -(devid) == PCI_CHIP_VALLEYVIEW_PO) +(devid) == PCI_CHIP_IVYBRIDGE_S_GT2) #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ (devid) == PCI_CHIP_VALLEYVIEW_1 || \ -- 1.7.12.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915: create functions for the unclaimed register checks
From: Paulo Zanoni paulo.r.zan...@intel.com
This avoids polluting i915_write##x and also allows us to reuse code
on i915_read##x.
v2: Rebase
v3: Convert the macros to static functions
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c5b8c81..b820c26 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,6 +1131,27 @@ ilk_dummy_write(struct drm_i915_private *dev_priv)
I915_WRITE_NOTRACE(MI_MODE, 0);
}
+static void
+hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
+{
+ if (IS_HASWELL(dev_priv-dev)
+ (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) {
+ DRM_ERROR(Unknown unclaimed register before writing to %x\n,
+ reg);
+ I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED);
+ }
+}
+
+static void
+hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
+{
+ if (IS_HASWELL(dev_priv-dev)
+ (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) {
+ DRM_ERROR(Unclaimed write to %x\n, reg);
+ writel(ERR_INT_MMIO_UNCLAIMED, dev_priv-regs + GEN7_ERR_INT);
+ }
+}
+
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
u##x val = 0; \
@@ -1167,18 +1188,12 @@ void i915_write##x(struct drm_i915_private *dev_priv,
u32 reg, u##x val) { \
} \
if (IS_GEN5(dev_priv-dev)) \
ilk_dummy_write(dev_priv); \
- if (IS_HASWELL(dev_priv-dev) (I915_READ_NOTRACE(GEN7_ERR_INT)
ERR_INT_MMIO_UNCLAIMED)) { \
- DRM_ERROR(Unknown unclaimed register before writing to %x\n,
reg); \
- I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
- } \
+ hsw_unclaimed_reg_clear(dev_priv, reg); \
write##y(val, dev_priv-regs + reg); \
if (unlikely(__fifo_ret)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
- if (IS_HASWELL(dev_priv-dev) (I915_READ_NOTRACE(GEN7_ERR_INT)
ERR_INT_MMIO_UNCLAIMED)) { \
- DRM_ERROR(Unclaimed write to %x\n, reg); \
- writel(ERR_INT_MMIO_UNCLAIMED, dev_priv-regs + GEN7_ERR_INT);
\
- } \
+ hsw_unclaimed_reg_check(dev_priv, reg); \
}
__i915_write(8, b)
__i915_write(16, w)
--
1.7.10.4
___
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[Intel-gfx] [PATCH 3/8] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise, if the BIOS did anything wrong, our first I915_{WRITE,READ}
will give us unclaimed register messages.
V2: Even earlier.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58897
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c |4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4fa6beb..6d8672e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1542,6 +1542,10 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
goto put_gmch;
}
+ /* This must happen before any I915_{READ,WRITE}: */
+ if (IS_HASWELL(dev))
+ I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+
aperture_size = dev_priv-gtt.mappable_end;
dev_priv-gtt.mappable =
--
1.7.10.4
___
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[Intel-gfx] [PATCH 5/8] drm/i915: wait_event_timeout's timeout is in jiffies
From: Paulo Zanoni paulo.r.zan...@intel.com So use msecs_to_jiffies(10) to make the timeout the same as in the !has_aux_irq case. This patch was initially written by Daniel Vetter and posted on pastebin a few weeks ago. I'm just bringing it to the mailing list. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_dp.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 770ec90..00bc79f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -353,7 +353,8 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) #define C (((status = I915_READ_NOTRACE(ch_ctl)) DP_AUX_CH_CTL_SEND_BUSY) == 0) if (has_aux_irq) - done = wait_event_timeout(dev_priv-gmbus_wait_queue, C, 10); + done = wait_event_timeout(dev_priv-gmbus_wait_queue, C, + msecs_to_jiffies(10)); else done = wait_for_atomic(C, 10) == 0; if (!done) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/8] drm/i915: add aux_ch_ctl_reg to struct intel_dp
From: Paulo Zanoni paulo.r.zan...@intel.com
This way we can remove some duplicated code and avoid more mistakes
and regressions with these registers in the future.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 66 --
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 22 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 00bc79f..0e2750c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -328,29 +328,10 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool
has_aux_irq)
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- uint32_t ch_ctl = intel_dp-output_reg + 0x10;
+ uint32_t ch_ctl = intel_dp-aux_ch_ctl_reg;
uint32_t status;
bool done;
- if (HAS_DDI(dev)) {
- switch (intel_dig_port-port) {
- case PORT_A:
- ch_ctl = DPA_AUX_CH_CTL;
- break;
- case PORT_B:
- ch_ctl = PCH_DPB_AUX_CH_CTL;
- break;
- case PORT_C:
- ch_ctl = PCH_DPC_AUX_CH_CTL;
- break;
- case PORT_D:
- ch_ctl = PCH_DPD_AUX_CH_CTL;
- break;
- default:
- BUG();
- }
- }
-
#define C (((status = I915_READ_NOTRACE(ch_ctl)) DP_AUX_CH_CTL_SEND_BUSY) ==
0)
if (has_aux_irq)
done = wait_event_timeout(dev_priv-gmbus_wait_queue, C,
@@ -370,11 +351,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
uint8_t *send, int send_bytes,
uint8_t *recv, int recv_size)
{
- uint32_t output_reg = intel_dp-output_reg;
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- uint32_t ch_ctl = output_reg + 0x10;
+ uint32_t ch_ctl = intel_dp-aux_ch_ctl_reg;
uint32_t ch_data = ch_ctl + 4;
int i, ret, recv_bytes;
uint32_t status;
@@ -388,29 +368,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
*/
pm_qos_update_request(dev_priv-pm_qos, 0);
- if (HAS_DDI(dev)) {
- switch (intel_dig_port-port) {
- case PORT_A:
- ch_ctl = DPA_AUX_CH_CTL;
- ch_data = DPA_AUX_CH_DATA1;
- break;
- case PORT_B:
- ch_ctl = PCH_DPB_AUX_CH_CTL;
- ch_data = PCH_DPB_AUX_CH_DATA1;
- break;
- case PORT_C:
- ch_ctl = PCH_DPC_AUX_CH_CTL;
- ch_data = PCH_DPC_AUX_CH_DATA1;
- break;
- case PORT_D:
- ch_ctl = PCH_DPD_AUX_CH_CTL;
- ch_data = PCH_DPD_AUX_CH_DATA1;
- break;
- default:
- BUG();
- }
- }
-
intel_dp_check_edp(intel_dp);
/* The clock divider is based off the hrawclk,
* and would like to run at 2MHz. So, take the
@@ -2832,6 +2789,25 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
else
intel_connector-get_hw_state = intel_connector_get_hw_state;
+ intel_dp-aux_ch_ctl_reg = intel_dp-output_reg + 0x10;
+ if (HAS_DDI(dev)) {
+ switch (intel_dig_port-port) {
+ case PORT_A:
+ intel_dp-aux_ch_ctl_reg = DPA_AUX_CH_CTL;
+ break;
+ case PORT_B:
+ intel_dp-aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
+ break;
+ case PORT_C:
+ intel_dp-aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
+ break;
+ case PORT_D:
+ intel_dp-aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
+ break;
+ default:
+ BUG();
+ }
+ }
/* Set up the DDC bus. */
switch (port) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 005a91f..6f41a07 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -366,6 +366,7 @@ struct intel_hdmi {
struct intel_dp {
uint32_t output_reg;
+ uint32_t aux_ch_ctl_reg;
uint32_t DP;
uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
bool has_audio;
--
1.7.10.4
___
[Intel-gfx] [PATCH 7/8] drm/i915: rename sdvox_reg to hdmi_reg on HDMI context
From: Paulo Zanoni paulo.r.zan...@intel.com
Some (but not all) of the HDMI registers can be used to control sDVO,
so those registers have two names. IMHO, when we're talking about
HDMI, we really should call the HDMI control register hdmi_reg
instead of sdvox_reg, otherwise we'll just confuse people reading
our code (we now have platforms with HDMI but without SDVO). So now
struct intel_hdmi has a member called hdmi_reg instead of
sdvox_reg.
Also, don't worry: struct intel_sdvo still has a member called
sdvo_reg.
v2: Rebase (v1 was sent in May 2012).
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c |4 +--
drivers/gpu/drm/i915/intel_drv.h |4 +--
drivers/gpu/drm/i915/intel_hdmi.c | 72 ++---
3 files changed, 39 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 816c45c..56bb7cb 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1538,9 +1538,7 @@ void intel_ddi_init(struct drm_device *dev, enum port
port)
intel_dig_port-port_reversal = I915_READ(DDI_BUF_CTL(port))
DDI_BUF_PORT_REVERSAL;
if (hdmi_connector)
- intel_dig_port-hdmi.sdvox_reg = DDI_BUF_CTL(port);
- else
- intel_dig_port-hdmi.sdvox_reg = 0;
+ intel_dig_port-hdmi.hdmi_reg = DDI_BUF_CTL(port);
intel_dig_port-dp.output_reg = DDI_BUF_CTL(port);
intel_encoder-type = INTEL_OUTPUT_UNKNOWN;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6f41a07..8659df2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -347,7 +347,7 @@ struct dip_infoframe {
} __attribute__((packed));
struct intel_hdmi {
- u32 sdvox_reg;
+ u32 hdmi_reg;
int ddc_bus;
uint32_t color_range;
bool color_range_auto;
@@ -444,7 +444,7 @@ extern void intel_attach_broadcast_rgb_property(struct
drm_connector *connector)
extern void intel_crt_init(struct drm_device *dev);
extern void intel_hdmi_init(struct drm_device *dev,
- int sdvox_reg, enum port port);
+ int hdmi_reg, enum port port);
extern void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
struct intel_connector *intel_connector);
extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index ed65c6d..fcb36c6 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -50,7 +50,7 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
- WARN(I915_READ(intel_hdmi-sdvox_reg) enabled_bits,
+ WARN(I915_READ(intel_hdmi-hdmi_reg) enabled_bits,
HDMI port enabled, expecting disabled\n);
}
@@ -597,40 +597,40 @@ static void intel_hdmi_mode_set(struct drm_encoder
*encoder,
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder-crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- u32 sdvox;
+ u32 hdmi_val;
- sdvox = SDVO_ENCODING_HDMI;
+ hdmi_val = SDVO_ENCODING_HDMI;
if (!HAS_PCH_SPLIT(dev))
- sdvox |= intel_hdmi-color_range;
+ hdmi_val |= intel_hdmi-color_range;
if (adjusted_mode-flags DRM_MODE_FLAG_PVSYNC)
- sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
+ hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
if (adjusted_mode-flags DRM_MODE_FLAG_PHSYNC)
- sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
+ hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
if (intel_crtc-bpp 24)
- sdvox |= COLOR_FORMAT_12bpc;
+ hdmi_val |= COLOR_FORMAT_12bpc;
else
- sdvox |= COLOR_FORMAT_8bpc;
+ hdmi_val |= COLOR_FORMAT_8bpc;
/* Required on CPT */
if (intel_hdmi-has_hdmi_sink HAS_PCH_CPT(dev))
- sdvox |= HDMI_MODE_SELECT;
+ hdmi_val |= HDMI_MODE_SELECT;
if (intel_hdmi-has_audio) {
DRM_DEBUG_DRIVER(Enabling HDMI audio on pipe %c\n,
pipe_name(intel_crtc-pipe));
- sdvox |= SDVO_AUDIO_ENABLE;
- sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
+ hdmi_val |= SDVO_AUDIO_ENABLE;
+ hdmi_val |= SDVO_NULL_PACKETS_DURING_VSYNC;
intel_write_eld(encoder, adjusted_mode);
}
if (HAS_PCH_CPT(dev))
- sdvox |= PORT_TRANS_SEL_CPT(intel_crtc-pipe);
+ hdmi_val |= PORT_TRANS_SEL_CPT(intel_crtc-pipe);
else if (intel_crtc-pipe == PIPE_B)
-
[Intel-gfx] [PATCH 8/8] drm/i915: clarify confusion between SDVO and HDMI registers
From: Paulo Zanoni paulo.r.zan...@intel.com
Some HDMI registers can be used for SDVO, so saying HDMIB should be
the same as saying SDVOB for a given HW generation. This was not
true and led to confusions and even a regression.
Previously we had:
- SDVO{B,C} defined as the Gen3+ registers
- HDMI{B,C,D} and PCH_SDVOB defined as the PCH registers
But now:
- SDVO{B,C} became GEN3_SDVO{B,C} on SDVO code
- SDVO{B,C} became GEN4_HDMI{B,C} on HDMI code
- HDMI{B,C,D} became PCH_HDMI{B,C,D}
- PCH_SDVOB is still the same thing
v2: Rebase (v1 was sent in May 2012).
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 19 ---
drivers/gpu/drm/i915/intel_display.c | 42 ++
drivers/gpu/drm/i915/intel_sdvo.c| 22 +-
3 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9e5844b..cd31af2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1680,8 +1680,9 @@
#define SDVOB_HOTPLUG_INT_STATUS_I915(1 6)
/* SDVO port control */
-#define SDVOB 0x61140
-#define SDVOC 0x61160
+#define GEN3_SDVOB 0x61140
+#define GEN3_SDVOC 0x61160
+#define PCH_SDVOB 0xe1140
#define SDVO_ENABLE (1 31)
#define SDVO_PIPE_B_SELECT (1 30)
#define SDVO_STALL_SELECT(1 29)
@@ -3979,8 +3980,12 @@
#define FDI_PLL_CTL_1 0xfe000
#define FDI_PLL_CTL_2 0xfe004
-/* or SDVOB */
-#define HDMIB 0xe1140
+/* The same register may be used for SDVO or HDMI */
+#define GEN4_HDMIB GEN3_SDVOB
+#define GEN4_HDMIC GEN3_SDVOC
+#define PCH_HDMIB PCH_SDVOB
+#define PCH_HDMIC 0xe1150
+#define PCH_HDMID 0xe1160
#define PORT_ENABLE(1 31)
#define TRANSCODER(pipe) ((pipe) 30)
#define TRANSCODER_CPT(pipe) ((pipe) 29)
@@ -4001,12 +4006,6 @@
#define HSYNC_ACTIVE_HIGH (1 3)
#define PORT_DETECTED (1 2)
-/* PCH SDVOB multiplex with HDMIB */
-#define PCH_SDVOB HDMIB
-
-#define HDMIC 0xe1150
-#define HDMID 0xe1160
-
#define PCH_LVDS 0xe1180
#define LVDS_DETECTED (1 1)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6eb3882..744db70 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1419,9 +1419,9 @@ static void assert_pch_ports_disabled(struct
drm_i915_private *dev_priv,
PCH LVDS enabled on transcoder %c, should be disabled\n,
pipe_name(pipe));
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
- assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
}
/**
@@ -8323,20 +8323,20 @@ static void intel_setup_outputs(struct drm_device *dev)
if (has_edp_a(dev))
intel_dp_init(dev, DP_A, PORT_A);
- if (I915_READ(HDMIB) PORT_DETECTED) {
+ if (I915_READ(PCH_HDMIB) PORT_DETECTED) {
/* PCH SDVOB multiplex with HDMIB */
found = intel_sdvo_init(dev, PCH_SDVOB, true);
if (!found)
- intel_hdmi_init(dev, HDMIB, PORT_B);
+ intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
if (!found (I915_READ(PCH_DP_B) DP_DETECTED))
intel_dp_init(dev, PCH_DP_B, PORT_B);
}
- if (I915_READ(HDMIC) PORT_DETECTED)
- intel_hdmi_init(dev, HDMIC, PORT_C);
+ if (I915_READ(PCH_HDMIC) PORT_DETECTED)
+ intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
- if (!dpd_is_edp I915_READ(HDMID) PORT_DETECTED)
- intel_hdmi_init(dev, HDMID, PORT_D);
+ if (!dpd_is_edp I915_READ(PCH_HDMID) PORT_DETECTED)
+ intel_hdmi_init(dev, PCH_HDMID, PORT_D);
if (I915_READ(PCH_DP_C) DP_DETECTED)
intel_dp_init(dev, PCH_DP_C, PORT_C);
@@ -8348,24 +8348,26 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(VLV_DISPLAY_BASE + DP_C) DP_DETECTED)
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
- if (I915_READ(VLV_DISPLAY_BASE + SDVOB) PORT_DETECTED) {
- intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
+ if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) PORT_DETECTED) {
+ intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
+
Re: [Intel-gfx] [Alsa-user] intel-hda: sound via HDMI only when using interlaced modes
On Thu, Feb 07, 2013 at 11:00:13AM +0100, Daniel Vetter wrote: On Wed, Feb 06, 2013 at 10:35:33PM +0100, David Härdeman wrote: a) switching between 1080p30 and 1080p50 or 1080p60 is enough to make the sound go away (higher frame rates) or work (1080p30). So, it has nothing to do with interlacing. I'm far away from an hdmi/snd expert, but iirc the bandwidth to squeeze hdmi sound packets between the video frames is limited. And atm our code does not bother with checking for that at all (and updating the capabilities of the hdmi snd widget). But that's just an idea, I have no idea how much bandwidth there actually is. I spent some time this weekend dumping the audio related registers while outputting a stereo stream under Windows. It turns out that 48kHz stereo audio works under windows (16bit, 48kHz stereo audio is the default setting in Win7 for a shared audio device) while 44.1kHz doesn't (with the Pioneer SC LX-76 receiver). I've also tested with a different receiver (Marantz SR8002) and it happily accepts 44.1kHz and 48kHz stereo audio (only tested with Win7) so I'm guessing that the Pioneer receiver is being picky and/or buggy (esp. with regard to 44.1kHz audio). Anyway, since 48kHz audio works under Windows and not under Linux, the Windows driver was doing something right. I've narrowed it down to the Pixel_Clock(HDMI) bits (19:16) in register AUD_CONFIG_A. The Linux driver currently sets the entire register blindly to 0x0 (see the write to aud_config in ironlake_write_eld() in drivers/gpu/drm/i915/intel_display.c) while it should set those bits in accordance with the HDMI pixel clock of the mode that is about to be set (which the Windows driver does). Manually setting those bits to eg 0x9 (which would be the correct value for a 1080p60 mode which uses a 148.5Mhz pixel clock) gets me working 48kHz audio (i.e. feature parity with Windows) when running in 1080p60. (And on a big sidenote...the value 0x6, which corresponds to a 74.25/1.001 Mhz pixel clock, gets me working 44.1kHz *and* 48kHz audio no matter what the resolution/refresh rate is...must be some kind of Pioneer quirk...but I'm happy it exists). I could write a patch, but the Intel docs (IHD-OS-V3 Pt 4, section 4.2.1, pp 87 - 88) are a bit terse so I'm a bit nervous about whether I'd get it right or not... -- David Härdeman ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel tree
Hi Daniel, On Fri, 15 Feb 2013 08:16:26 -0800 Jesse Barnes jbar...@virtuousgeek.org wrote: On Fri, 15 Feb 2013 10:30:16 +0100 Daniel Vetter daniel.vet...@ffwll.ch wrote: On Fri, Feb 15, 2013 at 3:37 AM, Stephen Rothwell s...@canb.auug.org.au wrote: After merging the drm-intel tree, today's linux-next build (x86_64 allmodconfig) failed like this: ERROR: pm_vt_switch_unregister [drivers/video/fb.ko] undefined! I have dropped the tree for today. Meh, that fail was already reported from Wu's kernel builder a few days ago, but no patch yet showed up to fix things. Since the i915 side of that work isn't ready yet either I've dropped the offending patches. I sent a patch yesterday for this. I'll bounce it over again. I am still getting that build failure. -- Cheers, Stephen Rothwells...@canb.auug.org.au pgp0zWQkl_7yx.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Vanish some unused 3d commands
i915_reg.h is messy enough without the extra stuff. Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_reg.h | 21 - 1 file changed, 21 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 11fbeec..f7e7037 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -275,29 +275,10 @@ */ #define GFX_INSTR(opcode, flags) ((0x3 29) | ((opcode) 24) | (flags)) -#define GFX_OP_RASTER_RULES((0x329)|(0x724)) -#define GFX_OP_SCISSOR ((0x329)|(0x1c24)|(0x1019)) -#define SC_UPDATE_SCISSOR (0x11) -#define SC_ENABLE_MASK (0x10) -#define SC_ENABLE (0x10) -#define GFX_OP_LOAD_INDIRECT ((0x329)|(0x1d24)|(0x716)) -#define GFX_OP_SCISSOR_INFO((0x329)|(0x1d24)|(0x8116)|(0x1)) -#define SCI_YMIN_MASK (0x16) -#define SCI_XMIN_MASK (0x0) -#define SCI_YMAX_MASK (0x16) -#define SCI_XMAX_MASK (0x0) -#define GFX_OP_SCISSOR_ENABLE ((0x329)|(0x1c24)|(0x1019)) -#define GFX_OP_SCISSOR_RECT ((0x329)|(0x1d24)|(0x8116)|1) -#define GFX_OP_COLOR_FACTOR ((0x329)|(0x1d24)|(0x116)|0x0) -#define GFX_OP_STIPPLE ((0x329)|(0x1d24)|(0x8316)) -#define GFX_OP_MAP_INFO ((0x329)|(0x1d24)|0x4) #define GFX_OP_DESTBUFFER_VARS ((0x329)|(0x1d24)|(0x8516)|0x0) -#define GFX_OP_DESTBUFFER_INFO ((0x329)|(0x1d24)|(0x8e16)|1) #define GFX_OP_DRAWRECT_INFO ((0x329)|(0x1d24)|(0x8016)|(0x3)) #define GFX_OP_DRAWRECT_INFO_I965 ((0x790016)|0x2) -#define SRC_COPY_BLT_CMD((229)|(0x4322)|4) #define XY_SRC_COPY_BLT_CMD((229)|(0x5322)|6) -#define XY_MONO_SRC_COPY_IMM_BLT ((229)|(0x7122)|5) #define XY_SRC_COPY_BLT_WRITE_ALPHA(121) #define XY_SRC_COPY_BLT_WRITE_RGB (120) #define BLT_DEPTH_8 (024) @@ -305,8 +286,6 @@ #define BLT_DEPTH_16_1555(224) #define BLT_DEPTH_32 (324) #define BLT_ROP_GXCOPY (0xcc16) -#define XY_SRC_COPY_BLT_SRC_TILED (115) /* 965+ only */ -#define XY_SRC_COPY_BLT_DST_TILED (111) /* 965+ only */ #define CMD_OP_DISPLAYBUFFER_INFO ((0x029)|(0x1423)|2) #define ASYNC_FLIP(122) #define DISPLAY_PLANE_A (020) -- 1.8.1.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: clarify logging about reasons for disabling FBC
Previously FBC disabling due to per-chip default was logged as being
disabled per module parameter. Distinguish between the two.
v2: Don't even squawk in the debug log if FBC is explicitly disabled (Chris
Wilson).
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c |5 -
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ---
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0911fcd..275954c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1294,7 +1294,10 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
seq_printf(m, multiple pipes are enabled);
break;
case FBC_MODULE_PARAM:
- seq_printf(m, disabled per module param (default
off));
+ seq_printf(m, disabled per module param);
+ break;
+ case FBC_PER_CHIP_DEFAULT:
+ seq_printf(m, per chip default is disabled);
break;
default:
seq_printf(m, unknown reason);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b1f6a09..1d552df 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -453,6 +453,7 @@ enum no_fbc_reason {
FBC_NOT_TILED, /* buffer not tiled */
FBC_MULTIPLE_PIPES, /* more than one pipe active */
FBC_MODULE_PARAM,
+ FBC_PER_CHIP_DEFAULT,
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61fee7f..9b2d7dd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -437,13 +437,14 @@ void intel_update_fbc(struct drm_device *dev)
enable_fbc = i915_enable_fbc;
if (enable_fbc 0) {
- DRM_DEBUG_KMS(fbc set to per-chip default\n);
- enable_fbc = 1;
- if (INTEL_INFO(dev)-gen = 6)
- enable_fbc = 0;
- }
- if (!enable_fbc) {
- DRM_DEBUG_KMS(fbc disabled per module param\n);
+ enable_fbc = INTEL_INFO(dev)-gen 6;
+ DRM_DEBUG_KMS(fbc set to per-chip default: %s\n,
+ enable_fbc ? enabled : disabled);
+ if (!enable_fbc) {
+ dev_priv-no_fbc_reason = FBC_PER_CHIP_DEFAULT;
+ goto out_disable;
+ }
+ } else if (!enable_fbc) {
dev_priv-no_fbc_reason = FBC_MODULE_PARAM;
goto out_disable;
}
--
1.7.9.5
___
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