[Intel-gfx] [PATCH] quick_dump: Add dpio read
The sample usage is in reg_access.dpio_read(). We should add some semantics to the text files to detect DPIO registers, and do the right thing. Cc: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- tools/quick_dump/Makefile.am | 3 ++- tools/quick_dump/chipset.i | 2 ++ tools/quick_dump/reg_access.py | 6 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am index 42ab140..afd6814 100644 --- a/tools/quick_dump/Makefile.am +++ b/tools/quick_dump/Makefile.am @@ -11,7 +11,8 @@ I915ChipsetPython_la_SOURCES = chipset_wrap_python.c intel_chipset.c \ $(top_srcdir)/lib/intel_drm.c \ $(top_srcdir)/lib/intel_pci.c \ $(top_srcdir)/lib/intel_reg_map.c \ - $(top_srcdir)/lib/intel_mmio.c + $(top_srcdir)/lib/intel_mmio.c \ + $(top_srcdir)/lib/intel_dpio.c chipset_wrap_python.c chipset.py: chipset.i $(SWIG) $(AX_SWIG_PYTHON_OPT) -I/usr/include -I$(top_srcdir)/lib -o $@ $ diff --git a/tools/quick_dump/chipset.i b/tools/quick_dump/chipset.i index 36e7f4c..0a15d38 100644 --- a/tools/quick_dump/chipset.i +++ b/tools/quick_dump/chipset.i @@ -14,6 +14,7 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val); extern void intel_register_access_fini(); extern int intel_register_access_needs_wake(); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); +extern uint32_t intel_dpio_reg_read(uint32_t reg); %} extern int is_sandybridge(unsigned short pciid); @@ -26,3 +27,4 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val); extern void intel_register_access_fini(); extern int intel_register_access_needs_wake(); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); +extern uint32_t intel_dpio_reg_read(uint32_t reg); diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py index b7f3100..e2a0a95 100755 --- a/tools/quick_dump/reg_access.py +++ b/tools/quick_dump/reg_access.py @@ -27,6 +27,12 @@ def get_wake(): mt_forcewake_get() vlv_forcewake_get() +def dpio_read(reg): + reg = int(reg, 16) + val = chipset.intel_dpio_reg_read(reg) + return val + + def init(): pci_dev = chipset.intel_get_pci_device() ret = chipset.intel_register_access_init(pci_dev, 0) -- 1.8.2.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [ASK] How can I set the X to select the DRI driver i965
Hi All, I am working for video accelerating for intel card (945GM), but the driver can not run well. Please help me . 1. vainfo libva info: VA-API version 0.33.0 libva info: va_getDriverName() returns 0 libva info: Trying to open /usr/lib/dri/i915_drv_video.so libva info: va_openDriver() returns -1 vaInitialize failed with error code -1 (unknown libva error),exit of course I know the reseon of this error, because there is no i915_drv_video.so in the path. but there is i965_drv_video.so in the path. I have read the code of libva, i know it get the driver name by getting the dri driver name, which is in the following. 2. xorg.0.log [44.095] (==) Depth 24 pixmap format is 32 bpp [44.096] (II) intel(0): [DRI2] Setup complete [44.096] (II) intel(0): [DRI2] DRI driver: i915 [44.096] (II) intel(0): Allocated new frame buffer 1408x768 stride 8192, tiled So, I hope X-server can load i965 as DRI driver, and i965_dri.so is in the /usr/lib/dri. Please help me . Tks Best Regards. Mingxing 2013/04/17___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [ASK] How can I set the X to select the DRI driver i965
On Wed, Apr 17, 2013 at 02:34:30PM +0800, 熊 wrote: Hi All, I am working for video accelerating for intel card (945GM), but the driver can not run well. Please help me . 1. vainfo libva info: VA-API version 0.33.0 libva info: va_getDriverName() returns 0 libva info: Trying to open /usr/lib/dri/i915_drv_video.so libva info: va_openDriver() returns -1 vaInitialize failed with error code -1 (unknown libva error),exit of course I know the reseon of this error, because there is no i915_drv_video.so in the path. but there is i965_drv_video.so in the path. I have read the code of libva, i know it get the driver name by getting the dri driver name, which is in the following. 2. xorg.0.log [ 44.095] (==) Depth 24 pixmap format is 32 bpp [ 44.096] (II) intel(0): [DRI2] Setup complete [ 44.096] (II) intel(0): [DRI2] DRI driver: i915 [ 44.096] (II) intel(0): Allocated new frame buffer 1408x768 stride 8192, tiled So, I hope X-server can load i965 as DRI driver, and i965_dri.so is in the /usr/lib/dri. Well you can tell X to select the i965_dri.so using Option DRI i965 but it is not going to do anything as it does not support your hardware. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: implement HSW display sequences for package C8+
On Tue, Apr 16, 2013 at 01:47:44PM -0300, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com This patch implements Display Sequences for Package C8, from the Display Mode Set Sequence section from the Haswell documentation. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- Hi This patch was tested and the machines do enter C8+, so it shows our driver is not preventing C8+. There may be additional patches in the future to allow C8+ in more cases, but they shouldn't stop this patch from being merged. Please also notice that we need i915.disable_power_well=1 because we can't allow C8+ if the power well is enabled. So even if we merge this patch, the feature won't be enabled by default. This is not really a problem and it allows us to properly test everything without needing to rebase a 600-line patch every time. I wrote this patch on top of drm-intel-next-queued + the 4 patches I already sent to this list: - 2 patches that fix CPT FDI RX polarity bugs (already reviewed by Imre) - 2 patches that enable FIFO underruns and Poison messages (not reviewed yet) Ok, a bunch of high-level bikesheds and a bunch of questions: - It looks like we also kill the gt interrupts, or at least the forwarding of them. What happens if package c8 is all enabled and someone tries to submit a batchbuffer? Depending upon the answer an igt test-case would be interesting (i.e. switch all outputs off, wait a bit to reach c8, then submit batch). - You have a bit a mess between refcounting and plain checks whether package c8 is allowed. To keep sane we should use refcounting everywhere and convert all the register checks in hsw_can_allow_package_c8 into WARN_ONs/assert. And imo the two encoder/connector loops at the top should be moved into -global_modeset_resources simply to decide whether we need to grab a refcount. Maybe the modeset state needs a has_package_c8_refcount bool. Essentially the the crtc/encoder checks and all the register checks _should_ agree. If they do not, there's a bug in our state tracking, and I want such a bug to result in a loud WARN backtrace if at all possible. - The irq safe/restore needs to be rethought - atm a lot of the irq register setup crucially depends upon correct ordering of register writes with irq handler enabling/disabling: A few registers are only ever touched by the setup code when the irq handler is guaranteed to not run, which allows us to touch them in the irq handler without locking. So just grabbing the irq spinlock is not enough. But before we go down this rabbit hole and try to fix it: Is setting all these irq register values mandated by hw (i.e. we can go into pc8 without them)? Or is this just a case of bspec recommend a possible approach (and trying to make it clear that most interrupts are gone)? - Slightly related: I've just merged Egberts hpd irq storm mitigation work, so unconditionally enabling hpd interrupt is a no-go no. - Still on the topic of interrupts: A bunch of these interrupt register we never use. Imo it'd be better to set the right values at irq setup time and just put a big WARN into the pc8 code to make sure it's still correct. Somewhat on the edge is the FDI_RX register: We only use it when modesetting is enabled, so imo it would be better to write the desired value into these regs once fdi link training completed (or the pipe is shut down, if we ever bother to handle fdi link failures at runtime). Similar for fifo underrun reporting. Of course in all cases a check in the pc8 code would be good. - And finally some bikesheds on the naming ;-) The hsw_package_c8_wakeup/sleep calls look a bit funny in the rather platform-agnostic connector detect callbacks. Generally we opt for a more generic intel_foo_meh pattern in such cases. For the generic interface I also vote for a more descriptive and less technical term, since maybe on SoC platforms the same concept is called a bit differently. Imo aux_display instead of package_c8 makes it much clearer what exactly we need to have powered on to do edid reads. Lastly I think we should consider using the established naming convention of the runtime pm framework - the refcounting uses runtime_forbid/allow. So all together I vote for the generic interface to be called something like intel_aux_display_runtime_forbid/allow Of course, hsw_package_c8 is perfect for the low-level implementation and every place interfacing with hsw platform code (i.e. everything else but connector state). So imo the above could be tiny static inline wrappers for now. Cheers, Daniel Thanks, Paulo drivers/gpu/drm/i915/i915_dma.c |1 + drivers/gpu/drm/i915/i915_drv.h | 29 +++ drivers/gpu/drm/i915/i915_reg.h | 27 ++ drivers/gpu/drm/i915/intel_crt.c | 26 +- drivers/gpu/drm/i915/intel_display.c | 459 ++
[Intel-gfx] ?????? [ASK] How can I set the X to select the DRI driveri965
On Wed, Apr 17, 2013 at 02:34:30PM +0800, ?? wrote: Hi All, I am working for video accelerating for intel card (945GM), but the driver can not run well. Please help me . 1. vainfo libva info: VA-API version 0.33.0 libva info: va_getDriverName() returns 0 libva info: Trying to open /usr/lib/dri/i915_drv_video.so libva info: va_openDriver() returns -1 vaInitialize failed with error code -1 (unknown libva error),exit of course I know the reseon of this error, because there is no i915_drv_video.so in the path. but there is i965_drv_video.so in the path. I have read the code of libva, i know it get the driver name by getting the dri driver name, which is in the following. 2. xorg.0.log [44.095] (==) Depth 24 pixmap format is 32 bpp [44.096] (II) intel(0): [DRI2] Setup complete [44.096] (II) intel(0): [DRI2] DRI driver: i915 [44.096] (II) intel(0): Allocated new frame buffer 1408x768 stride 8192, tiled So, I hope X-server can load i965 as DRI driver, and i965_dri.so is in the /usr/lib/dri. Well you can tell X to select the i965_dri.so using Option DRI i965 but it is not going to do anything as it does not support your hardware. -Chris -- Chris Wilson, Intel Open Source Technology Centre Yah, you mean the DRI driver i965 does not support my device 945GM ? but according to https://01.org/linuxgraphics/downloads/2012/2012q4-intel-graphics-stack-release, it should support my device. Now, I found the config file for DRI maybe in ~/.drirc , I will try to find way from this.___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/7] drm/i915: add intel_using_power_well
Hi Paulo,
On Fri, Mar 22, 2013 at 02:14:13PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
It returns true if we've requested to turn the power well on and it's
really on. It also returns true for all the previous gens.
For now there's just one caller, but I'm going to add more.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Yeah, I've merged this but just stumbled over it again while rebasing the
-internal tree. And I'm still unhappy with the name a bit, since
power_well is a bit generic. I know it's what bspec uses, but still I'd
like to have some notion in it that this is about display stuff
The other thing which always irked me is that sprinkling power wells
checks all over the place just feels ugly. What we actually want to check
is whether the display hw is powered on, which feels much less
platform-specific.
So what about a s/intel_using_power_well/intel_display_power_enabled? It's
not perfect since the actual piece of hw we care about is still platform
specific, so I'd suggest to throw an enum on top:
enum intel_display_power_domains {
POWER_DOMAIN_EDP,
POWER_DOMAIN_EDP_PFIT,
POWER_DOMAIN_OTHER
};
bool intel_display_power_enabled(struct drm_device *dev,
enum intel_display_power_domain domain);
We could easily add new domains for e.g. the pc8 stuff with a
POWER_DOMAIN_CONNECTOR_AUX or so if we need to work around more unclaimed
register warnings.
With that piece of infrastructure I think I'll stop being grumpy about
power wells checks and unclaimed register fixup patches and just merge
them all.
Comments?
Cheers, Daniel
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 16
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 188e31f..be70f2d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1227,8 +1227,8 @@ void assert_pipe(struct drm_i915_private *dev_priv,
if (pipe == PIPE_A dev_priv-quirks QUIRK_PIPEA_FORCE)
state = true;
- if (IS_HASWELL(dev_priv-dev) cpu_transcoder != TRANSCODER_EDP
- !(I915_READ(HSW_PWR_WELL_DRIVER) HSW_PWR_WELL_ENABLE)) {
+ if (!intel_using_power_well(dev_priv-dev)
+ cpu_transcoder != TRANSCODER_EDP) {
cur_state = false;
} else {
reg = PIPECONF(cpu_transcoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index e6f84d0..40733d9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -671,6 +671,7 @@ extern void intel_update_fbc(struct drm_device *dev);
extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
extern void intel_gpu_ips_teardown(void);
+extern bool intel_using_power_well(struct drm_device *dev);
extern void intel_init_power_well(struct drm_device *dev);
extern void intel_set_power_well(struct drm_device *dev, bool enable);
extern void intel_enable_gt_powersave(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2de6da6..13404f6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4086,6 +4086,22 @@ void intel_init_clock_gating(struct drm_device *dev)
dev_priv-display.init_clock_gating(dev);
}
+/**
+ * We should only use the power well if we explicitly asked the hardware to
+ * enable it, so check if it's enabled and also check if we've requested it
to
+ * be enabled.
+ */
+bool intel_using_power_well(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (IS_HASWELL(dev))
+ return I915_READ(HSW_PWR_WELL_DRIVER) ==
+(HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
+ else
+ return true;
+}
+
void intel_set_power_well(struct drm_device *dev, bool enable)
{
struct drm_i915_private *dev_priv = dev-dev_private;
--
1.7.10.4
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 14/16] drm/i915: refuse to submit more batchbuffers from guilty context
If context has recently submitted a faulty batchbuffers guilty of
gpu hang and decides to keep submitting more crap, ban it permanently.
v2: Store guilty ban status bool in gpu_error instead of pointers
that might become danling before hang is declared.
v3: Use return value for banned status instead of stashing state
into gpu_error (Chris Wilson)
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c|5 ++--
drivers/gpu/drm/i915/i915_drv.h|8 ++-
drivers/gpu/drm/i915/i915_gem.c| 35 +---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 13 +++
4 files changed, 49 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895..fe6f8d2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -883,16 +883,17 @@ int i915_reset(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev-dev_private;
int ret;
+ bool ctx_banned;
if (!i915_try_reset)
return 0;
mutex_lock(dev-struct_mutex);
- i915_gem_reset(dev);
+ ctx_banned = i915_gem_reset(dev);
ret = -ENODEV;
- if (get_seconds() - dev_priv-gpu_error.last_reset 5)
+ if (!ctx_banned get_seconds() - dev_priv-gpu_error.last_reset 5)
DRM_ERROR(GPU hanging too fast, declaring wedged!\n);
else
ret = intel_gpu_reset(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7fd16b..ecd979e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -459,6 +459,12 @@ struct i915_ctx_hang_stats {
/* This context had batch active when hang was declared */
unsigned batch_active;
+
+ /* Time when this context was last blamed for a GPU reset */
+ unsigned long batch_active_reset_ts;
+
+ /* This context is banned to submit more work */
+ bool banned;
};
/* This must match up with the value previously used for execbuf2.rsvd1. */
@@ -1662,7 +1668,7 @@ static inline bool i915_terminally_wedged(struct
i915_gpu_error *error)
return atomic_read(error-reset_counter) == I915_WEDGED;
}
-void i915_gem_reset(struct drm_device *dev);
+bool i915_gem_reset(struct drm_device *dev);
void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
uint32_t read_domains,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0e87765..646bb7e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2143,15 +2143,15 @@ static bool i915_request_guilty(struct
drm_i915_gem_request *request,
return false;
}
-static void i915_set_reset_status(struct intel_ring_buffer *ring,
+static bool i915_set_reset_status(struct intel_ring_buffer *ring,
struct drm_i915_gem_request *request,
u32 acthd)
{
struct i915_ctx_hang_stats *hs = NULL;
- bool inside, guilty;
+ bool inside, guilty, banned;
/* Innocent until proven guilty */
- guilty = false;
+ guilty = banned = false;
if (!ring-hangcheck.was_waiting
i915_request_guilty(request, acthd, inside)) {
@@ -2175,11 +2175,21 @@ static void i915_set_reset_status(struct
intel_ring_buffer *ring,
hs = request-file_priv-hang_stats;
if (hs) {
- if (guilty)
+ if (guilty) {
+ if (!hs-banned
+ get_seconds() - hs-batch_active_reset_ts 5) {
+ hs-banned = banned = true;
+ DRM_ERROR(context hanging too fast,
+ declaring banned\n);
+ }
hs-batch_active++;
- else
+ hs-batch_active_reset_ts = get_seconds();
+ } else {
hs-batch_pending++;
+ }
}
+
+ return banned;
}
static void i915_gem_free_request(struct drm_i915_gem_request *request)
@@ -2193,11 +2203,12 @@ static void i915_gem_free_request(struct
drm_i915_gem_request *request)
kfree(request);
}
-static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
+static bool i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
struct intel_ring_buffer *ring)
{
u32 completed_seqno;
u32 acthd;
+ bool ctx_banned = false;
acthd = intel_ring_get_active_head(ring);
completed_seqno = ring-get_seqno(ring, false);
@@ -2210,7 +2221,8 @@ static void i915_gem_reset_ring_lists(struct
drm_i915_private
[Intel-gfx] [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c |5 +
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 18 ++
5 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895..6902219 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -525,6 +525,8 @@ static int i915_drm_freeze(struct drm_device *dev)
*/
list_for_each_entry(crtc, dev-mode_config.crtc_list, head)
dev_priv-display.crtc_disable(crtc);
+
+ intel_modeset_suspend_hw(dev);
}
i915_save_state(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5a495a..e549e6c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) {
return; }
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
+extern void intel_modeset_suspend_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..dec9019 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9004,6 +9004,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
mutex_unlock(dev-struct_mutex);
}
+void intel_modeset_suspend_hw(struct drm_device *dev)
+{
+ intel_suspend_hw(dev);
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a124e05..3f31b2e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe,
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
extern void intel_init_clock_gating(struct drm_device *dev);
+extern void intel_suspend_hw(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f747cb0..8a163d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3750,6 +3750,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
PCH_LP_PARTITION_LEVEL_DISABLE);
}
+static void lpt_suspend_hw(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (dev_priv-pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
+ uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
+
+ val = ~PCH_LP_PARTITION_LEVEL_DISABLE;
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+ }
+}
+
static void haswell_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4100,6 +4112,12 @@ void intel_init_clock_gating(struct drm_device *dev)
dev_priv-display.init_clock_gating(dev);
}
+void intel_suspend_hw(struct drm_device *dev)
+{
+ if (HAS_PCH_LPT(dev))
+ lpt_suspend_hw(dev);
+}
+
/**
* We should only use the power well if we explicitly asked the hardware to
* enable it, so check if it's enabled and also check if we've requested it to
--
1.7.10.4
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: add intel_using_power_well
On Wed, Apr 17, 2013 at 11:04:23AM +0200, Daniel Vetter wrote:
Hi Paulo,
On Fri, Mar 22, 2013 at 02:14:13PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
It returns true if we've requested to turn the power well on and it's
really on. It also returns true for all the previous gens.
For now there's just one caller, but I'm going to add more.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Yeah, I've merged this but just stumbled over it again while rebasing the
-internal tree. And I'm still unhappy with the name a bit, since
power_well is a bit generic. I know it's what bspec uses, but still I'd
like to have some notion in it that this is about display stuff
The other thing which always irked me is that sprinkling power wells
checks all over the place just feels ugly. What we actually want to check
is whether the display hw is powered on, which feels much less
platform-specific.
So what about a s/intel_using_power_well/intel_display_power_enabled? It's
not perfect since the actual piece of hw we care about is still platform
specific, so I'd suggest to throw an enum on top:
enum intel_display_power_domains {
POWER_DOMAIN_EDP,
POWER_DOMAIN_EDP_PFIT,
POWER_DOMAIN_OTHER
};
bool intel_display_power_enabled(struct drm_device *dev,
enum intel_display_power_domain domain);
We could easily add new domains for e.g. the pc8 stuff with a
POWER_DOMAIN_CONNECTOR_AUX or so if we need to work around more unclaimed
register warnings.
With that piece of infrastructure I think I'll stop being grumpy about
power wells checks and unclaimed register fixup patches and just merge
them all.
Also, that function should probably use HAS_POWER_WELL instead of the
manual IS_HASWELL check.
-Daniel
--
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] [PATCH] drm/i915: move cpu_transcoder to the pipe configuration
For a bunch of reason we need to more accurately track this:
- hw pipe state readout for Haswell needs the cpu transcoder.
- We need to know the right cpu transcoder in a bunch of places in
-disable and other modeset callbacks.
In the future we need to add hw state readoutcheck support, too. But
to avoid ugly merge conflicts do the rote sed job now without any
functional changes.
Cc: Paulo Zanoni przan...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_ddi.c |8
drivers/gpu/drm/i915/intel_display.c | 32
drivers/gpu/drm/i915/intel_drv.h |6 +-
drivers/gpu/drm/i915/intel_hdmi.c|6 +++---
4 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 22524cb..26a0a57 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -924,7 +924,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
int type = intel_encoder-type;
uint32_t temp;
@@ -958,7 +958,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
struct drm_encoder *encoder = intel_encoder-base;
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
enum pipe pipe = intel_crtc-pipe;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder-type;
uint32_t temp;
@@ -1223,7 +1223,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1233,7 +1233,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv = intel_crtc-base.dev-dev_private;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..668b71e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -892,7 +892,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct
drm_i915_private *dev_priv,
struct drm_crtc *crtc = dev_priv-pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- return intel_crtc-cpu_transcoder;
+ return intel_crtc-config.cpu_transcoder;
}
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
@@ -3208,7 +3208,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
assert_transcoder_disabled(dev_priv, TRANSCODER_A);
@@ -3583,7 +3583,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc-pipe;
int plane = intel_crtc-plane;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (!intel_crtc-active)
return;
@@ -3643,7 +3643,7 @@ static void haswell_crtc_off(struct drm_crtc *crtc)
/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
* start using it. */
- intel_crtc-cpu_transcoder = (enum transcoder) intel_crtc-pipe;
+ intel_crtc-config.cpu_transcoder = (enum transcoder) intel_crtc-pipe;
intel_ddi_put_crtc_pll(crtc);
}
@@ -4499,7 +4499,7 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc,
struct drm_device *dev = intel_crtc-base.dev;
struct drm_i915_private
Re: [Intel-gfx] [PATCH] drm/i915: move cpu_transcoder to the pipe configuration
On Wed, Apr 17, 2013 at 03:31:44PM +0200, Daniel Vetter wrote: For a bunch of reason we need to more accurately track this: - hw pipe state readout for Haswell needs the cpu transcoder. - We need to know the right cpu transcoder in a bunch of places in -disable and other modeset callbacks. In the future we need to add hw state readoutcheck support, too. But to avoid ugly merge conflicts do the rote sed job now without any functional changes. Cc: Paulo Zanoni przan...@gmail.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch A rogue piece of whitespace crept into the end of struct pipe_config. Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/5] drm/i915: OCD fixes
After spotting one open coded pipe_name() some form of OCD kicked in and I had to fix it all. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915: Use pipe_name() and port_name() where appropriate
From: Ville Syrjälä ville.syrj...@linux.intel.com
Get rid of the few remaining open coded copies of
pipe_name() and port_name().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..d984bba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4723,7 +4723,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_SEL_PIPE_B;
}
- DRM_DEBUG_KMS(Mode for pipe %c:\n, pipe == 0 ? 'A' : 'B');
+ DRM_DEBUG_KMS(Mode for pipe %c:\n, pipe_name(pipe));
drm_mode_debug_printmodeline(mode);
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
@@ -6109,7 +6109,7 @@ static void ironlake_write_eld(struct drm_connector
*connector,
eldv |= IBX_ELD_VALIDB 4;
eldv |= IBX_ELD_VALIDB 8;
} else {
- DRM_DEBUG_DRIVER(ELD on port %c\n, 'A' + i);
+ DRM_DEBUG_DRIVER(ELD on port %c\n, port_name(i));
eldv = IBX_ELD_VALIDB ((i - 1) * 4);
}
--
1.8.1.5
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[Intel-gfx] [PATCH 2/5] drm/i915: Use port_name() in PCH port audio power change message
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0aa2ef0..3af983f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -763,10 +763,12 @@ static void ibx_irq_handler(struct drm_device *dev, u32
pch_iir)
ibx_hpd_irq_setup(dev);
queue_work(dev_priv-wq, dev_priv-hotplug_work);
}
- if (pch_iir SDE_AUDIO_POWER_MASK)
+ if (pch_iir SDE_AUDIO_POWER_MASK) {
+ int port = ffs((pch_iir SDE_AUDIO_POWER_MASK)
+ SDE_AUDIO_POWER_SHIFT);
DRM_DEBUG_DRIVER(PCH audio power change on port %d\n,
-(pch_iir SDE_AUDIO_POWER_MASK)
-SDE_AUDIO_POWER_SHIFT);
+port_name(port));
+ }
if (pch_iir SDE_AUX_MASK)
dp_aux_irq_handler(dev);
@@ -812,10 +814,12 @@ static void cpt_irq_handler(struct drm_device *dev, u32
pch_iir)
ibx_hpd_irq_setup(dev);
queue_work(dev_priv-wq, dev_priv-hotplug_work);
}
- if (pch_iir SDE_AUDIO_POWER_MASK_CPT)
- DRM_DEBUG_DRIVER(PCH audio power change on port %d\n,
-(pch_iir SDE_AUDIO_POWER_MASK_CPT)
-SDE_AUDIO_POWER_SHIFT_CPT);
+ if (pch_iir SDE_AUDIO_POWER_MASK_CPT) {
+ int port = ffs((pch_iir SDE_AUDIO_POWER_MASK_CPT)
+ SDE_AUDIO_POWER_SHIFT_CPT);
+ DRM_DEBUG_DRIVER(PCH audio power change on port %c\n,
+port_name(port));
+ }
if (pch_iir SDE_AUX_MASK_CPT)
dp_aux_irq_handler(dev);
--
1.8.1.5
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[Intel-gfx] [PATCH 4/5] drm/i915: Use alphabetical names for transcoders too
From: Ville Syrjälä ville.syrj...@linux.intel.com
Print the alphabetical name for transcoders. The code already used the
pipe_name() macro for transcoders, so I did the same. But we do have the
(unused) transcoder_name() macro which could be used instead.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 982fddd..2800044 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1097,14 +1097,14 @@ static void assert_pch_pll(struct drm_i915_private
*dev_priv,
pch_dpll = I915_READ(PCH_DPLL_SEL);
cur_state = pll-pll_reg == _PCH_DPLL_B;
if (!WARN(((pch_dpll (4 * crtc-pipe)) 1) != cur_state,
- PLL[%d] not attached to this transcoder %d: %08x\n,
- cur_state, crtc-pipe, pch_dpll)) {
+ PLL[%d] not attached to this transcoder %c: %08x\n,
+ cur_state, pipe_name(crtc-pipe), pch_dpll)) {
cur_state = !!(val (4*crtc-pipe + 3));
WARN(cur_state != state,
-PLL[%d] not %s on this transcoder %d: %08x\n,
+PLL[%d] not %s on this transcoder %c: %08x\n,
pll-pll_reg == _PCH_DPLL_B,
state_string(state),
-crtc-pipe,
+pipe_name(crtc-pipe),
val);
}
}
@@ -1733,7 +1733,7 @@ static void ironlake_enable_pch_transcoder(struct
drm_i915_private *dev_priv,
I915_WRITE(reg, val | TRANS_ENABLE);
if (wait_for(I915_READ(reg) TRANS_STATE_ENABLE, 100))
- DRM_ERROR(failed to enable transcoder %d\n, pipe);
+ DRM_ERROR(failed to enable transcoder %c\n, pipe_name(pipe));
}
static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -1786,7 +1786,7 @@ static void ironlake_disable_pch_transcoder(struct
drm_i915_private *dev_priv,
I915_WRITE(reg, val);
/* wait for PCH transcoder off, transcoder state */
if (wait_for((I915_READ(reg) TRANS_STATE_ENABLE) == 0, 50))
- DRM_ERROR(failed to disable transcoder %d\n, pipe);
+ DRM_ERROR(failed to disable transcoder %c\n, pipe_name(pipe));
if (!HAS_PCH_IBX(dev)) {
/* Workaround: Clear the timing override chicken bit again. */
--
1.8.1.5
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[Intel-gfx] [PATCH 3/5] drm/i915: Print plane, pipe, port names as alphabetical insted of decimal
From: Ville Syrjälä ville.syrj...@linux.intel.com
Alway use the alphabetical names in debug/error messages for planes,
pipes and ports, instead of using decimal numbers occasionally.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 10 -
drivers/gpu/drm/i915/intel_display.c | 42 ++--
drivers/gpu/drm/i915/intel_pm.c | 26 +++---
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 22524cb..c8e8c15 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -748,8 +748,8 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
}
if (num_encoders != 1)
- WARN(1, %d encoders on crtc for pipe %d\n, num_encoders,
-intel_crtc-pipe);
+ WARN(1, %d encoders on crtc for pipe %c\n, num_encoders,
+pipe_name(intel_crtc-pipe));
BUG_ON(ret == NULL);
return ret;
@@ -1047,8 +1047,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc)
}
} else {
- WARN(1, Invalid encoder type %d for pipe %d\n,
-intel_encoder-type, pipe);
+ WARN(1, Invalid encoder type %d for pipe %c\n,
+intel_encoder-type, pipe_name(pipe));
}
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
@@ -1148,7 +1148,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
}
}
- DRM_DEBUG_KMS(No pipe for ddi port %i found\n, port);
+ DRM_DEBUG_KMS(No pipe for ddi port %c found\n, port_name(port));
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d984bba..982fddd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2101,7 +2101,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
case 1:
break;
default:
- DRM_ERROR(Can't update plane %d in SAREA\n, plane);
+ DRM_ERROR(Can't update plane %c in SAREA\n,
plane_name(plane));
return -EINVAL;
}
@@ -2198,7 +2198,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
case 2:
break;
default:
- DRM_ERROR(Can't update plane %d in SAREA\n, plane);
+ DRM_ERROR(Can't update plane %c in SAREA\n,
plane_name(plane));
return -EINVAL;
}
@@ -2389,9 +2389,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
}
if (intel_crtc-plane INTEL_INFO(dev)-num_pipes) {
- DRM_ERROR(no plane for crtc: plane %d, num_pipes %d\n,
- intel_crtc-plane,
- INTEL_INFO(dev)-num_pipes);
+ DRM_ERROR(no plane for crtc: plane %c, num_pipes %d\n,
+ plane_name(intel_crtc-plane),
+ INTEL_INFO(dev)-num_pipes);
return -EINVAL;
}
@@ -3299,7 +3299,7 @@ static struct intel_pch_pll *intel_get_pch_pll(struct
intel_crtc *intel_crtc, u3
found:
intel_crtc-pch_pll = pll;
pll-refcount++;
- DRM_DEBUG_DRIVER(using pll %d for pipe %d\n, i, intel_crtc-pipe);
+ DRM_DEBUG_DRIVER(using pll %d for pipe %c\n, i,
pipe_name(intel_crtc-pipe));
prepare: /* separate function? */
DRM_DEBUG_DRIVER(switching PLL %x off\n, pll-pll_reg);
@@ -3324,7 +3324,7 @@ void intel_cpt_verify_modeset(struct drm_device *dev, int
pipe)
udelay(500);
if (wait_for(I915_READ(dslreg) != temp, 5)) {
if (wait_for(I915_READ(dslreg) != temp, 5))
- DRM_ERROR(mode set failed: pipe %d stuck\n, pipe);
+ DRM_ERROR(mode set failed: pipe %c stuck\n,
pipe_name(pipe));
}
}
@@ -5344,11 +5344,11 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc)
struct intel_crtc *pipe_B_crtc =
to_intel_crtc(dev_priv-pipe_to_crtc_mapping[PIPE_B]);
- DRM_DEBUG_KMS(checking fdi config on pipe %i, lanes %i\n,
- intel_crtc-pipe, intel_crtc-fdi_lanes);
+ DRM_DEBUG_KMS(checking fdi config on pipe %c, lanes %i\n,
+ pipe_name(intel_crtc-pipe), intel_crtc-fdi_lanes);
if (intel_crtc-fdi_lanes 4) {
- DRM_DEBUG_KMS(invalid fdi lane config on pipe %i: %i lanes\n,
- intel_crtc-pipe, intel_crtc-fdi_lanes);
+ DRM_DEBUG_KMS(invalid fdi lane config on pipe %c: %i lanes\n,
+ pipe_name(intel_crtc-pipe),
intel_crtc-fdi_lanes);
/* Clamp lanes to avoid programming the hw with bogus values. */
intel_crtc-fdi_lanes =
[Intel-gfx] [PATCH 5/5] drm/i915: Use alphabetical names for sprites
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add sprite_name() macro which should be used with the kind of sprites
that are fixed to pipes (gen4.5+).
Also use dev_priv-num_plane to calculate the sprite index insted
assuming two sprites per pipe. This should make it print the right
name.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 8
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5dcf7f..15d0a3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -76,6 +76,8 @@ enum plane {
};
#define plane_name(p) ((p) + 'A')
+#define sprite_name(p, s) ((p) * dev_priv-num_plane + (s) + 'A')
+
enum port {
PORT_A = 0,
PORT_B,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2800044..21f368c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1302,8 +1302,8 @@ static void assert_sprites_disabled(struct
drm_i915_private *dev_priv,
reg = SPCNTR(pipe, i);
val = I915_READ(reg);
WARN((val SP_ENABLE),
-sprite %d assertion failure, should be off on pipe %c but
is still active\n,
-pipe * 2 + i, pipe_name(pipe));
+sprite %c assertion failure, should be off on pipe %c but
is still active\n,
+sprite_name(pipe, i), pipe_name(pipe));
}
}
@@ -9049,8 +9049,8 @@ void intel_modeset_init(struct drm_device *dev)
for (j = 0; j dev_priv-num_plane; j++) {
ret = intel_plane_init(dev, i, j);
if (ret)
- DRM_DEBUG_KMS(pipe %c plane %d init failed:
%d\n,
- pipe_name(i), j, ret);
+ DRM_DEBUG_KMS(pipe %c sprite %c init failed:
%d\n,
+ pipe_name(i), sprite_name(i, j),
ret);
}
}
--
1.8.1.5
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Re: [Intel-gfx] GPU freeze on my Kubuntu 12.10 system
On Wed, Apr 17, 2013 at 10:25:42AM -0400, icanprog...@295.ca wrote: I'm new to your mailing list, so I'm not sure exactly how to report this. My KDE system is quite flaky.The Xorg.0.log and dmesg both are reporting that my GPU is hung out to dry.I have other issues in KDE, but I figure the first order of business is to get the GPU working correctly. I have attached the output from both dmesg and /sys/kernel/debug/dri/0/i915_error_state You have the TLB invalidate bug that crept into v3.5. Fixes are in progress for Ubuntu, but the easiest way to avoid the bug is to upgrade to v3.8. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] GPU freeze on Kubuntu 12.10 system
On Wed, Apr 17, 2013 at 10:25:42AM -0400, icanprog...@295.ca wrote: I'm new to your mailing list, so I'm not sure exactly how to report this. My KDE system is quite flaky.The Xorg.0.log and dmesg both are reporting that my GPU is hung out to dry.I have other issues in KDE, but I figure the first order of business is to get the GPU working correctly. I have attached the output from both dmesg and /sys/kernel/debug/dri/0/i915_error_state You have the TLB invalidate bug that crept into v3.5. Fixes are in progress for Ubuntu, but the easiest way to avoid the bug is to upgrade to v3.8. -Chris -- Chris Wilson, Intel Open Source Technology Centre === Apologies for messing up the threading by my digest mode. Thanks for the speedy response.How do I go about upgrading to v3.8? It wasn't clear from the website what to do. Am I likely to encounter that ./configure problem I had with the intel-gpu-tools? Thanks again in advance for your help. bob ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: move cpu_transcoder to the pipe configuration
On Wed, Apr 17, 2013 at 03:43:54PM +0100, Chris Wilson wrote: On Wed, Apr 17, 2013 at 03:31:44PM +0200, Daniel Vetter wrote: For a bunch of reason we need to more accurately track this: - hw pipe state readout for Haswell needs the cpu transcoder. - We need to know the right cpu transcoder in a bunch of places in -disable and other modeset callbacks. In the future we need to add hw state readoutcheck support, too. But to avoid ugly merge conflicts do the rote sed job now without any functional changes. Cc: Paulo Zanoni przan...@gmail.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch A rogue piece of whitespace crept into the end of struct pipe_config. Killed. Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk Picked up for -fixes, thanks for the review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/5] drm/i915: OCD fixes
On Wed, Apr 17, 2013 at 05:48:46PM +0300, ville.syrj...@linux.intel.com wrote: After spotting one open coded pipe_name() some form of OCD kicked in and I had to fix it all. OCD approved, entire pile shovelled on top of dinq. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] GPU freeze on Kubuntu 12.10 system
On Wed, Apr 17, 2013 at 11:23:41AM -0400, bob295 wrote: Thanks for the speedy response.How do I go about upgrading to v3.8? It wasn't clear from the website what to do. Am I likely to encounter that ./configure problem I had with the intel-gpu-tools? The answer is to use your distribution packages and upgrade tools. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Enable FBC at Haswell.
On Tue, Apr 16, 2013 at 01:33:44PM -0300, Rodrigo Vivi wrote: This patch introduce Frame Buffer Compression (FBC) support for HSW. It adds a new function haswell_enable_fbc to avoid getting ironlake_enable_fbc messed with many IS_HASWELL checks. v2: Fixes from Ville. * Fix Plane. FBC is tied to primary plane A in HSW * Fix DPFC initial write to avoid let trash on the register. v3: Checking for bad plane on intel_update_fbc() as Chris suggested. v4: Ville pointed out that according to BSpec FBC_CTL bits 0:3 must be 0. Cc: Chris Wilson ch...@chris-wilson.co.uk Cc: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com I'm failing in sanity checking FBC on HSW due to lack of the appropriate hardware. I still believe we need a cooperative userspace to make best use of FBC, avoid known limitations and apply required workarounds. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] quick_dump: Add dpio read
On Tue, 16 Apr 2013 23:09:25 -0700 Ben Widawsky b...@bwidawsk.net wrote: The sample usage is in reg_access.dpio_read(). We should add some semantics to the text files to detect DPIO registers, and do the right thing. Cc: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- tools/quick_dump/Makefile.am | 3 ++- tools/quick_dump/chipset.i | 2 ++ tools/quick_dump/reg_access.py | 6 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am index 42ab140..afd6814 100644 --- a/tools/quick_dump/Makefile.am +++ b/tools/quick_dump/Makefile.am @@ -11,7 +11,8 @@ I915ChipsetPython_la_SOURCES = chipset_wrap_python.c intel_chipset.c \ $(top_srcdir)/lib/intel_drm.c \ $(top_srcdir)/lib/intel_pci.c \ $(top_srcdir)/lib/intel_reg_map.c \ -$(top_srcdir)/lib/intel_mmio.c +$(top_srcdir)/lib/intel_mmio.c \ +$(top_srcdir)/lib/intel_dpio.c chipset_wrap_python.c chipset.py: chipset.i $(SWIG) $(AX_SWIG_PYTHON_OPT) -I/usr/include -I$(top_srcdir)/lib -o $@ $ diff --git a/tools/quick_dump/chipset.i b/tools/quick_dump/chipset.i index 36e7f4c..0a15d38 100644 --- a/tools/quick_dump/chipset.i +++ b/tools/quick_dump/chipset.i @@ -14,6 +14,7 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val); extern void intel_register_access_fini(); extern int intel_register_access_needs_wake(); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); +extern uint32_t intel_dpio_reg_read(uint32_t reg); %} extern int is_sandybridge(unsigned short pciid); @@ -26,3 +27,4 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val); extern void intel_register_access_fini(); extern int intel_register_access_needs_wake(); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); +extern uint32_t intel_dpio_reg_read(uint32_t reg); diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py index b7f3100..e2a0a95 100755 --- a/tools/quick_dump/reg_access.py +++ b/tools/quick_dump/reg_access.py @@ -27,6 +27,12 @@ def get_wake(): mt_forcewake_get() vlv_forcewake_get() +def dpio_read(reg): + reg = int(reg, 16) + val = chipset.intel_dpio_reg_read(reg) + return val + + def init(): pci_dev = chipset.intel_get_pci_device() ret = chipset.intel_register_access_init(pci_dev, 0) Looks good, thanks. Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] tests/prime_self_import: export/import a second gem buffer
Signed-off-by: Imre Deak imre.d...@intel.com
---
tests/prime_self_import.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 111ed4d..a17e942 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_self_import.c
@@ -48,11 +48,13 @@
#define BO_SIZE (16*1024)
+static char counter1;
+static char counter2;
+
static void
-check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2)
+check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2, char *counter)
{
char *ptr1, *ptr2;
- static char counter = 0;
int i;
ptr1 = gem_mmap(fd1, handle1, BO_SIZE, PROT_READ | PROT_WRITE);
@@ -62,13 +64,13 @@ check_bo(int fd1, uint32_t handle1, int fd2, uint32_t
handle2)
/* check whether it's still our old object first. */
for (i = 0; i BO_SIZE; i++) {
- assert(ptr1[i] == counter);
- assert(ptr2[i] == counter);
+ assert(ptr1[i] == *counter);
+ assert(ptr2[i] == *counter);
}
- counter++;
+ (*counter)++;
- memset(ptr1, counter, BO_SIZE);
+ memset(ptr1, *counter, BO_SIZE);
assert(memcmp(ptr1, ptr2, BO_SIZE) == 0);
munmap(ptr1, BO_SIZE);
@@ -79,17 +81,19 @@ int main(int argc, char **argv)
{
int fd1, fd2;
uint32_t handle, handle_import1, handle_import2, handle_selfimport;
+ uint32_t handle2;
int dma_buf_fd;
fd1 = drm_open_any();
fd2 = drm_open_any();
handle = gem_create(fd1, BO_SIZE);
+ handle2 = gem_create(fd1, BO_SIZE);
dma_buf_fd = prime_handle_to_fd(fd1, handle);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
/* reimport should give us the same handle so that userspace can check
* whether it has that bo already somewhere. */
@@ -102,10 +106,17 @@ int main(int argc, char **argv)
/* close dma_buf, check whether nothing disappears. */
close(dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
gem_close(fd1, handle);
- check_bo(fd2, handle_import1, fd2, handle_import1);
+ check_bo(fd2, handle_import1, fd2, handle_import1, counter1);
+
+ dma_buf_fd = prime_handle_to_fd(fd1, handle2);
+ handle = prime_fd_to_handle(fd2, dma_buf_fd);
+ check_bo(fd1, handle2, fd2, handle, counter2);
+ gem_close(fd2, handle);
+ gem_close(fd1, handle2);
+ close(dma_buf_fd);
/* re-import into old exporter */
dma_buf_fd = prime_handle_to_fd(fd2, handle_import1);
@@ -113,11 +124,11 @@ int main(int argc, char **argv)
gem_close(fd2, handle_import1);
handle = prime_fd_to_handle(fd1, dma_buf_fd);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
/* Completely rip out exporting fd. */
close(fd1);
- check_bo(fd2, handle_import1, fd2, handle_import1);
+ check_bo(fd2, handle_import1, fd2, handle_import1, counter1);
return 0;
}
--
1.7.10.4
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Re: [Intel-gfx] [PATCH] drm/i915: move cpu_transcoder to the pipe configuration
Hi 2013/4/17 Daniel Vetter dan...@ffwll.ch: On Wed, Apr 17, 2013 at 03:43:54PM +0100, Chris Wilson wrote: On Wed, Apr 17, 2013 at 03:31:44PM +0200, Daniel Vetter wrote: For a bunch of reason we need to more accurately track this: - hw pipe state readout for Haswell needs the cpu transcoder. - We need to know the right cpu transcoder in a bunch of places in -disable and other modeset callbacks. In the future we need to add hw state readoutcheck support, too. But to avoid ugly merge conflicts do the rote sed job now without any functional changes. Cc: Paulo Zanoni przan...@gmail.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch A rogue piece of whitespace crept into the end of struct pipe_config. Killed. Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk The patch looks correct and I was going to give a Reviewed-by tag too, but then I decided to test it. There's new stuff in dmesg now: [ 16.172092] [ cut here ] [ 16.172139] WARNING: at drivers/gpu/drm/i915/intel_display.c:3944 intel_modeset_check_state+0xac/0x5d0 [i915]() [ 16.172144] Hardware name: Shark Bay Client platform [ 16.172147] wrong connector dpms state [ 16.172484] [ cut here ] [ 16.172506] WARNING: at drivers/gpu/drm/i915/intel_display.c:3946 intel_modeset_check_state+0xcf/0x5d0 [i915]() [ 16.172509] Hardware name: Shark Bay Client platform [ 16.172511] active connector not linked to encoder [ 16.172818] [ cut here ] [ 16.172839] WARNING: at drivers/gpu/drm/i915/intel_display.c:3948 intel_modeset_check_state+0xf0/0x5d0 [i915]() [ 16.172842] Hardware name: Shark Bay Client platform [ 16.172844] encoder-connectors_active not set [ 16.173150] [ cut here ] [ 16.173170] WARNING: at drivers/gpu/drm/i915/intel_display.c:3952 intel_modeset_check_state+0x13b/0x5d0 [i915]() [ 16.173173] Hardware name: Shark Bay Client platform [ 16.173481] [ cut here ] [ 16.173501] WARNING: at drivers/gpu/drm/i915/intel_display.c:8363 intel_modeset_check_state+0x34b/0x5d0 [i915]() [ 16.173505] Hardware name: Shark Bay Client platform [ 16.173507] encoder's hw state doesn't match sw tracking (expected 0, found 1) [ 16.182789] [ cut here ] [ 16.182809] WARNING: at drivers/gpu/drm/i915/intel_display.c:6284 haswell_crtc_mode_set+0x159/0x475 [i915]() [ 16.182810] Hardware name: Shark Bay Client platform [ 16.183055] [ cut here ] [ 16.183073] WARNING: at drivers/gpu/drm/i915/intel_display.c:6286 haswell_crtc_mode_set+0x18f/0x475 [i915]() [ 16.183074] Hardware name: Shark Bay Client platform Picked up for -fixes, thanks for the review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] quick_dump: Add dpio read
On Wed, Apr 17, 2013 at 08:49:51AM -0700, Jesse Barnes wrote: On Tue, 16 Apr 2013 23:09:25 -0700 Ben Widawsky b...@bwidawsk.net wrote: The sample usage is in reg_access.dpio_read(). We should add some semantics to the text files to detect DPIO registers, and do the right thing. Cc: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- tools/quick_dump/Makefile.am | 3 ++- tools/quick_dump/chipset.i | 2 ++ tools/quick_dump/reg_access.py | 6 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am index 42ab140..afd6814 100644 --- a/tools/quick_dump/Makefile.am +++ b/tools/quick_dump/Makefile.am @@ -11,7 +11,8 @@ I915ChipsetPython_la_SOURCES = chipset_wrap_python.c intel_chipset.c \ $(top_srcdir)/lib/intel_drm.c \ $(top_srcdir)/lib/intel_pci.c \ $(top_srcdir)/lib/intel_reg_map.c \ - $(top_srcdir)/lib/intel_mmio.c + $(top_srcdir)/lib/intel_mmio.c \ + $(top_srcdir)/lib/intel_dpio.c chipset_wrap_python.c chipset.py: chipset.i $(SWIG) $(AX_SWIG_PYTHON_OPT) -I/usr/include -I$(top_srcdir)/lib -o $@ $ diff --git a/tools/quick_dump/chipset.i b/tools/quick_dump/chipset.i index 36e7f4c..0a15d38 100644 --- a/tools/quick_dump/chipset.i +++ b/tools/quick_dump/chipset.i @@ -14,6 +14,7 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val); extern void intel_register_access_fini(); extern int intel_register_access_needs_wake(); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); +extern uint32_t intel_dpio_reg_read(uint32_t reg); %} extern int is_sandybridge(unsigned short pciid); @@ -26,3 +27,4 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val); extern void intel_register_access_fini(); extern int intel_register_access_needs_wake(); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); +extern uint32_t intel_dpio_reg_read(uint32_t reg); diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py index b7f3100..e2a0a95 100755 --- a/tools/quick_dump/reg_access.py +++ b/tools/quick_dump/reg_access.py @@ -27,6 +27,12 @@ def get_wake(): mt_forcewake_get() vlv_forcewake_get() +def dpio_read(reg): + reg = int(reg, 16) + val = chipset.intel_dpio_reg_read(reg) + return val + + def init(): pci_dev = chipset.intel_get_pci_device() ret = chipset.intel_register_access_init(pci_dev, 0) Looks good, thanks. Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org Applied, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] tests/prime_self_import: export/import a second gem buffer
On Wed, Apr 17, 2013 at 07:10:00PM +0300, Imre Deak wrote:
Signed-off-by: Imre Deak imre.d...@intel.com
I'm a bit confused what this does ... can you please elaborate?
-Daniel
---
tests/prime_self_import.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 111ed4d..a17e942 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_self_import.c
@@ -48,11 +48,13 @@
#define BO_SIZE (16*1024)
+static char counter1;
+static char counter2;
+
static void
-check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2)
+check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2, char *counter)
{
char *ptr1, *ptr2;
- static char counter = 0;
int i;
ptr1 = gem_mmap(fd1, handle1, BO_SIZE, PROT_READ | PROT_WRITE);
@@ -62,13 +64,13 @@ check_bo(int fd1, uint32_t handle1, int fd2, uint32_t
handle2)
/* check whether it's still our old object first. */
for (i = 0; i BO_SIZE; i++) {
- assert(ptr1[i] == counter);
- assert(ptr2[i] == counter);
+ assert(ptr1[i] == *counter);
+ assert(ptr2[i] == *counter);
}
- counter++;
+ (*counter)++;
- memset(ptr1, counter, BO_SIZE);
+ memset(ptr1, *counter, BO_SIZE);
assert(memcmp(ptr1, ptr2, BO_SIZE) == 0);
munmap(ptr1, BO_SIZE);
@@ -79,17 +81,19 @@ int main(int argc, char **argv)
{
int fd1, fd2;
uint32_t handle, handle_import1, handle_import2, handle_selfimport;
+ uint32_t handle2;
int dma_buf_fd;
fd1 = drm_open_any();
fd2 = drm_open_any();
handle = gem_create(fd1, BO_SIZE);
+ handle2 = gem_create(fd1, BO_SIZE);
dma_buf_fd = prime_handle_to_fd(fd1, handle);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
/* reimport should give us the same handle so that userspace can check
* whether it has that bo already somewhere. */
@@ -102,10 +106,17 @@ int main(int argc, char **argv)
/* close dma_buf, check whether nothing disappears. */
close(dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
gem_close(fd1, handle);
- check_bo(fd2, handle_import1, fd2, handle_import1);
+ check_bo(fd2, handle_import1, fd2, handle_import1, counter1);
+
+ dma_buf_fd = prime_handle_to_fd(fd1, handle2);
+ handle = prime_fd_to_handle(fd2, dma_buf_fd);
+ check_bo(fd1, handle2, fd2, handle, counter2);
+ gem_close(fd2, handle);
+ gem_close(fd1, handle2);
+ close(dma_buf_fd);
/* re-import into old exporter */
dma_buf_fd = prime_handle_to_fd(fd2, handle_import1);
@@ -113,11 +124,11 @@ int main(int argc, char **argv)
gem_close(fd2, handle_import1);
handle = prime_fd_to_handle(fd1, dma_buf_fd);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
/* Completely rip out exporting fd. */
close(fd1);
- check_bo(fd2, handle_import1, fd2, handle_import1);
+ check_bo(fd2, handle_import1, fd2, handle_import1, counter1);
return 0;
}
--
1.7.10.4
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] [RFC][PATCH] drm: Insane but more fine grained locking for planes
From: Ville Syrjälä ville.syrj...@linux.intel.com
Instead of locking all modeset locks during plane updates, use just
a single CRTC mutex. To make that work, track the CRTC that owns
the plane currently. During enable/update that means the new
CRTC, and during disable it means the old CRTC.
Since the plane state is no longer protected by a single lock, we
need to sprinkle some additional memory barriers when relinquishing
ownership. Otherwise the next CRTC might observe some stale state
even though the crtc_mutex already got updated.
drm_framebuffer_remove() doesn't need extra barriers since it
already holds all CRTC locks, and thus no-one can be poking around
at the same time. On the read side cmpxchg() already should have
the necessary memory barriers.
This design implies that before a plane can be moved to another CRTC,
it must be disabled first, even if the hardware would offer some kind
of mechanism to move an active plane over directly. I believe everyone
has agreed that this an acceptable compromise.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/drm_crtc.c | 43 +++
include/drm/drm_crtc.h | 3 +++
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 957fb70..6f7385e 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -576,6 +576,7 @@ void drm_framebuffer_remove(struct drm_framebuffer *fb)
__drm_framebuffer_unreference(plane-fb);
plane-fb = NULL;
plane-crtc = NULL;
+ plane-crtc_mutex = NULL;
}
}
drm_modeset_unlock_all(dev);
@@ -1785,6 +1786,7 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
int ret = 0;
unsigned int fb_width, fb_height;
int i;
+ struct mutex *old_crtc_mutex;
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -EINVAL;
@@ -1804,12 +1806,33 @@ int drm_mode_setplane(struct drm_device *dev, void
*data,
/* No fb means shut it down */
if (!plane_req-fb_id) {
- drm_modeset_lock_all(dev);
+ struct mutex *crtc_mutex;
+
+ retry:
+ crtc_mutex = ACCESS_ONCE(plane-crtc_mutex);
+
+ /* plane was already disabled? */
+ if (!crtc_mutex)
+ return 0;
+
+ mutex_lock(crtc_mutex);
+
+ /* re-check that plane is still on the same crtc... */
+ if (crtc_mutex != plane-crtc_mutex) {
+ mutex_unlock(crtc_mutex);
+ goto retry;
+ }
+
old_fb = plane-fb;
plane-funcs-disable_plane(plane);
plane-crtc = NULL;
plane-fb = NULL;
- drm_modeset_unlock_all(dev);
+
+ smp_wmb();
+ plane-crtc_mutex = NULL;
+
+ mutex_unlock(crtc_mutex);
+
goto out;
}
@@ -1875,7 +1898,15 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
goto out;
}
- drm_modeset_lock_all(dev);
+ mutex_lock(crtc-mutex);
+
+ old_crtc_mutex = cmpxchg(plane-crtc_mutex, NULL, crtc-mutex);
+ if (old_crtc_mutex != NULL old_crtc_mutex != crtc-mutex) {
+ mutex_unlock(crtc-mutex);
+ ret = -EBUSY;
+ goto out;
+ }
+
ret = plane-funcs-update_plane(plane, crtc, fb,
plane_req-crtc_x, plane_req-crtc_y,
plane_req-crtc_w, plane_req-crtc_h,
@@ -1886,8 +1917,12 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
plane-crtc = crtc;
plane-fb = fb;
fb = NULL;
+ } else {
+ smp_wmb();
+ plane-crtc_mutex = old_crtc_mutex;
}
- drm_modeset_unlock_all(dev);
+
+ mutex_unlock(crtc-mutex);
out:
if (fb)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8c7846b..cc3779f 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -651,6 +651,7 @@ struct drm_plane_funcs {
* @dev: DRM device this plane belongs to
* @head: for list management
* @base: base mode object
+ * @crtc_mutex: points to the mutex of the current owner CRTC
* @possible_crtcs: pipes this plane can be bound to
* @format_types: array of formats supported by this plane
* @format_count: number of formats supported
@@ -669,6 +670,8 @@ struct drm_plane {
struct drm_mode_object base;
+ struct mutex *crtc_mutex;
+
uint32_t possible_crtcs;
uint32_t *format_types;
uint32_t format_count;
--
1.8.1.5
___
Intel-gfx
[Intel-gfx] [PATCH] drm/i915: move cpu_transcoder to the pipe configuration
For a bunch of reason we need to more accurately track this:
- hw pipe state readout for Haswell needs the cpu transcoder.
- We need to know the right cpu transcoder in a bunch of places in
-disable and other modeset callbacks.
In the future we need to add hw state readoutcheck support, too. But
to avoid ugly merge conflicts do the rote sed job now without any
functional changes.
v2: Preserve the cpu_transcoder value when overwriting crtc-config.
Reported by Paulo.
Cc: Paulo Zanoni przan...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_ddi.c |8
drivers/gpu/drm/i915/intel_display.c | 37 +++---
drivers/gpu/drm/i915/intel_drv.h |6 +-
drivers/gpu/drm/i915/intel_hdmi.c|6 +++---
4 files changed, 33 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 22524cb..26a0a57 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -924,7 +924,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
int type = intel_encoder-type;
uint32_t temp;
@@ -958,7 +958,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
struct drm_encoder *encoder = intel_encoder-base;
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
enum pipe pipe = intel_crtc-pipe;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder-type;
uint32_t temp;
@@ -1223,7 +1223,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1233,7 +1233,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv = intel_crtc-base.dev-dev_private;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..948a2c3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -892,7 +892,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct
drm_i915_private *dev_priv,
struct drm_crtc *crtc = dev_priv-pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- return intel_crtc-cpu_transcoder;
+ return intel_crtc-config.cpu_transcoder;
}
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
@@ -3208,7 +3208,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
assert_transcoder_disabled(dev_priv, TRANSCODER_A);
@@ -3583,7 +3583,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc-pipe;
int plane = intel_crtc-plane;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (!intel_crtc-active)
return;
@@ -3643,7 +3643,7 @@ static void haswell_crtc_off(struct drm_crtc *crtc)
/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
* start using it. */
- intel_crtc-cpu_transcoder = (enum transcoder) intel_crtc-pipe;
+ intel_crtc-config.cpu_transcoder = (enum transcoder) intel_crtc-pipe;
intel_ddi_put_crtc_pll(crtc);
}
@@ -4499,7 +4499,7 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc,
[Intel-gfx] [PATCH 3/4] drm/i915: Sprite C support for Gen4 and earlier
From: Ville Syrjälä ville.syrj...@linux.intel.com Gen2-4 have a non-scalable sprite C, which can be assigned to either pipe A or pipe B dynamically. Expose sprite C as a drm_plame. I've tested this only on 85x (8086:3582) and 946 (8086:2972). Gen2/3 chipsets should also be able to re-assign the primary plane B to act as a sprite on pipe A. But in order to expose that, we should actually expose all primary planes as drm_planes. We should make that change eventually, but currently we're not yet ready for it. So for now only sprite C is exposed, and sprite B can't be used yet. Based on the gen2 docs, it seems that the sprite C support is usually present only on mobile platforms. The exception is SPG-B, which I'm assuming means i865g for our driver. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 27 +++ drivers/gpu/drm/i915/intel_display.c | 35 +++- drivers/gpu/drm/i915/intel_sprite.c | 339 +-- 3 files changed, 381 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 31de7e4..7a0037d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3085,15 +3085,24 @@ #define DISPPLANE_SRC_KEY_DISABLE0 #define DISPPLANE_LINE_DOUBLE(120) #define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_PLANE_CSC_DISABLE (119) #define DISPPLANE_STEREO_POLARITY_FIRST 0 #define DISPPLANE_STEREO_POLARITY_SECOND (118) +#define DISPPLANE_YUV_BYTE_ORDER_MASK (316) +#define DISPPLANE_YUV_ORDER_YUYV (016) +#define DISPPLANE_YUV_ORDER_UYVY (116) +#define DISPPLANE_YUV_ORDER_YVYU (216) +#define DISPPLANE_YUV_ORDER_VYUY (316) #define DISPPLANE_TRICKLE_FEED_DISABLE (114) /* Ironlake */ #define DISPPLANE_TILED (110) #define _DSPAADDR (dev_priv-info-display_mmio_offset + 0x70184) #define _DSPASTRIDE(dev_priv-info-display_mmio_offset + 0x70188) #define _DSPAPOS (dev_priv-info-display_mmio_offset + 0x7018C) /* reserved */ #define _DSPASIZE (dev_priv-info-display_mmio_offset + 0x70190) +#define _DSPAKEYMINVAL (dev_priv-info-display_mmio_offset + 0x70194) +#define _DSPAKEYMSK(dev_priv-info-display_mmio_offset + 0x70198) #define _DSPASURF (dev_priv-info-display_mmio_offset + 0x7019C) /* 965+ only */ +#define _DSPAKEYMAXVAL (dev_priv-info-display_mmio_offset + 0x701A0) #define _DSPATILEOFF (dev_priv-info-display_mmio_offset + 0x701A4) /* 965+ only */ #define _DSPAOFFSET(dev_priv-info-display_mmio_offset + 0x701A4) /* HSW */ #define _DSPASURFLIVE (dev_priv-info-display_mmio_offset + 0x701AC) @@ -3103,7 +3112,10 @@ #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) +#define DSPKEYMINVAL(plane) _PIPE(plane, _DSPAKEYMINVAL, _DSPBKEYMINVAL) +#define DSPKEYMSK(plane) _PIPE(plane, _DSPAKEYMSK, _DSPBKEYMSK) #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) +#define DSPKEYMAXVAL(plane) _PIPE(plane, _DSPAKEYMAXVAL, _DSPBKEYMAXVAL) #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) #define DSPLINOFF(plane) DSPADDR(plane) #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) @@ -3116,6 +3128,18 @@ #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg +/* plane C color correction */ +#define DCLRC0 (dev_priv-info-display_mmio_offset + 0x721d0) +#define DCLRC1 (dev_priv-info-display_mmio_offset + 0x721d4) + +/* plane C pre-blend gamma */ +#define GAMC5 (dev_priv-info-display_mmio_offset + 0x721e0) +#define GAMC4 (dev_priv-info-display_mmio_offset + 0x721e4) +#define GAMC3 (dev_priv-info-display_mmio_offset + 0x721e8) +#define GAMC2 (dev_priv-info-display_mmio_offset + 0x721ec) +#define GAMC1 (dev_priv-info-display_mmio_offset + 0x721f0) +#define GAMC0 (dev_priv-info-display_mmio_offset + 0x721f4) + /* VBIOS flags */ #define SWF00 (dev_priv-info-display_mmio_offset + 0x71410) #define SWF01 (dev_priv-info-display_mmio_offset + 0x71414) @@ -3151,9 +3175,12 @@ #define _DSPBSTRIDE(dev_priv-info-display_mmio_offset + 0x71188) #define _DSPBPOS (dev_priv-info-display_mmio_offset + 0x7118C) #define _DSPBSIZE (dev_priv-info-display_mmio_offset + 0x71190) +#define _DSPBKEYMINVAL (dev_priv-info-display_mmio_offset + 0x71194) +#define _DSPBKEYMSK(dev_priv-info-display_mmio_offset + 0x71198) #define _DSPBSURF
[Intel-gfx] [PATCH 4/4] drm/i915: Use ILK+ style video sprites for Gen4.5
From: Ville Syrjälä ville.syrj...@linux.intel.com
According to the docs CTG and BLC have similar video sprites
as ILK/SNB.
This is what the docs say about video sprite features:
CTG and BLC have video sprites, and in addition CTG-B has YUV byte
order selection, live surface registers, and sprite scale registers.
I'm not sure how to translate that into real code. BLC I assume means
Bearlake-C, but I don't really know what it means for us. I'm thinking
that the PCI ID for BLC could be 8086:2982, aka. G35 and apparently
sometimes called Bearlake-G+. Looks like cureently we're treating it
like a 965 though, not a g4x.
Also I'm not sure where ELK fits. It's not explicitly mentioned in
most places, but when it is, it usually seems to match CTG features.
The machine I have here is 8086:2e22 which is ELK AFAICT, and my code
works on it, so apparently ELK also has video sprites, and they seem
happy to scale the content, and YUV byte order selection seems to work
as well.
There's kind of similar confusion about the frame counter registers
since the docs just say that CL uses the old style, CTG/ELK use the
new style. No mention of BW, BL or BLC here.
BLC is special in may places, in some places it matches BW/CL and
in some cases CTG.
For now I just chose to enable use the video sprite code paths when
IS_G4X() is true, and I've ignored the no-scale/no-YUV byte order
selection issues. Unfortunatly I don't have the hardware to verify
all the details.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4f3b490..9ed2b04 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9056,7 +9056,7 @@ void intel_modeset_init(struct drm_device *dev)
for (i = 0; i INTEL_INFO(dev)-num_pipes; i++) {
intel_crtc_init(dev, i);
- if (INTEL_INFO(dev)-gen = 4)
+ if (INTEL_INFO(dev)-gen = 4 !IS_G4X(dev))
continue;
for (j = 0; j dev_priv-num_plane; j++) {
@@ -9087,7 +9087,7 @@ void intel_modeset_init(struct drm_device *dev)
}
/* two pipes and planes A+B+C */
- if (INTEL_INFO(dev)-gen = 4
+ if (INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)
INTEL_INFO(dev)-num_pipes == 2) {
ret = intel_plane_init(dev, 0, PLANE_C);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 026e6b8..ae78942 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -862,7 +862,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
return -EINVAL;
/* Don't modify another pipe's plane */
- if (INTEL_INFO(dev)-gen = 4) {
+ if (INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)) {
if (!gen2_check_pipe_sel(plane, pipe))
return -EINVAL;
} else {
@@ -1178,7 +1178,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
case 4:
case 5:
case 6:
- if (INTEL_INFO(dev)-gen = 4) {
+ if (INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)) {
intel_plane-can_scale = false;
intel_plane-max_downscale = 1;
@@ -1249,7 +1249,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane-pipe = pipe;
intel_plane-plane = plane;
- if (INTEL_INFO(dev)-gen = 5)
+ if (INTEL_INFO(dev)-gen = 5 || IS_G4X(dev))
possible_crtcs = 1 pipe;
else
possible_crtcs = (1 INTEL_INFO(dev)-num_pipes) - 1;
--
1.8.1.5
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[Intel-gfx] [PATCH 2/4] drm/i915: Clarify DSPPOS/DSPSIZE and pipe selection for planes A/B
From: Ville Syrjälä ville.syrj...@linux.intel.com
DSPPOS/DSPSIZE for planes A/B doesn't exist on Gen4+, so don't write
them.
Also the pipe selection for planes A and B is only relevant for Gen3
and earlier. Gen4 moved to fixed plane-pipe mapping. Plane C is
still movable between pipes on Gen4, but that fact is not relevant
for the CRTC codepaths since we never use plane C as the CRTC plane.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fb88356..4f4a8d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4719,8 +4719,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
- if (!IS_VALLEYVIEW(dev)) {
- if (pipe == 0)
+ /* planes A/B are fixed to pipes A/B respectively on Gen4+ */
+ if (INTEL_INFO(dev)-gen = 3) {
+ if (pipe == PIPE_A)
dspcntr = ~DISPPLANE_SEL_PIPE_MASK;
else
dspcntr |= DISPPLANE_SEL_PIPE_B;
@@ -4733,11 +4734,15 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
/* pipesrc and dspsize control the size that is scaled from,
* which should always be the user's requested size.
+*
+* DSPPOS/DSPSIZE for planes A/B only exist on Gen3 and earlier.
*/
- I915_WRITE(DSPSIZE(plane),
- ((mode-vdisplay - 1) 16) |
- (mode-hdisplay - 1));
- I915_WRITE(DSPPOS(plane), 0);
+ if (INTEL_INFO(dev)-gen = 3) {
+ I915_WRITE(DSPSIZE(plane),
+ ((mode-vdisplay - 1) 16) |
+ (mode-hdisplay - 1));
+ I915_WRITE(DSPPOS(plane), 0);
+ }
i9xx_set_pipeconf(intel_crtc);
--
1.8.1.5
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[Intel-gfx] [PATCH 1/4] drm/i915: Disable primary plane trickle feed for g4x
From: Ville Syrjälä ville.syrj...@linux.intel.com The docs say that the trickle feed disable bit is present (for primary planes only, not video sprites) on BLC and CTG, and that it must be set for ELK. Just set it for all g4x chipset. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 21f368c..fb88356 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2150,6 +2150,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, dspcntr = ~DISPPLANE_TILED; } + if (IS_G4X(dev)) + dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; + I915_WRITE(reg, dspcntr); linear_offset = y * fb-pitches[0] + x * (fb-bits_per_pixel / 8); -- 1.8.1.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable primary plane trickle feed for g4x
On Wed, Apr 17, 2013 at 08:11:58PM +0300, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com The docs say that the trickle feed disable bit is present (for primary planes only, not video sprites) on BLC and CTG, and that it must be set for ELK. Just set it for all g4x chipset. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com I'm stunned that we did all the post-pch chipsets but missed g4x. Perhaps we should also do it during init_clock_gating() as we do for other generations? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/4] drm/edid: Recognize 60Hz and 59.94Hz CEA modes
This series attempts to make our CEA mode matching recognize both the 60Hz and 59.94Hz variants of the modes (and similarly for 24/23.97, 30/29.97, etc.). The benefits should include: - Send the correct VIC in the AVI infoframe - Pick the correct RGB quantization range in automatic mode ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm: Remove explicit vrefresh initialization from DRM_MODE()
From: Ville Syrjälä ville.syrj...@linux.intel.com
No need to zero initialize .vrefresh in DRM_MODE() since it's using
desgignated initializers.
This will also avoid some duplicate initialization warnings later.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
include/drm/drm_crtc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8c7846b..b85575b 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -120,7 +120,7 @@ enum drm_mode_status {
.hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
.htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
.vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
- .vscan = (vs), .flags = (f), .vrefresh = 0, \
+ .vscan = (vs), .flags = (f), \
.base.type = DRM_MODE_OBJECT_MODE
#define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
--
1.8.1.5
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[Intel-gfx] [PATCH 2/4] drm: Add drm_mode_equal_no_clocks()
From: Ville Syrjälä ville.syrj...@linux.intel.com
drm_mode_equal_no_clocks() is like drm_mode_equal() except it doesn't
compare the clock or vrefresh values. drm_mode_equal() is now
implemented by first doing the clock checks, and then calling
drm_mode_equal_no_clocks().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/drm_modes.c | 20 +++-
include/drm/drm_crtc.h | 1 +
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 04fa6f1..db85d0b9 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -848,6 +848,24 @@ bool drm_mode_equal(const struct drm_display_mode *mode1,
const struct drm_displ
} else if (mode1-clock != mode2-clock)
return false;
+ return drm_mode_equal_no_clocks(mode1, mode2);
+}
+/**
+ * drm_mode_equal_no_clocks - test modes for equality
+ * @mode1: first mode
+ * @mode2: second mode
+ *
+ * LOCKING:
+ * None.
+ *
+ * Check to see if @mode1 and @mode2 are equivalent, but
+ * don't check the pixel clocks.
+ *
+ * RETURNS:
+ * True if the modes are equal, false otherwise.
+ */
+bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, const
struct drm_display_mode *mode2)
+{
if (mode1-hdisplay == mode2-hdisplay
mode1-hsync_start == mode2-hsync_start
mode1-hsync_end == mode2-hsync_end
@@ -863,7 +881,7 @@ bool drm_mode_equal(const struct drm_display_mode *mode1,
const struct drm_displ
return false;
}
-EXPORT_SYMBOL(drm_mode_equal);
+EXPORT_SYMBOL(drm_mode_equal_no_clocks);
/**
* drm_mode_validate_size - make sure modes adhere to size constraints
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index b85575b..836438d 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -922,6 +922,7 @@ extern void drm_mode_config_reset(struct drm_device *dev);
extern void drm_mode_config_cleanup(struct drm_device *dev);
extern void drm_mode_set_name(struct drm_display_mode *mode);
extern bool drm_mode_equal(const struct drm_display_mode *mode1, const struct
drm_display_mode *mode2);
+extern bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1,
const struct drm_display_mode *mode2);
extern int drm_mode_width(const struct drm_display_mode *mode);
extern int drm_mode_height(const struct drm_display_mode *mode);
--
1.8.1.5
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[Intel-gfx] [PATCH 3/4] drm/edid: Populate vrefresh for CEA modes
From: Ville Syrjälä ville.syrj...@linux.intel.com
Well have use for the vrefresh information of CEA modes later. Just
populate the information into the table to avoid having to calculate
it.
I'm too lazy to check if someone relies on newly allocated CEA
modes having 0 vrefresh, so just clear vrefresh back to 0 when
adding the mode to the connector's modelist.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/drm_edid.c | 193 ++---
1 file changed, 129 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e2acfdb..e233ff5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -587,284 +587,348 @@ static const struct drm_display_mode edid_cea_modes[] =
{
/* 1 - 640x480@60Hz */
{ DRM_MODE(640x480, DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752, 800, 0, 480, 490, 492, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ .vrefresh = 60, },
/* 2 - 720x480@60Hz */
{ DRM_MODE(720x480, DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ .vrefresh = 60, },
/* 3 - 720x480@60Hz */
{ DRM_MODE(720x480, DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ .vrefresh = 60, },
/* 4 - 1280x720@60Hz */
{ DRM_MODE(1280x720, DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1430, 1650, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 60, },
/* 5 - 1920x1080i@60Hz */
{ DRM_MODE(1920x1080i, DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE) },
+ DRM_MODE_FLAG_INTERLACE),
+ .vrefresh = 60, },
/* 6 - 1440x480i@60Hz */
{ DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK) },
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ .vrefresh = 60, },
/* 7 - 1440x480i@60Hz */
{ DRM_MODE(1440x480i, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK) },
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ .vrefresh = 60, },
/* 8 - 1440x240@60Hz */
{ DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 240, 244, 247, 262, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK) },
+ DRM_MODE_FLAG_DBLCLK),
+ .vrefresh = 60, },
/* 9 - 1440x240@60Hz */
{ DRM_MODE(1440x240, DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 240, 244, 247, 262, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK) },
+ DRM_MODE_FLAG_DBLCLK),
+ .vrefresh = 60, },
/* 10 - 2880x480i@60Hz */
{ DRM_MODE(2880x480i, DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE) },
+ DRM_MODE_FLAG_INTERLACE),
+ .vrefresh = 60, },
/* 11 - 2880x480i@60Hz */
{ DRM_MODE(2880x480i, DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE) },
+ DRM_MODE_FLAG_INTERLACE),
+ .vrefresh = 60, },
/* 12 - 2880x240@60Hz */
{ DRM_MODE(2880x240, DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 240, 244, 247, 262, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ .vrefresh = 60, },
/* 13 -
[Intel-gfx] [PATCH 4/4] drm/edid: Check both 60Hz and 59.94Hz when looking for a CEA mode
From: Ville Syrjälä ville.syrj...@linux.intel.com
drm_match_cea_mode() should be able to match both the 60Hz version,
and the 59.94Hz version of modes.
We only store one pixel clock value per mode in edid_cea_modes, so the
other value must be calculated. Depending on the mode, edid_cea_modes
contains the pixel clock for either the 60Hz version or the 59.94Hz
version, so a bit of care is needed so that the calculation produces
the correct result.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46800
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/drm_edid.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e233ff5..71d49f2 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2330,13 +2330,34 @@ EXPORT_SYMBOL(drm_find_cea_extension);
*/
u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
{
- struct drm_display_mode *cea_mode;
u8 mode;
+ if (!to_match-clock)
+ return 0;
+
for (mode = 0; mode ARRAY_SIZE(edid_cea_modes); mode++) {
- cea_mode = (struct drm_display_mode *)edid_cea_modes[mode];
+ const struct drm_display_mode *cea_mode = edid_cea_modes[mode];
+ unsigned int clock1, clock2;
- if (drm_mode_equal(to_match, cea_mode))
+ clock1 = clock2 = cea_mode-clock;
+
+ /* Check both 60Hz and 59.94Hz */
+ if (cea_mode-vrefresh % 6 == 0) {
+ /*
+* edid_cea_modes contains the 59.94Hz
+* variant for 240 and 480 line modes,
+* and the 60Hz variant otherwise.
+*/
+ if (cea_mode-vdisplay == 240 ||
+ cea_mode-vdisplay == 480)
+ clock1 = clock1 * 1001 / 1000;
+ else
+ clock2 = DIV_ROUND_UP(clock2 * 1000, 1001);
+ }
+
+ if ((KHZ2PICOS(to_match-clock) == KHZ2PICOS(clock1) ||
+KHZ2PICOS(to_match-clock) == KHZ2PICOS(clock2))
+ drm_mode_equal_no_clocks(to_match, cea_mode))
return mode + 1;
}
return 0;
--
1.8.1.5
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable primary plane trickle feed for g4x
On Wed, Apr 17, 2013 at 06:25:29PM +0100, Chris Wilson wrote: On Wed, Apr 17, 2013 at 08:11:58PM +0300, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com The docs say that the trickle feed disable bit is present (for primary planes only, not video sprites) on BLC and CTG, and that it must be set for ELK. Just set it for all g4x chipset. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com I'm stunned that we did all the post-pch chipsets but missed g4x. Perhaps we should also do it during init_clock_gating() as we do for other generations? Actually we do it in both ironlake_update_plane() and init_clock_gating() for gen5+. I guess someone wanted to make sure the bit sticks ;) I'm thinking I'd rather kill the init_clock_gating() parts since that would keep the whole plane setup in one place. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC][PATCH] drm: Insane but more fine grained locking for planes
On Wed, Apr 17, 2013 at 08:04:52PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Instead of locking all modeset locks during plane updates, use just
a single CRTC mutex. To make that work, track the CRTC that owns
the plane currently. During enable/update that means the new
CRTC, and during disable it means the old CRTC.
Since the plane state is no longer protected by a single lock, we
need to sprinkle some additional memory barriers when relinquishing
ownership. Otherwise the next CRTC might observe some stale state
even though the crtc_mutex already got updated.
drm_framebuffer_remove() doesn't need extra barriers since it
already holds all CRTC locks, and thus no-one can be poking around
at the same time. On the read side cmpxchg() already should have
the necessary memory barriers.
This design implies that before a plane can be moved to another CRTC,
it must be disabled first, even if the hardware would offer some kind
of mechanism to move an active plane over directly. I believe everyone
has agreed that this an acceptable compromise.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Since the insanity is around plane-crtc_mutex, why not just add a plane
mutex which _only_ protects that?
That way we could partially resurect the old semantics by simply first
grabbing the old crtc mutex, removing the fb, then grabbing the new crtc
mutex and displaying it there. Whoever shows up with hw which can do that
in one atomic step gets to fix the resulting mess then ;-)
-Daniel
---
drivers/gpu/drm/drm_crtc.c | 43 +++
include/drm/drm_crtc.h | 3 +++
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 957fb70..6f7385e 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -576,6 +576,7 @@ void drm_framebuffer_remove(struct drm_framebuffer *fb)
__drm_framebuffer_unreference(plane-fb);
plane-fb = NULL;
plane-crtc = NULL;
+ plane-crtc_mutex = NULL;
}
}
drm_modeset_unlock_all(dev);
@@ -1785,6 +1786,7 @@ int drm_mode_setplane(struct drm_device *dev, void
*data,
int ret = 0;
unsigned int fb_width, fb_height;
int i;
+ struct mutex *old_crtc_mutex;
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -EINVAL;
@@ -1804,12 +1806,33 @@ int drm_mode_setplane(struct drm_device *dev, void
*data,
/* No fb means shut it down */
if (!plane_req-fb_id) {
- drm_modeset_lock_all(dev);
+ struct mutex *crtc_mutex;
+
+ retry:
+ crtc_mutex = ACCESS_ONCE(plane-crtc_mutex);
+
+ /* plane was already disabled? */
+ if (!crtc_mutex)
+ return 0;
+
+ mutex_lock(crtc_mutex);
+
+ /* re-check that plane is still on the same crtc... */
+ if (crtc_mutex != plane-crtc_mutex) {
+ mutex_unlock(crtc_mutex);
+ goto retry;
+ }
+
old_fb = plane-fb;
plane-funcs-disable_plane(plane);
plane-crtc = NULL;
plane-fb = NULL;
- drm_modeset_unlock_all(dev);
+
+ smp_wmb();
+ plane-crtc_mutex = NULL;
+
+ mutex_unlock(crtc_mutex);
+
goto out;
}
@@ -1875,7 +1898,15 @@ int drm_mode_setplane(struct drm_device *dev, void
*data,
goto out;
}
- drm_modeset_lock_all(dev);
+ mutex_lock(crtc-mutex);
+
+ old_crtc_mutex = cmpxchg(plane-crtc_mutex, NULL, crtc-mutex);
+ if (old_crtc_mutex != NULL old_crtc_mutex != crtc-mutex) {
+ mutex_unlock(crtc-mutex);
+ ret = -EBUSY;
+ goto out;
+ }
+
ret = plane-funcs-update_plane(plane, crtc, fb,
plane_req-crtc_x, plane_req-crtc_y,
plane_req-crtc_w, plane_req-crtc_h,
@@ -1886,8 +1917,12 @@ int drm_mode_setplane(struct drm_device *dev, void
*data,
plane-crtc = crtc;
plane-fb = fb;
fb = NULL;
+ } else {
+ smp_wmb();
+ plane-crtc_mutex = old_crtc_mutex;
}
- drm_modeset_unlock_all(dev);
+
+ mutex_unlock(crtc-mutex);
out:
if (fb)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8c7846b..cc3779f 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -651,6 +651,7 @@ struct drm_plane_funcs {
* @dev: DRM device this plane belongs to
* @head: for list management
* @base: base mode object
+ * @crtc_mutex: points to the
Re: [Intel-gfx] [PATCH] tests/prime_self_import: export/import a second gem buffer
On Wed, 2013-04-17 at 19:06 +0200, Daniel Vetter wrote:
On Wed, Apr 17, 2013 at 07:10:00PM +0300, Imre Deak wrote:
Signed-off-by: Imre Deak imre.d...@intel.com
I'm a bit confused what this does ... can you please elaborate?
It creates a second GEM buffer on fd1, exports it, imports it on fd2 and
check if the imported buffer contents matches the original one.
--Imre
-Daniel
---
tests/prime_self_import.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 111ed4d..a17e942 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_self_import.c
@@ -48,11 +48,13 @@
#define BO_SIZE (16*1024)
+static char counter1;
+static char counter2;
+
static void
-check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2)
+check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2, char
*counter)
{
char *ptr1, *ptr2;
- static char counter = 0;
int i;
ptr1 = gem_mmap(fd1, handle1, BO_SIZE, PROT_READ | PROT_WRITE);
@@ -62,13 +64,13 @@ check_bo(int fd1, uint32_t handle1, int fd2, uint32_t
handle2)
/* check whether it's still our old object first. */
for (i = 0; i BO_SIZE; i++) {
- assert(ptr1[i] == counter);
- assert(ptr2[i] == counter);
+ assert(ptr1[i] == *counter);
+ assert(ptr2[i] == *counter);
}
- counter++;
+ (*counter)++;
- memset(ptr1, counter, BO_SIZE);
+ memset(ptr1, *counter, BO_SIZE);
assert(memcmp(ptr1, ptr2, BO_SIZE) == 0);
munmap(ptr1, BO_SIZE);
@@ -79,17 +81,19 @@ int main(int argc, char **argv)
{
int fd1, fd2;
uint32_t handle, handle_import1, handle_import2, handle_selfimport;
+ uint32_t handle2;
int dma_buf_fd;
fd1 = drm_open_any();
fd2 = drm_open_any();
handle = gem_create(fd1, BO_SIZE);
+ handle2 = gem_create(fd1, BO_SIZE);
dma_buf_fd = prime_handle_to_fd(fd1, handle);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
/* reimport should give us the same handle so that userspace can check
* whether it has that bo already somewhere. */
@@ -102,10 +106,17 @@ int main(int argc, char **argv)
/* close dma_buf, check whether nothing disappears. */
close(dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
gem_close(fd1, handle);
- check_bo(fd2, handle_import1, fd2, handle_import1);
+ check_bo(fd2, handle_import1, fd2, handle_import1, counter1);
+
+ dma_buf_fd = prime_handle_to_fd(fd1, handle2);
+ handle = prime_fd_to_handle(fd2, dma_buf_fd);
+ check_bo(fd1, handle2, fd2, handle, counter2);
+ gem_close(fd2, handle);
+ gem_close(fd1, handle2);
+ close(dma_buf_fd);
/* re-import into old exporter */
dma_buf_fd = prime_handle_to_fd(fd2, handle_import1);
@@ -113,11 +124,11 @@ int main(int argc, char **argv)
gem_close(fd2, handle_import1);
handle = prime_fd_to_handle(fd1, dma_buf_fd);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
- check_bo(fd1, handle, fd2, handle_import1);
+ check_bo(fd1, handle, fd2, handle_import1, counter1);
/* Completely rip out exporting fd. */
close(fd1);
- check_bo(fd2, handle_import1, fd2, handle_import1);
+ check_bo(fd2, handle_import1, fd2, handle_import1, counter1);
return 0;
}
--
1.7.10.4
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[Intel-gfx] [PATCH] drm/i915: fix bpc vs. bpp confusion in intel_crtc_compute_config
Oops.
This regression has been introduced in
commit 5d2d38ddcac991f71c19d03d95bde8e14abc0352
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Wed Mar 27 00:45:01 2013 +0100
drm/i915: clean up pipe bpp confusion
Reported-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 85acef5..47104e0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4006,9 +4006,9 @@ static int intel_crtc_compute_config(struct drm_crtc
*crtc,
adjusted_mode-hsync_start == adjusted_mode-hdisplay)
return -EINVAL;
- if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) pipe_config-pipe_bpp 10) {
+ if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) pipe_config-pipe_bpp
10*3) {
pipe_config-pipe_bpp = 10*3; /* 12bpc is gen5+ */
- } else if (INTEL_INFO(dev)-gen = 4 pipe_config-pipe_bpp 8) {
+ } else if (INTEL_INFO(dev)-gen = 4 pipe_config-pipe_bpp 8*3) {
/* only a 8bpc pipe, with 6bpc dither through the panel fitter
* for lvds. */
pipe_config-pipe_bpp = 8*3;
--
1.7.11.7
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Re: [Intel-gfx] [PATCH] drm/i915: move cpu_transcoder to the pipe configuration
2013/4/17 Daniel Vetter daniel.vet...@ffwll.ch:
For a bunch of reason we need to more accurately track this:
- hw pipe state readout for Haswell needs the cpu transcoder.
- We need to know the right cpu transcoder in a bunch of places in
-disable and other modeset callbacks.
In the future we need to add hw state readoutcheck support, too. But
to avoid ugly merge conflicts do the rote sed job now without any
functional changes.
v2: Preserve the cpu_transcoder value when overwriting crtc-config.
Reported by Paulo.
No more WARNs here. Just booted, checked dmesg and checked if there
are pixels on the screen.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Cc: Paulo Zanoni przan...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_ddi.c |8
drivers/gpu/drm/i915/intel_display.c | 37
+++---
drivers/gpu/drm/i915/intel_drv.h |6 +-
drivers/gpu/drm/i915/intel_hdmi.c|6 +++---
4 files changed, 33 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c
index 22524cb..26a0a57 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -924,7 +924,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_encoder(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
int type = intel_encoder-type;
uint32_t temp;
@@ -958,7 +958,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc)
struct drm_encoder *encoder = intel_encoder-base;
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
enum pipe pipe = intel_crtc-pipe;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder-type;
uint32_t temp;
@@ -1223,7 +1223,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1233,7 +1233,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv = intel_crtc-base.dev-dev_private;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..948a2c3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -892,7 +892,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct
drm_i915_private *dev_priv,
struct drm_crtc *crtc = dev_priv-pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- return intel_crtc-cpu_transcoder;
+ return intel_crtc-config.cpu_transcoder;
}
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
@@ -3208,7 +3208,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
assert_transcoder_disabled(dev_priv, TRANSCODER_A);
@@ -3583,7 +3583,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc-pipe;
int plane = intel_crtc-plane;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (!intel_crtc-active)
return;
@@ -3643,7 +3643,7 @@ static void haswell_crtc_off(struct drm_crtc *crtc)
/* Stop saying we're using TRANSCODER_EDP because some other CRTC
might
* start using
Re: [Intel-gfx] [PATCH] drm/i915: move cpu_transcoder to the pipe configuration
On Wed, Apr 17, 2013 at 03:09:50PM -0300, Paulo Zanoni wrote:
2013/4/17 Daniel Vetter daniel.vet...@ffwll.ch:
For a bunch of reason we need to more accurately track this:
- hw pipe state readout for Haswell needs the cpu transcoder.
- We need to know the right cpu transcoder in a bunch of places in
-disable and other modeset callbacks.
In the future we need to add hw state readoutcheck support, too. But
to avoid ugly merge conflicts do the rote sed job now without any
functional changes.
v2: Preserve the cpu_transcoder value when overwriting crtc-config.
Reported by Paulo.
No more WARNs here. Just booted, checked dmesg and checked if there
are pixels on the screen.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Let's try this again ... thanks for the review.
-Daniel
Cc: Paulo Zanoni przan...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_ddi.c |8
drivers/gpu/drm/i915/intel_display.c | 37
+++---
drivers/gpu/drm/i915/intel_drv.h |6 +-
drivers/gpu/drm/i915/intel_hdmi.c|6 +++---
4 files changed, 33 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c
index 22524cb..26a0a57 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -924,7 +924,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_encoder(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
int type = intel_encoder-type;
uint32_t temp;
@@ -958,7 +958,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc)
struct drm_encoder *encoder = intel_encoder-base;
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
enum pipe pipe = intel_crtc-pipe;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder-type;
uint32_t temp;
@@ -1223,7 +1223,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1233,7 +1233,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc)
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv =
intel_crtc-base.dev-dev_private;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..948a2c3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -892,7 +892,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct
drm_i915_private *dev_priv,
struct drm_crtc *crtc = dev_priv-pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- return intel_crtc-cpu_transcoder;
+ return intel_crtc-config.cpu_transcoder;
}
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
@@ -3208,7 +3208,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
assert_transcoder_disabled(dev_priv, TRANSCODER_A);
@@ -3583,7 +3583,7 @@ static void haswell_crtc_disable(struct drm_crtc
*crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc-pipe;
int plane = intel_crtc-plane;
- enum transcoder cpu_transcoder = intel_crtc-cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc-config.cpu_transcoder;
Re: [Intel-gfx] [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend
Hi
2013/4/17 Imre Deak imre.d...@intel.com:
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
s/Paolo/Paulo/ :)
Besides this, the patch looks fine. But I can't test it right now
since suspend seems to be broken on my machine, even with nomodeset.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c |5 +
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 18 ++
5 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895..6902219 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -525,6 +525,8 @@ static int i915_drm_freeze(struct drm_device *dev)
*/
list_for_each_entry(crtc, dev-mode_config.crtc_list, head)
dev_priv-display.crtc_disable(crtc);
+
+ intel_modeset_suspend_hw(dev);
}
i915_save_state(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5a495a..e549e6c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) {
return; }
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
+extern void intel_modeset_suspend_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..dec9019 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9004,6 +9004,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
mutex_unlock(dev-struct_mutex);
}
+void intel_modeset_suspend_hw(struct drm_device *dev)
+{
+ intel_suspend_hw(dev);
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index a124e05..3f31b2e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe,
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
extern void intel_init_clock_gating(struct drm_device *dev);
+extern void intel_suspend_hw(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f747cb0..8a163d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3750,6 +3750,18 @@ static void lpt_init_clock_gating(struct drm_device
*dev)
PCH_LP_PARTITION_LEVEL_DISABLE);
}
+static void lpt_suspend_hw(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (dev_priv-pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
+ uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
+
+ val = ~PCH_LP_PARTITION_LEVEL_DISABLE;
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+ }
+}
+
static void haswell_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4100,6 +4112,12 @@ void intel_init_clock_gating(struct drm_device *dev)
dev_priv-display.init_clock_gating(dev);
}
+void intel_suspend_hw(struct drm_device *dev)
+{
+ if (HAS_PCH_LPT(dev))
+ lpt_suspend_hw(dev);
+}
+
/**
* We should only use the power well if we explicitly asked the hardware to
* enable it, so check if it's enabled and also check if we've requested it
to
--
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Re: [Intel-gfx] [PATCH 2/4] drm: Add drm_mode_equal_no_clocks()
Hi
2013/4/17 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
drm_mode_equal_no_clocks() is like drm_mode_equal() except it doesn't
compare the clock or vrefresh values. drm_mode_equal() is now
implemented by first doing the clock checks, and then calling
drm_mode_equal_no_clocks().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/drm_modes.c | 20 +++-
include/drm/drm_crtc.h | 1 +
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 04fa6f1..db85d0b9 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -848,6 +848,24 @@ bool drm_mode_equal(const struct drm_display_mode
*mode1, const struct drm_displ
} else if (mode1-clock != mode2-clock)
return false;
+ return drm_mode_equal_no_clocks(mode1, mode2);
+}
EXPORT_SYMBOL(drm_mode_equal) is gone. I'd also add a newline here.
+/**
+ * drm_mode_equal_no_clocks - test modes for equality
+ * @mode1: first mode
+ * @mode2: second mode
+ *
+ * LOCKING:
+ * None.
+ *
+ * Check to see if @mode1 and @mode2 are equivalent, but
+ * don't check the pixel clocks.
+ *
+ * RETURNS:
+ * True if the modes are equal, false otherwise.
+ */
+bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, const
struct drm_display_mode *mode2)
+{
if (mode1-hdisplay == mode2-hdisplay
mode1-hsync_start == mode2-hsync_start
mode1-hsync_end == mode2-hsync_end
@@ -863,7 +881,7 @@ bool drm_mode_equal(const struct drm_display_mode *mode1,
const struct drm_displ
return false;
}
-EXPORT_SYMBOL(drm_mode_equal);
+EXPORT_SYMBOL(drm_mode_equal_no_clocks);
/**
* drm_mode_validate_size - make sure modes adhere to size constraints
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index b85575b..836438d 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -922,6 +922,7 @@ extern void drm_mode_config_reset(struct drm_device *dev);
extern void drm_mode_config_cleanup(struct drm_device *dev);
extern void drm_mode_set_name(struct drm_display_mode *mode);
extern bool drm_mode_equal(const struct drm_display_mode *mode1, const
struct drm_display_mode *mode2);
+extern bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1,
const struct drm_display_mode *mode2);
extern int drm_mode_width(const struct drm_display_mode *mode);
extern int drm_mode_height(const struct drm_display_mode *mode);
--
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Re: [Intel-gfx] [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend
On Wed, 2013-04-17 at 16:05 -0300, Paulo Zanoni wrote:
Hi
2013/4/17 Imre Deak imre.d...@intel.com:
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
s/Paolo/Paulo/ :)
Ok, sorry..
Besides this, the patch looks fine. But I can't test it right now
since suspend seems to be broken on my machine, even with nomodeset.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Yes, same here suspend is broken even without loading i915.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c |5 +
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 18 ++
5 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895..6902219 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -525,6 +525,8 @@ static int i915_drm_freeze(struct drm_device *dev)
*/
list_for_each_entry(crtc, dev-mode_config.crtc_list, head)
dev_priv-display.crtc_disable(crtc);
+
+ intel_modeset_suspend_hw(dev);
}
i915_save_state(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index b5a495a..e549e6c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void)
{ return; }
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
+extern void intel_modeset_suspend_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dce643c..dec9019 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9004,6 +9004,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
mutex_unlock(dev-struct_mutex);
}
+void intel_modeset_suspend_hw(struct drm_device *dev)
+{
+ intel_suspend_hw(dev);
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index a124e05..3f31b2e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe,
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
extern void intel_init_clock_gating(struct drm_device *dev);
+extern void intel_suspend_hw(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index f747cb0..8a163d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3750,6 +3750,18 @@ static void lpt_init_clock_gating(struct drm_device
*dev)
PCH_LP_PARTITION_LEVEL_DISABLE);
}
+static void lpt_suspend_hw(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (dev_priv-pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
+ uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
+
+ val = ~PCH_LP_PARTITION_LEVEL_DISABLE;
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+ }
+}
+
static void haswell_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4100,6 +4112,12 @@ void intel_init_clock_gating(struct drm_device *dev)
dev_priv-display.init_clock_gating(dev);
}
+void intel_suspend_hw(struct drm_device *dev)
+{
+ if (HAS_PCH_LPT(dev))
+ lpt_suspend_hw(dev);
+}
+
/**
* We should only use the power well if we explicitly asked the hardware to
* enable it, so check if it's enabled and also check if we've requested
it to
--
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[Intel-gfx] [PATCH v2] tests/prime_self_import: add subtest to export/import a second gem buffer
Also add a subtest for the fd=handle_to_fd(), fd2=dup(fd), close(fd)
case (idea from Kristian Høgsberg).
Signed-off-by: Imre Deak imre.d...@intel.com
v2:
- add a new subtest instead of modifying the original test (Daniel)
- add a new subtest for testing dup (Kristian)
---
tests/Makefile.am |2 +-
tests/prime_self_import.c | 88 +++--
2 files changed, 87 insertions(+), 3 deletions(-)
diff --git a/tests/Makefile.am b/tests/Makefile.am
index e147e4e..d4e25a7 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -32,6 +32,7 @@ TESTS_progs_M = \
gem_tiled_partial_pwrite_pread \
$(NOUVEAU_TESTS_M) \
kms_flip \
+ prime_self_import \
$(NULL)
TESTS_progs = \
@@ -101,7 +102,6 @@ TESTS_progs = \
gem_reg_read \
gem_tiling_max_stride \
$(NOUVEAU_TESTS) \
- prime_self_import \
prime_udl \
$(NULL)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 111ed4d..abdc220 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_self_import.c
@@ -48,11 +48,14 @@
#define BO_SIZE (16*1024)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static char counter;
+
static void
check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2)
{
char *ptr1, *ptr2;
- static char counter = 0;
int i;
ptr1 = gem_mmap(fd1, handle1, BO_SIZE, PROT_READ | PROT_WRITE);
@@ -75,7 +78,68 @@ check_bo(int fd1, uint32_t handle1, int fd2, uint32_t
handle2)
munmap(ptr2, BO_SIZE);
}
-int main(int argc, char **argv)
+static void test_with_fd_dup(void)
+{
+ int fd1, fd2;
+ uint32_t handle, handle_import;
+ int dma_buf_fd1, dma_buf_fd2;
+
+ counter = 0;
+
+ fd1 = drm_open_any();
+ fd2 = drm_open_any();
+
+ handle = gem_create(fd1, BO_SIZE);
+
+ dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
+ gem_close(fd1, handle);
+
+ dma_buf_fd2 = dup(dma_buf_fd1);
+ close(dma_buf_fd1);
+ handle_import = prime_fd_to_handle(fd2, dma_buf_fd2);
+ check_bo(fd2, handle_import, fd2, handle_import);
+
+ close(dma_buf_fd2);
+ check_bo(fd2, handle_import, fd2, handle_import);
+
+ close(fd1);
+ close(fd2);
+}
+
+static void test_with_two_bos(void)
+{
+ int fd1, fd2;
+ uint32_t handle1, handle2, handle_import;
+ int dma_buf_fd;
+
+ counter = 0;
+
+ fd1 = drm_open_any();
+ fd2 = drm_open_any();
+
+ handle1 = gem_create(fd1, BO_SIZE);
+ handle2 = gem_create(fd1, BO_SIZE);
+
+ dma_buf_fd = prime_handle_to_fd(fd1, handle1);
+ handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
+
+ close(dma_buf_fd);
+ gem_close(fd1, handle1);
+
+ dma_buf_fd = prime_handle_to_fd(fd1, handle2);
+ handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
+ check_bo(fd1, handle2, fd2, handle_import);
+
+ gem_close(fd1, handle2);
+ close(dma_buf_fd);
+
+ check_bo(fd2, handle_import, fd2, handle_import);
+
+ close(fd1);
+ close(fd2);
+}
+
+static void test_with_one_bo(void)
{
int fd1, fd2;
uint32_t handle, handle_import1, handle_import2, handle_selfimport;
@@ -118,6 +182,26 @@ int main(int argc, char **argv)
/* Completely rip out exporting fd. */
close(fd1);
check_bo(fd2, handle_import1, fd2, handle_import1);
+}
+
+int main(int argc, char **argv)
+{
+ struct {
+ const char *name;
+ void (*fn)(void);
+ } tests[] = {
+ { with_one_bo, test_with_one_bo },
+ { with_two_bos, test_with_two_bos },
+ { with_fd_dup, test_with_fd_dup },
+ };
+ int i;
+
+ drmtest_subtest_init(argc, argv);
+
+ for (i = 0; i ARRAY_SIZE(tests); i++) {
+ if (drmtest_run_subtest(tests[i].name))
+ tests[i].fn();
+ }
return 0;
}
--
1.7.10.4
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Re: [Intel-gfx] [PATCH 0/4] drm/edid: Recognize 60Hz and 59.94Hz CEA modes
2013/4/17 ville.syrj...@linux.intel.com: This series attempts to make our CEA mode matching recognize both the 60Hz and 59.94Hz variants of the modes (and similarly for 24/23.97, 30/29.97, etc.). The benefits should include: - Send the correct VIC in the AVI infoframe - Pick the correct RGB quantization range in automatic mode Everything looks correct, but I really didn't test anything. If you apply my comments from patch 2, then you have Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com for all the 4 patches. Optional bikeshedding: you could add a follow-up patch fixing the comments inside edid_cea_modes to reflect the correct Hz used, replacing, for example, AxB@60Hz with AxB@59.94Hz. But I can certainly live without this :) ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix bpc vs. bpp confusion in intel_crtc_compute_config
On Wed, 17 Apr 2013 20:01:39 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Oops.
This regression has been introduced in
commit 5d2d38ddcac991f71c19d03d95bde8e14abc0352
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Wed Mar 27 00:45:01 2013 +0100
drm/i915: clean up pipe bpp confusion
Reported-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 85acef5..47104e0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4006,9 +4006,9 @@ static int intel_crtc_compute_config(struct drm_crtc
*crtc,
adjusted_mode-hsync_start == adjusted_mode-hdisplay)
return -EINVAL;
- if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) pipe_config-pipe_bpp 10) {
+ if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) pipe_config-pipe_bpp
10*3) {
pipe_config-pipe_bpp = 10*3; /* 12bpc is gen5+ */
- } else if (INTEL_INFO(dev)-gen = 4 pipe_config-pipe_bpp 8) {
+ } else if (INTEL_INFO(dev)-gen = 4 pipe_config-pipe_bpp 8*3) {
/* only a 8bpc pipe, with 6bpc dither through the panel fitter
* for lvds. */
pipe_config-pipe_bpp = 8*3;
Yep, looks good. Thanks.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org (the first part is
t-b me too).
--
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Re: [Intel-gfx] [PATCH v2] tests/prime_self_import: add subtest to export/import a second gem buffer
On Wed, Apr 17, 2013 at 11:18:02PM +0300, Imre Deak wrote:
Also add a subtest for the fd=handle_to_fd(), fd2=dup(fd), close(fd)
case (idea from Kristian Høgsberg).
Signed-off-by: Imre Deak imre.d...@intel.com
v2:
- add a new subtest instead of modifying the original test (Daniel)
- add a new subtest for testing dup (Kristian)
Merged, thanks for the patch.
-Daniel
---
tests/Makefile.am |2 +-
tests/prime_self_import.c | 88
+++--
2 files changed, 87 insertions(+), 3 deletions(-)
diff --git a/tests/Makefile.am b/tests/Makefile.am
index e147e4e..d4e25a7 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -32,6 +32,7 @@ TESTS_progs_M = \
gem_tiled_partial_pwrite_pread \
$(NOUVEAU_TESTS_M) \
kms_flip \
+ prime_self_import \
$(NULL)
TESTS_progs = \
@@ -101,7 +102,6 @@ TESTS_progs = \
gem_reg_read \
gem_tiling_max_stride \
$(NOUVEAU_TESTS) \
- prime_self_import \
prime_udl \
$(NULL)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 111ed4d..abdc220 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_self_import.c
@@ -48,11 +48,14 @@
#define BO_SIZE (16*1024)
+#define ARRAY_SIZE(x)(sizeof(x) / sizeof((x)[0]))
+
+static char counter;
+
static void
check_bo(int fd1, uint32_t handle1, int fd2, uint32_t handle2)
{
char *ptr1, *ptr2;
- static char counter = 0;
int i;
ptr1 = gem_mmap(fd1, handle1, BO_SIZE, PROT_READ | PROT_WRITE);
@@ -75,7 +78,68 @@ check_bo(int fd1, uint32_t handle1, int fd2, uint32_t
handle2)
munmap(ptr2, BO_SIZE);
}
-int main(int argc, char **argv)
+static void test_with_fd_dup(void)
+{
+ int fd1, fd2;
+ uint32_t handle, handle_import;
+ int dma_buf_fd1, dma_buf_fd2;
+
+ counter = 0;
+
+ fd1 = drm_open_any();
+ fd2 = drm_open_any();
+
+ handle = gem_create(fd1, BO_SIZE);
+
+ dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
+ gem_close(fd1, handle);
+
+ dma_buf_fd2 = dup(dma_buf_fd1);
+ close(dma_buf_fd1);
+ handle_import = prime_fd_to_handle(fd2, dma_buf_fd2);
+ check_bo(fd2, handle_import, fd2, handle_import);
+
+ close(dma_buf_fd2);
+ check_bo(fd2, handle_import, fd2, handle_import);
+
+ close(fd1);
+ close(fd2);
+}
+
+static void test_with_two_bos(void)
+{
+ int fd1, fd2;
+ uint32_t handle1, handle2, handle_import;
+ int dma_buf_fd;
+
+ counter = 0;
+
+ fd1 = drm_open_any();
+ fd2 = drm_open_any();
+
+ handle1 = gem_create(fd1, BO_SIZE);
+ handle2 = gem_create(fd1, BO_SIZE);
+
+ dma_buf_fd = prime_handle_to_fd(fd1, handle1);
+ handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
+
+ close(dma_buf_fd);
+ gem_close(fd1, handle1);
+
+ dma_buf_fd = prime_handle_to_fd(fd1, handle2);
+ handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
+ check_bo(fd1, handle2, fd2, handle_import);
+
+ gem_close(fd1, handle2);
+ close(dma_buf_fd);
+
+ check_bo(fd2, handle_import, fd2, handle_import);
+
+ close(fd1);
+ close(fd2);
+}
+
+static void test_with_one_bo(void)
{
int fd1, fd2;
uint32_t handle, handle_import1, handle_import2, handle_selfimport;
@@ -118,6 +182,26 @@ int main(int argc, char **argv)
/* Completely rip out exporting fd. */
close(fd1);
check_bo(fd2, handle_import1, fd2, handle_import1);
+}
+
+int main(int argc, char **argv)
+{
+ struct {
+ const char *name;
+ void (*fn)(void);
+ } tests[] = {
+ { with_one_bo, test_with_one_bo },
+ { with_two_bos, test_with_two_bos },
+ { with_fd_dup, test_with_fd_dup },
+ };
+ int i;
+
+ drmtest_subtest_init(argc, argv);
+
+ for (i = 0; i ARRAY_SIZE(tests); i++) {
+ if (drmtest_run_subtest(tests[i].name))
+ tests[i].fn();
+ }
return 0;
}
--
1.7.10.4
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: fix bpc vs. bpp confusion in intel_crtc_compute_config
On Wed, Apr 17, 2013 at 01:40:56PM -0700, Jesse Barnes wrote:
On Wed, 17 Apr 2013 20:01:39 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Oops.
This regression has been introduced in
commit 5d2d38ddcac991f71c19d03d95bde8e14abc0352
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Wed Mar 27 00:45:01 2013 +0100
drm/i915: clean up pipe bpp confusion
Reported-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 85acef5..47104e0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4006,9 +4006,9 @@ static int intel_crtc_compute_config(struct drm_crtc
*crtc,
adjusted_mode-hsync_start == adjusted_mode-hdisplay)
return -EINVAL;
- if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) pipe_config-pipe_bpp 10) {
+ if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) pipe_config-pipe_bpp
10*3) {
pipe_config-pipe_bpp = 10*3; /* 12bpc is gen5+ */
- } else if (INTEL_INFO(dev)-gen = 4 pipe_config-pipe_bpp 8) {
+ } else if (INTEL_INFO(dev)-gen = 4 pipe_config-pipe_bpp 8*3) {
/* only a 8bpc pipe, with 6bpc dither through the panel fitter
* for lvds. */
pipe_config-pipe_bpp = 8*3;
Yep, looks good. Thanks.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org (the first part is
t-b me too).
Picked up for -fixes, thanks for the review.
-Daniel
--
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT
From: Paulo Zanoni paulo.r.zan...@intel.com This should prevent mode set failures on LPT. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_pm.c |5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 413877d..15ff0ac 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev) I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | PCH_LP_PARTITION_LEVEL_DISABLE); + + /* WADPOClockGatingDisable */ + I915_WRITE(_TRANSA_CHICKEN1, + I915_READ(_TRANSA_CHICKEN1) | + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); } static void haswell_init_clock_gating(struct drm_device *dev) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915: VLV GPU frequency to opcode functions
When requesting frequency changes or querying status from the Punit, we
need to use an opcode that corresponds to the frequency, taking into
account the memory frequency.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/intel_pm.c | 56 +++
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15d0a3a..abb0655 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1887,6 +1887,8 @@ int sandybridge_pcode_read(struct drm_i915_private
*dev_priv, u8 mbox, u32 *val)
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
val);
int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32
*val);
int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32
val);
+int vlv_gpu_freq(int ddr_freq, int val);
+int vlv_freq_opcode(int ddr_freq, int val);
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 413877d..f802368 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4620,3 +4620,59 @@ int valleyview_punit_write(struct drm_i915_private
*dev_priv, u8 addr, u32 val)
{
return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, val);
}
+
+int vlv_gpu_freq(int ddr_freq, int val)
+{
+ int mult, base;
+
+ switch (ddr_freq) {
+ case 800:
+ mult = 20;
+ base = 120;
+ break;
+ case 1066:
+ mult = 22;
+ base = 133;
+ break;
+ case 1333:
+ mult = 21;
+ base = 125;
+ break;
+ default:
+ return -1;
+ }
+
+ return ((val - 0xbd) * mult) + base;
+}
+
+int vlv_freq_opcode(int ddr_freq, int val)
+{
+ int mult, base;
+
+ switch (ddr_freq) {
+ case 800:
+ mult = 20;
+ base = 120;
+ break;
+ case 1066:
+ mult = 22;
+ base = 133;
+ break;
+ case 1333:
+ mult = 21;
+ base = 125;
+ break;
+ default:
+ return -1;
+ }
+
+ val /= mult;
+ val -= base / mult;
+ val += 0xbd;
+
+ if (val 0xea)
+ val = 0xea;
+
+ return val;
+}
+
--
1.7.10.4
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[Intel-gfx] [PATCH 2/5] drm/i915: turbo RC6 support for VLV v7
Uses slightly different interfaces than other platforms.
v2: track actual set freq, not requested (Rohit)
fix debug prints in init code (Jesse)
v3: don't write sleep reg (Jesse)
re-add RC6 wake limit write (Ben)
fixup thresholds to match other platforms (Ben)
clean up mem freq calculation (Ben)
clean up debug prints (Ben)
v4: move defines from punit patch (Ville)
v5: remove writes to nonexistent regs (Jesse)
put RP and RC regs together (Jesse)
fix RC6 enable (Jesse)
v6: use correct fuse reads from NC (Jesse)
split out min/max funcs for use in sysfs (Jesse)
add debugfs sysfs freq controls (Jesse)
v7: update with Ben's hw_max changes (Jesse)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Conflicts:
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_sysfs.c
---
drivers/gpu/drm/i915/i915_debugfs.c | 58 --
drivers/gpu/drm/i915/i915_drv.h |5 +
drivers/gpu/drm/i915/i915_irq.c |5 +-
drivers/gpu/drm/i915/i915_reg.h | 21
drivers/gpu/drm/i915/i915_sysfs.c | 71 +
drivers/gpu/drm/i915/intel_pm.c | 199 +--
6 files changed, 320 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e913d32..367b534 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -941,7 +941,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void
*unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, Current P-state: %d\n,
(rgvstat MEMSTAT_PSTATE_MASK)
MEMSTAT_PSTATE_SHIFT);
- } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
+ } else if ((IS_GEN6(dev) || IS_GEN7(dev)) !IS_VALLEYVIEW(dev)) {
u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1009,6 +1009,25 @@ static int i915_cur_delayinfo(struct seq_file *m, void
*unused)
seq_printf(m, Max overclocked frequency: %dMHz\n,
dev_priv-rps.hw_max * GT_FREQUENCY_MULTIPLIER);
+ } else if (IS_VALLEYVIEW(dev)) {
+ u32 freq_sts, val;
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,
+ freq_sts);
+ seq_printf(m, PUNIT_REG_GPU_FREQ_STS: 0x%08x\n, freq_sts);
+ seq_printf(m, DDR freq: %d MHz\n, dev_priv-mem_freq);
+
+ valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, val);
+ seq_printf(m, max GPU freq: %d MHz\n,
+ vlv_gpu_freq(dev_priv-mem_freq, val));
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, val);
+ seq_printf(m, min GPU freq: %d MHz\n,
+ vlv_gpu_freq(dev_priv-mem_freq, val));
+
+ seq_printf(m, current GPU freq: %d MHz\n,
+ vlv_gpu_freq(dev_priv-mem_freq,
+ (freq_sts 8) 0xff));
} else {
seq_printf(m, no P-state info available\n);
}
@@ -1812,7 +1831,11 @@ i915_max_freq_get(void *data, u64 *val)
if (ret)
return ret;
- *val = dev_priv-rps.max_delay * GT_FREQUENCY_MULTIPLIER;
+ if (IS_VALLEYVIEW(dev))
+ *val = vlv_gpu_freq(dev_priv-mem_freq,
+ dev_priv-rps.max_delay);
+ else
+ *val = dev_priv-rps.max_delay * GT_FREQUENCY_MULTIPLIER;
mutex_unlock(dev_priv-rps.hw_lock);
return 0;
@@ -1837,9 +1860,16 @@ i915_max_freq_set(void *data, u64 val)
/*
* Turbo will still be enabled, but won't go above the set value.
*/
- do_div(val, GT_FREQUENCY_MULTIPLIER);
- dev_priv-rps.max_delay = val;
- gen6_set_rps(dev, val);
+ if (IS_VALLEYVIEW(dev)) {
+ val = vlv_freq_opcode(dev_priv-mem_freq, val);
+ dev_priv-rps.max_delay = val;
+ gen6_set_rps(dev, val);
+ } else {
+ do_div(val, GT_FREQUENCY_MULTIPLIER);
+ dev_priv-rps.max_delay = val;
+ gen6_set_rps(dev, val);
+ }
+
mutex_unlock(dev_priv-rps.hw_lock);
return 0;
@@ -1863,7 +1893,11 @@ i915_min_freq_get(void *data, u64 *val)
if (ret)
return ret;
- *val = dev_priv-rps.min_delay * GT_FREQUENCY_MULTIPLIER;
+ if (IS_VALLEYVIEW(dev))
+ *val = vlv_gpu_freq(dev_priv-mem_freq,
+ dev_priv-rps.min_delay);
+ else
+ *val = dev_priv-rps.min_delay * GT_FREQUENCY_MULTIPLIER;
mutex_unlock(dev_priv-rps.hw_lock);
return 0;
@@ -1888,9 +1922,15 @@ i915_min_freq_set(void *data, u64 val)
/*
* Turbo will
[Intel-gfx] [PATCH 3/5] drm/i915/dp: program VSwing and Preemphasis control settings on VLV
From: Pallavi G pallav...@intel.com
Program few Tx buffer Swing control settings through DPIO.
Signed-off-by: Pallavi G pallav...@intel.com
Signed-off-by: Yogesh M yogesh.mohan.marimu...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |3 +-
drivers/gpu/drm/i915/intel_dp.c | 114 +-
drivers/gpu/drm/i915/intel_drv.h |2 +
3 files changed, 115 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8872f71..28b8fac 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -450,8 +450,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv, int
reg)
return I915_READ(DPIO_DATA);
}
-static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
-u32 val)
+void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
{
WARN_ON(!mutex_is_locked(dev_priv-dpio_lock));
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 89f89b7..2e800f5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1461,7 +1461,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
- if (IS_GEN7(dev) is_cpu_edp(intel_dp))
+ if (IS_VALLEYVIEW(dev))
+ return DP_TRAIN_VOLTAGE_SWING_1200;
+ else if (IS_GEN7(dev) is_cpu_edp(intel_dp))
return DP_TRAIN_VOLTAGE_SWING_800;
else if (HAS_PCH_CPT(dev) !is_cpu_edp(intel_dp))
return DP_TRAIN_VOLTAGE_SWING_1200;
@@ -1486,7 +1488,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPHASIS_0;
}
- } else if (IS_GEN7(dev) is_cpu_edp(intel_dp) !IS_VALLEYVIEW(dev))
{
+ } else if (IS_VALLEYVIEW(dev)) {
+ switch (voltage_swing DP_TRAIN_VOLTAGE_SWING_MASK) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ return DP_TRAIN_PRE_EMPHASIS_9_5;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ return DP_TRAIN_PRE_EMPHASIS_6;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ return DP_TRAIN_PRE_EMPHASIS_3_5;
+ case DP_TRAIN_VOLTAGE_SWING_1200:
+ default:
+ return DP_TRAIN_PRE_EMPHASIS_0;
+ }
+ } else if (IS_GEN7(dev) is_cpu_edp(intel_dp)) {
switch (voltage_swing DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1511,15 +1525,111 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
uint8_t voltage_swing)
}
}
+static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
+ uint8_t p)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long Demph_reg_value, Preemph_reg_value,
+ Uniqtranscale_reg_value;
+ switch (p) {
+ case DP_TRAIN_PRE_EMPHASIS_0:
+ Preemph_reg_value = 0x0004000;
+ switch (v) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ Demph_reg_value = 0x2B40;
+ Uniqtranscale_reg_value = 0x552AB83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ Demph_reg_value = 0x2B404040;
+ Uniqtranscale_reg_value = 0x5548B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ Demph_reg_value = 0x2B24;
+ Uniqtranscale_reg_value = 0x5560B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_1200:
+ Demph_reg_value = 0x2B40;
+ Uniqtranscale_reg_value = 0x5598DA3A;
+ break;
+ default:
+ return;
+ }
+ break;
+ case DP_TRAIN_PRE_EMPHASIS_3_5:
+ Preemph_reg_value = 0x0002000;
+ switch (v) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ Demph_reg_value = 0x2B404040;
+ Uniqtranscale_reg_value = 0x5552B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ Demph_reg_value = 0x2B404848;
+ Uniqtranscale_reg_value = 0x5580B83A;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ Demph_reg_value = 0x2B404040;
+ Uniqtranscale_reg_value = 0x55ADDA3A;
+
[Intel-gfx] [PATCH 5/5] drm/i915: update VLV PLL and DPIO code v10
In Valleyview voltage swing, pre-emphasis and lane control registers can be programmed only through the h/w side band fabric. Update vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the appropriate programming. We need to make sure that the tx lane reset occurs in both the full mode set and DPMS paths, so factor things out to allow that. v2: use different DPIO_DIVISOR values for VGA and DisplayPort v3: Fix update pll logic to use same DPIO_DIVISOR DPIO_REFSFR values for all display interfaces v4: collapse with various updates v5: squash with crtc enable/pll enable bits v6: split out DP code (jbarnes) put phyready check under IS_VALLEYVIEW (jbarnes) remove unneeded check in 9xx pll div update (Jani) wrap VLV pll update call in IS_VALLEYVIEW (Jani) move port enable back to end of crtc enable (jbarnes) put phyready check under IS_VALLEYVIEW (jbarnes) v7: fix up conflicts against latest drm-intel-next-queued v8: use DPIO reg names, fix pipes (Jani) from mPhy_registers_VLV2_ww20p5 doc v9: update to latest info from driver enabling notes doc driver_vbios_notes_9 v10: fixup a bit of pipe/port confusion to allow eDP and HDMI to work simultaneously (Jesse) Signed-off-by: Pallavi G pallav...@intel.com Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com Signed-off-by: Gajanan Bhat gajanan.b...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Conflicts: drivers/gpu/drm/i915/intel_display.c --- drivers/gpu/drm/i915/i915_reg.h | 118 +++- drivers/gpu/drm/i915/intel_display.c | 351 +++--- 2 files changed, 399 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 66fb8dd..fb1a4fa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -353,6 +353,8 @@ * 0x8100: fast clock controls * * DPIO is VLV only. + * + * Note: digital port B is DDI0, digital pot C is DDI1 */ #define DPIO_PKT (VLV_DISPLAY_BASE + 0x2100) #define DPIO_RID (024) @@ -369,8 +371,20 @@ #define DPIO_SFR_BYPASS (11) #define DPIO_RESET(10) +#define _DPIO_TX3_SWING_CTL4_A 0x690 +#define _DPIO_TX3_SWING_CTL4_B 0x2a90 +#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \ + _DPIO_TX3_SWING_CTL4_B) + +/* + * Per pipe/PLL DPIO regs + */ #define _DPIO_DIV_A0x800c #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ +#define DPIO_POST_DIV_DAC0 +#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ +#define DPIO_POST_DIV_LVDS1 2 +#define DPIO_POST_DIV_LVDS2 3 #define DPIO_K_SHIFT (24) /* 4 bits */ #define DPIO_P1_SHIFT(21) /* 3 bits */ #define DPIO_P2_SHIFT(16) /* 5 bits */ @@ -396,14 +410,111 @@ #define _DPIO_CORE_CLK_B 0x803c #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) +#define _DPIO_IREF_CTL_A 0x8040 +#define _DPIO_IREF_CTL_B 0x8060 +#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B) + +#define DPIO_IREF_BCAST0xc044 +#define _DPIO_IREF_A 0x8044 +#define _DPIO_IREF_B 0x8064 +#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B) + +#define _DPIO_PLL_CML_A0x804c +#define _DPIO_PLL_CML_B0x806c +#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) + #define _DPIO_LFP_COEFF_A 0x8048 #define _DPIO_LFP_COEFF_B 0x8068 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) +#define DPIO_CALIBRATION 0x80ac + #define DPIO_FASTCLK_DISABLE 0x8100 -#define DPIO_DATA_CHANNEL1 0x8220 -#define DPIO_DATA_CHANNEL2 0x8420 +/* + * Per DDI channel DPIO regs + */ + +#define _DPIO_PCS_TX_0 0x8200 +#define _DPIO_PCS_TX_1 0x8400 +#define DPIO_PCS_TX_LANE2_RESET (116) +#define DPIO_PCS_TX_LANE1_RESET (17) +#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1) + +#define _DPIO_PCS_CLK_00x8204 +#define _DPIO_PCS_CLK_10x8404 +#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN(122) +#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (121) +#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) +#define DPIO_PCS_CLK_SOFT_RESET (15) +#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1) + +#define _DPIO_PCS_CTL_OVR1_A 0x8224 +#define _DPIO_PCS_CTL_OVR1_B 0x8424 +#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \ +
[Intel-gfx] Rebase v42 of the outstanding VLV patches
Just 5 more to go! Daniel, please apply these or I'll be forced to fly to Europe and hunt you down. I know 3 and 4 have some coding style issues, but either fix those up when you apply or let me do that after they're applied as I need to get my patch count up and don't want to rebase yet again!!! Thanks, Jesse ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915: fix VLV limits and m/n/p calculations v2
From: Pallavi G pallav...@intel.com
For high res modes m n p calculation is fixed for VLV platform.
v2: use 64 bit types and math (Ville)
Signed-off-by: Pallavi G pallav...@intel.com
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Yogesh M yogesh.mohan.marimu...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 28b8fac..f3aa24f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -31,6 +31,7 @@
#include linux/kernel.h
#include linux/slab.h
#include linux/vgaarb.h
+#include linux/math64.h
#include drm/drm_edid.h
#include drm/drmP.h
#include intel_drv.h
@@ -396,21 +397,21 @@ static const intel_limit_t intel_limits_vlv_dac = {
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
- .p1 = { .min = 2, .max = 3 },
+ .p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 27,
.p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
};
static const intel_limit_t intel_limits_vlv_hdmi = {
- .dot = { .min = 2, .max = 165000 },
- .vco = { .min = 400, .max = 5994000},
- .n = { .min = 1, .max = 7 },
+ .dot = { .min = 25000, .max = 18 },
+ .vco = { .min = 404, .max = 596 },
+ .n = { .min = 1, .max = 5 },
.m = { .min = 60, .max = 300 }, /* guess */
.m1 = { .min = 2, .max = 3 },
- .m2 = { .min = 11, .max = 156 },
+ .m2 = { .min = 15, .max = 149 },
.p = { .min = 10, .max = 30 },
- .p1 = { .min = 2, .max = 3 },
+ .p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 27,
.p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
@@ -424,7 +425,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
- .p1 = { .min = 2, .max = 3 },
+ .p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 27,
.p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
@@ -821,10 +822,13 @@ intel_vlv_find_best_pll(const intel_limit_t *limit,
struct drm_crtc *crtc,
int target, int refclk, intel_clock_t *match_clock,
intel_clock_t *best_clock)
{
+#define LONG_OVERFLOW 0x7FFF
+#define DIFF_OVERFLOW (LONG_OVERFLOW/1)
+
u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
u32 m, n, fastclk;
u32 updrate, minupdate, fracbits, p;
- unsigned long bestppm, ppm, absppm;
+ s64 bestppm, ppm, absppm, ppmdiff;
int dotclk, flag;
flag = 0;
@@ -853,8 +857,9 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct
drm_crtc *crtc,
m = m1 * m2;
vco = updrate * m;
if (vco = limit-vco.min vco
limit-vco.max) {
- ppm = 100 * ((vco / p) -
fastclk) / fastclk;
- absppm = (ppm 0) ? ppm :
(-ppm);
+ ppmdiff = div_s64((100*vco), p)
- (100*fastclk);
+ absppm =
div_s64((abs64(ppmdiff)*1), fastclk);
+
if (absppm 100 ((p1 * p2)
(bestp1 * bestp2))) {
bestppm = 0;
flag = 1;
--
1.7.10.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] [RFC] drm/i915: Scratch page checker
Periodically check the scratch page to see if it changes. Scratch page
changes almost always indicate something is wrong.
We never expect a non-zero filled page, so potentially we could directly
put that md5 value for checking. I think the code as it is will be a bit
more robust.
Pretty RFC here since I've only compiled and run it for a few seconds.
Recommended-by: Stephane Marchesin marc...@chromium.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/i915/i915_drv.c | 5 +++
drivers/gpu/drm/i915/i915_drv.h | 14 +++
drivers/gpu/drm/i915/i915_gem_gtt.c | 73 +
4 files changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 19b8e0d..44efe74 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -125,6 +125,8 @@ config DRM_I915
depends on DRM
depends on AGP
depends on AGP_INTEL
+ select CRYPTO
+ select CRYPTO_MD5
# we need shmfs for the swappable backing store, and in particular
# the shmem_readpage() which depends upon tmpfs
select SHMEM
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895..a1f6142 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -128,6 +128,11 @@ module_param_named(disable_power_well,
i915_disable_power_well, int, 0600);
MODULE_PARM_DESC(disable_power_well,
Disable the power well when possible (default: false));
+int i915_enable_scratch_checker __read_mostly = 0;
+module_param_named(enable_scratch_checker, i915_enable_scratch_checker, int,
0600);
+MODULE_PARM_DESC(enable_scratch_checker,
+Enable periodic timer to find stray writes to the scratch
page (default: false));
+
static struct drm_driver driver;
extern int intel_agp_enabled;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5dcf7f..c1f4ef7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -43,6 +43,8 @@
#include linux/intel-iommu.h
#include linux/kref.h
#include linux/pm_qos.h
+#include linux/crypto.h
+#include crypto/md5.h
/* General customization:
*/
@@ -869,6 +871,16 @@ struct i915_gpu_error {
unsigned int stop_rings;
};
+struct i915_scratch_checker {
+ struct scatterlist sg; /* sg for scratch page */
+ struct hash_desc hash;
+ char last_hash[MD5_DIGEST_SIZE];
+
+#define I915_SCRATCH_DIRT_PERIOD 1000 /* in ms */
+#define I915_SCRATCH_DIRT_JIFFIES msecs_to_jiffies(I915_SCRATCH_DIRT_PERIOD)
+ struct timer_list timer;
+};
+
enum modeset_restore {
MODESET_ON_LID_OPEN,
MODESET_DONE,
@@ -1058,6 +1070,7 @@ typedef struct drm_i915_private {
struct drm_mm_node *compressed_llb;
struct i915_gpu_error gpu_error;
+ struct i915_scratch_checker scratch_checker;
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
@@ -1435,6 +1448,7 @@ extern bool i915_enable_hangcheck __read_mostly;
extern int i915_enable_ppgtt __read_mostly;
extern unsigned int i915_preliminary_hw_support __read_mostly;
extern int i915_disable_power_well __read_mostly;
+extern int i915_enable_scratch_checker __read_mostly;
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 50df194..df7a3a8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -660,6 +660,72 @@ void i915_gem_init_global_gtt(struct drm_device *dev)
i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
}
+static void scratch_checker(unsigned long data)
+{
+ struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
+ char hash[MD5_DIGEST_SIZE];
+ int ret;
+
+ ret = crypto_hash_digest(dev_priv-scratch_checker.hash,
+dev_priv-scratch_checker.sg, PAGE_SIZE,
+hash);
+ if (ret) {
+ DRM_DEBUG_DRIVER(Couldn't hash scratch\n);
+ goto out;
+ }
+
+ if (!memcmp(hash, dev_priv-scratch_checker.last_hash, MD5_DIGEST_SIZE))
+ goto out;
+
+ DRM_DEBUG(Scratch page contents changed\n);
+ memcpy(dev_priv-scratch_checker.last_hash, hash, MD5_DIGEST_SIZE);
+
+out:
+ mod_timer(dev_priv-scratch_checker.timer,
+ round_jiffies_up(jiffies + I915_SCRATCH_DIRT_JIFFIES));
+}
+
+static void scratch_checker_init(struct drm_i915_private *dev_priv)
+{
+ int ret;
+
+ sg_init_table(dev_priv-scratch_checker.sg, 1);
+ sg_set_page(dev_priv-scratch_checker.sg, dev_priv-gtt.scratch_page,
+ 4096, 0);
+
+ dev_priv-scratch_checker.hash.tfm = crypto_alloc_hash(md5, 0,
+
Re: [Intel-gfx] 回复： [ASK] How can I set the X to select the DRI driveri965
On Wed, Apr 17, 2013 at 12:43 AM, 熊 546496...@qq.com wrote: Yah, you mean the DRI driver i965 does not support my device 945GM ? but according to https://01.org/linuxgraphics/downloads/2012/2012q4-intel-graphics-stack-release, it should support my device. No, that means that they also test the i915 driver (which supports your i945). ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
