Re: [Intel-gfx] [PATCH 1/7] drm/i915: remove SDV support from lpt_pch_init_refclk

[Ben Widawsky]

On Fri, Jul 12, 2013 at 02:19:36PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni 
> 
> The machines that fall in the "is_sdv" case are some very early
> pre-production steppings. This patch may break VGA output after
> suspend/resume on these machines.
> 
> Even the documentation for the is_sdv cases was removed from BSpec.
> 
> Signed-off-by: Paulo Zanoni 

Was hoping to get through the first 3 before I got too tired, but I
didn't make it. This one is:
Reviewed-by: Ben Widawsky 

Will try to finish up some more this weekend.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 104 
> ---
>  1 file changed, 34 insertions(+), 70 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index c79addd..5821ffc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5170,7 +5170,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
>   struct drm_mode_config *mode_config = &dev->mode_config;
>   struct intel_encoder *encoder;
>   bool has_vga = false;
> - bool is_sdv = false;
>   u32 tmp;
>  
>   list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
> @@ -5186,10 +5185,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
>  
>   mutex_lock(&dev_priv->dpio_lock);
>  
> - /* XXX: Rip out SDV support once Haswell ships for real. */
> - if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
> - is_sdv = true;
> -
>   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
>   tmp &= ~SBI_SSCCTL_DISABLE;
>   tmp |= SBI_SSCCTL_PATHALT;
> @@ -5201,36 +5196,27 @@ static void lpt_init_pch_refclk(struct drm_device 
> *dev)
>   tmp &= ~SBI_SSCCTL_PATHALT;
>   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
>  
> - if (!is_sdv) {
> - tmp = I915_READ(SOUTH_CHICKEN2);
> - tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> - I915_WRITE(SOUTH_CHICKEN2, tmp);
> + tmp = I915_READ(SOUTH_CHICKEN2);
> + tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> + I915_WRITE(SOUTH_CHICKEN2, tmp);
>  
> - if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
> -FDI_MPHY_IOSFSB_RESET_STATUS, 100))
> - DRM_ERROR("FDI mPHY reset assert timeout\n");
> + if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
> +FDI_MPHY_IOSFSB_RESET_STATUS, 100))
> + DRM_ERROR("FDI mPHY reset assert timeout\n");
>  
> - tmp = I915_READ(SOUTH_CHICKEN2);
> - tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> - I915_WRITE(SOUTH_CHICKEN2, tmp);
> + tmp = I915_READ(SOUTH_CHICKEN2);
> + tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> + I915_WRITE(SOUTH_CHICKEN2, tmp);
>  
> - if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
> - FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
> -100))
> - DRM_ERROR("FDI mPHY reset de-assert timeout\n");
> - }
> + if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
> + FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
> + DRM_ERROR("FDI mPHY reset de-assert timeout\n");
>  
>   tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
>   tmp &= ~(0xFF << 24);
>   tmp |= (0x12 << 24);
>   intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
>  
> - if (is_sdv) {
> - tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
> - tmp |= 0x7FFF;
> - intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
> - }
> -
>   tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
>   tmp |= (1 << 11);
>   intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
> @@ -5239,24 +5225,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
>   tmp |= (1 << 11);
>   intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
>  
> - if (is_sdv) {
> - tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
> - tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
> - intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
> - tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
> - intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
> - tmp |= (0x3F << 8);
> - intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
> -
> - tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
> - tmp |= (0x3F << 8);
> - intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
> - }
> -
>   tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
>   tmp |= (1 << 24) | (1 << 21) | (1 << 18);
>   intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
> @@ -5265,17 +5233,15 @@ static void lpt_init_

[Intel-gfx] [PATCH 1/3] drm/i915: Add bind/unbind object functions to VM

[Ben Widawsky]

As we plumb the code with more VM information, it has become more
obvious that the easiest way to deal with bind and unbind is to simply
put the function pointers in the vm, and let those choose the correct
way to handle the page table updates. This change allows many places in
the code to simply be vm->bind, and not have to worry about
distinguishing PPGTT vs GGTT.

NOTE: At some point in the future, brining back insert_entries may in
fact be desirable in order to use 1 bind/unbind for multiple generations
of PPGTT. For now however, it's just not necessary.

Signed-off-by: Ben Widawsky 
---
 drivers/gpu/drm/i915/i915_drv.h |  9 +
 drivers/gpu/drm/i915/i915_gem_gtt.c | 72 +
 2 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e6694ae..c2a9c98 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -484,9 +484,18 @@ struct i915_address_space {
/* FIXME: Need a more generic return type */
gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
 enum i915_cache_level level);
+
+   /** Unmap an object from an address space. This usually consists of
+* setting the valid PTE entries to a reserved scratch page. */
+   void (*unbind_object)(struct i915_address_space *vm,
+ struct drm_i915_gem_object *obj);
void (*clear_range)(struct i915_address_space *vm,
unsigned int first_entry,
unsigned int num_entries);
+   /* Map an object into an address space with the given cache flags. */
+   void (*bind_object)(struct i915_address_space *vm,
+   struct drm_i915_gem_object *obj,
+   enum i915_cache_level cache_level);
void (*insert_entries)(struct i915_address_space *vm,
   struct sg_table *st,
   unsigned int first_entry,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c0d0223..31ff971 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -45,6 +45,12 @@
 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
 
+static void gen6_ppgtt_bind_object(struct i915_address_space *vm,
+  struct drm_i915_gem_object *obj,
+  enum i915_cache_level cache_level);
+static void gen6_ppgtt_unbind_object(struct i915_address_space *vm,
+struct drm_i915_gem_object *obj);
+
 static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,
  enum i915_cache_level level)
 {
@@ -285,7 +291,9 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
}
ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
ppgtt->enable = gen6_ppgtt_enable;
+   ppgtt->base.unbind_object = gen6_ppgtt_unbind_object;
ppgtt->base.clear_range = gen6_ppgtt_clear_range;
+   ppgtt->base.bind_object = gen6_ppgtt_bind_object;
ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.scratch = dev_priv->gtt.base.scratch;
@@ -397,6 +405,17 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
   cache_level);
 }
 
+static void gen6_ppgtt_bind_object(struct i915_address_space *vm,
+  struct drm_i915_gem_object *obj,
+  enum i915_cache_level cache_level)
+{
+   const unsigned long entry = i915_gem_obj_offset(obj, vm);
+
+   gen6_ppgtt_insert_entries(vm, obj->pages, entry >> PAGE_SHIFT,
+ cache_level);
+   obj->has_aliasing_ppgtt_mapping = 1;
+}
+
 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
  struct drm_i915_gem_object *obj)
 {
@@ -407,6 +426,16 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
obj->base.size >> PAGE_SHIFT);
 }
 
+static void gen6_ppgtt_unbind_object(struct i915_address_space *vm,
+struct drm_i915_gem_object *obj)
+{
+   const unsigned long entry = i915_gem_obj_offset(obj, vm);
+
+   gen6_ppgtt_clear_range(vm, entry >> PAGE_SHIFT,
+  obj->base.size >> PAGE_SHIFT);
+   obj->has_aliasing_ppgtt_mapping = 0;
+}
+
 extern int intel_iommu_gfx_mapped;
 /* Certain Gen5 chipsets require require idling the GPU before
  * unmapping anything from the GTT when VT-d is enabled.
@@ -555,6 +584,18 @@ static void i915_ggtt_insert_entries(struct 
i915_address_space *vm,
 
 }
 
+static void i915_ggtt_bind_object(struct i915_address_space *vm,
+ struct drm_i915_gem_object *obj,
+   

[Intel-gfx] [PATCH 12/15] [RFC] create vm->bind,unbind

[Ben Widawsky]

In response to some of Daniel's requests on patch 6, I tried to clean up some
of our code via bind/unbind. I haven't done terribly thorough testing so far -
but basic tests are passing on IVB, and the code is a lot cleaner IMO. This
could be squashed in to patch 6, but I would prefer to leave it as this small
series on top of the bunch.

I have tried a lesser version of this before in my earlier gtt/agp cleanups.
Daniel rejected it then in favor of his own version. I am trying again because
I think the latest PPGTT work provide an even greater case for it.

References:
http://lists.freedesktop.org/archives/intel-gfx/2013-January/023920.html

Ben Widawsky (3):
  drm/i915: Add bind/unbind object functions to VM
  drm/i915: Use the new vm [un]bind functions
  drm/i915: eliminate vm->insert_entries()

 drivers/gpu/drm/i915/i915_drv.h|  23 +++---
 drivers/gpu/drm/i915/i915_gem.c|  36 +-
 drivers/gpu/drm/i915/i915_gem_context.c|   6 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  19 ++---
 drivers/gpu/drm/i915/i915_gem_gtt.c| 109 ++---
 5 files changed, 109 insertions(+), 84 deletions(-)

-- 
1.8.3.2

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[Intel-gfx] [PATCH 3/3] drm/i915: eliminate vm->insert_entries()

[Ben Widawsky]

With bind/unbind function pointers in place, we no longer need
insert_entries. We could, and want, to remove clear_range, however it's
not totally easy at this point. Since it's used in a couple of place
still that don't only deal in objects: setup, ppgtt init, and restore
gtt mappings.

Signed-off-by: Ben Widawsky 
---
 drivers/gpu/drm/i915/i915_drv.h |  4 
 drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ---
 2 files changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8f9569b..eb13399 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -496,10 +496,6 @@ struct i915_address_space {
void (*bind_object)(struct i915_address_space *vm,
struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
-   void (*insert_entries)(struct i915_address_space *vm,
-  struct sg_table *st,
-  unsigned int first_entry,
-  enum i915_cache_level cache_level);
void (*cleanup)(struct i915_address_space *vm);
 };
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 31bffb9..dd3d5e5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -294,7 +294,6 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.unbind_object = gen6_ppgtt_unbind_object;
ppgtt->base.clear_range = gen6_ppgtt_clear_range;
ppgtt->base.bind_object = gen6_ppgtt_bind_object;
-   ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.scratch = dev_priv->gtt.base.scratch;
ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
@@ -551,18 +550,6 @@ static void gen6_ggtt_clear_range(struct 
i915_address_space *vm,
 }
 
 
-static void i915_ggtt_insert_entries(struct i915_address_space *vm,
-struct sg_table *st,
-unsigned int pg_start,
-enum i915_cache_level cache_level)
-{
-   unsigned int flags = (cache_level == I915_CACHE_NONE) ?
-   AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
-
-   intel_gtt_insert_sg_entries(st, pg_start, flags);
-
-}
-
 static void i915_ggtt_bind_object(struct i915_address_space *vm,
  struct drm_i915_gem_object *obj,
  enum i915_cache_level cache_level)
@@ -864,7 +851,6 @@ static int gen6_gmch_probe(struct drm_device *dev,
 
dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
dev_priv->gtt.base.unbind_object = gen6_ggtt_unbind_object;
-   dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
dev_priv->gtt.base.bind_object = gen6_ggtt_bind_object;
 
return ret;
@@ -898,7 +884,6 @@ static int i915_gmch_probe(struct drm_device *dev,
dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
dev_priv->gtt.base.unbind_object = i915_ggtt_unbind_object;
-   dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
dev_priv->gtt.base.bind_object = i915_ggtt_bind_object;
 
return 0;
-- 
1.8.3.2

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[Intel-gfx] [PATCH 2/3] drm/i915: Use the new vm [un]bind functions

[Ben Widawsky]

Building on the last patch which created the new function pointers in
the VM for bind/unbind, here we actually put those new function pointers
to use.

Split out as a separate patch to aid in review. I'm fine with squashing
into the previous patch if people request it.

Signed-off-by: Ben Widawsky 
---
 drivers/gpu/drm/i915/i915_drv.h| 10 -
 drivers/gpu/drm/i915/i915_gem.c| 36 +++
 drivers/gpu/drm/i915/i915_gem_context.c|  6 ++-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 19 
 drivers/gpu/drm/i915/i915_gem_gtt.c| 70 +-
 5 files changed, 52 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c2a9c98..8f9569b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1923,18 +1923,8 @@ int i915_gem_context_destroy_ioctl(struct drm_device 
*dev, void *data,
 
 /* i915_gem_gtt.c */
 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
-void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
-   struct drm_i915_gem_object *obj,
-   enum i915_cache_level cache_level);
-void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
- struct drm_i915_gem_object *obj);
-
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
-/* FIXME: this is never okay with full PPGTT */
-void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
-   enum i915_cache_level cache_level);
-void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
 void i915_gem_init_global_gtt(struct drm_device *dev);
 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 90d49fb..8e7a12d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2655,12 +2655,9 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj,
 
trace_i915_gem_object_unbind(obj, vm);
 
-   if (obj->has_global_gtt_mapping && i915_is_ggtt(vm))
-   i915_gem_gtt_unbind_object(obj);
-   if (obj->has_aliasing_ppgtt_mapping) {
-   i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
-   obj->has_aliasing_ppgtt_mapping = 0;
-   }
+
+   vm->unbind_object(vm, obj);
+
i915_gem_gtt_finish_object(obj);
i915_gem_object_unpin_pages(obj);
 
@@ -3393,7 +3390,6 @@ int i915_gem_object_set_cache_level(struct 
drm_i915_gem_object *obj,
enum i915_cache_level cache_level)
 {
struct drm_device *dev = obj->base.dev;
-   drm_i915_private_t *dev_priv = dev->dev_private;
struct i915_vma *vma = i915_gem_obj_to_vma(obj, vm);
int ret;
 
@@ -3428,13 +3424,8 @@ int i915_gem_object_set_cache_level(struct 
drm_i915_gem_object *obj,
return ret;
}
 
-   if (obj->has_global_gtt_mapping)
-   i915_gem_gtt_bind_object(obj, cache_level);
-   if (obj->has_aliasing_ppgtt_mapping)
-   i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
-  obj, cache_level);
-
-   i915_gem_obj_set_color(obj, vma->vm, cache_level);
+   vm->bind_object(vm, obj, cache_level);
+   i915_gem_obj_set_color(obj, vm, cache_level);
}
 
if (cache_level == I915_CACHE_NONE) {
@@ -3716,6 +3707,7 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
bool map_and_fenceable,
bool nonblocking)
 {
+   struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
int ret;
 
if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
@@ -3741,20 +3733,24 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
}
 
if (!i915_gem_obj_bound(obj, vm)) {
-   struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
-
ret = i915_gem_object_bind_to_gtt(obj, vm, alignment,
  map_and_fenceable,
  nonblocking);
if (ret)
return ret;
 
-   if (!dev_priv->mm.aliasing_ppgtt)
-   i915_gem_gtt_bind_object(obj, obj->cache_level);
+   if (!dev_priv->mm.aliasing_ppgtt) {
+   dev_priv->gtt.base.bind_object(&dev_priv->gtt.base,
+  obj,
+  obj->cache_level);
+   }
}
 
-   if (!obj->has_global_gtt_mapping && m

[Intel-gfx] [Update][PATCH] ACPI / video / i915: Remove ACPI backlight if firmware expects Windows 8

[Rafael J. Wysocki]

From: Rafael J. Wysocki 

According to Matthew Garrett, "Windows 8 leaves backlight control up
to individual graphics drivers rather than making ACPI calls itself.
There's plenty of evidence to suggest that the Intel driver for
Windows [8] doesn't use the ACPI interface, including the fact that
it's broken on a bunch of machines when the OS claims to support
Windows 8.  The simplest thing to do appears to be to disable the
ACPI backlight interface on these systems".

There's a problem with that approach, however, because simply
avoiding to register the ACPI backlight interface if the firmware
calls _OSI for Windows 8 may not work in the following situations:
 (1) The ACPI backlight interface actually works on the given system
 and the i915 driver is not loaded (e.g. another graphics driver
 is used).
 (2) The ACPI backlight interface doesn't work on the given system,
 but there is a vendor platform driver that will register its
 own, equally broken, backlight interface if not prevented from
 doing so by the ACPI subsystem.
Therefore we need to allow the ACPI backlight interface to be
registered until the i915 driver is loaded which then will unregister
it if the firmware has called _OSI for Windows 8 (or will register
the ACPI video driver without backlight support if not already
present).

For this reason, introduce an alternative function for registering
ACPI video, acpi_video_register_with_quirks(), that will check
whether or not the ACPI video driver has already been registered
and whether or not the backlight Windows 8 quirk has to be applied.
If the quirk has to be applied, it will block the ACPI backlight
support and either unregister the backlight interface if the ACPI
video driver has already been registered, or register the ACPI
video driver without the backlight interface otherwise.  Make
the i915 driver use acpi_video_register_with_quirks() instead of
acpi_video_register() in i915_driver_load().

This change is based on earlier patches from Matthew Garrett,
Chun-Yi Lee and Seth Forshee and Aaron Lu's comments.

Signed-off-by: Rafael J. Wysocki 
---
 drivers/acpi/internal.h |   11 ++
 drivers/acpi/video.c|   65 
 drivers/acpi/video_detect.c |   21 
 drivers/gpu/drm/i915/i915_dma.c |2 -
 include/acpi/video.h|   11 ++
 include/linux/acpi.h|1 
 6 files changed, 103 insertions(+), 8 deletions(-)

Index: linux-pm/drivers/acpi/video.c
===
--- linux-pm.orig/drivers/acpi/video.c
+++ linux-pm/drivers/acpi/video.c
@@ -44,6 +44,8 @@
 #include 
 #include 
 
+#include "internal.h"
+
 #define PREFIX "ACPI: "
 
 #define ACPI_VIDEO_BUS_NAME"Video Bus"
@@ -898,7 +900,7 @@ static void acpi_video_device_find_cap(s
device->cap._DDC = 1;
}
 
-   if (acpi_video_backlight_support()) {
+   if (acpi_video_verify_backlight_support()) {
struct backlight_properties props;
struct pci_dev *pdev;
acpi_handle acpi_parent;
@@ -1854,6 +1856,46 @@ static int acpi_video_bus_remove(struct
return 0;
 }
 
+static acpi_status video_unregister_backlight(acpi_handle handle, u32 lvl,
+ void *context, void **rv)
+{
+   struct acpi_device *acpi_dev;
+   struct acpi_video_bus *video;
+   struct acpi_video_device *dev, *next;
+
+   if (acpi_bus_get_device(handle, &acpi_dev))
+   return AE_OK;
+
+   if (acpi_match_device_ids(acpi_dev, video_device_ids))
+   return AE_OK;
+
+   video = acpi_driver_data(acpi_dev);
+   if (!video)
+   return AE_OK;
+
+   acpi_video_bus_stop_devices(video);
+   mutex_lock(&video->device_list_lock);
+   list_for_each_entry_safe(dev, next, &video->video_device_list, entry) {
+   if (dev->backlight) {
+   backlight_device_unregister(dev->backlight);
+   dev->backlight = NULL;
+   kfree(dev->brightness->levels);
+   kfree(dev->brightness);
+   }
+   if (dev->cooling_dev) {
+   sysfs_remove_link(&dev->dev->dev.kobj,
+ "thermal_cooling");
+   sysfs_remove_link(&dev->cooling_dev->device.kobj,
+ "device");
+   thermal_cooling_device_unregister(dev->cooling_dev);
+   dev->cooling_dev = NULL;
+   }
+   }
+   mutex_unlock(&video->device_list_lock);
+   acpi_video_bus_start_devices(video);
+   return AE_OK;
+}
+
 static int __init is_i740(struct pci_dev *dev)
 {
if (dev->device == 0x00D1)
@@ -1885,14 +1927,25 @@ static int __init intel_opregion_present
return opregion;
 }
 
-int acpi_video_register(

Re: [Intel-gfx] Question about how brightness up/down to call the code of xf86-video-intel like intel_output_dpms_backlight etc

[Li, Hao H]

For userspace listens to this key event and reacts appropriately, is it done on 
gnome-shell? Or any other packages?

Thanks!

-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Friday, July 12, 2013 8:10 PM
To: Li, Hao H
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] Question about how brightness up/down to call the code 
of xf86-video-intel like intel_output_dpms_backlight etc

On Fri, Jul 12, 2013 at 08:53:23AM +, Li, Hao H wrote:
> Hi
> 
> When we press the key like brightness up/down from keyboard, kernel will 
> receive the keyevent.
> My question is how the keyevent from kernel call the code of xf86-video-intel 
> like intel_output_dpms_backlight etc to adjust the backlight.
> Can someone help to explain more details about it?

Kernel doesn't call the brightness adjustment code. There's a bit of bonghits 
in acpi where the acpi brightness keys directly adjust the acpi backlight, but 
that's just not yet been fixed.

What's supposed to happen is that userspace listens to this key event and 
reacts appropriately, e.g. by adjusting the brightness but also by drawing a 
nice brightness scale on the screen

Cheers, Daniel
--
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: debugfs entries for [e]LLC

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi 

I actually tested it too here on my ult... 0Mb ellc as expected...
unfortunately I don't have any cristallwell to test it for real ;)

On Thu, Jul 4, 2013 at 3:02 PM, Ben Widawsky  wrote:
> To make users life a little easier figuring out what they have on their
> system.
>
> Ideally, I'd really like to report LLC size, but it turned out to be a
> bit of a pain. Maybe I'll revisit it in the future.
>
> Signed-off-by: Ben Widawsky 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3e36756..b75d0a6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1941,6 +1941,19 @@ static int i915_dpio_info(struct seq_file *m, void 
> *data)
> return 0;
>  }
>
> +static int i915_llc(struct seq_file *m, void *data)
> +{
> +   struct drm_info_node *node = (struct drm_info_node *) m->private;
> +   struct drm_device *dev = node->minor->dev;
> +   struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +   /* Size calculation for LLC is a bit of a pain. Ignore for now. */
> +   seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
> +   seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
> +
> +   return 0;
> +}
> +
>  static int
>  i915_wedged_get(void *data, u64 *val)
>  {
> @@ -2370,6 +2383,7 @@ static struct drm_info_list i915_debugfs_list[] = {
> {"i915_swizzle_info", i915_swizzle_info, 0},
> {"i915_ppgtt_info", i915_ppgtt_info, 0},
> {"i915_dpio", i915_dpio_info, 0},
> +   {"i915_llc", i915_llc, 0},
>  };
>  #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>
> --
> 1.8.3
>
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Use eLLC/LLC by default when available

[Rodrigo Vivi]

I don't have a strong opinion on iris x crw and you know that I like
to split different things in different functions, however in this case
I think either iris or crw are still hsw
so if it is possible to get  dev_priv->ellc_size inside hsw_pte_encode
somehow I in favor of not creating another function for iris...
otherwise, fell free to use:
Reviewed-by: Rodrigo Vivi 

On Thu, Jul 4, 2013 at 3:40 PM, Ben Widawsky  wrote:
> On Thu, Jul 04, 2013 at 08:17:09PM +0200, Daniel Vetter wrote:
>> On Thu, Jul 04, 2013 at 11:02:06AM -0700, Ben Widawsky wrote:
>> > DRI clients really should be using MOCS to get fine grained streaming
>> > cache controls. With that note, I *hope* that this patch doesn't improve
>> > performance overwhelmingly, because if it does - it means there is a
>> > problem elsewhere.
>> >
>> > In any case, the kernel, and old userspace should get some benefit from
>> > this, so let's do it. eLLC is always a good default, and really not
>> > using it is the special case for MOCS.
>> >
>> > References: 
>> > http://www.intel.com/newsroom/kits/restricted/ha$well!/pdfs/4th_Gen_Intel_Core_PressBriefing_5-29.pdf
>> >  (page 57)
>> >
>> > Signed-off-by: Ben Widawsky 
>>
>> Iris is the marketing name and likely to stick around for a bit (like HD
>> Graphics), I'd vote to use the codename for this thing here, i.e. crw.
>> -Daniel
>>
> I think we've agreed on IRC to leave this as is?
> --
> Ben Widawsky, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 3.5/5] drm/i915: Do eLLC detection earlier

[Rodrigo Vivi]

to be honest I didn't understood the other idea with forcewake, but
this way is fine for me, so:

Reviewed-by: Rodrigo Vivi 

On Thu, Jul 4, 2013 at 3:42 PM, Ben Widawsky  wrote:
> We need it before we set the pte_encode function pointers, which happens
> really early, in gtt_init.
>
> The problem with just doing the normal sequence earlier is we don't have
> the ability to use forcewake until after the pte functions have been set
> up.
>
> Since all solutions are somewhat ugly (barring rewriting all the init
> ordering), I've opted to do the detection really early, and the enabling
> later - since the register to detect doesn't require forcewake.
>
> Signed-off-by: Ben Widawsky 
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 10 ++
>  drivers/gpu/drm/i915/i915_gem.c |  9 +
>  2 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 0e22142..7eda8ab 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1524,6 +1524,16 @@ int i915_driver_load(struct drm_device *dev, unsigned 
> long flags)
>
> intel_early_sanitize_regs(dev);
>
> +   if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1)) {
> +   /* The docs do not explain exactly how the calculation can be
> +* made. It is somewhat guessable, but for now, it's always
> +* 128MB.
> +* NB: We can't write IDICR yet because we do not have gt 
> funcs
> +* set up */
> +   dev_priv->ellc_size = 128;
> +   DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
> +   }
> +
> ret = i915_gem_gtt_init(dev);
> if (ret)
> goto put_bridge;
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 2df993d..f9834f2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4153,15 +4153,8 @@ i915_gem_init_hw(struct drm_device *dev)
> if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
> return -EIO;
>
> -   if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1)) {
> +   if (dev_priv->ellc_size)
> I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> -   /* The docs do not explain exactly how the calculation can be
> -* made. It is somewhat guessable, but for now, it's always
> -* 128MB.
> -*/
> -   dev_priv->ellc_size = 128;
> -   DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
> -   }
>
> if (HAS_PCH_NOP(dev)) {
> u32 temp = I915_READ(GEN7_MSG_CTL);
> --
> 1.8.3
>
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: Define some of the eLLC magic

[Rodrigo Vivi]

On Thu, Jul 4, 2013 at 3:02 PM, Ben Widawsky  wrote:
> The EDRAM present register isn't really defined in the docs. It just
> says check to see if it's set to 1. So I haven't defined the 1 value not
> knowing what it actually means.
>
> Signed-off-by: Ben Widawsky 
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h | 4 
>  2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4200c32..edea2cb 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4153,8 +4153,8 @@ i915_gem_init_hw(struct drm_device *dev)
> if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
> return -EIO;
>
> -   if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
> -   I915_WRITE(0x9008, I915_READ(0x9008) | 0xf);
> +   if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1))
> +   I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));

even though you said doc doesn't define this register please fwd me
the doc... or please explain what is that
sorry about that, but as I said I'm without access :(

>
> if (HAS_PCH_NOP(dev)) {
> u32 temp = I915_READ(GEN7_MSG_CTL);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9b51be8..a2553ed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4469,6 +4469,10 @@
>  #define  GT_FIFO_FREE_ENTRIES  0x120008
>  #defineGT_FIFO_NUM_RESERVED_ENTRIES20
>
> +#define  HSW_IDICR 0x9008
> +#defineIDIHASHMSK(x)   (((x) & 0x3f) << 16)
> +#define  HSW_EDRAM_PRESENT 0x120010
> +
>  #define GEN6_UCGCTL1   0x9400
>  # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE   (1 << 5)
>  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE(1 << 7)
> --
> 1.8.3
>
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

[Rodrigo Vivi]

Hi Ben,

sorry for taking so long to look at your patches.
Well, since I changed my TI password I'm not able to see bspec
anymore, so I couldn't verify many things that I'm going to ask many
questions.
If the answer is on spec or any other doc please send me in pvt!


On Thu, Jul 4, 2013 at 3:02 PM, Ben Widawsky  wrote:
> From: Ben Widawsky 
>
> The cacheability controls have changed, and the bits have been
> rearranged in general.
>
> v2: Remove comments for snb/ivb cache leves, that's a separate change.
>
> v3: Resolve conflicts due to patch series reordering.
>
> v4: Rebased on top of Kenneth Graunke's ->pet_encode refactoring.

pet like in leper?! :P
just kidding never mind.

>
> v5: Removed eLLC bits for separate patch.
>
> In the internal repository this was:
> Signed-off-by: Ben Widawsky 
> Signed-off-by: Kenneth Graunke 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 66929ea..42262d0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -33,6 +33,7 @@
>
>  /* PPGTT stuff */
>  #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
> +#define HSW_GTT_ADDR_ENCODE(addr)  ((addr) | (((addr) >> 28) & 0x7f0))

why not masking bit 10 anymore?

>
>  #define GEN6_PDE_VALID (1 << 0)
>  /* gen6+ has bit 11-4 for physical addr bit 39-32 */
> @@ -44,6 +45,14 @@
>  #define GEN6_PTE_CACHE_LLC (2 << 1)
>  #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
>  #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
> +#define HSW_PTE_ADDR_ENCODE(addr)  HSW_GTT_ADDR_ENCODE(addr)
> +
> +/* Cacheability Control is a 4-bit value. The low three bits are stored in *
> + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
> + */
> +#define HSW_CACHEABILITY_CONTROL(bits) bits) & 0x7) << 1) | \
> +(((bits) & 0x8) << (11 - 3)))
> +#define HSW_WB_LLC_AGE0HSW_CACHEABILITY_CONTROL(0x3)

where did you get that? and are you really using that in any other patch?

>
>  static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,
>   enum i915_cache_level level)
> @@ -92,10 +101,10 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
>  enum i915_cache_level level)
>  {
> gen6_gtt_pte_t pte = GEN6_PTE_VALID;
> -   pte |= GEN6_PTE_ADDR_ENCODE(addr);
> +   pte |= HSW_PTE_ADDR_ENCODE(addr);
>
> if (level != I915_CACHE_NONE)
> -   pte |= GEN6_PTE_CACHE_LLC;
> +   pte |= HSW_WB_LLC_AGE0;
>
> return pte;
>  }
> --
> 1.8.3
>
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[Intel-gfx] [PATCH 9/9] drm/i915: kill ivybridge_irq_postinstall

[Paulo Zanoni]

From: Paulo Zanoni 

It was very similar to ironlake_irq_postinstall, so IMHO merging both
functions results in a code that is easier to maintain.

With this change, all the irq handler vfuncs between ironlake and
ivybridge are now unified.

v2: Add "(" and ")" to make at least one vim user much happier (Chris)

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 69 -
 1 file changed, 20 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d084057..8b48a32 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2161,21 +2161,33 @@ static void gen5_gt_irq_postinstall(struct drm_device 
*dev)
 static int ironlake_irq_postinstall(struct drm_device *dev)
 {
unsigned long irqflags;
-
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   /* enable kind of interrupts always enabled */
-   u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
-  DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
-  DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
-  DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
+   u32 display_mask, extra_mask;
+
+   if (INTEL_INFO(dev)->gen >= 7) {
+   display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
+   DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
+   DE_PLANEB_FLIP_DONE_IVB |
+   DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
+   DE_ERR_INT_IVB);
+   extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
+ DE_PIPEA_VBLANK_IVB);
+
+   I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
+   } else {
+   display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
+   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
+   DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
+   DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
+   extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
+   }
 
dev_priv->irq_mask = ~display_mask;
 
/* should always can generate irq */
I915_WRITE(DEIIR, I915_READ(DEIIR));
I915_WRITE(DEIMR, dev_priv->irq_mask);
-   I915_WRITE(DEIER, display_mask |
- DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
+   I915_WRITE(DEIER, display_mask | extra_mask);
POSTING_READ(DEIER);
 
gen5_gt_irq_postinstall(dev);
@@ -2196,38 +2208,6 @@ static int ironlake_irq_postinstall(struct drm_device 
*dev)
return 0;
 }
 
-static int ivybridge_irq_postinstall(struct drm_device *dev)
-{
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   /* enable kind of interrupts always enabled */
-   u32 display_mask =
-   DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
-   DE_PLANEC_FLIP_DONE_IVB |
-   DE_PLANEB_FLIP_DONE_IVB |
-   DE_PLANEA_FLIP_DONE_IVB |
-   DE_AUX_CHANNEL_A_IVB |
-   DE_ERR_INT_IVB;
-
-   dev_priv->irq_mask = ~display_mask;
-
-   /* should always can generate irq */
-   I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
-   I915_WRITE(DEIIR, I915_READ(DEIIR));
-   I915_WRITE(DEIMR, dev_priv->irq_mask);
-   I915_WRITE(DEIER,
-  display_mask |
-  DE_PIPEC_VBLANK_IVB |
-  DE_PIPEB_VBLANK_IVB |
-  DE_PIPEA_VBLANK_IVB);
-   POSTING_READ(DEIER);
-
-   gen5_gt_irq_postinstall(dev);
-
-   ibx_irq_postinstall(dev);
-
-   return 0;
-}
-
 static int valleyview_irq_postinstall(struct drm_device *dev)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -3036,15 +3016,6 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->enable_vblank = valleyview_enable_vblank;
dev->driver->disable_vblank = valleyview_disable_vblank;
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
-   } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
-   /* Share uninstall handlers with ILK/SNB */
-   dev->driver->irq_handler = ironlake_irq_handler;
-   dev->driver->irq_preinstall = ironlake_irq_preinstall;
-   dev->driver->irq_postinstall = ivybridge_irq_postinstall;
-   dev->driver->irq_uninstall = ironlake_irq_uninstall;
-   dev->driver->enable_vblank = ironlake_enable_vblank;
-   dev->driver->disable_vblank = ironlake_disable_vblank;
-   dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
} else if (HAS_PCH_SPLIT(dev)) {
dev->driver->irq_handler = ironlake_irq_han

[Intel-gfx] [PATCH 8/9] drm/i915: kill Ivybridge vblank irq vfuncs

[Paulo Zanoni]

From: Paulo Zanoni 

The IVB funtions are exactly the same as the ILK ones, with the
exception of the bit register. So add IVB/HSW support to
ironlake_enable_vblank and ironlake_disable_vblank, then kill the
ivybridge functions.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 41 -
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 2 files changed, 11 insertions(+), 33 deletions(-)

This replaces patches 8 and 9 from the series. I'm not really sure what Chris
had in mind when he mentioned I could be a little more creative, so this is my
attempt.

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f54a02b..d084057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1663,29 +1663,14 @@ static int ironlake_enable_vblank(struct drm_device 
*dev, int pipe)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
+   uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
+DE_PIPE_VBLANK_ILK(pipe);
 
if (!i915_pipe_enabled(dev, pipe))
return -EINVAL;
 
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
-   DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
-   spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-
-   return 0;
-}
-
-static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
-{
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   unsigned long irqflags;
-
-   if (!i915_pipe_enabled(dev, pipe))
-   return -EINVAL;
-
-   spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_enable_display_irq(dev_priv,
-   DE_PIPEA_VBLANK_IVB << (5 * pipe));
+   ironlake_enable_display_irq(dev_priv, bit);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
return 0;
@@ -1736,21 +1721,11 @@ static void ironlake_disable_vblank(struct drm_device 
*dev, int pipe)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
+   uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
+DE_PIPE_VBLANK_ILK(pipe);
 
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
-DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
-   spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-}
-
-static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
-{
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   unsigned long irqflags;
-
-   spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_disable_display_irq(dev_priv,
-DE_PIPEA_VBLANK_IVB << (pipe * 5));
+   ironlake_disable_display_irq(dev_priv, bit);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
@@ -3067,8 +3042,8 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->irq_preinstall = ironlake_irq_preinstall;
dev->driver->irq_postinstall = ivybridge_irq_postinstall;
dev->driver->irq_uninstall = ironlake_irq_uninstall;
-   dev->driver->enable_vblank = ivybridge_enable_vblank;
-   dev->driver->disable_vblank = ivybridge_disable_vblank;
+   dev->driver->enable_vblank = ironlake_enable_vblank;
+   dev->driver->disable_vblank = ironlake_disable_vblank;
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
} else if (HAS_PCH_SPLIT(dev)) {
dev->driver->irq_handler = ironlake_irq_handler;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9556dff..dd2306e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3729,6 +3729,9 @@
 #define DE_PLANEA_FLIP_DONE_IVB(1<<3)
 #define DE_PIPEA_VBLANK_IVB(1<<0)
 
+#define DE_PIPE_VBLANK_ILK(pipe)   (1 << ((pipe * 8) + 7))
+#define DE_PIPE_VBLANK_IVB(pipe)   (1 << (pipe * 5))
+
 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE  (1<<31)
 
-- 
1.8.1.2

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[Intel-gfx] [PATCH 7/9] drm/i915: add ILK/SNB support to ivybridge_irq_handler

[Paulo Zanoni]

From: Paulo Zanoni 

And then rename it to ironlake_irq_handler. Also move
ilk_gt_irq_handler up to avoid forward declarations.

In the previous patches I did small modifications to both
ironlake_irq_handler an ivybridge_irq_handler so they became very
similar functions. Now it should be very easy to verify that all we
need to add ILK/SNB support is to call ilk_gt_irq_handler, call
ilk_display_irq_handler and avoid reading pm_iir on gen 5.

v2: - Rebase due to changes on the previous patches
- Move pm_iir to a tighter scope (Chris)
- Change some Gen checks for readability

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 115 +++-
 1 file changed, 32 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ba38aa8..f54a02b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -849,6 +849,17 @@ static void ivybridge_parity_error_irq_handler(struct 
drm_device *dev)
queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 }
 
+static void ilk_gt_irq_handler(struct drm_device *dev,
+  struct drm_i915_private *dev_priv,
+  u32 gt_iir)
+{
+   if (gt_iir &
+   (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
+   notify_ring(dev, &dev_priv->ring[RCS]);
+   if (gt_iir & ILK_BSD_USER_INTERRUPT)
+   notify_ring(dev, &dev_priv->ring[VCS]);
+}
+
 static void snb_gt_irq_handler(struct drm_device *dev,
   struct drm_i915_private *dev_priv,
   u32 gt_iir)
@@ -1290,11 +1301,11 @@ static void ivb_display_irq_handler(struct drm_device 
*dev, u32 de_iir)
}
 }
 
-static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
+static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 {
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
+   u32 de_iir, gt_iir, de_ier, sde_ier = 0;
irqreturn_t ret = IRQ_NONE;
 
atomic_inc(&dev_priv->irq_received);
@@ -1334,27 +1345,34 @@ static irqreturn_t ivybridge_irq_handler(int irq, void 
*arg)
 
gt_iir = I915_READ(GTIIR);
if (gt_iir) {
-   snb_gt_irq_handler(dev, dev_priv, gt_iir);
+   if (IS_GEN5(dev))
+   ilk_gt_irq_handler(dev, dev_priv, gt_iir);
+   else
+   snb_gt_irq_handler(dev, dev_priv, gt_iir);
I915_WRITE(GTIIR, gt_iir);
ret = IRQ_HANDLED;
}
 
de_iir = I915_READ(DEIIR);
if (de_iir) {
-   ivb_display_irq_handler(dev, de_iir);
-
+   if (INTEL_INFO(dev)->gen >= 7)
+   ivb_display_irq_handler(dev, de_iir);
+   else
+   ilk_display_irq_handler(dev, de_iir);
I915_WRITE(DEIIR, de_iir);
ret = IRQ_HANDLED;
}
 
-   pm_iir = I915_READ(GEN6_PMIIR);
-   if (pm_iir) {
-   if (IS_HASWELL(dev))
-   hsw_pm_irq_handler(dev_priv, pm_iir);
-   else if (pm_iir & GEN6_PM_RPS_EVENTS)
-   gen6_rps_irq_handler(dev_priv, pm_iir);
-   I915_WRITE(GEN6_PMIIR, pm_iir);
-   ret = IRQ_HANDLED;
+   if (INTEL_INFO(dev)->gen >= 6) {
+   u32 pm_iir = I915_READ(GEN6_PMIIR);
+   if (pm_iir) {
+   if (IS_HASWELL(dev))
+   hsw_pm_irq_handler(dev_priv, pm_iir);
+   else if (pm_iir & GEN6_PM_RPS_EVENTS)
+   gen6_rps_irq_handler(dev_priv, pm_iir);
+   I915_WRITE(GEN6_PMIIR, pm_iir);
+   ret = IRQ_HANDLED;
+   }
}
 
if (IS_HASWELL(dev)) {
@@ -1374,75 +1392,6 @@ static irqreturn_t ivybridge_irq_handler(int irq, void 
*arg)
return ret;
 }
 
-static void ilk_gt_irq_handler(struct drm_device *dev,
-  struct drm_i915_private *dev_priv,
-  u32 gt_iir)
-{
-   if (gt_iir &
-   (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
-   notify_ring(dev, &dev_priv->ring[RCS]);
-   if (gt_iir & ILK_BSD_USER_INTERRUPT)
-   notify_ring(dev, &dev_priv->ring[VCS]);
-}
-
-static irqreturn_t ironlake_irq_handler(int irq, void *arg)
-{
-   struct drm_device *dev = (struct drm_device *) arg;
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   int ret = IRQ_NONE;
-   u32 de_iir, gt_iir, de_ier, sde_ier;
-
-   atomic_inc(&dev_priv->irq_received);
-
-   /* disable master interrupt before clearing iir  */
-   de_ier = I915_READ(DEIER);
-

[Intel-gfx] [PATCH 5/9] drm/i915: reorganize ironlake_irq_handler

[Paulo Zanoni]

From: Paulo Zanoni 

The ironlake_irq_handler and ivybridge_irq_handler functions do
basically the same thing, but they have different implementation
styles. With this patch we reorganize ironlake_irq_handler in a way
that makes it look very similar to ivybridge_irq_handler.

One of the advantages of this new function style is that we don't
write 0 to the IIR registers anymore.

v2: - Rebase due to changes on previous patches
- Move pm_iir to a tighter scope (Chris)

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 46 -
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c674dc3..88eb380 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1389,7 +1389,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int ret = IRQ_NONE;
-   u32 de_iir, gt_iir, de_ier, pm_iir = 0, sde_ier;
+   u32 de_iir, gt_iir, de_ier, sde_ier;
 
atomic_inc(&dev_priv->irq_received);
 
@@ -1407,33 +1407,33 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
I915_WRITE(SDEIER, 0);
POSTING_READ(SDEIER);
 
-   de_iir = I915_READ(DEIIR);
gt_iir = I915_READ(GTIIR);
-   if (IS_GEN6(dev))
-   pm_iir = I915_READ(GEN6_PMIIR);
-
-   if (de_iir == 0 && gt_iir == 0 && pm_iir == 0)
-   goto done;
-
-   ret = IRQ_HANDLED;
-
-   if (IS_GEN5(dev))
-   ilk_gt_irq_handler(dev, dev_priv, gt_iir);
-   else
-   snb_gt_irq_handler(dev, dev_priv, gt_iir);
+   if (gt_iir) {
+   if (IS_GEN5(dev))
+   ilk_gt_irq_handler(dev, dev_priv, gt_iir);
+   else
+   snb_gt_irq_handler(dev, dev_priv, gt_iir);
+   I915_WRITE(GTIIR, gt_iir);
+   ret = IRQ_HANDLED;
+   }
 
-   if (de_iir)
+   de_iir = I915_READ(DEIIR);
+   if (de_iir) {
ilk_display_irq_handler(dev, de_iir);
+   I915_WRITE(DEIIR, de_iir);
+   ret = IRQ_HANDLED;
+   }
 
-   if (pm_iir & GEN6_PM_RPS_EVENTS)
-   gen6_rps_irq_handler(dev_priv, pm_iir);
-
-   I915_WRITE(GTIIR, gt_iir);
-   I915_WRITE(DEIIR, de_iir);
-   if (pm_iir)
-   I915_WRITE(GEN6_PMIIR, pm_iir);
+   if (IS_GEN6(dev)) {
+   u32 pm_iir = I915_READ(GEN6_PMIIR);
+   if (pm_iir) {
+   if (pm_iir & GEN6_PM_RPS_EVENTS)
+   gen6_rps_irq_handler(dev_priv, pm_iir);
+   I915_WRITE(GEN6_PMIIR, pm_iir);
+   ret = IRQ_HANDLED;
+   }
+   }
 
-done:
I915_WRITE(DEIER, de_ier);
POSTING_READ(DEIER);
I915_WRITE(SDEIER, sde_ier);
-- 
1.8.1.2

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[Intel-gfx] [PATCH 4/9] drm/i915: don't read or write GEN6_PMIIR on Gen 5

[Paulo Zanoni]

From: Paulo Zanoni 

The register doesn't exist on Gen 5.

v2: Simplify checks since pm_iir is always 0 on Gen 5 (Chris)

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9167219..c674dc3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1389,7 +1389,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int ret = IRQ_NONE;
-   u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
+   u32 de_iir, gt_iir, de_ier, pm_iir = 0, sde_ier;
 
atomic_inc(&dev_priv->irq_received);
 
@@ -1409,9 +1409,10 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
 
de_iir = I915_READ(DEIIR);
gt_iir = I915_READ(GTIIR);
-   pm_iir = I915_READ(GEN6_PMIIR);
+   if (IS_GEN6(dev))
+   pm_iir = I915_READ(GEN6_PMIIR);
 
-   if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
+   if (de_iir == 0 && gt_iir == 0 && pm_iir == 0)
goto done;
 
ret = IRQ_HANDLED;
@@ -1424,12 +1425,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
if (de_iir)
ilk_display_irq_handler(dev, de_iir);
 
-   if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
+   if (pm_iir & GEN6_PM_RPS_EVENTS)
gen6_rps_irq_handler(dev_priv, pm_iir);
 
I915_WRITE(GTIIR, gt_iir);
I915_WRITE(DEIIR, de_iir);
-   I915_WRITE(GEN6_PMIIR, pm_iir);
+   if (pm_iir)
+   I915_WRITE(GEN6_PMIIR, pm_iir);
 
 done:
I915_WRITE(DEIER, de_ier);
-- 
1.8.1.2

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Re: [Intel-gfx] [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios

[Paulo Zanoni]

2013/7/12 Paulo Zanoni :
> 2013/7/12 Stéphane Marchesin :
>> Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes
>> on eDP. This fixes eDP on hsw with > 2 lanes.
>>
>> Also s/port_reversal/saved_port_bits/ since the current name is
>> confusing.
>>
>> Signed-off-by: Stéphane Marchesin 
>
> Reviewed-by: Paulo Zanoni 
>
> Should we also Cc: sta...@kernel.org ?

And I forgot to mention: as discussed on IRC, we need 2 additional
patches on top of that:
- Don't intel_init_crt if DDI A has 4 lanes
- We should do our own wrapper around drm_dp_max_lane_count and return
minimum of drm_dp_max_lane_count and the value set on DDI_BUF_CTL_A

>
>> ---
>>  drivers/gpu/drm/i915/intel_ddi.c | 10 ++
>>  drivers/gpu/drm/i915/intel_drv.h |  2 +-
>>  2 files changed, 7 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index 324211a..b042ee5 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -301,7 +301,7 @@ static void intel_ddi_mode_set(struct drm_encoder 
>> *encoder,
>> struct intel_digital_port *intel_dig_port =
>> enc_to_dig_port(encoder);
>>
>> -   intel_dp->DP = intel_dig_port->port_reversal |
>> +   intel_dp->DP = intel_dig_port->saved_port_bits |
>>DDI_BUF_CTL_ENABLE | 
>> DDI_BUF_EMP_400MV_0DB_HSW;
>> intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
>>
>> @@ -1109,7 +1109,8 @@ static void intel_enable_ddi(struct intel_encoder 
>> *intel_encoder)
>>  * enabling the port.
>>  */
>> I915_WRITE(DDI_BUF_CTL(port),
>> -  intel_dig_port->port_reversal | 
>> DDI_BUF_CTL_ENABLE);
>> +  intel_dig_port->saved_port_bits |
>> +  DDI_BUF_CTL_ENABLE);
>> } else if (type == INTEL_OUTPUT_EDP) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> @@ -1347,8 +1348,9 @@ void intel_ddi_init(struct drm_device *dev, enum port 
>> port)
>> intel_encoder->get_config = intel_ddi_get_config;
>>
>> intel_dig_port->port = port;
>> -   intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
>> -   DDI_BUF_PORT_REVERSAL;
>> +   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
>> + (DDI_BUF_PORT_REVERSAL |
>> +  DDI_A_4_LANES);
>> intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
>>
>> intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index c8c9b6f..b7d6e09 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -504,7 +504,7 @@ struct intel_dp {
>>  struct intel_digital_port {
>> struct intel_encoder base;
>> enum port port;
>> -   u32 port_reversal;
>> +   u32 saved_port_bits;
>> struct intel_dp dp;
>> struct intel_hdmi hdmi;
>>  };
>> --
>> 1.8.3
>>
>> ___
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>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni



-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios

[Paulo Zanoni]

2013/7/12 Stéphane Marchesin :
> Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes
> on eDP. This fixes eDP on hsw with > 2 lanes.
>
> Also s/port_reversal/saved_port_bits/ since the current name is
> confusing.
>
> Signed-off-by: Stéphane Marchesin 

Reviewed-by: Paulo Zanoni 

Should we also Cc: sta...@kernel.org ?

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 10 ++
>  drivers/gpu/drm/i915/intel_drv.h |  2 +-
>  2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 324211a..b042ee5 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -301,7 +301,7 @@ static void intel_ddi_mode_set(struct drm_encoder 
> *encoder,
> struct intel_digital_port *intel_dig_port =
> enc_to_dig_port(encoder);
>
> -   intel_dp->DP = intel_dig_port->port_reversal |
> +   intel_dp->DP = intel_dig_port->saved_port_bits |
>DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
> intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
>
> @@ -1109,7 +1109,8 @@ static void intel_enable_ddi(struct intel_encoder 
> *intel_encoder)
>  * enabling the port.
>  */
> I915_WRITE(DDI_BUF_CTL(port),
> -  intel_dig_port->port_reversal | 
> DDI_BUF_CTL_ENABLE);
> +  intel_dig_port->saved_port_bits |
> +  DDI_BUF_CTL_ENABLE);
> } else if (type == INTEL_OUTPUT_EDP) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> @@ -1347,8 +1348,9 @@ void intel_ddi_init(struct drm_device *dev, enum port 
> port)
> intel_encoder->get_config = intel_ddi_get_config;
>
> intel_dig_port->port = port;
> -   intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
> -   DDI_BUF_PORT_REVERSAL;
> +   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
> + (DDI_BUF_PORT_REVERSAL |
> +  DDI_A_4_LANES);
> intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
>
> intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index c8c9b6f..b7d6e09 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -504,7 +504,7 @@ struct intel_dp {
>  struct intel_digital_port {
> struct intel_encoder base;
> enum port port;
> -   u32 port_reversal;
> +   u32 saved_port_bits;
> struct intel_dp dp;
> struct intel_hdmi hdmi;
>  };
> --
> 1.8.3
>
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Use a private interface for register access within GT

[Daniel Vetter]

On Fri, Jul 12, 2013 at 09:55:46PM +0100, Chris Wilson wrote:
> On Fri, Jul 12, 2013 at 01:25:27PM -0700, Ben Widawsky wrote:
> > On Fri, Jul 12, 2013 at 03:02:32PM +0100, Chris Wilson wrote:
> > > The GT functions for enabling register access also need to occasionally
> > > write to and read from registers. To avoid the potential recursion as we
> > > modify the public interface to be stricter, introduce a private register
> > > access API for the GT functions.
> > > 
> > > Signed-off-by: Chris Wilson 
> > > ---
> > >  drivers/gpu/drm/i915/intel_gt.c | 92 
> > > +
> > >  1 file changed, 56 insertions(+), 36 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_gt.c 
> > > b/drivers/gpu/drm/i915/intel_gt.c
> > > index 060e256..cb3116c 100644
> > > --- a/drivers/gpu/drm/i915/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/intel_gt.c
> > > @@ -26,6 +26,19 @@
> > >  
> > >  #define FORCEWAKE_ACK_TIMEOUT_MS 2
> > >  
> > > +#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + 
> > > (reg__))
> > > +#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, 
> > > (dev_priv__)->regs + (reg__))
> > > +
> > > +#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + 
> > > (reg__))
> > > +#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, 
> > > (dev_priv__)->regs + (reg__))
> > > +
> > > +#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
> > > (reg__))
> > > +#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
> > > (dev_priv__)->regs + (reg__))
> > 
> > Instead of what you did, I would have preferred
> > #define __raw_posting_read
> 
> In hindsight, I agree with using __raw_posting_read.

Patch on top to avoid another messy rebase? I've read through the patches
and also thought that the (void)__raw_read sprinkled all over is
unsightly, a __raw_posting_read would look better.
-Daniel
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Use a private interface for register access within GT

[Chris Wilson]

On Fri, Jul 12, 2013 at 01:25:27PM -0700, Ben Widawsky wrote:
> On Fri, Jul 12, 2013 at 03:02:32PM +0100, Chris Wilson wrote:
> > The GT functions for enabling register access also need to occasionally
> > write to and read from registers. To avoid the potential recursion as we
> > modify the public interface to be stricter, introduce a private register
> > access API for the GT functions.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/intel_gt.c | 92 
> > +
> >  1 file changed, 56 insertions(+), 36 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_gt.c 
> > b/drivers/gpu/drm/i915/intel_gt.c
> > index 060e256..cb3116c 100644
> > --- a/drivers/gpu/drm/i915/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/intel_gt.c
> > @@ -26,6 +26,19 @@
> >  
> >  #define FORCEWAKE_ACK_TIMEOUT_MS 2
> >  
> > +#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + 
> > (reg__))
> > +#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, 
> > (dev_priv__)->regs + (reg__))
> > +
> > +#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + 
> > (reg__))
> > +#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, 
> > (dev_priv__)->regs + (reg__))
> > +
> > +#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
> > (reg__))
> > +#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
> > (dev_priv__)->regs + (reg__))
> 
> Instead of what you did, I would have preferred
> #define __raw_posting_read

In hindsight, I agree with using __raw_posting_read.

Thanks,
-Chris

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[Intel-gfx] [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios

[Stéphane Marchesin]

Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes
on eDP. This fixes eDP on hsw with > 2 lanes.

Also s/port_reversal/saved_port_bits/ since the current name is
confusing.

Signed-off-by: Stéphane Marchesin 
---
 drivers/gpu/drm/i915/intel_ddi.c | 10 ++
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 324211a..b042ee5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -301,7 +301,7 @@ static void intel_ddi_mode_set(struct drm_encoder *encoder,
struct intel_digital_port *intel_dig_port =
enc_to_dig_port(encoder);
 
-   intel_dp->DP = intel_dig_port->port_reversal |
+   intel_dp->DP = intel_dig_port->saved_port_bits |
   DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 
@@ -1109,7 +1109,8 @@ static void intel_enable_ddi(struct intel_encoder 
*intel_encoder)
 * enabling the port.
 */
I915_WRITE(DDI_BUF_CTL(port),
-  intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
+  intel_dig_port->saved_port_bits |
+  DDI_BUF_CTL_ENABLE);
} else if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
@@ -1347,8 +1348,9 @@ void intel_ddi_init(struct drm_device *dev, enum port 
port)
intel_encoder->get_config = intel_ddi_get_config;
 
intel_dig_port->port = port;
-   intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
-   DDI_BUF_PORT_REVERSAL;
+   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
+ (DDI_BUF_PORT_REVERSAL |
+  DDI_A_4_LANES);
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
 
intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c8c9b6f..b7d6e09 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -504,7 +504,7 @@ struct intel_dp {
 struct intel_digital_port {
struct intel_encoder base;
enum port port;
-   u32 port_reversal;
+   u32 saved_port_bits;
struct intel_dp dp;
struct intel_hdmi hdmi;
 };
-- 
1.8.3

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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Serialize all register access

[Chris Wilson]

On Fri, Jul 12, 2013 at 01:37:28PM -0700, Ben Widawsky wrote:
> On Fri, Jul 12, 2013 at 03:02:34PM +0100, Chris Wilson wrote:
> > In theory, the different register blocks were meant to be only ever
> > touched when holding either the struct_mutex, mode_config.lock or even a
> > specific localised lock. This does not seem to be the case, and the
> > hardware reacts extremely badly if we attempt to concurrently access two
> > registers within the same cacheline.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63914
> > Signed-off-by: Chris Wilson 
> 
> You are crossing the point of no return here for doing this only on HSW
> where the bug is known to exist. As you are the resident performance
> curmudgeon I'll defer to you if that's okay or not... just pointing it
> out.

I looked at all the extra checks we are doing in addition to just
reading/writing the register and thought it would be better to close any
races there. Hence why I think this is a correctness fix above and
beyond the hsw issue.
-Chris

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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Use the common register access functions for NOTRACE variants

[Chris Wilson]

On Fri, Jul 12, 2013 at 01:34:09PM -0700, Ben Widawsky wrote:
> On Fri, Jul 12, 2013 at 03:02:33PM +0100, Chris Wilson wrote:
> >  #define __i915_write(x, y) \
> > -void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { 
> > \
> > +void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, 
> > bool trace) { \
> > u32 __fifo_ret = 0; \
> > -   trace_i915_reg_rw(true, reg, val, sizeof(val)); \
> > +   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
> > if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
> > __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
> > } \
> 
> 
> if (unlikely(trace))? taking a hit on the tracing case seems like what
> you want... but I never know the status of such compiler flags.

It would be likely, I guess. But it is not obvious, so leave it out. Later
on we replace it with the preferred form for conditional tracepoints.
-Chris

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[Intel-gfx] [PATCH 3/3] drm/i915: extract rps interrupt enable/disable helpers

[Daniel Vetter]

The VECS enabling required some changes to how rps interrupts are
enabled/disabled since VECS interrupts are handling with the PM
interrupt registers.

But now that the pre/postinstall sequences is identical for all
platforms with rps support (snb, ivb, hsw, vlv) we can also use the
exact same sequence to actually enable the rps interrupts. Strictly
speaking using spinlocks is overkill on snb/ivb & vlv since they have
no VECS ring, but imo that's more than made up by the common code.

Hence this just unifies the vlv code with the snb-hsw code which
matched exactly before the VECS enabling. See

commit eda63ffb906c2fb3b609a0e87aeb63c0f25b9e6b
Author: Ben Widawsky 
Date:   Tue May 28 19:22:26 2013 -0700

drm/i915: Add PM regs to pre/post install

and

commit 4848405cced3b46f4ec7d404b8ed5873171ae10a
Author: Ben Widawsky 
Date:   Tue May 28 19:22:27 2013 -0700

drm/i915: make PM interrupt writes non-destructive

for why the gen6 code (shared between snb, ivb and hsw) needed to be
changed originally.

v3: Improve the commit message to more clearly spell out why we want
to unify the code and what exactly changes.

Cc: Paulo Zanoni 
Cc: Ben Widawsky 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/intel_pm.c | 59 -
 1 file changed, 29 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e609232..190ab96 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3121,13 +3121,10 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
 }
 
-
-static void gen6_disable_rps(struct drm_device *dev)
+static void gen6_disable_rps_interrupts(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   I915_WRITE(GEN6_RC_CONTROL, 0);
-   I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_PMINTRMSK, 0x);
I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
/* Complete PM interrupt masking here doesn't race with the rps work
@@ -3142,23 +3139,23 @@ static void gen6_disable_rps(struct drm_device *dev)
I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
 }
 
-static void valleyview_disable_rps(struct drm_device *dev)
+static void gen6_disable_rps(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
I915_WRITE(GEN6_RC_CONTROL, 0);
-   I915_WRITE(GEN6_PMINTRMSK, 0x);
-   I915_WRITE(GEN6_PMIER, 0);
-   /* Complete PM interrupt masking here doesn't race with the rps work
-* item again unmasking PM interrupts because that is using a different
-* register (PMIMR) to mask PM interrupts. The only risk is in leaving
-* stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
+   I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 
-   spin_lock_irq(&dev_priv->irq_lock);
-   dev_priv->rps.pm_iir = 0;
-   spin_unlock_irq(&dev_priv->irq_lock);
+   gen6_disable_rps_interrupts(dev);
+}
+
+static void valleyview_disable_rps(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   I915_WRITE(GEN6_RC_CONTROL, 0);
 
-   I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
+   gen6_disable_rps_interrupts(dev);
 
if (dev_priv->vlv_pctx) {
drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
@@ -3191,6 +3188,21 @@ int intel_enable_rc6(const struct drm_device *dev)
return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
 }
 
+static void gen6_enable_rps_interrupts(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   spin_lock_irq(&dev_priv->irq_lock);
+   /* FIXME: Our interrupt enabling sequence is bonghits.
+* dev_priv->rps.pm_iir really should be 0 here. */
+   dev_priv->rps.pm_iir = 0;
+   I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
+   I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
+   spin_unlock_irq(&dev_priv->irq_lock);
+   /* unmask all PM interrupts */
+   I915_WRITE(GEN6_PMINTRMSK, 0);
+}
+
 static void gen6_enable_rps(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3319,15 +3331,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 
gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
 
-   spin_lock_irq(&dev_priv->irq_lock);
-   /* FIXME: Our interrupt enabling sequence is bonghits.
-* dev_priv->rps.pm_iir really should be 0 here. */
-   dev_priv->rps.pm_iir = 0;
-   I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
-   I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
-   spin_unlock_irq(&dev_priv->irq_lock);
-   /* unmask all PM interrupts */
-   I915_WRITE(GEN6_PMINTRMSK, 0);
+   gen6_enable_rps_interrupts(dev);
 
rc6

[Intel-gfx] [PATCH 2/3] drm/i915: unify GT/PM irq postinstall code

[Daniel Vetter]

Again extract a common helper. For the postinstall hook things are a
bit more complicated since we have more cases on ilk-hsw/vlv here.

But since vlv was clearly broken by failing to initialize
dev_priv->gt_irq_mask correctly the shared code is clearly justified.

Also kill the PMIER setting in the async rps enable work. I should
have been save, but also clearly looked rather fragile. PMIER setup is
not all down in the irq pre/postinstall hooks.

With this we now have the usual interrupt register sequence for GT/PM
irq registers:

- IER is setup once with all the interrupts we ever need in the
  postinstall hook and never touched again. Exceptions are SDEIER,
  which is touched in the preinstall hook (when the irq handler isn't
  enabled) and then only from the irq handler. And DEIER/VLV_IER with
  is used in the irq handler but also written to once in the
  postinstall hook. But since that write is essentially what enables
  the interrupt and we should always have MSI interrupts we should be
  save. In case we ever have non-MSI interrupts we'd be screwed.

- IIR is cleared in the postinstall hook before we enable/unmask the
  respective interrupt sources. Hence we can't steal an interrupt
  event an accidentally trigger the spurious interrupt logic in the
  core kernel. Note that after some discussion with Ben Widawsky we
  think that we actually should clear the IIR registers in the
  preinstall hook. But doing that is a much larger patch series.

- IMR regs are (usually) all masked off. Those are the only regs
  changed at runtime, which is all protected by dev_priv->irq_lock.

This unification also kills the cargo-culted read-modify-write PM
register setup for VECS. Interrupt setup is done without userspace
being able to interfere, so we better know what values we want to put
into those registers. RMW cycles otoh are really good at papering over
races, until stuff magically blows up and no one has a clue why.

v2: Touch the gen6+ PM interrupt registers only on gen6+.

v3: Improve the commit message to more clearly spell out why we want
to unify the code and what exactly changes.

Cc: Ben Widawsky 
Cc: Paulo Zanoni 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_irq.c | 92 +++--
 drivers/gpu/drm/i915/intel_pm.c |  4 --
 2 files changed, 42 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d5c3bef..ba61bc7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2725,6 +2725,45 @@ static void ibx_irq_postinstall(struct drm_device *dev)
I915_WRITE(SDEIMR, ~mask);
 }
 
+static void gen5_gt_irq_postinstall(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u32 pm_irqs, gt_irqs;
+
+   pm_irqs = gt_irqs = 0;
+
+   dev_priv->gt_irq_mask = ~0;
+   if (HAS_L3_GPU_CACHE(dev)) {
+   dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+   gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+   }
+
+   gt_irqs |= GT_RENDER_USER_INTERRUPT;
+   if (IS_GEN5(dev)) {
+   gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
+  ILK_BSD_USER_INTERRUPT;
+   } else {
+   gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
+   }
+
+   I915_WRITE(GTIIR, I915_READ(GTIIR));
+   I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+   I915_WRITE(GTIER, gt_irqs);
+   POSTING_READ(GTIER);
+
+   if (INTEL_INFO(dev)->gen >= 6) {
+   pm_irqs |= GEN6_PM_RPS_EVENTS;
+
+   if (HAS_VEBOX(dev))
+   pm_irqs |= PM_VEBOX_USER_INTERRUPT;
+
+   I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
+   I915_WRITE(GEN6_PMIMR, 0x);
+   I915_WRITE(GEN6_PMIER, pm_irqs);
+   POSTING_READ(GEN6_PMIER);
+   }
+}
+
 static int ironlake_irq_postinstall(struct drm_device *dev)
 {
unsigned long irqflags;
@@ -2735,7 +2774,6 @@ static int ironlake_irq_postinstall(struct drm_device 
*dev)
   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
   DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
   DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
-   u32 gt_irqs;
 
dev_priv->irq_mask = ~display_mask;
 
@@ -2746,21 +2784,7 @@ static int ironlake_irq_postinstall(struct drm_device 
*dev)
  DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
POSTING_READ(DEIER);
 
-   dev_priv->gt_irq_mask = ~0;
-
-   I915_WRITE(GTIIR, I915_READ(GTIIR));
-   I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
-
-   gt_irqs = GT_RENDER_USER_INTERRUPT;
-
-   if (IS_GEN6(dev))
-   gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
-   else
-   gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
-  ILK_BSD_USER_INTERR

[Intel-gfx] [PATCH 1/3] drm/i915: unify PM interrupt preinstall sequence

[Daniel Vetter]

Since the addition of VECS we have a slightly different enable
sequence for PM interrupts on ivb/hsw vs snb and vlv. Usually that
will end up in hard to track down surprises.

Hence unifiy things and since we have copies of this code in 3 places
now, extract it into its own little helper.

Note that this changes the irq preinstall sequence a bit for snb and
vlv: We now also clear the PM registers in the preinstall hook, in
addition to the PM register clearing/setup already done when actually
enabling rps. So this doesn't fix a bug but simply unifies the code
across all platforms. After the postinstall hook is similarly unified
we can rip out the then redundant PM interrupt setup from the rps
code.

v3: Rebase on top of the retained double-GTIIR clearing. Also
resurrect the masking/disabling of the gen6+ PM interrupts as spotted
by Ben Widaswky.

v4: Move the DE interrupt reset code out of gen5_gt_irq_preinstall
back to ironlake_irq_preinstall where it really belongs. Spotted by
Paulo.

v3: Improve the commit message to more clearly spell out why we want
to unify the code and what exactly changes.

Cc: Paulo Zanoni 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_irq.c | 39 +--
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cf1a21a..d5c3bef 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2583,6 +2583,23 @@ static void ibx_irq_preinstall(struct drm_device *dev)
POSTING_READ(SDEIER);
 }
 
+static void gen5_gt_irq_preinstall(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   /* and GT */
+   I915_WRITE(GTIMR, 0x);
+   I915_WRITE(GTIER, 0x0);
+   POSTING_READ(GTIER);
+
+   if (INTEL_INFO(dev)->gen >= 6) {
+   /* and GT */
+   I915_WRITE(GEN6_PMIMR, 0x);
+   I915_WRITE(GEN6_PMIER, 0x0);
+   POSTING_READ(GEN6_PMIER);
+   }
+}
+
 /* drm_dma.h hooks
 */
 static void ironlake_irq_preinstall(struct drm_device *dev)
@@ -2593,16 +2610,11 @@ static void ironlake_irq_preinstall(struct drm_device 
*dev)
 
I915_WRITE(HWSTAM, 0xeffe);
 
-   /* XXX hotplug from PCH */
-
I915_WRITE(DEIMR, 0x);
I915_WRITE(DEIER, 0x0);
POSTING_READ(DEIER);
 
-   /* and GT */
-   I915_WRITE(GTIMR, 0x);
-   I915_WRITE(GTIER, 0x0);
-   POSTING_READ(GTIER);
+   gen5_gt_irq_preinstall(dev);
 
ibx_irq_preinstall(dev);
 }
@@ -2621,15 +2633,7 @@ static void ivybridge_irq_preinstall(struct drm_device 
*dev)
I915_WRITE(DEIER, 0x0);
POSTING_READ(DEIER);
 
-   /* and GT */
-   I915_WRITE(GTIMR, 0x);
-   I915_WRITE(GTIER, 0x0);
-   POSTING_READ(GTIER);
-
-   /* Power management */
-   I915_WRITE(GEN6_PMIMR, 0x);
-   I915_WRITE(GEN6_PMIER, 0x0);
-   POSTING_READ(GEN6_PMIER);
+   gen5_gt_irq_preinstall(dev);
 
ibx_irq_preinstall(dev);
 }
@@ -2650,9 +2654,8 @@ static void valleyview_irq_preinstall(struct drm_device 
*dev)
/* and GT */
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIIR, I915_READ(GTIIR));
-   I915_WRITE(GTIMR, 0x);
-   I915_WRITE(GTIER, 0x0);
-   POSTING_READ(GTIER);
+
+   gen5_gt_irq_preinstall(dev);
 
I915_WRITE(DPINVGTT, 0xff);
 
-- 
1.8.1.4

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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Serialize all register access

[Ben Widawsky]

On Fri, Jul 12, 2013 at 03:02:34PM +0100, Chris Wilson wrote:
> In theory, the different register blocks were meant to be only ever
> touched when holding either the struct_mutex, mode_config.lock or even a
> specific localised lock. This does not seem to be the case, and the
> hardware reacts extremely badly if we attempt to concurrently access two
> registers within the same cacheline.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63914
> Signed-off-by: Chris Wilson 

You are crossing the point of no return here for doing this only on HSW
where the bug is known to exist. As you are the resident performance
curmudgeon I'll defer to you if that's okay or not... just pointing it
out.

> ---
>  drivers/gpu/drm/i915/intel_gt.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
> index d4bc7f4..e89e901 100644
> --- a/drivers/gpu/drm/i915/intel_gt.c
> +++ b/drivers/gpu/drm/i915/intel_gt.c
> @@ -331,21 +331,21 @@ hsw_unclaimed_reg_check(struct drm_i915_private 
> *dev_priv, u32 reg)
>  
>  #define __i915_read(x, y) \
>  u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
> + unsigned long irqflags; \
>   u##x val = 0; \
> + spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
>   if (IS_GEN5(dev_priv->dev)) \
>   ilk_dummy_write(dev_priv); \
>   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
> - unsigned long irqflags; \
> - spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
>   if (dev_priv->forcewake_count == 0) \
>   dev_priv->gt.force_wake_get(dev_priv); \
>   val = read##y(dev_priv->regs + reg); \
>   if (dev_priv->forcewake_count == 0) \
>   dev_priv->gt.force_wake_put(dev_priv); \
> - spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
>   } else { \
>   val = read##y(dev_priv->regs + reg); \
>   } \
> + spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
>   if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
>   return val; \
>  }
> @@ -358,8 +358,10 @@ __i915_read(64, q)
>  
>  #define __i915_write(x, y) \
>  void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, 
> bool trace) { \
> + unsigned long irqflags; \
>   u32 __fifo_ret = 0; \
>   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
> + spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
>   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
>   __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
>   } \
> @@ -371,6 +373,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 
> reg, u##x val, bool tr
>   gen6_gt_check_fifodbg(dev_priv); \
>   } \
>   hsw_unclaimed_reg_check(dev_priv, reg); \
> + spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
>  }
>  __i915_write(8, b)
>  __i915_write(16, w)
> -- 
> 1.8.3.2
> 
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-- 
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Use the common register access functions for NOTRACE variants

[Ben Widawsky]

On Fri, Jul 12, 2013 at 03:02:33PM +0100, Chris Wilson wrote:
> Detangle the confusion that NOTRACE variants of the register read/write
> routines were directly using the raw register access. We need for those
> routines to reuse the common code for serializing register access and
> ensuring the correct register power states. This is only possible now
> that the only routines that required raw access use their own API.
> 
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 28 ++--
>  drivers/gpu/drm/i915/intel_gt.c |  8 
>  2 files changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f140b04..1ab6d4e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2082,7 +2082,7 @@ int vlv_gpu_freq(int ddr_freq, int val);
>  int vlv_freq_opcode(int ddr_freq, int val);
>  
>  #define __i915_read(x, y) \
> - u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
> + u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool 
> trace);
>  
>  __i915_read(8, b)
>  __i915_read(16, w)
> @@ -2091,7 +2091,7 @@ __i915_read(64, q)
>  #undef __i915_read
>  
>  #define __i915_write(x, y) \
> - void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
> val);
> + void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
> val, bool trace);
>  
>  __i915_write(8, b)
>  __i915_write(16, w)
> @@ -2099,21 +2099,21 @@ __i915_write(32, l)
>  __i915_write(64, q)
>  #undef __i915_write
>  
> -#define I915_READ8(reg)  i915_read8(dev_priv, (reg))
> -#define I915_WRITE8(reg, val)i915_write8(dev_priv, (reg), (val))
> +#define I915_READ8(reg)  i915_read8(dev_priv, (reg), true)
> +#define I915_WRITE8(reg, val)i915_write8(dev_priv, (reg), (val), 
> true)
>  
> -#define I915_READ16(reg) i915_read16(dev_priv, (reg))
> -#define I915_WRITE16(reg, val)   i915_write16(dev_priv, (reg), (val))
> -#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
> -#define I915_WRITE16_NOTRACE(reg, val)   writew(val, dev_priv->regs + 
> (reg))
> +#define I915_READ16(reg) i915_read16(dev_priv, (reg), true)
> +#define I915_WRITE16(reg, val)   i915_write16(dev_priv, (reg), (val), 
> true)
> +#define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false)
> +#define I915_WRITE16_NOTRACE(reg, val)   i915_write16(dev_priv, (reg), 
> (val), false)
>  
> -#define I915_READ(reg)   i915_read32(dev_priv, (reg))
> -#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
> -#define I915_READ_NOTRACE(reg)   readl(dev_priv->regs + (reg))
> -#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
> +#define I915_READ(reg)   i915_read32(dev_priv, (reg), true)
> +#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true)
> +#define I915_READ_NOTRACE(reg)   i915_read32(dev_priv, (reg), 
> false)
> +#define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), 
> false)
>  
> -#define I915_WRITE64(reg, val)   i915_write64(dev_priv, (reg), (val))
> -#define I915_READ64(reg) i915_read64(dev_priv, (reg))
> +#define I915_WRITE64(reg, val)   i915_write64(dev_priv, (reg), (val), 
> true)
> +#define I915_READ64(reg) i915_read64(dev_priv, (reg), true)
>  
>  #define POSTING_READ(reg)(void)I915_READ_NOTRACE(reg)
>  #define POSTING_READ16(reg)  (void)I915_READ16_NOTRACE(reg)
> diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
> index cb3116c..d4bc7f4 100644
> --- a/drivers/gpu/drm/i915/intel_gt.c
> +++ b/drivers/gpu/drm/i915/intel_gt.c
> @@ -330,7 +330,7 @@ hsw_unclaimed_reg_check(struct drm_i915_private 
> *dev_priv, u32 reg)
>  }
>  
>  #define __i915_read(x, y) \
> -u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
> +u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
>   u##x val = 0; \
>   if (IS_GEN5(dev_priv->dev)) \
>   ilk_dummy_write(dev_priv); \
> @@ -346,7 +346,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
> reg) { \
>   } else { \
>   val = read##y(dev_priv->regs + reg); \
>   } \
> - trace_i915_reg_rw(false, reg, val, sizeof(val)); \
> + if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
>   return val; \
>  }
>  
> @@ -357,9 +357,9 @@ __i915_read(64, q)
>  #undef __i915_read
>  
>  #define __i915_write(x, y) \
> -void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
> +void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, 
> bool trace) { \
>   u32 __fifo_ret = 0; \
> - trace_i915_reg_rw(true, reg, val, sizeof(val)); \
> + if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
>   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
>   

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Use a private interface for register access within GT

[Ben Widawsky]

On Fri, Jul 12, 2013 at 03:02:32PM +0100, Chris Wilson wrote:
> The GT functions for enabling register access also need to occasionally
> write to and read from registers. To avoid the potential recursion as we
> modify the public interface to be stricter, introduce a private register
> access API for the GT functions.
> 
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/intel_gt.c | 92 
> +
>  1 file changed, 56 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
> index 060e256..cb3116c 100644
> --- a/drivers/gpu/drm/i915/intel_gt.c
> +++ b/drivers/gpu/drm/i915/intel_gt.c
> @@ -26,6 +26,19 @@
>  
>  #define FORCEWAKE_ACK_TIMEOUT_MS 2
>  
> +#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + 
> (reg__))
> +#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, 
> (dev_priv__)->regs + (reg__))
> +
> +#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + 
> (reg__))
> +#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, 
> (dev_priv__)->regs + (reg__))
> +
> +#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
> (reg__))
> +#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
> (dev_priv__)->regs + (reg__))

Instead of what you did, I would have preferred
#define __raw_posting_read

Also, I don't mind dev_priv as an implicit arg, but I know Daniel has
complained about such things before.

positive (I didn't check for missed conversions)
Reviewed-by: Ben Widawsky 

> +
> +#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + 
> (reg__))
> +#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, 
> (dev_priv__)->regs + (reg__))
> +
> +
>  static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
>  {
>   u32 gt_thread_status_mask;
> @@ -38,26 +51,27 @@ static void __gen6_gt_wait_for_thread_c0(struct 
> drm_i915_private *dev_priv)
>   /* w/a for a sporadic read returning 0 by waiting for the GT
>* thread to wake up.
>*/
> - if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & 
> gt_thread_status_mask) == 0, 500))
> + if (wait_for_atomic_us((__raw_i915_read32(dev_priv, 
> GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
>   DRM_ERROR("GT thread status wait timed out\n");
>  }
>  
>  static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
>  {
> - I915_WRITE_NOTRACE(FORCEWAKE, 0);
> - POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
> */
> + __raw_i915_write32(dev_priv, FORCEWAKE, 0);
> + /* something from same cacheline, but !FORCEWAKE */
> + (void)__raw_i915_read32(dev_priv, ECOBUS);
>  }
>  
>  static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
>  {
> - if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
> + if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 
> 0,
>   FORCEWAKE_ACK_TIMEOUT_MS))
>   DRM_ERROR("Timed out waiting for forcewake old ack to 
> clear.\n");
>  
> - I915_WRITE_NOTRACE(FORCEWAKE, 1);
> - POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
> */
> + __raw_i915_write32(dev_priv, FORCEWAKE, 1);
> + (void)__raw_i915_read32(dev_priv, ECOBUS); /* something from same 
> cacheline, but !FORCEWAKE */
>  
> - if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
> + if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
>   FORCEWAKE_ACK_TIMEOUT_MS))
>   DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
>  
> @@ -67,9 +81,9 @@ static void __gen6_gt_force_wake_get(struct 
> drm_i915_private *dev_priv)
>  
>  static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
>  {
> - I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
> + __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
>   /* something from same cacheline, but !FORCEWAKE_MT */
> - POSTING_READ(ECOBUS);
> + (void)__raw_i915_read32(dev_priv, ECOBUS);
>  }
>  
>  static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
> @@ -81,15 +95,16 @@ static void __gen6_gt_force_wake_mt_get(struct 
> drm_i915_private *dev_priv)
>   else
>   forcewake_ack = FORCEWAKE_MT_ACK;
>  
> - if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 
> FORCEWAKE_KERNEL) == 0,
> + if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & 
> FORCEWAKE_KERNEL) == 0,
>   FORCEWAKE_ACK_TIMEOUT_MS))
>   DRM_ERROR("Timed out waiting for forcewake old ack to 
> clear.\n");
>  
> - I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
> + __raw_i915_write32(dev_priv, FORCEWAKE_MT,
> +   

Re: [Intel-gfx] [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios

[Daniel Vetter]

On Fri, Jul 12, 2013 at 10:03 PM, Stéphane Marchesin
 wrote:
> Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes
> on eDP. This fixes eDP on hsw with > 2 lanes.
>
> Signed-off-by: Stéphane Marchesin 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  drivers/gpu/drm/i915/intel_dp.c  | 5 +++--
>  2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 324211a..5e3f97b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1348,7 +1348,7 @@ void intel_ddi_init(struct drm_device *dev, enum port 
> port)
>
> intel_dig_port->port = port;
> intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
> -   DDI_BUF_PORT_REVERSAL;
> +   (DDI_BUF_PORT_REVERSAL | 
> DDI_A_4_LANES);

I think we should do a s/port_reversal/saved_port_bits/ since the
current name is confusing.

> intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
>
> intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b739712..a1d838c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -834,10 +834,11 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
> drm_display_mode *mode,
>  * configuration happens (oddly) in ironlake_pch_enable
>  */
>
> -   /* Preserve the BIOS-computed detected bit. This is
> +   /* Preserve the BIOS-computed detected and 4 lanes bits. This is
>  * supposed to be read-only.
>  */
> -   intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
> +   intel_dp->DP = I915_READ(intel_dp->output_reg) &
> +  (DP_DETECTED | DDI_A_4_LANES);

Why is this hunk here required? It seems to not be needed for the port
reversal stuff, and this code here is run on all platforms ... If
possible I'd like to just ditch it.
-Daniel

>
> /* Handle DP bits in common between all three register formats */
> intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
> --
> 1.8.3
>
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--
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Re: [Intel-gfx] [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios

[Jesse Barnes]

On Fri, 12 Jul 2013 13:03:46 -0700
Stéphane Marchesin  wrote:

> Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes
> on eDP. This fixes eDP on hsw with > 2 lanes.
> 
> Signed-off-by: Stéphane Marchesin 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  drivers/gpu/drm/i915/intel_dp.c  | 5 +++--
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 324211a..5e3f97b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1348,7 +1348,7 @@ void intel_ddi_init(struct drm_device *dev, enum port 
> port)
>  
>   intel_dig_port->port = port;
>   intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
> - DDI_BUF_PORT_REVERSAL;
> + (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
>   intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
>  
>   intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b739712..a1d838c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -834,10 +834,11 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
> drm_display_mode *mode,
>* configuration happens (oddly) in ironlake_pch_enable
>*/
>  
> - /* Preserve the BIOS-computed detected bit. This is
> + /* Preserve the BIOS-computed detected and 4 lanes bits. This is
>* supposed to be read-only.
>*/
> - intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
> + intel_dp->DP = I915_READ(intel_dp->output_reg) &
> +(DP_DETECTED | DDI_A_4_LANES);
>  
>   /* Handle DP bits in common between all three register formats */
>   intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

Thanks.  Wonder if we're clobbering any other "BIOS must set this bit
and no one should touch it again" bits elsewhere...

Reviewed-by: Jesse Barnes 

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[Intel-gfx] [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios

[Stéphane Marchesin]

Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes
on eDP. This fixes eDP on hsw with > 2 lanes.

Signed-off-by: Stéphane Marchesin 
---
 drivers/gpu/drm/i915/intel_ddi.c | 2 +-
 drivers/gpu/drm/i915/intel_dp.c  | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 324211a..5e3f97b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1348,7 +1348,7 @@ void intel_ddi_init(struct drm_device *dev, enum port 
port)
 
intel_dig_port->port = port;
intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
-   DDI_BUF_PORT_REVERSAL;
+   (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
 
intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b739712..a1d838c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -834,10 +834,11 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
 * configuration happens (oddly) in ironlake_pch_enable
 */
 
-   /* Preserve the BIOS-computed detected bit. This is
+   /* Preserve the BIOS-computed detected and 4 lanes bits. This is
 * supposed to be read-only.
 */
-   intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
+   intel_dp->DP = I915_READ(intel_dp->output_reg) &
+  (DP_DETECTED | DDI_A_4_LANES);
 
/* Handle DP bits in common between all three register formats */
intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
-- 
1.8.3

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Re: [Intel-gfx] [PATCH 10/10] drm/i915: kill ivybridge_irq_postinstall

[Chris Wilson]

On Fri, Jul 12, 2013 at 04:35:18PM -0300, Paulo Zanoni wrote:
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0ad409a..ff3fb6d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2169,21 +2169,33 @@ static void gen5_gt_irq_postinstall(struct drm_device 
> *dev)
>  static int ironlake_irq_postinstall(struct drm_device *dev)
>  {
>   unsigned long irqflags;
> -
>   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> - /* enable kind of interrupts always enabled */
> - u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
> -DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
> -DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
> -DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
> + u32 display_mask, extra_mask;
> +
> + if (INTEL_INFO(dev)->gen >= 7) {
> + display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |

If you add a leading bracket here, you make at least one vim user much
happier.
-Chris

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Re: [Intel-gfx] [PATCH 08/10] drm/i915: kill ivybridge_enable_vblank

[Chris Wilson]

On Fri, Jul 12, 2013 at 04:35:16PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni 
> 
> It's the same thing as ironlake_enable_vblank, with the exception of
> the bit register, so add IVB/HSW support to ironlake_enable_vblank and
> kill ivybridge_enable_vblank.

If you are a little more creative, you can make the two paths look even
move alike.
-Chris

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Re: [Intel-gfx] [PATCH 05/10] drm/i915: reorganize ironlake_irq_handler

[Chris Wilson]

On Fri, Jul 12, 2013 at 04:35:13PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni 
> 
> The ironlake_irq_handler and ivybridge_irq_handler functions do
> basically the same thing, but they have different implementation
> styles. With this patch we reorganize ironlake_irq_handler in a way
> that makes it look very similar to ivybridge_irq_handler.
> 
> One of the advantages of this new function style is that we don't
> write 0 to the IIR registers anymore.

Please tightly scope the variables where applicable.
-Chris

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[Intel-gfx] Updated drm-intel-testing tree

[Daniel Vetter]

Hi all,

So new testing cycle! Due to rebasing stuff around it's there's almost
some patches from the previous cycle in the git log. But recollecting from
memory we have here:
- First slice of real ppgtt prep stuff from Ben.
- error state in sysfs and independent of CONFIG_DEBUG_FS (Mika)
- interrupt handling code improvements
- and an assorted pile of smaller stuff

In other words: Not much, people are on vacation ;-)

Happy testing!

Cheers, Daniel
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Re: [Intel-gfx] [PATCH 04/10] drm/i915: don't read or write GEN6_PMIIR on Gen 5

[Chris Wilson]

On Fri, Jul 12, 2013 at 04:35:12PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni 
> 
> The register doesn't exist on Gen 5.

Whilst you are fixing that, initialize pm_iir = 0 and simply the later
checks.
-Chris

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[Intel-gfx] [PATCH 10/10] drm/i915: kill ivybridge_irq_postinstall

[Paulo Zanoni]

From: Paulo Zanoni 

It was very similar to ironlake_irq_postinstall, so IMHO merging both
functions results in a code that is easier to maintain.

With this change, all the irq handler vfuncs between ironlake and
ivybridge are now unified.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 69 -
 1 file changed, 20 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0ad409a..ff3fb6d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2169,21 +2169,33 @@ static void gen5_gt_irq_postinstall(struct drm_device 
*dev)
 static int ironlake_irq_postinstall(struct drm_device *dev)
 {
unsigned long irqflags;
-
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   /* enable kind of interrupts always enabled */
-   u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
-  DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
-  DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
-  DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
+   u32 display_mask, extra_mask;
+
+   if (INTEL_INFO(dev)->gen >= 7) {
+   display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
+  DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
+  DE_PLANEB_FLIP_DONE_IVB |
+  DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
+  DE_ERR_INT_IVB;
+   extra_mask = DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
+DE_PIPEA_VBLANK_IVB;
+
+   I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
+   } else {
+   display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
+  DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
+  DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
+  DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
+   extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
+   }
 
dev_priv->irq_mask = ~display_mask;
 
/* should always can generate irq */
I915_WRITE(DEIIR, I915_READ(DEIIR));
I915_WRITE(DEIMR, dev_priv->irq_mask);
-   I915_WRITE(DEIER, display_mask |
- DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
+   I915_WRITE(DEIER, display_mask | extra_mask);
POSTING_READ(DEIER);
 
gen5_gt_irq_postinstall(dev);
@@ -2204,38 +2216,6 @@ static int ironlake_irq_postinstall(struct drm_device 
*dev)
return 0;
 }
 
-static int ivybridge_irq_postinstall(struct drm_device *dev)
-{
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   /* enable kind of interrupts always enabled */
-   u32 display_mask =
-   DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
-   DE_PLANEC_FLIP_DONE_IVB |
-   DE_PLANEB_FLIP_DONE_IVB |
-   DE_PLANEA_FLIP_DONE_IVB |
-   DE_AUX_CHANNEL_A_IVB |
-   DE_ERR_INT_IVB;
-
-   dev_priv->irq_mask = ~display_mask;
-
-   /* should always can generate irq */
-   I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
-   I915_WRITE(DEIIR, I915_READ(DEIIR));
-   I915_WRITE(DEIMR, dev_priv->irq_mask);
-   I915_WRITE(DEIER,
-  display_mask |
-  DE_PIPEC_VBLANK_IVB |
-  DE_PIPEB_VBLANK_IVB |
-  DE_PIPEA_VBLANK_IVB);
-   POSTING_READ(DEIER);
-
-   gen5_gt_irq_postinstall(dev);
-
-   ibx_irq_postinstall(dev);
-
-   return 0;
-}
-
 static int valleyview_irq_postinstall(struct drm_device *dev)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -3044,15 +3024,6 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->enable_vblank = valleyview_enable_vblank;
dev->driver->disable_vblank = valleyview_disable_vblank;
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
-   } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
-   /* Share uninstall handlers with ILK/SNB */
-   dev->driver->irq_handler = ironlake_irq_handler;
-   dev->driver->irq_preinstall = ironlake_irq_preinstall;
-   dev->driver->irq_postinstall = ivybridge_irq_postinstall;
-   dev->driver->irq_uninstall = ironlake_irq_uninstall;
-   dev->driver->enable_vblank = ironlake_enable_vblank;
-   dev->driver->disable_vblank = ironlake_disable_vblank;
-   dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
} else if (HAS_PCH_SPLIT(dev)) {
dev->driver->irq_handler = ironlake_irq_handler;
dev->driver->irq_preinstall = ironlake_irq_preinstall;
-- 
1.8.1

[Intel-gfx] [PATCH 09/10] drm/i915: kill ivybridge_disable_vblank

[Paulo Zanoni]

From: Paulo Zanoni 

Same reasons as ivybridge_enable_vblank.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 20 +++-
 1 file changed, 7 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d26bbb3..0ad409a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1725,21 +1725,15 @@ static void ironlake_disable_vblank(struct drm_device 
*dev, int pipe)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
+   uint32_t bit;
 
-   spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
-DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
-   spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-}
-
-static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
-{
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   unsigned long irqflags;
+   if (INTEL_INFO(dev)->gen >= 7)
+   bit = DE_PIPEA_VBLANK_IVB << (pipe * 5);
+   else
+   bit = (pipe == 0) ? DE_PIPEA_VBLANK : DE_PIPEB_VBLANK;
 
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_disable_display_irq(dev_priv,
-DE_PIPEA_VBLANK_IVB << (pipe * 5));
+   ironlake_disable_display_irq(dev_priv, bit);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
@@ -3057,7 +3051,7 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->irq_postinstall = ivybridge_irq_postinstall;
dev->driver->irq_uninstall = ironlake_irq_uninstall;
dev->driver->enable_vblank = ironlake_enable_vblank;
-   dev->driver->disable_vblank = ivybridge_disable_vblank;
+   dev->driver->disable_vblank = ironlake_disable_vblank;
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
} else if (HAS_PCH_SPLIT(dev)) {
dev->driver->irq_handler = ironlake_irq_handler;
-- 
1.8.1.2

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[Intel-gfx] [PATCH 08/10] drm/i915: kill ivybridge_enable_vblank

[Paulo Zanoni]

From: Paulo Zanoni 

It's the same thing as ironlake_enable_vblank, with the exception of
the bit register, so add IVB/HSW support to ironlake_enable_vblank and
kill ivybridge_enable_vblank.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 25 +++--
 1 file changed, 7 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3d49f0f..d26bbb3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1663,29 +1663,18 @@ static int ironlake_enable_vblank(struct drm_device 
*dev, int pipe)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
+   uint32_t bit;
 
if (!i915_pipe_enabled(dev, pipe))
return -EINVAL;
 
-   spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
-   DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
-   spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-
-   return 0;
-}
-
-static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
-{
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   unsigned long irqflags;
-
-   if (!i915_pipe_enabled(dev, pipe))
-   return -EINVAL;
+   if (INTEL_INFO(dev)->gen >= 7)
+   bit = DE_PIPEA_VBLANK_IVB << (pipe * 5);
+   else
+   bit = (pipe == 0) ? DE_PIPEA_VBLANK : DE_PIPEB_VBLANK;
 
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   ironlake_enable_display_irq(dev_priv,
-   DE_PIPEA_VBLANK_IVB << (5 * pipe));
+   ironlake_enable_display_irq(dev_priv, bit);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
return 0;
@@ -3067,7 +3056,7 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->irq_preinstall = ironlake_irq_preinstall;
dev->driver->irq_postinstall = ivybridge_irq_postinstall;
dev->driver->irq_uninstall = ironlake_irq_uninstall;
-   dev->driver->enable_vblank = ivybridge_enable_vblank;
+   dev->driver->enable_vblank = ironlake_enable_vblank;
dev->driver->disable_vblank = ivybridge_disable_vblank;
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
} else if (HAS_PCH_SPLIT(dev)) {
-- 
1.8.1.2

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[Intel-gfx] [PATCH 07/10] drm/i915: add ILK/SNB support to ivybridge_irq_handler

[Paulo Zanoni]

From: Paulo Zanoni 

And then rename it to ironlake_irq_handler. Also move
ilk_gt_irq_handler up to avoid forward declarations.

In the previous patches I did small modifications to both
ironlake_irq_handler an ivybridge_irq_handler so they became very
similar functions. Now it should be very easy to verify that all we
need to add ILK/SNB support is to call ilk_gt_irq_handler, call
ilk_display_irq_handler and avoid reading pm_iir on gen 5.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 113 +++-
 1 file changed, 31 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bdaab93..3d49f0f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -849,6 +849,17 @@ static void ivybridge_parity_error_irq_handler(struct 
drm_device *dev)
queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 }
 
+static void ilk_gt_irq_handler(struct drm_device *dev,
+  struct drm_i915_private *dev_priv,
+  u32 gt_iir)
+{
+   if (gt_iir &
+   (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
+   notify_ring(dev, &dev_priv->ring[RCS]);
+   if (gt_iir & ILK_BSD_USER_INTERRUPT)
+   notify_ring(dev, &dev_priv->ring[VCS]);
+}
+
 static void snb_gt_irq_handler(struct drm_device *dev,
   struct drm_i915_private *dev_priv,
   u32 gt_iir)
@@ -1290,7 +1301,7 @@ static void ivb_display_irq_handler(struct drm_device 
*dev, u32 de_iir)
}
 }
 
-static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
+static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 {
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1334,27 +1345,34 @@ static irqreturn_t ivybridge_irq_handler(int irq, void 
*arg)
 
gt_iir = I915_READ(GTIIR);
if (gt_iir) {
-   snb_gt_irq_handler(dev, dev_priv, gt_iir);
+   if (IS_GEN5(dev))
+   ilk_gt_irq_handler(dev, dev_priv, gt_iir);
+   else
+   snb_gt_irq_handler(dev, dev_priv, gt_iir);
I915_WRITE(GTIIR, gt_iir);
ret = IRQ_HANDLED;
}
 
de_iir = I915_READ(DEIIR);
if (de_iir) {
-   ivb_display_irq_handler(dev, de_iir);
-
+   if (INTEL_INFO(dev)->gen <= 6)
+   ilk_display_irq_handler(dev, de_iir);
+   else
+   ivb_display_irq_handler(dev, de_iir);
I915_WRITE(DEIIR, de_iir);
ret = IRQ_HANDLED;
}
 
-   pm_iir = I915_READ(GEN6_PMIIR);
-   if (pm_iir) {
-   if (IS_HASWELL(dev))
-   hsw_pm_irq_handler(dev_priv, pm_iir);
-   else if (pm_iir & GEN6_PM_RPS_EVENTS)
-   gen6_rps_irq_handler(dev_priv, pm_iir);
-   I915_WRITE(GEN6_PMIIR, pm_iir);
-   ret = IRQ_HANDLED;
+   if (!IS_GEN5(dev)) {
+   pm_iir = I915_READ(GEN6_PMIIR);
+   if (pm_iir) {
+   if (IS_HASWELL(dev))
+   hsw_pm_irq_handler(dev_priv, pm_iir);
+   else if (pm_iir & GEN6_PM_RPS_EVENTS)
+   gen6_rps_irq_handler(dev_priv, pm_iir);
+   I915_WRITE(GEN6_PMIIR, pm_iir);
+   ret = IRQ_HANDLED;
+   }
}
 
if (IS_HASWELL(dev)) {
@@ -1374,75 +1392,6 @@ static irqreturn_t ivybridge_irq_handler(int irq, void 
*arg)
return ret;
 }
 
-static void ilk_gt_irq_handler(struct drm_device *dev,
-  struct drm_i915_private *dev_priv,
-  u32 gt_iir)
-{
-   if (gt_iir &
-   (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
-   notify_ring(dev, &dev_priv->ring[RCS]);
-   if (gt_iir & ILK_BSD_USER_INTERRUPT)
-   notify_ring(dev, &dev_priv->ring[VCS]);
-}
-
-static irqreturn_t ironlake_irq_handler(int irq, void *arg)
-{
-   struct drm_device *dev = (struct drm_device *) arg;
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-   int ret = IRQ_NONE;
-   u32 de_iir, gt_iir, de_ier, pm_iir = 0, sde_ier;
-
-   atomic_inc(&dev_priv->irq_received);
-
-   /* disable master interrupt before clearing iir  */
-   de_ier = I915_READ(DEIER);
-   I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
-   POSTING_READ(DEIER);
-
-   /* Disable south interrupts. We'll only write to SDEIIR once, so further
-* interrupts will will be stored on its back queue, and then we'll be
-* able to process them after we restore SDEIER (as soon as we restore
-* it

[Intel-gfx] [PATCH 06/10] drm/i915: POSTING_READ(DEIER) on ivybridge_irq_handler

[Paulo Zanoni]

From: Paulo Zanoni 

We have this POSTING_READ inside ironlake_irq_handler. I suppose we
also want it on IVB because we want to stop the IRQ handler as soon as
possible at this point.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7bc36ae..bdaab93 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1310,6 +1310,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void 
*arg)
/* disable master interrupt before clearing iir  */
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+   POSTING_READ(DEIER);
 
/* Disable south interrupts. We'll only write to SDEIIR once, so further
 * interrupts will will be stored on its back queue, and then we'll be
-- 
1.8.1.2

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[Intel-gfx] [PATCH 05/10] drm/i915: reorganize ironlake_irq_handler

[Paulo Zanoni]

From: Paulo Zanoni 

The ironlake_irq_handler and ivybridge_irq_handler functions do
basically the same thing, but they have different implementation
styles. With this patch we reorganize ironlake_irq_handler in a way
that makes it look very similar to ivybridge_irq_handler.

One of the advantages of this new function style is that we don't
write 0 to the IIR registers anymore.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 44 -
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 19370db..7bc36ae 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1407,33 +1407,33 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
I915_WRITE(SDEIER, 0);
POSTING_READ(SDEIER);
 
-   de_iir = I915_READ(DEIIR);
gt_iir = I915_READ(GTIIR);
-   if (IS_GEN6(dev))
-   pm_iir = I915_READ(GEN6_PMIIR);
-
-   if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
-   goto done;
-
-   ret = IRQ_HANDLED;
-
-   if (IS_GEN5(dev))
-   ilk_gt_irq_handler(dev, dev_priv, gt_iir);
-   else
-   snb_gt_irq_handler(dev, dev_priv, gt_iir);
+   if (gt_iir) {
+   if (IS_GEN5(dev))
+   ilk_gt_irq_handler(dev, dev_priv, gt_iir);
+   else
+   snb_gt_irq_handler(dev, dev_priv, gt_iir);
+   I915_WRITE(GTIIR, gt_iir);
+   ret = IRQ_HANDLED;
+   }
 
-   if (de_iir)
+   de_iir = I915_READ(DEIIR);
+   if (de_iir) {
ilk_display_irq_handler(dev, de_iir);
+   I915_WRITE(DEIIR, de_iir);
+   ret = IRQ_HANDLED;
+   }
 
-   if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
-   gen6_rps_irq_handler(dev_priv, pm_iir);
-
-   I915_WRITE(GTIIR, gt_iir);
-   I915_WRITE(DEIIR, de_iir);
-   if (IS_GEN6(dev))
-   I915_WRITE(GEN6_PMIIR, pm_iir);
+   if (IS_GEN6(dev)) {
+   pm_iir = I915_READ(GEN6_PMIIR);
+   if (pm_iir) {
+   if (pm_iir & GEN6_PM_RPS_EVENTS)
+   gen6_rps_irq_handler(dev_priv, pm_iir);
+   I915_WRITE(GEN6_PMIIR, pm_iir);
+   ret = IRQ_HANDLED;
+   }
+   }
 
-done:
I915_WRITE(DEIER, de_ier);
POSTING_READ(DEIER);
I915_WRITE(SDEIER, sde_ier);
-- 
1.8.1.2

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[Intel-gfx] [PATCH 04/10] drm/i915: don't read or write GEN6_PMIIR on Gen 5

[Paulo Zanoni]

From: Paulo Zanoni 

The register doesn't exist on Gen 5.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9167219..19370db 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1389,7 +1389,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int ret = IRQ_NONE;
-   u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
+   u32 de_iir, gt_iir, de_ier, pm_iir = 0, sde_ier;
 
atomic_inc(&dev_priv->irq_received);
 
@@ -1409,7 +1409,8 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
 
de_iir = I915_READ(DEIIR);
gt_iir = I915_READ(GTIIR);
-   pm_iir = I915_READ(GEN6_PMIIR);
+   if (IS_GEN6(dev))
+   pm_iir = I915_READ(GEN6_PMIIR);
 
if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
goto done;
@@ -1429,7 +1430,8 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
 
I915_WRITE(GTIIR, gt_iir);
I915_WRITE(DEIIR, de_iir);
-   I915_WRITE(GEN6_PMIIR, pm_iir);
+   if (IS_GEN6(dev))
+   I915_WRITE(GEN6_PMIIR, pm_iir);
 
 done:
I915_WRITE(DEIER, de_ier);
-- 
1.8.1.2

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[Intel-gfx] [PATCH 03/10] drm/i915: extract ivb_display_irq_handler

[Paulo Zanoni]

From: Paulo Zanoni 

Just like we did with ilk_display_irq_handler.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 63 +++--
 1 file changed, 35 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 39160a2..9167219 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1256,13 +1256,46 @@ static void ilk_display_irq_handler(struct drm_device 
*dev, u32 de_iir)
ironlake_rps_change_irq_handler(dev);
 }
 
+static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   int i;
+
+   if (de_iir & DE_ERR_INT_IVB)
+   ivb_err_int_handler(dev);
+
+   if (de_iir & DE_AUX_CHANNEL_A_IVB)
+   dp_aux_irq_handler(dev);
+
+   if (de_iir & DE_GSE_IVB)
+   intel_opregion_asle_intr(dev);
+
+   for (i = 0; i < 3; i++) {
+   if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
+   drm_handle_vblank(dev, i);
+   if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
+   intel_prepare_page_flip(dev, i);
+   intel_finish_page_flip_plane(dev, i);
+   }
+   }
+
+   /* check event from PCH */
+   if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
+   u32 pch_iir = I915_READ(SDEIIR);
+
+   cpt_irq_handler(dev, pch_iir);
+
+   /* clear PCH hotplug event before clear CPU irq */
+   I915_WRITE(SDEIIR, pch_iir);
+   }
+}
+
 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 {
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
irqreturn_t ret = IRQ_NONE;
-   int i;
 
atomic_inc(&dev_priv->irq_received);
 
@@ -1307,33 +1340,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void 
*arg)
 
de_iir = I915_READ(DEIIR);
if (de_iir) {
-   if (de_iir & DE_ERR_INT_IVB)
-   ivb_err_int_handler(dev);
-
-   if (de_iir & DE_AUX_CHANNEL_A_IVB)
-   dp_aux_irq_handler(dev);
-
-   if (de_iir & DE_GSE_IVB)
-   intel_opregion_asle_intr(dev);
-
-   for (i = 0; i < 3; i++) {
-   if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
-   drm_handle_vblank(dev, i);
-   if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
-   intel_prepare_page_flip(dev, i);
-   intel_finish_page_flip_plane(dev, i);
-   }
-   }
-
-   /* check event from PCH */
-   if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
-   u32 pch_iir = I915_READ(SDEIIR);
-
-   cpt_irq_handler(dev, pch_iir);
-
-   /* clear PCH hotplug event before clear CPU irq */
-   I915_WRITE(SDEIIR, pch_iir);
-   }
+   ivb_display_irq_handler(dev, de_iir);
 
I915_WRITE(DEIIR, de_iir);
ret = IRQ_HANDLED;
-- 
1.8.1.2

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[Intel-gfx] [PATCH 02/10] drm/i915: extract ilk_display_irq_handler

[Paulo Zanoni]

From: Paulo Zanoni 

It's the code that deals with de_iir.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 104 +---
 1 file changed, 56 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f397f9a..39160a2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1202,6 +1202,60 @@ static void cpt_irq_handler(struct drm_device *dev, u32 
pch_iir)
cpt_serr_int_handler(dev);
 }
 
+static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   if (de_iir & DE_AUX_CHANNEL_A)
+   dp_aux_irq_handler(dev);
+
+   if (de_iir & DE_GSE)
+   intel_opregion_asle_intr(dev);
+
+   if (de_iir & DE_PIPEA_VBLANK)
+   drm_handle_vblank(dev, 0);
+
+   if (de_iir & DE_PIPEB_VBLANK)
+   drm_handle_vblank(dev, 1);
+
+   if (de_iir & DE_POISON)
+   DRM_ERROR("Poison interrupt\n");
+
+   if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
+   if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
+   DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
+
+   if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
+   if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
+   DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
+
+   if (de_iir & DE_PLANEA_FLIP_DONE) {
+   intel_prepare_page_flip(dev, 0);
+   intel_finish_page_flip_plane(dev, 0);
+   }
+
+   if (de_iir & DE_PLANEB_FLIP_DONE) {
+   intel_prepare_page_flip(dev, 1);
+   intel_finish_page_flip_plane(dev, 1);
+   }
+
+   /* check event from PCH */
+   if (de_iir & DE_PCH_EVENT) {
+   u32 pch_iir = I915_READ(SDEIIR);
+
+   if (HAS_PCH_CPT(dev))
+   cpt_irq_handler(dev, pch_iir);
+   else
+   ibx_irq_handler(dev, pch_iir);
+
+   /* should clear PCH hotplug event before clear CPU irq */
+   I915_WRITE(SDEIIR, pch_iir);
+   }
+
+   if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
+   ironlake_rps_change_irq_handler(dev);
+}
+
 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 {
struct drm_device *dev = (struct drm_device *) arg;
@@ -1360,54 +1414,8 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
else
snb_gt_irq_handler(dev, dev_priv, gt_iir);
 
-   if (de_iir & DE_AUX_CHANNEL_A)
-   dp_aux_irq_handler(dev);
-
-   if (de_iir & DE_GSE)
-   intel_opregion_asle_intr(dev);
-
-   if (de_iir & DE_PIPEA_VBLANK)
-   drm_handle_vblank(dev, 0);
-
-   if (de_iir & DE_PIPEB_VBLANK)
-   drm_handle_vblank(dev, 1);
-
-   if (de_iir & DE_POISON)
-   DRM_ERROR("Poison interrupt\n");
-
-   if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
-   if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
-   DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
-
-   if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
-   if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
-   DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
-
-   if (de_iir & DE_PLANEA_FLIP_DONE) {
-   intel_prepare_page_flip(dev, 0);
-   intel_finish_page_flip_plane(dev, 0);
-   }
-
-   if (de_iir & DE_PLANEB_FLIP_DONE) {
-   intel_prepare_page_flip(dev, 1);
-   intel_finish_page_flip_plane(dev, 1);
-   }
-
-   /* check event from PCH */
-   if (de_iir & DE_PCH_EVENT) {
-   u32 pch_iir = I915_READ(SDEIIR);
-
-   if (HAS_PCH_CPT(dev))
-   cpt_irq_handler(dev, pch_iir);
-   else
-   ibx_irq_handler(dev, pch_iir);
-
-   /* should clear PCH hotplug event before clear CPU irq */
-   I915_WRITE(SDEIIR, pch_iir);
-   }
-
-   if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
-   ironlake_rps_change_irq_handler(dev);
+   if (de_iir)
+   ilk_display_irq_handler(dev, de_iir);
 
if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
gen6_rps_irq_handler(dev_priv, pm_iir);
-- 
1.8.1.2

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[Intel-gfx] [PATCH 01/10] drm/i915: kill ivybridge_irq_preinstall

[Paulo Zanoni]

From: Paulo Zanoni 

After Daniel's latest changes it's now equal to
ironlake_irq_preinstall.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_irq.c | 21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ca9df54..f397f9a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2090,25 +2090,6 @@ static void ironlake_irq_preinstall(struct drm_device 
*dev)
ibx_irq_preinstall(dev);
 }
 
-static void ivybridge_irq_preinstall(struct drm_device *dev)
-{
-   drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-
-   atomic_set(&dev_priv->irq_received, 0);
-
-   I915_WRITE(HWSTAM, 0xeffe);
-
-   /* XXX hotplug from PCH */
-
-   I915_WRITE(DEIMR, 0x);
-   I915_WRITE(DEIER, 0x0);
-   POSTING_READ(DEIER);
-
-   gen5_gt_irq_preinstall(dev);
-
-   ibx_irq_preinstall(dev);
-}
-
 static void valleyview_irq_preinstall(struct drm_device *dev)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -3116,7 +3097,7 @@ void intel_irq_init(struct drm_device *dev)
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
/* Share uninstall handlers with ILK/SNB */
dev->driver->irq_handler = ivybridge_irq_handler;
-   dev->driver->irq_preinstall = ivybridge_irq_preinstall;
+   dev->driver->irq_preinstall = ironlake_irq_preinstall;
dev->driver->irq_postinstall = ivybridge_irq_postinstall;
dev->driver->irq_uninstall = ironlake_irq_uninstall;
dev->driver->enable_vblank = ivybridge_enable_vblank;
-- 
1.8.1.2

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[Intel-gfx] [PATCH 00/10] Unify ILK/SNB/IVB/HSW IRQ vfuncs

[Paulo Zanoni]

From: Paulo Zanoni 

Hi

These patches apply on top of -nightly + 4 patches from Daniel Vetter (the 4
unmerged patches from his irq series v2). I imagine we're probably going to
merge them soon in their current form, so if we have conflicts, they will be
small.

The basic idea here is that the IRQ handling for ILK, SNB, IVB and HSW is
actually pretty similar. If you look at the current code it looks very
different, but after moving some gen-specific code to separate functions
everything gets really similar. So on this series I just merged all the vfuncs.

I imagine not everybody will like all the patches, so we could discard one or
two or all if there are objections. The biggest advantage is that we now have
less vfuncs to change whenever we want to do work on the interrupt code, and we
also have a smaller amount of total source code lines: 151 insertions and 249
deletions. Also, IMHO, the resulting code is easier to maintain.

Another argument in favor of merging all the vfuncs is, for example, a few of
Daniel's fixes from his last IRQ rework and the one or two bugs I fix in this
series. We had quite a few registers that were exactly the same on SNB/IVB/HSW,
but they were handled in completely different ways between SNB (which uses the
ILK IRQ handlers) and IVB/HSW (which use the IVB IRQ handlers).

Patches 2-7 were already sent to this mailing list, but they were not on top of
Daniel's IRQ rework, so the versions contained here are the new ones, and you
can discard that old series.

Flames, bikesheds?

Cheers,
Paulo

Paulo Zanoni (10):
  drm/i915: kill ivybridge_irq_preinstall
  drm/i915: extract ilk_display_irq_handler
  drm/i915: extract ivb_display_irq_handler
  drm/i915: don't read or write GEN6_PMIIR on Gen 5
  drm/i915: reorganize ironlake_irq_handler
  drm/i915: POSTING_READ(DEIER) on ivybridge_irq_handler
  drm/i915: add ILK/SNB support to ivybridge_irq_handler
  drm/i915: kill ivybridge_enable_vblank
  drm/i915: kill ivybridge_disable_vblank
  drm/i915: kill ivybridge_irq_postinstall

 drivers/gpu/drm/i915/i915_irq.c | 400 +++-
 1 file changed, 151 insertions(+), 249 deletions(-)

-- 
1.8.1.2

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Re: [Intel-gfx] [PATCH] drm/i915: Decrease pll->refcount when freeze gpu

[Jesse Barnes]

So this is a dupe of
https://bugs.freedesktop.org/show_bug.cgi?id=64379, which is a bit
trickier than just the switchless stuff, as it indicates we're not
tracking PLL state correctly...

I thought Daniel had patches for that; I know I had some for IVB, but
they didn't apply to HSW, and those have been made obsolete by patches
from Daniel that are upstream.  Maybe we're just missing hsw bits?

Jesse

On Fri, 12 Jul 2013 08:11:14 +
"Zhang, Xiong Y"  wrote:

> Hi Jesse:
>   I supply this patch because I encounter the S3 and S4 problem on Haswell 
> connecting VGA or HDMI screen.
>   Currently nobody call intel_ddi_put_crtc_pll() to decrease pll_refcount and 
> clear ddi_pll_sel when enter sleep states.
>   So when resume from sleep states, pll_refcount is larger than zero. mode 
> setting function will call intel_ddi_pll_mode_set().
>   Intel_ddi_pll_mode_set call intel_ddi_put_crtc_pll() first, then set pll 
> and increase pll-refcount. The results are:
>   1. S3 resume have call trace in intel_ddi_put_crtc_pll()
> If connecting vga, the call trace is "WARN_ON(!SPLL_PLL_ENABLE)"
> If connecting HDMI, the call trace is "WARN_ON(!WRPLL_PLL_ENABLE)"
>   2. S4 resume fail in intel_ddi_pll_mode_set()
> If connecting VGA, intel_ddi_pll_mode_set () return false and mode 
> setting exit without setting mode, vga is black
> If connecting HDMI, before enter S4, HDMI use WRPLL1.After resume from 
> S4, HDMI use WRPLL2.  The status is different during S4
> 
>  Actually, the above problem is a regression caused by your commit:
>commit 24576d23976746cb52e7700c4cadbf4bc1bc3472
>Author: Jesse Barnes 
>Date:   Tue Mar 26 09:25:45 2013 -0700
>  drm/i915: enable VT switchless resume v3
>   
> In your patch, you delete intel_modeset_disable() from i915_drm_freeze(), 
> intel_modeset_disable() will call dev_priv->display.off(crtc) to 
> decrease pll_refcount and disable PLL.
> 
> My question is whether PLL can be disabled when enable VT switchless ?
> 
> Thanks
> 
> -Original Message-
> From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of 
> Daniel Vetter
> Sent: Friday, July 12, 2013 1:32 AM
> To: Jesse Barnes
> Cc: Zhang, Xiong Y; intel-gfx
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Decrease pll->refcount when freeze 
> gpu
> 
> On Thu, Jul 11, 2013 at 6:53 PM, Jesse Barnes  
> wrote:
> > On Thu, 11 Jul 2013 16:02:27 +0800
> > Xiong Zhang  wrote:
> >
> >> display.crtc_mode_set will increase pll->refcount, but no one will 
> >> decrease pll->refcount when freeze gpu. So when gpu resume from 
> >> freeze,
> >> pll->refcount is still larger than zero. This is abnormal
> >>
> >> Without this patch, connecting vga screen on Haswell platform, there 
> >> are following results:
> >> 1. when resume S3, call trace exist in intel_ddi_put_crtc_pll() 2. 
> >> when resume s4, vga monitor is black. because intel_ddi_pll_mode_set()
> >>return false and haswell_crtc_mode_set() exit without setting mode
> >>
> >> With this patch, I don't find S3 and S4 regression on SandyBridge and 
> >> IvyBridge platform connecting VGA, HDMI and DP screen.
> >>
> >> Signed-off-by: Xiong Zhang 
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.c |4 +++-
> >>  1 file changed, 3 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> >> b/drivers/gpu/drm/i915/i915_drv.c index 0485f43..0065735 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.c
> >> +++ b/drivers/gpu/drm/i915/i915_drv.c
> >> @@ -575,8 +575,10 @@ static int i915_drm_freeze(struct drm_device *dev)
> >>* Disable CRTCs directly since we want to preserve sw state
> >>* for _thaw.
> >>*/
> >> - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> >> + list_for_each_entry(crtc, &dev->mode_config.crtc_list, 
> >> + head) {
> >>   dev_priv->display.crtc_disable(crtc);
> >> + dev_priv->display.off(crtc);
> >> + }
> >>
> >>   intel_modeset_suspend_hw(dev);
> >>   }
> >
> > The comment above this call indicates we'll trash the sw state if we 
> > call ->off directly.  Does suspend/resume still work both with and 
> > without X with this patch applied?  If we trash the sw state, the VT 
> > switchless resume shouldn't work...
> 
> Even without that little issue: ddi refcounting issue need to be fixed in the 
> haswell platform code, not by papering over in the core modeset 
> infrastructure. We have refcounted pch plls on snb/ivb, and it works.
> So imo there's no issue with the core code in the driver.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> 


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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Colocate all GT access routines in the same file

[Chris Wilson]

On Fri, Jul 12, 2013 at 10:56:55AM -0700, Ben Widawsky wrote:
> On Fri, Jul 12, 2013 at 06:08:22PM +0100, Chris Wilson wrote:
> > Currently, the register access code is split between i915_drv.c and
> > intel_pm.c. It only bares a superficial resemblance to the reset of the
> > powermanagement code, so move it all into its own file. This is to ease
> > further patches to enforce serialised register access.
> > 
> > v2: Scan for random abuse of I915_WRITE_NOTRACE
> > v3: Take the opportunity to rename the GT functions as uncore. Uncore is
> > the term used by the hardware design (and bspec) for all functions
> > outside of the GPU (and CPU) cores in what is also known as the System
> > Agent.
> 
> Bikesheds:

And I thought you were going to suggest an improved description to try
and explain how GT evolved into System Agent into uncore.

> Would have preferred the gt/pm_init split as a separate patch.

To do that I would either had to export a function to only then unexport
it again immediately, or move everything into intel_pm.c and then out
again. Neither't seem appealing.

> intel_uncore_clear_errors/chec_errors seems silly to me.

Agreed, but I was keeping the current code intact...
-Chris

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Re: [Intel-gfx] [PATCH 5/7] drm/i915: disable CLKOUT_DP when it's not needed

[Paulo Zanoni]

2013/7/12 Daniel Vetter :
> On Fri, Jul 12, 2013 at 02:19:40PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni 
>>
>> We currently don't support HDMI clock bending nor use SSC for DP or
>> HDMI on Haswell, so the only case where we need CLKOUT_DP is for VGA.
>>
>> Signed-off-by: Paulo Zanoni 
>
> Just an aside: One of the many plans on my todo is to move the refclk
> updates into the global_modeset_resources callback and only enable the
> refclocks we actually need for the given configuration. Entirely different
> patch series though.

Yeah, that's a good idea. And for that, we'll need this series merged :)

> -Daniel
>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 38 
>> 
>>  1 file changed, 34 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 5f3b636..059c9a8 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5305,6 +5305,36 @@ static void lpt_enable_clkout_dp(struct drm_device 
>> *dev, bool with_spread,
>>   mutex_unlock(&dev_priv->dpio_lock);
>>  }
>>
>> +/* Sequence to disable CLKOUT_DP */
>> +static void lpt_disable_clkout_dp(struct drm_device *dev)
>> +{
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + uint32_t tmp;
>> +
>> + mutex_lock(&dev_priv->dpio_lock);
>> +
>> + if (IS_ULT(dev_priv->dev)) {
>> + tmp = intel_sbi_read(dev_priv, SBI_GEN0, SBI_ICLK);
>> + tmp &= ~SBI_GEN0_ENABLE;
>> + intel_sbi_write(dev_priv, SBI_GEN0, tmp, SBI_ICLK);
>> + } else {
>> + tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
>> + tmp &= ~SBI_DBUFF0_ENABLE;
>> + intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
>> + }
>> +
>> + tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
>> + if (!(tmp & SBI_SSCCTL_PATHALT)) {
>> + tmp |= SBI_SSCCTL_PATHALT;
>> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
>> + udelay(32);
>> + }
>> + tmp |= SBI_SSCCTL_DISABLE;
>> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
>> +
>> + mutex_unlock(&dev_priv->dpio_lock);
>> +}
>> +
>>  static void lpt_init_pch_refclk(struct drm_device *dev)
>>  {
>>   struct drm_mode_config *mode_config = &dev->mode_config;
>> @@ -5319,10 +5349,10 @@ static void lpt_init_pch_refclk(struct drm_device 
>> *dev)
>>   }
>>   }
>>
>> - if (!has_vga)
>> - return;
>> -
>> - lpt_enable_clkout_dp(dev, true, true);
>> + if (has_vga)
>> + lpt_enable_clkout_dp(dev, true, true);
>> + else
>> + lpt_disable_clkout_dp(dev);
>>  }
>>
>>  /*
>> --
>> 1.8.1.2
>>
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> --
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> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



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Re: [Intel-gfx] [PATCH 5/7] drm/i915: disable CLKOUT_DP when it's not needed

[Daniel Vetter]

On Fri, Jul 12, 2013 at 02:19:40PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni 
> 
> We currently don't support HDMI clock bending nor use SSC for DP or
> HDMI on Haswell, so the only case where we need CLKOUT_DP is for VGA.
> 
> Signed-off-by: Paulo Zanoni 

Just an aside: One of the many plans on my todo is to move the refclk
updates into the global_modeset_resources callback and only enable the
refclocks we actually need for the given configuration. Entirely different
patch series though.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 38 
> 
>  1 file changed, 34 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 5f3b636..059c9a8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5305,6 +5305,36 @@ static void lpt_enable_clkout_dp(struct drm_device 
> *dev, bool with_spread,
>   mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +/* Sequence to disable CLKOUT_DP */
> +static void lpt_disable_clkout_dp(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + uint32_t tmp;
> +
> + mutex_lock(&dev_priv->dpio_lock);
> +
> + if (IS_ULT(dev_priv->dev)) {
> + tmp = intel_sbi_read(dev_priv, SBI_GEN0, SBI_ICLK);
> + tmp &= ~SBI_GEN0_ENABLE;
> + intel_sbi_write(dev_priv, SBI_GEN0, tmp, SBI_ICLK);
> + } else {
> + tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
> + tmp &= ~SBI_DBUFF0_ENABLE;
> + intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
> + }
> +
> + tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
> + if (!(tmp & SBI_SSCCTL_PATHALT)) {
> + tmp |= SBI_SSCCTL_PATHALT;
> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> + udelay(32);
> + }
> + tmp |= SBI_SSCCTL_DISABLE;
> + intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
> +
> + mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
>  static void lpt_init_pch_refclk(struct drm_device *dev)
>  {
>   struct drm_mode_config *mode_config = &dev->mode_config;
> @@ -5319,10 +5349,10 @@ static void lpt_init_pch_refclk(struct drm_device 
> *dev)
>   }
>   }
>  
> - if (!has_vga)
> - return;
> -
> - lpt_enable_clkout_dp(dev, true, true);
> + if (has_vga)
> + lpt_enable_clkout_dp(dev, true, true);
> + else
> + lpt_disable_clkout_dp(dev);
>  }
>  
>  /*
> -- 
> 1.8.1.2
> 
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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Colocate all GT access routines in the same file

[Ben Widawsky]

On Fri, Jul 12, 2013 at 06:08:22PM +0100, Chris Wilson wrote:
> Currently, the register access code is split between i915_drv.c and
> intel_pm.c. It only bares a superficial resemblance to the reset of the
> powermanagement code, so move it all into its own file. This is to ease
> further patches to enforce serialised register access.
> 
> v2: Scan for random abuse of I915_WRITE_NOTRACE
> v3: Take the opportunity to rename the GT functions as uncore. Uncore is
> the term used by the hardware design (and bspec) for all functions
> outside of the GPU (and CPU) cores in what is also known as the System
> Agent.
>

Bikesheds:
Would have preferred the gt/pm_init split as a separate patch.
intel_uncore_clear_errors/chec_errors seems silly to me.

Acked-by: Ben Widawsky 

> 
> Signed-off-by: Chris Wilson 
>
[snip]
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Re: [Intel-gfx] [PATCH 1/2] intel_get_llc_size: Small tool to query LLC size

[Ben Widawsky]

On Fri, Jul 12, 2013 at 10:39:51AM -0700, Chad Versace wrote:
> On 07/11/2013 11:53 AM, Ben Widawsky wrote:
> >v2: Use the new param
> >
> >CC: Chad Versace 
> >CC: Bryan Bell 
> >Signed-off-by: Ben Widawsky 
> >---
> >  tools/Makefile.am  |  1 +
> >  tools/intel_get_llc_size.c | 58 
> > ++
> >  2 files changed, 59 insertions(+)
> >  create mode 100644 tools/intel_get_llc_size.c
> >
> >diff --git a/tools/Makefile.am b/tools/Makefile.am
> >index 2519169..a064b65 100644
> >--- a/tools/Makefile.am
> >+++ b/tools/Makefile.am
> >@@ -9,6 +9,7 @@ bin_PROGRAMS =   \
> > intel_bios_dumper   \
> > intel_bios_reader   \
> > intel_error_decode  \
> >+intel_get_llc_size  \
> > intel_gpu_top   \
> > intel_gpu_time  \
> > intel_gtt   \
> >diff --git a/tools/intel_get_llc_size.c b/tools/intel_get_llc_size.c
> >new file mode 100644
> >index 000..498e252
> >--- /dev/null
> >+++ b/tools/intel_get_llc_size.c
> >@@ -0,0 +1,58 @@
> >+/*
> >+ * Copyright © 2013 Intel Corporation
> >+ *
> >+ * Permission is hereby granted, free of charge, to any person obtaining a
> >+ * copy of this software and associated documentation files (the 
> >"Software"),
> >+ * to deal in the Software without restriction, including without limitation
> >+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> >+ * and/or sell copies of the Software, and to permit persons to whom the
> >+ * Software is furnished to do so, subject to the following conditions:
> >+ *
> >+ * The above copyright notice and this permission notice (including the next
> >+ * paragraph) shall be included in all copies or substantial portions of the
> >+ * Software.
> >+ *
> >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> >OR
> >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> >+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
> >OTHER
> >+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> >+ * DEALINGS IN THE SOFTWARE.
> >+ *
> >+ */
> >+
> >+#include 
> >+#include "drmtest.h"
> >+#include "i915_drm.h"
> >+
> >+#define LOCAL__I915_PARAM_LLC_SIZE 27
> >+static int get_llc_size(int fd)
> >+{
> >+struct drm_i915_getparam gp;
> >+int size;
> >+
> >+gp.param = LOCAL__I915_PARAM_LLC_SIZE;
> >+gp.value = &size;
> >+
> >+if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
> >+return 0;
> >+
> >+return size;
> >+}
> >+
> >+int main(int argc, char **argv)
> >+{
> >+int size, fd = drm_open_any();
> >+
> >+size = get_llc_size(fd);
> >+
> >+if (size == 0)
> >+fprintf(stdout, "Doesn't have LLC\n");
> >+else if (size == 1)
> >+fprintf(stdout, "Kernel is too old to determine LLC size\n");
> >+else
> >+fprintf(stdout, "LLC size = %dK\n", size>>10);
> 
> This if-tree looks wrong. If the kernel doesn't know about 
> I915_PARAM_LLC_SIZE,
> the ioctl returns -1, and get_llc_size() returns 0, and the if-tree prints the
> wrong error.
> 
> How about making get_llc_size() return -1 on error? Or am I missing something 
> here?
>

Looks like the tool needed updating after the last param change and I
missed it. It should have been correct before (though in the case of no
HAS_LLC param it was also bad). Your suggestion is the right thing to do.

If Daniel decides to merge the kernel patch, I will fix this.

> 
> >+
> >+return 0;
> >+}
> >
> 
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Re: [Intel-gfx] [PATCH 1/2] intel_get_llc_size: Small tool to query LLC size

[Chad Versace]

On 07/11/2013 11:53 AM, Ben Widawsky wrote:

v2: Use the new param

CC: Chad Versace 
CC: Bryan Bell 
Signed-off-by: Ben Widawsky 
---
  tools/Makefile.am  |  1 +
  tools/intel_get_llc_size.c | 58 ++
  2 files changed, 59 insertions(+)
  create mode 100644 tools/intel_get_llc_size.c

diff --git a/tools/Makefile.am b/tools/Makefile.am
index 2519169..a064b65 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -9,6 +9,7 @@ bin_PROGRAMS =  \
intel_bios_dumper   \
intel_bios_reader   \
intel_error_decode  \
+   intel_get_llc_size  \
intel_gpu_top   \
intel_gpu_time  \
intel_gtt   \
diff --git a/tools/intel_get_llc_size.c b/tools/intel_get_llc_size.c
new file mode 100644
index 000..498e252
--- /dev/null
+++ b/tools/intel_get_llc_size.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include 
+#include "drmtest.h"
+#include "i915_drm.h"
+
+#define LOCAL__I915_PARAM_LLC_SIZE 27
+static int get_llc_size(int fd)
+{
+   struct drm_i915_getparam gp;
+   int size;
+
+   gp.param = LOCAL__I915_PARAM_LLC_SIZE;
+   gp.value = &size;
+
+   if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
+   return 0;
+
+   return size;
+}
+
+int main(int argc, char **argv)
+{
+   int size, fd = drm_open_any();
+
+   size = get_llc_size(fd);
+
+   if (size == 0)
+   fprintf(stdout, "Doesn't have LLC\n");
+   else if (size == 1)
+   fprintf(stdout, "Kernel is too old to determine LLC size\n");
+   else
+   fprintf(stdout, "LLC size = %dK\n", size>>10);


This if-tree looks wrong. If the kernel doesn't know about I915_PARAM_LLC_SIZE,
the ioctl returns -1, and get_llc_size() returns 0, and the if-tree prints the
wrong error.

How about making get_llc_size() return -1 on error? Or am I missing something 
here?


+
+   return 0;
+}



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Re: [Intel-gfx] [PATCH] [v2] drm/i915: Expose LLC size to user space

[Chad Versace]

On 07/11/2013 11:52 AM, Ben Widawsky wrote:

The algorithm/information was originally written by Chad, though I
changed the control flow, and I think his original code had a couple of
bugs, though I didn't look very hard before rewriting. That could have
also been different interpretations of the spec.

I've tested this on two platforms, and it seems to perform how I want.

With this patch is a small tool for igt to query the size. This can be
used as a reference for DRI clients wishing to query the information.

v2: Update name of the SDM location (Bryan)
Dissent: Use a new param instead of reusing HAS_LLC param (Chris, Chad)
Fix unicode multiply symbol (Ben)

CC: Chad Versace 
CC: Bryan Bell 
Signed-off-by: Ben Widawsky 
---
  drivers/gpu/drm/i915/i915_dma.c |  3 +++
  drivers/gpu/drm/i915/i915_drv.h |  2 ++
  drivers/gpu/drm/i915/i915_gem.c | 55 +
  include/uapi/drm/i915_drm.h |  1 +
  4 files changed, 61 insertions(+)


As long as this is tested and returns the same as L3 in /proc/cpuinfo, this 
patch is
Reviewed-by: Chad Versace 

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Re: [Intel-gfx] [benjamin.widaw...@intel.com: intel_gpu_top broken for HSW. Ideas needed]

[Ben Widawsky]

On Fri, Jul 12, 2013 at 10:12:39AM -0700, Ben Widawsky wrote:
> FWD'd from our internal list now that we have more insight.
> - Forwarded message from Ben Widawsky  -
> 
> Date: Thu, 11 Jul 2013 10:32:03 -0700
> From: Ben Widawsky 
> To: linux-...@linux.intel.com
> Subject: intel_gpu_top broken for HSW. Ideas needed
> Message-ID: <20130711173202.gb8...@intel.com>
> 
> Hi everybody.
> 
> While investigating a hard hang on Haswell. Eero noticed that
> intel_gpu_top helped to invoke the hang faster. I used this in my test
> case to validation, and they are suspecting it is a known issue which we
> have not yet worked around (and cannot reasonably workaround).
> 
> [internal bug sighting redacted]
> 
> To sum up, we cannot concurrently access registers within the same
> cacheline. It has the potential to hit a known bug.
> 
> I see some choices:
> 1. Don't do anything.
> 2. Try to eliminate shared registers as much as possible. Instdone is
>used by the hangcheck, and we can eliminate hangcheck with a
>module parameter. Eero, can you try this as a workaround, btw?
> 3. Somehow make the kernel collect the top data and serialize access
>there.
> 
> Anyone else have input? I personally do not use top very much, so I
> won't be volunteering to do any of these.
> 

BTW, of course any tool which reads or writes registers is subject to
the same problem. GPU top is just the one that kind of depends upon us
not synchronizing with the kernel.

-- 
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Re: [Intel-gfx] [benjamin.widaw...@intel.com: intel_gpu_top broken for HSW. Ideas needed]

[Ben Widawsky]

On Fri, Jul 12, 2013 at 07:16:37PM +0200, Daniel Vetter wrote:
> On Fri, Jul 12, 2013 at 7:12 PM, Ben Widawsky
>  wrote:
> > FWD'd from our internal list now that we have more insight.
> > - Forwarded message from Ben Widawsky  
> > -
> >
> > Date: Thu, 11 Jul 2013 10:32:03 -0700
> > From: Ben Widawsky 
> > To: linux-...@linux.intel.com
> > Subject: intel_gpu_top broken for HSW. Ideas needed
> > Message-ID: <20130711173202.gb8...@intel.com>
> >
> > Hi everybody.
> >
> > While investigating a hard hang on Haswell. Eero noticed that
> > intel_gpu_top helped to invoke the hang faster. I used this in my test
> > case to validation, and they are suspecting it is a known issue which we
> > have not yet worked around (and cannot reasonably workaround).
> >
> > [internal bug sighting redacted]
> >
> > To sum up, we cannot concurrently access registers within the same
> > cacheline. It has the potential to hit a known bug.
> >
> > I see some choices:
> > 1. Don't do anything.
> > 2. Try to eliminate shared registers as much as possible. Instdone is
> >used by the hangcheck, and we can eliminate hangcheck with a
> >module parameter. Eero, can you try this as a workaround, btw?
> > 3. Somehow make the kernel collect the top data and serialize access
> >there.
> >
> > Anyone else have input? I personally do not use top very much, so I
> > won't be volunteering to do any of these.
> 
> 
> For now I'd just vote for a warning on gen6+ on the intel-gpu-top
> screen that this might hang hw. If anyone cares we could add a debugfs
> interface (or finally get real approval for the performance counters
> the hw has an expose them properly). Not a intel_gpu_top user myself
> though.
> -Daniel
>
Eero: I meant to add by the way, ring head/tail are also used as much as
instdone. So Maybe we can get rid of that for the ring fullness check.
We're *very* likely to hit that one.

-- 
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[Intel-gfx] [PATCH 6/7] drm/i915: add functions to disable and restore LCPLL

[Paulo Zanoni]

From: Paulo Zanoni 

For now there are no callers, but these functions are going to be
needed for the code that allows Package C8+. Other future features may
also require this code.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h  |  7 +++
 drivers/gpu/drm/i915/intel_display.c | 95 
 drivers/gpu/drm/i915/intel_drv.h |  3 ++
 3 files changed, 105 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index be6164f..8e5a5ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4930,7 +4930,14 @@
 #define  LCPLL_CLK_FREQ_450(0<<26)
 #define  LCPLL_CD_CLOCK_DISABLE(1<<25)
 #define  LCPLL_CD2X_CLOCK_DISABLE  (1<<23)
+#define  LCPLL_POWER_DOWN_ALLOW(1<<22)
 #define  LCPLL_CD_SOURCE_FCLK  (1<<21)
+#define  LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
+
+#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
+#define  D_COMP_RCOMP_IN_PROGRESS  (1<<9)
+#define  D_COMP_COMP_FORCE (1<<8)
+#define  D_COMP_COMP_DISABLE   (1<<0)
 
 /* Pipe WM_LINETIME - watermark line time */
 #define PIPE_WM_LINETIME_A 0x45270
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 059c9a8..ffb08bf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5922,6 +5922,101 @@ static bool ironlake_get_pipe_config(struct intel_crtc 
*crtc,
return true;
 }
 
+/*
+ * This function implements pieces of two sequences from BSpec:
+ * - Sequence for display software to disable LCPLL
+ * - Sequence for display software to allow package C8+
+ * The steps implemented here are just the steps that actually touch the LCPLL
+ * register. Callers should take care of disabling all the display engine
+ * functions, doing the mode unset, fixing interrupts, etc.
+ */
+void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
+  bool switch_to_fclk, bool allow_power_down)
+{
+   uint32_t val;
+
+   val = I915_READ(LCPLL_CTL);
+
+   if (switch_to_fclk) {
+   val |= LCPLL_CD_SOURCE_FCLK;
+   I915_WRITE(LCPLL_CTL, val);
+   POSTING_READ(LCPLL_CTL);
+
+   udelay(1);
+
+   val = I915_READ(LCPLL_CTL);
+   if (!(val & LCPLL_CD_SOURCE_FCLK_DONE))
+   DRM_ERROR("Switching to FCLK failed\n");
+   }
+
+   val |= LCPLL_PLL_DISABLE;
+   I915_WRITE(LCPLL_CTL, val);
+   POSTING_READ(LCPLL_CTL);
+
+   if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
+   DRM_ERROR("LCPLL still locked\n");
+
+   val = I915_READ(D_COMP);
+   val |= D_COMP_COMP_DISABLE;
+   I915_WRITE(D_COMP, val);
+   POSTING_READ(D_COMP);
+
+   udelay(2);
+
+   val = I915_READ(D_COMP);
+   if (val & D_COMP_RCOMP_IN_PROGRESS)
+   DRM_ERROR("D_COMP RCOMP still in progress\n");
+
+   if (allow_power_down) {
+   val = I915_READ(LCPLL_CTL);
+   val |= LCPLL_POWER_DOWN_ALLOW;
+   I915_WRITE(LCPLL_CTL, val);
+   POSTING_READ(LCPLL_CTL);
+   }
+}
+
+/*
+ * Fully restores LCPLL, disallowing power down and switching back to LCPLL
+ * source.
+ */
+void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
+{
+   uint32_t val;
+
+   val = I915_READ(LCPLL_CTL);
+
+   if (val & LCPLL_POWER_DOWN_ALLOW) {
+   val &= ~LCPLL_POWER_DOWN_ALLOW;
+   I915_WRITE(LCPLL_CTL, val);
+   }
+
+   val = I915_READ(D_COMP);
+   val |= D_COMP_COMP_FORCE;
+   val &= ~D_COMP_COMP_DISABLE;
+   I915_WRITE(D_COMP, val);
+
+   val = I915_READ(LCPLL_CTL);
+   val &= ~LCPLL_PLL_DISABLE;
+   I915_WRITE(LCPLL_CTL, val);
+   POSTING_READ(LCPLL_CTL);
+
+   if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
+   DRM_ERROR("LCPLL not locked yet\n");
+
+   if (val & LCPLL_CD_SOURCE_FCLK) {
+   val = I915_READ(LCPLL_CTL);
+   val &= ~LCPLL_CD_SOURCE_FCLK;
+   I915_WRITE(LCPLL_CTL, val);
+   POSTING_READ(LCPLL_CTL);
+
+   udelay(1);
+
+   val = I915_READ(LCPLL_CTL);
+   if (val & LCPLL_CD_SOURCE_FCLK_DONE)
+   DRM_ERROR("Switching back to LCPLL failed\n");
+   }
+}
+
 static void haswell_modeset_global_resources(struct drm_device *dev)
 {
bool enable = false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5dfc1a0..15989d1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -832,5 +832,8 @@ extern bool intel_set_cpu_fifo_underrun_reporting(struct 
drm_device *dev,
 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 enum trans

[Intel-gfx] [PATCH 7/7] drm/i915: add some assertions to hsw_disable_lcpll

[Paulo Zanoni]

From: Paulo Zanoni 

Most of the hardware needs to be disabled before LCPLL is disabled, so
let's add a function to assert some of items listed in the "Display
Sequences for LCPLL disabling" documentation.

The idea is that hsw_disable_lcpll should not disable the hardware,
the callers need to take care of calling hsw_disable_lcpll only once
everything is already disabled.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h  |  8 
 drivers/gpu/drm/i915/intel_display.c | 28 
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8e5a5ec..9556dff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2195,6 +2195,8 @@
 #define BLC_PWM_CPU_CTL2   0x48250
 #define BLC_PWM_CPU_CTL0x48254
 
+#define HSW_BLC_PWM2_CTL   0x48350
+
 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
 #define BLC_PWM_PCH_CTL1   0xc8250
@@ -2203,6 +2205,12 @@
 #define   BLM_PCH_POLARITY (1 << 29)
 #define BLC_PWM_PCH_CTL2   0xc8254
 
+#define UTIL_PIN_CTL   0x48400
+#define   UTIL_PIN_ENABLE  (1 << 31)
+
+#define PCH_GTC_CTL0xe7000
+#define   PCH_GTC_ENABLE   (1 << 31)
+
 /* TV port control */
 #define TV_CTL 0x68000
 /** Enables the TV encoder */
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ffb08bf..9055f60 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5922,6 +5922,32 @@ static bool ironlake_get_pipe_config(struct intel_crtc 
*crtc,
return true;
 }
 
+static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
+{
+   struct drm_device *dev = dev_priv->dev;
+   struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
+   struct intel_crtc *crtc;
+
+   list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
+   WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
+pipe_name(crtc->pipe));
+
+   WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
+   WARN(plls->spll_refcount, "SPLL enabled\n");
+   WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
+   WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
+   WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
+   WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
+"CPU PWM1 enabled\n");
+   WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
+"CPU PWM2 enabled\n");
+   WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
+"PCH PWM1 enabled\n");
+   WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
+"Utility pin enabled\n");
+   WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
+}
+
 /*
  * This function implements pieces of two sequences from BSpec:
  * - Sequence for display software to disable LCPLL
@@ -5935,6 +5961,8 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 {
uint32_t val;
 
+   assert_can_disable_lcpll(dev_priv);
+
val = I915_READ(LCPLL_CTL);
 
if (switch_to_fclk) {
-- 
1.8.1.2

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[Intel-gfx] [PATCH 5/7] drm/i915: disable CLKOUT_DP when it's not needed

[Paulo Zanoni]

From: Paulo Zanoni 

We currently don't support HDMI clock bending nor use SSC for DP or
HDMI on Haswell, so the only case where we need CLKOUT_DP is for VGA.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_display.c | 38 
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 5f3b636..059c9a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5305,6 +5305,36 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, 
bool with_spread,
mutex_unlock(&dev_priv->dpio_lock);
 }
 
+/* Sequence to disable CLKOUT_DP */
+static void lpt_disable_clkout_dp(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   uint32_t tmp;
+
+   mutex_lock(&dev_priv->dpio_lock);
+
+   if (IS_ULT(dev_priv->dev)) {
+   tmp = intel_sbi_read(dev_priv, SBI_GEN0, SBI_ICLK);
+   tmp &= ~SBI_GEN0_ENABLE;
+   intel_sbi_write(dev_priv, SBI_GEN0, tmp, SBI_ICLK);
+   } else {
+   tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
+   tmp &= ~SBI_DBUFF0_ENABLE;
+   intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
+   }
+
+   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
+   if (!(tmp & SBI_SSCCTL_PATHALT)) {
+   tmp |= SBI_SSCCTL_PATHALT;
+   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+   udelay(32);
+   }
+   tmp |= SBI_SSCCTL_DISABLE;
+   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+
+   mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void lpt_init_pch_refclk(struct drm_device *dev)
 {
struct drm_mode_config *mode_config = &dev->mode_config;
@@ -5319,10 +5349,10 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
}
}
 
-   if (!has_vga)
-   return;
-
-   lpt_enable_clkout_dp(dev, true, true);
+   if (has_vga)
+   lpt_enable_clkout_dp(dev, true, true);
+   else
+   lpt_disable_clkout_dp(dev);
 }
 
 /*
-- 
1.8.1.2

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[Intel-gfx] [PATCH 4/7] drm/i915: extend lpt_enable_clkout_dp

[Paulo Zanoni]

From: Paulo Zanoni 

Now it implements 3 different sequences from BSpec and also has
support for ULT.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_display.c | 41 +---
 2 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc3d6a7..be6164f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4863,6 +4863,8 @@
 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)((x)<<4)
 #define  SBI_DBUFF00x2a00
 #define   SBI_DBUFF0_ENABLE(1<<0)
+#define  SBI_GEN0  0x1f00
+#define   SBI_GEN0_ENABLE  (1<<0)
 
 /* LPT PIXCLK_GATE */
 #define PIXCLK_GATE0xC6020
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f4c5263..5f3b636 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5258,12 +5258,20 @@ static void lpt_program_fdi_mphy(struct 
drm_i915_private *dev_priv)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
 }
 
-/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
-static void lpt_enable_clkout_dp(struct drm_device *dev)
+/* Implements 3 different sequences from BSpec chapter "Display iCLK
+ * Programming" based on the parameters passed:
+ * - Sequence to enable CLKOUT_DP
+ * - Sequence to enable CLKOUT_DP without spread
+ * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
+ */
+static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
+bool with_fdi)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t tmp;
 
+   WARN(with_fdi && !with_spread, "FDI requires downspread\n");
+
mutex_lock(&dev_priv->dpio_lock);
 
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
@@ -5273,17 +5281,26 @@ static void lpt_enable_clkout_dp(struct drm_device *dev)
 
udelay(24);
 
-   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
-   tmp &= ~SBI_SSCCTL_PATHALT;
-   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+   if (with_spread) {
+   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
+   tmp &= ~SBI_SSCCTL_PATHALT;
+   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
 
-   lpt_reset_fdi_mphy(dev_priv);
-   lpt_program_fdi_mphy(dev_priv);
+   if (with_fdi) {
+   lpt_reset_fdi_mphy(dev_priv);
+   lpt_program_fdi_mphy(dev_priv);
+   }
+   }
 
-   /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
-   tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
-   tmp |= SBI_DBUFF0_ENABLE;
-   intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
+   if (IS_ULT(dev)) {
+   tmp = intel_sbi_read(dev_priv, SBI_GEN0, SBI_ICLK);
+   tmp |= SBI_GEN0_ENABLE;
+   intel_sbi_write(dev_priv, SBI_GEN0, tmp, SBI_ICLK);
+   } else {
+   tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
+   tmp |= SBI_DBUFF0_ENABLE;
+   intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
+   }
 
mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -5305,7 +5322,7 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
if (!has_vga)
return;
 
-   lpt_enable_clkout_dp(dev);
+   lpt_enable_clkout_dp(dev, true, true);
 }
 
 /*
-- 
1.8.1.2

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[Intel-gfx] [PATCH 3/7] drm/i915: extract lpt_enable_clkout_dp from lpt_init_pch_refclk

[Paulo Zanoni]

From: Paulo Zanoni 

The next step is to modify lpt_enable_clkout_dp to enable support for
"Sequence to enable CLKOUT_DP" and "Sequence to enable CLKOUT_DP
without spread".

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_display.c | 38 +---
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 753317d..f4c5263 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5259,24 +5259,10 @@ static void lpt_program_fdi_mphy(struct 
drm_i915_private *dev_priv)
 }
 
 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
-static void lpt_init_pch_refclk(struct drm_device *dev)
+static void lpt_enable_clkout_dp(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_mode_config *mode_config = &dev->mode_config;
-   struct intel_encoder *encoder;
-   bool has_vga = false;
-   u32 tmp;
-
-   list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
-   switch (encoder->type) {
-   case INTEL_OUTPUT_ANALOG:
-   has_vga = true;
-   break;
-   }
-   }
-
-   if (!has_vga)
-   return;
+   uint32_t tmp;
 
mutex_lock(&dev_priv->dpio_lock);
 
@@ -5302,6 +5288,26 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void lpt_init_pch_refclk(struct drm_device *dev)
+{
+   struct drm_mode_config *mode_config = &dev->mode_config;
+   struct intel_encoder *encoder;
+   bool has_vga = false;
+
+   list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+   switch (encoder->type) {
+   case INTEL_OUTPUT_ANALOG:
+   has_vga = true;
+   break;
+   }
+   }
+
+   if (!has_vga)
+   return;
+
+   lpt_enable_clkout_dp(dev);
+}
+
 /*
  * Initialize reference clocks when the driver loads
  */
-- 
1.8.1.2

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[Intel-gfx] [PATCH 2/7] drm/i915: extract FDI mPHY functions from lpt_init_pch_refclk

[Paulo Zanoni]

From: Paulo Zanoni 

Because lpt_init_pch_refclk implements the "Sequence to enable
CLKOUT_DP for FDI usage and configure PCH FDI I/O", which is very
similar to "Sequence to enable CLKOUT_DP" and "Sequence to enable
CLKOUT_DP without spread". With the extracted functions we can more
easily implement the two missing sequences.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_display.c | 75 +---
 1 file changed, 44 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 5821ffc..753317d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5163,38 +5163,9 @@ static void ironlake_init_pch_refclk(struct drm_device 
*dev)
BUG_ON(val != final);
 }
 
-/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
-static void lpt_init_pch_refclk(struct drm_device *dev)
+static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_mode_config *mode_config = &dev->mode_config;
-   struct intel_encoder *encoder;
-   bool has_vga = false;
-   u32 tmp;
-
-   list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
-   switch (encoder->type) {
-   case INTEL_OUTPUT_ANALOG:
-   has_vga = true;
-   break;
-   }
-   }
-
-   if (!has_vga)
-   return;
-
-   mutex_lock(&dev_priv->dpio_lock);
-
-   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
-   tmp &= ~SBI_SSCCTL_DISABLE;
-   tmp |= SBI_SSCCTL_PATHALT;
-   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
-
-   udelay(24);
-
-   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
-   tmp &= ~SBI_SSCCTL_PATHALT;
-   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+   uint32_t tmp;
 
tmp = I915_READ(SOUTH_CHICKEN2);
tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
@@ -5211,6 +5182,11 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
DRM_ERROR("FDI mPHY reset de-assert timeout\n");
+}
+
+static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
+{
+   uint32_t tmp;
 
tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
tmp &= ~(0xFF << 24);
@@ -5280,6 +5256,43 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
tmp &= ~(0xF << 28);
tmp |= (4 << 28);
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
+}
+
+/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
+static void lpt_init_pch_refclk(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct drm_mode_config *mode_config = &dev->mode_config;
+   struct intel_encoder *encoder;
+   bool has_vga = false;
+   u32 tmp;
+
+   list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+   switch (encoder->type) {
+   case INTEL_OUTPUT_ANALOG:
+   has_vga = true;
+   break;
+   }
+   }
+
+   if (!has_vga)
+   return;
+
+   mutex_lock(&dev_priv->dpio_lock);
+
+   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
+   tmp &= ~SBI_SSCCTL_DISABLE;
+   tmp |= SBI_SSCCTL_PATHALT;
+   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+
+   udelay(24);
+
+   tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
+   tmp &= ~SBI_SSCCTL_PATHALT;
+   intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
+
+   lpt_reset_fdi_mphy(dev_priv);
+   lpt_program_fdi_mphy(dev_priv);
 
/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
-- 
1.8.1.2

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[Intel-gfx] [PATCH 1/7] drm/i915: remove SDV support from lpt_pch_init_refclk

[Paulo Zanoni]

From: Paulo Zanoni 

The machines that fall in the "is_sdv" case are some very early
pre-production steppings. This patch may break VGA output after
suspend/resume on these machines.

Even the documentation for the is_sdv cases was removed from BSpec.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_display.c | 104 ---
 1 file changed, 34 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c79addd..5821ffc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5170,7 +5170,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
struct drm_mode_config *mode_config = &dev->mode_config;
struct intel_encoder *encoder;
bool has_vga = false;
-   bool is_sdv = false;
u32 tmp;
 
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
@@ -5186,10 +5185,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
 
mutex_lock(&dev_priv->dpio_lock);
 
-   /* XXX: Rip out SDV support once Haswell ships for real. */
-   if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
-   is_sdv = true;
-
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
tmp &= ~SBI_SSCCTL_DISABLE;
tmp |= SBI_SSCCTL_PATHALT;
@@ -5201,36 +5196,27 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
tmp &= ~SBI_SSCCTL_PATHALT;
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
 
-   if (!is_sdv) {
-   tmp = I915_READ(SOUTH_CHICKEN2);
-   tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
-   I915_WRITE(SOUTH_CHICKEN2, tmp);
+   tmp = I915_READ(SOUTH_CHICKEN2);
+   tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
+   I915_WRITE(SOUTH_CHICKEN2, tmp);
 
-   if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
-  FDI_MPHY_IOSFSB_RESET_STATUS, 100))
-   DRM_ERROR("FDI mPHY reset assert timeout\n");
+   if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
+  FDI_MPHY_IOSFSB_RESET_STATUS, 100))
+   DRM_ERROR("FDI mPHY reset assert timeout\n");
 
-   tmp = I915_READ(SOUTH_CHICKEN2);
-   tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
-   I915_WRITE(SOUTH_CHICKEN2, tmp);
+   tmp = I915_READ(SOUTH_CHICKEN2);
+   tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
+   I915_WRITE(SOUTH_CHICKEN2, tmp);
 
-   if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
-   FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
-  100))
-   DRM_ERROR("FDI mPHY reset de-assert timeout\n");
-   }
+   if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
+   FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
+   DRM_ERROR("FDI mPHY reset de-assert timeout\n");
 
tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
tmp &= ~(0xFF << 24);
tmp |= (0x12 << 24);
intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
 
-   if (is_sdv) {
-   tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
-   tmp |= 0x7FFF;
-   intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
-   }
-
tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
tmp |= (1 << 11);
intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
@@ -5239,24 +5225,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
tmp |= (1 << 11);
intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
 
-   if (is_sdv) {
-   tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
-   tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
-   intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
-
-   tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
-   tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
-   intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
-
-   tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
-   tmp |= (0x3F << 8);
-   intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
-
-   tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
-   tmp |= (0x3F << 8);
-   intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
-   }
-
tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
@@ -5265,17 +5233,15 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
 
-   if (!is_sdv) {
-   tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
-   tmp &= ~(7 << 13);
-   tmp |= (5 << 13);
-   

[Intel-gfx] [PATCH 0/7] HSW/LPT clocking code additional sequences

[Paulo Zanoni]

From: Paulo Zanoni 

Hi

On the code that allows Package C8+ we need to disable/reenable the PCH
reference clocks and also disable/reenable LCPLL. This series implements the
sequences that are going to be needed. I have local patches that use this code
and they seem to work (we survive going to C10 and back to C7), and I also sent
earlier versions of these patches to the mailing list, so open-source code that
uses these functions already exists on the intel-gfx mailing list. The goal here
is allow people to review/merge this while the final PC8+ patches are not yet
100% reviewer-compliant.

On the first 3 patches we massage our code so we can reuse it for PC8+ code. On
patch 4 we extend the current code to also implement one of the sequences
required by PC8+. On patch 5 we implement the equivalent disable sequence, also
needed by PC8+. On patch 6 we implement the functions to disable and restore
LCPLL, and on patch 7 we add some assertions that are going to be used.

If you want to review patches 1-3 all you need is C experience. For patches 4
and 5 you need to read the "Display iCLK programming" chapter of BSpec. For
patches 6 and 7 you need to read "Display sequences for LCPLL disabling" and
"Display sequences for Package C8".

Cheers,
Paulo

Paulo Zanoni (7):
  drm/i915: remove SDV support from lpt_pch_init_refclk
  drm/i915: extract FDI mPHY functions from lpt_init_pch_refclk
  drm/i915: extract lpt_enable_clkout_dp from lpt_init_pch_refclk
  drm/i915: extend lpt_enable_clkout_dp
  drm/i915: disable CLKOUT_DP when it's not needed
  drm/i915: add functions to disable and restore LCPLL
  drm/i915: add some assertions to hsw_disable_lcpll

 drivers/gpu/drm/i915/i915_reg.h  |  17 ++
 drivers/gpu/drm/i915/intel_display.c | 359 +--
 drivers/gpu/drm/i915/intel_drv.h |   3 +
 3 files changed, 276 insertions(+), 103 deletions(-)

-- 
1.8.1.2

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Re: [Intel-gfx] [benjamin.widaw...@intel.com: intel_gpu_top broken for HSW. Ideas needed]

[Daniel Vetter]

On Fri, Jul 12, 2013 at 7:12 PM, Ben Widawsky
 wrote:
> FWD'd from our internal list now that we have more insight.
> - Forwarded message from Ben Widawsky  -
>
> Date: Thu, 11 Jul 2013 10:32:03 -0700
> From: Ben Widawsky 
> To: linux-...@linux.intel.com
> Subject: intel_gpu_top broken for HSW. Ideas needed
> Message-ID: <20130711173202.gb8...@intel.com>
>
> Hi everybody.
>
> While investigating a hard hang on Haswell. Eero noticed that
> intel_gpu_top helped to invoke the hang faster. I used this in my test
> case to validation, and they are suspecting it is a known issue which we
> have not yet worked around (and cannot reasonably workaround).
>
> [internal bug sighting redacted]
>
> To sum up, we cannot concurrently access registers within the same
> cacheline. It has the potential to hit a known bug.
>
> I see some choices:
> 1. Don't do anything.
> 2. Try to eliminate shared registers as much as possible. Instdone is
>used by the hangcheck, and we can eliminate hangcheck with a
>module parameter. Eero, can you try this as a workaround, btw?
> 3. Somehow make the kernel collect the top data and serialize access
>there.
>
> Anyone else have input? I personally do not use top very much, so I
> won't be volunteering to do any of these.


For now I'd just vote for a warning on gen6+ on the intel-gpu-top
screen that this might hang hw. If anyone cares we could add a debugfs
interface (or finally get real approval for the performance counters
the hw has an expose them properly). Not a intel_gpu_top user myself
though.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] [benjamin.widaw...@intel.com: intel_gpu_top broken for HSW. Ideas needed]

[Ben Widawsky]

FWD'd from our internal list now that we have more insight.
- Forwarded message from Ben Widawsky  -

Date: Thu, 11 Jul 2013 10:32:03 -0700
From: Ben Widawsky 
To: linux-...@linux.intel.com
Subject: intel_gpu_top broken for HSW. Ideas needed
Message-ID: <20130711173202.gb8...@intel.com>

Hi everybody.

While investigating a hard hang on Haswell. Eero noticed that
intel_gpu_top helped to invoke the hang faster. I used this in my test
case to validation, and they are suspecting it is a known issue which we
have not yet worked around (and cannot reasonably workaround).

[internal bug sighting redacted]

To sum up, we cannot concurrently access registers within the same
cacheline. It has the potential to hit a known bug.

I see some choices:
1. Don't do anything.
2. Try to eliminate shared registers as much as possible. Instdone is
   used by the hangcheck, and we can eliminate hangcheck with a
   module parameter. Eero, can you try this as a workaround, btw?
3. Somehow make the kernel collect the top data and serialize access
   there.

Anyone else have input? I personally do not use top very much, so I
won't be volunteering to do any of these.

- End forwarded message -

-- 
Ben Widawsky, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 5/6] drm/i915: Squash gen lookup through multiple indirections inside GT access

[Chris Wilson]

The INTEL_INFO() macro extracts the dev_private pointer from the device,
so passing in the dev_private->dev is a long winded circumlocution.

v2: rebase onto uncore

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index a89efc6..dbf9f6c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -345,7 +345,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg, bool trace) { \
unsigned long irqflags; \
u##x val = 0; \
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
-   if (IS_GEN5(dev_priv->dev)) \
+   if (dev_priv->info->gen == 5) \
ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
if (dev_priv->uncore.forcewake_count == 0) \
@@ -376,7 +376,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 
reg, u##x val, bool tr
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
-   if (IS_GEN5(dev_priv->dev)) \
+   if (dev_priv->info->gen == 5) \
ilk_dummy_write(dev_priv); \
hsw_unclaimed_reg_clear(dev_priv, reg); \
write##y(val, dev_priv->regs + reg); \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 2/6] drm/i915: Use a private interface for register access within GT

[Chris Wilson]

The GT functions for enabling register access also need to occasionally
write to and read from registers. To avoid the potential recursion as we
modify the public interface to be stricter, introduce a private register
access API for the GT functions.

v2: Rebase
v3: Rebase onto uncore

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_uncore.c | 107 +---
 1 file changed, 64 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 8c2f460..9d4063f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -26,6 +26,19 @@
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
+#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
+#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, 
(dev_priv__)->regs + (reg__))
+
+
 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 {
u32 gt_thread_status_mask;
@@ -38,26 +51,27 @@ static void __gen6_gt_wait_for_thread_c0(struct 
drm_i915_private *dev_priv)
/* w/a for a sporadic read returning 0 by waiting for the GT
 * thread to wake up.
 */
-   if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & 
gt_thread_status_mask) == 0, 500))
+   if (wait_for_atomic_us((__raw_i915_read32(dev_priv, 
GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
DRM_ERROR("GT thread status wait timed out\n");
 }
 
 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE_NOTRACE(FORCEWAKE, 0);
-   POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
*/
+   __raw_i915_write32(dev_priv, FORCEWAKE, 0);
+   /* something from same cacheline, but !FORCEWAKE */
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 }
 
 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 {
-   if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 
0,
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake old ack to 
clear.\n");
 
-   I915_WRITE_NOTRACE(FORCEWAKE, 1);
-   POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
*/
+   __raw_i915_write32(dev_priv, FORCEWAKE, 1);
+   (void)__raw_i915_read32(dev_priv, ECOBUS); /* something from same 
cacheline, but !FORCEWAKE */
 
-   if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 
@@ -67,9 +81,9 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private 
*dev_priv)
 
 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
+   __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
/* something from same cacheline, but !FORCEWAKE_MT */
-   POSTING_READ(ECOBUS);
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 }
 
 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
@@ -81,15 +95,16 @@ static void __gen6_gt_force_wake_mt_get(struct 
drm_i915_private *dev_priv)
else
forcewake_ack = FORCEWAKE_MT_ACK;
 
-   if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 
FORCEWAKE_KERNEL) == 0,
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & 
FORCEWAKE_KERNEL) == 0,
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake old ack to 
clear.\n");
 
-   I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
+   __raw_i915_write32(dev_priv, FORCEWAKE_MT,
+  _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
/* something from same cacheline, but !FORCEWAKE_MT */
-   POSTING_READ(ECOBUS);
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 
-   if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 
FORCEWAKE_KERNEL),
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & 
FORCEWAKE_KERNEL),
FORCEWAKE_ACK_TIMEOU

[Intel-gfx] [PATCH 3/6] drm/i915: Use the common register access functions for NOTRACE variants

[Chris Wilson]

Detangle the confusion that NOTRACE variants of the register read/write
routines were directly using the raw register access. We need for those
routines to reuse the common code for serializing register access and
ensuring the correct register power states. This is only possible now
that the only routines that required raw access use their own API.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h | 28 ++--
 drivers/gpu/drm/i915/intel_uncore.c |  8 
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f14eddf..3364ac8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2084,7 +2084,7 @@ int vlv_gpu_freq(int ddr_freq, int val);
 int vlv_freq_opcode(int ddr_freq, int val);
 
 #define __i915_read(x, y) \
-   u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
+   u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool 
trace);
 
 __i915_read(8, b)
 __i915_read(16, w)
@@ -2093,7 +2093,7 @@ __i915_read(64, q)
 #undef __i915_read
 
 #define __i915_write(x, y) \
-   void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
val);
+   void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
val, bool trace);
 
 __i915_write(8, b)
 __i915_write(16, w)
@@ -2101,21 +2101,21 @@ __i915_write(32, l)
 __i915_write(64, q)
 #undef __i915_write
 
-#define I915_READ8(reg)i915_read8(dev_priv, (reg))
-#define I915_WRITE8(reg, val)  i915_write8(dev_priv, (reg), (val))
+#define I915_READ8(reg)i915_read8(dev_priv, (reg), true)
+#define I915_WRITE8(reg, val)  i915_write8(dev_priv, (reg), (val), true)
 
-#define I915_READ16(reg)   i915_read16(dev_priv, (reg))
-#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
-#define I915_READ16_NOTRACE(reg)   readw(dev_priv->regs + (reg))
-#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
+#define I915_READ16(reg)   i915_read16(dev_priv, (reg), true)
+#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true)
+#define I915_READ16_NOTRACE(reg)   i915_read16(dev_priv, (reg), false)
+#define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), 
false)
 
-#define I915_READ(reg) i915_read32(dev_priv, (reg))
-#define I915_WRITE(reg, val)   i915_write32(dev_priv, (reg), (val))
-#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
-#define I915_WRITE_NOTRACE(reg, val)   writel(val, dev_priv->regs + (reg))
+#define I915_READ(reg) i915_read32(dev_priv, (reg), true)
+#define I915_WRITE(reg, val)   i915_write32(dev_priv, (reg), (val), true)
+#define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false)
+#define I915_WRITE_NOTRACE(reg, val)   i915_write32(dev_priv, (reg), (val), 
false)
 
-#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
-#define I915_READ64(reg)   i915_read64(dev_priv, (reg))
+#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true)
+#define I915_READ64(reg)   i915_read64(dev_priv, (reg), true)
 
 #define POSTING_READ(reg)  (void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)(void)I915_READ16_NOTRACE(reg)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 9d4063f..d7989b8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -341,7 +341,7 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, 
u32 reg)
 }
 
 #define __i915_read(x, y) \
-u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
+u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
u##x val = 0; \
if (IS_GEN5(dev_priv->dev)) \
ilk_dummy_write(dev_priv); \
@@ -357,7 +357,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg) { \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
-   trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+   if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
 }
 
@@ -368,9 +368,9 @@ __i915_read(64, q)
 #undef __i915_read
 
 #define __i915_write(x, y) \
-void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
+void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
u32 __fifo_ret = 0; \
-   trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 4/6] drm/i915: Serialize all register access

[Chris Wilson]

In theory, the different register blocks were meant to be only ever
touched when holding either the struct_mutex, mode_config.lock or even a
specific localised lock. This does not seem to be the case, and the
hardware reacts extremely badly if we attempt to concurrently access two
registers within the same cacheline.

v2: Rebase onto uncore

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63914
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_uncore.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index d7989b8..a89efc6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -342,21 +342,21 @@ hsw_unclaimed_reg_check(struct drm_i915_private 
*dev_priv, u32 reg)
 
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
+   unsigned long irqflags; \
u##x val = 0; \
+   spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
if (IS_GEN5(dev_priv->dev)) \
ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
-   unsigned long irqflags; \
-   spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
if (dev_priv->uncore.forcewake_count == 0) \
dev_priv->uncore.funcs.force_wake_get(dev_priv); \
val = read##y(dev_priv->regs + reg); \
if (dev_priv->uncore.forcewake_count == 0) \
dev_priv->uncore.funcs.force_wake_put(dev_priv); \
-   spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
+   spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
 }
@@ -369,8 +369,10 @@ __i915_read(64, q)
 
 #define __i915_write(x, y) \
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
+   unsigned long irqflags; \
u32 __fifo_ret = 0; \
if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
@@ -382,6 +384,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 
reg, u##x val, bool tr
gen6_gt_check_fifodbg(dev_priv); \
} \
hsw_unclaimed_reg_check(dev_priv, reg); \
+   spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 }
 __i915_write(8, b)
 __i915_write(16, w)
-- 
1.8.3.2

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[Intel-gfx] [PATCH 6/6] drm/i915: Convert the register access tracepoint to be conditional

[Chris Wilson]

The TRACE_EVENT_CONDITION is supposed to generate more efficient code
than if (cond) trace(), which is what we are currently using inside the
register access functions.

v2: Rebase onto uncore

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
 drivers/gpu/drm/i915/i915_trace.h   | 8 +---
 drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7231322..85819dd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1002,7 +1002,7 @@ static int gen6_drpc_info(struct seq_file *m)
}
 
gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
-   trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
+   trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 7d283b5..2933e2f 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -406,10 +406,12 @@ TRACE_EVENT(i915_flip_complete,
TP_printk("plane=%d, obj=%p", __entry->plane, __entry->obj)
 );
 
-TRACE_EVENT(i915_reg_rw,
-   TP_PROTO(bool write, u32 reg, u64 val, int len),
+TRACE_EVENT_CONDITION(i915_reg_rw,
+   TP_PROTO(bool write, u32 reg, u64 val, int len, bool trace),
 
-   TP_ARGS(write, reg, val, len),
+   TP_ARGS(write, reg, val, len, trace),
+
+   TP_CONDITION(trace),
 
TP_STRUCT__entry(
__field(u64, val)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index dbf9f6c..21cbe8b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -357,7 +357,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg, bool trace) { \
val = read##y(dev_priv->regs + reg); \
} \
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
-   if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+   trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val; \
 }
 
@@ -371,7 +371,7 @@ __i915_read(64, q)
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
unsigned long irqflags; \
u32 __fifo_ret = 0; \
-   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
-- 
1.8.3.2

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Re: [Intel-gfx] [PATCH] drm/i915: fix pfit regression for non-autoscaled resolutions

[Daniel Vetter]

On Fri, Jul 12, 2013 at 08:04:16AM -0700, Jesse Barnes wrote:
> On Fri, 12 Jul 2013 08:07:30 +0200
> Daniel Vetter  wrote:
> 
> > I.e. for letter/pillarboxing. For those cases we need to adjust the
> > mode a bit, but Jesse gmch pfit refactoring in
> > 
> > commit 2dd24552cab40ea829ba3fda890eeafd2c4816d8
> > Author: Jesse Barnes 
> > Date:   Thu Apr 25 12:55:01 2013 -0700
> > 
> > drm/i915: factor out GMCH panel fitting code and use for eDP v3
> > 
> > broke that by reordering the computation of the gmch pfit state with
> > the block of code that prepared the adjusted mode for it and told the
> > modeset core not to overwrite the adjusted mode with default settings.
> > 
> > We might want to switch around the core code to just fill in defaults,
> > but this code predates the pipe_config modeset rework. And in the old
> > crtc helpers we did not have a suitable spot to do this.
> > 
> > Cc: Mika Kuoppala 
> > Cc: Jesse Barnes 
> > Cc: Hans de Bruin 
> > Reported-and-tested-by: Hans de Bruin 
> > Signed-off-by: Daniel Vetter 
> > ---
> >  drivers/gpu/drm/i915/intel_lvds.c  | 5 +
> >  drivers/gpu/drm/i915/intel_panel.c | 3 +++
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
> > b/drivers/gpu/drm/i915/intel_lvds.c
> > index b0e1088..0536c9b 100644
> > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > @@ -297,14 +297,11 @@ static bool intel_lvds_compute_config(struct 
> > intel_encoder *intel_encoder,
> >  
> > intel_pch_panel_fitting(intel_crtc, pipe_config,
> > intel_connector->panel.fitting_mode);
> > -   return true;
> > } else {
> > intel_gmch_panel_fitting(intel_crtc, pipe_config,
> >  intel_connector->panel.fitting_mode);
> > -   }
> >  
> > -   drm_mode_set_crtcinfo(adjusted_mode, 0);
> > -   pipe_config->timings_set = true;
> > +   }
> >  
> > /*
> >  * XXX: It would be nice to support lower refresh rates on the
> > diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> > b/drivers/gpu/drm/i915/intel_panel.c
> > index 80bea1d..45010bb 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -194,6 +194,9 @@ void intel_gmch_panel_fitting(struct intel_crtc 
> > *intel_crtc,
> > adjusted_mode->vdisplay == mode->vdisplay)
> > goto out;
> >  
> > +   drm_mode_set_crtcinfo(adjusted_mode, 0);
> > +   pipe_config->timings_set = true;
> > +
> > switch (fitting_mode) {
> > case DRM_MODE_SCALE_CENTER:
> > /*
> 
> This code is a bit confusing, but this looks better than what was there
> before (clobbering the adjusted_mode after calling gmch_panel_fitting
> definitely seems wrong).  Only nit is that the timings_set flag isn't
> very descriptive, but that's not the fault of this patch.

Yeah, that's just an artifact from the old crtc helper code, with the
new compute_config callbacks we could precompute sane crtc timings. I'll
fix this up for 3.12

> Reviewed-by: Jesse Barnes 

Picked up for -fixes, thanks for the review.
-Daniel
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Re: [Intel-gfx] [PATCH 06/11] drm/i915: plumb VM into object operations

[Daniel Vetter]

On Fri, Jul 12, 2013 at 08:46:48AM -0700, Ben Widawsky wrote:
> On Fri, Jul 12, 2013 at 08:26:07AM +0200, Daniel Vetter wrote:
> > On Thu, Jul 11, 2013 at 07:23:08PM -0700, Ben Widawsky wrote:
> > > On Tue, Jul 09, 2013 at 09:15:01AM +0200, Daniel Vetter wrote:
> > > > On Mon, Jul 08, 2013 at 11:08:37PM -0700, Ben Widawsky wrote:

[snip]

> > > > > @@ -,12 +3376,15 @@ int i915_gem_object_set_cache_level(struct 
> > > > > drm_i915_gem_object *obj,
> > > > >   }
> > > > >  
> > > > >   if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
> > > > > - ret = i915_gem_object_unbind(obj);
> > > > > + ret = i915_gem_object_unbind(obj, vm);
> > > > >   if (ret)
> > > > >   return ret;
> > > > >   }
> > > > >  
> > > > > - if (i915_gem_obj_ggtt_bound(obj)) {
> > > > > + list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
> > > > > + if (!i915_gem_obj_bound(obj, vm))
> > > > > + continue;
> > > > 
> > > > Hm, shouldn't we have a per-object list of vmas? Or will that follow 
> > > > later
> > > > on?
> > > > 
> > > > Self-correction: It exists already ... why can't we use this here?
> > > 
> > > Yes. That should work, I'll fix it and test it. It looks slightly worse
> > > IMO in terms of code clarity, but I don't mind the change.
> > 
> > Actually I think it'd gain in clarity, doing pte updatest (which
> > set_cache_level does) on the vma instead of the (obj, vm) pair feels more
> > natural. And we'd be able to drop lots of (obj, vm) -> vma lookups here.
> 
> That sounds good to me. Would you mind a patch on top?

If you want I guess we can refactor this after everything has settled. Has
the upside that assessing whether using vma or (obj, vm) is much easier.
So fine with me.

> 
> > 
> > > 
> > > > 
> > > > > +
> > > > >   ret = i915_gem_object_finish_gpu(obj);
> > > > >   if (ret)
> > > > >   return ret;
> > > > > @@ -3361,7 +3407,7 @@ int i915_gem_object_set_cache_level(struct 
> > > > > drm_i915_gem_object *obj,
> > > > >   
> > > > > i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
> > > > >  obj, cache_level);
> > > > >  
> > > > > - i915_gem_obj_ggtt_set_color(obj, cache_level);
> > > > > + i915_gem_obj_set_color(obj, vm, cache_level);
> > > > >   }
> > > > >  
> > > > >   if (cache_level == I915_CACHE_NONE) {
> > > > > @@ -3421,6 +3467,7 @@ int i915_gem_set_caching_ioctl(struct 
> > > > > drm_device *dev, void *data,
> > > > >  struct drm_file *file)
> > > > >  {
> > > > >   struct drm_i915_gem_caching *args = data;
> > > > > + struct drm_i915_private *dev_priv;
> > > > >   struct drm_i915_gem_object *obj;
> > > > >   enum i915_cache_level level;
> > > > >   int ret;
> > > > > @@ -3445,8 +3492,10 @@ int i915_gem_set_caching_ioctl(struct 
> > > > > drm_device *dev, void *data,
> > > > >   ret = -ENOENT;
> > > > >   goto unlock;
> > > > >   }
> > > > > + dev_priv = obj->base.dev->dev_private;
> > > > >  
> > > > > - ret = i915_gem_object_set_cache_level(obj, level);
> > > > > + /* FIXME: Add interface for specific VM? */
> > > > > + ret = i915_gem_object_set_cache_level(obj, &dev_priv->gtt.base, 
> > > > > level);
> > > > >  
> > > > >   drm_gem_object_unreference(&obj->base);
> > > > >  unlock:
> > > > > @@ -3464,6 +3513,7 @@ i915_gem_object_pin_to_display_plane(struct 
> > > > > drm_i915_gem_object *obj,
> > > > >u32 alignment,
> > > > >struct intel_ring_buffer 
> > > > > *pipelined)
> > > > >  {
> > > > > + struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
> > > > >   u32 old_read_domains, old_write_domain;
> > > > >   int ret;
> > > > >  
> > > > > @@ -3482,7 +3532,8 @@ i915_gem_object_pin_to_display_plane(struct 
> > > > > drm_i915_gem_object *obj,
> > > > >* of uncaching, which would allow us to flush all the 
> > > > > LLC-cached data
> > > > >* with that bit in the PTE to main memory with just one 
> > > > > PIPE_CONTROL.
> > > > >*/
> > > > > - ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
> > > > > + ret = i915_gem_object_set_cache_level(obj, &dev_priv->gtt.base,
> > > > > +   I915_CACHE_NONE);
> > > > >   if (ret)
> > > > >   return ret;
> > > > >  
> > > > > @@ -3490,7 +3541,7 @@ i915_gem_object_pin_to_display_plane(struct 
> > > > > drm_i915_gem_object *obj,
> > > > >* (e.g. libkms for the bootup splash), we have to ensure that 
> > > > > we
> > > > >* always use map_and_fenceable for all scanout buffers.
> > > > >*/
> > > > > - ret = i915_gem_object_pin(obj, alignment, true, false);
> > > > > + ret = i915_gem

Re: [Intel-gfx] [PATCH] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence

[Daniel Vetter]

On Thu, Jul 11, 2013 at 05:11:41PM +0300, Imre Deak wrote:
> This piece was not added to vlv_enable_pll. Other than this patches
> 29-31 look ok, so on those:
> 
> Reviewed-by: Imre Deak 

Ok, I've pushed the updated patch plus the other two, thanks for the
review.
-Daniel
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Re: [Intel-gfx] [PATCH 01/11] drm/i915: Move gtt and ppgtt under address space umbrella

[Ben Widawsky]

On Thu, Jul 11, 2013 at 04:57:30PM -0700, Ben Widawsky wrote:
> On Thu, Jul 11, 2013 at 02:14:06PM +0300, Imre Deak wrote:
> > On Mon, 2013-07-08 at 23:08 -0700, Ben Widawsky wrote:
> > > The GTT and PPGTT can be thought of more generally as GPU address
> > > spaces. Many of their actions (insert entries), state (LRU lists) and
> > > many of their characteristics (size), can be shared. Do that.
> > > 
> > > The change itself doesn't actually impact most of the VMA/VM rework
> > > coming up, it just fits in with the grand scheme. GGTT will usually be a
> > > special case where we either know an object must be in the GGTT (dislay
> > > engine, workarounds, etc.).
> > > 
> > > v2: Drop usage of i915_gtt_vm (Daniel)
> > > Make cleanup also part of the parent class (Ben)
> > > Modified commit msg
> > > Rebased
> > > 
> > > Signed-off-by: Ben Widawsky 
> > > ---
> > >  drivers/gpu/drm/i915/i915_debugfs.c |   4 +-
> > >  drivers/gpu/drm/i915/i915_dma.c |   4 +-
> > >  drivers/gpu/drm/i915/i915_drv.h |  57 ++---
> > >  drivers/gpu/drm/i915/i915_gem.c |   4 +-
> > >  drivers/gpu/drm/i915/i915_gem_gtt.c | 162 
> > > 
> > >  5 files changed, 121 insertions(+), 110 deletions(-)
> > > 
> > >[...]
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index 242d0f9..693115a 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -102,7 +102,7 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
> > >  
> > >  static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
> > >  {
> > > - struct drm_i915_private *dev_priv = ppgtt->dev->dev_private;
> > > + struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
> > >   gen6_gtt_pte_t __iomem *pd_addr;
> > >   uint32_t pd_entry;
> > >   int i;
> > > @@ -181,18 +181,18 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
> > >  }
> > >  
> > >  /* PPGTT support for Sandybdrige/Gen6 and later */
> > > -static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
> > > +static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
> > >  unsigned first_entry,
> > >  unsigned num_entries)
> > >  {
> > > - struct drm_i915_private *dev_priv = ppgtt->dev->dev_private;
> > > + struct i915_hw_ppgtt *ppgtt =
> > > + container_of(vm, struct i915_hw_ppgtt, base);
> > >   gen6_gtt_pte_t *pt_vaddr, scratch_pte;
> > >   unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
> > >   unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
> > >   unsigned last_pte, i;
> > >  
> > > - scratch_pte = ppgtt->pte_encode(dev_priv->gtt.scratch.addr,
> > > - I915_CACHE_LLC);
> > > + scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
> > 
> > I only see ggtt's scratch page being initialized, but can't find the
> > corresponding init/teardown for ppgtt. Btw, why do we need separate
> > global/per-process scratch pages? (would be nice to add it to the commit
> > message)
> > 
> > --Imre
> > 
> 
> There is indeed a bug here, it existed somewhere, so I've mistakenly dropped
> it. Here is my local fix, which is what I had done previously.
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 552e4cb..c8130db 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -295,6 +295,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> ppgtt->base.clear_range = gen6_ppgtt_clear_range;
> ppgtt->base.bind_object = gen6_ppgtt_bind_object;
> ppgtt->base.cleanup = gen6_ppgtt_cleanup;
> +   ppgtt->base.scratch = dev_priv->gtt.base.scratch;
> ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
>   GFP_KERNEL);
> if (!ppgtt->pt_pages)
> 
> 
> Not sure what you mean, there should be only 1 scratch page now.
>
I've updated my commit message to address what we discussed on IRC. The
VM has the scratch structure because I intend to have a scratch page per
PPGTT when we have full PPGTT.

Thanks for the insightful question ;-)
>
> 
> -- 
> Ben Widawsky, Intel Open Source Technology Center
> ___
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Re: [Intel-gfx] [PATCH 06/11] drm/i915: plumb VM into object operations

[Ben Widawsky]

On Fri, Jul 12, 2013 at 08:26:07AM +0200, Daniel Vetter wrote:
> On Thu, Jul 11, 2013 at 07:23:08PM -0700, Ben Widawsky wrote:
> > On Tue, Jul 09, 2013 at 09:15:01AM +0200, Daniel Vetter wrote:
> > > On Mon, Jul 08, 2013 at 11:08:37PM -0700, Ben Widawsky wrote:
> 
> [snip]
> 
> > > > index 058ad44..21015cd 100644
> > > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > > @@ -38,10 +38,12 @@
> > > >  
> > > >  static void i915_gem_object_flush_gtt_write_domain(struct 
> > > > drm_i915_gem_object *obj);
> > > >  static void i915_gem_object_flush_cpu_write_domain(struct 
> > > > drm_i915_gem_object *obj);
> > > > -static __must_check int i915_gem_object_bind_to_gtt(struct 
> > > > drm_i915_gem_object *obj,
> > > > -   unsigned alignment,
> > > > -   bool 
> > > > map_and_fenceable,
> > > > -   bool nonblocking);
> > > > +static __must_check int
> > > > +i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
> > > > +   struct i915_address_space *vm,
> > > > +   unsigned alignment,
> > > > +   bool map_and_fenceable,
> > > > +   bool nonblocking);
> > > >  static int i915_gem_phys_pwrite(struct drm_device *dev,
> > > > struct drm_i915_gem_object *obj,
> > > > struct drm_i915_gem_pwrite *args,
> > > > @@ -135,7 +137,7 @@ int i915_mutex_lock_interruptible(struct drm_device 
> > > > *dev)
> > > >  static inline bool
> > > >  i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
> > > >  {
> > > > -   return i915_gem_obj_ggtt_bound(obj) && !obj->active;
> > > > +   return i915_gem_obj_bound_any(obj) && !obj->active;
> > > >  }
> > > >  
> > > >  int
> > > > @@ -422,7 +424,7 @@ i915_gem_shmem_pread(struct drm_device *dev,
> > > >  * anyway again before the next pread happens. */
> > > > if (obj->cache_level == I915_CACHE_NONE)
> > > > needs_clflush = 1;
> > > > -   if (i915_gem_obj_ggtt_bound(obj)) {
> > > > +   if (i915_gem_obj_bound_any(obj)) {
> > > > ret = i915_gem_object_set_to_gtt_domain(obj, 
> > > > false);
> > > 
> > > This is essentially a very convoluted version of "if there's gpu rendering
> > > outstanding, please wait for it". Maybe we should switch this to
> > > 
> > >   if (obj->active)
> > >   wait_rendering(obj, true);
> > > 
> > > Same for the shmem_pwrite case below. Would be a separate patch to prep
> > > things though. Can I volunteer you for that? The ugly part is to review
> > > whether any of the lru list updating that set_domain does in addition to
> > > wait_rendering is required, but on a quick read that's not the case.
> > 
> > Just reading the comment above it says we need the clflush. I don't
> > actually understand why we do that even after reading the comment, but
> > meh. You tell me, I don't mind doing this as a prep first.
> 
> The comment right above is just for the needs_clflush = 1 assignment, the
> set_to_gtt_domain call afterwards is just to sync up with the gpu. The
> code is confusing and tricky and the lack of a white line in between the
> two things plus a comment explaining that we only care about the
> wait_rendering side-effect of set_to_gtt_domain doesn't help. If you do
> the proposed conversion (and add a white line) that should help a lot in
> unconfusing readers.
> 
> [snip]
> 
> > > > @@ -,12 +3376,15 @@ int i915_gem_object_set_cache_level(struct 
> > > > drm_i915_gem_object *obj,
> > > > }
> > > >  
> > > > if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
> > > > -   ret = i915_gem_object_unbind(obj);
> > > > +   ret = i915_gem_object_unbind(obj, vm);
> > > > if (ret)
> > > > return ret;
> > > > }
> > > >  
> > > > -   if (i915_gem_obj_ggtt_bound(obj)) {
> > > > +   list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
> > > > +   if (!i915_gem_obj_bound(obj, vm))
> > > > +   continue;
> > > 
> > > Hm, shouldn't we have a per-object list of vmas? Or will that follow later
> > > on?
> > > 
> > > Self-correction: It exists already ... why can't we use this here?
> > 
> > Yes. That should work, I'll fix it and test it. It looks slightly worse
> > IMO in terms of code clarity, but I don't mind the change.
> 
> Actually I think it'd gain in clarity, doing pte updatest (which
> set_cache_level does) on the vma instead of the (obj, vm) pair feels more
> natural. And we'd be able to drop lots of (obj, vm) -> vma lookups here.

That sounds good to me. Would you mind a patch on top?

> 
> > 
> > > 
> > > > +
> > > > ret = i915_gem_object_

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't attempt to read an unitialized stack value

[Daniel Vetter]

On Fri, Jul 12, 2013 at 04:24:40PM +0100, Damien Lespiau wrote:
> If intel_sdvo_get_value() fails here, val is unitialized and the cross
> check will compare the pipe config multiplier with a bogus value.
> 
> Instead, only set encoder_pixel_multiplier when the sdvo command has
> been successful. The cross check will compare the pipe config value with
> 0 otherwise.
> 
> v2: Do the cross check with the initial value of encoder_pixel_multiplier (0)
> if the sdvo command fails (and thus keep the warning) (Daniel Vetter)
> 
> Signed-off-by: Damien Lespiau 
Queued for -next, thanks for the patch.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 24 +---
>  1 file changed, 13 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
> b/drivers/gpu/drm/i915/intel_sdvo.c
> index b8e1623..eb2a603 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1357,17 +1357,19 @@ static void intel_sdvo_get_config(struct 
> intel_encoder *encoder,
>   }
>  
>   /* Cross check the port pixel multiplier with the sdvo encoder state. */
> - intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
> - switch (val) {
> - case SDVO_CLOCK_RATE_MULT_1X:
> - encoder_pixel_multiplier = 1;
> - break;
> - case SDVO_CLOCK_RATE_MULT_2X:
> - encoder_pixel_multiplier = 2;
> - break;
> - case SDVO_CLOCK_RATE_MULT_4X:
> - encoder_pixel_multiplier = 4;
> - break;
> + if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
> +  &val, 1)) {
> + switch (val) {
> + case SDVO_CLOCK_RATE_MULT_1X:
> + encoder_pixel_multiplier = 1;
> + break;
> + case SDVO_CLOCK_RATE_MULT_2X:
> + encoder_pixel_multiplier = 2;
> + break;
> + case SDVO_CLOCK_RATE_MULT_4X:
> + encoder_pixel_multiplier = 4;
> + break;
> + }
>   }
>  
>   if(HAS_PCH_SPLIT(dev))
> -- 
> 1.8.3.1
> 
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[Intel-gfx] [PATCH 1/2] drm/i915: Don't attempt to read an unitialized stack value

[Damien Lespiau]

If intel_sdvo_get_value() fails here, val is unitialized and the cross
check will compare the pipe config multiplier with a bogus value.

Instead, only set encoder_pixel_multiplier when the sdvo command has
been successful. The cross check will compare the pipe config value with
0 otherwise.

v2: Do the cross check with the initial value of encoder_pixel_multiplier (0)
if the sdvo command fails (and thus keep the warning) (Daniel Vetter)

Signed-off-by: Damien Lespiau 
---
 drivers/gpu/drm/i915/intel_sdvo.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
b/drivers/gpu/drm/i915/intel_sdvo.c
index b8e1623..eb2a603 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1357,17 +1357,19 @@ static void intel_sdvo_get_config(struct intel_encoder 
*encoder,
}
 
/* Cross check the port pixel multiplier with the sdvo encoder state. */
-   intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
-   switch (val) {
-   case SDVO_CLOCK_RATE_MULT_1X:
-   encoder_pixel_multiplier = 1;
-   break;
-   case SDVO_CLOCK_RATE_MULT_2X:
-   encoder_pixel_multiplier = 2;
-   break;
-   case SDVO_CLOCK_RATE_MULT_4X:
-   encoder_pixel_multiplier = 4;
-   break;
+   if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
+&val, 1)) {
+   switch (val) {
+   case SDVO_CLOCK_RATE_MULT_1X:
+   encoder_pixel_multiplier = 1;
+   break;
+   case SDVO_CLOCK_RATE_MULT_2X:
+   encoder_pixel_multiplier = 2;
+   break;
+   case SDVO_CLOCK_RATE_MULT_4X:
+   encoder_pixel_multiplier = 4;
+   break;
+   }
}
 
if(HAS_PCH_SPLIT(dev))
-- 
1.8.3.1

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[Intel-gfx] [PATCH 1/6] drm/i915: Colocate all GT access routines in the same file

[Chris Wilson]

Currently, the register access code is split between i915_drv.c and
intel_pm.c. It only bares a superficial resemblance to the reset of the
powermanagement code, so move it all into its own file. This is to ease
further patches to enforce serialised register access.

v2: Scan for random abuse of I915_WRITE_NOTRACE

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_dma.c  |   6 +-
 drivers/gpu/drm/i915/i915_drv.c  | 264 
 drivers/gpu/drm/i915/i915_drv.h  |   6 +-
 drivers/gpu/drm/i915/i915_irq.c  |   6 +-
 drivers/gpu/drm/i915/intel_display.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h |   1 -
 drivers/gpu/drm/i915/intel_gt.c  | 566 +++
 drivers/gpu/drm/i915/intel_pm.c  | 258 +---
 9 files changed, 584 insertions(+), 527 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_gt.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 40034ec..f1c5845 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
  intel_modes.o \
  intel_panel.o \
  intel_pm.o \
+ intel_gt.o \
  intel_i2c.o \
  intel_fb.o \
  intel_tv.o \
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 6ce9033..1eb4c96 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1445,10 +1445,7 @@ static void i915_dump_device_info(struct 
drm_i915_private *dev_priv)
  */
 static void intel_early_sanitize_regs(struct drm_device *dev)
 {
-   struct drm_i915_private *dev_priv = dev->dev_private;
-
-   if (HAS_FPGA_DBG_UNCLAIMED(dev))
-   I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+   intel_gt_early_sanitize(dev);
 }
 
 /**
@@ -1581,6 +1578,7 @@ int i915_driver_load(struct drm_device *dev, unsigned 
long flags)
 
intel_irq_init(dev);
intel_gt_init(dev);
+   intel_pm_init(dev);
 
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b07362f..0698413 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -761,140 +761,6 @@ int i915_resume(struct drm_device *dev)
return 0;
 }
 
-static int i8xx_do_reset(struct drm_device *dev)
-{
-   struct drm_i915_private *dev_priv = dev->dev_private;
-
-   if (IS_I85X(dev))
-   return -ENODEV;
-
-   I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
-   POSTING_READ(D_STATE);
-
-   if (IS_I830(dev) || IS_845G(dev)) {
-   I915_WRITE(DEBUG_RESET_I830,
-  DEBUG_RESET_DISPLAY |
-  DEBUG_RESET_RENDER |
-  DEBUG_RESET_FULL);
-   POSTING_READ(DEBUG_RESET_I830);
-   msleep(1);
-
-   I915_WRITE(DEBUG_RESET_I830, 0);
-   POSTING_READ(DEBUG_RESET_I830);
-   }
-
-   msleep(1);
-
-   I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
-   POSTING_READ(D_STATE);
-
-   return 0;
-}
-
-static int i965_reset_complete(struct drm_device *dev)
-{
-   u8 gdrst;
-   pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
-   return (gdrst & GRDOM_RESET_ENABLE) == 0;
-}
-
-static int i965_do_reset(struct drm_device *dev)
-{
-   int ret;
-
-   /*
-* Set the domains we want to reset (GRDOM/bits 2 and 3) as
-* well as the reset bit (GR/bit 0).  Setting the GR bit
-* triggers the reset; when done, the hardware will clear it.
-*/
-   pci_write_config_byte(dev->pdev, I965_GDRST,
- GRDOM_RENDER | GRDOM_RESET_ENABLE);
-   ret =  wait_for(i965_reset_complete(dev), 500);
-   if (ret)
-   return ret;
-
-   /* We can't reset render&media without also resetting display ... */
-   pci_write_config_byte(dev->pdev, I965_GDRST,
- GRDOM_MEDIA | GRDOM_RESET_ENABLE);
-
-   ret =  wait_for(i965_reset_complete(dev), 500);
-   if (ret)
-   return ret;
-
-   pci_write_config_byte(dev->pdev, I965_GDRST, 0);
-
-   return 0;
-}
-
-static int ironlake_do_reset(struct drm_device *dev)
-{
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   u32 gdrst;
-   int ret;
-
-   gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
-   gdrst &= ~GRDOM_MASK;
-   I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
-  gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
-   ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
-   if (ret)
-   return ret;
-
-   /* We can't reset render&media without also resetting display ... */
-   gdrst = I915_READ(M

Re: [Intel-gfx] [PATCH] drm/i915: fix pfit regression for non-autoscaled resolutions

[Jesse Barnes]

On Fri, 12 Jul 2013 08:07:30 +0200
Daniel Vetter  wrote:

> I.e. for letter/pillarboxing. For those cases we need to adjust the
> mode a bit, but Jesse gmch pfit refactoring in
> 
> commit 2dd24552cab40ea829ba3fda890eeafd2c4816d8
> Author: Jesse Barnes 
> Date:   Thu Apr 25 12:55:01 2013 -0700
> 
> drm/i915: factor out GMCH panel fitting code and use for eDP v3
> 
> broke that by reordering the computation of the gmch pfit state with
> the block of code that prepared the adjusted mode for it and told the
> modeset core not to overwrite the adjusted mode with default settings.
> 
> We might want to switch around the core code to just fill in defaults,
> but this code predates the pipe_config modeset rework. And in the old
> crtc helpers we did not have a suitable spot to do this.
> 
> Cc: Mika Kuoppala 
> Cc: Jesse Barnes 
> Cc: Hans de Bruin 
> Reported-and-tested-by: Hans de Bruin 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/i915/intel_lvds.c  | 5 +
>  drivers/gpu/drm/i915/intel_panel.c | 3 +++
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
> b/drivers/gpu/drm/i915/intel_lvds.c
> index b0e1088..0536c9b 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -297,14 +297,11 @@ static bool intel_lvds_compute_config(struct 
> intel_encoder *intel_encoder,
>  
>   intel_pch_panel_fitting(intel_crtc, pipe_config,
>   intel_connector->panel.fitting_mode);
> - return true;
>   } else {
>   intel_gmch_panel_fitting(intel_crtc, pipe_config,
>intel_connector->panel.fitting_mode);
> - }
>  
> - drm_mode_set_crtcinfo(adjusted_mode, 0);
> - pipe_config->timings_set = true;
> + }
>  
>   /*
>* XXX: It would be nice to support lower refresh rates on the
> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> b/drivers/gpu/drm/i915/intel_panel.c
> index 80bea1d..45010bb 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -194,6 +194,9 @@ void intel_gmch_panel_fitting(struct intel_crtc 
> *intel_crtc,
>   adjusted_mode->vdisplay == mode->vdisplay)
>   goto out;
>  
> + drm_mode_set_crtcinfo(adjusted_mode, 0);
> + pipe_config->timings_set = true;
> +
>   switch (fitting_mode) {
>   case DRM_MODE_SCALE_CENTER:
>   /*

This code is a bit confusing, but this looks better than what was there
before (clobbering the adjusted_mode after calling gmch_panel_fitting
definitely seems wrong).  Only nit is that the timings_set flag isn't
very descriptive, but that's not the fault of this patch.

Reviewed-by: Jesse Barnes 

-- 
Jesse Barnes, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 2/6] drm/i915: Use a private interface for register access within GT

[Chris Wilson]

The GT functions for enabling register access also need to occasionally
write to and read from registers. To avoid the potential recursion as we
modify the public interface to be stricter, introduce a private register
access API for the GT functions.

v2: Rebase

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_gt.c | 107 
 1 file changed, 64 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index 8046d05..b475f84 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -26,6 +26,19 @@
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
+#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
+#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, 
(dev_priv__)->regs + (reg__))
+
+
 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 {
u32 gt_thread_status_mask;
@@ -38,26 +51,27 @@ static void __gen6_gt_wait_for_thread_c0(struct 
drm_i915_private *dev_priv)
/* w/a for a sporadic read returning 0 by waiting for the GT
 * thread to wake up.
 */
-   if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & 
gt_thread_status_mask) == 0, 500))
+   if (wait_for_atomic_us((__raw_i915_read32(dev_priv, 
GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
DRM_ERROR("GT thread status wait timed out\n");
 }
 
 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE_NOTRACE(FORCEWAKE, 0);
-   POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
*/
+   __raw_i915_write32(dev_priv, FORCEWAKE, 0);
+   /* something from same cacheline, but !FORCEWAKE */
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 }
 
 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 {
-   if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 
0,
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake old ack to 
clear.\n");
 
-   I915_WRITE_NOTRACE(FORCEWAKE, 1);
-   POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
*/
+   __raw_i915_write32(dev_priv, FORCEWAKE, 1);
+   (void)__raw_i915_read32(dev_priv, ECOBUS); /* something from same 
cacheline, but !FORCEWAKE */
 
-   if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 
@@ -67,9 +81,9 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private 
*dev_priv)
 
 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
+   __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
/* something from same cacheline, but !FORCEWAKE_MT */
-   POSTING_READ(ECOBUS);
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 }
 
 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
@@ -81,15 +95,16 @@ static void __gen6_gt_force_wake_mt_get(struct 
drm_i915_private *dev_priv)
else
forcewake_ack = FORCEWAKE_MT_ACK;
 
-   if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 
FORCEWAKE_KERNEL) == 0,
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & 
FORCEWAKE_KERNEL) == 0,
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake old ack to 
clear.\n");
 
-   I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
+   __raw_i915_write32(dev_priv, FORCEWAKE_MT,
+  _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
/* something from same cacheline, but !FORCEWAKE_MT */
-   POSTING_READ(ECOBUS);
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 
-   if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 
FORCEWAKE_KERNEL),
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & 
FORCEWAKE_KERNEL),
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed 

[Intel-gfx] [PATCH 3/6] drm/i915: Use the common register access functions for NOTRACE variants

[Chris Wilson]

Detangle the confusion that NOTRACE variants of the register read/write
routines were directly using the raw register access. We need for those
routines to reuse the common code for serializing register access and
ensuring the correct register power states. This is only possible now
that the only routines that required raw access use their own API.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h | 28 ++--
 drivers/gpu/drm/i915/intel_gt.c |  8 
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1715d3f..01ce148 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2086,7 +2086,7 @@ int vlv_gpu_freq(int ddr_freq, int val);
 int vlv_freq_opcode(int ddr_freq, int val);
 
 #define __i915_read(x, y) \
-   u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
+   u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool 
trace);
 
 __i915_read(8, b)
 __i915_read(16, w)
@@ -2095,7 +2095,7 @@ __i915_read(64, q)
 #undef __i915_read
 
 #define __i915_write(x, y) \
-   void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
val);
+   void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
val, bool trace);
 
 __i915_write(8, b)
 __i915_write(16, w)
@@ -2103,21 +2103,21 @@ __i915_write(32, l)
 __i915_write(64, q)
 #undef __i915_write
 
-#define I915_READ8(reg)i915_read8(dev_priv, (reg))
-#define I915_WRITE8(reg, val)  i915_write8(dev_priv, (reg), (val))
+#define I915_READ8(reg)i915_read8(dev_priv, (reg), true)
+#define I915_WRITE8(reg, val)  i915_write8(dev_priv, (reg), (val), true)
 
-#define I915_READ16(reg)   i915_read16(dev_priv, (reg))
-#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
-#define I915_READ16_NOTRACE(reg)   readw(dev_priv->regs + (reg))
-#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
+#define I915_READ16(reg)   i915_read16(dev_priv, (reg), true)
+#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true)
+#define I915_READ16_NOTRACE(reg)   i915_read16(dev_priv, (reg), false)
+#define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), 
false)
 
-#define I915_READ(reg) i915_read32(dev_priv, (reg))
-#define I915_WRITE(reg, val)   i915_write32(dev_priv, (reg), (val))
-#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
-#define I915_WRITE_NOTRACE(reg, val)   writel(val, dev_priv->regs + (reg))
+#define I915_READ(reg) i915_read32(dev_priv, (reg), true)
+#define I915_WRITE(reg, val)   i915_write32(dev_priv, (reg), (val), true)
+#define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false)
+#define I915_WRITE_NOTRACE(reg, val)   i915_write32(dev_priv, (reg), (val), 
false)
 
-#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
-#define I915_READ64(reg)   i915_read64(dev_priv, (reg))
+#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true)
+#define I915_READ64(reg)   i915_read64(dev_priv, (reg), true)
 
 #define POSTING_READ(reg)  (void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)(void)I915_READ16_NOTRACE(reg)
diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index b475f84..257a2e9 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -338,7 +338,7 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, 
u32 reg)
 }
 
 #define __i915_read(x, y) \
-u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
+u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
u##x val = 0; \
if (IS_GEN5(dev_priv->dev)) \
ilk_dummy_write(dev_priv); \
@@ -354,7 +354,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg) { \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
-   trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+   if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
 }
 
@@ -365,9 +365,9 @@ __i915_read(64, q)
 #undef __i915_read
 
 #define __i915_write(x, y) \
-void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
+void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
u32 __fifo_ret = 0; \
-   trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 5/6] drm/i915: Squash gen lookup through multiple indirections inside GT access

[Chris Wilson]

The INTEL_INFO() macro extracts the dev_private pointer from the device,
so passing in the dev_private->dev is a long winded circumlocution.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_gt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index 9eeaefb..3dabbb1 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -342,7 +342,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg, bool trace) { \
unsigned long irqflags; \
u##x val = 0; \
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
-   if (IS_GEN5(dev_priv->dev)) \
+   if (dev_priv->info->gen == 5) \
ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
if (dev_priv->forcewake_count == 0) \
@@ -373,7 +373,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 
reg, u##x val, bool tr
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
-   if (IS_GEN5(dev_priv->dev)) \
+   if (dev_priv->info->gen == 5) \
ilk_dummy_write(dev_priv); \
hsw_unclaimed_reg_clear(dev_priv, reg); \
write##y(val, dev_priv->regs + reg); \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 6/6] drm/i915: Convert the register access tracepoint to be conditional

[Chris Wilson]

The TRACE_EVENT_CONDITION is supposed to generate more efficient code
than if (cond) trace(), which is what we are currently using inside the
register access functions.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
 drivers/gpu/drm/i915/i915_trace.h   | 8 +---
 drivers/gpu/drm/i915/intel_gt.c | 4 ++--
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d413812..29163a7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1415,7 +1415,7 @@ static int gen6_drpc_info(struct seq_file *m)
}
 
gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
-   trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
+   trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 7d283b5..2933e2f 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -406,10 +406,12 @@ TRACE_EVENT(i915_flip_complete,
TP_printk("plane=%d, obj=%p", __entry->plane, __entry->obj)
 );
 
-TRACE_EVENT(i915_reg_rw,
-   TP_PROTO(bool write, u32 reg, u64 val, int len),
+TRACE_EVENT_CONDITION(i915_reg_rw,
+   TP_PROTO(bool write, u32 reg, u64 val, int len, bool trace),
 
-   TP_ARGS(write, reg, val, len),
+   TP_ARGS(write, reg, val, len, trace),
+
+   TP_CONDITION(trace),
 
TP_STRUCT__entry(
__field(u64, val)
diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index 3dabbb1..e417247 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -354,7 +354,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg, bool trace) { \
val = read##y(dev_priv->regs + reg); \
} \
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
-   if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+   trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val; \
 }
 
@@ -368,7 +368,7 @@ __i915_read(64, q)
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
unsigned long irqflags; \
u32 __fifo_ret = 0; \
-   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 4/6] drm/i915: Serialize all register access

[Chris Wilson]

In theory, the different register blocks were meant to be only ever
touched when holding either the struct_mutex, mode_config.lock or even a
specific localised lock. This does not seem to be the case, and the
hardware reacts extremely badly if we attempt to concurrently access two
registers within the same cacheline.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63914
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_gt.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index 257a2e9..9eeaefb 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -339,21 +339,21 @@ hsw_unclaimed_reg_check(struct drm_i915_private 
*dev_priv, u32 reg)
 
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
+   unsigned long irqflags; \
u##x val = 0; \
+   spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (IS_GEN5(dev_priv->dev)) \
ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
-   unsigned long irqflags; \
-   spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (dev_priv->forcewake_count == 0) \
dev_priv->gt.force_wake_get(dev_priv); \
val = read##y(dev_priv->regs + reg); \
if (dev_priv->forcewake_count == 0) \
dev_priv->gt.force_wake_put(dev_priv); \
-   spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
+   spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
 }
@@ -366,8 +366,10 @@ __i915_read(64, q)
 
 #define __i915_write(x, y) \
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
+   unsigned long irqflags; \
u32 __fifo_ret = 0; \
if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
@@ -379,6 +381,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 
reg, u##x val, bool tr
gen6_gt_check_fifodbg(dev_priv); \
} \
hsw_unclaimed_reg_check(dev_priv, reg); \
+   spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
 }
 __i915_write(8, b)
 __i915_write(16, w)
-- 
1.8.3.2

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[Intel-gfx] [PATCH 2/6] drm/i915: Use a private interface for register access within GT

[Chris Wilson]

The GT functions for enabling register access also need to occasionally
write to and read from registers. To avoid the potential recursion as we
modify the public interface to be stricter, introduce a private register
access API for the GT functions.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_gt.c | 92 +
 1 file changed, 56 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index 060e256..cb3116c 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -26,6 +26,19 @@
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
+#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
+#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
(dev_priv__)->regs + (reg__))
+
+#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, 
(dev_priv__)->regs + (reg__))
+
+
 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 {
u32 gt_thread_status_mask;
@@ -38,26 +51,27 @@ static void __gen6_gt_wait_for_thread_c0(struct 
drm_i915_private *dev_priv)
/* w/a for a sporadic read returning 0 by waiting for the GT
 * thread to wake up.
 */
-   if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & 
gt_thread_status_mask) == 0, 500))
+   if (wait_for_atomic_us((__raw_i915_read32(dev_priv, 
GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
DRM_ERROR("GT thread status wait timed out\n");
 }
 
 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE_NOTRACE(FORCEWAKE, 0);
-   POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
*/
+   __raw_i915_write32(dev_priv, FORCEWAKE, 0);
+   /* something from same cacheline, but !FORCEWAKE */
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 }
 
 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 {
-   if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 
0,
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake old ack to 
clear.\n");
 
-   I915_WRITE_NOTRACE(FORCEWAKE, 1);
-   POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE 
*/
+   __raw_i915_write32(dev_priv, FORCEWAKE, 1);
+   (void)__raw_i915_read32(dev_priv, ECOBUS); /* something from same 
cacheline, but !FORCEWAKE */
 
-   if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 
@@ -67,9 +81,9 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private 
*dev_priv)
 
 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
+   __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0x));
/* something from same cacheline, but !FORCEWAKE_MT */
-   POSTING_READ(ECOBUS);
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 }
 
 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
@@ -81,15 +95,16 @@ static void __gen6_gt_force_wake_mt_get(struct 
drm_i915_private *dev_priv)
else
forcewake_ack = FORCEWAKE_MT_ACK;
 
-   if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 
FORCEWAKE_KERNEL) == 0,
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & 
FORCEWAKE_KERNEL) == 0,
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake old ack to 
clear.\n");
 
-   I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
+   __raw_i915_write32(dev_priv, FORCEWAKE_MT,
+  _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
/* something from same cacheline, but !FORCEWAKE_MT */
-   POSTING_READ(ECOBUS);
+   (void)__raw_i915_read32(dev_priv, ECOBUS);
 
-   if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 
FORCEWAKE_KERNEL),
+   if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & 
FORCEWAKE_KERNEL),
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting 

[Intel-gfx] [PATCH 3/6] drm/i915: Use the common register access functions for NOTRACE variants

[Chris Wilson]

Detangle the confusion that NOTRACE variants of the register read/write
routines were directly using the raw register access. We need for those
routines to reuse the common code for serializing register access and
ensuring the correct register power states. This is only possible now
that the only routines that required raw access use their own API.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h | 28 ++--
 drivers/gpu/drm/i915/intel_gt.c |  8 
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f140b04..1ab6d4e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2082,7 +2082,7 @@ int vlv_gpu_freq(int ddr_freq, int val);
 int vlv_freq_opcode(int ddr_freq, int val);
 
 #define __i915_read(x, y) \
-   u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
+   u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool 
trace);
 
 __i915_read(8, b)
 __i915_read(16, w)
@@ -2091,7 +2091,7 @@ __i915_read(64, q)
 #undef __i915_read
 
 #define __i915_write(x, y) \
-   void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
val);
+   void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x 
val, bool trace);
 
 __i915_write(8, b)
 __i915_write(16, w)
@@ -2099,21 +2099,21 @@ __i915_write(32, l)
 __i915_write(64, q)
 #undef __i915_write
 
-#define I915_READ8(reg)i915_read8(dev_priv, (reg))
-#define I915_WRITE8(reg, val)  i915_write8(dev_priv, (reg), (val))
+#define I915_READ8(reg)i915_read8(dev_priv, (reg), true)
+#define I915_WRITE8(reg, val)  i915_write8(dev_priv, (reg), (val), true)
 
-#define I915_READ16(reg)   i915_read16(dev_priv, (reg))
-#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
-#define I915_READ16_NOTRACE(reg)   readw(dev_priv->regs + (reg))
-#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
+#define I915_READ16(reg)   i915_read16(dev_priv, (reg), true)
+#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true)
+#define I915_READ16_NOTRACE(reg)   i915_read16(dev_priv, (reg), false)
+#define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), 
false)
 
-#define I915_READ(reg) i915_read32(dev_priv, (reg))
-#define I915_WRITE(reg, val)   i915_write32(dev_priv, (reg), (val))
-#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
-#define I915_WRITE_NOTRACE(reg, val)   writel(val, dev_priv->regs + (reg))
+#define I915_READ(reg) i915_read32(dev_priv, (reg), true)
+#define I915_WRITE(reg, val)   i915_write32(dev_priv, (reg), (val), true)
+#define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false)
+#define I915_WRITE_NOTRACE(reg, val)   i915_write32(dev_priv, (reg), (val), 
false)
 
-#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
-#define I915_READ64(reg)   i915_read64(dev_priv, (reg))
+#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true)
+#define I915_READ64(reg)   i915_read64(dev_priv, (reg), true)
 
 #define POSTING_READ(reg)  (void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)(void)I915_READ16_NOTRACE(reg)
diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index cb3116c..d4bc7f4 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -330,7 +330,7 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, 
u32 reg)
 }
 
 #define __i915_read(x, y) \
-u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
+u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
u##x val = 0; \
if (IS_GEN5(dev_priv->dev)) \
ilk_dummy_write(dev_priv); \
@@ -346,7 +346,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg) { \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
-   trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+   if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
 }
 
@@ -357,9 +357,9 @@ __i915_read(64, q)
 #undef __i915_read
 
 #define __i915_write(x, y) \
-void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
+void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
u32 __fifo_ret = 0; \
-   trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 6/6] drm/i915: Convert the register access tracepoint to be conditional

[Chris Wilson]

The TRACE_EVENT_CONDITION is supposed to generate more efficient code
than if (cond) trace(), which is what we are currently using inside the
register access functions.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
 drivers/gpu/drm/i915/i915_trace.h   | 8 +---
 drivers/gpu/drm/i915/intel_gt.c | 4 ++--
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d413812..29163a7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1415,7 +1415,7 @@ static int gen6_drpc_info(struct seq_file *m)
}
 
gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
-   trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
+   trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index 7d283b5..2933e2f 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -406,10 +406,12 @@ TRACE_EVENT(i915_flip_complete,
TP_printk("plane=%d, obj=%p", __entry->plane, __entry->obj)
 );
 
-TRACE_EVENT(i915_reg_rw,
-   TP_PROTO(bool write, u32 reg, u64 val, int len),
+TRACE_EVENT_CONDITION(i915_reg_rw,
+   TP_PROTO(bool write, u32 reg, u64 val, int len, bool trace),
 
-   TP_ARGS(write, reg, val, len),
+   TP_ARGS(write, reg, val, len, trace),
+
+   TP_CONDITION(trace),
 
TP_STRUCT__entry(
__field(u64, val)
diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index cfa18fe..f6c22fd 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -346,7 +346,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg, bool trace) { \
val = read##y(dev_priv->regs + reg); \
} \
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
-   if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+   trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val; \
 }
 
@@ -360,7 +360,7 @@ __i915_read(64, q)
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
unsigned long irqflags; \
u32 __fifo_ret = 0; \
-   if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 5/6] drm/i915: Squash gen lookup through multiple indirections inside GT access

[Chris Wilson]

The INTEL_INFO() macro extracts the dev_private pointer from the device,
so passing in the dev_private->dev is a long winded circumlocution.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_gt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index e89e901..cfa18fe 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -334,7 +334,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg, bool trace) { \
unsigned long irqflags; \
u##x val = 0; \
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
-   if (IS_GEN5(dev_priv->dev)) \
+   if (dev_priv->info->gen == 5) \
ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
if (dev_priv->forcewake_count == 0) \
@@ -365,7 +365,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 
reg, u##x val, bool tr
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
-   if (IS_GEN5(dev_priv->dev)) \
+   if (dev_priv->info->gen == 5) \
ilk_dummy_write(dev_priv); \
hsw_unclaimed_reg_clear(dev_priv, reg); \
write##y(val, dev_priv->regs + reg); \
-- 
1.8.3.2

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[Intel-gfx] [PATCH 1/6] drm/i915: Colocate all GT access routines in the same file

[Chris Wilson]

Currently, the register access code is split between i915_drv.c and
intel_pm.c. It only bares a superficial resemblance to the reset of the
powermanagement code, so move it all into its own file. This is to ease
further patches to enforce serialised register access.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_drv.c  | 130 -
 drivers/gpu/drm/i915/i915_drv.h  |   2 +-
 drivers/gpu/drm/i915/intel_drv.h |   1 -
 drivers/gpu/drm/i915/intel_gt.c  | 405 +++
 drivers/gpu/drm/i915/intel_pm.c  | 258 +
 6 files changed, 415 insertions(+), 382 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_gt.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 40034ec..f1c5845 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
  intel_modes.o \
  intel_panel.o \
  intel_pm.o \
+ intel_gt.o \
  intel_i2c.o \
  intel_fb.o \
  intel_tv.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b07362f..8bddb6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1224,133 +1224,3 @@ module_exit(i915_exit);
 MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL and additional rights");
-
-/* We give fast paths for the really cool registers */
-#define NEEDS_FORCE_WAKE(dev_priv, reg) \
-   ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
-((reg) < 0x4) &&\
-((reg) != FORCEWAKE))
-static void
-ilk_dummy_write(struct drm_i915_private *dev_priv)
-{
-   /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
-* the chip from rc6 before touching it for real. MI_MODE is masked,
-* hence harmless to write 0 into. */
-   I915_WRITE_NOTRACE(MI_MODE, 0);
-}
-
-static void
-hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
-{
-   if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
-   (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
-   DRM_ERROR("Unknown unclaimed register before writing to %x\n",
- reg);
-   I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
-   }
-}
-
-static void
-hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
-{
-   if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
-   (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
-   DRM_ERROR("Unclaimed write to %x\n", reg);
-   I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
-   }
-}
-
-#define __i915_read(x, y) \
-u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
-   u##x val = 0; \
-   if (IS_GEN5(dev_priv->dev)) \
-   ilk_dummy_write(dev_priv); \
-   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
-   unsigned long irqflags; \
-   spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
-   if (dev_priv->forcewake_count == 0) \
-   dev_priv->gt.force_wake_get(dev_priv); \
-   val = read##y(dev_priv->regs + reg); \
-   if (dev_priv->forcewake_count == 0) \
-   dev_priv->gt.force_wake_put(dev_priv); \
-   spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
-   } else { \
-   val = read##y(dev_priv->regs + reg); \
-   } \
-   trace_i915_reg_rw(false, reg, val, sizeof(val)); \
-   return val; \
-}
-
-__i915_read(8, b)
-__i915_read(16, w)
-__i915_read(32, l)
-__i915_read(64, q)
-#undef __i915_read
-
-#define __i915_write(x, y) \
-void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
-   u32 __fifo_ret = 0; \
-   trace_i915_reg_rw(true, reg, val, sizeof(val)); \
-   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
-   __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
-   } \
-   if (IS_GEN5(dev_priv->dev)) \
-   ilk_dummy_write(dev_priv); \
-   hsw_unclaimed_reg_clear(dev_priv, reg); \
-   write##y(val, dev_priv->regs + reg); \
-   if (unlikely(__fifo_ret)) { \
-   gen6_gt_check_fifodbg(dev_priv); \
-   } \
-   hsw_unclaimed_reg_check(dev_priv, reg); \
-}
-__i915_write(8, b)
-__i915_write(16, w)
-__i915_write(32, l)
-__i915_write(64, q)
-#undef __i915_write
-
-static const struct register_whitelist {
-   uint64_t offset;
-   uint32_t size;
-   uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, 
etc. */
-} whitelist[] = {
-   { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
-};
-
-int i915_reg_read_ioctl(struct drm_device *dev,
-   void *data, struct drm_file *file)
-{
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_i915_reg_rea

[Intel-gfx] [PATCH 4/6] drm/i915: Serialize all register access

[Chris Wilson]

In theory, the different register blocks were meant to be only ever
touched when holding either the struct_mutex, mode_config.lock or even a
specific localised lock. This does not seem to be the case, and the
hardware reacts extremely badly if we attempt to concurrently access two
registers within the same cacheline.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63914
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_gt.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt.c b/drivers/gpu/drm/i915/intel_gt.c
index d4bc7f4..e89e901 100644
--- a/drivers/gpu/drm/i915/intel_gt.c
+++ b/drivers/gpu/drm/i915/intel_gt.c
@@ -331,21 +331,21 @@ hsw_unclaimed_reg_check(struct drm_i915_private 
*dev_priv, u32 reg)
 
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
+   unsigned long irqflags; \
u##x val = 0; \
+   spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (IS_GEN5(dev_priv->dev)) \
ilk_dummy_write(dev_priv); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
-   unsigned long irqflags; \
-   spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (dev_priv->forcewake_count == 0) \
dev_priv->gt.force_wake_get(dev_priv); \
val = read##y(dev_priv->regs + reg); \
if (dev_priv->forcewake_count == 0) \
dev_priv->gt.force_wake_put(dev_priv); \
-   spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
+   spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
 }
@@ -358,8 +358,10 @@ __i915_read(64, q)
 
 #define __i915_write(x, y) \
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool 
trace) { \
+   unsigned long irqflags; \
u32 __fifo_ret = 0; \
if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+   spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
@@ -371,6 +373,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 
reg, u##x val, bool tr
gen6_gt_check_fifodbg(dev_priv); \
} \
hsw_unclaimed_reg_check(dev_priv, reg); \
+   spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
 }
 __i915_write(8, b)
 __i915_write(16, w)
-- 
1.8.3.2

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[Intel-gfx] [PATCH] tools/inter_error_decode: decode for ctl and acthd

[Mika Kuoppala]

Signed-off-by: Mika Kuoppala 
---
 tools/intel_error_decode.c |   35 +--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index 434c13a..b3d7efb 100644
--- a/tools/intel_error_decode.c
+++ b/tools/intel_error_decode.c
@@ -62,6 +62,31 @@ print_head(unsigned int reg)
return reg & (0x7<<2);
 }
 
+static uint32_t
+print_ctl(unsigned int reg)
+{
+   uint32_t ring_length =  (((reg & (0x1ff << 12)) >> 12) + 1) * 4096;
+
+#define BIT_STR(reg, x, on, off) ((1 << (x)) & reg) ? on : off
+
+   printf("len=%d%s%s%s\n", ring_length,
+  BIT_STR(reg, 0, ", enabled", ", disabled"),
+  BIT_STR(reg, 10, ", semaphore wait ", ""),
+  BIT_STR(reg, 11, ", rb wait ", "")
+   );
+#undef BIT_STR
+   return ring_length;
+}
+
+static void
+print_acthd(unsigned int reg, unsigned int ring_length)
+{
+   if ((reg & (0x7 << 2)) < ring_length)
+   printf("at ring: 0x%08x\n", reg & (0x7 << 2));
+   else
+   printf("at batch: 0x%08x\n", reg);
+}
+
 static void
 print_instdone(uint32_t devid, unsigned int instdone, unsigned int instdone1)
 {
@@ -304,7 +329,7 @@ read_data_file(FILE *file)
int data_size = 0, count = 0, line_number = 0, matched;
char *line = NULL;
size_t line_size;
-   uint32_t offset, value;
+   uint32_t offset, value, ring_length = 0;
uint32_t gtt_offset = 0, new_gtt_offset;
char *ring_name = NULL;
int is_batch = 1;
@@ -391,14 +416,20 @@ read_data_file(FILE *file)
decode_ctx = 
drm_intel_decode_context_alloc(devid);
}
 
+   matched = sscanf(line, "  CTL: 0x%08x\n", ®);
+   if (matched == 1)
+   ring_length = print_ctl(reg);
+
matched = sscanf(line, "  HEAD: 0x%08x\n", ®);
if (matched == 1) {
head[head_ndx++] = print_head(reg);
}
 
matched = sscanf(line, "  ACTHD: 0x%08x\n", ®);
-   if (matched == 1)
+   if (matched == 1) {
+   print_acthd(reg, ring_length);
drm_intel_decode_set_head_tail(decode_ctx, reg, 
0x);
+   }
 
matched = sscanf(line, "  PGTBL_ER: 0x%08x\n", ®);
if (matched == 1 && reg)
-- 
1.7.9.5

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Re: [Intel-gfx] [PATCH] drm/i915: Skip pixel multiplier x-check if we fail to send the command

[Daniel Vetter]

On Thu, Jul 11, 2013 at 09:35:17PM +0100, Damien Lespiau wrote:
> On Thu, Jul 11, 2013 at 09:52:33PM +0200, Daniel Vetter wrote:
> > On Thu, Jul 11, 2013 at 07:46:00PM +0100, Damien Lespiau wrote:
> > > If intel_sdvo_get_value() fails here, val is unitialized and the cross
> > > check won't check anything.
> > > 
> > > Signed-off-by: Damien Lespiau 
> > > ---
> > >  drivers/gpu/drm/i915/intel_sdvo.c | 5 -
> > >  1 file changed, 4 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
> > > b/drivers/gpu/drm/i915/intel_sdvo.c
> > > index b8e1623..4481f6a 100644
> > > --- a/drivers/gpu/drm/i915/intel_sdvo.c
> > > +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> > > @@ -1357,7 +1357,10 @@ static void intel_sdvo_get_config(struct 
> > > intel_encoder *encoder,
> > >   }
> > >  
> > >   /* Cross check the port pixel multiplier with the sdvo encoder state. */
> > > - intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
> > > + if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
> > > +   &val, 1))
> > > + return;
> > 
> > But now it fails silently instead of being paranoid ... Can we just shut
> > up the tool instead?
> 
> We absolutely can! (and it's done).

On second thought we could shovel the switch into an if block so that val
is only read when written. Since pixel_multiplier is already set to 0 (in
case the sdvo device returns garbage) we'll correctly WARN even when
get_value fails (and per chance the stack garbage in val is the right
value for the pixel multiplier).
-Daniel
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Re: [Intel-gfx] Question about how brightness up/down to call the code of xf86-video-intel like intel_output_dpms_backlight etc

[Daniel Vetter]

On Fri, Jul 12, 2013 at 08:53:23AM +, Li, Hao H wrote:
> Hi
> 
> When we press the key like brightness up/down from keyboard, kernel will 
> receive the keyevent.
> My question is how the keyevent from kernel call the code of xf86-video-intel 
> like intel_output_dpms_backlight etc to adjust the backlight.
> Can someone help to explain more details about it?

Kernel doesn't call the brightness adjustment code. There's a bit of
bonghits in acpi where the acpi brightness keys directly adjust the acpi
backlight, but that's just not yet been fixed.

What's supposed to happen is that userspace listens to this key event and
reacts appropriately, e.g. by adjusting the brightness but also by drawing
a nice brightness scale on the screen

Cheers, Daniel
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Re: [Intel-gfx] [PATCH] drm/i915: remove preliminary_hw_support variable

[Daniel Vetter]

On Thu, Jul 11, 2013 at 03:44:03PM -0700, Jesse Barnes wrote:
> It's currently unused upstream, and just gets in the way internally.  If
> things are really hosed for some reason on a given platform, users can
> still pass a bogus param to i915 to disable it (e.g. for installers with
> half baked hw support).  But really, if that happens in practice, we've
> failed pretty hard to get things out and tested on time...

And we did fail pretty hard. Both haswell and baytrail have been enabled,
but with only half of all outputs even working and other serious issues.

Until we've demonstrated that we can do better I'd like to keep this.
-Daniel

> 
> Signed-off-by: Jesse Barnes 
> ---
>  drivers/gpu/drm/i915/i915_drv.c |5 -
>  drivers/gpu/drm/i915/i915_drv.h |1 -
>  2 files changed, 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0485f43..53eac49 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -118,11 +118,6 @@ module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, 
> int, 0600);
>  MODULE_PARM_DESC(i915_enable_ppgtt,
>   "Enable PPGTT (default: true)");
>  
> -unsigned int i915_preliminary_hw_support __read_mostly = 0;
> -module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 
> 0600);
> -MODULE_PARM_DESC(preliminary_hw_support,
> - "Enable preliminary hardware support. (default: false)");
> -
>  int i915_disable_power_well __read_mostly = 0;
>  module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
>  MODULE_PARM_DESC(disable_power_well,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 846500a..c1e268f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1580,7 +1580,6 @@ extern int i915_enable_rc6 __read_mostly;
>  extern int i915_enable_fbc __read_mostly;
>  extern bool i915_enable_hangcheck __read_mostly;
>  extern int i915_enable_ppgtt __read_mostly;
> -extern unsigned int i915_preliminary_hw_support __read_mostly;
>  extern int i915_disable_power_well __read_mostly;
>  extern int i915_enable_ips __read_mostly;
>  extern bool i915_fastboot __read_mostly;
> -- 
> 1.7.9.5
> 
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[Intel-gfx] Question about how brightness up/down to call the code of xf86-video-intel like intel_output_dpms_backlight etc

[Li, Hao H]

Hi

When we press the key like brightness up/down from keyboard, kernel will 
receive the keyevent.
My question is how the keyevent from kernel call the code of xf86-video-intel 
like intel_output_dpms_backlight etc to adjust the backlight.
Can someone help to explain more details about it?


Thanks!

Li Hao
Best Regards
Email:hao.h...@intel.com

Tizen Enabling Team
Software and Service Group
Intel Asia-Pacific Research & Development Ltd.
Tel: 86-21-61167039

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Re: [Intel-gfx] [PATCH] drm/i915: Decrease pll->refcount when freeze gpu

[Zhang, Xiong Y]

Hi Jesse:
  I supply this patch because I encounter the S3 and S4 problem on Haswell 
connecting VGA or HDMI screen.
  Currently nobody call intel_ddi_put_crtc_pll() to decrease pll_refcount and 
clear ddi_pll_sel when enter sleep states.
  So when resume from sleep states, pll_refcount is larger than zero. mode 
setting function will call intel_ddi_pll_mode_set().
  Intel_ddi_pll_mode_set call intel_ddi_put_crtc_pll() first, then set pll and 
increase pll-refcount. The results are:
  1. S3 resume have call trace in intel_ddi_put_crtc_pll()
If connecting vga, the call trace is "WARN_ON(!SPLL_PLL_ENABLE)"
If connecting HDMI, the call trace is "WARN_ON(!WRPLL_PLL_ENABLE)"
  2. S4 resume fail in intel_ddi_pll_mode_set()
If connecting VGA, intel_ddi_pll_mode_set () return false and mode setting 
exit without setting mode, vga is black
If connecting HDMI, before enter S4, HDMI use WRPLL1.After resume from S4, 
HDMI use WRPLL2.  The status is different during S4

 Actually, the above problem is a regression caused by your commit:
   commit 24576d23976746cb52e7700c4cadbf4bc1bc3472
   Author: Jesse Barnes 
   Date:   Tue Mar 26 09:25:45 2013 -0700
 drm/i915: enable VT switchless resume v3
  
In your patch, you delete intel_modeset_disable() from i915_drm_freeze(), 
intel_modeset_disable() will call dev_priv->display.off(crtc) to 
decrease pll_refcount and disable PLL.

My question is whether PLL can be disabled when enable VT switchless ?

Thanks

-Original Message-
From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of 
Daniel Vetter
Sent: Friday, July 12, 2013 1:32 AM
To: Jesse Barnes
Cc: Zhang, Xiong Y; intel-gfx
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Decrease pll->refcount when freeze 
gpu

On Thu, Jul 11, 2013 at 6:53 PM, Jesse Barnes  wrote:
> On Thu, 11 Jul 2013 16:02:27 +0800
> Xiong Zhang  wrote:
>
>> display.crtc_mode_set will increase pll->refcount, but no one will 
>> decrease pll->refcount when freeze gpu. So when gpu resume from 
>> freeze,
>> pll->refcount is still larger than zero. This is abnormal
>>
>> Without this patch, connecting vga screen on Haswell platform, there 
>> are following results:
>> 1. when resume S3, call trace exist in intel_ddi_put_crtc_pll() 2. 
>> when resume s4, vga monitor is black. because intel_ddi_pll_mode_set()
>>return false and haswell_crtc_mode_set() exit without setting mode
>>
>> With this patch, I don't find S3 and S4 regression on SandyBridge and 
>> IvyBridge platform connecting VGA, HDMI and DP screen.
>>
>> Signed-off-by: Xiong Zhang 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c |4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c index 0485f43..0065735 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -575,8 +575,10 @@ static int i915_drm_freeze(struct drm_device *dev)
>>* Disable CRTCs directly since we want to preserve sw state
>>* for _thaw.
>>*/
>> - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
>> + list_for_each_entry(crtc, &dev->mode_config.crtc_list, 
>> + head) {
>>   dev_priv->display.crtc_disable(crtc);
>> + dev_priv->display.off(crtc);
>> + }
>>
>>   intel_modeset_suspend_hw(dev);
>>   }
>
> The comment above this call indicates we'll trash the sw state if we 
> call ->off directly.  Does suspend/resume still work both with and 
> without X with this patch applied?  If we trash the sw state, the VT 
> switchless resume shouldn't work...

Even without that little issue: ddi refcounting issue need to be fixed in the 
haswell platform code, not by papering over in the core modeset infrastructure. 
We have refcounted pch plls on snb/ivb, and it works.
So imo there's no issue with the core code in the driver.
-Daniel
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