Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: provide interface for audio driver to query cdclk
At Fri, 4 Jul 2014 10:00:37 +0800,
mengdong@intel.com wrote:
From: Jani Nikula jani.nik...@intel.com
For Haswell and Broadwell, if the display power well has been disabled,
the display audio controller divider values EM4 M VALUE and EM5 N VALUE
will have been lost. The CDCLK frequency is required for reprogramming them
to generate 24MHz HD-A link BCLK. So provide a private interface for the
audio driver to query CDCLK.
This is a stopgap solution until a more generic interface between audio
and display drivers has been implemented.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Mengdong Lin mengdong@intel.com
Thanks, applied (with Cc to stable).
Takashi
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a90fdbd..21170e5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6256,6 +6256,27 @@ int i915_release_power_well(void)
}
EXPORT_SYMBOL_GPL(i915_release_power_well);
+/*
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+{
+ struct drm_i915_private *dev_priv;
+
+ if (!hsw_pwr)
+ return -ENODEV;
+
+ dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+ power_domains);
+
+ return intel_ddi_get_cdclk_freq(dev_priv);
+}
+EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
+
+
#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
#define HSW_ALWAYS_ON_POWER_DOMAINS (\
diff --git a/include/drm/i915_powerwell.h b/include/drm/i915_powerwell.h
index 2baba99..baa6f11 100644
--- a/include/drm/i915_powerwell.h
+++ b/include/drm/i915_powerwell.h
@@ -32,5 +32,6 @@
/* For use by hda_i915 driver */
extern int i915_request_power_well(void);
extern int i915_release_power_well(void);
+extern int i915_get_cdclk_freq(void);
#endif /* _I915_POWERWELL_H_ */
--
1.8.1.2
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Re: [Intel-gfx] [PATCH 08/16] drm/i915/error: Do a better job of disambiguating VMAs
On Tue, Jul 01, 2014 at 11:17:43AM -0700, Ben Widawsky wrote:
Some of the original PPGTT patches in this area where unmerged, and this
left a lot of confusion in our error capture with regard to which vm/obj
we want to capture. There have been at least a couple of patches from
Chris, and myself to try to fix this up; so here is another shot. Nobody
running without full PPGTT is effected by this, and that is probably why
nobody has bothered to fix it yet.
Instead of using any of the global lists to find the VMAs we want to
capture, we use the union of the active, and the inactive list in the
VM. This allows us to replace our capture_bo with capture_vma, and know
all the VMAs we want to capture are valid.
I could have probably figured out a way to reuse mm_list. As we've had
bugs here before in the shrinker, I think the best way forward is to get
it working, and then optimize it later.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 39
++-
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a4153ee..88451dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2114,6 +2114,7 @@ static struct i915_vma *__i915_gem_vma_create(struct
drm_i915_gem_object *obj,
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(vma-vma_link);
+ INIT_LIST_HEAD(vma-pin_capture_link);
INIT_LIST_HEAD(vma-mm_list);
INIT_LIST_HEAD(vma-exec_list);
vma-vm = vm;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8d6f7c1..1d75801 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -126,6 +126,8 @@ struct i915_vma {
struct list_head vma_link; /* Link in the object's VMA list */
+ struct list_head pin_capture_link; /* Link in the error capture */
+
/** This vma's place in the batchbuffer or on the eviction list */
struct list_head exec_list;
We already have a slot for temporary lists...
-Chris
--
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Re: [Intel-gfx] [PATCH 16/16] drm/i915: Get the error state over the wire (HACKish)
On Tue, Jul 01, 2014 at 11:17:51AM -0700, Ben Widawsky wrote: I was dealing with a bug recently where the system would hard hang somewhere between hangcheck and reset. There was time after error collection to actually get my error state out, but I couldn't get the reads to work. This patch is also useful for when reset kills the machine, and you want to keep reset enabled but still get error state. Since I found the patch pretty useful, I decided to clean it up and submit it. It was mostly meant as a one-off hack originally though. If a maintainer decides it's useful, then here it is. I think we could certainly push the register dump into DRM_DEBUG. That's usually enough to identify duplicates and so may be useful from the dev perspective. Or throw in a QA parameter that dumps an interesting subset to KERN_ERR. Most people seem to manage to include the dmesg so getting the right information into it would reduce some of the annoyance in vague bug reports. (Too much of the wrong information though is equally annoying.) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/opregion: ignore firmware requests for backlight change
On Fri, 2014-06-27 at 11:20 +0800, Aaron Lu wrote:
On 06/25/2014 07:08 PM, Jani Nikula wrote:
On Tue, 24 Jun 2014, Aaron Lu aaron...@intel.com wrote:
Some Thinkpad laptops' firmware will initiate a backlight level change
request through operation region on the events of AC plug/unplug, but
since we are not using firmware's interface to do the backlight setting
on these affected laptops, we do not want the firmware to use some
arbitrary value from its ASL variable to set the backlight level on
AC plug/unplug either.
I'm curious whether this happens with EFI boot, or only with legacy.
Igor, Anton,
Hi,
Are you using legacy boot or UEFI boot?
I'm using UEFI.
Possible to test the other case?
yes, I'll test it with legacy in 10 mins.
One comment inline, otherwise
Will add that in next revision.
Acked-by: Jani Nikula jani.nik...@intel.com
Thanks for the review!
-Aaron
for merging through the ACPI tree, as the change is more likely to
conflict there.
Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=76491
Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=77091
Reported-and-tested-by: Igor Gnatenko i.gnatenko.br...@gmail.com
Reported-and-tested-by: Anton Gubarkov anton.gubar...@gmail.com
Signed-off-by: Aaron Lu aaron...@intel.com
---
drivers/acpi/video.c | 3 ++-
drivers/gpu/drm/i915/intel_opregion.c | 7 +++
include/acpi/video.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
index fb9ffe9adc64..cf99d6d2d491 100644
--- a/drivers/acpi/video.c
+++ b/drivers/acpi/video.c
@@ -241,13 +241,14 @@ static bool acpi_video_use_native_backlight(void)
return use_native_backlight_dmi;
}
-static bool acpi_video_verify_backlight_support(void)
+bool acpi_video_verify_backlight_support(void)
{
if (acpi_osi_is_win8() acpi_video_use_native_backlight()
backlight_device_registered(BACKLIGHT_RAW))
return false;
return acpi_video_backlight_support();
}
+EXPORT_SYMBOL(acpi_video_verify_backlight_support);
/* backlight device sysfs support */
static int acpi_video_get_brightness(struct backlight_device *bd)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 2e2c71fcc9ed..02943d93e88e 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -403,6 +403,13 @@ static u32 asle_set_backlight(struct drm_device *dev,
u32 bclp)
DRM_DEBUG_DRIVER(bclp = 0x%08x\n, bclp);
+ /*
+ * If the acpi_video interface is not supposed to be used, don't
+ * bother processing backlight level change requests from firmware.
+ */
+ if (!acpi_video_verify_backlight_support())
+ return 0;
I'd appreciate a DRM_DEBUG_KMS here about what happened. We're bound to
wonder about that staring at some dmesg later on!
+
if (!(bclp ASLE_BCLP_VALID))
return ASLC_BACKLIGHT_FAILED;
diff --git a/include/acpi/video.h b/include/acpi/video.h
index ea4c7bbded4d..92f8c4bffefb 100644
--- a/include/acpi/video.h
+++ b/include/acpi/video.h
@@ -22,6 +22,7 @@ extern void acpi_video_unregister(void);
extern void acpi_video_unregister_backlight(void);
extern int acpi_video_get_edid(struct acpi_device *device, int type,
int device_id, void **edid);
+extern bool acpi_video_verify_backlight_support(void);
#else
static inline int acpi_video_register(void) { return 0; }
static inline void acpi_video_unregister(void) { return; }
@@ -31,6 +32,7 @@ static inline int acpi_video_get_edid(struct acpi_device
*device, int type,
{
return -ENODEV;
}
+static bool acpi_video_verify_backlight_support() { return false; }
#endif
#endif
--
1.9.3
--
-Igor Gnatenko
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Re: [Intel-gfx] [PATCH 05/16] drm/i915/ctx: Return earlier on failure
On Tue, Jul 01, 2014 at 11:17:40AM -0700, Ben Widawsky wrote: As what was correctly debugged here: commit acc240d41ea1ab9c488a79219fb313b5b46265ae Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Thu Dec 5 15:42:34 2013 +0100 drm/i915: Fix use-after-free in do_switch It then becomes apparent that the default context cannot be the context being switched to for context switch because it is always bound. It follows that if the ring-last_context (from) has changed after the bind_to_gtt, it will always be the default context - this is commented in the code block. This assertion will help catch issues without our logic sooner than letting the system move long (which is possible for some time). I really want this to be a BUG(), but I also want the patch to get merged. I think the fact that none of the ERRNOs make any sense at all is just more evidence that this shouldn't be a WARN. Hmm, we could adopt EREMOTEIO or for driver bugs. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/opregion: ignore firmware requests for backlight change
I've tested legacy boot. I have this bug.
On Fri, Jun 27, 2014 at 7:20 AM, Aaron Lu aaron...@intel.com wrote:
On 06/25/2014 07:08 PM, Jani Nikula wrote:
On Tue, 24 Jun 2014, Aaron Lu aaron...@intel.com wrote:
Some Thinkpad laptops' firmware will initiate a backlight level change
request through operation region on the events of AC plug/unplug, but
since we are not using firmware's interface to do the backlight setting
on these affected laptops, we do not want the firmware to use some
arbitrary value from its ASL variable to set the backlight level on
AC plug/unplug either.
I'm curious whether this happens with EFI boot, or only with legacy.
Igor, Anton,
Are you using legacy boot or UEFI boot?
Possible to test the other case?
One comment inline, otherwise
Will add that in next revision.
Acked-by: Jani Nikula jani.nik...@intel.com
Thanks for the review!
-Aaron
for merging through the ACPI tree, as the change is more likely to
conflict there.
Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=76491
Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=77091
Reported-and-tested-by: Igor Gnatenko i.gnatenko.br...@gmail.com
Reported-and-tested-by: Anton Gubarkov anton.gubar...@gmail.com
Signed-off-by: Aaron Lu aaron...@intel.com
---
drivers/acpi/video.c | 3 ++-
drivers/gpu/drm/i915/intel_opregion.c | 7 +++
include/acpi/video.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
index fb9ffe9adc64..cf99d6d2d491 100644
--- a/drivers/acpi/video.c
+++ b/drivers/acpi/video.c
@@ -241,13 +241,14 @@ static bool acpi_video_use_native_backlight(void)
return use_native_backlight_dmi;
}
-static bool acpi_video_verify_backlight_support(void)
+bool acpi_video_verify_backlight_support(void)
{
if (acpi_osi_is_win8() acpi_video_use_native_backlight()
backlight_device_registered(BACKLIGHT_RAW))
return false;
return acpi_video_backlight_support();
}
+EXPORT_SYMBOL(acpi_video_verify_backlight_support);
/* backlight device sysfs support */
static int acpi_video_get_brightness(struct backlight_device *bd)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 2e2c71fcc9ed..02943d93e88e 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -403,6 +403,13 @@ static u32 asle_set_backlight(struct drm_device *dev,
u32 bclp)
DRM_DEBUG_DRIVER(bclp = 0x%08x\n, bclp);
+/*
+ * If the acpi_video interface is not supposed to be used, don't
+ * bother processing backlight level change requests from firmware.
+ */
+if (!acpi_video_verify_backlight_support())
+return 0;
I'd appreciate a DRM_DEBUG_KMS here about what happened. We're bound to
wonder about that staring at some dmesg later on!
+
if (!(bclp ASLE_BCLP_VALID))
return ASLC_BACKLIGHT_FAILED;
diff --git a/include/acpi/video.h b/include/acpi/video.h
index ea4c7bbded4d..92f8c4bffefb 100644
--- a/include/acpi/video.h
+++ b/include/acpi/video.h
@@ -22,6 +22,7 @@ extern void acpi_video_unregister(void);
extern void acpi_video_unregister_backlight(void);
extern int acpi_video_get_edid(struct acpi_device *device, int type,
int device_id, void **edid);
+extern bool acpi_video_verify_backlight_support(void);
#else
static inline int acpi_video_register(void) { return 0; }
static inline void acpi_video_unregister(void) { return; }
@@ -31,6 +32,7 @@ static inline int acpi_video_get_edid(struct acpi_device
*device, int type,
{
return -ENODEV;
}
+static bool acpi_video_verify_backlight_support() { return false; }
#endif
#endif
--
1.9.3
--
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Re: [Intel-gfx] [PATCH] drm/i915: Show cursor size in debugfs/i915_display_info
On Fri, Jul 04, 2014 at 08:20:11AM +0100, Chris Wilson wrote:
Inlcude the pipe-size and cursor-size in debugfs.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
--
Damien
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0869df682f63..6d3f925ae9a2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2434,17 +2434,17 @@ static int i915_display_info(struct seq_file *m, void
*unused)
bool active;
int x, y;
- seq_printf(m, CRTC %d: pipe: %c, active: %s\n,
+ seq_printf(m, CRTC %d: pipe: %c, active=%s (size=%dx%d)\n,
crtc-base.base.id, pipe_name(crtc-pipe),
-yesno(crtc-active));
+yesno(crtc-active), crtc-config.pipe_src_w,
crtc-config.pipe_src_h);
if (crtc-active) {
intel_crtc_info(m, crtc);
active = cursor_position(dev, crtc-pipe, x, y);
- seq_printf(m, \tcursor visible? %s, position (%d, %d),
addr 0x%08x, active? %s\n,
+ seq_printf(m, \tcursor visible? %s, position (%d, %d),
size %dx%d, addr 0x%08x, active? %s\n,
yesno(crtc-cursor_base),
-x, y, crtc-cursor_addr,
-yesno(active));
+x, y, crtc-cursor_width,
crtc-cursor_height,
+crtc-cursor_addr, yesno(active));
}
seq_printf(m, \tunderrun reporting: cpu=%s pch=%s \n,
--
2.0.1
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[Intel-gfx] [v2 01/11] drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h
From: Ville Syrjälä ville.syrjala at linux.intel.com
The rotation property stuff should be standardized among all drivers.
Move the bits to drm_crtc.h from omap_drv.h.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/omapdrm/omap_drv.h |7 ---
include/drm/drm_crtc.h |8
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h
b/drivers/gpu/drm/omapdrm/omap_drv.h
index 284b80f..b08a450 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -119,13 +119,6 @@ struct omap_drm_private {
struct omap_drm_irq error_handler;
};
-/* this should probably be in drm-core to standardize amongst drivers */
-#define DRM_ROTATE_0 0
-#define DRM_ROTATE_90 1
-#define DRM_ROTATE_180 2
-#define DRM_ROTATE_270 3
-#define DRM_REFLECT_X 4
-#define DRM_REFLECT_Y 5
#ifdef CONFIG_DEBUG_FS
int omap_debugfs_init(struct drm_minor *minor);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 4ee7e26..bfc7235 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -75,6 +75,14 @@ static inline uint64_t I642U64(int64_t val)
return (uint64_t)*((uint64_t *)val);
}
+/* rotation property bits */
+#define DRM_ROTATE_0 0
+#define DRM_ROTATE_90 1
+#define DRM_ROTATE_180 2
+#define DRM_ROTATE_270 3
+#define DRM_REFLECT_X 4
+#define DRM_REFLECT_Y 5
+
enum drm_connector_force {
DRM_FORCE_UNSPECIFIED,
DRM_FORCE_OFF,
--
1.7.10.4
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[Intel-gfx] [v2 00/11] Support for 180 degree HW rotation
From: Sonika Jindal sonika.jin...@intel.com Enables 180 degree rotation for sprite and primary planes. Updated the primary plane rotation support as per the new universal plane design. Most of these patches were already reviewed in intel-gfx in February 2014 thats why there is version history in few of them. v2: Moved rotation_property to drm_plane. Added updation of FBC when rotation is again set to 0. Testcase: kms_rotation_crc This igt can be extended for clipped rotation cases. Right it only tests 180 degree rotation for sprite and primary plane with crc check. Sonika Jindal (2): drm/i915: Add 180 degree primary plane rotation support drm: Resetting rotation property Ville Syrjälä (9): drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h drm: Add support_bits parameter to drm_property_create_bitmask() drm: Add drm_mode_create_rotation_property() drm/omap: Switch omapdrm over to drm_mode_create_rotation_property() drm: Add drm_rect rotation functions drm: Add drm_rotation_simplify() drm/i915: Add 180 degree sprite rotation support drm/i915: Make intel_plane_restore() return an error drm/i915: Add rotation property for sprites drivers/gpu/drm/drm_crtc.c | 65 +++- drivers/gpu/drm/drm_fb_helper.c | 16 +++- drivers/gpu/drm/drm_rect.c | 140 ++ drivers/gpu/drm/i915/i915_reg.h |4 + drivers/gpu/drm/i915/intel_display.c | 102 +++-- drivers/gpu/drm/i915/intel_drv.h |3 +- drivers/gpu/drm/i915/intel_pm.c |7 ++ drivers/gpu/drm/i915/intel_sprite.c | 91 -- drivers/gpu/drm/omapdrm/omap_drv.h |7 -- drivers/gpu/drm/omapdrm/omap_plane.c | 17 ++--- include/drm/drm_crtc.h | 16 +++- include/drm/drm_rect.h |6 ++ 12 files changed, 437 insertions(+), 37 deletions(-) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 03/11] drm: Add drm_mode_create_rotation_property()
From: Ville Syrjälä ville.syrjala at linux.intel.com
Add a function to create a standards compliant rotation property.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/drm_crtc.c | 18 ++
include/drm/drm_crtc.h |2 ++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 2fbee61..f224d4d 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -4959,3 +4959,21 @@ void drm_mode_config_cleanup(struct drm_device *dev)
drm_modeset_lock_fini(dev-mode_config.connection_mutex);
}
EXPORT_SYMBOL(drm_mode_config_cleanup);
+
+struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
+ unsigned int
supported_rotations)
+{
+ static const struct drm_prop_enum_list props[] = {
+ { DRM_ROTATE_0, rotate-0 },
+ { DRM_ROTATE_90, rotate-90 },
+ { DRM_ROTATE_180, rotate-180 },
+ { DRM_ROTATE_270, rotate-270 },
+ { DRM_REFLECT_X, reflect-x },
+ { DRM_REFLECT_Y, reflect-y },
+ };
+
+ return drm_property_create_bitmask(dev, 0, rotation,
+ props, ARRAY_SIZE(props),
+ supported_rotations);
+}
+EXPORT_SYMBOL(drm_mode_create_rotation_property);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index cb4850a..f7b383b 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1113,6 +1113,8 @@ extern int drm_format_plane_cpp(uint32_t format, int
plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
extern const char *drm_get_format_name(uint32_t format);
+extern struct drm_property *drm_mode_create_rotation_property(struct
drm_device *dev,
+ unsigned int
supported_rotations);
/* Helpers */
--
1.7.10.4
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[Intel-gfx] [v2 02/11] drm: Add support_bits parameter to drm_property_create_bitmask()
From: Ville Syrjälä ville.syrjala at linux.intel.com
Make drm_property_create_bitmask() a bit more generic by allowing the
caller to specify which bits are in fact supported. This allows multiple
callers to use the same enum list, but still create different versions
of the same property with different list of supported bits.
v2: Populate values[] array as non-sparse
Make supported_bits 64bit
Fix up omapdrm call site (Rob)
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
Reviewed-by: Sagar Kamble sagar.a.kam...@intel.com
---
drivers/gpu/drm/drm_crtc.c | 17 +
drivers/gpu/drm/omapdrm/omap_plane.c |5 -
include/drm/drm_crtc.h |3 ++-
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 41c7212..2fbee61 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3395,19 +3395,28 @@ EXPORT_SYMBOL(drm_property_create_enum);
struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
int flags, const char *name,
const struct drm_prop_enum_list *props,
-int num_values)
+int num_props,
+uint64_t supported_bits)
{
struct drm_property *property;
- int i, ret;
+ int i, ret, index = 0;
+ int num_values = hweight64(supported_bits);
flags |= DRM_MODE_PROP_BITMASK;
property = drm_property_create(dev, flags, name, num_values);
if (!property)
return NULL;
+ for (i = 0; i num_props; i++) {
+ if (!(supported_bits (1ULL props[i].type)))
+ continue;
- for (i = 0; i num_values; i++) {
- ret = drm_property_add_enum(property, i,
+ if (WARN_ON(index = num_values)) {
+ drm_property_destroy(dev, property);
+ return NULL;
+ }
+
+ ret = drm_property_add_enum(property, index++,
props[i].type,
props[i].name);
if (ret) {
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c
b/drivers/gpu/drm/omapdrm/omap_plane.c
index 3cf31ee..aff06e7 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -317,7 +317,10 @@ void omap_plane_install_properties(struct drm_plane *plane,
{ DRM_REFLECT_Y, reflect-y },
};
prop = drm_property_create_bitmask(dev, 0, rotation,
- props, ARRAY_SIZE(props));
+ props, ARRAY_SIZE(props),
+ BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) |
+ BIT(DRM_ROTATE_180) |
BIT(DRM_ROTATE_270) |
+ BIT(DRM_REFLECT_X) |
BIT(DRM_REFLECT_Y));
if (prop == NULL)
return;
priv-rotation_prop = prop;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index bfc7235..cb4850a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1006,7 +1006,8 @@ extern struct drm_property
*drm_property_create_enum(struct drm_device *dev, int
struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
int flags, const char *name,
const struct drm_prop_enum_list *props,
-int num_values);
+int num_props,
+uint64_t supported_bits);
struct drm_property *drm_property_create_range(struct drm_device *dev, int
flags,
const char *name,
uint64_t min, uint64_t max);
--
1.7.10.4
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[Intel-gfx] [v2 04/11] drm/omap: Switch omapdrm over to drm_mode_create_rotation_property()
From: Ville Syrjälä ville.syrjala at linux.intel.com
Use the new drm_mode_create_rotation_property() in omapdrm.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Rob Clark robdcl...@gmail.com
Reviewed-by: Imre Deak imre.d...@intel.com
Reviewed-by: Sagar Kamble sagar.a.kam...@intel.com
---
drivers/gpu/drm/omapdrm/omap_plane.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c
b/drivers/gpu/drm/omapdrm/omap_plane.c
index aff06e7..da9d15d 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -308,19 +308,13 @@ void omap_plane_install_properties(struct drm_plane
*plane,
if (priv-has_dmm) {
prop = priv-rotation_prop;
if (!prop) {
- const struct drm_prop_enum_list props[] = {
- { DRM_ROTATE_0, rotate-0 },
- { DRM_ROTATE_90, rotate-90 },
- { DRM_ROTATE_180, rotate-180 },
- { DRM_ROTATE_270, rotate-270 },
- { DRM_REFLECT_X, reflect-x },
- { DRM_REFLECT_Y, reflect-y },
- };
- prop = drm_property_create_bitmask(dev, 0, rotation,
- props, ARRAY_SIZE(props),
- BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) |
- BIT(DRM_ROTATE_180) |
BIT(DRM_ROTATE_270) |
- BIT(DRM_REFLECT_X) |
BIT(DRM_REFLECT_Y));
+ prop = drm_mode_create_rotation_property(dev,
+
BIT(DRM_ROTATE_0) |
+
BIT(DRM_ROTATE_90) |
+
BIT(DRM_ROTATE_180) |
+
BIT(DRM_ROTATE_270) |
+
BIT(DRM_REFLECT_X) |
+
BIT(DRM_REFLECT_Y));
if (prop == NULL)
return;
priv-rotation_prop = prop;
--
1.7.10.4
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[Intel-gfx] [v2 06/11] drm: Add drm_rotation_simplify()
From: Ville Syrjälä ville.syrjala at linux.intel.com
drm_rotation_simplify() can be used to eliminate unsupported rotation
flags. It will check if any unsupported flags are present, and if so
it will modify the rotation to an alternate form by adding 180 degrees
to rotation angle, and flipping the reflect x and y bits. The hope is
that this identity transform will eliminate the unsupported flags.
Of course that might not result in any more supported rotation, so
the caller is still responsible for checking the result afterwards.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/drm_crtc.c | 30 ++
include/drm/drm_crtc.h |2 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index f224d4d..89bab66 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -4842,6 +4842,36 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
/**
+ * drm_rotation_simplify() - Try to simplify the rotation
+ * @rotation: Rotation to be simplified
+ * @supported_rotations: Supported rotations
+ *
+ * Attempt to simplify the rotation to a form that is supported.
+ * Eg. if the hardware supports everything except DRM_REFLECT_X
+ * one could call this function like this:
+ *
+ * drm_rotation_simplify(rotation, BIT(DRM_ROTATE_0) |
+ * BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_180) |
+ * BIT(DRM_ROTATE_270) | BIT(DRM_REFLECT_Y));
+ *
+ * to eliminate the DRM_ROTATE_X flag. Depending on what kind of
+ * transforms the hardware supports, this function may not
+ * be able to produce a supported transform, so the caller should
+ * check the result afterwards.
+ */
+unsigned int drm_rotation_simplify(unsigned int rotation,
+ unsigned int supported_rotations)
+{
+ if (rotation ~supported_rotations) {
+ rotation ^= BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y);
+ rotation = (rotation ~0xf) | BIT((ffs(rotation 0xf) + 1) %
4);
+ }
+
+ return rotation;
+}
+EXPORT_SYMBOL(drm_rotation_simplify);
+
+/**
* drm_mode_config_init - initialize DRM mode_configuration structure
* @dev: DRM device
*
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index f7b383b..08ed55e 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1115,6 +1115,8 @@ extern int drm_format_vert_chroma_subsampling(uint32_t
format);
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct
drm_device *dev,
unsigned int
supported_rotations);
+extern unsigned int drm_rotation_simplify(unsigned int rotation,
+ unsigned int supported_rotations);
/* Helpers */
--
1.7.10.4
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[Intel-gfx] [v2 05/11] drm: Add drm_rect rotation functions
From: Ville Syrjälä ville.syrjala at linux.intel.com
Add some helper functions to move drm_rects between different rotated
coordinate spaces. One function does the forward transform and
another does the inverse.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/drm_rect.c | 140
include/drm/drm_rect.h |6 ++
2 files changed, 146 insertions(+)
diff --git a/drivers/gpu/drm/drm_rect.c b/drivers/gpu/drm/drm_rect.c
index 7047ca0..631f5af 100644
--- a/drivers/gpu/drm/drm_rect.c
+++ b/drivers/gpu/drm/drm_rect.c
@@ -293,3 +293,143 @@ void drm_rect_debug_print(const struct drm_rect *r, bool
fixed_point)
DRM_DEBUG_KMS(%dx%d%+d%+d\n, w, h, r-x1, r-y1);
}
EXPORT_SYMBOL(drm_rect_debug_print);
+
+/**
+ * drm_rect_rotate - Rotate the rectangle
+ * @r: rectangle to be rotated
+ * @width: Width of the coordinate space
+ * @height: Height of the coordinate space
+ * @rotation: Transformation to be applied
+ *
+ * Apply @rotation to the coordinates of rectangle @r.
+ *
+ * @width and @height combined with @rotation define
+ * the location of the new origin.
+ *
+ * @width correcsponds to the horizontal and @height
+ * to the vertical axis of the untransformed coordinate
+ * space.
+ */
+void drm_rect_rotate(struct drm_rect *r,
+int width, int height,
+unsigned int rotation)
+{
+ struct drm_rect tmp;
+
+ if (rotation (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
+ tmp = *r;
+
+ if (rotation BIT(DRM_REFLECT_X)) {
+ r-x1 = width - tmp.x2;
+ r-x2 = width - tmp.x1;
+ }
+
+ if (rotation BIT(DRM_REFLECT_Y)) {
+ r-y1 = height - tmp.y2;
+ r-y2 = height - tmp.y1;
+ }
+ }
+
+ switch (rotation 0xf) {
+ case BIT(DRM_ROTATE_0):
+ break;
+ case BIT(DRM_ROTATE_90):
+ tmp = *r;
+ r-x1 = tmp.y1;
+ r-x2 = tmp.y2;
+ r-y1 = width - tmp.x2;
+ r-y2 = width - tmp.x1;
+ break;
+ case BIT(DRM_ROTATE_180):
+ tmp = *r;
+ r-x1 = width - tmp.x2;
+ r-x2 = width - tmp.x1;
+ r-y1 = height - tmp.y2;
+ r-y2 = height - tmp.y1;
+ break;
+ case BIT(DRM_ROTATE_270):
+ tmp = *r;
+ r-x1 = height - tmp.y2;
+ r-x2 = height - tmp.y1;
+ r-y1 = tmp.x1;
+ r-y2 = tmp.x2;
+ break;
+ default:
+ break;
+ }
+}
+EXPORT_SYMBOL(drm_rect_rotate);
+
+/**
+ * drm_rect_rotate_inv - Inverse rotate the rectangle
+ * @r: rectangle to be rotated
+ * @width: Width of the coordinate space
+ * @height: Height of the coordinate space
+ * @rotation: Transformation whose inverse is to be applied
+ *
+ * Apply the inverse of @rotation to the coordinates
+ * of rectangle @r.
+ *
+ * @width and @height combined with @rotation define
+ * the location of the new origin.
+ *
+ * @width correcsponds to the horizontal and @height
+ * to the vertical axis of the original untransformed
+ * coordinate space, so that you never have to flip
+ * them when doing a rotatation and its inverse.
+ * That is, if you do:
+ *
+ * drm_rotate(r, width, height, rotation);
+ * drm_rotate_inv(r, width, height, rotation);
+ *
+ * you will always get back the original rectangle.
+ */
+void drm_rect_rotate_inv(struct drm_rect *r,
+int width, int height,
+unsigned int rotation)
+{
+ struct drm_rect tmp;
+
+ switch (rotation 0xf) {
+ case BIT(DRM_ROTATE_0):
+ break;
+ case BIT(DRM_ROTATE_90):
+ tmp = *r;
+ r-x1 = width - tmp.y2;
+ r-x2 = width - tmp.y1;
+ r-y1 = tmp.x1;
+ r-y2 = tmp.x2;
+ break;
+ case BIT(DRM_ROTATE_180):
+ tmp = *r;
+ r-x1 = width - tmp.x2;
+ r-x2 = width - tmp.x1;
+ r-y1 = height - tmp.y2;
+ r-y2 = height - tmp.y1;
+ break;
+ case BIT(DRM_ROTATE_270):
+ tmp = *r;
+ r-x1 = tmp.y1;
+ r-x2 = tmp.y2;
+ r-y1 = height - tmp.x2;
+ r-y2 = height - tmp.x1;
+ break;
+ default:
+ break;
+ }
+
+ if (rotation (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
+ tmp = *r;
+
+ if (rotation BIT(DRM_REFLECT_X)) {
+ r-x1 = width - tmp.x2;
+ r-x2 = width - tmp.x1;
+ }
+
+ if (rotation BIT(DRM_REFLECT_Y)) {
+ r-y1 =
[Intel-gfx] [v2 09/11] drm/i915: Add rotation property for sprites
From: Ville Syrjälä ville.syrjala at linux.intel.com
Sprite planes support 180 degree rotation. The lower layers are now in
place, so hook in the standard rotation property to expose the feature
to the users.
v2: Moving rotation_property to drm_plane
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_sprite.c | 40 ++-
include/drm/drm_crtc.h |1 +
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cbad738..aa63027 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1202,6 +1202,29 @@ out_unlock:
return ret;
}
+static int intel_plane_set_property(struct drm_plane *plane,
+ struct drm_property *prop,
+ uint64_t val)
+{
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ uint64_t old_val;
+ int ret = -ENOENT;
+
+ if (prop == plane-rotation_property) {
+ /* exactly one rotation angle please */
+ if (hweight32(val 0xf) != 1)
+ return -EINVAL;
+
+ old_val = intel_plane-rotation;
+ intel_plane-rotation = val;
+ ret = intel_plane_restore(plane);
+ if (ret)
+ intel_plane-rotation = old_val;
+ }
+
+ return ret;
+}
+
int intel_plane_restore(struct drm_plane *plane)
{
struct intel_plane *intel_plane = to_intel_plane(plane);
@@ -1228,6 +1251,7 @@ static const struct drm_plane_funcs intel_plane_funcs = {
.update_plane = intel_update_plane,
.disable_plane = intel_disable_plane,
.destroy = intel_destroy_plane,
+ .set_property = intel_plane_set_property,
};
static uint32_t ilk_plane_formats[] = {
@@ -1338,8 +1362,22 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane_funcs,
plane_formats, num_plane_formats,
false);
- if (ret)
+ if (ret) {
kfree(intel_plane);
+ goto out;
+ }
+
+ if (!intel_plane-base.rotation_property)
+ intel_plane-base.rotation_property =
+ drm_mode_create_rotation_property(dev,
+ BIT(DRM_ROTATE_0) |
+ BIT(DRM_ROTATE_180));
+
+ if (intel_plane-base.rotation_property)
+ drm_object_attach_property(intel_plane-base.base,
+ intel_plane-base.rotation_property,
+ intel_plane-rotation);
+ out:
return ret;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 08ed55e..6006c70 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -615,6 +615,7 @@ struct drm_plane {
const struct drm_plane_funcs *funcs;
+ struct drm_property *rotation_property;
struct drm_object_properties properties;
enum drm_plane_type type;
--
1.7.10.4
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[Intel-gfx] [v2 10/11] drm/i915: Add 180 degree primary plane rotation support
From: Sonika Jindal sonika.jin...@intel.com
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC is active before issueing update_plane. Added
wait for vblank to make sure we dont overtake page flips. Disabling
FBC since it does not work with rotated planes.
v4: Updated rotation checks for pending flips, fbc disable. Creating
rotation property only for Gen4 onwards. Property resetting as part
of lastclose.
v5: Resetting property in i915_driver_lastclose properly for planes
and crtcs. Fixed linear offset calculation that was off by 1 w.r.t
width in i9xx_update_plane and ironlake_update_plane. Removed tab
based indentation and unnecessary braces in intel_crtc_set_property
and intel_update_fbc. FBC and flip related checks should be done only
for valid crtcs.
v6: Minor nits in FBC disable checks for comments in intel_crtc_set_property
and positioning the disable code in intel_update_fbc.
v7: In case rotation property on inactive crtc is updated, we return
successfully printing debug log as crtc is inactive and only property change
is preserved.
v8: update_plane is changed to update_primary_plane, crtc-fb is changed to
crtc-primary-fb and return value of update_primary_plane is ignored.
v9: added rotation property to primary plane instead of crtc. Removing reset
of rotation property from lastclose. rotation_property is moved to drm_plane,so
drm layer will take care of resetting.
v10: adding updation of fbc when rotation is set to 0.
Testcase: igt/kms_rotation_crc
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Uma Shankar uma.shan...@intel.com
Signed-off-by: Sagar Kamble sagar.a.kam...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 102 --
drivers/gpu/drm/i915/intel_pm.c |7 +++
3 files changed, 105 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c70c804..c600d3b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4087,6 +4087,7 @@ enum punit_power_well {
#define DISPPLANE_NO_LINE_DOUBLE 0
#define DISPPLANE_STEREO_POLARITY_FIRST 0
#define DISPPLANE_STEREO_POLARITY_SECOND (118)
+#define DISPPLANE_ROTATE_180 (115)
#define DISPPLANE_TRICKLE_FEED_DISABLE (114) /* Ironlake */
#define DISPPLANE_TILED (110)
#define _DSPAADDR 0x70184
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5e8e711..7f16d6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2414,7 +2414,9 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
unsigned long linear_offset;
u32 dspcntr;
u32 reg;
+ int pixel_size;
+ pixel_size = drm_format_plane_cpp(fb-pixel_format, 0);
intel_fb = to_intel_framebuffer(fb);
obj = intel_fb-obj;
@@ -2422,6 +2424,8 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
dspcntr = I915_READ(reg);
/* Mask out pixel format bits in case we change it */
dspcntr = ~DISPPLANE_PIXFORMAT_MASK;
+ dspcntr = ~DISPPLANE_ROTATE_180;
+
switch (fb-pixel_format) {
case DRM_FORMAT_C8:
dspcntr |= DISPPLANE_8BPP;
@@ -2463,8 +2467,6 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
if (IS_G4X(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- I915_WRITE(reg, dspcntr);
-
linear_offset = y * fb-pitches[0] + x * (fb-bits_per_pixel / 8);
if (INTEL_INFO(dev)-gen = 4) {
@@ -2477,6 +2479,18 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
intel_crtc-dspaddr_offset = linear_offset;
}
+ if (to_intel_plane(crtc-primary)-rotation == BIT(DRM_ROTATE_180)) {
+ dspcntr |= DISPPLANE_ROTATE_180;
+
+ x += (intel_crtc-config.pipe_src_w - 1);
+ y += (intel_crtc-config.pipe_src_h - 1);
+ linear_offset += (intel_crtc-config.pipe_src_h - 1) *
+ fb-pitches[0] +
+ (intel_crtc-config.pipe_src_w - 1) * pixel_size;
+ }
+
+ I915_WRITE(reg, dspcntr);
+
DRM_DEBUG_KMS(Writing base %08lX %08lX %d %d %d\n,
i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
fb-pitches[0]);
@@ -2487,7 +2501,8 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(DSPTILEOFF(plane), (y 16) | x);
I915_WRITE(DSPLINOFF(plane), linear_offset);
} else
-
[Intel-gfx] [v2 11/11] drm: Resetting rotation property
From: Sonika Jindal sonika.jin...@intel.com
Reset rotation property to 0 wherever applicable
v2: Also calling set_property of the plane to set the rotation in the plane
structure.
Cc: damien.lesp...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/drm_fb_helper.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index d5d8cea..30806b4 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -282,9 +282,23 @@ static bool restore_fbdev_mode(struct drm_fb_helper
*fb_helper)
drm_warn_on_modeset_not_all_locked(dev);
- list_for_each_entry(plane, dev-mode_config.plane_list, head)
+ list_for_each_entry(plane, dev-mode_config.plane_list, head) {
+
+ if (plane-rotation_property) {
+ int ret = 0;
+ if (plane-funcs-set_property)
+ ret = plane-funcs-set_property(plane,
+ plane-rotation_property,
+ BIT(DRM_ROTATE_0));
+ if (!ret)
+ drm_object_property_set_value(plane-base,
+ plane-rotation_property,
+ BIT(DRM_ROTATE_0));
+ }
+
if (plane-type != DRM_PLANE_TYPE_PRIMARY)
drm_plane_force_disable(plane);
+ }
for (i = 0; i fb_helper-crtc_count; i++) {
struct drm_mode_set *mode_set =
fb_helper-crtc_info[i].mode_set;
--
1.7.10.4
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[Intel-gfx] [v2 08/11] drm/i915: Make intel_plane_restore() return an error
From: Ville Syrjälä ville.syrjala at linux.intel.com
Propagate the error from intel_update_plane() up through
intel_plane_restore() to the caller. This will be used for
rollback purposes when setting properties fails.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h|2 +-
drivers/gpu/drm/i915/intel_sprite.c | 14 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 67b1c59..da5a3ca 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -993,7 +993,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t
sdvo_reg, bool is_sdvob);
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane);
-void intel_plane_restore(struct drm_plane *plane);
+int intel_plane_restore(struct drm_plane *plane);
void intel_plane_disable(struct drm_plane *plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 54d4224..cbad738 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1202,18 +1202,18 @@ out_unlock:
return ret;
}
-void intel_plane_restore(struct drm_plane *plane)
+int intel_plane_restore(struct drm_plane *plane)
{
struct intel_plane *intel_plane = to_intel_plane(plane);
if (!plane-crtc || !plane-fb)
- return;
+ return 0;
- intel_update_plane(plane, plane-crtc, plane-fb,
- intel_plane-crtc_x, intel_plane-crtc_y,
- intel_plane-crtc_w, intel_plane-crtc_h,
- intel_plane-src_x, intel_plane-src_y,
- intel_plane-src_w, intel_plane-src_h);
+ return intel_update_plane(plane, plane-crtc, plane-fb,
+ intel_plane-crtc_x, intel_plane-crtc_y,
+ intel_plane-crtc_w, intel_plane-crtc_h,
+ intel_plane-src_x, intel_plane-src_y,
+ intel_plane-src_w, intel_plane-src_h);
}
void intel_plane_disable(struct drm_plane *plane)
--
1.7.10.4
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[Intel-gfx] [v2 07/11] drm/i915: Add 180 degree sprite rotation support
From: Ville Syrjälä ville.syrjala at linux.intel.com
The sprite planes (in fact all display planes starting from gen4)
support 180 degree rotation. Add the relevant low level bits to the
sprite code to make use of that feature.
The upper layers are not yet plugged in.
v2: HSW handles the rotated buffer offset automagically
v3: BDW also handles the rotated buffer offset automagically
Testcase: igt/kms_rotation_crc
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Sagar Kamble sagar.a.kam...@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c | 37 +++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3488567..c70c804 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4171,6 +4171,7 @@ enum punit_power_well {
#define DVS_YUV_ORDER_UYVY (116)
#define DVS_YUV_ORDER_YVYU (216)
#define DVS_YUV_ORDER_VYUY (316)
+#define DVS_ROTATE_180 (115)
#define DVS_DEST_KEY (12)
#define DVS_TRICKLE_FEED_DISABLE (114)
#define DVS_TILED(110)
@@ -4241,6 +4242,7 @@ enum punit_power_well {
#define SPRITE_YUV_ORDER_UYVY(116)
#define SPRITE_YUV_ORDER_YVYU(216)
#define SPRITE_YUV_ORDER_VYUY(316)
+#define SPRITE_ROTATE_180(115)
#define SPRITE_TRICKLE_FEED_DISABLE (114)
#define SPRITE_INT_GAMMA_ENABLE (113)
#define SPRITE_TILED (110)
@@ -4314,6 +4316,7 @@ enum punit_power_well {
#define SP_YUV_ORDER_UYVY(116)
#define SP_YUV_ORDER_YVYU(216)
#define SP_YUV_ORDER_VYUY(316)
+#define SP_ROTATE_180(115)
#define SP_TILED (110)
#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ab5962b..67b1c59 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -437,6 +437,7 @@ struct intel_plane {
unsigned int crtc_w, crtc_h;
uint32_t src_x, src_y;
uint32_t src_w, src_h;
+ unsigned int rotation;
/* Since we need to change the watermarks before/after
* enabling/disabling the planes, we need to store the parameters here
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 404335d..54d4224 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -163,6 +163,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
*crtc,
sprctl = ~SP_PIXFORMAT_MASK;
sprctl = ~SP_YUV_BYTE_ORDER_MASK;
sprctl = ~SP_TILED;
+ sprctl = ~SP_ROTATE_180;
switch (fb-pixel_format) {
case DRM_FORMAT_YUYV:
@@ -234,6 +235,14 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
*crtc,
fb-pitches[0]);
linear_offset -= sprsurf_offset;
+ if (intel_plane-rotation == BIT(DRM_ROTATE_180)) {
+ sprctl |= SP_ROTATE_180;
+
+ x += src_w;
+ y += src_h;
+ linear_offset += src_h * fb-pitches[0] + src_w * pixel_size;
+ }
+
atomic_update = intel_pipe_update_start(intel_crtc, start_vbl_count);
intel_update_primary_plane(intel_crtc);
@@ -363,6 +372,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
sprctl = ~SPRITE_RGB_ORDER_RGBX;
sprctl = ~SPRITE_YUV_BYTE_ORDER_MASK;
sprctl = ~SPRITE_TILED;
+ sprctl = ~SPRITE_ROTATE_180;
switch (fb-pixel_format) {
case DRM_FORMAT_XBGR:
@@ -424,6 +434,17 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
pixel_size, fb-pitches[0]);
linear_offset -= sprsurf_offset;
+ if (intel_plane-rotation == BIT(DRM_ROTATE_180)) {
+ sprctl |= SPRITE_ROTATE_180;
+
+ /* HSW and BDW does this automagically in hardware */
+ if (!IS_HASWELL(dev) !IS_BROADWELL(dev)) {
+ x += src_w;
+ y += src_h;
+ linear_offset += src_h * fb-pitches[0] + src_w *
pixel_size;
+ }
+ }
+
atomic_update = intel_pipe_update_start(intel_crtc, start_vbl_count);
intel_update_primary_plane(intel_crtc);
@@ -569,6 +590,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
dvscntr = ~DVS_RGB_ORDER_XBGR;
dvscntr = ~DVS_YUV_BYTE_ORDER_MASK;
dvscntr = ~DVS_TILED;
+ dvscntr =
Re: [Intel-gfx] [PATCH] drm/i915/vlv: T12 eDP panel timing enforcement during reboot
2014-07-03 19:07 GMT-03:00 Clint Taylor clinton.a.tay...@intel.com:
On 07/02/2014 07:40 AM, Paulo Zanoni wrote:
2014-07-02 5:35 GMT-03:00 Jani Nikula jani.nik...@intel.com:
From: Clint Taylor clinton.a.tay...@intel.com
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.
Ver2: removed redundant pr_crit(), commented magic value for pp_div_reg
Ver3: moved SYS_RESTART check earlier, new name for pp_div.
Ver4: Minor issue changes
Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
[Jani: rebased on current -nightly.]
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
I ended up doing the rebase myself, but I'd like to have a quick review
before pushing.
Thanks,
Jani.
---
drivers/gpu/drm/i915/intel_dp.c | 40
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index b5ec48913b47..f0d23c435cf6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -28,6 +28,8 @@
#include linux/i2c.h
#include linux/slab.h
#include linux/export.h
+#include linux/notifier.h
+#include linux/reboot.h
#include drm/drmP.h
#include drm/drm_crtc.h
#include drm/drm_crtc_helper.h
@@ -336,6 +338,36 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
return
VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}
+/* Reboot notifier handler to shutdown panel power to guarantee T12
timing */
+static int edp_notify_handler(struct notifier_block *this, unsigned long
code,
+ void *unused)
+{
+ struct intel_dp *intel_dp = container_of(this, typeof(*
intel_dp),
+edp_notifier);
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 pp_div;
+ u32 pp_ctrl_reg, pp_div_reg;
+ enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+
+ if (!is_edp(intel_dp) || code != SYS_RESTART)
What if someone does a power off and _very quickly_ starts the system
again? =P
insert same statement for the other code possibilities
If someone removes and applies power within ~300ms this W/A will break down
and the power sequence will not meet the eDP T12 timing. Since the PPS
sequencer does not allow modifications to the default time intervals during
the initial sequence the only way to guarantee we meet T12 time would be to
delay display block power ungate for 300ms. Further delay of the boot time
was not an acceptable solution for the customers.
My suggestion here was just to not-return in more cases, instead of
only SYS_RESTART.
Also, depending based on the suggestions below, you may not need the
is_edp() check (or you may want to convert it to a WARN).
+ return 0;
+
+ if (IS_VALLEYVIEW(dev)) {
This check is not really needed. It could also be an early return or a
WARN.
Since we currently don't handle PCH offsets this was a safe way to allowing
adding of the PCH functionality later if necessary.
+ pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
+ pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
+ pp_div = I915_READ(VLV_PIPE_PP_DIVISOR(pipe));
Or pp_div = I915_READ(pp_div_reg);, since we just defined it :)
Agreed that's another way to do the same thing.
+ pp_div = PP_REFERENCE_DIVIDER_MASK;
+
+ /* 0x1F write to PP_DIV_REG sets max cycle delay */
+ I915_WRITE(pp_div_reg, pp_div | 0x1F);
+ I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS |
PANEL_POWER_OFF);
So this is basically turning the panel off and turning the force VDD
bit off too, and we're not putting any power domain references back.
Even though this might not be a big problem since we're shutting down
the machine anyway, did we attach a serial cable and check if this
won't print any WARNs while shutting down? Shouldn't we try to make
this function call the other functions that shut down stuff instead of
forcing the panel down here?
Development of this W/A was done with serial port attached. This function is
the last method called in the I915 driver before power is removed. At reboot
notifier time there is no error handling possible calling the normal
shutdown functions does more housekeeping then we need for a system that
will not have power in 2 ms.
For this code, even if we don't change it, I think we should at least
put a comment here describing this is an acceptable solution for a
machine shutdown, but that this code should not be reused in other
cases since we're forcing a panel shutdown without respecting
Re: [Intel-gfx] [PATCH] drm/i915: Show cursor size in debugfs/i915_display_info
On Fri, 04 Jul 2014, Damien Lespiau damien.lesp...@intel.com wrote:
On Fri, Jul 04, 2014 at 08:20:11AM +0100, Chris Wilson wrote:
Inlcude the pipe-size and cursor-size in debugfs.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
Pushed to dinq, thanks for the patch and review.
BR,
Jani.
--
Damien
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0869df682f63..6d3f925ae9a2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2434,17 +2434,17 @@ static int i915_display_info(struct seq_file *m,
void *unused)
bool active;
int x, y;
-seq_printf(m, CRTC %d: pipe: %c, active: %s\n,
+seq_printf(m, CRTC %d: pipe: %c, active=%s (size=%dx%d)\n,
crtc-base.base.id, pipe_name(crtc-pipe),
- yesno(crtc-active));
+ yesno(crtc-active), crtc-config.pipe_src_w,
crtc-config.pipe_src_h);
if (crtc-active) {
intel_crtc_info(m, crtc);
active = cursor_position(dev, crtc-pipe, x, y);
-seq_printf(m, \tcursor visible? %s, position (%d, %d),
addr 0x%08x, active? %s\n,
+seq_printf(m, \tcursor visible? %s, position (%d, %d),
size %dx%d, addr 0x%08x, active? %s\n,
yesno(crtc-cursor_base),
- x, y, crtc-cursor_addr,
- yesno(active));
+ x, y, crtc-cursor_width,
crtc-cursor_height,
+ crtc-cursor_addr, yesno(active));
}
seq_printf(m, \tunderrun reporting: cpu=%s pch=%s \n,
--
2.0.1
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--
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[Intel-gfx] [PATCH 10.5/19] drm/i915: BDW also has special-purpose DP DDI clocks
From: Paulo Zanoni paulo.r.zan...@intel.com
Don't let it fall in the HAS_PCH_SPLIT() case.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b5ec489..aedce65 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -756,7 +756,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
if (IS_G4X(dev)) {
divisor = gen4_dpll;
count = ARRAY_SIZE(gen4_dpll);
- } else if (IS_HASWELL(dev)) {
+ } else if (HAS_DDI(dev)) {
/* Haswell has special-purpose DP DDI clocks. */
} else if (HAS_PCH_SPLIT(dev)) {
divisor = pch_dpll;
--
2.0.0
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[Intel-gfx] [PATCH 11/19] drm/i915: Precompute static ddi_pll_sel values in encoders
From: Daniel Vetter daniel.vet...@ffwll.ch
This way only the dynamic WRPLL selection for hdmi ddi mode is
done in intel_ddi_pll_select.
v2: Don't clobber the precomputed values when selecting clocks fro
hdmi encoders.
v3 (from Paulo): Rebase on top of the s/IS_HASWELL/HAS_DDI/ patch.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_crt.c | 4 +++-
drivers/gpu/drm/i915/intel_ddi.c | 34 +++---
drivers/gpu/drm/i915/intel_dp.c | 23 ---
3 files changed, 26 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 76ffa2c..88db4b6 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -315,8 +315,10 @@ static bool intel_crt_compute_config(struct intel_encoder
*encoder,
pipe_config-pipe_bpp = 24;
/* FDI must always be 2.7 GHz */
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev)) {
+ pipe_config-ddi_pll_sel = PORT_CLK_SEL_SPLL;
pipe_config-port_clock = 135000 * 2;
+ }
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5356e3e..6e976ba 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -403,6 +403,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
I915_WRITE(WRPLL_CTL1, val ~WRPLL_PLL_ENABLE);
POSTING_READ(WRPLL_CTL1);
}
+ intel_crtc-config.ddi_pll_sel = PORT_CLK_SEL_NONE;
break;
case PORT_CLK_SEL_WRPLL2:
plls-wrpll2_refcount--;
@@ -413,13 +414,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
I915_WRITE(WRPLL_CTL2, val ~WRPLL_PLL_ENABLE);
POSTING_READ(WRPLL_CTL2);
}
+ intel_crtc-config.ddi_pll_sel = PORT_CLK_SEL_NONE;
break;
}
WARN(plls-wrpll1_refcount 0, Invalid WRPLL1 refcount\n);
WARN(plls-wrpll2_refcount 0, Invalid WRPLL2 refcount\n);
-
- intel_crtc-config.ddi_pll_sel = PORT_CLK_SEL_NONE;
}
#define LC_FREQ 2700
@@ -739,7 +739,6 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
{
struct drm_crtc *crtc = intel_crtc-base;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- struct drm_encoder *encoder = intel_encoder-base;
struct drm_i915_private *dev_priv = crtc-dev-dev_private;
struct intel_ddi_plls *plls = dev_priv-ddi_plls;
int type = intel_encoder-type;
@@ -748,26 +747,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
intel_ddi_put_crtc_pll(crtc);
- if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- switch (intel_dp-link_bw) {
- case DP_LINK_BW_1_62:
- intel_crtc-config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
- break;
- case DP_LINK_BW_2_7:
- intel_crtc-config.ddi_pll_sel =
PORT_CLK_SEL_LCPLL_1350;
- break;
- case DP_LINK_BW_5_4:
- intel_crtc-config.ddi_pll_sel =
PORT_CLK_SEL_LCPLL_2700;
- break;
- default:
- DRM_ERROR(Link bandwidth %d unsupported\n,
- intel_dp-link_bw);
- return false;
- }
-
- } else if (type == INTEL_OUTPUT_HDMI) {
+ if (type == INTEL_OUTPUT_HDMI) {
uint32_t reg, val;
unsigned p, n2, r2;
@@ -808,14 +788,6 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
plls-wrpll2_refcount++;
intel_crtc-config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
}
-
- } else if (type == INTEL_OUTPUT_ANALOG) {
- DRM_DEBUG_KMS(Using SPLL on pipe %c\n,
- pipe_name(pipe));
- intel_crtc-config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
- } else {
- WARN(1, Invalid DDI encoder type %d\n, type);
- return false;
}
return true;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aedce65..69db121 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -746,6 +746,22 @@ intel_dp_connector_unregister(struct intel_connector
*intel_connector)
}
static void
+hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
+{
+ switch (link_bw) {
+ case DP_LINK_BW_1_62:
+ pipe_config-ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ pipe_config-ddi_pll_sel =
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Update the DSI ULPS entry/exit sequence
On Thu, 03 Jul 2014, Chris Wilson ch...@chris-wilson.co.uk wrote: On Thu, Jul 03, 2014 at 04:35:41PM +0530, Shobhit Kumar wrote: We should keep DEVICE_READY bit set in the ULPS enter sequence. In exit sequence also we should set DEVICE_READY, but thats causing blankout for me. Also exit sequence is simplified as per hw team recommendation. This should fix - [drm:intel_dsi_clear_device_ready] *ERROR* DSI LP not going Low Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80818 Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com They silence that warning and appears to still work, Tested-by: Chris Wilson ch...@chris-wilson.co.uk Pushed to -fixes, thanks for the patches and testing. BR, Jani. -Chris -- Chris Wilson, Intel Open Source Technology Centre -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13.5/19] drm/i915: add POWER_DOMAIN_PLLS
From: Paulo Zanoni paulo.r.zan...@intel.com
And get/put it when needed. The special thing about this commit is
that it will now return false in ibx_pch_dpll_get_hw_state() in case
the power domain is not enabled. This will fix some WARNs we have when
we run pm_rpm on SNB.
Testcase: igt/pm_rpm
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=80463
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 10 ++
drivers/gpu/drm/i915/intel_pm.c | 1 +
4 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a89cc7a..e79ddbf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2134,6 +2134,8 @@ static const char *power_domain_str(enum
intel_display_power_domain domain)
return VGA;
case POWER_DOMAIN_AUDIO:
return AUDIO;
+ case POWER_DOMAIN_PLLS:
+ return PLLS;
case POWER_DOMAIN_INIT:
return INIT;
default:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b1f1518..2ec7cb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -129,6 +129,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
+ POWER_DOMAIN_PLLS,
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3bbc798..1d919ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1837,6 +1837,8 @@ static void intel_enable_shared_dpll(struct intel_crtc
*crtc)
}
WARN_ON(pll-on);
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
DRM_DEBUG_KMS(enabling %s\n, pll-name);
pll-enable(dev_priv, pll);
pll-on = true;
@@ -1873,6 +1875,8 @@ static void intel_disable_shared_dpll(struct intel_crtc
*crtc)
DRM_DEBUG_KMS(disabling %s\n, pll-name);
pll-disable(dev_priv, pll);
pll-on = false;
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
}
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -11298,6 +11302,9 @@ static bool ibx_pch_dpll_get_hw_state(struct
drm_i915_private *dev_priv,
{
uint32_t val;
+ if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
+ return false;
+
val = I915_READ(PCH_DPLL(pll-id));
hw_state-dpll = val;
hw_state-fp0 = I915_READ(PCH_FP0(pll-id));
@@ -12864,6 +12871,9 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
DRM_DEBUG_KMS(%s hw state readout: refcount %i, on %i\n,
pll-name, pll-refcount, pll-on);
+
+ if (pll-refcount)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
}
list_for_each_entry(encoder, dev-mode_config.encoder_list,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 31ae2b4..cf4c521 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6310,6 +6310,7 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
BIT(POWER_DOMAIN_PORT_CRT) |\
+ BIT(POWER_DOMAIN_PLLS) |\
BIT(POWER_DOMAIN_INIT))
#define HSW_DISPLAY_POWER_DOMAINS (\
(POWER_DOMAIN_MASK ~HSW_ALWAYS_ON_POWER_DOMAINS) |\
--
2.0.0
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Re: [Intel-gfx] [PATCH 10.5/19] drm/i915: BDW also has special-purpose DP DDI clocks
On Fri, Jul 04, 2014 at 11:26:03AM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Don't let it fall in the HAS_PCH_SPLIT() case.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
--
Damien
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b5ec489..aedce65 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -756,7 +756,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
if (IS_G4X(dev)) {
divisor = gen4_dpll;
count = ARRAY_SIZE(gen4_dpll);
- } else if (IS_HASWELL(dev)) {
+ } else if (HAS_DDI(dev)) {
/* Haswell has special-purpose DP DDI clocks. */
} else if (HAS_PCH_SPLIT(dev)) {
divisor = pch_dpll;
--
2.0.0
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[Intel-gfx] [PATCH 2/5] drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW
From: Paulo Zanoni paulo.r.zan...@intel.com So don't write it, otherwise we will trigger unclaimed register errors. Testcase: igt/pm_rpm/rte Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c12a5da..14505a1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7345,8 +7345,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) WARN(I915_READ(PCH_PP_STATUS) PP_ON, Panel power on\n); WARN(I915_READ(BLC_PWM_CPU_CTL2) BLM_PWM_ENABLE, CPU PWM1 enabled\n); - WARN(I915_READ(HSW_BLC_PWM2_CTL) BLM_PWM_ENABLE, -CPU PWM2 enabled\n); + if (IS_HASWELL(dev)) + WARN(I915_READ(HSW_BLC_PWM2_CTL) BLM_PWM_ENABLE, +CPU PWM2 enabled\n); WARN(I915_READ(BLC_PWM_PCH_CTL1) BLM_PCH_PWM_ENABLE, PCH PWM1 enabled\n); WARN(I915_READ(UTIL_PIN_CTL) UTIL_PIN_ENABLE, -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915: don't write powered down IRQ registers on Gen 8
From: Paulo Zanoni paulo.r.zan...@intel.com If we enable unclaimed register reporting on Gen 8, we will discover that the IRQ registers for pipes B and C are also on the power well, so writes to them when the power well is disabled result in unclaimed register errors. Also, hsw_power_well_post_enable() already takes care of re-enabling them once the power well is enabled. Testcase: igt/pm_rpm/rte Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/i915_irq.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1c1ec22..2e116e9d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3193,7 +3193,9 @@ static void gen8_irq_reset(struct drm_device *dev) gen8_gt_irq_reset(dev_priv); for_each_pipe(pipe) - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); + if (intel_display_power_enabled(dev_priv, + POWER_DOMAIN_PIPE(pipe))) + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); GEN5_IRQ_RESET(GEN8_DE_PORT_); GEN5_IRQ_RESET(GEN8_DE_MISC_); @@ -3526,8 +3528,11 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv-de_irq_mask[PIPE_C] = ~de_pipe_masked; for_each_pipe(pipe) - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv-de_irq_mask[pipe], - de_pipe_enables); + if (intel_display_power_enabled(dev_priv, + POWER_DOMAIN_PIPE(pipe))) + GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, + dev_priv-de_irq_mask[pipe], + de_pipe_enables); GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); } -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: BDW can also detect unclaimed registers
From: Paulo Zanoni paulo.r.zan...@intel.com
By the time I wrote this patch, it allowed me to catch some problems.
But due to patch reordering - in order to prevent fake regression
reports - this patch may be merged after the fixes of the problems
identified by this patch.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/intel_uncore.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8a0cb0c..bdb223c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -303,6 +303,7 @@ static const struct intel_device_info
intel_broadwell_d_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
@@ -314,6 +315,7 @@ static const struct intel_device_info
intel_broadwell_m_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
@@ -325,6 +327,7 @@ static const struct intel_device_info
intel_broadwell_gt3d_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
@@ -336,6 +339,7 @@ static const struct intel_device_info
intel_broadwell_gt3m_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index de5402f..1fcf78b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -788,6 +788,7 @@ static bool is_gen8_shadowed(struct drm_i915_private
*dev_priv, u32 reg)
static void \
gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool
trace) { \
REG_WRITE_HEADER; \
+ hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
if (reg 0x4 !is_gen8_shadowed(dev_priv, reg)) { \
if (dev_priv-uncore.forcewake_count == 0) \
dev_priv-uncore.funcs.force_wake_get(dev_priv, \
@@ -799,6 +800,8 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg,
u##x val, bool trace
} else { \
__raw_i915_write##x(dev_priv, reg, val); \
} \
+ hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
+ hsw_unclaimed_reg_detect(dev_priv); \
REG_WRITE_FOOTER; \
}
--
2.0.0
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[Intel-gfx] [PATCH 0/5] BDW unclaimed registers
From: Paulo Zanoni paulo.r.zan...@intel.com Hi Even though this feature is super useful for hardware enabling, we ended up not enabling it on BDW, so we still silently hit some unclaimed registers on this platform. This series first fixes the bugs fround by the feature, then introduces the feature later. It also introduces some rework on the unclaimed register code, and I'd like to hear opinions and suggestsions about it. Also notice that a patch to detect unclaimed registers on BDW was also sent to this list on Feb 21. I tested these patches briefly before my BDW machine died. They worked at that time, so I hope they keep working now. Anyway, reviewers and QA should catch anything wrong with these, right? :) Thanks, Paulo Paulo Zanoni (5): drm/i915: don't write powered down IRQ registers on Gen 8 drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW drm/i915: extract and improve gen8_irq_power_well_post_enable drm/i915: reorganize the unclaimed register detection code drm/i915: BDW can also detect unclaimed registers drivers/gpu/drm/i915/i915_drv.c | 4 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 23 ++-- drivers/gpu/drm/i915/i915_params.c | 6 +++ drivers/gpu/drm/i915/intel_display.c | 5 ++- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 18 + drivers/gpu/drm/i915/intel_uncore.c | 71 8 files changed, 101 insertions(+), 28 deletions(-) -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: extract and improve gen8_irq_power_well_post_enable
From: Paulo Zanoni paulo.r.zan...@intel.com
Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
so we can reuse the nice IRQ macros we have there. The main difference
is that now we're going to check if the IIR register is non-zero when
we try to re-enable the interrupts.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 12
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 18 ++
3 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e116e9d..a8b8b6b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3204,6 +3204,18 @@ static void gen8_irq_reset(struct drm_device *dev)
ibx_irq_reset(dev);
}
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(dev_priv-irq_lock, irqflags);
+ GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv-de_irq_mask[PIPE_B],
+ ~dev_priv-de_irq_mask[PIPE_B]);
+ GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv-de_irq_mask[PIPE_C],
+ ~dev_priv-de_irq_mask[PIPE_C]);
+ spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
+}
+
static void cherryview_irq_preinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5f7c7bd..46a3a09 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -687,6 +687,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_device
*dev);
void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
int intel_get_crtc_scanline(struct intel_crtc *crtc);
void i9xx_check_fifo_underruns(struct drm_device *dev);
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
/* intel_crt.c */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 31ae2b4..4cc9e5c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5913,7 +5913,6 @@ bool intel_display_power_enabled(struct drm_i915_private
*dev_priv,
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv-dev;
- unsigned long irqflags;
/*
* After we re-enable the power well, if we touch VGA register 0x3d5
@@ -5929,21 +5928,8 @@ static void hsw_power_well_post_enable(struct
drm_i915_private *dev_priv)
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(dev-pdev, VGA_RSRC_LEGACY_IO);
- if (IS_BROADWELL(dev)) {
- spin_lock_irqsave(dev_priv-irq_lock, irqflags);
- I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
- dev_priv-de_irq_mask[PIPE_B]);
- I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
- ~dev_priv-de_irq_mask[PIPE_B] |
- GEN8_PIPE_VBLANK);
- I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
- dev_priv-de_irq_mask[PIPE_C]);
- I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
- ~dev_priv-de_irq_mask[PIPE_C] |
- GEN8_PIPE_VBLANK);
- POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
- spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
- }
+ if (IS_BROADWELL(dev))
+ gen8_irq_power_well_post_enable(dev_priv);
}
static void hsw_set_power_well(struct drm_i915_private *dev_priv,
--
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Re: [Intel-gfx] [v2 10/11] drm/i915: Add 180 degree primary plane rotation support
On Fri, Jul 04, 2014 at 03:14:02PM +0530, sonika.jin...@intel.com wrote:
+static int intel_primary_plane_set_property(struct drm_plane *plane,
+ struct drm_property *prop,
+ uint64_t val)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ struct intel_crtc *intel_crtc = to_intel_crtc(plane-crtc);
+ struct drm_crtc *crtc = intel_crtc-base;
+ uint64_t old_val;
+
+ if (prop == plane-rotation_property) {
+ /* exactly one rotation angle please */
+ if (hweight32(val 0xf) != 1)
+ return -EINVAL;
+
+ old_val = intel_plane-rotation;
+ intel_plane-rotation = val;
+
+ if (intel_crtc-active intel_crtc-primary_enabled) {
+ intel_crtc_wait_for_pending_flips(crtc);
+
+ /* FBC does not work on some platforms for rotated planes */
+ if (INTEL_INFO(dev)-gen = 4 !IS_G4X(dev)) {
+ if (dev_priv-fbc.plane == intel_crtc-plane
+ intel_plane-rotation !=
BIT(DRM_ROTATE_0))
+ intel_disable_fbc(dev);
+ /* If rotation was set earlier and new rotation
is 0, we might
+ * have disabled fbc earlier. So update it now
*/
+ else if (intel_plane-rotation ==
BIT(DRM_ROTATE_0)
+ old_val != BIT(DRM_ROTATE_0))
+ intel_update_fbc(dev);
I see a intel_update_fbc() called with the struct_mutext lock elsewhere,
don't we need it here as well?
mutex_lock(dev-struct_mutex);
intel_update_fbc(dev);
mutex_unlock(dev-struct_mutex);
--
Damien
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[Intel-gfx] [PATCH 2/2] drm/i915: fix D_COMP usage on BDW
From: Paulo Zanoni paulo.r.zan...@intel.com
On HSW, the D_COMP register can be accessed through the mailbox (read
and write) or through MMIO on a MCHBAR offset (read only). On BDW, the
access should be done through MMIO on another address. So to account
for all these cases, create hsw_read_dcomp() with the correct
implementation for reading, and also fix hsw_write_dcomp() to do the
correct thing on BDW.
With this patch, we can now get back from the PC8+ state on BDW. We
were previously getting a black screen and lots of dmesg errors.
Please notice that the bug only happens when you actually reach the
PC8+ states, not when you only allow it.
Testcase: igt/pm_rpm/rte
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 -
drivers/gpu/drm/i915/intel_display.c | 21 -
2 files changed, 20 insertions(+), 6 deletions(-)
I tested this before my BDW machine died and it worked. I couldn't test it again
since then. Please notice that this is an important patch that prevents the
machine from being useless after runtime PM is enabled (and we actually reach
package C8 or deeper states). This will be even easier to reproduce after we
merge Daniel's RPM on DPMS series.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3488567..3e4b13e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5962,7 +5962,10 @@ enum punit_power_well {
#define LCPLL_CD_SOURCE_FCLK (121)
#define LCPLL_CD_SOURCE_FCLK_DONE (119)
-#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
+/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this
register,
+ * since on HSW we can't write to it using I915_WRITE. */
+#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
+#define D_COMP_BDW 0x138144
#define D_COMP_RCOMP_IN_PROGRESS (19)
#define D_COMP_COMP_FORCE (18)
#define D_COMP_COMP_DISABLE (10)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6986594..3a8c9a7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7362,6 +7362,16 @@ static void assert_can_disable_lcpll(struct
drm_i915_private *dev_priv)
WARN(!dev_priv-pm.irqs_disabled, IRQs enabled\n);
}
+static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = dev_priv-dev;
+
+ if (IS_HASWELL(dev))
+ return I915_READ(D_COMP_HSW);
+ else
+ return I915_READ(D_COMP_BDW);
+}
+
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
{
struct drm_device *dev = dev_priv-dev;
@@ -7373,9 +7383,9 @@ static void hsw_write_dcomp(struct drm_i915_private
*dev_priv, uint32_t val)
DRM_ERROR(Failed to write D_COMP\n);
mutex_unlock(dev_priv-rps.hw_lock);
} else {
- I915_WRITE(D_COMP, val);
+ I915_WRITE(D_COMP_BDW, val);
+ POSTING_READ(D_COMP_BDW);
}
- POSTING_READ(D_COMP);
}
/*
@@ -7413,12 +7423,13 @@ static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv,
if (wait_for((I915_READ(LCPLL_CTL) LCPLL_PLL_LOCK) == 0, 1))
DRM_ERROR(LCPLL still locked\n);
- val = I915_READ(D_COMP);
+ val = hsw_read_dcomp(dev_priv);
val |= D_COMP_COMP_DISABLE;
hsw_write_dcomp(dev_priv, val);
ndelay(100);
- if (wait_for((I915_READ(D_COMP) D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
+ if (wait_for((hsw_read_dcomp(dev_priv) D_COMP_RCOMP_IN_PROGRESS) == 0,
+1))
DRM_ERROR(D_COMP RCOMP still in progress\n);
if (allow_power_down) {
@@ -7467,7 +7478,7 @@ static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv)
POSTING_READ(LCPLL_CTL);
}
- val = I915_READ(D_COMP);
+ val = hsw_read_dcomp(dev_priv);
val |= D_COMP_COMP_FORCE;
val = ~D_COMP_COMP_DISABLE;
hsw_write_dcomp(dev_priv, val);
--
2.0.0
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[Intel-gfx] [PATCH 1/2] drm/i915: fix hsw_write_dcomp() error message
From: Paulo Zanoni paulo.r.zan...@intel.com
That function can be used to write anything on D_COMP, not just
disable it, so print a more appropriate message.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c12a5da..6986594 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7370,7 +7370,7 @@ static void hsw_write_dcomp(struct drm_i915_private
*dev_priv, uint32_t val)
mutex_lock(dev_priv-rps.hw_lock);
if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
val))
- DRM_ERROR(Failed to disable D_COMP\n);
+ DRM_ERROR(Failed to write to D_COMP\n);
mutex_unlock(dev_priv-rps.hw_lock);
} else {
I915_WRITE(D_COMP, val);
--
2.0.0
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Re: [Intel-gfx] [v2 00/11] Support for 180 degree HW rotation
On Fri, Jul 04, 2014 at 03:13:52PM +0530, sonika.jin...@intel.com wrote: From: Sonika Jindal sonika.jin...@intel.com Enables 180 degree rotation for sprite and primary planes. Updated the primary plane rotation support as per the new universal plane design. Most of these patches were already reviewed in intel-gfx in February 2014 thats why there is version history in few of them. v2: Moved rotation_property to drm_plane. Added updation of FBC when rotation is again set to 0. Testcase: kms_rotation_crc This igt can be extended for clipped rotation cases. Right it only tests 180 degree rotation for sprite and primary plane with crc check. Sonika Jindal (2): drm/i915: Add 180 degree primary plane rotation support drm: Resetting rotation property Ville Syrjälä (9): drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h drm: Add support_bits parameter to drm_property_create_bitmask() drm: Add drm_mode_create_rotation_property() drm/omap: Switch omapdrm over to drm_mode_create_rotation_property() drm: Add drm_rect rotation functions drm: Add drm_rotation_simplify() drm/i915: Add 180 degree sprite rotation support drm/i915: Make intel_plane_restore() return an error drm/i915: Add rotation property for sprites Missing from this series, your two documentation patches (we need to bundle things up as a entity that makes sense for one of the maintainers to pick it up (either Dave or Daniel)). -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 11/11] drm: Resetting rotation property
On Fri, Jul 04, 2014 at 03:14:03PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Reset rotation property to 0 wherever applicable
v2: Also calling set_property of the plane to set the rotation in the plane
structure.
Cc: damien.lesp...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/drm_fb_helper.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index d5d8cea..30806b4 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -282,9 +282,23 @@ static bool restore_fbdev_mode(struct drm_fb_helper
*fb_helper)
drm_warn_on_modeset_not_all_locked(dev);
- list_for_each_entry(plane, dev-mode_config.plane_list, head)
+ list_for_each_entry(plane, dev-mode_config.plane_list, head) {
+
+ if (plane-rotation_property) {
+ int ret = 0;
+ if (plane-funcs-set_property)
+ ret = plane-funcs-set_property(plane,
+ plane-rotation_property,
+ BIT(DRM_ROTATE_0));
+ if (!ret)
+ drm_object_property_set_value(plane-base,
+ plane-rotation_property,
+ BIT(DRM_ROTATE_0));
+ }
+
if (plane-type != DRM_PLANE_TYPE_PRIMARY)
drm_plane_force_disable(plane);
+ }
for (i = 0; i fb_helper-crtc_count; i++) {
struct drm_mode_set *mode_set =
fb_helper-crtc_info[i].mode_set;
--
1.7.10.4
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[Intel-gfx] [PATCH 1/4] drm/i915: add POWER_DOMAIN_PLLS
From: Paulo Zanoni paulo.r.zan...@intel.com
And get/put it when needed. The special thing about this commit is
that it will now return false in ibx_pch_dpll_get_hw_state() in case
the power domain is not enabled. This will fix some WARNs we have when
we run pm_rpm on SNB.
Testcase: igt/pm_rpm
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=80463
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 10 ++
drivers/gpu/drm/i915/intel_pm.c | 1 +
4 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8da9985..18d4f9e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2134,6 +2134,8 @@ static const char *power_domain_str(enum
intel_display_power_domain domain)
return VGA;
case POWER_DOMAIN_AUDIO:
return AUDIO;
+ case POWER_DOMAIN_PLLS:
+ return PLLS;
case POWER_DOMAIN_INIT:
return INIT;
default:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ac06c0f..1cc1b8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -129,6 +129,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
+ POWER_DOMAIN_PLLS,
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c12a5da..3d69097 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1837,6 +1837,8 @@ static void intel_enable_shared_dpll(struct intel_crtc
*crtc)
}
WARN_ON(pll-on);
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
DRM_DEBUG_KMS(enabling %s\n, pll-name);
pll-enable(dev_priv, pll);
pll-on = true;
@@ -1873,6 +1875,8 @@ static void intel_disable_shared_dpll(struct intel_crtc
*crtc)
DRM_DEBUG_KMS(disabling %s\n, pll-name);
pll-disable(dev_priv, pll);
pll-on = false;
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
}
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -11280,6 +11284,9 @@ static bool ibx_pch_dpll_get_hw_state(struct
drm_i915_private *dev_priv,
{
uint32_t val;
+ if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
+ return false;
+
val = I915_READ(PCH_DPLL(pll-id));
hw_state-dpll = val;
hw_state-fp0 = I915_READ(PCH_FP0(pll-id));
@@ -12845,6 +12852,9 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
DRM_DEBUG_KMS(%s hw state readout: refcount %i, on %i\n,
pll-name, pll-refcount, pll-on);
+
+ if (pll-refcount)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
}
list_for_each_entry(encoder, dev-mode_config.encoder_list,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 31ae2b4..cf4c521 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6310,6 +6310,7 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
BIT(POWER_DOMAIN_PORT_CRT) |\
+ BIT(POWER_DOMAIN_PLLS) |\
BIT(POWER_DOMAIN_INIT))
#define HSW_DISPLAY_POWER_DOMAINS (\
(POWER_DOMAIN_MASK ~HSW_ALWAYS_ON_POWER_DOMAINS) |\
--
2.0.0
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[Intel-gfx] [PATCH 2/4] drm/i915: check the power domains in ironlake_get_pipe_config()
From: Paulo Zanoni paulo.r.zan...@intel.com Just like we already do in haswell_get_pipe_config(). This should prevent some WARNs when we run pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3d69097..0e6217a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7261,6 +7261,10 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev-dev_private; uint32_t tmp; + if (!intel_display_power_enabled(dev_priv, +POWER_DOMAIN_PIPE(crtc-pipe))) + return false; + pipe_config-cpu_transcoder = (enum transcoder) crtc-pipe; pipe_config-shared_dpll = DPLL_ID_PRIVATE; -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/4] SNB runtime PM fixes
From: Paulo Zanoni paulo.r.zan...@intel.com Hi When I originally wrote and tested SNB runtime PM it was working without any errors, then I sent the patches to the mailing list and we ended up discarding one of the patches that was needed. We ended up replacing that patch with a few patches that only plugged the HSW holes, leaving SNB runtime PM broken since then. Since I never got any bug report about this, I assumed SNB runtime PM was working and didn't test things again... Then a long time later we got the bug reports, and now we have fixes :) Also notice that patch 1 was also sent as part of the Runtime PM on DPMS on HSW series, so it's duplicated. Thanks, Paulo Paulo Zanoni (4): drm/i915: add POWER_DOMAIN_PLLS drm/i915: check the power domains in ironlake_get_pipe_config() drm/i915: check the power domains in intel_lvds_get_hw_state() drm/i915: don't read LVDS regs at compute_config time drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 14 ++ drivers/gpu/drm/i915/intel_lvds.c| 18 ++ drivers/gpu/drm/i915/intel_pm.c | 1 + 5 files changed, 32 insertions(+), 4 deletions(-) -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: don't read LVDS regs at compute_config time
From: Paulo Zanoni paulo.r.zan...@intel.com
We may reach this point while the machine is still runtime suspended,
so we'll hit a WARN. The other encoders also don't touch registers at
this point, so instead of waking the machine up, write some code to
keep the register always at the same state, including after we runtime
suspend/resume.
Testcase: igt/pm_rpm
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_lvds.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 8aa7973..c511287 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -51,6 +51,7 @@ struct intel_lvds_encoder {
bool is_dual_link;
u32 reg;
+ u32 a3_power;
struct intel_lvds_connector *attached_connector;
};
@@ -170,8 +171,11 @@ static void intel_pre_enable_lvds(struct intel_encoder
*encoder)
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
* appropriately here, but we need to look more thoroughly into how
-* panels behave in the two modes.
+* panels behave in the two modes. For now, let's just maintain the
+* value we got from the BIOS.
*/
+temp = ~LVDS_A3_POWER_MASK;
+temp |= lvds_encoder-a3_power;
/* Set the dithering flag on LVDS as needed, note that there is no
* special lvds dither control bit on pch-split platforms, dithering is
@@ -269,7 +273,6 @@ static bool intel_lvds_compute_config(struct intel_encoder
*intel_encoder,
struct intel_crtc_config *pipe_config)
{
struct drm_device *dev = intel_encoder-base.dev;
- struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_lvds_encoder *lvds_encoder =
to_lvds_encoder(intel_encoder-base);
struct intel_connector *intel_connector =
@@ -284,8 +287,7 @@ static bool intel_lvds_compute_config(struct intel_encoder
*intel_encoder,
return false;
}
- if ((I915_READ(lvds_encoder-reg) LVDS_A3_POWER_MASK) ==
- LVDS_A3_POWER_UP)
+ if (lvds_encoder-a3_power == LVDS_A3_POWER_UP)
lvds_bpp = 8*3;
else
lvds_bpp = 6*3;
@@ -1086,6 +1088,9 @@ out:
DRM_DEBUG_KMS(detected %s-link lvds configuration\n,
lvds_encoder-is_dual_link ? dual : single);
+ lvds_encoder-a3_power = I915_READ(lvds_encoder-reg)
+LVDS_A3_POWER_MASK;
+
/*
* Unlock registers and just
* leave them unlocked
--
2.0.0
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[Intel-gfx] [PATCH 3/4] drm/i915: check the power domains in intel_lvds_get_hw_state()
From: Paulo Zanoni paulo.r.zan...@intel.com Just like we do for the other encoders. This should fix some WARNs when running pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_lvds.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 4d29a83..8aa7973 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -71,8 +71,13 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, struct drm_device *dev = encoder-base.dev; struct drm_i915_private *dev_priv = dev-dev_private; struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder-base); + enum intel_display_power_domain power_domain; u32 tmp; + power_domain = intel_display_port_power_domain(encoder); + if (!intel_display_power_enabled(dev_priv, power_domain)) + return false; + tmp = I915_READ(lvds_encoder-reg); if (!(tmp LVDS_PORT_EN)) -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
