[Intel-gfx] [PATCH] drm: Fix race when checking for fb in the generic kms obj lookup
In my review of commit 98f75de40e9d83c3a90d294b8fd25fa2874212a9 Author: Rob Clark robdcl...@gmail.com Date: Fri May 30 11:37:03 2014 -0400 drm: add object property typ I asked for a check to make sure that we never leak an fb from the generic mode object lookup since those have completely different lifetime rules. Rob added it, but outside of the idr mutex, which means that our dereference of obj-type can already chase free'd memory. Somehow I didn't spot this, so fix this asap. Cc: Rob Clark robdcl...@gmail.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/drm_crtc.c | 6 +++--- drivers/gpu/drm/drm_fb_helper.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index f0a47907..853ab9cad071 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -429,6 +429,9 @@ static struct drm_mode_object *_object_find(struct drm_device *dev, if (!obj || (type != DRM_MODE_OBJECT_ANY obj-type != type) || (obj-id != id)) obj = NULL; + /* don't leak out unref'd fb's */ + if (obj (obj-type == DRM_MODE_OBJECT_FB)) + obj = NULL; mutex_unlock(dev-mode_config.idr_mutex); return obj; @@ -454,9 +457,6 @@ struct drm_mode_object *drm_mode_object_find(struct drm_device *dev, * function.*/ WARN_ON(type == DRM_MODE_OBJECT_FB); obj = _object_find(dev, id, type); - /* don't leak out unref'd fb's */ - if (obj (obj-type == DRM_MODE_OBJECT_FB)) - obj = NULL; return obj; } EXPORT_SYMBOL(drm_mode_object_find); diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index d5d8cea1a679..ff586ae3d92a 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -303,6 +303,7 @@ static bool restore_fbdev_mode(struct drm_fb_helper *fb_helper) } return error; } + /** * drm_fb_helper_restore_fbdev_mode - restore fbdev configuration * @fb_helper: fbcon to restore -- 2.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix cursor handling when runtime suspended
On Wed, Jul 23, 2014 at 08:38:19PM -0300, Paulo Zanoni wrote: 2014-07-23 19:41 GMT-03:00 Daniel Vetter dan...@ffwll.ch: On Thu, Jul 24, 2014 at 12:35:25AM +0200, Daniel Vetter wrote: On Wed, Jul 23, 2014 at 06:30:59PM -0300, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com If we're runtime suspended and try to use the cursor interfaces, we will get a lot of WARNs saying we did the wrong thing. For intel_crtc_update_cursor(), all we need to do is return if the CRTC is not active, since writing the registers won't really have any effect if the screen is not visible, and we will write the registers later when enabling the screen. For intel_crtc_cursor_set_obj(), we just get the proper power domain reference, since this function does a lot of stuff. Testcase: igt/pm_rpm/cursor Testcase: igt/pm_rpm/cursor-dpms Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81645 Cc: sta...@vger.kernel.org Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d1e9570..c8f36b0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8151,6 +8151,9 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, if (base == 0 intel_crtc-cursor_base == 0) return; + if (!intel_crtc-active) + return; Don't we need the same trick in intel_crtc_cursor_set_obj? This gets called if the cursor object changes (instead of just moving it around). Rechecked and realized the only I915_WRITE in there is for gen2. I guess we don't care ;-) Nope. You need to look at the subfunctions and their subsubfunctions and their subsubsubfunctions and so on. This is what happens when I remove just the display_power_get/put calls: [ 35.762635] [drm:intel_crtc_cursor_set_obj] cursor off [ 35.762665] [drm:add_framebuffer_internal] [FB:63] [ 35.762685] [ cut here ] [ 35.762714] WARNING: CPU: 0 PID: 3169 at drivers/gpu/drm/i915/i915_gem_gtt.c:1480 gen6_ggtt_insert_entries+0x116/0x120 [i915]() [ 35.762716] Modules linked in: fuse intel_rapl x86_pkg_temp_thermal intel_powerclamp serio_raw i915 i2c_algo_bit drm_kms_helper drm i2c_i801 mei_me mei i2c_designware_platform i2c_designware_core sg sd_mod ehci_pci ehci_hcd ahci libahci e1000e xhci_hcd sdhci_acpi sdhci [ 35.762748] CPU: 0 PID: 3169 Comm: pm_rpm Not tainted 3.16.0-rc6.1407232028+ #695 [ 35.762751] Hardware name: Intel Corporation Shark Bay Client platform/WhiteTip Mountain 1, BIOS HSWLPTU1.86C.0137.R00.1403031632 03/03/2014 [ 35.762754] 0009 88009ce139c8 816b6a61 [ 35.762760] 88009ce13a00 81075d88 92946000 [ 35.762765] c90010d04d74 88009d938bb8 c90010d04d68 88009ce13a10 [ 35.762770] Call Trace: [ 35.762782] [816b6a61] dump_stack+0x4d/0x66 [ 35.762789] [81075d88] warn_slowpath_common+0x78/0xa0 [ 35.762793] [81075e65] warn_slowpath_null+0x15/0x20 [ 35.762814] [a0169716] gen6_ggtt_insert_entries+0x116/0x120 [i915] [ 35.762831] [a0168ce9] ggtt_bind_vma+0xd9/0x100 [i915] [ 35.762850] [a0172583] i915_gem_object_pin+0x683/0x750 [i915] [ 35.762869] [a0173cd7] i915_gem_object_pin_to_display_plane+0x97/0x1d0 [i915] [ 35.762894] [a01a891c] intel_crtc_cursor_set_obj+0x16c/0x520 [i915] [ 35.762916] [a01a8df5] intel_cursor_plane_update+0xe5/0x120 [i915] [ 35.762937] [a00d83a4] setplane_internal+0x264/0x2b0 [drm] [ 35.762952] [a00d850e] drm_mode_cursor_common+0x11e/0x320 [drm] [ 35.762968] [a00dbb0c] drm_mode_cursor_ioctl+0x3c/0x40 [drm] [ 35.762978] [a00cb87f] drm_ioctl+0x1df/0x6a0 [drm] [ 35.762983] [816be9b9] ? mutex_unlock+0x9/0x10 [ 35.762988] [811eaae6] ? seq_read+0xb6/0x3e0 [ 35.762994] [811d97e0] do_vfs_ioctl+0x2e0/0x4e0 [ 35.762998] [816c0bf7] ? sysret_check+0x1b/0x56 [ 35.763004] [810c47fd] ? trace_hardirqs_on_caller+0x15d/0x200 [ 35.763008] [811d9a61] SyS_ioctl+0x81/0xa0 [ 35.763013] [816c0bd2] system_call_fastpath+0x16/0x1b [ 35.763015] ---[ end trace 189706dc7c79e8d7 ]--- [ 35.763018] [ cut here ] [ 35.763039] WARNING: CPU: 0 PID: 3169 at drivers/gpu/drm/i915/intel_uncore.c:47 assert_device_not_suspended.isra.8+0x43/0x50 [i915]() [ 35.763041] Device suspended [ 35.763043] Modules linked in: fuse intel_rapl x86_pkg_temp_thermal intel_powerclamp serio_raw i915 i2c_algo_bit drm_kms_helper drm i2c_i801 mei_me mei i2c_designware_platform
[Intel-gfx] [PATCH] drm: Fix race when checking for fb in the generic kms obj lookup
In my review of commit 98f75de40e9d83c3a90d294b8fd25fa2874212a9 Author: Rob Clark robdcl...@gmail.com Date: Fri May 30 11:37:03 2014 -0400 drm: add object property typ I asked for a check to make sure that we never leak an fb from the generic mode object lookup since those have completely different lifetime rules. Rob added it, but outside of the idr mutex, which means that our dereference of obj-type can already chase free'd memory. Somehow I didn't spot this, so fix this asap. Cc: Rob Clark robdcl...@gmail.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/drm_crtc.c | 6 +++--- drivers/gpu/drm/drm_fb_helper.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index f0a47907..853ab9cad071 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -429,6 +429,9 @@ static struct drm_mode_object *_object_find(struct drm_device *dev, if (!obj || (type != DRM_MODE_OBJECT_ANY obj-type != type) || (obj-id != id)) obj = NULL; + /* don't leak out unref'd fb's */ + if (obj (obj-type == DRM_MODE_OBJECT_FB)) + obj = NULL; mutex_unlock(dev-mode_config.idr_mutex); return obj; @@ -454,9 +457,6 @@ struct drm_mode_object *drm_mode_object_find(struct drm_device *dev, * function.*/ WARN_ON(type == DRM_MODE_OBJECT_FB); obj = _object_find(dev, id, type); - /* don't leak out unref'd fb's */ - if (obj (obj-type == DRM_MODE_OBJECT_FB)) - obj = NULL; return obj; } EXPORT_SYMBOL(drm_mode_object_find); diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index d5d8cea1a679..ff586ae3d92a 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -303,6 +303,7 @@ static bool restore_fbdev_mode(struct drm_fb_helper *fb_helper) } return error; } + /** * drm_fb_helper_restore_fbdev_mode - restore fbdev configuration * @fb_helper: fbcon to restore -- 2.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, This time in time! Just 32bit-pae fix from Hugh, semaphores fun from Chris and a fix for runtime pm cherry-picked from next. Paulo is still working on a fix for runtime pm when X does cursor fun when the display is off, but that one isn't ready yet. Cheers, Daniel The following changes since commit 9a3c4145af32125c5ee39c0272662b47307a8323: Linux 3.16-rc6 (2014-07-20 21:04:16 -0700) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/drm-intel-fixes-2014-07-24 for you to fetch changes up to eedd10f45bdcb2a5b2afa35f845e080c3bc984f2: drm/i915: Simplify i915_gem_release_all_mmaps() (2014-07-23 16:09:51 +0200) Chris Wilson (2): drm/i915: Reorder the semaphore deadlock check, again drm/i915: Simplify i915_gem_release_all_mmaps() Hugh Dickins (1): drm/i915: fix freeze with blank screen booting highmem drivers/gpu/drm/i915/i915_gem.c | 25 + drivers/gpu/drm/i915/i915_gem_render_state.c | 4 ++-- drivers/gpu/drm/i915/i915_irq.c | 11 --- 3 files changed, 15 insertions(+), 25 deletions(-) -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Fix race when checking for fb in the generic kms obj lookup
On Thu, Jul 24, 2014 at 09:54:27AM +0200, Daniel Vetter wrote: In my review of commit 98f75de40e9d83c3a90d294b8fd25fa2874212a9 Author: Rob Clark robdcl...@gmail.com Date: Fri May 30 11:37:03 2014 -0400 drm: add object property typ I asked for a check to make sure that we never leak an fb from the generic mode object lookup since those have completely different lifetime rules. Rob added it, but outside of the idr mutex, which means that our dereference of obj-type can already chase free'd memory. Somehow I didn't spot this, so fix this asap. Cc: Rob Clark robdcl...@gmail.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/drm_crtc.c | 6 +++--- drivers/gpu/drm/drm_fb_helper.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index f0a47907..853ab9cad071 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -429,6 +429,9 @@ static struct drm_mode_object *_object_find(struct drm_device *dev, if (!obj || (type != DRM_MODE_OBJECT_ANY obj-type != type) || (obj-id != id)) obj = NULL; + /* don't leak out unref'd fb's */ + if (obj (obj-type == DRM_MODE_OBJECT_FB)) + obj = NULL; - if (!obj || (type != DRM_MODE_OBJECT_ANY obj-type != type) || - (obj-id != id)) + if (obj obj-type != type type != DRM_MODE_OBJECT_ANY) + obj = NULL; + if (obj WARN_ON(obj-id != id)) + obj = NULL; + if (obj WARN_ON(obj-type == DRM_MODE_OBJECT_FB)) obj = NULL; To break the checks up into simple steps and show that they are unlikely errors? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] igt/gem_userptr_blits: Fix multi-threaded mm stress tester
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Tuesday, July 22, 2014 11:15 AM
To: Intel-gfx@lists.freedesktop.org
Cc: Tvrtko Ursulin; Ursulin, Tvrtko; Gore, Tim
Subject: [PATCH] igt/gem_userptr_blits: Fix multi-threaded mm stress tester
Two parts to the fix:
1. Do not use pthread_cancel since not available on Android.
2. Do not assert in the thread since that does not get propagated
to the process. Rather pass out any failures so we know test
did not work as expected.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Tim Gore tim.g...@intel.com
Reviewed-by: Tim Gore tim.g...@intel.com
Builds for Android now, and stress-mm test passes on linux. Fails for Android
but this is a different issue.
---
tests/gem_userptr_blits.c | 37 ++---
1 file changed, 26 insertions(+), 11 deletions(-)
diff --git a/tests/gem_userptr_blits.c b/tests/gem_userptr_blits.c index
2a52856..3277096 100644
--- a/tests/gem_userptr_blits.c
+++ b/tests/gem_userptr_blits.c
@@ -1137,21 +1137,32 @@ static void test_unmap_cycles(int fd, int
expected)
test_unmap(fd, expected);
}
+struct stress_thread_data {
+ unsigned int stop;
+ int exit_code;
+};
+
static void *mm_stress_thread(void *data) {
-void *ptr;
-int ret;
+ struct stress_thread_data *stdata = (struct stress_thread_data
*)data;
+ void *ptr;
+ int ret;
- for (;;) {
+ while (!stdata-stop) {
ptr = mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE,
MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
- igt_assert(ptr != MAP_FAILED);
+ if (ptr == MAP_FAILED) {
+ stdata-exit_code = -EFAULT;
+ break;
+ }
ret = munmap(ptr, PAGE_SIZE);
- igt_assert(ret == 0);
- pthread_testcancel();
-}
+ if (ret) {
+ stdata-exit_code = errno;
+ break;
+ }
+ }
-return NULL;
+ return NULL;
}
static void test_stress_mm(int fd)
@@ -1161,10 +1172,13 @@ static void test_stress_mm(int fd)
unsigned int loops = 10;
uint32_t handle;
void *ptr;
+ struct stress_thread_data stdata;
+
+ memset(stdata, 0, sizeof(stdata));
igt_assert(posix_memalign(ptr, PAGE_SIZE, PAGE_SIZE) == 0);
- ret = pthread_create(t, NULL, mm_stress_thread, NULL);
+ ret = pthread_create(t, NULL, mm_stress_thread, stdata);
igt_assert(ret == 0);
while (loops--) {
@@ -1176,10 +1190,11 @@ static void test_stress_mm(int fd)
free(ptr);
- ret = pthread_cancel(t);
- igt_assert(ret == 0);
+ stdata.stop = 1;
ret = pthread_join(t, NULL);
igt_assert(ret == 0);
+
+ igt_assert(stdata.exit_code == 0);
}
unsigned int total_ram;
--
1.9.3
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Re: [Intel-gfx] [PATCH] igt/gem_userptr_blits: Fix multi-threaded mm stress tester
On Thu, Jul 24, 2014 at 08:19:19AM +, Gore, Tim wrote: -Original Message- From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] Sent: Tuesday, July 22, 2014 11:15 AM To: Intel-gfx@lists.freedesktop.org Cc: Tvrtko Ursulin; Ursulin, Tvrtko; Gore, Tim Subject: [PATCH] igt/gem_userptr_blits: Fix multi-threaded mm stress tester Two parts to the fix: 1. Do not use pthread_cancel since not available on Android. 2. Do not assert in the thread since that does not get propagated to the process. Rather pass out any failures so we know test did not work as expected. Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com Cc: Tim Gore tim.g...@intel.com Reviewed-by: Tim Gore tim.g...@intel.com Pushed. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/8] lib: warn when attempting to run an unknown subtest
Looks fine to me
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Wednesday, July 23, 2014 11:58 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gore, Tim; daniel.vet...@ffwll.ch
Subject: [PATCH i-g-t 1/8] lib: warn when attempting to run an unknown
subtest
Signed-off-by: Thomas Wood thomas.w...@intel.com
Reviewed-by: Tim Gore tim.g...@intel.com
---
lib/igt_core.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c index b197932..5c20581 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -204,6 +204,7 @@ static unsigned int exit_handler_count;
/* subtests helpers */
static bool list_subtests = false;
static char *run_single_subtest = NULL;
+static bool run_single_subtest_found = false;
static const char *in_subtest = NULL;
static bool in_fixture = false;
static bool test_with_subtests = false; @@ -484,9 +485,14 @@ bool
__igt_run_subtest(const char *subtest_name)
return false;
}
- if (run_single_subtest
- strcmp(subtest_name, run_single_subtest) != 0)
- return false;
+ if (run_single_subtest) {
+ if (strcmp(subtest_name, run_single_subtest) != 0)
+ return false;
+ else
+ run_single_subtest_found = true;
+ }
+
+
if (skip_subtests_henceforth) {
printf(Subtest %s: %s\n, subtest_name, @@ -722,6
+728,12 @@ void igt_exit(void) {
igt_exit_called = true;
+ if (run_single_subtest !run_single_subtest_found) {
+ igt_warn(Unknown subtest: %s\n, run_single_subtest);
+ exit(-1);
+ }
+
+
if (igt_only_list_subtests())
exit(IGT_EXIT_SUCCESS);
--
1.9.3
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Re: [Intel-gfx] [PATCH i-g-t 2/8] tests: remove unused getopt header includes
Looks fine to me. -Original Message- From: Thomas Wood [mailto:thomas.w...@intel.com] Sent: Wednesday, July 23, 2014 11:58 AM To: intel-gfx@lists.freedesktop.org Cc: Gore, Tim; daniel.vet...@ffwll.ch Subject: [PATCH i-g-t 2/8] tests: remove unused getopt header includes Signed-off-by: Thomas Wood thomas.w...@intel.com Reviewed-by: Tim Gore tim.g...@intel.com --- lib/drmtest.c | 1 - lib/igt_aux.c | 1 - lib/rendercopy_gen6.c | 1 - lib/rendercopy_gen7.c | 1 - lib/rendercopy_gen8.c | 1 - lib/rendercopy_i830.c | 1 - lib/rendercopy_i915.c | 1 - tests/gem_media_fill.c | 1 - tests/gem_render_copy_redux.c | 1 - tests/gem_render_linear_blits.c | 1 - tests/gem_render_tiled_blits.c | 1 - tests/gem_wait_render_timeout.c | 1 - tests/kms_setmode.c | 1 - tests/pm_rps.c | 1 - 14 files changed, 14 deletions(-) diff --git a/lib/drmtest.c b/lib/drmtest.c index 7be2e40..f921f67 100644 --- a/lib/drmtest.c +++ b/lib/drmtest.c @@ -39,7 +39,6 @@ #include sys/mman.h #include signal.h #include pciaccess.h -#include getopt.h #include stdlib.h #include unistd.h #include sys/wait.h diff --git a/lib/igt_aux.c b/lib/igt_aux.c index 7b277be..0bcaa3b 100644 --- a/lib/igt_aux.c +++ b/lib/igt_aux.c @@ -39,7 +39,6 @@ #include sys/mman.h #include signal.h #include pciaccess.h -#include getopt.h #include stdlib.h #include unistd.h #include sys/wait.h diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c index 7b3104c..afe7562 100644 --- a/lib/rendercopy_gen6.c +++ b/lib/rendercopy_gen6.c @@ -9,7 +9,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h #include i915_drm.h #include drmtest.h diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c index 5131d8f..2932f1e 100644 --- a/lib/rendercopy_gen7.c +++ b/lib/rendercopy_gen7.c @@ -9,7 +9,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h #include i915_drm.h #include drmtest.h diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index a32871d..ff0b0c8 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -9,7 +9,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h #include i915_drm.h diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c index f0235a5..04215b1 100644 --- a/lib/rendercopy_i830.c +++ b/lib/rendercopy_i830.c @@ -8,7 +8,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h #include i915_drm.h #include drmtest.h diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c index 1acf9da..fc9583c 100644 --- a/lib/rendercopy_i915.c +++ b/lib/rendercopy_i915.c @@ -8,7 +8,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h #include i915_drm.h #include drmtest.h diff --git a/tests/gem_media_fill.c b/tests/gem_media_fill.c index db2380b..b06a556 100644 --- a/tests/gem_media_fill.c +++ b/tests/gem_media_fill.c @@ -41,7 +41,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h #include ioctl_wrappers.h #include drmtest.h diff --git a/tests/gem_render_copy_redux.c b/tests/gem_render_copy_redux.c index f711fdb..cb48aa7 100644 --- a/tests/gem_render_copy_redux.c +++ b/tests/gem_render_copy_redux.c @@ -43,7 +43,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h diff --git a/tests/gem_render_linear_blits.c b/tests/gem_render_linear_blits.c index ee99dea..28fd8c8 100644 --- a/tests/gem_render_linear_blits.c +++ b/tests/gem_render_linear_blits.c @@ -46,7 +46,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h diff --git a/tests/gem_render_tiled_blits.c b/tests/gem_render_tiled_blits.c index 3d83f7c..ea1d59d 100644 --- a/tests/gem_render_tiled_blits.c +++ b/tests/gem_render_tiled_blits.c @@ -42,7 +42,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h diff --git a/tests/gem_wait_render_timeout.c b/tests/gem_wait_render_timeout.c index a34c006..3afab9c 100644 --- a/tests/gem_wait_render_timeout.c +++ b/tests/gem_wait_render_timeout.c @@ -36,7 +36,6 @@ #include errno.h #include sys/stat.h #include sys/time.h -#include getopt.h #include drm.h diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c index 0b765a9..8762255 100644 --- a/tests/kms_setmode.c +++ b/tests/kms_setmode.c @@ -29,7 +29,6 @@ #include stdint.h #include unistd.h #include string.h -#include getopt.h #include sys/time.h #include drmtest.h diff --git a/tests/pm_rps.c b/tests/pm_rps.c index c1156a5..96fec99 100644 ---
Re: [Intel-gfx] [PATCH i-g-t 3/8] lib: move option parsing into common_init
Looks fine.
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Wednesday, July 23, 2014 11:58 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gore, Tim; daniel.vet...@ffwll.ch
Subject: [PATCH i-g-t 3/8] lib: move option parsing into common_init
Move option parsing into common_init so it can be shared between simple
tests and tests with subtests. This allows for more common command line
behaviour across all tests.
Signed-off-by: Thomas Wood thomas.w...@intel.com
Reviewed-by: Tim Gore tim.g...@intel.com
---
lib/igt_core.c | 118
-
1 file changed, 74 insertions(+), 44 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c index 5c20581..ee6f90c 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -291,30 +291,11 @@ static void oom_adjust_for_doom(void)
igt_assert(write(fd, always_kill, sizeof(always_kill)) ==
sizeof(always_kill)); }
-/**
- * igt_subtest_init_parse_opts:
- * @argc: argc from the test's main()
- * @argv: argv from the test's main()
- * @extra_short_opts: getopt_long() compliant list with additional short
options
- * @extra_long_opts: getopt_long() compliant list with additional long
options
- * @help_str: help string for the additional options
- * @extra_opt_handler: handler for the additional options
- *
- * This function handles the subtest related cmdline options and allows an
- * arbitrary set of additional options. This is useful for tests which have
- * additional knobs to tune when run manually like the number of rounds
execute
- * or the size of the allocated buffer objects.
- *
- * Tests without special needs should just use igt_subtest_init() or use
- * #igt_main directly instead of their own main() function.
- *
- * Returns: Forwards any option parsing errors from getopt_long.
- */
-int igt_subtest_init_parse_opts(int argc, char **argv,
- const char *extra_short_opts,
- struct option *extra_long_opts,
- const char *help_str,
- igt_opt_handler_t extra_opt_handler)
+static int common_init(int argc, char **argv,
+const char *extra_short_opts,
+struct option *extra_long_opts,
+const char *help_str,
+igt_opt_handler_t extra_opt_handler)
{
int c, option_index = 0;
static struct option long_options[] = { @@ -328,8 +309,18 @@ int
igt_subtest_init_parse_opts(int argc, char **argv,
int extra_opt_count;
int all_opt_count;
int ret = 0;
+ char *env = getenv(IGT_LOG_LEVEL);
- test_with_subtests = true;
+ if (env) {
+ if (strcmp(env, debug) == 0)
+ igt_log_level = IGT_LOG_DEBUG;
+ else if (strcmp(env, info) == 0)
+ igt_log_level = IGT_LOG_INFO;
+ else if (strcmp(env, warn) == 0)
+ igt_log_level = IGT_LOG_WARN;
+ else if (strcmp(env, none) == 0)
+ igt_log_level = IGT_LOG_NONE;
+ }
command_str = argv[0];
if (strrchr(command_str, '/'))
@@ -389,36 +380,70 @@ int igt_subtest_init_parse_opts(int argc, char
**argv,
}
}
- igt_install_exit_handler(check_igt_exit);
oom_adjust_for_doom();
out:
free(short_opts);
free(combined_opts);
+
+ /* exit immediately if this test has no subtests and a subtest or the
+ * list of subtests has been requested */
+ if (!test_with_subtests) {
+ if (run_single_subtest) {
+ igt_warn(Unknown subtest: %s\n,
run_single_subtest);
+ exit(-1);
+ }
+ if (list_subtests)
+ exit(-1);
+ }
+
+ if (ret 0)
+ /* exit with no error for -h/--help */
+ exit(ret == -1 ? 0 : ret);
+
print_version();
return ret;
}
-enum igt_log_level igt_log_level = IGT_LOG_INFO;
-static void common_init(void)
+/**
+ * igt_subtest_init_parse_opts:
+ * @argc: argc from the test's main()
+ * @argv: argv from the test's main()
+ * @extra_short_opts: getopt_long() compliant list with additional
+short options
+ * @extra_long_opts: getopt_long() compliant list with additional long
+options
+ * @help_str: help string for the additional options
+ * @extra_opt_handler: handler for the additional options
+ *
+ * This function handles the subtest related cmdline options and allows
+an
+ * arbitrary set of additional options. This is useful for tests which
+have
+ * additional knobs to tune when run manually like the number of rounds
+execute
+ * or the size of the allocated buffer objects.
+ *
+ * Tests without special needs should just use igt_subtest_init() or
+use
+ * #igt_main directly instead of their own main()
Re: [Intel-gfx] [PATCH i-g-t 4/8] lib: add igt_simple_init_parse_opts
Looks fine.
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Wednesday, July 23, 2014 11:58 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gore, Tim; daniel.vet...@ffwll.ch
Subject: [PATCH i-g-t 4/8] lib: add igt_simple_init_parse_opts
This function allows simple tests to register additional command line options.
Signed-off-by: Thomas Wood thomas.w...@intel.com
Reviewed-by: Tim Gore tim.g...@intel.com
---
lib/igt_core.c | 22 ++ lib/igt_core.h | 5 +
2 files changed, 27 insertions(+)
diff --git a/lib/igt_core.c b/lib/igt_core.c index ee6f90c..72c77e6 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -500,6 +500,28 @@ void igt_simple_init(int argc, char **argv)
optind = 1;
}
+/**
+ * igt_simple_init_parse_opts:
+ * @argc: argc from the test's main()
+ * @argv: argv from the test's main()
+ * @extra_short_opts: getopt_long() compliant list with additional
+short options
+ * @extra_long_opts: getopt_long() compliant list with additional long
+options
+ * @help_str: help string for the additional options
+ * @extra_opt_handler: handler for the additional options
+ *
+ * This initializes a simple test without any support for subtests and
+allows
+ * an arbitrary set of additional options.
+ */
+void igt_simple_init_parse_opts(int argc, char **argv,
+ const char *extra_short_opts,
+ struct option *extra_long_opts,
+ const char *help_str,
+ igt_opt_handler_t extra_opt_handler) {
+ common_init(argc, argv, extra_short_opts, extra_long_opts,
help_str,
+ extra_opt_handler);
+}
+
/*
* Note: Testcases which use these helpers MUST NOT output anything to
stdout
* outside of places protected by igt_run_subtest checks - the piglit diff
--git
a/lib/igt_core.h b/lib/igt_core.h index 6138487..408cf3a 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -162,6 +162,11 @@ bool igt_only_list_subtests(void);
static void igt_tokencat(__real_main, __LINE__)(void) \
void igt_simple_init(int argc, char **argv);
+void igt_simple_init_parse_opts(int argc, char **argv,
+ const char *extra_short_opts,
+ struct option *extra_long_opts,
+ const char *help_str,
+ igt_opt_handler_t extra_opt_handler);
/**
* igt_simple_main:
--
1.9.3
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Re: [Intel-gfx] [PATCH i-g-t 5/8] lib: don't ignore unknown options in multi-tests
Looks sensible.
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Wednesday, July 23, 2014 11:58 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gore, Tim; daniel.vet...@ffwll.ch
Subject: [PATCH i-g-t 5/8] lib: don't ignore unknown options in multi-tests
None of the current tests have additional options that might make use of any
unknown options and igt_subtest_init_parse_opts is available that integrates
additional option parsing.
Signed-off-by: Thomas Wood thomas.w...@intel.com
Reviewed-by: Tim Gore tim.g...@intel.com
---
lib/igt_core.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c index 72c77e6..0867c27 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -459,18 +459,7 @@ enum igt_log_level igt_log_level = IGT_LOG_INFO;
*/
void igt_subtest_init(int argc, char **argv) {
- int ret;
-
- /* supress getopt errors about unknown options */
- opterr = 0;
-
- ret = igt_subtest_init_parse_opts(argc, argv, NULL, NULL, NULL,
NULL);
- if (ret 0)
- /* exit with no error for -h/--help */
- exit(ret == -1 ? 0 : ret);
-
- /* reset opt parsing */
- optind = 1;
+ igt_subtest_init_parse_opts(argc, argv, NULL, NULL, NULL, NULL);
}
/**
--
1.9.3
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[Intel-gfx] [PATCH] drm: Fix race when checking for fb in the generic kms obj lookup
In my review of commit 98f75de40e9d83c3a90d294b8fd25fa2874212a9 Author: Rob Clark robdcl...@gmail.com Date: Fri May 30 11:37:03 2014 -0400 drm: add object property typ I asked for a check to make sure that we never leak an fb from the generic mode object lookup since those have completely different lifetime rules. Rob added it, but outside of the idr mutex, which means that our dereference of obj-type can already chase free'd memory. Somehow I didn't spot this, so fix this asap. v2: Simplify the conditionals as suggested by Chris. Cc: Rob Clark robdcl...@gmail.com Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/drm_crtc.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index f0a47907..d87df8836aa5 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -426,8 +426,12 @@ static struct drm_mode_object *_object_find(struct drm_device *dev, mutex_lock(dev-mode_config.idr_mutex); obj = idr_find(dev-mode_config.crtc_idr, id); - if (!obj || (type != DRM_MODE_OBJECT_ANY obj-type != type) || - (obj-id != id)) + if (obj type != DRM_MODE_OBJECT_ANY obj-type != type) + obj = NULL; + if (obj obj-id != id) + obj = NULL; + /* don't leak out unref'd fb's */ + if (obj (obj-type == DRM_MODE_OBJECT_FB)) obj = NULL; mutex_unlock(dev-mode_config.idr_mutex); @@ -454,9 +458,6 @@ struct drm_mode_object *drm_mode_object_find(struct drm_device *dev, * function.*/ WARN_ON(type == DRM_MODE_OBJECT_FB); obj = _object_find(dev, id, type); - /* don't leak out unref'd fb's */ - if (obj (obj-type == DRM_MODE_OBJECT_FB)) - obj = NULL; return obj; } EXPORT_SYMBOL(drm_mode_object_find); -- 2.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 6/8] tests: convert simple tests to use igt_simple_init_parse_opts
There is a problem here with the -r option in gem_seqno_wrap, as this conflicts
with the --run-subtest option in common_init. This is a general issue with this
method of splitting the responsibility for parsing the command line. As the
common command line options defined in common_init (--run-subtest etc)
do not support short options, a simple solution might be to use some non
printing characters for their getopt return codes, eg
{list-subtests, 0, 0, '\x0c'},
This way, individual tests are unlikely to clash with these. (I chose '\x0c'
since
'l' is the twelfth character ?) I tried this locally and it seemed to work.
Tim
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Wednesday, July 23, 2014 11:58 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gore, Tim; daniel.vet...@ffwll.ch
Subject: [PATCH i-g-t 6/8] tests: convert simple tests to use
igt_simple_init_parse_opts
Convert simple tests to use igt_simple_init_parse_opts if they require extra
options.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_core.h | 1 +
tests/gem_ctx_basic.c | 20 +++--
tests/gem_render_copy.c | 25 +--- tests/gem_seqno_wrap.c | 82
+++--
tests/gem_stress.c | 105 ++
--
5 files changed, 98 insertions(+), 135 deletions(-)
diff --git a/lib/igt_core.h b/lib/igt_core.h index 408cf3a..b19a897 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -36,6 +36,7 @@
#include string.h
#include sys/types.h
#include stdarg.h
+#include getopt.h
/**
* IGT_EXIT_TIMEOUT:
diff --git a/tests/gem_ctx_basic.c b/tests/gem_ctx_basic.c index
a2464fd..a0bec60 100644
--- a/tests/gem_ctx_basic.c
+++ b/tests/gem_ctx_basic.c
@@ -39,7 +39,6 @@
#include errno.h
#include sys/stat.h
#include sys/time.h
-#include getopt.h
#include drm.h
#include ioctl_wrappers.h
#include drmtest.h
@@ -119,11 +118,9 @@ static void *work(void *arg)
pthread_exit(NULL);
}
-static void parse(int argc, char *argv[])
+static int opt_handler(int opt, int opt_index)
{
- int opt;
- while ((opt = getopt(argc, argv, i:c:n:muh?)) != -1) {
- switch (opt) {
+ switch (opt) {
case 'i':
iter = atoi(optarg);
break;
@@ -136,20 +133,17 @@ static void parse(int argc, char *argv[])
case 'u':
uncontexted = 1;
break;
- case 'h':
- case '?':
- default:
- igt_success();
- break;
- }
}
+
+ return 0;
}
int main(int argc, char *argv[])
{
int i;
- igt_simple_init(argc, argv);
+ igt_simple_init_parse_opts(argc, argv, i:c:n:mu, NULL, NULL,
+opt_handler);
fd = drm_open_any_render();
devid = intel_get_drm_devid(fd);
@@ -159,8 +153,6 @@ int main(int argc, char *argv[])
iter = 4;
}
- parse(argc, argv);
-
threads = calloc(num_contexts, sizeof(*threads));
for (i = 0; i num_contexts; i++)
diff --git a/tests/gem_render_copy.c b/tests/gem_render_copy.c index
76ba40e..6ff0c77 100644
--- a/tests/gem_render_copy.c
+++ b/tests/gem_render_copy.c
@@ -41,7 +41,6 @@
#include errno.h
#include sys/stat.h
#include sys/time.h
-#include getopt.h
#include drm.h
@@ -67,6 +66,7 @@ typedef struct {
drm_intel_bufmgr *bufmgr;
uint32_t linear[WIDTH * HEIGHT];
} data_t;
+static int opt_dump_png = false;
static void scratch_buf_write_to_png(struct igt_buf *buf, const char
*filename) { @@ -117,27 +117,24 @@ scratch_buf_check(data_t *data,
struct igt_buf *buf, int x, int y,
color, val, x, y);
}
+static int opt_handler(int opt, int opt_index) {
+ if (opt == 'd') {
+ opt_dump_png = true;
+ }
+
+ return 0;
+}
+
int main(int argc, char **argv)
{
data_t data = {0, };
struct intel_batchbuffer *batch = NULL;
struct igt_buf src, dst;
igt_render_copyfunc_t render_copy = NULL;
- int opt;
- int opt_dump_png = false;
int opt_dump_aub = igt_aub_dump_enabled();
- igt_simple_init(argc, argv);
-
- while ((opt = getopt(argc, argv, d)) != -1) {
- switch (opt) {
- case 'd':
- opt_dump_png = true;
- break;
- default:
- break;
- }
- }
+ igt_simple_init_parse_opts(argc, argv, d, NULL, NULL,
opt_handler);
igt_fixture {
data.drm_fd = drm_open_any_render();
diff --git a/tests/gem_seqno_wrap.c b/tests/gem_seqno_wrap.c index
0fa722d..3a40860 100644
--- a/tests/gem_seqno_wrap.c
+++ b/tests/gem_seqno_wrap.c
@@ -38,7 +38,6 @@
#include sys/types.h
Re: [Intel-gfx] [PATCH i-g-t 7/8] lib: always warn about unknown options
Yes, this looks sensible.
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Wednesday, July 23, 2014 11:58 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gore, Tim; daniel.vet...@ffwll.ch
Subject: [PATCH i-g-t 7/8] lib: always warn about unknown options
All tests can now register extra options, so there should not be any unknown
options.
Signed-off-by: Thomas Wood thomas.w...@intel.com
Reviewed-by: Tim Gore tim.g...@intel.com
---
lib/igt_core.c | 27 ---
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c index 0867c27..42b22fc 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -362,17 +362,9 @@ static int common_init(int argc, char **argv,
ret = -1;
goto out;
case '?':
- if (opterr) {
- print_usage(command_str, help_str, true);
- ret = -2;
- goto out;
- }
- /*
- * Just ignore the error, since the unknown argument
- * can be something the caller understands and will
- * parse by doing a second getopt scanning.
- */
- break;
+ print_usage(command_str, help_str, true);
+ ret = -2;
+ goto out;
default:
ret = extra_opt_handler(c, option_index);
if (ret)
@@ -475,18 +467,7 @@ void igt_subtest_init(int argc, char **argv)
*/
void igt_simple_init(int argc, char **argv) {
- int ret;
-
- /* supress getopt errors about unknown options */
- opterr = 0;
-
- ret = common_init(argc, argv, NULL, NULL, NULL, NULL);
- if (ret 0)
- /* exit with no error for -h/--help */
- exit(ret == -1 ? 0 : ret);
-
- /* reset opt parsing */
- optind = 1;
+ common_init(argc, argv, NULL, NULL, NULL, NULL);
}
/**
--
1.9.3
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Re: [Intel-gfx] [PATCH i-g-t 8/8] lib: add a command line option to enable debug output in tests
See my comment on patch 6. --debug returns 'd' from getopt, which can conflict
with the short options for some tests, such as gem_render_copy and
gem_seqn0_wrap.
This problem also exists for the --run-subtest.
Tim
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Wednesday, July 23, 2014 11:58 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gore, Tim; daniel.vet...@ffwll.ch
Subject: [PATCH i-g-t 8/8] lib: add a command line option to enable debug
output in tests
Add --debug as a common command line option for all tests to enable debug
output.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_core.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c index 42b22fc..d90e6bb 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -276,7 +276,9 @@ static void print_usage(const char *command_str,
const char *help_str,
fprintf(f, Usage: %s [OPTIONS]\n
--list-subtests\n
- --run-subtest pattern\n, command_str);
+ --run-subtest pattern\n
+ --debug\n
+ --help\n, command_str);
if (help_str)
fprintf(f, %s\n, help_str);
}
@@ -301,6 +303,7 @@ static int common_init(int argc, char **argv,
static struct option long_options[] = {
{list-subtests, 0, 0, 'l'},
{run-subtest, 1, 0, 'r'},
+ {debug, 0, 0, 'd'},
{help, 0, 0, 'h'},
};
const char *command_str;
@@ -349,6 +352,9 @@ static int common_init(int argc, char **argv,
while ((c = getopt_long(argc, argv, short_opts, combined_opts,
option_index)) != -1) {
switch(c) {
+ case 'd':
+ igt_log_level = IGT_LOG_DEBUG;
+ break;
case 'l':
if (!run_single_subtest)
list_subtests = true;
--
1.9.3
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Re: [Intel-gfx] WAs in init_clock_gating?
On 07/07/2014 22:24, Daniel Vetter wrote: On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes jbar...@virtuousgeek.org wrote: I don't think it's unreasonable to use a macro that checks a global list for whether to apply a given WA. They'll be scattered all over, but at least it'll be easy to see: 1) whether we implement a given workaround and 2) which platforms steppings it applies to based on the table. Oh, I agree it's not unreasonable. But I'm kinda begging for the simple solution since months (years?) and haven't gotten it, while still getting a steady stream of bug reports and issues. So I've readjusted my expectations ;-) If someone delivers the real deal I'll certainly won't reject it. -Daniel I am moving bdw workarounds from clock_gating fn to render ring init fn and testing this before and after gpu reset. One of the workaround is to disable STC optimization, reg CACHE_MODE_1 bit6 set to 1. I observed that some times after boot this gets reset to 0 (default value) even after applying workarounds; other than workarounds no one else seems to write to this function. Any ideas about this behaviour? regards Arun ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] igt_core: Inject subtest message into dmesg
One of the side-effects we test for are kernel oops and knowing the
guilty subtest can help speed up debugging. We can write to /dev/kmsg to
inject messages into dmesg, so let's do so before the start of every
test.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
lib/igt_core.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index b0800e8..deaf145 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -269,8 +269,9 @@ static void print_version(void)
uts.sysname, uts.release, uts.machine);
}
-static void print_usage(const char *command_str, const char *help_str,
- bool output_on_stderr)
+static const char *command_str;
+
+static void print_usage(const char *help_str, bool output_on_stderr)
{
FILE *f = output_on_stderr ? stderr : stdout;
@@ -306,7 +307,6 @@ static int common_init(int argc, char **argv,
{debug, 0, 0, 'd'},
{help, 0, 0, 'h'},
};
- const char *command_str;
char *short_opts;
struct option *combined_opts;
int extra_opt_count;
@@ -364,11 +364,11 @@ static int common_init(int argc, char **argv,
run_single_subtest = strdup(optarg);
break;
case 'h':
- print_usage(command_str, help_str, false);
+ print_usage(help_str, false);
ret = -1;
goto out;
case '?':
- print_usage(command_str, help_str, true);
+ print_usage(help_str, true);
ret = -2;
goto out;
default:
@@ -498,6 +498,23 @@ void igt_simple_init_parse_opts(int argc, char **argv,
extra_opt_handler);
}
+__attribute__((format(printf, 2, 3)))
+static void echo(const char *path, const char *format, ...)
+{
+ va_list ap;
+ FILE *file;
+
+ file = fopen(path, w);
+ if (file == NULL)
+ return;
+
+ va_start(ap, format);
+ vfprintf(file, format, ap);
+ va_end(ap);
+
+ fclose(file);
+}
+
/*
* Note: Testcases which use these helpers MUST NOT output anything to stdout
* outside of places protected by igt_run_subtest checks - the piglit
@@ -529,6 +546,8 @@ bool __igt_run_subtest(const char *subtest_name)
return false;
}
+ echo(/dev/kmsg, %s: starting subtest %s\n, command_str,
subtest_name);
+
return (in_subtest = subtest_name);
}
--
1.9.1
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[Intel-gfx] [PATCH] drm/i915/userptr: Keep spin_lock/unlock in the same block
Move the code around in order to acquire and release the spinlock in the
same function and in the same block. This keeps static analysers happy
and the reader sane.
Suggested-by: Julia Lawall julia.law...@lip6.fr
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Julia Lawall julia.law...@lip6.fr
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 12358fd..4ef5a92 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -96,10 +96,10 @@ static unsigned long cancel_userptr(struct
drm_i915_gem_object *obj)
return end;
}
-static void invalidate_range__linear(struct i915_mmu_notifier *mn,
-struct mm_struct *mm,
-unsigned long start,
-unsigned long end)
+static void *invalidate_range__linear(struct i915_mmu_notifier *mn,
+ struct mm_struct *mm,
+ unsigned long start,
+ unsigned long end)
{
struct i915_mmu_object *mo;
unsigned long serial;
@@ -123,7 +123,7 @@ restart:
goto restart;
}
- spin_unlock(mn-lock);
+ return NULL;
}
static void i915_gem_userptr_mn_invalidate_range_start(struct mmu_notifier
*_mn,
@@ -138,13 +138,12 @@ static void
i915_gem_userptr_mn_invalidate_range_start(struct mmu_notifier *_mn,
end--; /* interval ranges are inclusive, but invalidate range is
exclusive */
while (next end) {
- struct drm_i915_gem_object *obj;
+ struct drm_i915_gem_object *obj = NULL;
- obj = NULL;
spin_lock(mn-lock);
if (mn-has_linear)
- return invalidate_range__linear(mn, mm, start, end);
- if (serial == mn-serial)
+ it = invalidate_range__linear(mn, mm, start, end);
+ else if (serial == mn-serial)
it = interval_tree_iter_next(it, next, end);
else
it = interval_tree_iter_first(mn-objects, start, end);
--
1.9.1
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Re: [Intel-gfx] WAs in init_clock_gating?
On Thu, Jul 24, 2014 at 11:43:11AM +0100, Siluvery, Arun wrote: On 07/07/2014 22:24, Daniel Vetter wrote: On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes jbar...@virtuousgeek.org wrote: I don't think it's unreasonable to use a macro that checks a global list for whether to apply a given WA. They'll be scattered all over, but at least it'll be easy to see: 1) whether we implement a given workaround and 2) which platforms steppings it applies to based on the table. Oh, I agree it's not unreasonable. But I'm kinda begging for the simple solution since months (years?) and haven't gotten it, while still getting a steady stream of bug reports and issues. So I've readjusted my expectations ;-) If someone delivers the real deal I'll certainly won't reject it. -Daniel I am moving bdw workarounds from clock_gating fn to render ring init fn and testing this before and after gpu reset. Testing = with an igt? Because I'll ask for this ;-) One of the workaround is to disable STC optimization, reg CACHE_MODE_1 bit6 set to 1. I observed that some times after boot this gets reset to 0 (default value) even after applying workarounds; other than workarounds no one else seems to write to this function. Any ideas about this behaviour? gpu init tends to do this, since clock_gating is run before that. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] igt_core: Inject subtest message into dmesg
On Thu, Jul 24, 2014 at 12:48:33PM +0100, Chris Wilson wrote:
One of the side-effects we test for are kernel oops and knowing the
guilty subtest can help speed up debugging. We can write to /dev/kmsg to
inject messages into dmesg, so let's do so before the start of every
test.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Should we change proc-comm too? Would help with the oops printing ... Ack
on the patch itself.
-Daniel
---
lib/igt_core.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index b0800e8..deaf145 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -269,8 +269,9 @@ static void print_version(void)
uts.sysname, uts.release, uts.machine);
}
-static void print_usage(const char *command_str, const char *help_str,
- bool output_on_stderr)
+static const char *command_str;
+
+static void print_usage(const char *help_str, bool output_on_stderr)
{
FILE *f = output_on_stderr ? stderr : stdout;
@@ -306,7 +307,6 @@ static int common_init(int argc, char **argv,
{debug, 0, 0, 'd'},
{help, 0, 0, 'h'},
};
- const char *command_str;
char *short_opts;
struct option *combined_opts;
int extra_opt_count;
@@ -364,11 +364,11 @@ static int common_init(int argc, char **argv,
run_single_subtest = strdup(optarg);
break;
case 'h':
- print_usage(command_str, help_str, false);
+ print_usage(help_str, false);
ret = -1;
goto out;
case '?':
- print_usage(command_str, help_str, true);
+ print_usage(help_str, true);
ret = -2;
goto out;
default:
@@ -498,6 +498,23 @@ void igt_simple_init_parse_opts(int argc, char **argv,
extra_opt_handler);
}
+__attribute__((format(printf, 2, 3)))
+static void echo(const char *path, const char *format, ...)
+{
+ va_list ap;
+ FILE *file;
+
+ file = fopen(path, w);
+ if (file == NULL)
+ return;
+
+ va_start(ap, format);
+ vfprintf(file, format, ap);
+ va_end(ap);
+
+ fclose(file);
+}
+
/*
* Note: Testcases which use these helpers MUST NOT output anything to stdout
* outside of places protected by igt_run_subtest checks - the piglit
@@ -529,6 +546,8 @@ bool __igt_run_subtest(const char *subtest_name)
return false;
}
+ echo(/dev/kmsg, %s: starting subtest %s\n, command_str,
subtest_name);
+
return (in_subtest = subtest_name);
}
--
1.9.1
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Re: [Intel-gfx] WAs in init_clock_gating?
On 24/07/2014 13:33, Daniel Vetter wrote: On Thu, Jul 24, 2014 at 11:43:11AM +0100, Siluvery, Arun wrote: On 07/07/2014 22:24, Daniel Vetter wrote: On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes jbar...@virtuousgeek.org wrote: I don't think it's unreasonable to use a macro that checks a global list for whether to apply a given WA. They'll be scattered all over, but at least it'll be easy to see: 1) whether we implement a given workaround and 2) which platforms steppings it applies to based on the table. Oh, I agree it's not unreasonable. But I'm kinda begging for the simple solution since months (years?) and haven't gotten it, while still getting a steady stream of bug reports and issues. So I've readjusted my expectations ;-) If someone delivers the real deal I'll certainly won't reject it. -Daniel I am moving bdw workarounds from clock_gating fn to render ring init fn and testing this before and after gpu reset. Testing = with an igt? Because I'll ask for this ;-) Yes, triggering gpu reset with igt, at the moment the test fails because of this register. One of the workaround is to disable STC optimization, reg CACHE_MODE_1 bit6 set to 1. I observed that some times after boot this gets reset to 0 (default value) even after applying workarounds; other than workarounds no one else seems to write to this function. Any ideas about this behaviour? gpu init tends to do this, since clock_gating is run before that. thanks, I will take a look. regards Arun -Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] igt_core: Inject subtest message into dmesg
On 24 July 2014 13:36, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Jul 24, 2014 at 12:48:33PM +0100, Chris Wilson wrote:
One of the side-effects we test for are kernel oops and knowing the
guilty subtest can help speed up debugging. We can write to /dev/kmsg to
inject messages into dmesg, so let's do so before the start of every
test.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Should we change proc-comm too? Would help with the oops printing ... Ack
on the patch itself.
It should also make sure that the log level is appropriate so that the
Piglit dmesg capture isn't triggered accidentally.
Would it be useful to include this in simple tests (tests without
subtests) as well?
-Daniel
---
lib/igt_core.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index b0800e8..deaf145 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -269,8 +269,9 @@ static void print_version(void)
uts.sysname, uts.release, uts.machine);
}
-static void print_usage(const char *command_str, const char *help_str,
- bool output_on_stderr)
+static const char *command_str;
+
+static void print_usage(const char *help_str, bool output_on_stderr)
{
FILE *f = output_on_stderr ? stderr : stdout;
@@ -306,7 +307,6 @@ static int common_init(int argc, char **argv,
{debug, 0, 0, 'd'},
{help, 0, 0, 'h'},
};
- const char *command_str;
char *short_opts;
struct option *combined_opts;
int extra_opt_count;
@@ -364,11 +364,11 @@ static int common_init(int argc, char **argv,
run_single_subtest = strdup(optarg);
break;
case 'h':
- print_usage(command_str, help_str, false);
+ print_usage(help_str, false);
ret = -1;
goto out;
case '?':
- print_usage(command_str, help_str, true);
+ print_usage(help_str, true);
ret = -2;
goto out;
default:
@@ -498,6 +498,23 @@ void igt_simple_init_parse_opts(int argc, char **argv,
extra_opt_handler);
}
+__attribute__((format(printf, 2, 3)))
+static void echo(const char *path, const char *format, ...)
+{
+ va_list ap;
+ FILE *file;
+
+ file = fopen(path, w);
+ if (file == NULL)
+ return;
+
+ va_start(ap, format);
+ vfprintf(file, format, ap);
+ va_end(ap);
+
+ fclose(file);
+}
+
/*
* Note: Testcases which use these helpers MUST NOT output anything to
stdout
* outside of places protected by igt_run_subtest checks - the piglit
@@ -529,6 +546,8 @@ bool __igt_run_subtest(const char *subtest_name)
return false;
}
+ echo(/dev/kmsg, %s: starting subtest %s\n, command_str,
subtest_name);
+
return (in_subtest = subtest_name);
}
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915/userptr: Keep spin_lock/unlock in the same block
All of the NULL tests are a bit complicated but since they are there
anyway, I guess it is reasonable to take advantage of them.
julia
On Thu, 24 Jul 2014, Chris Wilson wrote:
Move the code around in order to acquire and release the spinlock in the
same function and in the same block. This keeps static analysers happy
and the reader sane.
Suggested-by: Julia Lawall julia.law...@lip6.fr
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Julia Lawall julia.law...@lip6.fr
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 12358fd..4ef5a92 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -96,10 +96,10 @@ static unsigned long cancel_userptr(struct
drm_i915_gem_object *obj)
return end;
}
-static void invalidate_range__linear(struct i915_mmu_notifier *mn,
- struct mm_struct *mm,
- unsigned long start,
- unsigned long end)
+static void *invalidate_range__linear(struct i915_mmu_notifier *mn,
+ struct mm_struct *mm,
+ unsigned long start,
+ unsigned long end)
{
struct i915_mmu_object *mo;
unsigned long serial;
@@ -123,7 +123,7 @@ restart:
goto restart;
}
- spin_unlock(mn-lock);
+ return NULL;
}
static void i915_gem_userptr_mn_invalidate_range_start(struct mmu_notifier
*_mn,
@@ -138,13 +138,12 @@ static void
i915_gem_userptr_mn_invalidate_range_start(struct mmu_notifier *_mn,
end--; /* interval ranges are inclusive, but invalidate range is
exclusive */
while (next end) {
- struct drm_i915_gem_object *obj;
+ struct drm_i915_gem_object *obj = NULL;
- obj = NULL;
spin_lock(mn-lock);
if (mn-has_linear)
- return invalidate_range__linear(mn, mm, start, end);
- if (serial == mn-serial)
+ it = invalidate_range__linear(mn, mm, start, end);
+ else if (serial == mn-serial)
it = interval_tree_iter_next(it, next, end);
else
it = interval_tree_iter_first(mn-objects, start, end);
--
1.9.1
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[Intel-gfx] [PATCH] drm: Unlink dead file_priv from list of active files first
In order to prevent external observers walking the list of open DRM files from seeing an invalid drm_file_private in the process of being torndown, the first operation we need to take is to unlink the drm_file_private from that list. general protection fault: [#1] PREEMPT SMP Modules linked in: i915 i2c_algo_bit drm_kms_helper drm lpc_ich mfd_core nls_iso8859_1 i2c_hid video hid_generic usbhid hid e1000e ahci ptp libahci pps_core CPU: 3 PID: 8220 Comm: cat Not tainted 3.16.0-rc6+ #4 Hardware name: Intel Corporation Shark Bay Client platform/WhiteTip Mountain 1, BIOS HSWLPTU1.86C.0119.R00.1303230105 03/23/2013 task: 8800219642c0 ti: 880047024000 task.ti: 880047024000 RIP: 0010:[a0137c70] [a0137c70] per_file_stats+0x110/0x160 [i915] RSP: 0018:880047027d48 EFLAGS: 00010246 RAX: 6b6b6b6b6b6b6b6b RBX: 880047027e30 RCX: RDX: 0001 RSI: RDI: 88003a05cd00 RBP: 880047027d58 R08: 0001 R09: R10: 8800219642c0 R11: R12: 88003a05cd00 R13: R14: 88003a05cd00 R15: 880047027d88 FS: 7f5f73a13740() GS:88014e38() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 023ff038 CR3: 21a4b000 CR4: 001407e0 Stack: 0001 880047027dc8 813438e4 880047027e30 a0137b60 880021a8af58 880021a8f1a0 8800a2061fb0 8800a2062048 8800a2061fb0 8800a1e23478 Call Trace: [813438e4] idr_for_each+0xf4/0x180 [a0137b60] ? i915_gem_stolen_list_info+0x1f0/0x1f0 [i915] [a013a17a] i915_gem_object_info+0x5ca/0x6a0 [i915] [81193ec5] seq_read+0xf5/0x3a0 [8116d950] vfs_read+0x90/0x150 [8116e509] SyS_read+0x49/0xb0 [815d8622] tracesys+0xd0/0xd5 Code: 01 00 00 49 39 84 24 08 01 00 00 74 55 49 8b 84 24 b8 00 00 00 48 01 43 18 31 c0 5b 41 5c 5d c3 0f 1f 00 49 8b 44 24 08 4c 89 e7 48 8b 70 28 48 81 c6 48 80 00 00 e8 80 14 01 00 84 c0 74 bc 49 RIP [a0137c70] per_file_stats+0x110/0x160 [i915] RSP 880047027d48 Reported-by: Ursulin, Tvrtko tvrtko.ursu...@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81712 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Ursulin, Tvrtko tvrtko.ursu...@intel.com --- drivers/gpu/drm/drm_fops.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index a0c63cf..aff8217 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -416,6 +416,10 @@ int drm_release(struct inode *inode, struct file *filp) DRM_DEBUG(open_count = %d\n, dev-open_count); + mutex_lock(dev-struct_mutex); + list_del(file_priv-lhead); + mutex_unlock(dev-struct_mutex); + if (dev-driver-preclose) dev-driver-preclose(dev, file_priv); @@ -509,10 +513,6 @@ int drm_release(struct inode *inode, struct file *filp) file_priv-is_master = 0; mutex_unlock(dev-master_mutex); - mutex_lock(dev-struct_mutex); - list_del(file_priv-lhead); - mutex_unlock(dev-struct_mutex); - if (dev-driver-postclose) dev-driver-postclose(dev, file_priv); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Unlink dead file_priv from list of active files first
Hi On Thu, Jul 24, 2014 at 3:23 PM, Chris Wilson ch...@chris-wilson.co.uk wrote: In order to prevent external observers walking the list of open DRM files from seeing an invalid drm_file_private in the process of being torndown, the first operation we need to take is to unlink the drm_file_private from that list. general protection fault: [#1] PREEMPT SMP Modules linked in: i915 i2c_algo_bit drm_kms_helper drm lpc_ich mfd_core nls_iso8859_1 i2c_hid video hid_generic usbhid hid e1000e ahci ptp libahci pps_core CPU: 3 PID: 8220 Comm: cat Not tainted 3.16.0-rc6+ #4 Hardware name: Intel Corporation Shark Bay Client platform/WhiteTip Mountain 1, BIOS HSWLPTU1.86C.0119.R00.1303230105 03/23/2013 task: 8800219642c0 ti: 880047024000 task.ti: 880047024000 RIP: 0010:[a0137c70] [a0137c70] per_file_stats+0x110/0x160 [i915] RSP: 0018:880047027d48 EFLAGS: 00010246 RAX: 6b6b6b6b6b6b6b6b RBX: 880047027e30 RCX: RDX: 0001 RSI: RDI: 88003a05cd00 RBP: 880047027d58 R08: 0001 R09: R10: 8800219642c0 R11: R12: 88003a05cd00 R13: R14: 88003a05cd00 R15: 880047027d88 FS: 7f5f73a13740() GS:88014e38() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 023ff038 CR3: 21a4b000 CR4: 001407e0 Stack: 0001 880047027dc8 813438e4 880047027e30 a0137b60 880021a8af58 880021a8f1a0 8800a2061fb0 8800a2062048 8800a2061fb0 8800a1e23478 Call Trace: [813438e4] idr_for_each+0xf4/0x180 [a0137b60] ? i915_gem_stolen_list_info+0x1f0/0x1f0 [i915] [a013a17a] i915_gem_object_info+0x5ca/0x6a0 [i915] [81193ec5] seq_read+0xf5/0x3a0 [8116d950] vfs_read+0x90/0x150 [8116e509] SyS_read+0x49/0xb0 [815d8622] tracesys+0xd0/0xd5 Code: 01 00 00 49 39 84 24 08 01 00 00 74 55 49 8b 84 24 b8 00 00 00 48 01 43 18 31 c0 5b 41 5c 5d c3 0f 1f 00 49 8b 44 24 08 4c 89 e7 48 8b 70 28 48 81 c6 48 80 00 00 e8 80 14 01 00 84 c0 74 bc 49 RIP [a0137c70] per_file_stats+0x110/0x160 [i915] RSP 880047027d48 Reported-by: Ursulin, Tvrtko tvrtko.ursu...@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81712 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Ursulin, Tvrtko tvrtko.ursu...@intel.com I have the same change in my local drm_file cleanup. This is: Reviewed-by: David Herrmann dh.herrm...@gmail.com Thanks David --- drivers/gpu/drm/drm_fops.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index a0c63cf..aff8217 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -416,6 +416,10 @@ int drm_release(struct inode *inode, struct file *filp) DRM_DEBUG(open_count = %d\n, dev-open_count); + mutex_lock(dev-struct_mutex); + list_del(file_priv-lhead); + mutex_unlock(dev-struct_mutex); + if (dev-driver-preclose) dev-driver-preclose(dev, file_priv); @@ -509,10 +513,6 @@ int drm_release(struct inode *inode, struct file *filp) file_priv-is_master = 0; mutex_unlock(dev-master_mutex); - mutex_lock(dev-struct_mutex); - list_del(file_priv-lhead); - mutex_unlock(dev-struct_mutex); - if (dev-driver-postclose) dev-driver-postclose(dev, file_priv); -- 1.9.1 ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] intel-gpu-tools: add sys/wait.h to pm_rps.c
From: Tim Gore tim.g...@intel.com commit 745945546f7366a413a3a51a37f90caa3a227b1d breaks the build under Android because some of the macros used in pm_rps.c are defined in sys/wait.h which is not included. Signed-off-by: Tim Gore tim.g...@intel.com --- tests/pm_rps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/pm_rps.c b/tests/pm_rps.c index 8593e36..5264436 100644 --- a/tests/pm_rps.c +++ b/tests/pm_rps.c @@ -34,6 +34,7 @@ #include fcntl.h #include signal.h #include errno.h +#include sys/wait.h #include drmtest.h #include intel_io.h -- 1.9.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] igt_core: Inject subtest message into dmesg
On Thu, Jul 24, 2014 at 02:03:01PM +0100, Thomas Wood wrote: On 24 July 2014 13:36, Daniel Vetter dan...@ffwll.ch wrote: On Thu, Jul 24, 2014 at 12:48:33PM +0100, Chris Wilson wrote: One of the side-effects we test for are kernel oops and knowing the guilty subtest can help speed up debugging. We can write to /dev/kmsg to inject messages into dmesg, so let's do so before the start of every test. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Should we change proc-comm too? Would help with the oops printing ... Ack on the patch itself. It should also make sure that the log level is appropriate so that the Piglit dmesg capture isn't triggered accidentally. I found out how to set the log-level, so choose KERN_INFO which should be sufficient. Would it be useful to include this in simple tests (tests without subtests) as well? Definitely. Is there a way to do that automatically or do we need to adjust the tests themselves? I was thinkg we could add a kmsg() to common_init() to capture those. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] igt_core: Inject subtest message into dmesg
On Thu, Jul 24, 2014 at 02:58:08PM +0100, Chris Wilson wrote: On Thu, Jul 24, 2014 at 02:03:01PM +0100, Thomas Wood wrote: On 24 July 2014 13:36, Daniel Vetter dan...@ffwll.ch wrote: On Thu, Jul 24, 2014 at 12:48:33PM +0100, Chris Wilson wrote: One of the side-effects we test for are kernel oops and knowing the guilty subtest can help speed up debugging. We can write to /dev/kmsg to inject messages into dmesg, so let's do so before the start of every test. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Should we change proc-comm too? Would help with the oops printing ... Ack on the patch itself. It should also make sure that the log level is appropriate so that the Piglit dmesg capture isn't triggered accidentally. I found out how to set the log-level, so choose KERN_INFO which should be sufficient. Would it be useful to include this in simple tests (tests without subtests) as well? Definitely. Is there a way to do that automatically or do we need to adjust the tests themselves? I was thinkg we could add a kmsg() to common_init() to capture those. common_init kmsg'ing the test binary should be good. That should help in lining up any test setup work that's done before the first test starts, too. So useful even with subtests. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix crash when failing to parse MIPI VBT
From: Rafael Barbalho rafael.barba...@intel.com This particular nasty presented itself while trying to register the intelfb device (intel_fbdev.c). During the process of registering the device the driver will disable the crtc via i9xx_crtc_disable. These will also disable the panel using the generic mipi panel functions in dsi_mod_vbt_generic.c. The stale MIPI generic data sequence pointers would cause a crash within those functions. However, all of this is happening while console_lock is held from do_register_framebuffer inside fbcon.c. Which means that you got kernel log and just the device appearing to reboot/hang for no apparent reason. The fault started from the FB_EVENT_FB_REGISTERED event using the fb_notifier_call_chain call in fbcon.c. Cc: Shobhit Kumar shobhit.ku...@intel.com Signed-off-by: Rafael Barbalho rafael.barba...@intel.com --- drivers/gpu/drm/i915/intel_bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 608ed30..a669550 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -878,7 +878,7 @@ err: /* error during parsing so set all pointers to null * because of partial parsing */ - memset(dev_priv-vbt.dsi.sequence, 0, MIPI_SEQ_MAX); + memset(dev_priv-vbt.dsi.sequence, 0, sizeof(dev_priv-vbt.dsi.sequence)); } static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, -- 2.0.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] intel-gpu-tools: fix version.h creation in android
From: Tim Gore tim.g...@intel.com commit 743dc7997aa9f5210055896940d87c88983dcda6 breaks the build under Android because version.h is not created. This happens because the android make executes from the ANDROID_BUILD_TOP directory rather than from the directory containing the source files, so we need Android specific make instructions to generate version.h Signed-off-by: Tim Gore tim.g...@intel.com --- lib/Android.mk | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/lib/Android.mk b/lib/Android.mk index 6f444a0..d6b181d 100644 --- a/lib/Android.mk +++ b/lib/Android.mk @@ -1,6 +1,7 @@ LOCAL_PATH := $(call my-dir) GPU_TOOLS_PATH := $(LOCAL_PATH)/.. +IGT_LIB_PATH := $(LOCAL_PATH) # FIXME: autogenerate this info # $(GPU_TOOLS_PATH)/config.h: @@ -13,7 +14,7 @@ include $(LOCAL_PATH)/Makefile.sources include $(CLEAR_VARS) LOCAL_GENERATED_SOURCES := \ - $(GPU_TOOLS_PATH)/lib/version.h \ + $(IGT_LIB_PATH)/version.h \ $(GPU_TOOLS_PATH)/config.h LOCAL_C_INCLUDES += \ @@ -45,5 +46,30 @@ endif LOCAL_SRC_FILES := $(filter-out $(skip_lib_list),$(libintel_tools_la_SOURCES)) +.PHONY: version.h.tmp + +$(IGT_LIB_PATH)/version.h.tmp: + @touch $@ + @if test -d $(GPU_TOOLS_PATH)/.git; then \ + if which git /dev/null 21; then cd $(@D); \ + git log -n 1 --oneline | \ + sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 g\1/' \ +$(@F) ; \ + else \ + echo '#define IGT_GIT_SHA1 NO-GIT' $@ ; \ + fi \ + else \ + echo '#define IGT_GIT_SHA1 NOT-GIT' $@ ; \ + fi + + +$(IGT_LIB_PATH)/version.h: $(IGT_LIB_PATH)/version.h.tmp + @if ! cmp -s $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h; then \ + mv $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h ; \ + else \ + rm $(IGT_LIB_PATH)/version.h.tmp ; \ + fi + + include $(BUILD_STATIC_LIBRARY) -- 1.9.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] intel-gpu-tools: fix version.h creation in android
On 24 July 2014 15:40, tim.g...@intel.com wrote: From: Tim Gore tim.g...@intel.com commit 743dc7997aa9f5210055896940d87c88983dcda6 breaks the build under Android because version.h is not created. This happens because the android make executes from the ANDROID_BUILD_TOP directory rather than from the directory containing the source files, so we need Android specific make instructions to generate version.h Could this also be fixed by defining the various paths (as below) in Makefile.am as well and still re-use the same rule from Makefile.sources, which gets included by both Android.mk and Makefile.am anyway? Signed-off-by: Tim Gore tim.g...@intel.com --- lib/Android.mk | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/lib/Android.mk b/lib/Android.mk index 6f444a0..d6b181d 100644 --- a/lib/Android.mk +++ b/lib/Android.mk @@ -1,6 +1,7 @@ LOCAL_PATH := $(call my-dir) GPU_TOOLS_PATH := $(LOCAL_PATH)/.. +IGT_LIB_PATH := $(LOCAL_PATH) # FIXME: autogenerate this info # $(GPU_TOOLS_PATH)/config.h: @@ -13,7 +14,7 @@ include $(LOCAL_PATH)/Makefile.sources include $(CLEAR_VARS) LOCAL_GENERATED_SOURCES := \ - $(GPU_TOOLS_PATH)/lib/version.h \ + $(IGT_LIB_PATH)/version.h \ $(GPU_TOOLS_PATH)/config.h LOCAL_C_INCLUDES += \ @@ -45,5 +46,30 @@ endif LOCAL_SRC_FILES := $(filter-out $(skip_lib_list),$(libintel_tools_la_SOURCES)) +.PHONY: version.h.tmp + +$(IGT_LIB_PATH)/version.h.tmp: + @touch $@ + @if test -d $(GPU_TOOLS_PATH)/.git; then \ + if which git /dev/null 21; then cd $(@D); \ + git log -n 1 --oneline | \ + sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 g\1/' \ +$(@F) ; \ + else \ + echo '#define IGT_GIT_SHA1 NO-GIT' $@ ; \ + fi \ + else \ + echo '#define IGT_GIT_SHA1 NOT-GIT' $@ ; \ + fi + + +$(IGT_LIB_PATH)/version.h: $(IGT_LIB_PATH)/version.h.tmp + @if ! cmp -s $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h; then \ + mv $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h ; \ + else \ + rm $(IGT_LIB_PATH)/version.h.tmp ; \ + fi + + include $(BUILD_STATIC_LIBRARY) -- 1.9.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx - Intel Corporation (UK) Limited Registered No. 1134945 (England) Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] intel-gpu-tools: fix version.h creation in android
-Original Message- From: Thomas Wood [mailto:thomas.w...@intel.com] Sent: Thursday, July 24, 2014 4:27 PM To: Gore, Tim Cc: Intel Graphics Development Subject: Re: [Intel-gfx] [PATCH] intel-gpu-tools: fix version.h creation in android On 24 July 2014 15:40, tim.g...@intel.com wrote: From: Tim Gore tim.g...@intel.com commit 743dc7997aa9f5210055896940d87c88983dcda6 breaks the build under Android because version.h is not created. This happens because the android make executes from the ANDROID_BUILD_TOP directory rather than from the directory containing the source files, so we need Android specific make instructions to generate version.h Could this also be fixed by defining the various paths (as below) in Makefile.am as well and still re-use the same rule from Makefile.sources, which gets included by both Android.mk and Makefile.am anyway? That may be possible, I have not tried it. I'm something of a novice with Autotools but I'll give it a go. Signed-off-by: Tim Gore tim.g...@intel.com --- lib/Android.mk | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/lib/Android.mk b/lib/Android.mk index 6f444a0..d6b181d 100644 --- a/lib/Android.mk +++ b/lib/Android.mk @@ -1,6 +1,7 @@ LOCAL_PATH := $(call my-dir) GPU_TOOLS_PATH := $(LOCAL_PATH)/.. +IGT_LIB_PATH := $(LOCAL_PATH) # FIXME: autogenerate this info # $(GPU_TOOLS_PATH)/config.h: @@ -13,7 +14,7 @@ include $(LOCAL_PATH)/Makefile.sources include $(CLEAR_VARS) LOCAL_GENERATED_SOURCES := \ - $(GPU_TOOLS_PATH)/lib/version.h \ + $(IGT_LIB_PATH)/version.h \ $(GPU_TOOLS_PATH)/config.h LOCAL_C_INCLUDES += \ @@ -45,5 +46,30 @@ endif LOCAL_SRC_FILES := $(filter-out $(skip_lib_list),$(libintel_tools_la_SOURCES)) +.PHONY: version.h.tmp + +$(IGT_LIB_PATH)/version.h.tmp: + @touch $@ + @if test -d $(GPU_TOOLS_PATH)/.git; then \ + if which git /dev/null 21; then cd $(@D); \ + git log -n 1 --oneline | \ + sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 g\1/' \ +$(@F) ; \ + else \ + echo '#define IGT_GIT_SHA1 NO-GIT' $@ ; \ + fi \ + else \ + echo '#define IGT_GIT_SHA1 NOT-GIT' $@ ; \ + fi + + +$(IGT_LIB_PATH)/version.h: $(IGT_LIB_PATH)/version.h.tmp + @if ! cmp -s $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h; then \ + mv $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h ; \ + else \ + rm $(IGT_LIB_PATH)/version.h.tmp ; \ + fi + + include $(BUILD_STATIC_LIBRARY) -- 1.9.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx - Intel Corporation (UK) Limited Registered No. 1134945 (England) Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 15/44] drm/i915: Added deferred work handler for scheduler
On 23/07/2014 19:50, Daniel Vetter wrote:
On Wed, Jul 23, 2014 at 5:37 PM, John Harrison
john.c.harri...@intel.com wrote:
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 0977653..fbafa68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1075,6 +1075,16 @@ struct i915_gem_mm {
struct delayed_work idle_work;
/**
+* New scheme is to get an interrupt after every work packet
+* in order to allow the low latency scheduling of pending
+* packets. The idea behind adding new packets to a pending
+* queue rather than directly into the hardware ring buffer
+* is to allow high priority packets to over take low priority
+* ones.
+*/
+ struct work_struct scheduler_work;
Latency for work items isn't too awesome, and e.g. Oscar's execlist code
latches the next context right away from the irq handler. Why can't we do
something similar for the scheduler? Fishing the next item out of a
priority queue shouldn't be expensive ...
-Daniel
The problem is that taking batch buffers from the scheduler's queue and
submitting them to the hardware requires lots of processing that is not IRQ
compatible. It isn't just a simple register write. Half of the code in
'i915_gem_do_execbuffer()' must be executed. Probably/possibly it could be
made IRQ friendly but that would place a lot of restrictions on a lot of
code that currently doesn't expect to be restricted. Instead, the submission
is done via a work handler that acquires the driver mutex lock.
In order to cover the extra latency, the scheduler operates in a
multi-buffered mode and aims to keep eight batch buffers in flight at all
times. That number being obtained empirically by running lots of benchmarks
on Android with lots of different settings and seeing where the buffer size
stopped making a difference.
So I've tried to stitch together that part of the scheduler from the
patch series. Afaics you do the actual scheduling under the protection
of irqsave spinlocks (well you also hold the dev-struct_mutex). That
means you disable local interrupts. Up to the actual submit point I
spotted two such critcial sections encompassing pretty much all the
code.
If we'd run the same code from the interrupt handler then only our own
interrupt handler is blocked, all other interrupt processing can
continue. So that's actually a lot nicer than what you have. In any
case you can't do expensive operations under an irqsave spinlock
anyway.
So either I've missed something big here, or this justification doesn't hold up.
-Daniel
The irqsave spinlock is only held while manipulating the internal
scheduler data structures. It is released immediately prior to calling
i915_gem_do_execbuffer_final(). So the actual submission code path is
done with the driver mutex but no spinlocks. I'm sure I got 'scheduling
while atomic' bug checks the one time I accidentally left the spinlock held.
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[Intel-gfx] [PATCH 09/43] drm/i915/bdw: Populate LR contexts (somewhat)
From: Oscar Mateo oscar.ma...@intel.com
For the most part, logical ring context objects are similar to hardware
contexts in that the backing object is meant to be opaque. There are
some exceptions where we need to poke certain offsets of the object for
initialization, updating the tail pointer or updating the PDPs.
For our basic execlist implementation we'll only need our PPGTT PDs,
and ringbuffer addresses in order to set up the context. With previous
patches, we have both, so start prepping the context to be load.
Before running a context for the first time you must populate some
fields in the context object. These fields begin 1 PAGE + LRCA, ie. the
first page (in 0 based counting) of the context image. These same
fields will be read and written to as contexts are saved and restored
once the system is up and running.
Many of these fields are completely reused from previous global
registers: ringbuffer head/tail/control, context control matches some
previous MI_SET_CONTEXT flags, and page directories. There are other
fields which we don't touch which we may want in the future.
v2: CTX_LRI_HEADER_0 is MI_LOAD_REGISTER_IMM(14) for render and (11)
for other engines.
v3: Several rebases and general changes to the code.
v4: Squash with Extract LR context object populating
Also, Damien's review comments:
- Set the Force Posted bit on the LRI header, as the BSpec suggest we do.
- Prevent warning when compiling a 32-bits kernel without HIGHMEM64.
- Add a clarifying comment to the context population code.
v5: Damien's review comments:
- The third MI_LOAD_REGISTER_IMM in the context does not set Force Posted.
- Remove dead code.
v6: Add a note about the (presumed) differences between BDW and CHV state
contexts. Also, Brad's review comments:
- Use the _MASKED_BIT_ENABLE, upper_32_bits and lower_32_bits macros.
- Be less magical about how we set the ring size in the context.
Signed-off-by: Ben Widawsky b...@bwidawsk.net (v1)
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com (v2)
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_lrc.c | 159 +-
2 files changed, 156 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce70aa4..043a6ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -282,6 +282,7 @@
* address/value pairs. Don't overdue it, though, x = 2^4 must hold!
*/
#define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*(x)-1)
+#define MI_LRI_FORCE_POSTED (112)
#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
#define MI_SRM_LRM_GLOBAL_GTT(122)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2eb7db6..cf322ec 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -46,6 +46,38 @@
#define GEN8_LR_CONTEXT_ALIGN 4096
+#define RING_ELSP(ring)((ring)-mmio_base+0x230)
+#define RING_CONTEXT_CONTROL(ring) ((ring)-mmio_base+0x244)
+
+#define CTX_LRI_HEADER_0 0x01
+#define CTX_CONTEXT_CONTROL0x02
+#define CTX_RING_HEAD 0x04
+#define CTX_RING_TAIL 0x06
+#define CTX_RING_BUFFER_START 0x08
+#define CTX_RING_BUFFER_CONTROL0x0a
+#define CTX_BB_HEAD_U 0x0c
+#define CTX_BB_HEAD_L 0x0e
+#define CTX_BB_STATE 0x10
+#define CTX_SECOND_BB_HEAD_U 0x12
+#define CTX_SECOND_BB_HEAD_L 0x14
+#define CTX_SECOND_BB_STATE0x16
+#define CTX_BB_PER_CTX_PTR 0x18
+#define CTX_RCS_INDIRECT_CTX 0x1a
+#define CTX_RCS_INDIRECT_CTX_OFFSET0x1c
+#define CTX_LRI_HEADER_1 0x21
+#define CTX_CTX_TIMESTAMP 0x22
+#define CTX_PDP3_UDW 0x24
+#define CTX_PDP3_LDW 0x26
+#define CTX_PDP2_UDW 0x28
+#define CTX_PDP2_LDW 0x2a
+#define CTX_PDP1_UDW 0x2c
+#define CTX_PDP1_LDW 0x2e
+#define CTX_PDP0_UDW 0x30
+#define CTX_PDP0_LDW 0x32
+#define CTX_LRI_HEADER_2 0x41
+#define CTX_R_PWR_CLK_STATE0x42
+#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
+
int intel_sanitize_enable_execlists(struct drm_device *dev, int
enable_execlists)
{
if (enable_execlists == 0)
@@ -57,6 +89,115 @@ int intel_sanitize_enable_execlists(struct drm_device *dev,
int enable_execlists
return 0;
}
+static int
+populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object
*ctx_obj,
+ struct intel_engine_cs *ring, struct intel_ringbuffer
*ringbuf)
+{
+ struct drm_i915_gem_object *ring_obj = ringbuf-obj;
+ struct i915_hw_ppgtt
[Intel-gfx] [PATCH 08/43] drm/i915/bdw: Add a context and an engine pointers to the ringbuffer
From: Oscar Mateo oscar.ma...@intel.com
Any given ringbuffer is unequivocally tied to one context and one engine.
By setting the appropriate pointers to them, the ringbuffer struct holds
all the infromation you might need to submit a workload for processing,
Execlists style.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c|2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c |2 ++
drivers/gpu/drm/i915/intel_ringbuffer.h |3 +++
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a12b8c..2eb7db6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -132,6 +132,8 @@ int intel_lr_context_deferred_create(struct intel_context
*ctx,
return ret;
}
+ ringbuf-ring = ring;
+ ringbuf-ctx = ctx;
ringbuf-size = 32 * PAGE_SIZE;
ringbuf-effective_size = ringbuf-size;
ringbuf-head = 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 01e9840..279dda4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1570,6 +1570,8 @@ static int intel_init_ring_buffer(struct drm_device *dev,
INIT_LIST_HEAD(ring-active_list);
INIT_LIST_HEAD(ring-request_list);
ringbuf-size = 32 * PAGE_SIZE;
+ ringbuf-ring = ring;
+ ringbuf-ctx = ring-default_context;
memset(ring-semaphore.sync_seqno, 0,
sizeof(ring-semaphore.sync_seqno));
init_waitqueue_head(ring-irq_queue);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 053d004..be40788 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -88,6 +88,9 @@ struct intel_ringbuffer {
struct drm_i915_gem_object *obj;
void __iomem *virtual_start;
+ struct intel_engine_cs *ring;
+ struct intel_context *ctx;
+
u32 head;
u32 tail;
int space;
--
1.7.9.5
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[Intel-gfx] [PATCH 00/43] Execlists v5
From: Thomas Daniel thomas.dan...@intel.com For a description of this patchset, please check the previous cover letters: [1], [2], [3] and [4]. I have taken ownership of this patchset from Oscar, and this version represents his last work on the execlists patchset. The narrative below is from him. I have been given some grace period to fix the remaining issues in Execlists before I move to a different project, and this is the result. There are very little differences between this v5 and the v4 I sent out last week, so I was unsure whether to drop a new patchbomb or simply reply to the patches that have changed, but I decided for the former to make the review easier. The changes are: - New prep-work patch to prevent a potential problem with the legacy ringbuffer submission extraction that was done earlier. - Do the remaining intel_runtime_put while purging the execlists queue during reset. - Check arguments before doing stuff in intel_execlists_submission. Also, get rel_constants parsing right. - Do gen8_emit_flush = gen6_ring_flush + gen6_bsd_ring_flush. - New patches for pinning context and ringbuffer backing objects on-demand (before I was pinning on interrupt time, which was a no-no). These fix the reamining eviction issues I was seeing. The previous comment about the WAs still applies. I reproduce it here for completeness: One other caveat I have noticed is that many WAs in gen8_init_clock_gating (those that affect registers that now exist per-context) can get lost in the render default context. The reason is, in Execlists, a context is saved as soon as head = tail (with MI_SET_CONTEXT, however, the context wouldn't be saved until you tried to restore a different context). As we are sending the golden state batchbuffer to the render ring as soon as the rings are initialized, we are effectively saving the default context before gen8_init_clock_gating has an opportunity to set the WAs. I haven't noticed any ill-effect from this (yet) but it would be a good idea to move the WAs somewhere else (ring init looks like a good place). I believe there is already work in progress to create a new WA architecture, so this can be tackled there. The previous IGT test [4] still applies. There are three pending issues: - The test gem_close_race warns about scheduling while atomic when the shrinker gets called. Without Execlists, the shrinker does not get called at all (which kind of makes sense) but the tests timeouts before finishing. - The test gem_concurrent_blit fails in the gtt-* subtests: some pixels (14, to be exact) do not get copied correctly from one bo to another. Funnily enough, the tests pass if I do a i915 module reload first (./tests/drv_module_reload). Yesterday I dumped all the registers in the chip before and after a module reload (attached), but I havenŽt found any meaningful difference yet. - When I try to run a whole IGT suite using Piglit, sometimes I hit the BUG_ON(!i915_gem_obj_is_pinned(ctx_obj0)) in execlists_submit_context(). I havenŽt managed to reproduce the problem at will, but there is obviously something wrong with the last two Execlists patches. Keep the r-b tags coming, please!! -- Oscar [1] http://lists.freedesktop.org/archives/intel-gfx/2014-March/042563.html [2] http://lists.freedesktop.org/archives/intel-gfx/2014-May/044847.html [3] http://lists.freedesktop.org/archives/intel-gfx/2014-June/047138.html [4] http://lists.freedesktop.org/archives/intel-gfx/2014-July/048944.html [5] http://lists.freedesktop.org/archives/intel-gfx/2014-May/044846.html Ben Widawsky (2): drm/i915/bdw: Implement context switching (somewhat) drm/i915/bdw: Print context state in debugfs Michel Thierry (1): drm/i915/bdw: Two-stage execlist submit process Oscar Mateo (39): drm/i915: Reorder the actual workload submission so that args checking is done earlier drm/i915/bdw: New source and header file for LRs, LRCs and Execlists drm/i915/bdw: Macro for LRCs and module option for Execlists drm/i915/bdw: Initialization for Logical Ring Contexts drm/i915/bdw: Introduce one context backing object per engine drm/i915/bdw: A bit more advanced LR context alloc/free drm/i915/bdw: Allocate ringbuffers for Logical Ring Contexts drm/i915/bdw: Add a context and an engine pointers to the ringbuffer drm/i915/bdw: Populate LR contexts (somewhat) drm/i915/bdw: Deferred creation of user-created LRCs drm/i915/bdw: Render moot context reset and switch with Execlists drm/i915/bdw: Don't write PDP in the legacy way when using LRCs drm/i915: Abstract the legacy workload submission mechanism away drm/i915/bdw: Skeleton for the new logical rings submission path drm/i915/bdw: Generic logical ring init and cleanup drm/i915/bdw: GEN-specific logical ring init drm/i915/bdw: GEN-specific logical ring set/get seqno drm/i915/bdw: New logical ring submission mechanism drm/i915/bdw: GEN-specific logical ring emit request drm/i915/bdw: GEN-specific
[Intel-gfx] [PATCH 04/43] drm/i915/bdw: Initialization for Logical Ring Contexts
From: Oscar Mateo oscar.ma...@intel.com
For the moment this is just a placeholder, but it shows one of the
main differences between the good ol' HW contexts and the shiny
new Logical Ring Contexts: LR contexts allocate and free their
own backing objects. Another difference is that the allocation is
deferred (as the create function name suggests), but that does not
happen in this patch yet, because for the moment we are only dealing
with the default context.
Early in the series we had our own gen8_gem_context_init/fini
functions, but the truth is they now look almost the same as the
legacy hw context init/fini functions. We can always split them
later if this ceases to be the case.
Also, we do not fall back to legacy ringbuffers when logical ring
context initialization fails (not very likely to happen and, even
if it does, hw contexts would probably fail as well).
v2: Daniel says explain, do not showcase.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 29 +++--
drivers/gpu/drm/i915/intel_lrc.c| 15 +++
drivers/gpu/drm/i915/intel_lrc.h|5 +
3 files changed, 43 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index de72a28..718150e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -182,7 +182,10 @@ void i915_gem_context_free(struct kref *ctx_ref)
typeof(*ctx), ref);
struct i915_hw_ppgtt *ppgtt = NULL;
- if (ctx-legacy_hw_ctx.rcs_state) {
+ if (i915.enable_execlists) {
+ ppgtt = ctx_to_ppgtt(ctx);
+ intel_lr_context_free(ctx);
+ } else if (ctx-legacy_hw_ctx.rcs_state) {
/* We refcount even the aliasing PPGTT to keep the code
symmetric */
if (USES_PPGTT(ctx-legacy_hw_ctx.rcs_state-base.dev))
ppgtt = ctx_to_ppgtt(ctx);
@@ -419,7 +422,11 @@ int i915_gem_context_init(struct drm_device *dev)
if (WARN_ON(dev_priv-ring[RCS].default_context))
return 0;
- if (HAS_HW_CONTEXTS(dev)) {
+ if (i915.enable_execlists) {
+ /* NB: intentionally left blank. We will allocate our own
+* backing objects as we need them, thank you very much */
+ dev_priv-hw_context_size = 0;
+ } else if (HAS_HW_CONTEXTS(dev)) {
dev_priv-hw_context_size = round_up(get_context_size(dev),
4096);
if (dev_priv-hw_context_size (120)) {
DRM_DEBUG_DRIVER(Disabling HW Contexts; invalid size
%d\n,
@@ -435,11 +442,20 @@ int i915_gem_context_init(struct drm_device *dev)
return PTR_ERR(ctx);
}
- /* NB: RCS will hold a ref for all rings */
- for (i = 0; i I915_NUM_RINGS; i++)
- dev_priv-ring[i].default_context = ctx;
+ for (i = 0; i I915_NUM_RINGS; i++) {
+ struct intel_engine_cs *ring = dev_priv-ring[i];
+
+ /* NB: RCS will hold a ref for all rings */
+ ring-default_context = ctx;
+
+ /* FIXME: we really only want to do this for initialized rings
*/
+ if (i915.enable_execlists)
+ intel_lr_context_deferred_create(ctx, ring);
+ }
- DRM_DEBUG_DRIVER(%s context support initialized\n,
dev_priv-hw_context_size ? HW : fake);
+ DRM_DEBUG_DRIVER(%s context support initialized\n,
+ i915.enable_execlists ? LR :
+ dev_priv-hw_context_size ? HW : fake);
return 0;
}
@@ -781,6 +797,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
struct intel_context *ctx;
int ret;
+ /* FIXME: allow user-created LR contexts as well */
if (!hw_context_enabled(dev))
return -ENODEV;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 21f7f1c..8cc6b55 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -51,3 +51,18 @@ int intel_sanitize_enable_execlists(struct drm_device *dev,
int enable_execlists
return 0;
}
+
+void intel_lr_context_free(struct intel_context *ctx)
+{
+ /* TODO */
+}
+
+int intel_lr_context_deferred_create(struct intel_context *ctx,
+struct intel_engine_cs *ring)
+{
+ BUG_ON(ctx-legacy_hw_ctx.rcs_state != NULL);
+
+ /* TODO */
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 75ee9c3..3b93572 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -24,6 +24,11 @@
#ifndef _INTEL_LRC_H_
#define _INTEL_LRC_H_
+/* Logical Ring Contexts */
+void intel_lr_context_free(struct intel_context *ctx);
+int
[Intel-gfx] [PATCH 03/43] drm/i915/bdw: Macro for LRCs and module option for Execlists
From: Oscar Mateo oscar.ma...@intel.com
GEN8 brings an expansion of the HW contexts: Logical Ring Contexts.
These expanded contexts enable a number of new abilities, especially
Execlists.
The macro is defined to off until we have things in place to hope to
work.
v2: Rename advanced contexts to the more correct logical ring
contexts.
v3: Add a module parameter to enable execlists. Execlist are relatively
new, and so it'd be wise to be able to switch back to ring submission
to debug subtle problems that will inevitably arise.
v4: Add an intel_enable_execlists function.
v5: Sanitize early, as suggested by Daniel. Remove lrc_enabled.
Signed-off-by: Ben Widawsky b...@bwidawsk.net (v1)
Signed-off-by: Damien Lespiau damien.lesp...@intel.com (v3)
Signed-off-by: Oscar Mateo oscar.ma...@intel.com (v2, v4 v5)
---
drivers/gpu/drm/i915/i915_drv.h|2 ++
drivers/gpu/drm/i915/i915_gem.c|3 +++
drivers/gpu/drm/i915/i915_params.c |6 ++
drivers/gpu/drm/i915/intel_lrc.c | 11 +++
drivers/gpu/drm/i915/intel_lrc.h |3 +++
5 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54c2bd9..a793d6d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2037,6 +2037,7 @@ struct drm_i915_cmd_table {
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)-need_gfx_hws)
#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)-gen = 6)
+#define HAS_LOGICAL_RING_CONTEXTS(dev) 0
#define HAS_ALIASING_PPGTT(dev)(INTEL_INFO(dev)-gen = 6)
#define HAS_PPGTT(dev) (INTEL_INFO(dev)-gen = 7 !IS_GEN8(dev))
#define USES_PPGTT(dev)intel_enable_ppgtt(dev, false)
@@ -2122,6 +2123,7 @@ struct i915_params {
int enable_rc6;
int enable_fbc;
int enable_ppgtt;
+ int enable_execlists;
int enable_psr;
unsigned int preliminary_hw_support;
int disable_power_well;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5d4d73..d8bf4fa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4746,6 +4746,9 @@ int i915_gem_init(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
+ i915.enable_execlists = intel_sanitize_enable_execlists(dev,
+ i915.enable_execlists);
+
mutex_lock(dev-struct_mutex);
if (IS_VALLEYVIEW(dev)) {
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index bbdee21..7f0fb72 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -35,6 +35,7 @@ struct i915_params i915 __read_mostly = {
.vbt_sdvo_panel_type = -1,
.enable_rc6 = -1,
.enable_fbc = -1,
+ .enable_execlists = -1,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = 1,
@@ -117,6 +118,11 @@ MODULE_PARM_DESC(enable_ppgtt,
Override PPGTT usage.
(-1=auto [default], 0=disabled, 1=aliasing, 2=full));
+module_param_named(enable_execlists, i915.enable_execlists, int, 0400);
+MODULE_PARM_DESC(enable_execlists,
+ Override execlists usage.
+ (-1=auto [default], 0=disabled, 1=enabled));
+
module_param_named(enable_psr, i915.enable_psr, int, 0600);
MODULE_PARM_DESC(enable_psr, Enable PSR (default: true));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 49bb6fc..21f7f1c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -40,3 +40,14 @@
#include drm/drmP.h
#include drm/i915_drm.h
#include i915_drv.h
+
+int intel_sanitize_enable_execlists(struct drm_device *dev, int
enable_execlists)
+{
+ if (enable_execlists == 0)
+ return 0;
+
+ if (HAS_LOGICAL_RING_CONTEXTS(dev) USES_PPGTT(dev))
+ return 1;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f6830a4..75ee9c3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -24,4 +24,7 @@
#ifndef _INTEL_LRC_H_
#define _INTEL_LRC_H_
+/* Execlists */
+int intel_sanitize_enable_execlists(struct drm_device *dev, int
enable_execlists);
+
#endif /* _INTEL_LRC_H_ */
--
1.7.9.5
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[Intel-gfx] [PATCH 01/43] drm/i915: Reorder the actual workload submission so that args checking is done earlier
From: Oscar Mateo oscar.ma...@intel.com
In this patch:
commit 78382593e921c88371abd019aca8978db3248a8f
Author: Oscar Mateo oscar.ma...@intel.com
Date: Thu Jul 3 16:28:05 2014 +0100
drm/i915: Extract the actual workload submission mechanism from execbuffer
So that we isolate the legacy ringbuffer submission mechanism, which becomes
a good candidate to be abstracted away. This is prep-work for Execlists
(which
will its own workload submission mechanism).
No functional changes.
I changed the order in which the args checking is done. I don't know why I did
(brain
fade?) but itś not right. I haven't seen any ill effect from this, but the
Execlists
version of this function will have problems if the order is not correct.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 86 ++--
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 60998fc..c5115957 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1042,6 +1042,43 @@ legacy_ringbuffer_submission(struct drm_device *dev,
struct drm_file *file,
u32 instp_mask;
int i, ret = 0;
+ instp_mode = args-flags I915_EXEC_CONSTANTS_MASK;
+ instp_mask = I915_EXEC_CONSTANTS_MASK;
+ switch (instp_mode) {
+ case I915_EXEC_CONSTANTS_REL_GENERAL:
+ case I915_EXEC_CONSTANTS_ABSOLUTE:
+ case I915_EXEC_CONSTANTS_REL_SURFACE:
+ if (instp_mode != 0 ring != dev_priv-ring[RCS]) {
+ DRM_DEBUG(non-0 rel constants mode on non-RCS\n);
+ ret = -EINVAL;
+ goto error;
+ }
+
+ if (instp_mode != dev_priv-relative_constants_mode) {
+ if (INTEL_INFO(dev)-gen 4) {
+ DRM_DEBUG(no rel constants on pre-gen4\n);
+ ret = -EINVAL;
+ goto error;
+ }
+
+ if (INTEL_INFO(dev)-gen 5
+ instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
+ DRM_DEBUG(rel surface constants mode invalid
on gen5+\n);
+ ret = -EINVAL;
+ goto error;
+ }
+
+ /* The HW changed the meaning on this bit on gen6 */
+ if (INTEL_INFO(dev)-gen = 6)
+ instp_mask = ~I915_EXEC_CONSTANTS_REL_SURFACE;
+ }
+ break;
+ default:
+ DRM_DEBUG(execbuf with unknown constants: %d\n, instp_mode);
+ ret = -EINVAL;
+ goto error;
+ }
+
if (args-num_cliprects != 0) {
if (ring != dev_priv-ring[RCS]) {
DRM_DEBUG(clip rectangles are only valid with the
render ring\n);
@@ -1085,6 +1122,12 @@ legacy_ringbuffer_submission(struct drm_device *dev,
struct drm_file *file,
}
}
+ if (args-flags I915_EXEC_GEN7_SOL_RESET) {
+ ret = i915_reset_gen7_sol_offsets(dev, ring);
+ if (ret)
+ goto error;
+ }
+
ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);
if (ret)
goto error;
@@ -1093,43 +1136,6 @@ legacy_ringbuffer_submission(struct drm_device *dev,
struct drm_file *file,
if (ret)
goto error;
- instp_mode = args-flags I915_EXEC_CONSTANTS_MASK;
- instp_mask = I915_EXEC_CONSTANTS_MASK;
- switch (instp_mode) {
- case I915_EXEC_CONSTANTS_REL_GENERAL:
- case I915_EXEC_CONSTANTS_ABSOLUTE:
- case I915_EXEC_CONSTANTS_REL_SURFACE:
- if (instp_mode != 0 ring != dev_priv-ring[RCS]) {
- DRM_DEBUG(non-0 rel constants mode on non-RCS\n);
- ret = -EINVAL;
- goto error;
- }
-
- if (instp_mode != dev_priv-relative_constants_mode) {
- if (INTEL_INFO(dev)-gen 4) {
- DRM_DEBUG(no rel constants on pre-gen4\n);
- ret = -EINVAL;
- goto error;
- }
-
- if (INTEL_INFO(dev)-gen 5
- instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
- DRM_DEBUG(rel surface constants mode invalid
on gen5+\n);
- ret = -EINVAL;
- goto error;
- }
-
- /* The HW changed the meaning on this bit on gen6 */
- if (INTEL_INFO(dev)-gen = 6)
- instp_mask =
[Intel-gfx] [PATCH 10/43] drm/i915/bdw: Deferred creation of user-created LRCs
From: Oscar Mateo oscar.ma...@intel.com
The backing objects and ringbuffers for contexts created via open
fd are actually empty until the user starts sending execbuffers to
them. At that point, we allocate populate them. We do this because,
at create time, we really don't know which engine is going to be used
with the context later on (and we don't want to waste memory on
objects that we might never use).
v2: As contexts created via ioctl can only be used with the render
ring, we have enough information to allocate populate them right
away.
v3: Defer the creation always, even with ioctl-created contexts, as
requested by Daniel Vetter.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c|7 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c |8
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 48d7476..fbe7278 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -784,9 +784,9 @@ int i915_switch_context(struct intel_engine_cs *ring,
return do_switch(ring, to);
}
-static bool hw_context_enabled(struct drm_device *dev)
+static bool contexts_enabled(struct drm_device *dev)
{
- return to_i915(dev)-hw_context_size;
+ return i915.enable_execlists || to_i915(dev)-hw_context_size;
}
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
@@ -797,8 +797,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
struct intel_context *ctx;
int ret;
- /* FIXME: allow user-created LR contexts as well */
- if (!hw_context_enabled(dev))
+ if (!contexts_enabled(dev))
return -ENODEV;
ret = i915_mutex_lock_interruptible(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index c5115957..4e9b387 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -951,6 +951,14 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
return ERR_PTR(-EIO);
}
+ if (i915.enable_execlists !ctx-engine[ring-id].state) {
+ int ret = intel_lr_context_deferred_create(ctx, ring);
+ if (ret) {
+ DRM_DEBUG(Could not create LRC %u: %d\n, ctx_id, ret);
+ return ERR_PTR(ret);
+ }
+ }
+
return ctx;
}
--
1.7.9.5
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/43] drm/i915/bdw: Introduce one context backing object per engine
From: Oscar Mateo oscar.ma...@intel.com
A context backing object only makes sense for a given engine (because
it holds state data specific to that engine).
In legacy ringbuffer sumission mode, the only MI_SET_CONTEXT we really
perform is for the render engine, so one backing object is all we nee.
With Execlists, however, we need backing objects for every engine, as
contexts become the only way to submit workloads to the GPU. To tackle
this problem, we multiplex the context struct to contain no-of-engines
objects.
Originally, I colored this code by instantiating one new context for
every engine I wanted to use, but this change suggested by Brad Volkin
makes it more elegant.
v2: Leave the old backing object pointer behind. Daniel Vetter suggested
using a union, but it makes more sense to keep rcs_state as a NULL
pointer behind, to make sure no one uses it incorrectly when Execlists
are enabled, similar to what he suggested for ring-buffer (Rusty's API
level 5).
v3: Use the name state instead of the too-generic obj, so that it
mirrors the name choice for the legacy rcs_state.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a793d6d..b2b0c80 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -616,11 +616,17 @@ struct intel_context {
struct i915_ctx_hang_stats hang_stats;
struct i915_address_space *vm;
+ /* Legacy ring buffer submission */
struct {
struct drm_i915_gem_object *rcs_state;
bool initialized;
} legacy_hw_ctx;
+ /* Execlists */
+ struct {
+ struct drm_i915_gem_object *state;
+ } engine[I915_NUM_RINGS];
+
struct list_head link;
};
--
1.7.9.5
___
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[Intel-gfx] [PATCH 11/43] drm/i915/bdw: Render moot context reset and switch with Execlists
From: Oscar Mateo oscar.ma...@intel.com
These two functions make no sense in an Logical Ring Context Execlists
world.
v2: We got rid of lrc_enabled and centralized everything in the sanitized
i915.enbale_execlists instead.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index fbe7278..288f5de 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -380,6 +380,9 @@ void i915_gem_context_reset(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev-dev_private;
int i;
+ if (i915.enable_execlists)
+ return;
+
/* Prevent the hardware from restoring the last context (which hung) on
* the next switch */
for (i = 0; i I915_NUM_RINGS; i++) {
@@ -514,6 +517,9 @@ int i915_gem_context_enable(struct drm_i915_private
*dev_priv)
ppgtt-enable(ppgtt);
}
+ if (i915.enable_execlists)
+ return 0;
+
/* FIXME: We should make this work, even in reset */
if (i915_reset_in_progress(dev_priv-gpu_error))
return 0;
@@ -769,6 +775,9 @@ int i915_switch_context(struct intel_engine_cs *ring,
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
+ if (i915.enable_execlists)
+ return 0;
+
WARN_ON(!mutex_is_locked(dev_priv-dev-struct_mutex));
if (to-legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context
*/
--
1.7.9.5
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/43] drm/i915/bdw: Generic logical ring init and cleanup
From: Oscar Mateo oscar.ma...@intel.com
Allocate and populate the default LRC for every ring, call
gen-specific init/cleanup, init/fini the command parser and
set the status page (now inside the LRC object). These are
things all engines/rings have in common.
Stopping the ring before cleanup and initializing the seqnos
is left as a TODO task (we need more infrastructure in place
before we can achieve this).
v2: Check the ringbuffer backing obj for ring_is_initialized,
instead of the context backing obj (similar, but not exactly
the same).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c |4 ---
drivers/gpu/drm/i915/intel_lrc.c| 54 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 17 ++
drivers/gpu/drm/i915/intel_ringbuffer.h |6 +---
4 files changed, 70 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 288f5de..9085ff1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -450,10 +450,6 @@ int i915_gem_context_init(struct drm_device *dev)
/* NB: RCS will hold a ref for all rings */
ring-default_context = ctx;
-
- /* FIXME: we really only want to do this for initialized rings
*/
- if (i915.enable_execlists)
- intel_lr_context_deferred_create(ctx, ring);
}
DRM_DEBUG_DRIVER(%s context support initialized\n,
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cb56bb8..05b7069 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -108,12 +108,60 @@ void intel_logical_ring_stop(struct intel_engine_cs *ring)
void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
{
- /* TODO */
+ if (!intel_ring_initialized(ring))
+ return;
+
+ /* TODO: make sure the ring is stopped */
+ ring-preallocated_lazy_request = NULL;
+ ring-outstanding_lazy_seqno = 0;
+
+ if (ring-cleanup)
+ ring-cleanup(ring);
+
+ i915_cmd_parser_fini_ring(ring);
+
+ if (ring-status_page.obj) {
+ kunmap(sg_page(ring-status_page.obj-pages-sgl));
+ ring-status_page.obj = NULL;
+ }
}
static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs
*ring)
{
- /* TODO */
+ int ret;
+ struct intel_context *dctx = ring-default_context;
+ struct drm_i915_gem_object *dctx_obj;
+
+ /* Intentionally left blank. */
+ ring-buffer = NULL;
+
+ ring-dev = dev;
+ INIT_LIST_HEAD(ring-active_list);
+ INIT_LIST_HEAD(ring-request_list);
+ init_waitqueue_head(ring-irq_queue);
+
+ ret = intel_lr_context_deferred_create(dctx, ring);
+ if (ret)
+ return ret;
+
+ /* The status page is offset 0 from the context object in LRCs. */
+ dctx_obj = dctx-engine[ring-id].state;
+ ring-status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj);
+ ring-status_page.page_addr = kmap(sg_page(dctx_obj-pages-sgl));
+ if (ring-status_page.page_addr == NULL)
+ return -ENOMEM;
+ ring-status_page.obj = dctx_obj;
+
+ ret = i915_cmd_parser_init_ring(ring);
+ if (ret)
+ return ret;
+
+ if (ring-init) {
+ ret = ring-init(ring);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
@@ -397,6 +445,8 @@ int intel_lr_context_deferred_create(struct intel_context
*ctx,
int ret;
BUG_ON(ctx-legacy_hw_ctx.rcs_state != NULL);
+ if (ctx-engine[ring-id].state)
+ return 0;
context_size = round_up(get_lr_context_size(ring), 4096);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 279dda4..20eb1a4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -40,6 +40,23 @@
*/
#define CACHELINE_BYTES 64
+bool
+intel_ring_initialized(struct intel_engine_cs *ring)
+{
+ struct drm_device *dev = ring-dev;
+
+ if (!dev)
+ return false;
+
+ if (i915.enable_execlists) {
+ struct intel_context *dctx = ring-default_context;
+ struct intel_ringbuffer *ringbuf =
dctx-engine[ring-id].ringbuf;
+
+ return ringbuf-obj;
+ } else
+ return ring-buffer ring-buffer-obj;
+}
+
static inline int __ring_space(int head, int tail, int size)
{
int space = head - (tail + I915_RING_FREE_SPACE);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index be40788..7203ee2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -288,11 +288,7 @@ struct
[Intel-gfx] [PATCH 21/43] drm/i915/bdw: Emission of requests with logical rings
From: Oscar Mateo oscar.ma...@intel.com
On a previous iteration of this patch, I created an Execlists
version of __i915_add_request and asbtracted it away as a
vfunc. Daniel Vetter wondered then why that was needed:
with the clean split in command submission I expect every
function to know wether it'll submit to an lrc (everything in
intel_lrc.c) or wether it'll submit to a legacy ring (existing
code), so I don't see a need for an add_request vfunc.
The honest, hairy truth is that this patch is the glue keeping
the whole logical ring puzzle together:
- i915_add_request is used by intel_ring_idle, which in turn is
used by i915_gpu_idle, which in turn is used in several places
inside the eviction and gtt codes.
- Also, it is used by i915_gem_check_olr, which is littered all
over i915_gem.c
- ...
If I were to duplicate all the code that directly or indirectly
uses __i915_add_request, I'll end up creating a separate driver.
To show the differences between the existing legacy version and
the new Execlists one, this time I have special-cased
__i915_add_request instead of adding an add_request vfunc. I
hope this helps to untangle this Gordian knot.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 72 --
drivers/gpu/drm/i915/intel_lrc.c | 30 +---
drivers/gpu/drm/i915/intel_lrc.h |1 +
3 files changed, 80 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9560b40..1c83b9c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2327,10 +2327,21 @@ int __i915_add_request(struct intel_engine_cs *ring,
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
struct drm_i915_gem_request *request;
+ struct intel_ringbuffer *ringbuf;
u32 request_ring_position, request_start;
int ret;
- request_start = intel_ring_get_tail(ring-buffer);
+ request = ring-preallocated_lazy_request;
+ if (WARN_ON(request == NULL))
+ return -ENOMEM;
+
+ if (i915.enable_execlists) {
+ struct intel_context *ctx = request-ctx;
+ ringbuf = ctx-engine[ring-id].ringbuf;
+ } else
+ ringbuf = ring-buffer;
+
+ request_start = intel_ring_get_tail(ringbuf);
/*
* Emit any outstanding flushes - execbuf can fail to emit the flush
* after having emitted the batchbuffer command. Hence we need to fix
@@ -2338,24 +2349,32 @@ int __i915_add_request(struct intel_engine_cs *ring,
* is that the flush _must_ happen before the next request, no matter
* what.
*/
- ret = intel_ring_flush_all_caches(ring);
- if (ret)
- return ret;
-
- request = ring-preallocated_lazy_request;
- if (WARN_ON(request == NULL))
- return -ENOMEM;
+ if (i915.enable_execlists) {
+ ret = logical_ring_flush_all_caches(ringbuf);
+ if (ret)
+ return ret;
+ } else {
+ ret = intel_ring_flush_all_caches(ring);
+ if (ret)
+ return ret;
+ }
/* Record the position of the start of the request so that
* should we detect the updated seqno part-way through the
* GPU processing the request, we never over-estimate the
* position of the head.
*/
- request_ring_position = intel_ring_get_tail(ring-buffer);
+ request_ring_position = intel_ring_get_tail(ringbuf);
- ret = ring-add_request(ring);
- if (ret)
- return ret;
+ if (i915.enable_execlists) {
+ ret = ring-emit_request(ringbuf);
+ if (ret)
+ return ret;
+ } else {
+ ret = ring-add_request(ring);
+ if (ret)
+ return ret;
+ }
request-seqno = intel_ring_get_seqno(ring);
request-ring = ring;
@@ -2370,12 +2389,14 @@ int __i915_add_request(struct intel_engine_cs *ring,
*/
request-batch_obj = obj;
- /* Hold a reference to the current context so that we can inspect
-* it later in case a hangcheck error event fires.
-*/
- request-ctx = ring-last_context;
- if (request-ctx)
- i915_gem_context_reference(request-ctx);
+ if (!i915.enable_execlists) {
+ /* Hold a reference to the current context so that we can
inspect
+* it later in case a hangcheck error event fires.
+*/
+ request-ctx = ring-last_context;
+ if (request-ctx)
+ i915_gem_context_reference(request-ctx);
+ }
request-emitted_jiffies = jiffies;
list_add_tail(request-list, ring-request_list);
@@ -2630,6 +2651,7 @@
[Intel-gfx] [PATCH 14/43] drm/i915/bdw: Skeleton for the new logical rings submission path
From: Oscar Mateo oscar.ma...@intel.com
Execlists are indeed a brave new world with respect to workload
submission to the GPU.
In previous version of these series, I have tried to impact the
legacy ringbuffer submission path as little as possible (mostly,
passing the context around and using the correct ringbuffer when I
needed one) but Daniel is afraid (probably with a reason) that
these changes and, especially, future ones, will end up breaking
older gens.
This commit and some others coming next will try to limit the
damage by creating an alternative path for workload submission.
The first step is here: laying out a new ring init/fini.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c |5 ++
drivers/gpu/drm/i915/intel_lrc.c | 151 ++
drivers/gpu/drm/i915/intel_lrc.h | 12 +++
3 files changed, 168 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6544286..9560b40 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4764,6 +4764,11 @@ int i915_gem_init(struct drm_device *dev)
dev_priv-gt.init_rings = i915_gem_init_rings;
dev_priv-gt.cleanup_ring = intel_cleanup_ring_buffer;
dev_priv-gt.stop_ring = intel_stop_ring_buffer;
+ } else {
+ dev_priv-gt.do_execbuf = intel_execlists_submission;
+ dev_priv-gt.init_rings = intel_logical_rings_init;
+ dev_priv-gt.cleanup_ring = intel_logical_ring_cleanup;
+ dev_priv-gt.stop_ring = intel_logical_ring_stop;
}
i915_gem_init_userptr(dev);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cf322ec..cb56bb8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -89,6 +89,157 @@ int intel_sanitize_enable_execlists(struct drm_device *dev,
int enable_execlists
return 0;
}
+int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
+ struct intel_engine_cs *ring,
+ struct intel_context *ctx,
+ struct drm_i915_gem_execbuffer2 *args,
+ struct list_head *vmas,
+ struct drm_i915_gem_object *batch_obj,
+ u64 exec_start, u32 flags)
+{
+ /* TODO */
+ return 0;
+}
+
+void intel_logical_ring_stop(struct intel_engine_cs *ring)
+{
+ /* TODO */
+}
+
+void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
+{
+ /* TODO */
+}
+
+static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs
*ring)
+{
+ /* TODO */
+ return 0;
+}
+
+static int logical_render_ring_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring = dev_priv-ring[RCS];
+
+ ring-name = render ring;
+ ring-id = RCS;
+ ring-mmio_base = RENDER_RING_BASE;
+ ring-irq_enable_mask =
+ GT_RENDER_USER_INTERRUPT GEN8_RCS_IRQ_SHIFT;
+
+ return logical_ring_init(dev, ring);
+}
+
+static int logical_bsd_ring_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring = dev_priv-ring[VCS];
+
+ ring-name = bsd ring;
+ ring-id = VCS;
+ ring-mmio_base = GEN6_BSD_RING_BASE;
+ ring-irq_enable_mask =
+ GT_RENDER_USER_INTERRUPT GEN8_VCS1_IRQ_SHIFT;
+
+ return logical_ring_init(dev, ring);
+}
+
+static int logical_bsd2_ring_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring = dev_priv-ring[VCS2];
+
+ ring-name = bds2 ring;
+ ring-id = VCS2;
+ ring-mmio_base = GEN8_BSD2_RING_BASE;
+ ring-irq_enable_mask =
+ GT_RENDER_USER_INTERRUPT GEN8_VCS2_IRQ_SHIFT;
+
+ return logical_ring_init(dev, ring);
+}
+
+static int logical_blt_ring_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring = dev_priv-ring[BCS];
+
+ ring-name = blitter ring;
+ ring-id = BCS;
+ ring-mmio_base = BLT_RING_BASE;
+ ring-irq_enable_mask =
+ GT_RENDER_USER_INTERRUPT GEN8_BCS_IRQ_SHIFT;
+
+ return logical_ring_init(dev, ring);
+}
+
+static int logical_vebox_ring_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring = dev_priv-ring[VECS];
+
+ ring-name = video enhancement ring;
+ ring-id = VECS;
+ ring-mmio_base = VEBOX_RING_BASE;
+ ring-irq_enable_mask =
+ GT_RENDER_USER_INTERRUPT GEN8_VECS_IRQ_SHIFT;
+
+ return logical_ring_init(dev, ring);
+}
+
+int
[Intel-gfx] [PATCH 29/43] drm/i915/bdw: Write the tail pointer, LRC style
From: Oscar Mateo oscar.ma...@intel.com
Each logical ring context has the tail pointer in the context object,
so update it before submission.
v2: New namespace.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 535ef98..5b6f416 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -176,6 +176,21 @@ static void execlists_elsp_write(struct intel_engine_cs
*ring,
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
+static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32
tail)
+{
+ struct page *page;
+ uint32_t *reg_state;
+
+ page = i915_gem_object_get_page(ctx_obj, 1);
+ reg_state = kmap_atomic(page);
+
+ reg_state[CTX_RING_TAIL+1] = tail;
+
+ kunmap_atomic(reg_state);
+
+ return 0;
+}
+
static int execlists_submit_context(struct intel_engine_cs *ring,
struct intel_context *to0, u32 tail0,
struct intel_context *to1, u32 tail1)
@@ -187,10 +202,14 @@ static int execlists_submit_context(struct
intel_engine_cs *ring,
BUG_ON(!ctx_obj0);
BUG_ON(!i915_gem_obj_is_pinned(ctx_obj0));
+ execlists_ctx_write_tail(ctx_obj0, tail0);
+
if (to1) {
ctx_obj1 = to1-engine[ring-id].state;
BUG_ON(!ctx_obj1);
BUG_ON(!i915_gem_obj_is_pinned(ctx_obj1));
+
+ execlists_ctx_write_tail(ctx_obj1, tail1);
}
execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
--
1.7.9.5
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[Intel-gfx] [PATCH 25/43] drm/i915/bdw: Workload submission mechanism for Execlists
From: Oscar Mateo oscar.ma...@intel.com
This is what i915_gem_do_execbuffer calls when it wants to execute some
worload in an Execlists world.
v2: Check arguments before doing stuff in intel_execlists_submission. Also,
get rel_constants parsing right.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|6 ++
drivers/gpu/drm/i915/i915_gem_execbuffer.c |4 +-
drivers/gpu/drm/i915/intel_lrc.c | 130 +++-
3 files changed, 137 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1caed52..4303e2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2239,6 +2239,12 @@ int i915_gem_set_domain_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
+ struct intel_engine_cs *ring);
+void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
+struct drm_file *file,
+struct intel_engine_cs *ring,
+struct drm_i915_gem_object *obj);
int i915_gem_ringbuffer_submission(struct drm_device *dev,
struct drm_file *file,
struct intel_engine_cs *ring,
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 8c63d79..cae7df8 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -962,7 +962,7 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
return ctx;
}
-static void
+void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
struct intel_engine_cs *ring)
{
@@ -994,7 +994,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
}
}
-static void
+void
i915_gem_execbuffer_retire_commands(struct drm_device *dev,
struct drm_file *file,
struct intel_engine_cs *ring,
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 55ee8dd..cd834b3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -89,6 +89,57 @@ int intel_sanitize_enable_execlists(struct drm_device *dev,
int enable_execlists
return 0;
}
+static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ uint32_t flush_domains;
+ int ret;
+
+ flush_domains = 0;
+ if (ring-gpu_caches_dirty)
+ flush_domains = I915_GEM_GPU_DOMAINS;
+
+ ret = ring-emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains);
+ if (ret)
+ return ret;
+
+ ring-gpu_caches_dirty = false;
+ return 0;
+}
+
+static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
+struct list_head *vmas)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ struct i915_vma *vma;
+ uint32_t flush_domains = 0;
+ bool flush_chipset = false;
+ int ret;
+
+ list_for_each_entry(vma, vmas, exec_list) {
+ struct drm_i915_gem_object *obj = vma-obj;
+ ret = i915_gem_object_sync(obj, ring);
+ if (ret)
+ return ret;
+
+ if (obj-base.write_domain I915_GEM_DOMAIN_CPU)
+ flush_chipset |= i915_gem_clflush_object(obj, false);
+
+ flush_domains |= obj-base.write_domain;
+ }
+
+ if (flush_chipset)
+ i915_gem_chipset_flush(ring-dev);
+
+ if (flush_domains I915_GEM_DOMAIN_GTT)
+ wmb();
+
+ /* Unconditionally invalidate gpu caches and ensure that we do flush
+* any residual writes from the previous batch.
+*/
+ return logical_ring_invalidate_all_caches(ringbuf);
+}
+
int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
struct intel_engine_cs *ring,
struct intel_context *ctx,
@@ -97,7 +148,84 @@ int intel_execlists_submission(struct drm_device *dev,
struct drm_file *file,
struct drm_i915_gem_object *batch_obj,
u64 exec_start, u32 flags)
{
- /* TODO */
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ringbuffer *ringbuf = ctx-engine[ring-id].ringbuf;
+ int instp_mode;
+ u32 instp_mask;
+ int ret;
+
+ instp_mode = args-flags
[Intel-gfx] [PATCH 22/43] drm/i915/bdw: Ring idle and stop with logical rings
From: Oscar Mateo oscar.ma...@intel.com
This is a hard one, since there is no direct hardware ring to
control when in Execlists.
We reuse intel_ring_idle here, but it should be fine as long
as i915_add_request does the ring thing.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dcf59c6..c30518c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -103,7 +103,24 @@ int intel_execlists_submission(struct drm_device *dev,
struct drm_file *file,
void intel_logical_ring_stop(struct intel_engine_cs *ring)
{
- /* TODO */
+ struct drm_i915_private *dev_priv = ring-dev-dev_private;
+ int ret;
+
+ if (!intel_ring_initialized(ring))
+ return;
+
+ ret = intel_ring_idle(ring);
+ if (ret !i915_reset_in_progress(to_i915(ring-dev)-gpu_error))
+ DRM_ERROR(failed to quiesce %s whilst cleaning up: %d\n,
+ ring-name, ret);
+
+ /* TODO: Is this correct with Execlists enabled? */
+ I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
+ if (wait_for_atomic((I915_READ_MODE(ring) MODE_IDLE) != 0, 1000)) {
+ DRM_ERROR(%s :timed out trying to stop ring\n, ring-name);
+ return;
+ }
+ I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
}
int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
@@ -479,10 +496,13 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf)
void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
{
+ struct drm_i915_private *dev_priv = ring-dev-dev_private;
+
if (!intel_ring_initialized(ring))
return;
- /* TODO: make sure the ring is stopped */
+ intel_logical_ring_stop(ring);
+ WARN_ON((I915_READ_MODE(ring) MODE_IDLE) == 0);
ring-preallocated_lazy_request = NULL;
ring-outstanding_lazy_seqno = 0;
--
1.7.9.5
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[Intel-gfx] [PATCH 28/43] drm/i915/bdw: Implement context switching (somewhat)
From: Ben Widawsky benjamin.widaw...@intel.com
A context switch occurs by submitting a context descriptor to the
ExecList Submission Port. Given that we can now initialize a context,
it's possible to begin implementing the context switch by creating the
descriptor and submitting it to ELSP (actually two, since the ELSP
has two ports).
The context object must be mapped in the GGTT, which means it must exist
in the 0-4GB graphics VA range.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
v2: This code has changed quite a lot in various rebases. Of particular
importance is that now we use the globally unique Submission ID to send
to the hardware. Also, context pages are now pinned unconditionally to
GGTT, so there is no need to bind them.
v3: Use LRCA[31:12] as hwCtxId[19:0]. This guarantees that the HW context
ID we submit to the ELSP is globally unique and != 0 (Bspec requirements
of the software use-only bits of the Context ID in the Context Descriptor
Format) without the hassle of the previous submission Id construction.
Also, re-add the ELSP porting read (it was dropped somewhere during the
rebases).
v4:
- Squash with drm/i915/bdw: Add forcewake lock around ELSP writes (BSPEC
says: SW must set Force Wakeup bit to prevent GT from entering C6 while
ELSP writes are in progress) as noted by Thomas Daniel
(thomas.dan...@intel.com).
- Rename functions and use an execlists/intel_execlists_ namespace.
- The BUG_ON only checked that the LRCA was 32 bits, but it didn't make
sure that it was properly aligned. Spotted by Alistair Mcaulay
alistair.mcau...@intel.com.
v5:
- Improved source code comments as suggested by Chris Wilson.
- No need to abstract submit_ctx away, as pointed by Brad Volkin.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 116 +-
drivers/gpu/drm/i915/intel_lrc.h |1 +
2 files changed, 115 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4549eec..535ef98 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -47,6 +47,7 @@
#define GEN8_LR_CONTEXT_ALIGN 4096
#define RING_ELSP(ring)((ring)-mmio_base+0x230)
+#define RING_EXECLIST_STATUS(ring) ((ring)-mmio_base+0x234)
#define RING_CONTEXT_CONTROL(ring) ((ring)-mmio_base+0x244)
#define CTX_LRI_HEADER_0 0x01
@@ -78,6 +79,26 @@
#define CTX_R_PWR_CLK_STATE0x42
#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
+#define GEN8_CTX_VALID (10)
+#define GEN8_CTX_FORCE_PD_RESTORE (11)
+#define GEN8_CTX_FORCE_RESTORE (12)
+#define GEN8_CTX_L3LLC_COHERENT (15)
+#define GEN8_CTX_PRIVILEGE (18)
+enum {
+ ADVANCED_CONTEXT=0,
+ LEGACY_CONTEXT,
+ ADVANCED_AD_CONTEXT,
+ LEGACY_64B_CONTEXT
+};
+#define GEN8_CTX_MODE_SHIFT 3
+enum {
+ FAULT_AND_HANG=0,
+ FAULT_AND_HALT, /* Debug only */
+ FAULT_AND_STREAM,
+ FAULT_AND_CONTINUE /* Unsupported */
+};
+#define GEN8_CTX_ID_SHIFT 32
+
int intel_sanitize_enable_execlists(struct drm_device *dev, int
enable_execlists)
{
if (enable_execlists == 0)
@@ -90,6 +111,93 @@ int intel_sanitize_enable_execlists(struct drm_device *dev,
int enable_execlists
return 0;
}
+u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
+{
+ u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
+
+ /* LRCA is required to be 4K aligned so the more significant 20 bits
+* are globally unique */
+ return lrca 12;
+}
+
+static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
+{
+ uint64_t desc;
+ uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
+ BUG_ON(lrca 0x0FFFULL);
+
+ desc = GEN8_CTX_VALID;
+ desc |= LEGACY_CONTEXT GEN8_CTX_MODE_SHIFT;
+ desc |= GEN8_CTX_L3LLC_COHERENT;
+ desc |= GEN8_CTX_PRIVILEGE;
+ desc |= lrca;
+ desc |= (u64)intel_execlists_ctx_id(ctx_obj) GEN8_CTX_ID_SHIFT;
+
+ /* TODO: WaDisableLiteRestore when we start using semaphore
+* signalling between Command Streamers */
+ /* desc |= GEN8_CTX_FORCE_RESTORE; */
+
+ return desc;
+}
+
+static void execlists_elsp_write(struct intel_engine_cs *ring,
+struct drm_i915_gem_object *ctx_obj0,
+struct drm_i915_gem_object *ctx_obj1)
+{
+ struct drm_i915_private *dev_priv = ring-dev-dev_private;
+ uint64_t temp = 0;
+ uint32_t desc[4];
+
+ /* XXX: You must always write both descriptors in the order below. */
+ if (ctx_obj1)
+ temp = execlists_ctx_descriptor(ctx_obj1);
+ else
+ temp = 0;
+ desc[1] = (u32)(temp 32);
+ desc[0] = (u32)temp;
+
+ temp = execlists_ctx_descriptor(ctx_obj0);
+ desc[3] = (u32)(temp 32);
+ desc[2] = (u32)temp;
+
+ /* Set Force Wakeup bit to
[Intel-gfx] [PATCH 26/43] drm/i915/bdw: Always use MMIO flips with Execlists
From: Oscar Mateo oscar.ma...@intel.com The normal flip function places things in the ring in the legacy way, so we either fix that or force MMIO flips always as we do in this patch. Signed-off-by: Oscar Mateo oscar.ma...@intel.com --- drivers/gpu/drm/i915/intel_display.c |2 ++ drivers/gpu/drm/i915/intel_lrc.c |3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5ed6a1a..8129af4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9482,6 +9482,8 @@ static bool use_mmio_flip(struct intel_engine_cs *ring, return false; else if (i915.use_mmio_flip 0) return true; + else if (i915.enable_execlists) + return true; else return ring != obj-ring; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index cd834b3..0a04c03 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -83,7 +83,8 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists if (enable_execlists == 0) return 0; - if (HAS_LOGICAL_RING_CONTEXTS(dev) USES_PPGTT(dev)) + if (HAS_LOGICAL_RING_CONTEXTS(dev) USES_PPGTT(dev) + i915.use_mmio_flip = 0) return 1; return 0; -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 41/43] drm/i915/bdw: Enable Logical Ring Contexts (hence, Execlists)
From: Oscar Mateo oscar.ma...@intel.com
The time has come, the Walrus said, to talk of many things.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7cf0ec..1ce51d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2061,7 +2061,7 @@ struct drm_i915_cmd_table {
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)-need_gfx_hws)
#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)-gen = 6)
-#define HAS_LOGICAL_RING_CONTEXTS(dev) 0
+#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)-gen = 8)
#define HAS_ALIASING_PPGTT(dev)(INTEL_INFO(dev)-gen = 6)
#define HAS_PPGTT(dev) (INTEL_INFO(dev)-gen = 7 !IS_GEN8(dev))
#define USES_PPGTT(dev)intel_enable_ppgtt(dev, false)
--
1.7.9.5
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[Intel-gfx] [PATCH 23/43] drm/i915/bdw: Interrupts with logical rings
From: Oscar Mateo oscar.ma...@intel.com
We need to attend context switch interrupts from all rings. Also, fixed writing
IMR/IER and added HWSTAM at ring init time.
Notice that, if added to irq_enable_mask, the context switch interrupts would
be incorrectly masked out when the user interrupts are due to no users waiting
on a sequence number. Therefore, this commit adds a bitmask of interrupts to
be kept unmasked at all times.
v2: Disable HWSTAM, as suggested by Damien (nobody listens to these interrupts,
anyway).
v3: Add new get/put_irq functions.
Signed-off-by: Thomas Daniel thomas.dan...@intel.com (v1)
Signed-off-by: Oscar Mateo oscar.ma...@intel.com (v2 v3)
---
drivers/gpu/drm/i915/i915_irq.c | 19 --
drivers/gpu/drm/i915/i915_reg.h |3 ++
drivers/gpu/drm/i915/intel_lrc.c| 58 +++
drivers/gpu/drm/i915/intel_ringbuffer.h |1 +
4 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a38b5c3..f77a4ca 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1643,6 +1643,8 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device
*dev,
notify_ring(dev, dev_priv-ring[RCS]);
if (bcs GT_RENDER_USER_INTERRUPT)
notify_ring(dev, dev_priv-ring[BCS]);
+ if ((rcs | bcs) GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
+ DRM_DEBUG_DRIVER(TODO: Context switch\n);
} else
DRM_ERROR(The master control interrupt lied (GT0)!\n);
}
@@ -1655,9 +1657,13 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device
*dev,
vcs = tmp GEN8_VCS1_IRQ_SHIFT;
if (vcs GT_RENDER_USER_INTERRUPT)
notify_ring(dev, dev_priv-ring[VCS]);
+ if (vcs GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
+ DRM_DEBUG_DRIVER(TODO: Context switch\n);
vcs = tmp GEN8_VCS2_IRQ_SHIFT;
if (vcs GT_RENDER_USER_INTERRUPT)
notify_ring(dev, dev_priv-ring[VCS2]);
+ if (vcs GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
+ DRM_DEBUG_DRIVER(TODO: Context switch\n);
} else
DRM_ERROR(The master control interrupt lied (GT1)!\n);
}
@@ -1681,6 +1687,8 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device
*dev,
vcs = tmp GEN8_VECS_IRQ_SHIFT;
if (vcs GT_RENDER_USER_INTERRUPT)
notify_ring(dev, dev_priv-ring[VECS]);
+ if (vcs GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
+ DRM_DEBUG_DRIVER(TODO: Context switch\n);
} else
DRM_ERROR(The master control interrupt lied (GT3)!\n);
}
@@ -3768,12 +3776,17 @@ static void gen8_gt_irq_postinstall(struct
drm_i915_private *dev_priv)
/* These are interrupts we'll toggle with the ring mask register */
uint32_t gt_interrupts[] = {
GT_RENDER_USER_INTERRUPT GEN8_RCS_IRQ_SHIFT |
+ GEN8_GT_CONTEXT_SWITCH_INTERRUPT GEN8_RCS_IRQ_SHIFT |
GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
- GT_RENDER_USER_INTERRUPT GEN8_BCS_IRQ_SHIFT,
+ GT_RENDER_USER_INTERRUPT GEN8_BCS_IRQ_SHIFT |
+ GEN8_GT_CONTEXT_SWITCH_INTERRUPT GEN8_BCS_IRQ_SHIFT,
GT_RENDER_USER_INTERRUPT GEN8_VCS1_IRQ_SHIFT |
- GT_RENDER_USER_INTERRUPT GEN8_VCS2_IRQ_SHIFT,
+ GEN8_GT_CONTEXT_SWITCH_INTERRUPT GEN8_VCS1_IRQ_SHIFT
|
+ GT_RENDER_USER_INTERRUPT GEN8_VCS2_IRQ_SHIFT |
+ GEN8_GT_CONTEXT_SWITCH_INTERRUPT GEN8_VCS2_IRQ_SHIFT,
0,
- GT_RENDER_USER_INTERRUPT GEN8_VECS_IRQ_SHIFT
+ GT_RENDER_USER_INTERRUPT GEN8_VECS_IRQ_SHIFT |
+ GEN8_GT_CONTEXT_SWITCH_INTERRUPT GEN8_VECS_IRQ_SHIFT
};
for (i = 0; i ARRAY_SIZE(gt_interrupts); i++)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70dddac..bfc0c01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1062,6 +1062,7 @@ enum punit_power_well {
#define RING_ACTHD_UDW(base) ((base)+0x5c)
#define RING_NOPID(base) ((base)+0x94)
#define RING_IMR(base) ((base)+0xa8)
+#define RING_HWSTAM(base) ((base)+0x98)
#define RING_TIMESTAMP(base) ((base)+0x358)
#define TAIL_ADDR0x0018
#define HEAD_WRAP_COUNT 0xFFE0
@@ -4590,6 +4591,8 @@ enum punit_power_well {
#define GEN8_GT_IIR(which)
[Intel-gfx] [PATCH 17/43] drm/i915/bdw: GEN-specific logical ring set/get seqno
From: Oscar Mateo oscar.ma...@intel.com
No mistery here: the seqno is still retrieved from the engine's
HW status page (the one in the default context. For the moment,
I see no reason to worry about other context's HWS page).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7c8b75e..f171fd5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -149,6 +149,16 @@ static int gen8_init_render_ring(struct intel_engine_cs
*ring)
return ret;
}
+static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
+{
+ return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
+}
+
+static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
+{
+ intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
+}
+
void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
{
if (!intel_ring_initialized(ring))
@@ -221,6 +231,8 @@ static int logical_render_ring_init(struct drm_device *dev)
ring-init = gen8_init_render_ring;
ring-cleanup = intel_fini_pipe_control;
+ ring-get_seqno = gen8_get_seqno;
+ ring-set_seqno = gen8_set_seqno;
return logical_ring_init(dev, ring);
}
@@ -237,6 +249,8 @@ static int logical_bsd_ring_init(struct drm_device *dev)
GT_RENDER_USER_INTERRUPT GEN8_VCS1_IRQ_SHIFT;
ring-init = gen8_init_common_ring;
+ ring-get_seqno = gen8_get_seqno;
+ ring-set_seqno = gen8_set_seqno;
return logical_ring_init(dev, ring);
}
@@ -253,6 +267,8 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
GT_RENDER_USER_INTERRUPT GEN8_VCS2_IRQ_SHIFT;
ring-init = gen8_init_common_ring;
+ ring-get_seqno = gen8_get_seqno;
+ ring-set_seqno = gen8_set_seqno;
return logical_ring_init(dev, ring);
}
@@ -269,6 +285,8 @@ static int logical_blt_ring_init(struct drm_device *dev)
GT_RENDER_USER_INTERRUPT GEN8_BCS_IRQ_SHIFT;
ring-init = gen8_init_common_ring;
+ ring-get_seqno = gen8_get_seqno;
+ ring-set_seqno = gen8_set_seqno;
return logical_ring_init(dev, ring);
}
@@ -285,6 +303,8 @@ static int logical_vebox_ring_init(struct drm_device *dev)
GT_RENDER_USER_INTERRUPT GEN8_VECS_IRQ_SHIFT;
ring-init = gen8_init_common_ring;
+ ring-get_seqno = gen8_get_seqno;
+ ring-set_seqno = gen8_set_seqno;
return logical_ring_init(dev, ring);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 39/43] drm/i915/bdw: Print context state in debugfs
From: Ben Widawsky b...@bwidawsk.net
This has turned out to be really handy in debug so far.
Update:
Since writing this patch, I've gotten similar code upstream for error
state. I've used it quite a bit in debugfs however, and I'd like to keep
it here at least until preemption is working.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
This patch was accidentally dropped in the first Execlists version, and
it has been very useful indeed. Put it back again, but as a standalone
debugfs file.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0980cdd..968c3c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1695,6 +1695,57 @@ static int i915_context_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_dump_lrc(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m-private;
+ struct drm_device *dev = node-minor-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring;
+ struct intel_context *ctx;
+ int ret, i;
+
+ if (!i915.enable_execlists) {
+ seq_printf(m, Logical Ring Contexts are disabled\n);
+ return 0;
+ }
+
+ ret = mutex_lock_interruptible(dev-mode_config.mutex);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(ctx, dev_priv-context_list, link) {
+ for_each_ring(ring, dev_priv, i) {
+ struct drm_i915_gem_object *ctx_obj =
ctx-engine[i].state;
+
+ if (ring-default_context == ctx)
+ continue;
+
+ if (ctx_obj) {
+ struct page *page =
i915_gem_object_get_page(ctx_obj, 1);
+ uint32_t *reg_state = kmap_atomic(page);
+ int j;
+
+ seq_printf(m, CONTEXT: %s %u\n, ring-name,
+
intel_execlists_ctx_id(ctx_obj));
+
+ for (j = 0; j 0x600 / sizeof(u32) / 4; j +=
4) {
+ seq_printf(m, \t[0x%08lx] 0x%08x
0x%08x 0x%08x 0x%08x\n,
+ i915_gem_obj_ggtt_offset(ctx_obj) +
4096 + (j * 4),
+ reg_state[j], reg_state[j + 1],
+ reg_state[j + 2], reg_state[j + 3]);
+ }
+ kunmap_atomic(reg_state);
+
+ seq_putc(m, '\n');
+ }
+ }
+ }
+
+ mutex_unlock(dev-mode_config.mutex);
+
+ return 0;
+}
+
static int i915_execlists(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m-private;
@@ -3992,6 +4043,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{i915_opregion, i915_opregion, 0},
{i915_gem_framebuffer, i915_gem_framebuffer_info, 0},
{i915_context_status, i915_context_status, 0},
+ {i915_dump_lrc, i915_dump_lrc, 0},
{i915_execlists, i915_execlists, 0},
{i915_gen6_forcewake_count, i915_gen6_forcewake_count_info, 0},
{i915_swizzle_info, i915_swizzle_info, 0},
--
1.7.9.5
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[Intel-gfx] [PATCH 35/43] drm/i915/bdw: Make sure error capture keeps working with Execlists
From: Oscar Mateo oscar.ma...@intel.com
Since the ringbuffer does not belong per engine anymore, we have to
make sure that we are always recording the correct ringbuffer.
TODO: This is only a small fix to keep basic error capture working, but
we need to add more information for it to be useful (e.g. dump the
context being executed).
v2: Reorder how the ringbuffer is chosen to clarify the change and
rename the variable, both changes suggested by Chris Wilson. Also,
add the TODO comment to the code, as suggested by Daniel.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 45b6191..1e38576 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -874,9 +874,6 @@ static void i915_record_ring_state(struct drm_device *dev,
ering-hws = I915_READ(mmio);
}
- ering-cpu_ring_head = ring-buffer-head;
- ering-cpu_ring_tail = ring-buffer-tail;
-
ering-hangcheck_score = ring-hangcheck.score;
ering-hangcheck_action = ring-hangcheck.action;
@@ -936,6 +933,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
for (i = 0; i I915_NUM_RINGS; i++) {
struct intel_engine_cs *ring = dev_priv-ring[i];
+ struct intel_ringbuffer *rbuf;
error-ring[i].pid = -1;
@@ -979,8 +977,24 @@ static void i915_gem_record_rings(struct drm_device *dev,
}
}
+ if (i915.enable_execlists) {
+ /* TODO: This is only a small fix to keep basic error
+* capture working, but we need to add more information
+* for it to be useful (e.g. dump the context being
+* executed).
+*/
+ if (request)
+ rbuf = request-ctx-engine[ring-id].ringbuf;
+ else
+ rbuf =
ring-default_context-engine[ring-id].ringbuf;
+ } else
+ rbuf = ring-buffer;
+
+ error-ring[i].cpu_ring_head = rbuf-head;
+ error-ring[i].cpu_ring_tail = rbuf-tail;
+
error-ring[i].ringbuffer =
- i915_error_ggtt_object_create(dev_priv,
ring-buffer-obj);
+ i915_error_ggtt_object_create(dev_priv, rbuf-obj);
if (ring-status_page.obj)
error-ring[i].hws_page =
--
1.7.9.5
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[Intel-gfx] [PATCH 30/43] drm/i915/bdw: Two-stage execlist submit process
From: Michel Thierry michel.thie...@intel.com
Context switch (and execlist submission) should happen only when
other contexts are not active, otherwise pre-emption occurs.
To assure this, we place context switch requests in a queue and those
request are later consumed when the right context switch interrupt is
received (still TODO).
v2: Use a spinlock, do not remove the requests on unqueue (wait for
context switch completion).
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
v3: Several rebases and code changes. Use unique ID.
v4:
- Move the queue/lock init to the late ring initialization.
- Damien's kmalloc review comments: check return, use sizeof(*req),
do not cast.
v5:
- Do not reuse drm_i915_gem_request. Instead, create our own.
- New namespace.
Signed-off-by: Michel Thierry michel.thie...@intel.com (v1)
Signed-off-by: Oscar Mateo oscar.ma...@intel.com (v2-v5)
---
drivers/gpu/drm/i915/intel_lrc.c| 63 ++-
drivers/gpu/drm/i915/intel_lrc.h|8
drivers/gpu/drm/i915/intel_ringbuffer.h |2 +
3 files changed, 71 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5b6f416..9e91169 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -217,6 +217,63 @@ static int execlists_submit_context(struct intel_engine_cs
*ring,
return 0;
}
+static void execlists_context_unqueue(struct intel_engine_cs *ring)
+{
+ struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL;
+ struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL;
+
+ if (list_empty(ring-execlist_queue))
+ return;
+
+ /* Try to read in pairs */
+ list_for_each_entry_safe(cursor, tmp, ring-execlist_queue,
execlist_link) {
+ if (!req0)
+ req0 = cursor;
+ else if (req0-ctx == cursor-ctx) {
+ /* Same ctx: ignore first request, as second request
+* will update tail past first request's workload */
+ list_del(req0-execlist_link);
+ i915_gem_context_unreference(req0-ctx);
+ kfree(req0);
+ req0 = cursor;
+ } else {
+ req1 = cursor;
+ break;
+ }
+ }
+
+ BUG_ON(execlists_submit_context(ring, req0-ctx, req0-tail,
+ req1? req1-ctx : NULL, req1? req1-tail : 0));
+}
+
+static int execlists_context_queue(struct intel_engine_cs *ring,
+ struct intel_context *to,
+ u32 tail)
+{
+ struct intel_ctx_submit_request *req = NULL;
+ unsigned long flags;
+ bool was_empty;
+
+ req = kzalloc(sizeof(*req), GFP_KERNEL);
+ if (req == NULL)
+ return -ENOMEM;
+ req-ctx = to;
+ i915_gem_context_reference(req-ctx);
+ req-ring = ring;
+ req-tail = tail;
+
+ spin_lock_irqsave(ring-execlist_lock, flags);
+
+ was_empty = list_empty(ring-execlist_queue);
+ list_add_tail(req-execlist_link, ring-execlist_queue);
+ if (was_empty)
+ execlists_context_unqueue(ring);
+
+ spin_unlock_irqrestore(ring-execlist_lock, flags);
+
+ return 0;
+}
+
static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
{
struct intel_engine_cs *ring = ringbuf-ring;
@@ -405,8 +462,7 @@ void intel_logical_ring_advance_and_submit(struct
intel_ringbuffer *ringbuf)
if (intel_ring_stopped(ring))
return;
- /* FIXME: too cheeky, we don't even check if the ELSP is ready */
- execlists_submit_context(ring, ctx, ringbuf-tail, NULL, 0);
+ execlists_context_queue(ring, ctx, ringbuf-tail);
}
static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
@@ -850,6 +906,9 @@ static int logical_ring_init(struct drm_device *dev, struct
intel_engine_cs *rin
INIT_LIST_HEAD(ring-request_list);
init_waitqueue_head(ring-irq_queue);
+ INIT_LIST_HEAD(ring-execlist_queue);
+ spin_lock_init(ring-execlist_lock);
+
ret = intel_lr_context_deferred_create(dctx, ring);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index b59965b..14492a9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -60,4 +60,12 @@ int intel_execlists_submission(struct drm_device *dev,
struct drm_file *file,
u64 exec_start, u32 flags);
u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
+struct intel_ctx_submit_request {
+ struct intel_context *ctx;
+ struct intel_engine_cs *ring;
+ u32 tail;
+
+ struct list_head execlist_link;
+};
+
#endif /* _INTEL_LRC_H_ */
diff --git
[Intel-gfx] [PATCH 31/43] drm/i915/bdw: Handle context switch events
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on interrupt when a previously submitted
context completes (unless no contexts are queued, which means the GPU is
free).
We canot call intel_runtime_pm_get() in an interrupt (or with a spinlock
grabbed, FWIW), because it might sleep, which is not a nice thing to do.
Instead, do the runtime_pm get/put together with the create/destroy request,
and handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately, before trying to handle it (fix for
missing interrupts by Bob Beckett robert.beck...@intel.com).
- Update the Context Status Buffer Read Pointer, just in case (spotted
by Damien Lespiau).
v4: New namespace and multiple rebase changes.
v5: Squash with drm/i915/bdw: Do not call intel_runtime_pm_get() in an
interrupt, as suggested by Daniel.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 35 ++---
drivers/gpu/drm/i915/intel_lrc.c| 129 +--
drivers/gpu/drm/i915/intel_lrc.h|3 +
drivers/gpu/drm/i915/intel_ringbuffer.h |1 +
4 files changed, 151 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f77a4ca..e4077d1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1628,6 +1628,7 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device
*dev,
struct drm_i915_private *dev_priv,
u32 master_ctl)
{
+ struct intel_engine_cs *ring;
u32 rcs, bcs, vcs;
uint32_t tmp = 0;
irqreturn_t ret = IRQ_NONE;
@@ -1637,14 +1638,20 @@ static irqreturn_t gen8_gt_irq_handler(struct
drm_device *dev,
if (tmp) {
I915_WRITE(GEN8_GT_IIR(0), tmp);
ret = IRQ_HANDLED;
+
rcs = tmp GEN8_RCS_IRQ_SHIFT;
- bcs = tmp GEN8_BCS_IRQ_SHIFT;
+ ring = dev_priv-ring[RCS];
if (rcs GT_RENDER_USER_INTERRUPT)
- notify_ring(dev, dev_priv-ring[RCS]);
+ notify_ring(dev, ring);
+ if (rcs GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
+ intel_execlists_handle_ctx_events(ring);
+
+ bcs = tmp GEN8_BCS_IRQ_SHIFT;
+ ring = dev_priv-ring[BCS];
if (bcs GT_RENDER_USER_INTERRUPT)
- notify_ring(dev, dev_priv-ring[BCS]);
- if ((rcs | bcs) GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
- DRM_DEBUG_DRIVER(TODO: Context switch\n);
+ notify_ring(dev, ring);
+ if (bcs GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
+ intel_execlists_handle_ctx_events(ring);
} else
DRM_ERROR(The master control interrupt lied (GT0)!\n);
}
@@ -1654,16 +1661,20 @@ static irqreturn_t gen8_gt_irq_handler(struct
drm_device *dev,
if (tmp) {
I915_WRITE(GEN8_GT_IIR(1), tmp);
ret = IRQ_HANDLED;
+
vcs = tmp GEN8_VCS1_IRQ_SHIFT;
+ ring = dev_priv-ring[VCS];
if (vcs GT_RENDER_USER_INTERRUPT)
- notify_ring(dev, dev_priv-ring[VCS]);
+ notify_ring(dev, ring);
if (vcs GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
- DRM_DEBUG_DRIVER(TODO: Context switch\n);
+ intel_execlists_handle_ctx_events(ring);
+
vcs = tmp GEN8_VCS2_IRQ_SHIFT;
+ ring = dev_priv-ring[VCS2];
if (vcs GT_RENDER_USER_INTERRUPT)
- notify_ring(dev, dev_priv-ring[VCS2]);
+ notify_ring(dev, ring);
if (vcs GEN8_GT_CONTEXT_SWITCH_INTERRUPT)
- DRM_DEBUG_DRIVER(TODO: Context switch\n);
+ intel_execlists_handle_ctx_events(ring);
} else
DRM_ERROR(The master control interrupt lied (GT1)!\n);
}
@@ -1684,11 +1695,13 @@ static irqreturn_t gen8_gt_irq_handler(struct
drm_device *dev,
if (tmp) {
[Intel-gfx] [PATCH 19/43] drm/i915/bdw: GEN-specific logical ring emit request
From: Oscar Mateo oscar.ma...@intel.com
Very similar to the legacy add_request, only modified to account for
logical ringbuffer.
v2: Use MI_GLOBAL_GTT, as suggested by Brad Volkin.
v3: Unify render and non-render in the same function, as noticed by
Brad Volkin.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_lrc.c| 31 +++
drivers/gpu/drm/i915/intel_ringbuffer.h |3 +++
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 043a6ea..70dddac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -272,6 +272,7 @@
#define MI_SEMAPHORE_POLL(115)
#define MI_SEMAPHORE_SAD_GTE_SDD (112)
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
+#define MI_STORE_DWORD_IMM_GEN8MI_INSTR(0x20, 2)
#define MI_MEM_VIRTUAL (1 22) /* 965+ only */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
#define MI_STORE_DWORD_INDEX_SHIFT 2
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bd37d51..64bda7a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -352,6 +352,32 @@ static void gen8_set_seqno(struct intel_engine_cs *ring,
u32 seqno)
intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
}
+static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ u32 cmd;
+ int ret;
+
+ ret = intel_logical_ring_begin(ringbuf, 6);
+ if (ret)
+ return ret;
+
+ cmd = MI_STORE_DWORD_IMM_GEN8;
+ cmd |= MI_GLOBAL_GTT;
+
+ intel_logical_ring_emit(ringbuf, cmd);
+ intel_logical_ring_emit(ringbuf,
+ (ring-status_page.gfx_addr +
+ (I915_GEM_HWS_INDEX
MI_STORE_DWORD_INDEX_SHIFT)));
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, ring-outstanding_lazy_seqno);
+ intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance_and_submit(ringbuf);
+
+ return 0;
+}
+
void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
{
if (!intel_ring_initialized(ring))
@@ -426,6 +452,7 @@ static int logical_render_ring_init(struct drm_device *dev)
ring-cleanup = intel_fini_pipe_control;
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
+ ring-emit_request = gen8_emit_request;
return logical_ring_init(dev, ring);
}
@@ -444,6 +471,7 @@ static int logical_bsd_ring_init(struct drm_device *dev)
ring-init = gen8_init_common_ring;
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
+ ring-emit_request = gen8_emit_request;
return logical_ring_init(dev, ring);
}
@@ -462,6 +490,7 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
ring-init = gen8_init_common_ring;
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
+ ring-emit_request = gen8_emit_request;
return logical_ring_init(dev, ring);
}
@@ -480,6 +509,7 @@ static int logical_blt_ring_init(struct drm_device *dev)
ring-init = gen8_init_common_ring;
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
+ ring-emit_request = gen8_emit_request;
return logical_ring_init(dev, ring);
}
@@ -498,6 +528,7 @@ static int logical_vebox_ring_init(struct drm_device *dev)
ring-init = gen8_init_common_ring;
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
+ ring-emit_request = gen8_emit_request;
return logical_ring_init(dev, ring);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c305df0..176ee6a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -215,6 +215,9 @@ struct intel_engine_cs {
unsigned int num_dwords);
} semaphore;
+ /* Execlists */
+ int (*emit_request)(struct intel_ringbuffer *ringbuf);
+
/**
* List of objects currently involved in rendering from the
* ringbuffer.
--
1.7.9.5
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[Intel-gfx] [PATCH 34/43] drm/i915/bdw: Make sure gpu reset still works with Execlists
From: Oscar Mateo oscar.ma...@intel.com
If we reset a ring after a hang, we have to make sure that we clear
out all queued Execlists requests.
v2: The ring is, at this point, already being correctly re-programmed
for Execlists, and the hangcheck counters cleared.
v3: Daniel suggests to drop the if (execlists) because the Execlists
queue should be empty in legacy mode (which is true, if we do the
INIT_LIST_HEAD).
v4: Do the pending intel_runtime_pm_put
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 12
drivers/gpu/drm/i915/intel_ringbuffer.c |1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1c83b9c..143cff7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2567,6 +2567,18 @@ static void i915_gem_reset_ring_cleanup(struct
drm_i915_private *dev_priv,
i915_gem_free_request(request);
}
+ while (!list_empty(ring-execlist_queue)) {
+ struct intel_ctx_submit_request *submit_req;
+
+ submit_req = list_first_entry(ring-execlist_queue,
+ struct intel_ctx_submit_request,
+ execlist_link);
+ list_del(submit_req-execlist_link);
+ intel_runtime_pm_put(dev_priv);
+ i915_gem_context_unreference(submit_req-ctx);
+ kfree(submit_req);
+ }
+
/* These may not have been flush before the reset, do so now */
kfree(ring-preallocated_lazy_request);
ring-preallocated_lazy_request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3188403..6e604c9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1587,6 +1587,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
ring-dev = dev;
INIT_LIST_HEAD(ring-active_list);
INIT_LIST_HEAD(ring-request_list);
+ INIT_LIST_HEAD(ring-execlist_queue);
ringbuf-size = 32 * PAGE_SIZE;
ringbuf-ring = ring;
ringbuf-ctx = ring-default_context;
--
1.7.9.5
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[Intel-gfx] [PATCH 37/43] drm/i915/bdw: Display execlists info in debugfs
From: Oscar Mateo oscar.ma...@intel.com
v2: Warn and return if LRCs are not enabled.
v3: Grab the Execlists spinlock (noticed by Daniel Vetter).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 73 +++
drivers/gpu/drm/i915/intel_lrc.c|6 ---
drivers/gpu/drm/i915/intel_lrc.h|7
3 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fc39610..903ed67 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1674,6 +1674,78 @@ static int i915_context_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_execlists(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m-private;
+ struct drm_device *dev = node-minor-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring;
+ u32 status_pointer;
+ u8 read_pointer;
+ u8 write_pointer;
+ u32 status;
+ u32 ctx_id;
+ struct list_head *cursor;
+ int ring_id, i;
+
+ if (!i915.enable_execlists) {
+ seq_printf(m, Logical Ring Contexts are disabled\n);
+ return 0;
+ }
+
+ for_each_ring(ring, dev_priv, ring_id) {
+ struct intel_ctx_submit_request *head_req = NULL;
+ int count = 0;
+ unsigned long flags;
+
+ seq_printf(m, %s\n, ring-name);
+
+ status = I915_READ(RING_EXECLIST_STATUS(ring));
+ ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
+ seq_printf(m, \tExeclist status: 0x%08X, context: %u\n,
+ status, ctx_id);
+
+ status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
+ seq_printf(m, \tStatus pointer: 0x%08X\n, status_pointer);
+
+ read_pointer = ring-next_context_status_buffer;
+ write_pointer = status_pointer 0x07;
+ if (read_pointer write_pointer)
+ write_pointer += 6;
+ seq_printf(m, \tRead pointer: 0x%08X, write pointer 0x%08X\n,
+ read_pointer, write_pointer);
+
+ for (i = 0; i 6; i++) {
+ status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
+ ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i
+ 4);
+
+ seq_printf(m, \tStatus buffer %d: 0x%08X, context:
%u\n,
+ i, status, ctx_id);
+ }
+
+ spin_lock_irqsave(ring-execlist_lock, flags);
+ list_for_each(cursor, ring-execlist_queue)
+ count++;
+ head_req = list_first_entry_or_null(ring-execlist_queue,
+ struct intel_ctx_submit_request, execlist_link);
+ spin_unlock_irqrestore(ring-execlist_lock, flags);
+
+ seq_printf(m, \t%d requests in queue\n, count);
+ if (head_req) {
+ struct drm_i915_gem_object *ctx_obj;
+
+ ctx_obj = head_req-ctx-engine[ring_id].state;
+ seq_printf(m, \tHead request id: %u\n,
+ intel_execlists_ctx_id(ctx_obj));
+ seq_printf(m, \tHead request tail: %u\n,
head_req-tail);
+ }
+
+ seq_putc(m, '\n');
+ }
+
+ return 0;
+}
+
static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m-private;
@@ -3899,6 +3971,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{i915_opregion, i915_opregion, 0},
{i915_gem_framebuffer, i915_gem_framebuffer_info, 0},
{i915_context_status, i915_context_status, 0},
+ {i915_execlists, i915_execlists, 0},
{i915_gen6_forcewake_count, i915_gen6_forcewake_count_info, 0},
{i915_swizzle_info, i915_swizzle_info, 0},
{i915_ppgtt_info, i915_ppgtt_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 829b15d..8056fa4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -46,12 +46,6 @@
#define GEN8_LR_CONTEXT_ALIGN 4096
-#define RING_ELSP(ring)((ring)-mmio_base+0x230)
-#define RING_EXECLIST_STATUS(ring) ((ring)-mmio_base+0x234)
-#define RING_CONTEXT_CONTROL(ring) ((ring)-mmio_base+0x244)
-#define RING_CONTEXT_STATUS_BUF(ring) ((ring)-mmio_base+0x370)
-#define RING_CONTEXT_STATUS_PTR(ring) ((ring)-mmio_base+0x3a0)
-
#define RING_EXECLIST_QFULL(1 0x2)
#define RING_EXECLIST1_VALID (1 0x3)
#define RING_EXECLIST0_VALID (1 0x4)
diff --git a/drivers/gpu/drm/i915/intel_lrc.h
[Intel-gfx] [PATCH 24/43] drm/i915/bdw: GEN-specific logical ring emit batchbuffer start
From: Oscar Mateo oscar.ma...@intel.com
Dispatch_execbuffer's evil twin.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c| 28
drivers/gpu/drm/i915/intel_ringbuffer.h |2 ++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a6dcb3a..55ee8dd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -384,6 +384,29 @@ static int gen8_init_render_ring(struct intel_engine_cs
*ring)
return ret;
}
+static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
+ u64 offset, unsigned flags)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ struct drm_i915_private *dev_priv = ring-dev-dev_private;
+ bool ppgtt = dev_priv-mm.aliasing_ppgtt != NULL
+ !(flags I915_DISPATCH_SECURE);
+ int ret;
+
+ ret = intel_logical_ring_begin(ringbuf, 4);
+ if (ret)
+ return ret;
+
+ /* FIXME(BDW): Address space and security selectors. */
+ intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
(ppgtt8));
+ intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
+ intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance(ringbuf);
+
+ return 0;
+}
+
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring-dev;
@@ -615,6 +638,7 @@ static int logical_render_ring_init(struct drm_device *dev)
ring-emit_flush = gen8_emit_flush_render;
ring-irq_get = gen8_logical_ring_get_irq;
ring-irq_put = gen8_logical_ring_put_irq;
+ ring-emit_bb_start = gen8_emit_bb_start;
return logical_ring_init(dev, ring);
}
@@ -639,6 +663,7 @@ static int logical_bsd_ring_init(struct drm_device *dev)
ring-emit_flush = gen8_emit_flush;
ring-irq_get = gen8_logical_ring_get_irq;
ring-irq_put = gen8_logical_ring_put_irq;
+ ring-emit_bb_start = gen8_emit_bb_start;
return logical_ring_init(dev, ring);
}
@@ -663,6 +688,7 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
ring-emit_flush = gen8_emit_flush;
ring-irq_get = gen8_logical_ring_get_irq;
ring-irq_put = gen8_logical_ring_put_irq;
+ ring-emit_bb_start = gen8_emit_bb_start;
return logical_ring_init(dev, ring);
}
@@ -687,6 +713,7 @@ static int logical_blt_ring_init(struct drm_device *dev)
ring-emit_flush = gen8_emit_flush;
ring-irq_get = gen8_logical_ring_get_irq;
ring-irq_put = gen8_logical_ring_put_irq;
+ ring-emit_bb_start = gen8_emit_bb_start;
return logical_ring_init(dev, ring);
}
@@ -711,6 +738,7 @@ static int logical_vebox_ring_init(struct drm_device *dev)
ring-emit_flush = gen8_emit_flush;
ring-irq_get = gen8_logical_ring_get_irq;
ring-irq_put = gen8_logical_ring_put_irq;
+ ring-emit_bb_start = gen8_emit_bb_start;
return logical_ring_init(dev, ring);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 09102b2..c885d5c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -228,6 +228,8 @@ struct intel_engine_cs {
int (*emit_flush)(struct intel_ringbuffer *ringbuf,
u32 invalidate_domains,
u32 flush_domains);
+ int (*emit_bb_start)(struct intel_ringbuffer *ringbuf,
+u64 offset, unsigned flags);
/**
* List of objects currently involved in rendering from the
--
1.7.9.5
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[Intel-gfx] [PATCH 02/43] drm/i915/bdw: New source and header file for LRs, LRCs and Execlists
From: Oscar Mateo oscar.ma...@intel.com Some legacy HW context code assumptions don't make sense for this new submission method, so we will place this stuff in a separate file. Note for reviewers: I've carefully considered the best name for this file and this was my best option (other possibilities were intel_lr_context.c or intel_execlist.c). I am open to a certain bikeshedding on this matter, anyway. And some point in time, it would be a good idea to split intel_lrc.c/.h even further, but for the moment just shove everything together. v2: Change to intel_lrc.c v3: Squash together with the header file addition Signed-off-by: Oscar Mateo oscar.ma...@intel.com --- drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/intel_lrc.c | 42 ++ drivers/gpu/drm/i915/intel_lrc.h | 27 4 files changed, 71 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_lrc.c create mode 100644 drivers/gpu/drm/i915/intel_lrc.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index cad1683..9fee2a0 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -31,6 +31,7 @@ i915-y += i915_cmd_parser.o \ i915_gpu_error.o \ i915_irq.o \ i915_trace_points.o \ + intel_lrc.o \ intel_ringbuffer.o \ intel_uncore.o diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 44a63f3..54c2bd9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -35,6 +35,7 @@ #include i915_reg.h #include intel_bios.h #include intel_ringbuffer.h +#include intel_lrc.h #include i915_gem_gtt.h #include linux/io-mapping.h #include linux/i2c.h diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c new file mode 100644 index 000..49bb6fc --- /dev/null +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -0,0 +1,42 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + *Ben Widawsky b...@bwidawsk.net + *Michel Thierry michel.thie...@intel.com + *Thomas Daniel thomas.dan...@intel.com + *Oscar Mateo oscar.ma...@intel.com + * + */ + +/* + * GEN8 brings an expansion of the HW contexts: Logical Ring Contexts. + * These expanded contexts enable a number of new abilities, especially + * Execlists (also implemented in this file). + * + * Execlists are the new method by which, on gen8+ hardware, workloads are + * submitted for execution (as opposed to the legacy, ringbuffer-based, method). + */ + +#include drm/drmP.h +#include drm/i915_drm.h +#include i915_drv.h diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h new file mode 100644 index 000..f6830a4 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -0,0 +1,27 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +
[Intel-gfx] [PATCH 06/43] drm/i915/bdw: A bit more advanced LR context alloc/free
From: Oscar Mateo oscar.ma...@intel.com
Now that we have the ability to allocate our own context backing objects
and we have multiplexed one of them per engine inside the context structs,
we can finally allocate and free them correctly.
Regarding the context size, reading the register to calculate the sizes
can work, I think, however the docs are very clear about the actual
context sizes on GEN8, so just hardcode that and use it.
v2: Rebased on top of the Full PPGTT series. It is important to notice
that at this point we have one global default context per engine, all
of them using the aliasing PPGTT (as opposed to the single global
default context we have with legacy HW contexts).
v3:
- Go back to one single global default context, this time with multiple
backing objects inside.
- Use different context sizes for non-render engines, as suggested by
Damien (still hardcoded, since the information about the context size
registers in the BSpec is, well, *lacking*).
- Render ctx size is 20 (or 19) pages, but not 21 (caught by Damien).
- Move default context backing object creation to intel_init_ring (so
that we don't waste memory in rings that might not get initialized).
v4:
- Reuse the HW legacy context init/fini.
- Create a separate free function.
- Rename the functions with an intel_ preffix.
v5: Several rebases to account for the changes in the previous patches.
Signed-off-by: Ben Widawsky b...@bwidawsk.net (v1)
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem_context.c |2 +-
drivers/gpu/drm/i915/intel_lrc.c| 59 +--
3 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b2b0c80..f2a6598 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2500,6 +2500,8 @@ int i915_switch_context(struct intel_engine_cs *ring,
struct intel_context *
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
void i915_gem_context_free(struct kref *ctx_ref);
+struct drm_i915_gem_object *
+i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
static inline void i915_gem_context_reference(struct intel_context *ctx)
{
kref_get(ctx-ref);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 718150e..48d7476 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -201,7 +201,7 @@ void i915_gem_context_free(struct kref *ctx_ref)
kfree(ctx);
}
-static struct drm_i915_gem_object *
+struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
{
struct drm_i915_gem_object *obj;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8cc6b55..a3fc6fc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -41,6 +41,11 @@
#include drm/i915_drm.h
#include i915_drv.h
+#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
+#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
+
+#define GEN8_LR_CONTEXT_ALIGN 4096
+
int intel_sanitize_enable_execlists(struct drm_device *dev, int
enable_execlists)
{
if (enable_execlists == 0)
@@ -54,15 +59,65 @@ int intel_sanitize_enable_execlists(struct drm_device *dev,
int enable_execlists
void intel_lr_context_free(struct intel_context *ctx)
{
- /* TODO */
+ int i;
+
+ for (i = 0; i I915_NUM_RINGS; i++) {
+ struct drm_i915_gem_object *ctx_obj = ctx-engine[i].state;
+ if (ctx_obj) {
+ i915_gem_object_ggtt_unpin(ctx_obj);
+ drm_gem_object_unreference(ctx_obj-base);
+ }
+ }
+}
+
+static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
+{
+ int ret = 0;
+
+ WARN_ON(INTEL_INFO(ring-dev)-gen != 8);
+
+ switch (ring-id) {
+ case RCS:
+ ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+ break;
+ case VCS:
+ case BCS:
+ case VECS:
+ case VCS2:
+ ret = GEN8_LR_CONTEXT_OTHER_SIZE;
+ break;
+ }
+
+ return ret;
}
int intel_lr_context_deferred_create(struct intel_context *ctx,
struct intel_engine_cs *ring)
{
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_gem_object *ctx_obj;
+ uint32_t context_size;
+ int ret;
+
BUG_ON(ctx-legacy_hw_ctx.rcs_state != NULL);
- /* TODO */
+ context_size = round_up(get_lr_context_size(ring), 4096);
+
+ ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
+ if (IS_ERR(ctx_obj)) {
+ ret = PTR_ERR(ctx_obj);
+ DRM_DEBUG_DRIVER(Alloc LRC backing obj failed: %d\n, ret);
+ return ret;
+ }
+
+ ret =
[Intel-gfx] [PATCH 36/43] drm/i915/bdw: Disable semaphores for Execlists
From: Oscar Mateo oscar.ma...@intel.com Up until recently, semaphores weren't enabled in BDW so we didn't care about them. But then Rodrigo came and enabled them: commit 521e62e49a42661a4ee0102644517dbe2f100a23 Author: Rodrigo Vivi rodrigo.v...@intel.com drm/i915: Enable semaphores on BDW So now we have to explicitly disable them for Execlists until both features play nicely. Signed-off-by: Oscar Mateo oscar.ma...@intel.com --- drivers/gpu/drm/i915/i915_drv.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5e4fefd..3489102 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -477,6 +477,10 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) if (i915.semaphores = 0) return i915.semaphores; + /* TODO: make semaphores and Execlists play nicely together */ + if (i915.enable_execlists) + return false; + #ifdef CONFIG_INTEL_IOMMU /* Enable semaphores on SNB when IO remapping is off */ if (INTEL_INFO(dev)-gen == 6 intel_iommu_gfx_mapped) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 32/43] drm/i915/bdw: Avoid non-lite-restore preemptions
From: Oscar Mateo oscar.ma...@intel.com
In the current Execlists feeding mechanism, full preemption is not
supported yet: only lite-restores are allowed (this is: the GPU
simply samples a new tail pointer for the context currently in
execution).
But we have identified an scenario in which a full preemption occurs:
1) We submit two contexts for execution (A B).
2) The GPU finishes with the first one (A), switches to the second one
(B) and informs us.
3) We submit B again (hoping to cause a lite restore) together with C,
but in the time we spend writing to the ELSP, the GPU finishes B.
4) The GPU start executing B again (since we told it so).
5) We receive a B finished interrupt and, mistakenly, we submit C (again)
and D, causing a full preemption of B.
The race is avoided by keeping track of how many times a context has been
submitted to the hardware and by better discriminating the received context
switch interrupts: in the example, when we have submitted B twice, we won´t
submit C and D as soon as we receive the notification that B is completed
because we were expecting to get a LITE_RESTORE and we didn´t, so we know a
second completion will be received shortly.
Without this explicit checking, somehow, the batch buffer execution order
gets messed with. This can be verified with the IGT test I sent together with
the series. I don´t know the exact mechanism by which the pre-emption messes
with the execution order but, since other people is working on the Scheduler
+ Preemption on Execlists, I didn´t try to fix it. In these series, only Lite
Restores are supported (other kind of preemptions WARN).
v2: elsp_submitted belongs in the new intel_ctx_submit_request. Several
rebase changes.
v3: Clarify how the race is avoided, as requested by Daniel.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 28
drivers/gpu/drm/i915/intel_lrc.h |2 ++
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 65f4f26..895dbfc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -264,6 +264,7 @@ static void execlists_context_unqueue(struct
intel_engine_cs *ring)
else if (req0-ctx == cursor-ctx) {
/* Same ctx: ignore first request, as second request
* will update tail past first request's workload */
+ cursor-elsp_submitted = req0-elsp_submitted;
list_del(req0-execlist_link);
queue_work(dev_priv-wq, req0-work);
req0 = cursor;
@@ -273,8 +274,14 @@ static void execlists_context_unqueue(struct
intel_engine_cs *ring)
}
}
+ WARN_ON(req1 req1-elsp_submitted);
+
BUG_ON(execlists_submit_context(ring, req0-ctx, req0-tail,
req1? req1-ctx : NULL, req1? req1-tail : 0));
+
+ req0-elsp_submitted++;
+ if (req1)
+ req1-elsp_submitted++;
}
static bool execlists_check_remove_request(struct intel_engine_cs *ring,
@@ -291,9 +298,13 @@ static bool execlists_check_remove_request(struct
intel_engine_cs *ring,
struct drm_i915_gem_object *ctx_obj =
head_req-ctx-engine[ring-id].state;
if (intel_execlists_ctx_id(ctx_obj) == request_id) {
- list_del(head_req-execlist_link);
- queue_work(dev_priv-wq, head_req-work);
- return true;
+ WARN(head_req-elsp_submitted == 0,
+ Never submitted head request\n);
+ if (--head_req-elsp_submitted = 0) {
+ list_del(head_req-execlist_link);
+ queue_work(dev_priv-wq, head_req-work);
+ return true;
+ }
}
}
@@ -326,7 +337,16 @@ void intel_execlists_handle_ctx_events(struct
intel_engine_cs *ring)
status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
(read_pointer % 6) * 8 + 4);
- if (status GEN8_CTX_STATUS_COMPLETE) {
+ if (status GEN8_CTX_STATUS_PREEMPTED) {
+ if (status GEN8_CTX_STATUS_LITE_RESTORE) {
+ if (execlists_check_remove_request(ring,
status_id))
+ WARN(1, Lite Restored request removed
from queue\n);
+ } else
+ WARN(1, Preemption without Lite Restore\n);
+ }
+
+if ((status GEN8_CTX_STATUS_ACTIVE_IDLE) ||
+(status GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
if (execlists_check_remove_request(ring, status_id))
[Intel-gfx] [PATCH 18/43] drm/i915/bdw: New logical ring submission mechanism
From: Oscar Mateo oscar.ma...@intel.com
Well, new-ish: if all this code looks familiar, that's because it's
a clone of the existing submission mechanism (with some modifications
here and there to adapt it to LRCs and Execlists).
And why did we do this instead of reusing code, one might wonder?
Well, there are some fears that the differences are big enough that
they will end up breaking all platforms.
Also, Execlists offer several advantages, like control over when the
GPU is done with a given workload, that can help simplify the
submission mechanism, no doubt. I am interested in getting Execlists
to work first and foremost, but in the future this parallel submission
mechanism will help us to fine tune the mechanism without affecting
old gens.
v2: Pass the ringbuffer only (whenever possible).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c| 193 +++
drivers/gpu/drm/i915/intel_lrc.h| 12 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h |3 +
4 files changed, 218 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f171fd5..bd37d51 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -106,6 +106,199 @@ void intel_logical_ring_stop(struct intel_engine_cs *ring)
/* TODO */
}
+void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf)
+{
+ intel_logical_ring_advance(ringbuf);
+
+ if (intel_ring_stopped(ringbuf-ring))
+ return;
+
+ /* TODO: how to submit a context to the ELSP is not here yet */
+}
+
+static int logical_ring_alloc_seqno(struct intel_engine_cs *ring)
+{
+ if (ring-outstanding_lazy_seqno)
+ return 0;
+
+ if (ring-preallocated_lazy_request == NULL) {
+ struct drm_i915_gem_request *request;
+
+ request = kmalloc(sizeof(*request), GFP_KERNEL);
+ if (request == NULL)
+ return -ENOMEM;
+
+ ring-preallocated_lazy_request = request;
+ }
+
+ return i915_gem_get_seqno(ring-dev, ring-outstanding_lazy_seqno);
+}
+
+static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, int
bytes)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ struct drm_i915_gem_request *request;
+ u32 seqno = 0;
+ int ret;
+
+ if (ringbuf-last_retired_head != -1) {
+ ringbuf-head = ringbuf-last_retired_head;
+ ringbuf-last_retired_head = -1;
+
+ ringbuf-space = intel_ring_space(ringbuf);
+ if (ringbuf-space = bytes)
+ return 0;
+ }
+
+ list_for_each_entry(request, ring-request_list, list) {
+ if (__intel_ring_space(request-tail, ringbuf-tail,
+ ringbuf-size) = bytes) {
+ seqno = request-seqno;
+ break;
+ }
+ }
+
+ if (seqno == 0)
+ return -ENOSPC;
+
+ ret = i915_wait_seqno(ring, seqno);
+ if (ret)
+ return ret;
+
+ /* TODO: make sure we update the right ringbuffer's last_retired_head
+* when retiring requests */
+ i915_gem_retire_requests_ring(ring);
+ ringbuf-head = ringbuf-last_retired_head;
+ ringbuf-last_retired_head = -1;
+
+ ringbuf-space = intel_ring_space(ringbuf);
+ return 0;
+}
+
+static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, int
bytes)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long end;
+ int ret;
+
+ ret = logical_ring_wait_request(ringbuf, bytes);
+ if (ret != -ENOSPC)
+ return ret;
+
+ /* Force the context submission in case we have been skipping it */
+ intel_logical_ring_advance_and_submit(ringbuf);
+
+ /* With GEM the hangcheck timer should kick us out of the loop,
+* leaving it early runs the risk of corrupting GEM state (due
+* to running on almost untested codepaths). But on resume
+* timers don't work yet, so prevent a complete hang in that
+* case by choosing an insanely large timeout. */
+ end = jiffies + 60 * HZ;
+
+ do {
+ ringbuf-head = I915_READ_HEAD(ring);
+ ringbuf-space = intel_ring_space(ringbuf);
+ if (ringbuf-space = bytes) {
+ ret = 0;
+ break;
+ }
+
+ if (!drm_core_check_feature(dev, DRIVER_MODESET)
+ dev-primary-master) {
+ struct drm_i915_master_private *master_priv =
dev-primary-master-driver_priv;
+ if (master_priv-sarea_priv)
+
[Intel-gfx] [PATCH 42/43] drm/i915/bdw: Pin the context backing objects to GGTT on-demand
From: Oscar Mateo oscar.ma...@intel.com
Up until now, we have pinned every logical ring context backing object
during creation, and left it pinned until destruction. This made my life
easier, but it's a harmful thing to do, because we cause fragmentation
of the GGTT (and, eventually, we would run out of space).
This patch makes the pinning on-demand: the backing objects of the two
contexts that are written to the ELSP are pinned right before submission
and unpinned once the hardware is done with them. The only context that
is still pinned regardless is the global default one, so that the HWS can
still be accessed in the same way (ring-status_page).
v2: In the early version of this patch, we were pinning the context as
we put it into the ELSP: on the one hand, this is very efficient because
only a maximum two contexts are pinned at any given time, but on the other
hand, we cannot really pin in interrupt time :(
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +++--
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_gem.c | 44 ---
drivers/gpu/drm/i915/intel_lrc.c| 42 -
drivers/gpu/drm/i915/intel_lrc.h|2 ++
5 files changed, 73 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 968c3c0..84531cc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1721,10 +1721,15 @@ static int i915_dump_lrc(struct seq_file *m, void
*unused)
continue;
if (ctx_obj) {
- struct page *page =
i915_gem_object_get_page(ctx_obj, 1);
- uint32_t *reg_state = kmap_atomic(page);
+ struct page *page ;
+ uint32_t *reg_state;
int j;
+ i915_gem_obj_ggtt_pin(ctx_obj,
GEN8_LR_CONTEXT_ALIGN, 0);
+
+ page = i915_gem_object_get_page(ctx_obj, 1);
+ reg_state = kmap_atomic(page);
+
seq_printf(m, CONTEXT: %s %u\n, ring-name,
intel_execlists_ctx_id(ctx_obj));
@@ -1736,6 +1741,8 @@ static int i915_dump_lrc(struct seq_file *m, void *unused)
}
kunmap_atomic(reg_state);
+ i915_gem_object_ggtt_unpin(ctx_obj);
+
seq_putc(m, '\n');
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ce51d6..70466af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -628,6 +628,7 @@ struct intel_context {
struct {
struct drm_i915_gem_object *state;
struct intel_ringbuffer *ringbuf;
+ atomic_t unpin_count;
} engine[I915_NUM_RINGS];
struct list_head link;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 143cff7..42faaa3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2491,12 +2491,23 @@ static void i915_set_reset_status(struct
drm_i915_private *dev_priv,
static void i915_gem_free_request(struct drm_i915_gem_request *request)
{
+ struct intel_context *ctx = request-ctx;
+
list_del(request-list);
i915_gem_request_remove_from_client(request);
- if (request-ctx)
- i915_gem_context_unreference(request-ctx);
+ if (ctx) {
+ struct intel_engine_cs *ring = request-ring;
+ struct drm_i915_gem_object *ctx_obj =
ctx-engine[ring-id].state;
+ atomic_t *unpin_count = ctx-engine[ring-id].unpin_count;
+ if (ctx_obj) {
+ if (atomic_dec_return(unpin_count) == 0
+ ctx != ring-default_context)
+ i915_gem_object_ggtt_unpin(ctx_obj);
+ }
+ i915_gem_context_unreference(ctx);
+ }
kfree(request);
}
@@ -2551,6 +2562,23 @@ static void i915_gem_reset_ring_cleanup(struct
drm_i915_private *dev_priv,
}
/*
+* Clear the execlists queue up before freeing the requests, as those
+* are the ones that keep the context and ringbuffer backing objects
+* pinned in place.
+*/
+ while (!list_empty(ring-execlist_queue)) {
+ struct intel_ctx_submit_request *submit_req;
+
+ submit_req = list_first_entry(ring-execlist_queue,
+ struct intel_ctx_submit_request,
+ execlist_link);
+
[Intel-gfx] [PATCH 27/43] drm/i915/bdw: Render state init for Execlists
From: Oscar Mateo oscar.ma...@intel.com
The batchbuffer that sets the render context state is submitted
in a different way, and from different places.
We needed to make both the render state preparation and free functions
outside accesible, and namespace accordingly. This mess is so that all
LR, LRC and Execlists functionality can go together in intel_lrc.c: we
can fix all of this later on, once the interfaces are clear.
v2: Create a separate ctx-rcs_initialized for the Execlists case, as
suggested by Chris Wilson.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |4 +--
drivers/gpu/drm/i915/i915_gem_context.c | 17 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 40 ++
drivers/gpu/drm/i915/i915_gem_render_state.h | 47 ++
drivers/gpu/drm/i915/intel_lrc.c | 46 +
drivers/gpu/drm/i915/intel_lrc.h |2 ++
drivers/gpu/drm/i915/intel_renderstate.h |8 +
7 files changed, 139 insertions(+), 25 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gem_render_state.h
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4303e2c..b7cf0ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -37,6 +37,7 @@
#include intel_ringbuffer.h
#include intel_lrc.h
#include i915_gem_gtt.h
+#include i915_gem_render_state.h
#include linux/io-mapping.h
#include linux/i2c.h
#include linux/i2c-algo-bit.h
@@ -623,6 +624,7 @@ struct intel_context {
} legacy_hw_ctx;
/* Execlists */
+ bool rcs_initialized;
struct {
struct drm_i915_gem_object *state;
struct intel_ringbuffer *ringbuf;
@@ -2553,8 +2555,6 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
-/* i915_gem_render_state.c */
-int i915_gem_render_state_init(struct intel_engine_cs *ring);
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 9085ff1..0dc6992 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -513,8 +513,23 @@ int i915_gem_context_enable(struct drm_i915_private
*dev_priv)
ppgtt-enable(ppgtt);
}
- if (i915.enable_execlists)
+ if (i915.enable_execlists) {
+ struct intel_context *dctx;
+
+ ring = dev_priv-ring[RCS];
+ dctx = ring-default_context;
+
+ if (!dctx-rcs_initialized) {
+ ret = intel_lr_context_render_state_init(ring, dctx);
+ if (ret) {
+ DRM_ERROR(Init render state failed: %d\n,
ret);
+ return ret;
+ }
+ dctx-rcs_initialized = true;
+ }
+
return 0;
+ }
/* FIXME: We should make this work, even in reset */
if (i915_reset_in_progress(dev_priv-gpu_error))
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index e60be3f..a9a62d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -28,13 +28,6 @@
#include i915_drv.h
#include intel_renderstate.h
-struct render_state {
- const struct intel_renderstate_rodata *rodata;
- struct drm_i915_gem_object *obj;
- u64 ggtt_offset;
- int gen;
-};
-
static const struct intel_renderstate_rodata *
render_state_get_rodata(struct drm_device *dev, const int gen)
{
@@ -127,30 +120,47 @@ static int render_state_setup(struct render_state *so)
return 0;
}
-static void render_state_fini(struct render_state *so)
+void i915_gem_render_state_fini(struct render_state *so)
{
i915_gem_object_ggtt_unpin(so-obj);
drm_gem_object_unreference(so-obj-base);
}
-int i915_gem_render_state_init(struct intel_engine_cs *ring)
+int i915_gem_render_state_prepare(struct intel_engine_cs *ring,
+ struct render_state *so)
{
- struct render_state so;
int ret;
if (WARN_ON(ring-id != RCS))
return -ENOENT;
- ret = render_state_init(so, ring-dev);
+ ret = render_state_init(so, ring-dev);
if (ret)
return ret;
- if (so.rodata == NULL)
+ if (so-rodata == NULL)
return 0;
- ret = render_state_setup(so);
+ ret = render_state_setup(so);
+ if (ret) {
+ i915_gem_render_state_fini(so);
+
[Intel-gfx] [PATCH 20/43] drm/i915/bdw: GEN-specific logical ring emit flush
From: Oscar Mateo oscar.ma...@intel.com
Same as the legacy-style ring-flush.
v2: The BSD invalidate bit still exists in GEN8! Add it for the VCS
rings (but still consolidate the blt and bsd ring flushes into one).
This was noticed by Brad Volkin.
v3: The command for BSD and for other rings is slightly different:
get it exactly the same as in gen6_ring_flush + gen6_bsd_ring_flush
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c| 82 +++
drivers/gpu/drm/i915/intel_ringbuffer.c |7 ---
drivers/gpu/drm/i915/intel_ringbuffer.h | 10
3 files changed, 92 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 64bda7a..5dd63d6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -342,6 +342,83 @@ static int gen8_init_render_ring(struct intel_engine_cs
*ring)
return ret;
}
+static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
+ u32 invalidate_domains,
+ u32 unused)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t cmd;
+ int ret;
+
+ ret = intel_logical_ring_begin(ringbuf, 4);
+ if (ret)
+ return ret;
+
+ cmd = MI_FLUSH_DW + 1;
+
+ if (ring == dev_priv-ring[VCS]) {
+ if (invalidate_domains I915_GEM_GPU_DOMAINS)
+ cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
+ MI_FLUSH_DW_STORE_INDEX |
MI_FLUSH_DW_OP_STOREDW;
+ } else {
+ if (invalidate_domains I915_GEM_DOMAIN_RENDER)
+ cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
+ MI_FLUSH_DW_OP_STOREDW;
+ }
+
+ intel_logical_ring_emit(ringbuf, cmd);
+ intel_logical_ring_emit(ringbuf, I915_GEM_HWS_SCRATCH_ADDR |
MI_FLUSH_DW_USE_GTT);
+ intel_logical_ring_emit(ringbuf, 0); /* upper addr */
+ intel_logical_ring_emit(ringbuf, 0); /* value */
+ intel_logical_ring_advance(ringbuf);
+
+ return 0;
+}
+
+static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
+ u32 invalidate_domains,
+ u32 flush_domains)
+{
+ struct intel_engine_cs *ring = ringbuf-ring;
+ u32 scratch_addr = ring-scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 flags = 0;
+ int ret;
+
+ flags |= PIPE_CONTROL_CS_STALL;
+
+ if (flush_domains) {
+ flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ }
+
+ if (invalidate_domains) {
+ flags |= PIPE_CONTROL_TLB_INVALIDATE;
+ flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_QW_WRITE;
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+ }
+
+ ret = intel_logical_ring_begin(ringbuf, 6);
+ if (ret)
+ return ret;
+
+ intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+ intel_logical_ring_emit(ringbuf, flags);
+ intel_logical_ring_emit(ringbuf, scratch_addr);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_advance(ringbuf);
+
+ return 0;
+}
+
static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
{
return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
@@ -453,6 +530,7 @@ static int logical_render_ring_init(struct drm_device *dev)
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
ring-emit_request = gen8_emit_request;
+ ring-emit_flush = gen8_emit_flush_render;
return logical_ring_init(dev, ring);
}
@@ -472,6 +550,7 @@ static int logical_bsd_ring_init(struct drm_device *dev)
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
ring-emit_request = gen8_emit_request;
+ ring-emit_flush = gen8_emit_flush;
return logical_ring_init(dev, ring);
}
@@ -491,6 +570,7 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
ring-get_seqno = gen8_get_seqno;
ring-set_seqno = gen8_set_seqno;
ring-emit_request = gen8_emit_request;
+ ring-emit_flush = gen8_emit_flush;
return logical_ring_init(dev, ring);
}
@@ -510,6 +590,7 @@ static int logical_blt_ring_init(struct drm_device *dev)
ring-get_seqno = gen8_get_seqno;
[Intel-gfx] [PATCH 43/43] drm/i915/bdw: Pin the ringbuffer backing object to GGTT on-demand
From: Oscar Mateo oscar.ma...@intel.com
Same as with the context, pinning to GGTT regardless is harmful (it
badly fragments the GGTT and can even exhaust it).
Unfortunately, this case is also more complex than the previous one
because we need to map and access the ringbuffer in several places
along the execbuffer path (and we cannot make do by leaving the
default ringbuffer pinned, as before). Also, the context object
itself contains a pointer to the ringbuffer address that we have to
keep updated if we are going to allow the ringbuffer to move around.
v2: Same as with the context pinning, we cannot really do it during
an interrupt. Also, pin the default ringbuffers objects regardless
(makes error capture a lot easier).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c |5 +-
drivers/gpu/drm/i915/intel_lrc.c| 80 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 83 ++-
drivers/gpu/drm/i915/intel_ringbuffer.h |3 ++
4 files changed, 111 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 42faaa3..1a852b9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2498,13 +2498,16 @@ static void i915_gem_free_request(struct
drm_i915_gem_request *request)
if (ctx) {
struct intel_engine_cs *ring = request-ring;
+ struct intel_ringbuffer *ringbuf =
ctx-engine[ring-id].ringbuf;
struct drm_i915_gem_object *ctx_obj =
ctx-engine[ring-id].state;
atomic_t *unpin_count = ctx-engine[ring-id].unpin_count;
if (ctx_obj) {
if (atomic_dec_return(unpin_count) == 0
- ctx != ring-default_context)
+ ctx != ring-default_context) {
+ intel_unpin_ringbuffer_obj(ringbuf);
i915_gem_object_ggtt_unpin(ctx_obj);
+ }
}
i915_gem_context_unreference(ctx);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9fa8e35..4ca8278 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -315,7 +315,9 @@ static void execlists_elsp_write(struct intel_engine_cs
*ring,
spin_unlock_irqrestore(dev_priv-uncore.lock, flags);
}
-static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32
tail)
+static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
+ struct drm_i915_gem_object *ring_obj,
+ u32 tail)
{
struct page *page;
uint32_t *reg_state;
@@ -324,6 +326,7 @@ static int execlists_ctx_write_tail(struct
drm_i915_gem_object *ctx_obj, u32 tai
reg_state = kmap_atomic(page);
reg_state[CTX_RING_TAIL+1] = tail;
+ reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
kunmap_atomic(reg_state);
@@ -334,21 +337,25 @@ static int execlists_submit_context(struct
intel_engine_cs *ring,
struct intel_context *to0, u32 tail0,
struct intel_context *to1, u32 tail1)
{
- struct drm_i915_gem_object *ctx_obj0;
+ struct drm_i915_gem_object *ctx_obj0 = to0-engine[ring-id].state;
+ struct intel_ringbuffer *ringbuf0 = to0-engine[ring-id].ringbuf;
struct drm_i915_gem_object *ctx_obj1 = NULL;
+ struct intel_ringbuffer *ringbuf1 = NULL;
- ctx_obj0 = to0-engine[ring-id].state;
BUG_ON(!ctx_obj0);
BUG_ON(!i915_gem_obj_is_pinned(ctx_obj0));
+ BUG_ON(!i915_gem_obj_is_pinned(ringbuf0-obj));
- execlists_ctx_write_tail(ctx_obj0, tail0);
+ execlists_update_context(ctx_obj0, ringbuf0-obj, tail0);
if (to1) {
+ ringbuf1 = to1-engine[ring-id].ringbuf;
ctx_obj1 = to1-engine[ring-id].state;
BUG_ON(!ctx_obj1);
BUG_ON(!i915_gem_obj_is_pinned(ctx_obj1));
+ BUG_ON(!i915_gem_obj_is_pinned(ringbuf1-obj));
- execlists_ctx_write_tail(ctx_obj1, tail1);
+ execlists_update_context(ctx_obj1, ringbuf1-obj, tail1);
}
execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
@@ -772,6 +779,7 @@ static int logical_ring_alloc_seqno(struct intel_engine_cs
*ring,
if (ring-preallocated_lazy_request == NULL) {
struct drm_i915_gem_request *request;
+ struct intel_ringbuffer *ringbuf =
ctx-engine[ring-id].ringbuf;
struct drm_i915_gem_object *ctx_obj =
ctx-engine[ring-id].state;
atomic_t *unpin_count = ctx-engine[ring-id].unpin_count;
@@ -787,6 +795,13 @@ static int logical_ring_alloc_seqno(struct
[Intel-gfx] [PATCH 38/43] drm/i915/bdw: Display context backing obj ringbuffer info in debugfs
From: Oscar Mateo oscar.ma...@intel.com
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 903ed67..0980cdd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1629,6 +1629,12 @@ static int i915_gem_framebuffer_info(struct seq_file *m,
void *data)
return 0;
}
+static void describe_ctx_ringbuf(struct seq_file *m, struct intel_ringbuffer
*ringbuf)
+{
+ seq_printf(m, (ringbuffer, space: %d, head: %u, tail: %u, last head:
%d),
+ ringbuf-space, ringbuf-head, ringbuf-tail,
+ ringbuf-last_retired_head);
+}
static int i915_context_status(struct seq_file *m, void *unused)
{
@@ -1656,7 +1662,7 @@ static int i915_context_status(struct seq_file *m, void
*unused)
}
list_for_each_entry(ctx, dev_priv-context_list, link) {
- if (ctx-legacy_hw_ctx.rcs_state == NULL)
+ if (!i915.enable_execlists ctx-legacy_hw_ctx.rcs_state ==
NULL)
continue;
seq_puts(m, HW context );
@@ -1665,7 +1671,22 @@ static int i915_context_status(struct seq_file *m, void
*unused)
if (ring-default_context == ctx)
seq_printf(m, (default context %s) ,
ring-name);
- describe_obj(m, ctx-legacy_hw_ctx.rcs_state);
+ if (i915.enable_execlists) {
+ seq_putc(m, '\n');
+ for_each_ring(ring, dev_priv, i) {
+ struct drm_i915_gem_object *ctx_obj =
ctx-engine[i].state;
+ struct intel_ringbuffer *ringbuf =
ctx-engine[i].ringbuf;
+
+ seq_printf(m, %s: , ring-name);
+ if (ctx_obj)
+ describe_obj(m, ctx_obj);
+ if (ringbuf)
+ describe_ctx_ringbuf(m, ringbuf);
+ seq_putc(m, '\n');
+ }
+ } else
+ describe_obj(m, ctx-legacy_hw_ctx.rcs_state);
+
seq_putc(m, '\n');
}
--
1.7.9.5
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[Intel-gfx] [PATCH 40/43] drm/i915/bdw: Document Logical Rings, LR contexts and Execlists
From: Oscar Mateo oscar.ma...@intel.com Add theory of operation notes to intel_lrc.c and comments to externally visible functions. v2: Add notes on logical ring context creation. v3: Use kerneldoc. v4: Integrate it in the DocBook template. Signed-off-by: Thomas Daniel thomas.dan...@intel.com (v1) Signed-off-by: Oscar Mateo oscar.ma...@intel.com (v2, v3) --- Documentation/DocBook/drm.tmpl |5 + drivers/gpu/drm/i915/intel_lrc.c | 215 +- drivers/gpu/drm/i915/intel_lrc.h | 30 ++ 3 files changed, 249 insertions(+), 1 deletion(-) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 97838551..91a5620 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -3909,6 +3909,11 @@ int num_ioctls;/synopsis !Pdrivers/gpu/drm/i915/i915_cmd_parser.c batch buffer command parser !Idrivers/gpu/drm/i915/i915_cmd_parser.c /sect2 + sect2 +titleLogical Rings, Logical Ring Contexts and Execlists/title +!Pdrivers/gpu/drm/i915/intel_lrc.c Logical Rings, Logical Ring Contexts and Execlists +!Idrivers/gpu/drm/i915/intel_lrc.c + /sect2 /sect1 /chapter /part diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8056fa4..5faa084 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -28,13 +28,108 @@ * */ -/* +/** + * DOC: Logical Rings, Logical Ring Contexts and Execlists + * + * Motivation: * GEN8 brings an expansion of the HW contexts: Logical Ring Contexts. * These expanded contexts enable a number of new abilities, especially * Execlists (also implemented in this file). * + * One of the main differences with the legacy HW contexts is that logical + * ring contexts incorporate many more things to the context's state, like + * PDPs or ringbuffer control registers: + * + * The reason why PDPs are included in the context is straightforward: as + * PPGTTs (per-process GTTs) are actually per-context, having the PDPs + * contained there mean you don't need to do a ppgtt-switch_mm yourself, + * instead, the GPU will do it for you on the context switch. + * + * But, what about the ringbuffer control registers (head, tail, etc..)? + * shouldn't we just need a set of those per engine command streamer? This is + * where the name Logical Rings starts to make sense: by virtualizing the + * rings, the engine cs shifts to a new ring buffer with every context + * switch. When you want to submit a workload to the GPU you: A) choose your + * context, B) find its appropriate virtualized ring, C) write commands to it + * and then, finally, D) tell the GPU to switch to that context. + * + * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch + * to a contexts is via a context execution list, ergo Execlists. + * + * LRC implementation: + * Regarding the creation of contexts, we have: + * + * - One global default context. + * - One local default context for each opened fd. + * - One local extra context for each context create ioctl call. + * + * Now that ringbuffers belong per-context (and not per-engine, like before) + * and that contexts are uniquely tied to a given engine (and not reusable, + * like before) we need: + * + * - One ringbuffer per-engine inside each context. + * - One backing object per-engine inside each context. + * + * The global default context starts its life with these new objects fully + * allocated and populated. The local default context for each opened fd is + * more complex, because we don't know at creation time which engine is going + * to use them. To handle this, we have implemented a deferred creation of LR + * contexts: + * + * The local context starts its life as a hollow or blank holder, that only + * gets populated for a given engine once we receive an execbuffer. If later + * on we receive another execbuffer ioctl for the same context but a different + * engine, we allocate/populate a new ringbuffer and context backing object and + * so on. + * + * Finally, regarding local contexts created using the ioctl call: as they are + * only allowed with the render ring, we can allocate populate them right + * away (no need to defer anything, at least for now). + * + * Execlists implementation: * Execlists are the new method by which, on gen8+ hardware, workloads are * submitted for execution (as opposed to the legacy, ringbuffer-based, method). + * This method works as follows: + * + * When a request is committed, its commands (the BB start and any leading or + * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer + * for the appropriate context. The tail pointer in the hardware context is not + * updated at this time, but instead, kept by the driver in the ringbuffer + * structure. A structure representing this request is added to a request queue + * for the appropriate engine: this structure contains a copy of the context's + * tail after the
[Intel-gfx] [PATCH 33/43] drm/i915/bdw: Help out the ctx switch interrupt handler
From: Oscar Mateo oscar.ma...@intel.com
If we receive a storm of requests for the same context (see gem_storedw_loop_*)
we might end up iterating over too many elements in interrupt time, looking for
contexts to squash together. Instead, share the burden by giving more
intelligence to the queue function. At most, the interrupt will iterate over
three elements.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 895dbfc..829b15d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -384,9 +384,10 @@ static int execlists_context_queue(struct intel_engine_cs
*ring,
struct intel_context *to,
u32 tail)
{
- struct intel_ctx_submit_request *req = NULL;
+ struct drm_i915_private *dev_priv = ring-dev-dev_private;
+ struct intel_ctx_submit_request *req = NULL, *cursor;
unsigned long flags;
- bool was_empty;
+ int num_elements = 0;
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (req == NULL)
@@ -400,9 +401,26 @@ static int execlists_context_queue(struct intel_engine_cs
*ring,
spin_lock_irqsave(ring-execlist_lock, flags);
- was_empty = list_empty(ring-execlist_queue);
+ list_for_each_entry(cursor, ring-execlist_queue, execlist_link)
+ if (++num_elements 2)
+ break;
+
+ if (num_elements 2) {
+ struct intel_ctx_submit_request *tail_req;
+
+ tail_req = list_last_entry(ring-execlist_queue,
+ struct intel_ctx_submit_request,
+ execlist_link);
+ if (to == tail_req-ctx) {
+ WARN(tail_req-elsp_submitted != 0,
+ More than 2 already-submitted reqs
queued\n);
+ list_del(tail_req-execlist_link);
+ queue_work(dev_priv-wq, tail_req-work);
+ }
+ }
+
list_add_tail(req-execlist_link, ring-execlist_queue);
- if (was_empty)
+ if (num_elements == 0)
execlists_context_unqueue(ring);
spin_unlock_irqrestore(ring-execlist_lock, flags);
--
1.7.9.5
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[Intel-gfx] [PATCH 16/43] drm/i915/bdw: GEN-specific logical ring init
From: Oscar Mateo oscar.ma...@intel.com
Logical rings do not need most of the initialization their
legacy ringbuffer counterparts do: we just need the pipe
control object for the render ring, enable Execlists on the
hardware and a few workarounds.
v2: Squash with: drm/i915: Extract pipe control fini make
init outside accesible.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c| 54 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 34 +++
drivers/gpu/drm/i915/intel_ringbuffer.h |3 ++
3 files changed, 78 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 05b7069..7c8b75e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -106,6 +106,49 @@ void intel_logical_ring_stop(struct intel_engine_cs *ring)
/* TODO */
}
+static int gen8_init_common_ring(struct intel_engine_cs *ring)
+{
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(RING_MODE_GEN7(ring),
+ _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
+ _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+ POSTING_READ(RING_MODE_GEN7(ring));
+ DRM_DEBUG_DRIVER(Execlists enabled for %s\n, ring-name);
+
+ memset(ring-hangcheck, 0, sizeof(ring-hangcheck));
+
+ return 0;
+}
+
+static int gen8_init_render_ring(struct intel_engine_cs *ring)
+{
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int ret;
+
+ ret = gen8_init_common_ring(ring);
+ if (ret)
+ return ret;
+
+ /* We need to disable the AsyncFlip performance optimisations in order
+* to use MI_WAIT_FOR_EVENT within the CS. It should already be
+* programmed to '1' on all products.
+*
+* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
+*/
+ I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
+
+ ret = intel_init_pipe_control(ring);
+ if (ret)
+ return ret;
+
+ I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
+
+ return ret;
+}
+
void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
{
if (!intel_ring_initialized(ring))
@@ -176,6 +219,9 @@ static int logical_render_ring_init(struct drm_device *dev)
ring-irq_enable_mask =
GT_RENDER_USER_INTERRUPT GEN8_RCS_IRQ_SHIFT;
+ ring-init = gen8_init_render_ring;
+ ring-cleanup = intel_fini_pipe_control;
+
return logical_ring_init(dev, ring);
}
@@ -190,6 +236,8 @@ static int logical_bsd_ring_init(struct drm_device *dev)
ring-irq_enable_mask =
GT_RENDER_USER_INTERRUPT GEN8_VCS1_IRQ_SHIFT;
+ ring-init = gen8_init_common_ring;
+
return logical_ring_init(dev, ring);
}
@@ -204,6 +252,8 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
ring-irq_enable_mask =
GT_RENDER_USER_INTERRUPT GEN8_VCS2_IRQ_SHIFT;
+ ring-init = gen8_init_common_ring;
+
return logical_ring_init(dev, ring);
}
@@ -218,6 +268,8 @@ static int logical_blt_ring_init(struct drm_device *dev)
ring-irq_enable_mask =
GT_RENDER_USER_INTERRUPT GEN8_BCS_IRQ_SHIFT;
+ ring-init = gen8_init_common_ring;
+
return logical_ring_init(dev, ring);
}
@@ -232,6 +284,8 @@ static int logical_vebox_ring_init(struct drm_device *dev)
ring-irq_enable_mask =
GT_RENDER_USER_INTERRUPT GEN8_VECS_IRQ_SHIFT;
+ ring-init = gen8_init_common_ring;
+
return logical_ring_init(dev, ring);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 20eb1a4..ca45c58 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -573,8 +573,25 @@ out:
return ret;
}
-static int
-init_pipe_control(struct intel_engine_cs *ring)
+void
+intel_fini_pipe_control(struct intel_engine_cs *ring)
+{
+ struct drm_device *dev = ring-dev;
+
+ if (ring-scratch.obj == NULL)
+ return;
+
+ if (INTEL_INFO(dev)-gen = 5) {
+ kunmap(sg_page(ring-scratch.obj-pages-sgl));
+ i915_gem_object_ggtt_unpin(ring-scratch.obj);
+ }
+
+ drm_gem_object_unreference(ring-scratch.obj-base);
+ ring-scratch.obj = NULL;
+}
+
+int
+intel_init_pipe_control(struct intel_engine_cs *ring)
{
int ret;
@@ -649,7 +666,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
if (INTEL_INFO(dev)-gen = 5) {
- ret = init_pipe_control(ring);
+ ret = intel_init_pipe_control(ring);
if (ret)
return ret;
}
@@
[Intel-gfx] [PATCH 13/43] drm/i915: Abstract the legacy workload submission mechanism away
From: Oscar Mateo oscar.ma...@intel.com
As suggested by Daniel Vetter. The idea, in subsequent patches, is to
provide an alternative to these vfuncs for the Execlists submission
mechanism.
v2: Splitted into two and reordered to illustrate our intentions, instead
of showing it off. Also, remove the add_request vfunc and added the
stop_ring one.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 24
drivers/gpu/drm/i915/i915_gem.c| 15 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 20 ++--
3 files changed, 45 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff2c373..1caed52 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1617,6 +1617,21 @@ struct drm_i915_private {
/* Old ums support infrastructure, same warning applies. */
struct i915_ums_state ums;
+ /* Abstract the submission mechanism (legacy ringbuffer or execlists)
away */
+ struct {
+ int (*do_execbuf) (struct drm_device *dev, struct drm_file
*file,
+ struct intel_engine_cs *ring,
+ struct intel_context *ctx,
+ struct drm_i915_gem_execbuffer2 *args,
+ struct list_head *vmas,
+ struct drm_i915_gem_object *batch_obj,
+ u64 exec_start, u32 flags);
+ int (*init_rings) (struct drm_device *dev);
+ void (*cleanup_ring) (struct intel_engine_cs *ring);
+ void (*stop_ring) (struct intel_engine_cs *ring);
+ bool (*is_ring_initialized) (struct intel_engine_cs *ring);
+ } gt;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
@@ -2224,6 +2239,14 @@ int i915_gem_set_domain_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+int i915_gem_ringbuffer_submission(struct drm_device *dev,
+ struct drm_file *file,
+ struct intel_engine_cs *ring,
+ struct intel_context *ctx,
+ struct drm_i915_gem_execbuffer2 *args,
+ struct list_head *vmas,
+ struct drm_i915_gem_object *batch_obj,
+ u64 exec_start, u32 flags);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
@@ -2376,6 +2399,7 @@ void i915_gem_reset(struct drm_device *dev);
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
int __must_check i915_gem_init(struct drm_device *dev);
+int i915_gem_init_rings(struct drm_device *dev);
int __must_check i915_gem_init_hw(struct drm_device *dev);
int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
void i915_gem_init_swizzling(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d8bf4fa..6544286 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4518,7 +4518,7 @@ i915_gem_stop_ringbuffers(struct drm_device *dev)
int i;
for_each_ring(ring, dev_priv, i)
- intel_stop_ring_buffer(ring);
+ dev_priv-gt.stop_ring(ring);
}
int
@@ -4635,7 +4635,7 @@ intel_enable_blt(struct drm_device *dev)
return true;
}
-static int i915_gem_init_rings(struct drm_device *dev)
+int i915_gem_init_rings(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
@@ -4718,7 +4718,7 @@ i915_gem_init_hw(struct drm_device *dev)
i915_gem_init_swizzling(dev);
- ret = i915_gem_init_rings(dev);
+ ret = dev_priv-gt.init_rings(dev);
if (ret)
return ret;
@@ -4759,6 +4759,13 @@ int i915_gem_init(struct drm_device *dev)
DRM_DEBUG_DRIVER(allow wake ack timed out\n);
}
+ if (!i915.enable_execlists) {
+ dev_priv-gt.do_execbuf = i915_gem_ringbuffer_submission;
+ dev_priv-gt.init_rings = i915_gem_init_rings;
+ dev_priv-gt.cleanup_ring = intel_cleanup_ring_buffer;
+ dev_priv-gt.stop_ring = intel_stop_ring_buffer;
+ }
+
i915_gem_init_userptr(dev);
i915_gem_init_global_gtt(dev);
@@ -4794,7 +4801,7 @@
[Intel-gfx] [PATCH v2] intel-gpu-tools: fix version.h creation in android
From: Tim Gore tim.g...@intel.com commit 743dc7997aa9f5210055896940d87c88983dcda6 breaks the build under Android because version.h is not created. This happens because the android make executes from the ANDROID_BUILD_TOP directory rather than from the directory containing the source files, so we need to differentiate between Android and linux builds. This is V2 of this patch based on Thomas Wood's suggestion. Signed-off-by: Tim Gore tim.g...@intel.com --- lib/Android.mk | 3 ++- lib/Makefile.am | 3 +++ lib/Makefile.sources | 20 +++- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/lib/Android.mk b/lib/Android.mk index 6f444a0..5739c80 100644 --- a/lib/Android.mk +++ b/lib/Android.mk @@ -1,6 +1,7 @@ LOCAL_PATH := $(call my-dir) GPU_TOOLS_PATH := $(LOCAL_PATH)/.. +IGT_LIB_PATH := $(LOCAL_PATH) # FIXME: autogenerate this info # $(GPU_TOOLS_PATH)/config.h: @@ -13,7 +14,7 @@ include $(LOCAL_PATH)/Makefile.sources include $(CLEAR_VARS) LOCAL_GENERATED_SOURCES := \ - $(GPU_TOOLS_PATH)/lib/version.h \ + $(IGT_LIB_PATH)/version.h \ $(GPU_TOOLS_PATH)/config.h LOCAL_C_INCLUDES += \ diff --git a/lib/Makefile.am b/lib/Makefile.am index 4d4efe4..9f6a021 100644 --- a/lib/Makefile.am +++ b/lib/Makefile.am @@ -1,3 +1,6 @@ +IGT_LIB_PATH := . +GPU_TOOLS_PATH := .. + include Makefile.sources noinst_LTLIBRARIES = libintel_tools.la diff --git a/lib/Makefile.sources b/lib/Makefile.sources index 2d971c5..96786e0 100644 --- a/lib/Makefile.sources +++ b/lib/Makefile.sources @@ -48,12 +48,14 @@ libintel_tools_la_SOURCES = \ $(NULL) .PHONY: version.h.tmp -version.h.tmp: + +$(IGT_LIB_PATH)/version.h.tmp: @touch $@ - @if test -d $(top_srcdir)/.git; then \ - if which git /dev/null 21; then git log -n 1 --oneline | \ + @if test -d $(GPU_TOOLS_PATH)/.git; then \ + if which git /dev/null 21; then cd $(@D); \ + git log -n 1 --oneline | \ sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 g\1/' \ -$@ ; \ +$(@F) ; \ else \ echo '#define IGT_GIT_SHA1 NO-GIT' $@ ; \ fi \ @@ -61,12 +63,12 @@ version.h.tmp: echo '#define IGT_GIT_SHA1 NOT-GIT' $@ ; \ fi -version.h: version.h.tmp - @if ! cmp -s version.h.tmp version.h; then \ - echo updating version.h; \ - mv version.h.tmp version.h ;\ + +$(IGT_LIB_PATH)/version.h: $(IGT_LIB_PATH)/version.h.tmp + @if ! cmp -s $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h; then \ + mv $(IGT_LIB_PATH)/version.h.tmp $(IGT_LIB_PATH)/version.h ; \ else \ - rm version.h.tmp ;\ + rm $(IGT_LIB_PATH)/version.h.tmp ; \ fi BUILT_SOURCES = version.h -- 1.9.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/bdw: BDW Software Turbo
If that won't work, you could just use a timer, or tie into some other event that happens when the GPU is busy (e.g. execbuf or retire) instead of trying to tie into the display side of things. Jesse On Tue, 15 Jul 2014 06:35:20 + Sun, Daisy daisy@intel.com wrote: Hi Daniel, Chris The concern for traditional X and media server do make sense. I'll update the patch with RP_UP_EI_INTERRUPT as trigger instead of the page flip. Thanks for the valuable input. - Daisy -Original Message- From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Monday, July 14, 2014 12:04 AM To: Sun, Daisy Cc: Chris Wilson; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/bdw: BDW Software Turbo On Mon, Jul 14, 2014 at 8:59 AM, Daniel Vetter dan...@ffwll.ch wrote: On Mon, Jul 14, 2014 at 04:22:44AM +, Sun, Daisy wrote: 3) The function will be called when flip happened, this should cover most of the cases. One exception is background media process without any display output, it's relatively rare. Please let me know if you have concern on other cases, I will try to cover it definitely. Traditional X never flips. And we kinda have to keep this working. Instead of checking when flipping we need to check at regular time intervals I guess, for as long as the gt is busy. Oh and transcode servers are a real thing apparently. They also never flip, and we actually care from a business pov ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/12] Rework intel 2D driver glamor support
I spent the day just cleaning up this patch series and testing. I think it's ready for others to use and review. I've been running it on two machines for a couple of days now and it's been solid. I ran three different desktop environments (current Debian unstable versions): XFCE 4.10 Gnome 3.12 KDE4.13.3 I have not merged DRI2 support when running with Glamor; I've got that working locally, but if you accidentally try indirect rendering, you'll crash the X server with an assert failure. So, this is DRI3 only, at least for now. This patch series also adds a none acceleration mode. It's different from other unaccelerated drivers in offering DRI2 and DRI3 support so that you can run direct rendering. A brief synopsis of the series 1-4 cleanup patches 5 Identify and isolate UXA code; UXA-specific functions are renamed and moved into uxa-specific files. 6 Remove UXA-based Glamor support. This pulls out all of the Glamor calls from UXA rendering paths. This patch only builds with glamor disabled; I didn't worry about the existing glamor code or support for glamor within the rest of the driver. 7-9 Prepare for glamor support. Creates a couple of abstract functions for accel-dependent functionality needed by the initialization and modesetting code. Gets rid of the glamor stubs in intel_glamor.h 10 Add glamor support back in, using the regular glamor API. 11 Add an unaccelerated option (none). This offers fb-only support and is always compiled in to the driver. 12 Delay initial mode set operation until the root window is painted and the server is ready to go. This includes potentially copying an existing fbcon frame buffer to the root window in background none mode, providing support for this in all three acceleration modes. The driver used to support this by copying the fbcon buffer to the screen buffer during early server initialization; this change allows the driver to use regular GC-based CopyArea instead of needing custom rendering code. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/12] Move intel_alloc_framebuffer to intel_memory.c
UXA and Glamor both share this function, so move it out of the UXA file.
Signed-off-by: Keith Packard kei...@keithp.com
---
src/uxa/intel.h| 5 ++
src/uxa/intel_memory.c | 138 ++
src/uxa/intel_uxa.c| 158 -
3 files changed, 154 insertions(+), 147 deletions(-)
diff --git a/src/uxa/intel.h b/src/uxa/intel.h
index 409635d..8110c2e 100644
--- a/src/uxa/intel.h
+++ b/src/uxa/intel.h
@@ -539,6 +539,11 @@ unsigned long intel_get_fence_pitch(intel_screen_private
*intel, unsigned long p
Bool intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling);
void intel_set_gem_max_sizes(ScrnInfoPtr scrn);
+unsigned int
+intel_compute_size(struct intel_screen_private *intel,
+ int w, int h, int bpp, unsigned usage,
+ uint32_t *tiling, int *stride);
+
drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn,
int width, int height, int cpp,
int *out_stride,
diff --git a/src/uxa/intel_memory.c b/src/uxa/intel_memory.c
index 809b636..188a557 100644
--- a/src/uxa/intel_memory.c
+++ b/src/uxa/intel_memory.c
@@ -190,3 +190,141 @@ void intel_set_gem_max_sizes(ScrnInfoPtr scrn)
*/
intel-max_bo_size = intel-max_gtt_map_size;
}
+
+unsigned int
+intel_compute_size(struct intel_screen_private *intel,
+ int w, int h, int bpp, unsigned usage,
+ uint32_t *tiling, int *stride)
+{
+ int pitch, size;
+
+ if (*tiling != I915_TILING_NONE) {
+ /* First check whether tiling is necessary. */
+ pitch = (w * bpp + 7) / 8;
+ pitch = ALIGN(pitch, 64);
+ size = pitch * ALIGN (h, 2);
+ if (INTEL_INFO(intel)-gen 040) {
+ /* Gen 2/3 has a maximum stride for tiling of
+* 8192 bytes.
+*/
+ if (pitch KB(8))
+ *tiling = I915_TILING_NONE;
+
+ /* Narrower than half a tile? */
+ if (pitch 256)
+ *tiling = I915_TILING_NONE;
+
+ /* Older hardware requires fences to be pot size
+* aligned with a minimum of 1 MiB, so causes
+* massive overallocation for small textures.
+*/
+ if (size 1024*1024/2 !intel-has_relaxed_fencing)
+ *tiling = I915_TILING_NONE;
+ } else if (!(usage INTEL_CREATE_PIXMAP_DRI2) size = 4096)
{
+ /* Disable tiling beneath a page size, we will not see
+* any benefit from reducing TLB misses and instead
+* just incur extra cost when we require a fence.
+*/
+ *tiling = I915_TILING_NONE;
+ }
+ }
+
+ pitch = (w * bpp + 7) / 8;
+ if (!(usage INTEL_CREATE_PIXMAP_DRI2) pitch = 256)
+ *tiling = I915_TILING_NONE;
+
+ if (*tiling != I915_TILING_NONE) {
+ int aligned_h, tile_height;
+
+ if (IS_GEN2(intel))
+ tile_height = 16;
+ else if (*tiling == I915_TILING_X)
+ tile_height = 8;
+ else
+ tile_height = 32;
+ aligned_h = ALIGN(h, 2*tile_height);
+
+ *stride = intel_get_fence_pitch(intel,
+ ALIGN(pitch, 512),
+ *tiling);
+
+ /* Round the object up to the size of the fence it will live in
+* if necessary. We could potentially make the kernel allocate
+* a larger aperture space and just bind the subset of pages in,
+* but this is easier and also keeps us out of trouble (as much)
+* with drm_intel_bufmgr_check_aperture().
+*/
+ size = intel_get_fence_size(intel, *stride * aligned_h);
+
+ if (size intel-max_tiling_size)
+ *tiling = I915_TILING_NONE;
+ }
+
+ if (*tiling == I915_TILING_NONE) {
+ /* We only require a 64 byte alignment for scanouts, but
+* a 256 byte alignment for sharing with PRIME.
+*/
+ *stride = ALIGN(pitch, 256);
+ /* Round the height up so that the GPU's access to a 2x2 aligned
+* subspan doesn't address an invalid page offset beyond the
+* end of the GTT.
+*/
+ size = *stride * ALIGN(h, 2);
+ }
+
+ return size;
+}
+
+drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn,
+
[Intel-gfx] [PATCH 02/12] Fix present debug output
Was using 'low_msc', which isn't defined anymore. Signed-off-by: Keith Packard kei...@keithp.com --- src/uxa/intel_present.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/uxa/intel_present.c b/src/uxa/intel_present.c index 18fcbf8..5f98da8 100644 --- a/src/uxa/intel_present.c +++ b/src/uxa/intel_present.c @@ -193,7 +193,8 @@ intel_present_queue_vblank(RRCrtcPtr crtc, if (errno != EBUSY || !intel_present_flush_drm_events(screen)) return BadAlloc; } - DebugPresent((\t\tiq %lld seq %u msc %u (hw msc %u)\n, event_id, seq, low_msc, vbl.request.sequence)); + DebugPresent((\t\tiq %lld seq %u msc %llu (hw msc %u)\n, + (long long) event_id, seq, (long long) msc, vbl.request.sequence)); return Success; } -- 2.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/12] Stop trying to out-guess mesa for BO allocation
---
src/uxa/intel_uxa.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/uxa/intel_uxa.c b/src/uxa/intel_uxa.c
index b396188..717754f 100644
--- a/src/uxa/intel_uxa.c
+++ b/src/uxa/intel_uxa.c
@@ -758,6 +758,7 @@ free_priv:
goto free_priv;
}
+#if 0
if (tiling != I915_TILING_NONE) {
int height;
@@ -780,6 +781,7 @@ free_priv:
bo = NULL;
goto free_priv;
}
+#endif
}
BAIL:
--
2.0.1
___
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[Intel-gfx] [PATCH 03/12] Don't use GetScratchPixmapHeader for shadow pixmaps
GetScratchPixmapHeader should only be used for local memory pixmaps,
as used by PutImage and friends. That's because when you free the
scratch pixmap header, it doesn't actually free the pixmap; instead,
it gets stuffed in pScreen-pScratchPixmap and any private data stored
on it will be left hanging around forever.
In the case of glamor, that private data includes all of the GL
state. Using that scratch pixmap later results in glamor getting
mightily confused as the pixmap and underlying objects do not match.
Avoid this by allocating pixmap headers explicitly for this purpose.
Signed-off-by: Keith Packard kei...@keithp.com
---
src/uxa/intel_display.c | 44 ++--
1 file changed, 30 insertions(+), 14 deletions(-)
diff --git a/src/uxa/intel_display.c b/src/uxa/intel_display.c
index 0b83140..bcaafaa 100644
--- a/src/uxa/intel_display.c
+++ b/src/uxa/intel_display.c
@@ -545,13 +545,31 @@ intel_crtc_shadow_allocate(xf86CrtcPtr crtc, int width,
int height)
return NULL;
}
- drm_intel_bo_disable_reuse(intel_crtc-rotate_bo);
-
intel_crtc-rotate_pitch = rotate_pitch;
return intel_crtc-rotate_bo;
}
static PixmapPtr
+intel_create_pixmap_header(ScreenPtr pScreen, int width, int height, int depth,
+ int bitsPerPixel, int devKind, void *pPixData)
+{
+PixmapPtr pixmap;
+
+/* width and height of 0 means don't allocate any pixmap data */
+pixmap = (*pScreen-CreatePixmap) (pScreen, 0, 0, depth, 0);
+
+if (pixmap) {
+if ((*pScreen-ModifyPixmapHeader) (pixmap, width, height,
depth,
+bitsPerPixel, devKind,
pPixData))
+{
+return pixmap;
+}
+(*pScreen-DestroyPixmap) (pixmap);
+}
+return NullPixmap;
+}
+
+static PixmapPtr
intel_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
{
ScrnInfoPtr scrn = crtc-scrn;
@@ -573,12 +591,12 @@ intel_crtc_shadow_create(xf86CrtcPtr crtc, void *data,
int width, int height)
return NULL;
}
- rotate_pixmap = GetScratchPixmapHeader(scrn-pScreen,
- width, height,
- scrn-depth,
- scrn-bitsPerPixel,
- intel_crtc-rotate_pitch,
- NULL);
+ rotate_pixmap = intel_create_pixmap_header(scrn-pScreen,
+ width, height,
+ scrn-depth,
+ scrn-bitsPerPixel,
+ intel_crtc-rotate_pitch,
+ NULL);
if (rotate_pixmap == NULL) {
xf86DrvMsg(scrn-scrnIndex, X_ERROR,
@@ -602,8 +620,8 @@ intel_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr
rotate_pixmap, void *data)
struct intel_mode *mode = intel_crtc-mode;
if (rotate_pixmap) {
- intel_set_pixmap_bo(rotate_pixmap, NULL);
- FreeScratchPixmapHeader(rotate_pixmap);
+intel_set_pixmap_bo(rotate_pixmap, NULL);
+rotate_pixmap-drawable.pScreen-DestroyPixmap(rotate_pixmap);
}
if (data) {
@@ -1415,7 +1433,6 @@ intel_xf86crtc_resize(ScrnInfoPtr scrn, int width, int
height)
int i, old_width, old_height, old_pitch;
int pitch;
uint32_t tiling;
- ScreenPtr screen;
if (scrn-virtualX == width scrn-virtualY == height)
return TRUE;
@@ -1430,8 +1447,7 @@ intel_xf86crtc_resize(ScrnInfoPtr scrn, int width, int
height)
old_front = intel-front_buffer;
if (intel-back_pixmap) {
- screen = intel-back_pixmap-drawable.pScreen;
- screen-DestroyPixmap(intel-back_pixmap);
+ scrn-pScreen-DestroyPixmap(intel-back_pixmap);
intel-back_pixmap = NULL;
}
@@ -1454,7 +1470,6 @@ intel_xf86crtc_resize(ScrnInfoPtr scrn, int width, int
height)
if (ret)
goto fail;
- drm_intel_bo_disable_reuse(intel-front_buffer);
intel-front_pitch = pitch;
intel-front_tiling = tiling;
@@ -2204,6 +2219,7 @@ Bool intel_crtc_on(xf86CrtcPtr crtc)
return ret;
}
+
static PixmapPtr
intel_create_pixmap_for_bo(ScreenPtr pScreen, dri_bo *bo,
int width, int height,
--
2.0.1
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[Intel-gfx] [PATCH 10/12] Add glamor back into the driver
This adds glamor support back into the driver, but instad of going
through UXA, this uses it directly instead.
Signed-off-by: Keith Packard kei...@keithp.com
---
src/uxa/intel.h | 17 +++
src/uxa/intel_display.c | 30 -
src/uxa/intel_dri.c | 20 +++
src/uxa/intel_driver.c | 247 -
src/uxa/intel_glamor.c | 316 +---
src/uxa/intel_glamor.h | 18 ++-
src/uxa/intel_present.c | 5 -
src/uxa/intel_uxa.c | 5 +
src/uxa/intel_video.c | 75 +++-
9 files changed, 480 insertions(+), 253 deletions(-)
diff --git a/src/uxa/intel.h b/src/uxa/intel.h
index 64f573b..5fbb2c7 100644
--- a/src/uxa/intel.h
+++ b/src/uxa/intel.h
@@ -111,10 +111,21 @@ enum dri_type {
DRI_ACTIVE
};
+enum accel_type {
+#if USE_GLAMOR
+ACCEL_GLAMOR,
+#endif
+#if USE_UXA
+ACCEL_UXA,
+#endif
+};
+
typedef struct intel_screen_private {
ScrnInfoPtr scrn;
int cpp;
+enum accel_type accel;
+
#define RENDER_BATCH I915_EXEC_RENDER
#define BLT_BATCH I915_EXEC_BLT
unsigned int current_batch;
@@ -127,6 +138,7 @@ typedef struct intel_screen_private {
dri_bufmgr *bufmgr;
+#if USE_UXA
uint32_t batch_ptr[4096];
/** Byte offset in batch_ptr for the next dword to be emitted. */
unsigned int batch_used;
@@ -142,6 +154,7 @@ typedef struct intel_screen_private {
struct list batch_pixmaps;
drm_intel_bo *wa_scratch_bo;
OsTimerPtr cache_expire;
+#endif
/* For Xvideo */
Bool use_overlay;
@@ -178,8 +191,10 @@ typedef struct intel_screen_private {
void (*batch_flush) (struct intel_screen_private *intel);
void (*batch_commit_notify) (struct intel_screen_private *intel);
+#if USE_UXA
struct _UxaDriver *uxa_driver;
int uxa_flags;
+#endif
Bool need_sync;
int accel_pixmap_offset_alignment;
int accel_max_x;
@@ -212,6 +227,7 @@ typedef struct intel_screen_private {
drm_intel_bo *gen6_depth_stencil_bo;
} video;
+#if USE_UXA
/* Render accel state */
float scale_units[2][2];
/** Transform pointers for src/mask, or NULL if identity */
@@ -269,6 +285,7 @@ typedef struct intel_screen_private {
/* 965 render acceleration state */
struct gen4_render_state *gen4_render_state;
+#endif
/* DRI enabled this generation. */
enum dri_type dri2, dri3;
diff --git a/src/uxa/intel_display.c b/src/uxa/intel_display.c
index add09b0..a4c4b82 100644
--- a/src/uxa/intel_display.c
+++ b/src/uxa/intel_display.c
@@ -56,6 +56,9 @@
#include xf86DDC.h
#include fb.h
#include uxa.h
+#if USE_GLAMOR
+#include intel_glamor.h
+#endif
#define KNOWN_MODE_FLAGS ((114)-1)
@@ -182,7 +185,7 @@ intel_output_backlight_init(xf86OutputPtr output)
{
struct intel_output *intel_output = output-driver_private;
intel_screen_private *intel = intel_get_screen_private(output-scrn);
- char *str;
+ const char *str;
#if !USE_BACKLIGHT
return;
@@ -683,7 +686,10 @@ intel_set_scanout_pixmap(xf86CrtcPtr crtc, PixmapPtr ppix)
return TRUE;
}
- bo = intel_get_pixmap_bo(ppix);
+bo = intel_get_pixmap_bo(ppix);
+if (!bo)
+return FALSE;
+
if (intel-front_buffer) {
ErrorF(have front buffer\n);
}
@@ -1472,8 +1478,20 @@ intel_xf86crtc_resize(ScrnInfoPtr scrn, int width, int
height)
scrn-virtualX = width;
scrn-virtualY = height;
- if (!intel_uxa_create_screen_resources(scrn-pScreen))
- goto fail;
+switch (intel-accel) {
+#if USE_GLAMOR
+case ACCEL_GLAMOR:
+if (!intel_glamor_create_screen_resources(scrn-pScreen))
+goto fail;
+break;
+#endif
+#if USE_UXA
+case ACCEL_UXA:
+if (!intel_uxa_create_screen_resources(scrn-pScreen))
+goto fail;
+break;
+#endif
+}
for (i = 0; i xf86_config-num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config-crtc[i];
@@ -1532,7 +1550,7 @@ intel_do_pageflip(intel_screen_private *intel,
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
struct intel_crtc *crtc = config-crtc[0]-driver_private;
struct intel_mode *mode = crtc-mode;
- unsigned int pitch = scrn-displayWidth * intel-cpp;
+unsigned int pitch = scrn-displayWidth * intel-cpp;
struct intel_pageflip *flip;
uint32_t new_fb_id;
uint32_t flags;
@@ -2235,7 +2253,7 @@ intel_create_pixmap_for_bo(ScreenPtr pScreen, dri_bo *bo,
return NullPixmap;
}
- intel_set_pixmap_bo(pixmap, bo);
+intel_set_pixmap_bo(pixmap, bo);
return pixmap;
}
diff --git a/src/uxa/intel_dri.c
[Intel-gfx] [PATCH 06/12] Remove glamor support from UXA acceleration
Makes UXA no longer include calls to glamor acceleration functions.
Signed-off-by: Keith Packard kei...@keithp.com
---
src/uxa/Makefile.am| 9 --
src/uxa/intel_dri.c| 60 +
src/uxa/intel_driver.c | 1 -
src/uxa/intel_uxa.c| 49 ---
src/uxa/intel_uxa.h| 1 -
src/uxa/uxa-accel.c| 230 -
src/uxa/uxa-glamor.h | 65 --
src/uxa/uxa-glyphs.c | 28 --
src/uxa/uxa-render.c | 79 -
src/uxa/uxa.c | 7 --
src/uxa/uxa.h | 16
11 files changed, 2 insertions(+), 543 deletions(-)
delete mode 100644 src/uxa/uxa-glamor.h
diff --git a/src/uxa/Makefile.am b/src/uxa/Makefile.am
index 23b074d..b9618c9 100644
--- a/src/uxa/Makefile.am
+++ b/src/uxa/Makefile.am
@@ -34,7 +34,6 @@ libuxa_la_SOURCES = \
intel_batchbuffer.h \
intel_display.c \
intel_driver.c \
- intel_glamor.h \
intel_memory.c \
intel_uxa.c \
intel_video.c \
@@ -65,14 +64,6 @@ libuxa_la_SOURCES = \
uxa-unaccel.c
$(NULL)
-if GLAMOR
-AM_CFLAGS += $(LIBGLAMOR_CFLAGS)
-libuxa_la_LIBADD += $(LIBGLAMOR_LIBS)
-libuxa_la_SOURCES += \
-intel_glamor.c \
-$(NULL)
-endif
-
if DRI2
AM_CFLAGS += $(DRI2_CFLAGS)
libuxa_la_SOURCES += \
diff --git a/src/uxa/intel_dri.c b/src/uxa/intel_dri.c
index 65612f7..79978ab 100644
--- a/src/uxa/intel_dri.c
+++ b/src/uxa/intel_dri.c
@@ -793,38 +793,6 @@ I830DRI2ExchangeBuffers(struct intel_screen_private
*intel, DRI2BufferPtr front,
dri_bo_reference (intel-front_buffer);
}
-static PixmapPtr
-intel_glamor_create_back_pixmap(ScreenPtr screen,
- PixmapPtr front_pixmap,
- drm_intel_bo *back_bo)
-{
- PixmapPtr back_pixmap;
-
- back_pixmap = screen-CreatePixmap(screen,
- 0,
- 0,
- front_pixmap-drawable.depth,
- 0);
- if (back_pixmap == NULL)
- return NULL;
-
- screen-ModifyPixmapHeader(back_pixmap,
- front_pixmap-drawable.width,
- front_pixmap-drawable.height,
- 0, 0,
- front_pixmap-devKind,
- 0);
- intel_set_pixmap_bo(back_pixmap, back_bo);
- if (!intel_glamor_create_textured_pixmap(back_pixmap)) {
- ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
- xf86DrvMsg(scrn-scrnIndex, X_WARNING,
- Failed to create textured back pixmap.\n);
- screen-DestroyPixmap(back_pixmap);
- return NULL;
- }
- return back_pixmap;
-}
-
static drm_intel_bo *get_pixmap_bo(I830DRI2BufferPrivatePtr priv)
{
drm_intel_bo *bo = intel_get_pixmap_bo(priv-pixmap);
@@ -883,10 +851,6 @@ I830DRI2ScheduleFlip(struct intel_screen_private *intel,
}
if (intel-back_buffer == NULL) {
- I830DRI2BufferPrivatePtr drvpriv;
- PixmapPtr front_pixmap, back_pixmap;
- ScreenPtr screen;
-
new_back = drm_intel_bo_alloc(intel-bufmgr, front buffer,
intel-front_buffer-size, 0);
if (new_back == NULL)
@@ -903,21 +867,6 @@ I830DRI2ScheduleFlip(struct intel_screen_private *intel,
drm_intel_bo_disable_reuse(new_back);
dri_bo_flink(new_back, intel-back_name);
-
- if ((intel-uxa_flags UXA_USE_GLAMOR)) {
- screen = draw-pScreen;
- drvpriv = info-front-driverPrivate;
- front_pixmap = drvpriv-pixmap;
-
- back_pixmap = intel_glamor_create_back_pixmap(screen,
-
front_pixmap,
- new_back);
- if (back_pixmap == NULL) {
- drm_intel_bo_unreference(new_back);
- return FALSE;
- }
- intel-back_pixmap = back_pixmap;
- }
} else {
new_back = intel-back_buffer;
intel-back_buffer = NULL;
@@ -937,13 +886,8 @@ I830DRI2ScheduleFlip(struct intel_screen_private *intel,
intel-back_buffer = intel-front_buffer;
drm_intel_bo_reference(intel-back_buffer);
- if (!(intel-uxa_flags UXA_USE_GLAMOR)) {
- intel_set_pixmap_bo(priv-pixmap, new_back);
- drm_intel_bo_unreference(new_back);
- }
- else
- intel_exchange_pixmap_buffers(intel, priv-pixmap,
-
[Intel-gfx] [PATCH 07/12] Add intel_flush to abstract flushing pending acceleration operations
intel_flush flushes any pending acceleration operations to the
hardware, just like intel_uxa_batch_submit does today except that it is
not uxa-specific.
Signed-off-by: Keith Packard kei...@keithp.com
---
src/uxa/intel.h | 3 +++
src/uxa/intel_display.c | 11 +++
src/uxa/intel_driver.c | 14 +-
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/uxa/intel.h b/src/uxa/intel.h
index ade8742..64f573b 100644
--- a/src/uxa/intel.h
+++ b/src/uxa/intel.h
@@ -535,4 +535,7 @@ intel_get_pixmap_bo(PixmapPtr pixmap);
void
intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo *bo);
+void
+intel_flush(intel_screen_private *intel);
+
#endif /* _I830_H_ */
diff --git a/src/uxa/intel_display.c b/src/uxa/intel_display.c
index a4cbf00..add09b0 100644
--- a/src/uxa/intel_display.c
+++ b/src/uxa/intel_display.c
@@ -57,8 +57,6 @@
#include fb.h
#include uxa.h
-#include intel_glamor.h
-
#define KNOWN_MODE_FLAGS ((114)-1)
struct intel_drm_queue {
@@ -437,8 +435,7 @@ intel_crtc_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr
mode,
crtc-y = y;
crtc-rotation = rotation;
- intel_glamor_flush(intel);
- intel_batch_submit(crtc-scrn);
+intel_flush(intel);
mode_to_kmode(crtc-scrn, intel_crtc-kmode, mode);
ret = intel_crtc_apply(crtc);
@@ -1437,8 +1434,7 @@ intel_xf86crtc_resize(ScrnInfoPtr scrn, int width, int
height)
if (scrn-virtualX == width scrn-virtualY == height)
return TRUE;
- intel_glamor_flush(intel);
- intel_batch_submit(scrn);
+intel_flush(intel);
old_width = scrn-virtualX;
old_height = scrn-virtualY;
@@ -1552,8 +1548,7 @@ intel_do_pageflip(intel_screen_private *intel,
goto error_out;
drm_intel_bo_disable_reuse(new_front);
- intel_glamor_flush(intel);
- intel_batch_submit(scrn);
+intel_flush(intel);
mode-pageflip_data = pageflip_data;
mode-pageflip_handler = pageflip_handler;
diff --git a/src/uxa/intel_driver.c b/src/uxa/intel_driver.c
index d9f918b..a764b97 100644
--- a/src/uxa/intel_driver.c
+++ b/src/uxa/intel_driver.c
@@ -181,6 +181,12 @@ intel_get_pixmap_bo(PixmapPtr pixmap)
return intel_uxa_get_pixmap_bo(pixmap);
}
+void
+intel_flush(intel_screen_private *intel)
+{
+intel_batch_submit(intel-scrn);
+}
+
static void PreInitCleanup(ScrnInfoPtr scrn)
{
if (!scrn || !scrn-driverPrivate)
@@ -647,7 +653,7 @@ redisplay_dirty(ScreenPtr screen, PixmapDirtyUpdatePtr
dirty)
PixmapSyncDirtyHelper(dirty, pixregion);
RegionUninit(pixregion);
- intel_batch_submit(scrn);
+intel_flush(intel);
if (!intel-has_prime_vmap_flush) {
drm_intel_bo *bo =
intel_uxa_get_pixmap_bo(dirty-slave_dst-master_pixmap);
was_blocked = xf86BlockSIGIO();
@@ -732,10 +738,8 @@ intel_flush_callback(CallbackListPtr *list,
pointer user_data, pointer call_data)
{
ScrnInfoPtr scrn = user_data;
- if (scrn-vtSema) {
- intel_batch_submit(scrn);
- intel_glamor_flush(intel_get_screen_private(scrn));
- }
+ if (scrn-vtSema)
+intel_flush(intel_get_screen_private(scrn));
}
#if HAVE_UDEV
--
2.0.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/12] Get rid of glamor stubs in intel_glamor.h
This eliminates the stubs in intel_glamor.h and replaces them with
ifdefs instead.
Signed-off-by: Keith Packard kei...@keithp.com
---
src/uxa/intel_dri.c | 20 ++--
src/uxa/intel_driver.c | 6 ++
src/uxa/intel_glamor.h | 21 -
src/uxa/intel_present.c | 2 ++
src/uxa/intel_video.c | 4
5 files changed, 30 insertions(+), 23 deletions(-)
diff --git a/src/uxa/intel_dri.c b/src/uxa/intel_dri.c
index 79978ab..78734cb 100644
--- a/src/uxa/intel_dri.c
+++ b/src/uxa/intel_dri.c
@@ -66,7 +66,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include dri2.h
+#if USE_GLAMOR
#include intel_glamor.h
+#endif
#include uxa.h
typedef struct {
@@ -107,6 +109,7 @@ static PixmapPtr get_front_buffer(DrawablePtr drawable)
return pixmap;
}
+#if USE_GLAMOR
static PixmapPtr fixup_glamor(DrawablePtr drawable, PixmapPtr pixmap)
{
ScreenPtr screen = drawable-pScreen;
@@ -158,6 +161,7 @@ static PixmapPtr fixup_glamor(DrawablePtr drawable,
PixmapPtr pixmap)
intel_get_screen_private(xf86ScreenToScrn(screen))-needs_flush = TRUE;
return old;
}
+#endif
#if DRI2INFOREC_VERSION 2
static DRI2BufferPtr
@@ -170,7 +174,9 @@ I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int
*attachments,
DRI2BufferPtr buffers;
I830DRI2BufferPrivatePtr privates;
PixmapPtr pixmap, pDepthPixmap;
+#if USE_GLAMOR
Bool is_glamor_pixmap = FALSE;
+#endif
int i;
buffers = calloc(count, sizeof *buffers);
@@ -187,11 +193,12 @@ I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int
*attachments,
pixmap = NULL;
if (attachments[i] == DRI2BufferFrontLeft) {
pixmap = get_front_buffer(drawable);
-
+#if USE_GLAMOR
if (pixmap == NULL) {
drawable =
(get_drawable_pixmap(drawable)-drawable);
is_glamor_pixmap = TRUE;
}
+#endif
} else if (attachments[i] == DRI2BufferStencil pDepthPixmap)
{
pixmap = pDepthPixmap;
pixmap-refcnt++;
@@ -230,8 +237,10 @@ I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int
*attachments,
goto unwind;
}
+#if USE_GLAMOR
if (is_glamor_pixmap)
pixmap = fixup_glamor(drawable, pixmap);
+#endif
}
if (attachments[i] == DRI2BufferDepth)
@@ -292,7 +301,9 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int
attachment,
DRI2Buffer2Ptr buffer;
I830DRI2BufferPrivatePtr privates;
PixmapPtr pixmap;
+#if USE_GLAMOR
Bool is_glamor_pixmap = FALSE;
+#endif
buffer = calloc(1, sizeof *buffer);
if (buffer == NULL)
@@ -306,11 +317,12 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int
attachment,
pixmap = NULL;
if (attachment == DRI2BufferFrontLeft) {
pixmap = get_front_buffer(drawable);
-
+#if USE_GLAMOR
if (pixmap == NULL) {
drawable = (get_drawable_pixmap(drawable)-drawable);
is_glamor_pixmap = TRUE;
}
+#endif
}
if (pixmap == NULL) {
@@ -383,8 +395,10 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int
attachment,
free(buffer);
return NULL;
}
+#if USE_GLAMOR
if (is_glamor_pixmap)
pixmap = fixup_glamor(drawable, pixmap);
+#endif
}
buffer-attachment = attachment;
@@ -762,7 +776,9 @@ intel_exchange_pixmap_buffers(struct intel_screen_private
*intel, PixmapPtr fron
new_front-busy = 1;
new_back-busy = -1;
+#if USE_GLAMOR
intel_glamor_exchange_buffers(intel, front, back);
+#endif
DamageRegionProcessPending(front-drawable);
diff --git a/src/uxa/intel_driver.c b/src/uxa/intel_driver.c
index a764b97..6d38cfe 100644
--- a/src/uxa/intel_driver.c
+++ b/src/uxa/intel_driver.c
@@ -72,7 +72,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include i915_drm.h
+#if USE_GLAMOR
#include intel_glamor.h
+#endif
#include intel_options.h
static void i830AdjustFrame(ADJUST_FRAME_ARGS_DECL);
@@ -610,12 +612,14 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags)
return FALSE;
}
+#if USE_GLAMOR
if (!intel_glamor_pre_init(scrn)) {
PreInitCleanup(scrn);
xf86DrvMsg(scrn-scrnIndex, X_ERROR,
Failed to pre init glamor display.\n);
return FALSE;
}
+#endif
/* Load the dri modules if requested. */
#if HAVE_DRI2
@@ -1125,7 +1129,9 @@ static Bool I830CloseScreen(CLOSE_SCREEN_ARGS_DECL)
DeleteCallback(FlushCallback, intel_flush_callback, scrn);
+#if USE_GLAMOR
[Intel-gfx] [PATCH 11/12] Add none acceleration option
This just uses fb directly
Signed-off-by: Keith Packard kei...@keithp.com
---
configure.ac| 24 -
src/Makefile.am | 9 +-
src/intel_module.c | 12 ++-
src/uxa/Makefile.am | 46 ++---
src/uxa/intel.h | 5 +
src/uxa/intel_display.c | 6 ++
src/uxa/intel_dri3.c| 49 ++
src/uxa/intel_driver.c | 245 ++--
src/uxa/intel_glamor.c | 10 ++
src/uxa/intel_none.c| 189 +
src/uxa/intel_none.h| 38
src/uxa/intel_uxa.c | 9 ++
12 files changed, 504 insertions(+), 138 deletions(-)
create mode 100644 src/uxa/intel_none.c
create mode 100644 src/uxa/intel_none.h
diff --git a/configure.ac b/configure.ac
index 5c3dd20..46c3143 100644
--- a/configure.ac
+++ b/configure.ac
@@ -396,7 +396,6 @@ if test x$UXA = xauto; then
fi
if test x$UXA != xno; then
AC_DEFINE(USE_UXA, 1, [Enable UXA support])
- PKG_CHECK_MODULES(DRMINTEL, [libdrm_intel = $uxa_requires_libdrm])
required_pixman_version=0.24
UXA=yes
fi
@@ -407,9 +406,6 @@ AC_ARG_ENABLE(glamor,
[GLAMOR=$enableval],
[GLAMOR=no])
if test x$GLAMOR != xno; then
- if test x$UXA != xyes; then
- AC_MSG_ERROR([Glamor acceleration requested but UXA is not
enabled])
- fi
if pkg-config --exists xorg-server = 1.15.99.901; then
GLAMOR=yes (using Xorg glamor module)
else
@@ -417,9 +413,12 @@ if test x$GLAMOR != xno; then
PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
GLAMOR=yes (using libglamor)
fi
+ GLAMOR=yes
AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration])
fi
+PKG_CHECK_MODULES(DRMINTEL, [libdrm_intel = $uxa_requires_libdrm])
+
PKG_CHECK_MODULES(XORG, [xorg-server = $required_xorg_server_version xproto
fontsproto pixman-1 = $required_pixman_version $REQUIRED_MODULES])
ABI_VERSION=`$PKG_CONFIG --variable=abi_videodrv xorg-server`
@@ -661,6 +660,12 @@ if test x$accel = xauto; then
else
if test x$UXA != xno; then
accel=uxa
+ else
+ if test x$GLAMOR != xno; then
+ accel=glamor
+ else
+ accel=none
+ fi
fi
fi
if test x$accel = xauto -a x$KMS = xyes; then
@@ -696,6 +701,11 @@ if test x$accel = xglamor; then
fi
fi
+if test x$accel = xnone; then
+ AC_DEFINE(DEFAULT_ACCEL_METHOD, NONE, [Default acceleration method])
+ have_accel=yes
+fi
+
if test x$have_accel = xnone; then
if test x$KMS = xyes; then
AC_MSG_ERROR([Invalid default acceleration option])
@@ -886,6 +896,12 @@ if test x$GLAMOR != xno; then
fi
fi
+if test $accel = none; then
+ accel_msg=$accel_msg *none
+else
+ accel_msg=$accel_msg none
+fi
+
if test x$dri_msg = x; then
dri_msg= none
fi
diff --git a/src/Makefile.am b/src/Makefile.am
index aa8b47e..ce6f836 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -18,7 +18,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-SUBDIRS = render_program legacy
+SUBDIRS = render_program legacy uxa
# this is obnoxious:
# -module lets us name the module exactly how we want
@@ -41,18 +41,13 @@ endif
intel_drv_la_LTLIBRARIES = intel_drv.la
intel_drv_la_LDFLAGS = -module -avoid-version
intel_drv_ladir = $(moduledir)/drivers
-intel_drv_la_LIBADD = legacy/liblegacy.la $(PCIACCESS_LIBS) $(XORG_LIBS)
+intel_drv_la_LIBADD = legacy/liblegacy.la uxa/libuxa.la $(PCIACCESS_LIBS)
$(XORG_LIBS)
if SNA
SUBDIRS += sna
intel_drv_la_LIBADD += sna/libsna.la
endif
-if UXA
-SUBDIRS += uxa
-intel_drv_la_LIBADD += uxa/libuxa.la
-endif
-
NULL:=#
intel_drv_la_SOURCES = \
diff --git a/src/intel_module.c b/src/intel_module.c
index d6a0d3c..b8d7f91 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -489,7 +489,7 @@ _xf86findDriver(const char *ident, XF86ConfDevicePtr p)
return NULL;
}
-static enum accel_method { SNA, UXA, GLAMOR } get_accel_method(void)
+static enum accel_method { NONE, SNA, UXA, GLAMOR } get_accel_method(void)
{
enum accel_method accel_method = DEFAULT_ACCEL_METHOD;
XF86ConfDevicePtr dev;
@@ -509,6 +509,8 @@ static enum accel_method { SNA, UXA, GLAMOR }
get_accel_method(void)
accel_method = UXA;
else if (strcasecmp(s, glamor) == 0)
accel_method = GLAMOR;
+else if (strcasecmp(s, none) == 0)
+ accel_method = NONE;
}
}
@@ -564,12 +566,14 @@ intel_scrn_create(DriverPtr driver,
#if USE_SNA
case SNA: return
[Intel-gfx] [PATCH 12/12] Delay initial modeset until root window contents are prepared
Wait until the root window has been painted for the first time before
doing the modeset. This avoids flashing black while the root window
gets set up.
Signed-off-by: Keith Packard kei...@keithp.com
---
src/uxa/intel.h | 2 ++
src/uxa/intel_display.c | 39 ++-
src/uxa/intel_driver.c | 40 +++-
3 files changed, 55 insertions(+), 26 deletions(-)
diff --git a/src/uxa/intel.h b/src/uxa/intel.h
index ae33938..fa2aa64 100644
--- a/src/uxa/intel.h
+++ b/src/uxa/intel.h
@@ -194,6 +194,8 @@ typedef struct intel_screen_private {
void (*batch_flush) (struct intel_screen_private *intel);
void (*batch_commit_notify) (struct intel_screen_private *intel);
+Bool need_entervt;
+
#if USE_UXA
struct _UxaDriver *uxa_driver;
int uxa_flags;
diff --git a/src/uxa/intel_display.c b/src/uxa/intel_display.c
index 1d4ba3c..758f01f 100644
--- a/src/uxa/intel_display.c
+++ b/src/uxa/intel_display.c
@@ -2319,7 +2319,7 @@ void intel_copy_fb(ScrnInfoPtr scrn)
ScreenPtr pScreen = xf86ScrnToScreen(scrn);
intel_screen_private *intel = intel_get_screen_private(scrn);
PixmapPtr src, dst;
- unsigned int pitch = scrn-displayWidth * intel-cpp;
+GCPtr gc;
struct intel_crtc *intel_crtc;
int i, fbcon_id;
@@ -2339,30 +2339,27 @@ void intel_copy_fb(ScrnInfoPtr scrn)
if (src == NULL)
return;
- /* We dont have a screen Pixmap yet */
- dst = intel_create_pixmap_for_bo(pScreen, intel-front_buffer,
-scrn-virtualX, scrn-virtualY,
-scrn-depth, scrn-bitsPerPixel,
-pitch);
+dst = (*pScreen-GetScreenPixmap)(pScreen);
+
if (dst == NullPixmap)
goto cleanup_src;
- if (!intel-uxa_driver-prepare_copy(src, dst,
--1, -1,
-GXcopy, FB_ALLONES))
- goto cleanup_dst;
-
- intel-uxa_driver-copy(dst,
- 0, 0,
- 0, 0,
- scrn-virtualX, scrn-virtualY);
- intel-uxa_driver-done_copy(dst);
-#if ABI_VIDEODRV_VERSION = SET_ABI_VERSION(10, 0)
- pScreen-canDoBGNoneRoot = TRUE;
-#endif
+gc = GetScratchGC(scrn-depth, pScreen);
+
+if (!gc)
+goto cleanup_src;
+
+ValidateGC(dst-drawable, gc);
+
+(*gc-ops-CopyArea)(src-drawable,
+ dst-drawable,
+ gc,
+ 0, 0,
+ scrn-virtualX, scrn-virtualY,
+ 0, 0);
+
+FreeScratchGC(gc);
-cleanup_dst:
- (*pScreen-DestroyPixmap)(dst);
cleanup_src:
(*pScreen-DestroyPixmap)(src);
}
diff --git a/src/uxa/intel_driver.c b/src/uxa/intel_driver.c
index 316de64..0475a17 100644
--- a/src/uxa/intel_driver.c
+++ b/src/uxa/intel_driver.c
@@ -170,13 +170,19 @@ static Bool i830CreateScreenResources(ScreenPtr screen)
case ACCEL_GLAMOR:
if (!intel_glamor_create_screen_resources(screen))
return FALSE;
+#if ABI_VIDEODRV_VERSION = SET_ABI_VERSION(10, 0)
+screen-canDoBGNoneRoot = TRUE;
+#endif
break;
#endif
#if USE_UXA
case ACCEL_UXA:
if (!intel_uxa_create_screen_resources(screen))
return FALSE;
-intel_copy_fb(scrn);
+#if ABI_VIDEODRV_VERSION = SET_ABI_VERSION(10, 0)
+screen-canDoBGNoneRoot = TRUE;
+#endif
+break;
#endif
case ACCEL_NONE:
if (!intel_none_create_screen_resources(screen))
@@ -830,6 +836,29 @@ I830BlockHandler(BLOCKHANDLER_ARGS_DECL)
screen-BlockHandler = intel-BlockHandler;
+/* At server init time, get the root window bits from fbcon if
+ * available and then update the protocol-level information
+ * for both RandR and XINERAMA
+ */
+if (intel-need_entervt) {
+intel-need_entervt = FALSE;
+
+if (screen-root-backgroundState == None)
+intel_copy_fb(scrn);
+
+/* Must force it before EnterVT, so we are in control of VT and
+ * later memory should be bound when allocating, e.g
rotate_mem */
+scrn-vtSema = TRUE;
+
+if (!I830EnterVT(VT_FUNC_ARGS(0))) {
+xf86DrvMsg(scrn-scrnIndex, X_ERROR,
+ Failed to perform initial modeset.\n);
+FatalError(Mode set failed\n);
+}
+
+xf86RandR12CreateScreenResources(screen);
+}
+
(*screen-BlockHandler) (BLOCKHANDLER_ARGS);
[Intel-gfx] [PATCH 09/12] Do more checks for proposed flip pixmaps
Make sure the pitch and tiling are correct. Make sure there's a BO we can get at. Signed-off-by: Keith Packard kei...@keithp.com --- src/uxa/intel_present.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/uxa/intel_present.c b/src/uxa/intel_present.c index c53d71d..b901fb1 100644 --- a/src/uxa/intel_present.c +++ b/src/uxa/intel_present.c @@ -248,6 +248,8 @@ intel_present_check_flip(RRCrtcPtr crtc, ScreenPtr screen = window-drawable.pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); intel_screen_private*intel = intel_get_screen_private(scrn); +dri_bo *bo; +uint32_ttiling, swizzle; if (!scrn-vtSema) return FALSE; @@ -261,6 +263,22 @@ intel_present_check_flip(RRCrtcPtr crtc, if (crtc !intel_crtc_on(crtc-devPrivate)) return FALSE; +/* Check stride, can't change that on flip */ +if (pixmap-devKind != intel-front_pitch) +return FALSE; + +/* Make sure there's a bo we can get to */ +bo = intel_get_pixmap_bo(pixmap); +if (!bo) +return FALSE; + +/* Check tiling, can't change that on flip */ +if (drm_intel_bo_get_tiling((drm_intel_bo *) bo, tiling, swizzle) != 0) +return FALSE; + +if (tiling != intel-front_tiling) +return FALSE; + return TRUE; } -- 2.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/11] drm/i915: Register pipe level color properties
On Wed, Jul 23, 2014 at 11:34:56PM +0530, shashank.sha...@intel.com wrote:
From: Shashank Sharma shashank.sha...@intel.com
In valleyview we have two pipe level color correction
properties:
1. CSC correction (wide gamut)
2. Gamma correction
What this patch does:
1. This patch adds software infrastructure to register pipe level
color correction properties per CRTC. Adding a new function,
intel_attach_pipe_color_correction to register the pipe level
color correction properties with the given CRTC.
2. Adding a pointer in intel_crtc structure to store this property.
3. Adding structure gen6_pipe_color_corrections, which contains different
pipe level correction values for VLV.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
...snip...
+struct drm_property *intel_clrmgr_register(struct drm_device *dev,
+ struct drm_mode_object *obj, struct clrmgr_property *cp)
+{
+ struct drm_property *property;
+
+ /* Create drm property */
+ switch (cp-type) {
+ case DRM_MODE_PROP_BLOB:
+ property = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ cp-name, cp-len);
+ if (!property) {
+ DRM_ERROR(Failed to create property %s\n, cp-name);
+ goto error;
+ }
+ break;
+
+ case DRM_MODE_PROP_RANGE:
+ property = drm_property_create_range(dev, DRM_MODE_PROP_RANGE,
+ cp-name, cp-min, cp-max);
+ if (!property) {
+ DRM_ERROR(Failed to create property %s\n, cp-name);
+ goto error;
+ }
+ break;
+
+ default:
+ DRM_ERROR(Unsupported type for property %s\n, cp-name);
+ goto error;
+ }
+ /* Attach property to object */
+ drm_object_attach_property(obj, property, 0);
+ DRM_DEBUG_DRIVER(Registered property %s\n, property-name);
+ return property;
+
+error:
+ DRM_ERROR(Failed to create property %s\n, cp-name);
+ return NULL;
+}
If I'm reading this right, you're creating a unique property for each
DRM object (crtc in this case) that you work with. I.e., if you have
three pipes, then you wind up creating three CSC and three gamma
properties total. This isn't really the way properties are meant to be
used... A property describes a type of data that you want to store on a
per-object basis, but doesn't actually store anything itself. You can
then attach that single property to multiple objects and all of those
objects will track their own value of the quantity described by the
property. It's sort of like the difference between classes and objects
in OOP --- a DRM property is sort of like a class (just describes
something you plan to store) and attaching that property to a CRTC (or
plane, or connector) is like instantiating a new object of the class.
You should really only have two properties being created by the driver
here...one for CSC and one for Gamma. Once you've created a property
once, you'll attach it to all of your CRTC's and they'll all manage
their own values.
Matt
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling Development
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 00/11]: Color manager framework for I915 driver
On Thu, Jul 24, 2014 at 04:08:41AM +, Sharma, Shashank wrote:
Hi Daniel,
Thanks for your time and comments.
The current design is exactly same as we discussed previously in the mail
chain, color manager is just the framework which does this job:
1. Create a DRM property for requesting object.
2. Attach the DRM property with the object.
I didn't see Daniel's response when I sent my other message, but I had a
lot of the same thoughts that he brought up. I think my previous email
explains one of the concerns here --- properties don't hold values, so
you only need to create a property once total (well, technically once
per DRM device), not once per object.
Once you stop creating duplicate properties, you don't really need the
color manager framework at all. Just find an appropriate driver init
function and create each property once, storing the property pointer
somewhere in dev_priv (or, if these properties can become cross-driver
standard properties, they'd be created once by the DRM core and stored
in drm_device).
There is no other job done here in the framework, no parsing and nothing
else.
The color manager data structures also just add and array of DRM properties
for an object (CRTC/PIPE) and total no of DRM properties.
So there is nothing which is not required.
Typical sequence of how it works:
1. intel CRTC init calls color-manager init for that CRTC, gets a color
pointer, which has space to save DRM properties.
2. intel CRTC init calls attach color properties, which will register
the DRM property, add into the color pointer, and return.
CRTC init can just attach the (already created as described above)
properties to the new CRTC being created. No special color manager
interface calls needed.
3. A CRTC set property checks if this is color property, calls
color-manager-set-property.
4. Color manager set-property calls core set property function, which
takes care of calling platform specific set_propety function.
This level of indirection seems unnecessary.
intel_{crtc,plane}-set_property() can just point at functions that just
do:
if (property == dev_priv-foo_property) {
// do foo stuff;
} else if (property == dev_priv-bar_property) {
// do bar stuff;
} else if (property == dev_priv-baz_property) {
// do baz stuff;
} ...
The properties you're adding now as part of the color manager will
likely be joined by other, unrelated propeties in the future. There's
no need to isolate color manager properties behind another level of
function pointer abstraction.
5. Color manager exit gets call from CRTC/plane destroy, and frees the
DRM property per CRTC/plane, plus color pointer.
As with init, these can just be moved to the proper crtc/plane tear down
functions; no need to pull them out into separate color manager
functions.
Can you please point out, which of the above steps is not falling in line for
you?
I think Daniel's big point is that the i915 driver has (or will
eventually have) lots of crtc and plane properties that do various
things. You're pulling some of those properties out into a separate
framework that you call color manager that simply adds indirection.
But that extra indirection doesn't really add any value; the DRM core,
with its property support, is already all the framework we need.
Matt
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling Development
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH] NEWS: Updates
On Wed, Jul 23, 2014 at 10:32:43PM +0200, Daniel Vetter wrote: --- NEWS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/NEWS b/NEWS index 1b5ee83ec849..4866d59b5619 100644 --- a/NEWS +++ b/NEWS @@ -10,6 +10,12 @@ Release 1.8 (-xx-xx) - As usual piles of new tests. +- Improved plane/pipe handling in the igt_kms library (Damien). + +- Unified option parsing between simple tests and tests with subtests (Thomas). + This will allow us to merge the different Makefile targets once test runners + are converted. + Might be worth adding a bullet for the new commit style support in igt_kms (igt_display_commit2 / igt_display_try_commit2). That allows us to expose the universal plane interfaces today and also provides a natural way to expose atomic interfaces in the future. Matt Release 1.7 (2014-06-09) -- 2.0.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v2 1/1] drm/i915: Power gating display wells during i915_pm_suspend
On 23 July 2014 15:11, Daniel Vetter dan...@ffwll.ch wrote: On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kam...@intel.com wrote: From: Borun Fu borun...@intel.com On VLV, after i915_pm_suspend display power wells are staying power ungated. So, after initiating mem sleep echo mem /sys/power/state Display is staing D0 State. There might be better way/place to power gate these wells. Also, we need to make sure that if wells are power gated due to DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. [Daniel] Cc: Imre Deak imre.d...@intel.com Cc: Paulo Zanoni paulo.r.zan...@intel.com Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Jani Nikula jani.nik...@linux.intel.com Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 s-o-b from the original author (Borun Fu) missing. Added myself since we all work for the same company, but please don't forget this. Every person including the original author, who handles a patch must add their sob line. -Daniel Is this queued or on its way, I was getting a warning on HSW about not entering pc8+ due to display with MST enabled, and I thought it was MSTs fault, but I suspect its just this, mode set turns the global resources power well on, but nothing ever turns it off. Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/11]: Color manager framework for I915 driver
Thanks for your time, and review comments Matt.
I appreciate the suggestions by you, Daniel.
But I need a few more details, and I have a few concerns with the design
you suggest, please find my comments inline.
Regards
Shashank
On 7/25/2014 6:13 AM, Matt Roper wrote:
On Thu, Jul 24, 2014 at 04:08:41AM +, Sharma, Shashank wrote:
Hi Daniel,
Thanks for your time and comments.
The current design is exactly same as we discussed previously in the mail
chain, color manager is just the framework which does this job:
1. Create a DRM property for requesting object.
2. Attach the DRM property with the object.
I didn't see Daniel's response when I sent my other message, but I had a
lot of the same thoughts that he brought up. I think my previous email
explains one of the concerns here --- properties don't hold values, so
you only need to create a property once total (well, technically once
per DRM device), not once per object.
Once you stop creating duplicate properties, you don't really need the
color manager framework at all. Just find an appropriate driver init
function and create each property once, storing the property pointer
somewhere in dev_priv (or, if these properties can become cross-driver
standard properties, they'd be created once by the DRM core and stored
in drm_device).
Matt, do you suggest to create one DRM property named CSC for all pipes
? And one drm property named Gamma for all pipes ?
Can you please elaborate a bit more in this part: Create a DRM property
and attach to ech CRTC, managing their own values.
In this design the current design, I have few concerns here, on your
suggestion:
1. If I enable gamma correction on one pipe (pipe A, driving DSI
display) but don't apply gamma correction on other (pipe B, driving
HDMI), how to maintain the state of each, without adding additional
complexity in the driver. I have to create some additional data
structure and attach to dev_priv.
2. The previously applied values are to be stored somewhere, to be
re-stored in case of suspend/resume.
Plus, If I create a core DRM property for each of the color corrections,
not all HWs running DRM driver will have properties like CSC, Gamma, Hue
and Saturation, Contrast, Brightness. It would be a waste for them to
have this.
There is no other job done here in the framework, no parsing and nothing else.
The color manager data structures also just add and array of DRM properties for
an object (CRTC/PIPE) and total no of DRM properties.
So there is nothing which is not required.
Typical sequence of how it works:
1. intel CRTC init calls color-manager init for that CRTC, gets a color
pointer, which has space to save DRM properties.
2. intel CRTC init calls attach color properties, which will register
the DRM property, add into the color pointer, and return.
CRTC init can just attach the (already created as described above)
properties to the new CRTC being created. No special color manager
interface calls needed.
3. A CRTC set property checks if this is color property, calls
color-manager-set-property.
4. Color manager set-property calls core set property function, which
takes care of calling platform specific set_propety function.
This level of indirection seems unnecessary.
intel_{crtc,plane}-set_property() can just point at functions that just
do:
if (property == dev_priv-foo_property) {
// do foo stuff;
} else if (property == dev_priv-bar_property) {
// do bar stuff;
} else if (property == dev_priv-baz_property) {
// do baz stuff;
} ...
The properties you're adding now as part of the color manager will
likely be joined by other, unrelated propeties in the future. There's
no need to isolate color manager properties behind another level of
function pointer abstraction.
The main problems I see here is:
1. drm property doesn't hold a space to have a .set_property callback,
so we have to hardcode this every time, based on the platform and
property. For example, Gamma correction method in VLV and big core is
entirely different. Some platfroms might not even support
gamma_corerction, but some might support advance gamma_corerction.
2. If I have 10 properties, I keep on populating dev_priv with 10
pointers, for each property, and end up writing a lot of if (property ==
dev_priv-some_property), do something.
Seeing the increase of no of DRM properties, this doesn't look good.
3. every time there is a new platform or there is a new color property
added, I have to modify these places intel_crtc_set_property,
intel_plane_set_property, and add/remove one if condition.
Now, if we use color-manager, it would provide solutions for them in
this way (also explains the need of color-manager data structures):
1. add a container data structure name color_property, which just holds
a drm_property*, a bool status (to show if this current property
