Re: [Intel-gfx] [PATCH] drm/i915/skl: Fix a stale comment in the DDB allocation code
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6361 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB 342/342 342/342 BYT 286/286 286/286 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/chv: Extend set idle rps wa to chv
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6362 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK -1 302/302 301/302 SNB 316/316 316/316 IVB 342/342 342/342 BYT 286/286 286/286 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied *ILK igt@drv_suspend@fence-restore-tiled2untiled PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:drm_edid_block_valid[drm]]*ERROR*EDID_checksum_is_invalid,remainder_is@EDID checksum is .* remainder is Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/vlv: Remove wait for for punit to updates freq.
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
v2: Do forcewake before setting idle frequency (ville)
Update function comments to match the code (Deepak)
v3: Fix get/put across idle frequency Request. (Ville)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
suggested-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 41 +++--
1 file changed, 11 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a7516ed..82dfdbc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4043,51 +4043,32 @@ static void valleyview_set_rps(struct drm_device *dev,
u8 val)
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
}
-/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
+/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
*
* * If Gfx is Idle, then
- * 1. Mask Turbo interrupts
- * 2. Bring up Gfx clock
- * 3. Change the freq to Rpn and wait till P-Unit updates freq
- * 4. Clear the Force GFX CLK ON bit so that Gfx can down
- * 5. Unmask Turbo interrupts
+ * 1. Forcewake Media well.
+ * 2. Request idle freq.
+ * 3. Release Forcewake of Media well.
*/
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv-dev;
u32 val = dev_priv-rps.idle_freq;
- /* CHV and latest VLV don't need to force the gfx clock */
- if (IS_CHERRYVIEW(dev) || dev-pdev-revision = 0xd) {
+ /* CHV don't need to force the gfx clock */
+ if (IS_CHERRYVIEW(dev)) {
valleyview_set_rps(dev_priv-dev, val);
return;
}
- /*
-* When we are idle. Drop to min voltage state.
-*/
-
if (dev_priv-rps.cur_freq = val)
return;
- /* Mask turbo interrupt so that they will not come in between */
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_sanitize_rps_pm_mask(dev_priv, ~0));
-
- vlv_force_gfx_clock(dev_priv, true);
-
- dev_priv-rps.cur_freq = val;
-
- vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
-
- if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
-GENFREQSTATUS) == 0, 100))
- DRM_ERROR(timed out waiting for Punit\n);
-
- gen6_set_rps_thresholds(dev_priv, val);
- vlv_force_gfx_clock(dev_priv, false);
-
- I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
+ /* Wake up the media well, as that takes a lot less
+* power than the Render well. */
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
+ valleyview_set_rps(dev_priv-dev, val);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
}
void gen6_rps_busy(struct drm_i915_private *dev_priv)
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/edid: Kerneldoc for newly added edid_corrupt
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6360 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB -1 314/314 313/314 IVB 338/338 338/338 BYT 286/286 286/286 BDW 320/320 320/320 -Detailed- Platform Testdrm-intel-nightly Series Applied SNB igt@pm_rpm@dpms-mode-unset-non-lpsp DMESG_WARN(3)PASS(1) DMESG_WARN(2) (dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/chv: Extend set idle rps wa to chv
From: Deepak S deepa...@linux.intel.com
It is observed on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let GPU enter rc6
with a high frequency, Vnn remains slightly higher than at minimum
frequency. Extending vlv_set_rps_idle() workaround on CHV/BSW.
v2: Update commit msg (Ville)
suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82dfdbc..064f11a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4052,15 +4052,8 @@ static void valleyview_set_rps(struct drm_device *dev,
u8 val)
*/
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{
- struct drm_device *dev = dev_priv-dev;
u32 val = dev_priv-rps.idle_freq;
- /* CHV don't need to force the gfx clock */
- if (IS_CHERRYVIEW(dev)) {
- valleyview_set_rps(dev_priv-dev, val);
- return;
- }
-
if (dev_priv-rps.cur_freq = val)
return;
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915: Be optimistic about future display engines having 7 WM levels
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6368 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB 342/342 342/342 BYT 286/286 286/286 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915/chv: Set min freq to efficient frequency on chv
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the vgg input voltage to
minimum :(
Since Punit validates the rps range [RPe, RP0]. This patch
removes unused cherryview_rps_min_freq function.
v2: Change commit message
v3: set min_freq before idle_freq (chris)
v4: Squash 'Remove unused rps min function' patch
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 064f11a..c229d7e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4689,24 +4689,6 @@ static int cherryview_rps_guar_freq(struct
drm_i915_private *dev_priv)
return rp1;
}
-static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
-{
- struct drm_device *dev = dev_priv-dev;
- u32 val, rpn;
-
- if (dev-pdev-revision = 0x20) {
- val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
- rpn = ((val FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT)
- FB_GFX_FREQ_FUSE_MASK);
- } else { /* For pre-production hardware */
- val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
- rpn = ((val PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT)
- PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
- }
-
- return rpn;
-}
-
static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp1;
@@ -4958,7 +4940,8 @@ static void cherryview_init_gt_powersave(struct
drm_device *dev)
intel_gpu_freq(dev_priv, dev_priv-rps.rp1_freq),
dev_priv-rps.rp1_freq);
- dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ /* PUnit validated range is only [RPe, RP0] */
+ dev_priv-rps.min_freq = dev_priv-rps.efficient_freq;
DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n,
intel_gpu_freq(dev_priv, dev_priv-rps.min_freq),
dev_priv-rps.min_freq);
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915: Remove unused variable from i915_gem_mmap_gtt
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6363 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB -1 314/314 313/314 IVB 338/338 338/338 BYT 286/286 286/286 BDW -1 320/320 319/320 -Detailed- Platform Testdrm-intel-nightly Series Applied SNB igt@pm_rpm@dpms-mode-unset-non-lpsp DMESG_WARN(3)PASS(1) DMESG_WARN(2) (dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x *BDW igt@gem_gtt_hog PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_display.c:#assert_plane[i915]()@WARNING:.* at .* assert_plane assertion_failure@assertion failure WARNING:at_drivers/gpu/drm/drm_irq.c:#drm_wait_one_vblank[drm]()@WARNING:.* at .* drm_wait_one_vblank+0x Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Enable runtime pm
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6366 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB 342/342 342/342 BYT 286/286 286/286 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] tests: Add KMS blob-property test
Exercises the new blob-creation ioctl, testing lifetimes and behaviour
of user-created blobs, as well as exercising all the invariant
conditions we guarantee from modes exposed as blob properties.
Signed-off-by: Daniel Stone dani...@collabora.com
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_prop_blob.c | 226 +
3 files changed, 228 insertions(+)
create mode 100644 tests/kms_prop_blob.c
Kernel support:
http://lists.freedesktop.org/archives/dri-devel/2015-May/082530.html
libdrm support:
http://lists.freedesktop.org/archives/dri-devel/2015-May/082569.html
diff --git a/tests/.gitignore b/tests/.gitignore
index 86795c0..eb505d0 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -138,6 +138,7 @@ kms_mmio_vs_cs_flip
kms_pipe_b_c_ivb
kms_pipe_crc_basic
kms_plane
+kms_prop_blob
kms_psr_sink_crc
kms_pwrite_crc
kms_render
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 12f27f9..9a89167 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -70,6 +70,7 @@ TESTS_progs_M = \
kms_pipe_b_c_ivb \
kms_pipe_crc_basic \
kms_plane \
+ kms_prop_blob \
kms_psr_sink_crc \
kms_render \
kms_rotation_crc \
diff --git a/tests/kms_prop_blob.c b/tests/kms_prop_blob.c
new file mode 100644
index 000..03b85a9
--- /dev/null
+++ b/tests/kms_prop_blob.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright © 2014-2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Damien Lespiau damien.lesp...@intel.com
+ * Daniel Stone dani...@collabora.com
+ */
+
+#include errno.h
+#include stdbool.h
+#include stdio.h
+#include string.h
+
+#include drmtest.h
+#include igt_debugfs.h
+#include igt_kms.h
+#include igt_aux.h
+
+IGT_TEST_DESCRIPTION(Tests behaviour of mass-data 'blob' properties.);
+
+static const struct drm_mode_modeinfo test_mode_valid = {
+ .clock = 1234,
+ .hdisplay = 640,
+ .hsync_start = 641,
+ .hsync_end = 642,
+ .htotal = 643,
+ .hskew = 0,
+ .vdisplay = 480,
+ .vsync_start = 481,
+ .vsync_end = 482,
+ .vtotal = 483,
+ .vscan = 0,
+ .vrefresh = 6,
+ .flags = 0,
+ .type = 0,
+ .name = FROMUSER,
+};
+
+
+static int
+validate_prop(int fd, uint32_t prop_id)
+{
+ struct drm_mode_get_blob get;
+ struct drm_mode_modeinfo ret_mode;
+ int err;
+
+ get.blob_id = prop_id;
+ get.length = 0;
+ get.data = (uintptr_t) 0;
+
+ err = drmIoctl(fd, DRM_IOCTL_MODE_GETPROPBLOB, get);
+ if (err != 0)
+ return err;
+
+ if (get.length != sizeof(test_mode_valid))
+ return ENOMEM;
+
+ get.data = (uintptr_t) ret_mode;
+
+ err = drmIoctl(fd, DRM_IOCTL_MODE_GETPROPBLOB, get);
+ if (err != 0)
+ return err;
+
+ if (memcmp(ret_mode, test_mode_valid, sizeof(test_mode_valid)) != 0)
+ return EINVAL;
+
+ return 0;
+}
+
+static uint32_t
+create_prop(int fd)
+{
+ struct drm_mode_create_blob create;
+
+ create.length = sizeof(test_mode_valid);
+ create.data = (uintptr_t) test_mode_valid;
+
+ do_ioctl(fd, DRM_IOCTL_MODE_CREATEPROPBLOB, create);
+
+ return create.blob_id;
+}
+
+static int
+destroy_prop(int fd, uint32_t prop_id)
+{
+ struct drm_mode_destroy_blob destroy;
+ int err;
+
+ destroy.blob_id = prop_id;
+ err = drmIoctl(fd, DRM_IOCTL_MODE_DESTROYPROPBLOB, destroy);
+ return err;
+}
+
+static void
+test_validate(int fd)
+{
+ struct drm_mode_create_blob create;
+ struct drm_mode_get_blob get;
+ char too_small[32];
+ uint32_t prop_id;
+ int ret;
+
+ memset(too_small, 0, sizeof(too_small));
+
+ /* Outlandish size. */
+ create.length = 0x1;
+ create.data =
Re: [Intel-gfx] [PATCH v3] drm/i915/vlv: Remove wait for for punit to updates freq.
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6370 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB 342/342 342/342 BYT 286/286 286/286 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
