Re: [Intel-gfx] [PATCH 13/16] drm/i915: don't use the first stolen page on Broadwell
On Sat, Aug 15, 2015 at 09:30:18AM +0100, Chris Wilson wrote: On Fri, Aug 14, 2015 at 06:34:18PM -0300, Paulo Zanoni wrote: The spec says we just can't use it. But what about when we inherit a framebuffer at that address? Indeed. I asked the same question several times during the past attempts at this, and even tried to outline a potential solution at least once [1] Also limiting it to BDW is insufficient. CHV needs it too. [1] http://lists.freedesktop.org/archives/intel-gfx/2014-July/049924.html -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Split alloc from init for lrc
On Wed, Aug 19, 2015 at 01:24:28PM +0100, Nick Hoath wrote:
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr_context_deferred_alloc, to reflect reduced functionality
alloc/init split.
This patch is intended to split out the allocation of resources
initialisation
to allow easier reuse of code for resume/gpu reset.
v2: Removed function ptr wrapping of do_switch_context (Daniel Vetter)
Left -init_context int intel_lr_context_deferred_alloc (Daniel Vetter)
Remove unnecessary init flag ring type test. (Daniel Vetter)
Improve commit message (Daniel Vetter)
v3: On init/reinit, set the hw next sequence number to the sw next sequence
number. This is set to 1 at driver load time. This prevents the seqno
being reset on reinit (Chris Wilson)
Issue: VIZ-4798
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h| 1 -
drivers/gpu/drm/i915/i915_gem.c| 18 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-
drivers/gpu/drm/i915/intel_lrc.c | 147
++---
drivers/gpu/drm/i915/intel_lrc.h | 4 +-
5 files changed, 86 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7fd519..844ccf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -880,7 +880,6 @@ struct intel_context {
} legacy_hw_ctx;
/* Execlists */
- bool rcs_initialized;
struct {
struct drm_i915_gem_object *state;
struct intel_ringbuffer *ringbuf;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 73293b4..eb7c1f2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4603,14 +4603,8 @@ int i915_gem_init_rings(struct drm_device *dev)
goto cleanup_vebox_ring;
}
- ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
- if (ret)
- goto cleanup_bsd2_ring;
-
return 0;
-cleanup_bsd2_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[VCS2]);
cleanup_vebox_ring:
intel_cleanup_ring_buffer(dev_priv-ring[VECS]);
cleanup_blt_ring:
@@ -4629,6 +4623,7 @@ i915_gem_init_hw(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_engine_cs *ring;
int ret, i, j;
+ struct drm_i915_gem_request *req;
if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
return -EIO;
@@ -4680,9 +4675,12 @@ i915_gem_init_hw(struct drm_device *dev)
goto out;
}
+ ret = i915_gem_set_seqno(dev, dev_priv-next_seqno);
+ if (ret)
+ goto out;
The only reason to do this would be to ensure that the contents of the
registers are valid (assuming we take over from ourselves). The right
value to use then is last_seqno.
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 923a3c4..95f1a0d 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -994,6 +994,7 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
{
struct intel_context *ctx = NULL;
struct i915_ctx_hang_stats *hs;
+ int ret;
if (ring-id != RCS ctx_id != DEFAULT_CONTEXT_HANDLE)
return ERR_PTR(-EINVAL);
@@ -1009,7 +1010,7 @@ i915_gem_validate_context(struct drm_device *dev,
struct drm_file *file,
}
if (i915.enable_execlists !ctx-engine[ring-id].state) {
- int ret = intel_lr_context_deferred_create(ctx, ring);
+ ret = intel_lr_context_deferred_alloc(ctx, ring);
if (ret) {
DRM_DEBUG(Could not create LRC %u: %d\n, ctx_id, ret);
return ERR_PTR(ret);
Still modifying this for no reason, and you still haven't realised this
call is redundant (hint there is already a hook in alloc_request).
From last year:
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?id=37fbd370152211688bc5bce3d28d13233cfe7d8b
More recent (i.e a couple of months ago):
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=nightlyid=ba4950a8f489d54ec4898f94dad44f9ec13301d2
-Chris
--
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Re: [Intel-gfx] [PATCH 11/15] drm/i915: Enable DPIO SUS clock gating on CHV
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has supports some form of automagic clock gating for the
DPIO SUS clock. We can simply enable the magic bits and the
hardware should take care of the rest.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcfcbb62..8010200 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1133,6 +1133,10 @@ enum skl_disp_power_wells {
#define CHV_CMN_DW28 0x8170
#define DPIO_CL1POWERDOWNEN (1 23)
#define DPIO_DYNPWRDOWNEN_CH0 (1 22)
+#define DPIO_SUS_CLK_CONFIG_ON (0 0)
+#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 0)
+#define DPIO_SUS_CLK_CONFIG_GATE (2 0)
+#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 0)
#define CHV_CMN_DW30 0x8178
#define DPIO_LRC_BYPASS (1 3)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 551cf08..37e4375 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -972,7 +972,8 @@ static void chv_dpio_cmn_power_well_enable(struct
drm_i915_private *dev_priv,
/* Enable dynamic power down */
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
- tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN;
+ tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
+ DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
if (power_well-data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
Changes looks fine as per Bspec.
Reviewed-by: Deepak S deepa...@linux.intel.com
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Re: [Intel-gfx] [PATCH 12/15] drm/i915: Force CL2 off in CHV x1 PHY
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We can choose to leave the display PHY CL2 powerdown up to some hardware
signals, or we can force it. The BXT code forces the nonexistent CL2 in
the x1 PHY to power down. Follow suit on CHV. Maybe it can still save
some extra power by disabling some extra logic in CL1, or something.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8010200..395f556 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1139,6 +1139,7 @@ enum skl_disp_power_wells {
#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 0)
#define CHV_CMN_DW30 0x8178
+#define DPIO_CL2_LDOFUSE_PWRENB (1 6)
#define DPIO_LRC_BYPASS (1 3)
#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 37e4375..002b78f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -980,6 +980,15 @@ static void chv_dpio_cmn_power_well_enable(struct
drm_i915_private *dev_priv,
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
+ } else {
+ /*
+* Force the non-existing CL2 off. BXT does this
+* too, so maybe it saves some power even though
+* CL2 doesn't exist?
+*/
+ tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
+ tmp |= DPIO_CL2_LDOFUSE_PWRENB;
+ vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
}
Do we need to turn off CL2 each time we enable dpio cmn power wells?
btw, changes looks fine
Reviewed-by: Deepak S deepa...@linux.intel.com
mutex_unlock(dev_priv-sb_lock);
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Re: [Intel-gfx] [PATCH 2/4] drm/i915: Adding Panel Filter function for DP
On Wed, Aug 19, 2015 at 09:11:11AM +, Zhang, Xiong Y wrote:
On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote:
On Fri, Aug 14, 2015 at 05:12:57AM +, Zhang, Xiong Y wrote:
On Mon, Aug 10, 2015 at 03:26:09PM +0800, Xiong Zhang wrote:
Only internal eDP, LVDS, DVI screen could set scalling mode, some
customers need to set scalling mode for external DP, HDMI, VGA
screen.
Let's fulfill this.
bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90989
Signed-off-by: Xiong Zhang xiong.y.zh...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 63
-
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c index f1b9f93..2da334b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -207,7 +207,13 @@ intel_dp_mode_valid(struct drm_connector
*connector,
int target_clock = mode-clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
- if (is_edp(intel_dp) fixed_mode) {
+ if (mode-clock 1)
+ return MODE_CLOCK_LOW;
+
+ if (mode-flags DRM_MODE_FLAG_DBLCLK)
+ return MODE_H_ILLEGAL;
+
+ if (!intel_panel_scale_none(intel_connector-panel)) {
if (mode-hdisplay fixed_mode-hdisplay)
return MODE_PANEL;
@@ -226,12 +232,6 @@ intel_dp_mode_valid(struct drm_connector
*connector,
if (mode_rate max_rate)
return MODE_CLOCK_HIGH;
- if (mode-clock 1)
- return MODE_CLOCK_LOW;
-
- if (mode-flags DRM_MODE_FLAG_DBLCLK)
- return MODE_H_ILLEGAL;
-
return MODE_OK;
}
@@ -1378,7 +1378,7 @@ intel_dp_compute_config(struct
intel_encoder
*encoder,
pipe_config-has_drrs = false;
pipe_config-has_audio = intel_dp-has_audio port != PORT_A;
- if (is_edp(intel_dp) intel_connector-panel.fixed_mode) {
+ if (!intel_panel_scale_none(intel_connector-panel)) {
intel_fixed_panel_mode(intel_connector-panel.fixed_mode,
adjusted_mode);
@@ -4592,6 +4592,23 @@ static int intel_dp_get_modes(struct
drm_connector *connector)
edid = intel_connector-detect_edid;
if (edid) {
int ret = intel_connector_update_modes(connector, edid);
+
+ if (ret intel_connector-panel.fixed_mode == NULL) {
+ /* init fixed mode as preferred mode for DP */
+ struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *scan;
+
+ list_for_each_entry(scan,
connector-probed_modes,
head) {
+ if (scan-type
DRM_MODE_TYPE_PREFERRED)
+ fixed_mode =
drm_mode_duplicate(connector-dev,
+
scan);
+ }
+
+ if (fixed_mode)
+
intel_panel_init(intel_connector-panel,
+fixed_mode, NULL);
+ }
How are we supposed to get rid of a stale fixed_mode when some other
display gets plugged in?
[Zhang, Xiong Y] Thanks so much for your good question. Yes, we should
clear the
stale fitting_mode and fixed_mode when display is disconnect in
intel_dp_hpd_pulse() function.
Also what would happen if the preferred mode can't be supported due to
some
source limitation?
[Zhang, Xiong Y] In this case, which mode should be selected as
fixed_mode ?
At the very least we should make sure it's a mode we can use.
As you said maybe kernel isn't the right place to do such decision.
There are a lot of options how we could pick the mode. Eg. might want to
pick the next largest mode, and if there is none try to pick the largest
smaller mode (since pfit can't downscale by much). Also should we try to
pick an intelaced mode if the user requested one etc. Lots of open
questions how this policy should be handled. Would be easier to punt it
all to userspace, which would also avoid the kernel policy doing the
wrong thing when userspace knows what it wants.
In general I'm not entirely happy with having this kind of policy in
the
kernel.
I'd much prefer if we could get crtc size and border properties done
so
that
userspace could set up the scaling any which way it chooses.
[Zhang, Xiong Y] Could you give more detail about your
[Intel-gfx] [PATCH] drm/i915: Split alloc from init for lrc
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr_context_deferred_alloc, to reflect reduced functionality
alloc/init split.
This patch is intended to split out the allocation of resources initialisation
to allow easier reuse of code for resume/gpu reset.
v2: Removed function ptr wrapping of do_switch_context (Daniel Vetter)
Left -init_context int intel_lr_context_deferred_alloc (Daniel Vetter)
Remove unnecessary init flag ring type test. (Daniel Vetter)
Improve commit message (Daniel Vetter)
v3: On init/reinit, set the hw next sequence number to the sw next sequence
number. This is set to 1 at driver load time. This prevents the seqno
being reset on reinit (Chris Wilson)
Issue: VIZ-4798
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h| 1 -
drivers/gpu/drm/i915/i915_gem.c| 18 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-
drivers/gpu/drm/i915/intel_lrc.c | 147 ++---
drivers/gpu/drm/i915/intel_lrc.h | 4 +-
5 files changed, 86 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7fd519..844ccf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -880,7 +880,6 @@ struct intel_context {
} legacy_hw_ctx;
/* Execlists */
- bool rcs_initialized;
struct {
struct drm_i915_gem_object *state;
struct intel_ringbuffer *ringbuf;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 73293b4..eb7c1f2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4603,14 +4603,8 @@ int i915_gem_init_rings(struct drm_device *dev)
goto cleanup_vebox_ring;
}
- ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
- if (ret)
- goto cleanup_bsd2_ring;
-
return 0;
-cleanup_bsd2_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[VCS2]);
cleanup_vebox_ring:
intel_cleanup_ring_buffer(dev_priv-ring[VECS]);
cleanup_blt_ring:
@@ -4629,6 +4623,7 @@ i915_gem_init_hw(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_engine_cs *ring;
int ret, i, j;
+ struct drm_i915_gem_request *req;
if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
return -EIO;
@@ -4680,9 +4675,12 @@ i915_gem_init_hw(struct drm_device *dev)
goto out;
}
+ ret = i915_gem_set_seqno(dev, dev_priv-next_seqno);
+ if (ret)
+ goto out;
+
/* Now it is safe to go back round and do everything else: */
for_each_ring(ring, dev_priv, i) {
- struct drm_i915_gem_request *req;
WARN_ON(!ring-default_context);
@@ -4881,6 +4879,12 @@ i915_gem_load(struct drm_device *dev)
dev_priv-num_fence_regs =
I915_READ(vgtif_reg(avail_rs.fence_num));
+ /*
+* Set initial sequence number for requests.
+ */
+ dev_priv-next_seqno = 1;
+ dev_priv-last_seqno = ~((uint32_t)0);
+
/* Initialize fence registers to zero */
INIT_LIST_HEAD(dev_priv-mm.fence_list);
i915_gem_restore_fences(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 923a3c4..95f1a0d 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -994,6 +994,7 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
{
struct intel_context *ctx = NULL;
struct i915_ctx_hang_stats *hs;
+ int ret;
if (ring-id != RCS ctx_id != DEFAULT_CONTEXT_HANDLE)
return ERR_PTR(-EINVAL);
@@ -1009,7 +1010,7 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
}
if (i915.enable_execlists !ctx-engine[ring-id].state) {
- int ret = intel_lr_context_deferred_create(ctx, ring);
+ ret = intel_lr_context_deferred_alloc(ctx, ring);
if (ret) {
DRM_DEBUG(Could not create LRC %u: %d\n, ctx_id, ret);
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 138964a..d0dc6b5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1426,11 +1426,31 @@ out:
return ret;
}
+static void
Re: [Intel-gfx] [PATCH 12/15] drm/i915: Force CL2 off in CHV x1 PHY
On Wed, Aug 19, 2015 at 06:52:57PM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We can choose to leave the display PHY CL2 powerdown up to some hardware
signals, or we can force it. The BXT code forces the nonexistent CL2 in
the x1 PHY to power down. Follow suit on CHV. Maybe it can still save
some extra power by disabling some extra logic in CL1, or something.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index 8010200..395f556 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1139,6 +1139,7 @@ enum skl_disp_power_wells {
#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 0)
#define CHV_CMN_DW30 0x8178
+#define DPIO_CL2_LDOFUSE_PWRENB (1 6)
#define DPIO_LRC_BYPASS (1 3)
#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 37e4375..002b78f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -980,6 +980,15 @@ static void chv_dpio_cmn_power_well_enable(struct
drm_i915_private *dev_priv,
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
+ } else {
+ /*
+* Force the non-existing CL2 off. BXT does this
+* too, so maybe it saves some power even though
+* CL2 doesn't exist?
+*/
+ tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
+ tmp |= DPIO_CL2_LDOFUSE_PWRENB;
+ vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
}
Do we need to turn off CL2 each time we enable dpio cmn power wells?
Yes, all DPIO registers lose their state when the power well is off.
btw, changes looks fine
Reviewed-by: Deepak S deepa...@linux.intel.com
mutex_unlock(dev_priv-sb_lock);
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Intel OTC
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[Intel-gfx] [PATCH i-g-t] tests/gem_ctx_exec.c: only hang the ring we are testing
From: Tim Gore tim.g...@intel.com
In the reset-pin-leak test we were calling
igt_set_stop_rings(STOP_RING_DEFAULTS) which sets the
stop_rings bits for all gpu engines. But we only submit
work to the render engine. When TDR is enabled (as it is
in Android currently) only the render engine gets reset,
which clears the stop_rings bit for the render engine but
not for the other engines. This causes the test to fail on
the second iteration because stop_rings is not clear.
So just set the stop_rings bit for the engine we are going
to hang, namely the render engine.
Signed-off-by: Tim Gore tim.g...@intel.com
---
tests/gem_ctx_exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_ctx_exec.c b/tests/gem_ctx_exec.c
index 3df939c..b4e7f31 100644
--- a/tests/gem_ctx_exec.c
+++ b/tests/gem_ctx_exec.c
@@ -207,7 +207,7 @@ igt_main
* the last context is leaked at every reset.
*/
for (i = 0; i 20; i++) {
- igt_set_stop_rings(STOP_RING_DEFAULTS);
+
igt_set_stop_rings(igt_to_stop_ring_flag(I915_EXEC_RENDER));
igt_assert(exec(fd, handle, I915_EXEC_RENDER, 0) == 0);
igt_assert(exec(fd, handle, I915_EXEC_RENDER, ctx_id)
== 0);
gem_sync(fd, handle);
--
1.9.1
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Re: [Intel-gfx] [PATCH 09/15] drm/i915: Trick CL2 into life on CHV when using pipe B with port B
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Patch looks fine. It does what it says. One Q, why only for port B? Port
C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B-port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A-port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Reviewed-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
drivers/gpu/drm/i915/intel_drv.h| 3 +++
drivers/gpu/drm/i915/intel_hdmi.c | 23 +++
drivers/gpu/drm/i915/intel_runtime_pm.c | 29 +
4 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 6058129..8d088f3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2865,6 +2865,12 @@ static void chv_pre_enable_dp(struct intel_encoder
*encoder)
mutex_unlock(dev_priv-sb_lock);
intel_enable_dp(encoder);
+
+ /* Second common lane will stay alive on its own now */
+ if (dport-release_cl2_override) {
+ chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
+ dport-release_cl2_override = false;
+ }
}
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
@@ -2882,6 +2888,14 @@ static void chv_dp_pre_pll_enable(struct
intel_encoder *encoder)
intel_dp_prepare(encoder);
+ /*
+* Must trick the second common lane into life.
+* Otherwise we can't even access the PLL.
+*/
+ if (ch == DPIO_CH0 pipe == PIPE_B)
+ dport-release_cl2_override =
+ !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1,
true);
+
chv_phy_powergate_lanes(encoder, true, lane_mask);
mutex_lock(dev_priv-sb_lock);
@@ -2960,6 +2974,15 @@ static void chv_dp_post_pll_disable(struct
intel_encoder *encoder)
mutex_unlock(dev_priv-sb_lock);
+ /*
+* Leave the power down bit cleared for at least one
+* lane so that chv_powergate_phy_ch() will power
+* on something when the channel is otherwise unused.
+* When the port is off and the override is removed
+* the lanes power down anyway, so otherwise it doesn't
+* really matter what the state of power down bits is
+* after this.
+*/
chv_phy_powergate_lanes(encoder, false, 0x0);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index f8a16dc..6133a98 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -782,6 +782,7 @@ struct intel_digital_port {
struct intel_dp dp;
struct intel_hdmi hdmi;
enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
+ bool release_cl2_override;
};
struct intel_dp_mst_encoder {
@@ -1372,6 +1373,8 @@ void intel_display_set_init_power(struct
drm_i915_private *dev, bool enable);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask);
+bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy
phy,
+ enum dpio_channel ch, bool override);
/* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index b3f6c9f..4b604ee 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++
Re: [Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 7216 -Summary- Platform Delta drm-intel-nightly Series Applied ILK -1 283/283 282/283 SNB 315/315 315/315 IVB 336/336 336/336 BYT 283/283 283/283 HSW 378/378 378/378 -Detailed- Platform Testdrm-intel-nightly Series Applied *ILK igt@kms_flip@flip-vs-dpms-interruptible PASS(1) DMESG_WARN(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Adding Panel Filter function for DP
On Wednesday 19 August 2015 09:11:11 Zhang, Xiong Y wrote: On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote: Another thing we could do with this approach is expose the pipe PF-ID mode when the fixed mode is interlaced and the user mode is progressive. And if both are interlaced, or there's just an interlaced used mode w/o a fixed mode, we'd keep using IF-ID like we do today. [Zhang, Xiong Y] I checked the B spec, there isn't PF-ID / IF-ID control bit in PIPE_CONF since BDW. I never see a monitor supporting interlaced mode. Does a monitor could support both Interlaced and progressive mode ? Most of the computer monitors I see support interlaced modes on HDMI; I usually see CEA-861 VIC 5 (1920x1080i60) and VIC 20 (1920x1080i50) supported on HDMI by computer monitors. -- Simon Farnsworth Software Engineer ONELAN Ltd http://www.onelan.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/15] drm/i915: Force common lane on for the PPS kick on CHV
On Wed, Aug 19, 2015 at 07:51:57AM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
With DPIO powergating active the DPLL can't be accessed unless
something else is keeping the common lane in the channel on.
That means the PPS kick procedure could fail to enable the PLL.
Power up some data lanes to force the common lane to power up
so that the PLL can be enabled temporarily.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 8d088f3..817df87 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -341,7 +341,9 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
enum pipe pipe = intel_dp-pps_pipe;
- bool pll_enabled;
+ bool pll_enabled, release_cl_override;
+ enum dpio_phy phy = DPIO_PHY(pipe);
+ enum dpio_channel ch = vlv_pipe_to_channel(pipe);
uint32_t DP;
if (WARN(I915_READ(intel_dp-output_reg) DP_PORT_EN,
@@ -371,9 +373,13 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
* The DPLL for the pipe must be enabled for this to work.
* So enable temporarily it if it's not already enabled.
*/
- if (!pll_enabled)
+ if (!pll_enabled) {
+ release_cl_override = IS_CHERRYVIEW(dev)
+ !chv_phy_powergate_ch(dev_priv, phy, ch, true);
+
vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
chv_dpll[0].dpll : vlv_dpll[0].dpll);
+ }
/*
* Similar magic as in intel_dp_enable_port().
@@ -390,8 +396,12 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
I915_WRITE(intel_dp-output_reg, DP ~DP_PORT_EN);
POSTING_READ(intel_dp-output_reg);
- if (!pll_enabled)
+ if (!pll_enabled) {
vlv_force_pll_off(dev, pipe);
+
+ if (release_cl_override)
+ chv_phy_powergate_ch(dev_priv, phy, ch, false);
+ }
}
static enum pipe
Change looks fine
Reviewed-by: Deepak S deepa...@linux.intel.com
Note to Daniel: Please pick up v2 of this patch. The only change
was release_cl_override=false initialization to avoid a gcc warning.
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: add common intel_digital_port_connected function
On Wed, 19 Aug 2015, Jani Nikula jani.nik...@intel.com wrote:
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 53
++---
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4aa3d664765b..d48af8b0c84e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4473,15 +4473,8 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-/*
- * ibx_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
- *
- * Returns true if @port is connected, false otherwise.
- */
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
-struct intel_digital_port *port)
+static int ibx_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
{
u32 bit;
@@ -4497,7 +4490,7 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG;
break;
default:
- return true;
+ return 1;
}
} else {
switch (port-port) {
@@ -4511,20 +4504,19 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
- return true;
+ return 1;
BTW a follow-up could look into making the ibx/cpt default cases return
-EINVAL like the g4x/vlv/bxt cases do.
BR,
Jani.
}
}
- return I915_READ(SDEISR) bit;
+ return I915_READ(SDEISR) bit ? 1 : 0;
}
-static int g4x_digital_port_connected(struct drm_device *dev,
-struct intel_digital_port
*intel_dig_port)
+static int g4x_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
uint32_t bit;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv)) {
switch (intel_dig_port-port) {
case PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
@@ -4559,6 +4551,22 @@ static int g4x_digital_port_connected(struct
drm_device *dev,
return 1;
}
+/*
+ * intel_digital_port_connected - is the specified port connected?
+ * @dev_priv: i915 private structure
+ * @port: the port to test
+ *
+ * Returns a negative error code on errors, 1 for connected, 0 for
disconnected.
+ */
+static int intel_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
+{
+ if (HAS_PCH_SPLIT(dev_priv))
+ return ibx_digital_port_connected(dev_priv, port);
+ else
+ return g4x_digital_port_connected(dev_priv, port);
+}
+
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
@@ -4566,7 +4574,7 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
+ if (intel_digital_port_connected(dev_priv, intel_dig_port) != 1)
return connector_status_disconnected;
return intel_dp_detect_dpcd(intel_dp);
@@ -4589,7 +4597,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
return status;
}
- ret = g4x_digital_port_connected(dev, intel_dig_port);
+ ret = intel_digital_port_connected(dev-dev_private, intel_dig_port);
if (ret == -EINVAL)
return connector_status_unknown;
else if (ret == 0)
@@ -5055,13 +5063,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
/* indicate that we need to restart link training */
intel_dp-train_set_valid = false;
- if (HAS_PCH_SPLIT(dev)) {
- if (!ibx_digital_port_connected(dev_priv,
intel_dig_port))
- goto mst_fail;
- } else {
- if (g4x_digital_port_connected(dev, intel_dig_port) !=
1)
- goto mst_fail;
- }
+ if (intel_digital_port_connected(dev_priv, intel_dig_port) != 1)
+ goto mst_fail;
if (!intel_dp_get_dpcd(intel_dp)) {
goto mst_fail;
--
Re: [Intel-gfx] [PATCH v2] drm/i915: Change SRM, LRM instructions to use correct length
Arun Siluvery arun.siluv...@linux.intel.com writes:
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM instructions are not really
variable length instructions unlike MI_LOAD_REGISTER_IMM where it expects
(reg, addr) pairs so use fixed length for these instructions.
v2: rebase
Cc: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 8
drivers/gpu/drm/i915/i915_reg.h| 8
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 430571b..3771922 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -124,14 +124,14 @@ static const struct drm_i915_cmd_descriptor
common_cmds[] = {
CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
.reg = { .offset = 1, .mask = 0x007C, .step = 2 }),
- CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
+ CMD( MI_STORE_REGISTER_MEM,SMI,F, 1, W | B,
.reg = { .offset = 1, .mask = 0x007C },
.bits = {{
.offset = 0,
.mask = MI_GLOBAL_GTT,
.expected = 0,
}}, ),
- CMD( MI_LOAD_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
+ CMD( MI_LOAD_REGISTER_MEM, SMI,F, 1, W | B,
.reg = { .offset = 1, .mask = 0x007C },
.bits = {{
.offset = 0,
@@ -1021,7 +1021,7 @@ static bool check_cmd(const struct intel_engine_cs
*ring,
* only MI_LOAD_REGISTER_IMM commands.
*/
if (reg_addr == OACONTROL) {
- if (desc-cmd.value == MI_LOAD_REGISTER_MEM(1))
{
+ if (desc-cmd.value == MI_LOAD_REGISTER_MEM) {
DRM_DEBUG_DRIVER(CMD: Rejected LRM to
OACONTROL\n);
return false;
}
@@ -1035,7 +1035,7 @@ static bool check_cmd(const struct intel_engine_cs
*ring,
* allowed mask/value pair given in the whitelist entry.
*/
if (reg-mask) {
- if (desc-cmd.value == MI_LOAD_REGISTER_MEM(1))
{
+ if (desc-cmd.value == MI_LOAD_REGISTER_MEM) {
DRM_DEBUG_DRIVER(CMD: Rejected LRM to
masked register 0x%08X\n,
reg_addr);
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 827714c..e1a8876 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -343,8 +343,8 @@
*/
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
#define MI_LRI_FORCE_POSTED(112)
-#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
-#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
+#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
+#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT (122)
#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
#define MI_FLUSH_DW_STORE_INDEX(121)
@@ -355,8 +355,8 @@
#define MI_INVALIDATE_BSD (17)
#define MI_FLUSH_DW_USE_GTT(12)
#define MI_FLUSH_DW_USE_PPGTT (02)
-#define MI_LOAD_REGISTER_MEM(x) MI_INSTR(0x29, 2*(x)-1)
-#define MI_LOAD_REGISTER_MEM_GEN8(x) MI_INSTR(0x29, 3*(x)-1)
+#define MI_LOAD_REGISTER_MEMMI_INSTR(0x29, 1)
+#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
Minor nitpick: checkpatch complained about there being space before
tab in here.
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
#define MI_BATCH_NON_SECURE(1)
/* for snb/ivb/vlv this also means batch in ppgtt when ppgtt is enabled. */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index af0bcfe..e8f1c95 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11123,10 +11123,10 @@ static int intel_gen7_queue_flip(struct drm_device
*dev,
DERRMR_PIPEB_PRI_FLIP_DONE |
DERRMR_PIPEC_PRI_FLIP_DONE));
if (IS_GEN8(dev))
-
[Intel-gfx] [PATCH 1/5] drm/i915: move ibx_digital_port_connected to intel_dp.c
The function can be made static there. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 45 --
drivers/gpu/drm/i915/intel_dp.c | 61 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 --
3 files changed, 53 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f604ce1c528b..1a0670259cdf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1061,51 +1061,6 @@ static void intel_wait_for_pipe_off(struct intel_crtc
*crtc)
}
}
-/*
- * ibx_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
- *
- * Returns true if @port is connected, false otherwise.
- */
-bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
-{
- u32 bit;
-
- if (HAS_PCH_IBX(dev_priv-dev)) {
- switch (port-port) {
- case PORT_B:
- bit = SDE_PORTB_HOTPLUG;
- break;
- case PORT_C:
- bit = SDE_PORTC_HOTPLUG;
- break;
- case PORT_D:
- bit = SDE_PORTD_HOTPLUG;
- break;
- default:
- return true;
- }
- } else {
- switch (port-port) {
- case PORT_B:
- bit = SDE_PORTB_HOTPLUG_CPT;
- break;
- case PORT_C:
- bit = SDE_PORTC_HOTPLUG_CPT;
- break;
- case PORT_D:
- bit = SDE_PORTD_HOTPLUG_CPT;
- break;
- default:
- return true;
- }
- }
-
- return I915_READ(SDEISR) bit;
-}
-
static const char *state_string(bool enabled)
{
return enabled ? on : off;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d32ce4841654..4aa3d664765b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4473,17 +4473,49 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-static enum drm_connector_status
-ironlake_dp_detect(struct intel_dp *intel_dp)
+/*
+ * ibx_digital_port_connected - is the specified port connected?
+ * @dev_priv: i915 private structure
+ * @port: the port to test
+ *
+ * Returns true if @port is connected, false otherwise.
+ */
+static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ u32 bit;
- if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
- return connector_status_disconnected;
+ if (HAS_PCH_IBX(dev_priv-dev)) {
+ switch (port-port) {
+ case PORT_B:
+ bit = SDE_PORTB_HOTPLUG;
+ break;
+ case PORT_C:
+ bit = SDE_PORTC_HOTPLUG;
+ break;
+ case PORT_D:
+ bit = SDE_PORTD_HOTPLUG;
+ break;
+ default:
+ return true;
+ }
+ } else {
+ switch (port-port) {
+ case PORT_B:
+ bit = SDE_PORTB_HOTPLUG_CPT;
+ break;
+ case PORT_C:
+ bit = SDE_PORTC_HOTPLUG_CPT;
+ break;
+ case PORT_D:
+ bit = SDE_PORTD_HOTPLUG_CPT;
+ break;
+ default:
+ return true;
+ }
+ }
- return intel_dp_detect_dpcd(intel_dp);
+ return I915_READ(SDEISR) bit;
}
static int g4x_digital_port_connected(struct drm_device *dev,
@@ -4528,6 +4560,19 @@ static int g4x_digital_port_connected(struct drm_device
*dev,
}
static enum drm_connector_status
+ironlake_dp_detect(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+
+ if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
+ return connector_status_disconnected;
+
+ return intel_dp_detect_dpcd(intel_dp);
+}
+
+static enum drm_connector_status
g4x_dp_detect(struct intel_dp *intel_dp)
{
struct drm_device *dev =
[Intel-gfx] [PATCH 0/5] drm/i915: clean up *_digital_port_connected
Durgadoss' patch made me look at the {ibx,g4x}_digital_port_connected
functions, and I decided those need some love. No point in having the
platform specific code split both to functions and if ladders within
those functions. So add one common top level
intel_digital_port_connected function with one if ladder splitting out
to purely platform specific functions.
BR,
Jani.
Jani Nikula (5):
drm/i915: move ibx_digital_port_connected to intel_dp.c
drm/i915: add common intel_digital_port_connected function
drm/i915: split ibx_digital_port_connected to ibx and cpt variants
drm/i915: split g4x_digital_port_connected to g4x and vlv variants
drm/i915/bxt: Use correct live status register for BXT platform
drivers/gpu/drm/i915/intel_display.c | 45 -
drivers/gpu/drm/i915/intel_dp.c | 186 +--
drivers/gpu/drm/i915/intel_drv.h | 2 -
3 files changed, 136 insertions(+), 97 deletions(-)
--
2.1.4
___
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[Intel-gfx] [PATCH 5/5] drm/i915/bxt: Use correct live status register for BXT platform
BXT platform uses live status bits from 0x0 register to obtain DP
status on hotplug. The existing g4x_digital_port_connected() uses a
different register and hence misses DP hotplug events on BXT
platform. This patch fixes it by using the appropriate register(0x0)
and live status bits(3:5).
Based on a patch by Durgadoss R durgados...@intel.com, from whom the
commit message is shamelessly copy pasted.
Reported-by: Durgadoss R durgados...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bc3b94fa15cb..c6d4bb62e83a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4561,6 +4561,28 @@ static int vlv_digital_port_connected(struct
drm_i915_private *dev_priv,
return I915_READ(PORT_HOTPLUG_STAT) bit ? 1 : 0;
}
+static int bxt_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
+{
+ u32 bit;
+
+ switch (port-port) {
+ case PORT_A:
+ bit = BXT_DE_PORT_HP_DDIA;
+ break;
+ case PORT_B:
+ bit = BXT_DE_PORT_HP_DDIB;
+ break;
+ case PORT_C:
+ bit = BXT_DE_PORT_HP_DDIC;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return I915_READ(GEN8_DE_PORT_ISR) bit ? 1 : 0;
+}
+
/*
* intel_digital_port_connected - is the specified port connected?
* @dev_priv: i915 private structure
@@ -4577,6 +4599,8 @@ static int intel_digital_port_connected(struct
drm_i915_private *dev_priv,
return cpt_digital_port_connected(dev_priv, port);
else if (IS_VALLEYVIEW(dev_priv))
return vlv_digital_port_connected(dev_priv, port);
+ else if (IS_BROXTON(dev_priv))
+ return bxt_digital_port_connected(dev_priv, port);
else
return g4x_digital_port_connected(dev_priv, port);
}
--
2.1.4
___
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[Intel-gfx] [PATCH 2/5] drm/i915: add common intel_digital_port_connected function
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 53 ++---
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4aa3d664765b..d48af8b0c84e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4473,15 +4473,8 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-/*
- * ibx_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
- *
- * Returns true if @port is connected, false otherwise.
- */
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static int ibx_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
{
u32 bit;
@@ -4497,7 +4490,7 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG;
break;
default:
- return true;
+ return 1;
}
} else {
switch (port-port) {
@@ -4511,20 +4504,19 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
- return true;
+ return 1;
}
}
- return I915_READ(SDEISR) bit;
+ return I915_READ(SDEISR) bit ? 1 : 0;
}
-static int g4x_digital_port_connected(struct drm_device *dev,
- struct intel_digital_port
*intel_dig_port)
+static int g4x_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
uint32_t bit;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv)) {
switch (intel_dig_port-port) {
case PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
@@ -4559,6 +4551,22 @@ static int g4x_digital_port_connected(struct drm_device
*dev,
return 1;
}
+/*
+ * intel_digital_port_connected - is the specified port connected?
+ * @dev_priv: i915 private structure
+ * @port: the port to test
+ *
+ * Returns a negative error code on errors, 1 for connected, 0 for
disconnected.
+ */
+static int intel_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
+{
+ if (HAS_PCH_SPLIT(dev_priv))
+ return ibx_digital_port_connected(dev_priv, port);
+ else
+ return g4x_digital_port_connected(dev_priv, port);
+}
+
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
@@ -4566,7 +4574,7 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
+ if (intel_digital_port_connected(dev_priv, intel_dig_port) != 1)
return connector_status_disconnected;
return intel_dp_detect_dpcd(intel_dp);
@@ -4589,7 +4597,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
return status;
}
- ret = g4x_digital_port_connected(dev, intel_dig_port);
+ ret = intel_digital_port_connected(dev-dev_private, intel_dig_port);
if (ret == -EINVAL)
return connector_status_unknown;
else if (ret == 0)
@@ -5055,13 +5063,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
/* indicate that we need to restart link training */
intel_dp-train_set_valid = false;
- if (HAS_PCH_SPLIT(dev)) {
- if (!ibx_digital_port_connected(dev_priv,
intel_dig_port))
- goto mst_fail;
- } else {
- if (g4x_digital_port_connected(dev, intel_dig_port) !=
1)
- goto mst_fail;
- }
+ if (intel_digital_port_connected(dev_priv, intel_dig_port) != 1)
+ goto mst_fail;
if (!intel_dp_get_dpcd(intel_dp)) {
goto mst_fail;
--
2.1.4
___
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[Intel-gfx] [PATCH 3/5] drm/i915: split ibx_digital_port_connected to ibx and cpt variants
Choose the right function at the intel_digital_port_connected level.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 66 +++--
1 file changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d48af8b0c84e..2cb95dc88ba7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4478,34 +4478,40 @@ static int ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
{
u32 bit;
- if (HAS_PCH_IBX(dev_priv-dev)) {
- switch (port-port) {
- case PORT_B:
- bit = SDE_PORTB_HOTPLUG;
- break;
- case PORT_C:
- bit = SDE_PORTC_HOTPLUG;
- break;
- case PORT_D:
- bit = SDE_PORTD_HOTPLUG;
- break;
- default:
- return 1;
- }
- } else {
- switch (port-port) {
- case PORT_B:
- bit = SDE_PORTB_HOTPLUG_CPT;
- break;
- case PORT_C:
- bit = SDE_PORTC_HOTPLUG_CPT;
- break;
- case PORT_D:
- bit = SDE_PORTD_HOTPLUG_CPT;
- break;
- default:
- return 1;
- }
+ switch (port-port) {
+ case PORT_B:
+ bit = SDE_PORTB_HOTPLUG;
+ break;
+ case PORT_C:
+ bit = SDE_PORTC_HOTPLUG;
+ break;
+ case PORT_D:
+ bit = SDE_PORTD_HOTPLUG;
+ break;
+ default:
+ return 1;
+ }
+
+ return I915_READ(SDEISR) bit ? 1 : 0;
+}
+
+static int cpt_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
+{
+ u32 bit;
+
+ switch (port-port) {
+ case PORT_B:
+ bit = SDE_PORTB_HOTPLUG_CPT;
+ break;
+ case PORT_C:
+ bit = SDE_PORTC_HOTPLUG_CPT;
+ break;
+ case PORT_D:
+ bit = SDE_PORTD_HOTPLUG_CPT;
+ break;
+ default:
+ return 1;
}
return I915_READ(SDEISR) bit ? 1 : 0;
@@ -4561,8 +4567,10 @@ static int g4x_digital_port_connected(struct
drm_i915_private *dev_priv,
static int intel_digital_port_connected(struct drm_i915_private *dev_priv,
struct intel_digital_port *port)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_IBX(dev_priv))
return ibx_digital_port_connected(dev_priv, port);
+ if (HAS_PCH_SPLIT(dev_priv))
+ return cpt_digital_port_connected(dev_priv, port);
else
return g4x_digital_port_connected(dev_priv, port);
}
--
2.1.4
___
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[Intel-gfx] [PATCH 4/5] drm/i915: split g4x_digital_port_connected to g4x and vlv variants
Choose the right function at the intel_digital_port_connected level.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 72 ++---
1 file changed, 39 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2cb95dc88ba7..bc3b94fa15cb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4518,43 +4518,47 @@ static int cpt_digital_port_connected(struct
drm_i915_private *dev_priv,
}
static int g4x_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *intel_dig_port)
+ struct intel_digital_port *port)
{
- uint32_t bit;
+ u32 bit;
- if (IS_VALLEYVIEW(dev_priv)) {
- switch (intel_dig_port-port) {
- case PORT_B:
- bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
- break;
- case PORT_C:
- bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
- break;
- case PORT_D:
- bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
- break;
- default:
- return -EINVAL;
- }
- } else {
- switch (intel_dig_port-port) {
- case PORT_B:
- bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
- break;
- case PORT_C:
- bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
- break;
- case PORT_D:
- bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
- break;
- default:
- return -EINVAL;
- }
+ switch (port-port) {
+ case PORT_B:
+ bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
+ break;
+ case PORT_C:
+ bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
+ break;
+ case PORT_D:
+ bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
+ break;
+ default:
+ return -EINVAL;
}
- if ((I915_READ(PORT_HOTPLUG_STAT) bit) == 0)
- return 0;
- return 1;
+ return I915_READ(PORT_HOTPLUG_STAT) bit ? 1 : 0;
+}
+
+static int vlv_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
+{
+ u32 bit;
+
+ switch (port-port) {
+ case PORT_B:
+ bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
+ break;
+ case PORT_C:
+ bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
+ break;
+ case PORT_D:
+ bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return I915_READ(PORT_HOTPLUG_STAT) bit ? 1 : 0;
}
/*
@@ -4571,6 +4575,8 @@ static int intel_digital_port_connected(struct
drm_i915_private *dev_priv,
return ibx_digital_port_connected(dev_priv, port);
if (HAS_PCH_SPLIT(dev_priv))
return cpt_digital_port_connected(dev_priv, port);
+ else if (IS_VALLEYVIEW(dev_priv))
+ return vlv_digital_port_connected(dev_priv, port);
else
return g4x_digital_port_connected(dev_priv, port);
}
--
2.1.4
___
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Re: [Intel-gfx] [PATCH 07/16] drm/i915: disable FBC on FIFO underruns
On Fri, Aug 14, 2015 at 06:34:12PM -0300, Paulo Zanoni wrote:
If we want to try to enable FBC by default on any platform we need to
be on the safe side and disable it in case we get an underrun while
FBC is enabled on the corresponding pipe. We currently already have
other reasons for FIFO underruns on our driver, but the ones I saw
with FBC lead to black screens that only go away when you disable FBC.
We don't try to deal with underruns on other platforms either, and yes
on some, cough, chv, cough, they can definitely blank out the screen
until the next modeset. On even older platforms it's even worse and an
underrun can kill the display engine until display reset/reboot :(
Especially annoying on gen2 where we have no reset support. So I'm not
entirely convinced FBC deserves special treatment here.
The current FIFO underrun I see happens when the CFB is using the top
8mb of stolen memory. This is reproducible with a 2560x1440 DP Monitor
on a system with 32mb of stolen memory. On this case, all the IGT
tests fail while checking the screen CRC. A later patch on this series
will fix this problem for real.
With this patch, the tests will start failing while checking if FBC is
enabled instead of failing while comparing the CRC of the black screen
against the correct CRC. So this patch is not hiding any IGT bugs: the
tests still fail, but now they fail with a different reason.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 5 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_fbc.c | 61
++
drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +
4 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4fd7858..e74a844 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -926,6 +926,11 @@ struct i915_fbc {
struct drm_framebuffer *fb;
} *fbc_work;
+ struct intel_fbc_underrun_work {
+ struct work_struct work;
+ struct intel_crtc *crtc;
+ } underrun_work;
+
enum no_fbc_reason {
FBC_OK, /* FBC is enabled */
FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index 81b7d77..246925d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1247,6 +1247,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin);
const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
+void intel_fbc_handle_fifo_underrun(struct intel_crtc *crtc);
/* intel_hdmi.c */
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c
b/drivers/gpu/drm/i915/intel_fbc.c
index a63d10a..28e569c 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -955,6 +955,65 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
mutex_unlock(dev_priv-fbc.lock);
}
+static void intel_fbc_underrun_work_fn(struct work_struct *__work)
+{
+ struct intel_fbc_underrun_work *work =
+ container_of(__work, struct intel_fbc_underrun_work, work);
+ struct intel_crtc *crtc = work-crtc;
+ struct drm_i915_private *dev_priv = crtc-base.dev-dev_private;
+
+ mutex_lock(dev_priv-fbc.lock);
+ if (!intel_fbc_enabled(dev_priv) || dev_priv-fbc.crtc != crtc)
+ goto out;
+
+ DRM_DEBUG_KMS(Disabling FBC due to FIFO underrun.\n);
+ i915.enable_fbc = 0;
+ __intel_fbc_disable(dev_priv);
+
+out:
+ work-crtc = NULL;
+ mutex_unlock(dev_priv-fbc.lock);
+}
+
+/**
+ * intel_fbc_handle_fifo_underrun - handle FIFO underruns if FBC is enabled
+ * @crtc: the CRTC that caused the underrun
+ *
+ * Although we can't know for sure what caused an underrun, one of the
possible
+ * reasons is FBC. And on the FBC case, the user may have a black screen
until
+ * FBC is disabled. So whenever a FIFO underrun happens while FBC is enabled,
+ * disable FBC just because it may help.
+ *
+ * We disable FBC by changing the i915 param, so FBC won't come back on the
next
+ * frame just to cause another underrun. Test suites can force FBC back by
+ * changing the module parameter again through sysfs.
+ */
+void intel_fbc_handle_fifo_underrun(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc-base.dev-dev_private;
+ struct intel_fbc_underrun_work *work = dev_priv-fbc.underrun_work;
+
+ if (!dev_priv-fbc.enable_fbc)
+ return;
+
+ /* These checks are unlocked. We can't grab the lock since we're in the
+ * IRQ
Re: [Intel-gfx] [PATCH] drm/i915: Only move to the CPU write domain if keeping the GTT pages
On Sun, Aug 9, 2015 at 7:02 PM, Goel, Akash akash.g...@intel.com wrote: On 8/9/2015 6:19 PM, Chris Wilson wrote: On Sun, Aug 09, 2015 at 05:11:52PM +0530, Goel, Akash wrote: On 8/9/2015 4:25 PM, Chris Wilson wrote: On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote: On 8/7/2015 1:37 PM, Daniel Vetter wrote: I presume though you only want to avoid clflush when actually purging an object, so maybe we can keep this by purging the shmem backing node first and checking here for __I915_MADV_PURGED instead? An object marked as MADV_DONT_NEED, implies that it will be purged/truncated right away after the call to put_pages_gtt function. So doing the other way round by purging first and then checking for __I915_MADV_PURGED, might be equivalent. But disregards a few nice sanity checks, which I would like to keep. -Chris Fine, just wanted to convey that doing the other way round may not be really beneficial. About the other point of virtually indexed/physically tagged cache, would it be safe just rely on the MADV_DONT_NEED state of the object (which indicates that there are no active CPU mmappings) ? Due to an earlier CPU mmappings, there could be cachelines holding the stale data ? If the conflicts survive munmap(), I don't have a clever idea on how to avoid the clflush before we hand back the pages to the system. One case could be, as you suggested, check if ever there was a CPU mapping created for the object so avoid the clflush for GPU (GPU + GTT) only objects. We have verified (on BYT/CHV) that cachelines corresponding to object's pages do not get invalidated on munmap, so there is a possibility of stale data even when no CPU mappings are active. So we need to amend this patch to also check if ever there was a CPU mapping created for the object. Best regards Akash Best regards Akash -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Split alloc from init for lrc
On 19/08/2015 13:37, Chris Wilson wrote:
On Wed, Aug 19, 2015 at 01:24:28PM +0100, Nick Hoath wrote:
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr_context_deferred_alloc, to reflect reduced functionality
alloc/init split.
This patch is intended to split out the allocation of resources initialisation
to allow easier reuse of code for resume/gpu reset.
v2: Removed function ptr wrapping of do_switch_context (Daniel Vetter)
Left -init_context int intel_lr_context_deferred_alloc (Daniel Vetter)
Remove unnecessary init flag ring type test. (Daniel Vetter)
Improve commit message (Daniel Vetter)
v3: On init/reinit, set the hw next sequence number to the sw next sequence
number. This is set to 1 at driver load time. This prevents the seqno
being reset on reinit (Chris Wilson)
Issue: VIZ-4798
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h| 1 -
drivers/gpu/drm/i915/i915_gem.c| 18 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-
drivers/gpu/drm/i915/intel_lrc.c | 147 ++---
drivers/gpu/drm/i915/intel_lrc.h | 4 +-
5 files changed, 86 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7fd519..844ccf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -880,7 +880,6 @@ struct intel_context {
} legacy_hw_ctx;
/* Execlists */
- bool rcs_initialized;
struct {
struct drm_i915_gem_object *state;
struct intel_ringbuffer *ringbuf;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 73293b4..eb7c1f2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4603,14 +4603,8 @@ int i915_gem_init_rings(struct drm_device *dev)
goto cleanup_vebox_ring;
}
- ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
- if (ret)
- goto cleanup_bsd2_ring;
-
return 0;
-cleanup_bsd2_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[VCS2]);
cleanup_vebox_ring:
intel_cleanup_ring_buffer(dev_priv-ring[VECS]);
cleanup_blt_ring:
@@ -4629,6 +4623,7 @@ i915_gem_init_hw(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_engine_cs *ring;
int ret, i, j;
+ struct drm_i915_gem_request *req;
if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
return -EIO;
@@ -4680,9 +4675,12 @@ i915_gem_init_hw(struct drm_device *dev)
goto out;
}
+ ret = i915_gem_set_seqno(dev, dev_priv-next_seqno);
+ if (ret)
+ goto out;
The only reason to do this would be to ensure that the contents of the
registers are valid (assuming we take over from ourselves). The right
value to use then is last_seqno.
i915_gem_set_seqno uses the following code:
ret = i915_gem_init_seqno(dev, seqno - 1);
..
dev_priv-next_seqno = seqno;
dev_priv-last_seqno = seqno - 1;
So using last_seqno would rewind the seqno by one...
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 923a3c4..95f1a0d 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -994,6 +994,7 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
{
struct intel_context *ctx = NULL;
struct i915_ctx_hang_stats *hs;
+ int ret;
if (ring-id != RCS ctx_id != DEFAULT_CONTEXT_HANDLE)
return ERR_PTR(-EINVAL);
@@ -1009,7 +1010,7 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
}
if (i915.enable_execlists !ctx-engine[ring-id].state) {
- int ret = intel_lr_context_deferred_create(ctx, ring);
+ ret = intel_lr_context_deferred_alloc(ctx, ring);
if (ret) {
DRM_DEBUG(Could not create LRC %u: %d\n, ctx_id, ret);
return ERR_PTR(ret);
Still modifying this for no reason, and you still haven't realised this
call is redundant (hint there is already a hook in alloc_request).
From last year:
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?id=37fbd370152211688bc5bce3d28d13233cfe7d8b
More recent (i.e a couple of months ago):
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=nightlyid=ba4950a8f489d54ec4898f94dad44f9ec13301d2
-Chris
Re: [Intel-gfx] [PATCH 2/5] drm/i915: add common intel_digital_port_connected function
-Original Message-
From: Nikula, Jani
Sent: Wednesday, August 19, 2015 6:04 PM
To: intel-gfx@lists.freedesktop.org
Cc: R, Durgadoss
Subject: Re: [PATCH 2/5] drm/i915: add common intel_digital_port_connected
function
On Wed, 19 Aug 2015, Jani Nikula jani.nik...@intel.com wrote:
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 53
++---
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 4aa3d664765b..d48af8b0c84e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4473,15 +4473,8 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-/*
- * ibx_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
- *
- * Returns true if @port is connected, false otherwise.
- */
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static int ibx_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
{
u32 bit;
@@ -4497,7 +4490,7 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG;
break;
default:
-return true;
+return 1;
}
} else {
switch (port-port) {
@@ -4511,20 +4504,19 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
-return true;
+return 1;
BTW a follow-up could look into making the ibx/cpt default cases return
-EINVAL like the g4x/vlv/bxt cases do.
But the default case for ibx/cpt currently return 1 .. meaning connected
as default result.. In this case, by returning -EINVAL,
won't we break existing users ?
or,
Can we add a WARN_ON()/MISSING_CASE() and then return -EINVAL ?
Thanks,
Durga
BR,
Jani.
}
}
-return I915_READ(SDEISR) bit;
+return I915_READ(SDEISR) bit ? 1 : 0;
}
-static int g4x_digital_port_connected(struct drm_device *dev,
- struct intel_digital_port
*intel_dig_port)
+static int g4x_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port)
{
-struct drm_i915_private *dev_priv = dev-dev_private;
uint32_t bit;
-if (IS_VALLEYVIEW(dev)) {
+if (IS_VALLEYVIEW(dev_priv)) {
switch (intel_dig_port-port) {
case PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
@@ -4559,6 +4551,22 @@ static int g4x_digital_port_connected(struct
drm_device *dev,
return 1;
}
+/*
+ * intel_digital_port_connected - is the specified port connected?
+ * @dev_priv: i915 private structure
+ * @port: the port to test
+ *
+ * Returns a negative error code on errors, 1 for connected, 0 for
disconnected.
+ */
+static int intel_digital_port_connected(struct drm_i915_private *dev_priv,
+struct intel_digital_port *port)
+{
+if (HAS_PCH_SPLIT(dev_priv))
+return ibx_digital_port_connected(dev_priv, port);
+else
+return g4x_digital_port_connected(dev_priv, port);
+}
+
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
@@ -4566,7 +4574,7 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
+if (intel_digital_port_connected(dev_priv, intel_dig_port) != 1)
return connector_status_disconnected;
return intel_dp_detect_dpcd(intel_dp);
@@ -4589,7 +4597,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
return status;
}
-ret = g4x_digital_port_connected(dev, intel_dig_port);
+ret = intel_digital_port_connected(dev-dev_private, intel_dig_port);
if (ret == -EINVAL)
return connector_status_unknown;
else if (ret == 0)
@@ -5055,13 +5063,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool
long_hpd)
/* indicate that we need to restart link training */
intel_dp-train_set_valid = false;
-if (HAS_PCH_SPLIT(dev)) {
-if (!ibx_digital_port_connected(dev_priv,
intel_dig_port))
-
Re: [Intel-gfx] [PATCH 2/5] drm/i915: add common intel_digital_port_connected function
On Wed, 19 Aug 2015, R, Durgadoss durgados...@intel.com wrote:
-Original Message-
From: Nikula, Jani
Sent: Wednesday, August 19, 2015 6:04 PM
To: intel-gfx@lists.freedesktop.org
Cc: R, Durgadoss
Subject: Re: [PATCH 2/5] drm/i915: add common intel_digital_port_connected
function
On Wed, 19 Aug 2015, Jani Nikula jani.nik...@intel.com wrote:
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 53
++---
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 4aa3d664765b..d48af8b0c84e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4473,15 +4473,8 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-/*
- * ibx_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
- *
- * Returns true if @port is connected, false otherwise.
- */
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static int ibx_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
{
u32 bit;
@@ -4497,7 +4490,7 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG;
break;
default:
- return true;
+ return 1;
}
} else {
switch (port-port) {
@@ -4511,20 +4504,19 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
- return true;
+ return 1;
BTW a follow-up could look into making the ibx/cpt default cases return
-EINVAL like the g4x/vlv/bxt cases do.
But the default case for ibx/cpt currently return 1 .. meaning connected
as default result.. In this case, by returning -EINVAL,
won't we break existing users ?
By looking into I really meant figuring out why pch split platforms
are different, and what, if anything, would break. ;)
Thanks for the review.
BR,
Jani.
or,
Can we add a WARN_ON()/MISSING_CASE() and then return -EINVAL ?
Thanks,
Durga
BR,
Jani.
}
}
- return I915_READ(SDEISR) bit;
+ return I915_READ(SDEISR) bit ? 1 : 0;
}
-static int g4x_digital_port_connected(struct drm_device *dev,
- struct intel_digital_port
*intel_dig_port)
+static int g4x_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
uint32_t bit;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv)) {
switch (intel_dig_port-port) {
case PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
@@ -4559,6 +4551,22 @@ static int g4x_digital_port_connected(struct
drm_device *dev,
return 1;
}
+/*
+ * intel_digital_port_connected - is the specified port connected?
+ * @dev_priv: i915 private structure
+ * @port: the port to test
+ *
+ * Returns a negative error code on errors, 1 for connected, 0 for
disconnected.
+ */
+static int intel_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
+{
+ if (HAS_PCH_SPLIT(dev_priv))
+ return ibx_digital_port_connected(dev_priv, port);
+ else
+ return g4x_digital_port_connected(dev_priv, port);
+}
+
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
@@ -4566,7 +4574,7 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
+ if (intel_digital_port_connected(dev_priv, intel_dig_port) != 1)
return connector_status_disconnected;
return intel_dp_detect_dpcd(intel_dp);
@@ -4589,7 +4597,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
return status;
}
- ret = g4x_digital_port_connected(dev, intel_dig_port);
+ ret = intel_digital_port_connected(dev-dev_private, intel_dig_port);
if (ret == -EINVAL)
return connector_status_unknown;
else if (ret == 0)
@@ -5055,13 +5063,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool
long_hpd)
/* indicate that we need to restart link training */
[Intel-gfx] [PATCH 12/11] drm/i915: Reinitialize HPD after runtime D3
From: Ville Syrjälä ville.syrj...@linux.intel.com Runtime suspends disabled all interrupts, so in order to get them back fully we need to also do the HPD irq setup on runtime resume. Except on VLV/CHV where the display interrupt initialization is part of the display power well powerup. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 1d88745..4bbd3b7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1549,6 +1549,15 @@ static int intel_runtime_resume(struct device *device) gen6_update_ring_freq(dev); intel_runtime_pm_enable_interrupts(dev_priv); + + /* +* On VLV/CHV display interrupts are part of the display +* power well, so hpd is reinitialized from there. For +* everyone else do it here. +*/ + if (!IS_VALLEYVIEW(dev_priv)) + intel_hpd_init(dev_priv); + intel_enable_gt_powersave(dev); if (ret) -- 2.4.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: add common intel_digital_port_connected function
On Wed, Aug 19, 2015 at 05:50:52PM +, R, Durgadoss wrote:
-Original Message-
From: Nikula, Jani
Sent: Wednesday, August 19, 2015 6:04 PM
To: intel-gfx@lists.freedesktop.org
Cc: R, Durgadoss
Subject: Re: [PATCH 2/5] drm/i915: add common intel_digital_port_connected
function
On Wed, 19 Aug 2015, Jani Nikula jani.nik...@intel.com wrote:
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 53
++---
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 4aa3d664765b..d48af8b0c84e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4473,15 +4473,8 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-/*
- * ibx_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
- *
- * Returns true if @port is connected, false otherwise.
- */
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static int ibx_digital_port_connected(struct drm_i915_private *dev_priv,
+struct intel_digital_port *port)
{
u32 bit;
@@ -4497,7 +4490,7 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG;
break;
default:
- return true;
+ return 1;
}
} else {
switch (port-port) {
@@ -4511,20 +4504,19 @@ static bool ibx_digital_port_connected(struct
drm_i915_private *dev_priv,
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
- return true;
+ return 1;
BTW a follow-up could look into making the ibx/cpt default cases return
-EINVAL like the g4x/vlv/bxt cases do.
But the default case for ibx/cpt currently return 1 .. meaning connected
as default result.. In this case, by returning -EINVAL,
won't we break existing users ?
or,
Can we add a WARN_ON()/MISSING_CASE() and then return -EINVAL ?
Can we ever hit the default case except due to bugs somewhere else?
If not, then I suggest we just ignore it and make the thing return
bool.
Thanks,
Durga
BR,
Jani.
}
}
- return I915_READ(SDEISR) bit;
+ return I915_READ(SDEISR) bit ? 1 : 0;
}
-static int g4x_digital_port_connected(struct drm_device *dev,
- struct intel_digital_port
*intel_dig_port)
+static int g4x_digital_port_connected(struct drm_i915_private *dev_priv,
+struct intel_digital_port *intel_dig_port)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
uint32_t bit;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv)) {
switch (intel_dig_port-port) {
case PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
@@ -4559,6 +4551,22 @@ static int g4x_digital_port_connected(struct
drm_device *dev,
return 1;
}
+/*
+ * intel_digital_port_connected - is the specified port connected?
+ * @dev_priv: i915 private structure
+ * @port: the port to test
+ *
+ * Returns a negative error code on errors, 1 for connected, 0 for
disconnected.
+ */
+static int intel_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
+{
+ if (HAS_PCH_SPLIT(dev_priv))
+ return ibx_digital_port_connected(dev_priv, port);
+ else
+ return g4x_digital_port_connected(dev_priv, port);
+}
+
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
@@ -4566,7 +4574,7 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
+ if (intel_digital_port_connected(dev_priv, intel_dig_port) != 1)
return connector_status_disconnected;
return intel_dp_detect_dpcd(intel_dp);
@@ -4589,7 +4597,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
return status;
}
- ret = g4x_digital_port_connected(dev, intel_dig_port);
+ ret = intel_digital_port_connected(dev-dev_private, intel_dig_port);
if (ret == -EINVAL)
return connector_status_unknown;
else if (ret == 0)
@@ -5055,13 +5063,8 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool
long_hpd)
/*
Re: [Intel-gfx] [PATCH 02/11] drm/i915; Extract intel_hpd_enabled_irqs()
On Mon, Aug 17, 2015 at 05:06:17PM -0300, Paulo Zanoni wrote:
2015-08-12 12:44 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Eliminate a bunch of duplicated code that calculates the currently
enabled HPD interrupt bits.
Nice one! I see this one also depends on a patch that's not merged
yet, so I'm not sure if I should wait for it to be merged before
continuing the review, or if you plan to send a version rebased just
on -nightly.
I rebased it on top of nightly before I sent it. I guess some patches
got dropped from nightly.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 43
-
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c
index 8485bea..de0edbd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3002,27 +3002,34 @@ static void cherryview_irq_preinstall(struct
drm_device *dev)
vlv_display_irq_reset(dev_priv);
}
+static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
+ const u32 hpd[HPD_NUM_PINS])
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_encoder *encoder;
+ u32 enabled_irqs = 0;
+
+ for_each_intel_encoder(dev, encoder)
+ if (dev_priv-hotplug.stats[encoder-hpd_pin].state ==
HPD_ENABLED)
+ enabled_irqs |= hpd[encoder-hpd_pin];
+
+ return enabled_irqs;
+}
+
static void ibx_hpd_irq_setup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_encoder *intel_encoder;
- u32 hotplug_irqs, hotplug, enabled_irqs = 0;
+ u32 hotplug_irqs, hotplug, enabled_irqs;
if (HAS_PCH_IBX(dev)) {
hotplug_irqs = SDE_HOTPLUG_MASK;
- for_each_intel_encoder(dev, intel_encoder)
- if
(dev_priv-hotplug.stats[intel_encoder-hpd_pin].state == HPD_ENABLED)
- enabled_irqs |=
hpd_ibx[intel_encoder-hpd_pin];
+ enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
} else if (HAS_PCH_SPT(dev)) {
hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
- for_each_intel_encoder(dev, intel_encoder)
- if
(dev_priv-hotplug.stats[intel_encoder-hpd_pin].state == HPD_ENABLED)
- enabled_irqs |=
hpd_spt[intel_encoder-hpd_pin];
+ enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
} else {
hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
- for_each_intel_encoder(dev, intel_encoder)
- if
(dev_priv-hotplug.stats[intel_encoder-hpd_pin].state == HPD_ENABLED)
- enabled_irqs |=
hpd_cpt[intel_encoder-hpd_pin];
+ enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
}
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3051,15 +3058,10 @@ static void ibx_hpd_irq_setup(struct drm_device
*dev)
static void bxt_hpd_irq_setup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_encoder *intel_encoder;
- u32 hotplug_port = 0;
+ u32 hotplug_port;
u32 hotplug_ctrl;
- for_each_intel_encoder(dev, intel_encoder) {
- if (dev_priv-hotplug.stats[intel_encoder-hpd_pin].state
- == HPD_ENABLED)
- hotplug_port |= hpd_bxt[intel_encoder-hpd_pin];
- }
+ hotplug_port = intel_hpd_enabled_irqs(dev, hpd_bxt);
hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) ~BXT_HOTPLUG_CTL_MASK;
@@ -3935,7 +3937,6 @@ static int i965_irq_postinstall(struct drm_device
*dev)
static void i915_hpd_irq_setup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_encoder *intel_encoder;
u32 hotplug_en;
assert_spin_locked(dev_priv-irq_lock);
@@ -3944,9 +3945,7 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
hotplug_en = ~HOTPLUG_INT_EN_MASK;
/* Note HDMI and DP share hotplug bits */
/* enable bits are the same for all generations */
- for_each_intel_encoder(dev, intel_encoder)
- if (dev_priv-hotplug.stats[intel_encoder-hpd_pin].state
== HPD_ENABLED)
- hotplug_en |= hpd_mask_i915[intel_encoder-hpd_pin];
+ hotplug_en |= intel_hpd_enabled_irqs(dev, hpd_mask_i915);
/* Programming the CRT detection parameters tends
to generate a spurious hotplug event about three
seconds later.
Re: [Intel-gfx] [PATCH 1/5] drm/i915: move ibx_digital_port_connected to intel_dp.c
-Original Message-
From: Nikula, Jani
Sent: Wednesday, August 19, 2015 6:01 PM
To: intel-gfx@lists.freedesktop.org
Cc: R, Durgadoss; Nikula, Jani
Subject: [PATCH 1/5] drm/i915: move ibx_digital_port_connected to intel_dp.c
The function can be made static there. No functional changes.
This clean up series looks good to me.
Reviewed-by: Durgadoss R durgados...@intel.com
Thanks,
Durga
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 45 --
drivers/gpu/drm/i915/intel_dp.c | 61 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 --
3 files changed, 53 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f604ce1c528b..1a0670259cdf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1061,51 +1061,6 @@ static void intel_wait_for_pipe_off(struct intel_crtc
*crtc)
}
}
-/*
- * ibx_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
- *
- * Returns true if @port is connected, false otherwise.
- */
-bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
-{
- u32 bit;
-
- if (HAS_PCH_IBX(dev_priv-dev)) {
- switch (port-port) {
- case PORT_B:
- bit = SDE_PORTB_HOTPLUG;
- break;
- case PORT_C:
- bit = SDE_PORTC_HOTPLUG;
- break;
- case PORT_D:
- bit = SDE_PORTD_HOTPLUG;
- break;
- default:
- return true;
- }
- } else {
- switch (port-port) {
- case PORT_B:
- bit = SDE_PORTB_HOTPLUG_CPT;
- break;
- case PORT_C:
- bit = SDE_PORTC_HOTPLUG_CPT;
- break;
- case PORT_D:
- bit = SDE_PORTD_HOTPLUG_CPT;
- break;
- default:
- return true;
- }
- }
-
- return I915_READ(SDEISR) bit;
-}
-
static const char *state_string(bool enabled)
{
return enabled ? on : off;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d32ce4841654..4aa3d664765b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4473,17 +4473,49 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-static enum drm_connector_status
-ironlake_dp_detect(struct intel_dp *intel_dp)
+/*
+ * ibx_digital_port_connected - is the specified port connected?
+ * @dev_priv: i915 private structure
+ * @port: the port to test
+ *
+ * Returns true if @port is connected, false otherwise.
+ */
+static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ u32 bit;
- if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
- return connector_status_disconnected;
+ if (HAS_PCH_IBX(dev_priv-dev)) {
+ switch (port-port) {
+ case PORT_B:
+ bit = SDE_PORTB_HOTPLUG;
+ break;
+ case PORT_C:
+ bit = SDE_PORTC_HOTPLUG;
+ break;
+ case PORT_D:
+ bit = SDE_PORTD_HOTPLUG;
+ break;
+ default:
+ return true;
+ }
+ } else {
+ switch (port-port) {
+ case PORT_B:
+ bit = SDE_PORTB_HOTPLUG_CPT;
+ break;
+ case PORT_C:
+ bit = SDE_PORTC_HOTPLUG_CPT;
+ break;
+ case PORT_D:
+ bit = SDE_PORTD_HOTPLUG_CPT;
+ break;
+ default:
+ return true;
+ }
+ }
- return intel_dp_detect_dpcd(intel_dp);
+ return I915_READ(SDEISR) bit;
}
static int g4x_digital_port_connected(struct drm_device *dev,
@@ -4528,6 +4560,19 @@ static int g4x_digital_port_connected(struct drm_device
*dev,
}
static enum drm_connector_status
+ironlake_dp_detect(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+
+ if (!ibx_digital_port_connected(dev_priv,
Re: [Intel-gfx] [PATCH 00/11] drm/i915: Port A HPD and other HPD cleanups
On Wed, Aug 12, 2015 at 06:44:09PM +0300, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com I've had a bunch of this stuff sitting in a branch for quite a while, almost a year by the looks of the git dates :P I also had port E HPD in there but something similar has already landed in the meantime so I just rebased my junk on top. I've only quickly tested the port A HPD on my ILK. Don't have other machines with eDP on port A here. Tested on HSW ULT now too. Appears to work fine, well, after I added the missing hpd reinit on runtime resume. Patch amended to the series. Ville Syrjälä (11): drm/i915: Clean up various HPD defines drm/i915; Extract intel_hpd_enabled_irqs() drm/i915: Factor out ilk_update_display_irq() drm/i915: Add HAS_PCH_LPT_LP() macro drm/i915: Rename BXT PORTA HPD defines drm/i915: Introduce spt_irq_handler() drm/i915: Add port A HPD support for ILK/SNB drm/i915: Add port A HPD support for IVB/HSW drm/i915: LPT:LP needs port A HPD enabled in both north and south drm/i915: Add port A HPD support for BDW drm/i915: Add port A HPD support for SPT drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 367 +++ drivers/gpu/drm/i915/i915_reg.h | 82 drivers/gpu/drm/i915/intel_display.c | 13 +- drivers/gpu/drm/i915/intel_pm.c | 4 +- 5 files changed, 336 insertions(+), 131 deletions(-) -- 2.4.6 -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Also call frontbuffer flip when disabling planes.
I had forgotten I had this patch and lost sometime yesterday debugging and end up on same fix again :/ Daniel, do you need a reviewer on this? could you please take a quickly look? thanks in advance, Rodrigo. On Fri, Jul 24, 2015 at 4:41 PM Rodrigo Vivi rodrigo.v...@intel.com wrote: We also need to call the frontbuffer flip to trigger proper invalidations when disabling planes. Otherwise we will miss screen updates when disabling sprites or cursor. It was caught with kms_psr_sink_crc sprite_plane_onoff and cursor_plane_onoff subtests. This is probably a regression since I can also get this with the manual test case, but with so many changes on atomic modeset I couldn't track exactly when this was introduced. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index af0bcfe..bb124cc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11716,7 +11716,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, intel_crtc-atomic.update_wm_pre = true; } - if (visible) + if (visible || was_visible) intel_crtc-atomic.fb_bits |= to_intel_plane(plane)-frontbuffer_bit; -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/15] drm/i915: Upscale scaler max scale for NV12.
This patch updates max supported scaler limits for NV12.
v2:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 13 +
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 411b211..b1d9edf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13421,7 +13421,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format)
{
int max_scale;
struct drm_device *dev;
@@ -13441,11 +13443,13 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct
intel_crtc_state *crtc_state
/*
* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
+*close to 2 or 3 (NV12: 2, other formats: 3) but not equal,
+* -1 is for that purpose
*or
*cdclk/crtc_clock
*/
- max_scale = min((1 16) * 3 - 1, (1 8) * ((cdclk 8) /
crtc_clock));
+ max_scale = min((1 16) * (pixel_format == DRM_FORMAT_NV12 ? 2 : 3) -
1,
+ (1 8) * ((cdclk 8) / crtc_clock));
return max_scale;
}
@@ -13465,7 +13469,8 @@ intel_check_primary_plane(struct drm_plane *plane,
if (INTEL_INFO(plane-dev)-gen = 9
state-ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+ max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state,
+ fb ? fb-pixel_format : 0);
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18632a4..d50b8cb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1140,7 +1140,8 @@ void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
*crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 8b73bb8..66d60ae 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -780,7 +780,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (state-ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
+ max_scale = skl_max_scale(intel_crtc, crtc_state,
fb-pixel_format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
--
1.7.9.5
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/15] drm/i915: Add NV12 to sprite plane programming.
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 4e8c020..a1384a7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,6 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -234,24 +236,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
plane_size = (src_w 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
+
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
plane_size = (src_h 16) | src_w;
x_offset = x;
y_offset = y;
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+ I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset16 |
aux_x_offset);
/* program plane scaler */
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
- DRM_DEBUG_KMS(plane = %d PS_PLANE_SEL(plane) = 0x%x\n, plane,
- PS_PLANE_SEL(plane));
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
crtc_state-scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -262,6 +288,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, plane), 0);
} else {
+ WARN_ON(fb-pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y 16) | crtc_x);
}
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/15] drm/i915: Add NV12 to primary plane programming.
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)
v3:
-Allow 90/270 for NV12 as its remapping is now supported (me)
v4:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4df4d77..329651e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,8 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -3094,6 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane-state);
@@ -3150,11 +3154,34 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
@@ -3162,11 +3189,14 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset 16 |
aux_x_offset);
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
WARN_ON(!dst_w || !dst_h);
+
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
crtc_state-scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3175,6 +3205,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w 16) |
dst_h);
I915_WRITE(PLANE_POS(pipe, 0), 0);
} else {
+ WARN_ON(fb-pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, 0), (dst_y 16) | dst_x);
}
@@ -11626,6 +11657,12 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
bool turn_off, turn_on, visible, was_visible;
struct drm_framebuffer *fb = plane_state-fb;
+ /* Adjust (macro)pixel boundary
[Intel-gfx] [PATCH 05/15] drm/i915: Stage scaler request for NV12 as src format
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3ee1c17..411b211 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4341,10 +4341,27 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
}
}
+static int skl_need_scaling(int src_w, int dst_w, int src_h, int dst_h,
+ int rotation, uint32_t pixel_format)
+{
+ /* scaling is required when src dst sizes doesn't match or format is
NV12 */
+ if (src_w != dst_w || src_h != dst_h)
+ return 1;
+
+ if (intel_rotation_90_or_270(rotation)
+ (src_h != dst_w || src_w != dst_h))
+ return 1;
+
+ if (pixel_format == DRM_FORMAT_NV12)
+ return 1;
+
+ return 0;
+}
+
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned scaler_user, int *scaler_id, unsigned int rotation,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h, uint32_t
pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
crtc_state-scaler_state;
@@ -4352,9 +4369,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
to_intel_crtc(crtc_state-base.crtc);
int need_scaling;
- need_scaling = intel_rotation_90_or_270(rotation) ?
- (src_h != dst_w || src_w != dst_h):
- (src_w != dst_w || src_h != dst_h);
+ need_scaling = skl_need_scaling(src_w, dst_w, src_h, dst_h, rotation,
+ pixel_format);
/*
* if plane is being disabled or scaler is no more required or force
detach
@@ -4423,7 +4439,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state-base.active, SKL_CRTC_INDEX,
state-scaler_state.scaler_id, DRM_ROTATE_0,
state-pipe_src_w, state-pipe_src_h,
- adjusted_mode-hdisplay, adjusted_mode-vdisplay);
+ adjusted_mode-hdisplay, adjusted_mode-vdisplay, 0);
}
/**
@@ -4459,7 +4475,8 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
drm_rect_width(plane_state-src) 16,
drm_rect_height(plane_state-src) 16,
drm_rect_width(plane_state-dst),
- drm_rect_height(plane_state-dst));
+ drm_rect_height(plane_state-dst),
+ fb ? fb-pixel_format : 0);
if (ret || plane_state-scaler_id 0)
return ret;
@@ -4484,6 +4501,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS([PLANE:%d] FB:%d unsupported scaling format
0x%x\n,
--
1.7.9.5
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[Intel-gfx] [PATCH 00/15] drm/i915: Adding NV12 for skylake display
This patch series is adding initial NV12 support for Skylake display after rebasing on latest drm-intel-nightly. Earlier I had two patch series one for 0/180 and another for 90/270. Some of the patches were already merged. This is combined series to support 0/90/180/270 and removing the ones that are already merged. Feature is tested with igt/kms_nv12 testcases. Feature is unit tested for linear/X/Y formats in 0, 90, 180, 270 orientations with combinations of 1 or 2 planes enabled along with scaling. Also negatively tested for enabling NV12 on unsupported plane. The last patch in this series depends on Tvrtko's GEM remapping for NV12 format patch series. First two patches fixing couple things in dbuf logic to allocate correct min number of dbuf blocks and use correct source width and height in 90/270 rotation cases. Chandra Konduru (15): drm/i915: Allocate min dbuf blocks per bspec drm/i915: In DBUF/WM calcs for 90/270, swap w h drm/i915: Add register definitions for NV12 support drm/i915: Set scaler mode for NV12 drm/i915: Stage scaler request for NV12 as src format drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12. drm/i915: Add NV12 as supported format for primary plane drm/i915: Add NV12 as supported format for sprite plane drm/i915: Add NV12 support to intel_framebuffer_init drm/i915: Add NV12 to primary plane programming. drm/i915: Add NV12 to sprite plane programming. drm/i915: Set initial phase trip for NV12 scaler drm/i915: skl nv12 workarounds drm/i915: Add 90/270 rotation for NV12 format. drivers/gpu/drm/i915/i915_reg.h | 47 + drivers/gpu/drm/i915/intel_atomic.c |5 +- drivers/gpu/drm/i915/intel_csr.c |2 +- drivers/gpu/drm/i915/intel_display.c | 178 +++--- drivers/gpu/drm/i915/intel_drv.h |5 +- drivers/gpu/drm/i915/intel_pm.c | 71 -- drivers/gpu/drm/i915/intel_sprite.c | 121 +++ 7 files changed, 387 insertions(+), 42 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/15] drm/i915: Add register definitions for NV12 support
This patch adds register definitions for skylake
display NV12 support.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fa0554..c4d732f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5498,6 +5498,7 @@ enum skl_disp_power_wells {
#define PS_SCALER_MODE_MASK (3 28)
#define PS_SCALER_MODE_DYN (0 28)
#define PS_SCALER_MODE_HQ (1 28)
+#define PS_SCALER_MODE_NV12 (2 28)
#define PS_PLANE_SEL_MASK (7 25)
#define PS_PLANE_SEL(plane) ((plane + 1) 25)
#define PS_FILTER_MASK (3 23)
@@ -5601,6 +5602,32 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
+
+/*
+ * Skylake NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)\
+ _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
--
1.7.9.5
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[Intel-gfx] [PATCH 04/15] drm/i915: Set scaler mode for NV12
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_atomic.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 9336e80..fd3972c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -247,7 +247,10 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
}
/* set scaler mode */
- if (num_scalers_need == 1 intel_crtc-pipe != PIPE_C) {
+ if (plane_state plane_state-base.fb
+ plane_state-base.fb-pixel_format == DRM_FORMAT_NV12) {
+ scaler_state-scalers[*scaler_id].mode =
PS_SCALER_MODE_NV12;
+ } else if (num_scalers_need == 1 intel_crtc-pipe != PIPE_C)
{
/*
* when only 1 scaler is in use on either pipe A or B,
* scaler 0 operates in high quality (HQ) mode.
--
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[Intel-gfx] [PATCH 09/15] drm/i915: Add NV12 as supported format for sprite plane
This patch adds NV12 to list of supported formats for
sprite plane.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 66d60ae..4e8c020 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1041,6 +1041,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static uint32_t skl_plane_formats_with_nv12[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
@@ -1112,8 +1125,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane-disable_plane = skl_disable_plane;
state-scaler_id = -1;
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((pipe == PIPE_A || pipe == PIPE_B) (plane == 0)) {
+ plane_formats = skl_plane_formats_with_nv12;
+ num_plane_formats =
ARRAY_SIZE(skl_plane_formats_with_nv12);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats) - 1;
+ }
+
break;
default:
kfree(intel_plane);
--
1.7.9.5
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[Intel-gfx] [PATCH 01/15] drm/i915: Allocate min dbuf blocks per bspec
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22..da3046f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2959,6 +2959,41 @@ skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane !p-y_bytes_per_pixel)
+ return 0;
+
+
+ if (p-tiling == I915_FORMAT_MOD_Y_TILED ||
+ p-tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p-y_bytes_per_pixel : p-bytes_per_pixel;
+
+ switch (bytes_per_pixel) {
+ case 1:
+ min_scanlines = 32;
+ break;
+ case 2:
+ min_scanlines = 16;
+ break;
+ case 8:
+ WARN(1, Unsupported pixel depth for rotation);
+ }
+ min_alloc = DIV_ROUND_UP((4 * p-horiz_pixels/(y_plane ? 1 : 2)
*
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2999,9 +3034,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p-enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, 0);/*
uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p-y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, 1); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
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[Intel-gfx] [PATCH 08/15] drm/i915: Add NV12 as supported format for primary plane
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b1d9edf..e4a6a91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -74,6 +74,19 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
+/* Primary plane formats for gen = 9 with NV12 */
+static const uint32_t skl_primary_formats_with_nv12[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13606,8 +13619,13 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
primary-plane = !pipe;
if (INTEL_INFO(dev)-gen = 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ intel_primary_formats = skl_primary_formats_with_nv12;
+ num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
} else if (INTEL_INFO(dev)-gen = 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
--
1.7.9.5
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[Intel-gfx] [PATCH 10/15] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e4a6a91..4df4d77 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14343,6 +14343,34 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)-gen 9) {
+ DRM_DEBUG(unsupported pixel format: %s\n,
+ drm_get_format_name(mode_cmd-pixel_format));
+ return -EINVAL;
+ }
+ if (!mode_cmd-offsets[1]) {
+ DRM_DEBUG(uv start offset not set\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-pitches[0] != mode_cmd-pitches[1] ||
+ mode_cmd-handles[0] != mode_cmd-handles[1]) {
+ DRM_DEBUG(y and uv subplanes have different
parameters\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Yf_TILED
+ (mode_cmd-offsets[1] 0xFFF)) {
+ DRM_DEBUG(tile-Yf uv offset 0x%x isn't starting on new
tile-row\n,
+ mode_cmd-offsets[1]);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Y_TILED
+ ((mode_cmd-offsets[1] / mode_cmd-pitches[1]) % 4)) {
+ DRM_DEBUG(tile-Y uv offset 0x%x isn't 4-line
aligned\n,
+ mode_cmd-offsets[1]);
+ return -EINVAL;
+ }
+ break;
default:
DRM_DEBUG(unsupported pixel format: %s\n,
drm_get_format_name(mode_cmd-pixel_format));
--
1.7.9.5
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[Intel-gfx] [PATCH 06/15] drm/i915: Update format_is_yuv() to include NV12
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f44941b..18632a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1394,6 +1394,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev,
void *data,
void intel_pipe_update_start(struct intel_crtc *crtc,
uint32_t *start_vbl_count);
void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
+bool intel_format_is_yuv(uint32_t format);
/* intel_tv.c */
void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c13c529..8b73bb8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -39,14 +39,15 @@
#include drm/i915_drm.h
#include i915_drv.h
-static bool
-format_is_yuv(uint32_t format)
+bool
+intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -293,7 +294,7 @@ chv_update_csc(struct intel_plane *intel_plane, uint32_t
format)
int plane = intel_plane-plane;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -857,7 +858,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
src_y = src-y1 16;
src_h = drm_rect_height(src) 16;
- if (format_is_yuv(fb-pixel_format)) {
+ if (intel_format_is_yuv(fb-pixel_format)) {
src_x = ~1;
src_w = ~1;
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/15] drm/i915: Set initial phase trip for NV12 scaler
This patch sets default initial phase and trip to scale NV12 content. In future, if needed these can be set via properties or other means depending on incoming stream request. Until then defaults are fine. Signed-off-by: Chandra Konduru chandra.kond...@intel.com --- drivers/gpu/drm/i915/intel_display.c |7 +++ drivers/gpu/drm/i915/intel_sprite.c |7 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 329651e..419660d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3098,6 +3098,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, int scaler_id = -1; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_state = to_intel_plane_state(plane-state); @@ -3181,6 +3182,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb-modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset 16 | x_offset; @@ -3209,6 +3213,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, 0), (dst_y 16) | dst_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index a1384a7..0ea9273 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -190,6 +190,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int scaler_id; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -264,6 +265,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb-modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset 16 | x_offset; @@ -292,6 +296,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, plane), (crtc_y 16) | crtc_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane)); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 workarounds
Adding driver workarounds for nv12.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 20
drivers/gpu/drm/i915/intel_csr.c |2 +-
drivers/gpu/drm/i915/intel_display.c | 31 +++
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_sprite.c |7 +++
5 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4d732f..3192837 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5354,6 +5354,26 @@ enum skl_disp_power_wells {
#define PLANE_NV12_BUF_CFG(pipe, plane)\
_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+/*
+ * Skylake Chicken registers
+ */
+#define _CHICKEN_PIPESL_A 0x420B0
+#define _CHICKEN_PIPESL_B 0x420B4
+#define _CHICKEN_PIPESL_C 0x420B8
+#define DISABLE_STREAMER_FIX (1 22)
+#define CHICKEN_PIPESL(pipe) _PIPE(pipe, _CHICKEN_PIPESL_A, _CHICKEN_PIPESL_B)
+
+#define CHICKEN_DCPR_1 0x46430
+#define IDLE_WAKEMEM_MASK (1 13)
+
+#define CLKGATE_DIS_PSL_A0x46520
+#define CLKGATE_DIS_PSL_B0x46524
+#define CLKGATE_DIS_PSL_C0x46528
+#define DUPS1_GATING_DIS (1 15)
+#define DUPS2_GATING_DIS (1 19)
+#define DUPS3_GATING_DIS (1 23)
+#define CLKGATE_DIS_PSL(pipe) _PIPE(pipe, CLKGATE_DIS_PSL_A,
CLKGATE_DIS_PSL_B)
+
/* SKL new cursor registers */
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae03..559a7f5 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -181,7 +181,7 @@ static const struct stepping_info skl_stepping_info[] = {
{'G', '0'}, {'H', '0'}, {'I', '0'}
};
-static char intel_get_stepping(struct drm_device *dev)
+char intel_get_stepping(struct drm_device *dev)
{
if (IS_SKYLAKE(dev) (dev-pdev-revision
ARRAY_SIZE(skl_stepping_info)))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 419660d..2158b8f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3196,6 +3196,16 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset 16 |
aux_x_offset);
+ DRM_DEBUG_KMS(KCM: is_skl = %d is_bxt = %d\n,
+ IS_SKYLAKE(dev), IS_BROXTON(dev));
+
+ if (((IS_SKYLAKE(dev) intel_get_stepping(dev) == 'C') ||
+ (IS_BROXTON(dev) intel_get_stepping(dev) == 'A'))
+ fb-pixel_format == DRM_FORMAT_NV12) {
+ I915_WRITE(CHICKEN_PIPESL(pipe),
+ I915_READ(CHICKEN_PIPESL(pipe)) |
DISABLE_STREAMER_FIX);
+ }
+
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
@@ -5004,6 +5014,21 @@ static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc)
return HAS_IPS(crtc-base.dev) crtc-pipe == PIPE_A;
}
+
+static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
+ int pipe, int enable)
+{
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ if (enable)
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+ else
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe)
+ ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS)));
+ }
+}
+
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -5094,6 +5119,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, hsw_workaround_pipe);
intel_wait_for_vblank(dev, hsw_workaround_pipe);
}
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, pipe, 1);
}
static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -5211,6 +5239,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
intel_crtc-active = false;
intel_update_watermarks(crtc);
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, intel_crtc-pipe, 0);
}
static void i9xx_pfit_enable(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d50b8cb..63750d5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1158,6 +1158,7 @@ void intel_csr_load_status_set(struct drm_i915_private
*dev_priv,
enum csr_state state);
void
[Intel-gfx] [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format.
Adding NV12 90/270 rotation support for primary and sprite planes.
v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)
v3:
-Rebased (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28 +++--
drivers/gpu/drm/i915/intel_sprite.c | 56 ++
2 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2158b8f..19d0f8b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3096,7 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
@@ -3155,12 +3156,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist =
intel_plane_obj_offset(to_intel_plane(plane), obj, 1) -
+ surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
@@ -11697,8 +11702,13 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
/* Adjust (macro)pixel boundary */
if (fb intel_format_is_yuv(fb-pixel_format)) {
- to_intel_plane_state(plane_state)-src.x1 = ~0x1;
- to_intel_plane_state(plane_state)-src.x2 = ~0x1;
+ if (intel_rotation_90_or_270(plane_state-rotation)) {
+ to_intel_plane_state(plane_state)-src.y1 = ~0x1;
+ to_intel_plane_state(plane_state)-src.y2 = ~0x1;
+ } else {
+ to_intel_plane_state(plane_state)-src.x1 = ~0x1;
+ to_intel_plane_state(plane_state)-src.x2 = ~0x1;
+ }
}
if (crtc_state INTEL_INFO(dev)-gen = 9
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 9d1c5b9..3522cb0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,7 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
@@ -238,12 +239,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist = intel_plane_obj_offset(intel_plane, obj, 1)
- surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride =
[Intel-gfx] [PATCH i-g-t 2/2] Adding kms_nv12 to test display NV12 feature
From: chandra konduru chandra.kond...@intel.com
This patch adds kms_nv12 test case. It covers testing NV12
in linear/tile-X/tile-Y tiling formats in 0/90/180/270
orientations. For each tiling format, it tests several
combinations of planes and its scaling.
v2:
-Added 90/270 tests (me)
-took out crc test as it isn't adding much value due to chroma upsampling (me)
v3:
-Make --list-subtests option work (Tvrtko)
-Make nv12 unsupported test run properly either as a sub test
or along with all other tests (me)
-Added nv12 fb with invalid params (Daniel)
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_nv12.c | 759 +
3 files changed, 761 insertions(+)
create mode 100644 tests/kms_nv12.c
diff --git a/tests/.gitignore b/tests/.gitignore
index d6d05ff..2de4712 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -155,6 +155,7 @@ kms_setmode
kms_sink_crc_basic
kms_universal_plane
kms_vblank
+kms_nv12
pm_backlight
pm_lpsp
pm_rc6_residency
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index ef69299..a7804fa 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -85,6 +85,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_nv12 \
pm_backlight \
pm_lpsp \
pm_rpm \
diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c
new file mode 100644
index 000..9f90a85
--- /dev/null
+++ b/tests/kms_nv12.c
@@ -0,0 +1,759 @@
+/*
+ * Copyright © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include math.h
+#include fcntl.h
+#include sys/stat.h
+
+#include drmtest.h
+#include igt_debugfs.h
+#include igt_kms.h
+#include igt_core.h
+#include intel_chipset.h
+#include ioctl_wrappers.h
+
+IGT_TEST_DESCRIPTION(Test display NV12 support);
+
+uint32_t devid;
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ int num_scalers;
+ int num_planes;
+
+ struct igt_fb fb1;
+ struct igt_fb fb1_nv12;
+ struct igt_fb fb2;
+ struct igt_fb fb2_nv12;
+ struct igt_fb fb3;
+ struct igt_fb fb3_nv12;
+ int fb_id1;
+ int fb_id1_nv12;
+ int fb_id2;
+ int fb_id2_nv12;
+ int fb_id3;
+ int fb_id3_nv12;
+
+ igt_plane_t *plane1;
+ igt_plane_t *plane2;
+ igt_plane_t *plane3;
+
+ uint64_t tiled;
+ int rotation;
+} data_t;
+
+typedef struct {
+ int width;
+ int height;
+} res_t;
+
+#define IMG_FILE 1080p-left.png
+
+static void
+paint_pattern(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+static void
+paint_image(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_image(cr, IMG_FILE, 0, 0, w, h);
+ cairo_destroy(cr);
+}
+
+static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
+ igt_plane_t *plane, drmModeModeInfo *mode, enum
igt_commit_style s)
+{
+ igt_display_t *display = data-display;
+
+ igt_output_set_pipe(output, pipe);
+
+ /* before allocating, free if any older fb */
+ if (data-fb_id1) {
+ igt_remove_fb(data-drm_fd, data-fb1);
+ data-fb_id1 = 0;
+ }
+
+ /* allocate fb for plane 1 */
+ data-fb_id1 = igt_create_fb(data-drm_fd,
+ mode-hdisplay, mode-vdisplay,
+ DRM_FORMAT_XRGB,
+ data-tiled, /* tiled */
+ data-fb1);
+ igt_assert(data-fb_id1);
+
+ paint_pattern(data, data-fb1,
[Intel-gfx] [PATCH i-g-t 0/2] patches for testing nv12
From: chandra konduru chandra.kond...@intel.com This patch series made some necessary igt framework changes to support nv12 format. And adds kms_nv12 to test nv12 format. It is having several initial test combinations but any additional tests can be added as needed. chandra konduru (2): Prep work for adding NV12 testcase Adding kms_nv12 to test display NV12 feature lib/igt_fb.c| 316 +++- lib/igt_fb.h| 9 +- lib/intel_batchbuffer.c | 16 +- lib/intel_batchbuffer.h | 3 +- lib/intel_reg.h | 1 + lib/ioctl_wrappers.c| 10 +- lib/ioctl_wrappers.h| 2 +- tests/.gitignore| 1 + tests/Makefile.sources | 1 + tests/kms_nv12.c| 759 tests/kms_render.c | 4 +- 11 files changed, 1095 insertions(+), 27 deletions(-) create mode 100644 tests/kms_nv12.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] Prep work for adding NV12 testcase
From: chandra konduru chandra.kond...@intel.com
This patch adds necessary prep work for nv12 testcase:
- updated fb allocation functions to handle NV12 format
- igt helper function to return png image size
- igt helper function to calculate start of uv in a given NV12 buffer
- igt helper function to map buffer for host access
- populates fb-...[4] parameters for NV12
- igt helper function to convert RGB data to NV12
- updated drm_format to bpp to handle NV12
- updated fast copy blit function to deal NV12 subplanes
- made an update to kms_render testcase due to above changes
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
lib/igt_fb.c| 316 +---
lib/igt_fb.h| 9 +-
lib/intel_batchbuffer.c | 16 ++-
lib/intel_batchbuffer.h | 3 +-
lib/intel_reg.h | 1 +
lib/ioctl_wrappers.c| 10 +-
lib/ioctl_wrappers.h| 2 +-
tests/kms_render.c | 4 +-
8 files changed, 334 insertions(+), 27 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 134dbd2..788bb61 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -74,7 +74,7 @@ static struct format_desc_struct {
/* helpers to create nice-looking framebuffers */
-static int create_bo_for_fb(int fd, int width, int height, int bpp,
+static int create_bo_for_fb(int fd, int width, int height, int bpp, int bpp2,
uint64_t tiling, unsigned bo_size,
uint32_t *gem_handle_ret,
unsigned *size_ret,
@@ -99,13 +99,17 @@ static int create_bo_for_fb(int fd, int width, int height,
int bpp,
for (stride = 512; stride v; stride *= 2)
;
- v = stride * height;
+ /* planar formats height is 1.5x */
+ v = stride * (bpp2 ? (height * 3) / 2 : height);
+
for (size = 1024*1024; size v; size *= 2)
;
} else {
/* Scan-out has a 64 byte alignment restriction */
stride = (width * (bpp / 8) + 63) ~63;
- size = stride * height;
+
+ /* planar formats height is 1.5x */
+ size = stride * (bpp2 ? (height * 3) / 2 : height);
}
if (bo_size == 0)
@@ -393,6 +397,75 @@ void igt_paint_image(cairo_t *cr, const char *filename,
}
/**
+ * igt_get_image_size:
+ * @filename: filename of the png image
+ * @width: width of the image
+ * @height: height of the image
+ *
+ * This function returns @width and @height of the png image in @filename,
+ * which is loaded from the package data directory.
+ */
+void
+igt_get_image_size(const char *filename, int *width, int *height)
+{
+ cairo_surface_t *image;
+ FILE* f;
+
+ f = igt_fopen_data(filename);
+
+ image = cairo_image_surface_create_from_png_stream(stdio_read_func, f);
+ igt_assert(cairo_surface_status(image) == CAIRO_STATUS_SUCCESS);
+
+ *width = cairo_image_surface_get_width(image);
+ *height = cairo_image_surface_get_height(image);
+
+ cairo_surface_destroy(image);
+
+ fclose(f);
+}
+
+
+/**
+ * igt_fb_calc_uv:
+ * @fb: pointer to an #igt_fb structure
+ *
+ * This function calculates UV offset in bytes and UV starting line number
+ * for requested NV12 @fb.
+ */
+void
+igt_fb_calc_uv(struct igt_fb *fb)
+{
+ if (fb-drm_format != DRM_FORMAT_NV12)
+ return;
+
+ switch (fb-tiling) {
+ case LOCAL_DRM_FORMAT_MOD_NONE:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_X_TILED:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Y_TILED:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+ /* tile-Yf requires uv to start on a new tile row */
+ if (fb-height % 64)
+ fb-uv_y_start = (fb-height + 63) ~63;
+ else
+ fb-uv_y_start = fb-height;
+ break;
+ default:
+ igt_assert(0);
+ }
+
+ fb-uv_offset = fb-uv_y_start * fb-stride;
+
+ /* assert that fb has enough lines to hold y and uv sub-planes */
+ igt_assert(fb-size / fb-stride = fb-uv_y_start + fb-height / 2);
+}
+
+/**
* igt_create_fb_with_bo_size:
* @fd: open i915 drm file descriptor
* @width: width of the framebuffer in pixel
@@ -418,24 +491,32 @@ igt_create_fb_with_bo_size(int fd, int width, int height,
struct igt_fb *fb, unsigned bo_size)
{
uint32_t fb_id;
- int bpp;
+ int bpp, bpp2;
memset(fb, 0, sizeof(*fb));
- bpp = igt_drm_format_to_bpp(format);
+ bpp = igt_drm_format_to_bpp(format, 0);
+ bpp2 = igt_drm_format_to_bpp(format, 1);
- igt_debug(%s(width=%d, height=%d, format=0x%x [bpp=%d],
tiling=0x%PRIx64,
[Intel-gfx] [PATCH] drm/i915/bxt: Use correct live status register for BXT platform
BXT platform uses live status bits from 0x0 register to
obtain DP status on hotplug. The existing g4x_digital_port_connected()
uses a different register and hence misses DP hotplug events on
BXT platform. This patch fixes it by using the appropriate
register(0x0) and live status bits(3:5).
Signed-off-by: Durgadoss R durgados...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a1dac9c..821d770 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -,6 +,7 @@ static int g4x_digital_port_connected(struct drm_device
*dev,
{
struct drm_i915_private *dev_priv = dev-dev_private;
uint32_t bit;
+ uint32_t reg = IS_BROXTON(dev) ? GEN8_DE_PORT_ISR : PORT_HOTPLUG_STAT;
if (IS_VALLEYVIEW(dev)) {
switch (intel_dig_port-port) {
@@ -4459,6 +4460,20 @@ static int g4x_digital_port_connected(struct drm_device
*dev,
default:
return -EINVAL;
}
+ } else if (IS_BROXTON(dev)) {
+ switch (intel_dig_port-port) {
+ case PORT_A:
+ bit = BXT_DE_PORT_HP_DDIA;
+ break;
+ case PORT_B:
+ bit = BXT_DE_PORT_HP_DDIB;
+ break;
+ case PORT_C:
+ bit = BXT_DE_PORT_HP_DDIC;
+ break;
+ default:
+ return -EINVAL;
+ }
} else {
switch (intel_dig_port-port) {
case PORT_B:
@@ -4475,7 +4490,7 @@ static int g4x_digital_port_connected(struct drm_device
*dev,
}
}
- if ((I915_READ(PORT_HOTPLUG_STAT) bit) == 0)
+ if ((I915_READ(reg) bit) == 0)
return 0;
return 1;
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 3/8] drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters for DSC
On Wednesday 12 August 2015 07:05 PM, Daniel Vetter wrote:
On Wed, Aug 12, 2015 at 03:23:48PM +0530, vikas.korj...@intel.com wrote:
From: vkorjani vikas.korj...@intel.com
This patch adds code to initialize Picture Parameter set (PPS)
data structure for DSC.
DSC is enabled than the bitrate should be calculated using the
formula pixel_clock * bits_per_pixel / lane_count, where
bits_per_pixel can be 8bpp, 10bpp, 12bpp.
value of bits_per_pixel is available in step of 1/16 in
pps date structure.
DPHY parameters are computed based on data rate calculated
as per bits_per_pixel provided in pps data structure.
Signed-off-by: vkorjani vikas.korj...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.h |5 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 11 +++
drivers/gpu/drm/i915/intel_dsi_pll.c | 24
3 files changed, 32 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 24fc550..699f995 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -96,6 +96,11 @@ struct intel_dsi {
u16 panel_on_delay;
u16 panel_off_delay;
u16 panel_pwr_cycle_delay;
+
+ /*DSC Support */
+ u8 dsc_enable;
+ struct vesa_dsc_pps_data pps_data;
+ u8 dsc_bpp;
};
struct intel_dsi_host {
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a5e99ac..f893d37 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -413,6 +413,17 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
*intel_dsi, u16 panel_id)
bits_per_pixel = 18;
else if (intel_dsi-pixel_format == VID_MODE_FORMAT_RGB565)
bits_per_pixel = 16;
+ else if (intel_dsi-pixel_format == VID_MODE_FORMAT_COMPRESSED
+ dev_priv-vbt.dsc_param.dsc_support) {
+ intel_dsi-dsc_enable = true;
+ intel_dsi-dsc_bpp =
+ (intel_dsi-pps_data.bits_per_pixel / 16);
+ bits_per_pixel = intel_dsi-dsc_bpp;
+ intel_dsi-pps_data =
+ dev_priv-vbt.dsc_param.pps_data;
+ /*TODO If PPS not available in VBT compute PPS
+* from capablity parameter set in vbt */
We don't seem to feed back the dsi bits_per_pixel information into our
computation of pipe_config-pipe_bpp. We probably need to fix that to
actually be able to drive the higher bpc modes ...
Wiring this up correctly should probably be a prep patch.
Yes will fix this.
Also do we have to compute bpp differently for dsc? Can't we just store
bits_per_pixel somewhere?
-Daniel
intel_dsi-dsc_bpp stores target bpp after compression.
We can store orginal bpp in intel_dsi-dsi_bpp, some thing similar
is done in this patch
http://lists.freedesktop.org/archives/intel-gfx/2015-May/067627.html
which is still under review.
+ }
intel_dsi-operation_mode = mipi_config-is_cmd_mode;
intel_dsi-video_mode_format = mipi_config-video_transfer_mode;
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index b647f13..38c9433 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -143,10 +143,17 @@ static u32 dsi_rr_formula(const struct drm_display_mode
*mode,
#else
/* Get DSI clock from pixel clock */
-static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
+static u32 dsi_clk_from_pclk(struct intel_encoder *encoder,
+ u32 pclk, int pixel_format, int lane_count)
{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder-base);
u32 dsi_clk_khz;
- u32 bpp = dsi_pixel_format_bpp(pixel_format);
+ u32 bpp;
+
+ if (intel_dsi-dsc_enable)
+ bpp = intel_dsi-dsc_bpp;
+ else
+ bpp = dsi_pixel_format_bpp(pixel_format);
/* DSI data rate = pixel clock * bits per pixel / lane count
pixel clock is converted from KHz to Hz */
@@ -223,8 +230,8 @@ static void vlv_configure_dsi_pll(struct intel_encoder
*encoder)
struct dsi_mnp dsi_mnp;
u32 dsi_clk;
- dsi_clk = dsi_clk_from_pclk(intel_dsi-pclk, intel_dsi-pixel_format,
- intel_dsi-lane_count);
+ dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi-pclk,
+ intel_dsi-pixel_format, intel_dsi-lane_count);
ret = dsi_calc_mnp(dev_priv, dsi_mnp, dsi_clk);
if (ret) {
@@ -410,8 +417,9 @@ u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int
pipe_bpp)
dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
- /* pixel_format and pipe_bpp should agree */
- assert_bpp_mismatch(intel_dsi-pixel_format, pipe_bpp);
+ /* pixel_format and pipe_bpp
Re: [Intel-gfx] [RFC 0/8] *** DSC Inital Design RFC ***
On Wednesday 12 August 2015 07:09 PM, Daniel Vetter wrote: jn Wed, Aug 12, 2015 at 03:23:45PM +0530, vikas.korj...@intel.com wrote: From: vkorjani vikas.korj...@intel.com s RFC is for feature Display Stream Compression (DSC) for BXT, It is a VESA defined standard to compress and decompress image in display streams in a link independent manner. Some of the basic requirements of the standard are to support higher resolution on a given display link with fewer lanes or lower rate. DSC is architected to work in current Intel Display Engine design without modification how current display pipeline works. DSC hardware as per HAS is in b/n port and MIPI DSI controller. so most of the changes are at port level. At begining of frame display can start sending valid pixels to DSC at normal rate, DSC start compressing this image according to pps parameters programmed already to 8bpp, 10bpp, 12bpp. /*This bitstream is temprory stored in output buffer and sent as byte stream to DSI controller as soon as it is valid. */ Where exactly is that bistream stored? In some on-chip buffer which is hidden from us, or do we need to allocate some memory for this? I din't spot anything of the latter form ... -Daniel Yes this is a on-chip buffer. Following are the set of patches as per initial design in HLD, one can refer DSC HLD if more details about the changes is required. Tested these patches on fulsim simulation enviornment. vkorjani (8): drm/915/bxt: Adding DSC VBT parameter and PPS structures drm/i915/bxt: Adding registers to support DSC drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters for DSC drm/i915/bxt: MIPI DSI Register Programming for DSC drm/i915/bxt: Program MIPI_DPI_RESOLUTION for DSC drm/i915/bxt: Enable/Disable DSC and programme PPS. drm: Add support for pps and compression mode command packet drm/i915/bxt: Send PPS packet and compression mode command packet drivers/gpu/drm/drm_mipi_dsi.c | 29 +++ drivers/gpu/drm/i915/i915_drv.h|2 + drivers/gpu/drm/i915/i915_reg.h| 126 + drivers/gpu/drm/i915/intel_bios.h | 74 drivers/gpu/drm/i915/intel_dsi.c | 274 ++-- drivers/gpu/drm/i915/intel_dsi.h |5 + drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 23 +++ drivers/gpu/drm/i915/intel_dsi_pll.c | 24 ++- include/drm/drm_mipi_dsi.h |4 +- include/video/mipi_display.h |3 + 10 files changed, 539 insertions(+), 25 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix VBT parsing for SDVO child device mapping
On Tue, 18 Aug 2015, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Tue, Aug 18, 2015 at 02:28:55PM +0300, Jani Nikula wrote:
commit 75067ddecf21271631bc018d2fb23ddd09b66aae
Author: Antti Koskipaa antti.koski...@linux.intel.com
Date: Fri Jul 10 14:10:55 2015 +0300
drm/i915: Per-DDI I_boost override
increased size of union child_device_config without taking into account
the size check in parse_sdvo_device_mapping(). Switch the function over
to using the legacy struct only.
Fixes: 75067ddecf21 (drm/i915: Per-DDI I_boost override)
Cc: Antti Koskipaa antti.koski...@linux.intel.com
Cc: David Weinehall david.weineh...@linux.intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Also gave it a spin on my 946gz so:
Tested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Pushed to drm-intel-next-fixes, thanks for the review and testing.
BR,
Jani.
---
drivers/gpu/drm/i915/intel_bios.c | 50
+++
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 8e46149bafdd..1b7e1a591a37 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -401,7 +401,7 @@ parse_sdvo_device_mapping(struct drm_i915_private
*dev_priv,
{
struct sdvo_device_mapping *p_mapping;
const struct bdb_general_definitions *p_defs;
-const union child_device_config *p_child;
+const struct old_child_dev_config *child; /* legacy */
int i, child_device_num, count;
u16 block_size;
@@ -410,14 +410,14 @@ parse_sdvo_device_mapping(struct drm_i915_private
*dev_priv,
DRM_DEBUG_KMS(No general definition block is found, unable to
construct sdvo mapping.\n);
return;
}
-/* judge whether the size of child device meets the requirements.
- * If the child device size obtained from general definition block
- * is different with sizeof(struct child_device_config), skip the
- * parsing of sdvo device info
+
+/*
+ * Only parse SDVO mappings when the general definitions block child
+ * device size matches that of the *legacy* child device config
+ * struct. Thus, SDVO mapping will be skipped for newer VBT.
*/
-if (p_defs-child_dev_size != sizeof(*p_child)) {
-/* different child dev size . Ignore it */
-DRM_DEBUG_KMS(different child size is found. Invalid.\n);
+if (p_defs-child_dev_size != sizeof(*child)) {
+DRM_DEBUG_KMS(Unsupported child device size for SDVO
mapping.\n);
return;
}
/* get the block size of general definitions */
@@ -427,37 +427,37 @@ parse_sdvo_device_mapping(struct drm_i915_private
*dev_priv,
p_defs-child_dev_size;
count = 0;
for (i = 0; i child_device_num; i++) {
-p_child = child_device_ptr(p_defs, i);
-if (!p_child-old.device_type) {
+child = child_device_ptr(p_defs, i)-old;
+if (!child-device_type) {
/* skip the device block if device type is invalid */
continue;
}
-if (p_child-old.slave_addr != SLAVE_ADDR1
-p_child-old.slave_addr != SLAVE_ADDR2) {
+if (child-slave_addr != SLAVE_ADDR1
+child-slave_addr != SLAVE_ADDR2) {
/*
* If the slave address is neither 0x70 nor 0x72,
* it is not a SDVO device. Skip it.
*/
continue;
}
-if (p_child-old.dvo_port != DEVICE_PORT_DVOB
-p_child-old.dvo_port != DEVICE_PORT_DVOC) {
+if (child-dvo_port != DEVICE_PORT_DVOB
+child-dvo_port != DEVICE_PORT_DVOC) {
/* skip the incorrect SDVO port */
DRM_DEBUG_KMS(Incorrect SDVO port. Skip it\n);
continue;
}
DRM_DEBUG_KMS(the SDVO device with slave addr %2x is found on
- %s port\n,
-p_child-old.slave_addr,
-(p_child-old.dvo_port == DEVICE_PORT_DVOB) ?
-SDVOB : SDVOC);
-p_mapping = (dev_priv-sdvo_mappings[p_child-old.dvo_port -
1]);
+ %s port\n,
+ child-slave_addr,
+ (child-dvo_port == DEVICE_PORT_DVOB) ?
+ SDVOB : SDVOC);
+p_mapping = (dev_priv-sdvo_mappings[child-dvo_port - 1]);
if (!p_mapping-initialized) {
-p_mapping-dvo_port = p_child-old.dvo_port;
-p_mapping-slave_addr = p_child-old.slave_addr;
-
Re: [Intel-gfx] [PATCH for v4.2] Revert drm/i915: Allow parsing of variable size child device entries from VBT
On Wed, 19 Aug 2015, Jani Nikula jani.nik...@intel.com wrote:
On Wed, 19 Aug 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 18, 2015 at 10:00 AM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Tue, Aug 18, 2015 at 09:58:57AM -0700, Daniel Vetter wrote:
On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula jani.nik...@intel.com wrote:
This reverts
commit 047fe6e6db9161e69271f56daaafdaf2add023b1
Author: David Weinehall david.weineh...@linux.intel.com
Date: Tue Aug 4 16:55:52 2015 +0300
drm/i915: Allow parsing of variable size child device entries from
VBT
That commit is not valid for v4.2, however it will be valid for v4.3. It
was simply queued too early.
Nope, this patch from David also incidentally fixes a regression from
90e4f1592bb6e82f6690f0e05a8aadc which is why I merged it to.
What regression?
Quoting the commit message: ... since we're hitting a DRM_ERROR on
older platforms with this. Not every platform has the BSW vbt layout
;-) Oh and why do I even bother to write this stuff when no one reads
it?
I read it, and I think it's wrong. I even explained why in my commit
message (yes, please read it). I don't think there was a DRM_ERROR on
older platform with Ville's patch, on v4.2 where the revert is targeted,
and even if there were, David's patch would *not* fix it. Indeed there
was no discussion of a regression on the mailing list.
If there was any regression, it was introduced by
commit 75067ddecf21271631bc018d2fb23ddd09b66aae
Author: Antti Koskipaa antti.koski...@linux.intel.com
Date: Fri Jul 10 14:10:55 2015 +0300
drm/i915: Per-DDI I_boost override
when the size of union child_device_config changed. But that's headed
for v4.3. And we're talking about v4.2, which is getting pretty
urgent. We'll have a bit more time to sort out the mess that will land
in v4.3 (and I've already sent one patch sorting out SDVO breakage).
I'm not waiting with this. I'm taking my chances, pushed to
drm-intel-fixes. Thanks for the review.
Note that the commit remains in drm-intel-next-fixes and
drm-intel-next-queued, but not in drm-intel-nightly due to this
revert. We'll need to clear that up, but for the time being getting v4.2
fixed up is of a higher priority to me.
BR,
Jani.
BR,
Jani.
-Daniel
If you
want to revert this, you need to revert more (and with that also break
BSW).
Isn't there a more minimal fix we can do for 4.2?
-Daniel
The referenced regressing commit is just fine until the size of struct
common_child_dev_config changes, and that won't happen until
v4.3. Indeed, the expected size checks here rely on the increased size
of the struct, breaking new platforms.
Fixes: 047fe6e6db91 (drm/i915: Allow parsing of variable size child
device entries from VBT)
Cc: Daniel Vetter dan...@ffwll.ch
Cc: David Weinehall david.weineh...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
There was another patch from David increasing the size of the struct
[1], but that then regresses sdvo mapping parsing. It's the simplest to
just revert and fix this up properly for v4.3.
[1] http://mid.gmane.org/20150813131415.GO6150@boom
---
drivers/gpu/drm/i915/intel_bios.c | 27 ---
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 3dcd59e694db..198fc3c3291b 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1075,34 +1075,15 @@ parse_device_mapping(struct drm_i915_private
*dev_priv,
const union child_device_config *p_child;
union child_device_config *child_dev_ptr;
int i, child_device_num, count;
- u8 expected_size;
- u16 block_size;
+ u16 block_size;
p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
if (!p_defs) {
DRM_DEBUG_KMS(No general definition block is found, no
devices defined.\n);
return;
}
- if (bdb-version 195) {
- expected_size = 33;
- } else if (bdb-version == 195) {
- expected_size = 37;
- } else if (bdb-version = 197) {
- expected_size = 38;
- } else {
- expected_size = 38;
- DRM_DEBUG_DRIVER(Expected child_device_config size for
BDB version %u not known; assuming %u\n,
-expected_size, bdb-version);
- }
-
- if (expected_size sizeof(*p_child)) {
- DRM_ERROR(child_device_config cannot fit in p_child\n);
- return;
- }
-
- if (p_defs-child_dev_size != expected_size) {
- DRM_ERROR(Size mismatch; child_device_config size=%u
(expected %u); bdb-version: %u\n,
-
Re: [Intel-gfx] [PATCH for v4.2] Revert drm/i915: Allow parsing of variable size child device entries from VBT
On Tue, 2015-08-18 at 09:58 -0700, Daniel Vetter wrote:
On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula jani.nik...@intel.com wrote:
This reverts
commit 047fe6e6db9161e69271f56daaafdaf2add023b1
Author: David Weinehall david.weineh...@linux.intel.com
Date: Tue Aug 4 16:55:52 2015 +0300
drm/i915: Allow parsing of variable size child device entries from VBT
That commit is not valid for v4.2, however it will be valid for v4.3. It
was simply queued too early.
Nope, this patch from David also incidentally fixes a regression from
90e4f1592bb6e82f6690f0e05a8aadc which is why I merged it to. If you
want to revert this, you need to revert more (and with that also break
BSW).
Isn't there a more minimal fix we can do for 4.2?
I proposed a very minimal solution just to increase the size of the raw
buffer to the maximum of 38 bytes so we could later on parse the correct
info.
May not be relevant anymore
https://bugs.freedesktop.org/show_bug.cgi?id=91269
-Mika-
-Daniel
The referenced regressing commit is just fine until the size of struct
common_child_dev_config changes, and that won't happen until
v4.3. Indeed, the expected size checks here rely on the increased size
of the struct, breaking new platforms.
Fixes: 047fe6e6db91 (drm/i915: Allow parsing of variable size child device
entries from VBT)
Cc: Daniel Vetter dan...@ffwll.ch
Cc: David Weinehall david.weineh...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
There was another patch from David increasing the size of the struct
[1], but that then regresses sdvo mapping parsing. It's the simplest to
just revert and fix this up properly for v4.3.
[1] http://mid.gmane.org/20150813131415.GO6150@boom
---
drivers/gpu/drm/i915/intel_bios.c | 27 ---
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 3dcd59e694db..198fc3c3291b 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1075,34 +1075,15 @@ parse_device_mapping(struct drm_i915_private
*dev_priv,
const union child_device_config *p_child;
union child_device_config *child_dev_ptr;
int i, child_device_num, count;
- u8 expected_size;
- u16 block_size;
+ u16 block_size;
p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
if (!p_defs) {
DRM_DEBUG_KMS(No general definition block is found, no
devices defined.\n);
return;
}
- if (bdb-version 195) {
- expected_size = 33;
- } else if (bdb-version == 195) {
- expected_size = 37;
- } else if (bdb-version = 197) {
- expected_size = 38;
- } else {
- expected_size = 38;
- DRM_DEBUG_DRIVER(Expected child_device_config size for BDB
version %u not known; assuming %u\n,
-expected_size, bdb-version);
- }
-
- if (expected_size sizeof(*p_child)) {
- DRM_ERROR(child_device_config cannot fit in p_child\n);
- return;
- }
-
- if (p_defs-child_dev_size != expected_size) {
- DRM_ERROR(Size mismatch; child_device_config size=%u
(expected %u); bdb-version: %u\n,
- p_defs-child_dev_size, expected_size,
bdb-version);
+ if (p_defs-child_dev_size sizeof(*p_child)) {
+ DRM_ERROR(General definiton block child device size is too
small.\n);
return;
}
/* get the block size of general definitions */
@@ -1149,7 +1130,7 @@ parse_device_mapping(struct drm_i915_private
*dev_priv,
child_dev_ptr = dev_priv-vbt.child_dev + count;
count++;
- memcpy(child_dev_ptr, p_child, p_defs-child_dev_size);
+ memcpy(child_dev_ptr, p_child, sizeof(*p_child));
}
return;
}
--
2.1.4
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Re: [Intel-gfx] [PATCH for v4.2] Revert drm/i915: Allow parsing of variable size child device entries from VBT
On Wed, 19 Aug 2015, Mika Kahola mika.kah...@intel.com wrote:
On Tue, 2015-08-18 at 09:58 -0700, Daniel Vetter wrote:
On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula jani.nik...@intel.com wrote:
This reverts
commit 047fe6e6db9161e69271f56daaafdaf2add023b1
Author: David Weinehall david.weineh...@linux.intel.com
Date: Tue Aug 4 16:55:52 2015 +0300
drm/i915: Allow parsing of variable size child device entries from VBT
That commit is not valid for v4.2, however it will be valid for v4.3. It
was simply queued too early.
Nope, this patch from David also incidentally fixes a regression from
90e4f1592bb6e82f6690f0e05a8aadc which is why I merged it to. If you
want to revert this, you need to revert more (and with that also break
BSW).
Isn't there a more minimal fix we can do for 4.2?
I proposed a very minimal solution just to increase the size of the raw
buffer to the maximum of 38 bytes so we could later on parse the correct
info.
That doesn't work because it breaks parse_sdvo_device_mapping(). I've
fixed this now in drm-intel-next-fixes to be queued for v4.3, but I do
not want to start patching up broken commits at v4.2-rc7 stage.
As I've said, if Ville's commit 90e4f1592bb6 really does break stuff in
v4.2 (*), David's commit 047fe6e6db91 does not fix it in v4.2 anyway.
Thus I've applied the revert. It is the minimal fix. v4.2 will be
fine. For v4.3 I'll need to make a backmerge from drm-intel-fixes to
drm-intel-next-fixes, and we can move on to fixing v4.3.
BR,
Jani.
(*) which I highly doubt in the first place; likely this was seen in
-nightly and erroneously attributed as a regression on 90e4f1592bb6.
May not be relevant anymore
https://bugs.freedesktop.org/show_bug.cgi?id=91269
-Mika-
-Daniel
The referenced regressing commit is just fine until the size of struct
common_child_dev_config changes, and that won't happen until
v4.3. Indeed, the expected size checks here rely on the increased size
of the struct, breaking new platforms.
Fixes: 047fe6e6db91 (drm/i915: Allow parsing of variable size child
device entries from VBT)
Cc: Daniel Vetter dan...@ffwll.ch
Cc: David Weinehall david.weineh...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
There was another patch from David increasing the size of the struct
[1], but that then regresses sdvo mapping parsing. It's the simplest to
just revert and fix this up properly for v4.3.
[1] http://mid.gmane.org/20150813131415.GO6150@boom
---
drivers/gpu/drm/i915/intel_bios.c | 27 ---
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 3dcd59e694db..198fc3c3291b 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1075,34 +1075,15 @@ parse_device_mapping(struct drm_i915_private
*dev_priv,
const union child_device_config *p_child;
union child_device_config *child_dev_ptr;
int i, child_device_num, count;
- u8 expected_size;
- u16 block_size;
+ u16 block_size;
p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
if (!p_defs) {
DRM_DEBUG_KMS(No general definition block is found, no
devices defined.\n);
return;
}
- if (bdb-version 195) {
- expected_size = 33;
- } else if (bdb-version == 195) {
- expected_size = 37;
- } else if (bdb-version = 197) {
- expected_size = 38;
- } else {
- expected_size = 38;
- DRM_DEBUG_DRIVER(Expected child_device_config size for
BDB version %u not known; assuming %u\n,
-expected_size, bdb-version);
- }
-
- if (expected_size sizeof(*p_child)) {
- DRM_ERROR(child_device_config cannot fit in p_child\n);
- return;
- }
-
- if (p_defs-child_dev_size != expected_size) {
- DRM_ERROR(Size mismatch; child_device_config size=%u
(expected %u); bdb-version: %u\n,
- p_defs-child_dev_size, expected_size,
bdb-version);
+ if (p_defs-child_dev_size sizeof(*p_child)) {
+ DRM_ERROR(General definiton block child device size is
too small.\n);
return;
}
/* get the block size of general definitions */
@@ -1149,7 +1130,7 @@ parse_device_mapping(struct drm_i915_private
*dev_priv,
child_dev_ptr = dev_priv-vbt.child_dev + count;
count++;
- memcpy(child_dev_ptr, p_child, p_defs-child_dev_size);
+ memcpy(child_dev_ptr, p_child, sizeof(*p_child));
}
return;
}
--
2.1.4
--
Jani Nikula,
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Adding Panel Filter function for DP
On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote:
On Fri, Aug 14, 2015 at 05:12:57AM +, Zhang, Xiong Y wrote:
On Mon, Aug 10, 2015 at 03:26:09PM +0800, Xiong Zhang wrote:
Only internal eDP, LVDS, DVI screen could set scalling mode, some
customers need to set scalling mode for external DP, HDMI, VGA screen.
Let's fulfill this.
bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90989
Signed-off-by: Xiong Zhang xiong.y.zh...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 63
-
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c index f1b9f93..2da334b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -207,7 +207,13 @@ intel_dp_mode_valid(struct drm_connector
*connector,
int target_clock = mode-clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
- if (is_edp(intel_dp) fixed_mode) {
+ if (mode-clock 1)
+ return MODE_CLOCK_LOW;
+
+ if (mode-flags DRM_MODE_FLAG_DBLCLK)
+ return MODE_H_ILLEGAL;
+
+ if (!intel_panel_scale_none(intel_connector-panel)) {
if (mode-hdisplay fixed_mode-hdisplay)
return MODE_PANEL;
@@ -226,12 +232,6 @@ intel_dp_mode_valid(struct drm_connector
*connector,
if (mode_rate max_rate)
return MODE_CLOCK_HIGH;
- if (mode-clock 1)
- return MODE_CLOCK_LOW;
-
- if (mode-flags DRM_MODE_FLAG_DBLCLK)
- return MODE_H_ILLEGAL;
-
return MODE_OK;
}
@@ -1378,7 +1378,7 @@ intel_dp_compute_config(struct
intel_encoder
*encoder,
pipe_config-has_drrs = false;
pipe_config-has_audio = intel_dp-has_audio port != PORT_A;
- if (is_edp(intel_dp) intel_connector-panel.fixed_mode) {
+ if (!intel_panel_scale_none(intel_connector-panel)) {
intel_fixed_panel_mode(intel_connector-panel.fixed_mode,
adjusted_mode);
@@ -4592,6 +4592,23 @@ static int intel_dp_get_modes(struct
drm_connector *connector)
edid = intel_connector-detect_edid;
if (edid) {
int ret = intel_connector_update_modes(connector, edid);
+
+ if (ret intel_connector-panel.fixed_mode == NULL) {
+ /* init fixed mode as preferred mode for DP */
+ struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *scan;
+
+ list_for_each_entry(scan,
connector-probed_modes,
head) {
+ if (scan-type
DRM_MODE_TYPE_PREFERRED)
+ fixed_mode =
drm_mode_duplicate(connector-dev,
+
scan);
+ }
+
+ if (fixed_mode)
+
intel_panel_init(intel_connector-panel,
+ fixed_mode, NULL);
+ }
How are we supposed to get rid of a stale fixed_mode when some other
display gets plugged in?
[Zhang, Xiong Y] Thanks so much for your good question. Yes, we should
clear the
stale fitting_mode and fixed_mode when display is disconnect in
intel_dp_hpd_pulse() function.
Also what would happen if the preferred mode can't be supported due to
some
source limitation?
[Zhang, Xiong Y] In this case, which mode should be selected as
fixed_mode ?
At the very least we should make sure it's a mode we can use.
As you said maybe kernel isn't the right place to do such decision.
There are a lot of options how we could pick the mode. Eg. might want to
pick the next largest mode, and if there is none try to pick the largest
smaller mode (since pfit can't downscale by much). Also should we try to
pick an intelaced mode if the user requested one etc. Lots of open
questions how this policy should be handled. Would be easier to punt it
all to userspace, which would also avoid the kernel policy doing the
wrong thing when userspace knows what it wants.
In general I'm not entirely happy with having this kind of policy in the
kernel.
I'd much prefer if we could get crtc size and border properties done so
that
userspace could set up the scaling any which way it chooses.
[Zhang, Xiong Y] Could you give more detail about your preference ?
The idea would be to expose some sort of crtc size properties that would
provide pipe_src_{w,h}, and the
Re: [Intel-gfx] [PATCH] drm/i915: Avoid TP3 on CHV
On Tue, 18 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com
wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
v2: rename the function to indicate it checks source rates (Jani)
v3: update comment to indicate TP3 dependancy on HBR2 supported
hardware (Jani)
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
Pushed first three patches in the series to drm-intel-fixes, thanks for
the patches and review. (The last patch is skl specific, I'll pick it up
for v4.3 in drm-intel-next-fixes after a backmerge.)
BR,
Jani.
---
drivers/gpu/drm/i915/intel_dp.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 475d8cb..051614a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const
int **sink_rates)
return (intel_dp_max_link_bw(intel_dp) 3) + 1;
}
+static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
+{
+ /* WaDisableHBR2:skl */
+ if (IS_SKYLAKE(dev) INTEL_REVID(dev) = SKL_REVID_B0)
+ return false;
+
+ if ((IS_HASWELL(dev) !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
+ (INTEL_INFO(dev)-gen = 9))
+ return true;
+ else
+ return false;
+}
+
+
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
@@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const
int **source_rates)
*source_rates = default_rates;
- /* WaDisableHBR2:skl */
- if (IS_SKYLAKE(dev) INTEL_REVID(dev) = SKL_REVID_B0)
- return (DP_LINK_BW_2_7 3) + 1;
-
- if ((IS_HASWELL(dev) !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
- (INTEL_INFO(dev)-gen = 9))
+ /* This depends on the fact that 5.4 is last value in the array */
+ if (intel_dp_source_supports_hbr2(dev))
return (DP_LINK_BW_5_4 3) + 1;
else
return (DP_LINK_BW_2_7 3) + 1;
@@ -3923,10 +3933,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
}
}
- /* Training Pattern 3 support, both source and sink */
+ /* Training Pattern 3 support, Intel platforms that support HBR2 alone
+ * have support for TP3 hence that check is used along with dpcd check
+ * to ensure TP3 can be enabled.
+ * SKL B0: due it's WaDisableHBR2 is the only exception where TP3 is
+ * supported but still not enabled.
+ */
if (intel_dp-dpcd[DP_DPCD_REV] = 0x12
intel_dp-dpcd[DP_MAX_LANE_COUNT] DP_TPS3_SUPPORTED
- (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)-gen = 8)) {
+ intel_dp_source_supports_hbr2(dev)) {
intel_dp-use_tps3 = true;
DRM_DEBUG_KMS(Displayport TPS3 supported\n);
} else
--
1.7.9.5
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 15/16] Revert drm/i915: Allocate fbcon from stolen memory
On Tue, Aug 18, 2015 at 09:54:57PM +, Zanoni, Paulo R wrote: Em Sáb, 2015-08-15 às 09:24 +0100, Chris Wilson escreveu: On Fri, Aug 14, 2015 at 06:34:20PM -0300, Paulo Zanoni wrote: This reverts commit 0ffb0ff283cca16f72caf29c44496d83b0c291fb. Technology has evolved and now we have eDP panels with 3200x1800 resolution. In the meantime, the BIOS guys didn't change the default 32mb for stolen memory. And we can't assume our users will be able to increase the default stolen memory size to more than 32mb - I'm not even sure all BIOSes allow that. So just the fbcon buffer alone eats 22mb of my stolen memroy, and due to the BDW/SKL restriction of not using the last 8mb of stolen memory, all that's left for FBC is 2mb! Since fbcon is not the coolest feature ever, I think it's better to save our precious stolen resource to FBC and the other guys. Besides, neither the original commit message nor the review comments showed any arguments in favor of actually allocating fbcon from stolen. Pardon? pzanoni@panetone:~/git/kernel/kernel$ git show 0ffb0ff283cca16f72caf29c44496d83b0c291fb | head -n 12 commit 0ffb0ff283cca16f72caf29c44496d83b0c291fb Author: Chris Wilson ch...@chris-wilson.co.uk Date: Thu Nov 15 11:32:27 2012 + drm/i915: Allocate fbcon from stolen memory Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org Acked-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c pzanoni@panetone:~/git/kernel/kernel$ Sorry, I though it was pretty self explanatory that we want to reuse as much as stolen as is possible on all machines, epecially those where even 8MiB reserved is about 10% of available memory. So not using it for pinned memory is a double whammy. That would have been said in the preceeding patches to enable stolen memory. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/16] drm/i915: avoid the last 8mb of stolen on BDW/SKL
On Tue, Aug 18, 2015 at 09:49:34PM +, Zanoni, Paulo R wrote: Em Sáb, 2015-08-15 às 09:29 +0100, Chris Wilson escreveu: On Fri, Aug 14, 2015 at 06:34:13PM -0300, Paulo Zanoni wrote: The FBC hardware for these platforms doesn't have access to the bios_reserved range, so it always assumes the maximum (8mb) is used. So avoid this range while allocating. This solves a bunch of FIFO underruns that happen if you end up putting the CFB in that memory range. On my machine, with 32mb of stolen, I need a 2560x1440 mode for that. If the restriction applies only to FBC, apply it to only fbc. That's what the patch is doing. The part where we set the unusual start/end is at intel_fbc.c:find_compression_threshold(). Everything else should be behaving just as before. Maybe you're being confused by the addition of the stolen_usable_size variable. Hmm, I expected to see the constaint being passed into the search routine.a It looked like you were adjusting the stolen_size probably the root of my confusion. Anyway we have a quandary. You want to reserve stolen space, and I want to make sure as much of it gets used as possible (especially for long lived objects). What I have in mind is adding a priority to the search and allow us to evict anything of lower priority. We can use a page replacement algorithm even for the pinned fbcon (since only the GGTT itself is pinned and we can swap the pages underneath). This of course requires a callback for low priority evictable objects. I have 3 priorities in mind plus the evictable flag: USER, KERNEL, POWER (with FBC taking the highest priority of POWER). That will allow us to do the BIOS takeover and only if we run out of space force the copy. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] ALSA: hda - Wake the codec up on pin/ELD notify events
Whenever there is an event from the i915 driver, wake the codec
and recheck plug/unplug + ELD status.
This fixes the issue with lost unsol events in power save mode,
the codec and controller can now sleep in D3 and still know when
the HDMI monitor has been connected.
Signed-off-by: David Henningsson david.hennings...@canonical.com
---
sound/pci/hda/patch_hdmi.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index a97db5f..932292c 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -37,6 +37,8 @@
#include sound/jack.h
#include sound/asoundef.h
#include sound/tlv.h
+#include sound/hdaudio.h
+#include sound/hda_i915.h
#include hda_codec.h
#include hda_local.h
#include hda_jack.h
@@ -144,6 +146,9 @@ struct hdmi_spec {
*/
struct hda_multi_out multiout;
struct hda_pcm_stream pcm_playback;
+
+ /* i915/powerwell (Haswell+/Valleyview+) specific */
+ struct i915_audio_component_audio_ops i915_audio_ops;
};
@@ -2191,6 +2196,9 @@ static void generic_hdmi_free(struct hda_codec *codec)
struct hdmi_spec *spec = codec-spec;
int pin_idx;
+ if (is_haswell_plus(codec) || is_valleyview_plus(codec))
+ snd_hdac_i915_register_notifier(NULL);
+
for (pin_idx = 0; pin_idx spec-num_pins; pin_idx++) {
struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
@@ -2316,6 +2324,14 @@ static void haswell_set_power_state(struct hda_codec
*codec, hda_nid_t fg,
snd_hda_codec_set_power_to_all(codec, fg, power_state);
}
+static void intel_pin_eld_notify(void *audio_ptr, int port, int port_mst_index)
+{
+ struct hda_codec *codec = audio_ptr;
+ int pin_nid = port + 0x04;
+
+ check_presence_and_report(codec, pin_nid);
+}
+
static int patch_generic_hdmi(struct hda_codec *codec)
{
struct hdmi_spec *spec;
@@ -2342,8 +2358,12 @@ static int patch_generic_hdmi(struct hda_codec *codec)
if (is_valleyview_plus(codec) || is_skylake(codec))
codec-core.link_power_control = 1;
- if (is_haswell_plus(codec) || is_valleyview_plus(codec))
+ if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
codec-depop_delay = 0;
+ spec-i915_audio_ops.audio_ptr = codec;
+ spec-i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
+ snd_hdac_i915_register_notifier(spec-i915_audio_ops);
+ }
if (hdmi_parse_codec(codec) 0) {
codec-spec = NULL;
--
1.9.1
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[Intel-gfx] [PATCH 3/4] ALSA: hda - allow codecs to access the i915 pin/ELD callback
This lets the interested codec be notified when an i915 pin/ELD
event happens.
Signed-off-by: David Henningsson david.hennings...@canonical.com
---
include/sound/hda_i915.h | 7 +++
sound/hda/hdac_i915.c| 10 ++
2 files changed, 17 insertions(+)
diff --git a/include/sound/hda_i915.h b/include/sound/hda_i915.h
index adb5ba5..a0a1d67 100644
--- a/include/sound/hda_i915.h
+++ b/include/sound/hda_i915.h
@@ -4,12 +4,15 @@
#ifndef __SOUND_HDA_I915_H
#define __SOUND_HDA_I915_H
+#include drm/i915_component.h
+
#ifdef CONFIG_SND_HDA_I915
int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable);
int snd_hdac_display_power(struct hdac_bus *bus, bool enable);
int snd_hdac_get_display_clk(struct hdac_bus *bus);
int snd_hdac_i915_init(struct hdac_bus *bus);
int snd_hdac_i915_exit(struct hdac_bus *bus);
+int snd_hdac_i915_register_notifier(const struct
i915_audio_component_audio_ops *);
#else
static int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable)
{
@@ -31,6 +34,10 @@ static inline int snd_hdac_i915_exit(struct hdac_bus *bus)
{
return 0;
}
+static inline int snd_hdac_i915_register_notifier(const struct
i915_audio_component_audio_ops *)
+{
+ return -ENODEV;
+}
#endif
#endif /* __SOUND_HDA_I915_H */
diff --git a/sound/hda/hdac_i915.c b/sound/hda/hdac_i915.c
index 5676b84..55c3df4 100644
--- a/sound/hda/hdac_i915.c
+++ b/sound/hda/hdac_i915.c
@@ -134,6 +134,16 @@ static int hdac_component_master_match(struct device *dev,
void *data)
return !strcmp(dev-driver-name, i915);
}
+int snd_hdac_i915_register_notifier(const struct
i915_audio_component_audio_ops *aops)
+{
+ if (WARN_ON(!hdac_acomp))
+ return -ENODEV;
+
+ hdac_acomp-audio_ops = aops;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_i915_register_notifier);
+
int snd_hdac_i915_init(struct hdac_bus *bus)
{
struct component_match *match = NULL;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915: Call audio pin/ELD notify function
When the audio codec is enabled or disabled, notify the audio driver.
This will enable the audio driver to get the notification at all times
(even when audio is in different powersave states).
Signed-off-by: David Henningsson david.hennings...@canonical.com
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_audio.c | 23 ---
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fd1de45..1fc327d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1809,6 +1809,7 @@ struct drm_i915_private {
struct drm_property *force_audio_property;
/* hda/i915 audio component */
+ struct i915_audio_component *audio_component;
bool audio_component_registered;
uint32_t hw_context_size;
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 3da9b84..969835d 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -399,6 +399,9 @@ void intel_audio_codec_enable(struct intel_encoder
*intel_encoder)
struct drm_connector *connector;
struct drm_device *dev = encoder-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
+ struct i915_audio_component *acomp = dev_priv-audio_component;
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ enum port port = intel_dig_port-port;
connector = drm_select_eld(encoder, mode);
if (!connector)
@@ -419,6 +422,9 @@ void intel_audio_codec_enable(struct intel_encoder
*intel_encoder)
if (dev_priv-display.audio_codec_enable)
dev_priv-display.audio_codec_enable(connector, intel_encoder,
mode);
+
+ if (acomp acomp-audio_ops acomp-audio_ops-pin_eld_notify)
+ acomp-audio_ops-pin_eld_notify(acomp-audio_ops-audio_ptr,
(int) port, 0);
}
/**
@@ -428,13 +434,20 @@ void intel_audio_codec_enable(struct intel_encoder
*intel_encoder)
* The disable sequences must be performed before disabling the transcoder or
* port.
*/
-void intel_audio_codec_disable(struct intel_encoder *encoder)
+void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
{
- struct drm_device *dev = encoder-base.dev;
+ struct drm_encoder *encoder = intel_encoder-base;
+ struct drm_device *dev = encoder-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
+ struct i915_audio_component *acomp = dev_priv-audio_component;
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ enum port port = intel_dig_port-port;
if (dev_priv-display.audio_codec_disable)
- dev_priv-display.audio_codec_disable(encoder);
+ dev_priv-display.audio_codec_disable(intel_encoder);
+
+ if (acomp acomp-audio_ops acomp-audio_ops-pin_eld_notify)
+ acomp-audio_ops-pin_eld_notify(acomp-audio_ops-audio_ptr,
(int) port, 0);
}
/**
@@ -525,12 +538,14 @@ static int i915_audio_component_bind(struct device
*i915_dev,
struct device *hda_dev, void *data)
{
struct i915_audio_component *acomp = data;
+ struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
if (WARN_ON(acomp-ops || acomp-dev))
return -EEXIST;
acomp-ops = i915_audio_component_ops;
acomp-dev = i915_dev;
+ dev_priv-audio_component = acomp;
return 0;
}
@@ -539,9 +554,11 @@ static void i915_audio_component_unbind(struct device
*i915_dev,
struct device *hda_dev, void *data)
{
struct i915_audio_component *acomp = data;
+ struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
acomp-ops = NULL;
acomp-dev = NULL;
+ dev_priv-audio_component = NULL;
}
static const struct component_ops i915_audio_component_bind_ops = {
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 0/4] i915 to call hda driver on HDMI plug/unplug
It's been a while since the last patch set iteration, due to me being on vacation. But here's a new set, and I still hope that it can make it into the next merge window. Changes since v3 (with the person suggesting that change within parantheses): * Valleyview now has three pins like all the others (Libin Yang) * Renamed a few references from hotplug to pin_eld to reduce confusion with hotplug code on the i915 side (Jani Nikula) * Rewrote the dispatching from hda core to codec on the hda side (Takashi Iwai) This iteration has been tested and working on one Skylake machine. David Henningsson (4): drm/i915: Add audio pin sense / ELD callback drm/i915: Call audio pin/ELD notify function ALSA: hda - allow codecs to access the i915 pin/ELD callback ALSA: hda - Wake the codec up on pin/ELD notify events drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915/intel_audio.c | 23 --- include/drm/i915_component.h | 12 include/sound/hda_i915.h | 7 +++ sound/hda/hdac_i915.c | 10 ++ sound/pci/hda/patch_hdmi.c | 22 +- 6 files changed, 71 insertions(+), 4 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/i915: Add audio pin sense / ELD callback
This callback will be called by the i915 driver to notify the hda
driver that its HDMI information needs to be refreshed, i e,
that audio output is now available (or unavailable) - usually as a
result of a monitor being plugged in (or unplugged).
Signed-off-by: David Henningsson david.hennings...@canonical.com
---
include/drm/i915_component.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index c9a8b64..ab5bde37 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -34,6 +34,18 @@ struct i915_audio_component {
void (*codec_wake_override)(struct device *, bool enable);
int (*get_cdclk_freq)(struct device *);
} *ops;
+
+ const struct i915_audio_component_audio_ops {
+ void *audio_ptr;
+ /**
+* Call from i915 driver, notifying the HDA driver that
+* pin sense and/or ELD information has changed.
+* @audio_ptr: HDA driver object
+* @port: Which port has changed (PORTA / PORTB /
PORTC etc)
+* @port_mst_index: Index within that port, for DisplayPort
multistreaming
+*/
+ void (*pin_eld_notify)(void *audio_ptr, int port, int
port_mst_index);
+ } *audio_ops;
};
#endif /* _I915_COMPONENT_H_ */
--
1.9.1
___
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915: Always enable execlists on BDW for vgpu
Broadwell hardware supports both ring buffer mode and execlist mode. When i915 runs inside a VM with Intel GVT-g, we allow execlist mode only. The reason is that GVT-g does not support the dynamic mode switch between ring buffer mode and execlist mode when running multiple virtual machines. Consider that ring buffer mode is legacy mode, it makes sense to drop it inside virtual machines. Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com Signed-off-by: Zhi Wang zhi.a.w...@intel.com --- drivers/gpu/drm/i915/intel_lrc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 2dc8709..39df304 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -239,6 +239,9 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists if (INTEL_INFO(dev)-gen = 9) return 1; + if (HAS_LOGICAL_RING_CONTEXTS(dev) intel_vgpu_active(dev)) + return 1; + if (enable_execlists == 0) return 0; -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/7] drm/i915: Enable full ppgtt for vgpu
The full ppgtt is supported in Intel GVT-g device model. So the restriction can be removed. Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com Signed-off-by: Zhi Wang zhi.a.w...@intel.com --- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index ed10e77..823005c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -108,9 +108,6 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) has_aliasing_ppgtt = INTEL_INFO(dev)-gen = 6; has_full_ppgtt = INTEL_INFO(dev)-gen = 7; - if (intel_vgpu_active(dev)) - has_full_ppgtt = false; /* emulation is too hard */ - /* * We don't allow disabling PPGTT for gen9+ as it's a requirement for * execlists, the sole mechanism available to submit work. -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915: preallocate pdps for 32 bit vgpu
This is based on Mika Kuoppala's patch below:
http://article.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/61104/match=workaround+hw+preload
The patch will preallocate the page directories for 32-bit PPGTT when
i915 runs inside a virtual machine with Intel GVT-g. With this change,
the root pointers in EXECLIST context will always keep the same.
The change is needed for vGPU because Intel GVT-g will do page table
shadowing, and needs to track all the page table changes from guest
i915 driver. However, if guest PPGTT is modified through GPU commands
like LRI, it is not possible to trap the operations in the right time,
so it will be hard to make shadow PPGTT to work correctly.
Shadow PPGTT could be much simpler with this change. Meanwhile
hypervisor could simply prohibit any attempt of PPGTT modification
through GPU command for security.
The function gen8_preallocate_top_level_pdps() in the patch is from
Mika, with only one change to set used_pdpes to avoid duplicated
allocation later.
Cc: Mika Kuoppala mika.kuopp...@intel.com
Cc: Dave Gordon david.s.gor...@intel.com
Cc: Michel Thierry michel.thie...@intel.com
Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com
Signed-off-by: Zhi Wang zhi.a.w...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +
drivers/gpu/drm/i915/intel_lrc.c| 3 ++-
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4a76807..ed10e77 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1441,6 +1441,33 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
}
}
+static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
+{
+ unsigned long *new_page_dirs, **new_page_tables;
+ uint32_t pdpes = I915_PDPES_PER_PDP(dev);
+ int ret;
+
+ /* We allocate temp bitmap for page tables for no gain
+* but as this is for init only, lets keep the things simple
+*/
+ ret = alloc_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+ if (ret)
+ return ret;
+
+ /* Allocate for all pdps regardless of how the ppgtt
+* was defined.
+*/
+ ret = gen8_ppgtt_alloc_page_directories(ppgtt-base, ppgtt-pdp,
+ 0, 1ULL 32,
+ new_page_dirs);
+ if (!ret)
+ *ppgtt-pdp.used_pdpes = *new_page_dirs;
+
+ free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+
+ return ret;
+}
+
/*
* GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
* with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1484,6 +1511,12 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
trace_i915_page_directory_pointer_entry_alloc(ppgtt-base,
0, 0,
GEN8_PML4E_SHIFT);
+
+ if (intel_vgpu_active(ppgtt-base.dev)) {
+ ret = gen8_preallocate_top_level_pdps(ppgtt);
+ if (ret)
+ goto free_scratch;
+ }
}
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e77b6b0..2dc8709 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1540,7 +1540,8 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request
*req,
* not needed in 48-bit.*/
if (req-ctx-ppgtt
(intel_ring_flag(req-ring) req-ctx-ppgtt-pd_dirty_rings)) {
- if (!USES_FULL_48BIT_PPGTT(req-i915)) {
+ if (!USES_FULL_48BIT_PPGTT(req-i915)
+ !intel_vgpu_active(req-i915-dev)) {
ret = intel_logical_ring_emit_pdps(req);
if (ret)
return ret;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/7] drm/intel: guest i915 changes for Broadwell to run inside VM with Intel GVT-g
I915 kernel driver can now work inside a virtual machine on Haswell with Intel GVT-g. In order to do the same thing on Broadwell, there are some extra changes needed. The two main things are to support the more complicated PPGTT page table structure and EXECLIST contexts. GVT-g will perform shadow PPGTT and shadow context, which requires guest driver to explicitly notify host device model the life cycle of PPGTT and EXECLIST contexts. The first and the forth patches added some restrictions to drivers in virtualization scenario to make the shadow work easier. The first patch is based on Mika's earlier one, but we use it for vgpu only. The sixth patch is the implementation of the notification for shadowing. Zhiyuan Lv (7): drm/i915: preallocate pdps for 32 bit vgpu drm/i915: Enable full ppgtt for vgpu drm/i915: Always enable execlists on BDW for vgpu drm/i915: always pin lrc context for vgpu with Intel GVT-g drm/i915: Update PV INFO page definition for Intel GVT-g drm/i915: guest i915 notification for Intel-GVTg drm/i915: Allow Broadwell guest with Intel GVT-g drivers/gpu/drm/i915/i915_gem_gtt.c | 77 +++-- drivers/gpu/drm/i915/i915_vgpu.c| 2 +- drivers/gpu/drm/i915/i915_vgpu.h| 34 +++- drivers/gpu/drm/i915/intel_lrc.c| 44 ++--- 4 files changed, 145 insertions(+), 12 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/7] drm/i915: Update PV INFO page definition for Intel GVT-g
Some more definitions in the PV info page are added. They are mainly
for the guest notification to Intel GVT-g device model. They are used
for Broadwell enabling.
Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com
Signed-off-by: Zhi Wang zhi.a.w...@intel.com
---
drivers/gpu/drm/i915/i915_vgpu.h | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 97a88b5..21c97f4 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -40,6 +40,19 @@
#define INTEL_VGT_IF_VERSION \
INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
+/*
+ * notifications from guest to vgpu device model
+ */
+enum vgt_g2v_type {
+ VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
+ VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
+ VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
+ VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
+ VGT_G2V_EXECLIST_CONTEXT_CREATE,
+ VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+ VGT_G2V_MAX,
+};
+
struct vgt_if {
uint64_t magic; /* VGT_MAGIC */
uint16_t version_major;
@@ -70,11 +83,28 @@ struct vgt_if {
uint32_t rsv3[0x200 - 24]; /* pad to half page */
/*
* The bottom half page is for response from Gfx driver to hypervisor.
-* Set to reserved fields temporarily by now.
*/
uint32_t rsv4;
uint32_t display_ready; /* ready for display owner switch */
- uint32_t rsv5[0x200 - 2]; /* pad to one page */
+
+ uint32_t rsv5[4];
+
+ uint32_t g2v_notify;
+ uint32_t rsv6[7];
+
+ uint32_t pdp0_lo;
+ uint32_t pdp0_hi;
+ uint32_t pdp1_lo;
+ uint32_t pdp1_hi;
+ uint32_t pdp2_lo;
+ uint32_t pdp2_hi;
+ uint32_t pdp3_lo;
+ uint32_t pdp3_hi;
+
+ uint32_t execlist_context_descriptor_lo;
+ uint32_t execlist_context_descriptor_hi;
+
+ uint32_t rsv7[0x200 - 24];/* pad to one page */
} __packed;
#define vgtif_reg(x) \
--
1.9.1
___
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915: always pin lrc context for vgpu with Intel GVT-g
Intel GVT-g will perform EXECLIST context shadowing and ring buffer
shadowing. The shadow copy is created when guest creates a context.
If a context changes its LRCA address, the hypervisor is hard to know
whether it is a new context or not. We always pin context objects to
global GTT to make life easier.
Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com
Signed-off-by: Zhi Wang zhi.a.w...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 39df304..4b2ac37 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2282,7 +2282,8 @@ void intel_lr_context_free(struct intel_context *ctx)
ctx-engine[i].ringbuf;
struct intel_engine_cs *ring = ringbuf-ring;
- if (ctx == ring-default_context) {
+ if ((ctx == ring-default_context) ||
+ (intel_vgpu_active(ring-dev))) {
intel_unpin_ringbuffer_obj(ringbuf);
i915_gem_object_ggtt_unpin(ctx_obj);
}
@@ -2353,6 +2354,8 @@ int intel_lr_context_deferred_create(struct intel_context
*ctx,
struct intel_engine_cs *ring)
{
const bool is_global_default_ctx = (ctx == ring-default_context);
+ const bool need_to_pin_ctx = (is_global_default_ctx ||
+ (intel_vgpu_active(ring-dev)));
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_gem_object *ctx_obj;
@@ -2374,7 +2377,7 @@ int intel_lr_context_deferred_create(struct intel_context
*ctx,
return -ENOMEM;
}
- if (is_global_default_ctx) {
+ if (need_to_pin_ctx) {
ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
if (ret) {
@@ -2415,7 +2418,7 @@ int intel_lr_context_deferred_create(struct intel_context
*ctx,
goto error_free_rbuf;
}
- if (is_global_default_ctx) {
+ if (need_to_pin_ctx) {
ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
if (ret) {
DRM_ERROR(
@@ -2464,14 +2467,14 @@ int intel_lr_context_deferred_create(struct
intel_context *ctx,
return 0;
error:
- if (is_global_default_ctx)
+ if (need_to_pin_ctx)
intel_unpin_ringbuffer_obj(ringbuf);
error_destroy_rbuf:
intel_destroy_ringbuffer_obj(ringbuf);
error_free_rbuf:
kfree(ringbuf);
error_unpin_ctx:
- if (is_global_default_ctx)
+ if (need_to_pin_ctx)
i915_gem_object_ggtt_unpin(ctx_obj);
drm_gem_object_unreference(ctx_obj-base);
return ret;
--
1.9.1
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/7] drm/i915: Allow Broadwell guest with Intel GVT-g
I915 Broadwell guest driver is now supported to run inside a VM with Intel GVT-g Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com Signed-off-by: Zhi Wang zhi.a.w...@intel.com --- drivers/gpu/drm/i915/i915_vgpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 5eee75b..fdeb461 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -66,7 +66,7 @@ void i915_check_vgpu(struct drm_device *dev) BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE); - if (!IS_HASWELL(dev)) + if (!IS_HASWELL(dev) !IS_BROADWELL(dev)) return; magic = readq(dev_priv-regs + vgtif_reg(magic)); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915: guest i915 notification for Intel-GVTg
When i915 drivers run inside a VM with Intel-GVTg, some explicit
notifications are needed from guest to host device model through PV
INFO page write. The notifications include:
PPGTT create/destroy
EXECLIST create/destroy
They are used for the shadow implementation of PPGTT and EXECLIST
context. Intel GVT-g needs to write-protect the guest pages of PPGTT
and contexts, and clear the write protection when they end their life
cycle.
Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com
Signed-off-by: Zhi Wang zhi.a.w...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +
drivers/gpu/drm/i915/intel_lrc.c| 25 ++
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 823005c..00dafb0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -896,6 +896,41 @@ static int gen8_init_scratch(struct i915_address_space *vm)
return 0;
}
+static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
+{
+ enum vgt_g2v_type msg;
+ struct drm_device *dev = ppgtt-base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned int offset = vgtif_reg(pdp0_lo);
+ int i;
+
+ if (USES_FULL_48BIT_PPGTT(dev)) {
+ u64 daddr = px_dma(ppgtt-pml4);
+
+ I915_WRITE(offset, daddr 0x);
+ I915_WRITE(offset + 4, daddr 32);
+
+ msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
+ VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
+ } else {
+ for (i = 0; i GEN8_LEGACY_PDPES; i++) {
+ u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
+
+ I915_WRITE(offset, daddr 0x);
+ I915_WRITE(offset + 4, daddr 32);
+
+ offset += 8;
+ }
+
+ msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
+ VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
+ }
+
+ I915_WRITE(vgtif_reg(g2v_notify), msg);
+
+ return 0;
+}
+
static void gen8_free_scratch(struct i915_address_space *vm)
{
struct drm_device *dev = vm-dev;
@@ -942,6 +977,9 @@ static void gen8_ppgtt_cleanup(struct i915_address_space
*vm)
struct i915_hw_ppgtt *ppgtt =
container_of(vm, struct i915_hw_ppgtt, base);
+ if (intel_vgpu_active(vm-dev))
+ gen8_ppgtt_notify_vgt(ppgtt, false);
+
if (!USES_FULL_48BIT_PPGTT(ppgtt-base.dev))
gen8_ppgtt_cleanup_3lvl(ppgtt-base.dev, ppgtt-pdp);
else
@@ -1516,6 +1554,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
}
}
+ if (intel_vgpu_active(ppgtt-base.dev))
+ gen8_ppgtt_notify_vgt(ppgtt, true);
+
return 0;
free_scratch:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b2ac37..80d424b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -136,6 +136,7 @@
#include drm/i915_drm.h
#include i915_drv.h
#include intel_mocs.h
+#include i915_vgpu.h
#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
@@ -2122,6 +2123,22 @@ make_rpcs(struct drm_device *dev)
return rpcs;
}
+static void intel_lr_context_notify_vgt(struct intel_context *ctx,
+ struct intel_engine_cs *ring,
+ int msg)
+{
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u64 tmp = intel_lr_context_descriptor(ctx, ring);
+
+ I915_WRITE(vgtif_reg(execlist_context_descriptor_lo),
+ tmp 0x);
+ I915_WRITE(vgtif_reg(execlist_context_descriptor_hi),
+ tmp 32);
+
+ I915_WRITE(vgtif_reg(g2v_notify), msg);
+}
+
static int
populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object
*ctx_obj,
struct intel_engine_cs *ring, struct intel_ringbuffer
*ringbuf)
@@ -2282,6 +2299,10 @@ void intel_lr_context_free(struct intel_context *ctx)
ctx-engine[i].ringbuf;
struct intel_engine_cs *ring = ringbuf-ring;
+ if (intel_vgpu_active(ringbuf-ring-dev))
+ intel_lr_context_notify_vgt(ctx, ring,
+ VGT_G2V_EXECLIST_CONTEXT_DESTROY);
+
if ((ctx == ring-default_context) ||
(intel_vgpu_active(ring-dev))) {
intel_unpin_ringbuffer_obj(ringbuf);
@@ -2439,6 +2460,10 @@ int intel_lr_context_deferred_create(struct
intel_context *ctx,
ctx-engine[ring-id].ringbuf
