Re: [Intel-gfx] [RFC DP-typeC 0/2] Support USB typeC based DP on BXT

[Jani Nikula]

On Tue, 15 Sep 2015, Durgadoss R  wrote:
> This is an RFC series to start the review/discussion on approach
> to support USB type C based DP panel.
>
> To support USB type C alternate DP mode, the display driver needs to
> know the number of lanes required by the DP panel as well as number
> of lanes that can be supported by the type-C cable. Sometimes, the
> type-C cable may limit the bandwidth even if Panel can support
> more lanes.
>
> The goal is to find out the number of lanes which can be supported
> using a particular cable so that we can cap 'max_available_lanes'
> to that number during modeset.
>
> These two patches are based on 4.2-rc2 and tested only on
> a BXT A1 platform for now.
>
> Brief summary of the approach taken:
> ---
> 1.As soon as DP-hotplug is detected, driver starts link training
>   with highest number of lanes/bandwidth possible. If it fails,
>   driver retries link training with lane/2 for same bandwidth.
>   We continue this procedure until we find a working configuration
>   of lane/bandwidth values. This 'number of lanes' is then
>   set as the 'max_available_lanes', so that the following
>   intel_dp_compute_config() during modeset picks it up as
>   max_lane_count (instead of 4 always, from DPCD).

Would all of this work automatically if our link training sequence
followed the DP spec to the letter wrt degrading the link on failures?

BR,
Jani.


>
> 2.Since we do only link training on hotplug, only the port
>   and its PLLs are enabled/disabled without touching pipe/
>   planes etc.
>
> 3.For scenarios where we boot with DP connected (along with
>   an LFP like MIPI/eDP) we disable the crtc and then start
>   link training, since BIOS brings up DP. The crtc is
>   enabled back during subsequent modeset. This needs some
>   changes for latest -nightly branch since we do not have
>   intel_crtc_control() anymore.
>
> 4.Since we are doing the link training on hotplug (as
>   opposed to during modeset) we named the function
>   '{chv/bxt/*}_upfront_link_train'. We can also think
>   of a virtual func for this, inside intel_encoder.
>
> Durgadoss R (2):
>   drm/i915/dp: Make bxt_ddi_pll_select non-static
>   drm/i915/dp: Enable Upfront link training for type-C DP support
>
>  drivers/gpu/drm/i915/intel_ddi.c |  11 +--
>  drivers/gpu/drm/i915/intel_display.c | 130 
> +++
>  drivers/gpu/drm/i915/intel_dp.c  |  22 ++
>  drivers/gpu/drm/i915/intel_drv.h |   6 ++
>  4 files changed, 165 insertions(+), 4 deletions(-)
>
> -- 
> 1.9.1
>

-- 
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/bxt: work around HW context corruption due to coherency problem

[Chris Wilson]

On Tue, Sep 15, 2015 at 09:30:20PM +0300, Imre Deak wrote:
> The execlist context object is mapped with a CPU/GPU coherent mapping
> everywhere, but on BXT A stepping due to a HW issue the coherency is not
> guaranteed. To work around this flush the CPU cache after any change
> from the CPU to the context object. Note that this also includes any
> changes done by the VM core as opposed to the driver, when
> reading from backing store/bzeroing the pages.
> 
> I noticed this problem via a GPU hang, where IPEHR pointed to an invalid
> opcode value. I couldn't find this value on the ring but looking at the
> contents of the active context object it turned out to be a parameter
> dword of a bigger command there. The original command opcode itself
> was zeroed out, based on the above I assume due to a CPU writeback of
> the corresponding cacheline. When restoring the context the GPU would
> jump over the zeroed out opcode and hang when trying to execute the
> above parameter dword.
> 
> I could easily reproduce this by running igt/gem_render_copy_redux and
> gem_tiled_blits/basic in parallel, but I guess it could be triggered by
> anything involving frequent switches between two separate contexts. With
> this workaround I couldn't reproduce the problem.
> 
> Note that I also considered using set_pages_array_uc/wc on the context
> object but this wouldn't work with kmap_atomic which always returns a WB
> mapping, at least on HIGHMEM. The alternative would be keeping a UC/WC
> kernel mapping around whenever the context object is pinned, but this
> would be a bigger change. Since I'm not sure if there would be any
> benefit in using set_pages_array, I chose the simpler clflush method.

Nope. Fix execlists to use correct GEM domain management. From
experience the whole context object needs to be flushed if no longer
coherent.

Are you absolutely sure that you want to enable snooping on those pages
since that historically would be bogus? I would expect some strong
bspec reference saying that it is legal.
-Chris

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[Intel-gfx] [PATCH 4/4] drm/i915: Program vactive & hactive display size for both ports

[Gaurav K Singh]

Program the required mmio regs for hactive and vactive display size.

Signed-off-by: Gaurav K Singh 
---
 drivers/gpu/drm/i915/intel_display.c |   37 ++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ab9f06a..0285af9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7653,6 +7653,7 @@ static void intel_get_pipe_timings(struct intel_crtc 
*crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+   bool is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
uint32_t tmp;
 
tmp = I915_READ(HTOTAL(cpu_transcoder));
@@ -7681,6 +7682,25 @@ static void intel_get_pipe_timings(struct intel_crtc 
*crtc,
pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
}
 
+if (IS_BROXTON(dev) && is_dsi) {
+   struct intel_encoder *encoder;
+
+   for_each_encoder_on_crtc(dev, >base, encoder) {
+   struct intel_dsi *intel_dsi =
+   enc_to_intel_dsi(>base);
+   enum port port;
+
+   for_each_dsi_port(port, intel_dsi->ports) {
+   pipe_config->base.adjusted_mode.crtc_hdisplay =
+   
I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
+   pipe_config->base.adjusted_mode.crtc_vdisplay =
+   
I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
+   pipe_config->base.adjusted_mode.crtc_vtotal =
+   
I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
+   }
+   }
+   }
+
tmp = I915_READ(PIPESRC(crtc->pipe));
pipe_config->pipe_src_h = (tmp & 0x) + 1;
pipe_config->pipe_src_w = ((tmp >> 16) & 0x) + 1;
@@ -10569,6 +10589,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct 
drm_device *dev,
int vtot = I915_READ(VTOTAL(cpu_transcoder));
int vsync = I915_READ(VSYNC(cpu_transcoder));
enum pipe pipe = intel_crtc->pipe;
+   bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
 
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
@@ -10598,6 +10619,22 @@ struct drm_display_mode *intel_crtc_mode_get(struct 
drm_device *dev,
mode->vsync_start = (vsync & 0x) + 1;
mode->vsync_end = ((vsync & 0x) >> 16) + 1;
 
+   if (IS_BROXTON(dev) && is_dsi) {
+   struct intel_encoder *encoder;
+
+   for_each_encoder_on_crtc(dev, _crtc->base, encoder) {
+   struct intel_dsi *intel_dsi =
+   
enc_to_intel_dsi(>base);
+   enum port port;
+
+   for_each_dsi_port(port, intel_dsi->ports) {
+   mode->vtotal = 
I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
+   mode->hdisplay = 
I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
+   mode->vdisplay = 
I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
+   }
+   }
+   }
+
drm_mode_set_name(mode);
 
return mode;
-- 
1.7.9.5

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[Intel-gfx] [PATCH 2/4] drm/i915: Use adjusted mode clk for calculating DSI clk

[Gaurav K Singh]

Earlier, pclk was getting used for calculating DSI clk. For single link
MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
halved, DSI clk will have a wrong value.

Signed-off-by: Gaurav K Singh 
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index bf0f622..a53ccc9 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -468,12 +468,14 @@ static void bxt_dsi_program_clocks(struct drm_device 
*dev, enum port port)
 static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+   struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+   struct drm_display_mode *mode = _crtc->config->base.adjusted_mode;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
u8 dsi_ratio;
u32 dsi_clk;
u32 val;
 
-   dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
+   dsi_clk = dsi_clk_from_pclk(mode->clock, intel_dsi->pixel_format,
intel_dsi->lane_count);
 
/*
-- 
1.7.9.5

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[Intel-gfx] [PATCH 1/4] drm/i915: Enable dual link mode in BXT

[Gaurav K Singh]

Enable BIT 0 of MIPI Port Ctrl reg to enable dual link mode.

Signed-off-by: Deepak M 
Signed-off-by: Gaurav K Singh 
---
 drivers/gpu/drm/i915/i915_reg.h  |7 ---
 drivers/gpu/drm/i915/intel_dsi.c |9 ++---
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1ea4686..4e5c0bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7581,17 +7581,17 @@ enum skl_disp_power_wells {
 /* BXT MIPI mode configure */
 #define  _BXT_MIPIA_TRANS_HACTIVE  0x6B0F8
 #define  _BXT_MIPIC_TRANS_HACTIVE  0x6B8F8
-#define  BXT_MIPI_TRANS_HACTIVE(tc)_MIPI_PORT(tc, \
+#define  BXT_MIPI_TRANS_HACTIVE(port)  _MIPI_PORT(port, \
_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
 
 #define  _BXT_MIPIA_TRANS_VACTIVE  0x6B0FC
 #define  _BXT_MIPIC_TRANS_VACTIVE  0x6B8FC
-#define  BXT_MIPI_TRANS_VACTIVE(tc)_MIPI_PORT(tc, \
+#define  BXT_MIPI_TRANS_VACTIVE(port)  _MIPI_PORT(port, \
_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
 
 #define  _BXT_MIPIA_TRANS_VTOTAL   0x6B100
 #define  _BXT_MIPIC_TRANS_VTOTAL   0x6B900
-#define  BXT_MIPI_TRANS_VTOTAL(tc) _MIPI_PORT(tc, \
+#define  BXT_MIPI_TRANS_VTOTAL(port)   _MIPI_PORT(port, \
_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
 
 #define BXT_DSI_PLL_CTL0x161000
@@ -7665,6 +7665,7 @@ enum skl_disp_power_wells {
 #define  LANE_CONFIGURATION_4LANE  (0 << 0)
 #define  LANE_CONFIGURATION_DUAL_LINK_A(1 << 0)
 #define  LANE_CONFIGURATION_DUAL_LINK_B(2 << 0)
+#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE   (1 << 0)
 
 #define _MIPIA_TEARING_CTRL(VLV_DISPLAY_BASE + 0x61194)
 #define _MIPIC_TEARING_CTRL(VLV_DISPLAY_BASE + 0x61704)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 2ccbda5..ec7e48b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -400,9 +400,12 @@ static void intel_dsi_port_enable(struct intel_encoder 
*encoder)
if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
temp |= (intel_dsi->dual_link - 1)
<< DUAL_LINK_MODE_SHIFT;
-   temp |= intel_crtc->pipe ?
-   LANE_CONFIGURATION_DUAL_LINK_B :
-   LANE_CONFIGURATION_DUAL_LINK_A;
+   if (IS_VALLEYVIEW(dev))
+   temp |= intel_crtc->pipe ?
+   LANE_CONFIGURATION_DUAL_LINK_B :
+   LANE_CONFIGURATION_DUAL_LINK_A;
+   else if (IS_BROXTON(dev))
+   temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
}
/* assert ip_tg_enable signal */
I915_WRITE(port_ctrl, temp | DPI_ENABLE);
-- 
1.7.9.5

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[Intel-gfx] [RFC PATCH] drm/i915: Consider SPLL as another shared pll.

[Maarten Lankhorst]

When diagnosing a unrelated bug for someone on irc, it would seem the hardware 
can
be brought up by the BIOS with the embedded displayport using the SPLL for 
spread spectrum.

Right now this is not handled well in i915, and it calculates the crtc needs to
be reprogrammed on the first modeset without SSC, but  the SPLL itself was kept
active. Fix this by exposing SPLL as a shared pll that will not be returned
by intel_get_shared_dpll; you have to know it exists to use it. ;-)

Cc: Emil Renner Berthing 
Signed-off-by: Maarten Lankhorst 
---
RFC because I haven't tested it with VGA, but it seems to work according to fix
the problem mentioned above.

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 81adf89b92f1..cacdac67d9ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -345,6 +345,8 @@ enum intel_dpll_id {
/* hsw/bdw */
DPLL_ID_WRPLL1 = 0,
DPLL_ID_WRPLL2 = 1,
+   DPLL_ID_SPLL = 2,
+
/* skl */
DPLL_ID_SKL_DPLL1 = 0,
DPLL_ID_SKL_DPLL2 = 1,
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index af5e43bef4a4..592d8fe9f991 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -138,18 +138,6 @@ static void hsw_crt_get_config(struct intel_encoder 
*encoder,
pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 }
 
-static void hsw_crt_pre_enable(struct intel_encoder *encoder)
-{
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-
-   WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");
-   I915_WRITE(SPLL_CTL,
-  SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC);
-   POSTING_READ(SPLL_CTL);
-   udelay(20);
-}
-
 /* Note: The caller is required to filter out dpms modes not supported by the
  * platform. */
 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
@@ -216,19 +204,6 @@ static void pch_post_disable_crt(struct intel_encoder 
*encoder)
intel_disable_crt(encoder);
 }
 
-static void hsw_crt_post_disable(struct intel_encoder *encoder)
-{
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   uint32_t val;
-
-   DRM_DEBUG_KMS("Disabling SPLL\n");
-   val = I915_READ(SPLL_CTL);
-   WARN_ON(!(val & SPLL_PLL_ENABLE));
-   I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
-   POSTING_READ(SPLL_CTL);
-}
-
 static void intel_enable_crt(struct intel_encoder *encoder)
 {
struct intel_crt *crt = intel_encoder_to_crt(encoder);
@@ -280,6 +255,8 @@ static bool intel_crt_compute_config(struct intel_encoder 
*encoder,
if (HAS_DDI(dev)) {
pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
pipe_config->port_clock = 135000 * 2;
+   pipe_config->dpll_hw_state.wrpll =
+   SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
}
 
return true;
@@ -861,8 +838,6 @@ void intel_crt_init(struct drm_device *dev)
if (HAS_DDI(dev)) {
crt->base.get_config = hsw_crt_get_config;
crt->base.get_hw_state = intel_ddi_get_hw_state;
-   crt->base.pre_enable = hsw_crt_pre_enable;
-   crt->base.post_disable = hsw_crt_post_disable;
} else {
crt->base.get_config = intel_crt_get_config;
crt->base.get_hw_state = intel_crt_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 61575f67a626..dabd903147fa 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1269,6 +1269,18 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
}
 
crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
+   } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
+   struct drm_atomic_state *state = crtc_state->base.state;
+   struct intel_shared_dpll_config *spll =
+   
_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
+
+   if (spll->crtc_mask &&
+   WARN_ON(spll->hw_state.wrpll != 
crtc_state->dpll_hw_state.wrpll))
+   return false;
+
+   crtc_state->shared_dpll = DPLL_ID_SPLL;
+   spll->hw_state.wrpll = crtc_state->dpll_hw_state.wrpll;
+   spll->crtc_mask |= 1 << intel_crtc->pipe;
}
 
return true;
@@ -2414,19 +2426,31 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder)
 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
   struct intel_shared_dpll *pll)
 {
-   I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
-   POSTING_READ(WRPLL_CTL(pll->id));
+ 

[Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in i915_gem_gtt.c

[Geliang Tang]

Fix the following 'make htmldocs' warnings:

  .//drivers/gpu/drm/i915/i915_gem_gtt.c:758: warning: No description found for 
parameter 'length'
  .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found for 
parameter 'length'
  .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found for 
parameter 'new_pds'
  .//drivers/gpu/drm/i915/i915_gem_gtt.c:758: warning: No description found for 
parameter 'length'
  .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found for 
parameter 'length'
  .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found for 
parameter 'new_pds'

Signed-off-by: Geliang Tang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 96054a5..c070a1f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -737,7 +737,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space 
*vm)
  * @ppgtt: Master ppgtt structure.
  * @pd:Page directory for this address range.
  * @start: Starting virtual address to begin allocations.
- * @length Size of the allocations.
+ * @length:Size of the allocations.
  * @new_pts:   Bitmap set by function with new allocations. Likely used by the
  * caller to free on error.
  *
@@ -792,8 +792,8 @@ unwind_out:
  * @ppgtt: Master ppgtt structure.
  * @pdp:   Page directory pointer for this address range.
  * @start: Starting virtual address to begin allocations.
- * @length Size of the allocations.
- * @new_pdsBitmap set by function with new allocations. Likely used by the
+ * @length:Size of the allocations.
+ * @new_pds:   Bitmap set by function with new allocations. Likely used by the
  * caller to free on error.
  *
  * Allocate the required number of page directories starting at the pde index 
of
-- 
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[Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in intel_lrc.c

[Geliang Tang]

Fix the following 'make htmldocs' warnings:

  .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: No description found for 
parameter 'req'
  .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: Excess function parameter 
'request' description in 'intel_logical_ring_begin'
  .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: Excess function parameter 
'ctx' description in 'intel_logical_ring_begin'

Signed-off-by: Geliang Tang 
---
 drivers/gpu/drm/i915/intel_lrc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 72e0edd..963992a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -765,8 +765,7 @@ static int logical_ring_prepare(struct drm_i915_gem_request 
*req, int bytes)
 /**
  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some 
commands
  *
- * @request: The request to start some new work for
- * @ctx: Logical ring context whose ringbuffer is being prepared.
+ * @req: The request to start some new work for
  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
  *
  * The ringbuffer might not be ready to accept the commands right away (maybe 
it needs to
-- 
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[Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in intel_audio.c

[Geliang Tang]

Fix the following 'make htmldocs' warnings:

  .//drivers/gpu/drm/i915/intel_audio.c:439: warning: No description found for 
parameter 'intel_encoder'
  .//drivers/gpu/drm/i915/intel_audio.c:439: warning: Excess function parameter 
'encoder' description in 'intel_audio_codec_disable'
  .//drivers/gpu/drm/i915/intel_audio.c:439: warning: No description found for 
parameter 'intel_encoder'
  .//drivers/gpu/drm/i915/intel_audio.c:439: warning: Excess function parameter 
'encoder' description in 'intel_audio_codec_disable'

Signed-off-by: Geliang Tang 
---
 drivers/gpu/drm/i915/intel_audio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index f73de0b..e35997e 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -430,7 +430,7 @@ void intel_audio_codec_enable(struct intel_encoder 
*intel_encoder)
 
 /**
  * intel_audio_codec_disable - Disable the audio codec for HD audio
- * @encoder: encoder on which to disable audio
+ * @intel_encoder: encoder on which to disable audio
  *
  * The disable sequences must be performed before disabling the transcoder or
  * port.
-- 
1.9.1


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[Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in i915_gem.c

[Geliang Tang]

Fix the following 'make htmldocs' warnings:

  .//drivers/gpu/drm/i915/i915_gem.c:1729: warning: No description found for 
parameter 'vma'
  .//drivers/gpu/drm/i915/i915_gem.c:1729: warning: No description found for 
parameter 'vmf'

  .//drivers/gpu/drm/i915/i915_gem.c:4962: warning: No description found for 
parameter 'old'
  .//drivers/gpu/drm/i915/i915_gem.c:4962: warning: No description found for 
parameter 'new'
  .//drivers/gpu/drm/i915/i915_gem.c:4962: warning: No description found for 
parameter 'frontbuffer_bits'

Signed-off-by: Geliang Tang 
---
 drivers/gpu/drm/i915/i915_gem.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4d631a9..a96f97c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1711,8 +1711,8 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 
 /**
  * i915_gem_fault - fault a page into the GTT
- * vma: VMA in question
- * vmf: fault info
+ * @vma: VMA in question
+ * @vmf: fault info
  *
  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
  * from userspace.  The fault handler takes care of binding the object to
@@ -4949,9 +4949,9 @@ int i915_gem_open(struct drm_device *dev, struct drm_file 
*file)
 
 /**
  * i915_gem_track_fb - update frontbuffer tracking
- * old: current GEM buffer for the frontbuffer slots
- * new: new GEM buffer for the frontbuffer slots
- * frontbuffer_bits: bitmask of frontbuffer slots
+ * @old: current GEM buffer for the frontbuffer slots
+ * @new: new GEM buffer for the frontbuffer slots
+ * @frontbuffer_bits: bitmask of frontbuffer slots
  *
  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing 
them
  * from @old and setting them in @new. Both @old and @new can be NULL.
-- 
1.9.1


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Re: [Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views

[Chris Wilson]

On Tue, Sep 15, 2015 at 07:05:12PM -0700, Vivek Kasireddy wrote:
> While pinning a fb object to the display plane, only install a fence
> if the object is using a normal view. This corresponds with the
> behavior found in i915_gem_object_do_pin() where the fencability
> criteria is determined only for objects with normal views.
> 
> Suggested-by: Tvrtko Ursulin 
> Cc: Chris Wilson 
> Cc: Tvrtko Ursulin 
> Signed-off-by: Vivek Kasireddy 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 52fb3f2..8b3e943 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2357,7 +2357,8 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
>* framebuffer compression.  For simplicity, we always install
>* a fence as the cost is not that onerous.
>*/
> - ret = i915_gem_object_get_fence(obj);
> + ret = view.type == I915_GGTT_VIEW_NORMAL ?
> + i915_gem_object_get_fence(obj) : 0;

ret = 0;
if (vma->map_and_fenceable)
ret = i915_gem_object_get_fence(obj);

is how I wrote it in my patch. One day that will become
i915_vma_get_fence().
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 0/4] DSI Dual link enabling on BXT

[Gaurav K Singh]

Hi,

These patches enable DSI dual link mode on BXT boards. These set of patches
build on top of the floated DSI Video mode patches on BXT (Uma's patches).

Regards
Gaurav

Gaurav K Singh (4):
  drm/i915: Enable dual link mode in BXT
  drm/i915: Use adjusted mode clk for calculating DSI clk
  drm/i915: Execute RESET sequence before device ready
  drm/i915: Program vactive & hactive display size for both ports

 drivers/gpu/drm/i915/i915_reg.h|7 +++---
 drivers/gpu/drm/i915/intel_display.c   |   37 
 drivers/gpu/drm/i915/intel_dsi.c   |   11 ++---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++
 drivers/gpu/drm/i915/intel_dsi_pll.c   |4 ++-
 include/drm/drm_panel.h|9 +++
 6 files changed, 76 insertions(+), 7 deletions(-)

-- 
1.7.9.5

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[Intel-gfx] [PATCH 3/4] drm/i915: Execute RESET sequence before device ready

[Gaurav K Singh]

Before setting the MIPI device to ready state, execute the RESET
sequence.

Signed-off-by: Gaurav K Singh 
---
 drivers/gpu/drm/i915/intel_dsi.c   |2 ++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++
 include/drm/drm_panel.h|9 +
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index ec7e48b..d7e2118 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -497,6 +497,8 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder)
I915_WRITE(DSPCLK_GATE_D, tmp);
}
 
+   drm_panel_reset(intel_dsi->panel);
+
/* put device in ready state */
intel_dsi_device_ready(encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a5e99ac..feeca59 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -292,6 +292,20 @@ static void generic_exec_sequence(struct intel_dsi 
*intel_dsi, const u8 *data)
}
 }
 
+static int vbt_panel_reset(struct drm_panel *panel)
+{
+   struct vbt_panel *vbt_panel = to_vbt_panel(panel);
+   struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   const u8 *sequence;
+
+   sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
+   generic_exec_sequence(intel_dsi, sequence);
+
+   return 0;
+}
+
 static int vbt_panel_prepare(struct drm_panel *panel)
 {
struct vbt_panel *vbt_panel = to_vbt_panel(panel);
@@ -377,6 +391,7 @@ static const struct drm_panel_funcs vbt_panel_funcs = {
.disable = vbt_panel_disable,
.unprepare = vbt_panel_unprepare,
.prepare = vbt_panel_prepare,
+   .reset = vbt_panel_reset,
.enable = vbt_panel_enable,
.get_modes = vbt_panel_get_modes,
 };
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 13ff44b..1e2432e 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -68,6 +68,7 @@ struct display_timing;
 struct drm_panel_funcs {
int (*disable)(struct drm_panel *panel);
int (*unprepare)(struct drm_panel *panel);
+   int (*reset)(struct drm_panel *panel);
int (*prepare)(struct drm_panel *panel);
int (*enable)(struct drm_panel *panel);
int (*get_modes)(struct drm_panel *panel);
@@ -101,6 +102,14 @@ static inline int drm_panel_disable(struct drm_panel 
*panel)
return panel ? -ENOSYS : -EINVAL;
 }
 
+static inline int drm_panel_reset(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->prepare)
+   return panel->funcs->reset(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
 static inline int drm_panel_prepare(struct drm_panel *panel)
 {
if (panel && panel->funcs && panel->funcs->prepare)
-- 
1.7.9.5

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[Intel-gfx] [PATCH v3 2/2] drm/i915/gtt: Avoid using addresses in non-canonical form.

[Michał Winiarski]

According to bspec, some parts of HW expect the addresses to be in
a canonical form where bits [63:48] == [47].
If we're using 32b addressing, we never need to handle such high
addresses, but since we've recently added 48b address space support,
lets satisfy the HW by converting the address prior to
alloc/insert/clear.

v2: Commit msg update,
move WARN to gen8_alloc_va_range,
also convert to canonical in insert_entries.
v3: Also convert for !48b (causes no harm, improves code stucture),
update wrap comment.

Cc: Chris Wilson 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 20 
 drivers/gpu/drm/i915/i915_gem_gtt.h |  5 +
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 01f3521..feb499d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -759,6 +759,7 @@ static void gen8_ppgtt_clear_range(struct 
i915_address_space *vm,
container_of(vm, struct i915_hw_ppgtt, base);
gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 I915_CACHE_LLC, use_scratch);
+   start = gen8_canonical_addr(start);
 
if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
gen8_ppgtt_clear_pte_range(vm, >pdp, start, length,
@@ -827,6 +828,7 @@ static void gen8_ppgtt_insert_entries(struct 
i915_address_space *vm,
struct sg_page_iter sg_iter;
 
__sg_page_iter_start(_iter, pages->sgl, sg_nents(pages->sgl), 0);
+   start = gen8_canonical_addr(start);
 
if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
gen8_ppgtt_insert_pte_entries(vm, >pdp, _iter, start,
@@ -1227,14 +1229,6 @@ static int gen8_alloc_va_range_3lvl(struct 
i915_address_space *vm,
uint32_t pdpes = I915_PDPES_PER_PDP(dev);
int ret;
 
-   /* Wrap is never okay since we can only represent 48b, and we don't
-* actually use the other side of the canonical address space.
-*/
-   if (WARN_ON(start + length < start))
-   return -ENODEV;
-
-   if (WARN_ON(start + length > vm->total))
-   return -ENODEV;
 
ret = alloc_gen8_temp_bitmaps(_page_dirs, _page_tables, pdpes);
if (ret)
@@ -1377,6 +1371,16 @@ static int gen8_alloc_va_range(struct i915_address_space 
*vm,
struct i915_hw_ppgtt *ppgtt =
container_of(vm, struct i915_hw_ppgtt, base);
 
+   /* Wrap is not okay since we're dealing with addresses that have not
+* been converted to canonical form yet */
+   if (WARN_ON(start + length < start))
+   return -ENODEV;
+
+   if (WARN_ON(start + length > vm->total))
+   return -ENODEV;
+
+   start = gen8_canonical_addr(start);
+
if (USES_FULL_48BIT_PPGTT(vm->dev))
return gen8_alloc_va_range_4lvl(vm, >pml4, start, 
length);
else
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8275007..9397387 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -503,6 +503,11 @@ static inline size_t gen8_pte_count(uint64_t address, 
uint64_t length)
return i915_pte_count(address, length, GEN8_PDE_SHIFT);
 }
 
+static inline uint64_t gen8_canonical_addr(uint64_t address)
+{
+   return ((int64_t)address << 16) >> 16;
+}
+
 static inline dma_addr_t
 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
 {
-- 
2.4.3

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[Intel-gfx] [PATCH v3 1/2] drm/i915/gtt: Do not initialize drm_mm twice.

[Michał Winiarski]

It would be initialized just moments later by i915_init_vm.

v2: Commit msg update,
s/i915_init_vm/i915_address_space_init, move to i915_gem_gtt.c,
init address_space during i915_gem_setup_global_gtt for ggtt.
v3: Do not init global_link - we are adding it to vm_list moments later,
make i915_address_space_init static, use OOP style parameter order.

Cc: Chris Wilson 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.h |  2 --
 drivers/gpu/drm/i915/i915_gem.c | 14 --
 drivers/gpu/drm/i915/i915_gem_gtt.c | 26 ++
 3 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3bf8a9b..039227d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2804,8 +2804,6 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct 
drm_device *dev,
  size_t size);
 struct drm_i915_gem_object *i915_gem_object_create_from_data(
struct drm_device *dev, const void *data, size_t size);
-void i915_init_vm(struct drm_i915_private *dev_priv,
- struct i915_address_space *vm);
 void i915_gem_free_object(struct drm_gem_object *obj);
 void i915_gem_vma_destroy(struct i915_vma *vma);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cb0df7e..4811f8a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4844,18 +4844,6 @@ init_ring_lists(struct intel_engine_cs *ring)
INIT_LIST_HEAD(>request_list);
 }
 
-void i915_init_vm(struct drm_i915_private *dev_priv,
- struct i915_address_space *vm)
-{
-   if (!i915_is_ggtt(vm))
-   drm_mm_init(>mm, vm->start, vm->total);
-   vm->dev = dev_priv->dev;
-   INIT_LIST_HEAD(>active_list);
-   INIT_LIST_HEAD(>inactive_list);
-   INIT_LIST_HEAD(>global_link);
-   list_add_tail(>global_link, _priv->vm_list);
-}
-
 void
 i915_gem_load(struct drm_device *dev)
 {
@@ -4879,8 +4867,6 @@ i915_gem_load(struct drm_device *dev)
  NULL);
 
INIT_LIST_HEAD(_priv->vm_list);
-   i915_init_vm(dev_priv, _priv->gtt.base);
-
INIT_LIST_HEAD(_priv->context_list);
INIT_LIST_HEAD(_priv->mm.unbound_list);
INIT_LIST_HEAD(_priv->mm.bound_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8786281..01f3521 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2121,6 +2121,16 @@ static int __hw_ppgtt_init(struct drm_device *dev, 
struct i915_hw_ppgtt *ppgtt)
return gen8_ppgtt_init(ppgtt);
 }
 
+static void i915_address_space_init(struct i915_address_space *vm,
+   struct drm_i915_private *dev_priv)
+{
+   drm_mm_init(>mm, vm->start, vm->total);
+   vm->dev = dev_priv->dev;
+   INIT_LIST_HEAD(>active_list);
+   INIT_LIST_HEAD(>inactive_list);
+   list_add_tail(>global_link, _priv->vm_list);
+}
+
 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2129,9 +2139,7 @@ int i915_ppgtt_init(struct drm_device *dev, struct 
i915_hw_ppgtt *ppgtt)
ret = __hw_ppgtt_init(dev, ppgtt);
if (ret == 0) {
kref_init(>ref);
-   drm_mm_init(>base.mm, ppgtt->base.start,
-   ppgtt->base.total);
-   i915_init_vm(dev_priv, >base);
+   i915_address_space_init(>base, dev_priv);
}
 
return ret;
@@ -2618,11 +2626,13 @@ static int i915_gem_setup_global_gtt(struct drm_device 
*dev,
 
BUG_ON(mappable_end > end);
 
-   /* Subtract the guard page ... */
-   drm_mm_init(_vm->mm, start, end - start - PAGE_SIZE);
+   ggtt_vm->start = start;
 
-   dev_priv->gtt.base.start = start;
-   dev_priv->gtt.base.total = end - start;
+   /* Subtract the guard page before address space initialization to
+* shrink the range used by drm_mm */
+   ggtt_vm->total = end - start - PAGE_SIZE;
+   i915_address_space_init(ggtt_vm, dev_priv);
+   ggtt_vm->total += PAGE_SIZE;
 
if (intel_vgpu_active(dev)) {
ret = intel_vgt_balloon(dev);
@@ -2631,7 +2641,7 @@ static int i915_gem_setup_global_gtt(struct drm_device 
*dev,
}
 
if (!HAS_LLC(dev))
-   dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
+   ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
 
/* Mark any preallocated objects as occupied */
list_for_each_entry(obj, _priv->mm.bound_list, global_list) {
-- 
2.4.3

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Add support for stealing purgable stolen pages

[Ankitprasad Sharma]

On Tue, 2015-09-15 at 16:14 +0100, Tvrtko Ursulin wrote:
> On 09/15/2015 09:33 AM, ankitprasad.r.sha...@intel.com wrote:
> > From: Chris Wilson 
> >
> > If we run out of stolen memory when trying to allocate an object, see if
> > we can reap enough purgeable objects to free up enough contiguous free
> > space for the allocation. This is in principle very much like evicting
> > objects to free up enough contiguous space in the vma when binding
> > a new object - and you will be forgiven for thinking that the code looks
> > very similar.
> >
> > At the moment, we do not allow userspace to allocate objects in stolen,
> > so there is neither the memory pressure to trigger stolen eviction nor
> > any purgeable objects inside the stolen arena. However, this will change
> > in the near future, and so better management and defragmentation of
> > stolen memory will become a real issue.
> >
> > v2: Remember to remove the drm_mm_node.
> >
> > v3: Rebased to the latest drm-intel-nightly (Ankit)
> >
> > v4: corrected if-else braces format (Tvrtko/kerneldoc)
> >
> > v5: Rebased to the latest drm-intel-nightly (Ankit)
> > Added a seperate list to maintain purgable objects from stolen memory
> > region (Chris/Daniel)
> >
> > Testcase: igt/gem_stolen
> >
> > Signed-off-by: Chris Wilson 
> > Signed-off-by: Ankitprasad Sharma 
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c|   4 +-
> >   drivers/gpu/drm/i915/i915_drv.h|  17 +++-
> >   drivers/gpu/drm/i915/i915_gem.c|  16 +++
> >   drivers/gpu/drm/i915/i915_gem_stolen.c | 176 
> > -
> >   drivers/gpu/drm/i915/intel_pm.c|   4 +-
> >   5 files changed, 187 insertions(+), 30 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 7a28de5..0db8c47 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -179,7 +179,7 @@ describe_obj(struct seq_file *m, struct 
> > drm_i915_gem_object *obj)
> > seq_puts(m, ")");
> > }
> > if (obj->stolen)
> > -   seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
> > +   seq_printf(m, " (stolen: %08llx)", obj->stolen->base.start);
> > if (obj->pin_display || obj->fault_mappable) {
> > char s[3], *t = s;
> > if (obj->pin_display)
> > @@ -258,7 +258,7 @@ static int obj_rank_by_stolen(void *priv,
> > struct drm_i915_gem_object *b =
> > container_of(B, struct drm_i915_gem_object, obj_exec_link);
> >
> > -   return a->stolen->start - b->stolen->start;
> > +   return a->stolen->base.start - b->stolen->base.start;
> >   }
> >
> >   static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index e6ef083..37ee32d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -841,6 +841,12 @@ struct i915_ctx_hang_stats {
> > bool banned;
> >   };
> >
> > +struct i915_stolen_node {
> > +   struct drm_mm_node base;
> > +   struct list_head mm_link;
> > +   struct drm_i915_gem_object *obj;
> > +};
> > +
> >   /* This must match up with the value previously used for execbuf2.rsvd1. 
> > */
> >   #define DEFAULT_CONTEXT_HANDLE 0
> >
> > @@ -1268,6 +1274,13 @@ struct i915_gem_mm {
> >  */
> > struct list_head unbound_list;
> >
> > +   /**
> > +* List of stolen objects that have been marked as purgeable and
> > +* thus available for reaping if we need more space for a new
> > +* allocation. Ordered by time of marking purgeable.
> > +*/
> > +   struct list_head stolen_list;
> > +
> > /** Usable portion of the GTT for GEM */
> > unsigned long stolen_base; /* limited to low memory (32-bit) */
> >
> > @@ -2026,7 +2039,7 @@ struct drm_i915_gem_object {
> > struct list_head vma_list;
> >
> > /** Stolen memory for this object, instead of being backed by shmem. */
> > -   struct drm_mm_node *stolen;
> > +   struct i915_stolen_node *stolen;
> > struct list_head global_list;
> >
> > struct list_head ring_list[I915_NUM_RINGS];
> > @@ -2034,6 +2047,7 @@ struct drm_i915_gem_object {
> > struct list_head obj_exec_link;
> >
> > struct list_head batch_pool_link;
> > +   struct list_head tmp_link;
> >
> > /**
> >  * This is set if the object is on the active lists (has pending
> > @@ -2150,6 +2164,7 @@ struct drm_i915_gem_object {
> > };
> >   };
> >   #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
> > +#define I915_BO_IS_ACTIVE(__obj) (__obj->active)
> >
> >   void i915_gem_track_fb(struct drm_i915_gem_object *old,
> >struct drm_i915_gem_object *new,
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 6568a7f..85025b1 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ 

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/gtt: Avoid using addresses in non-canonical form.

[Chris Wilson]

On Wed, Sep 16, 2015 at 11:50:50AM +0200, Michał Winiarski wrote:
> According to bspec, some parts of HW expect the addresses to be in
> a canonical form where bits [63:48] == [47].
> If we're using 32b addressing, we never need to handle such high
> addresses, but since we've recently added 48b address space support,
> lets satisfy the HW by converting the address prior to
> alloc/insert/clear.
> 
> v2: Commit msg update,
> move WARN to gen8_alloc_va_range,
> also convert to canonical in insert_entries.
> v3: Also convert for !48b (causes no harm, improves code stucture),
> update wrap comment.
> 
> Cc: Chris Wilson 
> Cc: Michel Thierry 
> Cc: Mika Kuoppala 
> Signed-off-by: Michał Winiarski 

I didn't even complain about the surplus brackets :)
Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] Contribute to DRM

[Jani Nikula]

On Tue, 15 Sep 2015, Lucas Tanure  wrote:
> Hi,
>
> I would like to start to contribute to drm part of kernel. I tried a few
> things:
>
> - Compiled linux-next tree using C=1 (sparse) to find things to improve.
> But couldn't find any problem or issue.
> - I looked in "www.x.org/wiki/DRMJanitors/" for stuff to do, but seems that
> most of them are already done when I checked the code.
>
> - Compiled and run the linux-next tree to test the code. And for this I got
> the warning below.
> I tried to compile a few older versions of linux-next in order to find the
> offending commit. But I didn't succeed, many commits don't boot at all, and
> is difficult to get more information about the status of the warning for
> that version.

I think especially for getting started linux-next is too volatile. I'd
go for Linus' git master first. After that, I'd still recommend driver
specific trees rather than linux-next.

drm/i915 branches are at http://cgit.freedesktop.org/drm-intel

> So, I would like some tips about how to debug DRM code, how to test, how to
> get more information about issues.
> What I do is :
> - Compile and run
> - Restart to a good kernel
> - "journalctl --boot=-1"  to see if I got any warning on previous kernel
>
> Also, if any developer needs/wants some help and it's ok to guide a new guy
> in DRM code, I would like to get help about tasks to do, things to
> clean/improve.
> I'm reading https://www.kernel.org/doc/htmldocs/drm/ to start, and I have
> done a few courses from linux foundation.

It's pretty hard to give generic advise; what works for me doesn't
necessarily work for you. With that out of the way, try focusing on some
detail and figure out how it works. Or find an itch and scratch it,
maybe a bug you experience. Or a bug someone else has and you can
reproduce it (product "DRI" at https://bugs.freedesktop.org/, you'll
probably need to narrow the search down). Expand on related details,
etc.

Based on the warn you seem to have an Intel GPU, so you might find
https://01.org/linuxgraphics/documentation helful.

You might also get faster replies on IRC at #dri-devel and #intel-gfx on
freenode, as long as you don't bug people too much. ;)

HTH,
Jani.


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Re: [Intel-gfx] [RFC DP-typeC 0/2] Support USB typeC based DP on BXT

[R, Durgadoss]

Hi Jani,

>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Wednesday, September 16, 2015 3:18 PM
>To: R, Durgadoss; intel-gfx@lists.freedesktop.org
>Cc: R, Durgadoss
>Subject: Re: [RFC DP-typeC 0/2] Support USB typeC based DP on BXT
>
>On Tue, 15 Sep 2015, Durgadoss R  wrote:
>> This is an RFC series to start the review/discussion on approach
>> to support USB type C based DP panel.
>>
>> To support USB type C alternate DP mode, the display driver needs to
>> know the number of lanes required by the DP panel as well as number
>> of lanes that can be supported by the type-C cable. Sometimes, the
>> type-C cable may limit the bandwidth even if Panel can support
>> more lanes.
>>
>> The goal is to find out the number of lanes which can be supported
>> using a particular cable so that we can cap 'max_available_lanes'
>> to that number during modeset.
>>
>> These two patches are based on 4.2-rc2 and tested only on
>> a BXT A1 platform for now.
>>
>> Brief summary of the approach taken:
>> ---
>> 1.As soon as DP-hotplug is detected, driver starts link training
>>   with highest number of lanes/bandwidth possible. If it fails,
>>   driver retries link training with lane/2 for same bandwidth.
>>   We continue this procedure until we find a working configuration
>>   of lane/bandwidth values. This 'number of lanes' is then
>>   set as the 'max_available_lanes', so that the following
>>   intel_dp_compute_config() during modeset picks it up as
>>   max_lane_count (instead of 4 always, from DPCD).
>
>Would all of this work automatically if our link training sequence
>followed the DP spec to the letter wrt degrading the link on failures?

That is one part of it.

Our intention is also to filter out the modes that cannot be set
with 'max_available_lanes' through connector->mode_valid
callback, which uses these variables. Otherwise, we risk failing
a modeset that uses higher resolutions than possible.

Sorry, I should have also added this as part of the commit message.

Thanks,
Durga

>
>BR,
>Jani.
>
>
>>
>> 2.Since we do only link training on hotplug, only the port
>>   and its PLLs are enabled/disabled without touching pipe/
>>   planes etc.
>>
>> 3.For scenarios where we boot with DP connected (along with
>>   an LFP like MIPI/eDP) we disable the crtc and then start
>>   link training, since BIOS brings up DP. The crtc is
>>   enabled back during subsequent modeset. This needs some
>>   changes for latest -nightly branch since we do not have
>>   intel_crtc_control() anymore.
>>
>> 4.Since we are doing the link training on hotplug (as
>>   opposed to during modeset) we named the function
>>   '{chv/bxt/*}_upfront_link_train'. We can also think
>>   of a virtual func for this, inside intel_encoder.
>>
>> Durgadoss R (2):
>>   drm/i915/dp: Make bxt_ddi_pll_select non-static
>>   drm/i915/dp: Enable Upfront link training for type-C DP support
>>
>>  drivers/gpu/drm/i915/intel_ddi.c |  11 +--
>>  drivers/gpu/drm/i915/intel_display.c | 130 
>> +++
>>  drivers/gpu/drm/i915/intel_dp.c  |  22 ++
>>  drivers/gpu/drm/i915/intel_drv.h |   6 ++
>>  4 files changed, 165 insertions(+), 4 deletions(-)
>>
>> --
>> 1.9.1
>>
>
>--
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Protect MST retraining with connection_mutex

[Maarten Lankhorst]

Hey,

Op 03-09-15 om 14:11 schreef Ville Syrjälä:
> On Thu, Aug 27, 2015 at 06:36:48PM +0300, ville.syrj...@linux.intel.com wrote:
>> From: Ville Syrjälä 
>>
>> Grab the connection_mutex around MSR link retraining to protect it
>> against a concurrent modeset. We already do the same for SST.
>>
>> DP hpd_pulse can still otherwise race against modeset and ->detect(), so
>> it's not clear what will happen when both want to scribble into eg.
>> intel_dp->dpcd[] at the same time. But sorting it all out requires way
>> more thought than I'm willing to expend now.
> Actually I suppose this might not work out so well after all. I suppose
> MST depends on short HPDs during modeset due to the sideband stuff.
>
> So if we want to grab modeset locks for retraining, I suppose we'd
> need to move the retraining to happen from .hot_plug() which gets run
> from the other hotplug work, and so wouldn't interfere with sideband.
>
I think it would be better to have a per encoder mutex. In the future we may 
want to run modeset
disable/enable async, in which case it may not hold the connection_mutex.

If we do decide on a separate mutex then it would also be useful to also think 
about how to
protect intel_mst_*(dis,en)able_dp. :)

~Maarten
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Flatten the mst suspend/resume functions a bit

[Maarten Lankhorst]

Hey,

Op 27-08-15 om 17:36 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä 
>
> I'm not a fan of deeply nested ifs. Just pull most of the conditions
> into a single place to flatten things a bit.
I like flat..

Reviewed-by: Maarten Lankhorst 
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/bxt: work around HW context corruption due to coherency problem

[Imre Deak]

On ke, 2015-09-16 at 09:17 +0100, Chris Wilson wrote:
> On Tue, Sep 15, 2015 at 09:30:20PM +0300, Imre Deak wrote:
> > The execlist context object is mapped with a CPU/GPU coherent mapping
> > everywhere, but on BXT A stepping due to a HW issue the coherency is not
> > guaranteed. To work around this flush the CPU cache after any change
> > from the CPU to the context object. Note that this also includes any
> > changes done by the VM core as opposed to the driver, when
> > reading from backing store/bzeroing the pages.
> > 
> > I noticed this problem via a GPU hang, where IPEHR pointed to an invalid
> > opcode value. I couldn't find this value on the ring but looking at the
> > contents of the active context object it turned out to be a parameter
> > dword of a bigger command there. The original command opcode itself
> > was zeroed out, based on the above I assume due to a CPU writeback of
> > the corresponding cacheline. When restoring the context the GPU would
> > jump over the zeroed out opcode and hang when trying to execute the
> > above parameter dword.
> > 
> > I could easily reproduce this by running igt/gem_render_copy_redux and
> > gem_tiled_blits/basic in parallel, but I guess it could be triggered by
> > anything involving frequent switches between two separate contexts. With
> > this workaround I couldn't reproduce the problem.
> > 
> > Note that I also considered using set_pages_array_uc/wc on the context
> > object but this wouldn't work with kmap_atomic which always returns a WB
> > mapping, at least on HIGHMEM. The alternative would be keeping a UC/WC
> > kernel mapping around whenever the context object is pinned, but this
> > would be a bigger change. Since I'm not sure if there would be any
> > benefit in using set_pages_array, I chose the simpler clflush method.
> 
> Nope. Fix execlists to use correct GEM domain management.

Not sure what you mean. In both execlist and ringbuffer mode the context
object is already put to the CPU domain, so there is no difference
there. We don't touch the context in ringbuffer mode, so there is
nothing else to do there. In execlist mode we do and so - after this
change - call i915_gem_clflush_object() which is what is done for all
other GEM objects too. This one in turn will do the proper thing based
on the given platform and the object's cache level, which is also
correct after patch 1/2.

> From experience the whole context object needs to be flushed if no longer
> coherent.

We know it's no longer coherent when we first pin it in
intel_lr_context_do_pin() so we need to flush there the whole object.
(This is after we initialized it in populate_lr_context() and/or
possibly read it back from backing storage.) Afterwards we know it won't
get accessed from the CPU until we submit it (execlist_update_context),
where we only update the ring tail/start and PDP values in it, so there
it's enough to flush these particular addresses.

Btw, I noticed now that I missed the GUC path, where there is a similar
update before submission in lr_context_update().

> Are you absolutely sure that you want to enable snooping on those pages
> since that historically would be bogus? I would expect some strong
> bspec reference saying that it is legal.

Well I don't want it, but this is what we do already anyway. On CHV and
BXT the GTT PTE PAT index is ignored and so all entries map to PAT index
0. We set up this PAT index as snooped, since we also have the HWSP in
GTT. We could go around this by mapping the HWSP also non-snooped and do
uncached seqno reads or as Ville pointed out, moving the HWSP to PPGTT.
In both cases we could set PAT index 0 as not snooped.

In either case I think the above is a separate issue that could be
addressed as a follow-up. Even if we map the context object unsnooped
we'll need the logic to flush it.

--Imre

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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Enable dual link mode in BXT

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:38PM +0530, Gaurav K Singh wrote:
> Enable BIT 0 of MIPI Port Ctrl reg to enable dual link mode.
> 
> Signed-off-by: Deepak M 
> Signed-off-by: Gaurav K Singh 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |7 ---
>  drivers/gpu/drm/i915/intel_dsi.c |9 ++---
>  2 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1ea4686..4e5c0bb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7581,17 +7581,17 @@ enum skl_disp_power_wells {
>  /* BXT MIPI mode configure */
>  #define  _BXT_MIPIA_TRANS_HACTIVE0x6B0F8
>  #define  _BXT_MIPIC_TRANS_HACTIVE0x6B8F8
> -#define  BXT_MIPI_TRANS_HACTIVE(tc)  _MIPI_PORT(tc, \
> +#define  BXT_MIPI_TRANS_HACTIVE(port)_MIPI_PORT(port, \
>   _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
>  
>  #define  _BXT_MIPIA_TRANS_VACTIVE0x6B0FC
>  #define  _BXT_MIPIC_TRANS_VACTIVE0x6B8FC
> -#define  BXT_MIPI_TRANS_VACTIVE(tc)  _MIPI_PORT(tc, \
> +#define  BXT_MIPI_TRANS_VACTIVE(port)_MIPI_PORT(port, \
>   _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
>  
>  #define  _BXT_MIPIA_TRANS_VTOTAL 0x6B100
>  #define  _BXT_MIPIC_TRANS_VTOTAL 0x6B900
> -#define  BXT_MIPI_TRANS_VTOTAL(tc)   _MIPI_PORT(tc, \
> +#define  BXT_MIPI_TRANS_VTOTAL(port) _MIPI_PORT(port, \
>   _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
>  
>  #define BXT_DSI_PLL_CTL  0x161000
> @@ -7665,6 +7665,7 @@ enum skl_disp_power_wells {
>  #define  LANE_CONFIGURATION_4LANE(0 << 0)
>  #define  LANE_CONFIGURATION_DUAL_LINK_A  (1 << 0)
>  #define  LANE_CONFIGURATION_DUAL_LINK_B  (2 << 0)
> +#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE (1 << 0)
>  
>  #define _MIPIA_TEARING_CTRL  (VLV_DISPLAY_BASE + 0x61194)
>  #define _MIPIC_TEARING_CTRL  (VLV_DISPLAY_BASE + 0x61704)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 2ccbda5..ec7e48b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -400,9 +400,12 @@ static void intel_dsi_port_enable(struct intel_encoder 
> *encoder)
>   if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
>   temp |= (intel_dsi->dual_link - 1)
>   << DUAL_LINK_MODE_SHIFT;
> - temp |= intel_crtc->pipe ?
> - LANE_CONFIGURATION_DUAL_LINK_B :
> - LANE_CONFIGURATION_DUAL_LINK_A;
> + if (IS_VALLEYVIEW(dev))
> + temp |= intel_crtc->pipe ?
> + LANE_CONFIGURATION_DUAL_LINK_B :
> + LANE_CONFIGURATION_DUAL_LINK_A;
> + else if (IS_BROXTON(dev))
> + temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
>   }
>   /* assert ip_tg_enable signal */
>   I915_WRITE(port_ctrl, temp | DPI_ENABLE);
> -- 
> 1.7.9.5
> 
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Re: [Intel-gfx] [PATCH 0/4] DSI Dual link enabling on BXT

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:37PM +0530, Gaurav K Singh wrote:
> Hi,
> 
> These patches enable DSI dual link mode on BXT boards. These set of patches
> build on top of the floated DSI Video mode patches on BXT (Uma's patches).

BTW I posted a few DSI related patch. Maybe you can take a look?

http://lists.freedesktop.org/archives/intel-gfx/2015-September/075097.html
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075568.html

> 
> Regards
> Gaurav
> 
> Gaurav K Singh (4):
>   drm/i915: Enable dual link mode in BXT
>   drm/i915: Use adjusted mode clk for calculating DSI clk
>   drm/i915: Execute RESET sequence before device ready
>   drm/i915: Program vactive & hactive display size for both ports
> 
>  drivers/gpu/drm/i915/i915_reg.h|7 +++---
>  drivers/gpu/drm/i915/intel_display.c   |   37 
> 
>  drivers/gpu/drm/i915/intel_dsi.c   |   11 ++---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++
>  drivers/gpu/drm/i915/intel_dsi_pll.c   |4 ++-
>  include/drm/drm_panel.h|9 +++
>  6 files changed, 76 insertions(+), 7 deletions(-)
> 
> -- 
> 1.7.9.5
> 
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Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 03/11] drm/i915: Parsing VBT if size of VBT exceeds 6KB

[Jani Nikula]

On Thu, 10 Sep 2015, Deepak M  wrote:
> Currently the iomap for VBT works only if the size of the
> VBT is less than 6KB, but if the size of the VBT exceeds
> 6KB than the physical address and the size of the VBT to
> be iomapped is specified in the mailbox3 and is iomapped
> accordingly.
>
> v2: - Moving the validate_vbt to opregion file (Jani)
> - Fix the i915_opregion() in debugfs (Jani)
>
> Signed-off-by: Deepak M 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c   |   24 ++-
>  drivers/gpu/drm/i915/i915_drv.h   |4 +
>  drivers/gpu/drm/i915/intel_bios.c |   49 +-
>  drivers/gpu/drm/i915/intel_opregion.c |  279 
> +
>  drivers/gpu/drm/i915/intel_opregion.h |  230 +++

Why are you adding this file? I think it's better to have all of this in
the .c file so that nobody will have any ideas about accessing the data
outside of intel_opregion.c.

BR,
Jani.

>  5 files changed, 329 insertions(+), 257 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_opregion.h
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 41629fa..5534aa2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -26,6 +26,8 @@
>   *
>   */
>  
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -39,6 +41,7 @@
>  #include "intel_ringbuffer.h"
>  #include 
>  #include "i915_drv.h"
> +#include "intel_opregion.h"
>  
>  enum {
>   ACTIVE_LIST,
> @@ -1832,7 +1835,7 @@ static int i915_opregion(struct seq_file *m, void 
> *unused)
>   struct drm_device *dev = node->minor->dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   struct intel_opregion *opregion = _priv->opregion;
> - void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
> + void *data = kmalloc(OPREGION_VBT_OFFSET, GFP_KERNEL);
>   int ret;
>  
>   if (data == NULL)
> @@ -1843,12 +1846,25 @@ static int i915_opregion(struct seq_file *m, void 
> *unused)
>   goto out;
>  
>   if (opregion->header) {
> - memcpy_fromio(data, opregion->header, OPREGION_SIZE);
> - seq_write(m, data, OPREGION_SIZE);
> + memcpy_fromio(data, opregion->header, OPREGION_VBT_OFFSET);
> + seq_write(m, data, OPREGION_VBT_OFFSET);
> + kfree(data);
> + if (opregion->asle->rvda) {
> + data = kmalloc(opregion->asle->rvds, GFP_KERNEL);
> + memcpy_fromio(data,
> + (const void __iomem *) opregion->asle->rvda,
> + opregion->asle->rvds);
> + seq_write(m, data, opregion->asle->rvds);
> + } else {
> + data = kmalloc(OPREGION_SIZE - OPREGION_VBT_OFFSET,
> + GFP_KERNEL);
> + memcpy_fromio(data, opregion->vbt,
> + OPREGION_SIZE - OPREGION_VBT_OFFSET);
> + seq_write(m, data, OPREGION_SIZE - OPREGION_VBT_OFFSET);
> + }
>   }
>  
>   mutex_unlock(>struct_mutex);
> -
>  out:
>   kfree(data);
>   return 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1287007..507d57a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1780,6 +1780,7 @@ struct drm_i915_private {
>   struct i915_hotplug hotplug;
>   struct i915_fbc fbc;
>   struct i915_drrs drrs;
> + const struct bdb_header *bdb_start;
>   struct intel_opregion opregion;
>   struct intel_vbt_data vbt;
>  
> @@ -3306,6 +3307,9 @@ intel_opregion_notify_adapter(struct drm_device *dev, 
> pci_power_t state)
>  }
>  #endif
>  
> +const struct bdb_header *validate_vbt(const void __iomem *_vbt,
> + size_t size, const char *source);
> +
>  /* intel_acpi.c */
>  #ifdef CONFIG_ACPI
>  extern void intel_register_dsm_handler(void);
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index 0bf0942..1932a86 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1227,49 +1227,6 @@ static const struct dmi_system_id 
> intel_no_opregion_vbt[] = {
>   { }
>  };
>  
> -static const struct bdb_header *validate_vbt(const void __iomem *_base,
> -  size_t size,
> -  const void __iomem *_vbt,
> -  const char *source)
> -{
> - /*
> -  * This is the one place where we explicitly discard the address space
> -  * (__iomem) of the BIOS/VBT. (And this will cause a sparse complaint.)
> -  * From now on everything is based on 'base', and treated as regular
> -  * memory.
> -  */
> - const void *base = (const void *) _base;

Re: [Intel-gfx] [PATCH 02/11] drm: Move timestamping constants into drm_vblank_crtc

[Maarten Lankhorst]

Op 14-09-15 om 21:43 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä 
>
> Collect the timestamping constants alongside the rest of the relevant
> stuff under drm_vblank_crtc.
>
> We can now get rid of the 'refcrtc' parameter to
> drm_calc_vbltimestamp_from_scanoutpos().
>
> Signed-off-by: Ville Syrjälä 
>
That's a much better place. :-)

I reviewed the whole series and didn't find anything obvious wrong, but didn't 
compile or runtime test it.

For the whole series:
Acked-by: Maarten Lankhorst 
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Re: [Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in i915_gem_gtt.c

[Jani Nikula]

On Tue, 15 Sep 2015, Geliang Tang  wrote:
> Fix the following 'make htmldocs' warnings:
>
>   .//drivers/gpu/drm/i915/i915_gem_gtt.c:758: warning: No description found 
> for parameter 'length'
>   .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found 
> for parameter 'length'
>   .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found 
> for parameter 'new_pds'
>   .//drivers/gpu/drm/i915/i915_gem_gtt.c:758: warning: No description found 
> for parameter 'length'
>   .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found 
> for parameter 'length'
>   .//drivers/gpu/drm/i915/i915_gem_gtt.c:818: warning: No description found 
> for parameter 'new_pds'

These are already fixed by

commit d4ec9da0e17cb6a86c0b76c5b254981601d25031
Author: Michel Thierry 
Date:   Thu Jul 30 11:02:03 2015 +0100

drm/i915/gen8: Abstract PDP usage

Thanks,
Jani.


>
> Signed-off-by: Geliang Tang 
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 96054a5..c070a1f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -737,7 +737,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space 
> *vm)
>   * @ppgtt:   Master ppgtt structure.
>   * @pd:  Page directory for this address range.
>   * @start:   Starting virtual address to begin allocations.
> - * @length   Size of the allocations.
> + * @length:  Size of the allocations.
>   * @new_pts: Bitmap set by function with new allocations. Likely used by the
>   *   caller to free on error.
>   *
> @@ -792,8 +792,8 @@ unwind_out:
>   * @ppgtt:   Master ppgtt structure.
>   * @pdp: Page directory pointer for this address range.
>   * @start:   Starting virtual address to begin allocations.
> - * @length   Size of the allocations.
> - * @new_pds  Bitmap set by function with new allocations. Likely used by the
> + * @length:  Size of the allocations.
> + * @new_pds: Bitmap set by function with new allocations. Likely used by the
>   *   caller to free on error.
>   *
>   * Allocate the required number of page directories starting at the pde 
> index of
> -- 
> 1.9.1
>
>

-- 
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Re: [Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in intel_lrc.c

[Jani Nikula]

On Tue, 15 Sep 2015, Geliang Tang  wrote:
> Fix the following 'make htmldocs' warnings:
>
>   .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: No description found for 
> parameter 'req'
>   .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: Excess function parameter 
> 'request' description in 'intel_logical_ring_begin'
>   .//drivers/gpu/drm/i915/intel_lrc.c:780: warning: Excess function parameter 
> 'ctx' description in 'intel_logical_ring_begin'

This is already fixed by

commit 374887bae861be2e691381f704b3d6068a54457c
Author: Masanari Iida 
Date:   Sun Sep 13 21:08:31 2015 +0900

drm/i915: Fix warnings while make xmldocs caused by intel_lrc.c

Thanks,
Jani.



>
> Signed-off-by: Geliang Tang 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 72e0edd..963992a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -765,8 +765,7 @@ static int logical_ring_prepare(struct 
> drm_i915_gem_request *req, int bytes)
>  /**
>   * intel_logical_ring_begin() - prepare the logical ringbuffer to accept 
> some commands
>   *
> - * @request: The request to start some new work for
> - * @ctx: Logical ring context whose ringbuffer is being prepared.
> + * @req: The request to start some new work for
>   * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
>   *
>   * The ringbuffer might not be ready to accept the commands right away 
> (maybe it needs to
> -- 
> 1.9.1
>
>

-- 
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Flatten intel_dp_check_mst_status()

[Maarten Lankhorst]

Op 27-08-15 om 17:36 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä 
>
> Restructure intel_dp_check_mst_status() to be more straightforward to
> read.
>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 92 
> +
>  1 file changed, 47 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6c34784..033ee20 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> 

> + for (;;) {
>   bool handled;
> - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> -go_again:
> - if (bret == true) {
> + int retry;
> + int ret;
>  
> - drm_modeset_lock(>mode_config.connection_mutex, 
> NULL);
> + drm_modeset_lock(>mode_config.connection_mutex, NULL);
>  
> - /* check link status - esi[10] = 0x200c */
> - if (intel_dp->active_mst_links &&
> - !drm_dp_channel_eq_ok([10], 
> intel_dp->lane_count)) {
> - DRM_DEBUG_KMS("channel EQ not ok, 
> retraining\n");
> - intel_dp_start_link_train(intel_dp);
> - intel_dp_complete_link_train(intel_dp);
> - intel_dp_stop_link_train(intel_dp);
> - }
> + /* check link status - esi[10] = 0x200c */
> + if (intel_dp->active_mst_links &&
> + !drm_dp_channel_eq_ok([10], intel_dp->lane_count)) {
> + DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
> + intel_dp_start_link_train(intel_dp);
> + intel_dp_complete_link_train(intel_dp);
> + intel_dp_stop_link_train(intel_dp);
> + }
>  
> - drm_modeset_unlock(>mode_config.connection_mutex);
>  
> - DRM_DEBUG_KMS("got esi %3ph\n", esi);
> - ret = drm_dp_mst_hpd_irq(_dp->mst_mgr, esi, 
> );
> -
> - if (handled) {
> - for (retry = 0; retry < 3; retry++) {
> - int wret;
> - wret = drm_dp_dpcd_write(_dp->aux,
> -  
> DP_SINK_COUNT_ESI+1,
> -  [1], 3);
> - if (wret == 3) {
> - break;
> - }
> - }
> + drm_modeset_unlock(>mode_config.connection_mutex);
>  
> - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> - if (bret == true) {
> - DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
> - goto go_again;
> - }
> - } else
> - ret = 0;
> + DRM_DEBUG_KMS("got esi %3ph\n", esi);
> + ret = drm_dp_mst_hpd_irq(_dp->mst_mgr, esi, );
>  
> - return ret;
> - } else {
> - struct intel_digital_port *intel_dig_port = 
> dp_to_dig_port(intel_dp);
> - DRM_DEBUG_KMS("failed to get ESI - device may have 
> failed\n");
> - intel_dp->is_mst = false;
> - drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr, 
> intel_dp->is_mst);
> - /* send a hotplug event */
> - 
> drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
> + if (!handled)
> + return 0;
> +
> + for (retry = 0; retry < 3; retry++) {
> + int wret = drm_dp_dpcd_write(_dp->aux,
> +  DP_SINK_COUNT_ESI+1,
> +  [1], 3);
> + if (wret == 3)
> + break;
>   }
> +
> + bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> + if (!bret)
> + return ret;
^This seemed like a bug the first time I looked at it with the indent changes.

Original indent with if (handled) {.. } seems better here, but with a continue 
instead of a goto.
I think a single return ret; would make it more clear when the loop finishes.

The original code sets ret = 0 when handled = false, but looking a  
drm_dp_mst_hpd_irq
this is unneeded.


> +
> + DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
>   }
> +
>   return -EINVAL;
Can this -EINVAL be removed? It cannot be reached any more.
___

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Program vactive & hactive display size for both ports

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:41PM +0530, Gaurav K Singh wrote:
> Program the required mmio regs for hactive and vactive display size.

This doesn't program anything, just reads them out.

As for readout, do the pipe registers contain the same values? In that
case we could just do a sanity check to make sure the DSI and pipe
registers match.

> 
> Signed-off-by: Gaurav K Singh 
> ---
>  drivers/gpu/drm/i915/intel_display.c |   37 
> ++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index ab9f06a..0285af9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7653,6 +7653,7 @@ static void intel_get_pipe_timings(struct intel_crtc 
> *crtc,
>   struct drm_device *dev = crtc->base.dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + bool is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
>   uint32_t tmp;
>  
>   tmp = I915_READ(HTOTAL(cpu_transcoder));
> @@ -7681,6 +7682,25 @@ static void intel_get_pipe_timings(struct intel_crtc 
> *crtc,
>   pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
>   }
>  
> +  if (IS_BROXTON(dev) && is_dsi) {
> + struct intel_encoder *encoder;
> +
> + for_each_encoder_on_crtc(dev, >base, encoder) {
> + struct intel_dsi *intel_dsi =
> + enc_to_intel_dsi(>base);
> + enum port port;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + pipe_config->base.adjusted_mode.crtc_hdisplay =
> + 
> I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> + pipe_config->base.adjusted_mode.crtc_vdisplay =
> + 
> I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> + pipe_config->base.adjusted_mode.crtc_vtotal =
> + 
> I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> + }
> + }
> + }
> +
>   tmp = I915_READ(PIPESRC(crtc->pipe));
>   pipe_config->pipe_src_h = (tmp & 0x) + 1;
>   pipe_config->pipe_src_w = ((tmp >> 16) & 0x) + 1;
> @@ -10569,6 +10589,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct 
> drm_device *dev,
>   int vtot = I915_READ(VTOTAL(cpu_transcoder));
>   int vsync = I915_READ(VSYNC(cpu_transcoder));
>   enum pipe pipe = intel_crtc->pipe;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>  
>   mode = kzalloc(sizeof(*mode), GFP_KERNEL);
>   if (!mode)
> @@ -10598,6 +10619,22 @@ struct drm_display_mode *intel_crtc_mode_get(struct 
> drm_device *dev,
>   mode->vsync_start = (vsync & 0x) + 1;
>   mode->vsync_end = ((vsync & 0x) >> 16) + 1;
>  
> + if (IS_BROXTON(dev) && is_dsi) {
> + struct intel_encoder *encoder;
> +
> + for_each_encoder_on_crtc(dev, _crtc->base, encoder) {
> + struct intel_dsi *intel_dsi =
> + 
> enc_to_intel_dsi(>base);
> + enum port port;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + mode->vtotal = 
> I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> + mode->hdisplay = 
> I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> + mode->vdisplay = 
> I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> + }
> + }
> + }
> +
>   drm_mode_set_name(mode);
>  
>   return mode;
> -- 
> 1.7.9.5
> 
> ___
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-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: set proper N/CTS in modeset

[Jani Nikula]

On Fri, 11 Sep 2015, libin.y...@intel.com wrote:
> From: Libin Yang 
>
> When modeset occurs and the TMDS frequency is set to some
> speical values, the N/CTS need to be set manually if audio
> is playing.
>
> Signed-off-by: Libin Yang 
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 56 
> --
>  include/drm/i915_component.h   | 10 +++
>  2 files changed, 57 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index e3c32ce..a12bf57 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -128,6 +128,20 @@ static int audio_config_get_n(const struct 
> drm_display_mode *mode, int rate)
>   return 0;
>  }
>  
> +static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
> +{
> + int n_low, n_up;
> + uint32_t tmp = val;
> +
> + n_low = n & 0xfff;
> + n_up = (n >> 12) & 0xff;
> + tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
> + tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
> + (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
> + AUD_CONFIG_N_PROG_ENABLE);
> + return tmp;
> +}
> +
>  /* check whether N/CTS/M need be set manually */
>  static bool audio_rate_need_prog(struct intel_crtc *crtc,
>   struct drm_display_mode *mode)
> @@ -262,9 +276,14 @@ static void hsw_audio_codec_enable(struct drm_connector 
> *connector,
>   struct drm_i915_private *dev_priv = connector->dev->dev_private;
>   struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>   enum pipe pipe = intel_crtc->pipe;
> + struct i915_audio_component *acomp = dev_priv->audio_component;
>   const uint8_t *eld = connector->eld;
> + struct intel_digital_port *intel_dig_port =
> + enc_to_dig_port(>base);
> + enum port port = intel_dig_port->port;
>   uint32_t tmp;
>   int len, i;
> + int n, rate;
>  
>   DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
> pipe_name(pipe), drm_eld_size(eld));
> @@ -302,12 +321,29 @@ static void hsw_audio_codec_enable(struct drm_connector 
> *connector,
>   /* Enable timestamps */
>   tmp = I915_READ(HSW_AUD_CFG(pipe));
>   tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
> - tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
>   tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
>   if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
>   tmp |= AUD_CONFIG_N_VALUE_INDEX;
>   else
>   tmp |= audio_config_hdmi_pixel_clock(mode);
> +
> + tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> + if (audio_rate_need_prog(intel_crtc, mode)) {
> + if (!acomp)
> + rate = 0;
> + else if (port >= PORT_A && port <= PORT_E)
> + rate = acomp->aud_sample_rate[port];
> + else {
> + DRM_ERROR("invalid port: %d\n", port);
> + rate = 0;
> + }
> + n = audio_config_get_n(mode, rate);
> + if (n != 0)
> + tmp = audio_config_setup_n_reg(n, tmp);
> + else
> + DRM_DEBUG_KMS("no suitable N value is found\n");
> + }
> +
>   I915_WRITE(HSW_AUD_CFG(pipe), tmp);
>  
>   mutex_unlock(_priv->av_mutex);
> @@ -594,9 +630,10 @@ static int i915_audio_component_sync_audio_rate(struct 
> device *dev,
>   struct intel_digital_port *intel_dig_port;
>   struct intel_crtc *crtc;
>   struct drm_display_mode *mode;
> + struct i915_audio_component *acomp = dev_priv->audio_component;
>   enum pipe pipe = -1;
>   u32 tmp;
> - int n_low, n_up, n;
> + int n;
>  
>   /* HSW, BDW SKL need this fix */
>   if (!IS_SKYLAKE(dev_priv) &&
> @@ -630,6 +667,9 @@ static int i915_audio_component_sync_audio_rate(struct 
> device *dev,
> pipe_name(pipe), port_name(port));
>   mode = >config->base.adjusted_mode;
>  
> + /* port must be valid now, otherwise the pipe will be invalid */
> + acomp->aud_sample_rate[port] = rate;
> +
>   /* 2. check whether to set the N/CTS/M manually or not */
>   if (!audio_rate_need_prog(crtc, mode)) {
>   tmp = I915_READ(HSW_AUD_CFG(pipe));
> @@ -649,15 +689,10 @@ static int i915_audio_component_sync_audio_rate(struct 
> device *dev,
>   mutex_unlock(_priv->av_mutex);
>   return 0;
>   }
> - n_low = n & 0xfff;
> - n_up = (n >> 12) & 0xff;
>  
> - /* 4. set the N/CTS/M */
> + /* 3. set the N/CTS/M */
>   tmp = I915_READ(HSW_AUD_CFG(pipe));
> - tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
> - tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
> - (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
> - AUD_CONFIG_N_PROG_ENABLE);
> +

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Use adjusted mode clk for calculating DSI clk

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:39PM +0530, Gaurav K Singh wrote:
> Earlier, pclk was getting used for calculating DSI clk. For single link
> MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
> halved, DSI clk will have a wrong value.

Shouldn't we then do pclk*!!dual_link. pclk can be higher than the
dotclock due to the pixel overlap / burst mode stuff, no?

> 
> Signed-off-by: Gaurav K Singh 
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index bf0f622..a53ccc9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -468,12 +468,14 @@ static void bxt_dsi_program_clocks(struct drm_device 
> *dev, enum port port)
>  static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
>  {
>   struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct drm_display_mode *mode = _crtc->config->base.adjusted_mode;
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>   u8 dsi_ratio;
>   u32 dsi_clk;
>   u32 val;
>  
> - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> + dsi_clk = dsi_clk_from_pclk(mode->clock, intel_dsi->pixel_format,
>   intel_dsi->lane_count);
>  
>   /*
> -- 
> 1.7.9.5
> 
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH i-g-t] lib: allow wildcard matching when specifying subtests

[Thomas Wood]

This allows multiple subtests to be specified using standard wildcard
characters when using the --run-subtest command line option.

Signed-off-by: Thomas Wood 
---
 lib/igt_core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/igt_core.c b/lib/igt_core.c
index 129476c..59127ca 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -56,6 +56,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "drmtest.h"
 #include "intel_chipset.h"
@@ -771,7 +772,7 @@ bool __igt_run_subtest(const char *subtest_name)
}
 
if (run_single_subtest) {
-   if (strcmp(subtest_name, run_single_subtest) != 0)
+   if (fnmatch(run_single_subtest, subtest_name, 0) != 0)
return false;
else
run_single_subtest_found = true;
-- 
1.9.1

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Re: [Intel-gfx] [PULL] topic/drm-misc

[Daniel Vetter]

On Mon, Sep 14, 2015 at 8:22 AM, Daniel Vetter  wrote:
> Hi Dave,
>
> -rc1 is out the door and here's my first pull request for drm-next. It's
> all over:
> - better atomic helpers for runtime pm drivers
> - atomic fbdev

David Herrmann just pointed out to me that atomic fbdev isn't actually
in this pull. Just checked my mails and it looks like there's some
small things pending for the kerneldoc. I'll do a separate pull for
atomic fbdev when I'm back from xdc.
-Daniel

> - dp aux i2c STATUS_UPDATE handling (for short i2c replies from the sink)
> - bunch of constify patches
> - various polish all over
>
> There's a few atomic drivers who want the goodies in here (at least rcar
> and i915).
>
> Cheers, Daniel
>
>
> The following changes since commit 73bf1b7be7aab60d7c651402441dd0b0b4991098:
>
>   Merge branch 'drm-next-4.3' of git://people.freedesktop.org/~agd5f/linux 
> into drm-next (2015-09-05 07:46:09 +1000)
>
> are available in the git repository at:
>
>   git://anongit.freedesktop.org/drm-intel tags/topic/drm-misc-2015-09-14
>
> for you to fetch changes up to 216c59d65f99aa1ef1a92e1ae64f1f1c2590dddc:
>
>   drm/atomic-helper: Don't skip plane disabling on active CRTC (2015-09-13 
> 23:20:54 +0200)
>
> 
> Bob Paauwe (1):
>   dtrm/edid: Allow comma separated edid binaries. (v3)
>
> Daniel Vetter (8):
>   drm/atomic-helper: properly annotate functions in kerneldoc
>   drm/fb-helper: Use -errno return in restore_mode_unlocked
>   drm: Make drm_fb_unregister/remove accept NULL fb
>   drm/fb-helper: Add module option to disable fbdev emulation
>   drm/atomic: refuse changing CRTC for planes directly
>   drm/atomic-helper: Add option to update planes only on active crtc
>   drm/atomic-helper: Pimp docs with recommendations for rpm drivers
>   drm: Nuke drm_framebuffer->helper_private
>
> Danilo Cesar Lemes de Paula (1):
>   drm/doc: Fixing xml documentation warning
>
> David Herrmann (2):
>   drm: simplify drm_sysfs_destroy() via IS_ERR_OR_NULL()
>   drm: move drm_class into drm_sysfs.c
>
> Gustavo Padovan (1):
>   drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers
>
> Laurent Pinchart (1):
>   drm/atomic-helper: Don't skip plane disabling on active CRTC
>
> Maarten Lankhorst (3):
>   drm/atomic: Make sure lock is held in trylock contexts.
>   drm/atomic: Make prepare_fb/cleanup_fb only take state, v3.
>   drm/core: Do not call drm_framebuffer_remove internally during teardown.
>
> Michel Thierry (1):
>   drm/mm: Do DRM_MM_CREATE_TOP adj_start calculation after color_adjust
>
> Rob Clark (1):
>   drm: cleanup modesetting ioctls, one param per line
>
> Thierry Reding (1):
>   drm/atomic-helper: Implement drm_atomic_helper_duplicate_state()
>
> Ville Syrjälä (11):
>   drm: Constify generic_edid_names[]
>   drm: Constify TV mode names
>   drm/i2c/ch7006: Constify ch7006_tv_norms[] and ch7006_modes[]
>   drm/dp: s/I2C_STATUS/I2C_WRITE_STATUS_UPDATE/
>   drm/i915: Handle DP_AUX_I2C_WRITE_STATUS_UPDATE
>   drm/radeon: Handle DP_AUX_I2C_WRITE_STATUS_UPDATE
>   drm/tegra: Handle I2C_WRITE_STATUS_UPDATE for address only writes
>   drm/dp: Use I2C_WRITE_STATUS_UPDATE to drain partial I2C_WRITE requests
>   drm: Make some modes const when iterating through them
>   drm: Remove the 'mode' argument from drm_select_eld()
>   drm: Make drm_av_sync_delay() 'mode' argument const
>
>  Documentation/kernel-parameters.txt |  15 +-
>  drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |   4 +-
>  drivers/gpu/drm/drm_atomic.c|  25 
>  drivers/gpu/drm/drm_atomic_helper.c | 185 
> 
>  drivers/gpu/drm/drm_crtc.c  |  18 ++-
>  drivers/gpu/drm/drm_dp_helper.c |  43 +-
>  drivers/gpu/drm/drm_drv.c   |   8 +-
>  drivers/gpu/drm/drm_edid.c  |   8 +-
>  drivers/gpu/drm/drm_edid_load.c |  43 --
>  drivers/gpu/drm/drm_fb_helper.c |  48 +-
>  drivers/gpu/drm/drm_internal.h  |   2 +-
>  drivers/gpu/drm/drm_mm.c|   6 +-
>  drivers/gpu/drm/drm_modeset_lock.c  |   2 +
>  drivers/gpu/drm/drm_plane_helper.c  |   6 +-
>  drivers/gpu/drm/drm_sysfs.c |  49 +++
>  drivers/gpu/drm/exynos/exynos_drm_drv.c |   2 +-
>  drivers/gpu/drm/i2c/ch7006_drv.c|   6 +-
>  drivers/gpu/drm/i2c/ch7006_mode.c   |  26 ++--
>  drivers/gpu/drm/i2c/ch7006_priv.h   |  12 +-
>  drivers/gpu/drm/i915/intel_audio.c  |   2 +-
>  drivers/gpu/drm/i915/intel_display.c|   9 +-
>  drivers/gpu/drm/i915/intel_dp.c |   1 +
>  drivers/gpu/drm/i915/intel_drv.h|   2 -
>  

[Intel-gfx] [PATCH] drm/i915: cleanup pipe_update trace functions with new crtc debug info v2

[Jesse Barnes]

Use the new debug info in the intel_crtc struct in these functions
rather than passing them as args.

v2: move min/max assignment back above first trace call (Ville)
use scanline from crtc->debug rather than fetching a new one (Ville)

Requested-by: Ville Syrjälä 
Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_trace.h   | 22 +++---
 drivers/gpu/drm/i915/intel_sprite.c |  9 -
 2 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h 
b/drivers/gpu/drm/i915/i915_trace.h
index e6b5c74..016a07d 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -17,8 +17,8 @@
 /* pipe updates */
 
 TRACE_EVENT(i915_pipe_update_start,
-   TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max),
-   TP_ARGS(crtc, min, max),
+   TP_PROTO(struct intel_crtc *crtc),
+   TP_ARGS(crtc),
 
TP_STRUCT__entry(
 __field(enum pipe, pipe)
@@ -33,8 +33,8 @@ TRACE_EVENT(i915_pipe_update_start,
   __entry->frame = 
crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,

   crtc->pipe);
   __entry->scanline = intel_get_crtc_scanline(crtc);
-  __entry->min = min;
-  __entry->max = max;
+  __entry->min = crtc->debug.min_vbl;
+  __entry->max = crtc->debug.max_vbl;
   ),
 
TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
@@ -43,8 +43,8 @@ TRACE_EVENT(i915_pipe_update_start,
 );
 
 TRACE_EVENT(i915_pipe_update_vblank_evaded,
-   TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max, u32 frame),
-   TP_ARGS(crtc, min, max, frame),
+   TP_PROTO(struct intel_crtc *crtc),
+   TP_ARGS(crtc),
 
TP_STRUCT__entry(
 __field(enum pipe, pipe)
@@ -56,10 +56,10 @@ TRACE_EVENT(i915_pipe_update_vblank_evaded,
 
TP_fast_assign(
   __entry->pipe = crtc->pipe;
-  __entry->frame = frame;
-  __entry->scanline = intel_get_crtc_scanline(crtc);
-  __entry->min = min;
-  __entry->max = max;
+  __entry->frame = crtc->debug.start_vbl_count;
+  __entry->scanline = crtc->debug.scanline_start;
+  __entry->min = crtc->debug.min_vbl;
+  __entry->max = crtc->debug.max_vbl;
   ),
 
TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
@@ -80,7 +80,7 @@ TRACE_EVENT(i915_pipe_update_end,
TP_fast_assign(
   __entry->pipe = crtc->pipe;
   __entry->frame = frame;
-  __entry->scanline = intel_get_crtc_scanline(crtc);
+  __entry->scanline = crtc->debug.scanline_start;
   ),
 
TP_printk("pipe %c, frame=%u, scanline=%u",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 7de121d..a60a657 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -102,7 +102,9 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
if (WARN_ON(drm_crtc_vblank_get(>base)))
return;
 
-   trace_i915_pipe_update_start(crtc, min, max);
+   crtc->debug.min_vbl = min;
+   crtc->debug.max_vbl = max;
+   trace_i915_pipe_update_start(crtc);
 
for (;;) {
/*
@@ -133,15 +135,12 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
 
drm_crtc_vblank_put(>base);
 
-   crtc->debug.min_vbl = min;
-   crtc->debug.max_vbl = max;
crtc->debug.scanline_start = scanline;
crtc->debug.start_vbl_time = ktime_get();
crtc->debug.start_vbl_count =
dev->driver->get_vblank_counter(dev, pipe);
 
-   trace_i915_pipe_update_vblank_evaded(crtc, min, max,
-crtc->debug.start_vbl_count);
+   trace_i915_pipe_update_vblank_evaded(crtc);
 }
 
 /**
-- 
1.9.1

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Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Fix fb object's frontbuffer-bits

[Paulo Zanoni]

2015-09-14 14:16 GMT-03:00 Daniel Vetter :
> On Mon, Sep 14, 2015 at 09:35:42PM +0530, Sagar Arun Kamble wrote:
>> Shared frontbuffer bits are causing warnings when same FB is displayed
>> in another plane without clearing the bits from previous plane.
>>
>> v2: Removing coversion of fb bits to 64 bit as it is not needed for now. 
>> (Daniel)
>>
>> Change-Id: Ic2df80747f314b82afd22f8326297c57d1e652c6
>> Signed-off-by: Sagar Arun Kamble 
>> Signed-off-by: Kumar, Mahesh 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h | 17 ++---
>>  drivers/gpu/drm/i915/intel_sprite.c |  2 +-
>>  2 files changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 16e604e..892aa78 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2014,25 +2014,28 @@ struct drm_i915_gem_object_ops {
>>
>>  /*
>>   * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
>> - * considered to be the frontbuffer for the given plane interface-vise. This
>> + * considered to be the frontbuffer for the given plane interface-wise. This
>>   * doesn't mean that the hw necessarily already scans it out, but that any
>>   * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
>>   *
>>   * We have one bit per pipe and per scanout plane type.
>>   */
>> -#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
>> +#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
>> +#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
>>  #define INTEL_FRONTBUFFER_BITS \
>>   (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
>>  #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
>>   (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>>  #define INTEL_FRONTBUFFER_CURSOR(pipe) \
>> - (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
>> -#define INTEL_FRONTBUFFER_SPRITE(pipe) \
>> - (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
>> + (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
>> +#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
>> + (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
>>  #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
>> - (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
>> + (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + 
>> (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
>>  #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
>> - (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>> + (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>> +#define INTEL_FRONTBUFFER_SPRITE_MASK(pipe) \
>> + (0x7C << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>
> Patch was a bit confusing to read since tons of spurious whitespace
> change. Anyway looks good once applied except for
> INTEL_FRONTBUFFER_SPRITE_MASK which is unused and hence I removed it
> again.
>
> Queued for -next, thanks for the patch.

Maybe we could have an IGT test for this...

> -Daniel
>
>>
>>  struct drm_i915_gem_object {
>>   struct drm_gem_object base;
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index 9553859..4d27243 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -1123,7 +1123,7 @@ intel_plane_init(struct drm_device *dev, enum pipe 
>> pipe, int plane)
>>
>>   intel_plane->pipe = pipe;
>>   intel_plane->plane = plane;
>> - intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe);
>> + intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
>>   intel_plane->check_plane = intel_check_sprite_plane;
>>   intel_plane->commit_plane = intel_commit_sprite_plane;
>>   possible_crtcs = (1 << pipe);
>> --
>> 1.9.1
>>
>> ___
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>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Implement stolen reserved detection for ctg/elk

[Paulo Zanoni]

2015-09-14 16:34 GMT-03:00  :
> From: Ville Syrjälä 
>
> Finally managed to dig up enough hints as to where the stolen
> reserved stuff lives on ctg/elk. So add the code to decode it.
> This was a combination of old chipset specs, diggin up an old
> elk grits release with an ctg/elk AubLoad etc.
>
> This was only tested on an elk as I don't have a ctg here
> unfortunately.
>
> This leaves ilk as the only platform that doesn't have a way
> to detect this stuff. Looking at the register contents on my
> ilk, it might be that the elk way works there too, but I
> can't be sure since I can't affect the amount of reserved
> memory on that machine, and if I am to trust the register
> contents, by default it would reserve 0 bytes.
>
> Cc: Paulo Zanoni 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_gem_stolen.c | 31 ---
>  drivers/gpu/drm/i915/i915_reg.h|  5 +
>  2 files changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index bf26ecc..2e721ff 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -186,6 +186,29 @@ void i915_gem_cleanup_stolen(struct drm_device *dev)
> drm_mm_takedown(_priv->mm.stolen);
>  }
>
> +static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
> +   unsigned long *base, unsigned long *size)
> +{
> +   uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
> +CTG_STOLEN_RESERVED :
> +ELK_STOLEN_RESERVED);
> +   unsigned long stolen_top = dev_priv->mm.stolen_base +
> +   dev_priv->gtt.stolen_size;
> +
> +   *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
> +
> +   WARN_ON_ONCE((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);

Since we're only going to run this code at driver init, not using the
_ONCE version of the macro will save us a static variable.

Part of the code seems to match one of the docs you pointed, and I
couldn't find the docs for the other part. Also, I'm always way too
confused when I have to deal with the various gen4 sub-gens, so I'll
never be confident enough to give a full R-B, so:
Acked-by: Paulo Zanoni 

More importantly, I see the patches to allow user space to allocate
stolen are back on the mailing list. Once that lands, we'll be able to
write simple IGT tests that allocate all of stolen and check if
everything is usable (check if we read what we just wrote). Or we can
also think about other stuff such as allocating an extra page for
every stolen memory allocation and write/check magic words on it in
order to try to catch corruptions. Just ideas...

> +
> +   /* On these platforms, the register doesn't have a size field, so the
> +* size is the distance between the base and the top of the stolen
> +* memory. We also have the genuine case where base is zero and 
> there's
> +* nothing reserved. */
> +   if (*base == 0)
> +   *size = 0;
> +   else
> +   *size = stolen_top - *base;
> +}
> +
>  static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv,
>  unsigned long *base, unsigned long *size)
>  {
> @@ -305,10 +328,12 @@ int i915_gem_init_stolen(struct drm_device *dev)
> switch (INTEL_INFO(dev_priv)->gen) {
> case 2:
> case 3:
> +   break;
> case 4:
> -   if (!IS_G4X(dev))
> -   break;
> -   /* fall through */
> +   if (IS_G4X(dev))
> +   g4x_get_stolen_reserved(dev_priv, _base,
> +   _size);
> +   break;
> case 5:
> /* Assume the gen6 maximum for the older platforms. */
> reserved_size = 1024 * 1024;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 812b7b2..4f570b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2494,6 +2494,11 @@ enum skl_disp_power_wells {
>
>  #define MCHBAR_MIRROR_BASE_SNB 0x14
>
> +#define CTG_STOLEN_RESERVED(MCHBAR_MIRROR_BASE + 0x34)
> +#define ELK_STOLEN_RESERVED(MCHBAR_MIRROR_BASE + 0x48)
> +#define G4X_STOLEN_RESERVED_ADDR1_MASK (0x << 16)
> +#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
> +
>  /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
>  #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
>
> --
> 2.4.6
>
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> 

Re: [Intel-gfx] [PATCH 01/23] drm: Create Color Management DRM properties

[Matt Roper]

On Wed, Sep 16, 2015 at 11:06:58PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi 
> 
> Color Management is an extension to Kernel display framework. It allows
> abstraction of hardware color correction and enhancement capabilities by
> virtue of DRM properties.
> 
> This patch initializes color management framework by :
> 1. Introducing new pointers in DRM mode_config structure to
>carry CTM and Palette color correction properties.
> 2. Creating these DRM properties in DRM standard properties creation
>sequence.
> 
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Kausal Malladi 

We should probably update the property section of
Documentation/DocBook/drm.tmpl with this patch as well to include these
new properties in the table (that docbook ultimately generates
documentation that looks like
https://kernel.org/doc/htmldocs/drm/drm-kms-properties.html ).

One minor note:  people not involved in color management probably won't
immediately figure out what "CTM" stands for, so you might want to just
add a comment somewhere that spells out the full "color transformation
matrix" term.


Matt


> ---
>  drivers/gpu/drm/drm_crtc.c | 26 ++
>  include/drm/drm_crtc.h |  6 ++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 9b9c4b4..d809c67 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -1472,6 +1472,32 @@ static int drm_mode_create_standard_properties(struct 
> drm_device *dev)
>   return -ENOMEM;
>   dev->mode_config.prop_mode_id = prop;
>  
> + /* Color Management properties */
> + prop = drm_property_create(dev,
> + DRM_MODE_PROP_BLOB | DRM_MODE_PROP_IMMUTABLE,
> + "CRTC_PALETTE_CAPABILITIES", 0);
> + if (!prop)
> + return -ENOMEM;
> + dev->mode_config.cm_crtc_palette_capabilities_property = prop;
> +
> + prop = drm_property_create(dev,
> + DRM_MODE_PROP_BLOB, "PALETTE_AFTER_CTM", 0);
> + if (!prop)
> + return -ENOMEM;
> + dev->mode_config.cm_palette_after_ctm_property = prop;
> +
> + prop = drm_property_create(dev,
> + DRM_MODE_PROP_BLOB, "PALETTE_BEFORE_CTM", 0);
> + if (!prop)
> + return -ENOMEM;
> + dev->mode_config.cm_palette_before_ctm_property = prop;
> +
> + prop = drm_property_create(dev,
> + DRM_MODE_PROP_BLOB, "CTM", 0);
> + if (!prop)
> + return -ENOMEM;
> + dev->mode_config.cm_ctm_property = prop;
> +
>   return 0;
>  }
>  
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index c0366e9..c35531e 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -1153,6 +1153,12 @@ struct drm_mode_config {
>   struct drm_property *suggested_x_property;
>   struct drm_property *suggested_y_property;
>  
> + /* Color Management Properties */
> + struct drm_property *cm_crtc_palette_capabilities_property;
> + struct drm_property *cm_palette_before_ctm_property;
> + struct drm_property *cm_palette_after_ctm_property;
> + struct drm_property *cm_ctm_property;
> +
>   /* dumb ioctl parameters */
>   uint32_t preferred_depth, prefer_shadow;
>  
> -- 
> 1.9.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 02/23] drm: Add structure for querying palette color capabilities

[Matt Roper]

On Wed, Sep 16, 2015 at 11:06:59PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi 
> 
> The DRM color management framework is targeting various hardware
> platforms and drivers. Different platforms can have different color
> correction and enhancement capabilities.
> 
> A commom user space application can query these capabilities using the
> DRM property interface. Each driver can fill this property with its
> platform's palette color capabilities.
> 
> This patch adds new structure in DRM layer for querying palette color
> capabilities. This structure will be used by all user space
> agents to configure appropriate color configurations.
> 
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Kausal Malladi 

I think you provided an explanation on a previous code review cycle, but
I forget the details now...what's the benefit to using a blob for caps
rather than having these be individual properties?  Individual
properties seems more natural to me, but I think you had a justification
for blobbing them together; that reasoning would be good to include in
the commit message.


Matt

> ---
>  include/uapi/drm/drm.h | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
> index 3801584..e3c642f 100644
> --- a/include/uapi/drm/drm.h
> +++ b/include/uapi/drm/drm.h
> @@ -829,6 +829,17 @@ struct drm_event_vblank {
>   __u32 reserved;
>  };
>  
> +struct drm_palette_caps {
> + /* Structure version. Should be 1 currently */
> + __u32 version;
> + /* For padding and future use */
> + __u32 reserved;
> + /* This may be 0 if not supported. e.g. plane palette or VLV pipe */
> + __u32 num_samples_before_ctm;
> + /* This will be non-zero for pipe. May be zero for planes on some HW */
> + __u32 num_samples_after_ctm;
> +};
> +
>  /* typedef area */
>  #ifndef __KERNEL__
>  typedef struct drm_clip_rect drm_clip_rect_t;
> -- 
> 1.9.1
> 

-- 
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Graphics Software Engineer
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[Intel-gfx] [PATCH v2] drm/i915: Implement stolen reserved detection for ctg/elk

[ville . syrjala]

From: Ville Syrjälä 

Finally managed to dig up enough hints as to where the stolen
reserved stuff lives on ctg/elk. So add the code to decode it.
This was a combination of old chipset specs, diggin up an old
elk grits release with an ctg/elk AubLoad etc.

This was only tested on an elk as I don't have a ctg here
unfortunately.

This leaves ilk as the only platform that doesn't have a way
to detect this stuff. Looking at the register contents on my
ilk, it might be that the elk way works there too, but I
can't be sure since I can't affect the amount of reserved
memory on that machine, and if I am to trust the register
contents, by default it would reserve 0 bytes.

v2: s/WARN_ON_ONCE/WARN_ON/ since it's in one time init code
anyway (Paulo)

Cc: Paulo Zanoni 
Cc: Chris Wilson 
Acked-by: Paulo Zanoni 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_gem_stolen.c | 31 ---
 drivers/gpu/drm/i915/i915_reg.h|  5 +
 2 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index bf26ecc..0a3cffb 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -186,6 +186,29 @@ void i915_gem_cleanup_stolen(struct drm_device *dev)
drm_mm_takedown(_priv->mm.stolen);
 }
 
+static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
+   unsigned long *base, unsigned long *size)
+{
+   uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
+CTG_STOLEN_RESERVED :
+ELK_STOLEN_RESERVED);
+   unsigned long stolen_top = dev_priv->mm.stolen_base +
+   dev_priv->gtt.stolen_size;
+
+   *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
+
+   WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
+
+   /* On these platforms, the register doesn't have a size field, so the
+* size is the distance between the base and the top of the stolen
+* memory. We also have the genuine case where base is zero and there's
+* nothing reserved. */
+   if (*base == 0)
+   *size = 0;
+   else
+   *size = stolen_top - *base;
+}
+
 static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv,
 unsigned long *base, unsigned long *size)
 {
@@ -305,10 +328,12 @@ int i915_gem_init_stolen(struct drm_device *dev)
switch (INTEL_INFO(dev_priv)->gen) {
case 2:
case 3:
+   break;
case 4:
-   if (!IS_G4X(dev))
-   break;
-   /* fall through */
+   if (IS_G4X(dev))
+   g4x_get_stolen_reserved(dev_priv, _base,
+   _size);
+   break;
case 5:
/* Assume the gen6 maximum for the older platforms. */
reserved_size = 1024 * 1024;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 812b7b2..4f570b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2494,6 +2494,11 @@ enum skl_disp_power_wells {
 
 #define MCHBAR_MIRROR_BASE_SNB 0x14
 
+#define CTG_STOLEN_RESERVED(MCHBAR_MIRROR_BASE + 0x34)
+#define ELK_STOLEN_RESERVED(MCHBAR_MIRROR_BASE + 0x48)
+#define G4X_STOLEN_RESERVED_ADDR1_MASK (0x << 16)
+#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
+
 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
 
-- 
2.4.6

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Only check pipe state for fast modeset when it's possible.

[Jesse Barnes]

On 09/14/2015 02:30 AM, Maarten Lankhorst wrote:
> + if (!crtc_state->connectors_changed &&
> + !crtc_state->active_changed &&
> + crtc_state->active &&
> + intel_pipe_config_compare(state->dev,
> +   to_intel_crtc_state(crtc->state),
> +   pipe_config, true)) {
>   crtc_state->mode_changed = false;
> - to_intel_crtc_state(crtc_state)->update_pipe = true;
> - }

Doesn't needs_modeset() cover the connectors and active changed cases?  Could 
we just hoist that up earlier in this function instead?

Jesse
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix fastboot scalers for skylake.

[Jesse Barnes]

On 09/14/2015 02:30 AM, Maarten Lankhorst wrote:
> The scaler_id in intel_pipe_config_compare should not be checked
> when adjusting in intel_pipe_config_compare. The hw scaler id may
> be changed in intel_update_pipe_config.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 452e8f77151d..deb76c84a307 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12467,9 +12467,9 @@ intel_pipe_config_compare(struct drm_device *dev,
>   PIPE_CONF_CHECK_X(pch_pfit.pos);
>   PIPE_CONF_CHECK_X(pch_pfit.size);
>   }
> - }
>  
> - PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> + PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> + }
>  
>   /* BDW+ don't expose a synchronous way to read the state */
>   if (IS_HASWELL(dev))
> 

Reviewed-by: Jesse Barnes 
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Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

[Ville Syrjälä]

On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> We need to be able to control if DC6 is allowed or not. Much like
> requesting power to a specific piece of the hardware we need to be able
> to request that we don't enter DC6 during certain hw access.
> 
> To solve this without introducing too much infrastructure I'm hooking
> into the power well / power domain framework. DC6 prevention is modeled
> much like an enabled power well. Thus I'm using the terminology on/off
> for DC states instead of enable/disable.
> 
> The problem that started this work is the need for DC6 to be disabled
> when accessing DP_AUX_A during CRTC on/off. That is also fixed in this
> patch.
> 
> This is posted as an RFC since DMC and DC state handling is being
> reworked and will possibly affect the outcome of this patch. The patch
> has known warnings.
> 
> Signed-off-by: Patrik Jakobsson 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c|  9 +
>  drivers/gpu/drm/i915/intel_drv.h|  2 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 69 
> +
>  3 files changed, 64 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 4823184..c2c1ad2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2288,6 +2288,8 @@ static void intel_ddi_pre_enable(struct intel_encoder 
> *intel_encoder)
>   if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
>   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
> + intel_display_power_get(dev_priv, POWER_DOMAIN_AUX_A);
> +

These I think shouldn't be necessary with my
intel_display_port_aux_power_domain() stuff since intel_dp_aux_ch() will
itself grab the appropriate power domain.

That's of course assuming that AUX is the only reason why we need to
keep DC6 disabled here.

>   intel_dp_set_link_params(intel_dp, crtc->config);
>  
>   intel_ddi_init_dp_buf_reg(intel_encoder);
> @@ -2297,6 +2299,8 @@ static void intel_ddi_pre_enable(struct intel_encoder 
> *intel_encoder)
>   intel_dp_complete_link_train(intel_dp);
>   if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
>   intel_dp_stop_link_train(intel_dp);
> +
> + intel_display_power_put(dev_priv, POWER_DOMAIN_AUX_A);
>   } else if (type == INTEL_OUTPUT_HDMI) {
>   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  
> @@ -2339,9 +2343,14 @@ static void intel_ddi_post_disable(struct 
> intel_encoder *intel_encoder)
>  
>   if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
>   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_display_power_get(dev_priv, POWER_DOMAIN_AUX_A);
> +
>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>   intel_edp_panel_vdd_on(intel_dp);
>   intel_edp_panel_off(intel_dp);
> +
> + intel_display_power_put(dev_priv, POWER_DOMAIN_AUX_A);
>   }
>  
>   if (IS_SKYLAKE(dev))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 46484e4..82489ad 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1367,6 +1367,8 @@ void chv_phy_powergate_lanes(struct intel_encoder 
> *encoder,
>bool override, unsigned int mask);
>  bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy 
> phy,
> enum dpio_channel ch, bool override);
> +void skl_enable_dc6(struct drm_i915_private *dev_priv);
> +void skl_disable_dc6(struct drm_i915_private *dev_priv);
>  
>  
>  /* intel_pm.c */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3f682a1..e30c9a6 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -335,6 +335,10 @@ static void hsw_set_power_well(struct drm_i915_private 
> *dev_priv,
>   SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
>   BIT(POWER_DOMAIN_PLLS) |\
>   BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_DC6_OFF_POWER_DOMAINS (  \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_AUX_A))
> +
>  #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (\
>   (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
>   SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> @@ -550,7 +554,7 @@ static void assert_can_disable_dc6(struct 
> drm_i915_private *dev_priv)
>   "DC6 already programmed to be disabled.\n");
>  }
>  
> -static void skl_enable_dc6(struct drm_i915_private *dev_priv)
> +void skl_enable_dc6(struct drm_i915_private *dev_priv)
>  {
>   uint32_t val;
>  
> @@ -567,7 +571,7 @@ static void 

[Intel-gfx] [drm-intel:topic/drm-misc 33/35] DockBook: Warning(include/drm/drm_fb_helper.h:148): No description found for parameter 'atomic'

[kbuild test robot]

tree:   git://anongit.freedesktop.org/drm-intel topic/drm-misc
head:   28cc504e8d52248962f5b485bdc65f539e3fe21d
commit: bbb1e52402b2a288b09ae37e8182599931c7e9df [33/35] drm/fb-helper: atomic 
restore_fbdev_mode()..
reproduce: make htmldocs

All warnings (new ones prefixed by >>):

   Warning(drivers/gpu/drm/i915/i915_irq.c:491): No description found for 
parameter 'dev'
   Warning(drivers/gpu/drm/i915/i915_irq.c:2191): No description found for 
parameter 'dev'
   Warning(drivers/gpu/drm/i915/i915_irq.c:2371): No description found for 
parameter 'wedged'
   Warning(drivers/gpu/drm/i915/i915_irq.c:2371): No description found for 
parameter 'fmt'
   Warning(include/drm/drm_crtc.h:308): No description found for parameter 
'mode_blob'
   Warning(include/drm/drm_crtc.h:746): No description found for parameter 
'tile_blob_ptr'
   Warning(include/drm/drm_crtc.h:785): No description found for parameter 
'rotation'
   Warning(include/drm/drm_crtc.h:881): No description found for parameter 
'mutex'
   Warning(include/drm/drm_crtc.h:881): No description found for parameter 
'helper_private'
   Warning(include/drm/drm_crtc.h:929): Excess struct/union/enum/typedef member 
'base' description in 'drm_bridge'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tile_idr'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'delayed_event'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'edid_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'dpms_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'path_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tile_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'plane_type_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'rotation_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_src_x'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_src_y'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_src_w'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_src_h'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_crtc_x'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_crtc_y'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_crtc_w'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_crtc_h'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_fb_id'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_crtc_id'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_active'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'prop_mode_id'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'dvi_i_subconnector_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'dvi_i_select_subconnector_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_subconnector_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_select_subconnector_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_mode_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_left_margin_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_right_margin_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_top_margin_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_bottom_margin_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_brightness_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_contrast_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_flicker_reduction_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_overscan_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_saturation_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'tv_hue_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'scaling_mode_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'aspect_ratio_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 
'dirty_info_property'
   Warning(include/drm/drm_crtc.h:1167): No description found for parameter 

[Intel-gfx] [drm-intel:drm-intel-nightly 3/5] include/drm/drm_fb_helper.h:148: warning: No description found for parameter 'connector_info'

[kbuild test robot]

tree:   git://anongit.freedesktop.org/drm-intel drm-intel-nightly
head:   7738abac2b4564d3e4dfac769054dde326fbcafb
commit: a50fc26383859d01caa8f886b611fdeb86946757 [3/5] Merge remote-tracking 
branch 'origin/topic/drm-misc' into drm-intel-nightly
config: i386-allnoconfig (attached as .config)
reproduce:
  git checkout a50fc26383859d01caa8f886b611fdeb86946757
  # save the attached .config to linux build tree
  make ARCH=i386 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_irq.c:548: warning: No description found for 
parameter 'dev'
   drivers/gpu/drm/i915/i915_irq.c:2333: warning: No description found for 
parameter 'dev'
   drivers/gpu/drm/i915/i915_irq.c:2513: warning: No description found for 
parameter 'wedged'
   drivers/gpu/drm/i915/i915_irq.c:2513: warning: No description found for 
parameter 'fmt'
   include/drm/drm_crtc.h:308: warning: No description found for parameter 
'mode_blob'
   include/drm/drm_crtc.h:746: warning: No description found for parameter 
'tile_blob_ptr'
   include/drm/drm_crtc.h:785: warning: No description found for parameter 
'rotation'
   include/drm/drm_crtc.h:881: warning: No description found for parameter 
'mutex'
   include/drm/drm_crtc.h:881: warning: No description found for parameter 
'helper_private'
   include/drm/drm_crtc.h:929: warning: Excess struct/union/enum/typedef member 
'base' description in 'drm_bridge'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tile_idr'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'delayed_event'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'edid_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'dpms_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'path_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tile_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'plane_type_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'rotation_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_src_x'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_src_y'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_src_w'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_src_h'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_crtc_x'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_crtc_y'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_crtc_w'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_crtc_h'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_fb_id'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_crtc_id'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_active'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'prop_mode_id'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'dvi_i_subconnector_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'dvi_i_select_subconnector_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_subconnector_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_select_subconnector_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_mode_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_left_margin_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_right_margin_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_top_margin_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_bottom_margin_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_brightness_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_contrast_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_flicker_reduction_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_overscan_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_saturation_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'tv_hue_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'scaling_mode_property'
   include/drm/drm_crtc.h:1167: warning: No description found for parameter 
'aspect_ratio_property'
   

[Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_irq.c

between commit:

  4e3d1e26c2b2 ("drm/i915: Pass hpd_status_i915[] to intel_get_hpd_pins() in 
pre-g4x")

from Linus' tree and commit:

  58f2cf241fb9 ("drm/i915: Don't call intel_get_hpd_pins() when there's no 
hotplug interrupt")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwells...@canb.auug.org.au

diff --cc drivers/gpu/drm/i915/i915_irq.c
index 5a244ab9395b,ca6d806a195a..
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@@ -1557,10 -1652,13 +1652,13 @@@ static void i9xx_hpd_irq_handler(struc
} else {
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  
-   intel_get_hpd_pins(_mask, _mask, hotplug_trigger,
-  hotplug_trigger, hpd_status_i915,
-  i9xx_port_hotplug_long_detect);
-   intel_hpd_irq_handler(dev, pin_mask, long_mask);
+   if (hotplug_trigger) {
+   intel_get_hpd_pins(_mask, _mask, 
hotplug_trigger,
 - hotplug_trigger, hpd_status_g4x,
++ hotplug_trigger, hpd_status_i915,
+  i9xx_port_hotplug_long_detect);
+ 
+   intel_hpd_irq_handler(dev, pin_mask, long_mask);
+   }
}
  }
  
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[Intel-gfx] Safe watermark value for BDW

[Xie, William]

Dear,

I would like to hardcode the safe watermark value for BDW for some tests and 
don't care about power,
Do you have a safe watermark value at hand so that I can give a try?

Thanks
William

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Re: [Intel-gfx] [DMC_BUGFIX_SKL_V2 1/5] drm/i915/skl: Added a check for the hardware status of csr fw before loading.

[Animesh Manna]

On 9/14/2015 1:16 PM, Daniel Vetter wrote:

On Fri, Sep 11, 2015 at 12:36:24AM +0530, Animesh Manna wrote:


On 9/10/2015 8:15 PM, Daniel Vetter wrote:

On Thu, Sep 10, 2015 at 01:58:54AM +0530, Animesh Manna wrote:

On 9/2/2015 2:24 PM, Daniel Vetter wrote:

On Wed, Aug 26, 2015 at 07:40:54PM +0530, Animesh Manna wrote:

On 8/26/2015 6:40 PM, Daniel Vetter wrote:

On Wed, Aug 26, 2015 at 01:36:05AM +0530, Animesh Manna wrote:

Dmc will restore the csr program except DC9, cold boot,
warm reset, PCI function level reset, and hibernate/suspend.

intel_csr_load_program() function is used to load the firmware
data from kernel memory to csr address space.

All values of csr address space will be zero if it got reset and
the first byte of csr program is always a non-zero if firmware
is loaded successfuly. Based on hardware status will load the
firmware.

Without this condition check if we overwrite the firmware data the
counters exposed for dc5/dc6 (help for debugging) will be nullified.

Bacause of the above reason mentioned just above we need to block firmware 
loading again.
So only WARN_ON will not help.



v1: Initial version.

v2: Based on review comments from Daniel,
- Added a check to know hardware status and load the firmware if not loaded.

Cc: Daniel Vetter 
Cc: Damien Lespiau 
Cc: Imre Deak 
Cc: Sunil Kamath 
Signed-off-by: Animesh Manna 
Signed-off-by: Vathsala Nagaraju 
---
  drivers/gpu/drm/i915/intel_csr.c | 9 +
  1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae03..682cc26 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -252,6 +252,15 @@ void intel_csr_load_program(struct drm_device *dev)
return;
}
+   /*
+* Dmc will restore the csr the program except DC9, cold boot,
+* warm reset, PCI function level reset, and hibernate/suspend.
+* This condition will help to check if csr address space is reset/
+* not loaded.
+*/

Atm we call this from driver load and resume, which doesn seem to cover
all the cases you mention in the comment. Should this be a WARN_ON
instead? Or do we have troubles in our init sequence where we load too
many times?

Yes, the above statement taken from bspec to describe about the special cases 
dmc will not restore the firmware.
Agree, In our cases cold boot and hibernate/suspend mainly we need to load the 
firmware again, so in my
second sentence I wanted to comment mainly regarding this condition check added 
for suspend-hibernate(reset)
and cold boot(not loaded).

Anyways the same api later can be used to load the firmware from anywhere, so 
my intention to check firmware loaded or not.
If already loaded then not to overwrite the csr address space to maintain the 
dc5/dc6 counter value.

Can the below comment more clear to you.

/*
 * Dmc will restore the csr the program except DC9, cold boot,
 * warm reset, PCI function level reset, and hibernate/suspend.
 * If firmware is restored by dmc then no need to load again which
 * will keep the dc5/dc6 counter exposed by firmware.
 */

No issue in init sequence.

That seems to still cover all the callers of the function afaics - we do
pci resets over suspend resume unconditionally. So I still don't
understand where exactly we try to load the dmc firmware in i915.ko when
it's already loaded.

During resume intel_csr_load_program() will be called from
intel_runtime_resume().

intel_runtime_resume()-> skl_resume_prepare()-> intel_csr_load_program()

During Pc10 entry testing I can see dmc is restoring back the firmware always,
but as you mentioned pci-reset can happen unconditionally, but still then
also during resume intel_runtime_resume() will be called and based on
register read of csr-base-address firmware loading will happen.

But in your comment you're saying it won't get restored in case of dc9 and
suspend. So that seems to mismatch what you're saying here (and what the
commit message says) and what the code does. And this function here is
called for resume after suspend/hibernate only.

pc10 entry explanation I told is for skylake. dc9 in skylake is not possible.
I think you are confusing between dc6 and dc9. Pc10 can be achieved by
entering into dc6 (not dc9) for skylake. dc9 is the lowest possible state
for broxton which is not present for skylake.

I have no idea at all about different pc levels on skl. What I'm talking
about is system suspend/resume and driver load, which are the places this
function gets called. At least afaics.


Here intel_csr_load_program() will be used for both skylake and broxton, and 
instruction
execution flow will be different in case of suspend/resume which I think is 
confusing
you.

That seems like really 

[Intel-gfx] [PATCH 00/23] Color Management for DRM

[Shashank Sharma]

This patch set adds Color Manager implementation in DRM layer. Color Manager
is an extension in DRM framework to support color correction/enhancement.

Various Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows a user
space UI agent to correct/enhance the display using the DRM property interface.

How is this going to work?
==
1. This patch series adds a few new properties in DRM framework. These 
properties are:
a. color_capabilities property (type blob)
b. Color Transformation Matrix property for corrections like CSC 
(called CTM, type blob)
c. Palette correction properties for corrections like gamma fixup 
(called palette_correction, type blob) 
2. Also, this patch series adds few structures to indicate specifications of a 
property like size, no_of_samples for correction etc.
3. These properties are present in mode_config.
4. When the platform's display driver loads, it fills up the values of 
color_capabilities property using the standard structures (added in step 2).
   For example, Intel's I915 driver adds following color correction 
capabilities:
a. gamma correction capability as palette correction property, with 257 
correction coefficients and a max/min value
b. csc correction capability as CTM correction property, with 3x3 
transformation matrix values and max/min values 
5. Now when userspace comes up, it queries the platform's color capabilities by 
doing a get_property() on color_capabilities DRM property
6. Reading the blob, the userspace understands the color capabilities of the 
platform.
   For example, userspace will understand it can support:
a. palette_correction with 257 coefficients
b. CSC correction with 3x3 = 9 values 
7. To set color correction values, userspace:
a. creates a blob using the create_blob_ioctl in standard 
palette_correction structure format, with the correction values
b. calls the set_property_ioctl with the blob_id as value for the 
property 
8. Driver refers to the blob, gets the correction values and applies the 
correction in HW.
9. To get currently applied color correction values, userspace:
a. calls a get_property_ioctl on that color property
b. gets the blob_id for the currently applied correction from DRM 
infrastructure
c. gets the blob using get_blob_ioctl and hence the currently applied 
values

That's all! :)

About the patch series:
===
The patch series first adds the color management support in DRM layer.
Then it adds the color management framework in I915 layer. 
After that, it implements platform specific core color correction functios. 

Intel color manager registers color correction with DRM color manager in this 
way:
 - CSC transformation is registered as CTM DRM property
 - Gamma correction is registered as palette_after_ctm DRM property
 - Degamma correction is registered as palette_before_ctm DRM property

Our thanks to all the reviewers who have given valuable comments in terms
of design and implementation to our previous sets of patches. Special mention
of thanks should go to Matt Roper for all his inputs/suggestions in 
implementation
of this module, using DRM atomic CRTC commit path.

V2: Worked on review comments from Matt, Jim, Thierry, Rob.
V3: Worked on review comments from Matt, Jim, Rob:
 - Jim, Rob:
   
   Re-arranged the whole patch series in the sequence of features, currently:
   First 5 patches add color management support in DRM layer
   Next 7 patches add Intel color management framework in I915 driver
   Next 5 patches add color correction for CHV (gamma, degamma and CSC)
   Next 2 patches enable color management, by attaching the properties to 
CRTC(Matt)
   Next 4 patches add color correction for BDW (gamma, degamma)
 - Matt:
   =
   Patch 3: Added refernce/unreference for blob
   Patch 7: return -EINVAL and added debug message
   Patch 8: check for valid blob, from create blob
moved call to intel_crtc_attach_color_prop in the end of full 
implementation (CHV)
   Patch 9: DRM_ERROR->DRM_DEBUG for NULL blob case
   Patch 13: Added static for internal functions
   Patch 20-24: renamed gen9_* functions to bdw_*
   Added new variables in device_info structure num_samples_after_ctm and 
num_samples_before_ctm
   Added new function in patch 8 to load capabilities based on device_info 
across all platforms

Shashank Sharma (23):
  drm: Create Color Management DRM properties
  drm: Add structure for querying palette color capabilities
  drm: Add color correction blobs in CRTC state
  drm: Add drm structures for palette color property
  drm: Add structure to set/get a CTM color property
  drm/i915: Add atomic set property interface for CRTC
  drm/i915: Add atomic get property interface for CRTC
  drm/i915: Create color management files
  drm/i915: Register pipe color capabilities
  

[Intel-gfx] [PATCH 01/23] drm: Create Color Management DRM properties

[Shashank Sharma]

From: Kausal Malladi 

Color Management is an extension to Kernel display framework. It allows
abstraction of hardware color correction and enhancement capabilities by
virtue of DRM properties.

This patch initializes color management framework by :
1. Introducing new pointers in DRM mode_config structure to
   carry CTM and Palette color correction properties.
2. Creating these DRM properties in DRM standard properties creation
   sequence.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/drm_crtc.c | 26 ++
 include/drm/drm_crtc.h |  6 ++
 2 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 9b9c4b4..d809c67 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1472,6 +1472,32 @@ static int drm_mode_create_standard_properties(struct 
drm_device *dev)
return -ENOMEM;
dev->mode_config.prop_mode_id = prop;
 
+   /* Color Management properties */
+   prop = drm_property_create(dev,
+   DRM_MODE_PROP_BLOB | DRM_MODE_PROP_IMMUTABLE,
+   "CRTC_PALETTE_CAPABILITIES", 0);
+   if (!prop)
+   return -ENOMEM;
+   dev->mode_config.cm_crtc_palette_capabilities_property = prop;
+
+   prop = drm_property_create(dev,
+   DRM_MODE_PROP_BLOB, "PALETTE_AFTER_CTM", 0);
+   if (!prop)
+   return -ENOMEM;
+   dev->mode_config.cm_palette_after_ctm_property = prop;
+
+   prop = drm_property_create(dev,
+   DRM_MODE_PROP_BLOB, "PALETTE_BEFORE_CTM", 0);
+   if (!prop)
+   return -ENOMEM;
+   dev->mode_config.cm_palette_before_ctm_property = prop;
+
+   prop = drm_property_create(dev,
+   DRM_MODE_PROP_BLOB, "CTM", 0);
+   if (!prop)
+   return -ENOMEM;
+   dev->mode_config.cm_ctm_property = prop;
+
return 0;
 }
 
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c0366e9..c35531e 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1153,6 +1153,12 @@ struct drm_mode_config {
struct drm_property *suggested_x_property;
struct drm_property *suggested_y_property;
 
+   /* Color Management Properties */
+   struct drm_property *cm_crtc_palette_capabilities_property;
+   struct drm_property *cm_palette_before_ctm_property;
+   struct drm_property *cm_palette_after_ctm_property;
+   struct drm_property *cm_ctm_property;
+
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
 
-- 
1.9.1

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[Intel-gfx] [PATCH 04/23] drm: Add drm structures for palette color property

[Shashank Sharma]

From: Kausal Malladi 

This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 include/uapi/drm/drm.h | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index e3c642f..f72b916 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -840,6 +840,33 @@ struct drm_palette_caps {
__u32 num_samples_after_ctm;
 };
 
+struct drm_r32g32b32 {
+   /*
+* Data is in U8.24 fixed point format.
+* All platforms support values within [0, 1.0] range,
+* for Red, Green and Blue colors.
+*/
+   __u32 r32;
+   __u32 g32;
+   __u32 b32;
+};
+
+struct drm_palette {
+   /* Structure version. Should be 1 currently */
+   __u32 version;
+   /*
+* This has to be a supported value during get call.
+* Feature will be disabled if this is 0 while set
+*/
+   __u32 num_samples;
+   /*
+* Starting of palette LUT in R32G32B32 format.
+* Each of RGB value is in U8.24 fixed point format.
+* Actual number of samples will depend upon num_samples
+*/
+   struct drm_r32g32b32 lut[0];
+};
+
 /* typedef area */
 #ifndef __KERNEL__
 typedef struct drm_clip_rect drm_clip_rect_t;
-- 
1.9.1

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[Intel-gfx] [PATCH 03/23] drm: Add color correction blobs in CRTC state

[Shashank Sharma]

From: Kausal Malladi 

This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/drm_atomic_helper.c | 12 
 include/drm/drm_crtc.h  |  5 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 94d6c8e..1fe91ee 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2168,6 +2168,12 @@ void __drm_atomic_helper_crtc_duplicate_state(struct 
drm_crtc *crtc,
 
if (state->mode_blob)
drm_property_reference_blob(state->mode_blob);
+   if (state->ctm_blob)
+   drm_property_reference_blob(state->ctm_blob);
+   if (state->palette_after_ctm_blob)
+   drm_property_reference_blob(state->palette_after_ctm_blob);
+   if (state->palette_before_ctm_blob)
+   drm_property_reference_blob(state->palette_before_ctm_blob);
state->mode_changed = false;
state->active_changed = false;
state->planes_changed = false;
@@ -2213,6 +2219,12 @@ void __drm_atomic_helper_crtc_destroy_state(struct 
drm_crtc *crtc,
 {
if (state->mode_blob)
drm_property_unreference_blob(state->mode_blob);
+   if (state->ctm_blob)
+   drm_property_unreference_blob(state->ctm_blob);
+   if (state->palette_after_ctm_blob)
+   drm_property_unreference_blob(state->palette_after_ctm_blob);
+   if (state->palette_before_ctm_blob)
+   drm_property_unreference_blob(state->palette_before_ctm_blob);
 }
 EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);
 
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c35531e..fcbe682 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -302,6 +302,11 @@ struct drm_crtc_state {
/* blob property to expose current mode to atomic userspace */
struct drm_property_blob *mode_blob;
 
+   /* blob properties to hold the color properties' blobs */
+   struct drm_property_blob *palette_before_ctm_blob;
+   struct drm_property_blob *palette_after_ctm_blob;
+   struct drm_property_blob *ctm_blob;
+
struct drm_pending_vblank_event *event;
 
struct drm_atomic_state *state;
-- 
1.9.1

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[Intel-gfx] [PATCH 02/23] drm: Add structure for querying palette color capabilities

[Shashank Sharma]

From: Kausal Malladi 

The DRM color management framework is targeting various hardware
platforms and drivers. Different platforms can have different color
correction and enhancement capabilities.

A commom user space application can query these capabilities using the
DRM property interface. Each driver can fill this property with its
platform's palette color capabilities.

This patch adds new structure in DRM layer for querying palette color
capabilities. This structure will be used by all user space
agents to configure appropriate color configurations.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 include/uapi/drm/drm.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 3801584..e3c642f 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -829,6 +829,17 @@ struct drm_event_vblank {
__u32 reserved;
 };
 
+struct drm_palette_caps {
+   /* Structure version. Should be 1 currently */
+   __u32 version;
+   /* For padding and future use */
+   __u32 reserved;
+   /* This may be 0 if not supported. e.g. plane palette or VLV pipe */
+   __u32 num_samples_before_ctm;
+   /* This will be non-zero for pipe. May be zero for planes on some HW */
+   __u32 num_samples_after_ctm;
+};
+
 /* typedef area */
 #ifndef __KERNEL__
 typedef struct drm_clip_rect drm_clip_rect_t;
-- 
1.9.1

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[Intel-gfx] [PATCH 10/23] drm/i915: Add gamma correction handlers

[Shashank Sharma]

I915 driver registers gamma correction as palette correction
property with DRM layer. This patch adds set_property() and get_property()
handlers for pipe level gamma correction.

The set function attaches the Gamma correction blob to CRTC state, these
values will be committed during atomic commit.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_atomic.c| 20 
 drivers/gpu/drm/i915/intel_color_manager.c | 21 +
 drivers/gpu/drm/i915/intel_drv.h   |  5 +
 3 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index 500d2998..0b61fef 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -315,6 +315,13 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
   struct drm_property *property,
   uint64_t val)
 {
+   struct drm_device *dev = crtc->dev;
+   struct drm_mode_config *config = >mode_config;
+
+   if (property == config->cm_palette_after_ctm_property)
+   return intel_color_manager_set_pipe_gamma(dev, state,
+   >base, val);
+
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
 }
@@ -324,6 +331,19 @@ int intel_crtc_atomic_get_property(struct drm_crtc *crtc,
   struct drm_property *property,
   uint64_t *val)
 {
+   struct drm_device *dev = crtc->dev;
+   struct drm_mode_config *config = >mode_config;
+
+   if (property == config->cm_palette_after_ctm_property) {
+   *val = (state->palette_after_ctm_blob) ?
+   state->palette_after_ctm_blob->base.id : 0;
+   goto found;
+   }
+
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
+
+found:
+   DRM_DEBUG_KMS("Found property %s\n", property->name);
+   return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index 77f58f2..9421bb6 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,27 @@
 
 #include "intel_color_manager.h"
 
+int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state,
+   struct drm_mode_object *obj, uint32_t blob_id)
+{
+   struct drm_property_blob *blob;
+
+   blob = drm_property_lookup_blob(dev, blob_id);
+   if (!blob) {
+   DRM_DEBUG_KMS("Invalid Blob ID\n");
+   return -EINVAL;
+   }
+
+   if (crtc_state->palette_after_ctm_blob)
+   drm_property_unreference_blob(
+   crtc_state->palette_after_ctm_blob);
+
+   /* Attach the blob to be committed in state */
+   crtc_state->palette_after_ctm_blob = blob;
+   return 0;
+}
+
 int get_pipe_capabilities(struct drm_device *dev,
struct drm_palette_caps *palette_caps, struct drm_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e27e754..d0193e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1466,4 +1466,9 @@ void intel_plane_destroy_state(struct drm_plane *plane,
   struct drm_plane_state *state);
 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
 
+/* intel_color_manager.c */
+int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state,
+   struct drm_mode_object *obj, uint32_t blob_id);
+
 #endif /* __INTEL_DRV_H__ */
-- 
1.9.1

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[Intel-gfx] [PATCH 22/23] drm/i915: BDW: Load degamma correction values

[Shashank Sharma]

I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.

This patch adds the no of coefficients(65) for degamma correction
as "num_samples_before_ctm" parameter in device info structures,
for BDW and higher platforms.

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_drv.c| 7 +++
 drivers/gpu/drm/i915/intel_color_manager.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 69afed3..23ad2cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -303,6 +303,7 @@ static const struct intel_device_info 
intel_broadwell_d_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+   .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -316,6 +317,7 @@ static const struct intel_device_info 
intel_broadwell_m_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+   .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -329,6 +331,7 @@ static const struct intel_device_info 
intel_broadwell_gt3d_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+   .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -342,6 +345,7 @@ static const struct intel_device_info 
intel_broadwell_gt3m_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+   .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -368,6 +372,7 @@ static const struct intel_device_info intel_skylake_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+   .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -382,6 +387,7 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+   .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -396,6 +402,7 @@ static const struct intel_device_info intel_broxton_info = {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
+   .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS,
.num_pipes = 3,
.has_ddi = 1,
.has_fpga_dbg = 1,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h 
b/drivers/gpu/drm/i915/intel_color_manager.h
index 17fcf3d..a428825 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -72,6 +72,8 @@
 #define CHV_DEGAMMA_MSB_SHIFT  2
 #define CHV_DEGAMMA_GREEN_SHIFT16
 
+#define BDW_DEGAMMA_MAX_VALS   512
+
 /* CSC correction */
 #define CSC_DATA_STRUCT_VERSION1
 /*
-- 
1.9.1

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[Intel-gfx] [PATCH 17/23] drm/i915: CHV: Pipe level CSC correction

[Shashank Sharma]

CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.

This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC correction macros

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/i915_reg.h|  8 +++
 drivers/gpu/drm/i915/intel_color_manager.c | 99 ++
 drivers/gpu/drm/i915/intel_color_manager.h | 20 ++
 3 files changed, 127 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3dde6a8..5c7759d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7995,4 +7995,12 @@ enum skl_disp_power_wells {
 #define _PIPE_DEGAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
 
+#define PIPEA_CGM_CSC  (VLV_DISPLAY_BASE + 0x67900)
+#define PIPEB_CGM_CSC  (VLV_DISPLAY_BASE + 0x69900)
+#define PIPEC_CGM_CSC  (VLV_DISPLAY_BASE + 0x6B900)
+#define _PIPE_CSC_BASE(pipe) \
+   (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
+
+
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index e2ffbdc..22b708f 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -66,6 +66,99 @@ int intel_color_manager_set_pipe_degamma(struct drm_device 
*dev,
return 0;
 }
 
+static s16 get_csc_s3_12_format(s64 csc_value)
+{
+   s32 csc_int_value;
+   u32 csc_fract_value;
+   s16 csc_s3_12_format;
+
+   if (csc_value >= 0) {
+   csc_value += CHV_CSC_FRACT_ROUNDOFF;
+   if (csc_value > CHV_CSC_COEFF_MAX)
+   csc_value = CHV_CSC_COEFF_MAX;
+   } else {
+   csc_value = -csc_value;
+   csc_value += CHV_CSC_FRACT_ROUNDOFF;
+   if (csc_value > CHV_CSC_COEFF_MAX + 1)
+   csc_value = CHV_CSC_COEFF_MAX + 1;
+   csc_value = -csc_value;
+   }
+
+   csc_int_value = csc_value >> CHV_CSC_COEFF_SHIFT;
+   csc_int_value <<= CHV_CSC_COEFF_INT_SHIFT;
+   if (csc_value < 0)
+   csc_int_value |= CSC_COEFF_SIGN;
+   csc_fract_value = csc_value;
+   csc_fract_value >>= CHV_CSC_COEFF_FRACT_SHIFT;
+   csc_s3_12_format = csc_int_value | csc_fract_value;
+
+   return csc_s3_12_format;
+}
+
+static int chv_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
+   struct drm_crtc *crtc)
+{
+   struct drm_ctm *csc_data;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u32 reg;
+   enum pipe pipe;
+   s32 word, temp;
+   int count = 0;
+
+   if (!blob) {
+   DRM_ERROR("NULL Blob\n");
+   return -EINVAL;
+   }
+
+   if (blob->length != sizeof(struct drm_ctm)) {
+   DRM_ERROR("Invalid length of data received\n");
+   return -EINVAL;
+   }
+
+   csc_data = (struct drm_ctm *)blob->data;
+   if (csc_data->version != CSC_DATA_STRUCT_VERSION) {
+   DRM_ERROR("Invalid CSC Data struct version\n");
+   return -EINVAL;
+   }
+
+   pipe = to_intel_crtc(crtc)->pipe;
+
+   /* Disable CSC functionality */
+   reg = _PIPE_CGM_CONTROL(pipe);
+   I915_WRITE(reg, I915_READ(reg) & (~CGM_CSC_EN));
+
+   DRM_DEBUG_DRIVER("Disabled CSC Functionality on Pipe %c\n",
+   pipe_name(pipe));
+
+   reg = _PIPE_CSC_BASE(pipe);
+   while (count < CSC_MAX_VALS) {
+   word = get_csc_s3_12_format(csc_data->ctm_coeff[count]);
+
+   /*
+* Last value to be written in 1 register.
+* Otherwise, each pair of CSC values go
+* into 1 register
+*/
+   if (count != (CSC_MAX_VALS - 1)) {
+   count++;
+   temp = get_csc_s3_12_format(csc_data->ctm_coeff[count]);
+   word |= temp;
+   }
+   I915_WRITE(reg, word);
+   reg += 4;
+   count++;
+   }
+
+   DRM_DEBUG_DRIVER("All CSC values written to registers\n");
+
+   /* Enable CSC functionality */
+   reg = _PIPE_CGM_CONTROL(pipe);
+   I915_WRITE(reg, I915_READ(reg) | CGM_CSC_EN);
+   DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe));
+
+   return 0;
+}
+
 static int chv_set_degamma(struct drm_device *dev,
struct drm_property_blob *blob, struct drm_crtc *crtc)
 {
@@ -372,5 +465,11 @@ void intel_attach_color_properties_to_crtc(struct 
drm_device *dev,
DRM_DEBUG_DRIVER("palette before CTM attached to 

[Intel-gfx] [PATCH 19/23] drm/i915: Attach color properties to CRTC

[Shashank Sharma]

Function intel_attach_color_properties_to_crtc attaches a
color property to its CRTC object. This patch calls this
function from crtc initialization sequence.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_display.c | 1 +
 drivers/gpu/drm/i915/intel_drv.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9b9d267..8b5f266 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13818,6 +13818,7 @@ static void intel_crtc_init(struct drm_device *dev, int 
pipe)
intel_crtc->cursor_size = ~0;
 
intel_crtc->wm.cxsr_allowed = true;
+   intel_attach_color_properties_to_crtc(dev, _crtc->base.base);
 
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
   dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f87a99d..f992345 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1478,4 +1478,6 @@ int intel_color_manager_set_pipe_csc(struct drm_device 
*dev,
struct drm_mode_object *obj, uint32_t blob_id);
 void intel_color_manager_crtc_commit(struct drm_device *dev,
struct drm_crtc_state *crtc_state);
+void intel_attach_color_properties_to_crtc(struct drm_device *dev,
+   struct drm_mode_object *mode_obj);
 #endif /* __INTEL_DRV_H__ */
-- 
1.9.1

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[Intel-gfx] [PATCH 05/23] drm: Add structure to set/get a CTM color property

[Shashank Sharma]

From: Kausal Malladi 

Color Manager framework defines a color correction property for color
space transformation and Gamut mapping. This property is called CTM (Color
Transformation Matrix).

This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents to
configure CTM coefficients for color correction.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 include/uapi/drm/drm.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index f72b916..9580772 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -867,6 +867,18 @@ struct drm_palette {
struct drm_r32g32b32 lut[0];
 };
 
+struct drm_ctm {
+   /* Structure version. Should be 1 currently */
+   __u32 version;
+   /*
+* Each value is in S31.32 format.
+* This is 3x3 matrix in row major format.
+* Integer part will be clipped to nearest
+* max/min boundary as supported by the HW platform.
+*/
+   __s64 ctm_coeff[9];
+};
+
 /* typedef area */
 #ifndef __KERNEL__
 typedef struct drm_clip_rect drm_clip_rect_t;
-- 
1.9.1

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[Intel-gfx] [PATCH 13/23] drm/i915: CHV: Load gamma color correction values

[Shashank Sharma]

DRM color manager allows the driver to showcase its best color
correction capabilities using the cm_crtc_palette_capabilities_property.
Driver loads the no. of coefficients for various color correction
as per the platform, during the init time.

This patch adds no of coefficitents for best gamma color correction
modes possible in CHV, in device info structure, which is:
Gamma(10 bit, CGM HW unit):- 257 coeff
These values will be loaded in cm_crtc_palette_capabilities_property
during the CRTC init section, by color manager's attach function.

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_drv.c| 2 ++
 drivers/gpu/drm/i915/intel_color_manager.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bdec64c..04a8e45 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -34,6 +34,7 @@
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "intel_drv.h"
+#include "intel_color_manager.h"
 
 #include 
 #include 
@@ -349,6 +350,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+   .num_samples_after_ctm = CHV_10BIT_GAMMA_MAX_VALS,
.is_valleyview = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h 
b/drivers/gpu/drm/i915/intel_color_manager.h
index 1a42244..99ef646 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -29,3 +29,4 @@
 #include "i915_drv.h"
 
 #define COLOR_STRUCT_VERSION   1
+#define CHV_10BIT_GAMMA_MAX_VALS   257
-- 
1.9.1

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[Intel-gfx] [PATCH 20/23] drm/i915: BDW: Load gamma correction values

[Shashank Sharma]

I915 color manager registers pipe gamma correction as palette
correction after CTM property.

For BDW and higher platforms, split gamma correction is the best
gamma correction. This patch adds the no of coefficients(512) for
split gamma correction as "num_samples_after_ctm" parameter in device
info structures, for all of those.

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_drv.c| 7 +++
 drivers/gpu/drm/i915/intel_color_manager.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 03db841..69afed3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -302,6 +302,7 @@ static const struct intel_device_info 
intel_broadwell_d_info = {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+   .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -314,6 +315,7 @@ static const struct intel_device_info 
intel_broadwell_m_info = {
.gen = 8, .is_mobile = 1, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+   .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -326,6 +328,7 @@ static const struct intel_device_info 
intel_broadwell_gt3d_info = {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+   .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -338,6 +341,7 @@ static const struct intel_device_info 
intel_broadwell_gt3m_info = {
.gen = 8, .is_mobile = 1, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+   .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -363,6 +367,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+   .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -376,6 +381,7 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.gen = 9, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+   .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.has_llc = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
@@ -389,6 +395,7 @@ static const struct intel_device_info intel_broxton_info = {
.gen = 9,
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+   .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS,
.num_pipes = 3,
.has_ddi = 1,
.has_fpga_dbg = 1,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h 
b/drivers/gpu/drm/i915/intel_color_manager.h
index 6e5158e..3687989 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -42,6 +42,8 @@
 #define CHV_10BIT_GAMMA_MSB_SHIFT  6
 #define CHV_GAMMA_SHIFT_GREEN  16
 
+#define BDW_SPLITGAMMA_MAX_VALS512
+
 /* Gamma values are u8.24 format */
 #define GAMMA_INT_SHIFT24
 #define GAMMA_FRACT_SHIFT  8
-- 
1.9.1

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[Intel-gfx] [PATCH 15/23] drm/i915: CHV: Pipe level Gamma correction

[Shashank Sharma]

From: Kausal Malladi 

CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode

This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Adds Gamma correction macros

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/i915_reg.h|  12 +++
 drivers/gpu/drm/i915/intel_color_manager.c | 127 +
 drivers/gpu/drm/i915/intel_color_manager.h |  21 +
 3 files changed, 160 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67bf205..93aa1f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7977,4 +7977,16 @@ enum skl_disp_power_wells {
 #define GEN9_VEBOX_MOCS_0  0xcb00  /* Video MOCS base register*/
 #define GEN9_BLT_MOCS_00xcc00  /* Blitter MOCS base register*/
 
+/* Color Management */
+#define PIPEA_CGM_CONTROL  (VLV_DISPLAY_BASE + 0x67A00)
+#define PIPEB_CGM_CONTROL  (VLV_DISPLAY_BASE + 0x69A00)
+#define PIPEC_CGM_CONTROL  (VLV_DISPLAY_BASE + 0x6BA00)
+#define PIPEA_CGM_GAMMA(VLV_DISPLAY_BASE + 0x67000)
+#define PIPEB_CGM_GAMMA(VLV_DISPLAY_BASE + 0x69000)
+#define PIPEC_CGM_GAMMA(VLV_DISPLAY_BASE + 0x6B000)
+#define _PIPE_CGM_CONTROL(pipe) \
+   (_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL))
+#define _PIPE_GAMMA_BASE(pipe) \
+   (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index 2ba3fd7..222924d 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -66,6 +66,127 @@ int intel_color_manager_set_pipe_degamma(struct drm_device 
*dev,
return 0;
 }
 
+static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob 
*blob,
+ struct drm_crtc *crtc)
+{
+   bool flag = false;
+   enum pipe pipe;
+   u8 red_int, blue_int, green_int;
+   u16 red_fract, green_fract, blue_fract;
+   u32 red, green, blue;
+   u32 cgm_control_reg = 0;
+   u32 cgm_gamma_reg = 0;
+   u32 count = 0, num_samples, word;
+   int ret = 0, length;
+   struct drm_r32g32b32 *correction_values = NULL;
+   struct drm_palette *gamma_data;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   if (WARN_ON(!blob))
+   return -EINVAL;
+
+   gamma_data = (struct drm_palette *)blob->data;
+
+   if (gamma_data->version != GAMMA_DATA_STRUCT_VERSION) {
+   DRM_DEBUG_KMS("Invalid Gamma Data struct version\n");
+   return -EINVAL;
+   }
+
+   pipe = to_intel_crtc(crtc)->pipe;
+   num_samples = gamma_data->num_samples;
+   length = num_samples * sizeof(struct drm_r32g32b32);
+
+   switch (num_samples) {
+   case 0:
+
+   /* Disable Gamma functionality on Pipe - CGM Block */
+   cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));
+   cgm_control_reg &= ~CGM_GAMMA_EN;
+   I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);
+
+   DRM_DEBUG_DRIVER("Gamma disabled on Pipe %c\n",
+   pipe_name(pipe));
+   ret = 0;
+   break;
+
+   case CHV_8BIT_GAMMA_MAX_VALS:
+   case CHV_10BIT_GAMMA_MAX_VALS:
+
+   count = 0;
+   cgm_gamma_reg = _PIPE_GAMMA_BASE(pipe);
+   correction_values = (struct drm_r32g32b32 *)_data->lut;
+
+   while (count < num_samples) {
+   blue = correction_values[count].b32;
+   green = correction_values[count].g32;
+   red = correction_values[count].r32;
+
+   blue_int = _GAMMA_INT_PART(blue);
+   if (blue_int > GAMMA_INT_MAX)
+   blue = CHV_MAX_GAMMA;
+
+   green_int = _GAMMA_INT_PART(green);
+   if (green_int > GAMMA_INT_MAX)
+   green = CHV_MAX_GAMMA;
+
+   red_int = _GAMMA_INT_PART(red);
+   if (red_int > GAMMA_INT_MAX)
+   red = CHV_MAX_GAMMA;
+
+   blue_fract = _GAMMA_FRACT_PART(blue);
+   green_fract = _GAMMA_FRACT_PART(green);
+   red_fract = _GAMMA_FRACT_PART(red);
+
+   blue_fract >>= CHV_10BIT_GAMMA_MSB_SHIFT;
+   green_fract >>= CHV_10BIT_GAMMA_MSB_SHIFT;
+   

[Intel-gfx] [PATCH 09/23] drm/i915: Register pipe color capabilities

[Shashank Sharma]

DRM color manager contains these color properties:

1. "crtc_palette_capabilities_property": to allow a
core driver to load and showcase its color correction
capabilities to user space.
2. "ctm": Color transformation matrix property, where a
color transformation matrix of 9 correction values gets
applied as correction.
3. "palette_before_ctm": for corrections which get applied
beore color transformation matrix correction.
4. "palette_after_ctm": for corrections which get applied
after color transformation matrix correction.

Intel color manager registers:
1. Gamma correction property as "palette_after_ctm" property
2. Degamma correction capability as "palette_bafore_ctm" property
capability as "palette_after_ctm" DRM color property hook.
3. CSC as "ctm" property.

This patch does the following:
1. Add a function which loads the platform's color correction
capabilities in the cm_crtc_palette_capabilities_property structure.
2. Attaches the cm_crtc_palette_capabilities_property to every CRTC
getting initiaized.
3. Adds two new parameters "num_samples_after_ctm" and
"num_samples_before_ctm" in intel_device_info as gamma and
degamma coefficients vary per platform basis.

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_drv.h|  2 ++
 drivers/gpu/drm/i915/intel_color_manager.c | 45 ++
 drivers/gpu/drm/i915/intel_color_manager.h |  2 ++
 3 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3bf8a9b..22de2cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -798,6 +798,8 @@ struct intel_device_info {
u8 num_sprites[I915_MAX_PIPES];
u8 gen;
u8 ring_mask; /* Rings supported by the HW */
+   u16 num_samples_after_ctm;
+   u16 num_samples_before_ctm;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index 7357d99..77f58f2 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,7 +27,52 @@
 
 #include "intel_color_manager.h"
 
+int get_pipe_capabilities(struct drm_device *dev,
+   struct drm_palette_caps *palette_caps, struct drm_crtc *crtc)
+{
+   struct drm_property_blob *blob;
+
+   /*
+* This function loads best capability for gamma correction
+* For example:
+* CHV best Gamma correction (CGM unit, 10 bit)
+* has 257 entries, best degamma is 65 entries
+*/
+   palette_caps->version = COLOR_STRUCT_VERSION;
+   palette_caps->num_samples_after_ctm =
+   INTEL_INFO(dev)->num_samples_after_ctm;
+   palette_caps->num_samples_before_ctm =
+   INTEL_INFO(dev)->num_samples_before_ctm;
+   blob = drm_property_create_blob(dev, sizeof(struct drm_palette_caps),
+   (const void *) palette_caps);
+   if (IS_ERR_OR_NULL(blob)) {
+   DRM_ERROR("Create blob for capabilities failed\n");
+   return PTR_ERR(blob);
+   }
+
+   return blob->base.id;
+}
+
 void intel_attach_color_properties_to_crtc(struct drm_device *dev,
struct drm_mode_object *mode_obj)
 {
+   struct drm_mode_config *config = >mode_config;
+   struct drm_palette_caps *palette_caps;
+   struct drm_crtc *crtc;
+   int capabilities_blob_id;
+
+   crtc = obj_to_crtc(mode_obj);
+   palette_caps = kzalloc(sizeof(struct drm_palette_caps),
+   GFP_KERNEL);
+   capabilities_blob_id = get_pipe_capabilities(dev,
+   palette_caps, crtc);
+
+   if (config->cm_crtc_palette_capabilities_property) {
+   drm_object_attach_property(mode_obj,
+   config->cm_crtc_palette_capabilities_property,
+   capabilities_blob_id);
+   DRM_DEBUG_DRIVER("Capabilities attached to CRTC\n");
+   }
+
+   kfree(palette_caps);
 }
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h 
b/drivers/gpu/drm/i915/intel_color_manager.h
index 04c921d..1a42244 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -27,3 +27,5 @@
 #include 
 #include 
 #include "i915_drv.h"
+
+#define COLOR_STRUCT_VERSION   1
-- 
1.9.1

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[Intel-gfx] [PATCH 16/23] drm/i915: CHV: Pipe level degamma correction

[Shashank Sharma]

CHV/BSW supports DeGamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.

This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
   CHV/BSW platform
2. Add DeGamma correction macros/defines

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/i915_reg.h|   6 ++
 drivers/gpu/drm/i915/intel_color_manager.c | 111 +
 drivers/gpu/drm/i915/intel_color_manager.h |   6 ++
 3 files changed, 123 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93aa1f9..3dde6a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7989,4 +7989,10 @@ enum skl_disp_power_wells {
 #define _PIPE_GAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
 
+#define PIPEA_CGM_DEGAMMA  (VLV_DISPLAY_BASE + 0x66000)
+#define PIPEB_CGM_DEGAMMA  (VLV_DISPLAY_BASE + 0x68000)
+#define PIPEC_CGM_DEGAMMA  (VLV_DISPLAY_BASE + 0x6A000)
+#define _PIPE_DEGAMMA_BASE(pipe) \
+   (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index 222924d..e2ffbdc 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -66,6 +66,111 @@ int intel_color_manager_set_pipe_degamma(struct drm_device 
*dev,
return 0;
 }
 
+static int chv_set_degamma(struct drm_device *dev,
+   struct drm_property_blob *blob, struct drm_crtc *crtc)
+{
+   struct drm_palette *degamma_data;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u32 cgm_control_reg = 0;
+   u32 cgm_degamma_reg = 0;
+   enum pipe pipe;
+   u32 red, green, blue;
+   u8 red_int, green_int, blue_int;
+   u16 red_fract, green_fract, blue_fract;
+   u32 count = 0;
+   struct drm_r32g32b32 *correction_values = NULL;
+   u32 num_samples;
+   u32 word;
+   int ret = 0, length;
+
+   if (!blob) {
+   DRM_ERROR("NULL Blob\n");
+   return -EINVAL;
+   }
+
+   degamma_data = (struct drm_palette *)blob->data;
+
+   if (degamma_data->version != DEGAMMA_DATA_STRUCT_VERSION) {
+   DRM_ERROR("Invalid DeGamma Data struct version\n");
+   return -EINVAL;
+   }
+
+   pipe = to_intel_crtc(crtc)->pipe;
+   num_samples = degamma_data->num_samples;
+   length = num_samples * sizeof(struct drm_r32g32b32);
+
+   if (num_samples == 0) {
+
+   /* Disable DeGamma functionality on Pipe - CGM Block */
+   cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));
+   cgm_control_reg &= ~CGM_DEGAMMA_EN;
+   I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);
+
+   DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n",
+   pipe_name(pipe));
+   ret = 0;
+   } else if (num_samples == CHV_DEGAMMA_MAX_VALS) {
+   cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe);
+
+   count = 0;
+   correction_values = (struct drm_r32g32b32 *)_data->lut;
+   while (count < CHV_DEGAMMA_MAX_VALS) {
+   blue = correction_values[count].b32;
+   green = correction_values[count].g32;
+   red = correction_values[count].r32;
+
+   blue_int = _GAMMA_INT_PART(blue);
+   if (blue_int > GAMMA_INT_MAX)
+   blue = CHV_MAX_GAMMA;
+   green_int = _GAMMA_INT_PART(green);
+   if (green_int > GAMMA_INT_MAX)
+   green = CHV_MAX_GAMMA;
+   red_int = _GAMMA_INT_PART(red);
+   if (red_int > GAMMA_INT_MAX)
+   red = CHV_MAX_GAMMA;
+
+   blue_fract = _GAMMA_FRACT_PART(blue);
+   green_fract = _GAMMA_FRACT_PART(green);
+   red_fract = _GAMMA_FRACT_PART(red);
+
+   blue_fract >>= CHV_DEGAMMA_MSB_SHIFT;
+   green_fract >>= CHV_DEGAMMA_MSB_SHIFT;
+   red_fract >>= CHV_DEGAMMA_MSB_SHIFT;
+
+   /* Green (29:16) and Blue (13:0) in DWORD1 */
+   word = green_fract;
+   word <<= CHV_DEGAMMA_GREEN_SHIFT;
+   word = word | blue;
+   I915_WRITE(cgm_degamma_reg, word);
+
+   cgm_degamma_reg += 4;
+
+   /* Red (13:0) to be written to DWORD2 */
+   

[Intel-gfx] [PATCH 12/23] drm/i915: Add pipe CSC correction handlers

[Shashank Sharma]

This patch adds set_property and get_property handlers for pipe
level CSC color correction for CHV/BSW platform. The set
function just attaches the CSC blob to CRTC state, that later
gets committed using atomic path.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_atomic.c|  8 
 drivers/gpu/drm/i915/intel_color_manager.c | 19 +++
 drivers/gpu/drm/i915/intel_drv.h   |  3 +++
 3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index b504b4f..57eafca 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -325,6 +325,9 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
if (property == config->cm_palette_before_ctm_property)
return intel_color_manager_set_pipe_degamma(dev, state,
>base, val);
+   if (property == config->cm_ctm_property)
+   return intel_color_manager_set_pipe_csc(dev, state,
+   >base, val);
 
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
@@ -350,6 +353,11 @@ int intel_crtc_atomic_get_property(struct drm_crtc *crtc,
goto found;
}
 
+   if (property == config->cm_ctm_property) {
+   *val = (state->ctm_blob) ? state->ctm_blob->base.id : 0;
+   goto found;
+   }
+
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
 
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index 8890b09..2ba3fd7 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,25 @@
 
 #include "intel_color_manager.h"
 
+int intel_color_manager_set_pipe_csc(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state,
+   struct drm_mode_object *obj, uint32_t blob_id)
+{
+   struct drm_property_blob *blob;
+
+   blob = drm_property_lookup_blob(dev, blob_id);
+   if (!blob) {
+   DRM_ERROR("Invalid Blob ID\n");
+   return -EINVAL;
+   }
+
+   if (crtc_state->ctm_blob)
+   drm_property_unreference_blob(crtc_state->ctm_blob);
+
+   crtc_state->ctm_blob = blob;
+   return 0;
+}
+
 int intel_color_manager_set_pipe_degamma(struct drm_device *dev,
struct drm_crtc_state *crtc_state,
struct drm_mode_object *obj, uint32_t blob_id)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0298dd0..4d571a2f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1473,4 +1473,7 @@ int intel_color_manager_set_pipe_gamma(struct drm_device 
*dev,
 int intel_color_manager_set_pipe_degamma(struct drm_device *dev,
struct drm_crtc_state *crtc_state,
struct drm_mode_object *obj, uint32_t blob_id);
+int intel_color_manager_set_pipe_csc(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state,
+   struct drm_mode_object *obj, uint32_t blob_id);
 #endif /* __INTEL_DRV_H__ */
-- 
1.9.1

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[Intel-gfx] [PATCH 07/23] drm/i915: Add atomic get property interface for CRTC

[Shashank Sharma]

From: Kausal Malladi 

This patch adds atomic get property interface for Intel CRTC. This
interface will be used for get operation on any non-core DRM properties.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_atomic.c  | 9 +
 drivers/gpu/drm/i915/intel_display.c | 1 +
 drivers/gpu/drm/i915/intel_drv.h | 4 
 3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index d5b7eb1..500d2998 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -318,3 +318,12 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
 }
+
+int intel_crtc_atomic_get_property(struct drm_crtc *crtc,
+  const struct drm_crtc_state *state,
+  struct drm_property *property,
+  uint64_t *val)
+{
+   DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
+   return -EINVAL;
+}
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 444ea30..010acca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13194,6 +13194,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.page_flip = intel_crtc_page_flip,
.set_property = drm_atomic_helper_crtc_set_property,
.atomic_set_property = intel_crtc_atomic_set_property,
+   .atomic_get_property = intel_crtc_atomic_get_property,
.atomic_duplicate_state = intel_crtc_duplicate_state,
.atomic_destroy_state = intel_crtc_destroy_state,
 };
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 510f559..e27e754 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1454,6 +1454,10 @@ int intel_crtc_atomic_set_property(struct drm_crtc 
*plane,
   struct drm_crtc_state *state,
   struct drm_property *property,
   uint64_t val);
+int intel_crtc_atomic_get_property(struct drm_crtc *plane,
+  const struct drm_crtc_state *state,
+  struct drm_property *property,
+  uint64_t *val);
 
 /* intel_atomic_plane.c */
 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
-- 
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[Intel-gfx] [PATCH 11/23] drm/i915: Add pipe deGamma correction handlers

[Shashank Sharma]

This patch adds set_property and get_property handlers for deGamma
color correction capability at Pipe level.

Set function just attaches the deGamma correction blob to CRTC state, which
will be later committed in the atomic commit path.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_atomic.c| 10 ++
 drivers/gpu/drm/i915/intel_color_manager.c | 20 
 drivers/gpu/drm/i915/intel_drv.h   |  4 +++-
 3 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index 0b61fef..b504b4f 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -322,6 +322,10 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
return intel_color_manager_set_pipe_gamma(dev, state,
>base, val);
 
+   if (property == config->cm_palette_before_ctm_property)
+   return intel_color_manager_set_pipe_degamma(dev, state,
+   >base, val);
+
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
 }
@@ -340,6 +344,12 @@ int intel_crtc_atomic_get_property(struct drm_crtc *crtc,
goto found;
}
 
+   if (property == config->cm_palette_before_ctm_property) {
+   *val = (state->palette_before_ctm_blob) ?
+   state->palette_before_ctm_blob->base.id : 0;
+   goto found;
+   }
+
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
 
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index 9421bb6..8890b09 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,26 @@
 
 #include "intel_color_manager.h"
 
+int intel_color_manager_set_pipe_degamma(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state,
+   struct drm_mode_object *obj, uint32_t blob_id)
+{
+   struct drm_property_blob *blob;
+
+   blob = drm_property_lookup_blob(dev, blob_id);
+   if (!blob) {
+   DRM_ERROR("Invalid Blob ID\n");
+   return -EINVAL;
+   }
+
+   if (crtc_state->palette_before_ctm_blob)
+   drm_property_unreference_blob(
+   crtc_state->palette_before_ctm_blob);
+
+   crtc_state->palette_before_ctm_blob = blob;
+   return 0;
+}
+
 int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
struct drm_crtc_state *crtc_state,
struct drm_mode_object *obj, uint32_t blob_id)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d0193e2..0298dd0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1470,5 +1470,7 @@ extern const struct drm_plane_helper_funcs 
intel_plane_helper_funcs;
 int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
struct drm_crtc_state *crtc_state,
struct drm_mode_object *obj, uint32_t blob_id);
-
+int intel_color_manager_set_pipe_degamma(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state,
+   struct drm_mode_object *obj, uint32_t blob_id);
 #endif /* __INTEL_DRV_H__ */
-- 
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[Intel-gfx] [PATCH 18/23] drm/i915: Commit color changes to CRTC

[Shashank Sharma]

The color correction blob values are loaded during set_property
calls. This patch adds a function to find the blob and apply the
correction values to the display registers, during the atomic
commit call.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_color_manager.c | 46 ++
 drivers/gpu/drm/i915/intel_display.c   |  2 ++
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 3 files changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index 22b708f..d33a2be 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -406,6 +406,52 @@ int intel_color_manager_set_pipe_gamma(struct drm_device 
*dev,
return 0;
 }
 
+void intel_color_manager_crtc_commit(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state)
+{
+   struct drm_property_blob *blob;
+   struct drm_crtc *crtc = crtc_state->crtc;
+   int ret = -EINVAL;
+
+   blob = crtc_state->palette_after_ctm_blob;
+   if (blob) {
+   /* Gamma correction is platform specific */
+   if (IS_CHERRYVIEW(dev))
+   ret = chv_set_gamma(dev, blob, crtc);
+
+   if (ret)
+   DRM_ERROR("set Gamma correction failed\n");
+   else
+   DRM_DEBUG_DRIVER("Gamma correction success\n");
+   }
+
+   blob = crtc_state->palette_before_ctm_blob;
+   if (blob) {
+   /* degamma correction */
+   if (IS_CHERRYVIEW(dev))
+   ret = chv_set_degamma(dev, blob, crtc);
+
+   if (ret)
+   DRM_ERROR("set degamma correction failed\n");
+   else
+   DRM_DEBUG_DRIVER("degamma correction success\n");
+   }
+
+   blob = crtc_state->ctm_blob;
+   if (blob) {
+   /* CSC correction */
+   if (IS_CHERRYVIEW(dev))
+   ret = chv_set_csc(dev, blob, crtc);
+
+   if (ret)
+   DRM_ERROR("set CSC correction failed\n");
+   else
+   DRM_DEBUG_DRIVER("CSC correction success\n");
+   }
+
+}
+
+
 int get_pipe_capabilities(struct drm_device *dev,
struct drm_palette_caps *palette_caps, struct drm_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 010acca..9b9d267 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13487,6 +13487,8 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
intel_update_pipe_config(intel_crtc, old_intel_state);
else if (INTEL_INFO(dev)->gen >= 9)
skl_detach_scalers(intel_crtc);
+
+   intel_color_manager_crtc_commit(dev, crtc->state);
 }
 
 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4d571a2f..f87a99d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1476,4 +1476,6 @@ int intel_color_manager_set_pipe_degamma(struct 
drm_device *dev,
 int intel_color_manager_set_pipe_csc(struct drm_device *dev,
struct drm_crtc_state *crtc_state,
struct drm_mode_object *obj, uint32_t blob_id);
+void intel_color_manager_crtc_commit(struct drm_device *dev,
+   struct drm_crtc_state *crtc_state);
 #endif /* __INTEL_DRV_H__ */
-- 
1.9.1

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[Intel-gfx] [PATCH 08/23] drm/i915: Create color management files

[Shashank Sharma]

From: Kausal Malladi 

This patch create new files intel_color_manager.c which
will contain the core color correction code for I915 driver
and its header intel_color_manager.h

The per color property patches coming up in this patch series
will fill the appropriate functions in this file.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/Makefile  |  3 ++-
 drivers/gpu/drm/i915/intel_color_manager.c | 33 ++
 drivers/gpu/drm/i915/intel_color_manager.h | 29 ++
 3 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_color_manager.c
 create mode 100644 drivers/gpu/drm/i915/intel_color_manager.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44d290a..56caf9e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -64,7 +64,8 @@ i915-y += intel_audio.o \
  intel_overlay.o \
  intel_psr.o \
  intel_sideband.o \
- intel_sprite.o
+ intel_sprite.o \
+ intel_color_manager.o
 i915-$(CONFIG_ACPI)+= intel_acpi.o intel_opregion.o
 i915-$(CONFIG_DRM_FBDEV_EMULATION) += intel_fbdev.o
 
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
new file mode 100644
index 000..7357d99
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Shashank Sharma 
+ * Kausal Malladi 
+ */
+
+#include "intel_color_manager.h"
+
+void intel_attach_color_properties_to_crtc(struct drm_device *dev,
+   struct drm_mode_object *mode_obj)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h 
b/drivers/gpu/drm/i915/intel_color_manager.h
new file mode 100644
index 000..04c921d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Shashank Sharma 
+ * Kausal Malladi 
+ */
+#include 
+#include 
+#include "i915_drv.h"
-- 
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[Intel-gfx] [PATCH 14/23] drm/i915: CHV: Load degamma color correction values

[Shashank Sharma]

DRM color manager allows the driver to showcase its best color
correction capabilities using the cm_crtc_palette_capabilities_property.

This patch adds no of coefficitents for degamma color correction
modes possible in CHV, in device info structure, which is:
CGM Degamma(10 bit, CGM HW unit):- 65 coeff

These values will be loaded in cm_crtc_palette_capabilities_property
during the CRTC init section, by color manager's attach function.

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_drv.c| 1 +
 drivers/gpu/drm/i915/intel_color_manager.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 04a8e45..03db841 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -351,6 +351,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.num_samples_after_ctm = CHV_10BIT_GAMMA_MAX_VALS,
+   .num_samples_before_ctm = CHV_DEGAMMA_MAX_VALS,
.is_valleyview = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h 
b/drivers/gpu/drm/i915/intel_color_manager.h
index 99ef646..402b825 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -30,3 +30,4 @@
 
 #define COLOR_STRUCT_VERSION   1
 #define CHV_10BIT_GAMMA_MAX_VALS   257
+#define CHV_DEGAMMA_MAX_VALS   65
-- 
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[Intel-gfx] [PATCH 06/23] drm/i915: Add atomic set property interface for CRTC

[Shashank Sharma]

From: Kausal Malladi 

This patch adds atomic set property interface for Intel CRTC. This
interface will be used for set operation on any DRM properties.

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_atomic.c  | 9 +
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 drivers/gpu/drm/i915/intel_drv.h | 4 
 3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index f1975f2..d5b7eb1 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -309,3 +309,12 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
drm_atomic_state_default_clear(>base);
state->dpll_set = false;
 }
+
+int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
+  struct drm_crtc_state *state,
+  struct drm_property *property,
+  uint64_t val)
+{
+   DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
+   return -EINVAL;
+}
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index fc00867..444ea30 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13192,6 +13192,8 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.destroy = intel_crtc_destroy,
.page_flip = intel_crtc_page_flip,
+   .set_property = drm_atomic_helper_crtc_set_property,
+   .atomic_set_property = intel_crtc_atomic_set_property,
.atomic_duplicate_state = intel_crtc_duplicate_state,
.atomic_destroy_state = intel_crtc_destroy_state,
 };
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 02a755a..510f559 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1450,6 +1450,10 @@ intel_atomic_get_crtc_state(struct drm_atomic_state 
*state,
 int intel_atomic_setup_scalers(struct drm_device *dev,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state);
+int intel_crtc_atomic_set_property(struct drm_crtc *plane,
+  struct drm_crtc_state *state,
+  struct drm_property *property,
+  uint64_t val);
 
 /* intel_atomic_plane.c */
 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
-- 
1.9.1

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[Intel-gfx] [PATCH 23/23] drm/i915: BDW: Pipe level degamma correction

[Shashank Sharma]

BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied before Color Transformation.

This patch does the following:
1. Adds the core function to program DeGamma correction values for
   BDW/SKL/BXT platform
2. Adds DeGamma correction macros/defines

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/intel_color_manager.c | 61 ++
 1 file changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index d935fd8..46f880d 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -532,6 +532,65 @@ static int bdw_set_gamma(struct drm_device *dev, struct 
drm_property_blob *blob,
return 0;
 }
 
+static int bdw_set_degamma(struct drm_device *dev,
+   struct drm_property_blob *blob, struct drm_crtc *crtc)
+{
+   enum pipe pipe;
+   int num_samples, length;
+   int count = 0;
+   u32 index, word;
+   u32 blue, green, red;
+   u32 mode, pal_prec_index, pal_prec_data;
+   struct drm_palette *degamma_data;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct drm_r32g32b32 *correction_values = NULL;
+
+   if (WARN_ON(!blob))
+   return -EINVAL;
+
+   degamma_data = (struct drm_palette *)blob->data;
+   if (degamma_data->version != DEGAMMA_DATA_STRUCT_VERSION) {
+   DRM_ERROR("Invalid DeGamma Data struct version\n");
+   return -EINVAL;
+   }
+
+   pipe = to_intel_crtc(crtc)->pipe;
+   num_samples = degamma_data->num_samples;
+   if (num_samples != BDW_SPLITGAMMA_MAX_VALS) {
+   DRM_ERROR("Invalid number of samples\n");
+   return -EINVAL;
+   }
+
+   length = num_samples * sizeof(struct drm_r32g32b32);
+   mode = I915_READ(GAMMA_MODE(pipe));
+   pal_prec_index = _PREC_PAL_INDEX(pipe);
+   pal_prec_data = _PREC_PAL_DATA(pipe);
+
+   correction_values = (struct drm_r32g32b32 *)_data->lut;
+   index = I915_READ(pal_prec_index);
+   index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE;
+   I915_WRITE(pal_prec_index, index);
+
+   while (count < num_samples) {
+   blue = correction_values[count].b32;
+   green = correction_values[count].g32;
+   red = correction_values[count].r32;
+
+   word = bdw_write_10bit_gamma_precision(red, green, blue);
+   I915_WRITE(pal_prec_data, word);
+   count++;
+   }
+
+   /* Enable DeGamma on Pipe */
+   mode &= ~GAMMA_MODE_MODE_MASK;
+   I915_WRITE(GAMMA_MODE(pipe), mode | GAMMA_MODE_MODE_SPLIT);
+
+   DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",
+   pipe_name(pipe));
+
+   return 0;
+}
+
 static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob 
*blob,
  struct drm_crtc *crtc)
 {
@@ -700,6 +759,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
/* degamma correction */
if (IS_CHERRYVIEW(dev))
ret = chv_set_degamma(dev, blob, crtc);
+   else if (IS_BROADWELL(dev) || IS_GEN9(dev))
+   ret = bdw_set_degamma(dev, blob, crtc);
 
if (ret)
DRM_ERROR("set degamma correction failed\n");
-- 
1.9.1

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[Intel-gfx] [PATCH 21/23] drm/i915: BDW: Pipe level Gamma correction

[Shashank Sharma]

BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. 10-bit Split Gamma mode
4. 12-bit mode

This patch does the following:
1. Adds the core function to program Gamma correction values
   for BDW/SKL/BXT platforms
2. Adds Gamma correction macros/defines

Signed-off-by: Shashank Sharma 
Signed-off-by: Kausal Malladi 
---
 drivers/gpu/drm/i915/i915_reg.h|  17 +-
 drivers/gpu/drm/i915/intel_color_manager.c | 270 +
 drivers/gpu/drm/i915/intel_color_manager.h |  15 ++
 3 files changed, 300 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5c7759d..88f4e41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5634,7 +5634,9 @@ enum skl_disp_power_wells {
 
 #define _GAMMA_MODE_A  0x4a480
 #define _GAMMA_MODE_B  0x4ac80
-#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
+#define _GAMMA_MODE_C  0x4b480
+#define GAMMA_MODE(pipe) \
+   _PIPE3(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B, _GAMMA_MODE_C)
 #define GAMMA_MODE_MODE_MASK   (3 << 0)
 #define GAMMA_MODE_MODE_8BIT   (0 << 0)
 #define GAMMA_MODE_MODE_10BIT  (1 << 0)
@@ -8001,6 +8003,17 @@ enum skl_disp_power_wells {
 #define _PIPE_CSC_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
 
-
+/* BDW gamma correction */
+#define PAL_PREC_INDEX_A   0x4A400
+#define PAL_PREC_INDEX_B   0x4AC00
+#define PAL_PREC_INDEX_C   0x4B400
+#define PAL_PREC_DATA_A0x4A404
+#define PAL_PREC_DATA_B0x4AC04
+#define PAL_PREC_DATA_C0x4B404
+
+#define _PREC_PAL_INDEX(pipe) \
+   (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B, PAL_PREC_INDEX_C))
+#define _PREC_PAL_DATA(pipe) \
+   (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B, PAL_PREC_DATA_C))
 
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c 
b/drivers/gpu/drm/i915/intel_color_manager.c
index d33a2be..d935fd8 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -264,6 +264,274 @@ static int chv_set_degamma(struct drm_device *dev,
return ret;
 }
 
+static u32 bdw_write_10bit_gamma_precision(u32 red, u32 green, u32 blue)
+{
+   u32 word;
+   u8 blue_int, green_int, red_int;
+   u16 blue_fract, green_fract, red_fract;
+
+   blue_int = _GAMMA_INT_PART(blue);
+   if (blue_int > GAMMA_INT_MAX)
+   blue = BDW_MAX_GAMMA;
+
+   green_int = _GAMMA_INT_PART(green);
+   if (green_int > GAMMA_INT_MAX)
+   green = BDW_MAX_GAMMA;
+
+   red_int = _GAMMA_INT_PART(red);
+   if (red_int > GAMMA_INT_MAX)
+   red = BDW_MAX_GAMMA;
+
+   blue_fract = _GAMMA_FRACT_PART(blue);
+   green_fract = _GAMMA_FRACT_PART(green);
+   red_fract = _GAMMA_FRACT_PART(red);
+
+   blue_fract >>= BDW_10BIT_GAMMA_MSB_SHIFT;
+   green_fract >>= BDW_10BIT_GAMMA_MSB_SHIFT;
+   red_fract >>= BDW_10BIT_GAMMA_MSB_SHIFT;
+
+   /* Red (29:20) Green (19:10) and Blue (9:0) */
+   word = red_fract;
+   word <<= BDW_GAMMA_SHIFT;
+   word = word | green_fract;
+   word <<= BDW_GAMMA_SHIFT;
+   word = word | blue_fract;
+
+   return word;
+}
+
+/* Apply unity gamma for gamma reset */
+static void bdw_reset_gamma(struct drm_i915_private *dev_priv,
+   enum pipe pipe)
+{
+   u16 count = 0;
+   u32 val;
+   u32 pal_prec_data = LGC_PALETTE(pipe);
+
+   DRM_DEBUG_DRIVER("\n");
+
+   /* Reset the palette for unit gamma */
+   while (count < BDW_8BIT_GAMMA_MAX_VALS) {
+   /* Red (23:16) Green (15:8) and Blue (7:0) */
+   val = (count << 16) | (count << 8) | count;
+   I915_WRITE(pal_prec_data, val);
+   pal_prec_data += 4;
+   count++;
+   }
+}
+
+static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob 
*blob,
+  struct drm_crtc *crtc)
+{
+   u8 blue_int, green_int, red_int;
+   u16 blue_fract, green_fract, red_fract;
+   u16 blue_odd, green_odd, red_odd;
+   u16 blue_even, green_even, red_even;
+
+   enum pipe pipe;
+   int count, num_samples;
+   u32 blue, green, red;
+   u32 mode, pal_prec_index, pal_prec_data;
+   u32 index, word;
+   struct drm_palette *gamma_data;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct drm_r32g32b32 *correction_values = NULL;
+
+   if (!blob) {
+   DRM_ERROR("Null Blob\n");
+   return -EINVAL;
+   }
+
+   gamma_data = (struct drm_palette *)blob->data;
+
+   if (gamma_data->version != GAMMA_DATA_STRUCT_VERSION) {
+   

Re: [Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views

[Vivek Kasireddy]

On Wed, 16 Sep 2015 09:03:33 +0100
Chris Wilson  wrote:

> On Tue, Sep 15, 2015 at 07:05:12PM -0700, Vivek Kasireddy wrote:
> > While pinning a fb object to the display plane, only install a fence
> > if the object is using a normal view. This corresponds with the
> > behavior found in i915_gem_object_do_pin() where the fencability
> > criteria is determined only for objects with normal views.
> > 
> > Suggested-by: Tvrtko Ursulin 
> > Cc: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > Signed-off-by: Vivek Kasireddy 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c index 52fb3f2..8b3e943 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2357,7 +2357,8 @@ intel_pin_and_fence_fb_obj(struct drm_plane
> > *plane,
> >  * framebuffer compression.  For simplicity, we always
> > install
> >  * a fence as the cost is not that onerous.
> >  */
> > -   ret = i915_gem_object_get_fence(obj);
> > +   ret = view.type == I915_GGTT_VIEW_NORMAL ?
> > +   i915_gem_object_get_fence(obj) : 0;
> 
> ret = 0;
> if (vma->map_and_fenceable)
>   ret = i915_gem_object_get_fence(obj);
> 
> is how I wrote it in my patch. One day that will become
> i915_vma_get_fence().
> -Chris
Hi Chris,

Looks like your solution to this problem -- and potentially others --
is better and more comprehensive. When do you plan on sending your
patch out to the mailing list?

Thanks,
Vivek

> 

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