[Intel-gfx] ✗ Ro.CI.BAT: warning for mutex: Do not spin/queue before performing ww_mutex deadlock avoidance (rev2)

[Patchwork]

== Series Details ==

Series: mutex: Do not spin/queue before performing ww_mutex deadlock avoidance 
(rev2)
URL   : https://patchwork.freedesktop.org/series/7788/
State : warning

== Summary ==

Series 7788v2 mutex: Do not spin/queue before performing ww_mutex deadlock 
avoidance
http://patchwork.freedesktop.org/api/1.0/series/7788/revisions/2/mbox

Test gem_busy:
Subgroup basic-blt:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-vebox:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_sink_crc_basic:
skip   -> PASS   (ro-skl-i7-6700hq)

ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:179  dwarn:4   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 

Results at /archive/results/CI_IGT_test/RO_Patchwork_1030/

c17d7e8 drm-intel-nightly: 2016y-05m-26d-15h-04m-52s UTC integration manifest
1e55a3d mutex: Report recursive ww_mutex locking early

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[Intel-gfx] [PATCH i-g-t] igt_core: Search "." as final fallback for igt_fopen_data()

[Matt Roper]

Some validation teams seem to run tests out of source directories that
have been nfs mounted or rsync'd to different locations on the target
machine.  This causes the igt_srcdir that the tests were built with to
be invalid on the machine the tests get run on.  Add the current
directory as a final fallback for data file searches.

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=92248
Cc: Humberto Israel Perez Rodriguez 
Signed-off-by: Matt Roper 
---
 lib/igt_core.c | 4 
 lib/igt_core.h | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/igt_core.c b/lib/igt_core.c
index 56061c3..92a875c 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -1882,6 +1882,10 @@ FILE *__igt_fopen_data(const char* igt_srcdir, const 
char* igt_datadir,
snprintf(path, sizeof(path), "%s/%s", igt_srcdir, filename);
fp = fopen(path, "r");
}
+   if (!fp) {
+   snprintf(path, sizeof(path), "./%s", filename);
+   fp = fopen(path, "r");
+   }
 
if (!fp)
igt_critical("Could not open data file \"%s\": %s", filename,
diff --git a/lib/igt_core.h b/lib/igt_core.h
index 1b62371..5995233 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -842,8 +842,8 @@ FILE *__igt_fopen_data(const char* igt_srcdir, const char* 
igt_datadir,
  * igt_fopen_data:
  * @filename: filename to open.
  *
- * Open a datafile for test, first try from installation directory
- * then from build directory.
+ * Open a datafile for test, first try from installation directory,
+ * then from build directory, and finally from current directory.
  */
 #define igt_fopen_data(filename) \
__igt_fopen_data(IGT_SRCDIR, IGT_DATADIR, filename)
-- 
2.1.4

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[Intel-gfx] [PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v5)

[Matt Roper]

From: "Kumar, Mahesh" 

don't always use 8 ddb as minimum, instead calculate using proper
algorithm.

v2: optimizations as per Matt's comments.

v3 (by Matt):
 - Fix boolean logic for !fb test in skl_ddb_min_alloc()
 - Adjust negative tiling format comparisons in skl_ddb_min_alloc() to
   improve readability.

v4 (by Matt):
 - Rebase onto recent atomic watermark changes
 - Slight tweaks to code flow to make the logic more closely match the
   description in the bspec.

v5 (by Matt):
 - Handle minimum scanline calculation properly for 4 & 8 bpp formats.
   8bpp isn't actually possible right now, but it's listed in the bspec
   so I've included it here for forward compatibility (similar to how
   we have logic for NV12).

Cc: matthew.d.ro...@intel.com
Signed-off-by: Kumar, Mahesh 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/intel_pm.c | 68 ++---
 1 file changed, 63 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3cf36dc..00b50bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3042,6 +3042,67 @@ skl_get_total_relative_data_rate(struct intel_crtc_state 
*intel_cstate)
return total_data_rate;
 }
 
+static uint16_t
+skl_ddb_min_alloc(const struct drm_plane_state *pstate,
+ const int y)
+{
+   struct drm_framebuffer *fb = pstate->fb;
+   struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
+   uint32_t src_w, src_h;
+   uint32_t min_scanlines = 8;
+   uint8_t plane_bpp;
+
+   if (WARN_ON(!fb))
+   return 0;
+
+   /* For packed formats, no y-plane, return 0 */
+   if (y && fb->pixel_format != DRM_FORMAT_NV12)
+   return 0;
+
+   /* For Non Y-tile return 8-blocks */
+   if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
+   fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
+   return 8;
+
+   src_w = drm_rect_width(_pstate->src) >> 16;
+   src_h = drm_rect_height(_pstate->src) >> 16;
+
+   if (intel_rotation_90_or_270(pstate->rotation))
+   swap(src_w, src_h);
+
+   /* Halve UV plane width and height for NV12 */
+   if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
+   src_w /= 2;
+   src_h /= 2;
+   }
+
+   plane_bpp = y ? drm_format_plane_cpp(fb->pixel_format, 0) :
+   drm_format_plane_cpp(fb->pixel_format, 1);
+
+   if (intel_rotation_90_or_270(pstate->rotation)) {
+   switch (plane_bpp) {
+   case 1:
+   min_scanlines = 32;
+   break;
+   case 2:
+   min_scanlines = 16;
+   break;
+   case 4:
+   min_scanlines = 8;
+   break;
+   case 8:
+   min_scanlines = 4;
+   break;
+   default:
+   WARN(1, "Unsupported pixel depth %u for rotation",
+plane_bpp);
+   min_scanlines = 32;
+   }
+   }
+
+   return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
  struct skl_ddb_allocation *ddb /* out */)
@@ -3104,11 +3165,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
continue;
}
 
-   minimum[id] = 8;
-   if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
-   y_minimum[id] = 8;
-   else
-   y_minimum[id] = 0;
+   minimum[id] = skl_ddb_min_alloc(pstate, 0);
+   y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
}
 
for (i = 0; i < PLANE_CURSOR; i++) {
-- 
2.1.4

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[Intel-gfx] Regression in i915 in kernel 4.6.0-git - bisected to f21a21983ef13a031

[Larry Finger]

The latest mainline kernel (commit 3f59de0) shows a regression. The symptom is 
that as soon as the kernel is started, the display is blanked, and it is never 
turned on again. This problem was bisected to commit 
f21a21983ef13a031250c4c3f6018e29a549d0f1
("drm/i915: Splitting intel_dp_detect"). The adapter in question is the 
integrated graphics controller on a Toshiba Tecra A50 laptop. The output of 
"lspci -nnv" for that controller is as follows:



00:02.0 VGA compatible controller [0300]: Intel Corporation 4th Gen Core 
Processor Integrated Graphics Controller [8086:0416] (rev 06) (prog-if 00 [VGA 
controller])

Subsystem: Toshiba America Info Systems Device [1179:0002]
Flags: bus master, fast devsel, latency 0, IRQ 27
Memory at e000 (64-bit, non-prefetchable) [size=4M]
Memory at d000 (64-bit, prefetchable) [size=256M]
I/O ports at 4000 [size=64]
Expansion ROM at  [disabled]
Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit-
Capabilities: [d0] Power Management version 2
Capabilities: [a4] PCI Advanced Features
Kernel driver in use: i915
Kernel modules: i915

If the kernel is booted with "nomodeset", the display is normal.

I will be happy to test any patches, or to answer any further questions.

Thanks,

Larry
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[Intel-gfx] [PATCH] mutex: Report recursive ww_mutex locking early

[Chris Wilson]

Recursive locking for ww_mutexes was originally conceived as an
exception. However, it is heavily used by the DRM atomic modesetting
code. Currently, the recursive deadlock is checked after we have queued
up for a busy-spin and as we never release the lock, we spin until
kicked, whereupon the deadlock is discovered and reported.

A simple solution for the now common problem is to move the recursive
deadlock discovery to the first action when taking the ww_mutex.

Testcase: igt/kms_cursor_legacy
Suggested-by: Maarten Lankhorst 
Signed-off-by: Chris Wilson 
Cc: Peter Zijlstra 
Cc: Ingo Molnar 
Cc: Christian König 
Cc: Maarten Lankhorst 
Cc: linux-ker...@vger.kernel.org
---

Maarten suggested this as a simpler fix to the immediate problem. Imo,
we still want to perform deadlock detection within the spin in order to
catch more complicated deadlocks without osq_lock() forcing fairness!
-Chris

---
 kernel/locking/mutex.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/kernel/locking/mutex.c b/kernel/locking/mutex.c
index d60f1ba3e64f..1659398dc8f8 100644
--- a/kernel/locking/mutex.c
+++ b/kernel/locking/mutex.c
@@ -502,9 +502,6 @@ __ww_mutex_lock_check_stamp(struct mutex *lock, struct 
ww_acquire_ctx *ctx)
if (!hold_ctx)
return 0;
 
-   if (unlikely(ctx == hold_ctx))
-   return -EALREADY;
-
if (ctx->stamp - hold_ctx->stamp <= LONG_MAX &&
(ctx->stamp != hold_ctx->stamp || ctx > hold_ctx)) {
 #ifdef CONFIG_DEBUG_MUTEXES
@@ -530,6 +527,12 @@ __mutex_lock_common(struct mutex *lock, long state, 
unsigned int subclass,
unsigned long flags;
int ret;
 
+   if (use_ww_ctx) {
+   struct ww_mutex *ww = container_of(lock, struct ww_mutex, base);
+   if (unlikely(ww_ctx == READ_ONCE(ww->ctx)))
+   return -EALREADY;
+   }
+
preempt_disable();
mutex_acquire_nest(>dep_map, subclass, 0, nest_lock, ip);
 
-- 
2.8.1

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[Intel-gfx] ✗ Ro.CI.BAT: warning for kbl and gen9 workarounds (rev5)

[Patchwork]

== Series Details ==

Series: kbl and gen9 workarounds (rev5)
URL   : https://patchwork.freedesktop.org/series/7824/
State : warning

== Summary ==

Series 7824v5 kbl and gen9 workarounds
http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/5/mbox

Test gem_exec_basic:
Subgroup gtt-default:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-skl-i7-6700k)
Test kms_sink_crc_basic:
skip   -> PASS   (ro-skl-i7-6700hq)

fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i7-6700k  total:209  pass:183  dwarn:1   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:180  dwarn:3   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
fi-bdw-i7-5557u failed to connect after reboot
fi-byt-n2820 failed to connect after reboot
fi-hsw-i7-4770k failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1029/

c17d7e8 drm-intel-nightly: 2016y-05m-26d-15h-04m-52s UTC integration manifest
87be4c0 drm/i195/fbc: Add WaFbcNukeOnHostModify
8f40648 drm/i915/gen9: Add WaFbcWakeMemOn
9da082e drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
fdc35ab drm/i915/gen9: Add WaEnableChickenDCPR
1381f29 drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
ab1f052 drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
ee87a20 drm/i915/kbl: Add WaForGAMHang
46e8133 drm/i915/skl: Add WAC6entrylatency
d0b632d drm/i915/gen9: Add WaDisableSkipCaching
cfb4f0a drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
6eff6d2 drm/i915/kbl: Add WaDisableDynamicCreditSharing
7d1faa3 drm/i915/kbl: Add WaDisableGamClockGating
35d92fb drm/i915/gen9: Enable must set chicken bits in config0 reg
79f7b60 drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
f665c0b drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw, skl
1129de9 drm/i915/kbl: Add WaDisableSDEUnitClockGating
74edba7 drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
0bf8e7a drm/i915/kbl: Add WaEnableGapsTsvCreditFix
528548d drm/i915: Mimic skl with WaForceEnableNonCoherent
f4427f0 drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
851ccbac drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
7139e3a drm/i915/kbl: Add REVID macro
112a177 drm/i915/kbl: Init gen9 workarounds

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[Intel-gfx] [PATCH 23/23] drm/i195/fbc: Add WaFbcNukeOnHostModify

[Mika Kuoppala]

Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.

v2: proper workaround name

References: HSD#2227109, HSDES#1404569388
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 8 
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f3a3960f5f7..e08f29685b25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
 #define ILK_DPFC_FENCE_YOFF_MMIO(0x43218)
 #define ILK_DPFC_CHICKEN   _MMIO(0x43224)
 #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
+#define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION(1<<23)
 #define ILK_FBC_RT_BASE_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID (1<<0)
 #define   SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3ac0015f8508..c91ff8254c8e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6887,6 +6887,10 @@ static void kabylake_init_clock_gating(struct drm_device 
*dev)
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
+
+   /* WaFbcNukeOnHostModify:kbl */
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void skylake_init_clock_gating(struct drm_device *dev)
@@ -6902,6 +6906,10 @@ static void skylake_init_clock_gating(struct drm_device 
*dev)
/* WAC6entrylatency:skl */
I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
   FBC_LLC_FULLY_OPEN);
+
+   /* WaFbcNukeOnHostModify:skl */
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] [PATCH 22/23] drm/i915/gen9: Add WaFbcWakeMemOn

[Mika Kuoppala]

Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.

v2: use correct workaround name

References: HSD#2137218, HSD#2227171, HSD#2136579, BSID#883
Cc: Paulo Zanoni 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 9 +++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 280d2137f90f..2f3a3960f5f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2208,6 +2208,7 @@ enum skl_disp_power_wells {
 #define ILK_DPFC_STATUS_MMIO(0x43210)
 #define ILK_DPFC_FENCE_YOFF_MMIO(0x43218)
 #define ILK_DPFC_CHICKEN   _MMIO(0x43224)
+#define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
 #define ILK_FBC_RT_BASE_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID (1<<0)
 #define   SNB_FBC_FRONT_BUFFER (1<<1)
@@ -6053,6 +6054,7 @@ enum skl_disp_power_wells {
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
_CHICKEN_PIPESL_1_B)
 
 #define DISP_ARB_CTL   _MMIO(0x45000)
+#define  DISP_FBC_MEMORY_WAKE  (1<<31)
 #define  DISP_TILE_SURFACE_SWIZZLING   (1<<13)
 #define  DISP_FBC_WM_DIS   (1<<15)
 #define DISP_ARB_CTL2  _MMIO(0x45004)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 416a1a356dec..3ac0015f8508 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -70,8 +70,13 @@ static void gen9_init_clock_gating(struct drm_device *dev)
   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
-   I915_WRITE(DISP_ARB_CTL,
-  I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
+   /* WaFbcWakeMemOn:skl,bxt,kbl */
+   I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+  DISP_FBC_WM_DIS |
+  DISP_FBC_MEMORY_WAKE);
+
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_DISABLE_DUMMY0);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] [PATCH 21/23] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

[Mika Kuoppala]

According to bspec this prevents screen corruption when fbc is
used.

v2: This workaround has a name, use it (Ville)

References: HSD#213, HSD#2137270, BSID#562
Cc: Paulo Zanoni 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2da09adb8d3d..416a1a356dec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -68,6 +68,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
/* WaEnableChickenDCPR:skl,bxt,kbl */
I915_WRITE(GEN8_CHICKEN_DCPR_1,
   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+
+   /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
+   I915_WRITE(DISP_ARB_CTL,
+  I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
@@ -2799,7 +2803,7 @@ static void ilk_write_wm_values(struct drm_i915_private 
*dev_priv,
 
if (dirty & WM_DIRTY_FBC) {
val = I915_READ(DISP_ARB_CTL);
-   if (results->enable_fbc_wm)
+   if (!IS_GEN9(dev) && results->enable_fbc_wm)
val &= ~DISP_FBC_WM_DIS;
else
val |= DISP_FBC_WM_DIS;
-- 
2.5.0

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[Intel-gfx] [PATCH 20/23] drm/i915/gen9: Add WaEnableChickenDCPR

[Mika Kuoppala]

Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.

v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 509238561935..280d2137f90f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6066,6 +6066,9 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE(1<<4)
 
+#define GEN8_CHICKEN_DCPR_1_MMIO(0x46430)
+#define   MASK_WAKEMEM (1<<13)
+
 #define SKL_DFSM   _MMIO(0x51000)
 #define SKL_DFSM_CDCLK_LIMIT_MASK  (3 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_675   (0 << 23)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 04b0a5fdccd8..2da09adb8d3d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -64,6 +64,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 
I915_WRITE(GEN8_CONFIG0,
   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
+
+   /* WaEnableChickenDCPR:skl,bxt,kbl */
+   I915_WRITE(GEN8_CHICKEN_DCPR_1,
+  I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] ✗ Ro.CI.BAT: warning for kbl and gen9 workarounds

[Patchwork]

== Series Details ==

Series: kbl and gen9 workarounds
URL   : https://patchwork.freedesktop.org/series/7824/
State : warning

== Summary ==

Series 7824v1 kbl and gen9 workarounds
http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/1/mbox

Test drv_module_reload_basic:
pass   -> SKIP   (ro-skl-i7-6700hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-skl-i7-6700k)
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-hsw-i7-4770k)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_sink_crc_basic:
skip   -> PASS   (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i7-6700k  total:209  pass:183  dwarn:1   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:181  dwarn:1   dfail:0   fail:0   skip:22 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
fi-byt-n2820 failed to connect after reboot
ro-ilk1-i5-650 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1027/

c17d7e8 drm-intel-nightly: 2016y-05m-26d-15h-04m-52s UTC integration manifest
9ad30ac drm/i195/fbc: Enable wa to prevent fbc corruption with skl and kbl
335ebfa drm/i915/gen9: Prevent fbc corruption/system hangs with high bw
4bc5809 drm/i915/gen9: Set fbc watermarks disabled
aeca8b0 drm/i915/gen9: Set wa for display underrun issues with Y & Yf Tiling.
d217b10 drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
cdd5209 drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
3a8fffa drm/i915/kbl: Add WaForGAMHang
1638d63 drm/i915/skl: Add WAC6entrylatency
d2d65e2 drm/i915/gen9: Add WaDisableSkipCaching
d258bd6 drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
eb97dc4 drm/i915/kbl: Add WaDisableDynamicCreditSharing
24c329e drm/i915/kbl: Add WaDisableGamClockGating
b30fa1a drm/i915/gen9: Enable must set chicken bits in config0 reg
794122fd drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
4f52225 drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw, skl
a187094 drm/i915/kbl: Add WaDisableSDEUnitClockGating
97483e1 drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
7c8be959 drm/i915/kbl: Add WaEnableGapsTsvCreditFix
6e9f99e drm/i915: Mimic skl with WaForceEnableNonCoherent
9d5d6bc drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
f85b90e drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
c629726 drm/i915/kbl: Add REVID macro
f66b182 drm/i915/kbl: Init gen9 workarounds

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[Intel-gfx] [PATCH igt v3] lib: Add simple sysfs accessors

[Chris Wilson]

igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for
reading.

v2: Lots of little bugs in igt_sysfs_get()
v3: Pass device to open, stop assuming Intel rules.
v4: Test opening and reading!

Signed-off-by: Chris Wilson 
---
 lib/Makefile.sources |   2 +
 lib/igt_sysfs.c  | 205 +++
 lib/igt_sysfs.h  |  34 +
 3 files changed, 241 insertions(+)
 create mode 100644 lib/igt_sysfs.c
 create mode 100644 lib/igt_sysfs.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 1316fd2..f50ff4d 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -16,6 +16,8 @@ libintel_tools_la_SOURCES =   \
igt_gt.h\
igt_stats.c \
igt_stats.h \
+   igt_sysfs.c \
+   igt_sysfs.h \
instdone.c  \
instdone.h  \
intel_batchbuffer.c \
diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
new file mode 100644
index 000..e9dba0a
--- /dev/null
+++ b/lib/igt_sysfs.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "igt_sysfs.h"
+
+static int readN(int fd, char *buf, int len)
+{
+   int total = 0;
+   do {
+   int ret = read(fd, buf + total, len - total);
+   if (ret < 0 && (errno == EINTR || errno == EAGAIN))
+   continue;
+
+   if (ret <= 0)
+   return total ?: ret;
+
+   total += ret;
+   } while (1);
+}
+
+static int writeN(int fd, const char *buf, int len)
+{
+   int total = 0;
+   do {
+   int ret = write(fd, buf + total, len - total);
+   if (ret < 0 && (errno == EINTR || errno == EAGAIN))
+   continue;
+
+   if (ret <= 0)
+   return total ?: ret;
+
+   total += ret;
+   } while (1);
+}
+
+/**
+ * igt_sysfs_open:
+ * @device: fd of the device (or -1 to default to Intel)
+ *
+ * This opens the sysfs directory corresponding to device for use
+ * with igt_sysfs_set() and igt_sysfs_get().
+ *
+ * Returns:
+ * The directory fd, or -1 on failure.
+ */
+int igt_sysfs_open(int fd, int *idx)
+{
+   char device[80];
+   char path[80];
+   struct stat st;
+
+   device[0] = '\0';
+   if (fd != -1) {
+   if (fstat(fd, ) || !S_ISCHR(st.st_mode))
+   return -1;
+
+   sprintf(device, "%d:%d", major(st.st_rdev), minor(st.st_rdev));
+   }
+
+   for (int n = 0; n < 16; n++) {
+   int len = sprintf(path, "/sys/class/drm/card%d", n);
+   if (device[0]) {
+   char tmp[80];
+   int ret;
+
+   sprintf(path + len, "/dev");
+   fd = open(path, O_RDONLY);
+   if (fd == -1)
+   continue;
+
+   ret = read(fd, tmp, sizeof(tmp-1));
+   if (ret < 0)
+   ret = 0;
+   tmp[ret] = '\0';
+   while (ret > 0 && tmp[ret-1] == '\n')
+   tmp[--ret] = '\0';
+   close(fd);
+
+   if (strcmp(tmp, device))
+   continue;
+   } else {
+   /* Bleh. Search for intel */
+   sprintf(path + len, "/error");
+   if (stat(path, ))
+   continue;
+   }
+
+   path[len] = '\0';
+   if (idx)
+   *idx 

Re: [Intel-gfx] [PATCH 21/23] drm/i915/gen9: Set fbc watermarks disabled

[Ville Syrjälä]

On Thu, May 26, 2016 at 06:53:18PM +0300, Ville Syrjälä wrote:
> On Thu, May 26, 2016 at 06:29:44PM +0300, Mika Kuoppala wrote:
> > According to bspec this prevents screen corruption when fbc is
> > used.
> > 
> > References: HSD#213, HSD#2137270
> > Cc: Paulo Zanoni 
> > Signed-off-by: Mika Kuoppala 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 262180c0ba70..62734a16e873 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -67,6 +67,9 @@ static void gen9_init_clock_gating(struct drm_device *dev)
> >  
> > I915_WRITE(GEN8_CHICKEN_DCPR_1,
> >I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> > +
> > +   I915_WRITE(DISP_ARB_CTL,
> > +  I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
> 
> Hmm I thought that FBC WM doesn't exist anymore on SKL+. I'm pretty sure
> we don't have any code for it at least.

Hmm. I guess the bit still does something though.

Do we want to start using the bspec w/a IDs in comments?

Hmm. w/a db seems to have a name for this FBC stuff as well. This one
looks like
WaFbcTurnOffFbcWatermark

> 
> >  }
> >  
> >  static void bxt_init_clock_gating(struct drm_device *dev)
> > @@ -2798,7 +2801,7 @@ static void ilk_write_wm_values(struct 
> > drm_i915_private *dev_priv,
> >  
> > if (dirty & WM_DIRTY_FBC) {
> > val = I915_READ(DISP_ARB_CTL);
> > -   if (results->enable_fbc_wm)
> > +   if (!IS_GEN9(dev) && results->enable_fbc_wm)
> 
> That code won't even run SKL+.
> 
> > val &= ~DISP_FBC_WM_DIS;
> > else
> > val |= DISP_FBC_WM_DIS;
> > -- 
> > 2.5.0
> > 
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> ___
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Re: [Intel-gfx] [PATCH 21/23] drm/i915/gen9: Set fbc watermarks disabled

[Ville Syrjälä]

On Thu, May 26, 2016 at 06:29:44PM +0300, Mika Kuoppala wrote:
> According to bspec this prevents screen corruption when fbc is
> used.
> 
> References: HSD#213, HSD#2137270
> Cc: Paulo Zanoni 
> Signed-off-by: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 262180c0ba70..62734a16e873 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -67,6 +67,9 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>  
>   I915_WRITE(GEN8_CHICKEN_DCPR_1,
>  I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> +
> + I915_WRITE(DISP_ARB_CTL,
> +I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);

Hmm I thought that FBC WM doesn't exist anymore on SKL+. I'm pretty sure
we don't have any code for it at least.

>  }
>  
>  static void bxt_init_clock_gating(struct drm_device *dev)
> @@ -2798,7 +2801,7 @@ static void ilk_write_wm_values(struct drm_i915_private 
> *dev_priv,
>  
>   if (dirty & WM_DIRTY_FBC) {
>   val = I915_READ(DISP_ARB_CTL);
> - if (results->enable_fbc_wm)
> + if (!IS_GEN9(dev) && results->enable_fbc_wm)

That code won't even run SKL+.

>   val &= ~DISP_FBC_WM_DIS;
>   else
>   val |= DISP_FBC_WM_DIS;
> -- 
> 2.5.0
> 
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[Intel-gfx] [PATCH 17/23] drm/i915/kbl: Add WaForGAMHang

[Mika Kuoppala]

Add this workaround for A0 and B0 revisions

References: HSD#2226935
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c | 36 ++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 819adbdee1c2..0612b6c8ffcf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1674,9 +1674,10 @@ static int gen8_emit_flush_render(struct 
drm_i915_gem_request *request,
struct intel_ringbuffer *ringbuf = request->ringbuf;
struct intel_engine_cs *engine = ringbuf->engine;
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
-   bool vf_flush_wa = false;
+   bool vf_flush_wa = false, dc_flush_wa = false;
u32 flags = 0;
int ret;
+   int len;
 
flags |= PIPE_CONTROL_CS_STALL;
 
@@ -1703,9 +1704,21 @@ static int gen8_emit_flush_render(struct 
drm_i915_gem_request *request,
 */
if (IS_GEN9(request->i915))
vf_flush_wa = true;
+
+   /* WaForGAMHang:kbl */
+   if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
+   dc_flush_wa = true;
}
 
-   ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
+   len = 6;
+
+   if (vf_flush_wa)
+   len += 6;
+
+   if (dc_flush_wa)
+   len += 12;
+
+   ret = intel_ring_begin(request, len);
if (ret)
return ret;
 
@@ -1718,12 +1731,31 @@ static int gen8_emit_flush_render(struct 
drm_i915_gem_request *request,
intel_logical_ring_emit(ringbuf, 0);
}
 
+   if (dc_flush_wa) {
+   intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+   intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE);
+   intel_logical_ring_emit(ringbuf, 0);
+   intel_logical_ring_emit(ringbuf, 0);
+   intel_logical_ring_emit(ringbuf, 0);
+   intel_logical_ring_emit(ringbuf, 0);
+   }
+
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
intel_logical_ring_emit(ringbuf, flags);
intel_logical_ring_emit(ringbuf, scratch_addr);
intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, 0);
+
+   if (dc_flush_wa) {
+   intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+   intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL);
+   intel_logical_ring_emit(ringbuf, 0);
+   intel_logical_ring_emit(ringbuf, 0);
+   intel_logical_ring_emit(ringbuf, 0);
+   intel_logical_ring_emit(ringbuf, 0);
+   }
+
intel_logical_ring_advance(ringbuf);
 
return 0;
-- 
2.5.0

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[Intel-gfx] [PATCH 20/23] drm/i915/gen9: Set wa for display underrun issues with Y & Yf Tiling.

[Mika Kuoppala]

Set this on all gen9 as stated by bspec.

References: HSD#2136383
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 509238561935..280d2137f90f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6066,6 +6066,9 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE(1<<4)
 
+#define GEN8_CHICKEN_DCPR_1_MMIO(0x46430)
+#define   MASK_WAKEMEM (1<<13)
+
 #define SKL_DFSM   _MMIO(0x51000)
 #define SKL_DFSM_CDCLK_LIMIT_MASK  (3 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_675   (0 << 23)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 04b0a5fdccd8..262180c0ba70 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -64,6 +64,9 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 
I915_WRITE(GEN8_CONFIG0,
   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
+
+   I915_WRITE(GEN8_CHICKEN_DCPR_1,
+  I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] [PATCH 12/23] drm/i915/kbl: Add WaDisableGamClockGating

[Mika Kuoppala]

According to bspec we need to disable gam unit clock gating on
on kbl revids A0 and B0.

References: HSD#2226858, HSD#1944358
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 5 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cba851370ec..14e0ec818ea4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6937,6 +6937,7 @@ enum skl_disp_power_wells {
 #defineEDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
 
 #define GEN6_UCGCTL1   _MMIO(0x9400)
+# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE   (1 << 22)
 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE   (1 << 5)
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE(1 << 7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b40f9dbbb215..8291f32db76e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6869,6 +6869,11 @@ static void kabylake_init_clock_gating(struct drm_device 
*dev)
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+   /* WaDisableGamClockGating:kbl */
+   if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+   I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+  GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void skylake_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] [PATCH 13/23] drm/i915/kbl: Add WaDisableDynamicCreditSharing

[Mika Kuoppala]

Bspec states that we need to turn off dynamic credit
sharing on kbl revid a0 and b0. This happens by writing bit 28
on 0x4ab8.

References: HSD#2225601, HSD#2226938, HSD#2225763
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 14e0ec818ea4..e0441da08201 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1672,6 +1672,8 @@ enum skl_disp_power_wells {
 
 #define GEN7_TLB_RD_ADDR   _MMIO(0x4700)
 
+#define GAMT_CHKN_BIT_REG  _MMIO(0x4ab8)
+
 #if 0
 #define PRB0_TAIL  _MMIO(0x2030)
 #define PRB0_HEAD  _MMIO(0x2034)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 64922ae9bd69..402e0feb4cca 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1188,6 +1188,10 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaDisableDynamicCreditSharing:kbl */
+   if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+   WA_SET_BIT(GAMT_CHKN_BIT_REG, (1 << 28));
+
/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
WA_SET_BIT_MASKED(HDC_CHICKEN0,
-- 
2.5.0

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[Intel-gfx] [PATCH 18/23] drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl

[Mika Kuoppala]

We need this gafs bit to be enabled for hw fix to
take effect.

References: HSD#2227156, HSD#2227050
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77f5edc5f915..509238561935 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6084,6 +6084,7 @@ enum skl_disp_power_wells {
 
 #define GEN9_CS_DEBUG_MODE1_MMIO(0x20ec)
 #define GEN8_CS_CHICKEN1   _MMIO(0x2580)
+#define GEN8_CS_CHICKEN2   _MMIO(0x2194)
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d60b7a3ebb47..234f0e288f44 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1118,6 +1118,9 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+   /* WaDisableGafsUnitClkGating:skl */
+   WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));
+
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
@@ -1215,6 +1218,9 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
+   /* WaDisableGafsUnitClkGating:kbl */
+   WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));
+
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
-- 
2.5.0

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[Intel-gfx] [PATCH 15/23] drm/i915/gen9: Add WaDisableSkipCaching

[Mika Kuoppala]

Make sure that we never enable skip caching on gen9 by
accident.

References: HSD#2134698
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_mocs.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
b/drivers/gpu/drm/i915/intel_mocs.c
index b765c75f3fcd..8f96c40e415c 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -156,6 +156,16 @@ static bool get_mocs_settings(struct drm_i915_private 
*dev_priv,
  "Platform that should have a MOCS table does not.\n");
}
 
+   /* WaDisableSkipCaching:skl,bxt,kbl */
+   if (IS_GEN9(dev_priv)) {
+   int i;
+
+   for (i = 0; i < table->size; i++)
+   if (WARN_ON(table->table[i].l3cc_value &
+   (L3_ESC(1) || L3_SCC(0x7
+   return false;
+   }
+
return result;
 }
 
-- 
2.5.0

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[Intel-gfx] [PATCH 10/23] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL

[Mika Kuoppala]

Extend the scope of this workaround, already used in skl,
to also take effect in kbl.

References: HSD#2132677
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c|  5 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 98cb1f178e3e..ffad2840b72f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2717,6 +2717,9 @@ struct drm_i915_cmd_table {
 
 #define KBL_REVID_A0   0x0
 #define KBL_REVID_B0   0x1
+#define KBL_REVID_C0   0x2
+#define KBL_REVID_D0   0x3
+#define KBL_REVID_E0   0x3
 
 #define IS_KBL_REVID(p, since, until) \
(IS_KABYLAKE(p) && IS_REVID(p, since, until))
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c5e0094d0e75..819adbdee1c2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1081,12 +1081,13 @@ static inline int gen8_emit_flush_coherentl3_wa(struct 
intel_engine_cs *engine,
uint32_t l3sqc4_flush = (0x4040 | GEN8_LQSC_FLUSH_COHERENT_LINES);
 
/*
-* WaDisableLSQCROPERFforOCL:skl
+* WaDisableLSQCROPERFforOCL:skl,kbl
 * This WA is implemented in skl_init_clock_gating() but since
 * this batch updates GEN8_L3SQCREG4 with default value we need to
 * set this bit here to retain the WA during flush.
 */
-   if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
+   if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0) ||
+   IS_KBL_REVID(engine->i915, 0, KBL_REVID_E0))
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
 
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 195943f77d04..64922ae9bd69 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1193,6 +1193,19 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(HDC_CHICKEN0,
  HDC_FENCE_DEST_SLM_DISABLE);
 
+   /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
+* involving this register should also be added to WA batch as required.
+*/
+   if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
+   /* WaDisableLSQCROPERFforOCL:kbl */
+   I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+  GEN8_LQSC_RO_PERF_DIS);
+
+   /* WaDisableLSQCROPERFforOCL:kbl */
+   ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
2.5.0

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[Intel-gfx] [PATCH 23/23] drm/i195/fbc: Enable wa to prevent fbc corruption with skl and kbl

[Mika Kuoppala]

Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.

References: HSDES#1404569388
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f3a3960f5f7..e08f29685b25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
 #define ILK_DPFC_FENCE_YOFF_MMIO(0x43218)
 #define ILK_DPFC_CHICKEN   _MMIO(0x43224)
 #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
+#define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION(1<<23)
 #define ILK_FBC_RT_BASE_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID (1<<0)
 #define   SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6bd73fb5c4bb..a6606156a40f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6884,6 +6884,9 @@ static void kabylake_init_clock_gating(struct drm_device 
*dev)
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
+
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void skylake_init_clock_gating(struct drm_device *dev)
@@ -6899,6 +6902,9 @@ static void skylake_init_clock_gating(struct drm_device 
*dev)
/* WAC6entrylatency:skl */
I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
   FBC_LLC_FULLY_OPEN);
+
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] [PATCH 16/23] drm/i915/skl: Add WAC6entrylatency

[Mika Kuoppala]

This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.

References: HSD#4712857
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ec31eca06807..77f5edc5f915 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2166,6 +2166,9 @@ enum skl_disp_power_wells {
 
 #define FBC_LL_SIZE(1536)
 
+#define FBC_LLC_READ_CTRL  _MMIO(0x9044)
+#define   FBC_LLC_FULLY_OPEN   (1<<30)
+
 /* Framebuffer compression for GM45+ */
 #define DPFC_CB_BASE   _MMIO(0x3200)
 #define DPFC_CONTROL   _MMIO(0x3208)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8291f32db76e..04b0a5fdccd8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6885,6 +6885,10 @@ static void skylake_init_clock_gating(struct drm_device 
*dev)
/* WaKVMNotificationOnConfigChange:skl */
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+
+   /* WAC6entrylatency:skl */
+   I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+  FBC_LLC_FULLY_OPEN);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] [PATCH 08/23] drm/i915/kbl: Add WaDisableSDEUnitClockGating

[Mika Kuoppala]

Add this workaround until upto kbl revid B0.

References: HSD#1802092
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b6dfd0264950..fc34add6ab82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6849,11 +6849,25 @@ static void gen8_set_l3sqc_credits(struct 
drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static void kabylake_init_clock_gating(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   /* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */
+   I915_WRITE(CHICKEN_PAR1_1,
+  I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+
+   /* WaDisableSDEUnitClockGating:kbl */
+   if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+}
+
 static void skylake_init_clock_gating(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */
+   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
I915_WRITE(CHICKEN_PAR1_1,
   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 }
@@ -7319,7 +7333,7 @@ void intel_init_clock_gating_hooks(struct 
drm_i915_private *dev_priv)
if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = skylake_init_clock_gating;
+   dev_priv->display.init_clock_gating = 
kabylake_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
-- 
2.5.0

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[Intel-gfx] [PATCH 05/23] drm/i915: Mimic skl with WaForceEnableNonCoherent

[Mika Kuoppala]

Past evidence with system hangs and hsds tie
WaForceEnableNonCoherent and WaDisableHDCInvalidation to
WaForceContextSaveRestoreNonCoherent. Documentation
states that WaForceContextSaveRestoreNonCoherent would
not be needed on skl past E0 but evidence proved otherwise. See
commit <510650e8b2ab> ("drm/i915/skl: Fix spurious gpu hang with gt3/gt4
revs"). In this scope consider kbl to be skl with a bigger revision than
E0 so play it safe and bind these two workarounds to the
WaForceContextSaveRestoreNonCoherent, and apply to all gen9.

References: HSD#2134449, HSD#2131413
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++--
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 47557bd34945..91d5d093f3cb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -972,6 +972,27 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 
+   /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
+* both tied to WaForceContextSaveRestoreNonCoherent
+* in some hsds for skl. We keep the tie for all gen9. The
+* documentation is a bit hazy and so we want to get common behaviour,
+* even tho there is no clear evidence we would need both on kbl/bxt.
+* This area has been source of system hangs so we play it safe
+* and mimic the skl regarless of what bspec says.
+*
+* Use Force Non-Coherent whenever executing a 3D context. This
+* is a workaround for a possible hang in the unlikely event
+* a TLB invalidation occurs during a PSD flush.
+*/
+
+   /* WaForceEnableNonCoherent:skl,bxt,kbl */
+   WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_NON_COHERENT);
+
+   /* WaDisableHDCInvalidation:skl,bxt,kbl */
+   I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+  BDW_DISABLE_HDC_INVALIDATION);
+
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
if (IS_SKYLAKE(dev_priv) ||
IS_KABYLAKE(dev_priv) ||
@@ -1084,22 +1105,6 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(HIZ_CHICKEN,
  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
-   /* This is tied to WaForceContextSaveRestoreNonCoherent */
-   if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
-   /*
-*Use Force Non-Coherent whenever executing a 3D context. This
-* is a workaround for a possible hang in the unlikely event
-* a TLB invalidation occurs during a PSD flush.
-*/
-   /* WaForceEnableNonCoherent:skl */
-   WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FORCE_NON_COHERENT);
-
-   /* WaDisableHDCInvalidation:skl */
-   I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-  BDW_DISABLE_HDC_INVALIDATION);
-   }
-
/* WaBarrierPerformanceFixDisable:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
WA_SET_BIT_MASKED(HDC_CHICKEN0,
-- 
2.5.0

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[Intel-gfx] [PATCH 09/23] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw, skl

[Mika Kuoppala]

According to bspec this workaround helps to reduce lag and improve
performance on edp.

References: HSD#2134579
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 8 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e3077259541a..1f84c2ff3563 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6035,6 +6035,9 @@ enum skl_disp_power_wells {
 #define  FORCE_ARB_IDLE_PLANES (1 << 14)
 #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
 
+#define CHICKEN_PAR2_1 _MMIO(0x42090)
+#define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
+
 #define _CHICKEN_PIPESL_1_A0x420b0
 #define _CHICKEN_PIPESL_1_B0x420b4
 #define  HSW_FBCQ_DIS  (1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fc34add6ab82..5d9b7ff9dc18 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6870,6 +6870,10 @@ static void skylake_init_clock_gating(struct drm_device 
*dev)
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
I915_WRITE(CHICKEN_PAR1_1,
   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+
+   /* WaKVMNotificationOnConfigChange:skl */
+   I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
+  | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)
@@ -6916,6 +6920,10 @@ static void broadwell_init_clock_gating(struct 
drm_device *dev)
 */
I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
 
+   /* WaKVMNotificationOnConfigChange:bdw */
+   I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
+  | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+
lpt_init_clock_gating(dev);
 }
 
-- 
2.5.0

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[Intel-gfx] [PATCH 22/23] drm/i915/gen9: Prevent fbc corruption/system hangs with high bw

[Mika Kuoppala]

Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.

References: HSD#2137218, HSD#2227171, HSD#2136579
Cc: Paulo Zanoni 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 8 ++--
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 280d2137f90f..2f3a3960f5f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2208,6 +2208,7 @@ enum skl_disp_power_wells {
 #define ILK_DPFC_STATUS_MMIO(0x43210)
 #define ILK_DPFC_FENCE_YOFF_MMIO(0x43218)
 #define ILK_DPFC_CHICKEN   _MMIO(0x43224)
+#define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
 #define ILK_FBC_RT_BASE_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID (1<<0)
 #define   SNB_FBC_FRONT_BUFFER (1<<1)
@@ -6053,6 +6054,7 @@ enum skl_disp_power_wells {
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
_CHICKEN_PIPESL_1_B)
 
 #define DISP_ARB_CTL   _MMIO(0x45000)
+#define  DISP_FBC_MEMORY_WAKE  (1<<31)
 #define  DISP_TILE_SURFACE_SWIZZLING   (1<<13)
 #define  DISP_FBC_WM_DIS   (1<<15)
 #define DISP_ARB_CTL2  _MMIO(0x45004)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62734a16e873..6bd73fb5c4bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -68,8 +68,12 @@ static void gen9_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN8_CHICKEN_DCPR_1,
   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
-   I915_WRITE(DISP_ARB_CTL,
-  I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
+   I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+  DISP_FBC_WM_DIS |
+  DISP_FBC_MEMORY_WAKE);
+
+   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+  ILK_DPFC_DISABLE_DUMMY0);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[Intel-gfx] [PATCH 11/23] drm/i915/gen9: Enable must set chicken bits in config0 reg

[Mika Kuoppala]

The bspec states that these must be set in CONFIG0 for all gen9.

References: HSD#2134995
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 22 ++
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1f84c2ff3563..5cba851370ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ECOCHK_PPGTT_WT_HSW  (0x2<<3)
 #define   ECOCHK_PPGTT_WB_HSW  (0x3<<3)
 
+#define GEN8_CONFIG0   _MMIO(0xD00)
+#define  GEN9_DEFAULT_FIXES(1<<3 | 1<<2 | 1 << 1)
+
 #define GAC_ECO_BITS   _MMIO(0x14090)
 #define   ECOBITS_SNB_BIT  (1<<13)
 #define   ECOBITS_PPGTT_CACHE64B   (3<<8)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d9b7ff9dc18..b40f9dbbb215 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -54,14 +54,24 @@
 #define INTEL_RC6p_ENABLE  (1<<1)
 #define INTEL_RC6pp_ENABLE (1<<2)
 
-static void bxt_init_clock_gating(struct drm_device *dev)
+static void gen9_init_clock_gating(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   /* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */
+   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
I915_WRITE(CHICKEN_PAR1_1,
   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
+   I915_WRITE(GEN8_CONFIG0,
+  I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
+}
+
+static void bxt_init_clock_gating(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   gen9_init_clock_gating(dev);
+
/* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -6853,9 +6863,7 @@ static void kabylake_init_clock_gating(struct drm_device 
*dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   /* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */
-   I915_WRITE(CHICKEN_PAR1_1,
-  I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+   gen9_init_clock_gating(dev);
 
/* WaDisableSDEUnitClockGating:kbl */
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
@@ -6867,9 +6875,7 @@ static void skylake_init_clock_gating(struct drm_device 
*dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
-   I915_WRITE(CHICKEN_PAR1_1,
-  I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+   gen9_init_clock_gating(dev);
 
/* WaKVMNotificationOnConfigChange:skl */
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
-- 
2.5.0

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[Intel-gfx] [PATCH 21/23] drm/i915/gen9: Set fbc watermarks disabled

[Mika Kuoppala]

According to bspec this prevents screen corruption when fbc is
used.

References: HSD#213, HSD#2137270
Cc: Paulo Zanoni 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_pm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 262180c0ba70..62734a16e873 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -67,6 +67,9 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 
I915_WRITE(GEN8_CHICKEN_DCPR_1,
   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+
+   I915_WRITE(DISP_ARB_CTL,
+  I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
@@ -2798,7 +2801,7 @@ static void ilk_write_wm_values(struct drm_i915_private 
*dev_priv,
 
if (dirty & WM_DIRTY_FBC) {
val = I915_READ(DISP_ARB_CTL);
-   if (results->enable_fbc_wm)
+   if (!IS_GEN9(dev) && results->enable_fbc_wm)
val &= ~DISP_FBC_WM_DIS;
else
val |= DISP_FBC_WM_DIS;
-- 
2.5.0

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[Intel-gfx] [PATCH 06/23] drm/i915/kbl: Add WaEnableGapsTsvCreditFix

[Mika Kuoppala]

We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.

References: HSD#2126660
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 91d5d093f3cb..3902700d37ef 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1000,6 +1000,13 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
+   /* WaEnableGapsTsvCreditFix:skl,kbl */
+   if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER) ||
+   IS_KABYLAKE(dev_priv)) {
+   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+  GEN9_GAPS_TSV_CREDIT_DISABLE));
+   }
+
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
@@ -1094,12 +1101,6 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
   GEN8_LQSC_RO_PERF_DIS);
 
-   /* WaEnableGapsTsvCreditFix:skl */
-   if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
-   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-  GEN9_GAPS_TSV_CREDIT_DISABLE));
-   }
-
/* WaDisablePowerCompilerClockGating:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
WA_SET_BIT_MASKED(HIZ_CHICKEN,
-- 
2.5.0

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[Intel-gfx] [PATCH 19/23] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing

[Mika Kuoppala]

Move this workaround to common gen9 workarounds and
enable for all kbl revision.

References: HSD#2135593
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 21 -
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 234f0e288f44..0f3c3ffc85d5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1014,6 +1014,14 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
+   /* WaDisableSbeCacheDispatchPortSharing:skl,bxt,kbl */
+   if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0) ||
+   IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0) ||
+   IS_KABYLAKE(dev_priv))
+   WA_SET_BIT_MASKED(
+   GEN7_HALF_SLICE_CHICKEN1,
+   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret)
@@ -1112,12 +1120,6 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
  HDC_FENCE_DEST_SLM_DISABLE |
  HDC_BARRIER_PERFORMANCE_DISABLE);
 
-   /* WaDisableSbeCacheDispatchPortSharing:skl */
-   if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
-   WA_SET_BIT_MASKED(
-   GEN7_HALF_SLICE_CHICKEN1,
-   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
-
/* WaDisableGafsUnitClkGating:skl */
WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));
 
@@ -1153,13 +1155,6 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
  STALL_DOP_GATING_DISABLE);
 
-   /* WaDisableSbeCacheDispatchPortSharing:bxt */
-   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
-   WA_SET_BIT_MASKED(
-   GEN7_HALF_SLICE_CHICKEN1,
-   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
-   }
-
/* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
-- 
2.5.0

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[Intel-gfx] [PATCH 02/23] drm/i915/kbl: Add REVID macro

[Mika Kuoppala]

Add REVID macro for kbl to limit wa applicability to particular
revision range.

Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4c8e341655c..98cb1f178e3e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2715,6 +2715,12 @@ struct drm_i915_cmd_table {
 
 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, 
until))
 
+#define KBL_REVID_A0   0x0
+#define KBL_REVID_B0   0x1
+
+#define IS_KBL_REVID(p, since, until) \
+   (IS_KABYLAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
-- 
2.5.0

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[Intel-gfx] [PATCH 07/23] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

[Mika Kuoppala]

Add this workaround for kbl revid A0 only.

References: HSD#1911714
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c| 16 
 drivers/gpu/drm/i915/intel_ringbuffer.c |  6 ++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c191a1afaaf..c5e0094d0e75 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1260,6 +1260,22 @@ static int gen9_init_indirectctx_bb(struct 
intel_engine_cs *engine,
return ret;
index = ret;
 
+   /* WaClearSlmSpaceAtContextSwitch:kbl */
+   /* Actual scratch location is at 128 bytes offset */
+   if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
+   uint32_t scratch_addr
+   = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
+
+   wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
+   wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
+  PIPE_CONTROL_GLOBAL_GTT_IVB |
+  PIPE_CONTROL_CS_STALL |
+  PIPE_CONTROL_QW_WRITE));
+   wa_ctx_emit(batch, index, scratch_addr);
+   wa_ctx_emit(batch, index, 0);
+   wa_ctx_emit(batch, index, 0);
+   wa_ctx_emit(batch, index, 0);
+   }
/* Pad to end of cacheline */
while (index % CACHELINE_DWORDS)
wa_ctx_emit(batch, index, MI_NOOP);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3902700d37ef..195943f77d04 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1181,12 +1181,18 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
 
 static int kbl_init_workarounds(struct intel_engine_cs *engine)
 {
+   struct drm_i915_private *dev_priv = engine->i915;
int ret;
 
ret = gen9_init_workarounds(engine);
if (ret)
return ret;
 
+   /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
+   if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
+   WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FENCE_DEST_SLM_DISABLE);
+
return 0;
 }
 
-- 
2.5.0

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[Intel-gfx] [PATCH 03/23] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0

[Mika Kuoppala]

We need this for kbl a0 boards. Note that this should be also
for bxt A0 but we omit that on purpose as bxt A0's are
out of fashion already.

References: HSD#1912158, HSD#4393097
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_stolen.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f9253f2b7ba0..e9cd82290408 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -55,8 +55,10 @@ int i915_gem_stolen_insert_node_in_range(struct 
drm_i915_private *dev_priv,
return -ENODEV;
 
/* See the comment at the drm_mm_init() call for more about this check.
-* WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */
-   if (IS_GEN8(dev_priv) && start < 4096)
+* WaSkipStolenMemoryFirstPage:bdw,chv,kbl (incomplete)
+*/
+   if (start < 4096 && (IS_GEN8(dev_priv) ||
+IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)))
start = 4096;
 
mutex_lock(_priv->mm.stolen_lock);
-- 
2.5.0

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[Intel-gfx] [PATCH 01/23] drm/i915/kbl: Init gen9 workarounds

[Mika Kuoppala]

Kabylake is part of gen9 family so init the generic gen9
workarounds for it.

Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++---
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d35a3978f9b..f52105531877 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -911,21 +911,21 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
uint32_t tmp;
int ret;
 
-   /* WaEnableLbsSlaRetryTimerDecrement:skl */
+   /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 
-   /* WaDisableKillLogic:bxt,skl */
+   /* WaDisableKillLogic:bxt,skl,kbl */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
   ECOCHK_DIS_TLB);
 
-   /* WaClearFlowControlGpgpuContextSave:skl,bxt */
-   /* WaDisablePartialInstShootdown:skl,bxt */
+   /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
+   /* WaDisablePartialInstShootdown:skl,bxt,kbl */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
  FLOW_CONTROL_ENABLE |
  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-   /* Syncing dependencies between camera and graphics:skl,bxt */
+   /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
@@ -947,18 +947,18 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
 */
}
 
-   /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
-   /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
+   /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
+   /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
  GEN9_ENABLE_YV12_BUGFIX |
  GEN9_ENABLE_GPGPU_PREEMPTION);
 
-   /* Wa4x4STCOptimizationDisable:skl,bxt */
-   /* WaDisablePartialResolveInVc:skl,bxt */
+   /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
+   /* WaDisablePartialResolveInVc:skl,bxt,kbl */
WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 
-   /* WaCcsTlbPrefetchDisable:skl,bxt */
+   /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
@@ -975,24 +975,26 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
-   /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
-   if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+   /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
+   if (IS_SKYLAKE(dev_priv) ||
+   IS_KABYLAKE(dev_priv) ||
+   IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
-   /* WaDisableSTUnitPowerOptimization:skl,bxt */
+   /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
-   /* WaOCLCoherentLineFlush:skl,bxt */
+   /* WaOCLCoherentLineFlush:skl,bxt,kbl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-   /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
+   /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret)
return ret;
 
-   /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
+   /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
if (ret)
return ret;
@@ -1174,6 +1176,17 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
return 0;
 }
 
+static int kbl_init_workarounds(struct intel_engine_cs *engine)
+{
+   int ret;
+
+   ret = gen9_init_workarounds(engine);
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
@@ -1195,6 +1208,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
if (IS_BROXTON(dev_priv))
return bxt_init_workarounds(engine);
 
+   if (IS_KABYLAKE(dev_priv))
+   return 

[Intel-gfx] [PATCH 04/23] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent

[Mika Kuoppala]

The revision id range for this workaround has changed. So apply
it to all revids on all gen9.

References: HSD#2134449
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f52105531877..47557bd34945 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -908,7 +908,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*engine)
 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
-   uint32_t tmp;
int ret;
 
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
@@ -968,12 +967,10 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
  PIXEL_MASK_CAMMING_DISABLE);
 
-   /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
-   tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
-   if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
-   IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
-   tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
-   WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+   /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
+   WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
+ HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
if (IS_SKYLAKE(dev_priv) ||
-- 
2.5.0

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[Intel-gfx] [PATCH 00/23] kbl and gen9 workarounds

[Mika Kuoppala]

I noticed that we didn't setup any workarounds for kbl and so
here is a series to get necessities covered on kbl. And while on
it add few to bxt and skl. In the end there are also few fbc
ones I bumped into.

Mika Kuoppala (23):
  drm/i915/kbl: Init gen9 workarounds
  drm/i915/kbl: Add REVID macro
  drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
  drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
  drm/i915: Mimic skl with WaForceEnableNonCoherent
  drm/i915/kbl: Add WaEnableGapsTsvCreditFix
  drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
  drm/i915/kbl: Add WaDisableSDEUnitClockGating
  drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw,skl
  drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
  drm/i915/gen9: Enable must set chicken bits in config0 reg
  drm/i915/kbl: Add WaDisableGamClockGating
  drm/i915/kbl: Add WaDisableDynamicCreditSharing
  drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
  drm/i915/gen9: Add WaDisableSkipCaching
  drm/i915/skl: Add WAC6entrylatency
  drm/i915/kbl: Add WaForGAMHang
  drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
  drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
  drm/i915/gen9: Set wa for display underrun issues with Y & Yf Tiling.
  drm/i915/gen9: Set fbc watermarks disabled
  drm/i915/gen9: Prevent fbc corruption/system hangs with high bw
  drm/i195/fbc: Enable wa to prevent fbc corruption with skl and kbl

 drivers/gpu/drm/i915/i915_drv.h |   9 ++
 drivers/gpu/drm/i915/i915_gem_stolen.c  |   6 +-
 drivers/gpu/drm/i915/i915_reg.h |  20 
 drivers/gpu/drm/i915/intel_lrc.c|  57 ++-
 drivers/gpu/drm/i915/intel_mocs.c   |  10 ++
 drivers/gpu/drm/i915/intel_pm.c |  67 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 167 +---
 7 files changed, 266 insertions(+), 70 deletions(-)

-- 
2.5.0

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[Intel-gfx] [PATCH 14/23] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl

[Mika Kuoppala]

Add this workaround for both bxt and kbl up to until
rev B0.

References: HSD#2136703
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0441da08201..ec31eca06807 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6087,6 +6087,7 @@ enum skl_disp_power_wells {
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
 # define GEN9_RHWO_OPTIMIZATION_DISABLE(1<<14)
 #define COMMON_SLICE_CHICKEN2  _MMIO(0x7014)
+# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE  (1<<0)
 
 #define HIZ_CHICKEN_MMIO(0x7018)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 402e0feb4cca..d60b7a3ebb47 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1176,6 +1176,11 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
   L3_HIGH_PRIO_CREDITS(2));
 
+   /* WaInsertDummyPushConstPs:bxt */
+   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+   WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
return 0;
 }
 
@@ -1205,6 +1210,11 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
   GEN8_LQSC_RO_PERF_DIS);
 
+   /* WaInsertDummyPushConstPs:kbl */
+   if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+   WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
-- 
2.5.0

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Re: [Intel-gfx] [PATCH] drm: Store the plane's index

[Matt Roper]

On Thu, May 26, 2016 at 01:17:18PM +0100, Chris Wilson wrote:
> Currently the plane's index is determined by walking the list of all
> planes in the mode and finding the position of that plane in the list. A
> linear walk, especially a linear walk within a linear walk as frequently
> conceived by i915.ko [O(N^2)] quickly comes to dominate profiles.
> 
> The plane's index is constant for as long as no earlier planes are
> removed from the list. For most drivers, planes are static, determined
> at boot and then untouched until shutdown. Storing the index upon
> construction and then only walking the tail upon removal should
> be a major improvement for all.
> 
> v2: Convert drm_crtc_index() and drm_encoder_index() as well.
> 
> Signed-off-by: Chris Wilson 
> Cc: Daniel Vetter 
> Cc: Matt Roper 
> Cc: Ville Syrjälä 

Looks good to me.

Reviewed-by: Matt Roper 

Your commit message says "most drivers" have static
planes/crtcs/encoders...are there any drivers today that this isn't true
for?  Wouldn't we need special locking for list iteration in general
like we have for connectors if that was the case?


Matt

> ---
>  drivers/gpu/drm/drm_crtc.c | 98 
> ++
>  include/drm/drm_crtc.h | 25 ++--
>  2 files changed, 43 insertions(+), 80 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index d2a6d958ca76..4d978099aa17 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -692,7 +692,7 @@ int drm_crtc_init_with_planes(struct drm_device *dev, 
> struct drm_crtc *crtc,
>   crtc->base.properties = >properties;
>  
>   list_add_tail(>head, >crtc_list);
> - config->num_crtc++;
> + crtc->index = config->num_crtc++;
>  
>   crtc->primary = primary;
>   crtc->cursor = cursor;
> @@ -721,6 +721,11 @@ EXPORT_SYMBOL(drm_crtc_init_with_planes);
>  void drm_crtc_cleanup(struct drm_crtc *crtc)
>  {
>   struct drm_device *dev = crtc->dev;
> + struct drm_crtc *other;
> +
> + other = list_next_entry(crtc, head);
> + list_for_each_entry_from(other, >mode_config.crtc_list, head)
> + other->index--;
>  
>   kfree(crtc->gamma_store);
>   crtc->gamma_store = NULL;
> @@ -741,29 +746,6 @@ void drm_crtc_cleanup(struct drm_crtc *crtc)
>  }
>  EXPORT_SYMBOL(drm_crtc_cleanup);
>  
> -/**
> - * drm_crtc_index - find the index of a registered CRTC
> - * @crtc: CRTC to find index for
> - *
> - * Given a registered CRTC, return the index of that CRTC within a DRM
> - * device's list of CRTCs.
> - */
> -unsigned int drm_crtc_index(struct drm_crtc *crtc)
> -{
> - unsigned int index = 0;
> - struct drm_crtc *tmp;
> -
> - drm_for_each_crtc(tmp, crtc->dev) {
> - if (tmp == crtc)
> - return index;
> -
> - index++;
> - }
> -
> - BUG();
> -}
> -EXPORT_SYMBOL(drm_crtc_index);
> -
>  /*
>   * drm_mode_remove - remove and free a mode
>   * @connector: connector list to modify
> @@ -1166,7 +1148,7 @@ int drm_encoder_init(struct drm_device *dev,
>   }
>  
>   list_add_tail(>head, >mode_config.encoder_list);
> - dev->mode_config.num_encoder++;
> + encoder->index = dev->mode_config.num_encoder++;
>  
>  out_put:
>   if (ret)
> @@ -1180,29 +1162,6 @@ out_unlock:
>  EXPORT_SYMBOL(drm_encoder_init);
>  
>  /**
> - * drm_encoder_index - find the index of a registered encoder
> - * @encoder: encoder to find index for
> - *
> - * Given a registered encoder, return the index of that encoder within a DRM
> - * device's list of encoders.
> - */
> -unsigned int drm_encoder_index(struct drm_encoder *encoder)
> -{
> - unsigned int index = 0;
> - struct drm_encoder *tmp;
> -
> - drm_for_each_encoder(tmp, encoder->dev) {
> - if (tmp == encoder)
> - return index;
> -
> - index++;
> - }
> -
> - BUG();
> -}
> -EXPORT_SYMBOL(drm_encoder_index);
> -
> -/**
>   * drm_encoder_cleanup - cleans up an initialised encoder
>   * @encoder: encoder to cleanup
>   *
> @@ -1211,6 +1170,11 @@ EXPORT_SYMBOL(drm_encoder_index);
>  void drm_encoder_cleanup(struct drm_encoder *encoder)
>  {
>   struct drm_device *dev = encoder->dev;
> + struct drm_encoder *other;
> +
> + other = list_next_entry(encoder, head);
> + list_for_each_entry_from(other, >mode_config.encoder_list, head)
> + other->index--;
>  
>   drm_modeset_lock_all(dev);
>   drm_mode_object_unregister(dev, >base);
> @@ -1300,7 +1264,7 @@ int drm_universal_plane_init(struct drm_device *dev, 
> struct drm_plane *plane,
>   plane->type = type;
>  
>   list_add_tail(>head, >plane_list);
> - config->num_total_plane++;
> + plane->index = config->num_total_plane++;
>   if (plane->type == DRM_PLANE_TYPE_OVERLAY)
>   

[Intel-gfx] [PATCH igt v2 2/2] lib: Override the connector status using the sysfs status attribute

[Chris Wilson]

There are two paths to force enable a connector, via debugfs and via
sysfs. sysfs has the advantage of being a stable interface and of
updating the connector after application (allowing us to not force a
reprobe from userspace).

v2: Don't assume Intel only

Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
---
 lib/igt_kms.c | 45 +
 1 file changed, 25 insertions(+), 20 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 4da645a..b12a5b3 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -48,10 +48,12 @@
 #include "igt_aux.h"
 #include "intel_chipset.h"
 #include "igt_debugfs.h"
+#include "igt_sysfs.h"
 
 /* list of connectors that need resetting on exit */
 #define MAX_CONNECTORS 32
 static char *forced_connectors[MAX_CONNECTORS + 1];
+static int forced_connectors_device[MAX_CONNECTORS + 1];
 
 static void update_edid_csum(unsigned char *edid)
 {
@@ -596,9 +598,9 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
*connector,
 {
char *path, **tmp;
const char *value;
-   int debugfs_fd, ret, len;
drmModeConnector *temp;
uint32_t devid;
+   int len, dir, idx;
 
devid = intel_get_drm_devid(drm_fd);
 
@@ -615,7 +617,7 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
*connector,
value = "on";
break;
case FORCE_CONNECTOR_DIGITAL:
-   value = "digital";
+   value = "on-digital";
break;
case FORCE_CONNECTOR_OFF:
value = "off";
@@ -623,20 +625,26 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
*connector,
 
default:
case FORCE_CONNECTOR_UNSPECIFIED:
-   value = "unspecified";
+   value = "detect";
break;
}
 
-   igt_assert_neq(asprintf(, "%s-%d/force", 
kmstest_connector_type_str(connector->connector_type), 
connector->connector_type_id),
-  -1);
-   debugfs_fd = igt_debugfs_open(path, O_WRONLY | O_TRUNC);
+   dir = igt_sysfs_open(drm_fd, );
+   if (dir < 0)
+   return false;
 
-   if (debugfs_fd == -1) {
+   if (asprintf(, "card%d-%s-%d/status",
+idx,
+kmstest_connector_type_str(connector->connector_type),
+connector->connector_type_id) < 0) {
+   close(dir);
return false;
}
 
-   ret = write(debugfs_fd, value, strlen(value));
-   close(debugfs_fd);
+   if (!igt_sysfs_set(drm_fd, path, value)) {
+   close(dir);
+   return false;
+   }
 
for (len = 0, tmp = forced_connectors; *tmp; tmp++) {
/* check the connector is not already present */
@@ -647,8 +655,10 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
*connector,
len++;
}
 
-   if (len != -1 && len < MAX_CONNECTORS)
+   if (len != -1 && len < MAX_CONNECTORS) {
forced_connectors[len] = path;
+   forced_connectors_device[len] = dir;
+   }
 
if (len >= MAX_CONNECTORS)
igt_warn("Connector limit reached, %s will not be reset\n",
@@ -669,8 +679,7 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
*connector,
temp = drmModeGetConnector(drm_fd, connector->connector_id);
drmModeFreeConnector(temp);
 
-   igt_assert(ret != -1);
-   return (ret == -1) ? false : true;
+   return true;
 }
 
 /**
@@ -2543,14 +2552,10 @@ void igt_enable_connectors(void)
  */
 void igt_reset_connectors(void)
 {
-   char **tmp;
-
/* reset the connectors stored in forced_connectors, avoiding any
 * functions that are not safe to call in signal handlers */
-
-   for (tmp = forced_connectors; *tmp; tmp++) {
-   int fd = igt_debugfs_open(*tmp, O_WRONLY | O_TRUNC);
-   igt_assert(write(fd, "unspecified", 11) == 11);
-   close(fd);
-   }
+   for (int i = 0; forced_connectors[i]; i++)
+   igt_sysfs_set(forced_connectors_device[i],
+ forced_connectors[i],
+ "detect");
 }
-- 
2.8.1

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[Intel-gfx] [PATCH igt v2 1/2] lib: Add simple sysfs accessors

[Chris Wilson]

igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for
reading.

v2: Lots of little bugs in igt_sysfs_get()
v3: Pass device to open, stop assuming Intel rules.

Signed-off-by: Chris Wilson 
---
 lib/Makefile.sources |   2 +
 lib/igt_sysfs.c  | 198 +++
 lib/igt_sysfs.h  |  34 +
 3 files changed, 234 insertions(+)
 create mode 100644 lib/igt_sysfs.c
 create mode 100644 lib/igt_sysfs.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 1316fd2..f50ff4d 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -16,6 +16,8 @@ libintel_tools_la_SOURCES =   \
igt_gt.h\
igt_stats.c \
igt_stats.h \
+   igt_sysfs.c \
+   igt_sysfs.h \
instdone.c  \
instdone.h  \
intel_batchbuffer.c \
diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
new file mode 100644
index 000..4b993dc
--- /dev/null
+++ b/lib/igt_sysfs.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "igt_sysfs.h"
+
+static int readN(int fd, char *buf, int len)
+{
+   int total = 0;
+   do {
+   int ret = read(fd, buf + total, len - total);
+   if (ret < 0 && (errno == EINTR || errno == EAGAIN))
+   continue;
+
+   if (ret <= 0)
+   return total ?: ret;
+
+   total += ret;
+   } while (1);
+}
+
+static int writeN(int fd, const char *buf, int len)
+{
+   int total = 0;
+   do {
+   int ret = write(fd, buf + total, len - total);
+   if (ret < 0 && (errno == EINTR || errno == EAGAIN))
+   continue;
+
+   if (ret <= 0)
+   return total ?: ret;
+
+   total += ret;
+   } while (1);
+}
+
+/**
+ * igt_sysfs_open:
+ * @device: fd of the device (or -1 to default to Intel)
+ *
+ * This opens the sysfs directory corresponding to device for use
+ * with igt_sysfs_set() and igt_sysfs_get().
+ *
+ * Returns:
+ * The directory fd, or -1 on failure.
+ */
+int igt_sysfs_open(int fd, int *idx)
+{
+   char device[80];
+   char path[80];
+   struct stat st;
+
+   device[0] = '\0';
+   if (fd != -1) {
+   if (fstat(fd, ) || !S_ISCHR(st.st_mode))
+   return -1;
+
+   sprintf(device, "%d:%d", major(st.st_rdev), minor(st.st_rdev));
+   }
+
+   for (int n = 0; n < 16; n++) {
+   int len = sprintf(path, "/sys/class/drm/card%d", n);
+   if (device[0]) {
+   sprintf(path + len, "/dev");
+   fd = open(path, O_RDONLY);
+   if (fd == -1)
+   continue;
+
+   len = read(fd, path, sizeof(path-1));
+   if (len < 0)
+   len = 0;
+   path[len] = '\0';
+   close(fd);
+
+   if (strcmp(path, device))
+   continue;
+   } else {
+   /* Bleh. Search for intel */
+   sprintf(path + len, "/error");
+   if (stat(path, ))
+   continue;
+   }
+
+   path[len] = '\0';
+   if (idx)
+   *idx = n;
+   return open(path, O_RDONLY);
+   }
+
+   return -1;
+}
+
+/**
+ * igt_sysfs_set:
+ * @device: directory for the device from igt_sysfs_open()
+ * @attr: name of the sysfs node to open

Re: [Intel-gfx] [PATCH igt 2/2] lib: Override the connector status using the sysfs status attribute

[Chris Wilson]

On Thu, May 26, 2016 at 05:39:32PM +0300, Ville Syrjälä wrote:
> On Thu, May 26, 2016 at 03:14:30PM +0100, Chris Wilson wrote:
> > There are two paths to force enable a connector, via debugfs and via
> > sysfs. sysfs has the advantage of being a stable interface and of
> > updating the connector after application (allowing us to not force a
> > reprobe from userspace).
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Ville Syrjälä 
> > ---
> >  lib/igt_kms.c | 27 +--
> >  1 file changed, 9 insertions(+), 18 deletions(-)
> > 
> > diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> > index 4da645a..5678248 100644
> > --- a/lib/igt_kms.c
> > +++ b/lib/igt_kms.c
> > @@ -48,6 +48,7 @@
> >  #include "igt_aux.h"
> >  #include "intel_chipset.h"
> >  #include "igt_debugfs.h"
> > +#include "igt_sysfs.h"
> >  
> >  /* list of connectors that need resetting on exit */
> >  #define MAX_CONNECTORS 32
> > @@ -596,9 +597,9 @@ bool kmstest_force_connector(int drm_fd, 
> > drmModeConnector *connector,
> >  {
> > char *path, **tmp;
> > const char *value;
> > -   int debugfs_fd, ret, len;
> > drmModeConnector *temp;
> > uint32_t devid;
> > +   int len;
> >  
> > devid = intel_get_drm_devid(drm_fd);
> >  
> > @@ -615,7 +616,7 @@ bool kmstest_force_connector(int drm_fd, 
> > drmModeConnector *connector,
> > value = "on";
> > break;
> > case FORCE_CONNECTOR_DIGITAL:
> > -   value = "digital";
> > +   value = "on-digital";
> > break;
> > case FORCE_CONNECTOR_OFF:
> > value = "off";
> > @@ -623,20 +624,14 @@ bool kmstest_force_connector(int drm_fd, 
> > drmModeConnector *connector,
> >  
> > default:
> > case FORCE_CONNECTOR_UNSPECIFIED:
> > -   value = "unspecified";
> > +   value = "detect";
> > break;
> > }
> >  
> > -   igt_assert_neq(asprintf(, "%s-%d/force", 
> > kmstest_connector_type_str(connector->connector_type), 
> > connector->connector_type_id),
> > +   igt_assert_neq(asprintf(, "%s-%d/status", 
> > kmstest_connector_type_str(connector->connector_type), 
> > connector->connector_type_id),
> 
> That'll need a cardN- prefix. Rather annoying.

Oh dear. That is annoying.

Be right back.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH igt 1/2] lib: Add simple sysfs accessors

[Chris Wilson]

On Thu, May 26, 2016 at 05:36:09PM +0300, Ville Syrjälä wrote:
> > +
> > +   for (int n = 0; n < 16; n++) {
> > +   int len = sprintf(path, "/sys/class/drm/card%d", n);
> > +   sprintf(path + len, "/error");
> 
> That's goint to limit this to i915. I was thinking we could pass
> the drm_fd here to find the correct minor for it.

Hah, I was rewriting it to avoid the i915 presumption. Using fstat and
comparing sysfs/cardN/dev is what I went with. Pretty much equivalent to
drmGetDeviceNameFromFd(), yes.

> > +bool igt_sysfs_set(const char *filename, const char *value)
> > +{
> > +   int sysfs = __igt_sysfs_singleton();
> > +   int fd, len, ret;
> > +
> > +   if (sysfs < 0)
> > +   return false;
> > +
> > +   fd = openat(sysfs, filename, O_WRONLY);
> > +   if (fd < 0)
> > +   return false;
> > +
> > +   len = strlen(value);
> > +   ret = write(fd, value, len);
> 
> EINTR?

Pesky signals.
-Chris

-- 
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Re: [Intel-gfx] [PATCH igt 2/2] lib: Override the connector status using the sysfs status attribute

[Ville Syrjälä]

On Thu, May 26, 2016 at 03:14:30PM +0100, Chris Wilson wrote:
> There are two paths to force enable a connector, via debugfs and via
> sysfs. sysfs has the advantage of being a stable interface and of
> updating the connector after application (allowing us to not force a
> reprobe from userspace).
> 
> Signed-off-by: Chris Wilson 
> Cc: Ville Syrjälä 
> ---
>  lib/igt_kms.c | 27 +--
>  1 file changed, 9 insertions(+), 18 deletions(-)
> 
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 4da645a..5678248 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -48,6 +48,7 @@
>  #include "igt_aux.h"
>  #include "intel_chipset.h"
>  #include "igt_debugfs.h"
> +#include "igt_sysfs.h"
>  
>  /* list of connectors that need resetting on exit */
>  #define MAX_CONNECTORS 32
> @@ -596,9 +597,9 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
> *connector,
>  {
>   char *path, **tmp;
>   const char *value;
> - int debugfs_fd, ret, len;
>   drmModeConnector *temp;
>   uint32_t devid;
> + int len;
>  
>   devid = intel_get_drm_devid(drm_fd);
>  
> @@ -615,7 +616,7 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
> *connector,
>   value = "on";
>   break;
>   case FORCE_CONNECTOR_DIGITAL:
> - value = "digital";
> + value = "on-digital";
>   break;
>   case FORCE_CONNECTOR_OFF:
>   value = "off";
> @@ -623,20 +624,14 @@ bool kmstest_force_connector(int drm_fd, 
> drmModeConnector *connector,
>  
>   default:
>   case FORCE_CONNECTOR_UNSPECIFIED:
> - value = "unspecified";
> + value = "detect";
>   break;
>   }
>  
> - igt_assert_neq(asprintf(, "%s-%d/force", 
> kmstest_connector_type_str(connector->connector_type), 
> connector->connector_type_id),
> + igt_assert_neq(asprintf(, "%s-%d/status", 
> kmstest_connector_type_str(connector->connector_type), 
> connector->connector_type_id),

That'll need a cardN- prefix. Rather annoying.

>  -1);
> - debugfs_fd = igt_debugfs_open(path, O_WRONLY | O_TRUNC);
> -
> - if (debugfs_fd == -1) {
> + if (!igt_sysfs_set(path, value))
>   return false;
> - }
> -
> - ret = write(debugfs_fd, value, strlen(value));
> - close(debugfs_fd);
>  
>   for (len = 0, tmp = forced_connectors; *tmp; tmp++) {
>   /* check the connector is not already present */
> @@ -669,8 +664,7 @@ bool kmstest_force_connector(int drm_fd, drmModeConnector 
> *connector,
>   temp = drmModeGetConnector(drm_fd, connector->connector_id);
>   drmModeFreeConnector(temp);
>  
> - igt_assert(ret != -1);
> - return (ret == -1) ? false : true;
> + return true;
>  }
>  
>  /**
> @@ -2548,9 +2542,6 @@ void igt_reset_connectors(void)
>   /* reset the connectors stored in forced_connectors, avoiding any
>* functions that are not safe to call in signal handlers */
>  
> - for (tmp = forced_connectors; *tmp; tmp++) {
> - int fd = igt_debugfs_open(*tmp, O_WRONLY | O_TRUNC);
> - igt_assert(write(fd, "unspecified", 11) == 11);
> - close(fd);
> - }
> + for (tmp = forced_connectors; *tmp; tmp++)
> + igt_sysfs_set(*tmp, "detect");
>  }
> -- 
> 2.8.1

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH igt 1/2] lib: Add simple sysfs accessors

[Ville Syrjälä]

On Thu, May 26, 2016 at 03:14:29PM +0100, Chris Wilson wrote:
> igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for
> reading.
> 
> Signed-off-by: Chris Wilson 
> ---
>  lib/Makefile.sources |   2 +
>  lib/igt_sysfs.c  | 145 
> +++
>  lib/igt_sysfs.h  |  33 
>  3 files changed, 180 insertions(+)
>  create mode 100644 lib/igt_sysfs.c
>  create mode 100644 lib/igt_sysfs.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 1316fd2..f50ff4d 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -16,6 +16,8 @@ libintel_tools_la_SOURCES = \
>   igt_gt.h\
>   igt_stats.c \
>   igt_stats.h \
> + igt_sysfs.c \
> + igt_sysfs.h \
>   instdone.c  \
>   instdone.h  \
>   intel_batchbuffer.c \
> diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
> new file mode 100644
> index 000..4dd6089
> --- /dev/null
> +++ b/lib/igt_sysfs.c
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "igt_sysfs.h"
> +
> +typedef struct {
> + int dir;
> +} igt_sysfs_t;
> +
> +static int __igt_sysfs_init(void)
> +{
> + char path[1024];
> + struct stat st;


> +
> + for (int n = 0; n < 16; n++) {
> + int len = sprintf(path, "/sys/class/drm/card%d", n);
> + sprintf(path + len, "/error");

That's goint to limit this to i915. I was thinking we could pass
the drm_fd here to find the correct minor for it.

Maybe drmGetDeviceNameFromFd() is the right thing for that?

> + if (stat(path, ) == 0) {
> + path[len] = '\0';
> + return open(path, O_RDONLY);
> + }
> + }
> +
> + return -1;
> +}
> +
> +static int __igt_sysfs_singleton(void)
> +{
> + static int sysfs = -1;
> +
> + if (sysfs == -1)
> + sysfs = __igt_sysfs_init();
> +
> + return sysfs;
> +}
> +
> +/**
> + * igt_sysfs_set:
> + * @filename: name of the sysfs node to open
> + * @value: the string to write
> + *
> + * This writes the value to the sysfs file.
> + *
> + * Returns:
> + * True on success, false on failure.
> + */
> +bool igt_sysfs_set(const char *filename, const char *value)
> +{
> + int sysfs = __igt_sysfs_singleton();
> + int fd, len, ret;
> +
> + if (sysfs < 0)
> + return false;
> +
> + fd = openat(sysfs, filename, O_WRONLY);
> + if (fd < 0)
> + return false;
> +
> + len = strlen(value);
> + ret = write(fd, value, len);

EINTR?

> + close(fd);
> +
> + return len == ret;
> +}
> +
> +/**
> + * igt_sysfs_get:
> + * @filename: name of the sysfs node to open
> + *
> + * This reads the value from the sysfs file.
> + *
> + * Returns:
> + * A nul-terminated string, must be freed by caller after use, or NULL
> + * on failure.
> + */
> +char *igt_sysfs_get(const char *filename)
> +{
> + int sysfs = __igt_sysfs_singleton();
> + char *buf;
> + int len, offset, rem;
> + int ret, fd;
> +
> + if (sysfs < 0)
> + return NULL;
> +
> + fd = openat(sysfs, filename, O_WRONLY);
> + if (fd < 0)
> + return NULL;
> +
> + offset = 0;
> + len = 64;
> + rem =  len - offset - 1;
> + buf = malloc(len);
> + if (!buf)
> + return NULL;
> +
> + while ((ret = read(fd, buf + offset, rem)) == rem) {

EINTR?

> + char *newbuf;
> +
> + len *= 2;
> + offset += ret;
> +
> + newbuf = 

Re: [Intel-gfx] [PATCH] drm/i915: Register debugfs interface last

[Ville Syrjälä]

On Thu, May 26, 2016 at 02:17:27PM +0100, Chris Wilson wrote:
> Currently debugfs files are created before the driver is even loads.
> This gives the opportunity for userspace to open that interface and poke
> around before the backing data structures are initialised - with the
> possibility of oopsing or worse.
> 
> Move the creation of the debugfs files to our registration phase, where
> we announce our presence to the world when we are ready.
> 
> Signed-off-by: Chris Wilson 
> Cc: Ville Syrjälä 

Makes sense to me. I never understood why these kinds of hooks existed
in the first place.

So the sequence changes from

drm_dev_register()
 -> drm_minor_register()
   -> drm_debugfs_init()
 -> i915_debugfs_init()
 -> i915_driver_load()

to something like

drm_dev_register()
 -> drm_minor_register()
   -> drm_debugfs_init()
 -> i915_driver_load()
   -> i915_debugfs_register()

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 6 --
>  drivers/gpu/drm/i915/i915_dma.c | 2 ++
>  drivers/gpu/drm/i915/i915_drv.c | 4 
>  drivers/gpu/drm/i915/i915_drv.h | 6 --
>  4 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 615cef736356..4a3546f114c6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -5498,8 +5498,9 @@ void intel_display_crc_init(struct drm_device *dev)
>   }
>  }
>  
> -int i915_debugfs_init(struct drm_minor *minor)
> +int i915_debugfs_register(struct drm_i915_private *dev_priv)
>  {
> + struct drm_minor *minor = dev_priv->dev->primary;
>   int ret, i;
>  
>   ret = i915_forcewake_create(minor->debugfs_root, minor);
> @@ -5525,8 +5526,9 @@ int i915_debugfs_init(struct drm_minor *minor)
>   minor->debugfs_root, minor);
>  }
>  
> -void i915_debugfs_cleanup(struct drm_minor *minor)
> +void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
>  {
> + struct drm_minor *minor = dev_priv->dev->primary;
>   int i;
>  
>   drm_debugfs_remove_files(i915_debugfs_list,
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 07edaed9d5a2..af0a6ce6f0b9 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1372,6 +1372,7 @@ static void i915_driver_register(struct 
> drm_i915_private *dev_priv)
>   if (intel_vgpu_active(dev_priv))
>   I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
>  
> + i915_debugfs_register(dev_priv);
>   i915_setup_sysfs(dev);
>  
>   if (INTEL_INFO(dev_priv)->num_pipes) {
> @@ -1397,6 +1398,7 @@ static void i915_driver_unregister(struct 
> drm_i915_private *dev_priv)
>   acpi_video_unregister();
>   intel_opregion_unregister(dev_priv);
>   i915_teardown_sysfs(dev_priv->dev);
> + i915_debugfs_unregister(dev_priv);
>   i915_gem_shrinker_cleanup(dev_priv);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 943d7b222fd4..fa9e16b2247c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1761,10 +1761,6 @@ static struct drm_driver driver = {
>   .postclose = i915_driver_postclose,
>   .set_busid = drm_pci_set_busid,
>  
> -#if defined(CONFIG_DEBUG_FS)
> - .debugfs_init = i915_debugfs_init,
> - .debugfs_cleanup = i915_debugfs_cleanup,
> -#endif
>   .gem_free_object = i915_gem_free_object,
>   .gem_vm_ops = _gem_vm_ops,
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b9d9a4205992..8f2994ef4386 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3543,12 +3543,14 @@ int i915_verify_lists(struct drm_device *dev);
>  #endif
>  
>  /* i915_debugfs.c */
> -int i915_debugfs_init(struct drm_minor *minor);
> -void i915_debugfs_cleanup(struct drm_minor *minor);
>  #ifdef CONFIG_DEBUG_FS
> +int i915_debugfs_register(struct drm_i915_private *dev_priv);
> +void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
>  int i915_debugfs_connector_add(struct drm_connector *connector);
>  void intel_display_crc_init(struct drm_device *dev);
>  #else
> +static inline int i915_debugfs_register(struct drm_i915_private *) {return 
> 0;}
> +static inline void i915_debugfs_unregister(struct drm_i915_private *) {}
>  static inline int i915_debugfs_connector_add(struct drm_connector *connector)
>  { return 0; }
>  static inline void intel_display_crc_init(struct drm_device *dev) {}
> -- 
> 2.8.1

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH igt 1/2] lib: Add simple sysfs accessors

[Chris Wilson]

igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for
reading.

Signed-off-by: Chris Wilson 
---
 lib/Makefile.sources |   2 +
 lib/igt_sysfs.c  | 145 +++
 lib/igt_sysfs.h  |  33 
 3 files changed, 180 insertions(+)
 create mode 100644 lib/igt_sysfs.c
 create mode 100644 lib/igt_sysfs.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 1316fd2..f50ff4d 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -16,6 +16,8 @@ libintel_tools_la_SOURCES =   \
igt_gt.h\
igt_stats.c \
igt_stats.h \
+   igt_sysfs.c \
+   igt_sysfs.h \
instdone.c  \
instdone.h  \
intel_batchbuffer.c \
diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
new file mode 100644
index 000..4dd6089
--- /dev/null
+++ b/lib/igt_sysfs.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "igt_sysfs.h"
+
+typedef struct {
+   int dir;
+} igt_sysfs_t;
+
+static int __igt_sysfs_init(void)
+{
+   char path[1024];
+   struct stat st;
+
+   for (int n = 0; n < 16; n++) {
+   int len = sprintf(path, "/sys/class/drm/card%d", n);
+   sprintf(path + len, "/error");
+   if (stat(path, ) == 0) {
+   path[len] = '\0';
+   return open(path, O_RDONLY);
+   }
+   }
+
+   return -1;
+}
+
+static int __igt_sysfs_singleton(void)
+{
+   static int sysfs = -1;
+
+   if (sysfs == -1)
+   sysfs = __igt_sysfs_init();
+
+   return sysfs;
+}
+
+/**
+ * igt_sysfs_set:
+ * @filename: name of the sysfs node to open
+ * @value: the string to write
+ *
+ * This writes the value to the sysfs file.
+ *
+ * Returns:
+ * True on success, false on failure.
+ */
+bool igt_sysfs_set(const char *filename, const char *value)
+{
+   int sysfs = __igt_sysfs_singleton();
+   int fd, len, ret;
+
+   if (sysfs < 0)
+   return false;
+
+   fd = openat(sysfs, filename, O_WRONLY);
+   if (fd < 0)
+   return false;
+
+   len = strlen(value);
+   ret = write(fd, value, len);
+   close(fd);
+
+   return len == ret;
+}
+
+/**
+ * igt_sysfs_get:
+ * @filename: name of the sysfs node to open
+ *
+ * This reads the value from the sysfs file.
+ *
+ * Returns:
+ * A nul-terminated string, must be freed by caller after use, or NULL
+ * on failure.
+ */
+char *igt_sysfs_get(const char *filename)
+{
+   int sysfs = __igt_sysfs_singleton();
+   char *buf;
+   int len, offset, rem;
+   int ret, fd;
+
+   if (sysfs < 0)
+   return NULL;
+
+   fd = openat(sysfs, filename, O_WRONLY);
+   if (fd < 0)
+   return NULL;
+
+   offset = 0;
+   len = 64;
+   rem =  len - offset - 1;
+   buf = malloc(len);
+   if (!buf)
+   return NULL;
+
+   while ((ret = read(fd, buf + offset, rem)) == rem) {
+   char *newbuf;
+
+   len *= 2;
+   offset += ret;
+
+   newbuf = realloc(buf, len);
+   if (!newbuf)
+   break;
+
+   rem = len - offset - 1;
+   }
+
+   buf[offset] = '0';
+   return buf;
+}
diff --git a/lib/igt_sysfs.h b/lib/igt_sysfs.h
new file mode 100644
index 000..48c218d
--- /dev/null
+++ b/lib/igt_sysfs.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated 

[Intel-gfx] ✗ Ro.CI.BAT: warning for series starting with [v3,01/10] drm/i915: Skip idling an idle engine (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm/i915: Skip idling an idle engine 
(rev3)
URL   : https://patchwork.freedesktop.org/series/7792/
State : warning

== Summary ==

Series 7792v3 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/7792/revisions/3/mbox

Test gem_basic:
Subgroup bad-close:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_busy:
Subgroup basic-blt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_basic:
Subgroup basic-vebox:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_store:
Subgroup basic-default:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
Subgroup basic-read:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_ringfill:
Subgroup basic-default-forked:
pass   -> DMESG-WARN (ro-byt-n2820)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (ro-bdw-i7-5600u)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-bsw-n3050 total:209  pass:167  dwarn:0   dfail:0   fail:2   skip:40 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:1   dfail:0   fail:2   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:178  dwarn:5   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
fi-byt-n2820 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1025/

fc9d741 drm-intel-nightly: 2016y-05m-25d-07h-45m-48s UTC integration manifest
c654dd5 drm/i915: Defer enabling rc6 til after we submit the first batch/context
9e6501a drm/i915: Register debugfs interface last
e9d58a4 drm/i915: Preserve current RPS frequency
6b991ad drm/i915: Only switch to default context when evicting from GGTT
e67b6dc drm/i915: Split idling from forcing context switch
0b8ae7f drm/i915: No need to wait for idle on L3 remap
0ac86ee drm/i915: Mark all default contexts as uninitialised after context loss
87cba42 drm/i915: Treat kernel context as initialised
16ea248 drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c
b828f51 drm/i915: Skip idling an idle engine

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[Intel-gfx] [PATCH] drm/i915: Register debugfs interface last

[Chris Wilson]

Currently debugfs files are created before the driver is even loads.
This gives the opportunity for userspace to open that interface and poke
around before the backing data structures are initialised - with the
possibility of oopsing or worse.

Move the creation of the debugfs files to our registration phase, where
we announce our presence to the world when we are ready.

Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 --
 drivers/gpu/drm/i915/i915_dma.c | 2 ++
 drivers/gpu/drm/i915/i915_drv.c | 4 
 drivers/gpu/drm/i915/i915_drv.h | 6 --
 4 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 615cef736356..4a3546f114c6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5498,8 +5498,9 @@ void intel_display_crc_init(struct drm_device *dev)
}
 }
 
-int i915_debugfs_init(struct drm_minor *minor)
+int i915_debugfs_register(struct drm_i915_private *dev_priv)
 {
+   struct drm_minor *minor = dev_priv->dev->primary;
int ret, i;
 
ret = i915_forcewake_create(minor->debugfs_root, minor);
@@ -5525,8 +5526,9 @@ int i915_debugfs_init(struct drm_minor *minor)
minor->debugfs_root, minor);
 }
 
-void i915_debugfs_cleanup(struct drm_minor *minor)
+void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
 {
+   struct drm_minor *minor = dev_priv->dev->primary;
int i;
 
drm_debugfs_remove_files(i915_debugfs_list,
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 07edaed9d5a2..af0a6ce6f0b9 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1372,6 +1372,7 @@ static void i915_driver_register(struct drm_i915_private 
*dev_priv)
if (intel_vgpu_active(dev_priv))
I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
 
+   i915_debugfs_register(dev_priv);
i915_setup_sysfs(dev);
 
if (INTEL_INFO(dev_priv)->num_pipes) {
@@ -1397,6 +1398,7 @@ static void i915_driver_unregister(struct 
drm_i915_private *dev_priv)
acpi_video_unregister();
intel_opregion_unregister(dev_priv);
i915_teardown_sysfs(dev_priv->dev);
+   i915_debugfs_unregister(dev_priv);
i915_gem_shrinker_cleanup(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 943d7b222fd4..fa9e16b2247c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1761,10 +1761,6 @@ static struct drm_driver driver = {
.postclose = i915_driver_postclose,
.set_busid = drm_pci_set_busid,
 
-#if defined(CONFIG_DEBUG_FS)
-   .debugfs_init = i915_debugfs_init,
-   .debugfs_cleanup = i915_debugfs_cleanup,
-#endif
.gem_free_object = i915_gem_free_object,
.gem_vm_ops = _gem_vm_ops,
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9d9a4205992..8f2994ef4386 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3543,12 +3543,14 @@ int i915_verify_lists(struct drm_device *dev);
 #endif
 
 /* i915_debugfs.c */
-int i915_debugfs_init(struct drm_minor *minor);
-void i915_debugfs_cleanup(struct drm_minor *minor);
 #ifdef CONFIG_DEBUG_FS
+int i915_debugfs_register(struct drm_i915_private *dev_priv);
+void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
 int i915_debugfs_connector_add(struct drm_connector *connector);
 void intel_display_crc_init(struct drm_device *dev);
 #else
+static inline int i915_debugfs_register(struct drm_i915_private *) {return 0;}
+static inline void i915_debugfs_unregister(struct drm_i915_private *) {}
 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
 { return 0; }
 static inline void intel_display_crc_init(struct drm_device *dev) {}
-- 
2.8.1

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[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [v3,01/10] drm/i915: Skip idling an idle engine (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm/i915: Skip idling an idle engine 
(rev2)
URL   : https://patchwork.freedesktop.org/series/7792/
State : failure

== Summary ==

Series 7792v2 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/7792/revisions/2/mbox

Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (ro-bdw-i7-5557U)
pass   -> INCOMPLETE (ro-ilk1-i5-650)
pass   -> INCOMPLETE (ro-hsw-i3-4010u)
pass   -> INCOMPLETE (ro-bdw-i7-5600u)
pass   -> INCOMPLETE (ro-bdw-i5-5250u)
pass   -> INCOMPLETE (ro-snb-i7-2620M)
pass   -> INCOMPLETE (ro-skl-i7-6700hq)
pass   -> INCOMPLETE (ro-ivb2-i7-3770)
pass   -> INCOMPLETE (ro-byt-n2820)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup basic-flip-vs-modeset:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup basic-plain-flip:
pass   -> FAIL   (fi-hsw-i7-4770k)
Test kms_force_connector_basic:
Subgroup force-connector-state:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup force-edid:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup force-load-detect:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup prune-stale-modes:
pass   -> FAIL   (fi-hsw-i7-4770k)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> FAIL   (fi-hsw-i7-4770k)
Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup bad-nb-words-3:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup bad-pipe:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup bad-source:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup hang-read-crc-pipe-a:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup hang-read-crc-pipe-b:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup hang-read-crc-pipe-c:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup nonblocking-crc-pipe-a:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup nonblocking-crc-pipe-b:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup nonblocking-crc-pipe-c:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup read-crc-pipe-a:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup read-crc-pipe-a-frame-sequence:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup read-crc-pipe-b:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup read-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup read-crc-pipe-c:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup read-crc-pipe-c-frame-sequence:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup suspend-read-crc-pipe-a:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup suspend-read-crc-pipe-b:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-hsw-i7-4770k)
Test kms_setmode:
Subgroup basic-clone-single-crtc:
pass   -> FAIL   (fi-hsw-i7-4770k)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> FAIL   (fi-hsw-i7-4770k)
Subgroup basic-rte:
pass   -> FAIL   (fi-hsw-i7-4770k)

fi-hsw-i7-4770k  total:209  pass:156  dwarn:0   dfail:0   fail:34  skip:19 
ro-bdw-i5-5250u  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-bdw-i7-5557U  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-bdw-i7-5600u  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-bsw-n3050 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-byt-n2820 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-hsw-i3-4010u  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk-i7-620lm  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:1pass:0

Re: [Intel-gfx] [PATCH] drm: Register the debugfs interfaces after loading the driver

[Chris Wilson]

On Thu, May 26, 2016 at 01:35:18PM +0100, Chris Wilson wrote:
> In order to give the driver the chance to initialise the data structures
> that will be exposed through debugfs, perform driver->load() before
> registering the debugfs entries. (Otherwise it may be possible for
> userspace to cause an oops through the debugfs interfaces.) As the
> driver load is now before debugfs registration, make the registration
> non-fatal (as it simply prevents us exposing an optional debug facility
> and not hard ABI).

The alternative here would be for i915.ko to stop registering a
driver->debugfs_init and do it as part of its registration phase (like
sysfs).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

[Mika Kuoppala]

Chris Wilson  writes:

> [ text/plain ]
> This is so that we have symmetry with intel_lrc.c and avoid a source of
> if (i915.enable_execlists) layering violation within i915_gem_context.c -
> that is we move the specific handling of the dev_priv->kernel_context
> for legacy submission into the legacy submission code.
>
> This depends upon the init/fini ordering between contexts and engines
> already defined by intel_lrc.c, and also exporting the context alignment
> required for pinning the legacy context.
>
> v2: Separate out pin/unpin context funcs for greater symmetry with
> intel_lrc. One more step towards unifying behaviour between the two
> classes of engines and towards fixing another bug in i915_switch_context
> vs requests.
>
> Signed-off-by: Chris Wilson 

Reviewed-by: Mika Kuoppala 


> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 ++
>  drivers/gpu/drm/i915/i915_gem_context.c | 27 ++--
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 55 
> +
>  3 files changed, 60 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e4c8e341655c..19d0194c728f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -867,6 +867,8 @@ struct i915_gem_context {
>   u32 user_handle;
>  #define CONTEXT_NO_ZEROMAP   (1<<0)
>  
> + u32 ggtt_alignment;
> +
>   struct intel_context {
>   struct drm_i915_gem_object *state;
>   struct intel_ringbuffer *ringbuf;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index a3b11aac23a4..c620fe6c9d96 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -268,6 +268,8 @@ __create_hw_context(struct drm_device *dev,
>   list_add_tail(>link, _priv->context_list);
>   ctx->i915 = dev_priv;
>  
> + ctx->ggtt_alignment = get_context_alignment(dev_priv);
> +
>   if (dev_priv->hw_context_size) {
>   struct drm_i915_gem_object *obj =
>   i915_gem_alloc_context_obj(dev, 
> dev_priv->hw_context_size);
> @@ -413,26 +415,6 @@ int i915_gem_context_init(struct drm_device *dev)
>   return PTR_ERR(ctx);
>   }
>  
> - if (!i915.enable_execlists && ctx->engine[RCS].state) {
> - int ret;
> -
> - /* We may need to do things with the shrinker which
> -  * require us to immediately switch back to the default
> -  * context. This can cause a problem as pinning the
> -  * default context also requires GTT space which may not
> -  * be available. To avoid this we always pin the default
> -  * context.
> -  */
> - ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state,
> - get_context_alignment(dev_priv), 0);
> - if (ret) {
> - DRM_ERROR("Failed to pinned default global context 
> (error %d)\n",
> -   ret);
> - i915_gem_context_unreference(ctx);
> - return ret;
> - }
> - }
> -
>   dev_priv->kernel_context = ctx;
>  
>   DRM_DEBUG_DRIVER("%s context support initialized\n",
> @@ -469,9 +451,6 @@ void i915_gem_context_fini(struct drm_device *dev)
>  
>   lockdep_assert_held(>struct_mutex);
>  
> - if (!i915.enable_execlists && dctx->engine[RCS].state)
> - i915_gem_object_ggtt_unpin(dctx->engine[RCS].state);
> -
>   i915_gem_context_unreference(dctx);
>   dev_priv->kernel_context = NULL;
>  
> @@ -721,7 +700,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
>  
>   /* Trying to pin first makes error handling easier. */
>   ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
> - get_context_alignment(engine->i915),
> + to->ggtt_alignment,
>   0);
>   if (ret)
>   return ret;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a3978f9b..92bb376e5039 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2240,6 +2240,47 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring)
>   kfree(ring);
>  }
>  
> +static int intel_ring_context_pin(struct i915_gem_context *ctx,
> +   struct intel_engine_cs *engine)
> +{
> + struct intel_context *ce = >engine[engine->id];
> + int ret;
> +
> + lockdep_assert_held(>i915->dev->struct_mutex);
> +
> + if (ce->pin_count++)
> + return 0;
> +
> + if (ce->state) {
> + ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0);
> +  

[Intel-gfx] [PATCH] drm: Register the debugfs interfaces after loading the driver

[Chris Wilson]

In order to give the driver the chance to initialise the data structures
that will be exposed through debugfs, perform driver->load() before
registering the debugfs entries. (Otherwise it may be possible for
userspace to cause an oops through the debugfs interfaces.) As the
driver load is now before debugfs registration, make the registration
non-fatal (as it simply prevents us exposing an optional debug facility
and not hard ABI).

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/drm_debugfs.c | 13 ++---
 drivers/gpu/drm/drm_drv.c | 62 +++
 2 files changed, 54 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index 3bcf8e6a85b3..8f36e014fbd2 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -160,10 +160,8 @@ int drm_debugfs_init(struct drm_minor *minor, int minor_id,
ret = drm_debugfs_create_files(drm_debugfs_list, DRM_DEBUGFS_ENTRIES,
   minor->debugfs_root, minor);
if (ret) {
-   debugfs_remove(minor->debugfs_root);
-   minor->debugfs_root = NULL;
DRM_ERROR("Failed to create core drm debugfs files\n");
-   return ret;
+   goto err_root;
}
 
if (dev->driver->debugfs_init) {
@@ -171,10 +169,17 @@ int drm_debugfs_init(struct drm_minor *minor, int 
minor_id,
if (ret) {
DRM_ERROR("DRM: Driver failed to initialize "
  "/sys/kernel/debug/dri.\n");
-   return ret;
+   goto err_core;
}
}
return 0;
+
+err_core:
+   drm_debugfs_remove_files(drm_debugfs_list, DRM_DEBUGFS_ENTRIES, minor);
+err_root:
+   debugfs_remove(minor->debugfs_root);
+   minor->debugfs_root = NULL;
+   return ret;
 }
 
 
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index bff89226a344..82d1e80c2bf4 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -307,15 +307,9 @@ static int drm_minor_register(struct drm_device *dev, 
unsigned int type)
if (!minor)
return 0;
 
-   ret = drm_debugfs_init(minor, minor->index, drm_debugfs_root);
-   if (ret) {
-   DRM_ERROR("DRM: Failed to initialize /sys/kernel/debug/dri.\n");
-   return ret;
-   }
-
ret = device_add(minor->kdev);
if (ret)
-   goto err_debugfs;
+   return ret;
 
/* replace NULL with @minor so lookups will succeed from now on */
spin_lock_irqsave(_minor_lock, flags);
@@ -324,10 +318,36 @@ static int drm_minor_register(struct drm_device *dev, 
unsigned int type)
 
DRM_DEBUG("new minor registered %d\n", minor->index);
return 0;
+}
+
+static void drm_debugfs_register(struct drm_device *dev, unsigned int type)
+{
+   struct drm_minor *minor;
+
+   DRM_DEBUG("\n");
+   if (!drm_debugfs_root)
+   return;
+
+   minor = *drm_minor_get_slot(dev, type);
+   if (!minor)
+   return;
+
+   if (drm_debugfs_init(minor, minor->index, drm_debugfs_root))
+   DRM_ERROR("DRM: Failed to initialize /sys/kernel/debug/dri.\n");
+}
+
+static void drm_debugfs_unregister(struct drm_device *dev, unsigned int type)
+{
+   struct drm_minor *minor;
+
+   if (!drm_debugfs_root)
+   return;
+
+   minor = *drm_minor_get_slot(dev, type);
+   if (!minor || !device_is_registered(minor->kdev))
+   return;
 
-err_debugfs:
drm_debugfs_cleanup(minor);
-   return ret;
 }
 
 static void drm_minor_unregister(struct drm_device *dev, unsigned int type)
@@ -346,7 +366,6 @@ static void drm_minor_unregister(struct drm_device *dev, 
unsigned int type)
 
device_del(minor->kdev);
dev_set_drvdata(minor->kdev, NULL); /* safety belt */
-   drm_debugfs_cleanup(minor);
 }
 
 /**
@@ -460,6 +479,10 @@ EXPORT_SYMBOL(drm_put_dev);
 
 void drm_unplug_dev(struct drm_device *dev)
 {
+   drm_debugfs_unregister(dev, DRM_MINOR_LEGACY);
+   drm_debugfs_unregister(dev, DRM_MINOR_RENDER);
+   drm_debugfs_unregister(dev, DRM_MINOR_CONTROL);
+
/* for a USB device */
drm_minor_unregister(dev, DRM_MINOR_LEGACY);
drm_minor_unregister(dev, DRM_MINOR_RENDER);
@@ -759,6 +782,10 @@ int drm_dev_register(struct drm_device *dev, unsigned long 
flags)
goto err_minors;
}
 
+   drm_debugfs_register(dev, DRM_MINOR_CONTROL);
+   drm_debugfs_register(dev, DRM_MINOR_RENDER);
+   drm_debugfs_register(dev, DRM_MINOR_LEGACY);
+
ret = 0;
goto out_unlock;
 
@@ -800,6 +827,10 @@ void drm_dev_unregister(struct drm_device *dev)
list_for_each_entry_safe(r_list, list_temp, >maplist, head)
drm_legacy_rmmap(dev, r_list->map);

Re: [Intel-gfx] [PATCH v3 03/10] drm/i915: Treat kernel context as initialised

[Chris Wilson]

On Thu, May 26, 2016 at 12:51:45PM +0100, Chris Wilson wrote:
> On Thu, May 26, 2016 at 09:52:33AM +0100, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 4e0aa7e9d5da..203b7952052a 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -2278,7 +2278,14 @@ static int intel_init_ring_buffer(struct drm_device 
> > *dev,
> > if (ret)
> > goto error;
> >  
> > -   ce->initialised = false;
> > +   /* The kernel context is only used as a placeholder
> > +* for flushing the active context. It is never used
> > +* for submitting rendering and as such never requires
> > +* the golden render context, and so we can skip
> > +* emitting it when we switch to the kernel context
> > +* (during eviction).
> > +*/
> > +   ce->initialised = true;
> 
> This is really too much of a hack to live. So long as we avoid the
> switch during suspend, we can let this patch drop.

Hmm, but marking it as initialised stops us from having to allocate
the renderstate during eviction. :|

So far, this seems to be the least clumsy approach.
-Chris

-- 
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Re: [Intel-gfx] [PATCH v3 02/10] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

[Chris Wilson]

On Thu, May 26, 2016 at 03:04:11PM +0300, Mika Kuoppala wrote:
> > +   if (ce->state) {
> > +   i915_gem_context_reference(kctx);
> > +
> > +   /* We may need to do things with the shrinker which
> > +* require us to immediately switch back to the default
> > +* context. This can cause a problem as pinning the
> > +* default context also requires GTT space which may not
> > +* be available. To avoid this we always pin the default
> > +* context.
> > +*/
> > +   ret = i915_gem_obj_ggtt_pin(ce->state,
> > +   kctx->ggtt_alignment,
> > +   0);
> > +   if (ret)
> > +   goto error;
> > +
> 
> If you fail here, you will unpin regardless. Is that a problem?

To be here, ce->pin_count == 1 (because it is locked and we only init if
ce->pin_count == 0 on entry). So on error we restore it back to 0.
-Chris

-- 
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Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Fix NULL pointer deference when out of PLLs in IVB

[Ander Conselvan De Oliveira]

On Tue, 2016-05-24 at 07:00 +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Fix NULL pointer deference when out of PLLs in IVB
> URL   : https://patchwork.freedesktop.org/series/7458/
> State : failure
> 
> == Summary ==
> 
> Series 7458v1 drm/i915: Fix NULL pointer deference when out of PLLs in IVB
> http://patchwork.freedesktop.org/api/1.0/series/7458/revisions/1/mbox
> 
> Test gem_busy:
> Subgroup basic-parallel-blt:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)

*ERROR* Potential atomic update failure on pipe A

https://bugs.freedesktop.org/show_bug.cgi?id=95632

> Subgroup basic-parallel-vebox:
> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> Test gem_ringfill:
> Subgroup basic-default:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)

Same here.

> Subgroup basic-default-interruptible:
> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> Test gem_storedw_loop:
> Subgroup basic-default:
> pass   -> INCOMPLETE (ro-byt-n2820)

BYT doesn't use the shared DPLL code that is changed by this patch.

> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> Test kms_frontbuffer_tracking:
> Subgroup basic:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)

More atomic update failure.

> Test kms_pipe_crc_basic:
> Subgroup bad-pipe:
> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> Subgroup bad-source:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)

Here too.

> Test kms_setmode:
> Subgroup basic-clone-single-crtc:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)


Here too.


Patch pushed to dinq. Thanks for reviews.

Ander

> Test kms_sink_crc_basic:
> pass   -> SKIP   (ro-skl-i7-6700hq)
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> fail   -> DMESG-WARN (ro-skl-i7-6700hq)
> Test pm_rps:
> Subgroup basic-api:
> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> 
> ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
> ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
> ro-bdw-i7-5600u  total:209  pass:180  dwarn:0   dfail:0   fail:1   skip:28 
> ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
> ro-byt-n2820 total:10   pass:9dwarn:0   dfail:0   fail:0   skip:0  
> ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
> ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
> ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
> ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
> ro-skl-i7-6700hq total:204  pass:174  dwarn:8   dfail:0   fail:0   skip:22 
> ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
> fi-bsw-n3050 failed to connect after reboot
> 
> Results at /archive/results/CI_IGT_test/RO_Patchwork_983/
> 
> 8621fb5 drm-intel-nightly: 2016y-05m-23d-18h-18m-33s UTC integration manifest
> a62bb7c drm/i915: Fix NULL pointer deference when out of PLLs in IVB
> 
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[Intel-gfx] [PATCH] drm: Store the plane's index

[Chris Wilson]

Currently the plane's index is determined by walking the list of all
planes in the mode and finding the position of that plane in the list. A
linear walk, especially a linear walk within a linear walk as frequently
conceived by i915.ko [O(N^2)] quickly comes to dominate profiles.

The plane's index is constant for as long as no earlier planes are
removed from the list. For most drivers, planes are static, determined
at boot and then untouched until shutdown. Storing the index upon
construction and then only walking the tail upon removal should
be a major improvement for all.

v2: Convert drm_crtc_index() and drm_encoder_index() as well.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Cc: Matt Roper 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/drm_crtc.c | 98 ++
 include/drm/drm_crtc.h | 25 ++--
 2 files changed, 43 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index d2a6d958ca76..4d978099aa17 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -692,7 +692,7 @@ int drm_crtc_init_with_planes(struct drm_device *dev, 
struct drm_crtc *crtc,
crtc->base.properties = >properties;
 
list_add_tail(>head, >crtc_list);
-   config->num_crtc++;
+   crtc->index = config->num_crtc++;
 
crtc->primary = primary;
crtc->cursor = cursor;
@@ -721,6 +721,11 @@ EXPORT_SYMBOL(drm_crtc_init_with_planes);
 void drm_crtc_cleanup(struct drm_crtc *crtc)
 {
struct drm_device *dev = crtc->dev;
+   struct drm_crtc *other;
+
+   other = list_next_entry(crtc, head);
+   list_for_each_entry_from(other, >mode_config.crtc_list, head)
+   other->index--;
 
kfree(crtc->gamma_store);
crtc->gamma_store = NULL;
@@ -741,29 +746,6 @@ void drm_crtc_cleanup(struct drm_crtc *crtc)
 }
 EXPORT_SYMBOL(drm_crtc_cleanup);
 
-/**
- * drm_crtc_index - find the index of a registered CRTC
- * @crtc: CRTC to find index for
- *
- * Given a registered CRTC, return the index of that CRTC within a DRM
- * device's list of CRTCs.
- */
-unsigned int drm_crtc_index(struct drm_crtc *crtc)
-{
-   unsigned int index = 0;
-   struct drm_crtc *tmp;
-
-   drm_for_each_crtc(tmp, crtc->dev) {
-   if (tmp == crtc)
-   return index;
-
-   index++;
-   }
-
-   BUG();
-}
-EXPORT_SYMBOL(drm_crtc_index);
-
 /*
  * drm_mode_remove - remove and free a mode
  * @connector: connector list to modify
@@ -1166,7 +1148,7 @@ int drm_encoder_init(struct drm_device *dev,
}
 
list_add_tail(>head, >mode_config.encoder_list);
-   dev->mode_config.num_encoder++;
+   encoder->index = dev->mode_config.num_encoder++;
 
 out_put:
if (ret)
@@ -1180,29 +1162,6 @@ out_unlock:
 EXPORT_SYMBOL(drm_encoder_init);
 
 /**
- * drm_encoder_index - find the index of a registered encoder
- * @encoder: encoder to find index for
- *
- * Given a registered encoder, return the index of that encoder within a DRM
- * device's list of encoders.
- */
-unsigned int drm_encoder_index(struct drm_encoder *encoder)
-{
-   unsigned int index = 0;
-   struct drm_encoder *tmp;
-
-   drm_for_each_encoder(tmp, encoder->dev) {
-   if (tmp == encoder)
-   return index;
-
-   index++;
-   }
-
-   BUG();
-}
-EXPORT_SYMBOL(drm_encoder_index);
-
-/**
  * drm_encoder_cleanup - cleans up an initialised encoder
  * @encoder: encoder to cleanup
  *
@@ -1211,6 +1170,11 @@ EXPORT_SYMBOL(drm_encoder_index);
 void drm_encoder_cleanup(struct drm_encoder *encoder)
 {
struct drm_device *dev = encoder->dev;
+   struct drm_encoder *other;
+
+   other = list_next_entry(encoder, head);
+   list_for_each_entry_from(other, >mode_config.encoder_list, head)
+   other->index--;
 
drm_modeset_lock_all(dev);
drm_mode_object_unregister(dev, >base);
@@ -1300,7 +1264,7 @@ int drm_universal_plane_init(struct drm_device *dev, 
struct drm_plane *plane,
plane->type = type;
 
list_add_tail(>head, >plane_list);
-   config->num_total_plane++;
+   plane->index = config->num_total_plane++;
if (plane->type == DRM_PLANE_TYPE_OVERLAY)
config->num_overlay_plane++;
 
@@ -1367,6 +1331,7 @@ EXPORT_SYMBOL(drm_plane_init);
 void drm_plane_cleanup(struct drm_plane *plane)
 {
struct drm_device *dev = plane->dev;
+   struct drm_plane *other;
 
drm_modeset_lock_all(dev);
kfree(plane->format_types);
@@ -1374,6 +1339,10 @@ void drm_plane_cleanup(struct drm_plane *plane)
 
BUG_ON(list_empty(>head));
 
+   other = list_next_entry(plane, head);
+   list_for_each_entry_from(other, >mode_config.plane_list, head)
+   other->index--;
+
list_del(>head);

Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: No need to wait for idle on L3 remap

[Joonas Lahtinen]

On to, 2016-05-26 at 09:52 +0100, Chris Wilson wrote:
> As the L3 remapping is applied before the next execution, there is no
> need to wait until all previous uses are idle, the application will not
> occur any sooner.
> 
> Signed-off-by: Chris Wilson 

Reviewed-by: Joonas Lahtinen 

> ---
>  drivers/gpu/drm/i915/i915_sysfs.c | 7 ---
>  1 file changed, 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
> b/drivers/gpu/drm/i915/i915_sysfs.c
> index 02507bfc8def..a6e90fe05a1e 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -227,13 +227,6 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
>   }
>   }
>  
> - ret = i915_gpu_idle(drm_dev);
> - if (ret) {
> - kfree(temp);
> - mutex_unlock(_dev->struct_mutex);
> - return ret;
> - }
> -
>   /* TODO: Ideally we really want a GPU reset here to make sure errors
>    * aren't propagated. Since I cannot find a stable way to reset the GPU
>    * at this point it is left as a TODO.
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: No need to wait for idle on L3 remap

[Mika Kuoppala]

Chris Wilson  writes:

> [ text/plain ]
> As the L3 remapping is applied before the next execution, there is no
> need to wait until all previous uses are idle, the application will not
> occur any sooner.
>
> Signed-off-by: Chris Wilson 

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/i915_sysfs.c | 7 ---
>  1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
> b/drivers/gpu/drm/i915/i915_sysfs.c
> index 02507bfc8def..a6e90fe05a1e 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -227,13 +227,6 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
>   }
>   }
>  
> - ret = i915_gpu_idle(drm_dev);
> - if (ret) {
> - kfree(temp);
> - mutex_unlock(_dev->struct_mutex);
> - return ret;
> - }
> -
>   /* TODO: Ideally we really want a GPU reset here to make sure errors
>* aren't propagated. Since I cannot find a stable way to reset the GPU
>* at this point it is left as a TODO.
> -- 
> 2.8.1
>
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Re: [Intel-gfx] [PATCH v3 02/10] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

[Mika Kuoppala]

Chris Wilson  writes:

> [ text/plain ]
> This is so that we have symmetry with intel_lrc.c and avoid a source of
> if (i915.enable_execlists) layering violation within i915_gem_context.c -
> that is we move the specific handling of the dev_priv->kernel_context
> for legacy submission into the legacy submission code.
>
> This depends upon the init/fini ordering between contexts and engines
> already defined by intel_lrc.c, and also exporting the context alignment
> required for pinning the legacy context.
>
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 ++
>  drivers/gpu/drm/i915/i915_gem_context.c | 27 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 31 +++
>  3 files changed, 36 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e4c8e341655c..19d0194c728f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -867,6 +867,8 @@ struct i915_gem_context {
>   u32 user_handle;
>  #define CONTEXT_NO_ZEROMAP   (1<<0)
>  
> + u32 ggtt_alignment;
> +
>   struct intel_context {
>   struct drm_i915_gem_object *state;
>   struct intel_ringbuffer *ringbuf;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index a3b11aac23a4..c620fe6c9d96 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -268,6 +268,8 @@ __create_hw_context(struct drm_device *dev,
>   list_add_tail(>link, _priv->context_list);
>   ctx->i915 = dev_priv;
>  
> + ctx->ggtt_alignment = get_context_alignment(dev_priv);
> +
>   if (dev_priv->hw_context_size) {
>   struct drm_i915_gem_object *obj =
>   i915_gem_alloc_context_obj(dev, 
> dev_priv->hw_context_size);
> @@ -413,26 +415,6 @@ int i915_gem_context_init(struct drm_device *dev)
>   return PTR_ERR(ctx);
>   }
>  
> - if (!i915.enable_execlists && ctx->engine[RCS].state) {
> - int ret;
> -
> - /* We may need to do things with the shrinker which
> -  * require us to immediately switch back to the default
> -  * context. This can cause a problem as pinning the
> -  * default context also requires GTT space which may not
> -  * be available. To avoid this we always pin the default
> -  * context.
> -  */
> - ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state,
> - get_context_alignment(dev_priv), 0);
> - if (ret) {
> - DRM_ERROR("Failed to pinned default global context 
> (error %d)\n",
> -   ret);
> - i915_gem_context_unreference(ctx);
> - return ret;
> - }
> - }
> -
>   dev_priv->kernel_context = ctx;
>  
>   DRM_DEBUG_DRIVER("%s context support initialized\n",
> @@ -469,9 +451,6 @@ void i915_gem_context_fini(struct drm_device *dev)
>  
>   lockdep_assert_held(>struct_mutex);
>  
> - if (!i915.enable_execlists && dctx->engine[RCS].state)
> - i915_gem_object_ggtt_unpin(dctx->engine[RCS].state);
> -
>   i915_gem_context_unreference(dctx);
>   dev_priv->kernel_context = NULL;
>  
> @@ -721,7 +700,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
>  
>   /* Trying to pin first makes error handling easier. */
>   ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
> - get_context_alignment(engine->i915),
> + to->ggtt_alignment,
>   0);
>   if (ret)
>   return ret;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a3978f9b..4e0aa7e9d5da 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2244,6 +2244,8 @@ static int intel_init_ring_buffer(struct drm_device 
> *dev,
> struct intel_engine_cs *engine)
>  {
>   struct drm_i915_private *dev_priv = to_i915(dev);
> + struct i915_gem_context *kctx = dev_priv->kernel_context;
> + struct intel_context *ce = >engine[engine->id];
>   struct intel_ringbuffer *ringbuf;
>   int ret;
>  
> @@ -2260,6 +2262,25 @@ static int intel_init_ring_buffer(struct drm_device 
> *dev,
>  
>   init_waitqueue_head(>irq_queue);
>  
> + if (ce->state) {
> + i915_gem_context_reference(kctx);
> +
> + /* We may need to do things with the shrinker which
> +  * require us to immediately switch back to the default
> +  * context. This can cause a problem as pinning the
> +

Re: [Intel-gfx] [PATCH v3 09/10] drm/i915: Remove superfluous powersave work flushing

[Chris Wilson]

On Thu, May 26, 2016 at 02:45:09PM +0300, Ville Syrjälä wrote:
> On Thu, May 26, 2016 at 09:52:39AM +0100, Chris Wilson wrote:
> > Instead of flushing the outstanding enabling, remember the requested
> > frequency to apply when the powersave work runs.
> 
> I didn't see a patch to move the frequency init to happen before
> debugfs init. So methinks we still need the flush.

Considering debugfs_init is exposing us to userspace, it should be part
of the registration phase (i.e. last thing) after we have all the hw
probed / minimally prepared.
-Chris

-- 
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Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

[Maarten Lankhorst]

Op 26-05-16 om 13:46 schreef Ville Syrjälä:
> On Thu, May 26, 2016 at 01:38:02PM +0200, Maarten Lankhorst wrote:
>> Op 26-05-16 om 13:35 schreef Ville Syrjälä:
>>> On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote:
 Add some minor changes to prevent bisect breaking.

 Main change is making sure crtc_state is not freed while the mmio update 
 still runs.
>>> I didn't see fixes for the other obvious issues.
>> This doesn't reapply nonblocking unpin/pageflip, which caused all problems. 
>> So what issues do you mean?
> The two I now remember off the top of my head were the killing of the
> flip tracepoints and the annoying dmesg spamming.
>
Flip tracepoint is still there, but I can remove the 'Finished page flip' spam 
from patch 5.
Patch 4 accidentally seems to call trace_i915_flip_request twice, which was 
fixed in patch 5.

I'll send new versions for those 2 patches.

~Maarten

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Re: [Intel-gfx] [PATCH v3 03/10] drm/i915: Treat kernel context as initialised

[Chris Wilson]

On Thu, May 26, 2016 at 09:52:33AM +0100, Chris Wilson wrote:
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4e0aa7e9d5da..203b7952052a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2278,7 +2278,14 @@ static int intel_init_ring_buffer(struct drm_device 
> *dev,
>   if (ret)
>   goto error;
>  
> - ce->initialised = false;
> + /* The kernel context is only used as a placeholder
> +  * for flushing the active context. It is never used
> +  * for submitting rendering and as such never requires
> +  * the golden render context, and so we can skip
> +  * emitting it when we switch to the kernel context
> +  * (during eviction).
> +  */
> + ce->initialised = true;

This is really too much of a hack to live. So long as we avoid the
switch during suspend, we can let this patch drop.
-Chris

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Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

[Ville Syrjälä]

On Thu, May 26, 2016 at 01:38:02PM +0200, Maarten Lankhorst wrote:
> Op 26-05-16 om 13:35 schreef Ville Syrjälä:
> > On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote:
> >> Add some minor changes to prevent bisect breaking.
> >>
> >> Main change is making sure crtc_state is not freed while the mmio update 
> >> still runs.
> > I didn't see fixes for the other obvious issues.
> This doesn't reapply nonblocking unpin/pageflip, which caused all problems. 
> So what issues do you mean?

The two I now remember off the top of my head were the killing of the
flip tracepoints and the annoying dmesg spamming.

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH v3 09/10] drm/i915: Remove superfluous powersave work flushing

[Ville Syrjälä]

On Thu, May 26, 2016 at 09:52:39AM +0100, Chris Wilson wrote:
> Instead of flushing the outstanding enabling, remember the requested
> frequency to apply when the powersave work runs.

I didn't see a patch to move the frequency init to happen before
debugfs init. So methinks we still need the flush.

> 
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 30 ++
>  drivers/gpu/drm/i915/i915_sysfs.c   | 42 
> +++--
>  2 files changed, 10 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 615cef736356..a49c7a0019b7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1193,8 +1193,6 @@ static int i915_frequency_info(struct seq_file *m, void 
> *unused)
>  
>   intel_runtime_pm_get(dev_priv);
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
>   if (IS_GEN5(dev)) {
>   u16 rgvswctl = I915_READ16(MEMSWCTL);
>   u16 rgvstat = I915_READ16(MEMSTAT_ILK);
> @@ -1881,8 +1879,6 @@ static int i915_ring_freq_table(struct seq_file *m, 
> void *unused)
>  
>   intel_runtime_pm_get(dev_priv);
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
>   ret = mutex_lock_interruptible(_priv->rps.hw_lock);
>   if (ret)
>   goto out;
> @@ -4970,20 +4966,11 @@ i915_max_freq_get(void *data, u64 *val)
>  {
>   struct drm_device *dev = data;
>   struct drm_i915_private *dev_priv = dev->dev_private;
> - int ret;
>  
>   if (INTEL_INFO(dev)->gen < 6)
>   return -ENODEV;
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
> - ret = mutex_lock_interruptible(_priv->rps.hw_lock);
> - if (ret)
> - return ret;
> -
>   *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
> - mutex_unlock(_priv->rps.hw_lock);
> -
>   return 0;
>  }
>  
> @@ -4998,8 +4985,6 @@ i915_max_freq_set(void *data, u64 val)
>   if (INTEL_INFO(dev)->gen < 6)
>   return -ENODEV;
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
>   DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
>  
>   ret = mutex_lock_interruptible(_priv->rps.hw_lock);
> @@ -5037,20 +5022,11 @@ i915_min_freq_get(void *data, u64 *val)
>  {
>   struct drm_device *dev = data;
>   struct drm_i915_private *dev_priv = dev->dev_private;
> - int ret;
>  
> - if (INTEL_INFO(dev)->gen < 6)
> + if (INTEL_GEN(dev_priv) < 6)
>   return -ENODEV;
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
> - ret = mutex_lock_interruptible(_priv->rps.hw_lock);
> - if (ret)
> - return ret;
> -
>   *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
> - mutex_unlock(_priv->rps.hw_lock);
> -
>   return 0;
>  }
>  
> @@ -5062,11 +5038,9 @@ i915_min_freq_set(void *data, u64 val)
>   u32 hw_max, hw_min;
>   int ret;
>  
> - if (INTEL_INFO(dev)->gen < 6)
> + if (INTEL_GEN(dev_priv) < 6)
>   return -ENODEV;
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
>   DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
>  
>   ret = mutex_lock_interruptible(_priv->rps.hw_lock);
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
> b/drivers/gpu/drm/i915/i915_sysfs.c
> index a6e90fe05a1e..915e97cdc4d5 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -271,8 +271,6 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   int ret;
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
>   intel_runtime_pm_get(dev_priv);
>  
>   mutex_lock(_priv->rps.hw_lock);
> @@ -303,19 +301,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>   struct drm_minor *minor = dev_to_drm_minor(kdev);
>   struct drm_device *dev = minor->dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
> - int ret;
>  
> - flush_delayed_work(_priv->rps.delayed_resume_work);
> -
> - intel_runtime_pm_get(dev_priv);
> -
> - mutex_lock(_priv->rps.hw_lock);
> - ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
> - mutex_unlock(_priv->rps.hw_lock);
> -
> - intel_runtime_pm_put(dev_priv);
> -
> - return snprintf(buf, PAGE_SIZE, "%d\n", ret);
> + return snprintf(buf, PAGE_SIZE, "%d\n",
> + intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
>  }
>  
>  static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
> @@ -335,15 +323,10 @@ static ssize_t gt_max_freq_mhz_show(struct device 
> *kdev, struct device_attribute
>   struct drm_minor *minor = dev_to_drm_minor(kdev);
>   struct drm_device *dev = minor->dev;
>   struct 

Re: [Intel-gfx] [PATCH v3 06/10] drm/i915: Split idling from forcing context switch

[Joonas Lahtinen]

On to, 2016-05-26 at 09:52 +0100, Chris Wilson wrote:
> We only need to force a switch to the kernel context placeholder during
> eviction. All other uses of i915_gpu_idle() just want to wait until
> existing work on the GPU is idle. Rename i915_gpu_idle() to
> i915_gem_wait_for_idle() to avoid any implications about "parking" the
> context first.
> 
> v2: Tweak an error message if the wait fails for the ilk vtd w/a
> 

Reviewed-by: Joonas Lahtinen 

> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  drivers/gpu/drm/i915/i915_gem.c  | 20 +++--
>  drivers/gpu/drm/i915/i915_gem_evict.c| 51 
> +---
>  drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
>  drivers/gpu/drm/i915/i915_gem_shrinker.c |  2 +-
>  6 files changed, 56 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ac7e5692496d..615cef736356 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4941,7 +4941,7 @@ i915_drop_caches_set(void *data, u64 val)
>   return ret;
>  
>   if (val & DROP_ACTIVE) {
> - ret = i915_gpu_idle(dev);
> + ret = i915_gem_wait_for_idle(dev_priv);
>   if (ret)
>   goto unlock;
>   }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 19d0194c728f..b9d9a4205992 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3285,7 +3285,7 @@ int i915_gem_init_engines(struct drm_device *dev);
>  int __must_check i915_gem_init_hw(struct drm_device *dev);
>  void i915_gem_init_swizzling(struct drm_device *dev);
>  void i915_gem_cleanup_engines(struct drm_device *dev);
> -int __must_check i915_gpu_idle(struct drm_device *dev);
> +int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv);
>  int __must_check i915_gem_suspend(struct drm_device *dev);
>  void __i915_add_request(struct drm_i915_gem_request *req,
>   struct drm_i915_gem_object *batch_obj,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 61812a53e56d..e94758850c77 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3420,29 +3420,17 @@ int __i915_vma_unbind_no_wait(struct i915_vma *vma)
>   return __i915_vma_unbind(vma, false);
>  }
>  
> -int i915_gpu_idle(struct drm_device *dev)
> +int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
>  {
> - struct drm_i915_private *dev_priv = dev->dev_private;
>   struct intel_engine_cs *engine;
>   int ret;
>  
> + lockdep_assert_held(_priv->dev->struct_mutex);
> +
>   for_each_engine(engine, dev_priv) {
>   if (engine->last_context == NULL)
>   continue;
>  
> - if (!i915.enable_execlists) {
> - struct drm_i915_gem_request *req;
> -
> - req = i915_gem_request_alloc(engine, NULL);
> - if (IS_ERR(req))
> - return PTR_ERR(req);
> -
> - ret = i915_switch_context(req);
> - i915_add_request_no_flush(req);
> - if (ret)
> - return ret;
> - }
> -
>   ret = intel_engine_idle(engine);
>   if (ret)
>   return ret;
> @@ -4703,7 +4691,7 @@ i915_gem_suspend(struct drm_device *dev)
>   int ret = 0;
>  
>   mutex_lock(>struct_mutex);
> - ret = i915_gpu_idle(dev);
> + ret = i915_gem_wait_for_idle(dev_priv);
>   if (ret)
>   goto err;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c 
> b/drivers/gpu/drm/i915/i915_gem_evict.c
> index b144c3f5c650..5741b58d186c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> @@ -33,6 +33,37 @@
>  #include "intel_drv.h"
>  #include "i915_trace.h"
>  
> +static int switch_to_pinned_context(struct drm_i915_private *dev_priv)
> +{
> + struct intel_engine_cs *engine;
> +
> + if (i915.enable_execlists)
> + return 0;
> +
> + for_each_engine(engine, dev_priv) {
> + struct drm_i915_gem_request *req;
> + int ret;
> +
> + if (engine->last_context == NULL)
> + continue;
> +
> + if (engine->last_context == dev_priv->kernel_context)
> + continue;
> +
> + req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
> + if (IS_ERR(req))
> + return PTR_ERR(req);
> +
> + ret = i915_switch_context(req);
> + i915_add_request_no_flush(req);
> + if (ret)
> + 

Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

[Maarten Lankhorst]

Op 26-05-16 om 13:35 schreef Ville Syrjälä:
> On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote:
>> Add some minor changes to prevent bisect breaking.
>>
>> Main change is making sure crtc_state is not freed while the mmio update 
>> still runs.
> I didn't see fixes for the other obvious issues.
This doesn't reapply nonblocking unpin/pageflip, which caused all problems. So 
what issues do you mean?

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Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

[Ville Syrjälä]

On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote:
> Add some minor changes to prevent bisect breaking.
> 
> Main change is making sure crtc_state is not freed while the mmio update 
> still runs.

I didn't see fixes for the other obvious issues.

> 
> Maarten Lankhorst (9):
>   drm/i915: Allow mmio updates on all platforms, v3.
>   drm/i915: Convert flip_work to a list, v2.
>   drm/i915: Add the exclusive fence to plane_state.
>   drm/i915: Rework intel_crtc_page_flip to be almost atomic, v4.
>   drm/i915: Remove cs based page flip support, v2.
>   drm/i915: Remove use_mmio_flip kernel parameter.
>   drm/i915: Remove queue_flip pointer.
>   drm/i915: Remove reset_counter from intel_crtc.
>   drm/i915: Pass atomic states to fbc update functions.
> 
>  drivers/gpu/drm/i915/i915_debugfs.c   |   89 ++-
>  drivers/gpu/drm/i915/i915_drv.h   |5 -
>  drivers/gpu/drm/i915/i915_irq.c   |  120 +---
>  drivers/gpu/drm/i915/i915_params.c|5 -
>  drivers/gpu/drm/i915/i915_params.h|1 -
>  drivers/gpu/drm/i915/intel_atomic_plane.c |1 +
>  drivers/gpu/drm/i915/intel_display.c  | 1118 
> -
>  drivers/gpu/drm/i915/intel_drv.h  |   37 +-
>  drivers/gpu/drm/i915/intel_fbc.c  |   39 +-
>  drivers/gpu/drm/i915/intel_lrc.c  |4 +-
>  10 files changed, 417 insertions(+), 1002 deletions(-)
> 
> -- 
> 2.5.5
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH v3 07/10] drm/i915: Only switch to default context when evicting from GGTT

[Joonas Lahtinen]

On to, 2016-05-26 at 09:52 +0100, Chris Wilson wrote:
> The contexts only pin space within the global GTT. Therefore forcing the
> switch to the perma-pinned kernel context only has an effect when trying
> to evict from and find room within the global GTT. We can then restrict
> the switch to only when operating on the default context. This is mostly
> a no-op as full-ppgtt only exists with execlists at present which skips
> the context switch anyway.
> 

Reviewed-by: Joonas Lahtinen 

> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_gem_evict.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c 
> b/drivers/gpu/drm/i915/i915_gem_evict.c
> index 5741b58d186c..3c1280ec7ff6 100644
> --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> @@ -183,9 +183,11 @@ none:
>   if (pass++ == 0) {
>   struct drm_i915_private *dev_priv = to_i915(dev);
>  
> - ret = switch_to_pinned_context(dev_priv);
> - if (ret)
> - return ret;
> + if (i915_is_ggtt(vm)) {
> + ret = switch_to_pinned_context(dev_priv);
> + if (ret)
> + return ret;
> + }
>  
>   ret = i915_gem_wait_for_idle(dev_priv);
>   if (ret)
> @@ -300,9 +302,11 @@ int i915_gem_evict_vm(struct i915_address_space *vm, 
> bool do_idle)
>   if (do_idle) {
>   struct drm_i915_private *dev_priv = to_i915(vm->dev);
>  
> - ret = switch_to_pinned_context(dev_priv);
> - if (ret)
> - return ret;
> + if (i915_is_ggtt(vm)) {
> + ret = switch_to_pinned_context(dev_priv);
> + if (ret)
> + return ret;
> + }
>  
>   ret = i915_gem_wait_for_idle(dev_priv);
>   if (ret)
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCHv6 5/5] drm/i915/dp: Enable Upfront link training for typeC DP support on BXT

[Ville Syrjälä]

On Thu, May 26, 2016 at 10:03:22AM +, R, Durgadoss wrote:
> 
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Wednesday, May 25, 2016 9:05 PM
> > To: R, Durgadoss 
> > Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander
> > 
> > Subject: Re: [Intel-gfx] [PATCHv6 5/5] drm/i915/dp: Enable Upfront link
> > training for typeC DP support on BXT
> > 
> > On Fri, May 20, 2016 at 02:29:02PM +0530, Durgadoss R wrote:
> > > To support USB type C alternate DP mode, the display driver needs to
> > > know the number of lanes required by the DP panel as well as number
> > > of lanes that can be supported by the type-C cable. Sometimes, the
> > > type-C cable may limit the bandwidth even if Panel can support
> > > more lanes. To address these scenarios, the display driver will
> > > start link training with max lanes, and if that fails, the driver
> > > falls back to x2 lanes; and repeats this procedure for all
> > > bandwidth/lane configurations.
> > >
> > > * Since link training is done before modeset only the port
> > >   (and not pipe/planes) and its associated PLLs are enabled.
> > > * On DP hotplug: Directly start link training on the DP encoder.
> > > * On Connected boot scenarios: When booted with an LFP and a DP,
> > >   sometimes BIOS brings up DP. In these cases, we disable the
> > >   crtc and then do upfront link training; and bring it back up.
> > > * All local changes made for upfront link training are reset
> > >   to their previous values once it is done; so that the
> > >   subsequent modeset is not aware of these changes.
> > >
> > > Changes since v5:
> > > * Moved retry logic in upfront to intel_dp.c so that it
> > >   can be used for all platforms.
> > > Changes since v4:
> > > * Removed usage of crtc_state in upfront link training;
> > >   Hence no need to find free crtc to do upfront now.
> > > * Re-enable crtc if it was disabled for upfront.
> > > * Use separate variables to track max lane count
> > >   and link rate found by upfront, without modifying
> > >   the original DPCD read from panel.
> > > Changes since v3:
> > > * Fixed a return value on BXT check
> > > * Reworked on top of bxt_ddi_pll_select split from Ander
> > > * Renamed from ddi_upfront to bxt_upfront since the
> > >   upfront logic includes BXT specific functions for now.
> > > Changes since v2:
> > > * Rebased on top of latest dpll_mgr.c code and
> > >   latest HPD related clean ups.
> > > * Corrected return values from upfront (Ander)
> > > * Corrected atomic locking for upfront in intel_dp.c (Ville)
> > > Changes since v1:
> > > *  all pll related functions inside ddi.c
> > >
> > > Signed-off-by: Durgadoss R 
> > > ---
> > >  drivers/gpu/drm/i915/intel_ddi.c |  45 ++
> > >  drivers/gpu/drm/i915/intel_dp.c  | 179
> > +--
> > >  drivers/gpu/drm/i915/intel_drv.h |   8 ++
> > >  3 files changed, 226 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index 7e6331a..8d224bf 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -2330,6 +2330,51 @@ intel_ddi_init_hdmi_connector(struct
> > intel_digital_port *intel_dig_port)
> > >   return connector;
> > >  }
> > >
> > > +bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
> > > + int clock, uint8_t lane_count)
> > > +{
> > > + struct intel_connector *connector = intel_dp->attached_connector;
> > > + struct intel_encoder *encoder = connector->encoder;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + struct intel_shared_dpll *pll;
> > > + struct intel_shared_dpll_config tmp_pll_config;
> > > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > > + enum intel_dpll_id dpll_id = (enum intel_dpll_id)dig_port->port;
> > > +
> > > + /*
> > > +  * FIXME: Works only for BXT.
> > > +  * Select the required PLL. This works for platforms where
> > > +  * there is no shared DPLL.
> > > +  */
> > > + pll = _priv->shared_dplls[dpll_id];
> > > + if (WARN_ON(pll->active_mask)) {
> > > + DRM_ERROR("Shared DPLL already in use.
> > active_mask:%x\n", pll->active_mask);
> > > + return false;
> > > + }
> > > +
> > > + tmp_pll_config = pll->config;
> > > +
> > > + if (!bxt_ddi_dp_set_dpll_hw_state(clock, >config.hw_state)) {
> > > + DRM_ERROR("Could not setup DPLL\n");
> > > + pll->config = tmp_pll_config;
> > > + return false;
> > > + }
> > > +
> > > + /* Enable PLL followed by port */
> > > + pll->funcs.enable(dev_priv, pll);
> > > + intel_ddi_pre_enable_dp(encoder, clock, lane_count, pll);
> > > +
> > > + DRM_DEBUG_KMS("Upfront link train %s: link_clock:%d
> > lanes:%d\n",
> > > + intel_dp->train_set_valid ? "Passed" : "Failed", clock, lane_count);
> > > +

Re: [Intel-gfx] [PATCH] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

[Joonas Lahtinen]

On to, 2016-05-26 at 12:18 +0100, Chris Wilson wrote:
> This is so that we have symmetry with intel_lrc.c and avoid a source of
> if (i915.enable_execlists) layering violation within i915_gem_context.c -
> that is we move the specific handling of the dev_priv->kernel_context
> for legacy submission into the legacy submission code.
> 
> This depends upon the init/fini ordering between contexts and engines
> already defined by intel_lrc.c, and also exporting the context alignment
> required for pinning the legacy context.
> 
> v2: Separate out pin/unpin context funcs for greater symmetry with
> intel_lrc. One more step towards unifying behaviour between the two
> classes of engines and towards fixing another bug in i915_switch_context
> vs requests.
> 

Much better.

Reviewed-by: Joonas Lahtinen 

> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 ++
>  drivers/gpu/drm/i915/i915_gem_context.c | 27 ++--
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 55 
> +
>  3 files changed, 60 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e4c8e341655c..19d0194c728f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -867,6 +867,8 @@ struct i915_gem_context {
>   u32 user_handle;
>  #define CONTEXT_NO_ZEROMAP   (1<<0)
>  
> + u32 ggtt_alignment;
> +
>   struct intel_context {
>   struct drm_i915_gem_object *state;
>   struct intel_ringbuffer *ringbuf;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index a3b11aac23a4..c620fe6c9d96 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -268,6 +268,8 @@ __create_hw_context(struct drm_device *dev,
>   list_add_tail(>link, _priv->context_list);
>   ctx->i915 = dev_priv;
>  
> + ctx->ggtt_alignment = get_context_alignment(dev_priv);
> +
>   if (dev_priv->hw_context_size) {
>   struct drm_i915_gem_object *obj =
>   i915_gem_alloc_context_obj(dev, 
> dev_priv->hw_context_size);
> @@ -413,26 +415,6 @@ int i915_gem_context_init(struct drm_device *dev)
>   return PTR_ERR(ctx);
>   }
>  
> - if (!i915.enable_execlists && ctx->engine[RCS].state) {
> - int ret;
> -
> - /* We may need to do things with the shrinker which
> -  * require us to immediately switch back to the default
> -  * context. This can cause a problem as pinning the
> -  * default context also requires GTT space which may not
> -  * be available. To avoid this we always pin the default
> -  * context.
> -  */
> - ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state,
> - get_context_alignment(dev_priv), 0);
> - if (ret) {
> - DRM_ERROR("Failed to pinned default global context 
> (error %d)\n",
> -   ret);
> - i915_gem_context_unreference(ctx);
> - return ret;
> - }
> - }
> -
>   dev_priv->kernel_context = ctx;
>  
>   DRM_DEBUG_DRIVER("%s context support initialized\n",
> @@ -469,9 +451,6 @@ void i915_gem_context_fini(struct drm_device *dev)
>  
>   lockdep_assert_held(>struct_mutex);
>  
> - if (!i915.enable_execlists && dctx->engine[RCS].state)
> - i915_gem_object_ggtt_unpin(dctx->engine[RCS].state);
> -
>   i915_gem_context_unreference(dctx);
>   dev_priv->kernel_context = NULL;
>  
> @@ -721,7 +700,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
>  
>   /* Trying to pin first makes error handling easier. */
>   ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
> - get_context_alignment(engine->i915),
> + to->ggtt_alignment,
>   0);
>   if (ret)
>   return ret;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a3978f9b..92bb376e5039 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2240,6 +2240,47 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring)
>   kfree(ring);
>  }
>  
> +static int intel_ring_context_pin(struct i915_gem_context *ctx,
> +   struct intel_engine_cs *engine)
> +{
> + struct intel_context *ce = >engine[engine->id];
> + int ret;
> +
> + lockdep_assert_held(>i915->dev->struct_mutex);
> +
> + if (ce->pin_count++)
> + return 0;
> +
> + if (ce->state) {
> + ret = i915_gem_obj_ggtt_pin(ce->state, 

Re: [Intel-gfx] [PATCH] drm: Store the plane's index

[Ville Syrjälä]

On Thu, May 26, 2016 at 10:34:57AM +0100, Chris Wilson wrote:
> Currently the plane's index is determined by walking the list of all
> planes in the mode and finding the position of that plane in the list. A
> linear walk, especially a linear walk within a linear walk as frequently
> conceived by i915.ko [O(N^2)] quickly comes to dominate profiles.
> 
> The plane's index is constant for as long as no earlier planes are
> removed from the list. For most drivers, planes are static, determined
> at boot and then untouched until shutdown. Storing the index upon
> construction and then only walking the tail upon removal should
> be a major improvement for all.
> 
> Signed-off-by: Chris Wilson 
> Cc: Daniel Vetter 
> Cc: Matt Roper 

I've been wondering about the cost of these silly walks myself.

Patch looks sane to me
Reviewed-by: Ville Syrjälä 

Same for crtcs?

> ---
>  drivers/gpu/drm/drm_crtc.c | 38 +-
>  include/drm/drm_crtc.h |  6 +-
>  2 files changed, 14 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 3a0384cce4a2..00ee01126b6f 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -1302,7 +1302,7 @@ int drm_universal_plane_init(struct drm_device *dev, 
> struct drm_plane *plane,
>   plane->type = type;
>  
>   list_add_tail(>head, >plane_list);
> - config->num_total_plane++;
> + plane->index = config->num_total_plane++;
>   if (plane->type == DRM_PLANE_TYPE_OVERLAY)
>   config->num_overlay_plane++;
>  
> @@ -1369,6 +1369,7 @@ EXPORT_SYMBOL(drm_plane_init);
>  void drm_plane_cleanup(struct drm_plane *plane)
>  {
>   struct drm_device *dev = plane->dev;
> + struct drm_plane *other;
>  
>   drm_modeset_lock_all(dev);
>   kfree(plane->format_types);
> @@ -1376,6 +1377,10 @@ void drm_plane_cleanup(struct drm_plane *plane)
>  
>   BUG_ON(list_empty(>head));
>  
> + other = list_next_entry(plane, head);
> + list_for_each_entry_from(other, >mode_config.plane_list, head)
> + other->index--;
> +
>   list_del(>head);
>   dev->mode_config.num_total_plane--;
>   if (plane->type == DRM_PLANE_TYPE_OVERLAY)
> @@ -1393,29 +1398,6 @@ void drm_plane_cleanup(struct drm_plane *plane)
>  EXPORT_SYMBOL(drm_plane_cleanup);
>  
>  /**
> - * drm_plane_index - find the index of a registered plane
> - * @plane: plane to find index for
> - *
> - * Given a registered plane, return the index of that CRTC within a DRM
> - * device's list of planes.
> - */
> -unsigned int drm_plane_index(struct drm_plane *plane)
> -{
> - unsigned int index = 0;
> - struct drm_plane *tmp;
> -
> - drm_for_each_plane(tmp, plane->dev) {
> - if (tmp == plane)
> - return index;
> -
> - index++;
> - }
> -
> - BUG();
> -}
> -EXPORT_SYMBOL(drm_plane_index);
> -
> -/**
>   * drm_plane_from_index - find the registered plane at an index
>   * @dev: DRM device
>   * @idx: index of registered plane to find for
> @@ -1427,13 +1409,11 @@ struct drm_plane *
>  drm_plane_from_index(struct drm_device *dev, int idx)
>  {
>   struct drm_plane *plane;
> - unsigned int i = 0;
>  
> - drm_for_each_plane(plane, dev) {
> - if (i == idx)
> + drm_for_each_plane(plane, dev)
> + if (idx == plane->index)
>   return plane;
> - i++;
> - }
> +
>   return NULL;
>  }
>  EXPORT_SYMBOL(drm_plane_from_index);
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 9771428e1ba8..eda3b1b3d3b4 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -1543,6 +1543,7 @@ struct drm_plane {
>   struct drm_object_properties properties;
>  
>   enum drm_plane_type type;
> + unsigned index;
>  
>   const struct drm_plane_helper_funcs *helper_private;
>  
> @@ -2316,7 +2317,10 @@ extern int drm_plane_init(struct drm_device *dev,
> const uint32_t *formats, unsigned int format_count,
> bool is_primary);
>  extern void drm_plane_cleanup(struct drm_plane *plane);
> -extern unsigned int drm_plane_index(struct drm_plane *plane);
> +static inline unsigned int drm_plane_index(struct drm_plane *plane)
> +{
> + return plane->index;
> +}
>  extern struct drm_plane * drm_plane_from_index(struct drm_device *dev, int 
> idx);
>  extern void drm_plane_force_disable(struct drm_plane *plane);
>  extern int drm_plane_check_pixel_format(const struct drm_plane *plane,
> -- 
> 2.8.1
> 
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Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Reapply page flip atomic preparation patches.

[Maarten Lankhorst]

Op 26-05-16 om 13:02 schreef Patchwork:
> == Series Details ==
>
> Series: drm/i915: Reapply page flip atomic preparation patches.
> URL   : https://patchwork.freedesktop.org/series/7801/
> State : failure
>
> == Summary ==
>
> Series 7801v1 drm/i915: Reapply page flip atomic preparation patches.
> http://patchwork.freedesktop.org/api/1.0/series/7801/revisions/1/mbox
>
> Test gem_busy:
> Subgroup basic-blt:
> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> Test gem_exec_flush:
> Subgroup basic-batch-kernel-default-cmd:
> pass   -> FAIL   (ro-byt-n2820)
Seems to fail pretty randomly on ro-byt-n2820.

https://bugs.freedesktop.org/show_bug.cgi?id=95372
> Test gem_flink_basic:
> Subgroup bad-open:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)
> Test kms_flip:
> Subgroup basic-flip-vs-wf_vblank:
> fail   -> PASS   (ro-bdw-i7-5600u)
> skip   -> PASS   (fi-skl-i5-6260u)
> Test kms_frontbuffer_tracking:
> Subgroup basic:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)
> Test kms_psr_sink_crc:
> Subgroup psr_basic:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)
-skl failures are all "[drm:intel_pipe_update_start [i915]] *ERROR* Potential 
atomic update failure on pipe A", which seem to happen randomly.
https://bugs.freedesktop.org/show_bug.cgi?id=95632
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[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/6] drm/i915: Skip idling an idle engine (rev9)

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Skip idling an idle engine (rev9)
URL   : https://patchwork.freedesktop.org/series/7708/
State : failure

== Summary ==

Applying: drm/i915: Skip idling an idle engine
Applying: drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c
Applying: drm/i915: Treat kernel context as initialised
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_ringbuffer.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_ringbuffer.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_ringbuffer.c
Patch failed at 0003 drm/i915: Treat kernel context as initialised
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] [PATCH] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

[Chris Wilson]

This is so that we have symmetry with intel_lrc.c and avoid a source of
if (i915.enable_execlists) layering violation within i915_gem_context.c -
that is we move the specific handling of the dev_priv->kernel_context
for legacy submission into the legacy submission code.

This depends upon the init/fini ordering between contexts and engines
already defined by intel_lrc.c, and also exporting the context alignment
required for pinning the legacy context.

v2: Separate out pin/unpin context funcs for greater symmetry with
intel_lrc. One more step towards unifying behaviour between the two
classes of engines and towards fixing another bug in i915_switch_context
vs requests.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_gem_context.c | 27 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 55 +
 3 files changed, 60 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4c8e341655c..19d0194c728f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -867,6 +867,8 @@ struct i915_gem_context {
u32 user_handle;
 #define CONTEXT_NO_ZEROMAP (1<<0)
 
+   u32 ggtt_alignment;
+
struct intel_context {
struct drm_i915_gem_object *state;
struct intel_ringbuffer *ringbuf;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index a3b11aac23a4..c620fe6c9d96 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -268,6 +268,8 @@ __create_hw_context(struct drm_device *dev,
list_add_tail(>link, _priv->context_list);
ctx->i915 = dev_priv;
 
+   ctx->ggtt_alignment = get_context_alignment(dev_priv);
+
if (dev_priv->hw_context_size) {
struct drm_i915_gem_object *obj =
i915_gem_alloc_context_obj(dev, 
dev_priv->hw_context_size);
@@ -413,26 +415,6 @@ int i915_gem_context_init(struct drm_device *dev)
return PTR_ERR(ctx);
}
 
-   if (!i915.enable_execlists && ctx->engine[RCS].state) {
-   int ret;
-
-   /* We may need to do things with the shrinker which
-* require us to immediately switch back to the default
-* context. This can cause a problem as pinning the
-* default context also requires GTT space which may not
-* be available. To avoid this we always pin the default
-* context.
-*/
-   ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state,
-   get_context_alignment(dev_priv), 0);
-   if (ret) {
-   DRM_ERROR("Failed to pinned default global context 
(error %d)\n",
- ret);
-   i915_gem_context_unreference(ctx);
-   return ret;
-   }
-   }
-
dev_priv->kernel_context = ctx;
 
DRM_DEBUG_DRIVER("%s context support initialized\n",
@@ -469,9 +451,6 @@ void i915_gem_context_fini(struct drm_device *dev)
 
lockdep_assert_held(>struct_mutex);
 
-   if (!i915.enable_execlists && dctx->engine[RCS].state)
-   i915_gem_object_ggtt_unpin(dctx->engine[RCS].state);
-
i915_gem_context_unreference(dctx);
dev_priv->kernel_context = NULL;
 
@@ -721,7 +700,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
 
/* Trying to pin first makes error handling easier. */
ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
-   get_context_alignment(engine->i915),
+   to->ggtt_alignment,
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d35a3978f9b..92bb376e5039 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2240,6 +2240,47 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring)
kfree(ring);
 }
 
+static int intel_ring_context_pin(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine)
+{
+   struct intel_context *ce = >engine[engine->id];
+   int ret;
+
+   lockdep_assert_held(>i915->dev->struct_mutex);
+
+   if (ce->pin_count++)
+   return 0;
+
+   if (ce->state) {
+   ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0);
+   if (ret)
+   goto error;
+   }
+
+   i915_gem_context_reference(ctx);
+   return 0;
+
+error:
+   ce->pin_count = 0;
+   return ret;
+}
+
+static void intel_ring_context_unpin(struct 

Re: [Intel-gfx] [PATCH] mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

[Maarten Lankhorst]

Op 26-05-16 om 12:43 schreef Chris Wilson:
> On Thu, May 26, 2016 at 12:37:30PM +0200, Maarten Lankhorst wrote:
>> The check should also not be for NULL, but for use_ww_ctx.
>> This way the if check is optimized out for the ww_ctx path, where
>> ww_ctx is always non-null.
> The compiler can see use_ww_ctx == false => ww_ctx == NULL just as well
> to do dead-code elimination, i.e. use_ww_ctx is superflouus and does not
> reduce the code size. (gcc 4.7.2, 4.9.1, 5.3.1)
That's true, but it cannot do the same when use_ww_ctx = true.
In this case the function will always be called with ww_ctx != NULL,
but the compiler can't see that, so it will keep the check even if it's always 
true.

~Maarten
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[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Reapply page flip atomic preparation patches.

[Patchwork]

== Series Details ==

Series: drm/i915: Reapply page flip atomic preparation patches.
URL   : https://patchwork.freedesktop.org/series/7801/
State : failure

== Summary ==

Series 7801v1 drm/i915: Reapply page flip atomic preparation patches.
http://patchwork.freedesktop.org/api/1.0/series/7801/revisions/1/mbox

Test gem_busy:
Subgroup basic-blt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
pass   -> FAIL   (ro-byt-n2820)
Test gem_flink_basic:
Subgroup bad-open:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (ro-bdw-i7-5600u)
skip   -> PASS   (fi-skl-i5-6260u)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-n2820 total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:178  dwarn:5   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
fi-bsw-n3050 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1020/

fc9d741 drm-intel-nightly: 2016y-05m-25d-07h-45m-48s UTC integration manifest
6a3f8a8 drm/i915: Pass atomic states to fbc update functions.
4d540eb drm/i915: Remove reset_counter from intel_crtc.
b6103e9 drm/i915: Remove queue_flip pointer.
95a5895 drm/i915: Remove use_mmio_flip kernel parameter.
526331d drm/i915: Remove cs based page flip support, v2.
d159e01 drm/i915: Rework intel_crtc_page_flip to be almost atomic, v4.
e8f5004 drm/i915: Add the exclusive fence to plane_state.
616a4b0 drm/i915: Convert flip_work to a list, v2.
0f8403b drm/i915: Allow mmio updates on all platforms, v3.

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Re: [Intel-gfx] [PATCH] mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

[Chris Wilson]

On Thu, May 26, 2016 at 12:37:30PM +0200, Maarten Lankhorst wrote:
> The check should also not be for NULL, but for use_ww_ctx.
> This way the if check is optimized out for the ww_ctx path, where
> ww_ctx is always non-null.

The compiler can see use_ww_ctx == false => ww_ctx == NULL just as well
to do dead-code elimination, i.e. use_ww_ctx is superflouus and does not
reduce the code size. (gcc 4.7.2, 4.9.1, 5.3.1)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 9/9] drm/i915: Pass atomic states to fbc update functions.

[Maarten Lankhorst]

This is required to let fbc updates run async. It has a lot of
checks whether certain locks are taken, which can be removed when
the relevant states are passed in as pointers.

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Patrik Jakobsson 
---
 drivers/gpu/drm/i915/intel_display.c |  8 +---
 drivers/gpu/drm/i915/intel_drv.h |  8 ++--
 drivers/gpu/drm/i915/intel_fbc.c | 39 +---
 3 files changed, 29 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e6d3721eeda3..f7f2ca24d062 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4590,7 +4590,7 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state)
struct intel_plane_state *old_primary_state =
to_intel_plane_state(old_pri_state);
 
-   intel_fbc_pre_update(crtc);
+   intel_fbc_pre_update(crtc, pipe_config, primary_state);
 
if (old_primary_state->visible &&
(modeset || !primary_state->visible))
@@ -11278,7 +11278,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (obj->base.dma_buf)
work->old_plane_state[0]->base.fence = 
intel_get_excl_fence(obj);
 
-   intel_fbc_pre_update(intel_crtc);
+   intel_fbc_pre_update(intel_crtc,
+to_intel_crtc_state(new_crtc_state),
+to_intel_plane_state(new_state));
 
schedule_work(>mmio_work);
 
@@ -13247,7 +13249,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 
if (crtc->state->active &&
drm_atomic_get_existing_plane_state(state, crtc->primary))
-   intel_fbc_enable(intel_crtc);
+   intel_fbc_enable(intel_crtc, pipe_config, 
to_intel_plane_state(crtc->primary->state));
 
if (crtc->state->active &&
(crtc->state->planes_changed || update_pipe))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 40f7925623fd..070b602ac594 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1424,11 +1424,15 @@ static inline void intel_fbdev_restore_mode(struct 
drm_device *dev)
 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
   struct drm_atomic_state *state);
 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
-void intel_fbc_pre_update(struct intel_crtc *crtc);
+void intel_fbc_pre_update(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state);
 void intel_fbc_post_update(struct intel_crtc *crtc);
 void intel_fbc_init(struct drm_i915_private *dev_priv);
 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
-void intel_fbc_enable(struct intel_crtc *crtc);
+void intel_fbc_enable(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state);
 void intel_fbc_disable(struct intel_crtc *crtc);
 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 0dea5fbcd8aa..d2b0269b2fe4 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -480,10 +480,10 @@ static void intel_fbc_deactivate(struct drm_i915_private 
*dev_priv)
intel_fbc_hw_deactivate(dev_priv);
 }
 
-static bool multiple_pipes_ok(struct intel_crtc *crtc)
+static bool multiple_pipes_ok(struct intel_crtc *crtc,
+ struct intel_plane_state *plane_state)
 {
-   struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
-   struct drm_plane *primary = crtc->base.primary;
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_fbc *fbc = _priv->fbc;
enum pipe pipe = crtc->pipe;
 
@@ -491,9 +491,7 @@ static bool multiple_pipes_ok(struct intel_crtc *crtc)
if (!no_fbc_on_multiple_pipes(dev_priv))
return true;
 
-   WARN_ON(!drm_modeset_is_locked(>mutex));
-
-   if (to_intel_plane_state(primary->state)->visible)
+   if (plane_state->visible)
fbc->visible_pipes_mask |= (1 << pipe);
else
fbc->visible_pipes_mask &= ~(1 << pipe);
@@ -708,21 +706,16 @@ static bool intel_fbc_hw_tracking_covers_screen(struct 
intel_crtc *crtc)
return effective_w <= max_w && effective_h <= max_h;
 }
 
-static void intel_fbc_update_state_cache(struct intel_crtc *crtc)
+static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
+   

[Intel-gfx] [PATCH 5/9] drm/i915: Remove cs based page flip support, v2.

[Maarten Lankhorst]

With mmio flips now available on all platforms it's time to remove
support for cs flips.

Changes since v1:
- Rebase for legacy cursor updates.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  19 +-
 drivers/gpu/drm/i915/i915_irq.c  | 120 ++-
 drivers/gpu/drm/i915/intel_display.c | 392 +--
 drivers/gpu/drm/i915/intel_drv.h |   9 +-
 4 files changed, 33 insertions(+), 507 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index b52c1a5f3451..b29ba16c90b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -628,7 +628,6 @@ static void i915_dump_pageflip(struct seq_file *m,
 {
const char pipe = pipe_name(crtc->pipe);
u32 pending;
-   u32 addr;
int i;
 
pending = atomic_read(>pending);
@@ -640,7 +639,6 @@ static void i915_dump_pageflip(struct seq_file *m,
   pipe, plane_name(crtc->plane));
}
 
-
for (i = 0; i < work->num_planes; i++) {
struct intel_plane_state *old_plane_state = 
work->old_plane_state[i];
struct drm_plane *plane = old_plane_state->base.plane;
@@ -664,22 +662,9 @@ static void i915_dump_pageflip(struct seq_file *m,
   i915_gem_request_completed(req, true));
}
 
-   seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now 
%d\n",
-  work->flip_queued_vblank,
-  work->flip_ready_vblank,
+   seq_printf(m, "Flip queued on frame %d, now %d\n",
+  pending ? work->flip_queued_vblank : -1,
   intel_crtc_get_vblank_counter(crtc));
-   seq_printf(m, "%d prepares\n", atomic_read(>pending));
-
-   if (INTEL_INFO(dev_priv)->gen >= 4)
-   addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
-   else
-   addr = I915_READ(DSPADDR(crtc->plane));
-   seq_printf(m, "Current scanout address 0x%08x\n", addr);
-
-   if (work->flip_queued_req) {
-   seq_printf(m, "New framebuffer address 0x%08lx\n", 
(long)work->gtt_offset);
-   seq_printf(m, "MMIO update completed? %d\n",  addr == 
work->gtt_offset);
-   }
 }
 
 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index caaf1e2a7bc1..fc2b2a7e2c55 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -136,6 +136,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
POSTING_READ(type##IIR); \
 } while (0)
 
+static void
+intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, unsigned pipe)
+{
+   DRM_DEBUG_KMS("Finished page flip\n");
+}
+
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
@@ -1631,16 +1637,11 @@ static void gen6_rps_irq_handler(struct 
drm_i915_private *dev_priv, u32 pm_iir)
}
 }
 
-static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
+static void intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
 enum pipe pipe)
 {
-   bool ret;
-
-   ret = drm_handle_vblank(dev_priv->dev, pipe);
-   if (ret)
+   if (drm_handle_vblank(dev_priv->dev, pipe))
intel_finish_page_flip_mmio(dev_priv, pipe);
-
-   return ret;
 }
 
 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
@@ -1707,9 +1708,8 @@ static void valleyview_pipestat_irq_handler(struct 
drm_i915_private *dev_priv,
enum pipe pipe;
 
for_each_pipe(dev_priv, pipe) {
-   if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
-   intel_pipe_handle_vblank(dev_priv, pipe))
-   intel_check_page_flip(dev_priv, pipe);
+   if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
+   intel_pipe_handle_vblank(dev_priv, pipe);
 
if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
intel_finish_page_flip_cs(dev_priv, pipe);
@@ -2155,9 +2155,8 @@ static void ilk_display_irq_handler(struct 
drm_i915_private *dev_priv,
DRM_ERROR("Poison interrupt\n");
 
for_each_pipe(dev_priv, pipe) {
-   if (de_iir & DE_PIPE_VBLANK(pipe) &&
-   intel_pipe_handle_vblank(dev_priv, pipe))
-   intel_check_page_flip(dev_priv, pipe);
+   if (de_iir & DE_PIPE_VBLANK(pipe))
+   intel_pipe_handle_vblank(dev_priv, pipe);
 
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
@@ -2206,9 +2205,8 @@ static void ivb_display_irq_handler(struct 
drm_i915_private *dev_priv,
intel_opregion_asle_intr(dev_priv);
 

[Intel-gfx] [PATCH 7/9] drm/i915: Remove queue_flip pointer.

[Maarten Lankhorst]

With the removal of cs support this is no longer reachable.
Can be revived if needed.

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Patrik Jakobsson 
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 -
 drivers/gpu/drm/i915/intel_display.c | 259 ---
 2 files changed, 264 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ce1d368e4e50..85a7c44ed55c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -618,11 +618,6 @@ struct drm_i915_display_funcs {
void (*audio_codec_disable)(struct intel_encoder *encoder);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
-   int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- struct drm_i915_gem_object *obj,
- struct drm_i915_gem_request *req,
- uint64_t gtt_offset);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
/* clock updates for mode set */
/* cursor updates */
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 2324b74f72f4..d0653f87a53a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11071,237 +11071,6 @@ void intel_finish_page_flip_mmio(struct 
drm_i915_private *dev_priv, int pipe)
spin_unlock_irqrestore(>event_lock, flags);
 }
 
-static int intel_gen2_queue_flip(struct drm_device *dev,
-struct drm_crtc *crtc,
-struct drm_framebuffer *fb,
-struct drm_i915_gem_object *obj,
-struct drm_i915_gem_request *req,
-uint64_t gtt_offset)
-{
-   struct intel_engine_cs *engine = req->engine;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   u32 flip_mask;
-   int ret;
-
-   ret = intel_ring_begin(req, 6);
-   if (ret)
-   return ret;
-
-   /* Can't queue multiple flips, so wait for the previous
-* one to finish before executing the next.
-*/
-   if (intel_crtc->plane)
-   flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
-   else
-   flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
-   intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
-   intel_ring_emit(engine, MI_NOOP);
-   intel_ring_emit(engine, MI_DISPLAY_FLIP |
-   MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-   intel_ring_emit(engine, fb->pitches[0]);
-   intel_ring_emit(engine, gtt_offset);
-   intel_ring_emit(engine, 0); /* aux display base address, unused */
-
-   return 0;
-}
-
-static int intel_gen3_queue_flip(struct drm_device *dev,
-struct drm_crtc *crtc,
-struct drm_framebuffer *fb,
-struct drm_i915_gem_object *obj,
-struct drm_i915_gem_request *req,
-uint64_t gtt_offset)
-{
-   struct intel_engine_cs *engine = req->engine;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   u32 flip_mask;
-   int ret;
-
-   ret = intel_ring_begin(req, 6);
-   if (ret)
-   return ret;
-
-   if (intel_crtc->plane)
-   flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
-   else
-   flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
-   intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
-   intel_ring_emit(engine, MI_NOOP);
-   intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
-   MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-   intel_ring_emit(engine, fb->pitches[0]);
-   intel_ring_emit(engine, gtt_offset);
-   intel_ring_emit(engine, MI_NOOP);
-
-   return 0;
-}
-
-static int intel_gen4_queue_flip(struct drm_device *dev,
-struct drm_crtc *crtc,
-struct drm_framebuffer *fb,
-struct drm_i915_gem_object *obj,
-struct drm_i915_gem_request *req,
-uint64_t gtt_offset)
-{
-   struct intel_engine_cs *engine = req->engine;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   uint32_t pf, pipesrc;
-   int ret;
-
-   ret = intel_ring_begin(req, 4);
-   if (ret)
-   return ret;
-
-   /* i965+ uses the linear or tiled offsets from the
-* Display Registers (which do not change across a page-flip)
-* so we need only reprogram the base address.
-*/
-   intel_ring_emit(engine, 

[Intel-gfx] [PATCH 6/9] drm/i915: Remove use_mmio_flip kernel parameter.

[Maarten Lankhorst]

With the removal of cs flips this is always force enabled.

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Patrik Jakobsson 
---
 drivers/gpu/drm/i915/i915_params.c | 5 -
 drivers/gpu/drm/i915/i915_params.h | 1 -
 drivers/gpu/drm/i915/intel_lrc.c   | 4 +---
 3 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 5e18cf9f754d..9a5d58b251f5 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -49,7 +49,6 @@ struct i915_params i915 __read_mostly = {
.invert_brightness = 0,
.disable_display = 0,
.enable_cmd_parser = 1,
-   .use_mmio_flip = 0,
.mmio_debug = 0,
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
@@ -175,10 +174,6 @@ module_param_named_unsafe(enable_cmd_parser, 
i915.enable_cmd_parser, int, 0600);
 MODULE_PARM_DESC(enable_cmd_parser,
 "Enable command parsing (1=enabled [default], 0=disabled)");
 
-module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600);
-MODULE_PARM_DESC(use_mmio_flip,
-"use MMIO flips (-1=never, 0=driver discretion [default], 
1=always)");
-
 module_param_named(mmio_debug, i915.mmio_debug, int, 0600);
 MODULE_PARM_DESC(mmio_debug,
"Enable the MMIO debug code for the first N failures (default: off). "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 1323261a0cdd..658ce7379671 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,6 @@ struct i915_params {
int enable_guc_loading;
int enable_guc_submission;
int guc_log_level;
-   int use_mmio_flip;
int mmio_debug;
int edp_vswing;
unsigned int inject_load_failure;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c191a1afaaf..53715037ab54 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -260,9 +260,7 @@ int intel_sanitize_enable_execlists(struct drm_i915_private 
*dev_priv, int enabl
if (enable_execlists == 0)
return 0;
 
-   if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
-   USES_PPGTT(dev_priv) &&
-   i915.use_mmio_flip >= 0)
+   if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && USES_PPGTT(dev_priv))
return 1;
 
return 0;
-- 
2.5.5

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[Intel-gfx] [PATCH 3/9] drm/i915: Add the exclusive fence to plane_state.

[Maarten Lankhorst]

Set plane_state->base.fence to the dma_buf exclusive fence,
and add a wait to the mmio function. This will make it easier
to unify plane updates later on.

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Patrik Jakobsson 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |  1 +
 drivers/gpu/drm/i915/intel_display.c  | 54 +++
 2 files changed, 42 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7de7721f65bc..2ab45f16fa65 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -102,6 +102,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
  struct drm_plane_state *state)
 {
WARN_ON(state && to_intel_plane_state(state)->wait_req);
+   WARN_ON(state && state->fence);
drm_atomic_helper_plane_destroy_state(plane, state);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ffd9b555d23f..0de232401f1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13476,6 +13476,15 @@ static int intel_atomic_prepare_commit(struct 
drm_device *dev,
struct intel_plane_state *intel_plane_state =
to_intel_plane_state(plane_state);
 
+   if (plane_state->fence) {
+   long lret = fence_wait(plane_state->fence, 
true);
+
+   if (lret < 0) {
+   ret = lret;
+   break;
+   }
+   }
+
if (!intel_plane_state->wait_req)
continue;
 
@@ -13820,6 +13829,33 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.atomic_destroy_state = intel_crtc_destroy_state,
 };
 
+static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
+{
+   struct reservation_object *resv;
+
+
+   if (!obj->base.dma_buf)
+   return NULL;
+
+   resv = obj->base.dma_buf->resv;
+
+   /* For framebuffer backed by dmabuf, wait for fence */
+   while (1) {
+   struct fence *fence_excl, *ret = NULL;
+
+   rcu_read_lock();
+
+   fence_excl = rcu_dereference(resv->fence_excl);
+   if (fence_excl)
+   ret = fence_get_rcu(fence_excl);
+
+   rcu_read_unlock();
+
+   if (ret == fence_excl)
+   return ret;
+   }
+}
+
 /**
  * intel_prepare_plane_fb - Prepare fb for usage on plane
  * @plane: drm plane to prepare for
@@ -13872,19 +13908,6 @@ intel_prepare_plane_fb(struct drm_plane *plane,
}
}
 
-   /* For framebuffer backed by dmabuf, wait for fence */
-   if (obj && obj->base.dma_buf) {
-   long lret;
-
-   lret = 
reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
-  false, true,
-  
MAX_SCHEDULE_TIMEOUT);
-   if (lret == -ERESTARTSYS)
-   return lret;
-
-   WARN(lret < 0, "waiting returns %li\n", lret);
-   }
-
if (!obj) {
ret = 0;
} else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
@@ -13904,6 +13927,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 
i915_gem_request_assign(_state->wait_req,
obj->last_write_req);
+
+   plane_state->base.fence = intel_get_excl_fence(obj);
}
 
i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
@@ -13946,6 +13971,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
 
i915_gem_request_assign(_intel_state->wait_req, NULL);
+
+   fence_put(old_intel_state->base.fence);
+   old_intel_state->base.fence = NULL;
 }
 
 int
-- 
2.5.5

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[Intel-gfx] [PATCH 4/9] drm/i915: Rework intel_crtc_page_flip to be almost atomic, v4.

[Maarten Lankhorst]

Create a work structure that will be used for all changes. This will
be used later on in the atomic commit function.

Changes since v1:
- Free old_crtc_state from unpin_work_fn properly.
Changes since v2:
- Add hunk for calling hw state verifier.
- Add missing support for color spaces.
Changes since v3:
- Update for legacy cursor work.
- null pointer to request_unreference is no longer allowed.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  36 +-
 drivers/gpu/drm/i915/intel_display.c | 676 +--
 drivers/gpu/drm/i915/intel_drv.h |  17 +-
 3 files changed, 444 insertions(+), 285 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index cced527af109..b52c1a5f3451 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -627,29 +627,43 @@ static void i915_dump_pageflip(struct seq_file *m,
   struct intel_flip_work *work)
 {
const char pipe = pipe_name(crtc->pipe);
-   const char plane = plane_name(crtc->plane);
u32 pending;
u32 addr;
+   int i;
 
pending = atomic_read(>pending);
if (pending) {
seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
-  pipe, plane);
+  pipe, plane_name(crtc->plane));
} else {
seq_printf(m, "Flip pending (waiting for vsync) on pipe %c 
(plane %c)\n",
-  pipe, plane);
+  pipe, plane_name(crtc->plane));
}
-   if (work->flip_queued_req) {
-   struct intel_engine_cs *engine = 
i915_gem_request_get_engine(work->flip_queued_req);
 
-   seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x 
[current breadcrumb %x], completed? %d\n",
+
+   for (i = 0; i < work->num_planes; i++) {
+   struct intel_plane_state *old_plane_state = 
work->old_plane_state[i];
+   struct drm_plane *plane = old_plane_state->base.plane;
+   struct drm_i915_gem_request *req = old_plane_state->wait_req;
+   struct intel_engine_cs *engine;
+
+   seq_printf(m, "[PLANE:%i] part of flip.\n", plane->base.id);
+
+   if (!req) {
+   seq_printf(m, "Plane not associated with any engine\n");
+   continue;
+   }
+
+   engine = i915_gem_request_get_engine(req);
+
+   seq_printf(m, "Plane blocked on %s at seqno %x, next seqno %x 
[current breadcrumb %x], completed? %d\n",
   engine->name,
-  i915_gem_request_get_seqno(work->flip_queued_req),
+  i915_gem_request_get_seqno(req),
   dev_priv->next_seqno,
   engine->get_seqno(engine),
-  i915_gem_request_completed(work->flip_queued_req, 
true));
-   } else
-   seq_printf(m, "Flip not associated with any ring\n");
+  i915_gem_request_completed(req, true));
+   }
+
seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now 
%d\n",
   work->flip_queued_vblank,
   work->flip_ready_vblank,
@@ -662,7 +676,7 @@ static void i915_dump_pageflip(struct seq_file *m,
addr = I915_READ(DSPADDR(crtc->plane));
seq_printf(m, "Current scanout address 0x%08x\n", addr);
 
-   if (work->pending_flip_obj) {
+   if (work->flip_queued_req) {
seq_printf(m, "New framebuffer address 0x%08lx\n", 
(long)work->gtt_offset);
seq_printf(m, "MMIO update completed? %d\n",  addr == 
work->gtt_offset);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0de232401f1d..0531cdb1cfa1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -50,7 +50,7 @@
 
 static bool is_mmio_work(struct intel_flip_work *work)
 {
-   return work->mmio_work.func;
+   return !work->flip_queued_req;
 }
 
 /* Primary plane formats for gen <= 3 */
@@ -124,6 +124,9 @@ static void intel_modeset_setup_hw_state(struct drm_device 
*dev);
 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 static int broxton_calc_cdclk(int max_pixclk);
+static void intel_modeset_verify_crtc(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_state,
+ struct drm_crtc_state *new_state);
 
 struct intel_limit {
struct {
@@ -2528,20 +2531,6 @@ out_unref_obj:
return false;
 }
 
-/* Update plane->state->fb to match plane->fb after driver-internal updates */
-static void
-update_state_fb(struct drm_plane *plane)
-{

[Intel-gfx] [PATCH 8/9] drm/i915: Remove reset_counter from intel_crtc.

[Maarten Lankhorst]

With the removal of cs-based flips all mmio waits will
finish without requiring the reset counter, because the
waits will complete during gpu reset.

Signed-off-by: Maarten Lankhorst 
Reviewed-by: Patrik Jakobsson 
---
 drivers/gpu/drm/i915/intel_display.c | 9 -
 drivers/gpu/drm/i915/intel_drv.h | 3 ---
 2 files changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d0653f87a53a..e6d3721eeda3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3180,14 +3180,6 @@ void intel_finish_reset(struct drm_i915_private 
*dev_priv)
 
 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
 {
-   struct drm_device *dev = crtc->dev;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   unsigned reset_counter;
-
-   reset_counter = i915_reset_counter(_i915(dev)->gpu_error);
-   if (intel_crtc->reset_counter != reset_counter)
-   return false;
-
return !list_empty_careful(_intel_crtc(crtc)->flip_work);
 }
 
@@ -11288,7 +11280,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
intel_fbc_pre_update(intel_crtc);
 
-   intel_crtc->reset_counter = i915_reset_counter(_priv->gpu_error);
schedule_work(>mmio_work);
 
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e7e262ac1f99..40f7925623fd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -662,9 +662,6 @@ struct intel_crtc {
 
struct intel_crtc_state *config;
 
-   /* reset counter value when the last flip was submitted */
-   unsigned int reset_counter;
-
/* Access to these should be protected by dev_priv->irq_lock. */
bool cpu_fifo_underrun_disabled;
bool pch_fifo_underrun_disabled;
-- 
2.5.5

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[Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

[Maarten Lankhorst]

Add some minor changes to prevent bisect breaking.

Main change is making sure crtc_state is not freed while the mmio update still 
runs.

Maarten Lankhorst (9):
  drm/i915: Allow mmio updates on all platforms, v3.
  drm/i915: Convert flip_work to a list, v2.
  drm/i915: Add the exclusive fence to plane_state.
  drm/i915: Rework intel_crtc_page_flip to be almost atomic, v4.
  drm/i915: Remove cs based page flip support, v2.
  drm/i915: Remove use_mmio_flip kernel parameter.
  drm/i915: Remove queue_flip pointer.
  drm/i915: Remove reset_counter from intel_crtc.
  drm/i915: Pass atomic states to fbc update functions.

 drivers/gpu/drm/i915/i915_debugfs.c   |   89 ++-
 drivers/gpu/drm/i915/i915_drv.h   |5 -
 drivers/gpu/drm/i915/i915_irq.c   |  120 +---
 drivers/gpu/drm/i915/i915_params.c|5 -
 drivers/gpu/drm/i915/i915_params.h|1 -
 drivers/gpu/drm/i915/intel_atomic_plane.c |1 +
 drivers/gpu/drm/i915/intel_display.c  | 1118 -
 drivers/gpu/drm/i915/intel_drv.h  |   37 +-
 drivers/gpu/drm/i915/intel_fbc.c  |   39 +-
 drivers/gpu/drm/i915/intel_lrc.c  |4 +-
 10 files changed, 417 insertions(+), 1002 deletions(-)

-- 
2.5.5

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[Intel-gfx] [PATCH 1/9] drm/i915: Allow mmio updates on all platforms, v3.

[Maarten Lankhorst]

With intel_pipe_update begin/end we ensure that the mmio updates
don't run during vblank interrupt, using the hw counter we can
be sure that when current vblank count != vblank count at the time
of pipe_update_end the mmio update is complete.

This allows us to use mmio updates on all platforms, using the
update_plane call.

With Chris Wilson's patch to skip waiting for vblanks for
legacy_cursor_update this potentially leaves a small race
condition. In case of !legacy_cursor_update we wait for flips to
complete so there's no race for freeing crtc_state. In case of
legacy_cursor_update there's a check for
work->crtc_state == old_crtc_state. In that case the old_crtc_state
is removed from intel_atomic_state and freed by intel_unpin_work_fn.
This ensures that intel_mmio_flip_work_func never uses a freed pointer
to crtc_state.

Changes since v1:
- Split out the flip_work rename.
Changes since v2:
- Do not break bisect by reverting the stall fix for cursor updates,
  instead add crtc_state to intel_flip_work, and make sure it's not
  freed in intel_atomic_commit for legacy cursor updates.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c | 118 ---
 drivers/gpu/drm/i915/intel_drv.h |   4 +-
 2 files changed, 29 insertions(+), 93 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9ccd76699f48..ae8036b5fe7c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10976,6 +10976,9 @@ static void intel_unpin_work_fn(struct work_struct 
*__work)
BUG_ON(atomic_read(>unpin_work_count) == 0);
atomic_dec(>unpin_work_count);
 
+   if (work->free_new_crtc_state)
+   intel_crtc_destroy_state(>base, 
>new_crtc_state->base);
+
kfree(work);
 }
 
@@ -11373,9 +11376,6 @@ static bool use_mmio_flip(struct intel_engine_cs 
*engine,
if (engine == NULL)
return true;
 
-   if (INTEL_GEN(engine->i915) < 5)
-   return false;
-
if (i915.use_mmio_flip < 0)
return false;
else if (i915.use_mmio_flip > 0)
@@ -11390,92 +11390,15 @@ static bool use_mmio_flip(struct intel_engine_cs 
*engine,
return engine != 
i915_gem_request_get_engine(obj->last_write_req);
 }
 
-static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
-unsigned int rotation,
-struct intel_flip_work *work)
-{
-   struct drm_device *dev = intel_crtc->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
-   const enum pipe pipe = intel_crtc->pipe;
-   u32 ctl, stride, tile_height;
-
-   ctl = I915_READ(PLANE_CTL(pipe, 0));
-   ctl &= ~PLANE_CTL_TILED_MASK;
-   switch (fb->modifier[0]) {
-   case DRM_FORMAT_MOD_NONE:
-   break;
-   case I915_FORMAT_MOD_X_TILED:
-   ctl |= PLANE_CTL_TILED_X;
-   break;
-   case I915_FORMAT_MOD_Y_TILED:
-   ctl |= PLANE_CTL_TILED_Y;
-   break;
-   case I915_FORMAT_MOD_Yf_TILED:
-   ctl |= PLANE_CTL_TILED_YF;
-   break;
-   default:
-   MISSING_CASE(fb->modifier[0]);
-   }
-
-   /*
-* The stride is either expressed as a multiple of 64 bytes chunks for
-* linear buffers or in number of tiles for tiled buffers.
-*/
-   if (intel_rotation_90_or_270(rotation)) {
-   /* stride = Surface height in tiles */
-   tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
-   stride = DIV_ROUND_UP(fb->height, tile_height);
-   } else {
-   stride = fb->pitches[0] /
-   intel_fb_stride_alignment(dev_priv, fb->modifier[0],
- fb->pixel_format);
-   }
-
-   /*
-* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
-* PLANE_SURF updates, the update is then guaranteed to be atomic.
-*/
-   I915_WRITE(PLANE_CTL(pipe, 0), ctl);
-   I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
-
-   I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
-   POSTING_READ(PLANE_SURF(pipe, 0));
-}
-
-static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
-struct intel_flip_work *work)
-{
-   struct drm_device *dev = intel_crtc->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct intel_framebuffer *intel_fb =
-   to_intel_framebuffer(intel_crtc->base.primary->fb);
-   struct drm_i915_gem_object *obj = intel_fb->obj;
-   i915_reg_t reg = DSPCNTR(intel_crtc->plane);
-   u32 dspcntr;
-
-   dspcntr = I915_READ(reg);
-
-   if (obj->tiling_mode != I915_TILING_NONE)
-   

[Intel-gfx] [PATCH 2/9] drm/i915: Convert flip_work to a list, v2.

[Maarten Lankhorst]

This will be required to allow more than 1 outstanding
update in the future. For now it's unclear how this will
will be handled, but with a list it's definitely possible.

Changes since v1:
- Changed to prevent breaking with the legacy cursor update changes.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  90 +++-
 drivers/gpu/drm/i915/i915_drv.h  |   2 +-
 drivers/gpu/drm/i915/intel_display.c | 156 +--
 drivers/gpu/drm/i915/intel_drv.h |   4 +-
 4 files changed, 149 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ac7e5692496d..cced527af109 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -621,6 +621,53 @@ static int i915_gem_gtt_info(struct seq_file *m, void 
*data)
return 0;
 }
 
+static void i915_dump_pageflip(struct seq_file *m,
+  struct drm_i915_private *dev_priv,
+  struct intel_crtc *crtc,
+  struct intel_flip_work *work)
+{
+   const char pipe = pipe_name(crtc->pipe);
+   const char plane = plane_name(crtc->plane);
+   u32 pending;
+   u32 addr;
+
+   pending = atomic_read(>pending);
+   if (pending) {
+   seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
+  pipe, plane);
+   } else {
+   seq_printf(m, "Flip pending (waiting for vsync) on pipe %c 
(plane %c)\n",
+  pipe, plane);
+   }
+   if (work->flip_queued_req) {
+   struct intel_engine_cs *engine = 
i915_gem_request_get_engine(work->flip_queued_req);
+
+   seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x 
[current breadcrumb %x], completed? %d\n",
+  engine->name,
+  i915_gem_request_get_seqno(work->flip_queued_req),
+  dev_priv->next_seqno,
+  engine->get_seqno(engine),
+  i915_gem_request_completed(work->flip_queued_req, 
true));
+   } else
+   seq_printf(m, "Flip not associated with any ring\n");
+   seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now 
%d\n",
+  work->flip_queued_vblank,
+  work->flip_ready_vblank,
+  intel_crtc_get_vblank_counter(crtc));
+   seq_printf(m, "%d prepares\n", atomic_read(>pending));
+
+   if (INTEL_INFO(dev_priv)->gen >= 4)
+   addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
+   else
+   addr = I915_READ(DSPADDR(crtc->plane));
+   seq_printf(m, "Current scanout address 0x%08x\n", addr);
+
+   if (work->pending_flip_obj) {
+   seq_printf(m, "New framebuffer address 0x%08lx\n", 
(long)work->gtt_offset);
+   seq_printf(m, "MMIO update completed? %d\n",  addr == 
work->gtt_offset);
+   }
+}
+
 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 {
struct drm_info_node *node = m->private;
@@ -639,48 +686,13 @@ static int i915_gem_pageflip_info(struct seq_file *m, 
void *data)
struct intel_flip_work *work;
 
spin_lock_irq(>event_lock);
-   work = crtc->flip_work;
-   if (work == NULL) {
+   if (list_empty(>flip_work)) {
seq_printf(m, "No flip due on pipe %c (plane %c)\n",
   pipe, plane);
} else {
-   u32 pending;
-   u32 addr;
-
-   pending = atomic_read(>pending);
-   if (pending) {
-   seq_printf(m, "Flip ioctl preparing on pipe %c 
(plane %c)\n",
-  pipe, plane);
-   } else {
-   seq_printf(m, "Flip pending (waiting for vsync) 
on pipe %c (plane %c)\n",
-  pipe, plane);
-   }
-   if (work->flip_queued_req) {
-   struct intel_engine_cs *engine = 
i915_gem_request_get_engine(work->flip_queued_req);
-
-   seq_printf(m, "Flip queued on %s at seqno %x, 
next seqno %x [current breadcrumb %x], completed? %d\n",
-  engine->name,
-  
i915_gem_request_get_seqno(work->flip_queued_req),
-  dev_priv->next_seqno,
-  engine->get_seqno(engine),
-  
i915_gem_request_completed(work->flip_queued_req, true));
-   } else
-   seq_printf(m, 

Re: [Intel-gfx] [PATCH] mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

[Maarten Lankhorst]

Op 26-05-16 om 10:31 schreef Chris Wilson:
> The ww_mutex has the property of allowing the lock to detect and report
> when it may be used in deadlocking scenarios (to allow the caller to
> unwind its locks and avoid the deadlock). This detection needs to be
> performed before we queue up for the spin, otherwise we wait on the
> osq_lock() for our turn to detect the deadlock that another thread is
> spinning on, waiting for us. Otherwise as we are stuck behind our waiter,
> throughput plummets.
>
> This can be demonstrated by trying concurrent atomic modesets.
>
> Testcase: igt/kms_cursor_legacy
> Signed-off-by: Chris Wilson 
> Cc: Peter Zijlstra 
> Cc: Ingo Molnar 
> Cc: Christian König 
> Cc: Maarten Lankhorst 
> Cc: linux-ker...@vger.kernel.org
> ---
>  kernel/locking/mutex.c | 56 
> --
>  1 file changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/kernel/locking/mutex.c b/kernel/locking/mutex.c
> index e364b424b019..d60f1ba3e64f 100644
> --- a/kernel/locking/mutex.c
> +++ b/kernel/locking/mutex.c
> @@ -217,12 +217,35 @@ ww_mutex_set_context_slowpath(struct ww_mutex *lock,
>  }
>  
>  #ifdef CONFIG_MUTEX_SPIN_ON_OWNER
> +static bool ww_mutex_may_deadlock(struct mutex *lock,
> +   struct ww_acquire_ctx *ww_ctx)
> +{
> + if (ww_ctx && ww_ctx->acquired > 0) {
> + struct ww_mutex *ww;
> +
> + ww = container_of(lock, struct ww_mutex, base);
> + /*
> +  * If ww->ctx is set the contents are undefined, only
> +  * by acquiring wait_lock there is a guarantee that
> +  * they are not invalid when reading.
> +  *
> +  * As such, when deadlock detection needs to be
> +  * performed the optimistic spinning cannot be done.
> +  */
> + if (READ_ONCE(ww->ctx))
> + return true;
> + }
> +
> + return false;
> +}
The check should be at the beginning of __mutex_lock_common,
regardless of spin_on_owner.

This is because -EALREADY was originally designed to be exceptional,
but is used a lot by design in drm/atomic now.

The other check for -EALREADY can be killed, or changed to a
DEBUG_LOCKS_WARN_ON.

The check should also not be for NULL, but for use_ww_ctx.
This way the if check is optimized out for the ww_ctx path, where
ww_ctx is always non-null.

This would also be something for Cc: stable. :)

~Maarten
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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

[Chris Wilson]

On Thu, May 26, 2016 at 01:22:04PM +0300, Joonas Lahtinen wrote:
> > @@ -2327,6 +2350,14 @@ void intel_cleanup_engine(struct intel_engine_cs 
> > *engine)
> >  
> >     i915_cmd_parser_fini_ring(engine);
> >     i915_gem_batch_pool_fini(>batch_pool);
> > +
> > +   kctx = dev_priv->kernel_context;
> > +   ce = >engine[engine->id];
> 
> I'd move these two upper in the function.

We can't just yet, because it is silly and has a dev_priv == NULL check.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

[Joonas Lahtinen]

On ke, 2016-05-25 at 15:04 +0100, Chris Wilson wrote:
> This is so that we have symmetry with intel_lrc.c and avoid a source of
> if (i915.enable_execlists) layering violation within i915_gem_context.c -
> that is we move the specific handling of the dev_priv->kernel_context
> for legacy submission into the legacy submission code.
> 
> This depends upon the init/fini ordering between contexts and engines
> already defined by intel_lrc.c, and also exporting the context alignment
> required for pinning the legacy context.
> 
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 ++
>  drivers/gpu/drm/i915/i915_gem_context.c | 27 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 31 +++
>  3 files changed, 36 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e4c8e341655c..19d0194c728f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -867,6 +867,8 @@ struct i915_gem_context {
>   u32 user_handle;
>  #define CONTEXT_NO_ZEROMAP   (1<<0)
>  
> + u32 ggtt_alignment;
> +
>   struct intel_context {
>   struct drm_i915_gem_object *state;
>   struct intel_ringbuffer *ringbuf;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index a3b11aac23a4..c620fe6c9d96 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -268,6 +268,8 @@ __create_hw_context(struct drm_device *dev,
>   list_add_tail(>link, _priv->context_list);
>   ctx->i915 = dev_priv;
>  
> + ctx->ggtt_alignment = get_context_alignment(dev_priv);
> +
>   if (dev_priv->hw_context_size) {
>   struct drm_i915_gem_object *obj =
>   i915_gem_alloc_context_obj(dev, 
> dev_priv->hw_context_size);
> @@ -413,26 +415,6 @@ int i915_gem_context_init(struct drm_device *dev)
>   return PTR_ERR(ctx);
>   }
>  
> - if (!i915.enable_execlists && ctx->engine[RCS].state) {
> - int ret;
> -
> - /* We may need to do things with the shrinker which
> -  * require us to immediately switch back to the default
> -  * context. This can cause a problem as pinning the
> -  * default context also requires GTT space which may not
> -  * be available. To avoid this we always pin the default
> -  * context.
> -  */
> - ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state,
> - get_context_alignment(dev_priv), 0);
> - if (ret) {
> - DRM_ERROR("Failed to pinned default global context 
> (error %d)\n",
> -   ret);
> - i915_gem_context_unreference(ctx);
> - return ret;
> - }
> - }
> -
>   dev_priv->kernel_context = ctx;
>  
>   DRM_DEBUG_DRIVER("%s context support initialized\n",
> @@ -469,9 +451,6 @@ void i915_gem_context_fini(struct drm_device *dev)
>  
>   lockdep_assert_held(>struct_mutex);
>  
> - if (!i915.enable_execlists && dctx->engine[RCS].state)
> - i915_gem_object_ggtt_unpin(dctx->engine[RCS].state);
> -
>   i915_gem_context_unreference(dctx);
>   dev_priv->kernel_context = NULL;
>  
> @@ -721,7 +700,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
>  
>   /* Trying to pin first makes error handling easier. */
>   ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
> - get_context_alignment(engine->i915),
> + to->ggtt_alignment,
>   0);
>   if (ret)
>   return ret;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a3978f9b..4e0aa7e9d5da 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2244,6 +2244,8 @@ static int intel_init_ring_buffer(struct drm_device 
> *dev,
>     struct intel_engine_cs *engine)
>  {
>   struct drm_i915_private *dev_priv = to_i915(dev);
> + struct i915_gem_context *kctx = dev_priv->kernel_context;
> + struct intel_context *ce = >engine[engine->id];

I'd prefer kctxe name, just to make it clear they're tightly related.

>   struct intel_ringbuffer *ringbuf;
>   int ret;
>  
> @@ -2260,6 +2262,25 @@ static int intel_init_ring_buffer(struct drm_device 
> *dev,
>  
>   init_waitqueue_head(>irq_queue);
>  
> + if (ce->state) {
> + i915_gem_context_reference(kctx);

Without rename this looks rather odd.

> +
> + /* We may need to do things with the shrinker which
> +  * require us to immediately 

Re: [Intel-gfx] [PATCHv6 5/5] drm/i915/dp: Enable Upfront link training for typeC DP support on BXT

[R, Durgadoss]

> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Wednesday, May 25, 2016 9:05 PM
> To: R, Durgadoss 
> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander
> 
> Subject: Re: [Intel-gfx] [PATCHv6 5/5] drm/i915/dp: Enable Upfront link
> training for typeC DP support on BXT
> 
> On Fri, May 20, 2016 at 02:29:02PM +0530, Durgadoss R wrote:
> > To support USB type C alternate DP mode, the display driver needs to
> > know the number of lanes required by the DP panel as well as number
> > of lanes that can be supported by the type-C cable. Sometimes, the
> > type-C cable may limit the bandwidth even if Panel can support
> > more lanes. To address these scenarios, the display driver will
> > start link training with max lanes, and if that fails, the driver
> > falls back to x2 lanes; and repeats this procedure for all
> > bandwidth/lane configurations.
> >
> > * Since link training is done before modeset only the port
> >   (and not pipe/planes) and its associated PLLs are enabled.
> > * On DP hotplug: Directly start link training on the DP encoder.
> > * On Connected boot scenarios: When booted with an LFP and a DP,
> >   sometimes BIOS brings up DP. In these cases, we disable the
> >   crtc and then do upfront link training; and bring it back up.
> > * All local changes made for upfront link training are reset
> >   to their previous values once it is done; so that the
> >   subsequent modeset is not aware of these changes.
> >
> > Changes since v5:
> > * Moved retry logic in upfront to intel_dp.c so that it
> >   can be used for all platforms.
> > Changes since v4:
> > * Removed usage of crtc_state in upfront link training;
> >   Hence no need to find free crtc to do upfront now.
> > * Re-enable crtc if it was disabled for upfront.
> > * Use separate variables to track max lane count
> >   and link rate found by upfront, without modifying
> >   the original DPCD read from panel.
> > Changes since v3:
> > * Fixed a return value on BXT check
> > * Reworked on top of bxt_ddi_pll_select split from Ander
> > * Renamed from ddi_upfront to bxt_upfront since the
> >   upfront logic includes BXT specific functions for now.
> > Changes since v2:
> > * Rebased on top of latest dpll_mgr.c code and
> >   latest HPD related clean ups.
> > * Corrected return values from upfront (Ander)
> > * Corrected atomic locking for upfront in intel_dp.c (Ville)
> > Changes since v1:
> > *  all pll related functions inside ddi.c
> >
> > Signed-off-by: Durgadoss R 
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c |  45 ++
> >  drivers/gpu/drm/i915/intel_dp.c  | 179
> +--
> >  drivers/gpu/drm/i915/intel_drv.h |   8 ++
> >  3 files changed, 226 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> > index 7e6331a..8d224bf 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2330,6 +2330,51 @@ intel_ddi_init_hdmi_connector(struct
> intel_digital_port *intel_dig_port)
> > return connector;
> >  }
> >
> > +bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
> > +   int clock, uint8_t lane_count)
> > +{
> > +   struct intel_connector *connector = intel_dp->attached_connector;
> > +   struct intel_encoder *encoder = connector->encoder;
> > +   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +   struct intel_shared_dpll *pll;
> > +   struct intel_shared_dpll_config tmp_pll_config;
> > +   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +   enum intel_dpll_id dpll_id = (enum intel_dpll_id)dig_port->port;
> > +
> > +   /*
> > +* FIXME: Works only for BXT.
> > +* Select the required PLL. This works for platforms where
> > +* there is no shared DPLL.
> > +*/
> > +   pll = _priv->shared_dplls[dpll_id];
> > +   if (WARN_ON(pll->active_mask)) {
> > +   DRM_ERROR("Shared DPLL already in use.
> active_mask:%x\n", pll->active_mask);
> > +   return false;
> > +   }
> > +
> > +   tmp_pll_config = pll->config;
> > +
> > +   if (!bxt_ddi_dp_set_dpll_hw_state(clock, >config.hw_state)) {
> > +   DRM_ERROR("Could not setup DPLL\n");
> > +   pll->config = tmp_pll_config;
> > +   return false;
> > +   }
> > +
> > +   /* Enable PLL followed by port */
> > +   pll->funcs.enable(dev_priv, pll);
> > +   intel_ddi_pre_enable_dp(encoder, clock, lane_count, pll);
> > +
> > +   DRM_DEBUG_KMS("Upfront link train %s: link_clock:%d
> lanes:%d\n",
> > +   intel_dp->train_set_valid ? "Passed" : "Failed", clock, lane_count);
> > +
> > +   /* Disable port followed by PLL for next retry/clean up */
> > +   intel_ddi_post_disable(encoder);
> > +   pll->funcs.disable(dev_priv, pll);
> > +
> > +   pll->config = tmp_pll_config;
> > +   return 

[Intel-gfx] ✗ Ro.CI.BAT: failure for drm: Store the plane's index

[Patchwork]

== Series Details ==

Series: drm: Store the plane's index
URL   : https://patchwork.freedesktop.org/series/7796/
State : failure

== Summary ==

Series 7796v1 drm: Store the plane's index
http://patchwork.freedesktop.org/api/1.0/series/7796/revisions/1/mbox

Test drv_hangman:
Subgroup error-state-basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_busy:
Subgroup basic-blt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
pass   -> FAIL   (ro-byt-n2820)
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-hsw-i7-4770k)
Test gem_flink_basic:
Subgroup double-flink:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
Subgroup basic-read:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (ro-bdw-i7-5600u)
skip   -> PASS   (fi-skl-i5-6260u)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-bsw-n3050 total:209  pass:167  dwarn:0   dfail:0   fail:2   skip:40 
fi-byt-n2820 total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38 
fi-hsw-i7-4770k  total:102  pass:86   dwarn:0   dfail:0   fail:0   skip:15 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:179  dwarn:4   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
ro-bsw-n3050 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1019/

fc9d741 drm-intel-nightly: 2016y-05m-25d-07h-45m-48s UTC integration manifest
a43c03e drm: Store the plane's index

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[Intel-gfx] [PATCH] drm: Store the plane's index

[Chris Wilson]

Currently the plane's index is determined by walking the list of all
planes in the mode and finding the position of that plane in the list. A
linear walk, especially a linear walk within a linear walk as frequently
conceived by i915.ko [O(N^2)] quickly comes to dominate profiles.

The plane's index is constant for as long as no earlier planes are
removed from the list. For most drivers, planes are static, determined
at boot and then untouched until shutdown. Storing the index upon
construction and then only walking the tail upon removal should
be a major improvement for all.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Cc: Matt Roper 
---
 drivers/gpu/drm/drm_crtc.c | 38 +-
 include/drm/drm_crtc.h |  6 +-
 2 files changed, 14 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3a0384cce4a2..00ee01126b6f 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1302,7 +1302,7 @@ int drm_universal_plane_init(struct drm_device *dev, 
struct drm_plane *plane,
plane->type = type;
 
list_add_tail(>head, >plane_list);
-   config->num_total_plane++;
+   plane->index = config->num_total_plane++;
if (plane->type == DRM_PLANE_TYPE_OVERLAY)
config->num_overlay_plane++;
 
@@ -1369,6 +1369,7 @@ EXPORT_SYMBOL(drm_plane_init);
 void drm_plane_cleanup(struct drm_plane *plane)
 {
struct drm_device *dev = plane->dev;
+   struct drm_plane *other;
 
drm_modeset_lock_all(dev);
kfree(plane->format_types);
@@ -1376,6 +1377,10 @@ void drm_plane_cleanup(struct drm_plane *plane)
 
BUG_ON(list_empty(>head));
 
+   other = list_next_entry(plane, head);
+   list_for_each_entry_from(other, >mode_config.plane_list, head)
+   other->index--;
+
list_del(>head);
dev->mode_config.num_total_plane--;
if (plane->type == DRM_PLANE_TYPE_OVERLAY)
@@ -1393,29 +1398,6 @@ void drm_plane_cleanup(struct drm_plane *plane)
 EXPORT_SYMBOL(drm_plane_cleanup);
 
 /**
- * drm_plane_index - find the index of a registered plane
- * @plane: plane to find index for
- *
- * Given a registered plane, return the index of that CRTC within a DRM
- * device's list of planes.
- */
-unsigned int drm_plane_index(struct drm_plane *plane)
-{
-   unsigned int index = 0;
-   struct drm_plane *tmp;
-
-   drm_for_each_plane(tmp, plane->dev) {
-   if (tmp == plane)
-   return index;
-
-   index++;
-   }
-
-   BUG();
-}
-EXPORT_SYMBOL(drm_plane_index);
-
-/**
  * drm_plane_from_index - find the registered plane at an index
  * @dev: DRM device
  * @idx: index of registered plane to find for
@@ -1427,13 +1409,11 @@ struct drm_plane *
 drm_plane_from_index(struct drm_device *dev, int idx)
 {
struct drm_plane *plane;
-   unsigned int i = 0;
 
-   drm_for_each_plane(plane, dev) {
-   if (i == idx)
+   drm_for_each_plane(plane, dev)
+   if (idx == plane->index)
return plane;
-   i++;
-   }
+
return NULL;
 }
 EXPORT_SYMBOL(drm_plane_from_index);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 9771428e1ba8..eda3b1b3d3b4 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1543,6 +1543,7 @@ struct drm_plane {
struct drm_object_properties properties;
 
enum drm_plane_type type;
+   unsigned index;
 
const struct drm_plane_helper_funcs *helper_private;
 
@@ -2316,7 +2317,10 @@ extern int drm_plane_init(struct drm_device *dev,
  const uint32_t *formats, unsigned int format_count,
  bool is_primary);
 extern void drm_plane_cleanup(struct drm_plane *plane);
-extern unsigned int drm_plane_index(struct drm_plane *plane);
+static inline unsigned int drm_plane_index(struct drm_plane *plane)
+{
+   return plane->index;
+}
 extern struct drm_plane * drm_plane_from_index(struct drm_device *dev, int 
idx);
 extern void drm_plane_force_disable(struct drm_plane *plane);
 extern int drm_plane_check_pixel_format(const struct drm_plane *plane,
-- 
2.8.1

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[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [v3,01/10] drm/i915: Skip idling an idle engine

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm/i915: Skip idling an idle engine
URL   : https://patchwork.freedesktop.org/series/7792/
State : failure

== Summary ==

Series 7792v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/7792/revisions/1/mbox

Test gem_busy:
Subgroup basic-blt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
pass   -> FAIL   (ro-byt-n2820)
Test gem_mmap_gtt:
Subgroup basic-read:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (ro-bdw-i7-5600u)
skip   -> PASS   (fi-skl-i5-6260u)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-bsw-n3050 total:209  pass:167  dwarn:0   dfail:0   fail:2   skip:40 
fi-byt-n2820 total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:181  dwarn:2   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 

Results at /archive/results/CI_IGT_test/RO_Patchwork_1018/

fc9d741 drm-intel-nightly: 2016y-05m-25d-07h-45m-48s UTC integration manifest
74f34c4 drm/i915: Defer enabling rc6 til after we submit the first batch/context
1b32d08 drm/i915: Remove superfluous powersave work flushing
1ceeaf8f drm/i915: Preserve current RPS frequency
fd62102 drm/i915: Only switch to default context when evicting from GGTT
ad05e18 drm/i915: Split idling from forcing context switch
abdffae drm/i915: No need to wait for idle on L3 remap
33ef68f drm/i915: Mark all default contexts as uninitialised after context loss
97c1019 drm/i915: Treat kernel context as initialised
95c103e drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c
a3add04 drm/i915: Skip idling an idle engine

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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Implement intel_dp_autotest_video_pattern function for DP Video pattern compliance tests

[Ander Conselvan De Oliveira]

On Wed, 2016-05-25 at 15:46 -0700, Manasi Navare wrote:
> On Mon, May 23, 2016 at 03:00:20PM +0300, Ander Conselvan De Oliveira wrote:
> > 
> > On Fri, 2016-04-29 at 18:28 -0700, Manasi Navare wrote:
> > > 
> > > This video pattern test function gets invoked through the
> > > compliance test handler on a HPD short pulse if the test type is
> > > set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers
> > > reads to read the requested test pattern, video pattern resolution,
> > > frame rate and bits per color value. The results of this analysis
> > > are handed off to userspace so that the userspace app can set the
> > > video pattern mode appropriately for the test result/response.
> > > 
> > > The compliance_test_active flag is set at the end of the individual
> > > test handling functions. This is so that the kernel-side operations
> > > can be completed without the risk of interruption from the userspace
> > > app that is polling on that flag.
> > > 
> > > Signed-off-by: Manasi Navare 
> > > ---
> > >  drivers/gpu/drm/i915/i915_debugfs.c | 14 ++-
> > >  drivers/gpu/drm/i915/intel_dp.c | 76
> > > +
> > >  drivers/gpu/drm/i915/intel_drv.h|  9 +
> > >  include/drm/drm_dp_helper.h | 14 ++-
> > >  4 files changed, 111 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 6ee69b1..c8d0805 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -4458,7 +4458,19 @@ static int i915_displayport_test_data_show(struct
> > > seq_file *m, void *data)
> > >   if (connector->status == connector_status_connected &&
> > >   connector->encoder != NULL) {
> > >   intel_dp = enc_to_intel_dp(connector->encoder);
> > > - seq_printf(m, "%lx", intel_dp-
> > > >compliance_test_data);
> > > + if (intel_dp->compliance_test_type ==
> > > + DP_TEST_LINK_EDID_READ)
> > > + seq_printf(m, "%lx",
> > > +    intel_dp-
> > > >compliance_test_data);
> > > + else if (intel_dp->compliance_test_type ==
> > > +  DP_TEST_LINK_VIDEO_PATTERN) {
> > > + seq_printf(m, "hdisplay: %lu\n",
> > > +    intel_dp->test_data.hdisplay);
> > > + seq_printf(m, "vdisplay: %lu\n",
> > > +    intel_dp->test_data.vdisplay);
> > > + seq_printf(m, "bpc: %u\n",
> > > +    intel_dp->test_data.bpc);
> > > + }
> > >   } else
> > >   seq_puts(m, "0");
> > >   }
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 456fc17..134cff8 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -4018,6 +4018,82 @@ static uint8_t
> > > intel_dp_autotest_link_training(struct
> > > intel_dp *intel_dp)
> > >  static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
> > >  {
> > >   uint8_t test_result = DP_TEST_NAK;
> > > + uint8_t test_pattern;
> > > + uint16_t  h_width, v_height, test_misc;
> > > + int status = 0;
> > > +
> > > + /* Automation support for Video Pattern Tests has a dependency
> > > +  * on Link training Automation support (CTS Test 4.3.1.11)
> > > +  * Hence it returns a TEST NAK until the Link Training automation
> > > +  * support is added to the kernel
> > > +  */
> > > + return test_result;
> > We shouldn't merge this patch until this is resolved. There's no point in
> > adding
> > dead code.
> > 
> > 
> I agree. I would still respin it based on the review feedback and keep it
> ready.
> So as soon as the link training rework is done, this patch can be pulled in
> and 
> this test can b enabled.
>  
> > 
> > > 
> > > +
> > > + /* Read the TEST_PATTERN (DP CTS 3.1.5) */
> > > + status = drm_dp_dpcd_read(_dp->aux, DP_TEST_PATTERN,
> > > +   _pattern, 1);
> > > + if (status <= 0) {
> > > + DRM_DEBUG_KMS("Could not read test pattern from"
> > > +   "refernce sink\n");
> > > + return 0;
> > > + }
> > > + if (test_pattern != DP_COLOR_RAMP)
> > > + return test_result;
> > > + intel_dp->test_data.video_pattern = test_pattern;
> > > +
> > > + status = drm_dp_dpcd_read(_dp->aux, DP_TEST_H_WIDTH,
> > > +   _width, 2);
> > > + if (status <= 0) {
> > > + DRM_DEBUG_KMS("Could not read H Width from"
> > > +   "refernce sink\n");
> > > + return 0;
> > > + }
> > > + intel_dp->test_data.hdisplay = (h_width & DP_TEST_MSB_MASK) >> 8
> > > |
> > > + (h_width << 8);
> > Just use the 

[Intel-gfx] ✗ Ro.CI.BAT: warning for mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

[Patchwork]

== Series Details ==

Series: mutex: Do not spin/queue before performing ww_mutex deadlock avoidance
URL   : https://patchwork.freedesktop.org/series/7788/
State : warning

== Summary ==

Series 7788v1 mutex: Do not spin/queue before performing ww_mutex deadlock 
avoidance
http://patchwork.freedesktop.org/api/1.0/series/7788/revisions/1/mbox

Test gem_busy:
Subgroup basic-blt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
fail   -> PASS   (fi-byt-n2820)
Test gem_mmap_gtt:
Subgroup basic-read:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (ro-byt-n2820)
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (ro-bdw-i7-5600u)
skip   -> PASS   (fi-skl-i5-6260u)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test pm_rps:
Subgroup basic-api:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:2   skip:38 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-byt-n2820 total:209  pass:169  dwarn:1   dfail:0   fail:2   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:180  dwarn:3   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
fi-bsw-n3050 failed to connect after reboot
ro-bsw-n3050 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1017/

fc9d741 drm-intel-nightly: 2016y-05m-25d-07h-45m-48s UTC integration manifest
71d575d mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

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Re: [Intel-gfx] [PATCH 4/5] Add support for forcing 6 bpc on DP pipes.

[Ander Conselvan De Oliveira]

On Wed, 2016-05-25 at 17:42 -0700, Manasi Navare wrote:
> On Tue, May 24, 2016 at 08:45:45AM +0300, Ander Conselvan De Oliveira wrote:
> > 
> > On Mon, 2016-05-23 at 10:42 -0700, Jim Bride wrote:
> > > 
> > > On Mon, May 23, 2016 at 11:22:17AM +0300, Ander Conselvan De Oliveira
> > > wrote:
> > > > 
> > > > 
> > > > On Fri, 2016-04-29 at 18:28 -0700, Manasi Navare wrote:
> > > > > 
> > > > > 
> > > > > From: Jim Bride 
> > > > > 
> > > > > For DP compliance we need to be able to control the output color
> > > > > type for the pipe associated with the DP port. To do this we rely
> > > > > on the intel_dp_test_force_bpc debugfs file and the associated value
> > > > > stored in struct intel_dp. If the debugfs file has a non-zero value
> > > > > and we're on a display port connector, then we use the value from
> > > > > debugfs to calculate the bpp for the pipe.  For cases where we are
> > > > > not on DP or there has not been an overridden value then we behave
> > > > > as normal.
> > > > > 
> > > > > Signed-off-by: Jim Bride 
> > > > > Signed-off-by: Manasi Navare 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_display.c | 32
> > > > > ++-
> > > > > -
> > > > >  drivers/gpu/drm/i915/intel_drv.h |  1 +
> > > > >  2 files changed, 31 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > > index 5ffccf6..1618d36 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > > @@ -12102,11 +12102,39 @@ compute_baseline_pipe_bpp(struct intel_crtc
> > > > > *crtc,
> > > > >  
> > > > >   /* Clamp display bpp to EDID value */
> > > > >   for_each_connector_in_state(state, connector,
> > > > > connector_state, i)
> > > > > {
> > > > > + int type = 0;
> > > > > +
> > > > > + if (connector_state->best_encoder) {
> > > > > + struct intel_encoder *ienc;
> > > > > +
> > > > > + ienc = to_intel_encoder(connector_state-
> > > > > > 
> > > > > > 
> > > > > > best_encoder);
> > > > > + type = ienc->type;
> > > > > + }
> > > > > +
> > > > >   if (connector_state->crtc != >base)
> > > > >   continue;
> > > > >  
> > > > > - connected_sink_compute_bpp(to_intel_connector(connect
> > > > > or),
> > > > > -    pipe_config);
> > > > > + /* For DP compliance we need to ensure that we can
> > > > > override
> > > > > +  * the computed bpp for the pipe.
> > > > > +  */
> > > > > + if (type == INTEL_OUTPUT_DISPLAYPORT) {
> > > > > + struct intel_dp *intel_dp =
> > > > > + enc_to_intel_dp(connector_state-
> > > > > > 
> > > > > > 
> > > > > > best_encoder);
> > > > > +
> > > > > + if (intel_dp &&
> > > > > + (intel_dp->compliance_force_bpc != 0)) {
> > > > > + pipe_config->pipe_bpp =
> > > > > + intel_dp-
> > > > > >compliance_force_bpc*3;
> > > > > + DRM_DEBUG_KMS("JMB Setting pipe_bpp
> > > > > to
> > > > > %d\n",
> > > > > +   pipe_config->pipe_bpp);
> > > > > + } else {
> > > > > + connected_sink_compute_bpp(to_intel_c
> > > > > onne
> > > > > ctor
> > > > > (connector),
> > > > > +    pipe_config);
> > > > This kind of thing should be done in the encoder compute_config hook.
> > > Even though it's really not specific to an individual encoder
> > > configuration?
> > > This seems to be the central place where we're ensuring that we have a
> > > sane
> > > value for bpp relative to the display, and thus a good place to set this
> > > override to make compliance happy (which needs a specific bpc value for
> > > some
> > > test cases rather than one that is deemed sane relative to the sink's
> > > capabilities.
> > Well, this code path is only reached when the DisplayPort associated with a
> > given encoder is in the middle of compliance testing. I'd say that's very
> > encoder specific.
> > 
> > The bpp computation happens in two phases. Here a baseline is computed,
> > considering what is generally supported by the hardware. The encoders are
> > allowed to override that value. You can look at HDMI for an example: it may
> > require a bpp override since HDMI doesn't supports 10 bpc, only 8 or 12. You
> > can
> >  find similar code also in LVDS and even DP.
> > 
> > Unfortunately, there is very little documentation of what the hooks are
> > supposed
> > to do. But for the question at hand, yes, it should really be in
> > 

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Fixes to support the DP Compliance EDID tests.

[Ander Conselvan De Oliveira]

On Wed, 2016-05-25 at 17:22 -0700, Manasi Navare wrote:
> On Mon, May 23, 2016 at 11:18:20AM +0300, Ander Conselvan De Oliveira wrote:
> > 
> > On Fri, 2016-04-29 at 18:28 -0700, Manasi Navare wrote:
> > > 
> > > This patch addresses a few issues from the original patch for
> > > DP Compliance EDID test support submitted by
> > > Todd Previte
> > Do you mean commit 559be30cb74d ("drm/i915: Implement the
> > intel_dp_autotest_edid
> > function for DP EDID complaince tests")? Please see the link below on how to
> > refer to other commits in the commit message and how to add a Fixes: tag.
> > 
> > https://www.kernel.org/doc/Documentation/SubmittingPatches
> > 
> > > 
> > > 
> > > Video Mode requested in the EDID test handler for the EDID Read
> > > test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
> > > Intel connector status should be connected even if detect_edid is
> > > NULL when compliance_test flag is set. This is required to handle
> > > the corrupt EDID (CTS 4.2.2.6) or EDID Read Failure I2C NACK/I2C
> > > DEFER (CTS 4.2.2.4 and 4.2.2.5) tests from CTS spec.
> > What exactly do those tests test? It sounds like this patch adds a separate
> > code
> > path to implement the right behavior only when running the CTS. Shouldn't
> > the
> > driver handle those failures during normal operation in the same way?
> > 
> These tests see if the system behaves as expected in case of currupt EDID 
> or I2C NACK or I2C DEFER and validates if in all these cases it displays
> the failsafe mode. This test gets triggered on a long pulse sent by DPR 120.

So my question is, in those failure scenarios when not in the middle of
compliance testing, does the system behaves as expected?

Ander

> 
>  
> > 
> > > 
> > > 
> > > Signed-off-by: Manasi Navare 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 0961f22..456fc17 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -4023,7 +4023,7 @@ static uint8_t
> > > intel_dp_autotest_video_pattern(struct
> > > intel_dp *intel_dp)
> > >  
> > >  static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
> > >  {
> > > - uint8_t test_result = DP_TEST_NAK;
> > > + uint8_t test_result = DP_TEST_ACK;
> > >   struct intel_connector *intel_connector = intel_dp-
> > > > 
> > > > attached_connector;
> > >   struct drm_connector *connector = _connector->base;
> > >  
> > > @@ -4058,7 +4058,7 @@ static uint8_t intel_dp_autotest_edid(struct
> > > intel_dp
> > > *intel_dp)
> > >   DRM_DEBUG_KMS("Failed to write EDID checksum\n");
> > >  
> > >   test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
> > > - intel_dp->compliance_test_data =
> > > INTEL_DP_RESOLUTION_STANDARD;
> > > + intel_dp->compliance_test_data =
> > > INTEL_DP_RESOLUTION_PREFERRED;
> > Is this used for anything else than logging?
> > 
> This is used to tell the userspace app to display the Preferred mode
> or failsafe mode for that test scenario.
> This compliance test data gets read in userspace IGT App.
> 
> 
> > 
> > > 
> > >   }
> > >  
> > >   /* Set test active flag here so userspace doesn't interrupt
> > > things */
> > > @@ -4650,7 +4650,7 @@ intel_dp_detect(struct drm_connector *connector,
> > > bool
> > > force)
> > >  
> > >   intel_dp->detect_done = false;
> > >  
> > > - if (intel_connector->detect_edid)
> > > + if (intel_connector->detect_edid || intel_dp-
> > > >compliance_test_active)
> > Should this check connector->edid_corrupt instead? I guess that would
> > require
> > some logic to fallback to fail safe mode and bpc too.
> > 
> > I think Shubhangi had a patch for this same problem, but it also seems to
> > create
> > a separate path for compliance.
> > 
> > Ander
> This check only makes sure that if the compliance test is in progress then
> that means
> it is testing for cases like corrupt edid and NACK/I2C defer and hence its a
> fake or
> purposely created corrupt EDID or I2C failure scenario so report the connector
> as connected. Otherwise, it reports it out as disconnected and treats this
> test scenario
> as a real failure and the test does not complete.
> 
> Manasi
> 
> > 
> > > 
> > >   return connector_status_connected;
> > >   else
> > >   return connector_status_disconnected;
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[Intel-gfx] [PATCH v3 08/10] drm/i915: Preserve current RPS frequency

[Chris Wilson]

Select idle frequency during initialisation, then reset the last known
frequency when re-enabling. This allows us to preserve the user selected
frequency across resets.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_pm.c | 34 +-
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b6dfd0264950..b85b7840a2ca 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4954,6 +4954,7 @@ static void gen6_init_rps_frequencies(struct 
drm_i915_private *dev_priv)
}
 
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
+   dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
 
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
@@ -4970,6 +4971,15 @@ static void gen6_init_rps_frequencies(struct 
drm_i915_private *dev_priv)
}
 }
 
+static void reset_rps(struct drm_i915_private *dev_priv,
+ void (*set)(struct drm_i915_private *, u8))
+{
+   u8 freq = dev_priv->rps.cur_freq; /* force a reset */
+   dev_priv->rps.power = -1;
+   dev_priv->rps.cur_freq = -1;
+   set(dev_priv, freq);
+}
+
 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 {
@@ -5006,8 +5016,7 @@ static void gen9_enable_rps(struct drm_i915_private 
*dev_priv)
/* Leaning on the below call to gen6_set_rps to program/setup the
 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
-   dev_priv->rps.power = HIGH_POWER; /* force a reset */
-   gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
+   reset_rps(dev_priv, gen6_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
@@ -5153,8 +5162,7 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
 
/* 6: Ring frequency + overclocking (our driver does this later */
 
-   dev_priv->rps.power = HIGH_POWER; /* force a reset */
-   gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
+   reset_rps(dev_priv, gen6_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
@@ -5247,8 +5255,7 @@ static void gen6_enable_rps(struct drm_i915_private 
*dev_priv)
dev_priv->rps.max_freq = pcu_mbox & 0xff;
}
 
-   dev_priv->rps.power = HIGH_POWER; /* force a reset */
-   gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
+   reset_rps(dev_priv, gen6_set_rps);
 
rc6vids = 0;
ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, 
);
@@ -5612,6 +5619,7 @@ static void valleyview_init_gt_powersave(struct 
drm_i915_private *dev_priv)
 dev_priv->rps.min_freq);
 
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
+   dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
 
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5676,6 +5684,7 @@ static void cherryview_init_gt_powersave(struct 
drm_i915_private *dev_priv)
  "Odd GPU freq values\n");
 
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
+   dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
 
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5784,7 +5793,7 @@ static void cherryview_enable_rps(struct drm_i915_private 
*dev_priv)
 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
 dev_priv->rps.idle_freq);
 
-   valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
+   reset_rps(dev_priv, valleyview_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
@@ -5864,16 +5873,7 @@ static void valleyview_enable_rps(struct 
drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
 
-   dev_priv->rps.cur_freq = (val >> 8) & 0xff;
-   DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
-intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
-dev_priv->rps.cur_freq);
-
-   DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
-dev_priv->rps.idle_freq);
-
-   valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
+   reset_rps(dev_priv, valleyview_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
-- 
2.8.1

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