[Intel-gfx] [PATCH] drm/i915: Restore DMC required version for Skylake (1.26)

[Rodrigo Vivi]

With commit 4aa7fb9c ("drm/i915/dmc: Step away from symbolic
links") we started loading the firmware version directly
instead of symbolic links.

With this VERSION_REQUIRED variables changed the meaning
from minimal required to exact version required. Along
with this change we started using the latest stable
DMC firmware as the required one 1.26.

This patch is correct. However in some merge this
change got missed and it was overwritten by the old
version.

1.23 is unstable and can cause blank screens so let's
avoid it.

Cc: sta...@vger.kernel.org
Cc: Jani Nikula 
Cc: Daniel Vetter 
Cc: Patrik Jakobsson 
Cc: Matthew Atwood 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97182
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index fb27d18..0efce3f 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -40,7 +40,7 @@ MODULE_FIRMWARE(I915_CSR_KBL);
 
 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
 MODULE_FIRMWARE(I915_CSR_SKL);
-#define SKL_CSR_VERSION_REQUIRED   CSR_VERSION(1, 23)
+#define SKL_CSR_VERSION_REQUIRED   CSR_VERSION(1, 26)
 
 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
 MODULE_FIRMWARE(I915_CSR_BXT);
-- 
2.5.5

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] Correct DMC version for Skylake (1.23 vs 1.26)

[Rodrigo Vivi]

On Tue, Aug 9, 2016 at 1:48 AM, Jani Nikula  wrote:
> On Tue, 09 Aug 2016, Daniel Klaffenbach  wrote:
>> Hi,
>>
>> which one is the correct DMC version to load for Linux 4.8-rc1? The
>> binary blob in linux-firmware.git is v1.26, which is also the latest
>> version available for download at the linuxgraphics website.
>>
>> Version 1.26 used to load just fine on Kernels 4.6 and 4.7. Commit
>> 4aa7fb9c introduced version pinning for v1.26 (both in
>> drm-intel-nightly and the current for-linux-next branch). Later an
>> older commit was pushed (a4a027a8), which lowered the
>> required DMC firmware to v1.23 again, without removing the
>> pinning.
>>
>> Now the situation is that v1.23 is pinned ATM, but v1.26 has been
>> released through linux-firmware.git and is being rolled out to end
>> users right now.
>>
>> What to do now? Is this a bug or a feature?

It is a bug, I'm sending a patch right now.

>
> You should use whichever version the kernel asks. The bug is that v1.23
> was dropped from linux-firmware.

1.23 was intentionally dropped from linux-firmware since 1.26 was
already the required one by our driver.

Some merge probably failed and overwrote what Patrik had properly done
in commit  4aa7fb9c ("drm/i915/dmc: Step away from symbolic
links")

> We may later upgrade the firmware the
> kernel asks, and even backport said upgrade to stable kernels after
> ensuring it works.
>
> Rodrigo, please fix linux-firmware.

No, I'm going to fix our driver.

Well, I can restore the 1.23 there if you tell me there is no way we
can make sure this patch that I'm about to send will land and be
backported on time, but this is not the ideal since we know 1.23 will
cause bugs.

Thanks,
Rodrigo

>
> BR,
> Jani.
>
>>
>>
>> Regards,
>>  Dan
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Add smp_rmb() to busy ioctl's RCU dance

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Add smp_rmb() to busy ioctl's 
RCU dance
URL   : https://patchwork.freedesktop.org/series/10828/
State : failure

== Summary ==

Applying: drm/i915: Add smp_rmb() to busy ioctl's RCU dance
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_gem.c
M   drivers/gpu/drm/i915/i915_gem_request.h
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.
Applying: drm/i915: Do not overwrite the request with zero on reallocation
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_gem_request.c
M   drivers/gpu/drm/i915/i915_gem_request.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_gem_request.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_request.c
error: Failed to merge in the changes.
Patch failed at 0002 drm/i915: Do not overwrite the request with zero on 
reallocation
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Remove unused i915_gem_active_peek_rcu()

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915: Remove unused 
i915_gem_active_peek_rcu()
URL   : https://patchwork.freedesktop.org/series/10826/
State : failure

== Summary ==

Applying: drm/i915: Remove unused i915_gem_active_peek_rcu()
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_gem_request.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_gem_request.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_request.h
error: Failed to merge in the changes.
Patch failed at 0001 drm/i915: Remove unused i915_gem_active_peek_rcu()
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Fix braces in conditonal branches

[Pandiyan, Dhinakaran]

On Tue, 2016-08-09 at 23:08 +0100, Chris Wilson wrote:
> On Tue, Aug 09, 2016 at 03:06:10PM -0700, Dhinakaran Pandiyan wrote:
> > No functional change, just adding braces to all branches of conditional
> > statement because one of them already had.
> > ---
> >  drivers/gpu/drm/i915/intel_audio.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index d32f586..26a795f 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -335,11 +335,11 @@ static void hsw_audio_codec_enable(struct 
> > drm_connector *connector,
> >  
> > tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> > if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
> > -   if (!acomp)
> > +   if (!acomp) {
> > rate = 0;
> > -   else if (port >= PORT_A && port <= PORT_E)
> > +   } else if (port >= PORT_A && port <= PORT_E) {
> > rate = acomp->aud_sample_rate[port];
> > -   else {
> > +   } else {
> > DRM_ERROR("invalid port: %d\n", port);
> > rate = 0;
> > }
> 
> Or you could improve scoping of the locals and eliminate a few lines
> whilst adding more information to the debug:
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index d32f586..98d4576 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -282,14 +282,9 @@ static void hsw_audio_codec_enable(struct drm_connector 
> *connector,
> struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> enum pipe pipe = intel_crtc->pipe;
> -   struct i915_audio_component *acomp = dev_priv->audio_component;
> const uint8_t *eld = connector->eld;
> -   struct intel_digital_port *intel_dig_port =
> -   enc_to_dig_port(>base);
> -   enum port port = intel_dig_port->port;
> uint32_t tmp;
> int len, i;
> -   int n, rate;
>  
> DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
>   pipe_name(pipe), drm_eld_size(eld));
> @@ -335,19 +330,18 @@ static void hsw_audio_codec_enable(struct drm_connector 
> *connector,
>  
> tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
> -   if (!acomp)
> -   rate = 0;
> -   else if (port >= PORT_A && port <= PORT_E)
> +   enum port port = enc_to_dig_port(_base)->port;
> +   struct i915_audio_component *acomp = 
> dev_priv->audio_component;
> +   int rate, n;
> +
> +   rate = 0;
> +   if (acomp && port >= PORT_A && port <= PORT_E)
> rate = acomp->aud_sample_rate[port];
> -   else {
> -   DRM_ERROR("invalid port: %d\n", port);
> -   rate = 0;
> -   }
> +
> n = audio_config_get_n(adjusted_mode, rate);
> -   if (n != 0)
> +   DRM_DEBUG_KMS("port %d audio rate %d => N=%x\n", port, rate, 
> n);
> +   if (n)
> tmp = audio_config_setup_n_reg(n, tmp);
> -   else
> -   DRM_DEBUG_KMS("no suitable N value is found\n");
> }
>  
> I915_WRITE(HSW_AUD_CFG(pipe), tmp);
> 
> 

This looks a lot cleaner. 

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Fix braces in conditonal branches

[Chris Wilson]

On Tue, Aug 09, 2016 at 03:06:10PM -0700, Dhinakaran Pandiyan wrote:
> No functional change, just adding braces to all branches of conditional
> statement because one of them already had.
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index d32f586..26a795f 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -335,11 +335,11 @@ static void hsw_audio_codec_enable(struct drm_connector 
> *connector,
>  
>   tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
>   if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
> - if (!acomp)
> + if (!acomp) {
>   rate = 0;
> - else if (port >= PORT_A && port <= PORT_E)
> + } else if (port >= PORT_A && port <= PORT_E) {
>   rate = acomp->aud_sample_rate[port];
> - else {
> + } else {
>   DRM_ERROR("invalid port: %d\n", port);
>   rate = 0;
>   }

Or you could improve scoping of the locals and eliminate a few lines
whilst adding more information to the debug:

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index d32f586..98d4576 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -282,14 +282,9 @@ static void hsw_audio_codec_enable(struct drm_connector 
*connector,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
enum pipe pipe = intel_crtc->pipe;
-   struct i915_audio_component *acomp = dev_priv->audio_component;
const uint8_t *eld = connector->eld;
-   struct intel_digital_port *intel_dig_port =
-   enc_to_dig_port(>base);
-   enum port port = intel_dig_port->port;
uint32_t tmp;
int len, i;
-   int n, rate;
 
DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
  pipe_name(pipe), drm_eld_size(eld));
@@ -335,19 +330,18 @@ static void hsw_audio_codec_enable(struct drm_connector 
*connector,
 
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
-   if (!acomp)
-   rate = 0;
-   else if (port >= PORT_A && port <= PORT_E)
+   enum port port = enc_to_dig_port(_base)->port;
+   struct i915_audio_component *acomp = dev_priv->audio_component;
+   int rate, n;
+
+   rate = 0;
+   if (acomp && port >= PORT_A && port <= PORT_E)
rate = acomp->aud_sample_rate[port];
-   else {
-   DRM_ERROR("invalid port: %d\n", port);
-   rate = 0;
-   }
+
n = audio_config_get_n(adjusted_mode, rate);
-   if (n != 0)
+   DRM_DEBUG_KMS("port %d audio rate %d => N=%x\n", port, rate, n);
+   if (n)
tmp = audio_config_setup_n_reg(n, tmp);
-   else
-   DRM_DEBUG_KMS("no suitable N value is found\n");
}
 
I915_WRITE(HSW_AUD_CFG(pipe), tmp);


-- 
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Fix braces in conditonal branches

[Dhinakaran Pandiyan]

No functional change, just adding braces to all branches of conditional
statement because one of them already had.
---
 drivers/gpu/drm/i915/intel_audio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index d32f586..26a795f 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -335,11 +335,11 @@ static void hsw_audio_codec_enable(struct drm_connector 
*connector,
 
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
-   if (!acomp)
+   if (!acomp) {
rate = 0;
-   else if (port >= PORT_A && port <= PORT_E)
+   } else if (port >= PORT_A && port <= PORT_E) {
rate = acomp->aud_sample_rate[port];
-   else {
+   } else {
DRM_ERROR("invalid port: %d\n", port);
rate = 0;
}
-- 
2.5.0

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2] drm/i915/dp: DP audio API changes for MST

[Dhinakaran Pandiyan]

DP MST provides the capability to send multiple video and audio streams
through a single port. This requires the API's between i915 and audio
drivers to distinguish between multiple audio capable displays that can be
connected to a port. Currently only the port identity is shared in the
APIs. This patch adds support for MST with an additional parameter
'int pipe'.  The existing parameter 'port' does not change it's meaning.

pipe =
MST : display pipe that the stream originates from
Non-MST : -1

Affected APIs:
struct i915_audio_component_ops
-   int (*sync_audio_rate)(struct device *, int port, int rate);
+   int (*sync_audio_rate)(struct device *, int port, int pipe,
+int rate);

-   int (*get_eld)(struct device *, int port, bool *enabled,
-   unsigned char *buf, int max_bytes);
+   int (*get_eld)(struct device *, int port, int pipe,
+  bool *enabled, unsigned char *buf, int max_bytes);

struct i915_audio_component_audio_ops
-   void (*pin_eld_notify)(void *audio_ptr, int port);
+   void (*pin_eld_notify)(void *audio_ptr, int port, int pipe);

This patch makes dummy changes in the audio drivers (Libin) for build to
succeed. The audio side drivers will send the right 'pipe' values in
patches that will follow.

v2:
Renamed the new API parameter from 'dev_id' to 'pipe'. (Jim, Ville)
Included Asoc driver API compatibility changes from Jeeja.
Added WARN_ON() for invalid pipe in get_saved_encoder(). (Takashi)
Added comment for av_enc_map[] definition. (Takashi)

Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_drv.h|  3 +-
 drivers/gpu/drm/i915/intel_audio.c | 92 ++
 include/drm/i915_component.h   |  6 +--
 include/sound/hda_i915.h   | 11 ++---
 sound/hda/hdac_i915.c  |  9 ++--
 sound/pci/hda/patch_hdmi.c |  7 +--
 sound/soc/codecs/hdac_hdmi.c   |  2 +-
 7 files changed, 85 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c36d176..8e4a88f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2036,7 +2036,8 @@ struct drm_i915_private {
/* perform PHY state sanity checks? */
bool chv_phy_assert[2];
 
-   struct intel_encoder *dig_port_map[I915_MAX_PORTS];
+   /* Used to save the pipe-to-encoder mapping for audio */
+   struct intel_encoder *av_enc_map[I915_MAX_PIPES];
 
/*
 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index ef20875..240dad2 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -500,6 +500,7 @@ void intel_audio_codec_enable(struct intel_encoder 
*intel_encoder)
struct i915_audio_component *acomp = dev_priv->audio_component;
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
enum port port = intel_dig_port->port;
+   enum pipe pipe = -1;
 
connector = drm_select_eld(encoder);
if (!connector)
@@ -524,12 +525,18 @@ void intel_audio_codec_enable(struct intel_encoder 
*intel_encoder)
 
mutex_lock(_priv->av_mutex);
intel_encoder->audio_connector = connector;
+
/* referred in audio callbacks */
-   dev_priv->dig_port_map[port] = intel_encoder;
+   dev_priv->av_enc_map[pipe] = intel_encoder;
mutex_unlock(_priv->av_mutex);
 
+
+   if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
+   pipe = crtc->pipe;
+
if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
-   acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 
(int) port);
+   acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
+(int) port, (int) pipe);
 }
 
 /**
@@ -542,22 +549,28 @@ void intel_audio_codec_enable(struct intel_encoder 
*intel_encoder)
 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
 {
struct drm_encoder *encoder = _encoder->base;
+   struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_audio_component *acomp = dev_priv->audio_component;
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
enum port port = intel_dig_port->port;
+   enum pipe pipe = -1;
 
if (dev_priv->display.audio_codec_disable)
dev_priv->display.audio_codec_disable(intel_encoder);
 
mutex_lock(_priv->av_mutex);
intel_encoder->audio_connector = NULL;
-   dev_priv->dig_port_map[port] = NULL;
+   dev_priv->av_enc_map[pipe] = NULL;
mutex_unlock(_priv->av_mutex);
 
+   if 

Re: [Intel-gfx] [PATCH] drm: avoid "possible bad bitmask?" warning

[Daniel Vetter]

On Tue, Aug 9, 2016 at 9:53 PM, Chris Wilson  wrote:
> On Tue, Aug 09, 2016 at 06:35:10PM +0100, Dave Gordon wrote:
>> Recent versions of gcc say this:
>>
>> include/drm/i915_drm.h:96:34: warning: result of ‘65535 << 20’
>> requires 37 bits to represent, but ‘int’ only has 32 bits
>> [-Wshift-overflow=]
>>
>> Reported-by: David Binderman 
>> Signed-off-by: Dave Gordon 
>> Cc: Dave Airlie 
>> ---
>>  include/drm/i915_drm.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
>> index b1755f8..4e1b274 100644
>> --- a/include/drm/i915_drm.h
>> +++ b/include/drm/i915_drm.h
>> @@ -93,6 +93,6 @@ extern bool i915_gpu_turbo_disable(void);
>>  #defineI845_TSEG_SIZE_1M (3 << 1)
>>
>>  #define INTEL_BSM 0x5c
>> -#define   INTEL_BSM_MASK (0x << 20)
>> +#define   INTEL_BSM_MASK (-(1u << 20))
>
> Reviewed-by: Chris Wilson 

And applied, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm: avoid "possible bad bitmask?" warning

[Chris Wilson]

On Tue, Aug 09, 2016 at 06:35:10PM +0100, Dave Gordon wrote:
> Recent versions of gcc say this:
> 
> include/drm/i915_drm.h:96:34: warning: result of ‘65535 << 20’
> requires 37 bits to represent, but ‘int’ only has 32 bits
> [-Wshift-overflow=]
> 
> Reported-by: David Binderman 
> Signed-off-by: Dave Gordon 
> Cc: Dave Airlie 
> ---
>  include/drm/i915_drm.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index b1755f8..4e1b274 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -93,6 +93,6 @@ extern bool i915_gpu_turbo_disable(void);
>  #defineI845_TSEG_SIZE_1M (3 << 1)
>  
>  #define INTEL_BSM 0x5c
> -#define   INTEL_BSM_MASK (0x << 20)
> +#define   INTEL_BSM_MASK (-(1u << 20))

Reviewed-by: Chris Wilson 
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 7/9] drm/i915/dp: Enable upfront link training on SKL

[Manasi Navare]

From: Jim Bride 

Split the PLL selection code out of the BXT upfront link training
implementation and into a stand-alone function in order to allow
for the implementation of a platform neutral upfront link training
function, and then enable upfront link training for Skylake.

Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/intel_ddi.c  | 58 ---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 38 +++
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  2 ++
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++-
 5 files changed, 85 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3921230..ed9ebca 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2378,8 +2378,43 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port 
*intel_dig_port)
return connector;
 }
 
+struct intel_shared_dpll *
+intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
+{
+   struct intel_connector *connector = intel_dp->attached_connector;
+   struct intel_encoder *encoder = connector->encoder;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   struct intel_shared_dpll *pll = NULL;
+   struct intel_shared_dpll_config tmp_pll_config;
+   enum intel_dpll_id dpll_id;
 
-bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
+   if (IS_BROXTON(dev_priv)) {
+   dpll_id =  (enum intel_dpll_id)dig_port->port;
+   /*
+* Select the required PLL. This works for platforms where
+* there is no shared DPLL.
+*/
+   pll = _priv->shared_dplls[dpll_id];
+   if (WARN_ON(pll->active_mask)) {
+
+   DRM_ERROR("Shared DPLL in use. active_mask:%x\n",
+ pll->active_mask);
+   pll = NULL;
+   }
+   tmp_pll_config = pll->config;
+   if (!bxt_ddi_dp_set_dpll_hw_state(clock,
+ >config.hw_state)) {
+   DRM_ERROR("Could not setup DPLL\n");
+   pll->config = tmp_pll_config;
+   }
+   } else if (IS_SKYLAKE(dev_priv)) {
+   pll = skl_find_link_pll(dev_priv, clock);
+   }
+   return pll;
+}
+
+bool intel_ddi_upfront_link_train(struct intel_dp *intel_dp,
  int clock, uint8_t lane_count,
  bool link_mst)
 {
@@ -2388,28 +2423,15 @@ bool intel_bxt_upfront_link_train(struct intel_dp 
*intel_dp,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll;
struct intel_shared_dpll_config tmp_pll_config;
-   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-   enum intel_dpll_id dpll_id = (enum intel_dpll_id)dig_port->port;
 
-   /*
-* FIXME: Works only for BXT.
-* Select the required PLL. This works for platforms where
-* there is no shared DPLL.
-*/
-   pll = _priv->shared_dplls[dpll_id];
-   if (WARN_ON(pll->active_mask)) {
-   DRM_ERROR("Shared DPLL already in use. active_mask:%x\n", 
pll->active_mask);
+   pll = intel_ddi_get_link_dpll(intel_dp, clock);
+   if (pll == NULL) {
+   DRM_ERROR("Could not find DPLL for link training.\n");
return false;
}
-
+   
tmp_pll_config = pll->config;
 
-   if (!bxt_ddi_dp_set_dpll_hw_state(clock, >config.hw_state)) {
-   DRM_ERROR("Could not setup DPLL\n");
-   pll->config = tmp_pll_config;
-   return false;
-   }
-
/* Enable PLL followed by port */
pll->funcs.enable(dev_priv, pll);
intel_ddi_pre_enable_dp(encoder, clock, lane_count, pll, link_mst);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4c03e28..572119e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5762,8 +5762,8 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
 
/* Initialize upfront link training vfunc for DP */
if (intel_encoder->type != INTEL_OUTPUT_EDP) {
-   if (IS_BROXTON(dev))
-   intel_dp->upfront_link_train = 
intel_bxt_upfront_link_train;
+   if (IS_BROXTON(dev) || IS_SKYLAKE(dev))
+   intel_dp->upfront_link_train = 
intel_ddi_upfront_link_train;
}
 
/* eDP only on port B and/or C on vlv/chv */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8ce220e..e5c025e 100644
--- 

[Intel-gfx] [PATCH 9/9] drm/i915: Enable upfront link training support for HSW/BDW

[Manasi Navare]

Get the PLLs for HSW/BDW using the platform specific function
and add hooks for enabling upfront link training on HSW and BDW.

Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_ddi.c | 2 ++
 drivers/gpu/drm/i915/intel_dp.c  | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ed9ebca..fd0c538 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2410,6 +2410,8 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int 
clock)
}
} else if (IS_SKYLAKE(dev_priv)) {
pll = skl_find_link_pll(dev_priv, clock);
+   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+   pll = hsw_ddi_dp_get_dpll(encoder, clock);
}
return pll;
 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 572119e..25190fa 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5762,8 +5762,10 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
 
/* Initialize upfront link training vfunc for DP */
if (intel_encoder->type != INTEL_OUTPUT_EDP) {
-   if (IS_BROXTON(dev) || IS_SKYLAKE(dev))
+   if (IS_BROXTON(dev) || IS_SKYLAKE(dev) ||
+   IS_BROADWELL(dev) || IS_HASWELL(dev))
intel_dp->upfront_link_train = 
intel_ddi_upfront_link_train;
+
}
 
/* eDP only on port B and/or C on vlv/chv */
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 4/9] drm/i915: Split bxt_ddi_pll_select()

[Manasi Navare]

From: Durgadoss R 

Split out of bxt_ddi_pll_select() the logic that calculates the pll
dividers and dpll_hw_state into a new function that doesn't depend on
crtc state. This will be used for enabling the port pll when doing
upfront link training.

v2:
* Refactored code so that bxt_clk_div need not be exported (Durga)
v1:
* Rebased on top of intel_dpll_mgr.c (Durga)
* Initial version from Ander on top of intel_ddi.c

Signed-off-by: Ander Conselvan de Oliveira 

Signed-off-by: Durgadoss R 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 165 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   3 +
 2 files changed, 104 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 0e1af4d..61d2311 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1460,6 +1460,8 @@ struct bxt_clk_div {
uint32_t m2_frac;
bool m2_frac_en;
uint32_t n;
+
+   int vco;
 };
 
 /* pre-calculated values for DP linkrates */
@@ -1473,57 +1475,60 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
{432000, 3, 1, 32, 1677722, 1, 1}
 };
 
-static struct intel_shared_dpll *
-bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
-struct intel_encoder *encoder)
+static bool
+bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state, int clock,
+ struct bxt_clk_div *clk_div)
 {
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_shared_dpll *pll;
-   enum intel_dpll_id i;
-   struct intel_digital_port *intel_dig_port;
-   struct bxt_clk_div clk_div = {0};
-   int vco = 0;
-   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
-   uint32_t lanestagger;
-   int clock = crtc_state->port_clock;
+   struct dpll best_clock;
 
-   if (encoder->type == INTEL_OUTPUT_HDMI) {
-   struct dpll best_clock;
+   /* Calculate HDMI div */
+   /*
+* FIXME: tie the following calculation into
+* i9xx_crtc_compute_clock
+*/
+   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
+   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
+clock, pipe_name(intel_crtc->pipe));
+   return false;
+   }
 
-   /* Calculate HDMI div */
-   /*
-* FIXME: tie the following calculation into
-* i9xx_crtc_compute_clock
-*/
-   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
-   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d 
pipe %c\n",
-clock, pipe_name(crtc->pipe));
-   return NULL;
-   }
+   clk_div->p1 = best_clock.p1;
+   clk_div->p2 = best_clock.p2;
+   WARN_ON(best_clock.m1 != 2);
+   clk_div->n = best_clock.n;
+   clk_div->m2_int = best_clock.m2 >> 22;
+   clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
+   clk_div->m2_frac_en = clk_div->m2_frac != 0;
 
-   clk_div.p1 = best_clock.p1;
-   clk_div.p2 = best_clock.p2;
-   WARN_ON(best_clock.m1 != 2);
-   clk_div.n = best_clock.n;
-   clk_div.m2_int = best_clock.m2 >> 22;
-   clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
-   clk_div.m2_frac_en = clk_div.m2_frac != 0;
+   clk_div->vco = best_clock.vco;
 
-   vco = best_clock.vco;
-   } else if (encoder->type == INTEL_OUTPUT_DP ||
-  encoder->type == INTEL_OUTPUT_EDP) {
-   int i;
+   return true;
+}
 
-   clk_div = bxt_dp_clk_val[0];
-   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-   if (bxt_dp_clk_val[i].clock == clock) {
-   clk_div = bxt_dp_clk_val[i];
-   break;
-   }
+static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
+{
+   int i;
+
+   *clk_div = bxt_dp_clk_val[0];
+   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+   if (bxt_dp_clk_val[i].clock == clock) {
+   *clk_div = bxt_dp_clk_val[i];
+   break;
}
-   vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
}
 
+   clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
+}
+
+static bool bxt_ddi_set_dpll_hw_state(int clock,
+ struct bxt_clk_div *clk_div,
+ struct intel_dpll_hw_state *dpll_hw_state)
+{
+   int vco = clk_div->vco;
+   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
+  

[Intel-gfx] [PATCH v8 5/9] drm/i915/dp: Enable Upfront link training for typeC DP support on BXT

[Manasi Navare]

From: Durgadoss R 

To support USB type C alternate DP mode, the display driver needs to
know the number of lanes required by the DP panel as well as number
of lanes that can be supported by the type-C cable. Sometimes, the
type-C cable may limit the bandwidth even if Panel can support
more lanes. To address these scenarios, the display driver will
start link training with max lanes, and if that fails, the driver
falls back to x2 lanes; and repeats this procedure for all
bandwidth/lane configurations.

* Since link training is done before modeset only the port
  (and not pipe/planes) and its associated PLLs are enabled.
* On DP hotplug: Directly start link training on the DP encoder.
* On Connected boot scenarios: When booted with an LFP and a DP,
  sometimes BIOS brings up DP. In these cases, we disable the
  crtc and then do upfront link training; and bring it back up.
* All local changes made for upfront link training are reset
  to their previous values once it is done; so that the
  subsequent modeset is not aware of these changes.

Changes since v7:
* Move the upfront link training to intel_dp_mode_valid()
  to avoid a race condition with DP MST sideband comms. (Ville)
Changes since v6:
* Fix some initialization bugs on link_rate (Jim Bride)
* Use link_rate (and not link_bw) for upfront (Ville)
* Make intel_dp_upfront*() as a vfunc (Ander)
* The train_set_valid variable in intel_dp was removed due to
  issues in fast link training. So, to indicate the link train
  status, move the channel_eq inside intel_dp.
Changes since v5:
* Moved retry logic in upfront to intel_dp.c so that it
  can be used for all platforms.
Changes since v4:
* Removed usage of crtc_state in upfront link training;
  Hence no need to find free crtc to do upfront now.
* Re-enable crtc if it was disabled for upfront.
* Use separate variables to track max lane count
  and link rate found by upfront, without modifying
  the original DPCD read from panel.
Changes since v3:
* Fixed a return value on BXT check
* Reworked on top of bxt_ddi_pll_select split from Ander
* Renamed from ddi_upfront to bxt_upfront since the
  upfront logic includes BXT specific functions for now.
Changes since v2:
* Rebased on top of latest dpll_mgr.c code and
  latest HPD related clean ups.
* Corrected return values from upfront (Ander)
* Corrected atomic locking for upfront in intel_dp.c (Ville)
Changes since v1:
*  all pll related functions inside ddi.c

Signed-off-by: Durgadoss R 
Signed-off-by: Jim Bride 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_ddi.c  |  47 
 drivers/gpu/drm/i915/intel_dp.c   | 370 +++---
 drivers/gpu/drm/i915/intel_dp_link_training.c |   7 +-
 drivers/gpu/drm/i915/intel_drv.h  |  16 ++
 4 files changed, 337 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index dfb3fb6..3921230 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2378,6 +2378,53 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port 
*intel_dig_port)
return connector;
 }
 
+
+bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
+ int clock, uint8_t lane_count,
+ bool link_mst)
+{
+   struct intel_connector *connector = intel_dp->attached_connector;
+   struct intel_encoder *encoder = connector->encoder;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_shared_dpll *pll;
+   struct intel_shared_dpll_config tmp_pll_config;
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   enum intel_dpll_id dpll_id = (enum intel_dpll_id)dig_port->port;
+
+   /*
+* FIXME: Works only for BXT.
+* Select the required PLL. This works for platforms where
+* there is no shared DPLL.
+*/
+   pll = _priv->shared_dplls[dpll_id];
+   if (WARN_ON(pll->active_mask)) {
+   DRM_ERROR("Shared DPLL already in use. active_mask:%x\n", 
pll->active_mask);
+   return false;
+   }
+
+   tmp_pll_config = pll->config;
+
+   if (!bxt_ddi_dp_set_dpll_hw_state(clock, >config.hw_state)) {
+   DRM_ERROR("Could not setup DPLL\n");
+   pll->config = tmp_pll_config;
+   return false;
+   }
+
+   /* Enable PLL followed by port */
+   pll->funcs.enable(dev_priv, pll);
+   intel_ddi_pre_enable_dp(encoder, clock, lane_count, pll, link_mst);
+
+   DRM_DEBUG_KMS("Upfront link train %s: link_clock:%d lanes:%d\n",
+   intel_dp->channel_eq_status ? "Passed" : "Failed", clock, lane_count);
+
+   /* Disable port followed by PLL for next retry/clean up */
+   intel_ddi_post_disable(encoder);
+   pll->funcs.disable(dev_priv, pll);
+
+   

[Intel-gfx] [PATCH v2 3/9] drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions

[Manasi Navare]

From: Ander Conselvan de Oliveira 

Split intel_ddi_pre_enable() into encoder type specific versions that
don't depend on crtc_state. The necessary parameters are passed as
function arguments. This split will be necessary for implementing DP
upfront link training.

v2:
* Rebased onto kernel v4.7 (Jim)

Reviewed-by: Durgadoss R 
Signed-off-by: Ander Conselvan de Oliveira 

Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/intel_ddi.c | 96 +++-
 1 file changed, 55 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8c87d21..dfb3fb6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1634,59 +1634,73 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
}
 }
 
-static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
+static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
+   int link_rate, uint32_t lane_count,
+   struct intel_shared_dpll *pll,
+   bool link_mst)
 {
-   struct drm_encoder *encoder = _encoder->base;
-   struct drm_i915_private *dev_priv = to_i915(encoder->dev);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
-   enum port port = intel_ddi_get_encoder_port(intel_encoder);
-   int type = intel_encoder->type;
-
-   if (type == INTEL_OUTPUT_HDMI) {
-   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+   struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = intel_ddi_get_encoder_port(encoder);
 
-   intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
-   }
+   intel_dp_set_link_params(intel_dp, link_rate, lane_count,
+link_mst);
 
-   if (type == INTEL_OUTPUT_EDP) {
-   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   if (encoder->type == INTEL_OUTPUT_EDP)
intel_edp_panel_on(intel_dp);
-   }
-
-   intel_ddi_clk_select(intel_encoder, crtc->config->shared_dpll);
 
-   if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
-   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   intel_ddi_clk_select(encoder, pll);
+   intel_prepare_dp_ddi_buffers(encoder);
+   intel_ddi_init_dp_buf_reg(encoder);
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   intel_dp_start_link_train(intel_dp);
+   if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
+   intel_dp_stop_link_train(intel_dp);
+}
 
-   intel_prepare_dp_ddi_buffers(intel_encoder);
+static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
+ bool has_hdmi_sink,
+ struct drm_display_mode *adjusted_mode,
+ struct intel_shared_dpll *pll)
+{
+   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(>base);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct drm_encoder *drm_encoder = >base;
+   enum port port = intel_ddi_get_encoder_port(encoder);
+   int level = intel_ddi_hdmi_level(dev_priv, port);
 
-   intel_dp_set_link_params(intel_dp, crtc->config->port_clock,
-crtc->config->lane_count,
-intel_crtc_has_type(crtc->config,
-
INTEL_OUTPUT_DP_MST));
+   intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
+   intel_ddi_clk_select(encoder, pll);
+   intel_prepare_hdmi_ddi_buffers(encoder);
 
-   intel_ddi_init_dp_buf_reg(intel_encoder);
+   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+   skl_ddi_set_iboost(encoder, level);
+   else if (IS_BROXTON(dev_priv))
+   bxt_ddi_vswing_sequence(dev_priv, level, port,
+   INTEL_OUTPUT_HDMI);
 
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
-   intel_dp_start_link_train(intel_dp);
-   if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
-   intel_dp_stop_link_train(intel_dp);
-   } else if (type == INTEL_OUTPUT_HDMI) {
-   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-   int level = intel_ddi_hdmi_level(dev_priv, port);
+   intel_hdmi->set_infoframes(drm_encoder, has_hdmi_sink, adjusted_mode);
+}
 
-   intel_prepare_hdmi_ddi_buffers(intel_encoder);
+static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
+{
+   struct drm_encoder *encoder 

[Intel-gfx] [PATCH v2 2/9] drm/i915: Remove ddi_pll_sel from intel_crtc_state

[Manasi Navare]

From: Ander Conselvan de Oliveira 

The value of ddi_pll_sel is derived from the selection of shared dpll,
so just calculate the final value when necessary.

v2: Actually remove it from crtc state and delete remaining usages. (CI)

Reviewed-by: Durgadoss R 
Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c  | 45 ++-
 drivers/gpu/drm/i915/intel_display.c  | 43 +++--
 drivers/gpu/drm/i915/intel_dp_mst.c   |  3 ++-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 27 -
 drivers/gpu/drm/i915/intel_drv.h  |  8 +--
 5 files changed, 45 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 530ee9f..8c87d21 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -546,6 +546,27 @@ static void intel_wait_ddi_buf_idle(struct 
drm_i915_private *dev_priv,
DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 }
 
+static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
+{
+   switch (pll->id) {
+   case DPLL_ID_WRPLL1:
+   return PORT_CLK_SEL_WRPLL1;
+   case DPLL_ID_WRPLL2:
+   return PORT_CLK_SEL_WRPLL2;
+   case DPLL_ID_SPLL:
+   return PORT_CLK_SEL_SPLL;
+   case DPLL_ID_LCPLL_810:
+   return PORT_CLK_SEL_LCPLL_810;
+   case DPLL_ID_LCPLL_1350:
+   return PORT_CLK_SEL_LCPLL_1350;
+   case DPLL_ID_LCPLL_2700:
+   return PORT_CLK_SEL_LCPLL_2700;
+   default:
+   MISSING_CASE(pll->id);
+   return PORT_CLK_SEL_NONE;
+   }
+}
+
 /* Starting with Haswell, different DDI ports can work in FDI mode for
  * connection to the PCH-located connectors. For this, it is necessary to train
  * both the DDI port and PCH receiver for the desired DDI buffer settings.
@@ -561,7 +582,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
-   u32 temp, i, rx_ctl_val;
+   u32 temp, i, rx_ctl_val, ddi_pll_sel;
 
for_each_encoder_on_crtc(dev, crtc, encoder) {
WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
@@ -592,8 +613,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 
/* Configure Port Clock Select */
-   I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
-   WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
+   ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);
+   I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
+   WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
 
/* Start the training iterating through available voltages and emphasis,
 * testing each value twice. */
@@ -870,7 +892,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
int link_clock = 0;
uint32_t dpll_ctl1, dpll;
 
-   dpll = pipe_config->ddi_pll_sel;
+   dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
 
dpll_ctl1 = I915_READ(DPLL_CTRL1);
 
@@ -918,7 +940,7 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
int link_clock = 0;
u32 val, pll;
 
-   val = pipe_config->ddi_pll_sel;
+   val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
switch (val & PORT_CLK_SEL_MASK) {
case PORT_CLK_SEL_LCPLL_810:
link_clock = 81000;
@@ -1586,13 +1608,15 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 }
 
 void intel_ddi_clk_select(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config)
+ struct intel_shared_dpll *pll)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = intel_ddi_get_encoder_port(encoder);
 
+   if (WARN_ON(!pll))
+   return;
+
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
-   uint32_t dpll = pipe_config->ddi_pll_sel;
uint32_t val;
 
/* DDI -> PLL mapping  */
@@ -1600,14 +1624,13 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
 
val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-   val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
+   val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
 
I915_WRITE(DPLL_CTRL2, val);
 
} else if (INTEL_INFO(dev_priv)->gen < 9) {
-   WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
-   

[Intel-gfx] [PATCH 8/9] drm/i915: Split hsw_get_dpll()

[Manasi Navare]

Split out the DisplayPort and HDMI pll setup code into separate
functions and refactor the DP code that calculates the pll
so that it doesn't depend on crtc state.
This will be used for acquiring port pll when doing
upfront link training.

Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 90 ++-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  6 +++
 2 files changed, 63 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e5c025e..93f7aae 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -705,11 +705,65 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
 }
 
+static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,
+  struct intel_crtc *crtc,
+  struct intel_crtc_state 
*crtc_state)
+{
+   struct intel_shared_dpll *pll;
+   uint32_t val;
+   unsigned p, n2, r2;
+
+   hsw_ddi_calculate_wrpll(clock * 1000, , , );
+
+   val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
+ WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+ WRPLL_DIVIDER_POST(p);
+
+   crtc_state->dpll_hw_state.wrpll = val;
+
+   pll = intel_find_shared_dpll(crtc, crtc_state,
+DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
+
+   if (!pll)
+   return NULL;
+
+   return pll;
+}
+
+struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder *encoder,
+ int clock)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_shared_dpll *pll;
+   enum intel_dpll_id pll_id;
+
+   switch (clock / 2) {
+   case 81000:
+   pll_id = DPLL_ID_LCPLL_810;
+   break;
+   case 135000:
+   pll_id = DPLL_ID_LCPLL_1350;
+   break;
+   case 27:
+   pll_id = DPLL_ID_LCPLL_2700;
+   break;
+   default:
+   DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
+   return NULL;
+   }
+
+   pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+
+   if (!pll)
+   return NULL;
+
+   return pll;
+}
+
 static struct intel_shared_dpll *
 hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 struct intel_encoder *encoder)
 {
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
int clock = crtc_state->port_clock;
 
@@ -717,41 +771,12 @@ hsw_get_dpll(struct intel_crtc *crtc, struct 
intel_crtc_state *crtc_state,
   sizeof(crtc_state->dpll_hw_state));
 
if (encoder->type == INTEL_OUTPUT_HDMI) {
-   uint32_t val;
-   unsigned p, n2, r2;
-
-   hsw_ddi_calculate_wrpll(clock * 1000, , , );
-
-   val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
- WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
- WRPLL_DIVIDER_POST(p);
-
-   crtc_state->dpll_hw_state.wrpll = val;
-
-   pll = intel_find_shared_dpll(crtc, crtc_state,
-DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
+   pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state);
 
} else if (encoder->type == INTEL_OUTPUT_DP ||
   encoder->type == INTEL_OUTPUT_DP_MST ||
   encoder->type == INTEL_OUTPUT_EDP) {
-   enum intel_dpll_id pll_id;
-
-   switch (clock / 2) {
-   case 81000:
-   pll_id = DPLL_ID_LCPLL_810;
-   break;
-   case 135000:
-   pll_id = DPLL_ID_LCPLL_1350;
-   break;
-   case 27:
-   pll_id = DPLL_ID_LCPLL_2700;
-   break;
-   default:
-   DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
-   return NULL;
-   }
-
-   pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+   pll = hsw_ddi_dp_get_dpll(encoder, clock);
 
} else if (encoder->type == INTEL_OUTPUT_ANALOG) {
if (WARN_ON(crtc_state->port_clock / 2 != 135000))
@@ -774,7 +799,6 @@ hsw_get_dpll(struct intel_crtc *crtc, struct 
intel_crtc_state *crtc_state,
return pll;
 }
 
-
 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index ec0fe66..f438535 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ 

[Intel-gfx] [PATCH 1/9] drm/i915: Don't pass crtc_state to intel_dp_set_link_params()

[Manasi Navare]

From: Ander Conselvan de Oliveira 

Decouple intel_dp_set_link_params() from struct intel_crtc_state. This
will be useful for implementing DP upfront link training.

Reviewed-by: Durgadoss R 
Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c|  5 -
 drivers/gpu/drm/i915/intel_dp.c | 14 +-
 drivers/gpu/drm/i915/intel_dp_mst.c |  6 --
 drivers/gpu/drm/i915/intel_drv.h|  3 ++-
 4 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c2df4e4..530ee9f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1637,7 +1637,10 @@ static void intel_ddi_pre_enable(struct intel_encoder 
*intel_encoder)
 
intel_prepare_dp_ddi_buffers(intel_encoder);
 
-   intel_dp_set_link_params(intel_dp, crtc->config);
+   intel_dp_set_link_params(intel_dp, crtc->config->port_clock,
+crtc->config->lane_count,
+intel_crtc_has_type(crtc->config,
+
INTEL_OUTPUT_DP_MST));
 
intel_ddi_init_dp_buf_reg(intel_encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8fe2afa..39d5be5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1647,11 +1647,12 @@ found:
 }
 
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config)
+ int link_rate, uint8_t lane_count,
+ bool link_mst)
 {
-   intel_dp->link_rate = pipe_config->port_clock;
-   intel_dp->lane_count = pipe_config->lane_count;
-   intel_dp->link_mst = intel_crtc_has_type(pipe_config, 
INTEL_OUTPUT_DP_MST);
+   intel_dp->link_rate = link_rate;
+   intel_dp->lane_count = lane_count;
+   intel_dp->link_mst = link_mst;
 }
 
 static void intel_dp_prepare(struct intel_encoder *encoder)
@@ -1663,7 +1664,10 @@ static void intel_dp_prepare(struct intel_encoder 
*encoder)
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
const struct drm_display_mode *adjusted_mode = 
>config->base.adjusted_mode;
 
-   intel_dp_set_link_params(intel_dp, crtc->config);
+   intel_dp_set_link_params(intel_dp, crtc->config->port_clock,
+crtc->config->lane_count,
+intel_crtc_has_type(crtc->config,
+INTEL_OUTPUT_DP_MST));
 
/*
 * There are four kinds of DP registers:
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 629337d..e654fea 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder)
intel_ddi_clk_select(_dig_port->base, intel_crtc->config);
 
intel_prepare_dp_ddi_buffers(_dig_port->base);
-
-   intel_dp_set_link_params(intel_dp, intel_crtc->config);
+   intel_dp_set_link_params(intel_dp,
+intel_crtc->config->port_clock,
+intel_crtc->config->lane_count,
+true);
 
intel_ddi_init_dp_buf_reg(_dig_port->base);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c29a429..86d243e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1342,7 +1342,8 @@ bool intel_dp_init(struct drm_device *dev, i915_reg_t 
output_reg, enum port port
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 struct intel_connector *intel_connector);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config);
+ int link_rate, uint8_t lane_count,
+ bool link_mst);
 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 0/9] Enable upfront link training on DDI platforms

[Manasi Navare]

This patch series enables upfront link training on DDI platforms
(SKL/BDW/HSW/BXT). They are based on some of the patches submitted
earlier by Ander and Durgadoss.

The upfront link training had to be factored out of long pulse
hanlder because of deadlock issues seen on DP MST cases.
Now the upfront link training takes place in intel_dp_mode_valid()
to find the maximum lane count and link rate at which the DP link
can be successfully trained. These values are used to prune the
invalid modes before modeset. Modeset makes use the upfront lane
count and link train values.

These patches have been validated for DP SST on DDI platforms
(SKL/HSW/BDW/BXT). They have also been tested for any regressions
on non DDI platforms (CHV).

Ander Conselvan de Oliveira (3):
  drm/i915: Don't pass crtc_state to intel_dp_set_link_params()
  drm/i915: Remove ddi_pll_sel from intel_crtc_state
  drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions

Durgadoss R (2):
  drm/i915: Split bxt_ddi_pll_select()
  drm/i915/dp: Enable Upfront link training for typeC DP support on BXT

Jim Bride (2):
  drm/i915: Split skl_get_dpll()
  drm/i915/dp: Enable upfront link training on SKL

Manasi Navare (2):
  drm/i915: Split hsw_get_dpll()
  drm/i915: Enable upfront link training support for HSW/BDW

 drivers/gpu/drm/i915/intel_ddi.c  | 207 +---
 drivers/gpu/drm/i915/intel_display.c  |  43 +--
 drivers/gpu/drm/i915/intel_dp.c   | 386 --
 drivers/gpu/drm/i915/intel_dp_link_training.c |   7 +-
 drivers/gpu/drm/i915/intel_dp_mst.c   |   9 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 457 --
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  15 +
 drivers/gpu/drm/i915/intel_drv.h  |  29 +-
 8 files changed, 776 insertions(+), 377 deletions(-)

-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 05/21] drm/i915: Get rid of HAS_CORE_RING_FREQ

[Chris Wilson]

On Tue, Aug 09, 2016 at 11:45:11AM -0700, Carlos Santa wrote:
> No need for HAS_CORE_RING_FREQ as that flag is actually the same as
> .has_llc. Feedback from V. Syrjala.
> 
> Signed-off-by: Carlos Santa 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
>  drivers/gpu/drm/i915/i915_drv.h | 4 
>  2 files changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9bd4158..01b6735 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1898,11 +1898,12 @@ static int i915_ring_freq_table(struct seq_file *m, 
> void *unused)
>   struct drm_info_node *node = m->private;
>   struct drm_device *dev = node->minor->dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_device_info *info = mkwrite_device_info(dev_priv);
>   int ret = 0;
>   int gpu_freq, ia_freq;
>   unsigned int max_gpu_freq, min_gpu_freq;
>  
> - if (!HAS_CORE_RING_FREQ(dev)) {
> + if (!info->has_llc) {

Why do you need write access?

if (INTEL_INFO(dev_priv)->has_llc)

or even if (HAS_LLC(dev_priv).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 3/6] drm/i915/lvds: Restore initial HW state during encoder enabling

[Imre Deak]

Atm the LVDS encoder depends on the PPS HW context being saved/restored
from generic suspend/resume code. Since the PPS is specific to the LVDS
and eDP encoders a cleaner way is to reinitialize it during encoder
enabling, so do this here for LVDS. Follow-up patches will init the PPS
for the eDP encoder similarly and remove the suspend/resume time save /
restore.

v2:
- Apply BSpec +1 offset and use DIV_ROUND_UP() when programming the
power cycle delay. (Ville)
v3: (Ville)
- Fix +1 vs. round-up order.
- s/reset_on_powerdown/powerdown_on_reset/

Signed-off-by: Imre Deak 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h   |   1 +
 drivers/gpu/drm/i915/intel_lvds.c | 114 +-
 2 files changed, 102 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 889508f..da82744 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3710,6 +3710,7 @@ enum {
 
 #define _PP_ON_DELAYS  0x61208
 #define PP_ON_DELAYS(pps_idx)  _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
+#define  PANEL_PORT_SELECT_SHIFT   30
 #define  PANEL_PORT_SELECT_MASK(3 << 30)
 #define  PANEL_PORT_SELECT_LVDS(0 << 30)
 #define  PANEL_PORT_SELECT_DPA (1 << 30)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
b/drivers/gpu/drm/i915/intel_lvds.c
index c5739fc..e79fae4 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -48,6 +48,20 @@ struct intel_lvds_connector {
struct notifier_block lid_notifier;
 };
 
+struct intel_lvds_pps {
+   /* 100us units */
+   int t1_t2;
+   int t3;
+   int t4;
+   int t5;
+   int tx;
+
+   int divider;
+
+   int port;
+   bool powerdown_on_reset;
+};
+
 struct intel_lvds_encoder {
struct intel_encoder base;
 
@@ -55,6 +69,9 @@ struct intel_lvds_encoder {
i915_reg_t reg;
u32 a3_power;
 
+   struct intel_lvds_pps init_pps;
+   u32 init_lvds_val;
+
struct intel_lvds_connector *attached_connector;
 };
 
@@ -136,6 +153,83 @@ static void intel_lvds_get_config(struct intel_encoder 
*encoder,
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
+static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
+   struct intel_lvds_pps *pps)
+{
+   u32 val;
+
+   pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
+
+   val = I915_READ(PP_ON_DELAYS(0));
+   pps->port = (val & PANEL_PORT_SELECT_MASK) >>
+   PANEL_PORT_SELECT_SHIFT;
+   pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
+PANEL_POWER_UP_DELAY_SHIFT;
+   pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
+ PANEL_LIGHT_ON_DELAY_SHIFT;
+
+   val = I915_READ(PP_OFF_DELAYS(0));
+   pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
+ PANEL_POWER_DOWN_DELAY_SHIFT;
+   pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
+ PANEL_LIGHT_OFF_DELAY_SHIFT;
+
+   val = I915_READ(PP_DIVISOR(0));
+   pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
+  PP_REFERENCE_DIVIDER_SHIFT;
+   val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
+ PANEL_POWER_CYCLE_DELAY_SHIFT;
+   /*
+* Remove the BSpec specified +1 (100ms) offset that accounts for a
+* too short power-cycle delay due to the asynchronous programming of
+* the register.
+*/
+   if (val)
+   val--;
+   /* Convert from 100ms to 100us units */
+   pps->t4 = val * 1000;
+
+   if (INTEL_INFO(dev_priv)->gen <= 4 &&
+   pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
+   DRM_DEBUG_KMS("Panel power timings uninitialized, "
+ "setting defaults\n");
+   /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
+   pps->t1_t2 = 40 * 10;
+   pps->t5 = 200 * 10;
+   /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
+   pps->t3 = 35 * 10;
+   pps->tx = 200 * 10;
+   }
+
+   DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
+"divider %d port %d powerdown_on_reset %d\n",
+pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
+pps->divider, pps->port, pps->powerdown_on_reset);
+}
+
+static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
+  struct intel_lvds_pps *pps)
+{
+   u32 val;
+
+   val = I915_READ(PP_CONTROL(0));
+   WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
+   if (pps->powerdown_on_reset)
+   val |= PANEL_POWER_RESET;
+   I915_WRITE(PP_CONTROL(0), val);

[Intel-gfx] [PATCH v3 5/6] drm/i915: Apply the PPS register unlock workaround more consistently

[Imre Deak]

Atm, we apply this workaround somewhat inconsistently at the following
points: driver loading, LVDS init, eDP PPS init, system resume. As this
workaround also affects registers other than PPS (timing, PLL) a more
consistent way is to apply it early after the PPS HW context is known to
be lost: driver loading, system resume and on VLV/CHV/BXT when turning
on power domains.

This is needed by the next patch that removes saving/restoring of the
PP_CONTROL register.

This also removes the incorrect programming of the workaround on HSW+
PCH platforms which don't have the register locking mechanism.

v2: (Ville)
- Don't apply the workaround on BXT.
- Simplify platform checks using HAS_DDI().
v3:
- Move the call of intel_pps_unlock_regs_wa() to the more
  logical vlv_display_power_well_init() (also fixing CHV) (Ville).

Signed-off-by: Imre Deak 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.c |  1 +
 drivers/gpu/drm/i915/intel_display.c| 26 ++
 drivers/gpu/drm/i915/intel_dp.c |  3 ++-
 drivers/gpu/drm/i915/intel_drv.h|  1 +
 drivers/gpu/drm/i915/intel_lvds.c   |  8 
 drivers/gpu/drm/i915/intel_runtime_pm.c |  4 
 6 files changed, 34 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8cfc264..0fcd1c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1560,6 +1560,7 @@ static int i915_drm_resume(struct drm_device *dev)
i915_gem_resume(dev);
 
i915_restore_state(dev);
+   intel_pps_unlock_regs_wa(dev_priv);
intel_opregion_setup(dev_priv);
 
intel_init_pch_refclk(dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3d5fd06..bcbf277 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14635,6 +14635,30 @@ static bool intel_crt_present(struct drm_device *dev)
return true;
 }
 
+void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
+{
+   int pps_num;
+   int pps_idx;
+
+   if (HAS_DDI(dev_priv))
+   return;
+   /*
+* This w/a is needed at least on CPT/PPT, but to be sure apply it
+* everywhere where registers can be write protected.
+*/
+   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+   pps_num = 2;
+   else
+   pps_num = 1;
+
+   for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
+   u32 val = I915_READ(PP_CONTROL(pps_idx));
+
+   val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
+   I915_WRITE(PP_CONTROL(pps_idx), val);
+   }
+}
+
 static void intel_pps_init(struct drm_i915_private *dev_priv)
 {
if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
@@ -14643,6 +14667,8 @@ static void intel_pps_init(struct drm_i915_private 
*dev_priv)
dev_priv->pps_mmio_base = VLV_PPS_BASE;
else
dev_priv->pps_mmio_base = PPS_BASE;
+
+   intel_pps_unlock_regs_wa(dev_priv);
 }
 
 static void intel_setup_outputs(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2ef7b14..3d3d3fb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1829,7 +1829,8 @@ static  u32 ironlake_get_pp_control(struct intel_dp 
*intel_dp)
lockdep_assert_held(_priv->pps_mutex);
 
control = I915_READ(_pp_ctrl_reg(intel_dp));
-   if (!IS_BROXTON(dev)) {
+   if (WARN_ON(!HAS_DDI(dev_priv) &&
+(control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
control &= ~PANEL_UNLOCK_MASK;
control |= PANEL_UNLOCK_REGS;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c29a429..cbce786 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1159,6 +1159,7 @@ void intel_mark_busy(struct drm_i915_private *dev_priv);
 void intel_mark_idle(struct drm_i915_private *dev_priv);
 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 int intel_display_suspend(struct drm_device *dev);
+void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 int intel_connector_init(struct intel_connector *);
 struct intel_connector *intel_connector_alloc(void);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
b/drivers/gpu/drm/i915/intel_lvds.c
index e79fae4..668eabb 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -978,14 +978,6 @@ void intel_lvds_init(struct drm_device *dev)
int pipe;
u8 pin;
 
-   /*
-* Unlock registers and just leave them unlocked. Do this before
-* checking quirk lists to avoid bogus WARNINGs.
-*/
-   if 

[Intel-gfx] [PATCH v3 09/21] drm/i915: Move HAS_RC6p definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bc6df5b..611771b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -775,6 +775,7 @@ struct intel_csr {
func(has_csr) sep \
func(has_resource_streamer) sep \
func(has_rc6) sep \
+   func(has_rc6p) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2775,7 +2776,7 @@ struct drm_i915_cmd_table {
 #define HAS_PSR(dev)   (INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)(INTEL_INFO(dev)->has_runtime_pm)
 #define HAS_RC6(dev)   (INTEL_INFO(dev)->has_rc6)
-#define HAS_RC6p(dev)  (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_RC6p(dev)  (INTEL_INFO(dev)->has_rc6p)
 
 #define HAS_CSR(dev)   (INTEL_INFO(dev)->has_csr)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 42108dc..ce78a18 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -202,6 +202,7 @@ static const struct intel_device_info intel_ironlake_m_info 
= {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
.has_rc6 = 1, \
+   .has_rc6p = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
@@ -221,6 +222,7 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
.has_rc6 = 1, \
+   .has_rc6p = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
@@ -264,6 +266,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
.has_fpga_dbg = 1, \
.has_psr = 1, \
.has_resource_streamer = 1, \
+   .has_rc6p = 0 /*RC6p excludes HSW*/, \
.has_runtime_pm = 1
 
 static const struct intel_device_info intel_haswell_info = {
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 17/21] drm/i915: Move HAS_LOGICAL_RING_CONTEXTS definition to platform

[Carlos Santa]

Moving all GPU features to the platform definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 -
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 919ae65..18c9fc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -779,6 +779,7 @@ struct intel_csr {
func(has_dp_mst) sep \
func(has_gmbus_irq) sep \
func(has_hw_contexts) sep \
+   func(has_logical_ring_contexts) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2731,7 +2732,7 @@ struct drm_i915_cmd_table {
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->has_hw_contexts)
-#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
+#define HAS_LOGICAL_RING_CONTEXTS(dev) 
(INTEL_INFO(dev)->has_logical_ring_contexts)
 #define USES_PPGTT(dev)(i915.enable_ppgtt)
 #define USES_FULL_PPGTT(dev)   (i915.enable_ppgtt >= 2)
 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9d42b68..db15fc2 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -276,7 +276,8 @@ static const struct intel_device_info intel_haswell_info = {
 
 #define BDW_FEATURES \
HSW_FEATURES, \
-   BDW_COLORS
+   BDW_COLORS, \
+   .has_logical_ring_contexts = 1
 
 static const struct intel_device_info intel_broadwell_info = {
BDW_FEATURES,
@@ -302,6 +303,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.has_rc6 = 1,
.has_gmbus_irq = 1,
.has_hw_contexts = 1,
+   .has_logical_ring_contexts = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -340,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_dp_mst = 1,
.has_gmbus_irq = 1,
.has_hw_contexts = 1,
+   .has_logical_ring_contexts = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 16/21] drm/i915: Move HAS_HW_CONTEXTS definition to platform

[Carlos Santa]

Moving all GPU features to the platform definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 729a91b..919ae65 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -778,6 +778,7 @@ struct intel_csr {
func(has_rc6p) sep \
func(has_dp_mst) sep \
func(has_gmbus_irq) sep \
+   func(has_hw_contexts) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2729,7 +2730,7 @@ struct drm_i915_cmd_table {
 HAS_EDRAM(dev))
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
-#define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->gen >= 6)
+#define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->has_hw_contexts)
 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
 #define USES_PPGTT(dev)(i915.enable_ppgtt)
 #define USES_FULL_PPGTT(dev)   (i915.enable_ppgtt >= 2)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3cd0d8f..9d42b68 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -196,6 +196,7 @@ static const struct intel_device_info intel_ironlake_m_info 
= {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+   .has_hw_contexts = 1, \
.has_gmbus_irq = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -218,6 +219,7 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.has_gmbus_irq = 1, \
+   .has_hw_contexts = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
@@ -244,6 +246,7 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
.has_runtime_pm = 1, \
.has_rc6 = 1, \
.has_gmbus_irq = 1, \
+   .has_hw_contexts = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -298,6 +301,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.has_resource_streamer = 1,
.has_rc6 = 1,
.has_gmbus_irq = 1,
+   .has_hw_contexts = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -335,6 +339,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_rc6 = 1,
.has_dp_mst = 1,
.has_gmbus_irq = 1,
+   .has_hw_contexts = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 04/21] drm/i915: Move HAS_RUNTIME_PM definition to platform

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Feedback from V. Syrjala: remove runtime PM support for snb as it breaks
hotplug support.

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 6 ++
 drivers/gpu/drm/i915/i915_pci.c | 6 +-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f2f066..0eaf28f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -771,6 +771,7 @@ struct intel_csr {
func(is_preliminary) sep \
func(has_fbc) sep \
func(has_psr) sep \
+   func(has_runtime_pm) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2769,10 +2770,7 @@ struct drm_i915_cmd_table {
 #define HAS_DDI(dev)   (INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)   (INTEL_INFO(dev)->has_psr)
-#define HAS_RUNTIME_PM(dev)(IS_GEN6(dev) || IS_HASWELL(dev) || \
-IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
-IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
-IS_KABYLAKE(dev) || IS_BROXTON(dev))
+#define HAS_RUNTIME_PM(dev)(INTEL_INFO(dev)->has_runtime_pm)
 #define HAS_RC6(dev)   (INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)  (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bdc2071..9d78836 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -242,6 +242,7 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
 #define VLV_FEATURES  \
.gen = 7, .num_pipes = 2, \
.has_psr = 1, \
+   .has_runtime_pm = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -258,7 +259,8 @@ static const struct intel_device_info intel_valleyview_info 
= {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
.has_ddi = 1, \
.has_fpga_dbg = 1, \
-   .has_psr = 1
+   .has_psr = 1, \
+   .has_runtime_pm = 1
 
 static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES,
@@ -288,6 +290,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.is_cherryview = 1,
.has_psr = 1,
+   .has_runtime_pm = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -316,6 +319,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_ddi = 1,
.has_fpga_dbg = 1,
.has_fbc = 1,
+   .has_runtime_pm = 1,
.has_pooled_eu = 0,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 00/21] drm/i915: Organize most GPU features by platform

[Carlos Santa]

 - organize most GPU features so that they are easy to group by platforms.
   It seems some of the ground work was already done for Gen7 features.

 - make most of these GPU features now a device_info flag also based on
   previous work done by others. The idea is here is to have a central place 
where
   to add new features, now it should also be possible to see what the 
supported 
   features are for a given platform by dumping of the struct definitions.
   The list of the features that were converted to a device_info flag include: 
PSR,
   RUNTIME_PM, CORE_RING_FREQ, CSR, GUC, RESOURCE_STREAMER, RC6,
   RC6p, DP_MST, GMBUS_IRQ, FW_BLC, HW_CONTEXTS, LOGICAL_RING_CONTEXTS, L3_DPF,
   HWS_NEEDS_PHYSICAL and GMCH_DISPLAY.

- Changes since v2, thanks to Rodrigo, Ville, Jani and others for the comments

  - Kill off the approach of inheriting GPU features from platform to platform, 
even though there's some code consolidation there's added complexity when going 
through the code to find out what feature is supported where, specifically for 
features supported across several generations.

- Patch 2: "drm/i915: Remove .is_mobile from platform struct"
  -  Kill off the distintion between desktop vs. mobile for HWS+ and VLV while 
still keeping it for ILK-IVB.

- Patch 4: "drm/i915: Move HAS_RUNTIME_PM definition to platform"
  - Remove runtime PM support for SNB as it breaks hotplut support.

- Patch 5: "drm/i915: Get rid of HAS_CORE_RING_FREQ"
  - No need for this flag anymore as this flag == .has_llc.

- Patch 20: "drm/i915: Make HWS_NEEDS_PHYSICAL the exception"
  - .hws_needs_physical should the exception, invert the logic so now older GPU 
h/w enables that since they are fewer to support. Remove support of 
.need_gfx_hws for newer GPU hardware revisions. 

Carlos Santa (21):
  drm/i915: Move HAS_PSR definition to platform struct definition
  drm/i915: Remove .is_mobile field from platform struct
  drm/i915: Introduce GEN6_FEATURES for device info
  drm/i915: Move HAS_RUNTIME_PM definition to platform
  drm/i915: Get rid of HAS_CORE_RING_FREQ
  drm/i915 Move HAS_CSR definition to platform definition
  drm/i915: Move HAS_RESOURCE_STREAMER definition to platform definition
  drm/i915: Move HAS_RC6 definition to platform definition
  drm/i915: Move HAS_RC6p definition to platform definition
  drm/i915: Move HAS_DP_MST definition to platform definition
  drm/i915: Introduce GEN5_FEATURES for device info
  drm/i915: Move HAS_GMBUS_IRQ definition to platform definition
  drm/i915: Introduce GEN4_FEATURES for device info
  drm/i915: Introduce GEN3_FEATURES for device info
  drm/i915: Introduce GEN2_FEATURES for device info
  drm/i915: Move HAS_HW_CONTEXTS definition to platform
  drm/i915: Move HAS_LOGICAL_RING_CONTEXTS definition to platform
  drm/i915: Move HAS_L3_DPF definition to platform definition
  drm/i915: Move HAS_GMCH_DISPLAY definition to platform
  drm/i915: Make HWS_NEEDS_PHYSICAL the exception
  drm/i915: Move HAS_GUC definition to platform definition

 arch/x86/kernel/early-quirks.c  |   9 +-
 drivers/gpu/drm/i915/i915_debugfs.c |   3 +-
 drivers/gpu/drm/i915/i915_drv.h |  57 +++
 drivers/gpu/drm/i915/i915_gpu_error.c   |   2 +-
 drivers/gpu/drm/i915/i915_pci.c | 275 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c |  20 +--
 include/drm/i915_pciids.h   |  38 ++---
 7 files changed, 207 insertions(+), 197 deletions(-)

-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 13/21] drm/i915: Introduce GEN4_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben W.

Use it for i965g, i965gm, g45 and gm45.

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_pci.c | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 59c958a4..356f16d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -123,23 +123,25 @@ static const struct intel_device_info intel_i945gm_info = 
{
CURSOR_OFFSETS,
 };
 
+#define GEN4_FEATURES \
+   .gen = 4, .num_pipes = 2, \
+   .has_hotplug = 1, \
+   .ring_mask = RENDER_RING, \
+   GEN_DEFAULT_PIPEOFFSETS, \
+   CURSOR_OFFSETS
+
 static const struct intel_device_info intel_i965g_info = {
-   .gen = 4, .is_broadwater = 1, .num_pipes = 2,
-   .has_hotplug = 1,
+   GEN4_FEATURES,
+   .is_broadwater = 1,
.has_overlay = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
-   .gen = 4, .is_crestline = 1, .num_pipes = 2,
-   .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
+   GEN4_FEATURES,
+   .is_crestline = 1,
+   .is_mobile = 1, .has_fbc = 1,
.has_overlay = 1,
.supports_tv = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_g33_info = {
@@ -152,21 +154,19 @@ static const struct intel_device_info intel_g33_info = {
 };
 
 static const struct intel_device_info intel_g45_info = {
-   .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
-   .has_pipe_cxsr = 1, .has_hotplug = 1,
+   GEN4_FEATURES,
+   .is_g4x = 1, .need_gfx_hws = 1,
+   .has_pipe_cxsr = 1,
.ring_mask = RENDER_RING | BSD_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_gm45_info = {
-   .gen = 4, .is_g4x = 1, .num_pipes = 2,
+   GEN4_FEATURES,
+   .is_g4x = 1,
.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
-   .has_pipe_cxsr = 1, .has_hotplug = 1,
+   .has_pipe_cxsr = 1,
.supports_tv = 1,
.ring_mask = RENDER_RING | BSD_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_pineview_info = {
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 10/21] drm/i915: Move HAS_DP_MST definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 611771b..c4621ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -776,6 +776,7 @@ struct intel_csr {
func(has_resource_streamer) sep \
func(has_rc6) sep \
func(has_rc6p) sep \
+   func(has_dp_mst) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2768,8 +2769,7 @@ struct drm_i915_cmd_table {
 
 #define HAS_IPS(dev)   (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
 
-#define HAS_DP_MST(dev)(IS_HASWELL(dev) || IS_BROADWELL(dev) 
|| \
-INTEL_INFO(dev)->gen >= 9)
+#define HAS_DP_MST(dev)(INTEL_INFO(dev)->has_dp_mst)
 
 #define HAS_DDI(dev)   (INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ce78a18..ba0f5c8f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -266,6 +266,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
.has_fpga_dbg = 1, \
.has_psr = 1, \
.has_resource_streamer = 1, \
+   .has_dp_mst = 1, \
.has_rc6p = 0 /*RC6p excludes HSW*/, \
.has_runtime_pm = 1
 
@@ -335,6 +336,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_csr = 1,
.has_resource_streamer = 1,
.has_rc6 = 1,
+   .has_dp_mst = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 11/21] drm/i915: Introduce GEN5_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben w.

Use it for ilk.

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_pci.c | 21 ++---
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ba0f5c8f..8a50e45 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -178,21 +178,20 @@ static const struct intel_device_info intel_pineview_info 
= {
CURSOR_OFFSETS,
 };
 
+#define GEN5_FEATURES \
+   .gen = 5, .num_pipes = 2, \
+   .need_gfx_hws = 1, .has_hotplug = 1, \
+   .ring_mask = RENDER_RING | BSD_RING, \
+   GEN_DEFAULT_PIPEOFFSETS, \
+   CURSOR_OFFSETS
+
 static const struct intel_device_info intel_ironlake_d_info = {
-   .gen = 5, .num_pipes = 2,
-   .need_gfx_hws = 1, .has_hotplug = 1,
-   .ring_mask = RENDER_RING | BSD_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
+   GEN5_FEATURES,
 };
 
 static const struct intel_device_info intel_ironlake_m_info = {
-   .gen = 5, .is_mobile = 1, .num_pipes = 2,
-   .need_gfx_hws = 1, .has_hotplug = 1,
-   .has_fbc = 1,
-   .ring_mask = RENDER_RING | BSD_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
+   GEN5_FEATURES,
+   .is_mobile = 1,
 };
 
 #define GEN6_FEATURES \
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 14/21] drm/i915: Introduce GEN3_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES from Ben W.

Use it for i915g, i915gm, i945g, i945gm, g33 and pnv.

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_pci.c | 30 ++
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 356f16d..2f65898 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -88,39 +88,37 @@ static const struct intel_device_info intel_i865g_info = {
CURSOR_OFFSETS,
 };
 
+#define GEN3_FEATURES \
+   .gen = 3, .num_pipes = 2, \
+   .ring_mask = RENDER_RING, \
+   GEN_DEFAULT_PIPEOFFSETS, \
+   CURSOR_OFFSETS
+
 static const struct intel_device_info intel_i915g_info = {
-   .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
+   GEN3_FEATURES,
+   .is_i915g = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i915gm_info = {
-   .gen = 3, .is_mobile = 1, .num_pipes = 2,
+   GEN3_FEATURES,
+   .is_mobile = 1,
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
.has_fbc = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945g_info = {
-   .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
+   GEN3_FEATURES,
+   .has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945gm_info = {
-   .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
+   GEN3_FEATURES,
+   .is_i945gm = 1, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
.has_fbc = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 
 #define GEN4_FEATURES \
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 21/21] drm/i915: Move HAS_GUC definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform definition allows for
- standard place when adding new features from new platform
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e0e0fa..497854e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -782,6 +782,7 @@ struct intel_csr {
func(has_logical_ring_contexts) sep \
func(has_l3_dpf) sep \
func(has_gmch_display) sep \
+   func(has_guc) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2790,7 +2791,7 @@ struct drm_i915_cmd_table {
  * command submission once loaded. But these are logically independent
  * properties, so we have separate macros to test them.
  */
-#define HAS_GUC(dev)   (IS_GEN9(dev))
+#define HAS_GUC(dev)   (INTEL_INFO(dev)->has_guc)
 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c5f4078..02a7619 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -331,6 +331,7 @@ static const struct intel_device_info intel_skylake_info = {
.is_skylake = 1,
.gen = 9,
.has_csr = 1,
+   .has_guc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
@@ -338,6 +339,7 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.is_skylake = 1,
.gen = 9,
.has_csr = 1,
+   .has_guc = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -359,6 +361,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_gmbus_irq = 1,
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
+   .has_guc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = 
{
.is_kabylake = 1,
.gen = 9,
.has_csr = 1,
+   .has_guc = 1,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -376,6 +380,7 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
.is_kabylake = 1,
.gen = 9,
.has_csr = 1,
+   .has_guc = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 02/21] drm/i915: Remove .is_mobile field from platform struct

[Carlos Santa]

As recommended by Ville Syrjala removing .is_mobile field from the
platform struct definition for vlv and hsw+ GPUs as there's no need to
make the distinction in later hardware anymore. Keep it for older GPUs
as it is still needed for ilk-ivb.

Signed-off-by: Carlos Santa 
---
 arch/x86/kernel/early-quirks.c  |  9 +++--
 drivers/gpu/drm/i915/i915_pci.c | 45 -
 include/drm/i915_pciids.h   | 38 +-
 3 files changed, 25 insertions(+), 67 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index de7501e..e6bd329 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -512,8 +512,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_I915GM_IDS(_early_ops),
INTEL_I945G_IDS(_early_ops),
INTEL_I945GM_IDS(_early_ops),
-   INTEL_VLV_M_IDS(_early_ops),
-   INTEL_VLV_D_IDS(_early_ops),
+   INTEL_VLV_IDS(_early_ops),
INTEL_PINEVIEW_IDS(_early_ops),
INTEL_I965G_IDS(_early_ops),
INTEL_G33_IDS(_early_ops),
@@ -526,10 +525,8 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_SNB_M_IDS(_early_ops),
INTEL_IVB_M_IDS(_early_ops),
INTEL_IVB_D_IDS(_early_ops),
-   INTEL_HSW_D_IDS(_early_ops),
-   INTEL_HSW_M_IDS(_early_ops),
-   INTEL_BDW_M_IDS(_early_ops),
-   INTEL_BDW_D_IDS(_early_ops),
+   INTEL_HSW_IDS(_early_ops),
+   INTEL_BDW_IDS(_early_ops),
INTEL_CHV_IDS(_early_ops),
INTEL_SKL_IDS(_early_ops),
INTEL_BXT_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e1caa0b..b5ec8a7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,13 +250,7 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
-static const struct intel_device_info intel_valleyview_m_info = {
-   VLV_FEATURES,
-   .is_valleyview = 1,
-   .is_mobile = 1,
-};
-
-static const struct intel_device_info intel_valleyview_d_info = {
+static const struct intel_device_info intel_valleyview_info = {
VLV_FEATURES,
.is_valleyview = 1,
 };
@@ -268,47 +262,28 @@ static const struct intel_device_info 
intel_valleyview_d_info = {
.has_fpga_dbg = 1, \
.has_psr = 1
 
-static const struct intel_device_info intel_haswell_d_info = {
+static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES,
.is_haswell = 1,
 };
 
-static const struct intel_device_info intel_haswell_m_info = {
-   HSW_FEATURES,
-   .is_haswell = 1,
-   .is_mobile = 1,
-};
-
 #define BDW_FEATURES \
HSW_FEATURES, \
BDW_COLORS
 
-static const struct intel_device_info intel_broadwell_d_info = {
+static const struct intel_device_info intel_broadwell_info = {
BDW_FEATURES,
.gen = 8,
.is_broadwell = 1,
 };
 
-static const struct intel_device_info intel_broadwell_m_info = {
-   BDW_FEATURES,
-   .gen = 8, .is_mobile = 1,
-   .is_broadwell = 1,
-};
-
-static const struct intel_device_info intel_broadwell_gt3d_info = {
+static const struct intel_device_info intel_broadwell_gt3_info = {
BDW_FEATURES,
.gen = 8,
.is_broadwell = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-static const struct intel_device_info intel_broadwell_gt3m_info = {
-   BDW_FEATURES,
-   .gen = 8, .is_mobile = 1,
-   .is_broadwell = 1,
-   .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
-};
-
 static const struct intel_device_info intel_cherryview_info = {
.gen = 8, .num_pipes = 3,
.need_gfx_hws = 1, .has_hotplug = 1,
@@ -390,14 +365,10 @@ static const struct pci_device_id pciidlist[] = {
INTEL_IVB_Q_IDS(_ivybridge_q_info), /* must be first IVB */
INTEL_IVB_M_IDS(_ivybridge_m_info),
INTEL_IVB_D_IDS(_ivybridge_d_info),
-   INTEL_HSW_D_IDS(_haswell_d_info),
-   INTEL_HSW_M_IDS(_haswell_m_info),
-   INTEL_VLV_M_IDS(_valleyview_m_info),
-   INTEL_VLV_D_IDS(_valleyview_d_info),
-   INTEL_BDW_GT12M_IDS(_broadwell_m_info),
-   INTEL_BDW_GT12D_IDS(_broadwell_d_info),
-   INTEL_BDW_GT3M_IDS(_broadwell_gt3m_info),
-   INTEL_BDW_GT3D_IDS(_broadwell_gt3d_info),
+   INTEL_HSW_IDS(_haswell_info),
+   INTEL_VLV_IDS(_valleyview_info),
+   INTEL_BDW_GT12_IDS(_broadwell_info),
+   INTEL_BDW_GT3_IDS(_broadwell_gt3_info),
INTEL_CHV_IDS(_cherryview_info),
INTEL_SKL_GT1_IDS(_skylake_info),
INTEL_SKL_GT2_IDS(_skylake_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 33466bf..0d5f426 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -134,7 +134,7 @@
 #define 

[Intel-gfx] [PATCH v3 19/21] drm/i915: Move HAS_GMCH_DISPLAY definition to platform

[Carlos Santa]

Moving all GPU features to the platform definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 drivers/gpu/drm/i915/i915_pci.c | 5 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20c793f..233feb9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -781,6 +781,7 @@ struct intel_csr {
func(has_hw_contexts) sep \
func(has_logical_ring_contexts) sep \
func(has_l3_dpf) sep \
+   func(has_gmch_display) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2821,8 +2822,7 @@ struct drm_i915_cmd_table {
 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
-  IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d219a01..1c2f5fa 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -57,6 +57,7 @@
 #define GEN2_FEATURES \
.gen = 2, \
.has_overlay = 1, .overlay_needs_physical = 1, \
+   .has_gmch_display = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -85,6 +86,7 @@ static const struct intel_device_info intel_i865g_info = {
 
 #define GEN3_FEATURES \
.gen = 3, .num_pipes = 2, \
+   .has_gmch_display = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -119,6 +121,7 @@ static const struct intel_device_info intel_i945gm_info = {
 #define GEN4_FEATURES \
.gen = 4, .num_pipes = 2, \
.has_hotplug = 1, \
+   .has_gmch_display = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -250,6 +253,7 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
.has_rc6 = 1, \
.has_gmbus_irq = 1, \
.has_hw_contexts = 1, \
+   .has_gmch_display = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -308,6 +312,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.has_gmbus_irq = 1,
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
+   .has_gmch_display = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 18/21] drm/i915: Move HAS_L3_DPF definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 4 
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18c9fc5..20c793f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ struct intel_csr {
func(has_gmbus_irq) sep \
func(has_hw_contexts) sep \
func(has_logical_ring_contexts) sep \
+   func(has_l3_dpf) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2824,7 +2825,7 @@ struct drm_i915_cmd_table {
   IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 
 /* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
 
 #define GT_FREQUENCY_MULTIPLIER 50
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index db15fc2..d219a01 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -226,18 +226,21 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
 static const struct intel_device_info intel_ivybridge_d_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
+   .has_l3_dpf = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.is_mobile = 1,
+   .has_l3_dpf = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.num_pipes = 0, /* legal, last one wins */
+   .has_l3_dpf = 1,
 };
 
 #define VLV_FEATURES  \
@@ -272,6 +275,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
 static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES,
.is_haswell = 1,
+   .has_l3_dpf = 1,
 };
 
 #define BDW_FEATURES \
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 01/21] drm/i915: Move HAS_PSR definition to platform struct definition

[Carlos Santa]

[patch series] Moving all GPU features to the platform struct definition
allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct definition

Signed-off-by: Carlos Santa 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_drv.h | 5 ++---
 drivers/gpu/drm/i915/i915_pci.c | 5 -
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index feec00f..6f2f066 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -770,6 +770,7 @@ struct intel_csr {
func(is_kabylake) sep \
func(is_preliminary) sep \
func(has_fbc) sep \
+   func(has_psr) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2767,9 +2768,7 @@ struct drm_i915_cmd_table {
 
 #define HAS_DDI(dev)   (INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
-IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
-IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+#define HAS_PSR(dev)   (INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)(IS_GEN6(dev) || IS_HASWELL(dev) || \
 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e1caa0b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -243,6 +243,7 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
 
 #define VLV_FEATURES  \
.gen = 7, .num_pipes = 2, \
+   .has_psr = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -264,7 +265,8 @@ static const struct intel_device_info 
intel_valleyview_d_info = {
GEN7_FEATURES, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
.has_ddi = 1, \
-   .has_fpga_dbg = 1
+   .has_fpga_dbg = 1, \
+   .has_psr = 1
 
 static const struct intel_device_info intel_haswell_d_info = {
HSW_FEATURES,
@@ -312,6 +314,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.need_gfx_hws = 1, .has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.is_cherryview = 1,
+   .has_psr = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 20/21] drm/i915: Make HWS_NEEDS_PHYSICAL the exception

[Carlos Santa]

Make the .hws_needs_physical the exception by switching the flag
on earlier platforms since they are fewer to support. Remove the flag on
later GPUs hardware since they all use GTT hws by default.

Switch the logic as well in the driver to reflect this change.

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h |  4 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c   |  2 +-
 drivers/gpu/drm/i915/i915_pci.c | 27 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++--
 4 files changed, 30 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 233feb9..8e0e0fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -755,7 +755,7 @@ struct intel_csr {
func(is_i915g) sep \
func(is_i945gm) sep \
func(is_g33) sep \
-   func(need_gfx_hws) sep \
+   func(hws_needs_physical) sep \
func(is_g4x) sep \
func(is_pineview) sep \
func(is_broadwater) sep \
@@ -2731,7 +2731,7 @@ struct drm_i915_cmd_table {
 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
 #define HAS_WT(dev)((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
 HAS_EDRAM(dev))
-#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
+#define HWS_NEEDS_PHYSICAL(dev)(INTEL_INFO(dev)->hws_needs_physical)
 
 #define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->has_hw_contexts)
 #define HAS_LOGICAL_RING_CONTEXTS(dev) 
(INTEL_INFO(dev)->has_logical_ring_contexts)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index eecb870..ba68327 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1008,7 +1008,7 @@ static void error_record_engine_registers(struct 
drm_i915_error_state *error,
ee->tail = I915_READ_TAIL(engine);
ee->ctl = I915_READ_CTL(engine);
 
-   if (I915_NEED_GFX_HWS(dev_priv)) {
+   if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
i915_reg_t mmio;
 
if (IS_GEN7(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1c2f5fa..c5f4078 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -58,6 +58,7 @@
.gen = 2, \
.has_overlay = 1, .overlay_needs_physical = 1, \
.has_gmch_display = 1, \
+   .hws_needs_physical = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -95,6 +96,7 @@ static const struct intel_device_info intel_i915g_info = {
GEN3_FEATURES,
.is_i915g = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+   .hws_needs_physical = 1,
 };
 static const struct intel_device_info intel_i915gm_info = {
GEN3_FEATURES,
@@ -103,11 +105,13 @@ static const struct intel_device_info intel_i915gm_info = 
{
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
.has_fbc = 1,
+   .hws_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945g_info = {
GEN3_FEATURES,
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+   .hws_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945gm_info = {
GEN3_FEATURES,
@@ -116,6 +120,7 @@ static const struct intel_device_info intel_i945gm_info = {
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
.has_fbc = 1,
+   .hws_needs_physical = 1,
 };
 
 #define GEN4_FEATURES \
@@ -130,6 +135,7 @@ static const struct intel_device_info intel_i965g_info = {
GEN4_FEATURES,
.is_broadwater = 1,
.has_overlay = 1,
+   .hws_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
@@ -138,11 +144,12 @@ static const struct intel_device_info intel_i965gm_info = 
{
.is_mobile = 1, .has_fbc = 1,
.has_overlay = 1,
.supports_tv = 1,
+   .hws_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_g33_info = {
.gen = 3, .is_g33 = 1, .num_pipes = 2,
-   .need_gfx_hws = 1, .has_hotplug = 1,
+   .has_hotplug = 1,
.has_overlay = 1,
.ring_mask = RENDER_RING,
GEN_DEFAULT_PIPEOFFSETS,
@@ -151,7 +158,7 @@ static const struct intel_device_info intel_g33_info = {
 
 static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
-   .is_g4x = 1, .need_gfx_hws = 1,
+   .is_g4x = 1,
.has_pipe_cxsr = 1,
.ring_mask = RENDER_RING | BSD_RING,
 };
@@ -159,7 +166,7 @@ static const struct intel_device_info intel_g45_info = {
 static const struct intel_device_info intel_gm45_info = {
GEN4_FEATURES,
.is_g4x = 1,
-   .is_mobile = 1, 

[Intel-gfx] [PATCH v3 08/21] drm/i915: Move HAS_RC6 definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9d95c5..bc6df5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -774,6 +774,7 @@ struct intel_csr {
func(has_runtime_pm) sep \
func(has_csr) sep \
func(has_resource_streamer) sep \
+   func(has_rc6) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2773,7 +2774,7 @@ struct drm_i915_cmd_table {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)   (INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)(INTEL_INFO(dev)->has_runtime_pm)
-#define HAS_RC6(dev)   (INTEL_INFO(dev)->gen >= 6)
+#define HAS_RC6(dev)   (INTEL_INFO(dev)->has_rc6)
 #define HAS_RC6p(dev)  (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
 #define HAS_CSR(dev)   (INTEL_INFO(dev)->has_csr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 46c48ed..42108dc 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -201,6 +201,7 @@ static const struct intel_device_info intel_ironlake_m_info 
= {
.has_fbc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
+   .has_rc6 = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
@@ -219,6 +220,7 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
.has_fbc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
+   .has_rc6 = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
@@ -243,6 +245,7 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
.gen = 7, .num_pipes = 2, \
.has_psr = 1, \
.has_runtime_pm = 1, \
+   .has_rc6 = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -293,6 +296,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.has_psr = 1,
.has_runtime_pm = 1,
.has_resource_streamer = 1,
+   .has_rc6 = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -327,6 +331,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_pooled_eu = 0,
.has_csr = 1,
.has_resource_streamer = 1,
+   .has_rc6 = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 07/21] drm/i915: Move HAS_RESOURCE_STREAMER definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 drivers/gpu/drm/i915/i915_pci.c | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14e8911..e9d95c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -773,6 +773,7 @@ struct intel_csr {
func(has_psr) sep \
func(has_runtime_pm) sep \
func(has_csr) sep \
+   func(has_resource_streamer) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2786,8 +2787,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
 
-#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
-   INTEL_INFO(dev)->gen >= 8)
+#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
 
 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 21a3bc5..46c48ed 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -260,6 +260,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
.has_ddi = 1, \
.has_fpga_dbg = 1, \
.has_psr = 1, \
+   .has_resource_streamer = 1, \
.has_runtime_pm = 1
 
 static const struct intel_device_info intel_haswell_info = {
@@ -291,6 +292,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.is_cherryview = 1,
.has_psr = 1,
.has_runtime_pm = 1,
+   .has_resource_streamer = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -324,6 +326,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_runtime_pm = 1,
.has_pooled_eu = 0,
.has_csr = 1,
+   .has_resource_streamer = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 15/21] drm/i915: Introduce GEN2_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben W.

Use it for 830, 845g, i85x, i865g.

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_pci.c | 37 -
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2f65898..3cd0d8f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -54,38 +54,33 @@
 #define CHV_COLORS \
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
 
+#define GEN2_FEATURES \
+   .gen = 2, \
+   .has_overlay = 1, .overlay_needs_physical = 1, \
+   .ring_mask = RENDER_RING, \
+   GEN_DEFAULT_PIPEOFFSETS, \
+   CURSOR_OFFSETS
+
 static const struct intel_device_info intel_i830_info = {
-   .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
-   .has_overlay = 1, .overlay_needs_physical = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
+   GEN2_FEATURES,
+   .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 };
 
 static const struct intel_device_info intel_845g_info = {
-   .gen = 2, .num_pipes = 1,
-   .has_overlay = 1, .overlay_needs_physical = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
+   GEN2_FEATURES,
+   .num_pipes = 1,
 };
 
 static const struct intel_device_info intel_i85x_info = {
-   .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
-   .cursor_needs_physical = 1,
-   .has_overlay = 1, .overlay_needs_physical = 1,
+   GEN2_FEATURES,
+   .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
+   .is_i85x = 1,
.has_fbc = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i865g_info = {
-   .gen = 2, .num_pipes = 1,
-   .has_overlay = 1, .overlay_needs_physical = 1,
-   .ring_mask = RENDER_RING,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
+   GEN2_FEATURES,
+   .num_pipes = 1,
 };
 
 #define GEN3_FEATURES \
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 05/21] drm/i915: Get rid of HAS_CORE_RING_FREQ

[Carlos Santa]

No need for HAS_CORE_RING_FREQ as that flag is actually the same as
.has_llc. Feedback from V. Syrjala.

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
 drivers/gpu/drm/i915/i915_drv.h | 4 
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9bd4158..01b6735 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1898,11 +1898,12 @@ static int i915_ring_freq_table(struct seq_file *m, 
void *unused)
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_device_info *info = mkwrite_device_info(dev_priv);
int ret = 0;
int gpu_freq, ia_freq;
unsigned int max_gpu_freq, min_gpu_freq;
 
-   if (!HAS_CORE_RING_FREQ(dev)) {
+   if (!info->has_llc) {
seq_puts(m, "unsupported on this chipset\n");
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0eaf28f..3ab63c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2788,10 +2788,6 @@ struct drm_i915_cmd_table {
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
INTEL_INFO(dev)->gen >= 8)
 
-#define HAS_CORE_RING_FREQ(dev)(INTEL_INFO(dev)->gen >= 6 && \
-!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
-!IS_BROXTON(dev))
-
 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK   0xff00
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 12/21] drm/i915: Move HAS_GMBUS_IRQ definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 6 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4621ae..729a91b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -777,6 +777,7 @@ struct intel_csr {
func(has_rc6) sep \
func(has_rc6p) sep \
func(has_dp_mst) sep \
+   func(has_gmbus_irq) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2753,7 +2754,7 @@ struct drm_i915_cmd_table {
  * interrupt source and so prevents the other device from working properly.
  */
 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
-#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
+#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8a50e45..59c958a4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -181,6 +181,7 @@ static const struct intel_device_info intel_pineview_info = 
{
 #define GEN5_FEATURES \
.gen = 5, .num_pipes = 2, \
.need_gfx_hws = 1, .has_hotplug = 1, \
+   .has_gmbus_irq = 1, \
.ring_mask = RENDER_RING | BSD_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -202,6 +203,7 @@ static const struct intel_device_info intel_ironlake_m_info 
= {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+   .has_gmbus_irq = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
 
@@ -222,6 +224,7 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+   .has_gmbus_irq = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
 
@@ -247,6 +250,7 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
.has_psr = 1, \
.has_runtime_pm = 1, \
.has_rc6 = 1, \
+   .has_gmbus_irq = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -300,6 +304,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.has_runtime_pm = 1,
.has_resource_streamer = 1,
.has_rc6 = 1,
+   .has_gmbus_irq = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -336,6 +341,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_resource_streamer = 1,
.has_rc6 = 1,
.has_dp_mst = 1,
+   .has_gmbus_irq = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 06/21] drm/i915 Move HAS_CSR definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
  definitions

Signed-off-by: Carlos Santa 
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ab63c0..14e8911 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -772,6 +772,7 @@ struct intel_csr {
func(has_fbc) sep \
func(has_psr) sep \
func(has_runtime_pm) sep \
+   func(has_csr) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2774,7 +2775,7 @@ struct drm_i915_cmd_table {
 #define HAS_RC6(dev)   (INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)  (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
-#define HAS_CSR(dev)   (IS_GEN9(dev))
+#define HAS_CSR(dev)   (INTEL_INFO(dev)->has_csr)
 
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9d78836..21a3bc5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -301,12 +301,14 @@ static const struct intel_device_info intel_skylake_info 
= {
BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
+   .has_csr = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
+   .has_csr = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -321,6 +323,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_fbc = 1,
.has_runtime_pm = 1,
.has_pooled_eu = 0,
+   .has_csr = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -330,12 +333,14 @@ static const struct intel_device_info intel_kabylake_info 
= {
BDW_FEATURES,
.is_kabylake = 1,
.gen = 9,
+   .has_csr = 1,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
BDW_FEATURES,
.is_kabylake = 1,
.gen = 9,
+   .has_csr = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 03/21] drm/i915: Introduce GEN6_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben W.

Use it for snb.

Signed-off-by: Carlos Santa 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_pci.c | 26 --
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b5ec8a7..bdc2071 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -195,24 +195,22 @@ static const struct intel_device_info 
intel_ironlake_m_info = {
CURSOR_OFFSETS,
 };
 
+#define GEN6_FEATURES \
+   .gen = 6, .num_pipes = 2, \
+   .need_gfx_hws = 1, .has_hotplug = 1, \
+   .has_fbc = 1, \
+   .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+   .has_llc = 1, \
+   GEN_DEFAULT_PIPEOFFSETS, \
+   CURSOR_OFFSETS
+
 static const struct intel_device_info intel_sandybridge_d_info = {
-   .gen = 6, .num_pipes = 2,
-   .need_gfx_hws = 1, .has_hotplug = 1,
-   .has_fbc = 1,
-   .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
-   .has_llc = 1,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
+   GEN6_FEATURES,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
-   .gen = 6, .is_mobile = 1, .num_pipes = 2,
-   .need_gfx_hws = 1, .has_hotplug = 1,
-   .has_fbc = 1,
-   .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
-   .has_llc = 1,
-   GEN_DEFAULT_PIPEOFFSETS,
-   CURSOR_OFFSETS,
+   GEN6_FEATURES,
+   .is_mobile = 1,
 };
 
 #define GEN7_FEATURES  \
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Remove LVDS and PPS suspend time save/restore

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 02:34:12PM +0300, Imre Deak wrote:
> In the preceeding patches we made sure that:
> - the LVDS encoder takes care of reiniting both the LVDS register
> and its PPS
> - the eDP encoder takes care of reiniting its PPS
> - the PPS register unlocking workaround is applied explicitly whenever
> the PPS context is lost
> 
> Based on the above we can safely remove the opaque LVDS and PPS save /
> restore from generic code.
> 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  7 ---
>  drivers/gpu/drm/i915/i915_suspend.c | 31 ---
>  2 files changed, 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fddaec6..a83c0a6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1061,13 +1061,6 @@ struct intel_gmbus {
>  
>  struct i915_suspend_saved_registers {
>   u32 saveDSPARB;
> - u32 saveLVDS;
> - u32 savePP_ON_DELAYS;
> - u32 savePP_OFF_DELAYS;
> - u32 savePP_ON;
> - u32 savePP_OFF;
> - u32 savePP_CONTROL;
> - u32 savePP_DIVISOR;

Sweet.

Reviewed-by: Ville Syrjälä 

>   u32 saveFBC_CONTROL;
>   u32 saveCACHE_MODE_0;
>   u32 saveMI_ARB_STATE;
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
> b/drivers/gpu/drm/i915/i915_suspend.c
> index c826b69..4f27277 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -37,20 +37,6 @@ static void i915_save_display(struct drm_device *dev)
>   if (INTEL_INFO(dev)->gen <= 4)
>   dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
>  
> - /* LVDS state */
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> - dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
> - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
> - dev_priv->regfile.saveLVDS = I915_READ(LVDS);
> -
> - /* Panel power sequencer */
> - if (HAS_PCH_SPLIT(dev_priv) || INTEL_GEN(dev_priv) <= 4) {
> - dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL(0));
> - dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS(0));
> - dev_priv->regfile.savePP_OFF_DELAYS = 
> I915_READ(PP_OFF_DELAYS(0));
> - dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR(0));
> - }
> -
>   /* save FBC interval */
>   if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
>   dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
> @@ -59,28 +45,11 @@ static void i915_save_display(struct drm_device *dev)
>  static void i915_restore_display(struct drm_device *dev)
>  {
>   struct drm_i915_private *dev_priv = to_i915(dev);
> - u32 mask = 0x;
>  
>   /* Display arbitration */
>   if (INTEL_INFO(dev)->gen <= 4)
>   I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
>  
> - mask = ~LVDS_PORT_EN;
> -
> - /* LVDS state */
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> - I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
> - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
> - I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
> -
> - /* Panel power sequencer */
> - if (HAS_PCH_SPLIT(dev_priv) || INTEL_GEN(dev_priv) <= 4) {
> - I915_WRITE(PP_ON_DELAYS(0), dev_priv->regfile.savePP_ON_DELAYS);
> - I915_WRITE(PP_OFF_DELAYS(0), 
> dev_priv->regfile.savePP_OFF_DELAYS);
> - I915_WRITE(PP_DIVISOR(0), dev_priv->regfile.savePP_DIVISOR);
> - I915_WRITE(PP_CONTROL(0), dev_priv->regfile.savePP_CONTROL);
> - }
> -
>   /* only restore FBC info on the platform that supports FBC*/
>   intel_fbc_global_disable(dev_priv);
>  
> -- 
> 2.5.0
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 0/9] Enable upfront link training on DDI platforms

[Manasi Navare]

This patch series had some git format-patch issues due to which
it did not apply cleanly in CI system. So please disregard this patch set.
I will be sending a new patch series for enabling upfront link
training.

Regards
Manasi

On Mon, Aug 08, 2016 at 07:33:09PM -0700, Manasi Navare wrote:
> This patch series enables upfront link training on DDI platforms
> (SKL/BDW/HSW/BXT). They are based on some of the pacthes submitted
> earlier by Ander and Durgadoss.
> 
> The upfront link training had to be factored out of long pulse
> hanlder because of deadlock issues seen on DP MST cases.
> Now the upfront link training takes place in intel_dp_mode_valid()
> to find the maximum lane count and link rate at which the DP link
> can be successfully trained. These values are used to prune the
> invalid modes before modeset. Modeset makes use the upfront lane
> count and link train values.
> 
> These patches have been validated for DP SST on DDI platforms
> (SKL/HSW/BDW/BXT). They have also been tested for any regressions
> on non DDI platforms (CHV).
> 
> Ander Conselvan de Oliveira (3):
>   drm/i915: Don't pass crtc_state to intel_dp_set_link_params()
>   drm/i915: Remove ddi_pll_sel from intel_crtc_state
>   drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions
> 
> Durgadoss R (2):
>   drm/i915: Split bxt_ddi_pll_select()
>   drm/i915/dp: Enable Upfront link training for typeC DP support on BXT
> 
> Jim Bride (2):
>   drm/i915: Split skl_get_dpll()
>   drm/i915/dp: Enable upfront link training on SKL
> 
> Manasi Navare (2):
>   drm/i915: Split hsw_get_dpll()
>   drm/i915: Enable upfront link training support for HSW/BDW
> 
>  drivers/gpu/drm/i915/intel_ddi.c  | 207 +---
>  drivers/gpu/drm/i915/intel_display.c  |  43 +--
>  drivers/gpu/drm/i915/intel_dp.c   | 386 --
>  drivers/gpu/drm/i915/intel_dp_link_training.c |   7 +-
>  drivers/gpu/drm/i915/intel_dp_mst.c   |   9 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 457 
> --
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  15 +
>  drivers/gpu/drm/i915/intel_drv.h  |  29 +-
>  8 files changed, 776 insertions(+), 377 deletions(-)
> 
> -- 
> 1.9.1
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Merge TARGET_POWER_ON and PANEL_POWER_ON flag definitions

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 02:34:08PM +0300, Imre Deak wrote:
> These two flags mean the same thing, so remove the duplication.
> 
> Signed-off-by: Imre Deak 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 1 -
>  drivers/gpu/drm/i915/intel_dp.c   | 6 +++---
>  drivers/gpu/drm/i915/intel_lvds.c | 4 ++--
>  3 files changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b65fe50..889508f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3707,7 +3707,6 @@ enum {
>  #define  PANEL_POWER_RESET   (1 << 1)
>  #define  PANEL_POWER_OFF (0 << 0)
>  #define  PANEL_POWER_ON  (1 << 0)
> -#define  POWER_TARGET_ON (1 << 0)
>  
>  #define _PP_ON_DELAYS0x61208
>  #define PP_ON_DELAYS(pps_idx)_MMIO_PPS(pps_idx, 
> _PP_ON_DELAYS)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a5cef91..4796ad7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1950,7 +1950,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp 
> *intel_dp)
>   DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
>   I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
>  
> - if ((pp & POWER_TARGET_ON) == 0)
> + if ((pp & PANEL_POWER_ON) == 0)
>   intel_dp->panel_power_off_time = ktime_get_boottime();
>  
>   power_domain = intel_display_port_aux_power_domain(intel_encoder);
> @@ -2037,7 +2037,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>   POSTING_READ(pp_ctrl_reg);
>   }
>  
> - pp |= POWER_TARGET_ON;
> + pp |= PANEL_POWER_ON;
>   if (!IS_GEN5(dev))
>   pp |= PANEL_POWER_RESET;
>  
> @@ -2089,7 +2089,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
>   pp = ironlake_get_pp_control(intel_dp);
>   /* We need to switch off panel power _and_ force vdd, for otherwise some
>* panels get very unhappy and cease to work. */
> - pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
> + pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
>   EDP_BLC_ENABLE);
>  
>   pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 413e729..c5739fc 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -220,7 +220,7 @@ static void intel_enable_lvds(struct intel_encoder 
> *encoder)
>  
>   I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | 
> LVDS_PORT_EN);
>  
> - I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | POWER_TARGET_ON);
> + I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
>   POSTING_READ(lvds_encoder->reg);
>   if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
>   DRM_ERROR("timed out waiting for panel to power on\n");
> @@ -234,7 +234,7 @@ static void intel_disable_lvds(struct intel_encoder 
> *encoder)
>   struct intel_lvds_encoder *lvds_encoder = 
> to_lvds_encoder(>base);
>   struct drm_i915_private *dev_priv = to_i915(dev);
>  
> - I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~POWER_TARGET_ON);
> + I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
>   if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
>   DRM_ERROR("timed out waiting for panel to power off\n");
>  
> -- 
> 2.5.0
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: Merge the PPS register definitions

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 08:21:31PM +0300, Imre Deak wrote:
> The PPS registers are pretty much the same everywhere, the differences
> being:
> - Register fields appearing, disappearing from one platform to the
>   next: panel-reset-on-powerdown, backlight-on, panel-port,
>   register-unlock
> - Different register base addresses
> - Different number of PPS instances: 2 on VLV/CHV/BXT, 1 everywhere
>   else.
> 
> We can merge the separate set of PPS definitions by extending the PPS
> instance argument to all platforms and using instance 0 on platforms
> with a single instance. This means we'll need to calculate the register
> addresses dynamically based on the given platform and PPS instance.
> 
> v2:
> - Simplify if ladder in intel_pps_get_registers(). (Ville)
> 
> Signed-off-by: Imre Deak 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |   2 +
>  drivers/gpu/drm/i915/i915_reg.h  | 145 
> ++-
>  drivers/gpu/drm/i915/i915_suspend.c  |  30 +++-
>  drivers/gpu/drm/i915/intel_display.c |  22 --
>  drivers/gpu/drm/i915/intel_dp.c  |  45 +--
>  drivers/gpu/drm/i915/intel_lvds.c|  43 +++
>  6 files changed, 117 insertions(+), 170 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c36d176..fddaec6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1749,6 +1749,8 @@ struct drm_i915_private {
>  
>   uint32_t psr_mmio_base;
>  
> + uint32_t pps_mmio_base;
> +
>   wait_queue_head_t gmbus_wait_queue;
>  
>   struct pci_dev *bridge_dev;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f38a5e2..b65fe50 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3660,8 +3660,17 @@ enum {
>  #define   VIDEO_DIP_ENABLE_SPD_HSW   (1 << 0)
>  
>  /* Panel power sequencing */
> -#define PP_STATUS_MMIO(0x61200)
> -#define   PP_ON  (1 << 31)
> +#define PPS_BASE 0x61200
> +#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
> +#define PCH_PPS_BASE 0xC7200
> +
> +#define _MMIO_PPS(pps_idx, reg)  _MMIO(dev_priv->pps_mmio_base - 
> \
> +   PPS_BASE + (reg) +\
> +   (pps_idx) * 0x100)
> +
> +#define _PP_STATUS   0x61200
> +#define PP_STATUS(pps_idx)   _MMIO_PPS(pps_idx, _PP_STATUS)
> +#define   PP_ON  (1 << 31)
>  /*
>   * Indicates that all dependencies of the panel are on:
>   *
> @@ -3669,14 +3678,14 @@ enum {
>   * - pipe enabled
>   * - LVDS/DVOB/DVOC on
>   */
> -#define   PP_READY   (1 << 30)
> -#define   PP_SEQUENCE_NONE   (0 << 28)
> -#define   PP_SEQUENCE_POWER_UP   (1 << 28)
> -#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
> -#define   PP_SEQUENCE_MASK   (3 << 28)
> -#define   PP_SEQUENCE_SHIFT  28
> -#define   PP_CYCLE_DELAY_ACTIVE  (1 << 27)
> -#define   PP_SEQUENCE_STATE_MASK 0x000f
> +#define   PP_READY   (1 << 30)
> +#define   PP_SEQUENCE_NONE   (0 << 28)
> +#define   PP_SEQUENCE_POWER_UP   (1 << 28)
> +#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
> +#define   PP_SEQUENCE_MASK   (3 << 28)
> +#define   PP_SEQUENCE_SHIFT  28
> +#define   PP_CYCLE_DELAY_ACTIVE  (1 << 27)
> +#define   PP_SEQUENCE_STATE_MASK 0x000f
>  #define   PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
>  #define   PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
>  #define   PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
> @@ -3686,11 +3695,46 @@ enum {
>  #define   PP_SEQUENCE_STATE_ON_S1_2  (0xa << 0)
>  #define   PP_SEQUENCE_STATE_ON_S1_3  (0xb << 0)
>  #define   PP_SEQUENCE_STATE_RESET(0xf << 0)
> -#define PP_CONTROL   _MMIO(0x61204)
> -#define   POWER_TARGET_ON(1 << 0)
> -#define PP_ON_DELAYS _MMIO(0x61208)
> -#define PP_OFF_DELAYS_MMIO(0x6120c)
> -#define PP_DIVISOR   _MMIO(0x61210)
> +
> +#define _PP_CONTROL  0x61204
> +#define PP_CONTROL(pps_idx)  _MMIO_PPS(pps_idx, _PP_CONTROL)
> +#define  PANEL_UNLOCK_REGS   (0xabcd << 16)
> +#define  PANEL_UNLOCK_MASK   (0x << 16)
> +#define  BXT_POWER_CYCLE_DELAY_MASK  0x1f0
> +#define  BXT_POWER_CYCLE_DELAY_SHIFT 4
> +#define  EDP_FORCE_VDD   (1 << 3)
> +#define  EDP_BLC_ENABLE  (1 << 2)
> +#define  PANEL_POWER_RESET   (1 << 1)
> +#define  PANEL_POWER_OFF (0 << 0)
> +#define  PANEL_POWER_ON  (1 << 0)
> +#define  POWER_TARGET_ON (1 << 0)
> +
> +#define _PP_ON_DELAYS0x61208
> +#define PP_ON_DELAYS(pps_idx)_MMIO_PPS(pps_idx, 
> _PP_ON_DELAYS)
> +#define  PANEL_PORT_SELECT_MASK  (3 << 30)
> +#define  

Re: [Intel-gfx] [PATCH v2 4/6] drm/i915/dp: Restore PPS HW state from the encoder resume hook

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 08:21:33PM +0300, Imre Deak wrote:
> Similarly to the previous patch, initialize the PPS from the DP
> encoder's resume hook. Note that as opposed to LVDS we can't do this
> during encoder enabling, since we need the PPS for DP detection as well.
> The PPS init code is now the same for init and resume, so factor out a
> new intel_dp_pps_init() helper for this.
> 
> v2:
> - Factor out intel_dp_pps_init() (Ville).
> 
> Signed-off-by: Imre Deak 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 31 ---
>  1 file changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a20faa0..2ef7b14 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -256,6 +256,8 @@ intel_dp_init_panel_power_sequencer(struct drm_device 
> *dev,
>  static void
>  intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> struct intel_dp *intel_dp);
> +static void
> +intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
>  
>  static void pps_lock(struct intel_dp *intel_dp)
>  {
> @@ -4657,13 +4659,8 @@ void intel_dp_encoder_reset(struct drm_encoder 
> *encoder)
>  
>   pps_lock(intel_dp);
>  
> - /*
> -  * Read out the current power sequencer assignment,
> -  * in case the BIOS did something with it.
> -  */
> - if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
> - vlv_initial_power_sequencer_setup(intel_dp);
> -
> + /* Reinit the power sequencer, in case BIOS did something with it. */
> + intel_dp_pps_init(encoder->dev, intel_dp);
>   intel_edp_panel_vdd_sanitize(intel_dp);
>  
>   pps_unlock(intel_dp);
> @@ -5011,6 +5008,17 @@ intel_dp_init_panel_power_sequencer_registers(struct 
> drm_device *dev,
> I915_READ(regs.pp_div));
>  }
>  
> +static void intel_dp_pps_init(struct drm_device *dev,
> +   struct intel_dp *intel_dp)
> +{
> + if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + vlv_initial_power_sequencer_setup(intel_dp);
> + } else {
> + intel_dp_init_panel_power_sequencer(dev, intel_dp);
> + intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
> + }
> +}
> +
>  /**
>   * intel_dp_set_drrs_state - program registers for RR switch to take effect
>   * @dev: DRM device
> @@ -5425,14 +5433,7 @@ static bool intel_edp_init_connector(struct intel_dp 
> *intel_dp,
>   pps_lock(intel_dp);
>  
>   intel_dp_init_panel_power_timestamps(intel_dp);
> -
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> - vlv_initial_power_sequencer_setup(intel_dp);
> - } else {
> - intel_dp_init_panel_power_sequencer(dev, intel_dp);
> - intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
> - }
> -
> + intel_dp_pps_init(dev, intel_dp);
>   intel_edp_panel_vdd_sanitize(intel_dp);
>  
>   pps_unlock(intel_dp);
> -- 
> 2.5.0

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/lvds: Restore initial HW state during encoder enabling

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 08:21:32PM +0300, Imre Deak wrote:
> Atm the LVDS encoder depends on the PPS HW context being saved/restored
> from generic suspend/resume code. Since the PPS is specific to the LVDS
> and eDP encoders a cleaner way is to reinitialize it during encoder
> enabling, so do this here for LVDS. Follow-up patches will init the PPS
> for the eDP encoder similarly and remove the suspend/resume time save /
> restore.
> 
> v2:
> - Apply BSpec +1 offset and use DIV_ROUND_UP() when programming the
> power cycle delay. (Ville)
> 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |   1 +
>  drivers/gpu/drm/i915/intel_lvds.c | 113 
> +-
>  2 files changed, 101 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 889508f..da82744 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3710,6 +3710,7 @@ enum {
>  
>  #define _PP_ON_DELAYS0x61208
>  #define PP_ON_DELAYS(pps_idx)_MMIO_PPS(pps_idx, 
> _PP_ON_DELAYS)
> +#define  PANEL_PORT_SELECT_SHIFT 30
>  #define  PANEL_PORT_SELECT_MASK  (3 << 30)
>  #define  PANEL_PORT_SELECT_LVDS  (0 << 30)
>  #define  PANEL_PORT_SELECT_DPA   (1 << 30)
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
> b/drivers/gpu/drm/i915/intel_lvds.c
> index c5739fc..939f51f 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -48,6 +48,20 @@ struct intel_lvds_connector {
>   struct notifier_block lid_notifier;
>  };
>  
> +struct intel_lvds_pps {
> + /* 100us units */
> + int t1_t2;
> + int t3;
> + int t4;
> + int t5;
> + int tx;
> +
> + int divider;
> +
> + int port;
> + bool reset_on_powerdown;

powerdown_on_reset?

> +};
> +
>  struct intel_lvds_encoder {
>   struct intel_encoder base;
>  
> @@ -55,6 +69,9 @@ struct intel_lvds_encoder {
>   i915_reg_t reg;
>   u32 a3_power;
>  
> + struct intel_lvds_pps init_pps;
> + u32 init_lvds_val;
> +
>   struct intel_lvds_connector *attached_connector;
>  };
>  
> @@ -136,6 +153,82 @@ static void intel_lvds_get_config(struct intel_encoder 
> *encoder,
>   pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
>  }
>  
> +static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
> + struct intel_lvds_pps *pps)
> +{
> + u32 val;
> +
> + pps->reset_on_powerdown = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
> +
> + val = I915_READ(PP_ON_DELAYS(0));
> + pps->port = (val & PANEL_PORT_SELECT_MASK) >>
> + PANEL_PORT_SELECT_SHIFT;
> + pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
> +  PANEL_POWER_UP_DELAY_SHIFT;
> + pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
> +   PANEL_LIGHT_ON_DELAY_SHIFT;
> +
> + val = I915_READ(PP_OFF_DELAYS(0));
> + pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
> +   PANEL_POWER_DOWN_DELAY_SHIFT;
> + pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
> +   PANEL_LIGHT_OFF_DELAY_SHIFT;
> +
> + val = I915_READ(PP_DIVISOR(0));
> + pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
> +PP_REFERENCE_DIVIDER_SHIFT;
> + val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
> +   PANEL_POWER_CYCLE_DELAY_SHIFT;
> + /*
> +  * Remove the BSpec specified +1 (100ms) offset that accounts for a
> +  * too short power-cycle delay due to the asynchronous programming of
> +  * the register.
> +  */
> + if (val)
> + val--;
> + /* Convert from 100ms to 100us units */
> + pps->t4 = val * 1000;
> +
> + if (INTEL_INFO(dev_priv)->gen <= 4 &&
> + pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
> + DRM_DEBUG_KMS("Panel power timings uninitialized, "
> +   "setting defaults\n");
> + /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
> + pps->t1_t2 = 40 * 10;
> + pps->t5 = 200 * 10;
> + /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
> + pps->t3 = 35 * 10;
> + pps->tx = 200 * 10;
> + }
> +
> + DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
> +  "divider %d port %d reset_on_powerdown %d\n",
> +  pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
> +  pps->divider, pps->port, pps->reset_on_powerdown);
> +}
> +
> +static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
> +struct intel_lvds_pps *pps)
> +{
> + u32 val;
> +
> + val = I915_READ(PP_CONTROL(0));
> + WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
> + if 

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Apply the PPS register unlock workaround more consistently

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 08:21:34PM +0300, Imre Deak wrote:
> Atm, we apply this workaround somewhat inconsistently at the following
> points: driver loading, LVDS init, eDP PPS init, system resume. As this
> workaround also affects registers other than PPS (timing, PLL) a more
> consistent way is to apply it early after the PPS HW context is known to
> be lost: driver loading, system resume and on VLV/CHV/BXT when turning
> on power domains.
> 
> This is needed by the next patch that removes saving/restoring of the
> PP_CONTROL register.
> 
> This also removes the incorrect programming of the workaround on HSW+
> PCH platforms which don't have the register locking mechanism.
> 
> v2: (Ville)
> - Don't apply the workaround on BXT.
> - Simplify platform checks using HAS_DDI().
> 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/i915_drv.c |  1 +
>  drivers/gpu/drm/i915/intel_display.c| 26 ++
>  drivers/gpu/drm/i915/intel_dp.c |  3 ++-
>  drivers/gpu/drm/i915/intel_drv.h|  1 +
>  drivers/gpu/drm/i915/intel_lvds.c   |  8 
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  4 
>  6 files changed, 34 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 8cfc264..0fcd1c0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1560,6 +1560,7 @@ static int i915_drm_resume(struct drm_device *dev)
>   i915_gem_resume(dev);
>  
>   i915_restore_state(dev);
> + intel_pps_unlock_regs_wa(dev_priv);
>   intel_opregion_setup(dev_priv);
>  
>   intel_init_pch_refclk(dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 3d5fd06..bcbf277 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14635,6 +14635,30 @@ static bool intel_crt_present(struct drm_device *dev)
>   return true;
>  }
>  
> +void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
> +{
> + int pps_num;
> + int pps_idx;
> +
> + if (HAS_DDI(dev_priv))
> + return;
> + /*
> +  * This w/a is needed at least on CPT/PPT, but to be sure apply it
> +  * everywhere where registers can be write protected.
> +  */
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + pps_num = 2;
> + else
> + pps_num = 1;
> +
> + for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
> + u32 val = I915_READ(PP_CONTROL(pps_idx));
> +
> + val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
> + I915_WRITE(PP_CONTROL(pps_idx), val);
> + }
> +}
> +
>  static void intel_pps_init(struct drm_i915_private *dev_priv)
>  {
>   if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
> @@ -14643,6 +14667,8 @@ static void intel_pps_init(struct drm_i915_private 
> *dev_priv)
>   dev_priv->pps_mmio_base = VLV_PPS_BASE;
>   else
>   dev_priv->pps_mmio_base = PPS_BASE;
> +
> + intel_pps_unlock_regs_wa(dev_priv);
>  }
>  
>  static void intel_setup_outputs(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2ef7b14..3d3d3fb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1829,7 +1829,8 @@ static  u32 ironlake_get_pp_control(struct intel_dp 
> *intel_dp)
>   lockdep_assert_held(_priv->pps_mutex);
>  
>   control = I915_READ(_pp_ctrl_reg(intel_dp));
> - if (!IS_BROXTON(dev)) {
> + if (WARN_ON(!HAS_DDI(dev_priv) &&
> +  (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
>   control &= ~PANEL_UNLOCK_MASK;
>   control |= PANEL_UNLOCK_REGS;
>   }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index c29a429..cbce786 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1159,6 +1159,7 @@ void intel_mark_busy(struct drm_i915_private *dev_priv);
>  void intel_mark_idle(struct drm_i915_private *dev_priv);
>  void intel_crtc_restore_mode(struct drm_crtc *crtc);
>  int intel_display_suspend(struct drm_device *dev);
> +void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
>  void intel_encoder_destroy(struct drm_encoder *encoder);
>  int intel_connector_init(struct intel_connector *);
>  struct intel_connector *intel_connector_alloc(void);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 939f51f..35d55f1 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -977,14 +977,6 @@ void intel_lvds_init(struct drm_device *dev)
>   int pipe;
>   u8 pin;
>  
> - /*
> -  * Unlock registers and just leave them unlocked. Do this before
> -  * checking quirk lists to avoid bogus 

[Intel-gfx] [PATCH] drm: avoid "possible bad bitmask?" warning

[Dave Gordon]

Recent versions of gcc say this:

include/drm/i915_drm.h:96:34: warning: result of ‘65535 << 20’
requires 37 bits to represent, but ‘int’ only has 32 bits
[-Wshift-overflow=]

Reported-by: David Binderman 
Signed-off-by: Dave Gordon 
Cc: Dave Airlie 
---
 include/drm/i915_drm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index b1755f8..4e1b274 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -93,6 +93,6 @@ extern bool i915_gpu_turbo_disable(void);
 #defineI845_TSEG_SIZE_1M   (3 << 1)
 
 #define INTEL_BSM 0x5c
-#define   INTEL_BSM_MASK (0x << 20)
+#define   INTEL_BSM_MASK   (-(1u << 20))
 
 #endif /* _I915_DRM_H_ */
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 3/6] drm/i915/lvds: Restore initial HW state during encoder enabling

[Imre Deak]

Atm the LVDS encoder depends on the PPS HW context being saved/restored
from generic suspend/resume code. Since the PPS is specific to the LVDS
and eDP encoders a cleaner way is to reinitialize it during encoder
enabling, so do this here for LVDS. Follow-up patches will init the PPS
for the eDP encoder similarly and remove the suspend/resume time save /
restore.

v2:
- Apply BSpec +1 offset and use DIV_ROUND_UP() when programming the
power cycle delay. (Ville)

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_reg.h   |   1 +
 drivers/gpu/drm/i915/intel_lvds.c | 113 +-
 2 files changed, 101 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 889508f..da82744 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3710,6 +3710,7 @@ enum {
 
 #define _PP_ON_DELAYS  0x61208
 #define PP_ON_DELAYS(pps_idx)  _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
+#define  PANEL_PORT_SELECT_SHIFT   30
 #define  PANEL_PORT_SELECT_MASK(3 << 30)
 #define  PANEL_PORT_SELECT_LVDS(0 << 30)
 #define  PANEL_PORT_SELECT_DPA (1 << 30)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
b/drivers/gpu/drm/i915/intel_lvds.c
index c5739fc..939f51f 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -48,6 +48,20 @@ struct intel_lvds_connector {
struct notifier_block lid_notifier;
 };
 
+struct intel_lvds_pps {
+   /* 100us units */
+   int t1_t2;
+   int t3;
+   int t4;
+   int t5;
+   int tx;
+
+   int divider;
+
+   int port;
+   bool reset_on_powerdown;
+};
+
 struct intel_lvds_encoder {
struct intel_encoder base;
 
@@ -55,6 +69,9 @@ struct intel_lvds_encoder {
i915_reg_t reg;
u32 a3_power;
 
+   struct intel_lvds_pps init_pps;
+   u32 init_lvds_val;
+
struct intel_lvds_connector *attached_connector;
 };
 
@@ -136,6 +153,82 @@ static void intel_lvds_get_config(struct intel_encoder 
*encoder,
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
+static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
+   struct intel_lvds_pps *pps)
+{
+   u32 val;
+
+   pps->reset_on_powerdown = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
+
+   val = I915_READ(PP_ON_DELAYS(0));
+   pps->port = (val & PANEL_PORT_SELECT_MASK) >>
+   PANEL_PORT_SELECT_SHIFT;
+   pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
+PANEL_POWER_UP_DELAY_SHIFT;
+   pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
+ PANEL_LIGHT_ON_DELAY_SHIFT;
+
+   val = I915_READ(PP_OFF_DELAYS(0));
+   pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
+ PANEL_POWER_DOWN_DELAY_SHIFT;
+   pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
+ PANEL_LIGHT_OFF_DELAY_SHIFT;
+
+   val = I915_READ(PP_DIVISOR(0));
+   pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
+  PP_REFERENCE_DIVIDER_SHIFT;
+   val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
+ PANEL_POWER_CYCLE_DELAY_SHIFT;
+   /*
+* Remove the BSpec specified +1 (100ms) offset that accounts for a
+* too short power-cycle delay due to the asynchronous programming of
+* the register.
+*/
+   if (val)
+   val--;
+   /* Convert from 100ms to 100us units */
+   pps->t4 = val * 1000;
+
+   if (INTEL_INFO(dev_priv)->gen <= 4 &&
+   pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
+   DRM_DEBUG_KMS("Panel power timings uninitialized, "
+ "setting defaults\n");
+   /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
+   pps->t1_t2 = 40 * 10;
+   pps->t5 = 200 * 10;
+   /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
+   pps->t3 = 35 * 10;
+   pps->tx = 200 * 10;
+   }
+
+   DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
+"divider %d port %d reset_on_powerdown %d\n",
+pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
+pps->divider, pps->port, pps->reset_on_powerdown);
+}
+
+static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
+  struct intel_lvds_pps *pps)
+{
+   u32 val;
+
+   val = I915_READ(PP_CONTROL(0));
+   WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
+   if (pps->reset_on_powerdown)
+   val |= PANEL_POWER_RESET;
+   I915_WRITE(PP_CONTROL(0), val);
+
+   I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
+   (pps->t1_t2 << 

[Intel-gfx] [PATCH v2 1/6] drm/i915: Merge the PPS register definitions

[Imre Deak]

The PPS registers are pretty much the same everywhere, the differences
being:
- Register fields appearing, disappearing from one platform to the
  next: panel-reset-on-powerdown, backlight-on, panel-port,
  register-unlock
- Different register base addresses
- Different number of PPS instances: 2 on VLV/CHV/BXT, 1 everywhere
  else.

We can merge the separate set of PPS definitions by extending the PPS
instance argument to all platforms and using instance 0 on platforms
with a single instance. This means we'll need to calculate the register
addresses dynamically based on the given platform and PPS instance.

v2:
- Simplify if ladder in intel_pps_get_registers(). (Ville)

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/i915_reg.h  | 145 ++-
 drivers/gpu/drm/i915/i915_suspend.c  |  30 +++-
 drivers/gpu/drm/i915/intel_display.c |  22 --
 drivers/gpu/drm/i915/intel_dp.c  |  45 +--
 drivers/gpu/drm/i915/intel_lvds.c|  43 +++
 6 files changed, 117 insertions(+), 170 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c36d176..fddaec6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1749,6 +1749,8 @@ struct drm_i915_private {
 
uint32_t psr_mmio_base;
 
+   uint32_t pps_mmio_base;
+
wait_queue_head_t gmbus_wait_queue;
 
struct pci_dev *bridge_dev;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f38a5e2..b65fe50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3660,8 +3660,17 @@ enum {
 #define   VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
 
 /* Panel power sequencing */
-#define PP_STATUS  _MMIO(0x61200)
-#define   PP_ON(1 << 31)
+#define PPS_BASE   0x61200
+#define VLV_PPS_BASE   (VLV_DISPLAY_BASE + PPS_BASE)
+#define PCH_PPS_BASE   0xC7200
+
+#define _MMIO_PPS(pps_idx, reg)_MMIO(dev_priv->pps_mmio_base - 
\
+ PPS_BASE + (reg) +\
+ (pps_idx) * 0x100)
+
+#define _PP_STATUS 0x61200
+#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
+#define   PP_ON(1 << 31)
 /*
  * Indicates that all dependencies of the panel are on:
  *
@@ -3669,14 +3678,14 @@ enum {
  * - pipe enabled
  * - LVDS/DVOB/DVOC on
  */
-#define   PP_READY (1 << 30)
-#define   PP_SEQUENCE_NONE (0 << 28)
-#define   PP_SEQUENCE_POWER_UP (1 << 28)
-#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
-#define   PP_SEQUENCE_MASK (3 << 28)
-#define   PP_SEQUENCE_SHIFT28
-#define   PP_CYCLE_DELAY_ACTIVE(1 << 27)
-#define   PP_SEQUENCE_STATE_MASK 0x000f
+#define   PP_READY (1 << 30)
+#define   PP_SEQUENCE_NONE (0 << 28)
+#define   PP_SEQUENCE_POWER_UP (1 << 28)
+#define   PP_SEQUENCE_POWER_DOWN   (2 << 28)
+#define   PP_SEQUENCE_MASK (3 << 28)
+#define   PP_SEQUENCE_SHIFT28
+#define   PP_CYCLE_DELAY_ACTIVE(1 << 27)
+#define   PP_SEQUENCE_STATE_MASK   0x000f
 #define   PP_SEQUENCE_STATE_OFF_IDLE   (0x0 << 0)
 #define   PP_SEQUENCE_STATE_OFF_S0_1   (0x1 << 0)
 #define   PP_SEQUENCE_STATE_OFF_S0_2   (0x2 << 0)
@@ -3686,11 +3695,46 @@ enum {
 #define   PP_SEQUENCE_STATE_ON_S1_2(0xa << 0)
 #define   PP_SEQUENCE_STATE_ON_S1_3(0xb << 0)
 #define   PP_SEQUENCE_STATE_RESET  (0xf << 0)
-#define PP_CONTROL _MMIO(0x61204)
-#define   POWER_TARGET_ON  (1 << 0)
-#define PP_ON_DELAYS   _MMIO(0x61208)
-#define PP_OFF_DELAYS  _MMIO(0x6120c)
-#define PP_DIVISOR _MMIO(0x61210)
+
+#define _PP_CONTROL0x61204
+#define PP_CONTROL(pps_idx)_MMIO_PPS(pps_idx, _PP_CONTROL)
+#define  PANEL_UNLOCK_REGS (0xabcd << 16)
+#define  PANEL_UNLOCK_MASK (0x << 16)
+#define  BXT_POWER_CYCLE_DELAY_MASK0x1f0
+#define  BXT_POWER_CYCLE_DELAY_SHIFT   4
+#define  EDP_FORCE_VDD (1 << 3)
+#define  EDP_BLC_ENABLE(1 << 2)
+#define  PANEL_POWER_RESET (1 << 1)
+#define  PANEL_POWER_OFF   (0 << 0)
+#define  PANEL_POWER_ON(1 << 0)
+#define  POWER_TARGET_ON   (1 << 0)
+
+#define _PP_ON_DELAYS  0x61208
+#define PP_ON_DELAYS(pps_idx)  _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
+#define  PANEL_PORT_SELECT_MASK(3 << 30)
+#define  PANEL_PORT_SELECT_LVDS(0 << 30)
+#define  PANEL_PORT_SELECT_DPA (1 << 30)
+#define  PANEL_PORT_SELECT_DPC (2 << 30)
+#define  PANEL_PORT_SELECT_DPD (3 << 30)
+#define  PANEL_PORT_SELECT_VLV(port)   ((port) << 30)
+#define  PANEL_POWER_UP_DELAY_MASK 

[Intel-gfx] [PATCH v2 5/6] drm/i915: Apply the PPS register unlock workaround more consistently

[Imre Deak]

Atm, we apply this workaround somewhat inconsistently at the following
points: driver loading, LVDS init, eDP PPS init, system resume. As this
workaround also affects registers other than PPS (timing, PLL) a more
consistent way is to apply it early after the PPS HW context is known to
be lost: driver loading, system resume and on VLV/CHV/BXT when turning
on power domains.

This is needed by the next patch that removes saving/restoring of the
PP_CONTROL register.

This also removes the incorrect programming of the workaround on HSW+
PCH platforms which don't have the register locking mechanism.

v2: (Ville)
- Don't apply the workaround on BXT.
- Simplify platform checks using HAS_DDI().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_drv.c |  1 +
 drivers/gpu/drm/i915/intel_display.c| 26 ++
 drivers/gpu/drm/i915/intel_dp.c |  3 ++-
 drivers/gpu/drm/i915/intel_drv.h|  1 +
 drivers/gpu/drm/i915/intel_lvds.c   |  8 
 drivers/gpu/drm/i915/intel_runtime_pm.c |  4 
 6 files changed, 34 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8cfc264..0fcd1c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1560,6 +1560,7 @@ static int i915_drm_resume(struct drm_device *dev)
i915_gem_resume(dev);
 
i915_restore_state(dev);
+   intel_pps_unlock_regs_wa(dev_priv);
intel_opregion_setup(dev_priv);
 
intel_init_pch_refclk(dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3d5fd06..bcbf277 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14635,6 +14635,30 @@ static bool intel_crt_present(struct drm_device *dev)
return true;
 }
 
+void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
+{
+   int pps_num;
+   int pps_idx;
+
+   if (HAS_DDI(dev_priv))
+   return;
+   /*
+* This w/a is needed at least on CPT/PPT, but to be sure apply it
+* everywhere where registers can be write protected.
+*/
+   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+   pps_num = 2;
+   else
+   pps_num = 1;
+
+   for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
+   u32 val = I915_READ(PP_CONTROL(pps_idx));
+
+   val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
+   I915_WRITE(PP_CONTROL(pps_idx), val);
+   }
+}
+
 static void intel_pps_init(struct drm_i915_private *dev_priv)
 {
if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
@@ -14643,6 +14667,8 @@ static void intel_pps_init(struct drm_i915_private 
*dev_priv)
dev_priv->pps_mmio_base = VLV_PPS_BASE;
else
dev_priv->pps_mmio_base = PPS_BASE;
+
+   intel_pps_unlock_regs_wa(dev_priv);
 }
 
 static void intel_setup_outputs(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2ef7b14..3d3d3fb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1829,7 +1829,8 @@ static  u32 ironlake_get_pp_control(struct intel_dp 
*intel_dp)
lockdep_assert_held(_priv->pps_mutex);
 
control = I915_READ(_pp_ctrl_reg(intel_dp));
-   if (!IS_BROXTON(dev)) {
+   if (WARN_ON(!HAS_DDI(dev_priv) &&
+(control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
control &= ~PANEL_UNLOCK_MASK;
control |= PANEL_UNLOCK_REGS;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c29a429..cbce786 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1159,6 +1159,7 @@ void intel_mark_busy(struct drm_i915_private *dev_priv);
 void intel_mark_idle(struct drm_i915_private *dev_priv);
 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 int intel_display_suspend(struct drm_device *dev);
+void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 int intel_connector_init(struct intel_connector *);
 struct intel_connector *intel_connector_alloc(void);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
b/drivers/gpu/drm/i915/intel_lvds.c
index 939f51f..35d55f1 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -977,14 +977,6 @@ void intel_lvds_init(struct drm_device *dev)
int pipe;
u8 pin;
 
-   /*
-* Unlock registers and just leave them unlocked. Do this before
-* checking quirk lists to avoid bogus WARNINGs.
-*/
-   if (HAS_PCH_SPLIT(dev_priv) || INTEL_GEN(dev_priv) <= 4)
-   I915_WRITE(PP_CONTROL(0),
-  I915_READ(PP_CONTROL(0)) | PANEL_UNLOCK_REGS);
-
if 

[Intel-gfx] [PATCH v2 4/6] drm/i915/dp: Restore PPS HW state from the encoder resume hook

[Imre Deak]

Similarly to the previous patch, initialize the PPS from the DP
encoder's resume hook. Note that as opposed to LVDS we can't do this
during encoder enabling, since we need the PPS for DP detection as well.
The PPS init code is now the same for init and resume, so factor out a
new intel_dp_pps_init() helper for this.

v2:
- Factor out intel_dp_pps_init() (Ville).

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/intel_dp.c | 31 ---
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a20faa0..2ef7b14 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -256,6 +256,8 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 static void
 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
  struct intel_dp *intel_dp);
+static void
+intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 
 static void pps_lock(struct intel_dp *intel_dp)
 {
@@ -4657,13 +4659,8 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
 
pps_lock(intel_dp);
 
-   /*
-* Read out the current power sequencer assignment,
-* in case the BIOS did something with it.
-*/
-   if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
-   vlv_initial_power_sequencer_setup(intel_dp);
-
+   /* Reinit the power sequencer, in case BIOS did something with it. */
+   intel_dp_pps_init(encoder->dev, intel_dp);
intel_edp_panel_vdd_sanitize(intel_dp);
 
pps_unlock(intel_dp);
@@ -5011,6 +5008,17 @@ intel_dp_init_panel_power_sequencer_registers(struct 
drm_device *dev,
  I915_READ(regs.pp_div));
 }
 
+static void intel_dp_pps_init(struct drm_device *dev,
+ struct intel_dp *intel_dp)
+{
+   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+   vlv_initial_power_sequencer_setup(intel_dp);
+   } else {
+   intel_dp_init_panel_power_sequencer(dev, intel_dp);
+   intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
+   }
+}
+
 /**
  * intel_dp_set_drrs_state - program registers for RR switch to take effect
  * @dev: DRM device
@@ -5425,14 +5433,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
pps_lock(intel_dp);
 
intel_dp_init_panel_power_timestamps(intel_dp);
-
-   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-   vlv_initial_power_sequencer_setup(intel_dp);
-   } else {
-   intel_dp_init_panel_power_sequencer(dev, intel_dp);
-   intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
-   }
-
+   intel_dp_pps_init(dev, intel_dp);
intel_edp_panel_vdd_sanitize(intel_dp);
 
pps_unlock(intel_dp);
-- 
2.5.0

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2] drm/i915: Always mark the writer as also a read for busy ioctl

[Chris Wilson]

One of the few guarantees we want the busy ioctl to provide is that the
reported busy writer is included in the set of busy read engines. This
should be provided by the ordering of setting and retiring the active
trackers, but we can do better by explicitly setting the busy read
engine flag for the last writer.

v2: More comments inside __busy_write_id() to explain why both fields
are set.

Fixes: 3fdc13c7a3cb ("drm/i915: Remove (struct_mutex) locking for busy-ioctl")
Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Cc: Joonas Lahtinen busy |= busy_check_reader(>last_read[idx]);
 
/* For ABI sanity, we only care that the write engine is in
-* the set of read engines. This is ensured by the ordering
-* of setting last_read/last_write in i915_vma_move_to_active,
-* and then in reverse in retire.
+* the set of read engines. This should be ensured by the
+* ordering of setting last_read/last_write in
+* i915_vma_move_to_active(), and then in reverse in retire.
+* However, for good measure, we always report the last_write
+* request as a busy read as well as being a busy write.
 *
 * We don't care that the set of active read/write engines
 * may change during construction of the result, as it is
-- 
2.8.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 2/3] drm/i915: Move missed interrupt detection from hangcheck to breadcrumbs

[Chris Wilson]

In commit 2529d57050af ("drm/i915: Drop racy markup of missed-irqs from
idle-worker") the racy detection of missed interrupts was removed when
we went idle. This however opened up the issue that the stuck waiters
were not being reported, causing a test case failure. If we move the
stuck waiter detection out of hangcheck and into the breadcrumb
mechanims (i.e. the waiter) itself, we can avoid this issue entirely.
This leaves hangcheck looking for a stuck GPU (inspecting for request
advancement and HEAD motion), and breadcrumbs looking for a stuck
waiter - hopefully make both easier to understand by their segregation.

v2: Reduce the error message as we now run independently of hangcheck,
and the hanging batch used by igt also counts as a stuck waiter causing
extra warnings in dmesg.
v3: Move the breadcrumb's hangcheck kickstart to the first missed wait.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97104
Fixes: 2529d57050af (waiter"drm/i915: Drop racy markup of missed-irqs...")
Testcase: igt/drv_missed_irq
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 11 ++---
 drivers/gpu/drm/i915/i915_gem.c  | 10 -
 drivers/gpu/drm/i915/i915_irq.c  | 26 +---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 69 ++--
 drivers/gpu/drm/i915/intel_engine_cs.c   |  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  6 +--
 6 files changed, 56 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index f62285c1ed7f..96bfc745a820 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -787,8 +787,6 @@ static void i915_ring_seqno_info(struct seq_file *m,
 
seq_printf(m, "Current sequence (%s): %x\n",
   engine->name, intel_engine_get_seqno(engine));
-   seq_printf(m, "Current user interrupts (%s): %lx\n",
-  engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
 
spin_lock(>lock);
for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {
@@ -1434,11 +1432,10 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
   engine->hangcheck.seqno,
   seqno[id],
   engine->last_submitted_seqno);
-   seq_printf(m, "\twaiters? %d\n",
-  intel_engine_has_waiter(engine));
-   seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
-  engine->hangcheck.user_interrupts,
-  READ_ONCE(engine->breadcrumbs.irq_wakeups));
+   seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
+  yesno(intel_engine_has_waiter(engine)),
+  yesno(test_bit(engine->id,
+ 
_priv->gpu_error.missed_irq_rings)));
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
   (long long)engine->hangcheck.acthd,
   (long long)acthd[id]);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0478e4610da4..c3652e09d272 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2524,7 +2524,6 @@ i915_gem_idle_work_handler(struct work_struct *work)
container_of(work, typeof(*dev_priv), gt.idle_work.work);
struct drm_device *dev = _priv->drm;
struct intel_engine_cs *engine;
-   unsigned int stuck_engines;
bool rearm_hangcheck;
 
if (!READ_ONCE(dev_priv->gt.awake))
@@ -2554,15 +2553,6 @@ i915_gem_idle_work_handler(struct work_struct *work)
dev_priv->gt.awake = false;
rearm_hangcheck = false;
 
-   /* As we have disabled hangcheck, we need to unstick any waiters still
-* hanging around. However, as we may be racing against the interrupt
-* handler or the waiters themselves, we skip enabling the fake-irq.
-*/
-   stuck_engines = intel_kick_waiters(dev_priv);
-   if (unlikely(stuck_engines))
-   DRM_DEBUG_DRIVER("kicked stuck waiters (%x)...missed irq?\n",
-stuck_engines);
-
if (INTEL_GEN(dev_priv) >= 6)
gen6_rps_idle(dev_priv);
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 591f452ece68..ebb83d5a448b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -972,10 +972,8 @@ static void ironlake_rps_change_irq_handler(struct 
drm_i915_private *dev_priv)
 static void notify_ring(struct intel_engine_cs *engine)
 {

[Intel-gfx] [CI 3/3] drm/i915: Use RCU to annotate and enforce protection for breadcrumb's bh

[Chris Wilson]

The bottom-half we use for processing the breadcrumb interrupt is a
task, which is an RCU protected struct. When accessing this struct, we
need to be holding the RCU read lock to prevent it disappearing beneath
us. We can use the RCU annotation to mark our irq_seqno_bh pointer as
being under RCU guard and then use the RCU accessors to both provide
correct ordering of access through the pointer.

Most notably, this fixes the access from hard irq context to use the RCU
read lock, which both Daniel and Tvrtko complained about.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Cc: Tvrtko Ursulin 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 22 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  2 --
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 25 -
 4 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54f789c75aa1..2cb91ffbbfa2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3849,7 +3849,7 @@ static inline bool __i915_request_irq_complete(struct 
drm_i915_gem_request *req)
 * is woken.
 */
if (engine->irq_seqno_barrier &&
-   READ_ONCE(engine->breadcrumbs.irq_seqno_bh) == current &&
+   rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
cmpxchg_relaxed(>breadcrumbs.irq_posted, 1, 0)) {
struct task_struct *tsk;
 
@@ -3874,7 +3874,7 @@ static inline bool __i915_request_irq_complete(struct 
drm_i915_gem_request *req)
 * irq_posted == false but we are still running).
 */
rcu_read_lock();
-   tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh);
+   tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
if (tsk && tsk != current)
/* Note that if the bottom-half is changed as we
 * are sending the wake-up, the new bottom-half will
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 7be9af1d5424..2491e4c1eaf0 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -71,10 +71,8 @@ static void intel_breadcrumbs_fake_irq(unsigned long data)
 * every jiffie in order to kick the oldest waiter to do the
 * coherent seqno check.
 */
-   rcu_read_lock();
if (intel_engine_wakeup(engine))
mod_timer(>breadcrumbs.fake_irq, jiffies + 1);
-   rcu_read_unlock();
 }
 
 static void irq_enable(struct intel_engine_cs *engine)
@@ -234,7 +232,7 @@ static bool __intel_engine_add_wait(struct intel_engine_cs 
*engine,
}
rb_link_node(>node, parent, p);
rb_insert_color(>node, >waiters);
-   GEM_BUG_ON(!first && !b->irq_seqno_bh);
+   GEM_BUG_ON(!first && !rcu_access_pointer(b->irq_seqno_bh));
 
if (completed) {
struct rb_node *next = rb_next(completed);
@@ -244,7 +242,7 @@ static bool __intel_engine_add_wait(struct intel_engine_cs 
*engine,
GEM_BUG_ON(first);
b->timeout = wait_timeout();
b->first_wait = to_wait(next);
-   smp_store_mb(b->irq_seqno_bh, b->first_wait->tsk);
+   rcu_assign_pointer(b->irq_seqno_bh, b->first_wait->tsk);
/* As there is a delay between reading the current
 * seqno, processing the completed tasks and selecting
 * the next waiter, we may have missed the interrupt
@@ -271,7 +269,7 @@ static bool __intel_engine_add_wait(struct intel_engine_cs 
*engine,
GEM_BUG_ON(rb_first(>waiters) != >node);
b->timeout = wait_timeout();
b->first_wait = wait;
-   smp_store_mb(b->irq_seqno_bh, wait->tsk);
+   rcu_assign_pointer(b->irq_seqno_bh, wait->tsk);
/* After assigning ourselves as the new bottom-half, we must
 * perform a cursory check to prevent a missed interrupt.
 * Either we miss the interrupt whilst programming the hardware,
@@ -282,7 +280,7 @@ static bool __intel_engine_add_wait(struct intel_engine_cs 
*engine,
 */
__intel_breadcrumbs_enable_irq(b);
}
-   GEM_BUG_ON(!b->irq_seqno_bh);
+   GEM_BUG_ON(!rcu_access_pointer(b->irq_seqno_bh));
GEM_BUG_ON(!b->first_wait);
GEM_BUG_ON(rb_first(>waiters) != >first_wait->node);
 
@@ -337,7 +335,7 @@ void intel_engine_remove_wait(struct intel_engine_cs 
*engine,
const int priority = wakeup_priority(b, wait->tsk);
struct rb_node 

[Intel-gfx] [CI 1/3] drm/i915: Always mark the writer as also a read for busy ioctl

[Chris Wilson]

One of the few guarantees we want the busy ioctl to provide is that the
reported busy writer is included in the set of busy read engines. This
should be provided by the ordering of setting and retiring the active
trackers, but we can do better by explicitly setting the busy read
engine flag for the last writer.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_gem.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d71fa9a93afa..0478e4610da4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3748,7 +3748,7 @@ static __always_inline unsigned int 
__busy_read_flag(unsigned int id)
 
 static __always_inline unsigned int __busy_write_id(unsigned int id)
 {
-   return id;
+   return id | __busy_read_flag(id);
 }
 
 static __always_inline unsigned int
@@ -3857,9 +3857,11 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
args->busy |= busy_check_reader(>last_read[idx]);
 
/* For ABI sanity, we only care that the write engine is in
-* the set of read engines. This is ensured by the ordering
-* of setting last_read/last_write in i915_vma_move_to_active,
-* and then in reverse in retire.
+* the set of read engines. This should be ensured by the
+* ordering of setting last_read/last_write in
+* i915_vma_move_to_active(), and then in reverse in retire.
+* However, for good measure, we always report the last_write
+* request as a busy read as well as being a busy write.
 *
 * We don't care that the set of active read/write engines
 * may change during construction of the result, as it is
-- 
2.8.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 02/20] drm/doc: Light drm-kms-helper.rst cleanup

[Sean Paul]

On Tue, Aug 9, 2016 at 9:41 AM, Daniel Vetter  wrote:
> - Move the common vtable stuff to the top
> - Move "Tile Group" to a more appropriate heading level
> - Throw away the old intro for the crtc helpers (it's entirely stale,
>   e.g. helpers have become modular years ago), and replace it with a
>   general intro about the motivation behind helpers.
> - Reorder helpers to group them together a bit better, and explain
>   that grouping in the intro.
> - Make sure the introductory DOC section is always first.
>
> Signed-off-by: Daniel Vetter 
> ---
>  Documentation/gpu/drm-kms-helpers.rst | 208 
> +-
>  drivers/gpu/drm/drm_kms_helper.c  |  66 +++
>  include/drm/drm_kms_helper.h  |  30 +
>  3 files changed, 200 insertions(+), 104 deletions(-)
>  create mode 100644 drivers/gpu/drm/drm_kms_helper.c
>  create mode 100644 include/drm/drm_kms_helper.h
>
> diff --git a/Documentation/gpu/drm-kms-helpers.rst 
> b/Documentation/gpu/drm-kms-helpers.rst
> index 0b302fedf1af..23458252f198 100644
> --- a/Documentation/gpu/drm-kms-helpers.rst
> +++ b/Documentation/gpu/drm-kms-helpers.rst
> @@ -2,38 +2,45 @@
>  Mode Setting Helper Functions
>  =
>
> -The plane, CRTC, encoder and connector functions provided by the drivers
> -implement the DRM API. They're called by the DRM core and ioctl handlers
> -to handle device state changes and configuration request. As
> -implementing those functions often requires logic not specific to
> -drivers, mid-layer helper functions are available to avoid duplicating
> -boilerplate code.
> -
> -The DRM core contains one mid-layer implementation. The mid-layer
> -provides implementations of several plane, CRTC, encoder and connector
> -functions (called from the top of the mid-layer) that pre-process
> -requests and call lower-level functions provided by the driver (at the
> -bottom of the mid-layer). For instance, the
> -:c:func:`drm_crtc_helper_set_config()` function can be used to
> -fill the :c:type:`struct drm_crtc_funcs `
> -set_config field. When called, it will split the set_config operation
> -in smaller, simpler operations and call the driver to handle them.
> -
> -To use the mid-layer, drivers call
> -:c:func:`drm_crtc_helper_add()`,
> -:c:func:`drm_encoder_helper_add()` and
> -:c:func:`drm_connector_helper_add()` functions to install their
> -mid-layer bottom operations handlers, and fill the :c:type:`struct
> -drm_crtc_funcs `, :c:type:`struct
> -drm_encoder_funcs ` and :c:type:`struct
> -drm_connector_funcs ` structures with
> -pointers to the mid-layer top API functions. Installing the mid-layer
> -bottom operation handlers is best done right after registering the
> -corresponding KMS object.
> -
> -The mid-layer is not split between CRTC, encoder and connector
> -operations. To use it, a driver must provide bottom functions for all of
> -the three KMS entities.
> +The DRM subsystem aims for a strong separation between core code and helper
> +libraries. Core code takes care of general setup and teardown and decoding
> +userspace requests to kernel internal objects. Everything else is handled by 
> a
> +large set of helper libraries, which can be combined freely to pick and 
> choose
> +for each driver what fits, and avoid shared code where special behaviour is
> +needed.
> +
> +This distinction between core code and helpers is especially strong in the
> +modesetting code, where there's a shared userspace ABI for all drivers. This 
> is
> +in contrast to the render side, where pretty much everything (with very few
> +exceptions) can be considered optional helper code.
> +
> +There are a few areas these helpers can grouped into:
> +
> +* Helpers to implement modesetting. This important ones here are the atomic

s/This important/The important/

> +  helpers. Old drivers still often use the legacy CRTC helpers. They both 
> share
> +  the same set of common helper vtables. For really simple drivers (anything
> +  that would have been a great fit in the deprecated fbdev subsystem) there's
> +  also the simple display pipe helpers.
> +
> +* There's a big pile of helpers for handling outputs. Firs the generic bridge

s/Firs/First,/

> +  helpers for handling encoder and transcoder IP blocks, and the panel 
> helpers

s/, and/. Second, /

I'm taking a bit of creative license, assuming this is what you're
trying to say :)

> +  for handling panel-related information and logic. Plus then a big set of
> +  helpers for the various sink standards (DisplayPort, HDMI, MIPI DSI). 
> Finally
> +  there's also generic helpers for handling output probing, and for dealing 
> with
> +  EDIDs.
> +
> +* The last group of helpers concerns itself with the frontend side of a 
> display
> +  pipeline: Planes, handling rectangles for visibility checking and 
> scissoring,
> +  flip queues and assorted bits.
> +
> +Modeset Helper Reference for Common Vtables
> 

[Intel-gfx] ✗ Ro.CI.BAT: failure for Enable upfront link training on DDI platforms

[Patchwork]

== Series Details ==

Series: Enable upfront link training on DDI platforms
URL   : https://patchwork.freedesktop.org/series/10821/
State : failure

== Summary ==

Applying: drm/i915: Don't pass crtc_state to intel_dp_set_link_params()
Applying: drm/i915: Remove ddi_pll_sel from intel_crtc_state
Applying: drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions
Applying: drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_ddi.c
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.
Applying: drm/i915/dp: Enable Upfront link training for typeC DP support on BXT
Applying: drm/i915: Split skl_get_dpll()
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_dpll_mgr.c
M   drivers/gpu/drm/i915/intel_dpll_mgr.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_dpll_mgr.h
Auto-merging drivers/gpu/drm/i915/intel_dpll_mgr.c
Applying: drm/i915/dp: Enable upfront link training on SKL
Applying: drm/i915: Split hsw_get_dpll()
fatal: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/intel_dpll_mgr.c).
error: could not build fake ancestor
Patch failed at 0008 drm/i915: Split hsw_get_dpll()
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 08/33] drm/i915: Move setting of request->batch into its single callsite

[Chris Wilson]

On Tue, Aug 09, 2016 at 06:53:16PM +0300, Mika Kuoppala wrote:
> Chris Wilson  writes:
> 
> > request->batch_obj is only set by execbuffer for the convenience of
> > debugging hangs. By moving that operation to the callsite, we can
> > simplify all other callers and future patches. We also move the
> > complications of reference handling of the request->batch_obj next to
> > where the active tracking is set up for the request.
> >
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +-
> >  drivers/gpu/drm/i915/i915_gem_request.c| 12 +---
> >  drivers/gpu/drm/i915/i915_gem_request.h|  8 +++-
> >  3 files changed, 13 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
> > b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > index c494b79ded20..c8d13fea4b25 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > @@ -1702,6 +1702,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, void 
> > *data,
> > goto err_batch_unpin;
> > }
> >  
> > +   /* Whilst this request exists, batch_obj will be on the
> > +* active_list, and so will hold the active reference. Only when this
> > +* request is retired will the the batch_obj be moved onto the
> > +* inactive_list and lose its active reference. Hence we do not need
> > +* to explicitly hold another reference here.
> > +*/
> 
> The comment here might or might not need revisiting. I can't say yet.

That's still true. Active objects have a reference that prevents them
from being freed whilst in use by the GPU - currently managed by
i915_gem_object_retire__read() iirc.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI] drm/i915: Correct typo for __i915_gem_active_get_rcu in a comment

[Chris Wilson]

I mistyped and added an extra _request_ to __i915_gem_active_get_rcu()
Also, the same happened to another comment for i915_gem_active_get_rcu()

Reported-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 06d1267e733d..76314e527cfd 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -360,7 +360,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
 * We use RCU to look up requests in flight. The lookups may
 * race with the request being allocated from the slab freelist.
 * That is the request we are writing to here, may be in the process
-* of being read by __i915_gem_active_get_request_rcu(). As such,
+* of being read by __i915_gem_active_get_rcu(). As such,
 * we have to be very careful when overwriting the contents. During
 * the RCU lookup, we change chase the request->engine pointer,
 * read the request->fence.seqno and increment the reference count.
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 43e545e44352..bf9a6e56e719 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -310,7 +310,7 @@ struct intel_engine_cs {
 
/* An RCU guarded pointer to the last request. No reference is
 * held to the request, users must carefully acquire a reference to
-* the request using i915_gem_active_get_request_rcu(), or hold the
+* the request using i915_gem_active_get_rcu(), or hold the
 * struct_mutex.
 */
struct i915_gem_active last_request;
-- 
2.8.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] include/drm/i915_drm.h:96: possible bad bitmask ?

[Dave Gordon]

On 09/08/16 03:59, Dave Airlie wrote:

On 8 August 2016 at 19:40, Daniel Vetter  wrote:

On Mon, Aug 08, 2016 at 10:31:32AM +0100, David Binderman wrote:

Hello there,

Recent versions of gcc say this:

include/drm/i915_drm.h:96:34: warning: result of ‘65535 << 20’
requires 37 bits to represent, but ‘int’ only has 32 bits
[-Wshift-overflow=]

Source code is

#define   INTEL_BSM_MASK (0x << 20)

Maybe something like

#define   INTEL_BSM_MASK (0xUL<< 20)

might be better.


Yup. Care to bake this into a patch (with s-o-b and everything per
Documentation/SubmittingPatches) so I can apply it?


Why would you want to apply a clearly incorrect patch :-)

INTEL_BSM_MASK is used in one place, on a 32-bit number

I'm not sure what it needs to be, but a 64-bit number it doesn't.

Dave.


I found two uses, but in both cases it's masking a value read
from a 32-bit PCI register, so it can just be (-(1 << 20)).

.Dave.

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Use connector atomic state in encoders.

[Patchwork]

== Series Details ==

Series: drm/i915: Use connector atomic state in encoders.
URL   : https://patchwork.freedesktop.org/series/10853/
State : failure

== Summary ==

Applying: drm/i915: handle DP_MST correctly in bxt_get_dpll
Applying: drm/i915: Pass atomic state to crtc enable/disable functions
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_drv.h
M   drivers/gpu/drm/i915/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Applying: drm/i915: Remove unused mode_set hook from encoder
Applying: drm/i915: Walk over encoders in crtc enable/disable using atomic 
state.
Applying: drm/i915: Pass crtc_state and connector_state to encoder functions
fatal: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/intel_display.c).
error: could not build fake ancestor
Patch failed at 0005 drm/i915: Pass crtc_state and connector_state to encoder 
functions
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 08/33] drm/i915: Move setting of request->batch into its single callsite

[Mika Kuoppala]

Chris Wilson  writes:

> request->batch_obj is only set by execbuffer for the convenience of
> debugging hangs. By moving that operation to the callsite, we can
> simplify all other callers and future patches. We also move the
> complications of reference handling of the request->batch_obj next to
> where the active tracking is set up for the request.
>
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +-
>  drivers/gpu/drm/i915/i915_gem_request.c| 12 +---
>  drivers/gpu/drm/i915/i915_gem_request.h|  8 +++-
>  3 files changed, 13 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index c494b79ded20..c8d13fea4b25 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1702,6 +1702,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, void 
> *data,
>   goto err_batch_unpin;
>   }
>  
> + /* Whilst this request exists, batch_obj will be on the
> +  * active_list, and so will hold the active reference. Only when this
> +  * request is retired will the the batch_obj be moved onto the
> +  * inactive_list and lose its active reference. Hence we do not need
> +  * to explicitly hold another reference here.
> +  */

The comment here might or might not need revisiting. I can't say yet.

But when I tried to learn how the current code works, I found
that there are comments referencing __i915_gem_active_get_request_rcu()
which does not exist.

-Mika

> + params->request->batch_obj = params->batch->obj;
> +
>   ret = i915_gem_request_add_to_client(params->request, file);
>   if (ret)
>   goto err_request;
> @@ -1720,7 +1728,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void 
> *data,
>  
>   ret = execbuf_submit(params, args, >vmas);
>  err_request:
> - __i915_add_request(params->request, params->batch->obj, ret == 0);
> + __i915_add_request(params->request, ret == 0);
>  
>  err_batch_unpin:
>   /*
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
> b/drivers/gpu/drm/i915/i915_gem_request.c
> index b7ffde002a62..c6f523e2879c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -461,9 +461,7 @@ static void i915_gem_mark_busy(const struct 
> intel_engine_cs *engine)
>   * request is not being tracked for completion but the work itself is
>   * going to happen on the hardware. This would be a Bad Thing(tm).
>   */
> -void __i915_add_request(struct drm_i915_gem_request *request,
> - struct drm_i915_gem_object *obj,
> - bool flush_caches)
> +void __i915_add_request(struct drm_i915_gem_request *request, bool 
> flush_caches)
>  {
>   struct intel_engine_cs *engine;
>   struct intel_ring *ring;
> @@ -504,14 +502,6 @@ void __i915_add_request(struct drm_i915_gem_request 
> *request,
>  
>   request->head = request_start;
>  
> - /* Whilst this request exists, batch_obj will be on the
> -  * active_list, and so will hold the active reference. Only when this
> -  * request is retired will the the batch_obj be moved onto the
> -  * inactive_list and lose its active reference. Hence we do not need
> -  * to explicitly hold another reference here.
> -  */
> - request->batch_obj = obj;
> -
>   /* Seal the request and mark it as pending execution. Note that
>* we may inspect this state, without holding any locks, during
>* hangcheck. Hence we apply the barrier to ensure that we do not
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.h 
> b/drivers/gpu/drm/i915/i915_gem_request.h
> index 721eb8cbce9b..d5176f9cc22f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.h
> +++ b/drivers/gpu/drm/i915/i915_gem_request.h
> @@ -225,13 +225,11 @@ static inline void i915_gem_request_assign(struct 
> drm_i915_gem_request **pdst,
>   *pdst = src;
>  }
>  
> -void __i915_add_request(struct drm_i915_gem_request *req,
> - struct drm_i915_gem_object *batch_obj,
> - bool flush_caches);
> +void __i915_add_request(struct drm_i915_gem_request *req, bool flush_caches);
>  #define i915_add_request(req) \
> - __i915_add_request(req, NULL, true)
> + __i915_add_request(req, true)
>  #define i915_add_request_no_flush(req) \
> - __i915_add_request(req, NULL, false)
> + __i915_add_request(req, false)
>  
>  struct intel_rps_client;
>  #define NO_WAITBOOST ERR_PTR(-1)
> -- 
> 2.8.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org

Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for Accommodate multiple GuC submission clients

[Dave Gordon]

On 09/08/16 15:55, Patchwork wrote:

== Series Details ==

Series: Accommodate multiple GuC submission clients
URL   : https://patchwork.freedesktop.org/series/10847/
State : failure

== Summary ==

Series 10847v1 Accommodate multiple GuC submission clients
http://patchwork.freedesktop.org/api/1.0/series/10847/revisions/1/mbox

Test drv_module_reload_basic:
pass   -> DMESG-WARN (ro-skl3-i5-6260u)


This machine is missing (the correct version of) the GuC firmware!


Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (ro-byt-n2820)


Bug 95236 - [BAT various] kms_flip fails with "inter-flip ts jitter: 0s, 
183334usec" or similar time around 180msec


.Dave.


fi-hsw-i7-4770k  total:107  pass:91   dwarn:0   dfail:0   fail:0   skip:15
fi-kbl-qkkr  total:107  pass:83   dwarn:0   dfail:0   fail:0   skip:23
fi-skl-i5-6260u  total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8
fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22
fi-snb-i7-2600   total:107  pass:77   dwarn:0   dfail:0   fail:0   skip:29
ro-bdw-i5-5250u  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9
ro-bdw-i7-5600u  total:107  pass:79   dwarn:0   dfail:0   fail:0   skip:27
ro-bsw-n3050 total:240  pass:194  dwarn:0   dfail:0   fail:4   skip:42
ro-byt-n2820 total:240  pass:196  dwarn:0   dfail:0   fail:4   skip:40
ro-hsw-i3-4010u  total:107  pass:87   dwarn:0   dfail:0   fail:0   skip:19
ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2   skip:60
ro-ivb-i7-3770   total:107  pass:80   dwarn:0   dfail:0   fail:0   skip:26
ro-skl3-i5-6260u total:107  pass:97   dwarn:1   dfail:0   fail:0   skip:8
ro-bdw-i7-5557U failed to connect after reboot
ro-hsw-i7-4770r failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1785/

e220d47 drm-intel-nightly: 2016y-08m-09d-09h-18m-12s UTC integration manifest
f93075d NOMERGE: re-enable GuC loading and submission by default
9fba995 drm/i915/guc: re-optimise i915_guc_client layout
64c9f76 drm/i915/guc: use for_each_engine_id() where appropriate
550dfa4 drm/i915/guc: add engine mask to GuC client & pass to GuC
fa78cb8 drm/i915/guc: refactor guc_init_doorbell_hw()
b194fc6 drm/i915/guc: doorbell reset should avoid used doorbells



___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Ro.CI.BAT: warning for drm/i915/guc: use symbolic names for module parameter values (rev2)

[Dave Gordon]

On 09/08/16 12:25, Patchwork wrote:

== Series Details ==

Series: drm/i915/guc: use symbolic names for module parameter values (rev2)
URL   : https://patchwork.freedesktop.org/series/10188/
State : warning

== Summary ==

Series 10188v2 drm/i915/guc: use symbolic names for module parameter values
http://patchwork.freedesktop.org/api/1.0/series/10188/revisions/2/mbox

Test drv_module_reload_basic:
pass   -> DMESG-WARN (fi-hsw-i7-4770k)


The RCU-related recursive locking already mentioned by Ville, and under 
investigation elsewhere.



pass   -> DMESG-WARN (ro-skl3-i5-6260u)


This machine is missing (the correct version of) the GuC firmware!

.Dave.


fi-hsw-i7-4770k  total:107  pass:90   dwarn:1   dfail:0   fail:0   skip:15
fi-kbl-qkkr  total:107  pass:83   dwarn:1   dfail:0   fail:0   skip:22
fi-skl-i5-6260u  total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8
fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22
fi-snb-i7-2600   total:107  pass:77   dwarn:0   dfail:0   fail:0   skip:29
ro-bdw-i5-5250u  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9
ro-bdw-i7-5557U  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9
ro-bdw-i7-5600u  total:107  pass:79   dwarn:0   dfail:0   fail:0   skip:27
ro-bsw-n3050 total:240  pass:194  dwarn:0   dfail:0   fail:4   skip:42
ro-byt-n2820 total:240  pass:197  dwarn:0   dfail:0   fail:3   skip:40
ro-hsw-i3-4010u  total:107  pass:87   dwarn:0   dfail:0   fail:0   skip:19
ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2   skip:60
ro-ivb-i7-3770   total:107  pass:80   dwarn:0   dfail:0   fail:0   skip:26
ro-skl3-i5-6260u total:107  pass:97   dwarn:1   dfail:0   fail:0   skip:8
ro-hsw-i7-4770r failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1777/

e220d47 drm-intel-nightly: 2016y-08m-09d-09h-18m-12s UTC integration manifest
c47d6cf drm/i915/guc: ignore unrecognised loading & submission options
32f71df drm/i915/guc: use symbolic names in setting defaults for module 
parameters
449ee3e drm/i915/guc: symbolic name for GuC log-level none
ec2cf78 drm/i915/guc: symbolic names for GuC firmare loading preferences
1a3ec82 drm/i915/guc: symbolic names for GuC submission preferences



___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI] mm/slub: Run free_partial() outside of the kmem_cache_node->list_lock

[Chris Wilson]

With debugobjects enabled and using SLAB_DESTROY_BY_RCU, when a
kmem_cache_node is destroyed the call_rcu() may trigger a slab
allocation to fill the debug object pool (__debug_object_init:fill_pool).
Everywhere but during kmem_cache_destroy(), discard_slab() is performed
outside of the kmem_cache_node->list_lock and avoids a lockdep warning
about potential recursion:

[  138.850350] =
[  138.850352] [ INFO: possible recursive locking detected ]
[  138.850355] 4.8.0-rc1-gfxbench+ #1 Tainted: G U
[  138.850357] -
[  138.850359] rmmod/8895 is trying to acquire lock:
[  138.850360]  (&(>list_lock)->rlock){-.-...}, at: [] 
get_partial_node.isra.63+0x47/0x430
[  138.850368]
   but task is already holding lock:
[  138.850371]  (&(>list_lock)->rlock){-.-...}, at: [] 
__kmem_cache_shutdown+0x54/0x320
[  138.850376]
   other info that might help us debug this:
[  138.850378]  Possible unsafe locking scenario:

[  138.850380]CPU0
[  138.850381]
[  138.850382]   lock(&(>list_lock)->rlock);
[  138.850385]   lock(&(>list_lock)->rlock);
[  138.850387]
*** DEADLOCK ***

[  138.850391]  May be due to missing lock nesting notation

[  138.850395] 5 locks held by rmmod/8895:
[  138.850397]  #0:  (>mutex){..}, at: [] 
driver_detach+0x42/0xc0
[  138.850404]  #1:  (>mutex){..}, at: [] 
driver_detach+0x50/0xc0
[  138.850410]  #2:  (cpu_hotplug.dep_map){++}, at: [] 
get_online_cpus+0x2d/0x80
[  138.850418]  #3:  (slab_mutex){+.+.+.}, at: [] 
kmem_cache_destroy+0x3c/0x220
[  138.850424]  #4:  (&(>list_lock)->rlock){-.-...}, at: 
[] __kmem_cache_shutdown+0x54/0x320
[  138.850431]
   stack backtrace:
[  138.850435] CPU: 6 PID: 8895 Comm: rmmod Tainted: G U  
4.8.0-rc1-gfxbench+ #1
[  138.850439] Hardware name: Gigabyte Technology Co., Ltd. H87M-D3H/H87M-D3H, 
BIOS F11 08/18/2015
[  138.850443]   880179b93800 814221f5 
8801d1e5ce40
[  138.850449]  827c6dd0 880179b938c0 810d48a6 
00ff
[  138.850454]  88017990d900 880179b93930 d445 
a70e0e46e14b0709
[  138.850459] Call Trace:
[  138.850463]  [] dump_stack+0x67/0x92
[  138.850467]  [] __lock_acquire+0x1646/0x1ad0
[  138.850492]  [] ? i915_exit+0x1a/0x1e2 [i915]
[  138.850509]  [] lock_acquire+0xb2/0x200
[  138.850512]  [] ? get_partial_node.isra.63+0x47/0x430
[  138.850516]  [] _raw_spin_lock+0x36/0x50
[  138.850519]  [] ? get_partial_node.isra.63+0x47/0x430
[  138.850522]  [] get_partial_node.isra.63+0x47/0x430
[  138.850543]  [] ? __module_address+0x27/0xf0
[  138.850558]  [] ? i915_exit+0x1a/0x1e2 [i915]
[  138.850561]  [] ? __module_text_address+0xd/0x60
[  138.850565]  [] ? is_module_text_address+0x2a/0x50
[  138.850568]  [] ? __kernel_text_address+0x31/0x80
[  138.850572]  [] ? print_context_stack+0x79/0xd0
[  138.850575]  [] ? dump_trace+0x124/0x300
[  138.850579]  [] ___slab_alloc.constprop.67+0x1a7/0x3b0
[  138.850582]  [] ? __debug_object_init+0x2de/0x400
[  138.850586]  [] ? 
add_lock_to_list.isra.22.constprop.41+0x77/0xc0
[  138.850590]  [] ? __lock_acquire+0x13ae/0x1ad0
[  138.850594]  [] ? __debug_object_init+0x2de/0x400
[  138.850597]  [] __slab_alloc.isra.64.constprop.66+0x43/0x80
[  138.850601]  [] kmem_cache_alloc+0x236/0x2d0
[  138.850604]  [] ? __debug_object_init+0x2de/0x400
[  138.850607]  [] __debug_object_init+0x2de/0x400
[  138.850611]  [] debug_object_activate+0x109/0x1e0
[  138.850614]  [] ? slab_cpuup_callback+0x100/0x100
[  138.850618]  [] __call_rcu.constprop.63+0x32/0x2f0
[  138.850621]  [] call_rcu+0x12/0x20
[  138.850624]  [] discard_slab+0x3d/0x40
[  138.850627]  [] __kmem_cache_shutdown+0xdb/0x320
[  138.850631]  [] ? kmem_cache_destroy+0x3c/0x220
[  138.850634]  [] shutdown_cache+0x19/0x60
[  138.850638]  [] kmem_cache_destroy+0x1ae/0x220
[  138.850650]  [] i915_gem_load_cleanup+0x14/0x40 [i915]
[  138.850660]  [] i915_driver_unload+0x151/0x180 [i915]
[  138.850670]  [] i915_pci_remove+0x14/0x20 [i915]
[  138.850673]  [] pci_device_remove+0x34/0xb0
[  138.850677]  [] __device_release_driver+0x95/0x140
[  138.850680]  [] driver_detach+0xb6/0xc0
[  138.850683]  [] bus_remove_driver+0x53/0xd0
[  138.850687]  [] driver_unregister+0x27/0x50
[  138.850689]  [] pci_unregister_driver+0x25/0x70
[  138.850704]  [] i915_exit+0x1a/0x1e2 [i915]
[  138.850707]  [] SyS_delete_module+0x193/0x1f0
[  138.850711]  [] entry_SYSCALL_64_fastpath+0x1c/0xac

v2: Keep remove_partial() under the lock, just move discard_slab()
outside the lock.

Fixes: 52b4b950b507 ("mm: slab: free kmem_cache_node after destroy sysfs file")
Reported-by: Dave Gordon 
Signed-off-by: Chris Wilson 
Cc: Christoph Lameter 
Cc: Pekka Enberg 
Cc: David Rientjes 
Cc: Joonsoo Kim 
Cc: Andrew Morton 

Re: [Intel-gfx] [PATCH v3] drm/i915: Move missed interrupt detection from hangcheck to breadcrumbs

[Mika Kuoppala]

Chris Wilson  writes:

> In commit 2529d57050af ("drm/i915: Drop racy markup of missed-irqs from
> idle-worker") the racy detection of missed interrupts was removed when
> we went idle. This however opened up the issue that the stuck waiters
> were not being reported, causing a test case failure. If we move the
> stuck waiter detection out of hangcheck and into the breadcrumb
> mechanims (i.e. the waiter) itself, we can avoid this issue entirely.
> This leaves hangcheck looking for a stuck GPU (inspecting for request
> advancement and HEAD motion), and breadcrumbs looking for a stuck
> waiter - hopefully make both easier to understand by their segregation.
>
> v2: Reduce the error message as we now run independently of hangcheck,
> and the hanging batch used by igt also counts as a stuck waiter causing
> extra warnings in dmesg.
> v3: Move the breadcrumb's hangcheck kickstart to the first missed wait.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97104
> Fixes: 2529d57050af (waiter"drm/i915: Drop racy markup of missed-irqs...")
> Testcase: igt/drv_missed_irq
> Signed-off-by: Chris Wilson 

Reviewed-by: Mika Kuoppala 

> Cc: Joonas Lahtinen 
> Cc: Tvrtko Ursulin 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  | 11 ++---
>  drivers/gpu/drm/i915/i915_gem.c  | 10 -
>  drivers/gpu/drm/i915/i915_irq.c  | 26 +---
>  drivers/gpu/drm/i915/intel_breadcrumbs.c | 69 
> ++--
>  drivers/gpu/drm/i915/intel_engine_cs.c   |  1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.h  |  6 +--
>  6 files changed, 56 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index f62285c1ed7f..96bfc745a820 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -787,8 +787,6 @@ static void i915_ring_seqno_info(struct seq_file *m,
>  
>   seq_printf(m, "Current sequence (%s): %x\n",
>  engine->name, intel_engine_get_seqno(engine));
> - seq_printf(m, "Current user interrupts (%s): %lx\n",
> -engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
>  
>   spin_lock(>lock);
>   for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {
> @@ -1434,11 +1432,10 @@ static int i915_hangcheck_info(struct seq_file *m, 
> void *unused)
>  engine->hangcheck.seqno,
>  seqno[id],
>  engine->last_submitted_seqno);
> - seq_printf(m, "\twaiters? %d\n",
> -intel_engine_has_waiter(engine));
> - seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
> -engine->hangcheck.user_interrupts,
> -READ_ONCE(engine->breadcrumbs.irq_wakeups));
> + seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
> +yesno(intel_engine_has_waiter(engine)),
> +yesno(test_bit(engine->id,
> +   
> _priv->gpu_error.missed_irq_rings)));
>   seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
>  (long long)engine->hangcheck.acthd,
>  (long long)acthd[id]);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index d71fa9a93afa..2bb9ef91a243 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2524,7 +2524,6 @@ i915_gem_idle_work_handler(struct work_struct *work)
>   container_of(work, typeof(*dev_priv), gt.idle_work.work);
>   struct drm_device *dev = _priv->drm;
>   struct intel_engine_cs *engine;
> - unsigned int stuck_engines;
>   bool rearm_hangcheck;
>  
>   if (!READ_ONCE(dev_priv->gt.awake))
> @@ -2554,15 +2553,6 @@ i915_gem_idle_work_handler(struct work_struct *work)
>   dev_priv->gt.awake = false;
>   rearm_hangcheck = false;
>  
> - /* As we have disabled hangcheck, we need to unstick any waiters still
> -  * hanging around. However, as we may be racing against the interrupt
> -  * handler or the waiters themselves, we skip enabling the fake-irq.
> -  */
> - stuck_engines = intel_kick_waiters(dev_priv);
> - if (unlikely(stuck_engines))
> - DRM_DEBUG_DRIVER("kicked stuck waiters (%x)...missed irq?\n",
> -  stuck_engines);
> -
>   if (INTEL_GEN(dev_priv) >= 6)
>   gen6_rps_idle(dev_priv);
>   intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 591f452ece68..ebb83d5a448b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -972,10 +972,8 @@ static 

[Intel-gfx] ✓ Ro.CI.BAT: success for Picture aspect ratio support in DRM layer

[Patchwork]

== Series Details ==

Series: Picture aspect ratio support in DRM layer
URL   : https://patchwork.freedesktop.org/series/10849/
State : success

== Summary ==

Series 10849v1 Picture aspect ratio support in DRM layer
http://patchwork.freedesktop.org/api/1.0/series/10849/revisions/1/mbox


fi-hsw-i7-4770k  total:107  pass:91   dwarn:0   dfail:0   fail:0   skip:15 
fi-kbl-qkkr  total:107  pass:82   dwarn:1   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8  
fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22 
fi-snb-i7-2600   total:107  pass:77   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i5-5250u  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9  
ro-bdw-i7-5600u  total:107  pass:79   dwarn:0   dfail:0   fail:0   skip:27 
ro-byt-n2820 total:240  pass:197  dwarn:0   dfail:0   fail:3   skip:40 
ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2   skip:60 
ro-ivb-i7-3770   total:107  pass:80   dwarn:0   dfail:0   fail:0   skip:26 
ro-skl3-i5-6260u total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8  
ro-bsw-n3050 failed to connect after reboot
ro-hsw-i3-4010u failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1786/

e220d47 drm-intel-nightly: 2016y-08m-09d-09h-18m-12s UTC integration manifest
61c0ca7 drm: Add and handle new aspect ratios in DRM layer
44a1120 video: Add new aspect ratios for HDMI 2.0
ebfc992 drm: Add aspect ratio parsing in DRM layer
8d3d607 drm: add picture aspect ratio flags

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Apply the PPS register unlock workaround more consistently

[Imre Deak]

On ti, 2016-08-09 at 16:01 +0300, Ville Syrjälä wrote:
> On Tue, Aug 09, 2016 at 02:34:11PM +0300, Imre Deak wrote:
> > Atm, we apply this workaround somewhat inconsistently at the following
> > points: driver loading, LVDS init, eDP PPS init, system resume. As this
> > workaround also affects registers other than PPS (timing, PLL) a more
> > consistent way is to apply it early after the PPS HW context is known to
> > be lost: driver loading, system resume and on VLV/CHV/BXT when turning
> > on power domains.
> > 
> > This is needed by the next patch that removes saving/restoring of the
> > PP_CONTROL register.
> > 
> > This also removes the incorrect programming of the workaround on HSW+
> > PCH platforms which don't have the register locking mechanism.
> > 
> > Signed-off-by: Imre Deak 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c |  1 +
> >  drivers/gpu/drm/i915/intel_display.c| 28 
> >  drivers/gpu/drm/i915/intel_dp.c |  4 +++-
> >  drivers/gpu/drm/i915/intel_drv.h|  1 +
> >  drivers/gpu/drm/i915/intel_lvds.c   |  8 
> >  drivers/gpu/drm/i915/intel_runtime_pm.c |  4 
> >  6 files changed, 37 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 8cfc264..0fcd1c0 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1560,6 +1560,7 @@ static int i915_drm_resume(struct drm_device *dev)
> >     i915_gem_resume(dev);
> >  
> >     i915_restore_state(dev);
> > +   intel_pps_unlock_regs_wa(dev_priv);
> >     intel_opregion_setup(dev_priv);
> >  
> >     intel_init_pch_refclk(dev);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 3d5fd06..dc4e600 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -14635,6 +14635,32 @@ static bool intel_crt_present(struct drm_device 
> > *dev)
> >     return true;
> >  }
> >  
> > +void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
> > +{
> > +   int pps_num;
> > +   int pps_idx;
> > +
> > +   /*
> > +    * This w/a is needed at least on CPT/PPT, but to be sure apply it
> > +    * everywhere where registers can be write protected.
> > +    */
> > +   if (INTEL_GEN(dev_priv) <= 4 ||
> > +   HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> > +   pps_num = 1;
> > +   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > +    IS_BROXTON(dev_priv))
> > +   pps_num = 2;
> > +   else
> > +   pps_num = 0;
> 
> BXT shouldn't need the unlock, I think.

Yes, got that wrong.

> 
> So I believe we just want
> 
> if (HAS_DDI())
>   return;
> 
> if (VLV||CHV)
>   num = 2;
> else
>   num = 1;

Ok.

> 
> > +
> > +   for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
> > +   u32 val = I915_READ(PP_CONTROL(pps_idx));
> > +
> > +   val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
> > +   I915_WRITE(PP_CONTROL(pps_idx), val);
> > +   }
> > +}
> > +
> >  static void intel_pps_init(struct drm_i915_private *dev_priv)
> >  {
> >     if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
> > @@ -14643,6 +14669,8 @@ static void intel_pps_init(struct drm_i915_private 
> > *dev_priv)
> >     dev_priv->pps_mmio_base = VLV_PPS_BASE;
> >     else
> >     dev_priv->pps_mmio_base = PPS_BASE;
> > +
> > +   intel_pps_unlock_regs_wa(dev_priv);
> >  }
> >  
> >  static void intel_setup_outputs(struct drm_device *dev)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 76f5b72..b27f1c5 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1829,7 +1829,9 @@ static  u32 ironlake_get_pp_control(struct intel_dp 
> > *intel_dp)
> >     lockdep_assert_held(_priv->pps_mutex);
> >  
> >     control = I915_READ(_pp_ctrl_reg(intel_dp));
> > -   if (!IS_BROXTON(dev)) {
> > +   if (WARN_ON((HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
> > +    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> 
> !HAS_DDI

Heh, was thinking of a shorter way, but this didn't occur to me. Will
change it.

> 
> > +    (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
> >     control &= ~PANEL_UNLOCK_MASK;
> >     control |= PANEL_UNLOCK_REGS;
> >     }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index c29a429..cbce786 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1159,6 +1159,7 @@ void intel_mark_busy(struct drm_i915_private 
> > *dev_priv);
> >  void intel_mark_idle(struct drm_i915_private *dev_priv);
> >  void intel_crtc_restore_mode(struct drm_crtc *crtc);
> >  int intel_display_suspend(struct drm_device *dev);
> > +void intel_pps_unlock_regs_wa(struct 

Re: [Intel-gfx] [PATCH 4/6] drm/i915/dp: Restore PPS HW state from the encoder resume hook

[Imre Deak]

On ti, 2016-08-09 at 15:52 +0300, Ville Syrjälä wrote:
> On Tue, Aug 09, 2016 at 02:34:10PM +0300, Imre Deak wrote:
> > Similarly to the previous patch, initialize the PPS from the DP
> > encoder's resume hook. Note that as opposed to LVDS we can't do this
> > during encoder enabling, since we need the PPS for DP detection as well.
> > 
> > Signed-off-by: Imre Deak 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 4796ad7..76f5b72 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4665,6 +4665,9 @@ void intel_dp_encoder_reset(struct drm_encoder 
> > *encoder)
> >      */
> >     if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
> >     vlv_initial_power_sequencer_setup(intel_dp);
> > +   else
> > +   intel_dp_init_panel_power_sequencer_registers(encoder->dev,
> > +     intel_dp);
> 
> This is almosts the same code as we have in intel_edp_init_connector(),
> excep not calling intel_dp_init_panel_power_sequencer() for !VLV/CHV.
> 
> intel_dp_init_panel_power_sequencer() should be safe to call multiple
> times since it checks if things were already initialized, and we already
> call it here for VLV/CHV. So I think we should just be able share the
> code for init and resume?

Ok, can factor these out to a new helper. Btw, would it make sense to
call intel_dp_init_panel_power_sequencer_registers()
from intel_dp_init_panel_power() directly, they are not called
separately any more.

> 
> >  
> >     intel_edp_panel_vdd_sanitize(intel_dp);
> >  
> > -- 
> > 2.5.0
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 03/15] drm/i915: Remove unused mode_set hook from encoder

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_drv.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1ad2e2c5f580..0e53cc1fd5cc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -198,7 +198,6 @@ struct intel_encoder {
void (*pre_pll_enable)(struct intel_encoder *);
void (*pre_enable)(struct intel_encoder *);
void (*enable)(struct intel_encoder *);
-   void (*mode_set)(struct intel_encoder *intel_encoder);
void (*disable)(struct intel_encoder *);
void (*post_disable)(struct intel_encoder *);
void (*post_pll_disable)(struct intel_encoder *);
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 0/4] drm/i915: Maarten's pre-g4x GPU reset regression fix + other reset stuff

[Ville Syrjälä]

On Fri, Aug 05, 2016 at 11:28:26PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> I got annoyed at the pre-g4x gpu reset regression again, so I
> picked up the latest (I think it was the latest anyway) version of
> Maarten's locking fix from the list and rebased it. I also changed
> one comment in there about mode_config.mutex as the original didn't
> make sense to me.
> 
> I tossed in a few polishing patches on top, and tested the whole lot
> on my 946gz, and I also ran it on hsw w/ and w/o the new modparam set.
> No problems whatsoever.
> 
> Maarten Lankhorst (2):
>   drm/i915: Fix modeset handling during gpu reset, v5.
>   drm/i915: Add a way to test the modeset done during gpu reset, v3.
> 
> Ville Syrjälä (2):
>   drm/i915: Introduce gpu_reset_clobbers_display()
>   drm/i915: Use the g4x+ approach on gen2 for handling display stuff
> around GPU reset

Entire series pushed to dinq. Thanks for the patches and reviews.

Maarten, did you have the igt for utilizing the new module param around
somewhere? Could push it now I suppose.

> 
>  drivers/gpu/drm/i915/i915_drv.h  |   1 +
>  drivers/gpu/drm/i915/i915_params.c   |   6 +
>  drivers/gpu/drm/i915/i915_params.h   |   1 +
>  drivers/gpu/drm/i915/intel_display.c | 205 
> ++-
>  4 files changed, 138 insertions(+), 75 deletions(-)
> 
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H

[Ville Syrjälä]

On Fri, Aug 05, 2016 at 10:22:48PM +0200, Daniel Vetter wrote:
> On Fri, Aug 05, 2016 at 08:00:17PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > Marking PCH transcoder FIFO underrun reporting as disabled for
> > transcoder B/C on LPT-H will block us from enabling the south error
> > interrupt. So let's only mark transcoder A underrun reporting as
> > disabled initially.
> > 
> > This is a little tricky to hit since you need a machine with LPT-H, and
> > the BIOS must enable either pipe B or C at boot. Then i915 would mark
> > the "transcoder B/C" underrun reporting as disabled and never enable it
> > again, meaning south interrupts would never get enabled either. The only
> > other interrupt in there is actually the poison interrupt which, if we
> > could ever trigger it, would just result in a little error in dmesg.
> > 
> > Here's the resulting change in SDEIMR on my HSW when I boot it with
> > multiple displays attached:
> > - (0x000c4004): 0xf115
> > + (0x000c4004): 0xf114
> > 
> > My previous attempt [1] tried to fix this a little differently, but
> > Daniel requested I do this instead.
> > 
> > [1] 
> > https://lists.freedesktop.org/archives/intel-gfx/2015-November/081420.html
> > 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> 
> Reviewed-by: Daniel Vetter 

Pushed to dinq. Thanks for the review.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 19 ++-
> >  1 file changed, 18 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 9cbf5431c1e3..888a52c64a26 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15771,6 +15771,13 @@ static bool intel_encoder_has_connectors(struct 
> > intel_encoder *encoder)
> > return false;
> >  }
> >  
> > +static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
> > + enum transcoder pch_transcoder)
> > +{
> > +   return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
> > +   (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
> > +}
> > +
> >  static void intel_sanitize_crtc(struct intel_crtc *crtc)
> >  {
> > struct drm_device *dev = crtc->base.dev;
> > @@ -15849,7 +15856,17 @@ static void intel_sanitize_crtc(struct intel_crtc 
> > *crtc)
> >  * worst a fifo underrun happens which also sets this to false.
> >  */
> > crtc->cpu_fifo_underrun_disabled = true;
> > -   crtc->pch_fifo_underrun_disabled = true;
> > +   /*
> > +* We track the PCH trancoder underrun reporting state
> > +* within the crtc. With crtc for pipe A housing the underrun
> > +* reporting state for PCH transcoder A, crtc for pipe B housing
> > +* it for PCH transcoder B, etc. LPT-H has only PCH transcoder 
> > A,
> > +* and marking underrun reporting as disabled for the 
> > non-existing
> > +* PCH transcoders B and C would prevent enabling the south
> > +* error interrupt (see cpt_can_enable_serr_int()).
> > +*/
> > +   if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
> > +   crtc->pch_fifo_underrun_disabled = true;
> > }
> >  }
> >  
> > -- 
> > 2.7.4
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Add some curly braces

[Ville Syrjälä]

On Fri, Aug 05, 2016 at 06:49:26PM +0100, Chris Wilson wrote:
> On Fri, Aug 05, 2016 at 08:41:34PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > intel_enable_pipe() looks rather confusing when one side doesn't have
> > the curly braces, and the other one does. And what's even worse,
> > there's another if-else inside the braceless side. Let's put braces
> > around it to make it clear which branch goes where.
> > 
> > Signed-off-by: Ville Syrjälä 
> 
> Easiest review of the day.
> Reviewed-by: Chris Wilson 

Pushed to dinq. Thanks for the review.

> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 04/15] drm/i915: Walk over encoders in crtc enable/disable using atomic state.

[Maarten Lankhorst]

This cleans up another possible use of the connector list,
encoder->crtc is legacy state and should not be used.

With the atomic state as argument it's easy to find the encoder from
the connector it belongs to.

intel_opregion_notify_encoder is a noop for !HAS_DDI, so it's harmless
to unconditionally include it in encoder enable/disable.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c | 190 ---
 1 file changed, 134 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ae555b4240c6..821dff719ec8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4694,6 +4694,123 @@ static void intel_crtc_disable_planes(struct drm_crtc 
*crtc, unsigned plane_mask
intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
 }
 
+static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
+ struct drm_atomic_state *old_state)
+{
+   struct drm_connector_state *old_conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   for_each_connector_in_state(old_state, conn, old_conn_state, i) {
+   struct drm_connector_state *conn_state = conn->state;
+   struct intel_encoder *encoder =
+   to_intel_encoder(conn_state->best_encoder);
+
+   if (conn_state->crtc != crtc)
+   continue;
+
+   if (encoder->pre_pll_enable)
+   encoder->pre_pll_enable(encoder);
+   }
+}
+
+static void intel_encoders_pre_enable(struct drm_crtc *crtc,
+ struct drm_atomic_state *old_state)
+{
+   struct drm_connector_state *old_conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   for_each_connector_in_state(old_state, conn, old_conn_state, i) {
+   struct drm_connector_state *conn_state = conn->state;
+   struct intel_encoder *encoder =
+   to_intel_encoder(conn_state->best_encoder);
+
+   if (conn_state->crtc != crtc)
+   continue;
+
+   if (encoder->pre_enable)
+   encoder->pre_enable(encoder);
+   }
+}
+
+static void intel_encoders_enable(struct drm_crtc *crtc,
+ struct drm_atomic_state *old_state)
+{
+   struct drm_connector_state *old_conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   for_each_connector_in_state(old_state, conn, old_conn_state, i) {
+   struct drm_connector_state *conn_state = conn->state;
+   struct intel_encoder *encoder =
+   to_intel_encoder(conn_state->best_encoder);
+
+   if (conn_state->crtc != crtc)
+   continue;
+
+   encoder->enable(encoder);
+   intel_opregion_notify_encoder(encoder, true);
+   }
+}
+
+static void intel_encoders_disable(struct drm_crtc *crtc,
+  struct drm_atomic_state *old_state)
+{
+   struct drm_connector_state *old_conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   for_each_connector_in_state(old_state, conn, old_conn_state, i) {
+   struct intel_encoder *encoder =
+   to_intel_encoder(old_conn_state->best_encoder);
+
+   if (old_conn_state->crtc != crtc)
+   continue;
+
+   intel_opregion_notify_encoder(encoder, false);
+   encoder->disable(encoder);
+   }
+}
+
+static void intel_encoders_post_disable(struct drm_crtc *crtc,
+   struct drm_atomic_state *old_state)
+{
+   struct drm_connector_state *old_conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   for_each_connector_in_state(old_state, conn, old_conn_state, i) {
+   struct intel_encoder *encoder =
+   to_intel_encoder(old_conn_state->best_encoder);
+
+   if (old_conn_state->crtc != crtc)
+   continue;
+
+   if (encoder->post_disable)
+   encoder->post_disable(encoder);
+   }
+}
+
+static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
+   struct drm_atomic_state *old_state)
+{
+   struct drm_connector_state *old_conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   for_each_connector_in_state(old_state, conn, old_conn_state, i) {
+   struct intel_encoder *encoder =
+   to_intel_encoder(old_conn_state->best_encoder);
+
+   if (old_conn_state->crtc != crtc)
+   continue;
+
+   if (encoder->post_pll_disable)
+   encoder->post_pll_disable(encoder);
+  

[Intel-gfx] [PATCH 06/15] drm/i915: Make encoder->compute_config take the connector state

[Maarten Lankhorst]

Some places iterate over connector_state to find the right
connector, pass it along as argument.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_crt.c | 3 ++-
 drivers/gpu/drm/i915/intel_ddi.c | 7 ---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_dp.c  | 3 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c  | 4 ++--
 drivers/gpu/drm/i915/intel_drv.h | 9 ++---
 drivers/gpu/drm/i915/intel_dsi.c | 3 ++-
 drivers/gpu/drm/i915/intel_dvo.c | 3 ++-
 drivers/gpu/drm/i915/intel_hdmi.c| 3 ++-
 drivers/gpu/drm/i915/intel_lvds.c| 3 ++-
 drivers/gpu/drm/i915/intel_sdvo.c| 3 ++-
 drivers/gpu/drm/i915/intel_tv.c  | 3 ++-
 12 files changed, 29 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 6e6c4bde105a..8fe36d049d2f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -261,7 +261,8 @@ intel_crt_mode_valid(struct drm_connector *connector,
 }
 
 static bool intel_crt_compute_config(struct intel_encoder *encoder,
-struct intel_crtc_state *pipe_config)
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state)
 {
struct drm_device *dev = encoder->base.dev;
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 66feb1eafc93..b23872839fe0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2285,7 +2285,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 }
 
 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
-struct intel_crtc_state *pipe_config)
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int type = encoder->type;
@@ -2298,9 +2299,9 @@ static bool intel_ddi_compute_config(struct intel_encoder 
*encoder,
pipe_config->cpu_transcoder = TRANSCODER_EDP;
 
if (type == INTEL_OUTPUT_HDMI)
-   ret = intel_hdmi_compute_config(encoder, pipe_config);
+   ret = intel_hdmi_compute_config(encoder, pipe_config, 
conn_state);
else
-   ret = intel_dp_compute_config(encoder, pipe_config);
+   ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
 
if (IS_BROXTON(dev_priv) && ret)
pipe_config->lane_lat_optim_mask =
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b536d22aaf59..c30feffc8be4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12589,7 +12589,7 @@ encoder_retry:
 
encoder = to_intel_encoder(connector_state->best_encoder);
 
-   if (!(encoder->compute_config(encoder, pipe_config))) {
+   if (!(encoder->compute_config(encoder, pipe_config, 
connector_state))) {
DRM_DEBUG_KMS("Encoder config failure\n");
goto fail;
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8bf1ba3166e9..2340c2b87a5d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1470,7 +1470,8 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int 
port_clock,
 
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
-   struct intel_crtc_state *pipe_config)
+   struct intel_crtc_state *pipe_config,
+   struct drm_connector_state *conn_state)
 {
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 3ec290caef17..694c67ebf82a 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -31,7 +31,8 @@
 #include 
 
 static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
-   struct intel_crtc_state *pipe_config)
+   struct intel_crtc_state *pipe_config,
+   struct drm_connector_state *conn_state)
 {
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
@@ -54,7 +55,6 @@ static bool intel_dp_mst_compute_config(struct intel_encoder 
*encoder,
 */
lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 
-
pipe_config->lane_count = lane_count;
 
pipe_config->pipe_bpp = 24;
diff --git a/drivers/gpu/drm/i915/intel_drv.h 

[Intel-gfx] [PATCH 05/15] drm/i915: Pass crtc_state and connector_state to encoder functions

[Maarten Lankhorst]

This is mostly code churn, with exception of a few places:
- intel_display.c has changes in intel_sanitize_encoder
- intel_ddi.c has intel_ddi_fdi_disable calling intel_ddi_post_disable,
  and required a function change. Also affects intel_display.c
- intel_dp_mst.c passes a NULL crtc_state and conn_state to
  intel_ddi_post_disable for shutting down the real encoder.

No other functional changes are done, diff stat is already huge.
Each encoder type will need to be fixed to use the atomic states
separately.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_crt.c |  18 +--
 drivers/gpu/drm/i915/intel_ddi.c |  31 +++
 drivers/gpu/drm/i915/intel_display.c | 102 ---
 drivers/gpu/drm/i915/intel_dp.c  |  48 -
 drivers/gpu/drm/i915/intel_dp_mst.c  |  20 +--
 drivers/gpu/drm/i915/intel_drv.h |  28 +++---
 drivers/gpu/drm/i915/intel_dsi.c |  16 --
 drivers/gpu/drm/i915/intel_dvo.c |  12 +++--
 drivers/gpu/drm/i915/intel_hdmi.c|  72 ++---
 drivers/gpu/drm/i915/intel_lvds.c|  29 +++---
 drivers/gpu/drm/i915/intel_sdvo.c|  22 +---
 drivers/gpu/drm/i915/intel_tv.c  |  12 +++--
 12 files changed, 284 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 827b6ef4e9ae..6e6c4bde105a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -193,21 +193,29 @@ static void intel_crt_set_dpms(struct intel_encoder 
*encoder, int mode)
I915_WRITE(crt->adpa_reg, adpa);
 }
 
-static void intel_disable_crt(struct intel_encoder *encoder)
+static void intel_disable_crt(struct intel_encoder *encoder,
+ struct intel_crtc_state *old_crtc_state,
+ struct drm_connector_state *old_conn_state)
 {
intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 }
 
-static void pch_disable_crt(struct intel_encoder *encoder)
+static void pch_disable_crt(struct intel_encoder *encoder,
+   struct intel_crtc_state *old_crtc_state,
+   struct drm_connector_state *old_conn_state)
 {
 }
 
-static void pch_post_disable_crt(struct intel_encoder *encoder)
+static void pch_post_disable_crt(struct intel_encoder *encoder,
+struct intel_crtc_state *old_crtc_state,
+struct drm_connector_state *old_conn_state)
 {
-   intel_disable_crt(encoder);
+   intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 }
 
-static void intel_enable_crt(struct intel_encoder *encoder)
+static void intel_enable_crt(struct intel_encoder *encoder,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state)
 {
intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON);
 }
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c2df4e429b19..66feb1eafc93 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1611,7 +1611,9 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
}
 }
 
-static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
+static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state)
 {
struct drm_encoder *encoder = _encoder->base;
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
@@ -1663,7 +1665,9 @@ static void intel_ddi_pre_enable(struct intel_encoder 
*intel_encoder)
}
 }
 
-static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
+static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
+  struct intel_crtc_state *old_crtc_state,
+  struct drm_connector_state *old_conn_state)
 {
struct drm_encoder *encoder = _encoder->base;
struct drm_device *dev = encoder->dev;
@@ -1673,6 +1677,8 @@ static void intel_ddi_post_disable(struct intel_encoder 
*intel_encoder)
uint32_t val;
bool wait = false;
 
+   /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
+
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
@@ -1708,7 +1714,9 @@ static void intel_ddi_post_disable(struct intel_encoder 
*intel_encoder)
}
 }
 
-static void intel_enable_ddi(struct intel_encoder *intel_encoder)
+static void intel_enable_ddi(struct intel_encoder *intel_encoder,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state)
 {
struct drm_encoder *encoder = _encoder->base;
 

[Intel-gfx] [PATCH 12/15] drm/i915: Convert intel_lvds to use atomic state

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_lvds.c | 22 ++
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
b/drivers/gpu/drm/i915/intel_lvds.c
index bfeec045579e..f5747a901ecc 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -141,17 +141,16 @@ static void intel_pre_enable_lvds(struct intel_encoder 
*encoder,
  struct drm_connector_state *conn_state)
 {
struct intel_lvds_encoder *lvds_encoder = 
to_lvds_encoder(>base);
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-   const struct drm_display_mode *adjusted_mode = 
>config->base.adjusted_mode;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+   const struct drm_display_mode *adjusted_mode = 
_config->base.adjusted_mode;
int pipe = crtc->pipe;
u32 temp;
 
-   if (HAS_PCH_SPLIT(dev)) {
+   if (HAS_PCH_SPLIT(dev_priv)) {
assert_fdi_rx_pll_disabled(dev_priv, pipe);
assert_shared_dpll_disabled(dev_priv,
-   crtc->config->shared_dpll);
+   pipe_config->shared_dpll);
} else {
assert_pll_disabled(dev_priv, pipe);
}
@@ -159,7 +158,7 @@ static void intel_pre_enable_lvds(struct intel_encoder 
*encoder,
temp = I915_READ(lvds_encoder->reg);
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 
-   if (HAS_PCH_CPT(dev)) {
+   if (HAS_PCH_CPT(dev_priv)) {
temp &= ~PORT_TRANS_SEL_MASK;
temp |= PORT_TRANS_SEL_CPT(pipe);
} else {
@@ -172,7 +171,7 @@ static void intel_pre_enable_lvds(struct intel_encoder 
*encoder,
 
/* set the corresponsding LVDS_BORDER bit */
temp &= ~LVDS_BORDER_ENABLE;
-   temp |= crtc->config->gmch_pfit.lvds_border_bits;
+   temp |= pipe_config->gmch_pfit.lvds_border_bits;
/* Set the B0-B3 data pairs corresponding to whether we're going to
 * set the DPLLs for dual-channel mode or not.
 */
@@ -195,7 +194,7 @@ static void intel_pre_enable_lvds(struct intel_encoder 
*encoder,
if (IS_GEN4(dev_priv)) {
/* Bspec wording suggests that LVDS port dithering only exists
 * for 18bpp panels. */
-   if (crtc->config->dither && crtc->config->pipe_bpp == 18)
+   if (pipe_config->dither && pipe_config->pipe_bpp == 18)
temp |= LVDS_ENABLE_DITHER;
else
temp &= ~LVDS_ENABLE_DITHER;
@@ -245,12 +244,11 @@ static void intel_disable_lvds(struct intel_encoder 
*encoder,
   struct intel_crtc_state *old_crtc_state,
   struct drm_connector_state *old_conn_state)
 {
-   struct drm_device *dev = encoder->base.dev;
struct intel_lvds_encoder *lvds_encoder = 
to_lvds_encoder(>base);
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
i915_reg_t ctl_reg, stat_reg;
 
-   if (HAS_PCH_SPLIT(dev)) {
+   if (HAS_PCH_SPLIT(dev_priv)) {
ctl_reg = PCH_PP_CONTROL;
stat_reg = PCH_PP_STATUS;
} else {
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 02/15] drm/i915: Pass atomic state to crtc enable/disable functions

[Maarten Lankhorst]

This is required for supporting nonblocking modesets. Iterating over
the connector list will no longer be allowed when we don't hold
connection_mutex, so we have to use the atomic state.

Fix disable_noatomic by populating the minimal state required to
disable a connector.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/i915_drv.h  |  6 ++--
 drivers/gpu/drm/i915/intel_display.c | 56 
 2 files changed, 42 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c36d17659ebe..6030d0edcf8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -628,8 +628,10 @@ struct drm_i915_display_funcs {
 struct intel_initial_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc,
  struct intel_crtc_state *crtc_state);
-   void (*crtc_enable)(struct drm_crtc *crtc);
-   void (*crtc_disable)(struct drm_crtc *crtc);
+   void (*crtc_enable)(struct intel_crtc_state *pipe_config,
+   struct drm_atomic_state *old_state);
+   void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
+struct drm_atomic_state *old_state);
void (*audio_codec_enable)(struct drm_connector *connector,
   struct intel_encoder *encoder,
   const struct drm_display_mode 
*adjusted_mode);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9cbf5431c1e3..ae555b4240c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4694,15 +4694,15 @@ static void intel_crtc_disable_planes(struct drm_crtc 
*crtc, unsigned plane_mask
intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
 }
 
-static void ironlake_crtc_enable(struct drm_crtc *crtc)
+static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
+struct drm_atomic_state *old_state)
 {
+   struct drm_crtc *crtc = pipe_config->base.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
-   struct intel_crtc_state *pipe_config =
-   to_intel_crtc_state(crtc->state);
 
if (WARN_ON(intel_crtc->active))
return;
@@ -4791,16 +4791,16 @@ static bool hsw_crtc_supports_ips(struct intel_crtc 
*crtc)
return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
 }
 
-static void haswell_crtc_enable(struct drm_crtc *crtc)
+static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
+   struct drm_atomic_state *old_state)
 {
+   struct drm_crtc *crtc = pipe_config->base.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
-   struct intel_crtc_state *pipe_config =
-   to_intel_crtc_state(crtc->state);
 
if (WARN_ON(intel_crtc->active))
return;
@@ -4930,8 +4930,10 @@ static void ironlake_pfit_disable(struct intel_crtc 
*crtc, bool force)
}
 }
 
-static void ironlake_crtc_disable(struct drm_crtc *crtc)
+static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
+ struct drm_atomic_state *old_state)
 {
+   struct drm_crtc *crtc = old_crtc_state->base.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -4993,8 +4995,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
 }
 
-static void haswell_crtc_disable(struct drm_crtc *crtc)
+static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
+struct drm_atomic_state *old_state)
 {
+   struct drm_crtc *crtc = old_crtc_state->base.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6098,14 +6102,14 @@ static void valleyview_modeset_commit_cdclk(struct 
drm_atomic_state *old_state)
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 }
 
-static void valleyview_crtc_enable(struct drm_crtc *crtc)
+static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
+ 

[Intel-gfx] [PATCH 15/15] drm/i915: Use more atomic state in intel_color.c

[Maarten Lankhorst]

crtc_state is already passed around, use it instead of crtc->config.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_color.c | 24 ++--
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index bc0fef3d3335..95a72771eea6 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -100,13 +100,14 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int i, pipe = intel_crtc->pipe;
uint16_t coeffs[9] = { 0, };
+   struct intel_crtc_state *intel_crtc_state = 
to_intel_crtc_state(crtc_state);
 
if (crtc_state->ctm) {
struct drm_color_ctm *ctm =
(struct drm_color_ctm *)crtc_state->ctm->data;
uint64_t input[9] = { 0, };
 
-   if (intel_crtc->config->limited_color_range) {
+   if (intel_crtc_state->limited_color_range) {
ctm_mult_by_limited(input, ctm->matrix);
} else {
for (i = 0; i < ARRAY_SIZE(input); i++)
@@ -158,7 +159,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
 * into consideration.
 */
for (i = 0; i < 3; i++) {
-   if (intel_crtc->config->limited_color_range)
+   if (intel_crtc_state->limited_color_range)
coeffs[i * 3 + i] =
I9XX_CSC_COEFF_LIMITED_RANGE;
else
@@ -182,7 +183,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
if (INTEL_INFO(dev)->gen > 6) {
uint16_t postoff = 0;
 
-   if (intel_crtc->config->limited_color_range)
+   if (intel_crtc_state->limited_color_range)
postoff = (16 * (1 << 12) / 255) & 0x1fff;
 
I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
@@ -193,7 +194,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
} else {
uint32_t mode = CSC_MODE_YUV_TO_RGB;
 
-   if (intel_crtc->config->limited_color_range)
+   if (intel_crtc_state->limited_color_range)
mode |= CSC_BLACK_SCREEN_OFFSET;
 
I915_WRITE(PIPE_CSC_MODE(pipe), mode);
@@ -263,7 +264,8 @@ void intel_color_set_csc(struct drm_crtc_state *crtc_state)
 
 /* Loads the legacy palette/gamma unit for the CRTC. */
 static void i9xx_load_luts_internal(struct drm_crtc *crtc,
-   struct drm_property_blob *blob)
+   struct drm_property_blob *blob,
+   struct intel_crtc_state *crtc_state)
 {
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -272,7 +274,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
int i;
 
if (HAS_GMCH_DISPLAY(dev)) {
-   if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI))
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
assert_dsi_pll_enabled(dev_priv);
else
assert_pll_enabled(dev_priv, pipe);
@@ -305,7 +307,8 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
 
 static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
 {
-   i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut);
+   i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
+   to_intel_crtc_state(crtc_state));
 }
 
 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
@@ -323,7 +326,7 @@ static void haswell_load_luts(struct drm_crtc_state 
*crtc_state)
 * Workaround : Do not read or write the pipe palette/gamma data while
 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 */
-   if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
+   if (IS_HASWELL(dev) && intel_crtc_state->ips_enabled &&
(intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
hsw_disable_ips(intel_crtc);
reenable_ips = true;
@@ -436,7 +439,8 @@ static void cherryview_load_luts(struct drm_crtc_state 
*state)
/* Turn off degamma/gamma on CGM block. */
I915_WRITE(CGM_PIPE_MODE(pipe),
   (state->ctm ? CGM_PIPE_MODE_CSC : 0));
-   i9xx_load_luts_internal(crtc, state->gamma_lut);
+   i9xx_load_luts_internal(crtc, state->gamma_lut,
+   to_intel_crtc_state(state));
return;
}
 
@@ -479,7 +483,7 @@ static void 

[Intel-gfx] [PATCH 11/15] drm/i915: Convert intel_sdvo to use atomic state

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_sdvo.c | 27 +++
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
b/drivers/gpu/drm/i915/intel_sdvo.c
index 7c08d555f35d..74a7c6c9b974 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1003,24 +1003,22 @@ static bool intel_sdvo_write_infoframe(struct 
intel_sdvo *intel_sdvo,
 }
 
 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
-const struct drm_display_mode 
*adjusted_mode)
+struct intel_crtc_state *pipe_config)
 {
uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
-   struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
union hdmi_infoframe frame;
int ret;
ssize_t len;
 
ret = drm_hdmi_avi_infoframe_from_display_mode(,
-  adjusted_mode);
+  
_config->base.adjusted_mode);
if (ret < 0) {
DRM_ERROR("couldn't fill AVI infoframe\n");
return false;
}
 
if (intel_sdvo->rgb_quant_range_selectable) {
-   if (intel_crtc->config->limited_color_range)
+   if (pipe_config->limited_color_range)
frame.avi.quantization_range =
HDMI_QUANTIZATION_RANGE_LIMITED;
else
@@ -1199,18 +1197,15 @@ static void intel_sdvo_pre_enable(struct intel_encoder 
*intel_encoder,
 {
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
-   const struct drm_display_mode *adjusted_mode = 
>config->base.adjusted_mode;
-   struct drm_display_mode *mode = >config->base.mode;
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   const struct drm_display_mode *adjusted_mode = 
_state->base.adjusted_mode;
+   struct drm_display_mode *mode = _state->base.mode;
struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
u32 sdvox;
struct intel_sdvo_in_out_map in_out;
struct intel_sdvo_dtd input_dtd, output_dtd;
int rate;
 
-   if (!mode)
-   return;
-
/* First, set the input mapping for the first input to our controlled
 * output. This is only correct if we're a single-input device, in
 * which case the first input is the output from the appropriate SDVO
@@ -1243,11 +1238,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder 
*intel_encoder,
if (!intel_sdvo_set_target_input(intel_sdvo))
return;
 
-   if (crtc->config->has_hdmi_sink) {
+   if (crtc_state->has_hdmi_sink) {
intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
intel_sdvo_set_colorimetry(intel_sdvo,
   SDVO_COLORIMETRY_RGB256);
-   intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
+   intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
} else
intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
 
@@ -1263,7 +1258,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder 
*intel_encoder,
DRM_INFO("Setting input timings on %s failed\n",
 SDVO_NAME(intel_sdvo));
 
-   switch (crtc->config->pixel_multiplier) {
+   switch (crtc_state->pixel_multiplier) {
default:
WARN(1, "unknown pixel multiplier specified\n");
case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
@@ -1278,7 +1273,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder 
*intel_encoder,
/* The real mode polarity is set by the SDVO commands, using
 * struct intel_sdvo_dtd. */
sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
-   if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
+   if (!HAS_PCH_SPLIT(dev) && crtc_state->limited_color_range)
sdvox |= HDMI_COLOR_RANGE_16_235;
if (INTEL_INFO(dev)->gen < 5)
sdvox |= SDVO_BORDER_ENABLE;
@@ -1304,7 +1299,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder 
*intel_encoder,
} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
/* done in crtc_mode_set as it lives inside the dpll register */
} else {
-   sdvox |= (crtc->config->pixel_multiplier - 1)
+   sdvox |= (crtc_state->pixel_multiplier - 1)
<< SDVO_PORT_MULTIPLY_SHIFT;
}
 
-- 
2.7.4

___

[Intel-gfx] [PATCH 08/15] drm/i915: Convert intel_crt to use atomic state

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_crt.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 8fe36d049d2f..1daf2d9c937e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -143,13 +143,15 @@ static void hsw_crt_get_config(struct intel_encoder 
*encoder,
 
 /* Note: The caller is required to filter out dpms modes not supported by the
  * platform. */
-static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
+static void intel_crt_set_dpms(struct intel_encoder *encoder,
+  struct intel_crtc_state *crtc_state,
+  int mode)
 {
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-   const struct drm_display_mode *adjusted_mode = 
>config->base.adjusted_mode;
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+   const struct drm_display_mode *adjusted_mode = 
_state->base.adjusted_mode;
u32 adpa;
 
if (INTEL_INFO(dev)->gen >= 5)
@@ -197,7 +199,7 @@ static void intel_disable_crt(struct intel_encoder *encoder,
  struct intel_crtc_state *old_crtc_state,
  struct drm_connector_state *old_conn_state)
 {
-   intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
+   intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 }
 
 static void pch_disable_crt(struct intel_encoder *encoder,
@@ -217,7 +219,7 @@ static void intel_enable_crt(struct intel_encoder *encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
 {
-   intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON);
+   intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
 }
 
 static enum drm_mode_status
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 13/15] drm/i915: Convert intel_dp_mst to use atomic state

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 48 ++---
 1 file changed, 18 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 1fb741a02813..b2f0ef5db64b 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -82,11 +82,13 @@ static void intel_mst_disable_dp(struct intel_encoder 
*encoder,
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = _dig_port->dp;
+   struct intel_connector *connector =
+   to_intel_connector(old_conn_state->connector);
int ret;
 
DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
 
-   drm_dp_mst_reset_vcpi_slots(_dp->mst_mgr, 
intel_mst->connector->port);
+   drm_dp_mst_reset_vcpi_slots(_dp->mst_mgr, connector->port);
 
ret = drm_dp_update_payload_part1(_dp->mst_mgr);
if (ret) {
@@ -101,6 +103,8 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = _dig_port->dp;
+   struct intel_connector *connector =
+   to_intel_connector(old_conn_state->connector);
 
DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
 
@@ -109,7 +113,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
/* and this can also fail */
drm_dp_update_payload_part2(_dp->mst_mgr);
 
-   drm_dp_mst_deallocate_vcpi(_dp->mst_mgr, 
intel_mst->connector->port);
+   drm_dp_mst_deallocate_vcpi(_dp->mst_mgr, connector->port);
 
intel_dp->active_mst_links--;
 
@@ -129,43 +133,29 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = _dig_port->dp;
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = intel_dig_port->port;
+   struct intel_connector *connector =
+   to_intel_connector(conn_state->connector);
int ret;
uint32_t temp;
-   struct intel_connector *found = NULL, *connector;
int slots;
-   struct drm_crtc *crtc = encoder->base.crtc;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-   for_each_intel_connector(dev, connector) {
-   if (connector->base.state->best_encoder == >base) {
-   found = connector;
-   break;
-   }
-   }
-
-   if (!found) {
-   DRM_ERROR("can't find connector\n");
-   return;
-   }
 
/* MST encoders are bound to a crtc, not to a connector,
 * force the mapping here for get_hw_state.
 */
-   found->encoder = encoder;
+   connector->encoder = encoder;
 
DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
 
-   intel_mst->connector = found;
+   intel_mst->connector = connector;
 
if (intel_dp->active_mst_links == 0) {
-   intel_ddi_clk_select(_dig_port->base, intel_crtc->config);
+   intel_ddi_clk_select(_dig_port->base, pipe_config);
 
intel_prepare_dp_ddi_buffers(_dig_port->base);
 
-   intel_dp_set_link_params(intel_dp, intel_crtc->config);
+   intel_dp_set_link_params(intel_dp, pipe_config);
 
intel_ddi_init_dp_buf_reg(_dig_port->base);
 
@@ -176,8 +166,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
}
 
ret = drm_dp_mst_allocate_vcpi(_dp->mst_mgr,
-  intel_mst->connector->port,
-  intel_crtc->config->pbn, );
+  connector->port,
+  pipe_config->pbn, );
if (ret == false) {
DRM_ERROR("failed to allocate vcpi\n");
return;
@@ -198,8 +188,7 @@ static void intel_mst_enable_dp(struct intel_encoder 
*encoder,
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = _dig_port->dp;
-   struct drm_device *dev = intel_dig_port->base.base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = intel_dig_port->port;
int ret;
 
@@ -232,9 +221,8 @@ static void 

[Intel-gfx] [PATCH 01/15] drm/i915: handle DP_MST correctly in bxt_get_dpll

[Maarten Lankhorst]

No idea if it supports it, but this is the minimum required from get_dpll.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 5c1f2d235ffa..655a5b382cf9 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1535,7 +1535,8 @@ bxt_get_dpll(struct intel_crtc *crtc, struct 
intel_crtc_state *crtc_state,
 
vco = best_clock.vco;
} else if (encoder->type == INTEL_OUTPUT_DP ||
-  encoder->type == INTEL_OUTPUT_EDP) {
+  encoder->type == INTEL_OUTPUT_EDP ||
+  encoder->type == INTEL_OUTPUT_DP_MST) {
int i;
 
clk_div = bxt_dp_clk_val[0];
@@ -1611,7 +1612,12 @@ bxt_get_dpll(struct intel_crtc *crtc, struct 
intel_crtc_state *crtc_state,
crtc_state->dpll_hw_state.pcsdw12 =
LANESTAGGER_STRAP_OVRD | lanestagger;
 
-   intel_dig_port = enc_to_dig_port(>base);
+   if (encoder->type == INTEL_OUTPUT_DP_MST) {
+   struct intel_dp_mst_encoder *intel_mst = 
enc_to_mst(>base);
+
+   intel_dig_port = intel_mst->primary;
+   } else
+   intel_dig_port = enc_to_dig_port(>base);
 
/* 1:1 mapping between ports and PLLs */
i = (enum intel_dpll_id) intel_dig_port->port;
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 14/15] drm/i915: Convert intel_dp to use atomic state

[Maarten Lankhorst]

Slightly less straightforward. Some of the drrs calls are done from
workers or from intel_ddi.c, pass along crtc_state when we can,
or crtc->config when we can't.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_ddi.c |   4 +-
 drivers/gpu/drm/i915/intel_dp.c  | 123 ++-
 drivers/gpu/drm/i915/intel_drv.h |   6 +-
 3 files changed, 64 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b23872839fe0..309ba7bc19ad 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1745,7 +1745,7 @@ static void intel_enable_ddi(struct intel_encoder 
*intel_encoder,
 
intel_edp_backlight_on(intel_dp);
intel_psr_enable(intel_dp);
-   intel_edp_drrs_enable(intel_dp);
+   intel_edp_drrs_enable(intel_dp, pipe_config);
}
 
if (intel_crtc->config->has_audio) {
@@ -1773,7 +1773,7 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder,
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-   intel_edp_drrs_disable(intel_dp);
+   intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp);
intel_edp_backlight_off(intel_dp);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2340c2b87a5d..8a4f34d2e126 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1655,16 +1655,17 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
intel_dp->link_mst = intel_crtc_has_type(pipe_config, 
INTEL_OUTPUT_DP_MST);
 }
 
-static void intel_dp_prepare(struct intel_encoder *encoder)
+static void intel_dp_prepare(struct intel_encoder *encoder,
+struct intel_crtc_state *pipe_config)
 {
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
enum port port = dp_to_dig_port(intel_dp)->port;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-   const struct drm_display_mode *adjusted_mode = 
>config->base.adjusted_mode;
+   const struct drm_display_mode *adjusted_mode = 
_config->base.adjusted_mode;
 
-   intel_dp_set_link_params(intel_dp, crtc->config);
+   intel_dp_set_link_params(intel_dp, pipe_config);
 
/*
 * There are four kinds of DP registers:
@@ -1690,7 +1691,7 @@ static void intel_dp_prepare(struct intel_encoder 
*encoder)
 
/* Handle DP bits in common between all three register formats */
intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
-   intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
+   intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
 
/* Split out the IBX/CPU vs CPT settings */
 
@@ -1718,7 +1719,7 @@ static void intel_dp_prepare(struct intel_encoder 
*encoder)
I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
} else {
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-   !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
+   !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -2256,10 +2257,10 @@ static void assert_edp_pll(struct drm_i915_private 
*dev_priv, bool state)
 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
 
-static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
+static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
+   struct intel_crtc_state *pipe_config)
 {
-   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-   struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+   struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -2267,11 +2268,11 @@ static void ironlake_edp_pll_on(struct intel_dp 
*intel_dp)
assert_edp_pll_disabled(dev_priv);
 
DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
- crtc->config->port_clock);
+ pipe_config->port_clock);
 
intel_dp->DP &= ~DP_PLL_FREQ_MASK;
 
-   if (crtc->config->port_clock == 162000)
+   if (pipe_config->port_clock == 162000)
intel_dp->DP |= DP_PLL_FREQ_162MHZ;
else
intel_dp->DP |= DP_PLL_FREQ_270MHZ;
@@ -2485,13 +2486,12 @@ static void intel_disable_dp(struct intel_encoder 
*encoder,
 struct 

[Intel-gfx] [PATCH 10/15] drm/i915: Convert intel_dsi to use atomic state

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_dsi.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1a2e1dcbff1a..8ffa6154e9c6 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -534,16 +534,15 @@ static void intel_dsi_enable(struct intel_encoder 
*encoder)
intel_panel_enable_backlight(intel_dsi->attached_connector);
 }
 
-static void intel_dsi_prepare(struct intel_encoder *intel_encoder);
+static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *pipe_config);
 
 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
 {
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
enum port port;
 
DRM_DEBUG_KMS("\n");
@@ -553,9 +552,9 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
 * lock. It needs to be fully powered down to fix it.
 */
intel_disable_dsi_pll(encoder);
-   intel_enable_dsi_pll(encoder, crtc->config);
+   intel_enable_dsi_pll(encoder, pipe_config);
 
-   intel_dsi_prepare(encoder);
+   intel_dsi_prepare(encoder, pipe_config);
 
/* Panel Enable over CRC PMIC */
if (intel_dsi->gpio_panel)
@@ -829,7 +828,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder 
*encoder,
crtc_hblank_start_sw, crtc_hblank_end_sw;
 
intel_crtc = to_intel_crtc(encoder->base.crtc);
-   adjusted_mode_sw = _crtc->config->base.adjusted_mode;
+   adjusted_mode_sw = _config->base.adjusted_mode;
 
/*
 * Atleast one port is active as encoder->get_config called only if
@@ -1113,14 +1112,15 @@ static u32 pixel_format_to_reg(enum 
mipi_dsi_pixel_format fmt)
}
 }
 
-static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
+static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *pipe_config)
 {
struct drm_encoder *encoder = _encoder->base;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+   struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
-   const struct drm_display_mode *adjusted_mode = 
_crtc->config->base.adjusted_mode;
+   const struct drm_display_mode *adjusted_mode = 
_config->base.adjusted_mode;
enum port port;
unsigned int bpp = 
mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
u32 val, tmp;
@@ -1357,7 +1357,7 @@ static int intel_dsi_set_property(struct drm_connector 
*connector,
intel_connector->panel.fitting_mode = val;
}
 
-   crtc = intel_attached_encoder(connector)->base.crtc;
+   crtc = connector->state->crtc;
if (crtc && crtc->state->enable) {
/*
 * If the CRTC is enabled, the display will be changed
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 07/15] drm/i915: Remove unused loop from intel_dp_mst_compute_config

[Maarten Lankhorst]

conn_state is passed as argument now, if anything required conn_state
they can get it without having to look it up.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 19 +--
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 694c67ebf82a..1fb741a02813 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -38,12 +38,9 @@ static bool intel_dp_mst_compute_config(struct intel_encoder 
*encoder,
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = _dig_port->dp;
struct drm_atomic_state *state;
-   int bpp, i;
+   int bpp;
int lane_count, slots;
const struct drm_display_mode *adjusted_mode = 
_config->base.adjusted_mode;
-   struct drm_connector *drm_connector;
-   struct intel_connector *connector, *found = NULL;
-   struct drm_connector_state *connector_state;
int mst_pbn;
 
pipe_config->dp_encoder_is_mst = true;
@@ -62,20 +59,6 @@ static bool intel_dp_mst_compute_config(struct intel_encoder 
*encoder,
 
state = pipe_config->base.state;
 
-   for_each_connector_in_state(state, drm_connector, connector_state, i) {
-   connector = to_intel_connector(drm_connector);
-
-   if (connector_state->best_encoder == >base) {
-   found = connector;
-   break;
-   }
-   }
-
-   if (!found) {
-   DRM_ERROR("can't find connector\n");
-   return false;
-   }
-
mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
 
pipe_config->pbn = mst_pbn;
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 00/15] drm/i915: Use connector atomic state in encoders.

[Maarten Lankhorst]

This is required for supporting nonblocking modeset and atomic connector 
properties.
Connector properties will need the connector state to be passed or it will not 
work
as intended.

Nonblocking modesets need to iterate over the atomic state, instead of relying 
on
the legacy state fixed up by atomic.

Maarten Lankhorst (15):
  drm/i915: handle DP_MST correctly in bxt_get_dpll
  drm/i915: Pass atomic state to crtc enable/disable functions
  drm/i915: Remove unused mode_set hook from encoder
  drm/i915: Walk over encoders in crtc enable/disable using atomic
state.
  drm/i915: Pass crtc_state and connector_state to encoder functions
  drm/i915: Make encoder->compute_config take the connector state
  drm/i915: Remove unused loop from intel_dp_mst_compute_config
  drm/i915: Convert intel_crt to use atomic state
  drm/i915: Convert intel_dvo to use atomic state
  drm/i915: Convert intel_dsi to use atomic state
  drm/i915: Convert intel_sdvo to use atomic state
  drm/i915: Convert intel_lvds to use atomic state
  drm/i915: Convert intel_dp_mst to use atomic state
  drm/i915: Convert intel_dp to use atomic state
  drm/i915: Use more atomic state in intel_color.c

 drivers/gpu/drm/i915/i915_drv.h   |   6 +-
 drivers/gpu/drm/i915/intel_color.c|  24 +--
 drivers/gpu/drm/i915/intel_crt.c  |  33 ++--
 drivers/gpu/drm/i915/intel_ddi.c  |  42 +++--
 drivers/gpu/drm/i915/intel_display.c  | 304 +++---
 drivers/gpu/drm/i915/intel_dp.c   | 174 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c   |  91 --
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  10 +-
 drivers/gpu/drm/i915/intel_drv.h  |  44 +++--
 drivers/gpu/drm/i915/intel_dsi.c  |  41 +++--
 drivers/gpu/drm/i915/intel_dvo.c  |  27 +--
 drivers/gpu/drm/i915/intel_hdmi.c |  75 ++---
 drivers/gpu/drm/i915/intel_lvds.c |  54 +++---
 drivers/gpu/drm/i915/intel_sdvo.c |  52 +++---
 drivers/gpu/drm/i915/intel_tv.c   |  15 +-
 15 files changed, 615 insertions(+), 377 deletions(-)

-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 09/15] drm/i915: Convert intel_dvo to use atomic state

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_dvo.c | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 141483fdcf7b..642c5550a1e5 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -194,13 +194,12 @@ static void intel_enable_dvo(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
u32 temp = I915_READ(dvo_reg);
 
intel_dvo->dev.dev_ops->mode_set(_dvo->dev,
->config->base.mode,
->config->base.adjusted_mode);
+_config->base.mode,
+_config->base.adjusted_mode);
 
I915_WRITE(dvo_reg, temp | DVO_ENABLE);
I915_READ(dvo_reg);
@@ -262,10 +261,9 @@ static void intel_dvo_pre_enable(struct intel_encoder 
*encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
 {
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-   const struct drm_display_mode *adjusted_mode = 
>config->base.adjusted_mode;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+   const struct drm_display_mode *adjusted_mode = 
_config->base.adjusted_mode;
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
int pipe = crtc->pipe;
u32 dvo_val;
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/6] drm/i915/lvds: Restore initial HW state during encoder enabling

[Ville Syrjälä]

On Tue, Aug 09, 2016 at 05:40:32PM +0300, Imre Deak wrote:
> On ti, 2016-08-09 at 15:48 +0300, Ville Syrjälä wrote:
> > On Tue, Aug 09, 2016 at 02:34:09PM +0300, Imre Deak wrote:
> > > Atm the LVDS encoder depends on the PPS HW context being saved/restored
> > > from generic suspend/resume code. Since the PPS is specific to the LVDS
> > > and eDP encoders a cleaner way is to reinitialize it during encoder
> > > enabling, so do this here for LVDS. Follow-up patches will init the PPS
> > > for the eDP encoder similarly and remove the suspend/resume time save /
> > > restore.
> > > 
> > > Signed-off-by: Imre Deak 
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h   |   1 +
> > >  drivers/gpu/drm/i915/intel_lvds.c | 103 
> > > +-
> > >  2 files changed, 91 insertions(+), 13 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 889508f..da82744 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3710,6 +3710,7 @@ enum {
> > >  
> > >  #define _PP_ON_DELAYS0x61208
> > >  #define PP_ON_DELAYS(pps_idx)_MMIO_PPS(pps_idx, 
> > > _PP_ON_DELAYS)
> > > +#define  PANEL_PORT_SELECT_SHIFT 30
> > >  #define  PANEL_PORT_SELECT_MASK  (3 << 30)
> > >  #define  PANEL_PORT_SELECT_LVDS  (0 << 30)
> > >  #define  PANEL_PORT_SELECT_DPA   (1 << 30)
> > > diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
> > > b/drivers/gpu/drm/i915/intel_lvds.c
> > > index c5739fc..d5158e5 100644
> > > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > > @@ -48,6 +48,20 @@ struct intel_lvds_connector {
> > >   struct notifier_block lid_notifier;
> > >  };
> > >  
> > > +struct intel_lvds_pps {
> > > + /* 100us units */
> > > + int t1_t2;
> > > + int t3;
> > > + int t4;
> > > + int t5;
> > > + int tx;
> > > +
> > > + int divider;
> > > +
> > > + int port;
> > > + bool reset_on_powerdown;
> > > +};
> > > +
> > >  struct intel_lvds_encoder {
> > >   struct intel_encoder base;
> > >  
> > > @@ -55,6 +69,9 @@ struct intel_lvds_encoder {
> > >   i915_reg_t reg;
> > >   u32 a3_power;
> > >  
> > > + struct intel_lvds_pps init_pps;
> > > + u32 init_lvds_val;
> > > +
> > >   struct intel_lvds_connector *attached_connector;
> > >  };
> > >  
> > > @@ -136,6 +153,72 @@ static void intel_lvds_get_config(struct 
> > > intel_encoder *encoder,
> > >   pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> > >  }
> > >  
> > > +static void intel_lvds_pps_get_hw_state(struct drm_i915_private 
> > > *dev_priv,
> > > + struct intel_lvds_pps *pps)
> > > +{
> > > + u32 val;
> > > +
> > > + pps->reset_on_powerdown = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
> > > +
> > > + val = I915_READ(PP_ON_DELAYS(0));
> > > + pps->port = (val & PANEL_PORT_SELECT_MASK) >>
> > > + PANEL_PORT_SELECT_SHIFT;
> > > + pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
> > > +  PANEL_POWER_UP_DELAY_SHIFT;
> > > + pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
> > > +   PANEL_LIGHT_ON_DELAY_SHIFT;
> > > +
> > > + val = I915_READ(PP_OFF_DELAYS(0));
> > > + pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
> > > +   PANEL_POWER_DOWN_DELAY_SHIFT;
> > > + pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
> > > +   PANEL_LIGHT_OFF_DELAY_SHIFT;
> > > +
> > > + val = I915_READ(PP_DIVISOR(0));
> > > + pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
> > > +    PP_REFERENCE_DIVIDER_SHIFT;
> > > + /* Convert from 100ms to 100us units */
> > > + pps->t4 = ((val & PANEL_POWER_CYCLE_DELAY_MASK) >>
> > > +    PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> > 
> > This should have the +1 offset handling I think.
> 
> Ok, will add that.
> 
> > Hmm. Looks like we mess that up even for eDP :(
> > > +
> > > + if (INTEL_INFO(dev_priv)->gen <= 4 &&
> > > + pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
> > > + DRM_DEBUG_KMS("Panel power timings uninitialized, "
> > > +   "setting defaults\n");
> > > + /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
> > > + pps->t1_t2 = 40 * 10;
> > > + pps->t5 = 200 * 10;
> > > + /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
> > > + pps->t3 = 35 * 10;
> > > + pps->tx = 200 * 10;
> > 
> > Not sure where these came from originally. The spgw spec tells us:
> > 
> > min max
> > t1  0.5 10
> > t2  0   50
> > t3  0   50
> > t4  200 -
> > t5  200 -
> > t6  200 -
> > t7  0   10
> > 
> > So maybe we should at least set t4=200 here based on the minimum t4
> > delay in the spec, probably should add the max t7 time there as well
> > as that's what the power cycle delays seems to be really: t4+t7.
> > Bspec seems to claim that spgw spec has an upper limit of 400 for 

[Intel-gfx] ✗ Ro.CI.BAT: failure for Accommodate multiple GuC submission clients

[Patchwork]

== Series Details ==

Series: Accommodate multiple GuC submission clients
URL   : https://patchwork.freedesktop.org/series/10847/
State : failure

== Summary ==

Series 10847v1 Accommodate multiple GuC submission clients
http://patchwork.freedesktop.org/api/1.0/series/10847/revisions/1/mbox

Test drv_module_reload_basic:
pass   -> DMESG-WARN (ro-skl3-i5-6260u)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (ro-byt-n2820)

fi-hsw-i7-4770k  total:107  pass:91   dwarn:0   dfail:0   fail:0   skip:15 
fi-kbl-qkkr  total:107  pass:83   dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8  
fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22 
fi-snb-i7-2600   total:107  pass:77   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i5-5250u  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9  
ro-bdw-i7-5600u  total:107  pass:79   dwarn:0   dfail:0   fail:0   skip:27 
ro-bsw-n3050 total:240  pass:194  dwarn:0   dfail:0   fail:4   skip:42 
ro-byt-n2820 total:240  pass:196  dwarn:0   dfail:0   fail:4   skip:40 
ro-hsw-i3-4010u  total:107  pass:87   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2   skip:60 
ro-ivb-i7-3770   total:107  pass:80   dwarn:0   dfail:0   fail:0   skip:26 
ro-skl3-i5-6260u total:107  pass:97   dwarn:1   dfail:0   fail:0   skip:8  
ro-bdw-i7-5557U failed to connect after reboot
ro-hsw-i7-4770r failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1785/

e220d47 drm-intel-nightly: 2016y-08m-09d-09h-18m-12s UTC integration manifest
f93075d NOMERGE: re-enable GuC loading and submission by default
9fba995 drm/i915/guc: re-optimise i915_guc_client layout
64c9f76 drm/i915/guc: use for_each_engine_id() where appropriate
550dfa4 drm/i915/guc: add engine mask to GuC client & pass to GuC
fa78cb8 drm/i915/guc: refactor guc_init_doorbell_hw()
b194fc6 drm/i915/guc: doorbell reset should avoid used doorbells

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 3/4] video: Add new aspect ratios for HDMI 2.0

[Shashank Sharma]

HDMI 2.0/CEA-861-F introduces two new aspect ratios:
- 64:27
- 256:135

This patch adds enumeration for the new aspect ratios
in the existing aspect ratio list.

V2: rebase

Signed-off-by: Shashank Sharma 
Reviewed-by: Sean Paul 
Cc: Daniel Vetter 
Cc: Emil Velikov 
---
 drivers/video/hdmi.c | 4 
 include/linux/hdmi.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 1626892..1cf907e 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -533,6 +533,10 @@ hdmi_picture_aspect_get_name(enum hdmi_picture_aspect 
picture_aspect)
return "4:3";
case HDMI_PICTURE_ASPECT_16_9:
return "16:9";
+   case HDMI_PICTURE_ASPECT_64_27:
+   return "64:27";
+   case HDMI_PICTURE_ASPECT_256_135:
+   return "256:135";
case HDMI_PICTURE_ASPECT_RESERVED:
return "Reserved";
}
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index e974420..edbb4fc 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -78,6 +78,8 @@ enum hdmi_picture_aspect {
HDMI_PICTURE_ASPECT_NONE,
HDMI_PICTURE_ASPECT_4_3,
HDMI_PICTURE_ASPECT_16_9,
+   HDMI_PICTURE_ASPECT_64_27,
+   HDMI_PICTURE_ASPECT_256_135,
HDMI_PICTURE_ASPECT_RESERVED,
 };
 
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 4/4] drm: Add and handle new aspect ratios in DRM layer

[Shashank Sharma]

HDMI 2.0/CEA-861-F introduces two new aspect ratios:
- 64:27
- 256:135

This patch:
-  Adds new DRM flags for to represent these new aspect ratios.
-  Adds new cases to handle these aspect ratios while converting
from user->kernel mode or vise versa.

V2: Rebase

Signed-off-by: Shashank Sharma 
Reviewed-by: Sean Paul 
Cc: Daniel Vetter 
Cc: Emil Velikov 
---
 drivers/gpu/drm/drm_modes.c | 12 
 include/uapi/drm/drm_mode.h |  6 ++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 9d8f00d..ed1b07b 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1481,6 +1481,12 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo 
*out,
case HDMI_PICTURE_ASPECT_16_9:
out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
break;
+   case HDMI_PICTURE_ASPECT_64_27:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_64_27;
+   break;
+   case DRM_MODE_PICTURE_ASPECT_256_135:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_256_135;
+   break;
case HDMI_PICTURE_ASPECT_RESERVED:
default:
out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
@@ -1542,6 +1548,12 @@ int drm_mode_convert_umode(struct drm_display_mode *out,
case DRM_MODE_FLAG_PIC_AR_16_9:
out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_16_9;
break;
+   case DRM_MODE_FLAG_PIC_AR_64_27:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_64_27;
+   break;
+   case DRM_MODE_FLAG_PIC_AR_256_135:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_256_135;
+   break;
default:
out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
break;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 77c869d6..4d3429b 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -81,6 +81,8 @@ extern "C" {
 #define DRM_MODE_PICTURE_ASPECT_NONE   0
 #define DRM_MODE_PICTURE_ASPECT_4_31
 #define DRM_MODE_PICTURE_ASPECT_16_9   2
+#define DRM_MODE_PICTURE_ASPECT_64_27  3
+#define DRM_MODE_PICTURE_ASPECT_256_1354
 
 /* Aspect ratio flag bitmask (4 bits 22:19) */
 #define DRM_MODE_FLAG_PIC_AR_MASK  (0x0F<<19)
@@ -90,6 +92,10 @@ extern "C" {
(DRM_MODE_PICTURE_ASPECT_4_3<<19)
 #define  DRM_MODE_FLAG_PIC_AR_16_9 \
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
+#define  DRM_MODE_FLAG_PIC_AR_64_27 \
+   (DRM_MODE_PICTURE_ASPECT_64_27<<19)
+#define  DRM_MODE_FLAG_PIC_AR_256_135 \
+   (DRM_MODE_PICTURE_ASPECT_256_135<<19)
 
 /* DPMS flags */
 /* bit compatible with the xorg definitions. */
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 2/4] drm: Add aspect ratio parsing in DRM layer

[Shashank Sharma]

Current DRM layer functions don't parse aspect ratio information
while converting a user mode->kernel mode or vice versa. This
causes modeset to pick mode with wrong aspect ratio, eventually
causing failures in HDMI compliance test cases, due to wrong VIC.

This patch adds aspect ratio information in DRM's mode conversion
and mode comparision functions, to make sure kernel picks mode
with right aspect ratio (as per the VIC).

V2: Addressed review comments from Sean:
- Fix spellings/typo
- No need to handle aspect ratio none
- Add a break, for default case too

Signed-off-by: Shashank Sharma 
Signed-off-by: Lin, Jia 
Signed-off-by: Akashdeep Sharma 

Cc: Daniel Vetter 
Cc: Emil Velikov 
---
 drivers/gpu/drm/drm_modes.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index fc5040a..9d8f00d 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -969,6 +969,7 @@ bool drm_mode_equal_no_clocks_no_stereo(const struct 
drm_display_mode *mode1,
mode1->vsync_end == mode2->vsync_end &&
mode1->vtotal == mode2->vtotal &&
mode1->vscan == mode2->vscan &&
+   mode1->picture_aspect_ratio == mode2->picture_aspect_ratio &&
(mode1->flags & ~DRM_MODE_FLAG_3D_MASK) ==
 (mode2->flags & ~DRM_MODE_FLAG_3D_MASK))
return true;
@@ -1471,6 +1472,21 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo 
*out,
out->vrefresh = in->vrefresh;
out->flags = in->flags;
out->type = in->type;
+   out->flags &= ~DRM_MODE_FLAG_PIC_AR_MASK;
+
+   switch (in->picture_aspect_ratio) {
+   case HDMI_PICTURE_ASPECT_4_3:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_4_3;
+   break;
+   case HDMI_PICTURE_ASPECT_16_9:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
+   break;
+   case HDMI_PICTURE_ASPECT_RESERVED:
+   default:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
+   break;
+   }
+
strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 }
@@ -1516,6 +1532,21 @@ int drm_mode_convert_umode(struct drm_display_mode *out,
strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 
+   /* Clearing picture aspect ratio bits from out flags */
+   out->flags &= ~DRM_MODE_FLAG_PIC_AR_MASK;
+
+   switch (in->flags & DRM_MODE_FLAG_PIC_AR_MASK) {
+   case DRM_MODE_FLAG_PIC_AR_4_3:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_4_3;
+   break;
+   case DRM_MODE_FLAG_PIC_AR_16_9:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_16_9;
+   break;
+   default:
+   out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+   break;
+   }
+
out->status = drm_mode_validate_basic(out);
if (out->status != MODE_OK)
goto out;
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 1/4] drm: add picture aspect ratio flags

[Shashank Sharma]

This patch adds drm flag bits for aspect ratio information

Currently drm flag bits don't have field for mode's picture
aspect ratio. This field will help the driver to pick mode with
right aspect ratio, and help in setting right VIC field in avi
infoframes.

Signed-off-by: Shashank Sharma 

V2: Addressed review comments from Sean
- Changed PAR-> PIC_AR

Cc: Daniel Vetter 
Cc: Emil Velikov 
---
 include/uapi/drm/drm_mode.h | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 49a7265..77c869d6 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -77,6 +77,19 @@ extern "C" {
 #define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM   (7<<14)
 #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14)
 
+/* Picture aspect ratio options */
+#define DRM_MODE_PICTURE_ASPECT_NONE   0
+#define DRM_MODE_PICTURE_ASPECT_4_31
+#define DRM_MODE_PICTURE_ASPECT_16_9   2
+
+/* Aspect ratio flag bitmask (4 bits 22:19) */
+#define DRM_MODE_FLAG_PIC_AR_MASK  (0x0F<<19)
+#define  DRM_MODE_FLAG_PIC_AR_NONE \
+   (DRM_MODE_PICTURE_ASPECT_NONE<<19)
+#define  DRM_MODE_FLAG_PIC_AR_4_3 \
+   (DRM_MODE_PICTURE_ASPECT_4_3<<19)
+#define  DRM_MODE_FLAG_PIC_AR_16_9 \
+   (DRM_MODE_PICTURE_ASPECT_16_9<<19)
 
 /* DPMS flags */
 /* bit compatible with the xorg definitions. */
@@ -92,11 +105,6 @@ extern "C" {
 #define DRM_MODE_SCALE_CENTER  2 /* Centered, no scaling */
 #define DRM_MODE_SCALE_ASPECT  3 /* Full screen, preserve aspect */
 
-/* Picture aspect ratio options */
-#define DRM_MODE_PICTURE_ASPECT_NONE   0
-#define DRM_MODE_PICTURE_ASPECT_4_31
-#define DRM_MODE_PICTURE_ASPECT_16_9   2
-
 /* Dithering mode options */
 #define DRM_MODE_DITHERING_OFF 0
 #define DRM_MODE_DITHERING_ON  1
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 0/4] Picture aspect ratio support in DRM layer

[Shashank Sharma]

This patch series adds 4 patches.
- The first two patches add aspect ratio support in DRM layes
- Next two patches add new aspect ratios defined in CEA-861-F
  supported for HDMI 2.0 4k modes.

Adding aspect ratio support in DRM layer:
- The CEA videmodes contain aspect ratio information, which we
  parse when we read the modes from EDID. But while transforming
  user_mode to kernel_mode or viceversa, DRM layer lose this
  information.
- HDMI compliance testing for CEA modes, expects the AVI info frames
  to contain exact VIC no for the 'video mode under test'. Now CEA
  modes have different VIC for same modes but different aspect ratio
  for example:
VIC 2 = 720x480@60 4:3
VIC 3 = 720x480@60 16:9
  In this way, lack of aspect ratio information, can cause wrong VIC
  no in AVI IF, causing HDMI complaince test to fail.
- This patch set adds code, which embeds the aspect ratio information
  also in DRM video mode flags, and uses it while comparing two modes.

Adding new aspect ratios for HDMI 2.0
- CEA-861-F defines two new aspect ratios, to be used for 4k HDMI 2.0
  modes.
- 64:27
- 256:135
Last two patches in the series, adds code to handle these new
aspect ratios.

V2: Fixed review comments from Sean, Emil, Daniel 

Shashank Sharma (4):
  drm: add picture aspect ratio flags
  drm: Add aspect ratio parsing in DRM layer
  video: Add new aspect ratios for HDMI 2.0
  drm: Add and handle new aspect ratios in DRM layer

 drivers/gpu/drm/drm_modes.c | 43 +++
 drivers/video/hdmi.c|  4 
 include/linux/hdmi.h|  2 ++
 include/uapi/drm/drm_mode.h | 24 +++-
 4 files changed, 68 insertions(+), 5 deletions(-)

-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx