Re: [Intel-gfx] [PATCH v4 0/3] drm/i915: fix some audio support 4K resolution issues

2016-08-21 Thread Yang, Libin 
Any comments?

Regards,
Libin


> -Original Message-
> From: libin.y...@linux.intel.com [mailto:libin.y...@linux.intel.com]
> Sent: Thursday, August 18, 2016 2:42 PM
> To: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> ville.syrj...@linux.intel.com; Vetter, Daniel ;
> ti...@suse.de
> Cc: Yang, Libin ; Libin Yang
> 
> Subject: [PATCH v4 0/3] drm/i915: fix some audio support 4K resolution
> issues
> 
> From: Libin Yang 
> 
> changelog:
> v1: initial patches
> 
> v2: change to use crtc->config->port_clock instead of mode->clock for dp
> change to use mode->crtc_clock instead of mode->clock
>   rename mode to adjusted_mode
> 
> v3: add support for 270MHz
> add more platforms support
>   use u16 n; u16 m to save the space
>   add support for 192KHz, 96KHz, 88.2KHz
>   split patch for more platform support separately
> 
> v4: change to use intel_crtc_has_dp_encoder() to support DP MST
> add support for 176.4KHz
> fix some tiny code style issues
> reset cts to 0 for HDMI mode
> 
> Libin Yang (3):
>   drm/i915: set proper N/M in modeset
>   drm/i915: set proper N/MCTS on more platforms
>   drm/i915: HDMI audio gets the TMDS clock by crtc_clock
> 
>  drivers/gpu/drm/i915/i915_reg.h|   7 ++
>  drivers/gpu/drm/i915/intel_audio.c | 155
> +++--
>  2 files changed, 140 insertions(+), 22 deletions(-)
> 
> --
> 1.9.1

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[Intel-gfx] [Regression report] Weekly regression report WW34

2016-08-21 Thread Jairo Miramontes 

This week's new regressions
+---+---+++
| BugId | Summary   | Created on | 
Bisect |

+---+---+++
| 97396 | [drm] stuck on bsd ring (bisected)| 2016-08-18 | 
Yes|

+---+---+++


Previous regressions
+---+---+++
| BugId | Summary   | Created on | 
Bisect |

+---+---+++
| 90112 | [BSW bisected] OglGSCloth/Lightsmark/CS/ Port | 2015-04-20 | 
Yes|
| 94590 | [KBL/BXT] igt/kms_fbcon_fbt/psr-suspend regre | 2016-03-17 | 
No |
| 97215 | [KBL] [Regression] pm_rps / reset fails   | 2016-08-05 | 
No |
| 93263 | 945GM regression since 4.3| 2015-12-05 | 
No |
| 72782 | [945GM bisected] screen blank on S3 resume on | 2013-12-17 | 
Yes|
| 92414 | [Intel-gfx] As of kernel 4.3-rc1 system will  | 2015-10-10 | 
Yes|
| 92050 | [regression]/bug introduced by commit [0e572f | 2015-09-19 | 
No |
| 93802 | [IVB bisected] switching to tty1 causes fifo  | 2016-01-20 | 
Yes|
| 94587 | [KBL] igt/kms_plane/plane-panning-bottom-righ | 2016-03-17 | 
No |
| 96800 | [regression] The drm-intel-nightly branch no  | 2016-07-04 | 
No |
| 95736 | [IVB bisected] *ERROR* uncleared fifo underru | 2016-05-24 | 
Yes|
| 89728 | [HSW/BDW/BYT bisected] igt / pm_rps / reset f | 2015-03-23 | 
Yes|
| 89629 | [i965 regression]igt/kms_rotation_crc/sprite- | 2015-03-18 | 
No |
| 92502 | [SKL] [Regression] igt/kms_flip/2x-flip-vs-ex | 2015-10-16 | 
No |
| 97254 | [SKL] [regression] divide error:  / RIP s | 2016-08-09 | 
No |
| 97242 | [SKL] Bad mouse cursor flickering since 4.8-r | 2016-08-08 | 
No |
| 97139 | [IVB][REGRESSION] i915: Intermittent short sy | 2016-07-29 | 
Yes|
| 96938 | [HSW modeset regression] i915/drm locks up wh | 2016-07-15 | 
No |
| 87131 | [PNV regression] igt/gem_exec_lut_handle take | 2014-12-09 | 
No |
| 87726 | [BDW Bisected] OglDrvCtx performance reduced  | 2014-12-26 | 
Yes|
| 91974 | [bisected] unrecoverable black screen after k | 2015-09-11 | 
Yes|
| 96645 | [regression 4.7] [BISECT]Low package c-states | 2016-06-22 | 
Yes|
| 94430 | [HSW+nvidia] regression: display becomes "dis | 2016-03-07 | 
No |
| 97295 | Regression backlight control broken on Dell X | 2016-08-11 | 
No |
| 93971 | video framerate performance regression with U | 2016-02-02 | 
No |
| 89872 | [ HSW Bisected ] VGA was white screen when re | 2015-04-02 | 
Yes|
| 96428 | [IVB bisected] [drm:intel_dp_aux_ch] *ERROR*  | 2016-06-07 | 
Yes|
| 91959 | [865g Linux regression] GPU hang and disabled | 2015-09-10 | 
No |
| 95097 | [hdmi regression ilk] no signal to TV | 2016-04-24 | 
No |
| 94748 | Black screen on Skylake (mouse position relat | 2016-03-29 | 
No |
| 97216 | [KBL] [Regression] pm_rps / min-max-config-lo | 2016-08-05 | 
No |
| 92972 | Black screen on Intel NUC hardware (i915) pos | 2015-11-16 | 
No |
| 87725 | [BDW Bisected] OglBatch7 performance reduced  | 2014-12-26 | 
Yes|
| 94676 | Possible kernel regression for gen3 and earli | 2016-03-23 | 
No |
| 97182 | [REGRESSION][BISECT] Linux 4.8: SKL DMC Versi | 2016-08-02 | 
Yes|
| 94337 | Linux 4.5 regression: FIFO underruns on Skyla | 2016-02-29 | 
No |
| 97017 | [SKL GT3e guc bisected] ~10% performance drop | 2016-07-21 | 
Yes|
| 96916 | Regression: screen flashes with PSR enabled   | 2016-07-13 | 
No |
| 90368 | [SNB BSW SKL BXT KBL] bisected igt/kms_3d has | 2015-05-08 | 
Yes|
| 94588 | [KBL/BSW/BXT] igt/gem_reloc_overflow regressi | 2016-03-17 | 
No |
| 96736 | kernel 4.6 regression: PSR causes screen to f | 2016-06-29 | 
No |
| 90732 | [BDW/BSW Bisected]igt/gem_reloc_vs_gpu/forked | 2015-05-29 | 
Yes|
| 90134 | [BSW Bisected]GFXBench3_gl_driver/GFXBench3_g | 2015-04-22 | 
Yes|
| 96704 | kernel 4.6 regression: PSR on Haswell causes  | 2016-06-28 | 
No |
| 93782 | [i9xx TV][BISECT] vblank wait timeout on crtc | 2016-01-19 | 
Yes|
| 89632 | [i965 regression]igt/kms_universal_plane/univ | 2015-03-18 | 
No |
| 88439 | [BDW Bisected]igt/gem_reloc_vs_gpu/forked-fau | 2015-01-15 | 
Yes|
| 92237 | [SNB]Horrible noise (audio) via DisplayPort [ | 2015-10-02 | 
No |
| 93393 | Regression for Skylake modesetting in kernel  | 2015-12-16 | 
No |
| 95197 | [i915] regression in 4.6-rc5: GPU HANG: ecode | 2016-04-28 | 
No |

+---+---+++
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Re: [Intel-gfx] drm/i915/slpc: Update freq min/max softlimits

2016-08-21 Thread Kamble, Sagar A 



On 8/21/2016 2:09 PM, Chris Wilson wrote:

On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote:


On 8/20/2016 1:32 PM, Chris Wilson wrote:

On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:

+   obj = dev_priv->guc.slpc.vma->obj;
+   if (obj) {

OOPS.

Fixed in next series.

+   intel_slpc_query_task_state(dev_priv);
+
+   page = i915_gem_object_get_page(obj, 0);
+   if (page)
+   pv = kmap_atomic(page);
+   }
+
+   if (pv) {
+   data = *(struct slpc_shared_data *) pv;
+   kunmap_atomic(pv);

Can kmap_atomic return zero?

Fixed in next series.

+
+   /*
+* TODO: Define separate variables for slice and unslice
+*   frequencies for driver state variable.
+*/
+   dev_priv->rps.max_freq_softlimit =
+   data.task_state_data.freq_unslice_max;
+   dev_priv->rps.min_freq_softlimit =
+   data.task_state_data.freq_unslice_min;

These are user values, you do not get to arbitrarily rewrite them.

You control dev_priv->rps.[min|max]_freq.

With SLPC, GuC firmware SLPC S/W requested frequency be operated in
the softlimits analogous to
Host softlimits. Limits might be different with SLPC and can be
controlled through regular interfaces.
dev_priv->rps.[min|max]_freq are HW Min/Max.

Exactly. The soft limits are *only* set by the user. They are not to
modified by the driver. (The caveat would be a dynamic update of the hw
range, but that too should never be required.)
-Chris

This initialization is similar to following from intel_init_gt_powersave
dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
I assume min_freq is hw min(RPn). With SLPC, min_freq(RPn) will not be 
requested.

SLPC operating range today is (>Rpe, Rp0) so I wanted user to know
the min_softlimit being initialized by SLPC by default.






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[Intel-gfx] [PATCH -next] drm/i915: Fix non static symbol warning

2016-08-21 Thread Wei Yongjun 
From: Wei Yongjun 

Fixes the following sparse warning:

drivers/gpu/drm/i915/intel_hotplug.c:480:6: warning:
 symbol 'i915_hpd_poll_init_work' was not declared. Should it be static?

Also move the '{' to new line.

Signed-off-by: Wei Yongjun 
---
 drivers/gpu/drm/i915/intel_hotplug.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hotplug.c 
b/drivers/gpu/drm/i915/intel_hotplug.c
index 5dc2c20..334d47b 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -477,7 +477,8 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
spin_unlock_irq(_priv->irq_lock);
 }
 
-void i915_hpd_poll_init_work(struct work_struct *work) {
+static void i915_hpd_poll_init_work(struct work_struct *work)
+{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
 hotplug.poll_init_work);

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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Track pinned vma in intel_plane_state

2016-08-21 Thread Chris Wilson 
On Sun, Aug 21, 2016 at 02:15:34PM +0100, Chris Wilson wrote:
>  intel_cleanup_plane_fb(struct drm_plane *plane,
>  struct drm_plane_state *old_state)
>  {
> - struct drm_device *dev = plane->dev;
> - struct intel_plane_state *old_intel_state;
> - struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
> - struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
> -
> - old_intel_state = to_intel_plane_state(old_state);
> -
> - if (!obj && !old_obj)
> - return;
> -
> - if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
> - !INTEL_INFO(dev)->cursor_needs_physical))
> - intel_unpin_fb_obj(old_state->fb, old_state->rotation);
> + /* Only called after a successful intel_prepare_plane_fb() */

Not true. Disabled state have NULL vma. Last minute changes...

> + intel_unpin_fb_vma(to_intel_plane_state(old_state)->vma);
>  }

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 5/6] drm/i915: Quick spring clean of intel_prepare_plane_fb()

2016-08-21 Thread Chris Wilson 
Just a quick tidy now to make the next patch neater.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_display.c | 43 +---
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9fc4c5406a75..8925f9d6ecfd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13904,6 +13904,17 @@ static int intel_atomic_check(struct drm_device *dev,
return calc_watermark_data(state);
 }
 
+static bool old_plane_needs_modeset(struct drm_plane *plane,
+   struct drm_plane_state *new_state)
+{
+   struct drm_crtc_state *crtc_state;
+
+   crtc_state = drm_atomic_get_existing_crtc_state(new_state->state,
+   plane->state->crtc);
+
+   return needs_modeset(crtc_state);
+}
+
 /**
  * intel_prepare_plane_fb - Prepare fb for usage on plane
  * @plane: drm plane to prepare for
@@ -13925,16 +13936,12 @@ intel_prepare_plane_fb(struct drm_plane *plane,
struct drm_device *dev = plane->dev;
struct drm_framebuffer *fb = new_state->fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-   struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
struct reservation_object *resv;
-   int ret = 0;
-
-   if (!obj && !old_obj)
-   return 0;
+   int ret;
 
-   if (old_obj) {
-   struct drm_crtc_state *crtc_state =
-   drm_atomic_get_existing_crtc_state(new_state->state, 
plane->state->crtc);
+   if (plane->state->fb && old_plane_needs_modeset(plane, new_state)) {
+   struct drm_i915_gem_object *old_obj =
+   intel_fb_obj(plane->state->fb);
 
/* Big Hammer, we also need to ensure that any pending
 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
@@ -13947,8 +13954,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 * This should only fail upon a hung GPU, in which case we
 * can safely continue.
 */
-   if (needs_modeset(crtc_state))
-   ret = i915_gem_object_wait_rendering(old_obj, true);
+
+   ret = i915_gem_object_wait_rendering(old_obj, true);
if (ret) {
/* GPU hangs should have been swallowed by the wait */
WARN_ON(ret == -EIO);
@@ -13976,25 +13983,25 @@ intel_prepare_plane_fb(struct drm_plane *plane,
INTEL_INFO(dev)->cursor_needs_physical) {
int align = IS_I830(dev) ? 16 * 1024 : 256;
ret = i915_gem_object_attach_phys(obj, align);
-   if (ret)
+   if (ret) {
DRM_DEBUG_KMS("failed to attach phys object\n");
+   return ret;
+   }
} else {
struct i915_vma *vma;
 
vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
if (IS_ERR(vma))
-   ret = PTR_ERR(vma);
+   return PTR_ERR(vma);
 
to_intel_plane_state(new_state)->vma = vma;
}
 
-   if (ret == 0) {
-   new_state->fence =
-   _gem_active_get(>last_write,
-
>base.dev->struct_mutex)->fence;
-   }
+   new_state->fence =
+   _gem_active_get(>last_write,
+>base.dev->struct_mutex)->fence;
 
-   return ret;
+   return 0;
 }
 
 /**
-- 
2.9.3

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[Intel-gfx] [PATCH 1/6] drm/i915: Replace intel_plane->wait_req with plane->fence

2016-08-21 Thread Chris Wilson 
Now that we subclass our request from struct fence, we start using the
common primitives more freely and so avoid hand-rolling routines already
provided for by the helpers.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |  3 --
 drivers/gpu/drm/i915/intel_display.c  | 52 +++
 drivers/gpu/drm/i915/intel_drv.h  |  1 -
 3 files changed, 5 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index b82de3072d4f..b41bf380f2ab 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -77,14 +77,12 @@ intel_plane_duplicate_state(struct drm_plane *plane)
struct intel_plane_state *intel_state;
 
intel_state = kmemdup(plane->state, sizeof(*intel_state), GFP_KERNEL);
-
if (!intel_state)
return NULL;
 
state = _state->base;
 
__drm_atomic_helper_plane_duplicate_state(plane, state);
-   intel_state->wait_req = NULL;
 
return state;
 }
@@ -101,7 +99,6 @@ void
 intel_plane_destroy_state(struct drm_plane *plane,
  struct drm_plane_state *state)
 {
-   WARN_ON(state && to_intel_plane_state(state)->wait_req);
drm_atomic_helper_plane_destroy_state(plane, state);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d224f64836c5..0eb30539f7f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13929,9 +13929,7 @@ static int intel_atomic_prepare_commit(struct 
drm_device *dev,
   bool nonblock)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct drm_plane_state *plane_state;
struct drm_crtc_state *crtc_state;
-   struct drm_plane *plane;
struct drm_crtc *crtc;
int i, ret;
 
@@ -13954,27 +13952,6 @@ static int intel_atomic_prepare_commit(struct 
drm_device *dev,
ret = drm_atomic_helper_prepare_planes(dev, state);
mutex_unlock(>struct_mutex);
 
-   if (!ret && !nonblock) {
-   for_each_plane_in_state(state, plane, plane_state, i) {
-   struct intel_plane_state *intel_plane_state =
-   to_intel_plane_state(plane_state);
-
-   if (!intel_plane_state->wait_req)
-   continue;
-
-   ret = i915_wait_request(intel_plane_state->wait_req,
-   true, NULL, NULL);
-   if (ret) {
-   /* Any hang should be swallowed by the wait */
-   WARN_ON(ret == -EIO);
-   mutex_lock(>struct_mutex);
-   drm_atomic_helper_cleanup_planes(dev, state);
-   mutex_unlock(>struct_mutex);
-   break;
-   }
-   }
-   }
-
return ret;
 }
 
@@ -14061,27 +14038,12 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
struct drm_crtc_state *old_crtc_state;
struct drm_crtc *crtc;
struct intel_crtc_state *intel_cstate;
-   struct drm_plane *plane;
-   struct drm_plane_state *plane_state;
bool hw_check = intel_state->modeset;
unsigned long put_domains[I915_MAX_PIPES] = {};
unsigned crtc_vblank_mask = 0;
-   int i, ret;
-
-   for_each_plane_in_state(state, plane, plane_state, i) {
-   struct intel_plane_state *intel_plane_state =
-   to_intel_plane_state(plane_state);
-
-   if (!intel_plane_state->wait_req)
-   continue;
-
-   ret = i915_wait_request(intel_plane_state->wait_req,
-   true, NULL, NULL);
-   /* EIO should be eaten, and we can't get interrupted in the
-* worker, and blocking commits have waited already. */
-   WARN_ON(ret);
-   }
+   int i;
 
+   drm_atomic_helper_wait_for_fences(dev, state);
drm_atomic_helper_wait_for_dependencies(state);
 
if (intel_state->modeset) {
@@ -14491,9 +14453,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
}
 
if (ret == 0) {
-   to_intel_plane_state(new_state)->wait_req =
-   i915_gem_active_get(>last_write,
-   >base.dev->struct_mutex);
+   new_state->fence =
+   _gem_active_get(>last_write,
+
>base.dev->struct_mutex)->fence;
}
 
return ret;
@@ -14514,7 +14476,6 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 {
struct drm_device *dev = plane->dev;
struct

[Intel-gfx] [PATCH 4/6] drm/i915: Track pinned vma in intel_plane_state

2016-08-21 Thread Chris Wilson 
With atomic plane states we are able to track an allocation right from
preparation, during use and through to the final free after being
swapped out for a new plane. We can couple the VMA we pin for the
framebuffer (and its rotation) to this lifetime and avoid all the clumsy
lookups in between.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h   | 16 ++
 drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +
 drivers/gpu/drm/i915/intel_display.c  | 85 +++
 drivers/gpu/drm/i915/intel_drv.h  |  9 +++-
 drivers/gpu/drm/i915/intel_fbc.c  | 58 -
 drivers/gpu/drm/i915/intel_fbdev.c|  4 +-
 drivers/gpu/drm/i915/intel_sprite.c   |  8 +--
 7 files changed, 70 insertions(+), 112 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cd102cd931e..536cb557ee17 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -949,6 +949,8 @@ struct intel_fbc {
bool active;
 
struct intel_fbc_state_cache {
+   struct i915_vma *vma;
+
struct {
unsigned int mode_flags;
uint32_t hsw_bdw_pixel_rate;
@@ -962,15 +964,14 @@ struct intel_fbc {
} plane;
 
struct {
-   u64 ilk_ggtt_offset;
uint32_t pixel_format;
unsigned int stride;
-   int fence_reg;
-   unsigned int tiling_mode;
} fb;
} state_cache;
 
struct intel_fbc_reg_params {
+   struct i915_vma *vma;
+
struct {
enum pipe pipe;
enum plane plane;
@@ -978,10 +979,8 @@ struct intel_fbc {
} crtc;
 
struct {
-   u64 ggtt_offset;
uint32_t pixel_format;
unsigned int stride;
-   int fence_reg;
} fb;
 
int cfb_size;
@@ -3325,13 +3324,6 @@ i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
return i915_gem_obj_to_vma(obj, _i915(obj->base.dev)->ggtt.base, 
view);
 }
 
-static inline unsigned long
-i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
-   const struct i915_ggtt_view *view)
-{
-   return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
-}
-
 /* i915_gem_fence.c */
 int __must_check i915_vma_get_fence(struct i915_vma *vma);
 int __must_check i915_vma_put_fence(struct i915_vma *vma);
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 76a5bbbaaa98..b919a4f31df0 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -84,6 +84,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
 
__drm_atomic_helper_plane_duplicate_state(plane, state);
 
+   intel_state->vma = NULL;
+
return state;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9c769b5c91b8..9fc4c5406a75 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2237,24 +2237,19 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 
unsigned int rotation)
i915_vma_pin_fence(vma);
}
 
+   i915_vma_get(vma);
 err:
intel_runtime_pm_put(dev_priv);
return vma;
 }
 
-void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
+void intel_unpin_fb_vma(struct i915_vma *vma)
 {
-   struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-   struct i915_ggtt_view view;
-   struct i915_vma *vma;
-
-   WARN_ON(!mutex_is_locked(>base.dev->struct_mutex));
-
-   intel_fill_fb_ggtt_view(, fb, rotation);
-   vma = i915_gem_object_to_ggtt(obj, );
+   lockdep_assert_held(>vm->dev->struct_mutex);
 
i915_vma_unpin_fence(vma);
i915_gem_object_unpin_from_display_plane(vma);
+   i915_vma_put(vma);
 }
 
 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
@@ -2748,7 +2743,6 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_crtc *c;
-   struct intel_crtc *i;
struct drm_i915_gem_object *obj;
struct drm_plane *primary = intel_crtc->base.primary;
struct drm_plane_state *plane_state = primary->state;
@@ -2773,20 +2767,19 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
 * an fb with another CRTC instead
 */
for_each_crtc(dev, c) {
-   i = to_intel_crtc(c);
+   struct intel_plane_state *state;
 
if (c == _crtc->base)

[Intel-gfx] [PATCH 2/6] drm/i915: Move intel_prepare_plane_fb() and intel_cleanup_plane_fb()

2016-08-21 Thread Chris Wilson 
In the next patch, a few rearrangements are made to make these static.
First, we move them so the changes are not lost in the noise.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_display.c | 239 ++-
 1 file changed, 120 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0eb30539f7f8..c4096204e5a3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13924,6 +13924,126 @@ static int intel_atomic_check(struct drm_device *dev,
return calc_watermark_data(state);
 }
 
+/**
+ * intel_prepare_plane_fb - Prepare fb for usage on plane
+ * @plane: drm plane to prepare for
+ * @fb: framebuffer to prepare for presentation
+ *
+ * Prepares a framebuffer for usage on a display plane.  Generally this
+ * involves pinning the underlying object and updating the frontbuffer tracking
+ * bits.  Some older platforms need special physical address handling for
+ * cursor planes.
+ *
+ * Must be called with struct_mutex held.
+ *
+ * Returns 0 on success, negative error code on failure.
+ */
+int
+intel_prepare_plane_fb(struct drm_plane *plane,
+  struct drm_plane_state *new_state)
+{
+   struct drm_device *dev = plane->dev;
+   struct drm_framebuffer *fb = new_state->fb;
+   struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+   struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
+   struct reservation_object *resv;
+   int ret = 0;
+
+   if (!obj && !old_obj)
+   return 0;
+
+   if (old_obj) {
+   struct drm_crtc_state *crtc_state =
+   drm_atomic_get_existing_crtc_state(new_state->state, 
plane->state->crtc);
+
+   /* Big Hammer, we also need to ensure that any pending
+* MI_WAIT_FOR_EVENT inside a user batch buffer on the
+* current scanout is retired before unpinning the old
+* framebuffer. Note that we rely on userspace rendering
+* into the buffer attached to the pipe they are waiting
+* on. If not, userspace generates a GPU hang with IPEHR
+* point to the MI_WAIT_FOR_EVENT.
+*
+* This should only fail upon a hung GPU, in which case we
+* can safely continue.
+*/
+   if (needs_modeset(crtc_state))
+   ret = i915_gem_object_wait_rendering(old_obj, true);
+   if (ret) {
+   /* GPU hangs should have been swallowed by the wait */
+   WARN_ON(ret == -EIO);
+   return ret;
+   }
+   }
+
+   if (!obj)
+   return 0;
+
+   /* For framebuffer backed by dmabuf, wait for fence */
+   resv = i915_gem_object_get_dmabuf_resv(obj);
+   if (resv) {
+   long lret;
+
+   lret = reservation_object_wait_timeout_rcu(resv, false, true,
+  
MAX_SCHEDULE_TIMEOUT);
+   if (lret == -ERESTARTSYS)
+   return lret;
+
+   WARN(lret < 0, "waiting returns %li\n", lret);
+   }
+
+   if (plane->type == DRM_PLANE_TYPE_CURSOR &&
+   INTEL_INFO(dev)->cursor_needs_physical) {
+   int align = IS_I830(dev) ? 16 * 1024 : 256;
+   ret = i915_gem_object_attach_phys(obj, align);
+   if (ret)
+   DRM_DEBUG_KMS("failed to attach phys object\n");
+   } else {
+   struct i915_vma *vma;
+
+   vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
+   if (IS_ERR(vma))
+   ret = PTR_ERR(vma);
+   }
+
+   if (ret == 0) {
+   new_state->fence =
+   _gem_active_get(>last_write,
+
>base.dev->struct_mutex)->fence;
+   }
+
+   return ret;
+}
+
+/**
+ * intel_cleanup_plane_fb - Cleans up an fb after plane use
+ * @plane: drm plane to clean up for
+ * @fb: old framebuffer that was on plane
+ *
+ * Cleans up a framebuffer that has just been removed from a plane.
+ *
+ * Must be called with struct_mutex held.
+ */
+void
+intel_cleanup_plane_fb(struct drm_plane *plane,
+  struct drm_plane_state *old_state)
+{
+   struct drm_device *dev = plane->dev;
+   struct intel_plane_state *old_intel_state;
+   struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
+   struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
+
+   old_intel_state = to_intel_plane_state(old_state);
+
+   if (!obj && !old_obj)
+   return;
+
+   if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
+   !INTEL_INFO(dev)->cursor_needs_physical))
+

[Intel-gfx] [PATCH 3/6] drm/i915: Always prepare planes at the start of an atomic commit

2016-08-21 Thread Chris Wilson 
The generic atomic helper likes to skip a prepare_plane_fb() if it
decides that the plane->fb is unchanged. This is wrong for us for a
couple of reasons:

 - if the pipe is reconfigured (i.e. a size change) but the framebuffer
   is untouched, we still have to flush any rendering prior to the
   reconfiguration to prevent wait-for-scanline GPU hangs

 - if the framebuffer is rotated, it remains the same but has a
   different view and a different address.

Finally, even if the framebuffer is unchanged the flip/modeset should be
ordered with respect to rendering to the frontbuffer.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |  2 --
 drivers/gpu/drm/i915/intel_display.c  | 60 ---
 drivers/gpu/drm/i915/intel_drv.h  |  4 ---
 3 files changed, 47 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index b41bf380f2ab..76a5bbbaaa98 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -190,8 +190,6 @@ static void intel_plane_atomic_update(struct drm_plane 
*plane,
 }
 
 const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
-   .prepare_fb = intel_prepare_plane_fb,
-   .cleanup_fb = intel_cleanup_plane_fb,
.atomic_check = intel_plane_atomic_check,
.atomic_update = intel_plane_atomic_update,
 };
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c4096204e5a3..9c769b5c91b8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13938,7 +13938,7 @@ static int intel_atomic_check(struct drm_device *dev,
  *
  * Returns 0 on success, negative error code on failure.
  */
-int
+static int
 intel_prepare_plane_fb(struct drm_plane *plane,
   struct drm_plane_state *new_state)
 {
@@ -14024,7 +14024,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
  *
  * Must be called with struct_mutex held.
  */
-void
+static void
 intel_cleanup_plane_fb(struct drm_plane *plane,
   struct drm_plane_state *old_state)
 {
@@ -14043,6 +14043,49 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
intel_unpin_fb_obj(old_state->fb, old_state->rotation);
 }
 
+static int intel_atomic_commit_prepare_planes(struct drm_atomic_state *state)
+{
+   struct drm_plane *plane;
+   struct drm_plane_state *plane_state;
+   int i, j, ret;
+
+   ret = mutex_lock_interruptible(>dev->struct_mutex);
+   if (ret)
+   return ret;
+
+   for_each_plane_in_state(state, plane, plane_state, i) {
+   ret = intel_prepare_plane_fb(plane, plane_state);
+   if (ret)
+   break;
+   }
+
+   if (ret) {
+   for_each_plane_in_state(state, plane, plane_state, j) {
+   if (j >= i)
+   break;
+
+   intel_cleanup_plane_fb(plane, plane_state);
+   }
+   }
+
+   mutex_unlock(>dev->struct_mutex);
+
+   return ret;
+}
+
+static void intel_atomic_commit_cleanup_planes(struct drm_atomic_state *state)
+{
+   struct drm_plane *plane;
+   struct drm_plane_state *plane_state;
+   int i;
+
+   mutex_lock(>dev->struct_mutex);
+
+   for_each_plane_in_state(state, plane, plane_state, i)
+   intel_cleanup_plane_fb(plane, plane_state);
+
+   mutex_unlock(>dev->struct_mutex);
+}
 
 static int intel_atomic_prepare_commit(struct drm_device *dev,
   struct drm_atomic_state *state,
@@ -14065,14 +14108,7 @@ static int intel_atomic_prepare_commit(struct 
drm_device *dev,
flush_workqueue(dev_priv->wq);
}
 
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   mutex_unlock(>struct_mutex);
-
-   return ret;
+   return intel_atomic_commit_prepare_planes(state);
 }
 
 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
@@ -14301,9 +14337,7 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
if (intel_state->modeset)
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
 
-   mutex_lock(>struct_mutex);
-   drm_atomic_helper_cleanup_planes(dev, state);
-   mutex_unlock(>struct_mutex);
+   intel_atomic_commit_cleanup_planes(state);
 
drm_atomic_helper_commit_cleanup_done(state);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index acb42d66fb08..3416796e5343 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1249,10 +1249,6 @@ __intel_framebuffer_create(struct drm_device *dev,
 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int

[Intel-gfx] [PATCH 6/6] drm/i915: Set crtc_state->fb_changed whenever a VMA is changed

2016-08-21 Thread Chris Wilson 
Since an fb may have multiple VMA (due to rotations etc), we need to
wait a vblank and unpin the old VMA not if the fb itself is changed, but
if the underlying VMA is changed.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_display.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8925f9d6ecfd..a52a7ef8aecf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12315,9 +12315,6 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
if (!was_visible && !visible)
return 0;
 
-   if (fb != old_plane_state->base.fb)
-   pipe_config->fb_changed = true;
-
turn_off = was_visible && (!visible || mode_changed);
turn_on = visible && (!was_visible || mode_changed);
 
@@ -13995,6 +13992,13 @@ intel_prepare_plane_fb(struct drm_plane *plane,
return PTR_ERR(vma);
 
to_intel_plane_state(new_state)->vma = vma;
+   if (to_intel_plane_state(plane->state)->vma != vma) {
+   struct intel_crtc_state *crtc_state;
+
+   crtc_state = 
intel_atomic_get_crtc_state(new_state->state,
+
to_intel_crtc(new_state->crtc));
+   crtc_state->fb_changed = true;
+   }
}
 
new_state->fence =
-- 
2.9.3

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Re: [Intel-gfx] drm/i915/slpc: Update freq min/max softlimits

2016-08-21 Thread Chris Wilson 
On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote:
> 
> 
> On 8/20/2016 1:32 PM, Chris Wilson wrote:
> >On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:
> >>+   obj = dev_priv->guc.slpc.vma->obj;
> >>+   if (obj) {
> >OOPS.
> Fixed in next series.
> >
> >>+   intel_slpc_query_task_state(dev_priv);
> >>+
> >>+   page = i915_gem_object_get_page(obj, 0);
> >>+   if (page)
> >>+   pv = kmap_atomic(page);
> >>+   }
> >>+
> >>+   if (pv) {
> >>+   data = *(struct slpc_shared_data *) pv;
> >>+   kunmap_atomic(pv);
> >Can kmap_atomic return zero?
> Fixed in next series.
> >
> >>+
> >>+   /*
> >>+* TODO: Define separate variables for slice and unslice
> >>+*   frequencies for driver state variable.
> >>+*/
> >>+   dev_priv->rps.max_freq_softlimit =
> >>+   data.task_state_data.freq_unslice_max;
> >>+   dev_priv->rps.min_freq_softlimit =
> >>+   data.task_state_data.freq_unslice_min;
> >These are user values, you do not get to arbitrarily rewrite them.
> >
> >You control dev_priv->rps.[min|max]_freq.
> With SLPC, GuC firmware SLPC S/W requested frequency be operated in
> the softlimits analogous to
> Host softlimits. Limits might be different with SLPC and can be
> controlled through regular interfaces.
> dev_priv->rps.[min|max]_freq are HW Min/Max.

Exactly. The soft limits are *only* set by the user. They are not to
modified by the driver. (The caveat would be a dynamic update of the hw
range, but that too should never be required.)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] drm/i915/slpc: Send reset event

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Add host2guc SLPC reset event and send reset event
during enable.

v1: Extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
host2guc_action to i915_guc_action change.(Sagar)
Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c | 28 
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index bb2e5fe..b6de200 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 
len)
+{
+   int ret = i915_guc_action(_priv->guc, data, len);
+
+   if (!ret) {
+   ret = I915_READ(SOFT_SCRATCH(1));
+   ret &= SLPC_EVENT_STATUS_MASK;
+   }
+
+   if (ret)
+   DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+   u32 data[4];
+   u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+   data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+   data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+   data[2] = shared_data_gtt_offset;
+   data[3] = 0;
+
+   host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
enum slpc_platform_sku platform_sku;
@@ -135,6 +161,8 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+   host2guc_slpc_reset(dev_priv);
+   dev_priv->guc.slpc.enabled = true;
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h 
b/drivers/gpu/drm/i915/intel_slpc.h
index e951289..031e36b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_event_id {
+   SLPC_EVENT_RESET = 0,
+   SLPC_EVENT_SHUTDOWN = 1,
+   SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+   SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+   SLPC_EVENT_FLIP_COMPLETE = 4,
+   SLPC_EVENT_QUERY_TASK_STATE = 5,
+   SLPC_EVENT_PARAMETER_SET = 6,
+   SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK 0xFF
+
 enum slpc_global_state {
SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[Intel-gfx] drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early

2016-08-21 Thread Sagar Arun Kamble 
This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d5d0a50..627d223 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1629,6 +1629,7 @@ static int i915_drm_resume(struct drm_device *dev)
 static int i915_drm_resume_early(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
int ret;
 
/*
@@ -1685,6 +1686,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
  ret);
 
+   /*
+* Mark GuC FW load status as PENDING to avoid any Host to GuC actions
+* invoked till GuC gets loaded in i915_drm_resume.
+   */
+   guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+
intel_uncore_early_sanitize(dev_priv, true);
 
if (IS_BROXTON(dev_priv)) {
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Add slpc support for max/min freq

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2ae1fff..6bbed50 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4959,6 +4959,15 @@ i915_max_freq_set(void *data, u64 val)
 
dev_priv->rps.max_freq_softlimit = val;
 
+   if (intel_slpc_active(dev_priv)) {
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   }
+
intel_set_rps(dev_priv, val);
 
mutex_unlock(_priv->rps.hw_lock);
@@ -5015,6 +5024,15 @@ i915_min_freq_set(void *data, u64 val)
 
dev_priv->rps.min_freq_softlimit = val;
 
+   if (intel_slpc_active(dev_priv)) {
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   }
+
intel_set_rps(dev_priv, val);
 
mutex_unlock(_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 5547f41..6a0b319 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -431,6 +431,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
dev_priv->rps.max_freq_softlimit = val;
 
+   if (intel_slpc_active(dev_priv)) {
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
  dev_priv->rps.min_freq_softlimit,
  dev_priv->rps.max_freq_softlimit);
@@ -488,6 +497,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
dev_priv->rps.min_freq_softlimit = val;
 
+   if (intel_slpc_active(dev_priv)) {
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+   }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
  dev_priv->rps.min_freq_softlimit,
  dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Send shutdown event

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Added SLPC state update during disable, suspend and reset.
Changed semantics of reset. It is supposed to just disable. (Sagar)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index b6de200..637eacb 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private 
*dev_priv)
host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+   u32 data[4];
+   u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+   data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+   data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+   data[2] = shared_data_gtt_offset;
+   data[3] = 0;
+
+   host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
enum slpc_platform_sku platform_sku;
@@ -153,10 +166,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
+   host2guc_slpc_shutdown(dev_priv);
+   dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
+   host2guc_slpc_shutdown(dev_priv);
+   dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
@@ -167,4 +184,6 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
 {
+   host2guc_slpc_shutdown(dev_priv);
+   dev_priv->guc.slpc.enabled = false;
 }
-- 
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[Intel-gfx] drm/i915/slpc: Use intel_slpc_* functions if supported

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v1: Return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with intel_slpc_enabled()
or intel_slpc_active() (Paulo)
Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
"drm/i915/bxt: Explicitly clear the Turbo control register"
Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
Performance drop with SLPC was happening as ring frequency table
was not programmed when SLPC was enabled. This patch programs ring
frequency table with SLPC. Initial reset of SLPC is based on kernel
parameter as planning to add slpc state in intel_slpc_active. Cleanup
is also based on kernel parameter as SLPC gets disabled in
disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
Checkpatch update.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/Makefile |  3 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_guc.h  |  1 +
 drivers/gpu/drm/i915/intel_pm.c   | 98 ++-
 drivers/gpu/drm/i915/intel_slpc.c | 50 
 drivers/gpu/drm/i915/intel_slpc.h | 35 ++
 6 files changed, 159 insertions(+), 32 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da246..229290d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,7 +52,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
- i915_guc_submission.o
+ i915_guc_submission.o \
+ intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 774aab3..353cb51 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1692,6 +1692,10 @@ void chv_phy_powergate_lanes(struct intel_encoder 
*encoder,
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
  enum dpio_channel ch, bool override);
 
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
+{
+   return 0;
+}
 
 /* intel_pm.c */
 void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index bf7624f..6fdbac5 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a73672..21dafe0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4906,7 +4906,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 * our rpm wakeref. And then disable the interrupts to stop any
 * futher RPS reclocking whilst we are asleep.
 */
-   gen6_disable_rps_interrupts(dev_priv);
+   if (!intel_slpc_active(dev_priv))
+   gen6_disable_rps_interrupts(dev_priv);
 
mutex_lock(_priv->rps.hw_lock);
if (dev_priv->rps.enabled) {
@@ -6557,6 +6558,9 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
/* Finally allow us to boost to max by default */
dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
 
+   if (intel_slpc_enabled())
+   intel_slpc_init(dev_priv);
+
mutex_unlock(_priv->rps.hw_lock);
mutex_unlock(_priv->drm.struct_mutex);
 
@@ -6565,7 +6569,9 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-   if (IS_VALLEYVIEW(dev_priv))
+   if (intel_slpc_enabled())
+   intel_slpc_cleanup(dev_priv);
+   else if (IS_VALLEYVIEW(dev_priv))
valleyview_cleanup_gt_powersave(dev_priv);
 
if (!i915.enable_rc6)
@@ -6585,28 +6591,42 @@ void intel_suspend_gt_powersave(struct drm_i915_private 
*dev_priv)
if (INTEL_GEN(dev_priv) < 6)
return;
 
-   if (cancel_delayed_work_sync(_priv->rps.autoenable_work))
+   if (cancel_delayed_work_sync(_priv->rps.autoenable_work)) {
+   if (intel_slpc_active(dev_priv))
+   intel_slpc_suspend(dev_priv);
intel_runtime_pm_put(dev_priv);
+   }
 
/* gen6_rps_idle() will be called later to disable interrupts */
 }

[Intel-gfx] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

SLPC shared data is used to pass information
to/from SLPC in GuC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v1: Update for SLPC interface version 2015.2.4
intel_slpc_active() returns 1 if slpc initialized (Paulo)
change default host_os to "Windows"
Spelling fixes (Sagar Kamble and Nick Hoath)
Added WARN for checking if upper 32bits of GTT offset
of shared object are zero. (ChrisW)
Changed function call from gem_allocate/release_guc_obj to
i915_guc_allocate/release_gem_obj. (Sagar)
Updated commit message and moved POWER_PLAN and POWER_SOURCE
definition from later patch. (Akash)
Add struct_mutex locking while allocating/releasing slpc shared
object. This was caught by CI BAT. Adding SLPC state variable
to determine if it is active as it not just dependent on shared
data setup.
Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes. (David)
Checkpatch update.

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_drv.h  |  7 ++-
 drivers/gpu/drm/i915/intel_guc.h  |  2 +
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++-
 drivers/gpu/drm/i915/intel_slpc.c | 92 +++
 drivers/gpu/drm/i915/intel_slpc.h | 78 +
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 353cb51..af96012 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,7 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private 
*dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
-   return 0;
+   int ret = 0;
+
+   if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
+   ret = 1;
+
+   return ret;
 }
 
 /* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 6fdbac5..af4310c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -145,6 +145,8 @@ struct intel_guc {
 
uint64_t submissions[I915_NUM_ENGINES];
uint32_t last_seqno[I915_NUM_ENGINES];
+
+   struct intel_slpc slpc;
 };
 
 static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 14c29b1..0c739c6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6572,7 +6572,8 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-   if (intel_slpc_enabled())
+   if (intel_slpc_enabled() &&
+   dev_priv->guc.slpc.vma)
intel_slpc_cleanup(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
valleyview_cleanup_gt_powersave(dev_priv);
@@ -6662,7 +6663,8 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
 
mutex_lock(_priv->rps.hw_lock);
 
-   if (intel_slpc_enabled()) {
+   if (intel_slpc_enabled() &&
+   dev_priv->guc.slpc.vma) {
gen9_enable_rc6(dev_priv);
intel_slpc_enable(dev_priv);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 2e509a7..bb2e5fe 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,15 +22,107 @@
  *
  */
 #include 
+#include 
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+   enum slpc_platform_sku platform_sku;
+
+   if (IS_SKL_ULX(dev_priv))
+   platform_sku = SLPC_PLATFORM_SKU_ULX;
+   else if (IS_SKL_ULT(dev_priv))
+   platform_sku = SLPC_PLATFORM_SKU_ULT;
+   else
+   platform_sku = SLPC_PLATFORM_SKU_DT;
+
+   WARN_ON(platform_sku > 0xFF);
+
+   return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+   unsigned int slice_count = 1;
+
+   if (IS_SKYLAKE(dev_priv))
+   slice_count = INTEL_INFO(dev_priv)->slice_total;
+
+   return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+   struct drm_i915_gem_object *obj;
+   struct page *page;
+   struct slpc_shared_data *data;
+   u64 msr_value;
+
+   if (!dev_priv->guc.slpc.vma)
+   return;
+
+   obj = dev_priv->guc.slpc.vma->obj;
+
+   page = i915_gem_object_get_page(obj, 0);
+   if (page) {
+

[Intel-gfx] drm/i915: Check GuC load status for Host to GuC action and SLPC status

2016-08-21 Thread Sagar Arun Kamble 
Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.

v2: Space and function return convention issues. (Deepak)

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 4 
 drivers/gpu/drm/i915/intel_drv.h   | 4 
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 9a69bf1..cc1d5e3 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -78,6 +78,7 @@ static inline bool host2guc_action_response(struct 
drm_i915_private *dev_priv,
 int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   struct intel_guc_fw *guc_fw = >guc_fw;
u32 status;
int i;
int ret;
@@ -85,6 +86,9 @@ int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
if (WARN_ON(len < 1 || len > 15))
return -EINVAL;
 
+   if (WARN_ON(guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS))
+   return -ENODEV;
+
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
dev_priv->guc.action_count += 1;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index af96012..64ca0d3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,8 +1694,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private 
*dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
 {
+   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
int ret = 0;
 
+   if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   return ret;
+
if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
ret = 1;
 
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Add SKL SLPC Support

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Move slpc_version_check to intel_guc_ucode_init.
fix whitespace (Sagar)
Moved version check to different patch as has_slpc
should not be updated based on it. Instead module parameter
should be updated based on version check. (Sagar)
Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e678051 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,12 +322,14 @@ static const struct intel_device_info intel_skylake_info 
= {
BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
+   .has_slpc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
+   .has_slpc = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Add enable/disable debugfs for slpc

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Adds debugfs hooks for each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
Avoid magic numbers (Jon Bloomfield)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 252 
 drivers/gpu/drm/i915/intel_slpc.h   |   5 +
 2 files changed, 257 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6bbed50..755941e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1101,6 +1101,255 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
i915_next_seqno_get, i915_next_seqno_set,
"0x%llx\n");
 
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+  enum slpc_param_id enable_id,
+  enum slpc_param_id disable_id)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   int override_enable, override_disable;
+   u32 value_enable, value_disable;
+   int ret = 0;
+
+   if (!intel_slpc_active(dev_priv)) {
+   ret = -ENODEV;
+   } else if (val) {
+   intel_slpc_get_param(dev_priv, enable_id, _enable,
+_enable);
+   intel_slpc_get_param(dev_priv, disable_id, _disable,
+_disable);
+
+   /* set the output value:
+   * 0: default
+   * 1: enabled
+   * 2: disabled
+   * 3: unknown (should not happen)
+   */
+   if (override_disable && (value_disable == 1))
+   *val = SLPC_PARAM_TASK_DISABLED;
+   else if (override_enable && (value_enable == 1))
+   *val = SLPC_PARAM_TASK_ENABLED;
+   else if (!override_enable && !override_disable)
+   *val = SLPC_PARAM_TASK_DEFAULT;
+   else
+   *val = SLPC_PARAM_TASK_UNKNOWN;
+
+   } else {
+   ret = -EINVAL;
+   }
+
+   return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+  enum slpc_param_id enable_id,
+  enum slpc_param_id disable_id)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   int ret = 0;
+
+   if (!intel_slpc_active(dev_priv)) {
+   ret = -ENODEV;
+   } else if (val == SLPC_PARAM_TASK_DEFAULT) {
+   /* set default */
+   intel_slpc_unset_param(dev_priv, enable_id);
+   intel_slpc_unset_param(dev_priv, disable_id);
+   } else if (val == SLPC_PARAM_TASK_ENABLED) {
+   /* set enable */
+   intel_slpc_set_param(dev_priv, enable_id, 1);
+   intel_slpc_unset_param(dev_priv, disable_id);
+   } else if (val == SLPC_PARAM_TASK_DISABLED) {
+   /* set disable */
+   intel_slpc_set_param(dev_priv, disable_id, 1);
+   intel_slpc_unset_param(dev_priv, enable_id);
+   } else {
+   ret = -EINVAL;
+   }
+
+   return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+   enum slpc_param_id disable_id)
+{
+   struct drm_device *dev = m->private;
+   const char *status;
+   u64 val;
+   int ret;
+
+   ret = slpc_enable_disable_get(dev, , enable_id, disable_id);
+
+   if (ret) {
+   seq_printf(m, "error %d\n", ret);
+   } else {
+   switch (val) {
+   case SLPC_PARAM_TASK_DEFAULT:
+   status = "default\n";
+   break;
+
+   case SLPC_PARAM_TASK_ENABLED:
+   status = "enabled\n";
+   break;
+
+   case SLPC_PARAM_TASK_DISABLED:
+   status = "disabled\n";
+   break;
+
+   default:
+   status = "unknown\n";
+   break;
+   }
+
+   seq_puts(m, status);
+   }
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+   size_t len, enum slpc_param_id enable_id,
+   enum slpc_param_id disable_id)
+{
+   struct drm_device *dev = m->private;
+   u64 val;
+   int ret = 0;
+   char buf[10];
+
+   if (len >= sizeof(buf))
+   ret = -EINVAL;
+   else if (copy_from_user(buf, ubuf, len))
+

[Intel-gfx] drm/i915/slpc: Update freq min/max softlimits

2016-08-21 Thread Sagar Arun Kamble 
v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 5ab8362..7062d8b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -293,6 +293,10 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+   struct drm_i915_gem_object *obj;
+   struct page *page;
+   void *pv = NULL;
+   struct slpc_shared_data data;
u64 val;
 
host2guc_slpc_reset(dev_priv);
@@ -336,6 +340,25 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
intel_slpc_set_param(dev_priv,
 
SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 0);
+
+   obj = dev_priv->guc.slpc.vma->obj;
+   intel_slpc_query_task_state(dev_priv);
+
+   pv = kmap_atomic(i915_gem_object_get_page(obj, 0));
+   data = *(struct slpc_shared_data *) pv;
+   kunmap_atomic(pv);
+
+   /*
+* TODO: Define separate variables for slice and unslice
+*   frequencies for driver state variable.
+*/
+   dev_priv->rps.max_freq_softlimit =
+   data.task_state_data.freq_unslice_max;
+   dev_priv->rps.min_freq_softlimit =
+   data.task_state_data.freq_unslice_min;
+
+   dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+   dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Sanitize SLPC version

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Updated with modified sanitize_slpc_option in earlier patch.

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2dfdb24..023064d 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -146,6 +146,8 @@ static void direct_interrupts_to_guc(struct 
drm_i915_private *dev_priv)
 
 static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
 {
+   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
+
/* Handle default case */
if (i915.enable_slpc < 0)
i915.enable_slpc = HAS_SLPC(dev_priv);
@@ -161,6 +163,9 @@ static void sanitize_slpc_option(struct drm_i915_private 
*dev_priv)
/* slpc requires guc submission */
if (!i915.enable_guc_submission)
i915.enable_slpc = 0;
+
+   if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+   i915.enable_slpc = 0;
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Add broxton support

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.

v1: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 -
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e678051..60a5eb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -342,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_ddi = 1,
.has_fpga_dbg = 1,
.has_fbc = 1,
+   .has_slpc = 1,
.has_pooled_eu = 0,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8d737b4..13ffd47 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -164,8 +164,11 @@ static void sanitize_slpc_option(struct drm_i915_private 
*dev_priv)
if (!i915.enable_guc_submission)
i915.enable_slpc = 0;
 
-   if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+   if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
+|| (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+   DRM_INFO("SLPC not supported with current GuC firmware\n");
i915.enable_slpc = 0;
+   }
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC

2016-08-21 Thread Sagar Arun Kamble 
v2: Checkpatch update.

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 71 ++--
 drivers/gpu/drm/i915/intel_guc_loader.c | 12 +++---
 drivers/gpu/drm/i915/intel_slpc.c   | 27 +++-
 drivers/gpu/drm/i915/intel_slpc.h   | 73 ++---
 4 files changed, 110 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index f0474f1..83f26ef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1359,10 +1359,10 @@ static int i915_slpc_info(struct seq_file *m, void 
*unused)
struct page *page;
void *pv = NULL;
struct slpc_shared_data data;
+   struct slpc_task_state_data *task_data;
int i, value;
enum slpc_global_state global_state;
enum slpc_platform_sku platform_sku;
-   enum slpc_host_os host_os;
enum slpc_power_plan power_plan;
enum slpc_power_source power_source;
 
@@ -1379,11 +1379,6 @@ static int i915_slpc_info(struct seq_file *m, void 
*unused)
data = *(struct slpc_shared_data *) pv;
kunmap_atomic(pv);
 
-   seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
-  data.slpc_version >> 16,
-  (data.slpc_version >> 8) & 0xFF,
-  data.slpc_version & 0xFF,
-  data.slpc_version);
seq_printf(m, "shared data size: %d\n", data.shared_data_size);
 
global_state = (enum slpc_global_state) data.global_state;
@@ -1442,20 +1437,6 @@ static int i915_slpc_info(struct seq_file *m, void 
*unused)
seq_printf(m, "slice count: %d\n",
   data.platform_info.slice_count);
 
-   host_os = (enum slpc_host_os) data.platform_info.host_os;
-   seq_printf(m, "host OS: %d (", host_os);
-   switch (host_os) {
-   case SLPC_HOST_OS_UNDEFINED:
-   seq_puts(m, "undefined)\n");
-   break;
-   case SLPC_HOST_OS_WINDOWS_8:
-   seq_puts(m, "Windows 8)\n");
-   break;
-   default:
-   seq_puts(m, "unknown)\n");
-   break;
-   }
-
seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
   data.platform_info.power_plan_source);
power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
@@ -1502,17 +1483,45 @@ static int i915_slpc_info(struct seq_file *m, void 
*unused)
   data.platform_info.P1_freq * 50,
   data.platform_info.Pe_freq * 50,
   data.platform_info.Pn_freq * 50);
-   seq_printf(m, "RAPL package power 
limits:\n\t0x%08x\n\t0x%08x\n",
-  data.platform_info.package_rapl_limit_high,
-  data.platform_info.package_rapl_limit_low);
-   seq_printf(m, "task state data: 0x%08x\n",
-  data.task_state_data);
-   seq_printf(m, "\tturbo active: %d\n",
-  (data.task_state_data & 1));
-   seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: 
%d\n\tdfps target fps: %d\n",
-  (data.task_state_data & 2),
-  (data.task_state_data & 4),
-  (data.task_state_data >> 3) & 0xFF);
+   task_data = _state_data;
+   seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+  task_data->bitfield1, task_data->bitfield2);
+
+   seq_printf(m, "\tgtperf task active: %s\n",
+  yesno(task_data->gtperf_task_active));
+   seq_printf(m, "\tgtperf stall possible: %s\n",
+  yesno(task_data->gtperf_stall_possible));
+   seq_printf(m, "\tgtperf gaming mode: %s\n",
+  yesno(task_data->gtperf_gaming_mode));
+   seq_printf(m, "\tgtperf target fps: %d\n",
+  task_data->gtperf_target_fps);
+
+   seq_printf(m, "\tdcc task active: %s\n",
+  yesno(task_data->dcc_task_active));
+   seq_printf(m, "\tin dcc: %s\n",
+  yesno(task_data->in_dcc));
+   seq_printf(m, "\tin dct: %s\n",
+  yesno(task_data->in_dct));
+   seq_printf(m, "\tfreq switch active: %d\n",
+  task_data->freq_switch_active);
+
+   seq_printf(m, "\tibc enabled: %s\n",
+  yesno(task_data->ibc_enabled));
+   seq_printf(m, "\tibc active: %s\n",
+  yesno(task_data->ibc_active));
+

[Intel-gfx] drm/i915/slpc: Add i915_slpc_info to debugfs

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers and use local variables (Jon Bloomfield)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Moved definition of power plan and power source to earlier
patch in the series.
drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
(Akash)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 184 
 drivers/gpu/drm/i915/intel_slpc.c   |  19 
 drivers/gpu/drm/i915/intel_slpc.h   |   1 +
 3 files changed, 204 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 755941e..1a8e4bb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1350,6 +1350,189 @@ static const struct file_operations i915_slpc_dcc_fops 
= {
.llseek  = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+   struct drm_info_node *node = m->private;
+   struct drm_device *dev = node->minor->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct drm_i915_gem_object *obj;
+   struct page *page;
+   void *pv = NULL;
+   struct slpc_shared_data data;
+   int i, value;
+   enum slpc_global_state global_state;
+   enum slpc_platform_sku platform_sku;
+   enum slpc_host_os host_os;
+   enum slpc_power_plan power_plan;
+   enum slpc_power_source power_source;
+
+   obj = dev_priv->guc.slpc.vma->obj;
+   if (obj) {
+   intel_slpc_query_task_state(dev_priv);
+
+   page = i915_gem_object_get_page(obj, 0);
+   if (page)
+   pv = kmap_atomic(page);
+   }
+
+   if (pv) {
+   data = *(struct slpc_shared_data *) pv;
+   kunmap_atomic(pv);
+
+   seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
+  data.slpc_version >> 16,
+  (data.slpc_version >> 8) & 0xFF,
+  data.slpc_version & 0xFF,
+  data.slpc_version);
+   seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+   global_state = (enum slpc_global_state) data.global_state;
+   seq_printf(m, "global state: %d (", global_state);
+   switch (global_state) {
+   case SLPC_GLOBAL_STATE_NOT_RUNNING:
+   seq_puts(m, "not running)\n");
+   break;
+   case SLPC_GLOBAL_STATE_INITIALIZING:
+   seq_puts(m, "initializing)\n");
+   break;
+   case SLPC_GLOBAL_STATE_RESETTING:
+   seq_puts(m, "resetting)\n");
+   break;
+   case SLPC_GLOBAL_STATE_RUNNING:
+   seq_puts(m, "running)\n");
+   break;
+   case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+   seq_puts(m, "shutting down)\n");
+   break;
+   case SLPC_GLOBAL_STATE_ERROR:
+   seq_puts(m, "error)\n");
+   break;
+   default:
+   seq_puts(m, "unknown)\n");
+   break;
+   }
+
+   platform_sku = (enum slpc_platform_sku)
+   data.platform_info.platform_sku;
+   seq_printf(m, "sku: %d (", platform_sku);
+   switch (platform_sku) {
+   case SLPC_PLATFORM_SKU_UNDEFINED:
+   seq_puts(m, "undefined)\n");
+   break;
+   case SLPC_PLATFORM_SKU_ULX:
+   seq_puts(m, "ULX)\n");
+   break;
+   case SLPC_PLATFORM_SKU_ULT:
+   seq_puts(m, "ULT)\n");
+   break;
+   case SLPC_PLATFORM_SKU_T:
+   seq_puts(m, "T)\n");
+   break;
+   case SLPC_PLATFORM_SKU_MOBL:
+   seq_puts(m, "Mobile)\n");
+   break;
+   case SLPC_PLATFORM_SKU_DT:
+   seq_puts(m, "DT)\n");
+   break;
+   case SLPC_PLATFORM_SKU_UNKNOWN:
+   default:
+   seq_puts(m, "unknown)\n");
+   break;
+   }
+   seq_printf(m, "slice count: %d\n",
+  data.platform_info.slice_count);
+
+   host_os = (enum slpc_host_os)

[Intel-gfx] drm/i915/slpc: Add has_slpc capability flag

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cd102c..d853d7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -652,6 +652,7 @@ struct intel_csr {
func(is_kabylake) sep \
func(is_preliminary) sep \
func(has_fbc) sep \
+   func(has_slpc) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2784,6 +2785,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC(dev)   (IS_GEN9(dev))
 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
+#define HAS_SLPC(dev)  (INTEL_INFO(dev)->has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
INTEL_INFO(dev)->gen >= 8)
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Enable SLPC in guc if supported

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 023064d..8d737b4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -211,6 +211,9 @@ static void set_guc_init_params(struct drm_i915_private 
*dev_priv)
params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
GUC_CTL_VCS2_ENABLED;
 
+   if (intel_slpc_enabled())
+   params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
if (i915.guc_log_level >= 0) {
params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
params[GUC_CTL_DEBUG] =
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Add slpc_status enum values

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

v1: fix whitespace (Sagar)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.h | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h 
b/drivers/gpu/drm/i915/intel_slpc.h
index 031e36b..9fe9ae3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,33 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_status {
+   SLPC_STATUS_OK = 0,
+   SLPC_STATUS_ERROR = 1,
+   SLPC_STATUS_ILLEGAL_COMMAND = 2,
+   SLPC_STATUS_INVALID_ARGS = 3,
+   SLPC_STATUS_INVALID_PARAMS = 4,
+   SLPC_STATUS_INVALID_DATA = 5,
+   SLPC_STATUS_OUT_OF_RANGE = 6,
+   SLPC_STATUS_NOT_SUPPORTED = 7,
+   SLPC_STATUS_NOT_IMPLEMENTED = 8,
+   SLPC_STATUS_NO_DATA = 9,
+   SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+   SLPC_STATUS_REGISTER_LOCKED = 11,
+   SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+   SLPC_STATUS_VALUE_ALREADY_SET = 13,
+   SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+   SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+   SLPC_STATUS_MISMATCHING_VERSION = 16,
+   SLPC_STATUS_MEMIO_ERROR = 17,
+   SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
+   SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
+   SLPC_STATUS_NO_EVENT_QUEUED = 20,
+   SLPC_STATUS_OUT_OF_SPACE = 21,
+   SLPC_STATUS_TIMEOUT = 22,
+   SLPC_STATUS_NO_LOCK = 23,
+};
+
 enum slpc_event_id {
SLPC_EVENT_RESET = 0,
SLPC_EVENT_SHUTDOWN = 1,
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Expose guc functions for use with SLPC

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

v1: Updated function names as they need to be made extern. (ChrisW)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 16 
 drivers/gpu/drm/i915/intel_guc.h   |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e436941..9a69bf1 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -47,7 +47,7 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
  *
  * Doorbells:
  * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct 
drm_i915_private *dev_priv,
return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 status;
@@ -141,7 +141,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
data[1] = client->ctx_index;
 
-   return host2guc_action(guc, data, 2);
+   return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -152,7 +152,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
data[1] = client->ctx_index;
 
-   return host2guc_action(guc, data, 2);
+   return i915_guc_action(guc, data, 2);
 }
 
 static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -169,7 +169,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
/* bit 0 and 1 are for Render and Media domain separately */
data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-   return host2guc_action(guc, data, ARRAY_SIZE(data));
+   return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 /*
@@ -621,7 +621,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return: A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct drm_i915_gem_object *obj;
@@ -1067,7 +1067,7 @@ int intel_guc_suspend(struct drm_device *dev)
/* first page is shared data with GuC */
data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-   return host2guc_action(guc, data, ARRAY_SIZE(data));
+   return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 
@@ -1092,5 +1092,5 @@ int intel_guc_resume(struct drm_device *dev)
/* first page is shared data with GuC */
data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
 
-   return host2guc_action(guc, data, ARRAY_SIZE(data));
+   return i915_guc_action(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c973262..9e6b948 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
 
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: If using SLPC, do not set frequency

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 21dafe0..14c29b1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4965,6 +4965,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+   if (intel_slpc_active(dev_priv))
+   return;
+
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
valleyview_set_rps(dev_priv, val);
else
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall

2016-08-21 Thread Sagar Arun Kamble 
v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/intel_slpc.c   | 30 ++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 +
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a8e4bb..f0474f1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1140,7 +1140,7 @@ static int slpc_enable_disable_get(struct drm_device 
*dev, u64 *val,
return ret;
 }
 
-static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
   enum slpc_param_id enable_id,
   enum slpc_param_id disable_id)
 {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 06e4a95..6883f44 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -299,8 +299,38 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
+   u64 val;
+
host2guc_slpc_reset(dev_priv);
dev_priv->guc.slpc.enabled = true;
+
+   /* Enable only GTPERF task, Disable others */
+   val = SLPC_PARAM_TASK_ENABLED;
+   slpc_enable_disable_set(_priv->drm, val,
+   SLPC_PARAM_TASK_ENABLE_GTPERF,
+   SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+   val = SLPC_PARAM_TASK_DISABLED;
+   slpc_enable_disable_set(_priv->drm, val,
+   SLPC_PARAM_TASK_ENABLE_BALANCER,
+   SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+   slpc_enable_disable_set(_priv->drm, val,
+   SLPC_PARAM_TASK_ENABLE_DCC,
+   SLPC_PARAM_TASK_DISABLE_DCC);
+
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
+1);
+
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+0);
+
+   intel_slpc_set_param(dev_priv,
+SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
+1);
+
 }
 
 void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h 
b/drivers/gpu/drm/i915/intel_slpc.h
index e236d9d..a2161b0b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -184,4 +184,9 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
  enum slpc_param_id id,
  int *overriding, u32 *value);
 void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
+
+/* i915_debugfs.c */
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+   enum slpc_param_id enable_id,
+   enum slpc_param_id disable_id);
 #endif
-- 
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[Intel-gfx] drm/i915/slpc: Add/Update interface for requested frequency

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLPC requested value needs to be made available to i915 without
reading RPNSWREQ.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
Avoid magic numbers (Nick)
Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
don't update cur_freq as it is driver internal request. (Chris)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  6 ++
 drivers/gpu/drm/i915/i915_sysfs.c   | 33 +
 2 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index a95d7bc..2ae1fff 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1110,6 +1110,9 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
 
intel_runtime_pm_get(dev_priv);
 
+   if (intel_slpc_active(dev_priv))
+   seq_puts(m, "SLPC Active\n");
+
if (IS_GEN5(dev)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2372,6 +2375,9 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_file *file;
 
+   if (intel_slpc_active(dev_priv))
+   return -ENODEV;
+
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
seq_printf(m, "GPU busy? %s [%x]\n",
   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index f1ffde7..5547f41 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -302,11 +302,42 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
struct drm_device *dev = minor->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
 
+   if (intel_slpc_active(dev_priv))
+   return -ENODEV;
+
return snprintf(buf, PAGE_SIZE, "%d\n",
intel_gpu_freq(dev_priv,
   dev_priv->rps.cur_freq));
 }
 
+static ssize_t gt_req_freq_mhz_show(struct device *kdev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_minor *minor = dev_to_drm_minor(kdev);
+   struct drm_device *dev = minor->dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
+   u32 reqf;
+
+   if (!intel_runtime_pm_get_if_in_use(dev_priv))
+   return -ENODEV;
+
+   reqf = I915_READ(GEN6_RPNSWREQ);
+   intel_runtime_pm_put(dev_priv);
+
+   if (IS_GEN9(dev))
+   reqf >>= 23;
+   else {
+   reqf &= ~GEN6_TURBO_DISABLE;
+   if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+   reqf >>= 24;
+   else
+   reqf >>= 25;
+   }
+   reqf = intel_gpu_freq(dev_priv, reqf);
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", reqf);
+}
+
 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct 
device_attribute *attr, char *buf)
 {
struct drm_minor *minor = dev_to_drm_minor(kdev);
@@ -476,6 +507,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
+static DEVICE_ATTR(gt_req_freq_mhz, S_IRUGO, gt_req_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, 
gt_boost_freq_mhz_store);
 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, 
gt_max_freq_mhz_store);
 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, 
gt_min_freq_mhz_store);
@@ -510,6 +542,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct 
device_attribute *attr
 static const struct attribute *gen6_attrs[] = {
_attr_gt_act_freq_mhz.attr,
_attr_gt_cur_freq_mhz.attr,
+   _attr_gt_req_freq_mhz.attr,
_attr_gt_boost_freq_mhz.attr,
_attr_gt_max_freq_mhz.attr,
_attr_gt_min_freq_mhz.attr,
-- 
1.9.1

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[Intel-gfx] drm/i915/slpc: Add enable_slpc module parameter

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
Remove sanitize enable_slpc call before firmware version check
is performed. (ChrisW)
Version check is added in next patch and that will be done as
part of slpc_enable_sanitize function in the next patch. (Sagar)
Updated slpc option sanitize function call for platforms without
GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
Code indentation based on checkpatch.

Suggested-by: Paulo Zanoni 
Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_params.c  |  6 ++
 drivers/gpu/drm/i915/i915_params.h  |  1 +
 drivers/gpu/drm/i915/intel_guc.h|  6 ++
 drivers/gpu/drm/i915/intel_guc_loader.c | 30 ++
 4 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
+   .enable_slpc = 0,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
"Override execlists usage. "
"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+   "Override single-loop-power-controller (slpc) usage. "
+   "(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 "(0=disabled, 1=enabled - link mode chosen per-platform, 
2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
int enable_fbc;
int enable_ppgtt;
int enable_execlists;
+   int enable_slpc;
int enable_psr;
unsigned int preliminary_hw_support;
int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..bf7624f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
uint32_t last_seqno[I915_NUM_ENGINES];
 };
 
+static inline int intel_slpc_enabled(void)
+{
+   WARN_ON(i915.enable_slpc < 0);
+   return i915.enable_slpc;
+}
+
 /* intel_guc_loader.c */
 extern void intel_guc_init(struct drm_device *dev);
 extern int intel_guc_setup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 324812d..2dfdb24 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct 
drm_i915_private *dev_priv)
}
 }
 
+static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+   /* Handle default case */
+   if (i915.enable_slpc < 0)
+   i915.enable_slpc = HAS_SLPC(dev_priv);
+
+   /* slpc requires hardware support and compatible firmware */
+   if (!HAS_SLPC(dev_priv))
+   i915.enable_slpc = 0;
+
+   /* slpc requires guc loaded */
+   if (!i915.enable_guc_loading)
+   i915.enable_slpc = 0;
+
+   /* slpc requires guc submission */
+   if (!i915.enable_guc_submission)
+   i915.enable_slpc = 0;
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -728,18 +747,21 @@ void intel_guc_init(struct drm_device *dev)
guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 
-   /* Early (and silent) return if GuC loading is disabled */
+   /* Return if GuC loading is disabled sanitizing SLPC option */
if (!i915.enable_guc_loading)
-   return;
+   goto

[Intel-gfx] drm/i915/slpc: Add parameter unset/set/get functions

2016-08-21 Thread Sagar Arun Kamble 
From: Tom O'Rourke 

Add slpc_param_id enum values.
Add events for setting/unsetting parameters.

v1: Use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)

v2: Checkpatch update.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c | 102 ++
 drivers/gpu/drm/i915/intel_slpc.h |  29 ++-
 2 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 637eacb..db912bc 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,108 @@ static void host2guc_slpc_shutdown(struct drm_i915_private 
*dev_priv)
host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+   enum slpc_param_id id, u32 value)
+{
+   u32 data[4];
+
+   data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+   data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+   data[2] = (u32) id;
+   data[3] = value;
+
+   host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id)
+{
+   u32 data[3];
+
+   data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+   data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+   data[2] = (u32) id;
+
+   host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+   enum slpc_param_id id)
+{
+   struct drm_i915_gem_object *obj;
+   struct page *page;
+   struct slpc_shared_data *data = NULL;
+
+   obj = dev_priv->guc.slpc.vma->obj;
+   if (obj) {
+   page = i915_gem_object_get_page(obj, 0);
+   if (page)
+   data = kmap_atomic(page);
+   }
+
+   if (data) {
+   data->override_parameters_set_bits[id >> 5]
+   &= (~(1 << (id % 32)));
+   data->override_parameters_values[id] = 0;
+   kunmap_atomic(data);
+
+   host2guc_slpc_unset_param(dev_priv, id);
+   }
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ u32 value)
+{
+   struct drm_i915_gem_object *obj;
+   struct page *page;
+   struct slpc_shared_data *data = NULL;
+
+   obj = dev_priv->guc.slpc.vma->obj;
+   if (obj) {
+   page = i915_gem_object_get_page(obj, 0);
+   if (page)
+   data = kmap_atomic(page);
+   }
+
+   if (data) {
+   data->override_parameters_set_bits[id >> 5]
+   |= (1 << (id % 32));
+   data->override_parameters_values[id] = value;
+   kunmap_atomic(data);
+
+   host2guc_slpc_set_param(dev_priv, id, value);
+   }
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ int *overriding, u32 *value)
+{
+   struct drm_i915_gem_object *obj;
+   struct page *page;
+   struct slpc_shared_data *data = NULL;
+   u32 bits;
+
+   obj = dev_priv->guc.slpc.vma->obj;
+   if (obj) {
+   page = i915_gem_object_get_page(obj, 0);
+   if (page)
+   data = kmap_atomic(page);
+   }
+
+   if (data) {
+   if (overriding) {
+   bits = data->override_parameters_set_bits[id >> 5];
+   *overriding = (0 != (bits & (1 << (id % 32;
+   }
+   if (value)
+   *value = data->override_parameters_values[id];
+
+   kunmap_atomic(data);
+   }
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h 
b/drivers/gpu/drm/i915/intel_slpc.h
index 9fe9ae3..018f772 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -69,6 +69,26 @@ enum slpc_event_id {
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 #define SLPC_EVENT_STATUS_MASK 0xFF
 
+enum slpc_param_id {
+   SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+   SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+   SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+   SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+   SLPC_PARAM_TASK_ENABLE_DCC = 4,
+   SLPC_PARAM_TASK_DISABLE_DCC = 5,
+   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+   SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+   SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+

[Intel-gfx] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

2016-08-21 Thread Sagar Arun Kamble 
With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0c739c6..2a3381c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4982,7 +4982,13 @@ static void gen9_disable_rc6(struct drm_i915_private 
*dev_priv)
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE(GEN6_RP_CONTROL, 0);
+   uint32_t rp_ctl = 0;
+
+   /* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
+   if (i915.enable_slpc)
+   rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
+
+   I915_WRITE(GEN6_RP_CONTROL, rp_ctl);
 
dev_priv->rps.enabled = false;
 }
-- 
1.9.1

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[Intel-gfx] Add support for GuC-based SLPC

2016-08-21 Thread Sagar Arun Kamble 
SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features.  The SLPC
implementation runs in firmware on GuC.

This series has been tested with SKL GuC firmware
version 9.18 which is yet to be released. Performance and
power testing with these patches and 9.18 firmware is at
parity and in some cases better than host solution today
on various Linux benchmarks.

The graphics power management features in SLPC in this
version are called GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate.  Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios.  BALANCER is only
active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.

The last series can be found in the archive at
"[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/094445.html

This series incorporates feedback from code reviews on earlier series.
It drops the display mode notification patches as it is not needed for
Turbo part of GTPERF. This series also adds new interface changes for
SLPC support on 9.18 GuC Firmware which is not yet published.
Will like to get review started prior to firmware is published.

With SLPC disabled by default, this series should be 
safe to merge now and it can be enabled when 9.18 firmware is released. 

v2: Addressed review comments on v1. Removed patch to enable SLPC by default.

VIZ-6773, VIZ-6889

Cc: Chris Wilson 
Cc: Daniel Vetter 
Cc: Beuchat, Marc 
Cc: Jeff McGee 


Sagar Arun Kamble (7):
  drm/i915: Remove RPM suspend dependency on rps.enabled and related
changes
  drm/i915: Check GuC load status for Host to GuC action and SLPC status
  drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
  drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS
Stall
  drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
  drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC
  drm/i915/slpc: Update freq min/max softlimits

Tom O'Rourke (18):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize SLPC version
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Add/Update interface for requested frequency
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add broxton support

 drivers/gpu/drm/i915/Makefile  |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c| 469 +
 drivers/gpu/drm/i915/i915_drv.c|  21 +-
 drivers/gpu/drm/i915/i915_drv.h|   2 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  20 +-
 drivers/gpu/drm/i915/i915_params.c |   6 +
 drivers/gpu/drm/i915/i915_params.h |   1 +
 drivers/gpu/drm/i915/i915_pci.c|   3 +
 drivers/gpu/drm/i915/i915_sysfs.c  |  51 
 drivers/gpu/drm/i915/intel_drv.h   |  13 +
 drivers/gpu/drm/i915/intel_guc.h   |  11 +
 drivers/gpu/drm/i915/intel_guc_loader.c|  49 ++-
 drivers/gpu/drm/i915/intel_pm.c| 131 +---
 drivers/gpu/drm/i915/intel_runtime_pm.c|   2 +-
 drivers/gpu/drm/i915/intel_slpc.c  | 368 ++
 drivers/gpu/drm/i915/intel_slpc.h  | 215 +
 16 files changed, 1310 insertions(+), 55 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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[Intel-gfx] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

2016-08-21 Thread Sagar Arun Kamble 
For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM
Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other
GENs this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.

v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
spacing changes. (David)
and commit message update for checkpatch issues.

Reviewed-by: David Weinehall 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c | 14 +++---
 drivers/gpu/drm/i915/intel_pm.c | 20 ++--
 drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 13ae340..d5d0a50 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2284,10 +2284,18 @@ static int intel_runtime_suspend(struct device *device)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
 
-   if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(
+   if (WARN_ON_ONCE(!intel_enable_rc6()))
return -ENODEV;
 
-   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+   /*
+* Once RC6 and RPS enabling is separated for non-GEN9 platforms
+* below check should be removed.
+   */
+   if (!IS_GEN9(dev_priv))
+   if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+   return -ENODEV;
+
+   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
 
DRM_DEBUG_KMS("Suspending device\n");
@@ -2391,7 +2399,7 @@ static int intel_runtime_resume(struct device *device)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret = 0;
 
-   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
 
DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a6751e..5a73672 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4979,6 +4979,8 @@ static void gen9_disable_rc6(struct drm_i915_private 
*dev_priv)
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+   dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -4986,11 +4988,15 @@ static void gen6_disable_rps(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+   dev_priv->rps.enabled = false;
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
I915_WRITE(GEN6_RC_CONTROL, 0);
+
+   dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5002,6 +5008,8 @@ static void valleyview_disable_rps(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+   dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5219,6 +5227,8 @@ static void gen9_enable_rps(struct drm_i915_private 
*dev_priv)
reset_rps(dev_priv, gen6_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+   dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5362,6 +5372,8 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
reset_rps(dev_priv, gen6_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+   dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5458,6 +5470,8 @@ static void gen6_enable_rps(struct drm_i915_private 
*dev_priv)
}
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+   dev_priv->rps.enabled = true;
 }
 
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -5932,6 +5946,8 @@ static void cherryview_enable_rps(struct drm_i915_private 
*dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+   dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6012,6 +6028,8 @@ static void valleyview_enable_rps(struct drm_i915_private 
*dev_priv)
reset_rps(dev_priv, valleyview_set_rps);

Re: [Intel-gfx] Add support for GuC-based SLPC

2016-08-21 Thread Kamble, Sagar A 



On 8/20/2016 1:46 PM, Chris Wilson wrote:

On Sat, Aug 20, 2016 at 10:38:59AM +0530, Sagar Arun Kamble wrote:

This series has been tested with SKL GuC firmware
version 9.18 which is yet to be released. Performance and
power testing with these patches and 9.18 firmware is at
parity and in some cases better than host solution today
on various Linux benchmarks.

Patches pending to support your claims?
-Chris
Only pending GuC firmware 9.18 integration. All kernel side changes for 
SLPC are part of the series.
I added patch to enable SLPC by default in this series, will remove in 
the next series and can add it

once 9.18 firmware gets integrated.




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Re: [Intel-gfx] drm/i915/slpc: Update current requested frequency

2016-08-21 Thread Kamble, Sagar A 



On 8/20/2016 1:45 PM, Chris Wilson wrote:

On Sat, Aug 20, 2016 at 10:39:10AM +0530, Sagar Arun Kamble wrote:

From: Tom O'Rourke 

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Before using rps.cur_freq in sysfs or debugfs, read
requested frequency from register to get the value
most recently requested by SLPC firmware.

v2: replace HAS_SLPC with intel_slpc_active (Paulo)
v3: Avoid magic numbers (Nick)
 Use a function for repeated code (Jon)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
  drivers/gpu/drm/i915/i915_drv.h | 5 +
  drivers/gpu/drm/i915/i915_reg.h | 1 +
  drivers/gpu/drm/i915/i915_sysfs.c   | 8 
  4 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 01ae5ee..a99a3f6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1110,6 +1110,9 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
  
  	intel_runtime_pm_get(dev_priv);
  
+	if (intel_slpc_active(dev_priv))

+   dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);

Do not alter cur_freq here, as we print out RPNSWEQ and updating
cur_freq defeats the purpose of showing the internal value vs the hw
value.

Instead add "SLPC active" to the output.

Fixed in the next series.



+
if (IS_GEN5(dev)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2372,6 +2375,9 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_file *file;

if (intel_slpc_active(dev_priv))
return -ENODEV;

Fixed in the next series.
  
+	if (intel_slpc_active(dev_priv))

+   dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
seq_printf(m, "GPU busy? %s [%x]\n",
   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 764fad0..fcd2e98 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3913,4 +3913,9 @@ bool i915_memcpy_from_wc(void *dst, const void *src, 
unsigned long len);
__T;\
  })
  
+static inline u8 gen9_read_requested_freq(struct drm_i915_private *dev_priv)

+{
+   return (u8) GEN9_GET_FREQUENCY(I915_READ(GEN6_RPNSWREQ));
+}

Removed in the next series.

Move to sysfs and look carefully at what you wrote.


  #endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4adf28..1654245 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6997,6 +6997,7 @@ enum {
  #define   GEN6_FREQUENCY(x)   ((x)<<25)
  #define   HSW_FREQUENCY(x)((x)<<24)
  #define   GEN9_FREQUENCY(x)   ((x)<<23)
+#define   GEN9_GET_FREQUENCY(x)((x)>>23)
  #define   GEN6_OFFSET(x)  ((x)<<19)
  #define   GEN6_AGGRESSIVE_TURBO   (0<<15)
  #define GEN6_RC_VIDEO_FREQ_MMIO(0xA00C)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index f1ffde7..8404816 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -302,6 +302,14 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
struct drm_device *dev = minor->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
  
+	if (intel_slpc_active(dev_priv)) {

+   intel_runtime_pm_get(dev_priv);

Use get_if_in_use and just show a stale value when the hw is asleep
would be my preference. cur_freq is just our request, act_freq is the
actual hw value.
With cur_freq not making sense currently with SLPC, I am removing this 
altogether and adding new sysfs interface

for knowing HW requested frequency which will be ideally SLPC requested.



+   mutex_lock(_priv->rps.hw_lock);

Useless mutex.


+   dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+   mutex_unlock(_priv->rps.hw_lock);
+   intel_runtime_pm_put(dev_priv);
+   }
+
return snprintf(buf, PAGE_SIZE, "%d\n",
intel_gpu_freq(dev_priv,
   dev_priv->rps.cur_freq));
--
1.9.1

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Re: [Intel-gfx] drm/i915/slpc: Update freq min/max softlimits

2016-08-21 Thread Kamble, Sagar A 



On 8/20/2016 1:32 PM, Chris Wilson wrote:

On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote:

+   obj = dev_priv->guc.slpc.vma->obj;
+   if (obj) {

OOPS.

Fixed in next series.



+   intel_slpc_query_task_state(dev_priv);
+
+   page = i915_gem_object_get_page(obj, 0);
+   if (page)
+   pv = kmap_atomic(page);
+   }
+
+   if (pv) {
+   data = *(struct slpc_shared_data *) pv;
+   kunmap_atomic(pv);

Can kmap_atomic return zero?

Fixed in next series.



+
+   /*
+* TODO: Define separate variables for slice and unslice
+*   frequencies for driver state variable.
+*/
+   dev_priv->rps.max_freq_softlimit =
+   data.task_state_data.freq_unslice_max;
+   dev_priv->rps.min_freq_softlimit =
+   data.task_state_data.freq_unslice_min;

These are user values, you do not get to arbitrarily rewrite them.

You control dev_priv->rps.[min|max]_freq.
With SLPC, GuC firmware SLPC S/W requested frequency be operated in the 
softlimits analogous to
Host softlimits. Limits might be different with SLPC and can be 
controlled through regular interfaces.

dev_priv->rps.[min|max]_freq are HW Min/Max.

-Chris



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Re: [Intel-gfx] drm/i915: Check GuC load status for Host to GuC action and SLPC status

2016-08-21 Thread Kamble, Sagar A 

Thanks for the review Deepak.

Have incorporated the changes and will send in next series.


On 8/20/2016 10:40 AM, Deepak S wrote:



On 20/08/16 10:39 AM, Sagar Arun Kamble wrote:

Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.

Signed-off-by: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/i915_guc_submission.c | 5 +
  drivers/gpu/drm/i915/intel_drv.h   | 4 
  2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c

index 680d9b4..27c937b 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -78,6 +78,8 @@ static inline bool host2guc_action_response(struct 
drm_i915_private *dev_priv,

  int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
  {
  struct drm_i915_private *dev_priv = guc_to_i915(guc);
+struct intel_guc_fw *guc_fw = >guc_fw;
+

remove the blank line

  u32 status;
  int i;
  int ret;
@@ -85,6 +87,9 @@ int i915_guc_action(struct intel_guc *guc, u32 
*data, u32 len)

  if (WARN_ON(len < 1 || len > 15))
  return -EINVAL;
  +if (WARN_ON(guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS))
+return -ENODEV;
+
  intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
dev_priv->guc.action_count += 1;
diff --git a/drivers/gpu/drm/i915/intel_drv.h 
b/drivers/gpu/drm/i915/intel_drv.h

index c46d619..71936dc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1694,8 +1694,12 @@ bool chv_phy_powergate_ch(struct 
drm_i915_private *dev_priv, enum dpio_phy phy,
static inline int intel_slpc_active(struct drm_i915_private 
*dev_priv)

  {
+struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
  int ret = 0;
  +if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+return 0;
+

Since we are initializing ret=0, I think can do "return ret" right?

  if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
  ret = 1;


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Re: [Intel-gfx] drm/i915/slpc: Use intel_slpc_* functions if supported

2016-08-21 Thread Kamble, Sagar A 

Thanks for the review David.

Have incorporated the changes and will send in next series.


On 8/20/2016 1:57 PM, David Weinehall wrote:

On Sat, Aug 20, 2016 at 10:39:06AM +0530, Sagar Arun Kamble wrote:

From: Tom O'Rourke 

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v2: return void instead of ignored error code (Paulo)
 enable/disable RC6 in SLPC flows (Sagar)
 replace HAS_SLPC() use with intel_slpc_enabled()
or intel_slpc_active() (Paulo)
v3: Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
 "drm/i915/bxt: Explicitly clear the Turbo control register"

v4?


v5: Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
 Performance drop with SLPC was happening as ring frequency table
 was not programmed when SLPC was enabled. This patch programs ring
 frequency table with SLPC. Initial reset of SLPC is based on kernel
 parameter as planning to add slpc state in intel_slpc_active. Cleanup
 is also based on kernel parameter as SLPC gets disabled in
 disable/suspend.(Sagar)

v6: Rebase.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/Makefile |  3 +-
  drivers/gpu/drm/i915/intel_drv.h  |  4 ++
  drivers/gpu/drm/i915/intel_guc.h  |  1 +
  drivers/gpu/drm/i915/intel_pm.c   | 98 ++-
  drivers/gpu/drm/i915/intel_slpc.c | 56 ++
  drivers/gpu/drm/i915/intel_slpc.h | 35 ++
  6 files changed, 165 insertions(+), 32 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
  create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3412413..b768c66 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -51,7 +51,8 @@ i915-y += i915_cmd_parser.o \
  
  # general-purpose microcontroller (GuC) support

  i915-y += intel_guc_loader.o \
- i915_guc_submission.o
+ i915_guc_submission.o \
+ intel_slpc.o
  
  # autogenerated null render state

  i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1c700b0..16fe13d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1692,6 +1692,10 @@ void chv_phy_powergate_lanes(struct intel_encoder 
*encoder,
  bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy 
phy,
  enum dpio_channel ch, bool override);
  
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)

+{
+   return 0;
+}
  
  /* intel_pm.c */

  void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 27a7459..cd23c4e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
  #include "intel_guc_fwif.h"
  #include "i915_guc_reg.h"
  #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
  
  struct drm_i915_gem_request;
  
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c

index 954e332..7156fb5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4893,7 +4893,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 * our rpm wakeref. And then disable the interrupts to stop any
 * futher RPS reclocking whilst we are asleep.
 */
-   gen6_disable_rps_interrupts(dev_priv);
+   if (!intel_slpc_active(dev_priv))
+   gen6_disable_rps_interrupts(dev_priv);
  
  	mutex_lock(_priv->rps.hw_lock);

if (dev_priv->rps.enabled) {
@@ -6544,6 +6545,9 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
/* Finally allow us to boost to max by default */
dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
  
+	if (intel_slpc_enabled())

+   intel_slpc_init(dev_priv);
+
mutex_unlock(_priv->rps.hw_lock);
mutex_unlock(_priv->drm.struct_mutex);
  
@@ -6552,7 +6556,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
  
  void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)

  {
-   if (IS_VALLEYVIEW(dev_priv))
+   if (intel_slpc_enabled())
+   intel_slpc_cleanup(dev_priv);
+   else if (IS_VALLEYVIEW(dev_priv))
valleyview_cleanup_gt_powersave(dev_priv);
  
  	if (!i915.enable_rc6)

@@ -6572,28 +6578,42 @@ void intel_suspend_gt_powersave(struct drm_i915_private 
*dev_priv)
if (INTEL_GEN(dev_priv) < 6)
return;
  
-	if (cancel_delayed_work_sync(_priv->rps.autoenable_work))

+   if (cancel_delayed_work_sync(_priv->rps.autoenable_work)) {
+   if (intel_slpc_active(dev_priv))
+