[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/1] drm/i915: Do RPM Wake during GuC/HuC status read
== Series Details == Series: series starting with [1/1] drm/i915: Do RPM Wake during GuC/HuC status read URL : https://patchwork.freedesktop.org/series/19034/ State : failure == Summary == Series 19034v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/19034/revisions/1/mbox/ Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (fi-skl-6770hq) fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:233 dwarn:0 dfail:0 fail:1 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest d0d917c drm/i915: Do RPM Wake during GuC/HuC status read == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3686/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Do RPM Wake during GuC/HuC status read
On Fri, Feb 03, 2017 at 01:00:18PM +0530, Sagar Arun Kamble wrote: > HUC_STATUS, GUC_STATUS, SOFT_SCRATCH registers are read in debugfs. > This patch covers those accesses by RPM get/put. See also I915_PARAM_HUC_STATUS. > Cc: Arkadiusz Hiler > Cc: Anusha Srivatsa > Signed-off-by: Sagar Arun Kamble Testcase? There's definitely at least one that should be covering this. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Dynamically alloc GuC descriptor
On Thu, Feb 02, 2017 at 07:27:45AM -0800, Oscar Mateo wrote: > From: Michal Wajdeczko > > The GuC descriptor is big in size. If we use local definition of > guc_desc we have a chance to overflow stack. Use allocated one. > > v2: Rebased > v3: Split > v4: Handle ENOMEM, cover all uses of guc_context_desc, use kzalloc (Oscar) > > Signed-off-by: Deepak S > Signed-off-by: Michal Wajdeczko > Signed-off-by: Oscar Mateo > --- > drivers/gpu/drm/i915/i915_guc_submission.c | 94 > ++ > 1 file changed, 57 insertions(+), 37 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c > b/drivers/gpu/drm/i915/i915_guc_submission.c > index 8ced9e2..b4f14f3 100644 > --- a/drivers/gpu/drm/i915/i915_guc_submission.c > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > @@ -102,9 +102,13 @@ static int guc_update_doorbell_id(struct intel_guc *guc, > struct sg_table *sg = guc->ctx_pool_vma->pages; > void *doorbell_bitmap = guc->doorbell_bitmap; > struct guc_doorbell_info *doorbell; > - struct guc_context_desc desc; > + struct guc_context_desc *desc; > size_t len; > > + desc = kzalloc(sizeof(*desc), GFP_KERNEL); > + if (!desc) > + return -ENOMEM; > + > doorbell = client->vaddr + client->doorbell_offset; > > if (client->doorbell_id != GUC_INVALID_DOORBELL_ID && > @@ -116,15 +120,22 @@ static int guc_update_doorbell_id(struct intel_guc *guc, > } > > /* Update the GuC's idea of the doorbell ID */ > - len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), > - sizeof(desc) * client->ctx_index); > - if (len != sizeof(desc)) > + len = sg_pcopy_to_buffer(sg->sgl, sg->nents, desc, sizeof(*desc), > + sizeof(*desc) * client->ctx_index); This is silly. You are creating a pointer using kmalloc to copy into a pointer created using alloc_page. Just write directly into the backing store. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915: Do RPM Wake during GuC/HuC status read
HUC_STATUS, GUC_STATUS, SOFT_SCRATCH registers are read in debugfs. This patch covers those accesses by RPM get/put. Cc: Arkadiusz Hiler Cc: Anusha Srivatsa Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3ae0656..639ed12 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2374,7 +2374,9 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) seq_printf(m, "\tRSA: offset is %d; size = %d\n", huc_fw->rsa_offset, huc_fw->rsa_size); + intel_runtime_pm_get(dev_priv); seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); + intel_runtime_pm_put(dev_priv); return 0; } @@ -2406,6 +2408,8 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) seq_printf(m, "\tRSA: offset is %d; size = %d\n", guc_fw->rsa_offset, guc_fw->rsa_size); + intel_runtime_pm_get(dev_priv); + tmp = I915_READ(GUC_STATUS); seq_printf(m, "\nGuC status 0x%08x:\n", tmp); @@ -2419,6 +2423,8 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) for (i = 0; i < 16; i++) seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); + intel_runtime_pm_put(dev_priv); + return 0; } -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/bxt: Add MST support when do DPLL calculation (rev3)
== Series Details == Series: drm/i915/bxt: Add MST support when do DPLL calculation (rev3) URL : https://patchwork.freedesktop.org/series/17815/ State : failure == Summary == Series 17815v3 drm/i915/bxt: Add MST support when do DPLL calculation https://patchwork.freedesktop.org/api/1.0/series/17815/revisions/3/mbox/ Test kms_setmode: Subgroup basic-clone-single-crtc: pass -> INCOMPLETE (fi-skl-6700k) fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:207 pass:188 dwarn:0 dfail:0 fail:0 skip:18 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest aeeab6a drm/i915/bxt: Add MST support when do DPLL calculation == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3685/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/bxt: Add MST support when do DPLL calculation
From: "Lee, Shawn C"
Add the missing INTEL_OUTPUT_DP_MST case in bxt_get_dpll()
to correctly initialize the crtc_state and port plls when
link training a DP MST monitor on BXT/APL devices.
Fixes: a277ca7dc01d ("drm/i915: Split bxt_ddi_pll_select()")
Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=99572
Reviewed-by: Cooper Chiou
Reviewed-by: Gary C Wang
Reviewed-by: Ciobanu, Nathan D
Reviewed-by: Herbert, Marc
Reviewed-by: Bride, Jim
Reviewed-by: Navare, Manasi D
Cc: Jani Nikula
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_dpll_mgr.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index c92a2558beb4..1a1d99d266ed 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1855,7 +1855,8 @@ bool bxt_ddi_dp_set_dpll_hw_state(int clock,
return NULL;
if ((encoder->type == INTEL_OUTPUT_DP ||
-encoder->type == INTEL_OUTPUT_EDP) &&
+encoder->type == INTEL_OUTPUT_EDP ||
+encoder->type == INTEL_OUTPUT_DP_MST ) &&
!bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
return NULL;
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 4/6] drm: scrambling support in drm layer
Regards
Shashank
On 2/2/2017 11:43 PM, Thierry Reding wrote:
On Thu, Feb 02, 2017 at 11:08:22AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 2/1/2017 10:02 PM, Thierry Reding wrote:
On Wed, Feb 01, 2017 at 06:14:39PM +0530, Shashank Sharma wrote:
HDMI 2.0 spec mandates scrambling for modes with pixel clock higher
than 340Mhz. This patch adds few new functions in drm layer for
core drivers to enable/disable scrambling.
This patch adds:
- A function to detect scrambling support parsing HF-VSDB
- A function to check scrambling status runtime using SCDC read.
- Two functions to enable/disable scrambling using SCDC read/write.
- Few new bools to reflect scrambling support and status.
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/drm_edid.c | 131
+++-
include/drm/drm_connector.h | 24
include/drm/drm_edid.h | 6 +-
3 files changed, 159 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 37902e5..f0d940a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -37,6 +37,7 @@
#include
#include
#include
+#include
#define version_greater(edid, maj, min) \
(((edid)->version > (maj)) || \
@@ -3814,6 +3815,132 @@ static void drm_detect_hdmi_scdc(struct drm_connector
*connector,
}
}
+static void drm_detect_hdmi_scrambling(struct drm_connector *connector,
+const u8 *hf_vsdb)
+{
+ struct drm_display_info *display = &connector->display_info;
+ struct drm_hdmi_info *hdmi = &display->hdmi_info;
+
+ /*
+* All HDMI 2.0 monitors must support scrambling at rates > 340M.
In comments below you use Mhz as the abbreviations. This should be
consistent. Also I think "MHz" is actually the correct spelling.
Agree.
+* And as per the spec, three factors confirm this:
+* * Availability of a HF-VSDB block in EDID (check)
+* * Non zero Max_TMDS_Char_Rate filed in HF-VSDB
+* * SCDC support available
+* Lets check it out.
+*/
+
+ if (hf_vsdb[5]) {
+ display->max_tmds_clock = hf_vsdb[5] * 5000;
+ DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
+ display->max_tmds_clock);
+
+ if (hdmi->scdc_supported) {
+ hdmi->scr_info.supported = true;
+
+ /* Few sinks support scrambling for cloks < 340M */
+ if ((hf_vsdb[6] & 0x8))
+ hdmi->scr_info.low_clocks = true;
+ }
+ }
+}
+
+/**
+ * drm_check_scrambling_status - what is status of scrambling?
+ * @adapter: i2c adapter for SCDC channel
"I2C", same in other parts of this patch.
Got it.
+ *
+ * Read the scrambler status over SCDC channel, and check the
+ * scrambling status.
+ *
+ * Return: True if the scrambling is enabled, false otherwise.
I think the rest of DRM/KMS kerneldoc tries to use "Returns:\n" as a
standard way to document return values.
Ok.
+ */
+
+bool drm_check_scrambling_status(struct i2c_adapter *adapter)
Maybe use a drm_scdc_*() prefix for this to make it more consistent with
other SCDC API.
While at it, would this not be better located in drm_scdc.c along with
the other helpers? drm_edid.c is more focussed on the parsing aspects of
all things EDID.
Yeah, the same is mentioned by Ville too, will do that.
+{
+ u8 status;
+
+ if (drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status) < 0) {
How about storing the error code...
+ DRM_ERROR("Failed to read scrambling status\n");
... and making it part of the error message? Sometimes its useful to
know what exact error triggered this because it helps narrowing down
where things went wrong.
Agree, in fact while debugging and testing this patch series, I had to print
it explicitly.
+ return false;
+ }
+
+ status &= SCDC_SCRAMBLING_STATUS;
+ return status != 0;
Maybe make this a single line:
return (status & SCDC_SCRAMBLING_STATUS) != 0;
Got it.
+}
+
+/**
+ * drm_enable_scrambling - enable scrambling
+ * @connector: target drm_connector
"target DRM connector"?
Got it.
+ * @adapter: i2c adapter for SCDC channel
+ * @force: enable scrambling, even if its already enabled
+ *
+ * Write the TMDS config over SCDC channel, and enable scrambling
+ * Return: True if scrambling is successfully enabled, false otherwise.
+ */
+
+bool drm_enable_scrambling(struct drm_connector *connector,
+ struct i2c_adapter *adapter, bool force)
I think I'd move this to drm_scdc.c as well because it primarily
operates on SCDC. If you do so, might be worth making adapter the first
argument for consistency with other SCDC API.
Agree, will move it.
+{
+ u8 config;
+ struct drm_hdmi_info *hdmi_info = &connector->display_info.hdmi_info;
+
+ if (
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Make intel_guc_send a function pointer
== Series Details == Series: drm/i915/guc: Make intel_guc_send a function pointer URL : https://patchwork.freedesktop.org/series/19024/ State : failure == Summary == Series 19024v1 drm/i915/guc: Make intel_guc_send a function pointer https://patchwork.freedesktop.org/api/1.0/series/19024/revisions/1/mbox/ Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (fi-skl-6700hq) pass -> FAIL (fi-skl-6770hq) fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:226 dwarn:0 dfail:0 fail:1 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:233 dwarn:0 dfail:0 fail:1 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest 10d15f9 drm/i915/guc: Make intel_guc_send a function pointer == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3684/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Dynamically alloc GuC descriptor
== Series Details == Series: drm/i915/guc: Dynamically alloc GuC descriptor URL : https://patchwork.freedesktop.org/series/19022/ State : success == Summary == Series 19022v1 drm/i915/guc: Dynamically alloc GuC descriptor https://patchwork.freedesktop.org/api/1.0/series/19022/revisions/1/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 fi-bxt-t5700 failed to collect. IGT log at Patchwork_3683/fi-bxt-t5700/igt.log 0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest 3cca7cd drm/i915/guc: Dynamically alloc GuC descriptor == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3683/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: Make intel_guc_send a function pointer
From: Michal Wajdeczko
Prepare for an alternate GuC communication interface.
v2: Make a few functions static and name them correctly while we are at it
(Oscar)
Signed-off-by: Michel Thierry
Signed-off-by: Michal Wajdeczko
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_uc.c | 25 +++--
drivers/gpu/drm/i915/intel_uc.h | 9 -
2 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c46bc85..0e45ef0 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -25,16 +25,11 @@
#include "i915_drv.h"
#include "intel_uc.h"
-void intel_uc_init_early(struct drm_i915_private *dev_priv)
-{
- mutex_init(&dev_priv->guc.send_mutex);
-}
-
/*
* Read GuC command/status register (SOFT_SCRATCH_0)
* Return true if it contains a response rather than a command
*/
-static bool intel_guc_recv(struct intel_guc *guc, u32 *status)
+static bool guc_recv(struct intel_guc *guc, u32 *status)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -43,7 +38,10 @@ static bool intel_guc_recv(struct intel_guc *guc, u32
*status)
return INTEL_GUC_RECV_IS_RESPONSE(val);
}
-int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
+/*
+ * This function implements the MMIO based host to GuC interface.
+ */
+static int guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 status;
@@ -71,9 +69,9 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action,
u32 len)
* up to that length of time, then switch to a slower sleep-wait loop.
* No inte_guc_send command should ever take longer than 10ms.
*/
- ret = wait_for_us(intel_guc_recv(guc, &status), 10);
+ ret = wait_for_us(guc_recv(guc, &status), 10);
if (ret)
- ret = wait_for(intel_guc_recv(guc, &status), 10);
+ ret = wait_for(guc_recv(guc, &status), 10);
if (status != INTEL_GUC_STATUS_SUCCESS) {
/*
* Either the GuC explicitly returned an error (which
@@ -98,6 +96,14 @@ int intel_guc_send(struct intel_guc *guc, const u32 *action,
u32 len)
return ret;
}
+void intel_uc_init_early(struct drm_i915_private *dev_priv)
+{
+ struct intel_guc *guc = &dev_priv->guc;
+
+ mutex_init(&dev_priv->guc.send_mutex);
+ guc->send = guc_send_mmio;
+}
+
int intel_guc_sample_forcewake(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -113,4 +119,3 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
-
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index d74f4d3..aed8653 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -174,6 +174,9 @@ struct intel_guc {
/* To serialize the intel_guc_send actions */
struct mutex send_mutex;
+
+ /* GuC's FW specific send function */
+ int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
};
struct intel_huc {
@@ -185,9 +188,13 @@ struct intel_huc {
/* intel_uc.c */
void intel_uc_init_early(struct drm_i915_private *dev_priv);
-int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_sample_forcewake(struct intel_guc *guc);
+static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32
len)
+{
+ return guc->send(guc, action, len);
+}
+
/* intel_guc_loader.c */
extern void intel_guc_init(struct drm_i915_private *dev_priv);
extern int intel_guc_setup(struct drm_i915_private *dev_priv);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: Dynamically alloc GuC descriptor
From: Michal Wajdeczko
The GuC descriptor is big in size. If we use local definition of
guc_desc we have a chance to overflow stack. Use allocated one.
v2: Rebased
v3: Split
v4: Handle ENOMEM, cover all uses of guc_context_desc, use kzalloc (Oscar)
Signed-off-by: Deepak S
Signed-off-by: Michal Wajdeczko
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_guc_submission.c | 94 ++
1 file changed, 57 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 8ced9e2..b4f14f3 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -102,9 +102,13 @@ static int guc_update_doorbell_id(struct intel_guc *guc,
struct sg_table *sg = guc->ctx_pool_vma->pages;
void *doorbell_bitmap = guc->doorbell_bitmap;
struct guc_doorbell_info *doorbell;
- struct guc_context_desc desc;
+ struct guc_context_desc *desc;
size_t len;
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
doorbell = client->vaddr + client->doorbell_offset;
if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
@@ -116,15 +120,22 @@ static int guc_update_doorbell_id(struct intel_guc *guc,
}
/* Update the GuC's idea of the doorbell ID */
- len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
-sizeof(desc) * client->ctx_index);
- if (len != sizeof(desc))
+ len = sg_pcopy_to_buffer(sg->sgl, sg->nents, desc, sizeof(*desc),
+sizeof(*desc) * client->ctx_index);
+ if (len != sizeof(*desc)) {
+ kfree(desc);
return -EFAULT;
- desc.db_id = new_id;
- len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
-sizeof(desc) * client->ctx_index);
- if (len != sizeof(desc))
+ }
+
+ desc->db_id = new_id;
+ len = sg_pcopy_from_buffer(sg->sgl, sg->nents, desc, sizeof(*desc),
+ sizeof(*desc) * client->ctx_index);
+ if (len != sizeof(*desc)) {
+ kfree(desc);
return -EFAULT;
+ }
+
+ kfree(desc);
client->doorbell_id = new_id;
if (new_id == GUC_INVALID_DOORBELL_ID)
@@ -229,30 +240,33 @@ static void guc_proc_desc_init(struct intel_guc *guc,
* This descriptor tells the GuC where (in GGTT space) to find the important
* data structures relating to this client (doorbell, process descriptor,
* write queue, etc).
+ *
+ * Returns: 0 on success, negative error code on failure.
*/
-
-static void guc_ctx_desc_init(struct intel_guc *guc,
+static int guc_ctx_desc_init(struct intel_guc *guc,
struct i915_guc_client *client)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_engine_cs *engine;
struct i915_gem_context *ctx = client->owner;
- struct guc_context_desc desc;
+ struct guc_context_desc *desc;
struct sg_table *sg;
unsigned int tmp;
u32 gfx_addr;
- memset(&desc, 0, sizeof(desc));
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
- desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
- desc.context_id = client->ctx_index;
- desc.priority = client->priority;
- desc.db_id = client->doorbell_id;
+ desc->attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
+ desc->context_id = client->ctx_index;
+ desc->priority = client->priority;
+ desc->db_id = client->doorbell_id;
for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
struct intel_context *ce = &ctx->engine[engine->id];
uint32_t guc_engine_id = engine->guc_id;
- struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
+ struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id];
/* TODO: We have a design issue to be solved here. Only when we
* receive the first batch, we know which engine is used by the
@@ -277,50 +291,56 @@ static void guc_ctx_desc_init(struct intel_guc *guc,
lrc->ring_next_free_location = lrc->ring_begin;
lrc->ring_current_tail_pointer_value = 0;
- desc.engines_used |= (1 << guc_engine_id);
+ desc->engines_used |= (1 << guc_engine_id);
}
DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
- client->engines, desc.engines_used);
- WARN_ON(desc.engines_used == 0);
+ client->engines, desc->engines_used);
+ WARN_ON(desc->engines_used == 0);
/*
* The doorbell, process descriptor, and workqueue are
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees (rev2)
== Series Details == Series: series starting with [v5] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees (rev2) URL : https://patchwork.freedesktop.org/series/18987/ State : success == Summary == Series 18987v2 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/18987/revisions/2/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest e0f0df0 drm: kselftest for drm_mm and bottom-up allocation ab8bcb9 drm: Improve drm_mm search (and fix topdown allocation) with rbtrees == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3682/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Drain the freed state from the tail of the next commit
== Series Details == Series: drm/i915: Drain the freed state from the tail of the next commit URL : https://patchwork.freedesktop.org/series/19012/ State : failure == Summary == Series 19012v1 drm/i915: Drain the freed state from the tail of the next commit https://patchwork.freedesktop.org/api/1.0/series/19012/revisions/1/mbox/ Test drv_hangman: Subgroup error-state-basic: pass -> INCOMPLETE (fi-hsw-4770) fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:5pass:4dwarn:0 dfail:0 fail:0 skip:0 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest 3bac83a drm/i915: Drain the freed state from the tail of the next commit == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3681/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees
The drm_mm range manager claimed to support top-down insertion, but it
was neither searching for the top-most hole that could fit the
allocation request nor fitting the request to the hole correctly.
In order to search the range efficiently, we create a secondary index
for the holes using either their size or their address. This index
allows us to find the smallest hole or the hole at the bottom or top of
the range efficiently, whilst keeping the hole stack to rapidly service
evictions.
v2: Search for holes both high and low. Rename flags to mode.
v3: Discover rb_entry_safe() and use it!
v4: Kerneldoc for enum drm_mm_insert_mode.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Russell King
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Sean Paul
Cc: Lucas Stach
Cc: Christian Gmeiner
Cc: Rob Clark
Cc: Thierry Reding
Cc: Stephen Warren
Cc: Alexandre Courbot
Cc: Eric Anholt
Cc: Sinclair Yeh
Cc: Thomas Hellstrom
Reviewed-by: Alex Deucher
Reviewed-by: Sinclair Yeh # vmwgfx
---
v5: Rebase onto etnaviv pull for 4.11 -- no intentional changes from v4.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 20 +-
drivers/gpu/drm/armada/armada_gem.c | 4 +-
drivers/gpu/drm/drm_mm.c | 488 +++
drivers/gpu/drm/drm_vma_manager.c| 3 +-
drivers/gpu/drm/etnaviv/etnaviv_mmu.c| 11 +-
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_evict.c| 9 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +--
drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +-
drivers/gpu/drm/msm/msm_gem.c| 3 +-
drivers/gpu/drm/msm/msm_gem_vma.c| 3 +-
drivers/gpu/drm/selftests/test-drm_mm.c | 58 ++--
drivers/gpu/drm/sis/sis_mm.c | 6 +-
drivers/gpu/drm/tegra/gem.c | 4 +-
drivers/gpu/drm/ttm/ttm_bo_manager.c | 18 +-
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
drivers/gpu/drm/vc4/vc4_hvs.c| 3 +-
drivers/gpu/drm/vc4/vc4_plane.c | 6 +-
drivers/gpu/drm/via/via_mm.c | 4 +-
drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c | 10 +-
include/drm/drm_mm.h | 184 +-
23 files changed, 470 insertions(+), 442 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index e4eb6dd3798a..0335c2f331e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -97,8 +97,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
{
struct amdgpu_gtt_mgr *mgr = man->priv;
struct drm_mm_node *node = mem->mm_node;
- enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST;
- enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT;
+ enum drm_mm_insert_mode mode;
unsigned long fpfn, lpfn;
int r;
@@ -115,15 +114,14 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
else
lpfn = man->size;
- if (place && place->flags & TTM_PL_FLAG_TOPDOWN) {
- sflags = DRM_MM_SEARCH_BELOW;
- aflags = DRM_MM_CREATE_TOP;
- }
+ mode = DRM_MM_INSERT_BEST;
+ if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
+ mode = DRM_MM_INSERT_HIGH;
spin_lock(&mgr->lock);
- r = drm_mm_insert_node_in_range_generic(&mgr->mm, node, mem->num_pages,
- mem->page_alignment, 0,
- fpfn, lpfn, sflags, aflags);
+ r = drm_mm_insert_node_in_range(&mgr->mm, node,
+ mem->num_pages, mem->page_alignment, 0,
+ fpfn, lpfn, mode);
spin_unlock(&mgr->lock);
if (!r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index ac9007986c11..9e577e3d3147 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -97,8 +97,7 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager
*man,
struct amdgpu_vram_mgr *mgr = man->priv;
struct drm_mm *mm = &mgr->mm;
struct drm_mm_node *nodes;
- enum drm_mm_search_flags sflags = DRM_MM_SEARCH_DEFAULT;
- enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT;
+ enum drm_mm_insert_mode mode;
unsigned long lpfn, num_nodes, pages_per_node, pages_left;
unsigned i;
int r;
@@ -121,10 +120,9 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager
*man,
if (!nodes)
return -ENOMEM;
- if (place->flags & TTM_PL_FLAG_TOPDOWN) {
-
[Intel-gfx] [drm-intel:drm-intel-nightly 1076/1086] drivers/gpu/drm/gma500/framebuffer.c:566:8: error: too few arguments to function 'drm_fb_helper_init'
tree: git://anongit.freedesktop.org/drm-intel drm-intel-nightly head: 0f01216949002d20b9dc6d300c82df5ffa59e9a7 commit: e4563f6ba71792c77aeccb2092cc23149b44e642 [1076/1086] drm: Rely on mode_config data for fb_helper initialization config: i386-randconfig-x0-02030244 (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: git checkout e4563f6ba71792c77aeccb2092cc23149b44e642 # save the attached .config to linux build tree make ARCH=i386 Note: the drm-intel/drm-intel-nightly HEAD 0f01216949002d20b9dc6d300c82df5ffa59e9a7 builds fine. It only hurts bisectibility. All errors (new ones prefixed by >>): drivers/gpu/drm/gma500/framebuffer.c: In function 'psb_fbdev_init': >> drivers/gpu/drm/gma500/framebuffer.c:566:8: error: too few arguments to >> function 'drm_fb_helper_init' ret = drm_fb_helper_init(dev, &fbdev->psb_fb_helper, ^~ In file included from drivers/gpu/drm/gma500/framebuffer.c:35:0: include/drm/drm_fb_helper.h:309:19: note: declared here static inline int drm_fb_helper_init(struct drm_device *dev, ^~ -- drivers/gpu/drm/qxl/qxl_fb.c: In function 'qxl_fbdev_init': >> drivers/gpu/drm/qxl/qxl_fb.c:401:8: error: too few arguments to function >> 'drm_fb_helper_init' ret = drm_fb_helper_init(&qdev->ddev, &qfbdev->helper, ^~ In file included from drivers/gpu/drm/qxl/qxl_fb.c:35:0: include/drm/drm_fb_helper.h:309:19: note: declared here static inline int drm_fb_helper_init(struct drm_device *dev, ^~ vim +/drm_fb_helper_init +566 drivers/gpu/drm/gma500/framebuffer.c 4d8d096e9 Alan Cox2011-11-03 560 } 4d8d096e9 Alan Cox2011-11-03 561 4d8d096e9 Alan Cox2011-11-03 562 dev_priv->fbdev = fbdev; 10a231026 Thierry Reding 2014-06-27 563 10a231026 Thierry Reding 2014-06-27 564 drm_fb_helper_prepare(dev, &fbdev->psb_fb_helper, &psb_fb_helper_funcs); 4d8d096e9 Alan Cox2011-11-03 565 01934c2a6 Thierry Reding 2014-12-19 @566 ret = drm_fb_helper_init(dev, &fbdev->psb_fb_helper, e4563f6ba Gabriel Krisman Bertazi 2017-02-02 567 INTELFB_CONN_LIMIT); 01934c2a6 Thierry Reding 2014-12-19 568 if (ret) 01934c2a6 Thierry Reding 2014-12-19 569 goto free; :: The code at line 566 was first introduced by commit :: 01934c2a691882185b3021d437df13bcba07711d drm/fb-helper: Propagate errors from initial config failure :: TO: Thierry Reding :: CC: Daniel Vetter --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Drain the freed state from the tail of the next commit
If we have any residual freed atomic state from earlier commits, flush
the freed list after performing the current modeset. This prevents the
freed list from ever-growing if userspace manages to starve the kernel
threads (i.e. we are never able to run our free state worker and
eventually the system may even oom).
Fixes: eb955eee27d9 ("drm/i915: Move atomic state free from out of fence
release")
Testcase: igt/kms_cursor/legacy/all-pipes-single-bo
Reported-by: Maarten Lankhorst
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
Cc: Joonas Lahtinen
Cc: Daniel Vetter
---
Though the earlier patch is cc'ed for v4.10, I don't this fix to the fix
merits applying to v4.10 this late. The impact should be small, it takes
the deliberate abuse of RT tasks to starve the kernel so badly as that
the delayed free of the atomic state will cause system-wide consequences
(e.g. oom)
---
drivers/gpu/drm/i915/intel_display.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 88689a0b4183..45e587496886 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14395,6 +14395,24 @@ static void skl_update_crtcs(struct drm_atomic_state
*state,
} while (progress);
}
+static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
+{
+ struct intel_atomic_state *state, *next;
+ struct llist_node *freed;
+
+ freed = llist_del_all(&dev_priv->atomic_helper.free_list);
+ llist_for_each_entry_safe(state, next, freed, freed)
+ drm_atomic_state_put(&state->base);
+}
+
+static void intel_atomic_helper_free_state_worker(struct work_struct *work)
+{
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), atomic_helper.free_work);
+
+ intel_atomic_helper_free_state(dev_priv);
+}
+
static void intel_atomic_commit_tail(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
@@ -14561,6 +14579,8 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
* can happen also when the device is completely off.
*/
intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
+
+ intel_atomic_helper_free_state(dev_priv);
}
static void intel_atomic_commit_work(struct work_struct *work)
@@ -16615,18 +16635,6 @@ static void sanitize_watermarks(struct drm_device *dev)
drm_modeset_acquire_fini(&ctx);
}
-static void intel_atomic_helper_free_state(struct work_struct *work)
-{
- struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), atomic_helper.free_work);
- struct intel_atomic_state *state, *next;
- struct llist_node *freed;
-
- freed = llist_del_all(&dev_priv->atomic_helper.free_list);
- llist_for_each_entry_safe(state, next, freed, freed)
- drm_atomic_state_put(&state->base);
-}
-
int intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -16647,7 +16655,7 @@ int intel_modeset_init(struct drm_device *dev)
dev->mode_config.funcs = &intel_mode_funcs;
INIT_WORK(&dev_priv->atomic_helper.free_work,
- intel_atomic_helper_free_state);
+ intel_atomic_helper_free_state_worker);
intel_init_quirks(dev);
--
2.11.0
___
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Re: [Intel-gfx] [v4.6-10530-g28165ec7a99b] i915: *ERROR* "CPU pipe/PCH transcoder" A FIFO underrun
On Fri, May 27, 2016 at 10:19 AM, Chris Bainbridge wrote: > On 25 May 2016 at 08:31, Sedat Dilek wrote: >> Hi Daniel, >> >> with latest Linus Git I see this with my Intel SandyBridge GPU... >> >> [ 17.629014] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] >> *ERROR* CPU pipe A FIFO underrun >> [ 17.630652] [drm:intel_set_pch_fifo_underrun_reporting [i915]] >> *ERROR* uncleared pch fifo underrun on pch transcoder A >> [ 17.630685] [drm:intel_pch_fifo_underrun_irq_handler [i915]] >> *ERROR* PCH transcoder A FIFO underrun > > Guessing this is https://bugs.freedesktop.org/show_bug.cgi?id=95736 Hi Matt, Hi Daniel, can you look at fdo #95736, please? I still see this on all my Linux-kernels up to Linus upstream of today. Thanks. Regards, - Sedat - ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-tip:drm-tip 1066/1073] drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c:376:8: error: too few arguments to function 'drm_fb_helper_init'
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: 36aab92fa2091dd54ea983752aa40e427e83d113
commit: e4563f6ba71792c77aeccb2092cc23149b44e642 [1066/1073] drm: Rely on
mode_config data for fb_helper initialization
config: i386-randconfig-x007-201705 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
git checkout e4563f6ba71792c77aeccb2092cc23149b44e642
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c: In function 'amdgpu_fbdev_init':
>> drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c:376:8: error: too few arguments to
>> function 'drm_fb_helper_init'
ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
^~
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:39:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:50,
from drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c:34:
include/drm/drm_fb_helper.h:309:19: note: declared here
static inline int drm_fb_helper_init(struct drm_device *dev,
^~
vim +/drm_fb_helper_init +376 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
d38ceaf9 Alex Deucher 2015-04-20 370 rfbdev->adev = adev;
d38ceaf9 Alex Deucher 2015-04-20 371 adev->mode_info.rfbdev = rfbdev;
d38ceaf9 Alex Deucher 2015-04-20 372
d38ceaf9 Alex Deucher 2015-04-20 373 drm_fb_helper_prepare(adev->ddev,
&rfbdev->helper,
d38ceaf9 Alex Deucher 2015-04-20 374
&amdgpu_fb_helper_funcs);
d38ceaf9 Alex Deucher 2015-04-20 375
d38ceaf9 Alex Deucher 2015-04-20 @376 ret = drm_fb_helper_init(adev->ddev,
&rfbdev->helper,
d38ceaf9 Alex Deucher 2015-04-20 377
AMDGPUFB_CONN_LIMIT);
d38ceaf9 Alex Deucher 2015-04-20 378 if (ret) {
d38ceaf9 Alex Deucher 2015-04-20 379 kfree(rfbdev);
:: The code at line 376 was first introduced by commit
:: d38ceaf99ed015f2a0b9af3499791bd3a3daae21 drm/amdgpu: add core driver (v4)
:: TO: Alex Deucher
:: CC: Alex Deucher
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
___
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Re: [Intel-gfx] [PATCH v4 1/2] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees
vmwgfx part: Reviewed-by: Sinclair Yeh
On Thu, Feb 02, 2017 at 11:44:33AM +, Chris Wilson wrote:
> The drm_mm range manager claimed to support top-down insertion, but it
> was neither searching for the top-most hole that could fit the
> allocation request nor fitting the request to the hole correctly.
>
> In order to search the range efficiently, we create a secondary index
> for the holes using either their size or their address. This index
> allows us to find the smallest hole or the hole at the bottom or top of
> the range efficiently, whilst keeping the hole stack to rapidly service
> evictions.
>
> v2: Search for holes both high and low. Rename flags to mode.
> v3: Discover rb_entry_safe() and use it!
> v4: Kerneldoc for enum drm_mm_insert_mode.
>
> Signed-off-by: Chris Wilson
> Reviewed-by: Joonas Lahtinen
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Russell King
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Cc: Sean Paul
> Cc: Lucas Stach
> Cc: Christian Gmeiner
> Cc: Rob Clark
> Cc: Thierry Reding
> Cc: Stephen Warren
> Cc: Alexandre Courbot
> Cc: Eric Anholt
> Cc: Sinclair Yeh
> Cc: Thomas Hellstrom
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 20 +-
> drivers/gpu/drm/armada/armada_gem.c | 4 +-
> drivers/gpu/drm/drm_mm.c | 488
> +++
> drivers/gpu/drm/drm_vma_manager.c| 3 +-
> drivers/gpu/drm/etnaviv/etnaviv_mmu.c| 16 +-
> drivers/gpu/drm/i915/i915_gem.c | 10 +-
> drivers/gpu/drm/i915/i915_gem_evict.c| 9 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +--
> drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +-
> drivers/gpu/drm/msm/msm_gem.c| 3 +-
> drivers/gpu/drm/msm/msm_gem_vma.c| 3 +-
> drivers/gpu/drm/selftests/test-drm_mm.c | 58 ++--
> drivers/gpu/drm/sis/sis_mm.c | 6 +-
> drivers/gpu/drm/tegra/gem.c | 4 +-
> drivers/gpu/drm/ttm/ttm_bo_manager.c | 18 +-
> drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
> drivers/gpu/drm/vc4/vc4_hvs.c| 3 +-
> drivers/gpu/drm/vc4/vc4_plane.c | 6 +-
> drivers/gpu/drm/via/via_mm.c | 4 +-
> drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c | 10 +-
> include/drm/drm_mm.h | 184 +-
> 23 files changed, 470 insertions(+), 447 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index e4eb6dd3798a..0335c2f331e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -97,8 +97,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
> {
> struct amdgpu_gtt_mgr *mgr = man->priv;
> struct drm_mm_node *node = mem->mm_node;
> - enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST;
> - enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT;
> + enum drm_mm_insert_mode mode;
> unsigned long fpfn, lpfn;
> int r;
>
> @@ -115,15 +114,14 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager
> *man,
> else
> lpfn = man->size;
>
> - if (place && place->flags & TTM_PL_FLAG_TOPDOWN) {
> - sflags = DRM_MM_SEARCH_BELOW;
> - aflags = DRM_MM_CREATE_TOP;
> - }
> + mode = DRM_MM_INSERT_BEST;
> + if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
> + mode = DRM_MM_INSERT_HIGH;
>
> spin_lock(&mgr->lock);
> - r = drm_mm_insert_node_in_range_generic(&mgr->mm, node, mem->num_pages,
> - mem->page_alignment, 0,
> - fpfn, lpfn, sflags, aflags);
> + r = drm_mm_insert_node_in_range(&mgr->mm, node,
> + mem->num_pages, mem->page_alignment, 0,
> + fpfn, lpfn, mode);
> spin_unlock(&mgr->lock);
>
> if (!r) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> index ac9007986c11..9e577e3d3147 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> @@ -97,8 +97,7 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager
> *man,
> struct amdgpu_vram_mgr *mgr = man->priv;
> struct drm_mm *mm = &mgr->mm;
> struct drm_mm_node *nodes;
> - enum drm_mm_search_flags sflags = DRM_MM_SEARCH_DEFAULT;
> - enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT;
> + enum drm_mm_insert_mode mode;
> unsigned long lpfn, num_nodes, pages_per_node, pages_left;
> unsigned i;
> int r;
> @@ -121,10 +120,9 @@ static int amdgpu_vram_mgr_new(struct
> ttm_me
Re: [Intel-gfx] [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring
On Wed, Feb 01, 2017 at 11:40:06AM -0800, Manasi Navare wrote: > Are you planning on submitting a v2 for these pretty soon > that can make it to patchwork/ > > Regards > Manasi > > On Thu, Jan 26, 2017 at 09:44:14PM +0200, Jani Nikula wrote: > > This is kind of version 1½ of [1], basically just rebased on current git > > (including Manasi's test automation patches) and a couple of more > > cleanups slammed on top. > > > > BR, > > Jani. > > So the problem we still have with link rate fallback after link failure->uevent-> fetch new modes->link retrain is that after we send a uevent, userspace fetches new modes which calls drm_helper_probe_single_connector_modes() that calls dp_detect which ends up calling intel_dp_long_pulse(). So while userspace is just trying to fetch new modes it overwrites the max_link_rate and max_lane_count values through intel_dp_long_pulse(). So while retraining, when it calls intel_dp_compute_config(), it will use the overwritten values of common_rates/max_link_rate/max_lane_count as opposed to the ones set in intel_dp_get_fallback_values(). I wonder if this patch series solves this problem somehow... else, do you have any insight on how we can solve this? Regards Manasi > > > > [1] cover.1485015599.git.jani.nikula@intel.com">http://mid.mail-archive.com/cover.1485015599.git.jani.nikula@intel.com > > > > > > Jani Nikula (13): > > drm/i915/dp: use known correct array size in rate_to_index > > drm/i915/dp: return errors from rate_to_index() > > drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse > > drm/i915/dp: cache source rates at init > > drm/i915/dp: generate and cache sink rate array for all DP, not just > > eDP 1.4 > > drm/i915/dp: use the sink rates array for max sink rates > > drm/i915/dp: cache common rates with sink rates > > drm/i915/dp: do not limit rate seek when not needed > > drm/i915/dp: don't call the link parameters sink parameters > > drm/i915/dp: add functions for max common link rate and lane count > > drm/i915/mst: use max link not sink lane count > > drm/i915/dp: localize link rate index variable more > > drm/i915/dp: use readb and writeb calls for single byte DPCD access > > > > drivers/gpu/drm/i915/intel_dp.c | 275 > > ++ > > drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +- > > drivers/gpu/drm/i915/intel_dp_mst.c | 4 +- > > drivers/gpu/drm/i915/intel_drv.h | 19 +- > > 4 files changed, 166 insertions(+), 135 deletions(-) > > > > -- > > 2.1.4 > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm: scrambling support in drm layer
On Thu, Feb 02, 2017 at 11:08:22AM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 2/1/2017 10:02 PM, Thierry Reding wrote:
> > On Wed, Feb 01, 2017 at 06:14:39PM +0530, Shashank Sharma wrote:
> > > HDMI 2.0 spec mandates scrambling for modes with pixel clock higher
> > > than 340Mhz. This patch adds few new functions in drm layer for
> > > core drivers to enable/disable scrambling.
> > >
> > > This patch adds:
> > > - A function to detect scrambling support parsing HF-VSDB
> > > - A function to check scrambling status runtime using SCDC read.
> > > - Two functions to enable/disable scrambling using SCDC read/write.
> > > - Few new bools to reflect scrambling support and status.
> > >
> > > Signed-off-by: Shashank Sharma
> > > ---
> > > drivers/gpu/drm/drm_edid.c | 131
> > > +++-
> > > include/drm/drm_connector.h | 24
> > > include/drm/drm_edid.h | 6 +-
> > > 3 files changed, 159 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index 37902e5..f0d940a 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -37,6 +37,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #define version_greater(edid, maj, min) \
> > > (((edid)->version > (maj)) || \
> > > @@ -3814,6 +3815,132 @@ static void drm_detect_hdmi_scdc(struct
> > > drm_connector *connector,
> > > }
> > > }
> > > +static void drm_detect_hdmi_scrambling(struct drm_connector *connector,
> > > + const u8 *hf_vsdb)
> > > +{
> > > + struct drm_display_info *display = &connector->display_info;
> > > + struct drm_hdmi_info *hdmi = &display->hdmi_info;
> > > +
> > > + /*
> > > + * All HDMI 2.0 monitors must support scrambling at rates > 340M.
> > In comments below you use Mhz as the abbreviations. This should be
> > consistent. Also I think "MHz" is actually the correct spelling.
> Agree.
> > > + * And as per the spec, three factors confirm this:
> > > + * * Availability of a HF-VSDB block in EDID (check)
> > > + * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB
> > > + * * SCDC support available
> > > + * Lets check it out.
> > > + */
> > > +
> > > + if (hf_vsdb[5]) {
> > > + display->max_tmds_clock = hf_vsdb[5] * 5000;
> > > + DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
> > > + display->max_tmds_clock);
> > > +
> > > + if (hdmi->scdc_supported) {
> > > + hdmi->scr_info.supported = true;
> > > +
> > > + /* Few sinks support scrambling for cloks < 340M */
> > > + if ((hf_vsdb[6] & 0x8))
> > > + hdmi->scr_info.low_clocks = true;
> > > + }
> > > + }
> > > +}
> > > +
> > > +/**
> > > + * drm_check_scrambling_status - what is status of scrambling?
> > > + * @adapter: i2c adapter for SCDC channel
> > "I2C", same in other parts of this patch.
> Got it.
> > > + *
> > > + * Read the scrambler status over SCDC channel, and check the
> > > + * scrambling status.
> > > + *
> > > + * Return: True if the scrambling is enabled, false otherwise.
> > I think the rest of DRM/KMS kerneldoc tries to use "Returns:\n" as a
> > standard way to document return values.
> Ok.
> > > + */
> > > +
> > > +bool drm_check_scrambling_status(struct i2c_adapter *adapter)
> > Maybe use a drm_scdc_*() prefix for this to make it more consistent with
> > other SCDC API.
> >
> > While at it, would this not be better located in drm_scdc.c along with
> > the other helpers? drm_edid.c is more focussed on the parsing aspects of
> > all things EDID.
> Yeah, the same is mentioned by Ville too, will do that.
> > > +{
> > > + u8 status;
> > > +
> > > + if (drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status) < 0) {
> > How about storing the error code...
> >
> > > + DRM_ERROR("Failed to read scrambling status\n");
> > ... and making it part of the error message? Sometimes its useful to
> > know what exact error triggered this because it helps narrowing down
> > where things went wrong.
> Agree, in fact while debugging and testing this patch series, I had to print
> it explicitly.
> >
> > > + return false;
> > > + }
> > > +
> > > + status &= SCDC_SCRAMBLING_STATUS;
> > > + return status != 0;
> > Maybe make this a single line:
> >
> > return (status & SCDC_SCRAMBLING_STATUS) != 0;
> Got it.
> >
> > > +}
> > > +
> > > +/**
> > > + * drm_enable_scrambling - enable scrambling
> > > + * @connector: target drm_connector
> > "target DRM connector"?
> Got it.
> > > + * @adapter: i2c adapter for SCDC channel
> > > + * @force: enable scrambling, even if its already enabled
> > > + *
> > > + * Write the TMDS config over SCDC channel, and enable scrambling
> > > + * Return: True if scrambling is successfully enabled, false otherwise.
> > > + */
> > > +
> > > +bool drm_enable_scrambling(struct
Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_plane_multiple: Test only with maximum number of planes
Reviewed-by: Robert Foss
On 2017-02-02 06:12 AM, Mika Kahola wrote:
To be more suitable for BAT testing, let's modify the test such a way
that it only uses the maximum number of available planes. This reduces
the total number of subtests.
v2: Fix broken kms_plane_multiple --list-subtests (Petri)
Cc: Petri Latvala
Cc: Robert Foss
Signed-off-by: Mika Kahola
---
tests/kms_plane_multiple.c | 141 +
1 file changed, 65 insertions(+), 76 deletions(-)
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index bb84878..4930286 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -171,7 +171,7 @@ create_fb_for_mode_position(data_t *data, igt_output_t
*output, drmModeModeInfo
mode->hdisplay, mode->vdisplay,
color->red, color->green, color->blue);
- for (int i = 0; i <= max_planes; i++) {
+ for (int i = 0; i < max_planes; i++) {
if (data->plane[i]->type == DRM_PLANE_TYPE_PRIMARY)
continue;
igt_paint_color(cr, rect_x[i], rect_y[i],
@@ -211,7 +211,7 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t
*color,
/* planes with random positions */
x[primary->index] = 0;
y[primary->index] = 0;
- for (i = 1; i <= max_planes; i++) {
+ for (i = 0; i < max_planes; i++) {
igt_plane_t *plane = igt_output_get_plane(output, i);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
@@ -247,7 +247,7 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t
*color,
static void
test_atomic_plane_position_with_output(data_t *data, enum pipe pipe,
igt_output_t *output, int n_planes,
- int max_planes, uint64_t tiling)
+ uint64_t tiling)
{
char buf[256];
struct drm_event *e = (void *)buf;
@@ -270,7 +270,7 @@ test_atomic_plane_position_with_output(data_t *data, enum
pipe pipe,
}
igt_info("Testing connector %s using pipe %s with %d planes %s with seed
%d\n",
-igt_output_name(output), kmstest_pipe_name(pipe), max_planes,
+igt_output_name(output), kmstest_pipe_name(pipe), n_planes,
info, opt.seed);
test_init(data, pipe, n_planes);
@@ -280,7 +280,7 @@ test_atomic_plane_position_with_output(data_t *data, enum
pipe pipe,
i = 0;
while (i < iterations || loop_forever) {
- prepare_planes(data, pipe, &blue, tiling, max_planes, output);
+ prepare_planes(data, pipe, &blue, tiling, n_planes, output);
vblank_start = kmstest_get_vblank(data->display.drm_fd, pipe,
DRM_VBLANK_NEXTONMISS);
@@ -316,7 +316,7 @@ test_atomic_plane_position_with_output(data_t *data, enum
pipe pipe,
static void
test_legacy_plane_position_with_output(data_t *data, enum pipe pipe,
igt_output_t *output, int n_planes,
- int max_planes, uint64_t tiling)
+ uint64_t tiling)
{
test_position_t test = { .data = data };
color_t blue = { 0.0f, 0.0f, 1.0f };
@@ -336,7 +336,7 @@ test_legacy_plane_position_with_output(data_t *data, enum
pipe pipe,
}
igt_info("Testing connector %s using pipe %s with %d planes %s with seed
%d\n",
-igt_output_name(output), kmstest_pipe_name(pipe), max_planes,
+igt_output_name(output), kmstest_pipe_name(pipe), n_planes,
info, opt.seed);
test_init(data, pipe, n_planes);
@@ -346,7 +346,7 @@ test_legacy_plane_position_with_output(data_t *data, enum
pipe pipe,
i = 0;
while (i < iterations || loop_forever) {
- prepare_planes(data, pipe, &blue, tiling, max_planes, output);
+ prepare_planes(data, pipe, &blue, tiling, n_planes, output);
igt_display_commit2(&data->display, COMMIT_LEGACY);
@@ -365,19 +365,16 @@ test_legacy_plane_position_with_output(data_t *data, enum
pipe pipe,
}
static void
-test_plane_position(data_t *data, enum pipe pipe, bool atomic, int n_planes,
- int max_planes, uint64_t tiling)
+test_plane_position(data_t *data, enum pipe pipe, bool atomic, uint64_t tiling)
{
igt_output_t *output;
int connected_outs;
int devid = intel_get_drm_devid(data->drm_fd);
+ int n_planes = data->display.pipes[pipe].n_planes;
if (atomic)
igt_require(data->display.is_atomic);
- igt_skip_on(pipe >= data->display.n_pipes);
- igt_skip_on(max_planes >= data->display.pipes[pipe].n_planes);
-
if ((tiling == LOCAL_I915_FORMAT_MOD_Y_TILED ||
tiling == LOCAL_I915_FORMAT_MOD_Yf_TILED))
igt_require
Re: [Intel-gfx] [PATCH 3/6] drm/edid: detect SCDC support in HF-VSDB
On Thu, Feb 02, 2017 at 10:58:43AM +0530, Sharma, Shashank wrote:
> Thanks for the review Thierry. My comments inline.
>
> Regards
> Shashank
> On 2/1/2017 9:40 PM, Thierry Reding wrote:
> > On Wed, Feb 01, 2017 at 06:14:38PM +0530, Shashank Sharma wrote:
> > > This patch does following:
> > > - Adds a new structure (drm_hdmi_info) in drm_display_info.
> > >This structure will be used to save and indicate if sink
> > >supports advance HDMI 2.0 features
> > "advanced"
> got it.
> >
> > > - Checks the HF-VSDB block for presence of SCDC, and marks it
> > >in hdmi_info structure.
> > "drm_hdmi_info structure"?
> yep, sure.
> > > - If SCDC is present, checks if sink is capable of generating
> > >scdc read request, and marks it in hdmi_info structure.
> > "SCDC" to be consistent and because it's an abbreviation.
> Agree.
> > > Signed-off-by: Shashank Sharma
> > > ---
> > > drivers/gpu/drm/drm_edid.c | 14 ++
> > > include/drm/drm_connector.h | 26 ++
> > > 2 files changed, 40 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index 96d3e47..37902e5 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -3802,6 +3802,18 @@ enum hdmi_quantization_range
> > > }
> > > EXPORT_SYMBOL(drm_default_rgb_quant_range);
> > > +static void drm_detect_hdmi_scdc(struct drm_connector *connector,
> > > + const u8 *hf_vsdb)
> > > +{
> > > + struct drm_hdmi_info *hdmi = &connector->display_info.hdmi_info;
> > > +
> > > + if (hf_vsdb[6] & 0x80) {
> > > + hdmi->scdc_supported = true;
> > > + if (hf_vsdb[6] & 0x40)
> > > + hdmi->scdc_rr = true;
> > > + }
> > > +}
> > > +
> > > static void drm_parse_hdmi_deep_color_info(struct drm_connector
> > > *connector,
> > > const u8 *hdmi)
> > > {
> > > @@ -3916,6 +3928,8 @@ static void drm_parse_cea_ext(struct drm_connector
> > > *connector,
> > > if (cea_db_is_hdmi_vsdb(db))
> > > drm_parse_hdmi_vsdb_video(connector, db);
> > > + if (cea_db_is_hdmi_forum_vsdb(db))
> > > + drm_detect_hdmi_scdc(connector, db);
> > > }
> > > }
> > > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> > > index e5e1edd..2435598 100644
> > > --- a/include/drm/drm_connector.h
> > > +++ b/include/drm/drm_connector.h
> > > @@ -87,6 +87,27 @@ enum subpixel_order {
> > > SubPixelVerticalRGB,
> > > SubPixelVerticalBGR,
> > > SubPixelNone,
> > > +
> > > +};
> > > +
> > > +/**
> > > + * struct drm_hdmi_info - runtime data about the connected sink
> > Maybe "connected HDMI sink"?
> Agree.
> > > + *
> > > + * Describes if a given hdmi display supports advance HDMI 2.0 featutes.
> > "HDMI", "advanced", "features"
> Oops, got it :-)
> > > + * This information is available in CEA-861-F extension blocks (like
> > > + * HF-VSDB)
> > This should be terminated by a full-stop.
> Ok
> > > + * For sinks which provide an EDID this can be filled out by calling
> > > + * drm_add_edid_modes().
> > And maybe make this sentence start right after the one above rather than
> > breaking it to the next line.
> Ok
> > I'm not sure how useful this line is. Most
> > driver will be calling drm_add_edid_modes() anyway, but the above makes
> > it sound like drm_add_edid_modes() is something you have to explicitly
> > call to get these fields parsed.
> Mostly a 'yy' and 'p' from the function above, but makes sense, I can remove
> this line.
> > > + */
> > > +struct drm_hdmi_info {
> > > + /**
> > > + * @scdc_supported: status control & data channel present.
> > > + */
> > > + bool scdc_supported;
> > > + /**
> > > + * @scdc_rr: sink is capable of generating scdc read request.
> > > + */
> > > + bool scdc_rr;
> > > };
> > > /**
> > > @@ -188,6 +209,11 @@ struct drm_display_info {
> > >* @cea_rev: CEA revision of the HDMI sink.
> > >*/
> > > u8 cea_rev;
> > > +
> > > + /**
> > > + * @hdmi_info: advance features of a HDMI sink.
> > > + */
> > > + struct drm_hdmi_info hdmi_info;
> > I think we can safely drop the _info suffix on the field name. It's
> > already inside a structure that carries this suffix.
> Sure, should I call it hdmi_sink OR connected_hdmi ?
No, I think just plain "hdmi" would be fine. This is part of
drm_display_info, which kind of implies that it's a sink, and I think
it's also fair to assume that this isn't valid if nothing's connected.
Thierry
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/19] drm/i915: Micro-optimise i915_get_ggtt_vma_pages()
== Series Details == Series: series starting with [01/19] drm/i915: Micro-optimise i915_get_ggtt_vma_pages() URL : https://patchwork.freedesktop.org/series/18997/ State : success == Summary == Series 18997v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/18997/revisions/1/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 11190c4421e0076a9f37205b0d53b2b3f2733711 drm-tip: 2017y-02m-02d-15h-01m-15s UTC integration manifest 0d8618c drm/i915: Micro-optimise gen8_ppgtt_insert_entries() 98f31b3 drm/i915: Micro-optimise gen6_ppgtt_insert_entries() 2724b29 drm/i915: Micro-optimise i915_get_ggtt_vma_pages() == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3680/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1½ 12/13] drm/i915/dp: localize link rate index variable more
On Thu, Feb 02, 2017 at 10:42:48AM +0200, Jani Nikula wrote:
> On Thu, 02 Feb 2017, Manasi Navare wrote:
> > On Thu, Jan 26, 2017 at 09:44:26PM +0200, Jani Nikula wrote:
> >> Localize link_rate_index to the if block, and rename to just index to
> >> reduce indent.
> >>
> >> Cc: Manasi Navare
> >> Cc: Ville Syrjälä
> >> Signed-off-by: Jani Nikula
> >> ---
> >> drivers/gpu/drm/i915/intel_dp.c | 13 +++--
> >> 1 file changed, 7 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> >> b/drivers/gpu/drm/i915/intel_dp.c
> >> index 7704d32286a3..429dc70c251a 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -1639,7 +1639,6 @@ intel_dp_compute_config(struct intel_encoder
> >> *encoder,
> >>/* Conveniently, the link BW constants become indices with a shift...*/
> >>int min_clock = 0;
> >>int max_clock;
> >> - int link_rate_index;
> >>int bpp, mode_rate;
> >>int link_avail, link_clock;
> >>const int *common_rates = intel_dp->common_rates;
> >> @@ -1684,11 +1683,13 @@ intel_dp_compute_config(struct intel_encoder
> >> *encoder,
> >>
> >>/* Use values requested by Compliance Test Request */
> >>if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> >> - link_rate_index = intel_dp_find_rate(intel_dp->common_rates,
> >> - intel_dp->num_common_rates,
> >> -
> >> intel_dp->compliance.test_link_rate);
> >
> > Can we not pass just the common_rates as an argument to this function
> > since common_rates is already assigned intel_dp->common_rates.
>
> Do you mean just pass intel_dp to intel_dp_find_rate? If yes, I think
> this keeps intel_dp_find_rate generic, independent of intel_dp or
> anything else, and you can be sure it's stateless (same as
> intersect_rates).
>
> If you don't mean that, I don't know what you mean... please explain.
>
> BR,
> Jani.
>
>
I agree that it needs to be stateless and hence we dont pass intel_dp directly.
What I was saying was that at the beginning of the function we do initialize
common_rates = intel_dp->common_rates;
so why cant we pass just common_rates to this function instead of
intel_dp->common_rates?
Not sure if this optimization will make any big impact but just a thought.
Regards
Manasi
> >
> > Regards
> > Manasi
> >
> >
> >> - if (link_rate_index >= 0)
> >> - min_clock = max_clock = link_rate_index;
> >> + int index;
> >> +
> >> + index = intel_dp_find_rate(intel_dp->common_rates,
> >> + intel_dp->num_common_rates,
> >> + intel_dp->compliance.test_link_rate);
> >> + if (index >= 0)
> >> + min_clock = max_clock = index;
> >>min_lane_count = max_lane_count =
> >> intel_dp->compliance.test_lane_count;
> >>}
> >>DRM_DEBUG_KMS("DP link computation with max lane count %i "
> >> --
> >> 2.1.4
> >>
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: remove 512GB allocation warning
== Series Details == Series: drm/i915: remove 512GB allocation warning URL : https://patchwork.freedesktop.org/series/18995/ State : success == Summary == Series 18995v1 drm/i915: remove 512GB allocation warning https://patchwork.freedesktop.org/api/1.0/series/18995/revisions/1/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 11190c4421e0076a9f37205b0d53b2b3f2733711 drm-tip: 2017y-02m-02d-15h-01m-15s UTC integration manifest e894021 drm/i915: remove 512GB allocation warning == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3679/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/19] drm/i915: Micro-optimise gen8_ppgtt_insert_entries()
On 02/02/2017 17:05, Chris Wilson wrote:
On Thu, Feb 02, 2017 at 04:39:49PM +, Tvrtko Ursulin wrote:
On 02/02/2017 16:10, Chris Wilson wrote:
On Thu, Feb 02, 2017 at 03:57:43PM +, Tvrtko Ursulin wrote:
On 02/02/2017 15:32, Chris Wilson wrote:
On Thu, Feb 02, 2017 at 03:02:32PM +, Chris Wilson wrote:
Improve the sg iteration and in hte process eliminate a bug in
miscomputing the pml4 length as orig_nents<
which fixes a corner case of 0c40ce130e38
Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
What do you mean? oring_nents is definitely the full length of the
sg table, especially after i915_sg_trim. Before it orig_nents was
often larger than the real length of the sg table.
The code is using orig_nents as obj->base.size/vma->size (a page count,
not the sg count), if I read it correctly as it is computing the address
range.
Oh right, I was misled by the commit message ("is not longer the
full length of the sg table"). Nasty. That means it was broken for
userptr objects as well.
And partial, and... pretty everything at some point.
Partials won't be in ppgtt. Neither the stolen ones, and internal ones
are only gen7 right?
Hmm, maybe it is the recent spat of NULL deref for gen8 ppgtt. I'd been
assuming that they had a similar unknown cause to the gen6 which have
been around for yonks.
Tart up the commit message and this could 4.10-rc material.
Yeah, but how this actually manifests? It should be blowing up left
right and center because sg trim in my testing managed to trim
impressively. I don't get it. I'll leave the thinking for tomorrow.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 03/19] drm/i915: Micro-optimise gen8_ppgtt_insert_entries()
On Thu, Feb 02, 2017 at 04:39:49PM +, Tvrtko Ursulin wrote:
>
> On 02/02/2017 16:10, Chris Wilson wrote:
> >On Thu, Feb 02, 2017 at 03:57:43PM +, Tvrtko Ursulin wrote:
> >>
> >>On 02/02/2017 15:32, Chris Wilson wrote:
> >>>On Thu, Feb 02, 2017 at 03:02:32PM +, Chris Wilson wrote:
> Improve the sg iteration and in hte process eliminate a bug in
> miscomputing the pml4 length as orig_nents< full length of the sg table.
>
> >>>
> >>>which fixes a corner case of 0c40ce130e38
> >>>Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
> >>
> >>What do you mean? oring_nents is definitely the full length of the
> >>sg table, especially after i915_sg_trim. Before it orig_nents was
> >>often larger than the real length of the sg table.
> >
> >The code is using orig_nents as obj->base.size/vma->size (a page count,
> >not the sg count), if I read it correctly as it is computing the address
> >range.
>
> Oh right, I was misled by the commit message ("is not longer the
> full length of the sg table"). Nasty. That means it was broken for
> userptr objects as well.
And partial, and... pretty everything at some point.
Hmm, maybe it is the recent spat of NULL deref for gen8 ppgtt. I'd been
assuming that they had a similar unknown cause to the gen6 which have
been around for yonks.
Tart up the commit message and this could 4.10-rc material.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for Still call-traces after suspend-resume (pm? i915? cpu/hotplug?) (rev2)
== Series Details == Series: Still call-traces after suspend-resume (pm? i915? cpu/hotplug?) (rev2) URL : https://patchwork.freedesktop.org/series/18871/ State : success == Summary == Series 18871v2 Still call-traces after suspend-resume (pm? i915? cpu/hotplug?) https://patchwork.freedesktop.org/api/1.0/series/18871/revisions/2/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 11190c4421e0076a9f37205b0d53b2b3f2733711 drm-tip: 2017y-02m-02d-15h-01m-15s UTC integration manifest d0adc5b Still call-traces after suspend-resume (pm? i915? cpu/hotplug?) == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3678/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/19] drm/i915: Micro-optimise gen8_ppgtt_insert_entries()
On 02/02/2017 16:10, Chris Wilson wrote:
On Thu, Feb 02, 2017 at 03:57:43PM +, Tvrtko Ursulin wrote:
On 02/02/2017 15:32, Chris Wilson wrote:
On Thu, Feb 02, 2017 at 03:02:32PM +, Chris Wilson wrote:
Improve the sg iteration and in hte process eliminate a bug in
miscomputing the pml4 length as orig_nents<
which fixes a corner case of 0c40ce130e38
Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
What do you mean? oring_nents is definitely the full length of the
sg table, especially after i915_sg_trim. Before it orig_nents was
often larger than the real length of the sg table.
The code is using orig_nents as obj->base.size/vma->size (a page count,
not the sg count), if I read it correctly as it is computing the address
range.
Oh right, I was misled by the commit message ("is not longer the full
length of the sg table"). Nasty. That means it was broken for userptr
objects as well.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH] drm/i915: Enable atomic support by default on supported platforms.
Hi, On 2 February 2017 at 07:41, Maarten Lankhorst wrote: > i915 is pretty much feature complete. Support for atomic i915-specific > connector properties is still missing; those properties can (for now) > only be set through the legacy ioctl. > > ILK style watermarks and gen9+ watermarks are handled atomically, > and nonblocking modesets work. FBC has also been made to work with > atomic. > > gen4x- and vlv/chv watermarks still need to be fixed, so disable atomic > by default there for now. > > Flip the switch!! Not until we have the multi-CRTC event support please. :\ I don't want to have divergent event paths for atomic-but-useless-events. I've been frantically typing up support for this in Weston (actual proper atomic modesetting, which is difficult when you have fiercely independent per-output repaint loops, but seems ~mostly done but for typing), which I'd hoped to have done a week or two ago but got derailed due to being sick. It's coming just as quickly as I can type it tho. Cheers, Daniel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/9] drm/i915: Use DRM_DEBUG_KMS() for framebuffer failure debug messages
On Wed, Jan 04, 2017 at 08:42:30PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> DRM_UT_CORE generates way too much noise usually, so having the
> framebuffer init failures use DRM_UT_CORE is a pain when trying to
> find out the reason why you failed in creating a framebuffer.
> Let's use DRM_UT_KMS for these debug messages instead.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 66
> ++--
> 1 file changed, 33 insertions(+), 33 deletions(-)
> [...]
> @@ -15940,17 +15940,17 @@ static int intel_framebuffer_init(struct drm_device
> *dev,
>*/
> if (INTEL_INFO(dev_priv)->gen < 4 &&
> tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
> - DRM_DEBUG("tiling_mode must match fb modifier exactly on
> gen2/3\n");
> + DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on
> gen2/3\n");
> return -EINVAL;
> }
>
> pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
> mode_cmd->pixel_format);
> if (mode_cmd->pitches[0] > pitch_limit) {
> - DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
> - mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
> - "tiled" : "linear",
> - mode_cmd->pitches[0], pitch_limit);
> + DRM_DEBUG_KMS("%s pitch (%u) must be at less than %d\n",
While at it: s/at less than/at most/
Reviewed-by: Imre Deak
> + mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
> + "tiled" : "linear",
> + mode_cmd->pitches[0], pitch_limit);
> return -EINVAL;
> }
>
> @@ -15960,9 +15960,9 @@ static int intel_framebuffer_init(struct drm_device
> *dev,
>*/
> if (tiling != I915_TILING_NONE &&
> mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
> - DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
> - mode_cmd->pitches[0],
> - i915_gem_object_get_stride(obj));
> + DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
> + mode_cmd->pitches[0],
> + i915_gem_object_get_stride(obj));
> return -EINVAL;
> }
>
> @@ -15975,16 +15975,16 @@ static int intel_framebuffer_init(struct drm_device
> *dev,
> break;
> case DRM_FORMAT_XRGB1555:
> if (INTEL_GEN(dev_priv) > 3) {
> - DRM_DEBUG("unsupported pixel format: %s\n",
> - drm_get_format_name(mode_cmd->pixel_format,
> &format_name));
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> }
> break;
> case DRM_FORMAT_ABGR:
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> INTEL_GEN(dev_priv) < 9) {
> - DRM_DEBUG("unsupported pixel format: %s\n",
> - drm_get_format_name(mode_cmd->pixel_format,
> &format_name));
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> }
> break;
> @@ -15992,15 +15992,15 @@ static int intel_framebuffer_init(struct drm_device
> *dev,
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
> if (INTEL_GEN(dev_priv) < 4) {
> - DRM_DEBUG("unsupported pixel format: %s\n",
> - drm_get_format_name(mode_cmd->pixel_format,
> &format_name));
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> }
> break;
> case DRM_FORMAT_ABGR2101010:
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
> - DRM_DEBUG("unsupported pixel format: %s\n",
> - drm_get_format_name(mode_cmd->pixel_format,
> &format_name));
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> }
> break;
> @@ -16009,14 +16009,14 @@ static int intel_framebuffer_init(struct drm_device
> *dev,
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_VYUY:
> if (INTEL_GEN(dev_priv) < 5) {
> -
Re: [Intel-gfx] [PATCH 6/9] drm/i915: Pass the correct plane index to _intel_compute_tile_offset()
On Wed, Jan 04, 2017 at 08:42:29PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > intel_fill_fb_info() should pass the correct plane index to > _intel_compute_tile_offset() once we start to care about the AUX > surface. > > Signed-off-by: Ville Syrjälä This changes how x/y and offset is calculated already now for planes with a cpp different than that of plane 0, but the end result remains the same: Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 0ca0dbccc005..5fee5a7ac9a4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2525,7 +2525,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, > intel_fb->normal[i].y = y; > > offset = _intel_compute_tile_offset(dev_priv, &x, &y, > - fb, 0, fb->pitches[i], > + fb, i, fb->pitches[i], > DRM_ROTATE_0, tile_size); > offset /= tile_size; > > -- > 2.10.2 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/19] drm/i915: Micro-optimise gen8_ppgtt_insert_entries()
On Thu, Feb 02, 2017 at 03:57:43PM +, Tvrtko Ursulin wrote:
>
> On 02/02/2017 15:32, Chris Wilson wrote:
> >On Thu, Feb 02, 2017 at 03:02:32PM +, Chris Wilson wrote:
> >>Improve the sg iteration and in hte process eliminate a bug in
> >>miscomputing the pml4 length as orig_nents< >>full length of the sg table.
> >>
> >
> >which fixes a corner case of 0c40ce130e38
> >Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
>
> What do you mean? oring_nents is definitely the full length of the
> sg table, especially after i915_sg_trim. Before it orig_nents was
> often larger than the real length of the sg table.
The code is using orig_nents as obj->base.size/vma->size (a page count,
not the sg count), if I read it correctly as it is computing the address
range.
-Chris
--
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Re: [Intel-gfx] [PATCH 03/19] drm/i915: Micro-optimise gen8_ppgtt_insert_entries()
On 02/02/2017 15:32, Chris Wilson wrote:
On Thu, Feb 02, 2017 at 03:02:32PM +, Chris Wilson wrote:
Improve the sg iteration and in hte process eliminate a bug in
miscomputing the pml4 length as orig_nents<
which fixes a corner case of 0c40ce130e38
Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
What do you mean? oring_nents is definitely the full length of the sg
table, especially after i915_sg_trim. Before it orig_nents was often
larger than the real length of the sg table.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH igt] intel-ci: Add all driver selftests to BAT
Hi, > > > > Add basic somewhere in the test names? > > Why? Does something still parse basic in the test name and add it to a test No > set? Shouldn't that now be pulling from these lists instead? You are right, yes , we control only static list and addition to it through reviews, Petri, more to add? So we are not using -t basic anymore. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] topic/vma-fix-for-4.10
Hi Dave, here's Maarten's backport of the vma fixes for v4.10. BR, Jani. The following changes since commit 566cf877a1fcb6d6dc0126b076aad062054c2637: Linux 4.10-rc6 (2017-01-29 14:25:17 -0800) are available in the git repository at: git://anongit.freedesktop.org/git/drm-intel tags/topic/vma-fix-for-4.10-2017-02-02 for you to fetch changes up to e8fe4f4b2b7b93048729538321c681c0cff33b39: drm/i915: Track pinned vma in intel_plane_state (2017-02-01 11:45:21 +0200) Chris Wilson (1): drm/i915: Track pinned vma in intel_plane_state Maarten Lankhorst (1): drm/atomic: Unconditionally call prepare_fb. drivers/gpu/drm/drm_atomic_helper.c | 9 --- drivers/gpu/drm/i915/i915_drv.h | 16 +--- drivers/gpu/drm/i915/intel_atomic_plane.c | 20 + drivers/gpu/drm/i915/intel_display.c | 125 ++ drivers/gpu/drm/i915/intel_drv.h | 9 ++- drivers/gpu/drm/i915/intel_fbc.c | 52 + drivers/gpu/drm/i915/intel_fbdev.c| 4 +- drivers/gpu/drm/i915/intel_sprite.c | 8 +- 8 files changed, 99 insertions(+), 144 deletions(-) -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/19] drm/i915: Micro-optimise gen8_ppgtt_insert_entries()
On Thu, Feb 02, 2017 at 03:02:32PM +, Chris Wilson wrote:
> Improve the sg iteration and in hte process eliminate a bug in
> miscomputing the pml4 length as orig_nents< full length of the sg table.
>
which fixes a corner case of 0c40ce130e38
Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table")
-Chris
--
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Re: [Intel-gfx] [PATCH 5/9] drm/i915: Fix Yf tile width
On Wed, Jan 04, 2017 at 08:42:28PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Based on empirical evidence the display engine (at least) always
> treats Yf tiles as 128Bx32. Currently we're assuming the tile dimensions
> change based on the pixel format. Let's adjust our code to match the
> hardware.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
BSpec "Address Tiling Function Introduction/Linear vs Tiled Storage":
"""
Note that the dimensions of tiles are irrespective of the data contained
within – e.g., a tile can hold twice as many 16-bit pixels (256
pixels/row x 8 rows = 2K pixels) than 32-bit pixels (128 pixels/row x 8
rows = 1K pixels).
"""
"Tile-Yf Format":
"""
The 64 Byte block is always 4-high. Width (in pixels) is defined by bpp.
"""
Then it continues to specify the different tile aspect ratios for
different bpps which contradict the above. This aspect ratio definition
is what matches the current code. Filing a BSpec issue for this would be
good.
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 ++--
> 1 file changed, 6 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index bc398743e941..0ca0dbccc005 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2070,20 +2070,12 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int plane)
> else
> return 512;
> case I915_FORMAT_MOD_Yf_TILED:
> - switch (cpp) {
> - case 1:
> - return 64;
> - case 2:
> - case 4:
> - return 128;
> - case 8:
> - case 16:
> - return 256;
> - default:
> - MISSING_CASE(cpp);
> - return cpp;
> - }
> - break;
> + /*
> + * Bspec seems to suggest that the Yf tile width would
> + * depend on the cpp. In reality it doesn't, at least
> + * as far as the display engine is concerned.
> + */
> + return 128;
> default:
> MISSING_CASE(fb->modifier);
> return cpp;
> --
> 2.10.2
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Recreate internal objects with single page segments if dmar fails
== Series Details == Series: drm/i915: Recreate internal objects with single page segments if dmar fails URL : https://patchwork.freedesktop.org/series/18991/ State : success == Summary == Series 18991v1 drm/i915: Recreate internal objects with single page segments if dmar fails https://patchwork.freedesktop.org/api/1.0/series/18991/revisions/1/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 0b2db2bbfbb3fd996e107f76a5c7382f302b0a4b drm-tip: 2017y-02m-02d-14h-27m-33s UTC integration manifest f725ea7 drm/i915: Recreate internal objects with single page segments if dmar fails == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3677/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Enable atomic support by default on supported platforms.
Nice! I actually was already thinking of bringing up the fact we should
just be turning this on by default now, especially so we can see atomic
start getting some real use.
So, I'm more then happy to say I support flipping the switch :)
Reviewed-by: Lyude
On Thu, 2017-02-02 at 08:41 +0100, Maarten Lankhorst wrote:
> i915 is pretty much feature complete. Support for atomic i915-
> specific
> connector properties is still missing; those properties can (for now)
> only be set through the legacy ioctl.
>
> ILK style watermarks and gen9+ watermarks are handled atomically,
> and nonblocking modesets work. FBC has also been made to work with
> atomic.
>
> gen4x- and vlv/chv watermarks still need to be fixed, so disable
> atomic
> by default there for now.
>
> Flip the switch!!
>
> Signed-off-by: Maarten Lankhorst
> Cc: Ander Conselvan de Oliveira m>
> Cc: Chris Wilson
> Cc: Daniel Vetter
> Cc: Lyude
> Cc: Matt Roper
> Cc: Paulo Zanoni
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> ---
> I probably missed a lot of people who also worked on atomic support
> in i915,
> feel free to ack the patch if you've worked on it. :)
>
> drivers/gpu/drm/i915/i915_drv.c| 10 +++---
> drivers/gpu/drm/i915/i915_params.c | 4 ++--
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 0e8eb4b6db00..d4d1abf6d9d2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1206,11 +1206,15 @@ static void i915_driver_unregister(struct
> drm_i915_private *dev_priv)
> */
> int i915_driver_load(struct pci_dev *pdev, const struct
> pci_device_id *ent)
> {
> + const struct intel_device_info *match_info =
> + (struct intel_device_info *) ent->driver_data;
> struct drm_i915_private *dev_priv;
> int ret;
>
> - if (i915.nuclear_pageflip)
> - driver.driver_features |= DRIVER_ATOMIC;
> + /* Enable nuclear pageflip on ILK+, except vlv/chv */
> + if (!i915.nuclear_pageflip &&
> + (match_info->gen < 5 || match_info->has_gmch_display))
> + driver.driver_features &= ~DRIVER_ATOMIC;
>
> ret = -ENOMEM;
> dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
> @@ -2614,7 +2618,7 @@ static struct drm_driver driver = {
> */
> .driver_features =
> DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
> DRIVER_PRIME |
> - DRIVER_RENDER | DRIVER_MODESET,
> + DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
> .open = i915_driver_open,
> .lastclose = i915_driver_lastclose,
> .preclose = i915_driver_preclose,
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 0e280fbd52f1..bb3feabec238 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -205,9 +205,9 @@ module_param_named(verbose_state_checks,
> i915.verbose_state_checks, bool, 0600);
> MODULE_PARM_DESC(verbose_state_checks,
> "Enable verbose logs (ie. WARN_ON()) in case of unexpected
> hw state conditions.");
>
> -module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip,
> bool, 0600);
> +module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip,
> bool, 0400);
> MODULE_PARM_DESC(nuclear_pageflip,
> - "Force atomic modeset functionality; asynchronous
> mode is not yet supported. (default: false).");
> + "Force enable atomic functionality on platforms
> that don't have full support yet.");
>
> /* WA to get away with the default setting in VBT for early
> platforms.Will be removed */
> module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, 0400);
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[Intel-gfx] [PATCH 07/14] drm/i915: Take a reference whilst processing the signaler request
The plan in the near-future is to allow requests to be removed from the
signaler. We can no longer then rely on holding a reference to the
request for the duration it is in the signaling tree, and instead must
obtain a reference to the request for the current operation using RCU.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 24
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 8a56bb516aa0..5bcd8436027c 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -474,7 +474,11 @@ static int intel_breadcrumbs_signaler(void *arg)
* need to wait for a new interrupt from the GPU or for
* a new client.
*/
- request = READ_ONCE(b->first_signal);
+ rcu_read_lock();
+ request = rcu_dereference(b->first_signal);
+ if (request)
+ request = i915_gem_request_get_rcu(request);
+ rcu_read_unlock();
if (signal_complete(request)) {
local_bh_disable();
dma_fence_signal(&request->fence);
@@ -493,21 +497,25 @@ static int intel_breadcrumbs_signaler(void *arg)
* the oldest before picking the next one.
*/
spin_lock_irq(&b->lock);
- if (request == b->first_signal) {
+ if (request == rcu_access_pointer(b->first_signal)) {
struct rb_node *rb =
rb_next(&request->signaling.node);
- b->first_signal = rb ? to_signaler(rb) : NULL;
+ rcu_assign_pointer(b->first_signal,
+ rb ? to_signaler(rb) : NULL);
}
rb_erase(&request->signaling.node, &b->signals);
spin_unlock_irq(&b->lock);
i915_gem_request_put(request);
} else {
- if (kthread_should_stop())
+ if (kthread_should_stop()) {
+ GEM_BUG_ON(request);
break;
+ }
schedule();
}
+ i915_gem_request_put(request);
} while (1);
__set_current_state(TASK_RUNNING);
@@ -572,7 +580,7 @@ void intel_engine_enable_signaling(struct
drm_i915_gem_request *request)
rb_link_node(&request->signaling.node, parent, p);
rb_insert_color(&request->signaling.node, &b->signals);
if (first)
- smp_store_mb(b->first_signal, request);
+ rcu_assign_pointer(b->first_signal, request);
spin_unlock(&b->lock);
@@ -646,7 +654,7 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs
*engine)
/* The engines should be idle and all requests accounted for! */
WARN_ON(READ_ONCE(b->first_wait));
WARN_ON(!RB_EMPTY_ROOT(&b->waiters));
- WARN_ON(READ_ONCE(b->first_signal));
+ WARN_ON(rcu_access_pointer(b->first_signal));
WARN_ON(!RB_EMPTY_ROOT(&b->signals));
if (!IS_ERR_OR_NULL(b->signaler))
@@ -662,8 +670,8 @@ bool intel_breadcrumbs_busy(struct intel_engine_cs *engine)
spin_lock_irq(&b->lock);
- if (b->first_wait) {
- wake_up_process(b->first_wait->tsk);
+ if (rcu_access_pointer(b->first_signal)) {
+ wake_up_process(b->signaler);
busy |= intel_engine_flag(engine);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 9e7fdbb92231..b87317c04e1b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -240,7 +240,7 @@ struct intel_engine_cs {
struct rb_root signals; /* sorted by retirement */
struct intel_wait *first_wait; /* oldest waiter by retirement */
struct task_struct *signaler; /* used for fence signalling */
- struct drm_i915_gem_request *first_signal;
+ struct drm_i915_gem_request __rcu *first_signal;
struct timer_list fake_irq; /* used after a missed interrupt */
struct timer_list hangcheck; /* detect missed interrupts */
--
2.11.0
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Re: [Intel-gfx] [PATCH 08/19] drm/i915: Remove user-triggerable WARN for large objects
On 2 February 2017 at 15:02, Chris Wilson wrote: > Very large objects are expected, so don't WARN the user if they are > using them! > > Signed-off-by: Chris Wilson Let's just go with yours then :) Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: remove 512GB allocation warning
On Thu, Feb 02, 2017 at 02:55:00PM +, Matthew Auld wrote: > Now that we have selftests in place exercising truly huge allocations > we will start to hit the 512GB warning, so now seems like a good time to > remove it. Hey! I wrote userspace tests to hit this WARN() a couple of years ago ;) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/14] drm/i915: Use a local to shorten req->i915->gpu_error.wait_queue
Use a local variable to avoid having to type out the full name of the
gpu_error wait_queue.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index d1ab4e3a8139..fc1e340aa1e1 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1056,6 +1056,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
{
const int state = flags & I915_WAIT_INTERRUPTIBLE ?
TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
+ wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue;
DEFINE_WAIT(reset);
struct intel_wait wait;
@@ -1091,7 +1092,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
set_current_state(state);
if (flags & I915_WAIT_LOCKED)
- add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
+ add_wait_queue(errq, &reset);
intel_wait_init(&wait, req->global_seqno);
if (intel_engine_add_wait(req->engine, &wait))
@@ -1142,8 +1143,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
i915_reset_in_progress(&req->i915->gpu_error)) {
__set_current_state(TASK_RUNNING);
i915_reset(req->i915);
- reset_wait_queue(&req->i915->gpu_error.wait_queue,
-&reset);
+ reset_wait_queue(errq, &reset);
continue;
}
@@ -1154,7 +1154,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
intel_engine_remove_wait(req->engine, &wait);
if (flags & I915_WAIT_LOCKED)
- remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
+ remove_wait_queue(errq, &reset);
__set_current_state(TASK_RUNNING);
complete:
--
2.11.0
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[Intel-gfx] [PATCH 12/14] drm/i915: Refactor direct GPU reset from request waiters
Combine the common code for the pair of waiters into a single function.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 6cf1210984d7..71ae3dc443d8 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1006,6 +1006,16 @@ bool __i915_spin_request(const struct
drm_i915_gem_request *req,
return false;
}
+static bool __i915_reset_request(struct drm_i915_gem_request *request)
+{
+ if (likely(!i915_reset_in_progress(&request->i915->gpu_error)))
+ return false;
+
+ __set_current_state(TASK_RUNNING);
+ i915_reset(request->i915);
+ return true;
+}
+
/**
* i915_wait_request - wait until execution of request has finished
* @req: the request to wait upon
@@ -1069,11 +1079,8 @@ long i915_wait_request(struct drm_i915_gem_request *req,
break;
if (flags & I915_WAIT_LOCKED &&
- i915_reset_in_progress(&req->i915->gpu_error)) {
- __set_current_state(TASK_RUNNING);
- i915_reset(req->i915);
+ __i915_reset_request(req))
continue;
- }
if (signal_pending_state(state, current)) {
timeout = -ERESTARTSYS;
@@ -1137,12 +1144,8 @@ long i915_wait_request(struct drm_i915_gem_request *req,
* to come along and update the breadcrumb (either directly
* itself, or indirectly by recovering the GPU).
*/
- if (flags & I915_WAIT_LOCKED &&
- i915_reset_in_progress(&req->i915->gpu_error)) {
- __set_current_state(TASK_RUNNING);
- i915_reset(req->i915);
+ if (flags & I915_WAIT_LOCKED && __i915_reset_request(req))
continue;
- }
/* Only spin if we know the GPU is processing this request */
if (i915_spin_request(req, state, 2))
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/14] drm/i915: Deconstruct execute fence
On reflection, we are only using the execute fence as a waitqueue on the
global_seqno and not using it for dependency tracking between fences
(unlike the submit and dma fences). By only treating it as a waitqueue,
we can then treat it similar to the other waitqueues durin submit,
making the code simpler.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 47 +++--
drivers/gpu/drm/i915/i915_gem_request.h | 10 +--
2 files changed, 11 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index e4eeb5f5453c..e385d0c3c890 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -69,7 +69,6 @@ static void i915_fence_release(struct dma_fence *fence)
* caught trying to reuse dead objects.
*/
i915_sw_fence_fini(&req->submit);
- i915_sw_fence_fini(&req->execute);
kmem_cache_free(req->i915->requests, req);
}
@@ -211,7 +210,6 @@ static void i915_gem_request_retire(struct
drm_i915_gem_request *request)
lockdep_assert_held(&request->i915->drm.struct_mutex);
GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
- GEM_BUG_ON(!i915_sw_fence_signaled(&request->execute));
GEM_BUG_ON(!i915_gem_request_completed(request));
GEM_BUG_ON(!request->i915->gt.active_requests);
@@ -422,7 +420,7 @@ void __i915_gem_request_submit(struct drm_i915_gem_request
*request)
list_move_tail(&request->link, &timeline->requests);
spin_unlock(&request->timeline->lock);
- i915_sw_fence_commit(&request->execute);
+ wake_up_all(&request->execute);
}
void i915_gem_request_submit(struct drm_i915_gem_request *request)
@@ -457,24 +455,6 @@ submit_notify(struct i915_sw_fence *fence, enum
i915_sw_fence_notify state)
return NOTIFY_DONE;
}
-static int __i915_sw_fence_call
-execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
-{
- struct drm_i915_gem_request *request =
- container_of(fence, typeof(*request), execute);
-
- switch (state) {
- case FENCE_COMPLETE:
- break;
-
- case FENCE_FREE:
- i915_gem_request_put(request);
- break;
- }
-
- return NOTIFY_DONE;
-}
-
/**
* i915_gem_request_alloc - allocate a request structure
*
@@ -567,13 +547,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
/* We bump the ref for the fence chain */
i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
- i915_sw_fence_init(&i915_gem_request_get(req)->execute, execute_notify);
-
- /* Ensure that the execute fence completes after the submit fence -
-* as we complete the execute fence from within the submit fence
-* callback, its completion would otherwise be visible first.
-*/
- i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq);
+ init_waitqueue_head(&req->execute);
i915_priotree_init(&req->priotree);
@@ -1015,6 +989,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue;
DEFINE_WAIT(reset);
+ DEFINE_WAIT(exec);
struct intel_wait wait;
might_sleep();
@@ -1036,12 +1011,11 @@ long i915_wait_request(struct drm_i915_gem_request *req,
if (flags & I915_WAIT_LOCKED)
add_wait_queue(errq, &reset);
- if (!i915_sw_fence_done(&req->execute)) {
- DEFINE_WAIT(exec);
-
+ reset_wait_queue(&req->execute, &exec);
+ if (!req->global_seqno) {
do {
- prepare_to_wait(&req->execute.wait, &exec, state);
- if (i915_sw_fence_done(&req->execute))
+ set_current_state(state);
+ if (req->global_seqno)
break;
if (flags & I915_WAIT_LOCKED &&
@@ -1059,15 +1033,14 @@ long i915_wait_request(struct drm_i915_gem_request *req,
timeout = io_schedule_timeout(timeout);
} while (timeout);
- finish_wait(&req->execute.wait, &exec);
+ finish_wait(&req->execute, &exec);
if (timeout < 0)
goto complete;
- GEM_BUG_ON(!i915_sw_fence_done(&req->execute));
+ GEM_BUG_ON(!req->global_seqno);
}
- GEM_BUG_ON(!i915_sw_fence_done(&req->submit));
- GEM_BUG_ON(!req->global_seqno);
+ GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
/* Optimistic short spin before touching IRQs */
if (i915_spin_request(req, state, 5))
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index 9049936c571c.
[Intel-gfx] [PATCH 08/14] drm/i915: Allow an request to be cancelled
If we preempt a request and remove it from the execution queue, we need
to undo its global seqno and restart any waiters.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 63 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
2 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 5bcd8436027c..96f78ab02447 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -333,22 +333,15 @@ static inline int wakeup_priority(struct
intel_breadcrumbs *b,
return tsk->prio;
}
-void intel_engine_remove_wait(struct intel_engine_cs *engine,
- struct intel_wait *wait)
+static void __intel_engine_remove_wait(struct intel_engine_cs *engine,
+ struct intel_wait *wait)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
- /* Quick check to see if this waiter was already decoupled from
-* the tree by the bottom-half to avoid contention on the spinlock
-* by the herd.
-*/
- if (RB_EMPTY_NODE(&wait->node))
- return;
-
- spin_lock_irq(&b->lock);
+ assert_spin_locked(&b->lock);
if (RB_EMPTY_NODE(&wait->node))
- goto out_unlock;
+ goto out;
if (b->first_wait == wait) {
const int priority = wakeup_priority(b, wait->tsk);
@@ -414,11 +407,27 @@ void intel_engine_remove_wait(struct intel_engine_cs
*engine,
GEM_BUG_ON(RB_EMPTY_NODE(&wait->node));
rb_erase(&wait->node, &b->waiters);
-out_unlock:
+out:
GEM_BUG_ON(b->first_wait == wait);
GEM_BUG_ON(rb_first(&b->waiters) !=
(b->first_wait ? &b->first_wait->node : NULL));
GEM_BUG_ON(!rcu_access_pointer(b->irq_seqno_bh) ^
RB_EMPTY_ROOT(&b->waiters));
+}
+
+void intel_engine_remove_wait(struct intel_engine_cs *engine,
+ struct intel_wait *wait)
+{
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+
+ /* Quick check to see if this waiter was already decoupled from
+* the tree by the bottom-half to avoid contention on the spinlock
+* by the herd.
+*/
+ if (RB_EMPTY_NODE(&wait->node))
+ return;
+
+ spin_lock_irq(&b->lock);
+ __intel_engine_remove_wait(engine, wait);
spin_unlock_irq(&b->lock);
}
@@ -504,6 +513,7 @@ static int intel_breadcrumbs_signaler(void *arg)
rb ? to_signaler(rb) : NULL);
}
rb_erase(&request->signaling.node, &b->signals);
+ RB_CLEAR_NODE(&request->signaling.node);
spin_unlock_irq(&b->lock);
i915_gem_request_put(request);
@@ -588,6 +598,35 @@ void intel_engine_enable_signaling(struct
drm_i915_gem_request *request)
wake_up_process(b->signaler);
}
+void intel_engine_cancel_signaling(struct drm_i915_gem_request *request)
+{
+ struct intel_engine_cs *engine = request->engine;
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+
+ assert_spin_locked(&request->lock);
+ GEM_BUG_ON(!request->signaling.wait.seqno);
+
+ spin_lock(&b->lock);
+
+ if (!RB_EMPTY_NODE(&request->signaling.node)) {
+ if (request == rcu_access_pointer(b->first_signal)) {
+ struct rb_node *rb =
+ rb_next(&request->signaling.node);
+ rcu_assign_pointer(b->first_signal,
+ rb ? to_signaler(rb) : NULL);
+ }
+ rb_erase(&request->signaling.node, &b->signals);
+ RB_CLEAR_NODE(&request->signaling.node);
+ }
+
+ __intel_engine_remove_wait(engine, &request->signaling.wait);
+
+ spin_unlock(&b->lock);
+
+ request->signaling.wait.seqno = 0;
+ i915_gem_request_put(request);
+}
+
int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b87317c04e1b..d55386d0b842 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -601,6 +601,7 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine,
void intel_engine_remove_wait(struct intel_engine_cs *engine,
struct intel_wait *wait);
void intel_engine_enable_signaling(struct drm_i915_gem_request *request);
+void intel_engine_cancel_signaling(struct drm_i915_gem_request *request);
static inline bool intel_engine_has_waiter(const struct intel_engine_cs
*engine)
{
--
2.11.0
__
[Intel-gfx] [PATCH 14/14] drm/i915: Remove one level of indention from wait-for-execute
Now that the code is getting simpler, we can reduce the indentation when
waiting for the global_seqno.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 33 ++---
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index bfdb1013da7d..e75edca2e6c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1071,29 +1071,24 @@ long i915_wait_request(struct drm_i915_gem_request *req,
wait.tsk = current;
restart:
- wait.seqno = i915_gem_request_global_seqno(req);
- if (!wait.seqno) {
- do {
- set_current_state(state);
-
- wait.seqno = i915_gem_request_global_seqno(req);
- if (wait.seqno)
- break;
+ do {
+ set_current_state(state);
+ wait.seqno = i915_gem_request_global_seqno(req);
+ if (wait.seqno)
+ break;
- if (flags & I915_WAIT_LOCKED &&
- __i915_reset_request(req))
- continue;
+ if (flags & I915_WAIT_LOCKED && __i915_reset_request(req))
+ continue;
- if (signal_pending_state(state, current)) {
- timeout = -ERESTARTSYS;
- goto complete;
- }
+ if (signal_pending_state(state, current)) {
+ timeout = -ERESTARTSYS;
+ goto complete;
+ }
- timeout = io_schedule_timeout(timeout);
- } while (timeout);
+ timeout = io_schedule_timeout(timeout);
+ } while (timeout);
- GEM_BUG_ON(!wait.seqno);
- }
+ GEM_BUG_ON(!wait.seqno);
GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
/* Optimistic short spin before touching IRQs */
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/14] drm/i915: Add ourselves to the gpu error waitqueue for the entire wait
Add ourselves to the gpu error waitqueue earllier on, even before we
determine we have to wait on the seqno. This is so that we can then
share the waitqueue between stages in subsequent patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index fc1e340aa1e1..8d4f0c859fee 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1076,6 +1076,9 @@ long i915_wait_request(struct drm_i915_gem_request *req,
trace_i915_gem_request_wait_begin(req);
+ if (flags & I915_WAIT_LOCKED)
+ add_wait_queue(errq, &reset);
+
if (!i915_sw_fence_done(&req->execute)) {
timeout = __i915_request_wait_for_execute(req, flags, timeout);
if (timeout < 0)
@@ -1091,9 +1094,6 @@ long i915_wait_request(struct drm_i915_gem_request *req,
goto complete;
set_current_state(state);
- if (flags & I915_WAIT_LOCKED)
- add_wait_queue(errq, &reset);
-
intel_wait_init(&wait, req->global_seqno);
if (intel_engine_add_wait(req->engine, &wait))
/* In order to check that we haven't missed the interrupt
@@ -1153,11 +1153,11 @@ long i915_wait_request(struct drm_i915_gem_request *req,
}
intel_engine_remove_wait(req->engine, &wait);
- if (flags & I915_WAIT_LOCKED)
- remove_wait_queue(errq, &reset);
__set_current_state(TASK_RUNNING);
complete:
+ if (flags & I915_WAIT_LOCKED)
+ remove_wait_queue(errq, &reset);
trace_i915_gem_request_wait_end(req);
return timeout;
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/14] drm/i915: Exercise request cancellation using a mock selftest
Add a mock selftest to preempt a request and check that we cancel it,
requeue the request and then complete its execution.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_request.c | 59 +++
drivers/gpu/drm/i915/selftests/mock_request.c | 19
drivers/gpu/drm/i915/selftests/mock_request.h | 2 +
3 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
index 92fa55bd68c8..4c565a7b9eff 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
@@ -26,6 +26,7 @@
#include "../i915_selftest.h"
+#include "mock_context.h"
#include "mock_gem_device.h"
static int igt_add_request(void *arg)
@@ -144,12 +145,70 @@ static int igt_fence_wait(void *arg)
return err;
}
+static int igt_request_rewind(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_request *request, *vip;
+ struct i915_gem_context *ctx[2];
+ int err = -EINVAL;
+
+ mutex_lock(&i915->drm.struct_mutex);
+ ctx[0] = mock_context(i915, "A");
+ request = mock_request(i915->engine[RCS], ctx[0], 2 * HZ);
+ if (!request) {
+ err = -ENOMEM;
+ goto err_device;
+ }
+ i915_add_request(request);
+
+ ctx[1] = mock_context(i915, "B");
+ vip = mock_request(i915->engine[RCS], ctx[1], 0);
+ if (!vip) {
+ err = -ENOMEM;
+ goto err_locked;
+ }
+
+ /* Simulate preemption by manual reordering */
+ if (!mock_cancel_request(request)) {
+ pr_err("failed to cancel request (already executed)!\n");
+ i915_add_request(vip);
+ goto err_locked;
+ }
+ i915_add_request(vip);
+ request->engine->submit_request(request);
+
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ if (i915_wait_request(vip, 0, HZ) == -ETIME) {
+ pr_err("timed out waiting for high priority request,
vip.seqno=%d, current seqno=%d\n",
+ vip->global_seqno,
intel_engine_get_seqno(i915->engine[RCS]));
+ goto err;
+ }
+
+ if (i915_gem_request_completed(request)) {
+ pr_err("low priority request already completed\n");
+ goto err;
+ }
+
+ err = 0;
+err:
+ mutex_lock(&i915->drm.struct_mutex);
+err_locked:
+ mock_context_close(ctx[1]);
+ mock_context_close(ctx[0]);
+err_device:
+ mock_device_flush(i915);
+ mutex_unlock(&i915->drm.struct_mutex);
+ return err;
+}
+
int i915_gem_request_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_add_request),
SUBTEST(igt_wait_request),
SUBTEST(igt_fence_wait),
+ SUBTEST(igt_request_rewind),
};
struct drm_i915_private *i915;
int err;
diff --git a/drivers/gpu/drm/i915/selftests/mock_request.c
b/drivers/gpu/drm/i915/selftests/mock_request.c
index e23242d1b88a..0e8d2e7f8c70 100644
--- a/drivers/gpu/drm/i915/selftests/mock_request.c
+++ b/drivers/gpu/drm/i915/selftests/mock_request.c
@@ -22,6 +22,7 @@
*
*/
+#include "mock_engine.h"
#include "mock_request.h"
struct drm_i915_gem_request *
@@ -42,3 +43,21 @@ mock_request(struct intel_engine_cs *engine,
return &mock->base;
}
+
+bool mock_cancel_request(struct drm_i915_gem_request *request)
+{
+ struct mock_request *mock = container_of(request, typeof(*mock), base);
+ struct mock_engine *engine =
+ container_of(request->engine, typeof(*engine), base);
+ bool was_queued;
+
+ spin_lock_irq(&engine->hw_lock);
+ was_queued = !list_empty(&mock->link);
+ list_del_init(&mock->link);
+ spin_unlock_irq(&engine->hw_lock);
+
+ if (was_queued)
+ i915_gem_request_unsubmit(request);
+
+ return was_queued;
+}
diff --git a/drivers/gpu/drm/i915/selftests/mock_request.h
b/drivers/gpu/drm/i915/selftests/mock_request.h
index cc76d4f4eb4e..4dea74c8e96d 100644
--- a/drivers/gpu/drm/i915/selftests/mock_request.h
+++ b/drivers/gpu/drm/i915/selftests/mock_request.h
@@ -41,4 +41,6 @@ mock_request(struct intel_engine_cs *engine,
struct i915_gem_context *context,
unsigned long delay);
+bool mock_cancel_request(struct drm_i915_gem_request *request);
+
#endif /* !__MOCK_REQUEST__ */
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/14] drm/i915: Immediately process a reset before starting waiting
As we handoff the GPU reset to the waiter, we need to check we don't
miss a wakeup if it has already been sent prior to us starting the wait.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 71ae3dc443d8..bfdb1013da7d 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1063,8 +1063,10 @@ long i915_wait_request(struct drm_i915_gem_request *req,
trace_i915_gem_request_wait_begin(req);
add_wait_queue(&req->execute, &exec);
- if (flags & I915_WAIT_LOCKED)
+ if (flags & I915_WAIT_LOCKED) {
add_wait_queue(errq, &reset);
+ __i915_reset_request(req);
+ }
wait.tsk = current;
@@ -1099,7 +1101,8 @@ long i915_wait_request(struct drm_i915_gem_request *req,
goto complete;
set_current_state(state);
- if (intel_engine_add_wait(req->engine, &wait))
+ if (intel_engine_add_wait(req->engine, &wait) ||
+ flags & I915_WAIT_LOCKED)
/* In order to check that we haven't missed the interrupt
* as we enabled it, we need to kick ourselves to do a
* coherent check on the seqno before we sleep.
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/14] drm/i915: Keep a global seqno per-engine
Replace the global device seqno with one for each engine, and account
for in-flight seqno on each separately. This is consistent with
dma-fence as each timeline has separate fence-contexts for each engine
and a seqno is only ordered within a fence-context (i.e. seqno do not
need to be ordered wrt to other engines, just ordered within a single
engine). This is required to enable request rewinding for preemption on
individual engines (we have to rewind the global seqno to avoid
overflow, and we do not have to rewind all engines just to preempt one.)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +--
drivers/gpu/drm/i915/i915_gem_request.c | 68 +++-
drivers/gpu/drm/i915/i915_gem_request.h | 8 +---
drivers/gpu/drm/i915/i915_gem_timeline.h | 4 +-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 33 +++-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +-
7 files changed, 52 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3fc14820a151..4f4c3fd40b80 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1079,10 +1079,7 @@ static const struct file_operations
i915_error_state_fops = {
static int
i915_next_seqno_get(void *data, u64 *val)
{
- struct drm_i915_private *dev_priv = data;
-
- *val = 1 + atomic_read(&dev_priv->gt.global_timeline.seqno);
- return 0;
+ return -ENODEV;
}
static int
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index bd2aeb290cad..d1ab4e3a8139 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -213,7 +213,9 @@ static void i915_gem_request_retire(struct
drm_i915_gem_request *request)
GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
GEM_BUG_ON(!i915_sw_fence_signaled(&request->execute));
GEM_BUG_ON(!i915_gem_request_completed(request));
+
GEM_BUG_ON(!request->i915->gt.active_requests);
+ GEM_BUG_ON(!request->engine->timeline->active_seqno);
trace_i915_gem_request_retire(request);
@@ -237,6 +239,7 @@ static void i915_gem_request_retire(struct
drm_i915_gem_request *request)
&request->i915->gt.idle_work,
msecs_to_jiffies(100));
}
+ request->engine->timeline->active_seqno--;
/* Walk through the active list, calling retire on each. This allows
* objects to track their GPU activity and mark themselves as idle
@@ -325,15 +328,19 @@ static int i915_gem_init_global_seqno(struct
drm_i915_private *i915, u32 seqno)
GEM_BUG_ON(i915->gt.active_requests > 1);
/* If the seqno wraps around, we need to clear the breadcrumb rbtree */
- if (!i915_seqno_passed(seqno, atomic_read(&timeline->seqno))) {
- while (intel_breadcrumbs_busy(i915))
- cond_resched(); /* spin until threads are complete */
- }
- atomic_set(&timeline->seqno, seqno);
+ for_each_engine(engine, i915, id) {
+ struct intel_timeline *tl = &timeline->engine[id];
- /* Finally reset hw state */
- for_each_engine(engine, i915, id)
+ if (!i915_seqno_passed(seqno, tl->seqno)) {
+ /* spin until threads are complete */
+ while (intel_breadcrumbs_busy(engine))
+ cond_resched();
+ }
+
+ /* Finally reset hw state */
+ tl->seqno = seqno;
intel_engine_init_global_seqno(engine, seqno);
+ }
list_for_each_entry(timeline, &i915->gt.timelines, link) {
for_each_engine(engine, i915, id) {
@@ -361,34 +368,28 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32
seqno)
return i915_gem_init_global_seqno(dev_priv, seqno - 1);
}
-static int reserve_global_seqno(struct drm_i915_private *i915)
+static int reserve_global_seqno(struct intel_engine_cs *engine)
{
- u32 active_requests = ++i915->gt.active_requests;
- u32 seqno = atomic_read(&i915->gt.global_timeline.seqno);
+ u32 active = ++engine->timeline->active_seqno;
+ u32 seqno = engine->timeline->seqno;
int ret;
/* Reservation is fine until we need to wrap around */
- if (likely(seqno + active_requests > seqno))
+ if (likely(seqno + active > seqno))
return 0;
- ret = i915_gem_init_global_seqno(i915, 0);
+ ret = i915_gem_init_global_seqno(engine->i915, 0);
if (ret) {
- i915->gt.active_requests--;
+ engine->timeline->active_seqno--;
return ret;
}
return 0;
}
-static u32 __timeline_get_seqno(struct i915_gem_timeline *tl)
+static u32 timeline_get_seqno(str
[Intel-gfx] [PATCH 09/14] drm/i915: Remove the preempted request from the execution queue
After the request is cancelled, we then need to remove it from the
global execution timeline and return it to the context timeline, the
inverse of submit_request().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 58 +++-
drivers/gpu/drm/i915/i915_gem_request.h | 3 ++
drivers/gpu/drm/i915/intel_breadcrumbs.c | 19 +--
3 files changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 82606f8fd244..f70a2c3d26cd 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -435,6 +435,55 @@ void i915_gem_request_submit(struct drm_i915_gem_request
*request)
spin_unlock_irqrestore(&engine->timeline->lock, flags);
}
+void __i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
+{
+ struct intel_engine_cs *engine = request->engine;
+ struct intel_timeline *timeline;
+
+ assert_spin_locked(&engine->timeline->lock);
+
+ /* Only unwind in reverse order, required so that the per-context list
+* is kept in seqno/ring order.
+*/
+ GEM_BUG_ON(request->global_seqno != engine->timeline->seqno);
+ engine->timeline->seqno--;
+
+ /* We may be recursing from the signal callback of another i915 fence */
+ spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
+ request->global_seqno = 0;
+ if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
+ intel_engine_cancel_signaling(request);
+ spin_unlock(&request->lock);
+
+ /* Transfer back from the global per-engine timeline to per-context */
+ timeline = request->timeline;
+ GEM_BUG_ON(timeline == engine->timeline);
+
+ spin_lock(&timeline->lock);
+ list_move(&request->link, &timeline->requests);
+ spin_unlock(&timeline->lock);
+
+ /* We don't need to wake_up any waiters on request->execute, they
+* will get woken by any other event or us re-adding this request
+* to the engine timeline (__i915_gem_request_submit()). The waiters
+* should be quite adapt at finding that the request now has a new
+* global_seqno to the one they went to sleep on.
+*/
+}
+
+void i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
+{
+ struct intel_engine_cs *engine = request->engine;
+ unsigned long flags;
+
+ /* Will be called from irq-context when using foreign fences. */
+ spin_lock_irqsave(&engine->timeline->lock, flags);
+
+ __i915_gem_request_unsubmit(request);
+
+ spin_unlock_irqrestore(&engine->timeline->lock, flags);
+}
+
static int __i915_sw_fence_call
submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
{
@@ -1016,9 +1065,11 @@ long i915_wait_request(struct drm_i915_gem_request *req,
if (flags & I915_WAIT_LOCKED)
add_wait_queue(errq, &reset);
- intel_wait_init(&wait, i915_gem_request_global_seqno(req));
+ wait.tsk = current;
+restart:
reset_wait_queue(&req->execute, &exec);
+ wait.seqno = i915_gem_request_global_seqno(req);
if (!wait.seqno) {
do {
set_current_state(state);
@@ -1112,6 +1163,11 @@ long i915_wait_request(struct drm_i915_gem_request *req,
/* Only spin if we know the GPU is processing this request */
if (i915_spin_request(req, state, 2))
break;
+
+ if (i915_gem_request_global_seqno(req) != wait.seqno) {
+ intel_engine_remove_wait(req->engine, &wait);
+ goto restart;
+ }
}
intel_engine_remove_wait(req->engine, &wait);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index b81f6709905c..5f73d8c0a38a 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -274,6 +274,9 @@ void __i915_add_request(struct drm_i915_gem_request *req,
bool flush_caches);
void __i915_gem_request_submit(struct drm_i915_gem_request *request);
void i915_gem_request_submit(struct drm_i915_gem_request *request);
+void __i915_gem_request_unsubmit(struct drm_i915_gem_request *request);
+void i915_gem_request_unsubmit(struct drm_i915_gem_request *request);
+
struct intel_rps_client;
#define NO_WAITBOOST ERR_PTR(-1)
#define IS_RPS_CLIENT(p) (!IS_ERR(p))
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 96f78ab02447..843195f13302 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -431,7 +431,14 @@ void intel_engine_remove_wait(struct intel_engine_cs
*engine,
spin_unlock_irq(&b->lock);
}
-static bool signal_complete(struct drm_i915_gem_request *request)
+static bool signal_valid
[Intel-gfx] [PATCH 06/14] drm/i915: Protect the request->global_seqno with the engine->timeline lock
A request is assigned a global seqno only when it is on the hardware
execution queue. The global seqno can be used to maintain a list of
requests on the same engine in retirement order, for example for
constructing a priority queue for waiting. Prior to its execution, or
if it is subsequently removed in the event of preemption, its global
seqno is zero. As both insertion and removal from the execution queue
may operate in IRQ context, it is not guarded by the usual struct_mutex
BKL. Instead those relying on the global seqno must be prepared for its
value to change between reads. Only when the request is complete can
the global seqno be stable (due to the memory barriers on submitting
the commands to the hardware to write the breadcrumb, if the HWS shows
that it has passed the global seqno and the global seqno is unchanged
after the read, it is indeed complete).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 16 ++--
drivers/gpu/drm/i915/i915_gem.c | 15 +---
drivers/gpu/drm/i915/i915_gem_request.c | 46 ++
drivers/gpu/drm/i915/i915_gem_request.h | 66 +---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 11 --
5 files changed, 113 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f82c59768f65..748aadb36e62 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3975,14 +3975,24 @@ wait_remaining_ms_from_jiffies(unsigned long
timestamp_jiffies, int to_wait_ms)
}
static inline bool
-__i915_request_irq_complete(struct drm_i915_gem_request *req)
+__i915_request_irq_complete(const struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
+ u32 seqno = i915_gem_request_global_seqno(req);
+
+ /* The request was dequeued before we were awoken. We check after
+* inspecting the hw to confirm that this was the same request
+* that generated the HWS update. The memory barriers within
+* the request execution are sufficient to ensure that a check
+* after reading the value from hw matches this request.
+*/
+ if (!seqno)
+ return false;
/* Before we do the heavier coherent read of the seqno,
* check the value (hopefully) in the CPU cacheline.
*/
- if (__i915_gem_request_completed(req))
+ if (__i915_gem_request_completed(req, seqno))
return true;
/* Ensure our read of the seqno is coherent so that we
@@ -4033,7 +4043,7 @@ __i915_request_irq_complete(struct drm_i915_gem_request
*req)
wake_up_process(tsk);
rcu_read_unlock();
- if (__i915_gem_request_completed(req))
+ if (__i915_gem_request_completed(req, seqno))
return true;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2749c64a35a3..0e34d11bc5a2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -399,7 +399,7 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
i915_gem_request_retire_upto(rq);
- if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
+ if (rps && i915_gem_request_global_seqno(rq) ==
intel_engine_last_submit(rq->engine)) {
/* The GPU is now idle and this client has stalled.
* Since no other client has submitted a request in the
* meantime, assume that this client is the only one
@@ -2590,7 +2590,8 @@ static void i915_gem_context_mark_innocent(struct
i915_gem_context *ctx)
struct drm_i915_gem_request *
i915_gem_find_active_request(struct intel_engine_cs *engine)
{
- struct drm_i915_gem_request *request;
+ struct drm_i915_gem_request *request, *active = NULL;
+ unsigned long flags;
/* We are called by the error capture and reset at a random
* point in time. In particular, note that neither is crucially
@@ -2600,15 +2601,19 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
* extra delay for a recent interrupt is pointless. Hence, we do
* not need an engine->irq_seqno_barrier() before the seqno reads.
*/
+ spin_lock_irqsave(&engine->timeline->lock, flags);
list_for_each_entry(request, &engine->timeline->requests, link) {
- if (__i915_gem_request_completed(request))
+ if (__i915_gem_request_completed(request,
+request->global_seqno))
continue;
GEM_BUG_ON(request->engine != engine);
- return request;
+ active = request;
+ break;
}
+ spin_unlock_irqrestore(&engine->timeline->lock, flags);
[Intel-gfx] [PATCH 11/14] drm/i915: Replace reset_wait_queue with default_wake_function
If we change the wait_queue_t from using the autoremove_wake_function to
the default_wake_function, we no longer have to restore the wait_queue_t
entry on the wait_queue_head_t list after being woken up by it, as we
are unusual in sleeping multiple times on the same wait_queue_t.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 28 ++--
1 file changed, 6 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index f70a2c3d26cd..6cf1210984d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -938,16 +938,6 @@ void __i915_add_request(struct drm_i915_gem_request
*request, bool flush_caches)
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
}
-static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&q->lock, flags);
- if (list_empty(&wait->task_list))
- __add_wait_queue(q, wait);
- spin_unlock_irqrestore(&q->lock, flags);
-}
-
static unsigned long local_clock_us(unsigned int *cpu)
{
unsigned long t;
@@ -1042,8 +1032,8 @@ long i915_wait_request(struct drm_i915_gem_request *req,
const int state = flags & I915_WAIT_INTERRUPTIBLE ?
TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue;
- DEFINE_WAIT(reset);
- DEFINE_WAIT(exec);
+ DEFINE_WAIT_FUNC(reset, default_wake_function);
+ DEFINE_WAIT_FUNC(exec, default_wake_function);
struct intel_wait wait;
might_sleep();
@@ -1062,13 +1052,13 @@ long i915_wait_request(struct drm_i915_gem_request *req,
trace_i915_gem_request_wait_begin(req);
+ add_wait_queue(&req->execute, &exec);
if (flags & I915_WAIT_LOCKED)
add_wait_queue(errq, &reset);
wait.tsk = current;
restart:
- reset_wait_queue(&req->execute, &exec);
wait.seqno = i915_gem_request_global_seqno(req);
if (!wait.seqno) {
do {
@@ -1082,21 +1072,16 @@ long i915_wait_request(struct drm_i915_gem_request *req,
i915_reset_in_progress(&req->i915->gpu_error)) {
__set_current_state(TASK_RUNNING);
i915_reset(req->i915);
- reset_wait_queue(errq, &reset);
continue;
}
if (signal_pending_state(state, current)) {
timeout = -ERESTARTSYS;
- break;
+ goto complete;
}
timeout = io_schedule_timeout(timeout);
} while (timeout);
- finish_wait(&req->execute, &exec);
-
- if (timeout < 0)
- goto complete;
GEM_BUG_ON(!wait.seqno);
}
@@ -1156,7 +1141,6 @@ long i915_wait_request(struct drm_i915_gem_request *req,
i915_reset_in_progress(&req->i915->gpu_error)) {
__set_current_state(TASK_RUNNING);
i915_reset(req->i915);
- reset_wait_queue(errq, &reset);
continue;
}
@@ -1171,11 +1155,11 @@ long i915_wait_request(struct drm_i915_gem_request *req,
}
intel_engine_remove_wait(req->engine, &wait);
- __set_current_state(TASK_RUNNING);
-
complete:
+ __set_current_state(TASK_RUNNING);
if (flags & I915_WAIT_LOCKED)
remove_wait_queue(errq, &reset);
+ remove_wait_queue(&req->execute, &exec);
trace_i915_gem_request_wait_end(req);
return timeout;
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/14] drm/i915: Inline __i915_gem_request_wait_for_execute()
It had only one callsite and existed to keep the code clearer. Now
having shared the wait-on-error between phases and with plans to change
the wait-for-execute in the next few patches, remove the out of line
wait loop and move it into the main body of i915_wait_request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 68 -
1 file changed, 24 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 8d4f0c859fee..e4eeb5f5453c 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -988,49 +988,6 @@ bool __i915_spin_request(const struct drm_i915_gem_request
*req,
return false;
}
-static long
-__i915_request_wait_for_execute(struct drm_i915_gem_request *request,
- unsigned int flags,
- long timeout)
-{
- const int state = flags & I915_WAIT_INTERRUPTIBLE ?
- TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
- wait_queue_head_t *q = &request->i915->gpu_error.wait_queue;
- DEFINE_WAIT(reset);
- DEFINE_WAIT(wait);
-
- if (flags & I915_WAIT_LOCKED)
- add_wait_queue(q, &reset);
-
- do {
- prepare_to_wait(&request->execute.wait, &wait, state);
-
- if (i915_sw_fence_done(&request->execute))
- break;
-
- if (flags & I915_WAIT_LOCKED &&
- i915_reset_in_progress(&request->i915->gpu_error)) {
- __set_current_state(TASK_RUNNING);
- i915_reset(request->i915);
- reset_wait_queue(q, &reset);
- continue;
- }
-
- if (signal_pending_state(state, current)) {
- timeout = -ERESTARTSYS;
- break;
- }
-
- timeout = io_schedule_timeout(timeout);
- } while (timeout);
- finish_wait(&request->execute.wait, &wait);
-
- if (flags & I915_WAIT_LOCKED)
- remove_wait_queue(q, &reset);
-
- return timeout;
-}
-
/**
* i915_wait_request - wait until execution of request has finished
* @req: the request to wait upon
@@ -1080,7 +1037,30 @@ long i915_wait_request(struct drm_i915_gem_request *req,
add_wait_queue(errq, &reset);
if (!i915_sw_fence_done(&req->execute)) {
- timeout = __i915_request_wait_for_execute(req, flags, timeout);
+ DEFINE_WAIT(exec);
+
+ do {
+ prepare_to_wait(&req->execute.wait, &exec, state);
+ if (i915_sw_fence_done(&req->execute))
+ break;
+
+ if (flags & I915_WAIT_LOCKED &&
+ i915_reset_in_progress(&req->i915->gpu_error)) {
+ __set_current_state(TASK_RUNNING);
+ i915_reset(req->i915);
+ reset_wait_queue(errq, &reset);
+ continue;
+ }
+
+ if (signal_pending_state(state, current)) {
+ timeout = -ERESTARTSYS;
+ break;
+ }
+
+ timeout = io_schedule_timeout(timeout);
+ } while (timeout);
+ finish_wait(&req->execute.wait, &exec);
+
if (timeout < 0)
goto complete;
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/2] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees
On Thu, Feb 02, 2017 at 02:33:54PM +0100, Lucas Stach wrote: > Am Donnerstag, den 02.02.2017, 11:44 + schrieb Chris Wilson: > > @@ -192,6 +188,8 @@ static int etnaviv_iommu_find_iova(struct etnaviv_iommu > > *mmu, > > list_del_init(&m->scan_node); > > } > > > > + mode = DRM_MM_INSERT_EVICT; > > + > > /* > > * We removed enough mappings so that the new allocation will > > * succeed. Ensure that the MMU will be flushed before the > > This needs a rebase on the etnaviv for 4.11 pull, that removes the hack > mentioned in the comment above. Otherwise the code change looks fine. Is that pull request already on the list and/or in drm-next? Chris' patch fell a bit through the cracks, but since it's fairly big I'd like to get it into 4.11 still if possible, instead of keeping it in drm-misc for a few weeks to route around the merge window blackout ... Otherwise I guess 4.12 it is, but I'll still push it into drm-misc-next next week if possible (we have drm-misc-next-fixes for bugfixes for the merge window, to be able to keep merging feature work). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/19] drm/i915: Remove superfluous posting reads after clear GGTT
The barrier here is not required - we apply the barrier before the range is ever reused by the GPU instead. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 5964b83df4e2..04636760fb38 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2166,7 +2166,6 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm, I915_CACHE_LLC); for (i = 0; i < num_entries; i++) gen8_set_pte(>t_base[i], scratch_pte); - readl(gtt_base); } static void gen6_ggtt_clear_range(struct i915_address_space *vm, @@ -2191,7 +2190,6 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm, for (i = 0; i < num_entries; i++) iowrite32(scratch_pte, >t_base[i]); - readl(gtt_base); } static void i915_ggtt_insert_page(struct i915_address_space *vm, @@ -2215,7 +2213,6 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm, AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); - } static void i915_ggtt_clear_range(struct i915_address_space *vm, -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/19] drm/i915: Remove unused ppgtt->enable()
We never assign or use the ppgtt->enable() callback, so remove it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 5af5a5d53d93..caaa2c5c23be 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -382,7 +382,6 @@ struct i915_hw_ppgtt {
gen6_pte_t __iomem *pd_addr;
- int (*enable)(struct i915_hw_ppgtt *ppgtt);
int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req);
void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
--
2.11.0
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[Intel-gfx] [PATCH 18/19] drm/i915: Remove defunct GTT tracepoints
The tracepoints are now entirely synonymous with binding and unbinding the
VMA (and the tracepoints there).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 --
drivers/gpu/drm/i915/i915_trace.h | 97 -
2 files changed, 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0a28913b06af..46170b3acc2a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -190,7 +190,6 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
u32 pte_flags;
int ret;
- trace_i915_va_alloc(vma);
ret = vma->vm->allocate_va_range(vma->vm,
vma->node.start, vma->size);
if (ret)
@@ -1312,9 +1311,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.total = 1ULL << 32;
ppgtt->switch_mm = gen8_legacy_mm_switch;
- trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
- 0, 0,
- GEN8_PML4E_SHIFT);
if (intel_vgpu_active(dev_priv)) {
ret = gen8_preallocate_top_level_pdps(ppgtt);
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index de31c49781d3..7a547cdfc381 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -175,103 +175,6 @@ TRACE_EVENT(i915_vma_unbind,
__entry->obj, __entry->offset, __entry->size, __entry->vm)
);
-TRACE_EVENT(i915_va_alloc,
- TP_PROTO(struct i915_vma *vma),
- TP_ARGS(vma),
-
- TP_STRUCT__entry(
- __field(struct i915_address_space *, vm)
- __field(u64, start)
- __field(u64, end)
- ),
-
- TP_fast_assign(
- __entry->vm = vma->vm;
- __entry->start = vma->node.start;
- __entry->end = vma->node.start + vma->node.size - 1;
- ),
-
- TP_printk("vm=%p (%c), 0x%llx-0x%llx",
- __entry->vm, i915_is_ggtt(__entry->vm) ? 'G' : 'P',
__entry->start, __entry->end)
-);
-
-DECLARE_EVENT_CLASS(i915_px_entry,
- TP_PROTO(struct i915_address_space *vm, u32 px, u64 start, u64
px_shift),
- TP_ARGS(vm, px, start, px_shift),
-
- TP_STRUCT__entry(
- __field(struct i915_address_space *, vm)
- __field(u32, px)
- __field(u64, start)
- __field(u64, end)
- ),
-
- TP_fast_assign(
- __entry->vm = vm;
- __entry->px = px;
- __entry->start = start;
- __entry->end = ((start + (1ULL << px_shift)) & ~((1ULL <<
px_shift)-1)) - 1;
- ),
-
- TP_printk("vm=%p, pde=%d (0x%llx-0x%llx)",
- __entry->vm, __entry->px, __entry->start, __entry->end)
-);
-
-DEFINE_EVENT(i915_px_entry, i915_page_table_entry_alloc,
-TP_PROTO(struct i915_address_space *vm, u32 pde, u64 start, u64
pde_shift),
-TP_ARGS(vm, pde, start, pde_shift)
-);
-
-DEFINE_EVENT_PRINT(i915_px_entry, i915_page_directory_entry_alloc,
- TP_PROTO(struct i915_address_space *vm, u32 pdpe, u64 start,
u64 pdpe_shift),
- TP_ARGS(vm, pdpe, start, pdpe_shift),
-
- TP_printk("vm=%p, pdpe=%d (0x%llx-0x%llx)",
-__entry->vm, __entry->px, __entry->start,
__entry->end)
-);
-
-DEFINE_EVENT_PRINT(i915_px_entry, i915_page_directory_pointer_entry_alloc,
- TP_PROTO(struct i915_address_space *vm, u32 pml4e, u64
start, u64 pml4e_shift),
- TP_ARGS(vm, pml4e, start, pml4e_shift),
-
- TP_printk("vm=%p, pml4e=%d (0x%llx-0x%llx)",
-__entry->vm, __entry->px, __entry->start,
__entry->end)
-);
-
-/* Avoid extra math because we only support two sizes. The format is defined by
- * bitmap_scnprintf. Each 32 bits is 8 HEX digits followed by comma */
-#define TRACE_PT_SIZE(bits) \
- bits) == 1024) ? 288 : 144) + 1)
-
-DECLARE_EVENT_CLASS(i915_page_table_entry_update,
- TP_PROTO(struct i915_address_space *vm, u32 pde,
-struct i915_page_table *pt, u32 first, u32 count),
- TP_ARGS(vm, pde, pt, first, count),
-
- TP_STRUCT__entry(
- __field(struct i915_address_space *, vm)
- __field(u32, pde)
- __field(u32, first)
- __field(u32, last)
- ),
-
- TP_fast_assign(
- __entry->vm = vm;
- __entry->pde = pde;
- __entry->first = first;
- __entry->last = first + count - 1;
- ),
-
- TP_printk("vm=%p, pde=%d, updating %u:%u",
- __entry->vm, __entry->pde, __entry->last, __entry->first)
-);
-
-DEFINE_EVENT(i915_page_tab
[Intel-gfx] [PATCH 04/19] drm/i915: Don't special case teardown of aliasing_ppgtt
The aliasing_ppgtt is a regular ppgtt, and we can use the regular
i915_ppgtt_put() to properly tear it down.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 53 +++--
1 file changed, 15 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f503fc0d8530..921aa1e902b4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2225,23 +2225,6 @@ static void gtt_write_workarounds(struct
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3_LRA_1_GPGPU,
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
}
-static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
- struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv,
- const char *name)
-{
- int ret;
-
- ret = __hw_ppgtt_init(ppgtt, dev_priv);
- if (ret == 0) {
- kref_init(&ppgtt->ref);
- i915_address_space_init(&ppgtt->base, dev_priv, name);
- ppgtt->base.file = file_priv;
- }
-
- return ret;
-}
-
int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
{
gtt_write_workarounds(dev_priv);
@@ -2279,12 +2262,16 @@ i915_ppgtt_create(struct drm_i915_private *dev_priv,
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name);
+ ret = __hw_ppgtt_init(ppgtt, dev_priv);
if (ret) {
kfree(ppgtt);
return ERR_PTR(ret);
}
+ kref_init(&ppgtt->ref);
+ i915_address_space_init(&ppgtt->base, dev_priv, name);
+ ppgtt->base.file = fpriv;
+
trace_i915_ppgtt_create(&ppgtt->base);
return ppgtt;
@@ -2775,21 +2762,17 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
ggtt->base.total - PAGE_SIZE, PAGE_SIZE);
if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
- ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
- if (!ppgtt) {
- ret = -ENOMEM;
+ ppgtt = i915_ppgtt_create(dev_priv, NULL, "[alias]");
+ if (IS_ERR(ppgtt)) {
+ ret = PTR_ERR(ppgtt);
goto err;
}
- ret = __hw_ppgtt_init(ppgtt, dev_priv);
- if (ret)
- goto err_ppgtt;
-
if (ppgtt->base.allocate_va_range) {
ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
ppgtt->base.total);
if (ret)
- goto err_ppgtt_cleanup;
+ goto err_ppgtt;
}
ppgtt->base.clear_range(&ppgtt->base,
@@ -2803,10 +2786,8 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
return 0;
-err_ppgtt_cleanup:
- ppgtt->base.cleanup(&ppgtt->base);
err_ppgtt:
- kfree(ppgtt);
+ i915_ppgtt_put(ppgtt);
err:
drm_mm_remove_node(&ggtt->error_capture);
return ret;
@@ -2829,26 +2810,22 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
WARN_ON(i915_vma_unbind(vma));
mutex_unlock(&dev_priv->drm.struct_mutex);
- if (dev_priv->mm.aliasing_ppgtt) {
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
- ppgtt->base.cleanup(&ppgtt->base);
- kfree(ppgtt);
- }
-
i915_gem_cleanup_stolen(&dev_priv->drm);
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ if (dev_priv->mm.aliasing_ppgtt)
+ i915_ppgtt_put(dev_priv->mm.aliasing_ppgtt);
+
if (drm_mm_node_allocated(&ggtt->error_capture))
drm_mm_remove_node(&ggtt->error_capture);
if (drm_mm_initialized(&ggtt->base.mm)) {
intel_vgt_deballoon(dev_priv);
-
- mutex_lock(&dev_priv->drm.struct_mutex);
i915_address_space_fini(&ggtt->base);
- mutex_unlock(&dev_priv->drm.struct_mutex);
}
ggtt->base.cleanup(&ggtt->base);
+ mutex_unlock(&dev_priv->drm.struct_mutex);
arch_phys_wc_del(ggtt->mtrr);
io_mapping_fini(&ggtt->mappable);
--
2.11.0
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[Intel-gfx] [PATCH 17/19] drm/i915: Always mark the PDP as dirty when altered
We want to reload the PDP (and flush the TLB) when the addresses are
changed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 04636760fb38..0a28913b06af 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1076,7 +1076,6 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm,
struct i915_page_directory_pointer *pdp,
u64 start, u64 length)
{
- struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory *pd;
u64 from = start;
unsigned int pdpe;
@@ -1091,6 +1090,8 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm,
gen8_initialize_pd(vm, pd);
gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
pdp->used_pdpes++;
+
+ mark_tlbs_dirty(i915_vm_to_ppgtt(vm));
}
ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
@@ -1102,7 +1103,6 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm,
}
}
- mark_tlbs_dirty(ppgtt);
return 0;
unwind:
--
2.11.0
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[Intel-gfx] [PATCH 03/19] drm/i915: Micro-optimise gen8_ppgtt_insert_entries()
Improve the sg iteration and in hte process eliminate a bug in
miscomputing the pml4 length as orig_nents<
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 157 +++-
1 file changed, 82 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0d540c244e85..f503fc0d8530 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -745,9 +745,9 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
unsigned int num_entries = gen8_pte_count(start, length);
unsigned int pte = gen8_pte_index(start);
unsigned int pte_end = pte + num_entries;
- gen8_pte_t *pt_vaddr;
- gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
-I915_CACHE_LLC);
+ gen8_pte_t scratch_pte =
+ gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
+ gen8_pte_t *vaddr;
if (WARN_ON(!px_page(pt)))
return false;
@@ -759,12 +759,10 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
if (bitmap_empty(pt->used_ptes, GEN8_PTES))
return true;
- pt_vaddr = kmap_px(pt);
-
+ vaddr = kmap_px(pt);
while (pte < pte_end)
- pt_vaddr[pte++] = scratch_pte;
-
- kunmap_px(ppgtt, pt_vaddr);
+ vaddr[pte++] = scratch_pte;
+ kunmap_px(ppgtt, vaddr);
return false;
}
@@ -872,71 +870,93 @@ static void gen8_ppgtt_clear_range(struct
i915_address_space *vm,
gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length);
}
-static void
-gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
+struct sgt_dma {
+ struct scatterlist *sg;
+ dma_addr_t dma, max;
+};
+
+static __always_inline bool
+gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
struct i915_page_directory_pointer *pdp,
- struct sg_page_iter *sg_iter,
- uint64_t start,
+ struct sgt_dma *iter,
+ u64 start,
enum i915_cache_level cache_level)
{
- struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- gen8_pte_t *pt_vaddr;
- unsigned pdpe = gen8_pdpe_index(start);
- unsigned pde = gen8_pde_index(start);
- unsigned pte = gen8_pte_index(start);
+ unsigned int pdpe = gen8_pdpe_index(start);
+ unsigned int pde = gen8_pde_index(start);
+ unsigned int pte = gen8_pte_index(start);
+ struct i915_page_directory *pd;
+ const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
+ gen8_pte_t *vaddr;
+ bool ret = true;
- pt_vaddr = NULL;
+ pd = pdp->page_directory[pdpe];
+ vaddr = kmap_px(pd->page_table[pde]);
+ do {
+ vaddr[pte] = pte_encode | iter->dma;
+ iter->dma += PAGE_SIZE;
+ if (iter->dma >= iter->max) {
+ iter->sg = __sg_next(iter->sg);
+ if (!iter->sg) {
+ ret = false;
+ break;
+ }
- while (__sg_page_iter_next(sg_iter)) {
- if (pt_vaddr == NULL) {
- struct i915_page_directory *pd =
pdp->page_directory[pdpe];
- struct i915_page_table *pt = pd->page_table[pde];
- pt_vaddr = kmap_px(pt);
+ iter->dma = sg_dma_address(iter->sg);
+ iter->max = iter->dma + iter->sg->length;
}
- pt_vaddr[pte] =
- gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
- cache_level);
if (++pte == GEN8_PTES) {
- kunmap_px(ppgtt, pt_vaddr);
- pt_vaddr = NULL;
if (++pde == I915_PDES) {
- if (++pdpe == I915_PDPES_PER_PDP(vm->i915))
- break;
+ pd = pdp->page_directory[++pdpe];
pde = 0;
}
+
+ kunmap_px(ppgtt, vaddr);
+ vaddr = kmap_px(pd->page_table[pde]);
pte = 0;
}
- }
+ } while (1);
+ kunmap_px(ppgtt, vaddr);
- if (pt_vaddr)
- kunmap_px(ppgtt, pt_vaddr);
+ return ret;
}
-static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
- struct sg_table *pages,
- uint64_t start,
- enum i915_cache_level cache_level,
- u32 unused)
+static void gen8_ppgtt_insert
[Intel-gfx] [PATCH 12/19] drm/i915: Remove bitmap tracking for used-ptes
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 338
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +-
drivers/gpu/drm/i915/i915_trace.h | 19 +-
3 files changed, 121 insertions(+), 241 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 66c3540eb387..5ea46c05462b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -454,62 +454,38 @@ static void cleanup_scratch_page(struct
i915_address_space *vm)
static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
{
struct i915_page_table *pt;
- const size_t count = INTEL_GEN(vm->i915) >= 8 ? GEN8_PTES : GEN6_PTES;
- int ret = -ENOMEM;
- pt = kzalloc(sizeof(*pt), GFP_KERNEL);
- if (!pt)
+ pt = kmalloc(sizeof(*pt), GFP_KERNEL | __GFP_NOWARN);
+ if (unlikely(!pt))
return ERR_PTR(-ENOMEM);
- pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
- GFP_KERNEL);
-
- if (!pt->used_ptes)
- goto fail_bitmap;
-
- ret = setup_px(vm, pt);
- if (ret)
- goto fail_page_m;
+ if (unlikely(setup_px(vm, pt))) {
+ kfree(pt);
+ return ERR_PTR(-ENOMEM);
+ }
+ pt->used_ptes = 0;
return pt;
-
-fail_page_m:
- kfree(pt->used_ptes);
-fail_bitmap:
- kfree(pt);
-
- return ERR_PTR(ret);
}
static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
{
cleanup_px(vm, pt);
- kfree(pt->used_ptes);
kfree(pt);
}
static void gen8_initialize_pt(struct i915_address_space *vm,
struct i915_page_table *pt)
{
- gen8_pte_t scratch_pte;
-
- scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
- I915_CACHE_LLC);
-
- fill_px(vm, pt, scratch_pte);
+ fill_px(vm, pt,
+ gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC));
}
static void gen6_initialize_pt(struct i915_address_space *vm,
struct i915_page_table *pt)
{
- gen6_pte_t scratch_pte;
-
- WARN_ON(vm->scratch_page.daddr == 0);
-
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
-I915_CACHE_LLC, 0);
-
- fill32_px(vm, pt, scratch_pte);
+ fill32_px(vm, pt,
+ vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
}
static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
@@ -553,11 +529,12 @@ static void free_pd(struct i915_address_space *vm,
static void gen8_initialize_pd(struct i915_address_space *vm,
struct i915_page_directory *pd)
{
- gen8_pde_t scratch_pde;
-
- scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
+ unsigned int i;
- fill_px(vm, pd, scratch_pde);
+ fill_px(vm, pd,
+ gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC));
+ for (i = 0; i < I915_PDES; i++)
+ pd->page_table[i] = vm->scratch_pt;
}
static int __pdp_init(struct drm_i915_private *dev_priv,
@@ -742,8 +719,7 @@ static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
*/
static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
struct i915_page_table *pt,
- uint64_t start,
- uint64_t length)
+ u64 start, u64 length)
{
unsigned int num_entries = gen8_pte_count(start, length);
unsigned int pte = gen8_pte_index(start);
@@ -752,14 +728,10 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
gen8_pte_t *vaddr;
- if (WARN_ON(!px_page(pt)))
- return false;
-
- GEM_BUG_ON(pte_end > GEN8_PTES);
+ GEM_BUG_ON(num_entries > pt->used_ptes);
- bitmap_clear(pt->used_ptes, pte, num_entries);
-
- if (bitmap_empty(pt->used_ptes, GEN8_PTES))
+ pt->used_ptes -= num_entries;
+ if (!pt->used_ptes)
return true;
vaddr = kmap_atomic_px(pt);
@@ -770,31 +742,38 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
return false;
}
+static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
+ struct i915_page_directory *pd,
+ struct i915_page_table *pt,
+ unsigned int pde)
+{
+ gen8_pde_t *vaddr;
+
+ pd->page_table[pde
[Intel-gfx] [PATCH 14/19] drm/i915: Remove bitmap tracking for used-pdpes
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 275 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +-
2 files changed, 84 insertions(+), 194 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 15e95904931f..99319461f86c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -526,24 +526,13 @@ static void gen8_initialize_pd(struct i915_address_space
*vm,
static int __pdp_init(struct i915_address_space *vm,
struct i915_page_directory_pointer *pdp)
{
- size_t pdpes = I915_PDPES_PER_PDP(vm->i915);
- int i;
-
- pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
- sizeof(unsigned long),
- GFP_KERNEL);
- if (!pdp->used_pdpes)
- return -ENOMEM;
+ const unsigned int pdpes = I915_PDPES_PER_PDP(vm->i915);
+ unsigned int i;
pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory),
- GFP_KERNEL);
- if (!pdp->page_directory) {
- kfree(pdp->used_pdpes);
- /* the PDP might be the statically allocated top level. Keep it
-* as clean as possible */
- pdp->used_pdpes = NULL;
+ GFP_KERNEL | __GFP_NOWARN);
+ if (unlikely(!pdp->page_directory))
return -ENOMEM;
- }
for (i = 0; i < pdpes; i++)
pdp->page_directory[i] = vm->scratch_pd;
@@ -553,7 +542,6 @@ static int __pdp_init(struct i915_address_space *vm,
static void __pdp_fini(struct i915_page_directory_pointer *pdp)
{
- kfree(pdp->used_pdpes);
kfree(pdp->page_directory);
pdp->page_directory = NULL;
}
@@ -611,23 +599,12 @@ static void gen8_initialize_pdp(struct i915_address_space
*vm,
static void gen8_initialize_pml4(struct i915_address_space *vm,
struct i915_pml4 *pml4)
{
- gen8_ppgtt_pml4e_t scratch_pml4e;
-
- scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
- I915_CACHE_LLC);
-
- fill_px(vm, pml4, scratch_pml4e);
-}
-
-static void
-gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
-struct i915_page_directory_pointer *pdp,
-int index)
-{
- gen8_ppgtt_pml4e_t *pagemap = kmap_atomic_px(pml4);
+ unsigned int i;
- pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
- kunmap_atomic(pagemap);
+ fill_px(vm, pml4,
+ gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC));
+ for (i = 0; i < GEN8_PML4ES_PER_PML4; i++)
+ pml4->pdps[i] = vm->scratch_pdp;
}
/* Broadwell Page Directory Pointer Descriptors */
@@ -781,15 +758,12 @@ static bool gen8_ppgtt_clear_pdp(struct
i915_address_space *vm,
continue;
gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
- __clear_bit(pdpe, pdp->used_pdpes);
+ pdp->used_pdpes--;
free_pd(vm, pd);
}
- if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)))
- return true;
-
- return false;
+ return !pdp->used_pdpes;
}
static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm,
@@ -798,6 +772,19 @@ static void gen8_ppgtt_clear_3lvl(struct
i915_address_space *vm,
gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length);
}
+static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
+struct i915_page_directory_pointer *pdp,
+unsigned int pml4e)
+{
+ gen8_ppgtt_pml4e_t *vaddr;
+
+ pml4->pdps[pml4e] = pdp;
+
+ vaddr = kmap_atomic_px(pml4);
+ vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
+ kunmap_atomic(vaddr);
+}
+
/* Removes entries from a single pml4.
* This is the top-level structure in 4-level page tables used on gen8+.
* Empty entries are always scratch pml4e.
@@ -808,19 +795,18 @@ static void gen8_ppgtt_clear_4lvl(struct
i915_address_space *vm,
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_pml4 *pml4 = &ppgtt->pml4;
struct i915_page_directory_pointer *pdp;
- uint64_t pml4e;
+ unsigned int pml4e;
GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->i915));
gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
- if (WARN_ON(!pml4->pdps[pml4e]))
- break;
+ if (!gen8_ppgtt_clear_pdp(vm, pdp, star
[Intel-gfx] [PATCH 15/19] drm/i915: Remove bitmap tracking for used-pml4
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 132 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 -
2 files changed, 38 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 99319461f86c..5964b83df4e2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -804,7 +804,6 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space
*vm,
continue;
gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
- __clear_bit(pml4e, pml4->used_pml4es);
free_pdp(vm, pdp);
}
@@ -1018,8 +1017,8 @@ static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt)
{
int i;
- for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
- if (WARN_ON(!ppgtt->pml4.pdps[i]))
+ for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
+ if (ppgtt->pml4.pdps[i] == ppgtt->base.scratch_pdp)
continue;
gen8_ppgtt_cleanup_3lvl(&ppgtt->base, ppgtt->pml4.pdps[i]);
@@ -1073,53 +1072,9 @@ static int gen8_ppgtt_alloc_pd(struct i915_address_space
*vm,
return -ENOMEM;
}
-/**
- * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
- * @vm:Master vm structure.
- * @pml4: Page map level 4 for this address range.
- * @start: Starting virtual address to begin allocations.
- * @length:Size of the allocations.
- * @new_pdps: Bitmap set by function with new allocations. Likely used by the
- * caller to free on error.
- *
- * Allocate the required number of page directory pointers. Extremely similar
to
- * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pd().
- * The main difference is here we are limited by the pml4 boundary (instead of
- * the page directory pointer).
- *
- * Return: 0 if success; negative error code otherwise.
- */
-static int
-gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
- struct i915_pml4 *pml4,
- uint64_t start,
- uint64_t length)
-{
- struct i915_page_directory_pointer *pdp;
- uint32_t pml4e;
-
- gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
- if (!test_bit(pml4e, pml4->used_pml4es)) {
- pdp = alloc_pdp(vm);
- if (IS_ERR(pdp))
- return PTR_ERR(pdp);
-
- gen8_initialize_pdp(vm, pdp);
- pml4->pdps[pml4e] = pdp;
- trace_i915_page_directory_pointer_entry_alloc(vm,
- pml4e,
- start,
-
GEN8_PML4E_SHIFT);
- }
- }
-
- return 0;
-}
-
-static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
- struct i915_page_directory_pointer *pdp,
- uint64_t start,
- uint64_t length)
+static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm,
+ struct i915_page_directory_pointer *pdp,
+ u64 start, u64 length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory *pd;
@@ -1155,58 +1110,46 @@ static int gen8_alloc_va_range_3lvl(struct
i915_address_space *vm,
return -ENOMEM;
}
-static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
- struct i915_pml4 *pml4,
- uint64_t start,
- uint64_t length)
+static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm,
+u64 start, u64 length)
{
- DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
- struct i915_page_directory_pointer *pdp;
- uint64_t pml4e;
- int ret = 0;
-
- /* Do the pml4 allocations first, so we don't need to track the newly
-* allocated tables below the pdp */
- bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
+ return gen8_ppgtt_alloc_pdp(vm,
+ &i915_vm_to_ppgtt(vm)->pdp, start, length);
+}
- /* The pagedirectory and pagetable allocations are done in the shared 3
-* and 4 level code. Just allocate the pdps.
-*/
- ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, leng
[Intel-gfx] [PATCH 01/19] drm/i915: Micro-optimise i915_get_ggtt_vma_pages()
The predominant VMA class is normal GTT, so allow gcc to emphasize that
path and avoid unnecessary stack movement.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 61 +++--
1 file changed, 32 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ec360ab939b8..f8cef51cf24c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2615,14 +2615,16 @@ static int ggtt_bind_vma(struct i915_vma *vma,
{
struct drm_i915_private *i915 = vma->vm->i915;
struct drm_i915_gem_object *obj = vma->obj;
- u32 pte_flags = 0;
- int ret;
+ u32 pte_flags;
- ret = i915_get_ggtt_vma_pages(vma);
- if (ret)
- return ret;
+ if (unlikely(!vma->pages)) {
+ int ret = i915_get_ggtt_vma_pages(vma);
+ if (ret)
+ return ret;
+ }
/* Currently applicable only to VLV */
+ pte_flags = 0;
if (obj->gt_ro)
pte_flags |= PTE_READ_ONLY;
@@ -2647,18 +2649,18 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
{
struct drm_i915_private *i915 = vma->vm->i915;
u32 pte_flags;
- int ret;
- ret = i915_get_ggtt_vma_pages(vma);
- if (ret)
- return ret;
+ if (unlikely(!vma->pages)) {
+ int ret = i915_get_ggtt_vma_pages(vma);
+ if (ret)
+ return ret;
+ }
/* Currently applicable only to VLV */
pte_flags = 0;
if (vma->obj->gt_ro)
pte_flags |= PTE_READ_ONLY;
-
if (flags & I915_VMA_GLOBAL_BIND) {
intel_runtime_pm_get(i915);
vma->vm->insert_entries(vma->vm,
@@ -3397,9 +3399,9 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
return sg;
}
-static struct sg_table *
-intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info,
- struct drm_i915_gem_object *obj)
+static noinline struct sg_table *
+intel_rotate_pages(struct intel_rotation_info *rot_info,
+ struct drm_i915_gem_object *obj)
{
const size_t n_pages = obj->base.size / PAGE_SIZE;
unsigned int size = intel_rotation_info_size(rot_info);
@@ -3460,7 +3462,7 @@ intel_rotate_fb_obj_pages(const struct
intel_rotation_info *rot_info,
return ERR_PTR(ret);
}
-static struct sg_table *
+static noinline struct sg_table *
intel_partial_pages(const struct i915_ggtt_view *view,
struct drm_i915_gem_object *obj)
{
@@ -3514,7 +3516,7 @@ intel_partial_pages(const struct i915_ggtt_view *view,
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma)
{
- int ret = 0;
+ int ret;
/* The vma->pages are only valid within the lifespan of the borrowed
* obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
@@ -3523,32 +3525,33 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
*/
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
- if (vma->pages)
+ switch (vma->ggtt_view.type) {
+ case I915_GGTT_VIEW_NORMAL:
+ vma->pages = vma->obj->mm.pages;
return 0;
- if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
- vma->pages = vma->obj->mm.pages;
- else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
+ case I915_GGTT_VIEW_ROTATED:
vma->pages =
- intel_rotate_fb_obj_pages(&vma->ggtt_view.rotated,
- vma->obj);
- else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
+ intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
+ break;
+
+ case I915_GGTT_VIEW_PARTIAL:
vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
- else
+ break;
+
+ default:
WARN_ONCE(1, "GGTT view %u not implemented!\n",
vma->ggtt_view.type);
+ return -EINVAL;
+ }
- if (!vma->pages) {
- DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
- vma->ggtt_view.type);
- ret = -EINVAL;
- } else if (IS_ERR(vma->pages)) {
+ ret = 0;
+ if (unlikely(IS_ERR(vma->pages))) {
ret = PTR_ERR(vma->pages);
vma->pages = NULL;
DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
vma->ggtt_view.type, ret);
}
-
return ret;
}
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/19] drm/i915: Remove bitmap tracking for used-pdes
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 246
drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +-
2 files changed, 84 insertions(+), 168 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5ea46c05462b..15e95904931f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -491,39 +491,25 @@ static void gen6_initialize_pt(struct i915_address_space
*vm,
static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
{
struct i915_page_directory *pd;
- int ret = -ENOMEM;
- pd = kzalloc(sizeof(*pd), GFP_KERNEL);
- if (!pd)
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL | __GFP_NOWARN);
+ if (unlikely(!pd))
return ERR_PTR(-ENOMEM);
- pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
- sizeof(*pd->used_pdes), GFP_KERNEL);
- if (!pd->used_pdes)
- goto fail_bitmap;
-
- ret = setup_px(vm, pd);
- if (ret)
- goto fail_page_m;
+ if (unlikely(setup_px(vm, pd))) {
+ kfree(pd);
+ return ERR_PTR(-ENOMEM);
+ }
+ pd->used_pdes = 0;
return pd;
-
-fail_page_m:
- kfree(pd->used_pdes);
-fail_bitmap:
- kfree(pd);
-
- return ERR_PTR(ret);
}
static void free_pd(struct i915_address_space *vm,
struct i915_page_directory *pd)
{
- if (px_page(pd)) {
- cleanup_px(vm, pd);
- kfree(pd->used_pdes);
- kfree(pd);
- }
+ cleanup_px(vm, pd);
+ kfree(pd);
}
static void gen8_initialize_pd(struct i915_address_space *vm,
@@ -537,10 +523,11 @@ static void gen8_initialize_pd(struct i915_address_space
*vm,
pd->page_table[i] = vm->scratch_pt;
}
-static int __pdp_init(struct drm_i915_private *dev_priv,
+static int __pdp_init(struct i915_address_space *vm,
struct i915_page_directory_pointer *pdp)
{
- size_t pdpes = I915_PDPES_PER_PDP(dev_priv);
+ size_t pdpes = I915_PDPES_PER_PDP(vm->i915);
+ int i;
pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
sizeof(unsigned long),
@@ -548,8 +535,8 @@ static int __pdp_init(struct drm_i915_private *dev_priv,
if (!pdp->used_pdpes)
return -ENOMEM;
- pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
- GFP_KERNEL);
+ pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory),
+ GFP_KERNEL);
if (!pdp->page_directory) {
kfree(pdp->used_pdpes);
/* the PDP might be the statically allocated top level. Keep it
@@ -558,6 +545,9 @@ static int __pdp_init(struct drm_i915_private *dev_priv,
return -ENOMEM;
}
+ for (i = 0; i < pdpes; i++)
+ pdp->page_directory[i] = vm->scratch_pd;
+
return 0;
}
@@ -580,7 +570,7 @@ alloc_pdp(struct i915_address_space *vm)
if (!pdp)
return ERR_PTR(-ENOMEM);
- ret = __pdp_init(vm->i915, pdp);
+ ret = __pdp_init(vm, pdp);
if (ret)
goto fail_bitmap;
@@ -630,25 +620,9 @@ static void gen8_initialize_pml4(struct i915_address_space
*vm,
}
static void
-gen8_setup_pdpe(struct i915_hw_ppgtt *ppgtt,
- struct i915_page_directory_pointer *pdp,
- struct i915_page_directory *pd,
- int index)
-{
- gen8_ppgtt_pdpe_t *page_directorypo;
-
- if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev)))
- return;
-
- page_directorypo = kmap_atomic_px(pdp);
- page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
- kunmap_atomic(page_directorypo);
-}
-
-static void
-gen8_setup_pml4e(struct i915_pml4 *pml4,
-struct i915_page_directory_pointer *pdp,
-int index)
+gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
+struct i915_page_directory_pointer *pdp,
+int index)
{
gen8_ppgtt_pml4e_t *pagemap = kmap_atomic_px(pml4);
@@ -756,9 +730,6 @@ static void gen8_ppgtt_set_pde(struct i915_address_space
*vm,
kunmap_atomic(vaddr);
}
-/* Removes entries from a single page dir, releasing it if it's empty.
- * Caller can use the return value to update higher-level entries
- */
static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
u64 start, u64 length)
@@ -7
[Intel-gfx] [PATCH 10/19] drm/i915: Remove redundant clear of appgtt
Upon creation of the va range, it is initialised to point at scratch.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e777ef19893e..991a15efe478 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2152,7 +2152,6 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
-
gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
@@ -2774,10 +2773,6 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
goto err_ppgtt;
}
- ppgtt->base.clear_range(&ppgtt->base,
- ppgtt->base.start,
- ppgtt->base.total);
-
dev_priv->mm.aliasing_ppgtt = ppgtt;
WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
--
2.11.0
___
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[Intel-gfx] [PATCH 05/19] drm/i915: Split ggtt/alasing_gtt unbind_vma
Similar to how we already split the bind_vma for ggtt/aliasing_gtt, also
split up the unbind for symmetry.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 921aa1e902b4..45bab7b7b026 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2635,6 +2635,15 @@ static int ggtt_bind_vma(struct i915_vma *vma,
return 0;
}
+static void ggtt_unbind_vma(struct i915_vma *vma)
+{
+ struct drm_i915_private *i915 = vma->vm->i915;
+
+ intel_runtime_pm_get(i915);
+ vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
+ intel_runtime_pm_put(i915);
+}
+
static int aliasing_gtt_bind_vma(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 flags)
@@ -2671,22 +2680,21 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
return 0;
}
-static void ggtt_unbind_vma(struct i915_vma *vma)
+static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
{
struct drm_i915_private *i915 = vma->vm->i915;
- struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
- const u64 size = min(vma->size, vma->node.size);
if (vma->flags & I915_VMA_GLOBAL_BIND) {
intel_runtime_pm_get(i915);
- vma->vm->clear_range(vma->vm,
-vma->node.start, size);
+ vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
intel_runtime_pm_put(i915);
}
- if (vma->flags & I915_VMA_LOCAL_BIND && appgtt)
- appgtt->base.clear_range(&appgtt->base,
-vma->node.start, size);
+ if (vma->flags & I915_VMA_LOCAL_BIND) {
+ struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base;
+
+ vm->clear_range(vm, vma->node.start, vma->size);
+ }
}
void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
@@ -2780,8 +2788,12 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
ppgtt->base.total);
dev_priv->mm.aliasing_ppgtt = ppgtt;
+
WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
ggtt->base.bind_vma = aliasing_gtt_bind_vma;
+
+ WARN_ON(ggtt->base.unbind_vma != ggtt_unbind_vma);
+ ggtt->base.unbind_vma = aliasing_gtt_unbind_vma;
}
return 0;
--
2.11.0
___
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[Intel-gfx] [PATCH 09/19] drm/i915: Move allocate_va_range to GTT
In the future, we need to call allocate_va_range on the aliasing-ppgtt
which means moving the call down from the vma into the vm (which is
more appropriate for calling the vm function).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +-
drivers/gpu/drm/i915/i915_vma.c | 9 -
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9eaa396b7402..e777ef19893e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -187,11 +187,19 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 unused)
{
- u32 pte_flags = 0;
+ u32 pte_flags;
+ int ret;
+
+ trace_i915_va_alloc(vma);
+ ret = vma->vm->allocate_va_range(vma->vm,
+vma->node.start, vma->size);
+ if (ret)
+ return ret;
vma->pages = vma->obj->mm.pages;
/* Currently applicable only to VLV */
+ pte_flags = 0;
if (vma->obj->gt_ro)
pte_flags |= PTE_READ_ONLY;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 341c3f82ec1f..623e85d97db2 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -260,15 +260,6 @@ int i915_vma_bind(struct i915_vma *vma, enum
i915_cache_level cache_level,
vma->vm->total)))
return -ENODEV;
- if (vma_flags == 0 && vma->vm->allocate_va_range) {
- trace_i915_va_alloc(vma);
- ret = vma->vm->allocate_va_range(vma->vm,
-vma->node.start,
-vma->node.size);
- if (ret)
- return ret;
- }
-
trace_i915_vma_bind(vma, bind_flags);
ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
if (ret)
--
2.11.0
___
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[Intel-gfx] [PATCH 11/19] drm/i915: Tidy gen6_write_pde()
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 34 --
1 file changed, 12 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 991a15efe478..66c3540eb387 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1699,36 +1699,29 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt, struct seq_file *m)
}
/* Write pde (index) from the page directory @pd to the page table @pt */
-static void gen6_write_pde(struct i915_page_directory *pd,
- const int pde, struct i915_page_table *pt)
+static void gen6_write_pde(struct i915_hw_ppgtt *ppgtt,
+ const int pde, struct i915_page_table *pt)
{
/* Caller needs to make sure the write completes if necessary */
- struct i915_hw_ppgtt *ppgtt =
- container_of(pd, struct i915_hw_ppgtt, pd);
u32 pd_entry;
- pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
- pd_entry |= GEN6_PDE_VALID;
-
+ pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID;
writel(pd_entry, ppgtt->pd_addr + pde);
}
/* Write all the page tables found in the ppgtt structure to incrementing page
* directories. */
-static void gen6_write_page_range(struct drm_i915_private *dev_priv,
- struct i915_page_directory *pd,
+static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
uint32_t start, uint32_t length)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct i915_page_table *pt;
- uint32_t pde;
+ unsigned int pde;
- gen6_for_each_pde(pt, pd, start, length, pde)
- gen6_write_pde(pd, pde, pt);
+ gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde)
+ gen6_write_pde(ppgtt, pde, pt);
+ wmb();
- /* Make sure write is complete before other code can use this page
-* table. Also require for WC mapped PTEs */
- readl(ggtt->gsm);
+ mark_tlbs_dirty(ppgtt);
}
static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
@@ -1993,7 +1986,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
gen6_pte_count(start, length));
if (__test_and_clear_bit(pde, new_page_tables))
- gen6_write_pde(&ppgtt->pd, pde, pt);
+ gen6_write_pde(ppgtt, pde, pt);
trace_i915_page_table_entry_map(vm, pde, pt,
gen6_pte_index(start),
@@ -2152,7 +2145,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
- gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
+ gen6_write_page_range(ppgtt, 0, ppgtt->base.total);
DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
ppgtt->node.size >> 20,
@@ -3335,8 +3328,6 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
struct i915_address_space *vm;
list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
- /* TODO: Perhaps it shouldn't be gen6 specific */
-
struct i915_hw_ppgtt *ppgtt;
if (i915_is_ggtt(vm))
@@ -3344,8 +3335,7 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
else
ppgtt = i915_vm_to_ppgtt(vm);
- gen6_write_page_range(dev_priv, &ppgtt->pd,
- 0, ppgtt->base.total);
+ gen6_write_page_range(ppgtt, 0, ppgtt->base.total);
}
}
--
2.11.0
___
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[Intel-gfx] [PATCH 02/19] drm/i915: Micro-optimise gen6_ppgtt_insert_entries()
Inline the address computation to avoid the vfunc call for every page.
We still have to pay the high overhead of sg_page_iter_next(), but now
at least GCC can optimise the inner most loop, giving a significant
boost to some thrashing Unreal Engine workloads.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 68 ++---
1 file changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f8cef51cf24c..0d540c244e85 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1885,6 +1885,11 @@ static void gen6_ppgtt_clear_range(struct
i915_address_space *vm,
}
}
+struct sgt_dma {
+ struct scatterlist *sg;
+ dma_addr_t dma, max;
+};
+
static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
struct sg_table *pages,
uint64_t start,
@@ -1894,27 +1899,34 @@ static void gen6_ppgtt_insert_entries(struct
i915_address_space *vm,
unsigned first_entry = start >> PAGE_SHIFT;
unsigned act_pt = first_entry / GEN6_PTES;
unsigned act_pte = first_entry % GEN6_PTES;
- gen6_pte_t *pt_vaddr = NULL;
- struct sgt_iter sgt_iter;
- dma_addr_t addr;
+ const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
+ struct sgt_dma iter;
+ gen6_pte_t *vaddr;
+
+ vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
+ iter.sg = pages->sgl;
+ iter.dma = sg_dma_address(iter.sg);
+ iter.max = iter.dma + iter.sg->length;
+ do {
+ vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
- for_each_sgt_dma(addr, sgt_iter, pages) {
- if (pt_vaddr == NULL)
- pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
+ iter.dma += PAGE_SIZE;
+ if (iter.dma == iter.max) {
+ iter.sg = __sg_next(iter.sg);
+ if (!iter.sg)
+ break;
- pt_vaddr[act_pte] =
- vm->pte_encode(addr, cache_level, flags);
+ iter.dma = sg_dma_address(iter.sg);
+ iter.max = iter.dma + iter.sg->length;
+ }
if (++act_pte == GEN6_PTES) {
- kunmap_px(ppgtt, pt_vaddr);
- pt_vaddr = NULL;
- act_pt++;
+ kunmap_px(ppgtt, vaddr);
+ vaddr = kmap_px(ppgtt->pd.page_table[++act_pt]);
act_pte = 0;
}
- }
-
- if (pt_vaddr)
- kunmap_px(ppgtt, pt_vaddr);
+ } while (1);
+ kunmap_px(ppgtt, vaddr);
}
static int gen6_alloc_va_range(struct i915_address_space *vm,
@@ -2496,27 +2508,13 @@ static void gen6_ggtt_insert_entries(struct
i915_address_space *vm,
enum i915_cache_level level, u32 flags)
{
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
- struct sgt_iter sgt_iter;
- gen6_pte_t __iomem *gtt_entries;
- gen6_pte_t gtt_entry;
+ gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
+ unsigned int i = start >> PAGE_SHIFT;
+ struct sgt_iter iter;
dma_addr_t addr;
- int i = 0;
-
- gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
-
- for_each_sgt_dma(addr, sgt_iter, st) {
- gtt_entry = vm->pte_encode(addr, level, flags);
- iowrite32(gtt_entry, >t_entries[i++]);
- }
-
- /* XXX: This serves as a posting read to make sure that the PTE has
-* actually been updated. There is some concern that even though
-* registers and PTEs are within the same BAR that they are potentially
-* of NUMA access patterns. Therefore, even with the way we assume
-* hardware should work, we must keep this posting read for paranoia.
-*/
- if (i != 0)
- WARN_ON(readl(>t_entries[i-1]) != gtt_entry);
+ for_each_sgt_dma(addr, iter, st)
+ iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]);
+ wmb();
/* This next bit makes the above posting read even more important. We
* want to flush the TLBs only after we're certain all the PTE updates
--
2.11.0
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[Intel-gfx] [PATCH 07/19] drm/i915: Remove kmap/kunmap wrappers
As these are now both plain and simple kmap_atomic/kunmap_atomic pairs,
we can remove the wrappers for a small gain of clarity (in particular,
not hiding the atomic critical sections!).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 69 ++---
1 file changed, 26 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 302aee193ce5..2428a5fe532e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -405,21 +405,7 @@ static void cleanup_page_dma(struct i915_address_space *vm,
vm_free_page(vm, p->page);
}
-static void *kmap_page_dma(struct i915_page_dma *p)
-{
- return kmap_atomic(p->page);
-}
-
-/* We use the flushing unmap only with ppgtt structures:
- * page directories, page tables and scratch pages.
- */
-static void kunmap_page_dma(void *vaddr)
-{
- kunmap_atomic(vaddr);
-}
-
-#define kmap_px(px) kmap_page_dma(px_base(px))
-#define kunmap_px(vaddr) kunmap_page_dma((vaddr))
+#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
#define setup_px(vm, px) setup_page_dma((vm), px_base(px))
#define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
@@ -430,13 +416,13 @@ static void fill_page_dma(struct i915_address_space *vm,
struct i915_page_dma *p,
const u64 val)
{
- u64 * const vaddr = kmap_page_dma(p);
+ u64 * const vaddr = kmap_atomic(p->page);
int i;
for (i = 0; i < 512; i++)
vaddr[i] = val;
- kunmap_page_dma(vaddr);
+ kunmap_atomic(vaddr);
}
static void fill_page_dma_32(struct i915_address_space *vm,
@@ -669,9 +655,9 @@ gen8_setup_pdpe(struct i915_hw_ppgtt *ppgtt,
if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev)))
return;
- page_directorypo = kmap_px(pdp);
+ page_directorypo = kmap_atomic_px(pdp);
page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
- kunmap_px(page_directorypo);
+ kunmap_atomic(page_directorypo);
}
static void
@@ -679,10 +665,10 @@ gen8_setup_pml4e(struct i915_pml4 *pml4,
struct i915_page_directory_pointer *pdp,
int index)
{
- gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
+ gen8_ppgtt_pml4e_t *pagemap = kmap_atomic_px(pml4);
pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
- kunmap_px(pagemap);
+ kunmap_atomic(pagemap);
}
/* Broadwell Page Directory Pointer Descriptors */
@@ -768,10 +754,10 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
if (bitmap_empty(pt->used_ptes, GEN8_PTES))
return true;
- vaddr = kmap_px(pt);
+ vaddr = kmap_atomic_px(pt);
while (pte < pte_end)
vaddr[pte++] = scratch_pte;
- kunmap_px(vaddr);
+ kunmap_atomic(vaddr);
return false;
}
@@ -796,9 +782,9 @@ static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm,
if (gen8_ppgtt_clear_pt(vm, pt, start, length)) {
__clear_bit(pde, pd->used_pdes);
- pde_vaddr = kmap_px(pd);
+ pde_vaddr = kmap_atomic_px(pd);
pde_vaddr[pde] = scratch_pde;
- kunmap_px(pde_vaddr);
+ kunmap_atomic(pde_vaddr);
free_pt(vm, pt);
}
}
@@ -898,7 +884,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
bool ret = true;
pd = pdp->page_directory[pdpe];
- vaddr = kmap_px(pd->page_table[pde]);
+ vaddr = kmap_atomic_px(pd->page_table[pde]);
do {
vaddr[pte] = pte_encode | iter->dma;
iter->dma += PAGE_SIZE;
@@ -919,12 +905,12 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
pde = 0;
}
- kunmap_px(vaddr);
- vaddr = kmap_px(pd->page_table[pde]);
+ kunmap_atomic(vaddr);
+ vaddr = kmap_atomic_px(pd->page_table[pde]);
pte = 0;
}
} while (1);
- kunmap_px(vaddr);
+ kunmap_atomic(vaddr);
return ret;
}
@@ -1357,7 +1343,7 @@ static int gen8_alloc_va_range_3lvl(struct
i915_address_space *vm,
/* Allocations have completed successfully, so set the bitmaps, and do
* the mappings. */
gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
- gen8_pde_t *const page_directory = kmap_px(pd);
+ gen8_pde_t *const page_directory = kmap_atomic_px(pd);
struct i915_page_table *pt;
uint64_t pd_len = length;
uint64_t pd_start = start;
@@ -1392,7 +1378,7 @@ static int gen8_alloc_va_range_3lvl(str
[Intel-gfx] [PATCH 06/19] drm/i915: Convert clflushed pagetables over to WC maps
We flush the entire page every time we update a few bytes, making the
update of a page table many, many times slower than is required. If we
create a WC map of the page for our updates, we can avoid the clflush
but incur additional cost for creating the pagetable. We amoritize that
cost by reusing page vmappings, and only changing the page protection in
batches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 329 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +
2 files changed, 172 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 45bab7b7b026..302aee193ce5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -340,43 +340,69 @@ static gen6_pte_t iris_pte_encode(dma_addr_t addr,
return pte;
}
-static int __setup_page_dma(struct drm_i915_private *dev_priv,
- struct i915_page_dma *p, gfp_t flags)
+static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
{
- struct device *kdev = &dev_priv->drm.pdev->dev;
+ struct page *page;
- p->page = alloc_page(flags);
- if (!p->page)
- return -ENOMEM;
+ if (vm->free_pages.nr)
+ return vm->free_pages.pages[--vm->free_pages.nr];
- p->daddr = dma_map_page(kdev,
- p->page, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ page = alloc_page(gfp);
+ if (!page)
+ return NULL;
- if (dma_mapping_error(kdev, p->daddr)) {
- __free_page(p->page);
- return -EINVAL;
+ if (vm->pt_kmap_wc)
+ set_pages_array_wc(&page, 1);
+
+ return page;
+}
+
+static void vm_free_pages_release(struct i915_address_space *vm)
+{
+ GEM_BUG_ON(!pagevec_count(&vm->free_pages));
+
+ if (vm->pt_kmap_wc)
+ set_pages_array_wb(vm->free_pages.pages,
+ pagevec_count(&vm->free_pages));
+
+ __pagevec_release(&vm->free_pages);
+}
+
+static void vm_free_page(struct i915_address_space *vm, struct page *page)
+{
+ if (!pagevec_add(&vm->free_pages, page))
+ vm_free_pages_release(vm);
+}
+
+static int __setup_page_dma(struct i915_address_space *vm,
+ struct i915_page_dma *p,
+ gfp_t gfp)
+{
+ p->page = vm_alloc_page(vm, gfp | __GFP_NOWARN | __GFP_NORETRY);
+ if (unlikely(!p->page))
+ return -ENOMEM;
+
+ p->daddr = dma_map_page(vm->dma, p->page, 0, PAGE_SIZE,
+ PCI_DMA_BIDIRECTIONAL);
+ if (unlikely(dma_mapping_error(vm->dma, p->daddr))) {
+ vm_free_page(vm, p->page);
+ return -ENOMEM;
}
return 0;
}
-static int setup_page_dma(struct drm_i915_private *dev_priv,
+static int setup_page_dma(struct i915_address_space *vm,
struct i915_page_dma *p)
{
- return __setup_page_dma(dev_priv, p, I915_GFP_DMA);
+ return __setup_page_dma(vm, p, I915_GFP_DMA);
}
-static void cleanup_page_dma(struct drm_i915_private *dev_priv,
+static void cleanup_page_dma(struct i915_address_space *vm,
struct i915_page_dma *p)
{
- struct pci_dev *pdev = dev_priv->drm.pdev;
-
- if (WARN_ON(!p->page))
- return;
-
- dma_unmap_page(&pdev->dev, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- __free_page(p->page);
- memset(p, 0, sizeof(*p));
+ dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ vm_free_page(vm, p->page);
}
static void *kmap_page_dma(struct i915_page_dma *p)
@@ -387,67 +413,54 @@ static void *kmap_page_dma(struct i915_page_dma *p)
/* We use the flushing unmap only with ppgtt structures:
* page directories, page tables and scratch pages.
*/
-static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
+static void kunmap_page_dma(void *vaddr)
{
- /* There are only few exceptions for gen >=6. chv and bxt.
-* And we are not sure about the latter so play safe for now.
-*/
- if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
- drm_clflush_virt_range(vaddr, PAGE_SIZE);
-
kunmap_atomic(vaddr);
}
#define kmap_px(px) kmap_page_dma(px_base(px))
-#define kunmap_px(ppgtt, vaddr) \
- kunmap_page_dma((ppgtt)->base.i915, (vaddr))
+#define kunmap_px(vaddr) kunmap_page_dma((vaddr))
-#define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px))
-#define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px))
-#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
-#define fill32_px(dev_priv, px, v) \
- fill_page_dma_32((dev_priv), px_base(px), (v))
+#define setup_px(vm, px) setup_page_dma((vm), px_base(px))
+#define clean
[Intel-gfx] [PATCH 08/19] drm/i915: Remove user-triggerable WARN for large objects
Very large objects are expected, so don't WARN the user if they are
using them!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2428a5fe532e..9eaa396b7402 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1426,10 +1426,6 @@ static int gen8_alloc_va_range_4lvl(struct
i915_address_space *vm,
if (ret)
return ret;
- WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
-"The allocation has spanned more than 512GB. "
-"It is highly likely this is incorrect.");
-
gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
WARN_ON(!pdp);
--
2.11.0
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[Intel-gfx] [PATCH] drm/i915: remove 512GB allocation warning
Now that we have selftests in place exercising truly huge allocations
we will start to hit the 512GB warning, so now seems like a good time to
remove it.
Cc: Joonas Lahtinen
Cc: Chris Wilson
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 048040efc3f0..c567b34800cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1423,10 +1423,6 @@ static int gen8_alloc_va_range_4lvl(struct
i915_address_space *vm,
if (ret)
return ret;
- WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
-"The allocation has spanned more than 512GB. "
-"It is highly likely this is incorrect.");
-
gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
WARN_ON(!pdp);
--
2.7.4
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Re: [Intel-gfx] [PATCH v4 1/2] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees
On Thu, Feb 2, 2017 at 6:44 AM, Chris Wilson wrote:
> The drm_mm range manager claimed to support top-down insertion, but it
> was neither searching for the top-most hole that could fit the
> allocation request nor fitting the request to the hole correctly.
>
> In order to search the range efficiently, we create a secondary index
> for the holes using either their size or their address. This index
> allows us to find the smallest hole or the hole at the bottom or top of
> the range efficiently, whilst keeping the hole stack to rapidly service
> evictions.
>
> v2: Search for holes both high and low. Rename flags to mode.
> v3: Discover rb_entry_safe() and use it!
> v4: Kerneldoc for enum drm_mm_insert_mode.
>
I haven't had drm_mm.c paged into my head in a while, but the patch
appears to do the right thing. The series is:
Reviewed-by: Alex Deucher
> Signed-off-by: Chris Wilson
> Reviewed-by: Joonas Lahtinen
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Russell King
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Cc: Sean Paul
> Cc: Lucas Stach
> Cc: Christian Gmeiner
> Cc: Rob Clark
> Cc: Thierry Reding
> Cc: Stephen Warren
> Cc: Alexandre Courbot
> Cc: Eric Anholt
> Cc: Sinclair Yeh
> Cc: Thomas Hellstrom
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 20 +-
> drivers/gpu/drm/armada/armada_gem.c | 4 +-
> drivers/gpu/drm/drm_mm.c | 488
> +++
> drivers/gpu/drm/drm_vma_manager.c| 3 +-
> drivers/gpu/drm/etnaviv/etnaviv_mmu.c| 16 +-
> drivers/gpu/drm/i915/i915_gem.c | 10 +-
> drivers/gpu/drm/i915/i915_gem_evict.c| 9 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +--
> drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +-
> drivers/gpu/drm/msm/msm_gem.c| 3 +-
> drivers/gpu/drm/msm/msm_gem_vma.c| 3 +-
> drivers/gpu/drm/selftests/test-drm_mm.c | 58 ++--
> drivers/gpu/drm/sis/sis_mm.c | 6 +-
> drivers/gpu/drm/tegra/gem.c | 4 +-
> drivers/gpu/drm/ttm/ttm_bo_manager.c | 18 +-
> drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
> drivers/gpu/drm/vc4/vc4_hvs.c| 3 +-
> drivers/gpu/drm/vc4/vc4_plane.c | 6 +-
> drivers/gpu/drm/via/via_mm.c | 4 +-
> drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c | 10 +-
> include/drm/drm_mm.h | 184 +-
> 23 files changed, 470 insertions(+), 447 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index e4eb6dd3798a..0335c2f331e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -97,8 +97,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
> {
> struct amdgpu_gtt_mgr *mgr = man->priv;
> struct drm_mm_node *node = mem->mm_node;
> - enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST;
> - enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT;
> + enum drm_mm_insert_mode mode;
> unsigned long fpfn, lpfn;
> int r;
>
> @@ -115,15 +114,14 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager
> *man,
> else
> lpfn = man->size;
>
> - if (place && place->flags & TTM_PL_FLAG_TOPDOWN) {
> - sflags = DRM_MM_SEARCH_BELOW;
> - aflags = DRM_MM_CREATE_TOP;
> - }
> + mode = DRM_MM_INSERT_BEST;
> + if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
> + mode = DRM_MM_INSERT_HIGH;
>
> spin_lock(&mgr->lock);
> - r = drm_mm_insert_node_in_range_generic(&mgr->mm, node,
> mem->num_pages,
> - mem->page_alignment, 0,
> - fpfn, lpfn, sflags, aflags);
> + r = drm_mm_insert_node_in_range(&mgr->mm, node,
> + mem->num_pages, mem->page_alignment,
> 0,
> + fpfn, lpfn, mode);
> spin_unlock(&mgr->lock);
>
> if (!r) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> index ac9007986c11..9e577e3d3147 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> @@ -97,8 +97,7 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager
> *man,
> struct amdgpu_vram_mgr *mgr = man->priv;
> struct drm_mm *mm = &mgr->mm;
> struct drm_mm_node *nodes;
> - enum drm_mm_search_flags sflags = DRM_MM_SEARCH_DEFAULT;
> - enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT;
> + enum drm_mm_insert_mode mode;
> unsigned long
Re: [Intel-gfx] [PATCH] drm/i915: don't warn about Skylake CPU - KabyPoint PCH combo
On Wed, 01 Feb 2017, "Vivi, Rodrigo" wrote:
> Reviewed-by: Rodrigo Vivi
Pushed to drm-intel-next-queued, thanks for the review.
BR,
Jani.
>
>> On Feb 1, 2017, at 5:46 AM, Nikula, Jani wrote:
>>
>> Apparently there are machines out there with Skylake CPU and KabyPoint
>> PCH. Judging from our driver code, there doesn't seem to be any code
>> paths that would do anything different between SunrisePoint and
>> KabyPoint PCHs, so it would seem okay to accept the combo without
>> warnings.
>>
>> Fixes: 22dea0be50b2 ("drm/i915: Introduce Kabypoint PCH for Kabylake H/DT.")
>> References:
>> https://lists.freedesktop.org/archives/intel-gfx/2017-February/118611.html
>> Reported-by: Rainer Koenig
>> Cc: Rainer Koenig
>> Cc: Rodrigo Vivi
>> Cc: # v4.8+
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 267d5f8c49e1..6a430648fa71 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -213,7 +213,8 @@ static void intel_detect_pch(struct drm_i915_private
>> *dev_priv)
>>} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
>>dev_priv->pch_type = PCH_KBP;
>>DRM_DEBUG_KMS("Found KabyPoint PCH\n");
>> -WARN_ON(!IS_KABYLAKE(dev_priv));
>> +WARN_ON(!IS_SKYLAKE(dev_priv) &&
>> +!IS_KABYLAKE(dev_priv));
>>} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
>> (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
>> ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
>> --
>> 2.1.4
>>
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v4,1/2] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees
== Series Details == Series: series starting with [v4,1/2] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees URL : https://patchwork.freedesktop.org/series/18987/ State : failure == Summary == Series 18987v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/18987/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: pass -> INCOMPLETE (fi-skl-6260u) fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21 fi-skl-6260u total:206 pass:195 dwarn:0 dfail:0 fail:0 skip:10 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 f9c08830c03caa5bc556eb7bb0e42dfd55d229cf drm-tip: 2017y-02m-02d-12h-26m-40s UTC integration manifest 1f32470 drm: kselftest for drm_mm and bottom-up allocation ecb28be drm: Improve drm_mm search (and fix topdown allocation) with rbtrees == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3676/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt] intel-ci: Add all driver selftests to BAT
Op 02-02-17 om 14:44 schreef Chris Wilson: > On Thu, Feb 02, 2017 at 02:30:19PM +0100, Maarten Lankhorst wrote: >> Op 02-02-17 om 10:18 schreef Chris Wilson: >>> These are meant to be fast and sensitive to new (and old) bugs... >>> >>> Signed-off-by: Chris Wilson >>> Cc: Petri Latvala >>> --- >>> tests/intel-ci/fast-feedback.testlist | 19 +++ >>> 1 file changed, 19 insertions(+) >>> >>> diff --git a/tests/intel-ci/fast-feedback.testlist >>> b/tests/intel-ci/fast-feedback.testlist >>> index 828bd3ff..a0c3f848 100644 >>> --- a/tests/intel-ci/fast-feedback.testlist >>> +++ b/tests/intel-ci/fast-feedback.testlist >>> @@ -249,4 +249,23 @@ igt@drv_module_reload@basic-reload >>> igt@drv_module_reload@basic-no-display >>> igt@drv_module_reload@basic-reload-inject >>> igt@drv_module_reload@basic-reload-final >>> +igt@drv_selftest@mock_sanitycheck >>> +igt@drv_selftest@mock_scatterlist >>> +igt@drv_selftest@mock_uncore >>> +igt@drv_selftest@mock_breadcrumbs >>> +igt@drv_selftest@mock_requests >>> +igt@drv_selftest@mock_objects >>> +igt@drv_selftest@mock_dmabuf >>> +igt@drv_selftest@mock_vma >>> +igt@drv_selftest@mock_evict >>> +igt@drv_selftest@mock_gtt >>> +igt@drv_selftest@live_sanitycheck >>> +igt@drv_selftest@live_uncore >>> +igt@drv_selftest@live_requests >>> +igt@drv_selftest@live_object >>> +igt@drv_selftest@live_dmabuf >>> +igt@drv_selftest@live_coherency >>> +igt@drv_selftest@live_gtt >>> +igt@drv_selftest@live_context >>> +igt@drv_selftest@live_hangcheck >>> igt@gvt_basic@invalid-placeholder-test >> Add basic somewhere in the test names? > Why? Does something still parse basic in the test name and add it to a > test set? Shouldn't that now be pulling from these lists instead? the fast feedback list is a subtest of all basic tests. scripts/run-tests.sh -t basic is supposed to run at least those. ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/scheduler: emulate a scheduler for guc (rev4)
== Series Details == Series: drm/i915/scheduler: emulate a scheduler for guc (rev4) URL : https://patchwork.freedesktop.org/series/18909/ State : success == Summary == Series 18909v4 drm/i915/scheduler: emulate a scheduler for guc https://patchwork.freedesktop.org/api/1.0/series/18909/revisions/4/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 f9c08830c03caa5bc556eb7bb0e42dfd55d229cf drm-tip: 2017y-02m-02d-12h-26m-40s UTC integration manifest 1df3b1f9 drm/i915/scheduler: emulate a scheduler for guc == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3675/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt] intel-ci: Add all driver selftests to BAT
On Thu, Feb 02, 2017 at 02:30:19PM +0100, Maarten Lankhorst wrote: > Op 02-02-17 om 10:18 schreef Chris Wilson: > > These are meant to be fast and sensitive to new (and old) bugs... > > > > Signed-off-by: Chris Wilson > > Cc: Petri Latvala > > --- > > tests/intel-ci/fast-feedback.testlist | 19 +++ > > 1 file changed, 19 insertions(+) > > > > diff --git a/tests/intel-ci/fast-feedback.testlist > > b/tests/intel-ci/fast-feedback.testlist > > index 828bd3ff..a0c3f848 100644 > > --- a/tests/intel-ci/fast-feedback.testlist > > +++ b/tests/intel-ci/fast-feedback.testlist > > @@ -249,4 +249,23 @@ igt@drv_module_reload@basic-reload > > igt@drv_module_reload@basic-no-display > > igt@drv_module_reload@basic-reload-inject > > igt@drv_module_reload@basic-reload-final > > +igt@drv_selftest@mock_sanitycheck > > +igt@drv_selftest@mock_scatterlist > > +igt@drv_selftest@mock_uncore > > +igt@drv_selftest@mock_breadcrumbs > > +igt@drv_selftest@mock_requests > > +igt@drv_selftest@mock_objects > > +igt@drv_selftest@mock_dmabuf > > +igt@drv_selftest@mock_vma > > +igt@drv_selftest@mock_evict > > +igt@drv_selftest@mock_gtt > > +igt@drv_selftest@live_sanitycheck > > +igt@drv_selftest@live_uncore > > +igt@drv_selftest@live_requests > > +igt@drv_selftest@live_object > > +igt@drv_selftest@live_dmabuf > > +igt@drv_selftest@live_coherency > > +igt@drv_selftest@live_gtt > > +igt@drv_selftest@live_context > > +igt@drv_selftest@live_hangcheck > > igt@gvt_basic@invalid-placeholder-test > > Add basic somewhere in the test names? Why? Does something still parse basic in the test name and add it to a test set? Shouldn't that now be pulling from these lists instead? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Add missing SKL ID
On Fri, Jan 27, 2017 at 09:54:01PM +0200, Jani Nikula wrote: > On Fri, 27 Jan 2017, "Vivi, Rodrigo" wrote: > > Reviewed-by: Rodrigo Vivi > > > > Jani this is a case for cc:stable? > > Yes, if we know old kernels can handle SRV GT3. > > BR, > Jani. I don't think this particular device is different from other GT3. -Michał > > > > On Fri, 2017-01-27 at 15:50 +0100, Michał Winiarski wrote: > >> Used by production device: > >> Intel(R) Iris(TM) Graphics P555 > >> > >> Cc: Mika Kuoppala > >> Cc: Rodrigo Vivi > >> Signed-off-by: Michał Winiarski > >> --- > >> include/drm/i915_pciids.h | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > >> index a1dd21d..466c715 100644 > >> --- a/include/drm/i915_pciids.h > >> +++ b/include/drm/i915_pciids.h > >> @@ -265,7 +265,8 @@ > >>INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ > >>INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ > >>INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ > >> - INTEL_VGA_DEVICE(0x192B, info) /* Halo GT3 */ \ > >> + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ > >> + INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ > >> > >> #define INTEL_SKL_GT4_IDS(info) \ > >>INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ > > > > -- > Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/9] drm/i915: Avoid div-by-zero when computing aux_stride w/o an aux plane
On Wed, Jan 04, 2017 at 08:42:27PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> To make life easier let's allow skl_plane_stride() to be called for the
> AUX surface even when there is no AUX surface. Avoids special cases in
> the callers.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4d514ca1da88..bc398743e941 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3261,7 +3261,12 @@ static void skl_detach_scalers(struct intel_crtc
> *intel_crtc)
> u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
>unsigned int rotation)
> {
> - u32 stride = intel_fb_pitch(fb, plane, rotation);
> + u32 stride;
> +
> + if (plane >= fb->format->num_planes)
> + return 0;
> +
> + stride = intel_fb_pitch(fb, plane, rotation);
>
> /*
>* The stride is either expressed as a multiple of 64 bytes chunks for
> --
> 2.10.2
>
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Re: [Intel-gfx] [PATCH v2 03/38] drm/i915: Add some selftests for sg_table manipulation
On Thu, Feb 02, 2017 at 12:41:42PM +, Tvrtko Ursulin wrote:
>
> On 01/02/2017 11:34, Chris Wilson wrote:
> >On Wed, Feb 01, 2017 at 11:17:39AM +, Tvrtko Ursulin wrote:
>
> >>>+
> >>>+ for (npages = npages_funcs; *npages; npages++) {
> >>>+ prandom_seed_state(&prng,
> >>>+ i915_selftest.random_seed);
> >>>+ if (!alloc_table(&pt, sz, sz, *npages, &prng))
> >>>+ return 0; /* out of memory, give up */
> >>
> >>You don't have skip status? Sounds not ideal to silently abort.
> >
> >It runs until we use all physical memory, if left to its own devices. It's
> >not a skip if we have already completed some tests. ENOMEM of the test
> >setup itself is not what I'm testing for here, the test is for the
> >iterators.
>
> But suppose you mess up the test so the starting condition asks for
> impossible amount of memory but the test claims it passed. I don't
> think that is a good behaviour.
Returing ENOMEM when the failure is intentional is not an option either.
diff --git a/drivers/gpu/drm/i915/selftests/scatterlist.c
b/drivers/gpu/drm/i915/selftests/scatterlist.c
index fa5bd09c863f..5eb732231749 100644
--- a/drivers/gpu/drm/i915/selftests/scatterlist.c
+++ b/drivers/gpu/drm/i915/selftests/scatterlist.c
@@ -245,6 +245,7 @@ static int igt_sg_alloc(void *ignored)
const unsigned long max_order = 20; /* approximating a 4GiB object */
struct rnd_state prng;
unsigned long prime;
+ int alloc_error = -ENOMEM;
for_each_prime_number(prime, max_order) {
unsigned long size = BIT(prime);
@@ -260,7 +261,7 @@ static int igt_sg_alloc(void *ignored)
prandom_seed_state(&prng,
i915_selftest.random_seed);
if (!alloc_table(&pt, sz, sz, *npages, &prng))
- return 0; /* out of memory, give up */
+ return alloc_error;
prandom_seed_state(&prng,
i915_selftest.random_seed);
@@ -270,6 +271,8 @@ static int igt_sg_alloc(void *ignored)
sg_free_table(&pt.st);
if (err)
return err;
+
+ alloc_error = 0;
}
}
}
-Chris
--
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Re: [Intel-gfx] [PATCH 3/9] drm/i915: Move nv12 chroma plane handling into intel_surf_alignment()
On Wed, Jan 04, 2017 at 08:42:26PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Let's try to keep the alignment requirements in one place, and so
> towards that end let's move the AUX_DIST alignment handling into
> intel_surf_alignment() alongside the main surface alignment stuff.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 +---
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index f0cb80aba89a..4d514ca1da88 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2163,6 +2163,10 @@ static unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
>
> + /* AUX_DIST needs only 4K alignment */
> + if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
> + return 4096;
> +
> switch (fb->modifier) {
> case DRM_FORMAT_MOD_NONE:
> return intel_linear_alignment(dev_priv);
> @@ -2452,13 +2456,7 @@ u32 intel_compute_tile_offset(int *x, int *y,
> const struct drm_framebuffer *fb = state->base.fb;
> unsigned int rotation = state->base.rotation;
> int pitch = intel_fb_pitch(fb, plane, rotation);
> - u32 alignment;
> -
> - /* AUX_DIST needs only 4K alignment */
> - if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
> - alignment = 4096;
> - else
> - alignment = intel_surf_alignment(fb, plane);
> + u32 alignment = intel_surf_alignment(fb, plane);
>
> return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
> rotation, alignment);
> --
> 2.10.2
>
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Re: [Intel-gfx] [PATCH v4 1/2] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees
Am Donnerstag, den 02.02.2017, 11:44 + schrieb Chris Wilson:
> The drm_mm range manager claimed to support top-down insertion, but it
> was neither searching for the top-most hole that could fit the
> allocation request nor fitting the request to the hole correctly.
>
> In order to search the range efficiently, we create a secondary index
> for the holes using either their size or their address. This index
> allows us to find the smallest hole or the hole at the bottom or top of
> the range efficiently, whilst keeping the hole stack to rapidly service
> evictions.
>
> v2: Search for holes both high and low. Rename flags to mode.
> v3: Discover rb_entry_safe() and use it!
> v4: Kerneldoc for enum drm_mm_insert_mode.
>
> Signed-off-by: Chris Wilson
> Reviewed-by: Joonas Lahtinen
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Russell King
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Cc: Sean Paul
> Cc: Lucas Stach
> Cc: Christian Gmeiner
> Cc: Rob Clark
> Cc: Thierry Reding
> Cc: Stephen Warren
> Cc: Alexandre Courbot
> Cc: Eric Anholt
> Cc: Sinclair Yeh
> Cc: Thomas Hellstrom
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 20 +-
> drivers/gpu/drm/armada/armada_gem.c | 4 +-
> drivers/gpu/drm/drm_mm.c | 488
> +++
> drivers/gpu/drm/drm_vma_manager.c| 3 +-
> drivers/gpu/drm/etnaviv/etnaviv_mmu.c| 16 +-
> drivers/gpu/drm/i915/i915_gem.c | 10 +-
> drivers/gpu/drm/i915/i915_gem_evict.c| 9 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +--
> drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +-
> drivers/gpu/drm/msm/msm_gem.c| 3 +-
> drivers/gpu/drm/msm/msm_gem_vma.c| 3 +-
> drivers/gpu/drm/selftests/test-drm_mm.c | 58 ++--
> drivers/gpu/drm/sis/sis_mm.c | 6 +-
> drivers/gpu/drm/tegra/gem.c | 4 +-
> drivers/gpu/drm/ttm/ttm_bo_manager.c | 18 +-
> drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
> drivers/gpu/drm/vc4/vc4_hvs.c| 3 +-
> drivers/gpu/drm/vc4/vc4_plane.c | 6 +-
> drivers/gpu/drm/via/via_mm.c | 4 +-
> drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c | 10 +-
> include/drm/drm_mm.h | 184 +-
> 23 files changed, 470 insertions(+), 447 deletions(-)
[...]
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
> b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
> index f503af462dad..004456534e48 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
> @@ -107,6 +107,7 @@ static int etnaviv_iommu_find_iova(struct etnaviv_iommu
> *mmu,
> struct drm_mm_node *node, size_t size)
> {
> struct etnaviv_vram_mapping *free = NULL;
> + enum drm_mm_insert_mode mode = DRM_MM_INSERT_LOW;
> int ret;
>
> lockdep_assert_held(&mmu->lock);
> @@ -117,15 +118,10 @@ static int etnaviv_iommu_find_iova(struct etnaviv_iommu
> *mmu,
> struct list_head list;
> bool found;
>
> - /*
> - * XXX: The DRM_MM_SEARCH_BELOW is really a hack to trick
> - * drm_mm into giving out a low IOVA after address space
> - * rollover. This needs a proper fix.
> - */
> ret = drm_mm_insert_node_in_range(&mmu->mm, node,
> - size, 0, mmu->last_iova, ~0UL,
> - mmu->last_iova ? DRM_MM_SEARCH_DEFAULT :
> DRM_MM_SEARCH_BELOW);
> -
> + size, 0, 0,
> + mmu->last_iova, U64_MAX,
> + mode);
> if (ret != -ENOSPC)
> break;
>
> @@ -140,7 +136,7 @@ static int etnaviv_iommu_find_iova(struct etnaviv_iommu
> *mmu,
> }
>
> /* Try to retire some entries */
> - drm_mm_scan_init(&scan, &mmu->mm, size, 0, 0, 0);
> + drm_mm_scan_init(&scan, &mmu->mm, size, 0, 0, mode);
>
> found = 0;
> INIT_LIST_HEAD(&list);
> @@ -192,6 +188,8 @@ static int etnaviv_iommu_find_iova(struct etnaviv_iommu
> *mmu,
> list_del_init(&m->scan_node);
> }
>
> + mode = DRM_MM_INSERT_EVICT;
> +
> /*
>* We removed enough mappings so that the new allocation will
>* succeed. Ensure that the MMU will be flushed before the
This needs a rebase on the etnaviv for 4.11 pull, that removes the hack
mentioned in the comment above. Otherwise the code change looks fine.
Regards,
Lucas
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Re: [Intel-gfx] [PATCH igt] intel-ci: Add all driver selftests to BAT
Op 02-02-17 om 10:18 schreef Chris Wilson: > These are meant to be fast and sensitive to new (and old) bugs... > > Signed-off-by: Chris Wilson > Cc: Petri Latvala > --- > tests/intel-ci/fast-feedback.testlist | 19 +++ > 1 file changed, 19 insertions(+) > > diff --git a/tests/intel-ci/fast-feedback.testlist > b/tests/intel-ci/fast-feedback.testlist > index 828bd3ff..a0c3f848 100644 > --- a/tests/intel-ci/fast-feedback.testlist > +++ b/tests/intel-ci/fast-feedback.testlist > @@ -249,4 +249,23 @@ igt@drv_module_reload@basic-reload > igt@drv_module_reload@basic-no-display > igt@drv_module_reload@basic-reload-inject > igt@drv_module_reload@basic-reload-final > +igt@drv_selftest@mock_sanitycheck > +igt@drv_selftest@mock_scatterlist > +igt@drv_selftest@mock_uncore > +igt@drv_selftest@mock_breadcrumbs > +igt@drv_selftest@mock_requests > +igt@drv_selftest@mock_objects > +igt@drv_selftest@mock_dmabuf > +igt@drv_selftest@mock_vma > +igt@drv_selftest@mock_evict > +igt@drv_selftest@mock_gtt > +igt@drv_selftest@live_sanitycheck > +igt@drv_selftest@live_uncore > +igt@drv_selftest@live_requests > +igt@drv_selftest@live_object > +igt@drv_selftest@live_dmabuf > +igt@drv_selftest@live_coherency > +igt@drv_selftest@live_gtt > +igt@drv_selftest@live_context > +igt@drv_selftest@live_hangcheck > igt@gvt_basic@invalid-placeholder-test Add basic somewhere in the test names? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/9] drm/i915: Plumb drm_framebuffer into more places
On Wed, Jan 04, 2017 at 08:42:25PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Now that framebuffers can be used even before calling
> drm_framebuffer_init() we can start to plumb them into more places,
> instead of passing individual pieces for fb metadata.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_display.c | 127
> +++
> drivers/gpu/drm/i915/intel_drv.h | 11 +--
> drivers/gpu/drm/i915/intel_fbdev.c | 4 +-
> 3 files changed, 57 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e2150a64860c..f0cb80aba89a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2050,10 +2050,13 @@ static unsigned int intel_tile_size(const struct
> drm_i915_private *dev_priv)
> return IS_GEN2(dev_priv) ? 2048 : 4096;
> }
>
> -static unsigned int intel_tile_width_bytes(const struct drm_i915_private
> *dev_priv,
> -uint64_t fb_modifier, unsigned int
> cpp)
> +static unsigned int
> +intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
> {
> - switch (fb_modifier) {
> + struct drm_i915_private *dev_priv = to_i915(fb->dev);
> + unsigned int cpp = fb->format->cpp[plane];
> +
> + switch (fb->modifier) {
> case DRM_FORMAT_MOD_NONE:
> return cpp;
> case I915_FORMAT_MOD_X_TILED:
> @@ -2082,41 +2085,38 @@ static unsigned int intel_tile_width_bytes(const
> struct drm_i915_private *dev_pr
> }
> break;
> default:
> - MISSING_CASE(fb_modifier);
> + MISSING_CASE(fb->modifier);
> return cpp;
> }
> }
>
> -unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
> -uint64_t fb_modifier, unsigned int cpp)
> +static unsigned int
> +intel_tile_height(const struct drm_framebuffer *fb, int plane)
> {
> - if (fb_modifier == DRM_FORMAT_MOD_NONE)
> + if (fb->modifier == DRM_FORMAT_MOD_NONE)
> return 1;
> else
> - return intel_tile_size(dev_priv) /
> - intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
> + return intel_tile_size(to_i915(fb->dev)) /
> + intel_tile_width_bytes(fb, plane);
> }
>
> /* Return the tile dimensions in pixel units */
> -static void intel_tile_dims(const struct drm_i915_private *dev_priv,
> +static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
> unsigned int *tile_width,
> - unsigned int *tile_height,
> - uint64_t fb_modifier,
> - unsigned int cpp)
> + unsigned int *tile_height)
> {
> - unsigned int tile_width_bytes =
> - intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
> + unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
> + unsigned int cpp = fb->format->cpp[plane];
>
> *tile_width = tile_width_bytes / cpp;
> - *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
> + *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
> }
>
> unsigned int
> -intel_fb_align_height(struct drm_device *dev, unsigned int height,
> - uint32_t pixel_format, uint64_t fb_modifier)
> +intel_fb_align_height(const struct drm_framebuffer *fb,
> + int plane, unsigned int height)
> {
> - unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
> - unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier,
> cpp);
> + unsigned int tile_height = intel_tile_height(fb, plane);
>
> return ALIGN(height, tile_height);
> }
> @@ -2158,21 +2158,23 @@ static unsigned int intel_linear_alignment(const
> struct drm_i915_private *dev_pr
> return 0;
> }
>
> -static unsigned int intel_surf_alignment(const struct drm_i915_private
> *dev_priv,
> - uint64_t fb_modifier)
> +static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> + int plane)
> {
> - switch (fb_modifier) {
> + struct drm_i915_private *dev_priv = to_i915(fb->dev);
> +
> + switch (fb->modifier) {
> case DRM_FORMAT_MOD_NONE:
> return intel_linear_alignment(dev_priv);
> case I915_FORMAT_MOD_X_TILED:
> - if (INTEL_INFO(dev_priv)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> - MISSING_CASE(fb_modifier);
> + MISSING_CASE(fb->modifier);
>
Re: [Intel-gfx] [PATCH 46/46] drm/i915: Add initial selftests for hang detection and resets
Chris Wilson writes:
> Check that we can reset the GPU and continue executing from the next
> request.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_drv.h| 4 +-
> drivers/gpu/drm/i915/intel_hangcheck.c | 4 +
> .../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
> drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 531
> +
> 4 files changed, 538 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/selftests/intel_hangcheck.c
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4a7e4b10c0a9..f82c59768f65 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3356,8 +3356,8 @@ int __must_check i915_gem_init(struct drm_i915_private
> *dev_priv);
> int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
> void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
> void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
> -int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> - unsigned int flags);
> +int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> +unsigned int flags);
> int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
> void i915_gem_resume(struct drm_i915_private *dev_priv);
> int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c
> b/drivers/gpu/drm/i915/intel_hangcheck.c
> index f05971f5586f..dce742243ba6 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -480,3 +480,7 @@ void intel_hangcheck_init(struct drm_i915_private *i915)
> INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
> i915_hangcheck_elapsed);
> }
> +
> +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> +#include "selftests/intel_hangcheck.c"
> +#endif
> diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
> b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
> index 15fb4e0dd503..d0d4f4bcd837 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
> +++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
> @@ -16,3 +16,4 @@ selftest(dmabuf, i915_gem_dmabuf_live_selftests)
> selftest(coherency, i915_gem_coherency_live_selftests)
> selftest(gtt, i915_gem_gtt_live_selftests)
> selftest(context, i915_gem_context_live_selftests)
> +selftest(hangcheck, intel_hangcheck_live_selftests)
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> new file mode 100644
> index ..2131d8707dfd
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -0,0 +1,531 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "../i915_selftest.h"
> +
> +struct hang {
> + struct drm_i915_private *i915;
> + struct drm_i915_gem_object *hws;
> + struct drm_i915_gem_object *obj;
> + u32 *seqno;
> + u32 *batch;
> +};
> +
> +static int hang_init(struct hang *h, struct drm_i915_private *i915)
> +{
> + void *vaddr;
> + int err;
> +
> + memset(h, 0, sizeof(*h));
> + h->i915 = i915;
> +
> + h->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
> + if (IS_ERR(h->hws))
> + return PTR_ERR(h->hws);
> +
> + h->obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
> + if (IS_ERR(h->obj)) {
> + err = PTR_ERR(h->obj);
> + goto err_hws;
Personally I like the verb added to the goto. Like goto free_hws,
put_hws or if you prefer, err_free_hws. The upside is
that comparing this code to what happens above and review
[Intel-gfx] [PATCH] drm/i915: Recreate internal objects with single page segments if dmar fails
If we fail to dma-map the object, the most common cause is lack of space
inside the SW-IOTLB due to fragmentation. If we recreate the_sg_table
using segments of PAGE_SIZE (and single page allocations), we may succeed
in remapping the scatterlist.
First became a significant problem for the mock selftests after commit
5584f1b1d73e ("drm/i915: fix i915 running as dom0 under Xen") increased
the max_order.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_internal.c | 37
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c
b/drivers/gpu/drm/i915/i915_gem_internal.c
index 2b9d5e94a8ae..fc950abbe400 100644
--- a/drivers/gpu/drm/i915/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/i915_gem_internal.c
@@ -48,24 +48,12 @@ static struct sg_table *
i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- unsigned int npages = obj->base.size / PAGE_SIZE;
struct sg_table *st;
struct scatterlist *sg;
+ unsigned int npages;
int max_order;
gfp_t gfp;
- st = kmalloc(sizeof(*st), GFP_KERNEL);
- if (!st)
- return ERR_PTR(-ENOMEM);
-
- if (sg_alloc_table(st, npages, GFP_KERNEL)) {
- kfree(st);
- return ERR_PTR(-ENOMEM);
- }
-
- sg = st->sgl;
- st->nents = 0;
-
max_order = MAX_ORDER;
#ifdef CONFIG_SWIOTLB
if (swiotlb_nr_tbl()) {
@@ -87,6 +75,20 @@ i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
gfp |= __GFP_DMA32;
}
+create_st:
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return ERR_PTR(-ENOMEM);
+
+ npages = obj->base.size / PAGE_SIZE;
+ if (sg_alloc_table(st, npages, GFP_KERNEL)) {
+ kfree(st);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ sg = st->sgl;
+ st->nents = 0;
+
do {
int order = min(fls(npages) - 1, max_order);
struct page *page;
@@ -114,8 +116,15 @@ i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
sg = __sg_next(sg);
} while (1);
- if (i915_gem_gtt_prepare_pages(obj, st))
+ if (i915_gem_gtt_prepare_pages(obj, st)) {
+ /* Failed to dma-map try again with single page sg segments */
+ if (get_order(st->sgl->length)) {
+ internal_free_pages(st);
+ max_order = 0;
+ goto create_st;
+ }
goto err;
+ }
/* Mark the pages as dontneed whilst they are still pinned. As soon
* as they are unpinned they are allowed to be reaped by the shrinker,
--
2.11.0
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Re: [Intel-gfx] [PATCH 21/46] drm/i915: Add selftests for object allocation, phys
On Thu, Feb 02, 2017 at 01:10:57PM +, Matthew Auld wrote:
> On 2 February 2017 at 09:08, Chris Wilson wrote:
> > + err = -EINVAL;
> > + mutex_lock(&i915->drm.struct_mutex);
> > + err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
> > + mutex_unlock(&i915->drm.struct_mutex);
> > + if (err) {
> > + pr_err("i915_gem_object_attach_phys failed, err=%d\n", err);
> > + goto out_obj;
> > + }
> > +
> > + if (obj->ops != &i915_gem_phys_ops) {
> > + pr_err("i915_gem_object_attach_phys did not create a phys
> > object\n");
> > + goto out_obj;
> I'm guessing that you meant to return an error value, see below also.
Looks like I still thought I had the err = -EINVAL set. Good thing the
purpose of the test was to trigger the oops!
-Chris
--
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Capture module parameters for the GPU error state
Joonas Lahtinen writes:
> On ke, 2017-02-01 at 16:50 +, Chris Wilson wrote:
>> They include useful material such as what mode the VM address space is
>> running in, what submission mode, extra quirks, etc.
>>
>> Signed-off-by: Chris Wilson
>
>
>
>> +static void err_print_params(struct drm_i915_error_state_buf *m,
>> + const struct i915_params *p)
>> +{
>> +#define PRINT(T, x) err_printf(m, #x ": %d\n", p->x);
>> +I915_PARAMS_FOR_EACH(PRINT);
>> +#undef PRINT_PARAM
>
> #undef PRINT
>
> That fixed;
>
> Reviewed-by: Joonas Lahtinen
>
> Needs some Acks before merging, though.
Acked-by: Mika Kuoppala
>
> Regards, Joonas
> --
> Joonas Lahtinen
> Open Source Technology Center
> Intel Corporation
> ___
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Re: [Intel-gfx] [PATCH 21/46] drm/i915: Add selftests for object allocation, phys
On 2 February 2017 at 09:08, Chris Wilson wrote:
> The phys object is a rarely used device (only very old machines require
> a chunk of physically contiguous pages for a few hardware interactions).
> As such, it is not exercised by CI and to combat that we want to add a
> test that exercises the phys object on all platforms.
>
> Signed-off-by: Chris Wilson
> Reviewed-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_gem.c| 1 +
> drivers/gpu/drm/i915/selftests/i915_gem_object.c | 120
> +
> .../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
> 3 files changed, 122 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_object.c
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index f35fda5d0abc..429c5e4350f7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4973,4 +4973,5 @@ i915_gem_object_get_dma_address(struct
> drm_i915_gem_object *obj,
> #include "selftests/scatterlist.c"
> #include "selftests/mock_gem_device.c"
> #include "selftests/huge_gem_object.c"
> +#include "selftests/i915_gem_object.c"
> #endif
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> new file mode 100644
> index ..db8f631e4993
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> @@ -0,0 +1,120 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "../i915_selftest.h"
> +
> +#include "mock_gem_device.h"
> +
> +static int igt_gem_object(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct drm_i915_gem_object *obj;
> + int err = -ENOMEM;
> +
> + /* Basic test to ensure we can create an object */
> +
> + obj = i915_gem_object_create(i915, PAGE_SIZE);
> + if (IS_ERR(obj)) {
> + err = PTR_ERR(obj);
> + pr_err("i915_gem_object_create failed, err=%d\n", err);
> + goto out;
> + }
> +
> + err = 0;
> + i915_gem_object_put(obj);
> +out:
> + return err;
> +}
> +
> +static int igt_phys_object(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct drm_i915_gem_object *obj;
> + int err = -ENOMEM;
> +
> + /* Create an object and bind it to a contiguous set of physical pages,
> +* i.e. exercise the i915_gem_object_phys API.
> +*/
> +
> + obj = i915_gem_object_create(i915, PAGE_SIZE);
> + if (IS_ERR(obj)) {
> + err = PTR_ERR(obj);
> + pr_err("i915_gem_object_create failed, err=%d\n", err);
> + goto out;
> + }
> +
> + err = -EINVAL;
> + mutex_lock(&i915->drm.struct_mutex);
> + err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
> + mutex_unlock(&i915->drm.struct_mutex);
> + if (err) {
> + pr_err("i915_gem_object_attach_phys failed, err=%d\n", err);
> + goto out_obj;
> + }
> +
> + if (obj->ops != &i915_gem_phys_ops) {
> + pr_err("i915_gem_object_attach_phys did not create a phys
> object\n");
> + goto out_obj;
I'm guessing that you meant to return an error value, see below also.
> + }
> +
> + if (!atomic_read(&obj->mm.pages_pin_count)) {
> + pr_err("i915_gem_object_attach_phys did not pin its phys
> pages\n");
> + goto out_obj;
> + }
> +
> + /* Make the object dirty so that put_pages must do copy back the data
> */
> + mutex_lock(&i915->drm.struct_mutex);
> + err = i915_gem_object_set_to_gtt_domain(obj, true);
> + mutex_unlock(&i915->drm.struct_mutex);
> + if (err) {
> + pr_err("i915_gem_object_set_to_gtt_d
Re: [Intel-gfx] [PATCH 09/46] drm/i915: Add unit tests for the breadcrumb rbtree, wakeups
On Thu, Feb 02, 2017 at 12:49:58PM +, Tvrtko Ursulin wrote:
>
> On 02/02/2017 09:08, Chris Wilson wrote:
> >+static bool wait_for_ready(struct igt_wakeup *w)
> >+{
> >+DEFINE_WAIT(ready);
> >+
> >+if (atomic_dec_and_test(w->done))
> >+wake_up_atomic_t(w->done);
> >+
> >+if (test_bit(STOP, &w->flags))
> >+goto out;
> >+
> >+set_bit(IDLE, &w->flags);
>
> I think this needs to be before atomic_dec_and_test(w->done), to
> avoid that same assert racing with the threads. Because immediately
> after the wake_up_atomic above the main loop starts asserting the
> IDLE bit which is not guaranteed to be set yet.
Before wake_up_atomic_t which is the same thing, yup.
-Chris
--
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Re: [Intel-gfx] [PATCH 38/46] drm/i915: Verify page layout for rotated VMA
On 02/02/2017 09:08, Chris Wilson wrote:
Exercise creating rotated VMA and checking the page order within.
v2: Be more creative in rotated params
v3: ...
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 179 ++
1 file changed, 179 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 095d8348f5f0..4a737a670199 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -352,11 +352,190 @@ static int igt_vma_pin1(void *arg)
return err;
}
+static unsigned long rotated_index(const struct intel_rotation_info *r,
+ unsigned int n,
+ unsigned int x,
+ unsigned int y)
+{
+ return (r->plane[n].stride * (r->plane[n].height - y - 1) +
+ r->plane[n].offset + x);
+}
+
+static struct scatterlist *
+assert_rotated(struct drm_i915_gem_object *obj,
+ const struct intel_rotation_info *r, unsigned int n,
+ struct scatterlist *sg)
+{
+ unsigned int x, y;
+
+ for (x = 0; x < r->plane[n].width; x++) {
+ for (y = 0; y < r->plane[n].height; y++) {
+ unsigned long src_idx;
+ dma_addr_t src;
+
+ if (!sg) {
+ pr_err("Invalid sg table: too short at plane %d,
(%d, %d)!\n",
+ n, x, y);
+ return ERR_PTR(-EINVAL);
+ }
+
+ src_idx = rotated_index(r, n, x, y);
+ src = i915_gem_object_get_dma_address(obj, src_idx);
+
+ if (sg_dma_len(sg) != PAGE_SIZE) {
+ pr_err("Invalid sg.length, found %d, expected %lu
for rotated page (%d, %d) [src index %lu]\n",
+ sg_dma_len(sg), PAGE_SIZE,
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (sg_dma_address(sg) != src) {
+ pr_err("Invalid address for rotated page (%d, %d)
[src index %lu]\n",
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ sg = sg_next(sg);
+ }
+ }
+
+ return sg;
+}
+
+static unsigned int rotated_size(const struct intel_rotation_plane_info *a,
+const struct intel_rotation_plane_info *b)
+{
+ return a->width * a->height + b->width * b->height;
+}
+
+static int igt_vma_rotate(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_address_space *vm = &i915->ggtt.base;
+ struct drm_i915_gem_object *obj;
+ const struct intel_rotation_plane_info planes[] = {
+ { .width = 1, .height = 1, .stride = 1 },
+ { .width = 2, .height = 2, .stride = 2 },
+ { .width = 4, .height = 4, .stride = 4 },
+ { .width = 8, .height = 8, .stride = 8 },
+
+ { .width = 3, .height = 5, .stride = 3 },
+ { .width = 3, .height = 5, .stride = 4 },
+ { .width = 3, .height = 5, .stride = 5 },
+
+ { .width = 5, .height = 3, .stride = 5 },
+ { .width = 5, .height = 3, .stride = 7 },
+ { .width = 5, .height = 3, .stride = 9 },
+
+ { .width = 4, .height = 6, .stride = 6 },
+ { .width = 6, .height = 4, .stride = 6 },
+ { }
+ }, *a, *b;
+ const unsigned int max_pages = 64;
+ int err = -ENOMEM;
+
+ /* Create VMA for many different combinations of planes and check
+* that the page layout within the rotated VMA match our expectations.
+*/
+
+ obj = i915_gem_object_create_internal(i915, max_pages * PAGE_SIZE);
+ if (IS_ERR(obj))
+ goto out;
+
+ for (a = planes; a->width; a++) {
+ for (b = planes + ARRAY_SIZE(planes); b-- != planes; ) {
+ struct i915_ggtt_view view;
+ unsigned int n, max_offset;
+
+ max_offset = max(a->stride * a->height,
+b->stride * b->height);
+ GEM_BUG_ON(max_offset > max_pages);
+ max_offset = max_pages - max_offset;
+
+ view.type = I915_GGTT_VIEW_ROTATED;
+ view.rotated.plane[0] = *a;
+ view.rotated.plane[1] = *b;
+
+
for_each_prime_number_from(view.rotated.plane[0].offset, 0, max_offset) {
+
for_each_prime_number_from(view.rotated.plane[1].offset, 0, max_offset)
Re: [Intel-gfx] [PATCH 09/46] drm/i915: Add unit tests for the breadcrumb rbtree, wakeups
On 02/02/2017 09:08, Chris Wilson wrote:
Third retroactive test, make sure that the seqno waiters are woken.
v2: Smattering of comments, rearrange code
v3: Fix assert.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 201 +
1 file changed, 201 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
index 32a27e56c353..fb368eb37660 100644
--- a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
@@ -259,11 +259,212 @@ static int igt_insert_complete(void *arg)
return err;
}
+struct igt_wakeup {
+ struct task_struct *tsk;
+ atomic_t *ready, *set, *done;
+ struct intel_engine_cs *engine;
+ unsigned long flags;
+#define STOP 0
+#define IDLE 1
+ wait_queue_head_t *wq;
+ u32 seqno;
+};
+
+static int wait_atomic(atomic_t *p)
+{
+ schedule();
+ return 0;
+}
+
+static int wait_atomic_timeout(atomic_t *p)
+{
+ return schedule_timeout(10 * HZ) ? 0 : -ETIMEDOUT;
+}
+
+static bool wait_for_ready(struct igt_wakeup *w)
+{
+ DEFINE_WAIT(ready);
+
+ if (atomic_dec_and_test(w->done))
+ wake_up_atomic_t(w->done);
+
+ if (test_bit(STOP, &w->flags))
+ goto out;
+
+ set_bit(IDLE, &w->flags);
I think this needs to be before atomic_dec_and_test(w->done), to avoid
that same assert racing with the threads. Because immediately after the
wake_up_atomic above the main loop starts asserting the IDLE bit which
is not guaranteed to be set yet.
Regards,
Tvrtko
+ for (;;) {
+ prepare_to_wait(w->wq, &ready, TASK_INTERRUPTIBLE);
+ if (atomic_read(w->ready) == 0)
+ break;
+
+ schedule();
+ }
+ finish_wait(w->wq, &ready);
+ clear_bit(IDLE, &w->flags);
+
+out:
+ if (atomic_dec_and_test(w->set))
+ wake_up_atomic_t(w->set);
+
+ return !test_bit(STOP, &w->flags);
+}
+
+static int igt_wakeup_thread(void *arg)
+{
+ struct igt_wakeup *w = arg;
+ struct intel_wait wait;
+
+ while (wait_for_ready(w)) {
+ GEM_BUG_ON(kthread_should_stop());
+
+ intel_wait_init(&wait, w->seqno);
+ intel_engine_add_wait(w->engine, &wait);
+ for (;;) {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ if (i915_seqno_passed(intel_engine_get_seqno(w->engine),
+ w->seqno))
+ break;
+
+ if (test_bit(STOP, &w->flags)) /* emergency escape */
+ break;
+
+ schedule();
+ }
+ intel_engine_remove_wait(w->engine, &wait);
+ __set_current_state(TASK_RUNNING);
+ }
+
+ return 0;
+}
+
+static void igt_wake_all_sync(atomic_t *ready,
+ atomic_t *set,
+ atomic_t *done,
+ wait_queue_head_t *wq,
+ int count)
+{
+ atomic_set(set, count);
+ atomic_set(ready, 0);
+ wake_up_all(wq);
+
+ wait_on_atomic_t(set, wait_atomic, TASK_UNINTERRUPTIBLE);
+ atomic_set(ready, count);
+ atomic_set(done, count);
+}
+
+static int igt_wakeup(void *arg)
+{
+ I915_RND_STATE(prng);
+ const int state = TASK_UNINTERRUPTIBLE;
+ struct intel_engine_cs *engine = arg;
+ struct igt_wakeup *waiters;
+ DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
+ const int count = 4096;
+ const u32 max_seqno = count / 4;
+ atomic_t ready, set, done;
+ int err = -ENOMEM;
+ int n, step;
+
+ mock_engine_reset(engine);
+
+ waiters = drm_malloc_gfp(count, sizeof(*waiters), GFP_TEMPORARY);
+ if (!waiters)
+ goto out_engines;
+
+ /* Create a large number of threads, each waiting on a random seqno.
+* Multiple waiters will be waiting for the same seqno.
+*/
+ atomic_set(&ready, count);
+ for (n = 0; n < count; n++) {
+ waiters[n].wq = &wq;
+ waiters[n].ready = &ready;
+ waiters[n].set = &set;
+ waiters[n].done = &done;
+ waiters[n].engine = engine;
+ waiters[n].flags = BIT(IDLE);
+
+ waiters[n].tsk = kthread_run(igt_wakeup_thread, &waiters[n],
+"i915/igt:%d", n);
+ if (IS_ERR(waiters[n].tsk))
+ goto out_waiters;
+
+ get_task_struct(waiters[n].tsk);
+ }
+
+ for (step = 1; step <= max_seqno; step <<= 1) {
+ u32 seqno;
+
+ /* The waiter threads start paused as we assign them a random
+* seqno and reset the engi
Re: [Intel-gfx] [PATCH v2 03/38] drm/i915: Add some selftests for sg_table manipulation
On 01/02/2017 11:34, Chris Wilson wrote:
On Wed, Feb 01, 2017 at 11:17:39AM +, Tvrtko Ursulin wrote:
+
+ for (npages = npages_funcs; *npages; npages++) {
+ prandom_seed_state(&prng,
+ i915_selftest.random_seed);
+ if (!alloc_table(&pt, sz, sz, *npages, &prng))
+ return 0; /* out of memory, give up */
You don't have skip status? Sounds not ideal to silently abort.
It runs until we use all physical memory, if left to its own devices. It's
not a skip if we have already completed some tests. ENOMEM of the test
setup itself is not what I'm testing for here, the test is for the
iterators.
But suppose you mess up the test so the starting condition asks for
impossible amount of memory but the test claims it passed. I don't think
that is a good behaviour.
+static int igt_sg_trim(void *ignored)
+{
+ IGT_TIMEOUT(end_time);
+ const unsigned long max = PAGE_SIZE; /* not prime! */
+ struct pfn_table pt;
+ unsigned long prime;
+
+ for_each_prime_number(prime, max) {
+ const npages_fn_t *npages;
+ int err;
+
+ for (npages = npages_funcs; *npages; npages++) {
+ struct rnd_state prng;
+
+ prandom_seed_state(&prng, i915_selftest.random_seed);
+ if (!alloc_table(&pt, prime, max, *npages, &prng))
+ return 0; /* out of memory, give up */
+
+ err = 0;
+ if (i915_sg_trim(&pt.st)) {
+ if (pt.st.orig_nents != prime ||
+ pt.st.nents != prime) {
+ pr_err("i915_sg_trim failed (nents %u,
orig_nents %u), expected %lu\n",
+ pt.st.nents, pt.st.orig_nents,
prime);
+ err = -EINVAL;
+ } else {
+ prandom_seed_state(&prng,
+
i915_selftest.random_seed);
+ err = expect_pfn_sgtable(&pt,
+*npages, &prng,
+"i915_sg_trim",
+end_time);
+ }
+ }
Similar to alloc_table failures above - no log or action when
i915_sg_trim fails due out of memory?
No, simply because that's an expected and acceptable result. The
question should be whether we always want to check after sg_trim.
Same as above really, I think that creates a big doubt in the test output.
Regards,
Tvrtko
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