Re: [Intel-gfx] [PATCH] drm/i915: Handle msr read failure gracefully

[Gabriel Krisman Bertazi]

Chris Wilson  writes:

> Quoting Gabriel Krisman Bertazi (2017-07-25 19:19:22)
>> power = (power & 0x1f00) >> 8;
>> units = 100 / (1 << power); /* convert to uJ */
>> power = I915_READ(MCH_SECP_NRG_STTS);
>
> Just after this is a useless cast. Though it will be neater to kill the
> (long long unsigned) and s/u64/unsigned long long/ so that we are
> consistent with the rdmsrl_safe interface.
>
> Also we should use 1u << power as we allow power to be 31, or better yet
> use:
>
>   units = (power & 0x1f00) >> 8;
>   power = I915_READ(MCH_SECP_NRG_STTS);
>   power = (10 * power) >> units; /* convert to uJ */

Hi Chris,

Thanks for your review.  I have added your suggestions on a v2 of the
patch below.

>8
Subject: [PATCH] drm/i915: Handle msr read failure gracefully

When reading the i915_energy_uJ debugfs file, it tries to fetch
MSR_RAPL_POWER_UNIT, which might not be available, like in a vm
environment, causing the exception shown below.

We can easily prevent it by doing a rdmsrl_safe read instead, which will
handle the exception, allowing us to abort the debugfs file read.

This was caught by the new igt@debugfs_test@read_all_entries testcase in
the CI.

  unchecked MSR access error: RDMSR from 0x606 at rIP:0xa0078f66
(i915_energy_uJ+0x36/0xb0 [i915])
  Call Trace:
   seq_read+0xdc/0x3a0
   full_proxy_read+0x4f/0x70
   __vfs_read+0x23/0x120
   ? putname+0x4f/0x60
   ? rcu_read_lock_sched_held+0x75/0x80
   ? entry_SYSCALL_64_fastpath+0x5/0xb1
   vfs_read+0xa0/0x150
   SyS_read+0x44/0xb0
   entry_SYSCALL_64_fastpath+0x1c/0xb1
  RIP: 0033:0x7f1f5e9f4500
  RSP: 002b:7ffc77e65cf8 EFLAGS: 0246 ORIG_RAX: 
  RAX: ffda RBX: 8146e003 RCX: 7f1f5e9f4500
  RDX: 0200 RSI: 7ffc77e65d10 RDI: 0006
  RBP: c97abf88 R08: 01eaff20 R09: 
  R10:  R11: 0246 R12: 
  R13: 0006 R14: 0005 R15: 01eb94db
   ? __this_cpu_preempt_check+0x13/0x20

v2:
 - Drop unsigned long long cast and improve calculation (Chris)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101901
Signed-off-by: Gabriel Krisman Bertazi 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index c25f42c60d61..1dba3a2be849 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2783,7 +2783,7 @@ static int i915_sink_crc(struct seq_file *m, void *data)
 static int i915_energy_uJ(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   u64 power;
+   unsigned long long power;
u32 units;
 
if (INTEL_GEN(dev_priv) < 6)
@@ -2791,15 +2791,18 @@ static int i915_energy_uJ(struct seq_file *m, void 
*data)
 
intel_runtime_pm_get(dev_priv);
 
-   rdmsrl(MSR_RAPL_POWER_UNIT, power);
-   power = (power & 0x1f00) >> 8;
-   units = 100 / (1 << power); /* convert to uJ */
+   if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, )) {
+   intel_runtime_pm_put(dev_priv);
+   return -ENODEV;
+   }
+
+   units = (power & 0x1f00) >> 8;
power = I915_READ(MCH_SECP_NRG_STTS);
-   power *= units;
+   power = (100 * power) >> units; /* convert to uJ */
 
intel_runtime_pm_put(dev_priv);
 
-   seq_printf(m, "%llu", (long long unsigned)power);
+   seq_printf(m, "%llu", power);
 
return 0;
 }
-- 
2.11.0

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Re: [Intel-gfx] [PATCH 18/20] drm/i915/selftests: Retarget igt_render_engine_reset_fallback()

[Michel Thierry]

On 7/21/2017 5:32 AM, Chris Wilson wrote:

The purpose of the test was to check per-engine resets would fallback to
the global reset when required, but first we actually need a test for a
basic i915_handle_error()!

Cc: Mika Kuoppala 
Cc: Michel Thierry 
Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 74 ++--
  1 file changed, 17 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 3ece564e4d96..e83503db3b66 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -771,22 +771,20 @@ static int igt_reset_queue(void *arg)
return err;
  }
  
-static int igt_render_engine_reset_fallback(void *arg)

+static int igt_handle_error(void *arg)
  {
struct drm_i915_private *i915 = arg;
struct intel_engine_cs *engine = i915->engine[RCS];
struct hang h;
struct drm_i915_gem_request *rq;
-   unsigned int reset_count, reset_engine_count;
-   int err = 0;
+   struct i915_gpu_state *error;
+   int err;
  
  	/* Check that we can issue a global GPU and engine reset */
  
  	if (!intel_has_reset_engine(i915))

return 0;
  
-	global_reset_lock(i915);

-
mutex_lock(>drm.struct_mutex);
  
  	err = hang_init(, i915);

@@ -802,69 +800,31 @@ static int igt_render_engine_reset_fallback(void *arg)
i915_gem_request_get(rq);
__i915_add_request(rq, true);
  
-	/* make reset engine fail */

-   rq->fence.error = -EIO;
-
if (!wait_for_hang(, rq)) {
pr_err("Failed to start request %x\n", rq->fence.seqno);
err = -EIO;
goto err_request;
}
  
-	reset_engine_count = i915_reset_engine_count(>gpu_error, engine);

-   reset_count = fake_hangcheck(rq);
-
-   /* unlock since we'll call handle_error */
mutex_unlock(>drm.struct_mutex);
-   global_reset_unlock(i915);
  
-	i915_handle_error(i915, intel_engine_flag(engine), "live test");

+   /* Temporarily disable error capture */
+   error = xchg(>gpu_error.first_error, (void *)-1);
  
-	if (i915_reset_engine_count(>gpu_error, engine) !=

-   reset_engine_count) {
-   pr_err("render engine reset recorded! (full reset expected)\n");
-   err = -EINVAL;
-   goto out_rq;
-   }
+   engine->hangcheck.stalled = true;
+   engine->hangcheck.seqno = intel_engine_get_seqno(engine);
  
-	if (i915_reset_count(>gpu_error) == reset_count) {

-   pr_err("No full GPU reset recorded!\n");
-   err = -EINVAL;
-   goto out_rq;
-   }
+   i915_handle_error(i915, intel_engine_flag(engine), "%s", __func__);
  
-	/*

-* by using fence.error = -EIO, full reset sets the wedged flag, do one
-* more full reset to re-enable the hw.
-*/
-   if (i915_terminally_wedged(>gpu_error)) {
-   global_reset_lock(i915);
-   rq->fence.error = 0;
-
-   mutex_lock(>drm.struct_mutex);
-   set_bit(I915_RESET_HANDOFF, >gpu_error.flags);
-   i915_reset(i915);


And now this will need to change again...
sorry I missed it yesterday.


-   GEM_BUG_ON(test_bit(I915_RESET_HANDOFF,
-   >gpu_error.flags));
-   mutex_unlock(>drm.struct_mutex);
-
-   if (i915_reset_count(>gpu_error) == reset_count) {
-   pr_err("No full GPU reset recorded!\n");
-   err = -EINVAL;
-   goto out_rq;
-   }
-   }
-
-out_rq:
-   i915_gem_request_put(rq);
-   hang_fini();
-out_backoff:
-   global_reset_unlock(i915);
+   xchg(>gpu_error.first_error, error);
  
-	if (i915_terminally_wedged(>gpu_error))

-   return -EIO;
+   mutex_lock(>drm.struct_mutex);
  
-	return err;

+   if (rq->fence.error != -EIO) {
+   pr_err("Guilty request not identified!\n");
+   err = -EINVAL;
+   goto err_request;
+   }
  
  err_request:

i915_gem_request_put(rq);
@@ -872,7 +832,7 @@ static int igt_render_engine_reset_fallback(void *arg)
hang_fini();
  err_unlock:
mutex_unlock(>drm.struct_mutex);
-   goto out_backoff;
+   return err;
  }
  
  int intel_hangcheck_live_selftests(struct drm_i915_private *i915)

@@ -884,7 +844,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private 
*i915)
SUBTEST(igt_reset_active_engines),
SUBTEST(igt_wait_reset),
SUBTEST(igt_reset_queue),
-   SUBTEST(igt_render_engine_reset_fallback),
+   SUBTEST(igt_handle_error),
};
  
  	if (!intel_has_gpu_reset(i915))

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Eliminate dead code in intel_sanitize_enable_ppgtt() (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Eliminate dead code in intel_sanitize_enable_ppgtt() (rev2)
URL   : https://patchwork.freedesktop.org/series/8105/
State : success

== Summary ==

Series 8105v2 drm/i915: Eliminate dead code in intel_sanitize_enable_ppgtt()
https://patchwork.freedesktop.org/api/1.0/series/8105/revisions/2/mbox/

Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-pnv-d510) fdo#101597

fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:455s
fi-blb-e6850 total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  
time:355s
fi-bsw-n3050 total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  
time:539s
fi-bxt-j4205 total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:522s
fi-byt-j1900 total:280  pass:255  dwarn:1   dfail:0   fail:0   skip:24  
time:492s
fi-byt-n2820 total:280  pass:251  dwarn:1   dfail:0   fail:0   skip:28  
time:493s
fi-glk-2atotal:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-hsw-4770  total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:436s
fi-hsw-4770r total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-ilk-650   total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  
time:415s
fi-ivb-3520m total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:506s
fi-ivb-3770  total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-kbl-7500u total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:470s
fi-kbl-7560u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:717s
fi-kbl-r total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:590s
fi-pnv-d510  total:280  pass:222  dwarn:3   dfail:0   fail:0   skip:55  
time:571s
fi-skl-6260u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:460s
fi-skl-6700hqtotal:280  pass:263  dwarn:0   dfail:0   fail:0   skip:17  
time:588s
fi-skl-6700k total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-skl-6770hqtotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:476s
fi-skl-gvtdvmtotal:280  pass:266  dwarn:1   dfail:0   fail:0   skip:13  
time:437s
fi-skl-x1585ltotal:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:489s
fi-snb-2520m total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:558s
fi-snb-2600  total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  
time:409s

fb7cda75b61e4ab4243dad8a23475d1c39ccb333 drm-tip: 2017y-07m-25d-17h-49m-38s UTC 
integration manifest
683d982b0f27 drm/i915: Eliminate dead code in intel_sanitize_enable_ppgtt()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5278/
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[Intel-gfx] [PATCH] drm/i915: Eliminate dead code in intel_sanitize_enable_ppgtt()

[Imre Deak]

From: Damien Lespiau 

We exit early if has_aliasing_ppgtt is 0, so towards the end of the
function has_aliasing_ppgtt can only be 1.

Also:

if (foo)
return 1;
else
return 0;

when foo is already a bool is really just:

return foo;

v2:
- Simplify more using the fact that i915.enable_execlists requires that
  GEN >= 8. (Chris)

Signed-off-by: Damien Lespiau 
Cc: Chris Wilson 
[Imre: updated to v2]
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 10aa7762d9a6..f401318430ed 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -133,7 +133,7 @@ static inline void i915_ggtt_invalidate(struct 
drm_i915_private *i915)
 }
 
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
-   int enable_ppgtt)
+   int enable_ppgtt)
 {
bool has_aliasing_ppgtt;
bool has_full_ppgtt;
@@ -180,10 +180,14 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private 
*dev_priv,
return 0;
}
 
-   if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt)
-   return has_full_48bit_ppgtt ? 3 : 2;
-   else
-   return has_aliasing_ppgtt ? 1 : 0;
+   if (!has_full_ppgtt)
+   return 1;
+
+   /* full-ppgtt doesn't yet work reliably in legacy ringbuffer mode */
+   if (!i915.enable_execlists)
+   return 1;
+
+   return has_full_48bit_ppgtt ? 3 : 2;
 }
 
 static int ppgtt_bind_vma(struct i915_vma *vma,
-- 
2.13.2

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Re: [Intel-gfx] [PATCH 11/21] drm/i915: support 1G pages for the 48b PPGTT

[Chris Wilson]

Quoting Matthew Auld (2017-07-25 20:21:23)
> Support inserting 1G gtt pages into the 48b PPGTT.
> 
> v2: sanity check sg->length against page_size
> 
> Signed-off-by: Matthew Auld 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 73 
> +++--
>  drivers/gpu/drm/i915/i915_gem_gtt.h |  2 +
>  2 files changed, 71 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 385cd85f47bb..acd0c0d1ba8d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -945,6 +945,66 @@ static void gen8_ppgtt_insert_3lvl(struct 
> i915_address_space *vm,
>   cache_level);
>  }
>  
> +static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
> +  struct i915_page_directory_pointer 
> **pdps,
> +  struct sgt_dma *iter,
> +  enum i915_cache_level cache_level)
> +{
> +   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
> +   u64 start = vma->node.start;
> +
> +   do {
> +   struct gen8_insert_pte idx = gen8_insert_pte(start);
> +   struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
> +   struct i915_page_directory *pd = 
> pdp->page_directory[idx.pdpe];
> +   struct i915_page_table *pt = pd->page_table[idx.pde];
> +   dma_addr_t rem = iter->max - iter->dma;

We don't need to recalculate rem each loop, it dwindles until we advance
the iter and then we reset rem = iter->sg->length.

> +   unsigned int page_size;
> +   gen8_pte_t encode = pte_encode;
> +   gen8_pte_t *vaddr;
> +   u16 index, max;
> +
> +   if (unlikely(vma->page_sizes.sg & I915_GTT_PAGE_SIZE_1G) &&
> +   IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_1G) &&
> +   rem >= I915_GTT_PAGE_SIZE_1G && !(idx.pte | idx.pde)) {
> +   vaddr = kmap_atomic_px(pdp);
> +   index = idx.pdpe;
> +   max = GEN8_PML4ES_PER_PML4;
> +   page_size = I915_GTT_PAGE_SIZE_1G;
> +   encode |= GEN8_PDPE_PS_1G;
> +   } else {
> +   vaddr = kmap_atomic_px(pt);
> +   index = idx.pte;
> +   max = GEN8_PTES;
> +   page_size = I915_GTT_PAGE_SIZE;
> +   }
> +
> +   do {
> +   GEM_BUG_ON(iter->sg->length < page_size);
> +   vaddr[index++] = encode | iter->dma;
> +
> +   start += page_size;
> +   iter->dma += page_size;

rem -= page_size;

> +   if (iter->dma >= iter->max) {
> +   iter->sg = __sg_next(iter->sg);
> +   if (!iter->sg)
> +   break;
> +
rem = iter->sg->length;
> +   iter->dma = sg_dma_address(iter->sg);
> +   iter->max = iter->dma + iter->sg->length;
iter->max = iter->dma + rem;

if (rem < page_size)
break;
> +
> +   if (unlikely(!IS_ALIGNED(iter->dma, 
> page_size)))
> +   break;
> +   }
> +   rem = iter->max - iter->dma;
> +
> +   } while (rem >= page_size && index < max);

Check against rem is now redundant.

Then to review the impact upon later patches.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for huge gtt pages (rev5)

[Patchwork]

== Series Details ==

Series: huge gtt pages (rev5)
URL   : https://patchwork.freedesktop.org/series/25118/
State : success

== Summary ==

Series 25118v5 huge gtt pages
https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/5/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900) fdo#101705

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:442s
fi-blb-e6850 total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  
time:361s
fi-bsw-n3050 total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  
time:550s
fi-bxt-j4205 total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:504s
fi-byt-j1900 total:280  pass:256  dwarn:0   dfail:0   fail:0   skip:24  
time:476s
fi-byt-n2820 total:280  pass:251  dwarn:1   dfail:0   fail:0   skip:28  
time:481s
fi-glk-2atotal:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:596s
fi-hsw-4770  total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:441s
fi-hsw-4770r total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:418s
fi-ilk-650   total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  
time:411s
fi-ivb-3520m total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:493s
fi-ivb-3770  total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:460s
fi-kbl-7560u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:573s
fi-kbl-r total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:579s
fi-pnv-d510  total:280  pass:224  dwarn:1   dfail:0   fail:0   skip:55  
time:568s
fi-skl-6260u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:461s
fi-skl-6700hqtotal:280  pass:263  dwarn:0   dfail:0   fail:0   skip:17  
time:584s
fi-skl-6700k total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-skl-6770hqtotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:469s
fi-skl-gvtdvmtotal:280  pass:266  dwarn:1   dfail:0   fail:0   skip:13  
time:434s
fi-skl-x1585ltotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:498s
fi-snb-2520m total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-snb-2600  total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  
time:406s

fb7cda75b61e4ab4243dad8a23475d1c39ccb333 drm-tip: 2017y-07m-25d-17h-49m-38s UTC 
integration manifest
da7072bdd419 drm/i915: enable platform support for 1G pages
356cd82401cf drm/i915: enable platform support for 2M pages
01f015637c66 drm/i915: enable platform support for 64K pages
f5c706b07687 drm/i915: disable platform support for vGPU huge gtt pages
50cd4026d273 drm/i915/selftests: mix huge pages
3a8f37d755d8 drm/i915/selftests: huge page tests
e561231b32c2 drm/i915/debugfs: include some gtt page size metrics
761bcb912235 drm/i915: accurate page size tracking for the ppgtt
bb866b5ff509 drm/i915: support 64K pages for the 48b PPGTT
bcc9a6fdd3e1 drm/i915: support 2M pages for the 48b PPGTT
a247d58934ce drm/i915: support 1G pages for the 48b PPGTT
7c2645ebfee3 drm/i915: disable GTT cache for 2M/1G pages
4c7c4ff939bd drm/i915: enable IPS bit for 64K pages
fc1643c887dc drm/i915: align 64K objects to 2M
5d0b73ab8a5b drm/i915: align the vma start to the largest gtt page size
32469c66dabe drm/i915: introduce vm set_pages/clear_pages
9bcac5940efb drm/i915: introduce page_size members
a27234d41301 drm/i915: introduce page_size_mask to dev_info
2bb16aff0d21 drm/i915/gemfs: enable THP
4d15748d33e8 drm/i915: introduce simple gemfs
ce0ac0a25eea mm/shmem: introduce shmem_file_setup_with_mnt

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5277/
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Re: [Intel-gfx] [PATCH 06/21] drm/i915: introduce vm set_pages/clear_pages

[Chris Wilson]

Quoting Matthew Auld (2017-07-25 20:21:18)
> @@ -471,25 +473,31 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 
> alignment, u64 flags)
> if (ret)
> return ret;
>  

GEM_BUG_ON(vma->pages);

> +   if (!vma->pages) {
> +   ret = vma->vm->set_pages(vma);
> +   if (ret)
> +   goto err_unpin;
> +   }

If we have not been inserted, vma->bind_flags == 0 and so vma->page must
be NULL.
-Chris
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[Intel-gfx] [PATCH 20/21] drm/i915: enable platform support for 2M pages

[Matthew Auld]

For gen8+ platforms which support the 48b PPGTT, enable platform level
support for 2M pages. Also enable for mock testing.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_pci.c  | 6 --
 drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c453ef752ee9..0b1699c574a5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -319,7 +319,8 @@ static const struct intel_device_info intel_haswell_info = {
 #define BDW_FEATURES \
HSW_FEATURES, \
BDW_COLORS, \
-   GEN_DEFAULT_PAGE_SIZES, \
+   .page_size_mask = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1, \
@@ -365,7 +366,8 @@ static const struct intel_device_info intel_cherryview_info 
= {
 
 #define GEN9_DEFAULT_PAGE_SIZES \
.page_size_mask = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_64K
+ I915_GTT_PAGE_SIZE_64K | \
+ I915_GTT_PAGE_SIZE_2M
 
 #define SKL_PLATFORM \
BDW_FEATURES, \
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c 
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index edafc6ad0aac..8235bfa09de0 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -171,7 +171,8 @@ struct drm_i915_private *mock_gem_device(void)
 
mkwrite_device_info(i915)->page_size_mask =
I915_GTT_PAGE_SIZE_4K |
-   I915_GTT_PAGE_SIZE_64K;
+   I915_GTT_PAGE_SIZE_64K |
+   I915_GTT_PAGE_SIZE_2M;
 
spin_lock_init(>mm.object_stat_lock);
mock_uncore_init(i915);
-- 
2.13.3

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[Intel-gfx] [PATCH 14/21] drm/i915: accurate page size tracking for the ppgtt

[Matthew Auld]

Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c| 10 ++
 drivers/gpu/drm/i915/i915_gem_object.h | 10 ++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 33c819d7d060..e727694120e9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -943,6 +943,8 @@ static void gen8_ppgtt_insert_3lvl(struct 
i915_address_space *vm,
 
gen8_ppgtt_insert_pte_entries(ppgtt, >pdp, , ,
  cache_level);
+
+   vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 }
 
 static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
@@ -1033,8 +1035,10 @@ static void gen8_ppgtt_insert_huge_entries(struct 
i915_vma *vma,
vaddr = kmap_atomic_px(pd);
vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
kunmap_atomic(vaddr);
+   page_size = I915_GTT_PAGE_SIZE_64K;
}
}
+   vma->page_sizes.gtt |= page_size;
 
} while (iter->sg);
 }
@@ -1060,6 +1064,8 @@ static void gen8_ppgtt_insert_4lvl(struct 
i915_address_space *vm,
while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
 , , cache_level))
GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+
+   vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
}
 }
 
@@ -1778,6 +1784,8 @@ static void gen6_ppgtt_insert_entries(struct 
i915_address_space *vm,
}
} while (1);
kunmap_atomic(vaddr);
+
+   vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 }
 
 static int gen6_alloc_va_range(struct i915_address_space *vm,
@@ -2468,6 +2476,8 @@ static int ggtt_bind_vma(struct i915_vma *vma,
vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
intel_runtime_pm_put(i915);
 
+   vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+
/*
 * Without aliasing PPGTT there's no difference between
 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h 
b/drivers/gpu/drm/i915/i915_gem_object.h
index 7fc8b8402897..2e0f3b48a81a 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -144,6 +144,7 @@ struct drm_i915_gem_object {
struct sg_table *pages;
void *mapping;
 
+   /* TODO: whack some of this into the error state */
struct i915_page_sizes {
/**
 * The sg mask of the pages sg_table. i.e the mask of
@@ -159,6 +160,15 @@ struct drm_i915_gem_object {
 * to use opportunistically.
 */
unsigned int sg;
+
+   /**
+* The actual gtt page size usage. Since we can have
+* multiple vma associated with this object we need to
+* prevent any trampling of state, hence a copy of this
+* struct also lives in each vma, therefore the gtt
+* value here should only be read/write through the vma.
+*/
+   unsigned int gtt;
} page_sizes;
 
struct i915_gem_object_page_iter {
-- 
2.13.3

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[Intel-gfx] [PATCH 19/21] drm/i915: enable platform support for 64K pages

[Matthew Auld]

For gen9+ enable platform level support for 64K pages. Also enable for
mock testing.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_pci.c  | 3 ++-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b07fabf1cd4f..c453ef752ee9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -364,7 +364,8 @@ static const struct intel_device_info intel_cherryview_info 
= {
 };
 
 #define GEN9_DEFAULT_PAGE_SIZES \
-   .page_size_mask = I915_GTT_PAGE_SIZE_4K
+   .page_size_mask = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_64K
 
 #define SKL_PLATFORM \
BDW_FEATURES, \
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c 
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index f84a52c05869..edafc6ad0aac 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -170,7 +170,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->gen = -1;
 
mkwrite_device_info(i915)->page_size_mask =
-   I915_GTT_PAGE_SIZE_4K;
+   I915_GTT_PAGE_SIZE_4K |
+   I915_GTT_PAGE_SIZE_64K;
 
spin_lock_init(>mm.object_stat_lock);
mock_uncore_init(i915);
-- 
2.13.3

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[Intel-gfx] [PATCH 15/21] drm/i915/debugfs: include some gtt page size metrics

[Matthew Auld]

Good to know, mostly for debugging purposes.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 42 +
 1 file changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ea50c4a1efae..ba5ef95286a5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -117,6 +117,26 @@ static u64 i915_gem_obj_total_ggtt_size(struct 
drm_i915_gem_object *obj)
return size;
 }
 
+static const char *stringify_page_sizes(unsigned int page_sizes)
+{
+   switch (page_sizes) {
+   case I915_GTT_PAGE_SIZE_4K:
+   return "4K";
+   case I915_GTT_PAGE_SIZE_64K:
+   return "64K";
+   case I915_GTT_PAGE_SIZE_2M:
+   return "2M";
+   case I915_GTT_PAGE_SIZE_1G:
+   return "1G";
+   default:
+   /* mixed-mode? */
+   if (page_sizes)
+   return "M";
+
+   return "";
+   }
+}
+
 static void
 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 {
@@ -154,9 +174,10 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)
if (!drm_mm_node_allocated(>node))
continue;
 
-   seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
+   seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
   i915_vma_is_ggtt(vma) ? "g" : "pp",
-  vma->node.start, vma->node.size);
+  vma->node.start, vma->node.size,
+  stringify_page_sizes(vma->page_sizes.gtt));
if (i915_vma_is_ggtt(vma)) {
switch (vma->ggtt_view.type) {
case I915_GGTT_VIEW_NORMAL:
@@ -401,8 +422,8 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_device *dev = _priv->drm;
struct i915_ggtt *ggtt = _priv->ggtt;
-   u32 count, mapped_count, purgeable_count, dpy_count;
-   u64 size, mapped_size, purgeable_size, dpy_size;
+   u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
+   u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
struct drm_i915_gem_object *obj;
struct drm_file *file;
int ret;
@@ -418,6 +439,7 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
size = count = 0;
mapped_size = mapped_count = 0;
purgeable_size = purgeable_count = 0;
+   huge_size = huge_count = 0;
list_for_each_entry(obj, _priv->mm.unbound_list, global_link) {
size += obj->base.size;
++count;
@@ -431,6 +453,11 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
mapped_count++;
mapped_size += obj->base.size;
}
+
+   if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
+   huge_count++;
+   huge_size += obj->base.size;
+   }
}
seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 
@@ -453,6 +480,11 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
mapped_count++;
mapped_size += obj->base.size;
}
+
+   if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
+   huge_count++;
+   huge_size += obj->base.size;
+   }
}
seq_printf(m, "%u bound objects, %llu bytes\n",
   count, size);
@@ -460,6 +492,8 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
   purgeable_count, purgeable_size);
seq_printf(m, "%u mapped objects, %llu bytes\n",
   mapped_count, mapped_size);
+   seq_printf(m, "%u huge-paged objects, %llu bytes\n",
+  huge_count, huge_size);
seq_printf(m, "%u display objects (pinned), %llu bytes\n",
   dpy_count, dpy_size);
 
-- 
2.13.3

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[Intel-gfx] [PATCH 16/21] drm/i915/selftests: huge page tests

[Matthew Auld]

v2: mock test page support configurations and add MI_STORE_DWORD test

v3: run all mockable huge page tests on all platforms via the mock_device

v4: add pin_update regression test
various improvements suggested by Chris

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c|1 +
 drivers/gpu/drm/i915/selftests/huge_pages.c| 1170 
 .../gpu/drm/i915/selftests/i915_live_selftests.h   |1 +
 .../gpu/drm/i915/selftests/i915_mock_selftests.h   |1 +
 4 files changed, 1173 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/selftests/huge_pages.c

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index aecdf0e3098d..74ad006cac15 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5400,6 +5400,7 @@ i915_gem_object_get_dma_address(struct 
drm_i915_gem_object *obj,
 #include "selftests/scatterlist.c"
 #include "selftests/mock_gem_device.c"
 #include "selftests/huge_gem_object.c"
+#include "selftests/huge_pages.c"
 #include "selftests/i915_gem_object.c"
 #include "selftests/i915_gem_coherency.c"
 #endif
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
new file mode 100644
index ..e0b95d34296b
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -0,0 +1,1170 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "../i915_selftest.h"
+
+#include 
+
+#include "mock_drm.h"
+
+static const unsigned int page_sizes[] = {
+   I915_GTT_PAGE_SIZE_1G,
+   I915_GTT_PAGE_SIZE_2M,
+   I915_GTT_PAGE_SIZE_64K,
+   I915_GTT_PAGE_SIZE_4K,
+};
+
+static unsigned int get_largest_page_size(struct drm_i915_private *i915,
+ size_t rem)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(page_sizes); ++i) {
+   unsigned int page_size = page_sizes[i];
+
+   if (HAS_PAGE_SIZE(i915, page_size) && rem >= page_size)
+   return page_size;
+   }
+
+   GEM_BUG_ON(1);
+}
+
+static struct sg_table *
+fake_get_huge_pages(struct drm_i915_gem_object *obj,
+   unsigned int *sg_mask)
+{
+#define GFP (GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY)
+   struct drm_i915_private *i915 = to_i915(obj->base.dev);
+   size_t max_len = rounddown_pow_of_two(UINT_MAX);
+   struct sg_table *st;
+   struct scatterlist *sg;
+   size_t rem;
+
+   st = kmalloc(sizeof(*st), GFP);
+   if (!st)
+   return ERR_PTR(-ENOMEM);
+
+   if (sg_alloc_table(st, obj->base.size >> PAGE_SHIFT, GFP)) {
+   kfree(st);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   /* Use optimal page sized chunks to fill in the sg table */
+   rem = obj->base.size;
+   sg = st->sgl;
+   st->nents = 0;
+   do {
+   unsigned int page_size = get_largest_page_size(i915, rem);
+   unsigned int len = min(page_size * (rem / page_size), max_len);
+
+   sg->offset = 0;
+   sg->length = len;
+   sg_dma_len(sg) = len;
+   sg_dma_address(sg) = page_size;
+
+   *sg_mask |= len;
+
+   st->nents++;
+
+   rem -= len;
+   if (!rem) {
+   sg_mark_end(sg);
+   break;
+   }
+
+   sg = sg_next(sg);
+   } while (1);
+
+   obj->mm.madv = I915_MADV_DONTNEED;
+
+   return st;
+#undef GFP
+}
+
+static void fake_free_huge_pages(struct drm_i915_gem_object *obj,
+struct sg_table *pages)
+{
+   sg_free_table(pages);
+   kfree(pages);
+}
+

[Intel-gfx] [PATCH 21/21] drm/i915: enable platform support for 1G pages

[Matthew Auld]

For gen8+ enable platforms which support the 48b PPGTT, enable support
for 1G pages. Also enable for mock testing.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_pci.c  | 6 --
 drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0b1699c574a5..f01e23d3ac28 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -320,7 +320,8 @@ static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES, \
BDW_COLORS, \
.page_size_mask = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_2M, \
+ I915_GTT_PAGE_SIZE_2M | \
+ I915_GTT_PAGE_SIZE_1G, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1, \
@@ -367,7 +368,8 @@ static const struct intel_device_info intel_cherryview_info 
= {
 #define GEN9_DEFAULT_PAGE_SIZES \
.page_size_mask = I915_GTT_PAGE_SIZE_4K | \
  I915_GTT_PAGE_SIZE_64K | \
- I915_GTT_PAGE_SIZE_2M
+ I915_GTT_PAGE_SIZE_2M | \
+ I915_GTT_PAGE_SIZE_1G
 
 #define SKL_PLATFORM \
BDW_FEATURES, \
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c 
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8235bfa09de0..70a5da9e33b1 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -172,7 +172,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->page_size_mask =
I915_GTT_PAGE_SIZE_4K |
I915_GTT_PAGE_SIZE_64K |
-   I915_GTT_PAGE_SIZE_2M;
+   I915_GTT_PAGE_SIZE_2M |
+   I915_GTT_PAGE_SIZE_1G;
 
spin_lock_init(>mm.object_stat_lock);
mock_uncore_init(i915);
-- 
2.13.3

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[Intel-gfx] [PATCH 18/21] drm/i915: disable platform support for vGPU huge gtt pages

[Matthew Auld]

Currently gvt gtt handling doesn't support huge page entries, so disable
for now.

Suggested-by: Zhenyu Wang 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Zhenyu Wang 
---
 drivers/gpu/drm/i915/i915_gem.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 74ad006cac15..c171511d3251 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4871,6 +4871,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 
mutex_lock(_priv->drm.struct_mutex);
 
+   /* If the guest supports the 48b PPGGT, then we need to fallback to 4K
+* pages, since gvt gtt handling doesn't support huge page entries - we
+* need to check either hypervisor mm can support huge guest page or
+* just do emulation in gvt.
+*/
+   if (USES_FULL_48BIT_PPGTT(dev_priv) && intel_vgpu_active(dev_priv))
+   mkwrite_device_info(dev_priv)->page_size_mask =
+   I915_GTT_PAGE_SIZE_4K;
+
dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
 
if (!i915.enable_execlists) {
-- 
2.13.3

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[Intel-gfx] [PATCH 17/21] drm/i915/selftests: mix huge pages

[Matthew Auld]

Try to mix sg page sizes for 4K, 64K and 2M pages.

v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/

Suggested-by: Chris Wilson 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/scatterlist.c 
b/drivers/gpu/drm/i915/selftests/scatterlist.c
index 1cc5d2931753..cd6d2a16071f 100644
--- a/drivers/gpu/drm/i915/selftests/scatterlist.c
+++ b/drivers/gpu/drm/i915/selftests/scatterlist.c
@@ -189,6 +189,20 @@ static unsigned int random(unsigned long n,
return 1 + (prandom_u32_state(rnd) % 1024);
 }
 
+static unsigned int random_page_size_pages(unsigned long n,
+  unsigned long count,
+  struct rnd_state *rnd)
+{
+   /* 4K, 64K, 2M */
+   static unsigned int page_count[] = {
+   BIT(12) >> PAGE_SHIFT,
+   BIT(16) >> PAGE_SHIFT,
+   BIT(21) >> PAGE_SHIFT,
+   };
+
+   return page_count[(prandom_u32_state(rnd) % 3)];
+}
+
 static inline bool page_contiguous(struct page *first,
   struct page *last,
   unsigned long npages)
@@ -252,6 +266,7 @@ static const npages_fn_t npages_funcs[] = {
grow,
shrink,
random,
+   random_page_size_pages,
NULL,
 };
 
-- 
2.13.3

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[Intel-gfx] [PATCH 12/21] drm/i915: support 2M pages for the 48b PPGTT

[Matthew Auld]

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 
 drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index acd0c0d1ba8d..55a9e8ecb349 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -972,6 +972,14 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma 
*vma,
max = GEN8_PML4ES_PER_PML4;
page_size = I915_GTT_PAGE_SIZE_1G;
encode |= GEN8_PDPE_PS_1G;
+   } else if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
+  IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
+  rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
+   vaddr = kmap_atomic_px(pd);
+   index = idx.pde;
+   max = I915_PDES;
+   page_size = I915_GTT_PAGE_SIZE_2M;
+   encode |= GEN8_PDE_PS_2M;
} else {
vaddr = kmap_atomic_px(pt);
index = idx.pte;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index e46f05f0cfd9..aa4488637fc9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -149,6 +149,8 @@ typedef u64 gen8_ppgtt_pml4e_t;
 #define GEN8_PPAT_ELLC_OVERRIDE(0<<2)
 #define GEN8_PPAT(i, x)((u64)(x) << ((i) * 8))
 
+#define GEN8_PDE_PS_2M   BIT(7)
+
 #define GEN8_PDPE_PS_1G  BIT(7)
 
 struct sg_table;
-- 
2.13.3

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[Intel-gfx] [PATCH 11/21] drm/i915: support 1G pages for the 48b PPGTT

[Matthew Auld]

Support inserting 1G gtt pages into the 48b PPGTT.

v2: sanity check sg->length against page_size

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 73 +++--
 drivers/gpu/drm/i915/i915_gem_gtt.h |  2 +
 2 files changed, 71 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 385cd85f47bb..acd0c0d1ba8d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -945,6 +945,66 @@ static void gen8_ppgtt_insert_3lvl(struct 
i915_address_space *vm,
  cache_level);
 }
 
+static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
+  struct i915_page_directory_pointer 
**pdps,
+  struct sgt_dma *iter,
+  enum i915_cache_level cache_level)
+{
+   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
+   u64 start = vma->node.start;
+
+   do {
+   struct gen8_insert_pte idx = gen8_insert_pte(start);
+   struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
+   struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
+   struct i915_page_table *pt = pd->page_table[idx.pde];
+   dma_addr_t rem = iter->max - iter->dma;
+   unsigned int page_size;
+   gen8_pte_t encode = pte_encode;
+   gen8_pte_t *vaddr;
+   u16 index, max;
+
+   if (unlikely(vma->page_sizes.sg & I915_GTT_PAGE_SIZE_1G) &&
+   IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_1G) &&
+   rem >= I915_GTT_PAGE_SIZE_1G && !(idx.pte | idx.pde)) {
+   vaddr = kmap_atomic_px(pdp);
+   index = idx.pdpe;
+   max = GEN8_PML4ES_PER_PML4;
+   page_size = I915_GTT_PAGE_SIZE_1G;
+   encode |= GEN8_PDPE_PS_1G;
+   } else {
+   vaddr = kmap_atomic_px(pt);
+   index = idx.pte;
+   max = GEN8_PTES;
+   page_size = I915_GTT_PAGE_SIZE;
+   }
+
+   do {
+   GEM_BUG_ON(iter->sg->length < page_size);
+   vaddr[index++] = encode | iter->dma;
+
+   start += page_size;
+   iter->dma += page_size;
+   if (iter->dma >= iter->max) {
+   iter->sg = __sg_next(iter->sg);
+   if (!iter->sg)
+   break;
+
+   iter->dma = sg_dma_address(iter->sg);
+   iter->max = iter->dma + iter->sg->length;
+
+   if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
+   break;
+   }
+   rem = iter->max - iter->dma;
+
+   } while (rem >= page_size && index < max);
+
+   kunmap_atomic(vaddr);
+
+   } while (iter->sg);
+}
+
 static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
   struct i915_vma *vma,
   enum i915_cache_level cache_level,
@@ -957,11 +1017,16 @@ static void gen8_ppgtt_insert_4lvl(struct 
i915_address_space *vm,
.max = iter.dma + iter.sg->length,
};
struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
-   struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
 
-   while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], ,
-, cache_level))
-   GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+   if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
+   gen8_ppgtt_insert_huge_entries(vma, pdps, , cache_level);
+   } else {
+   struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
+
+   while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
+, , cache_level))
+   GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+   }
 }
 
 static void gen8_free_page_tables(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 57738a61ea6e..e46f05f0cfd9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -149,6 +149,8 @@ typedef u64 gen8_ppgtt_pml4e_t;
 #define GEN8_PPAT_ELLC_OVERRIDE(0<<2)
 #define GEN8_PPAT(i, x)((u64)(x) << ((i) * 8))
 
+#define 

[Intel-gfx] [PATCH 08/21] drm/i915: align 64K objects to 2M

[Matthew Auld]

We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.

v2: don't separate logically connected ops

Suggested-by: Chris Wilson 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_vma.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 212da056ef7d..879d15b815e0 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -500,9 +500,17 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 
alignment, u64 flags)
if (end > (1ULL << 32) &&
vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
u64 page_alignment =
-   rounddown_pow_of_two(vma->page_sizes.sg);
+   rounddown_pow_of_two(vma->page_sizes.sg |
+I915_GTT_PAGE_SIZE_2M);
 
alignment = max(alignment, page_alignment);
+
+   /* We can't mix 64K and 4K PTEs in the same page-table 
(2M
+* block), and so to avoid the ugliness and complexity 
of
+* coloring we opt for just aligning 64K objects to 2M.
+*/
+   if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
+   size = round_up(size, I915_GTT_PAGE_SIZE_2M);
}
 
ret = i915_gem_gtt_insert(vma->vm, >node,
-- 
2.13.3

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[Intel-gfx] [PATCH 06/21] drm/i915: introduce vm set_pages/clear_pages

[Matthew Auld]

Move the setting/clearing of the vma->pages to a vm operation. Doing so
neatens things up a little, but more importantly gives us a sane place
to also set/clear the vma->pages_sizes, which we introduce later in
preparation for supporting huge-pages.

Suggested-by: Chris Wilson 
Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 70 +++
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  2 +
 drivers/gpu/drm/i915/i915_vma.c   | 29 +++--
 drivers/gpu/drm/i915/selftests/mock_gtt.c | 11 ++---
 4 files changed, 66 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 10aa7762d9a6..0d0b529c77c4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -200,8 +200,6 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
return ret;
}
 
-   vma->pages = vma->obj->mm.pages;
-
/* Currently applicable only to VLV */
pte_flags = 0;
if (vma->obj->gt_ro)
@@ -217,6 +215,26 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
 }
 
+static int ppgtt_set_pages(struct i915_vma *vma)
+{
+   GEM_BUG_ON(vma->pages);
+
+   vma->pages = vma->obj->mm.pages;
+
+   return 0;
+}
+
+static void clear_pages(struct i915_vma *vma)
+{
+   GEM_BUG_ON(!vma->pages);
+
+   if (vma->pages != vma->obj->mm.pages) {
+   sg_free_table(vma->pages);
+   kfree(vma->pages);
+   }
+   vma->pages = NULL;
+}
+
 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
  enum i915_cache_level level)
 {
@@ -1380,6 +1398,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.cleanup = gen8_ppgtt_cleanup;
ppgtt->base.unbind_vma = ppgtt_unbind_vma;
ppgtt->base.bind_vma = ppgtt_bind_vma;
+   ppgtt->base.set_pages = ppgtt_set_pages;
+   ppgtt->base.clear_pages = clear_pages;
ppgtt->debug_dump = gen8_dump_ppgtt;
 
return 0;
@@ -1822,6 +1842,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.unbind_vma = ppgtt_unbind_vma;
ppgtt->base.bind_vma = ppgtt_bind_vma;
+   ppgtt->base.set_pages = ppgtt_set_pages;
+   ppgtt->base.clear_pages = clear_pages;
ppgtt->base.cleanup = gen6_ppgtt_cleanup;
ppgtt->debug_dump = gen6_dump_ppgtt;
 
@@ -2333,12 +2355,6 @@ static int ggtt_bind_vma(struct i915_vma *vma,
struct drm_i915_gem_object *obj = vma->obj;
u32 pte_flags;
 
-   if (unlikely(!vma->pages)) {
-   int ret = i915_get_ggtt_vma_pages(vma);
-   if (ret)
-   return ret;
-   }
-
/* Currently applicable only to VLV */
pte_flags = 0;
if (obj->gt_ro)
@@ -2375,12 +2391,6 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
u32 pte_flags;
int ret;
 
-   if (unlikely(!vma->pages)) {
-   ret = i915_get_ggtt_vma_pages(vma);
-   if (ret)
-   return ret;
-   }
-
/* Currently applicable only to VLV */
pte_flags = 0;
if (vma->obj->gt_ro)
@@ -2395,7 +2405,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
 vma->node.start,
 vma->size);
if (ret)
-   goto err_pages;
+   return ret;
}
 
appgtt->base.insert_entries(>base, vma, cache_level,
@@ -2409,17 +2419,6 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
}
 
return 0;
-
-err_pages:
-   if (!(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND))) {
-   if (vma->pages != vma->obj->mm.pages) {
-   GEM_BUG_ON(!vma->pages);
-   sg_free_table(vma->pages);
-   kfree(vma->pages);
-   }
-   vma->pages = NULL;
-   }
-   return ret;
 }
 
 static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
@@ -2457,6 +2456,19 @@ void i915_gem_gtt_finish_pages(struct 
drm_i915_gem_object *obj,
dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL);
 }
 
+static int ggtt_set_pages(struct i915_vma *vma)
+{
+   int ret;
+
+   GEM_BUG_ON(vma->pages);
+
+   ret = i915_get_ggtt_vma_pages(vma);
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
 static void i915_gtt_color_adjust(const struct drm_mm_node *node,
  unsigned long 

[Intel-gfx] [PATCH 13/21] drm/i915: support 64K pages for the 48b PPGTT

[Matthew Auld]

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 26 ++
 drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
 2 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 55a9e8ecb349..33c819d7d060 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -960,6 +960,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma 
*vma,
struct i915_page_table *pt = pd->page_table[idx.pde];
dma_addr_t rem = iter->max - iter->dma;
unsigned int page_size;
+   bool maybe_64K = false;
gen8_pte_t encode = pte_encode;
gen8_pte_t *vaddr;
u16 index, max;
@@ -985,9 +986,17 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma 
*vma,
index = idx.pte;
max = GEN8_PTES;
page_size = I915_GTT_PAGE_SIZE;
+
+   if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K && 
!idx.pte)
+   maybe_64K = true;
}
 
do {
+   if (maybe_64K && (index % 16 == 0) &&
+   (!IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) ||
+rem < I915_GTT_PAGE_SIZE_64K))
+   maybe_64K = false;
+
GEM_BUG_ON(iter->sg->length < page_size);
vaddr[index++] = encode | iter->dma;
 
@@ -1010,6 +1019,23 @@ static void gen8_ppgtt_insert_huge_entries(struct 
i915_vma *vma,
 
kunmap_atomic(vaddr);
 
+
+   /* Is it safe to mark the 2M block as 64K? -- Either we have
+* filled whole page-table with 64K entries, or filled part of
+* it and have reached the end of the sg table and we have
+* enough padding.
+*/
+   if (maybe_64K) {
+   if (index == max ||
+   (!iter->sg && IS_ALIGNED(vma->node.start +
+vma->node.size,
+I915_GTT_PAGE_SIZE_2M))) {
+   vaddr = kmap_atomic_px(pd);
+   vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
+   kunmap_atomic(vaddr);
+   }
+   }
+
} while (iter->sg);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index aa4488637fc9..42be89d27193 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -149,6 +149,7 @@ typedef u64 gen8_ppgtt_pml4e_t;
 #define GEN8_PPAT_ELLC_OVERRIDE(0<<2)
 #define GEN8_PPAT(i, x)((u64)(x) << ((i) * 8))
 
+#define GEN8_PDE_IPS_64K BIT(11)
 #define GEN8_PDE_PS_2M   BIT(7)
 
 #define GEN8_PDPE_PS_1G  BIT(7)
-- 
2.13.3

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[Intel-gfx] [PATCH 10/21] drm/i915: disable GTT cache for 2M/1G pages

[Matthew Auld]

When SW enables the use of 2M/1G pages, it must disable the GTT cache.

v2: don't disable for Cherryview which doesn't even support 48b PPGTT!

v3: explicitly check that the system does support 2M/1G pages

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_pm.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 48785ef75d33..bab01eec4237 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8291,10 +8291,13 @@ static void broadwell_init_clock_gating(struct 
drm_i915_private *dev_priv)
 
/*
 * WaGttCachingOffByDefault:bdw
-* GTT cache may not work with big pages, so if those
-* are ever enabled GTT cache may need to be disabled.
+* The GTT cache must be disabled if the system is planning to use
+* 2M/1G pages.
 */
-   I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+   I915_WRITE(HSW_GTT_CACHE_EN,
+  HAS_PAGE_SIZE(dev_priv,
+I915_GTT_PAGE_SIZE_2M |
+I915_GTT_PAGE_SIZE_1G) ? 0 : GTT_CACHE_EN_ALL);
 
/* WaKVMNotificationOnConfigChange:bdw */
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
-- 
2.13.3

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[Intel-gfx] [PATCH 09/21] drm/i915: enable IPS bit for 64K pages

[Matthew Auld]

Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 11 +++
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b1b1d8ce46f7..aecdf0e3098d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4800,6 +4800,17 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
 
+   /* To support 64K PTE's we need to first enable the use of the
+* Intermediate-Page-Size(IPS) bit of the PDE field via some magical
+* mmio, otherwise the page-walker will simply ignore the IPS bit. This
+* shouldn't be needed after GEN10.
+*/
+   if (HAS_PAGE_SIZE(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
+   INTEL_GEN(dev_priv) <= 10)
+   I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
+  I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
+  GAMW_ECO_ENABLE_64K_IPS_FIELD);
+
i915_gem_init_swizzling(dev_priv);
 
/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc7e7a2a23b..e60c6d95608e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2215,6 +2215,9 @@ enum i915_power_well_id {
 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
 #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS  (1<<18)
 
+#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
+#define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
+
 #define GAMT_CHKN_BIT_REG  _MMIO(0x4ab8)
 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
 
-- 
2.13.3

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[Intel-gfx] [PATCH 05/21] drm/i915: introduce page_size members

[Matthew Auld]

In preparation for supporting huge gtt pages for the ppgtt, we introduce
page size members for gem objects.  We fill in the page sizes by
scanning the sg table.

v2: pass the sg_mask to set_pages

v3: calculate the sg_mask inline with populating the sg_table where
possible, and pass to set_pages along with the pages.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_drv.h  |  5 ++-
 drivers/gpu/drm/i915/i915_gem.c  | 43 
 drivers/gpu/drm/i915/i915_gem_dmabuf.c   | 17 --
 drivers/gpu/drm/i915/i915_gem_internal.c |  5 ++-
 drivers/gpu/drm/i915/i915_gem_object.h   | 20 ++-
 drivers/gpu/drm/i915/i915_gem_stolen.c   | 13 ---
 drivers/gpu/drm/i915/i915_gem_userptr.c  | 26 ++
 drivers/gpu/drm/i915/selftests/huge_gem_object.c |  4 ++-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c|  3 +-
 9 files changed, 110 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10f52937edec..8e49c44578a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2966,6 +2966,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define USES_PPGTT(dev_priv)   (i915.enable_ppgtt)
 #define USES_FULL_PPGTT(dev_priv)  (i915.enable_ppgtt >= 2)
 #define USES_FULL_48BIT_PPGTT(dev_priv)(i915.enable_ppgtt == 3)
+#define HAS_PAGE_SIZE(dev_priv, page_size) \
+   ((dev_priv)->info.page_size_mask & (page_size))
 
 #define HAS_OVERLAY(dev_priv)   ((dev_priv)->info.has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
@@ -3374,7 +3376,8 @@ i915_gem_object_get_dma_address(struct 
drm_i915_gem_object *obj,
unsigned long n);
 
 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
-struct sg_table *pages);
+struct sg_table *pages,
+unsigned int sg_mask);
 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
 
 static inline int __must_check
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9335f487400e..b1b1d8ce46f7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -163,7 +163,8 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void 
*data,
 }
 
 static struct sg_table *
-i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
+i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj,
+  unsigned int *sg_mask)
 {
struct address_space *mapping = obj->base.filp->f_mapping;
drm_dma_handle_t *phys;
@@ -223,6 +224,8 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object 
*obj)
sg->offset = 0;
sg->length = obj->base.size;
 
+   *sg_mask = sg->length;
+
sg_dma_address(sg) = phys->busaddr;
sg_dma_len(sg) = obj->base.size;
 
@@ -2298,6 +2301,8 @@ void __i915_gem_object_put_pages(struct 
drm_i915_gem_object *obj,
if (!IS_ERR(pages))
obj->ops->put_pages(obj, pages);
 
+   obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
+
 unlock:
mutex_unlock(>mm.lock);
 }
@@ -2329,7 +2334,8 @@ static bool i915_sg_trim(struct sg_table *orig_st)
 }
 
 static struct sg_table *
-i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
+i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
+ unsigned int *sg_mask)
 {
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
const unsigned long page_count = obj->base.size / PAGE_SIZE;
@@ -2376,6 +2382,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
 
sg = st->sgl;
st->nents = 0;
+   *sg_mask = 0;
for (i = 0; i < page_count; i++) {
const unsigned int shrink[] = {
I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | 
I915_SHRINK_PURGEABLE,
@@ -2428,8 +2435,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
if (!i ||
sg->length >= max_segment ||
page_to_pfn(page) != last_pfn + 1) {
-   if (i)
+   if (i) {
+   *sg_mask |= sg->length;
sg = sg_next(sg);
+   }
st->nents++;
sg_set_page(sg, page, PAGE_SIZE, 0);
} else {
@@ -2440,8 +2449,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object 
*obj)
/* Check that the i965g/gm workaround works. */
WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x0010UL));
}
-   if 

[Intel-gfx] [PATCH 03/21] drm/i915/gemfs: enable THP

[Matthew Auld]

Enable transparent-huge-pages through gemfs by mounting with
huge=within_size.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gemfs.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gemfs.c 
b/drivers/gpu/drm/i915/i915_gemfs.c
index 168d0bd98f60..999f0b6a2d64 100644
--- a/drivers/gpu/drm/i915/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 
 #include "i915_drv.h"
 #include "i915_gemfs.h"
@@ -41,6 +42,20 @@ int i915_gemfs_init(struct drm_i915_private *i915)
if (IS_ERR(gemfs))
return PTR_ERR(gemfs);
 
+   if (has_transparent_hugepage()) {
+   struct super_block *sb = gemfs->mnt_sb;
+   char options[] = "huge=within_size";
+   int flags = 0;
+
+   /* We don't consider failure to remount fatal, since this should
+* only ever attempt to modify the mount options of the sb, and
+* so should always leave us with a working mount upon failure.
+* Hence decoupling this from the actual kern_mount is probably
+* advisable.
+*/
+   WARN_ON(sb->s_op->remount_fs(sb, , options));
+   }
+
i915->mm.gemfs = gemfs;
 
return 0;
-- 
2.13.3

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[Intel-gfx] [PATCH 07/21] drm/i915: align the vma start to the largest gtt page size

[Matthew Auld]

For the 48b PPGTT try to align the vma start address to the required
page size boundary to guarantee we use said page size in the gtt. If we
are dealing with multiple page sizes, we can't guarantee anything and
just align to the largest. For soft pinning and objects which need to be
tightly packed into the lower 32bits we don't force any alignment.

v2: various improvements suggested by Chris

v3: use set_pages and better placement of page_sizes

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c |  8 
 drivers/gpu/drm/i915/i915_vma.c | 12 
 drivers/gpu/drm/i915/i915_vma.h |  1 +
 3 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0d0b529c77c4..385cd85f47bb 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -221,6 +221,9 @@ static int ppgtt_set_pages(struct i915_vma *vma)
 
vma->pages = vma->obj->mm.pages;
 
+   vma->page_sizes.phys = vma->obj->mm.page_sizes.phys;
+   vma->page_sizes.sg = vma->obj->mm.page_sizes.sg;
+
return 0;
 }
 
@@ -233,6 +236,8 @@ static void clear_pages(struct i915_vma *vma)
kfree(vma->pages);
}
vma->pages = NULL;
+
+   memset(>page_sizes, 0, sizeof(struct i915_page_sizes));
 }
 
 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
@@ -2466,6 +2471,9 @@ static int ggtt_set_pages(struct i915_vma *vma)
if (ret)
return ret;
 
+   vma->page_sizes.phys = vma->obj->mm.page_sizes.phys;
+   vma->page_sizes.sg = vma->obj->mm.page_sizes.sg;
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index c8d1b98cc260..212da056ef7d 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -493,6 +493,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 
alignment, u64 flags)
if (ret)
goto err_clear;
} else {
+   /* We only support huge gtt pages through the 48b PPGTT,
+* however we also don't want to force any alignment for
+* objects which need to be tightly packed into the low 32bits.
+*/
+   if (end > (1ULL << 32) &&
+   vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
+   u64 page_alignment =
+   rounddown_pow_of_two(vma->page_sizes.sg);
+
+   alignment = max(alignment, page_alignment);
+   }
+
ret = i915_gem_gtt_insert(vma->vm, >node,
  size, alignment, obj->cache_level,
  start, end, flags);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 4a673fc1a432..58256aec35f8 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -55,6 +55,7 @@ struct i915_vma {
void __iomem *iomap;
u64 size;
u64 display_alignment;
+   struct i915_page_sizes page_sizes;
 
u32 fence_size;
u32 fence_alignment;
-- 
2.13.3

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[Intel-gfx] [PATCH 04/21] drm/i915: introduce page_size_mask to dev_info

[Matthew Auld]

In preparation for huge gtt pages expose a page_size_mask as part of the
device info, to indicate the page sizes supported by the HW.  Currently
only 4K is supported.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Mika Kuoppala 
Cc: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/i915_gem_gtt.h  |  8 +++-
 drivers/gpu/drm/i915/i915_pci.c  | 20 
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  3 +++
 4 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4a7ad8c1d015..10f52937edec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -843,6 +843,7 @@ struct intel_device_info {
enum intel_platform platform;
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
+   unsigned int page_size_mask; /* page sizes supported by the HW */
 #define DEFINE_FLAG(name) u8 name:1
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index b4e3aa7c0ce1..4c2f7d7c1e7d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,7 +42,13 @@
 #include "i915_gem_request.h"
 #include "i915_selftest.h"
 
-#define I915_GTT_PAGE_SIZE 4096UL
+#define I915_GTT_PAGE_SIZE_4K BIT(12)
+#define I915_GTT_PAGE_SIZE_64K BIT(16)
+#define I915_GTT_PAGE_SIZE_2M BIT(21)
+#define I915_GTT_PAGE_SIZE_1G BIT(30)
+
+#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
+
 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
 
 #define I915_FENCE_REG_NONE -1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 09d97e0990b7..b07fabf1cd4f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -56,6 +56,10 @@
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
 
 /* Keep in gen based order, and chronological order within a gen */
+
+#define GEN_DEFAULT_PAGE_SIZES \
+   .page_size_mask = I915_GTT_PAGE_SIZE_4K
+
 #define GEN2_FEATURES \
.gen = 2, .num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
@@ -64,6 +68,7 @@
.unfenced_needs_alignment = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+   GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i830_info = {
@@ -96,6 +101,7 @@ static const struct intel_device_info intel_i865g_info = {
.has_gmch_display = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+   GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i915g_info = {
@@ -158,6 +164,7 @@ static const struct intel_device_info intel_pineview_info = 
{
.has_gmch_display = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+   GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i965g_info = {
@@ -198,6 +205,7 @@ static const struct intel_device_info intel_gm45_info = {
.has_gmbus_irq = 1, \
.ring_mask = RENDER_RING | BSD_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+   GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
 
 static const struct intel_device_info intel_ironlake_d_info = {
@@ -222,6 +230,7 @@ static const struct intel_device_info intel_ironlake_m_info 
= {
.has_gmbus_irq = 1, \
.has_aliasing_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
+   GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
 
 static const struct intel_device_info intel_sandybridge_d_info = {
@@ -247,6 +256,7 @@ static const struct intel_device_info 
intel_sandybridge_m_info = {
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
+   GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
 
 static const struct intel_device_info intel_ivybridge_d_info = {
@@ -284,6 +294,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
.has_full_ppgtt = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.display_mmio_offset = VLV_DISPLAY_BASE,
+   GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_PIPEOFFSETS,
CURSOR_OFFSETS
 };
@@ -308,6 +319,7 @@ static const struct intel_device_info intel_haswell_info = {
 #define BDW_FEATURES \
HSW_FEATURES, \
BDW_COLORS, \
+   GEN_DEFAULT_PAGE_SIZES, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1, \
@@ -345,13 +357,18 @@ static const struct intel_device_info 
intel_cherryview_info = {
.has_full_ppgtt = 1,

[Intel-gfx] [PATCH 00/21] huge gtt pages

[Matthew Auld]

Some updates to the kselftests as per Chris' comments.

Matthew Auld (21):
  mm/shmem: introduce shmem_file_setup_with_mnt
  drm/i915: introduce simple gemfs
  drm/i915/gemfs: enable THP
  drm/i915: introduce page_size_mask to dev_info
  drm/i915: introduce page_size members
  drm/i915: introduce vm set_pages/clear_pages
  drm/i915: align the vma start to the largest gtt page size
  drm/i915: align 64K objects to 2M
  drm/i915: enable IPS bit for 64K pages
  drm/i915: disable GTT cache for 2M/1G pages
  drm/i915: support 1G pages for the 48b PPGTT
  drm/i915: support 2M pages for the 48b PPGTT
  drm/i915: support 64K pages for the 48b PPGTT
  drm/i915: accurate page size tracking for the ppgtt
  drm/i915/debugfs: include some gtt page size metrics
  drm/i915/selftests: huge page tests
  drm/i915/selftests: mix huge pages
  drm/i915: disable platform support for vGPU huge gtt pages
  drm/i915: enable platform support for 64K pages
  drm/i915: enable platform support for 2M pages
  drm/i915: enable platform support for 1G pages

 drivers/gpu/drm/i915/Makefile  |1 +
 drivers/gpu/drm/i915/i915_debugfs.c|   42 +-
 drivers/gpu/drm/i915/i915_drv.h|9 +-
 drivers/gpu/drm/i915/i915_gem.c|   98 +-
 drivers/gpu/drm/i915/i915_gem_dmabuf.c |   17 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c|  195 +++-
 drivers/gpu/drm/i915/i915_gem_gtt.h|   15 +-
 drivers/gpu/drm/i915/i915_gem_internal.c   |5 +-
 drivers/gpu/drm/i915/i915_gem_object.h |   30 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c |   13 +-
 drivers/gpu/drm/i915/i915_gem_userptr.c|   26 +-
 drivers/gpu/drm/i915/i915_gemfs.c  |   67 ++
 drivers/gpu/drm/i915/i915_gemfs.h  |   34 +
 drivers/gpu/drm/i915/i915_pci.c|   25 +
 drivers/gpu/drm/i915/i915_reg.h|3 +
 drivers/gpu/drm/i915/i915_vma.c|   49 +-
 drivers/gpu/drm/i915/i915_vma.h|1 +
 drivers/gpu/drm/i915/intel_pm.c|9 +-
 drivers/gpu/drm/i915/selftests/huge_gem_object.c   |4 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c| 1170 
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c  |3 +-
 .../gpu/drm/i915/selftests/i915_live_selftests.h   |1 +
 .../gpu/drm/i915/selftests/i915_mock_selftests.h   |1 +
 drivers/gpu/drm/i915/selftests/mock_gem_device.c   |   16 +-
 drivers/gpu/drm/i915/selftests/mock_gtt.c  |   11 +-
 drivers/gpu/drm/i915/selftests/scatterlist.c   |   15 +
 include/linux/shmem_fs.h   |2 +
 mm/shmem.c |   30 +-
 28 files changed, 1797 insertions(+), 95 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_gemfs.c
 create mode 100644 drivers/gpu/drm/i915/i915_gemfs.h
 create mode 100644 drivers/gpu/drm/i915/selftests/huge_pages.c

-- 
2.13.3

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[Intel-gfx] [PATCH 01/21] mm/shmem: introduce shmem_file_setup_with_mnt

[Matthew Auld]

We are planning to use our own tmpfs mnt in i915 in place of the
shm_mnt, such that we can control the mount options, in particular
huge=, which we require to support huge-gtt-pages. So rather than roll
our own version of __shmem_file_setup, it would be preferred if we could
just give shmem our mnt, and let it do the rest.

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Dave Hansen 
Cc: Kirill A. Shutemov 
Cc: Hugh Dickins 
Cc: linux...@kvack.org
---
 include/linux/shmem_fs.h |  2 ++
 mm/shmem.c   | 30 ++
 2 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h
index a7d6bd2a918f..27de676f0b63 100644
--- a/include/linux/shmem_fs.h
+++ b/include/linux/shmem_fs.h
@@ -53,6 +53,8 @@ extern struct file *shmem_file_setup(const char *name,
loff_t size, unsigned long flags);
 extern struct file *shmem_kernel_file_setup(const char *name, loff_t size,
unsigned long flags);
+extern struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt,
+   const char *name, loff_t size, unsigned long flags);
 extern int shmem_zero_setup(struct vm_area_struct *);
 extern unsigned long shmem_get_unmapped_area(struct file *, unsigned long addr,
unsigned long len, unsigned long pgoff, unsigned long flags);
diff --git a/mm/shmem.c b/mm/shmem.c
index b0aa6075d164..293964c1dc6d 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -4133,7 +4133,7 @@ static const struct dentry_operations anon_ops = {
.d_dname = simple_dname
 };
 
-static struct file *__shmem_file_setup(const char *name, loff_t size,
+static struct file *__shmem_file_setup(struct vfsmount *mnt, const char *name, 
loff_t size,
   unsigned long flags, unsigned int 
i_flags)
 {
struct file *res;
@@ -4142,8 +4142,8 @@ static struct file *__shmem_file_setup(const char *name, 
loff_t size,
struct super_block *sb;
struct qstr this;
 
-   if (IS_ERR(shm_mnt))
-   return ERR_CAST(shm_mnt);
+   if (IS_ERR(mnt))
+   return ERR_CAST(mnt);
 
if (size < 0 || size > MAX_LFS_FILESIZE)
return ERR_PTR(-EINVAL);
@@ -4155,8 +4155,8 @@ static struct file *__shmem_file_setup(const char *name, 
loff_t size,
this.name = name;
this.len = strlen(name);
this.hash = 0; /* will go */
-   sb = shm_mnt->mnt_sb;
-   path.mnt = mntget(shm_mnt);
+   sb = mnt->mnt_sb;
+   path.mnt = mntget(mnt);
path.dentry = d_alloc_pseudo(sb, );
if (!path.dentry)
goto put_memory;
@@ -4201,7 +4201,7 @@ static struct file *__shmem_file_setup(const char *name, 
loff_t size,
  */
 struct file *shmem_kernel_file_setup(const char *name, loff_t size, unsigned 
long flags)
 {
-   return __shmem_file_setup(name, size, flags, S_PRIVATE);
+   return __shmem_file_setup(shm_mnt, name, size, flags, S_PRIVATE);
 }
 
 /**
@@ -4212,11 +4212,25 @@ struct file *shmem_kernel_file_setup(const char *name, 
loff_t size, unsigned lon
  */
 struct file *shmem_file_setup(const char *name, loff_t size, unsigned long 
flags)
 {
-   return __shmem_file_setup(name, size, flags, 0);
+   return __shmem_file_setup(shm_mnt, name, size, flags, 0);
 }
 EXPORT_SYMBOL_GPL(shmem_file_setup);
 
 /**
+ * shmem_file_setup_with_mnt - get an unlinked file living in tmpfs
+ * @mnt: the tmpfs mount where the file will be created
+ * @name: name for dentry (to be seen in /proc//maps
+ * @size: size to be set for the file
+ * @flags: VM_NORESERVE suppresses pre-accounting of the entire object size
+ */
+struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt, const char *name,
+  loff_t size, unsigned long flags)
+{
+   return __shmem_file_setup(mnt, name, size, flags, 0);
+}
+EXPORT_SYMBOL_GPL(shmem_file_setup_with_mnt);
+
+/**
  * shmem_zero_setup - setup a shared anonymous mapping
  * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
  */
@@ -4231,7 +4245,7 @@ int shmem_zero_setup(struct vm_area_struct *vma)
 * accessible to the user through its mapping, use S_PRIVATE flag to
 * bypass file security, in the same way as shmem_kernel_file_setup().
 */
-   file = __shmem_file_setup("dev/zero", size, vma->vm_flags, S_PRIVATE);
+   file = shmem_kernel_file_setup("dev/zero", size, vma->vm_flags);
if (IS_ERR(file))
return PTR_ERR(file);
 
-- 
2.13.3

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[Intel-gfx] [PATCH 02/21] drm/i915: introduce simple gemfs

[Matthew Auld]

Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
moves us away from the shmemfs shm_mnt, and gives us the much needed
flexibility to do things like set our own mount options, namely huge=
which should allow us to enable the use of transparent-huge-pages for
our shmem backed objects.

v2: various improvements suggested by Joonas

v3: move gemfs instance to i915.mm and simplify now that we have
file_setup_with_mnt

Signed-off-by: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Dave Hansen 
Cc: Kirill A. Shutemov 
Cc: Hugh Dickins 
Cc: linux...@kvack.org
---
 drivers/gpu/drm/i915/Makefile|  1 +
 drivers/gpu/drm/i915/i915_drv.h  |  3 ++
 drivers/gpu/drm/i915/i915_gem.c  | 34 +++-
 drivers/gpu/drm/i915/i915_gemfs.c| 52 
 drivers/gpu/drm/i915/i915_gemfs.h| 34 
 drivers/gpu/drm/i915/selftests/mock_gem_device.c | 10 -
 6 files changed, 131 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_gemfs.c
 create mode 100644 drivers/gpu/drm/i915/i915_gemfs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f8227318dcaf..29e3cfdf56ce 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -46,6 +46,7 @@ i915-y += i915_cmd_parser.o \
  i915_gem_tiling.o \
  i915_gem_timeline.o \
  i915_gem_userptr.o \
+ i915_gemfs.o \
  i915_trace_points.o \
  i915_vma.o \
  intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c7456f4ed38..4a7ad8c1d015 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1467,6 +1467,9 @@ struct i915_gem_mm {
/** Usable portion of the GTT for GEM */
dma_addr_t stolen_base; /* limited to low memory (32-bit) */
 
+   /** tmpfs instance used for shmem backed objects */
+   struct vfsmount *gemfs;
+
/** PPGTT used for aliasing the PPGTT with the GTT */
struct i915_hw_ppgtt *aliasing_ppgtt;
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6faabf34f142..9335f487400e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,6 +35,7 @@
 #include "intel_drv.h"
 #include "intel_frontbuffer.h"
 #include "intel_mocs.h"
+#include "i915_gemfs.h"
 #include 
 #include 
 #include 
@@ -4314,6 +4315,25 @@ static const struct drm_i915_gem_object_ops 
i915_gem_object_ops = {
.pwrite = i915_gem_object_pwrite_gtt,
 };
 
+static int i915_gem_object_create_shmem(struct drm_device *dev,
+   struct drm_gem_object *obj,
+   size_t size)
+{
+   struct drm_i915_private *i915 = to_i915(dev);
+   struct file *filp;
+
+   drm_gem_private_object_init(dev, obj, size);
+
+   filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,
+VM_NORESERVE);
+   if (IS_ERR(filp))
+   return PTR_ERR(filp);
+
+   obj->filp = filp;
+
+   return 0;
+}
+
 struct drm_i915_gem_object *
 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
 {
@@ -4337,7 +4357,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, 
u64 size)
if (obj == NULL)
return ERR_PTR(-ENOMEM);
 
-   ret = drm_gem_object_init(_priv->drm, >base, size);
+   ret = i915_gem_object_create_shmem(_priv->drm, >base, size);
if (ret)
goto fail;
 
@@ -4913,7 +4933,13 @@ i915_gem_load_init_fences(struct drm_i915_private 
*dev_priv)
 int
 i915_gem_load_init(struct drm_i915_private *dev_priv)
 {
-   int err = -ENOMEM;
+   int err;
+
+   err = i915_gemfs_init(dev_priv);
+   if (err)
+   return err;
+
+   err = -ENOMEM;
 
dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
if (!dev_priv->objects)
@@ -4977,6 +5003,8 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
 err_objects:
kmem_cache_destroy(dev_priv->objects);
 err_out:
+   i915_gemfs_fini(dev_priv);
+
return err;
 }
 
@@ -4999,6 +5027,8 @@ void i915_gem_load_cleanup(struct drm_i915_private 
*dev_priv)
 
/* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
rcu_barrier();
+
+   i915_gemfs_fini(dev_priv);
 }
 
 int i915_gem_freeze(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c 
b/drivers/gpu/drm/i915/i915_gemfs.c
new file mode 100644
index ..168d0bd98f60
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby 

Re: [Intel-gfx] [PATCH] drm/i915: Handle msr read failure gracefully

[Chris Wilson]

Quoting Gabriel Krisman Bertazi (2017-07-25 19:19:22)
> When reading the i915_energy_uJ debugfs file, it tries to fetch
> MSR_RAPL_POWER_UNIT, which might not be available, like in a vm
> environment, causing the exception shown below.
> 
> We can easily prevent it by doing a rdmsrl_safe read instead, which will
> handle the exception, allowing us to abort the debugfs file read.
> 
> This was caught by the new igt@debugfs_test@read_all_entries testcase in
> the CI.
> 
>   unchecked MSR access error: RDMSR from 0x606 at rIP:0xa0078f66 
> (i915_energy_uJ+0x36/0xb0 [i915])
>   Call Trace:
>seq_read+0xdc/0x3a0
>full_proxy_read+0x4f/0x70
>__vfs_read+0x23/0x120
>? putname+0x4f/0x60
>? rcu_read_lock_sched_held+0x75/0x80
>? entry_SYSCALL_64_fastpath+0x5/0xb1
>vfs_read+0xa0/0x150
>SyS_read+0x44/0xb0
>entry_SYSCALL_64_fastpath+0x1c/0xb1
>   RIP: 0033:0x7f1f5e9f4500
>   RSP: 002b:7ffc77e65cf8 EFLAGS: 0246 ORIG_RAX: 
>   RAX: ffda RBX: 8146e003 RCX: 7f1f5e9f4500
>   RDX: 0200 RSI: 7ffc77e65d10 RDI: 0006
>   RBP: c97abf88 R08: 01eaff20 R09: 
>   R10:  R11: 0246 R12: 
>   R13: 0006 R14: 0005 R15: 01eb94db
>? __this_cpu_preempt_check+0x13/0x20
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101901
> Signed-off-by: Gabriel Krisman Bertazi 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index c25f42c60d61..770b2846fed9 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2791,7 +2791,11 @@ static int i915_energy_uJ(struct seq_file *m, void 
> *data)
>  
> intel_runtime_pm_get(dev_priv);
>  
> -   rdmsrl(MSR_RAPL_POWER_UNIT, power);
> +   if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, )) {
> +   intel_runtime_pm_put(dev_priv);
> +   return -ENODEV;
> +   }
> +
> power = (power & 0x1f00) >> 8;
> units = 100 / (1 << power); /* convert to uJ */
> power = I915_READ(MCH_SECP_NRG_STTS);

Just after this is a useless cast. Though it will be neater to kill the
(long long unsigned) and s/u64/unsigned long long/ so that we are
consistent with the rdmsrl_safe interface.

Also we should use 1u << power as we allow power to be 31, or better yet
use:

units = (power & 0x1f00) >> 8;
power = I915_READ(MCH_SECP_NRG_STTS);
power = (10 * power) >> units; /* convert to uJ */
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Handle msr read failure gracefully

[Patchwork]

== Series Details ==

Series: drm/i915: Handle msr read failure gracefully
URL   : https://patchwork.freedesktop.org/series/27884/
State : success

== Summary ==

Series 27884v1 drm/i915: Handle msr read failure gracefully
https://patchwork.freedesktop.org/api/1.0/series/27884/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-skl-gvtdvm) fdo#101901
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900) fdo#101705 +1

fdo#101901 https://bugs.freedesktop.org/show_bug.cgi?id=101901
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:449s
fi-blb-e6850 total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  
time:353s
fi-bsw-n3050 total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  
time:540s
fi-bxt-j4205 total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:520s
fi-byt-j1900 total:280  pass:256  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-byt-n2820 total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:486s
fi-glk-2atotal:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:602s
fi-hsw-4770  total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:437s
fi-hsw-4770r total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:419s
fi-ilk-650   total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  
time:410s
fi-ivb-3520m total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7500u total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:471s
fi-kbl-7560u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:576s
fi-kbl-r total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:588s
fi-pnv-d510  total:280  pass:224  dwarn:1   dfail:0   fail:0   skip:55  
time:568s
fi-skl-6260u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:460s
fi-skl-6700hqtotal:280  pass:263  dwarn:0   dfail:0   fail:0   skip:17  
time:588s
fi-skl-6700k total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:466s
fi-skl-6770hqtotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:473s
fi-skl-gvtdvmtotal:280  pass:267  dwarn:0   dfail:0   fail:0   skip:13  
time:439s
fi-skl-x1585ltotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:496s
fi-snb-2520m total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-snb-2600  total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  
time:403s

fb7cda75b61e4ab4243dad8a23475d1c39ccb333 drm-tip: 2017y-07m-25d-17h-49m-38s UTC 
integration manifest
2a71644c8889 drm/i915: Handle msr read failure gracefully

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5276/
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Re: [Intel-gfx] [PATCH v5] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Paulo Zanoni]

Em Qua, 2017-07-19 às 00:27 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
> 
> cfb_stride = ceiling[(at least plane width in pixels)/
>    (32 * compression limit factor)] * 8
> 
> v2: Minor fix for a build error
> v3: Fixed subject, register name and platform check (Ville)
> v4: Added WA details in comment (Paulo)
> v5:
>  - Read modified reg write to preserve other bit values (Paulo)
>  - Store modified stride value in reg_params (Paulo)
>  - Keep GLK out of the WA (Paulo)
> 
> Cc: Paulo Zanoni 
> Signed-off-by: Praveen Paneri 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_fbc.c | 19 +++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c712d01..9e65f34 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6710,6 +6710,9 @@ enum {
>  #define CHICKEN_MISC_2   _MMIO(0x42084)
>  #define  COMP_PWR_DOWN   (1 << 23)
>  
> +#define CHICKEN_MISC_4   _MMIO(0x4208c)
> +#define   FBC_STRIDE_OVERRIDE(1<<13)
> +
>  #define _CHICKEN_PIPESL_1_A  0x420b0
>  #define _CHICKEN_PIPESL_1_B  0x420b4
>  #define  HSW_FBCQ_DIS(1 << 22)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 860b8c2..251d3f4 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -288,9 +288,28 @@ static bool ilk_fbc_is_active(struct
> drm_i915_private *dev_priv)
>  static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  {
>   struct intel_fbc_reg_params *params = _priv->fbc.params;
> + struct intel_fbc_state_cache *cache = _priv-
> >fbc.state_cache;
>   u32 dpfc_ctl;
>   int threshold = dev_priv->fbc.threshold;
>  
> + /* Display WA #0529: skl, kbl, bxt but not for glk*/
> + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
> + u32 chicken_misc4 = I915_READ(CHICKEN_MISC_4);
> +
> + if (i915_gem_object_get_tiling(cache->vma->obj)

params->vma->obj


> + != I915_TILING_X) {
> + int cfb_stride = DIV_ROUND_UP(cache-
> >plane.src_w,
> +  (32 * threshold)) * 8;
> + params->fb.stride = cfb_stride;

Setting this here is too late. We need to do this in the same place as
we generate the other params.

> +
> + I915_WRITE(CHICKEN_MISC_4, chicken_misc4 |
> + FBC_STRIDE_OVERRIDE |
> cfb_stride);

This code is forgetting to mask the values it's going to replace.

> + } else {
> + I915_WRITE(CHICKEN_MISC_4, chicken_misc4 &
> + ~FBC_STRIDE_OVERRIDE);
> + }
> + }
> +
>   dpfc_ctl = 0;
>   if (IS_IVYBRIDGE(dev_priv))
>   dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence

[Navare, Manasi D]

Thanks for the review !

Manasi


Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu:
> The condition for setting the Loadgen Select bit of
> PORT_TX_DW4 register during DDI Vswing Sequence should be Bit rate <=6 
> GHz whereas the existing code checks only Bit Rate < 6GHz. This patch 
> fixes this condition.
> While at it also remove the redundant paranthesis.
> 
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing
> sequence.")
> Cc: Paulo Zanoni 
> Cc: Rodrigo Vivi 
> Signed-off-by: Manasi Navare 

Reviewed-by: Paulo Zanoni 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index efb1358..f4fbb39 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct 
> intel_encoder *encoder, u32 level)
>   val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
>   val &= ~LOADGEN_SELECT;
>  
> - if (((rate < 60) && (width == 4) && (ln >=
> 1))  ||
> - ((rate < 60) && (width < 4) && ((ln == 1) ||
> (ln == 2 {
> + if ((rate <= 60 && width == 4 && ln >= 1)  ||
> + (rate <= 60 && width < 4 && (ln == 1 || ln
> == 2))) {
>   val |= LOADGEN_SELECT;
>   }
>   I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
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[Intel-gfx] [PATCH] drm/i915: Handle msr read failure gracefully

[Gabriel Krisman Bertazi]

When reading the i915_energy_uJ debugfs file, it tries to fetch
MSR_RAPL_POWER_UNIT, which might not be available, like in a vm
environment, causing the exception shown below.

We can easily prevent it by doing a rdmsrl_safe read instead, which will
handle the exception, allowing us to abort the debugfs file read.

This was caught by the new igt@debugfs_test@read_all_entries testcase in
the CI.

  unchecked MSR access error: RDMSR from 0x606 at rIP:0xa0078f66 
(i915_energy_uJ+0x36/0xb0 [i915])
  Call Trace:
   seq_read+0xdc/0x3a0
   full_proxy_read+0x4f/0x70
   __vfs_read+0x23/0x120
   ? putname+0x4f/0x60
   ? rcu_read_lock_sched_held+0x75/0x80
   ? entry_SYSCALL_64_fastpath+0x5/0xb1
   vfs_read+0xa0/0x150
   SyS_read+0x44/0xb0
   entry_SYSCALL_64_fastpath+0x1c/0xb1
  RIP: 0033:0x7f1f5e9f4500
  RSP: 002b:7ffc77e65cf8 EFLAGS: 0246 ORIG_RAX: 
  RAX: ffda RBX: 8146e003 RCX: 7f1f5e9f4500
  RDX: 0200 RSI: 7ffc77e65d10 RDI: 0006
  RBP: c97abf88 R08: 01eaff20 R09: 
  R10:  R11: 0246 R12: 
  R13: 0006 R14: 0005 R15: 01eb94db
   ? __this_cpu_preempt_check+0x13/0x20

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101901
Signed-off-by: Gabriel Krisman Bertazi 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index c25f42c60d61..770b2846fed9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2791,7 +2791,11 @@ static int i915_energy_uJ(struct seq_file *m, void *data)
 
intel_runtime_pm_get(dev_priv);
 
-   rdmsrl(MSR_RAPL_POWER_UNIT, power);
+   if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, )) {
+   intel_runtime_pm_put(dev_priv);
+   return -ENODEV;
+   }
+
power = (power & 0x1f00) >> 8;
units = 100 / (1 << power); /* convert to uJ */
power = I915_READ(MCH_SECP_NRG_STTS);
-- 
2.11.0

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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence

[Paulo Zanoni]

Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu:
> The condition for setting the Loadgen Select bit of
> PORT_TX_DW4 register during DDI Vswing Sequence should be
> Bit rate <=6 GHz whereas the existing code checks only
> Bit Rate < 6GHz. This patch fixes this condition.
> While at it also remove the redundant paranthesis.
> 
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing
> sequence.")
> Cc: Paulo Zanoni 
> Cc: Rodrigo Vivi 
> Signed-off-by: Manasi Navare 

Reviewed-by: Paulo Zanoni 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index efb1358..f4fbb39 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct
> intel_encoder *encoder, u32 level)
>   val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
>   val &= ~LOADGEN_SELECT;
>  
> - if (((rate < 60) && (width == 4) && (ln >=
> 1))  ||
> - ((rate < 60) && (width < 4) && ((ln == 1) ||
> (ln == 2 {
> + if ((rate <= 60 && width == 4 && ln >= 1)  ||
> + (rate <= 60 && width < 4 && (ln == 1 || ln
> == 2))) {
>   val |= LOADGEN_SELECT;
>   }
>   I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Kernel PSR Fix-ups

[Patchwork]

== Series Details ==

Series: Kernel PSR Fix-ups
URL   : https://patchwork.freedesktop.org/series/27879/
State : failure

== Summary ==

Series 27879v1 Kernel PSR Fix-ups
https://patchwork.freedesktop.org/api/1.0/series/27879/revisions/1/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (fi-skl-6700hq)
pass   -> INCOMPLETE (fi-kbl-r)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-n2820) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:448s
fi-blb-e6850 total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  
time:363s
fi-bsw-n3050 total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  
time:529s
fi-bxt-j4205 total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:514s
fi-byt-j1900 total:280  pass:255  dwarn:1   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:486s
fi-hsw-4770  total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:439s
fi-hsw-4770r total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:420s
fi-ilk-650   total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  
time:415s
fi-ivb-3520m total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:499s
fi-ivb-3770  total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:480s
fi-kbl-7500u total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:468s
fi-kbl-7560u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:583s
fi-kbl-r total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-pnv-d510  total:280  pass:222  dwarn:3   dfail:0   fail:0   skip:55  
time:567s
fi-skl-6260u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:465s
fi-skl-6700hqtotal:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-skl-6700k total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-skl-6770hqtotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:483s
fi-skl-gvtdvmtotal:280  pass:266  dwarn:1   dfail:0   fail:0   skip:13  
time:436s
fi-skl-x1585ltotal:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:472s
fi-snb-2520m total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:550s
fi-snb-2600  total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  
time:406s
fi-glk-2a failed to connect after reboot

92845e5dff13907ccebff6b9ae742e793ddc6a74 drm-tip: 2017y-07m-25d-14h-41m-13s UTC 
integration manifest
a6ed5a05fa72 drm/i915/edp: Allow alternate fixed mode for eDP if available.
898075eedd5c drm/i915/edp: Be less aggressive about changing link config on eDP
0d851135ba98 drm/i915/psr: Account for sink CRC raciness on some panels
59a3c66e6c05 drm/i915/psr: Clean-up intel_enable_source_psr1()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5275/
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Re: [Intel-gfx] [PATCH v4 RESEND 0/4] Kernel PSR Fix-ups

[David Weinehall]

On Tue, Jul 25, 2017 at 09:48:07AM -0700, Jim Bride wrote:
> These patches, along with an upcoming series for IGT, enable our
> PSR IGT tests to run reliably once again on HSW, BDW, and SKL.
> The first change enables us to run the PSR tests on some RVP platforms
> whose panels have too slow of a setup time when running in their
> preferred mode.  The second fixes a minor problem with the way that
> we were initializing SRD_CTL that caused us to clobber a bit that we
> are not supposed to change in that register on SKL and KBL.  The third
> change re-introduces some changes to our link training code to be less
> aggressive about changing link state for eDP, because PSR depends on
> the link state being the same at PSR exit as it was at PSR entry.
> The fourth change greatly increases the reliability of reading the
> sink CRC generated by the eDP panel.
> 
> v2 Highlights:
>* Rebased to current drm-tip
>* Greatly reduced looping around trying to read sink CRC (Jani)
>* Reduce amount of changes in the sink CRC patch (Jani)
>* Field-wise init of EDP_PSR_MAX_SLEEP_TIME (Rodrigo)
>* Minor commit message / cover letter tweaks
> 
> v3:
>* Re-ordered patches to put reviewed patches first.
>* Rebased to current drm-tip
> 
> v4: 
>* Addressed review feedback (see patches for details)
>* Rebase

Is this a pure resend, or does it include any fixes on top of earlier
versions? As mentioned elsewhere I experienced issues with both your
previous patch series and the two before that one.

I'll run a new testrun with this series just in case (it might be that
the issues I noticed were caused by bad interaction with some other
component).


Kind regards, David Weinehall
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Re: [Intel-gfx] [PATCH i-g-t 2/3] configure.ac: Disable chamelium by default and add enable argument

[Lyude Paul]

I like this patch, however there's a mistake in it:

On Tue, 2017-07-25 at 15:48 +0300, Paul Kocialkowski wrote:
> Since the chamelium is not a very usual piece of hardware and
> requires
> pulling-in lots of specific dependencies, it makes sense to keep it
> disabled by default.
> 
> An explicit --enable-chamelium argument is provided to enable it when
> necessary. This also leads to more predictable results than
> automatically enabling it when its dependencies are met.
> 
> Finally, whether chamelium support is enabled is printed by the
> information summary at end of the configure run.
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  configure.ac | 17 +
>  1 file changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index a6ab9e4a..17a226de 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -185,23 +185,23 @@ PKG_CHECK_MODULES(GSL, [gsl], [gsl=yes],
> [gsl=no])
>  AM_CONDITIONAL(HAVE_GSL, [test "x$gsl" = xyes])
>  
>  # for chamelium
> -AC_ARG_ENABLE(chamelium, AS_HELP_STRING([--disable-chamelium],
> -   [Enable building of chamelium libraries and tests
> (default: yes)]),
> -   [enable_chamelium=no], [enable_chamelium=yes])
> +AC_ARG_ENABLE(chamelium, AS_HELP_STRING([--enable-chamelium],
> +   [Enable building of chamelium libraries and tests
> (default: no)]),
> +   [enable_chamelium=yes], [enable_chamelium=no])
It appears you repeated my original mistake of switching the yes and no
parameters by accident :P. This causes passing --disable-chamelium to
result in enabling the chamelium tests instead of disabling them.

>  AM_CONDITIONAL(HAVE_CHAMELIUM, [test "x$enable_chamelium" = xyes])
>  if test "x$enable_chamelium" = xyes; then
>   PKG_CHECK_MODULES(XMLRPC, xmlrpc xmlrpc_util xmlrpc_client,
> [],
> -   [AC_MSG_ERROR([Failed to find xmlrpc,
> required by chamelium. Use --disable-chamelium to disable chamelium
> support.])])
> +   [AC_MSG_ERROR([Failed to find xmlrpc,
> required by chamelium.])])
>   PKG_CHECK_MODULES(PIXMAN, pixman-1, [],
> -   [AC_MSG_ERROR([Failed to find pixman,
> required by chamelium. Use --disable-chamelium to disable chamelium
> support.])])
> +   [AC_MSG_ERROR([Failed to find pixman,
> required by chamelium.])])
>   if test x"$udev" != xyes; then
> - AC_MSG_ERROR([Failed to find udev, required by
> chamelium. Use --disable-chamelium to disable chamelium support.])
> + AC_MSG_ERROR([Failed to find udev, required by
> chamelium.])
>   fi
>   if test x"$glib" != xyes; then
> - AC_MSG_ERROR([Failed to find glib, required by
> chamelium. Use --disable-chamelium to disable chamelium support.])
> + AC_MSG_ERROR([Failed to find glib, required by
> chamelium.])
>   fi
>   if test x"$gsl" != xyes; then
> - AC_MSG_ERROR([Failed to find gsl, required by
> chamelium. Use --disable-chamelium to disable chamelium support.])
> + AC_MSG_ERROR([Failed to find gsl, required by
> chamelium.])
>   fi
>  
>   AC_DEFINE(HAVE_CHAMELIUM, 1, [Enable Chamelium support])
> @@ -404,6 +404,7 @@ echo "Intel GPU tools"
>  echo ""
>  echo " • Tests:"
>  echo "   Build tests: ${BUILD_TESTS}"
> +echo "   Chamelium tests: ${enable_chamelium}"
>  echo "   Compile prime tests: ${NOUVEAU}"
>  echo "   Print stack traces : ${with_libunwind}"
>  echo "   Debug flags: ${DEBUG_CFLAGS}"
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [PATCH i-g-t 3/3] README: Add information about chamelium dependencies

[Lyude Paul]

R-b'd and pushed, thanks!

On Tue, 2017-07-25 at 15:48 +0300, Paul Kocialkowski wrote:
> This adds a list of dependencies required to build chamelium support,
> so that what needs to be installed to get it going is more obvious.
> 
> As done previously in the file, the list is relevant for Debian and
> its
> derivatives but should provide a template for other systems as well.
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  README | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/README b/README
> index 26171a17..d1ea9529 100644
> --- a/README
> +++ b/README
> @@ -131,7 +131,7 @@ Requirements
>  
>  
>  This is a non-exhaustive list of package dependencies required for
> building
> -everything (package names may vary):
> +the default configuration (package names may vary):
>  
>   gtk-doc-tools
>   libcairo2-dev
> @@ -144,6 +144,15 @@ everything (package names may vary):
>   x11proto-dri2-dev
>   xutils-dev
>  
> +The following dependencies are required for building chamelium
> support
> +(package names may vary):
> +
> + libxmlrpc-core-c3-dev
> + libpixman-1-dev
> + libudev-dev
> + libglib2.0-dev
> + libgsl-dev
> +
>  Releases for maintainers
>  
>  
-- 
Cheers,
Lyude
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Re: [Intel-gfx] [PATCH i-g-t 1/3] configure.ac: Make udev a dependency for chamelium

[Lyude Paul]

R-b'd and pushed, thanks!

On Tue, 2017-07-25 at 15:48 +0300, Paul Kocialkowski wrote:
> Chamelium testing has a hard dependency on udev. This makes this
> dependency explicit in configure instead of failing the build when it
> is missing.
> 
> Signed-off-by: Paul Kocialkowski 
> ---
>  configure.ac | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/configure.ac b/configure.ac
> index dec3e923..a6ab9e4a 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -194,6 +194,9 @@ if test "x$enable_chamelium" = xyes; then
> [AC_MSG_ERROR([Failed to find xmlrpc,
> required by chamelium. Use --disable-chamelium to disable chamelium
> support.])])
>   PKG_CHECK_MODULES(PIXMAN, pixman-1, [],
> [AC_MSG_ERROR([Failed to find pixman,
> required by chamelium. Use --disable-chamelium to disable chamelium
> support.])])
> + if test x"$udev" != xyes; then
> + AC_MSG_ERROR([Failed to find udev, required by
> chamelium. Use --disable-chamelium to disable chamelium support.])
> + fi
>   if test x"$glib" != xyes; then
>   AC_MSG_ERROR([Failed to find glib, required by
> chamelium. Use --disable-chamelium to disable chamelium support.])
>   fi
-- 
Cheers,
Lyude
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[Intel-gfx] [PATCH v4 RESEND 1/4] drm/i915/psr: Clean-up intel_enable_source_psr1()

[Jim Bride]

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

v2: * Do a field-wise init on EDP_PSR_MAX_SLEEP_TIME even though we
  always set it to the max value. (Rodrigo)
* Rebase
v3-v4: * Rebase

Cc: Rodrigo Vivi 
Cc: Paulo Zanoni 
Cc: Wayne Boyer 
Cc: Jani Nikula 
Reviewed-by: Rodrigo Vivi 
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_psr.c | 21 +++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c712d01..3e62429 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3789,18 +3789,22 @@ enum {
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES  (1<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES  (2<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES  (3<<25)
+#define   EDP_PSR_MAX_SLEEP_TIME_MASK   (0x1f<<20)
 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us (3<<8)
+#define   EDP_PSR_TP1_TIME_MASK (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us   (0<<4)
 #define   EDP_PSR_TP1_TIME_100us   (1<<4)
 #define   EDP_PSR_TP1_TIME_2500us  (2<<4)
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK   (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..132987b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,32 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
 * with the 5 or 6 idle patterns.
 */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-   uint32_t val = EDP_PSR_ENABLE;
+   uint32_t val = I915_READ(EDP_PSR_CTL);
 
+   val |= EDP_PSR_ENABLE;
+
+   val &= ~EDP_PSR_MAX_SLEEP_TIME_MASK;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+   val &= ~EDP_PSR_IDLE_FRAME_MASK;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+   val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (dev_priv->psr.link_standby)
+   if (dev_priv->psr.link_standby) {
val |= EDP_PSR_LINK_STANDBY;
 
+   /* SFU should only be enabled with link standby, but for
+* now we do not support it. */
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   } else {
+   val &= ~EDP_PSR_LINK_STANDBY;
+   val &= ~BDW_PSR_SINGLE_FRAME;
+   }
+
+   val &= ~EDP_PSR_TP1_TIME_MASK;
if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
val |= EDP_PSR_TP1_TIME_2500us;
else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TIME_0us;
 
+   val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR_TP2_TP3_TIME_2500us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +325,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+   val &= ~EDP_PSR_TP1_TP3_SEL;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

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[Intel-gfx] [PATCH v4 RESEND 3/4] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were

5fa836a9d859 ("drm/i915: DP link training optimization")
4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by

34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on

commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
Author: Mika Kahola 
Date:   Wed Apr 29 09:17:39 2015 +0300
drm/i915: eDP link training optimization

puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier reading. (Chris)
* Rebase

Cc: Chris Wilson 
Cc: Rodrigo Vivi 
Cc: Paulo Zanoni 
Cc: Manasi D Navare 
Cc: Mika Kahola 
Cc: Jani Nikula 
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 +++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  2 ++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c90ca1c..7c0e530 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -106,7 +106,7 @@ static const int default_rates[] = { 162000, 27, 54 
};
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
-static bool is_edp(struct intel_dp *intel_dp)
+bool is_edp(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 
@@ -4738,6 +4738,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6008,6 +6009,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index b79c1c0..d12200d 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock recovery in the specified configuration.
+*/
+   intel_dp->train_set_valid = false;
+
voltage_tries = 1;
max_vswing_tries = 0;
   

[Intel-gfx] [PATCH v4 RESEND 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

[Jim Bride]

According to the eDP spec, when the count field in TEST_SINK_MISC
increments then the six bytes of sink CRC information in the DPCD
should be valid.  Unfortunately, this doesn't seem to be the case
on some panels, and as a result we get some incorrect and inconsistent
values from the sink CRC DPCD locations at times.  This problem exhibits
itself more on faster processors (relative failure rates HSW < SKL < KBL.)
In order to try and account for this, we try a lot harder to read the sink
CRC until we get consistent values twice in a row before returning what we
read and delay for a time before trying to read.  We still see some
occasional failures, but reading the sink CRC is much more reliable,
particularly on SKL and KBL, with these changes than without.

v2: * Reduce number of retries when reading the sink CRC (Jani)
* Refactor to minimize changes to the code (Jani)
* Rebase
v3: * Rebase
v4: * Switch from do-while to for loop when reading CRC values (Jani)
* Rebase
Cc: Rodrigo Vivi 
Cc: Paulo Zanoni 
Cc: Jani Nikula 
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/intel_dp.c | 33 ++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2d42d09..c90ca1c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3906,6 +3906,11 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf;
int count, ret;
int attempts = 6;
+   u8 old_crc[6];
+
+   if (crc == NULL) {
+   return -ENOMEM;
+   }
 
ret = intel_dp_sink_crc_start(intel_dp);
if (ret)
@@ -3929,11 +3934,33 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
goto stop;
}
 
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
-   ret = -EIO;
-   goto stop;
+   /*
+* Sometimes it takes a while for the "real" CRC values to land in
+* the DPCD, so try several times until we get two reads in a row
+* that are the same.  If we're an eDP panel, delay between reads
+* for a while since the values take a bit longer to propagate.
+*/
+   for (attempts = 0; attempts < 6; attempts++) {
+   intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
+
+   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR,
+crc, 6) < 0) {
+   ret = -EIO;
+   break;
+   }
+
+   if (attempts && memcmp(old_crc, crc, 6) == 0)
+   break;
+   memcpy(old_crc, crc, 6);
+
+   if (is_edp(intel_dp))
+   usleep_range(2, 25000);
}
 
+   if (attempts == 6) {
+   DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
+   ret = -ETIMEDOUT;
+   }
 stop:
intel_dp_sink_crc_stop(intel_dp);
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH v4 RESEND 0/4] Kernel PSR Fix-ups

[Jim Bride]

These patches, along with an upcoming series for IGT, enable our
PSR IGT tests to run reliably once again on HSW, BDW, and SKL.
The first change enables us to run the PSR tests on some RVP platforms
whose panels have too slow of a setup time when running in their
preferred mode.  The second fixes a minor problem with the way that
we were initializing SRD_CTL that caused us to clobber a bit that we
are not supposed to change in that register on SKL and KBL.  The third
change re-introduces some changes to our link training code to be less
aggressive about changing link state for eDP, because PSR depends on
the link state being the same at PSR exit as it was at PSR entry.
The fourth change greatly increases the reliability of reading the
sink CRC generated by the eDP panel.

v2 Highlights:
   * Rebased to current drm-tip
   * Greatly reduced looping around trying to read sink CRC (Jani)
   * Reduce amount of changes in the sink CRC patch (Jani)
   * Field-wise init of EDP_PSR_MAX_SLEEP_TIME (Rodrigo)
   * Minor commit message / cover letter tweaks

v3:
   * Re-ordered patches to put reviewed patches first.
   * Rebased to current drm-tip

v4: 
   * Addressed review feedback (see patches for details)
   * Rebase
   
Jim Bride (4):
  drm/i915/psr: Clean-up intel_enable_source_psr1()
  drm/i915/psr: Account for sink CRC raciness on some panels
  drm/i915/edp: Be less aggressive about changing link config on eDP
  drm/i915/edp: Allow alternate fixed mode for eDP if available.

 drivers/gpu/drm/i915/i915_reg.h   |  4 ++
 drivers/gpu/drm/i915/intel_dp.c   | 71 +++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++
 drivers/gpu/drm/i915/intel_dsi.c  |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c  |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c |  3 +-
 drivers/gpu/drm/i915/intel_panel.c|  6 +++
 drivers/gpu/drm/i915/intel_psr.c  | 21 +++-
 9 files changed, 113 insertions(+), 15 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH v4 RESEND 4/4] drm/i915/edp: Allow alternate fixed mode for eDP if available.

[Jim Bride]

Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate.  Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.

v2 and v3: Rebase
v4: * Fix up some leaky mode stuff (Chris)
* Rebase

Cc: Rodrigo Vivi 
Cc: Paulo Zanoni 
Cc: Jani Nikula 
Cc: Chris Wilson 
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/intel_dp.c| 34 +-
 drivers/gpu/drm/i915/intel_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
 drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  3 ++-
 drivers/gpu/drm/i915/intel_panel.c |  6 ++
 6 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c0e530..c9db0e6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,19 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
return bpp;
 }
 
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+  struct drm_display_mode *m2)
+{
+   return (m1->hdisplay == m2->hdisplay &&
+   m1->hsync_start == m2->hsync_start &&
+   m1->hsync_end == m2->hsync_end &&
+   m1->htotal == m2->htotal &&
+   m1->vdisplay == m2->vdisplay &&
+   m1->vsync_start == m2->vsync_start &&
+   m1->vsync_end == m2->vsync_end &&
+   m1->vtotal == m2->vtotal);
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1665,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio == 
HDMI_AUDIO_ON;
 
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-   intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
-  adjusted_mode);
+   struct drm_display_mode *panel_mode =
+   intel_connector->panel.alt_fixed_mode;
+   struct drm_display_mode *req_mode = _config->base.mode;
+
+   if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+   panel_mode = intel_connector->panel.fixed_mode;
+
+   drm_mode_debug_printmodeline(panel_mode);
+
+   intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5810,6 +5831,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+   struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5865,13 +5887,14 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
}
intel_connector->edid = edid;
 
-   /* prefer fixed mode from EDID if available */
+   /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, >probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
-   break;
+   } else if (!alt_fixed_mode) {
+   alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
 
@@ -5908,7 +5931,8 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
  pipe_name(pipe));
}
 
-   intel_panel_init(_connector->panel, fixed_mode, downclock_mode);
+   intel_panel_init(_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
intel_panel_setup_backlight(connector, pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e45163a..3bd11e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,6 +265,7 @@ struct intel_encoder {
 
 struct intel_panel {
struct drm_display_mode *fixed_mode;
+   struct drm_display_mode *alt_fixed_mode;
struct drm_display_mode *downclock_mode;
 
/* backlight 

Re: [Intel-gfx] [PATCH v7 3/3] drm/i915: Implement I915_PERF_ADD/REMOVE_CONFIG interface

[Lionel Landwerlin]

On 25/07/17 12:30, Datczuk, Andrzej wrote:

I think you looked only at the changes prepared previously by Matthew and just 
ported by me. I made a change on top of it in a third patch to alight the 
whitelist with MDAPI needs.
The change you're looking for is "Subject: [PATCH 3/3] drm/i915: extended oa reg 
addresses whitelist". To make it easier below is the list:


Thanks for the list!



Perf modified   Perf modified 
Name
<0x2710,2b00), 0x2b04b_counter


0x2b00 & 0x2b04 are managed by the kernel, I don't think we should let 
userspace touch those at the same time.

This could only lead to painful debug when a bug appears.


0xE458, 0xE45C, 0xE558, 0xE55C, 0xE658, 0xE65C, 0xE758  flex


 We should be good on the flex registers.


<0x9800,0x9ec0>   mux


Looking at the internal code base, I can't see anything using those 
registers.

We have the kernel program GDT_CHICKEN_BITS (0x9840) to enable NOA.
If that's all we're doing from userspace, we can probably let the kernel 
do it.



<0x25100,0x2ff90> mux


Those should be in (HSW specific).


<0xD04,0xD2C>, 0xE180 mux


0xe180 is named HALF_SLICE_CHICKEN2 and touched by the kernel.
Would it be possible to provide some explanation as to why it's modified?
I'm concerned we're going to break something if we touch it from 
userspace, potentially dropping what the kernel put in.



<0x182300,0x1823A4>   mux


Should be in (CHV specific).


0x20CC  mux


Can you expand why we need this?
I don't see any internal configs using it.


<0x91B8,0x91C8>   mux


I guess we can whitelist those.
Again, I can't see anyone actually writing them, just reading.



Regards,
Andrzej

-Original Message-
From: Landwerlin, Lionel G
Sent: Tuesday, July 25, 2017 12:52 PM
To: Datczuk, Andrzej ; 
intel-gfx@lists.freedesktop.org
Cc: Auld, Matthew ; ch...@chris-wilson.co.uk
Subject: Re: [PATCH v7 3/3] drm/i915: Implement I915_PERF_ADD/REMOVE_CONFIG 
interface

Hi Andrzej,

Thanks for the feedback. Can you tell me if that following changes are correct?

Cheers,

-
Lionel

On 25/07/17 10:06, Datczuk, Andrzej wrote:

Hi Lionel,

What about the corrected whitelist I sent you before? Without allowing those 
registers the patch for MDAPI is basically useless.
FYI The whitelist from the patches I sent you contained merged ranges for 
gen7-9 platforms.

Regards,
Andrzej

   
+static bool gen8_is_valid_flex_addr(struct drm_i915_private

+*dev_priv,
+u32 addr) {
+   static const i915_reg_t flex_eu_regs[] = {
+   EU_PERF_CNTL0,
+   EU_PERF_CNTL1,
+   EU_PERF_CNTL2,
+   EU_PERF_CNTL3,
+   EU_PERF_CNTL4,
+   EU_PERF_CNTL5,
+   EU_PERF_CNTL6,
+   };
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
+   if (flex_eu_regs[i].reg == addr)
+   return true;
+   }
+   return false;
+}
+
+static bool gen7_is_valid_b_counter_addr(struct drm_i915_private
+*dev_priv, u32 addr) {
+   return (addr >= 0x2380 && addr <= 0x27ac); }

Here I dropped 0x2b20 because it's an interruption register. It probably should 
be left to its default value and only managed by the kernel.

Though I made a mistake as this should be addr >= 0x2374 && addr <= 0x27ac.


+
+static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+   return addr == NOA_WRITE.reg ||
+   (addr >= 0xd0c && addr <= 0xd3c) ||

Arg, missing 0xd24/0xd28 here...


+   (addr >= 0x25100 && addr <= 0x2FB9C); }
+
+static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+   return (addr >= 0x25100 && addr <= 0x2FF90) ||
+   gen7_is_valid_mux_addr(dev_priv, addr); }
+
+static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+   return (addr >= 0x182300 && addr <= 0x1823A4) ||
+   gen7_is_valid_mux_addr(dev_priv, addr); }
+
+



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Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add helper to detect whether EDID changed

[Daniel Vetter]

On Tue, Jul 25, 2017 at 03:18:04PM +0300, Paul Kocialkowski wrote:
> On Tue, 2017-07-25 at 10:16 +0200, Daniel Vetter wrote:
> > On Tue, Jul 25, 2017 at 10:58:55AM +0300, Paul Kocialkowski wrote:
> > > On Tue, 2017-07-25 at 09:34 +0200, Daniel Vetter wrote:
> > > > On Tue, Jul 25, 2017 at 9:25 AM, Paul Kocialkowski
> > > >  wrote:
> > > > > On Tue, 2017-07-25 at 08:53 +0200, Daniel Vetter wrote:
> > > > > > On Mon, Jul 24, 2017 at 05:54:46PM +0300, Paul Kocialkowski
> > > > > > wrote:
> > > > > > > This adds a common drm helper to detect whether the EDID
> > > > > > > changed
> > > > > > > from
> > > > > > > the last known cached one. This is useful help detect that a
> > > > > > > monitor
> > > > > > > was
> > > > > > > changed during a suspend/resume cycle.
> > > > > > > 
> > > > > > > When that happens (a monitor is replaced by another one
> > > > > > > during
> > > > > > > suspend),
> > > > > > > no hotplug event will be triggered so the change will not be
> > > > > > > caught
> > > > > > > at
> > > > > > > resume time. Detecting that the EDID changed allows
> > > > > > > detecting
> > > > > > > it.
> > > > > > > 
> > > > > > > Signed-off-by: Paul Kocialkowski  > > > > > > tel.
> > > > > > > com>
> > > > > > 
> > > > > > I can't find the older mails I've typed about this, but the
> > > > > > plan
> > > > > > we've
> > > > > > discussed a while back was:
> > > > > > - Add a generational counter to each connector, maybe even
> > > > > > expose
> > > > > > it
> > > > > > to
> > > > > >   userspace.
> > > > > > 
> > > > > > - Increment that counter every time something changed, e.g.
> > > > > >   connector->status in the propbe helpers, or when attaching a
> > > > > > new
> > > > > > edid
> > > > > >   with the set_edid helper.
> > > > > > 
> > > > > > - Tada, no changes needed to drivers, and easily extensible to
> > > > > > other
> > > > > >   things than edid!
> > > > > 
> > > > > I don't see how it solves the problem here though. After a
> > > > > suspend/resume cycle, there is simply no indication that
> > > > > anything
> > > > > has
> > > > > changed when a monitor was replaced by another one, so I don't
> > > > > see
> > > > > how
> > > > > adding a counter in the mix would help.
> > > > > 
> > > > > Could you provide more details about the reasoning? I feel like
> > > > > I'm
> > > > > missing something here.
> > > > 
> > > > Your bug doesn't just exist over s/r, it's just much easier to
> > > > observe
> > > > in s/r since users can take however long they want to with
> > > > plugging in
> > > > a different monitor. But the same issue exists e.g. when we go
> > > > from
> > > > hpd to polling because too much noise on the line.
> > > > 
> > > > Wrt the suspend/resume issue: What we need to do on resume is do a
> > > > full reprobe of all outputs, in an async worker. Telling userspace
> > > > to
> > > > do this by sending an uevent was the cheapest way, but it'd be
> > > > better
> > > > if the kernel could do that asynchronously and inform userspace
> > > > about
> > > > the exact changes. And there's more to reprobe than just the edid,
> > > > and
> > > > we don't want to re-invent a separate reprobe path just for resume
> > > > like you start in your patch series. So yeah my plan was missing:
> > > > 
> > > > - force a full async reprobe after resume (maybe we could reuse
> > > > the
> > > > poll worker for that as a one-shot).
> > > 
> > > First off, I definitely agree we need a way to tell userspace
> > > exactly
> > > what has happened. I wanted to start a discussion about that in i-g-
> > > t
> > > patch "Unrelated hotplug uevent masking out actual test result" but
> > > it
> > > didn't get much traction. For testing purposes, it is unacceptable
> > > that
> > > userspace only gets notified that "something happened".
> > > 
> > > Still, as far as I know, userspace is expected to ask for a full
> > > reprobe
> > > when something has changed, and that is apparently part of the DRM
> > > spec,
> > > so we can't expect that it could query for an update on "only the
> > > things
> > > that changed".
> > 
> > We can update that spec in a backwards compatible way. E.g. we can ask
> > for
> > the current properties without forcing a reprobe (won't even call down
> > into the driver), and userspace could use that to check which
> > connector
> > has an incremented epoche counter since the last time it sampled
> > things.
> > Then it can reprobe just that one.
> > 
> > Old userspace wouldn't know about this, and would keep working as-is.
> 
> So the level of detail you're aiming at providing userspace is
> "connector foo changed" then? I agree it is better than the current
> "some connector(s) changed", but what I'd like to see for proper testing
> is a way to find out "bar for connector foo changed".

If you want taht level of detail you need introspection in a in-kernel
selftest I think. We'd need to rather massively change/extend the 

Re: [Intel-gfx] [PATCH i-g-t 2/2] tests/drv_suspend: Add subtests to check that forcewake is kept after resume

[Chris Wilson]

Quoting Ewelina Musial (2017-07-25 16:26:09)
> In some cases we observed that forcewake isn't kept after
> resume and checking RC6 residency is a simple way to verify that.
> If forcewake is kept after resume residency should be constant.
> 
> Cc: Lukasz Fiedorowicz 
> Cc: Radoslaw Szwichtenberg 
> Cc: Michal Winiarski 
> Signed-off-by: Ewelina Musial 
> ---
>  tests/drv_suspend.c | 36 
>  1 file changed, 32 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/drv_suspend.c b/tests/drv_suspend.c
> index 2e39f20a..0c576055 100644
> --- a/tests/drv_suspend.c
> +++ b/tests/drv_suspend.c
> @@ -36,6 +36,9 @@
>  #include 
>  #include 
>  #include 
> +#include "igt_sysfs.h"
> +#include "igt_aux.h"
> +#include 
>  
>  #include 
>  
> @@ -160,8 +163,9 @@ test_sysfs_reader(bool hibernate)
> igt_stop_helper();
>  }
>  
> +#define SLEEP_DURATION 3
>  static void
> -test_forcewake(int fd, bool hibernate)
> +test_forcewake(int fd, bool hibernate, bool residency)
>  {
> int fw_fd;
>  
> @@ -174,8 +178,26 @@ test_forcewake(int fd, bool hibernate)
> else
> igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
>   SUSPEND_TEST_NONE);
> +if (residency)
> +{
> +int sysfs;
> +uint32_t residency_pre, residency_post;
>  
> -   close (fw_fd);
> +sysfs = igt_sysfs_open(fd, NULL);
> +igt_assert_lte(0, sysfs);
> +sleep(1); // time to fully resume

rc6 is not universal, failing just because it is not supported after
suspending/hibernate does not make for happy users.

You have the power to add additional sanity checks to the kernel and
report the failure via close() without resorting to indirect checks and
fragile assumptions.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t v3 0/5] Add Y-tiling support into IGTs

[Praveen Paneri]

On Tuesday 25 July 2017 08:48 PM, Paulo Zanoni wrote:

Em Ter, 2017-07-18 às 22:52 +0530, Praveen Paneri escreveu:

This series adds Y-tiled buffer creation support into IGT libraries
and
goes on to use this capability to add support into FBC tests to use
Y-tiled buffers.


Everything reviewed & merged. Thanks for the patches.

Thanks Paulo :)


Patch 5 contained a few coding style problems, which I fixed before
merging. Please try to keep the coding style used by the files touched.

Will take care going fwd.
Regards,
Praveen




v2: Adressed review comments
v3: Included original patches from Paulo and addressed more comments

Paulo Zanoni (2):
  lib/igt_draw: add support for Y tiling
  tests/kms_draw_crc: add support for Y tiling

Praveen Paneri (3):
  lib/igt_fb: Let others use igt_get_fb_tile_size
  lib/igt_fb: Add helper function for tile_to_mod
  igt/kms_fbc_crc.c : Add Y-tile tests

 lib/igt_draw.c   | 171 -
--
 lib/igt_fb.c |  41 +++-
 lib/igt_fb.h |   3 +
 tests/kms_draw_crc.c |  55 -
 tests/kms_fbc_crc.c  |  73 +-
 5 files changed, 246 insertions(+), 97 deletions(-)


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[Intel-gfx] [PATCH i-g-t 2/2] tests/drv_suspend: Add subtests to check that forcewake is kept after resume

[Ewelina Musial]

In some cases we observed that forcewake isn't kept after
resume and checking RC6 residency is a simple way to verify that.
If forcewake is kept after resume residency should be constant.

Cc: Lukasz Fiedorowicz 
Cc: Radoslaw Szwichtenberg 
Cc: Michal Winiarski 
Signed-off-by: Ewelina Musial 
---
 tests/drv_suspend.c | 36 
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/tests/drv_suspend.c b/tests/drv_suspend.c
index 2e39f20a..0c576055 100644
--- a/tests/drv_suspend.c
+++ b/tests/drv_suspend.c
@@ -36,6 +36,9 @@
 #include 
 #include 
 #include 
+#include "igt_sysfs.h"
+#include "igt_aux.h"
+#include 
 
 #include 
 
@@ -160,8 +163,9 @@ test_sysfs_reader(bool hibernate)
igt_stop_helper();
 }
 
+#define SLEEP_DURATION 3
 static void
-test_forcewake(int fd, bool hibernate)
+test_forcewake(int fd, bool hibernate, bool residency)
 {
int fw_fd;
 
@@ -174,8 +178,26 @@ test_forcewake(int fd, bool hibernate)
else
igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
  SUSPEND_TEST_NONE);
+if (residency)
+{
+int sysfs;
+uint32_t residency_pre, residency_post;
 
-   close (fw_fd);
+sysfs = igt_sysfs_open(fd, NULL);
+igt_assert_lte(0, sysfs);
+sleep(1); // time to fully resume
+
+// forcewake should keep residency constant after resume
+residency_pre = read_residency(sysfs, "rc6");
+sleep(SLEEP_DURATION);
+residency_post = read_residency(sysfs, "rc6");
+
+igt_assert_eq(residency_pre, residency_post);
+
+close(sysfs);
+}
+
+close (fw_fd);
 }
 
 int fd;
@@ -200,7 +222,10 @@ igt_main
test_sysfs_reader(false);
 
igt_subtest("forcewake")
-   test_forcewake(fd, false);
+   test_forcewake(fd, false, false);
+
+igt_subtest("rc6-forcewake")
+   test_forcewake(fd, false, true);
 
igt_subtest("fence-restore-tiled2untiled-hibernate")
test_fence_restore(fd, true, true);
@@ -215,7 +240,10 @@ igt_main
test_sysfs_reader(true);
 
igt_subtest("forcewake-hibernate")
-   test_forcewake(fd, true);
+   test_forcewake(fd, true, false);
+
+igt_subtest("rc6-forcewake-hibernate")
+   test_forcewake(fd, true, true);
 
igt_fixture
close(fd);
-- 
2.13.3

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[Intel-gfx] [PATCH i-g-t 1/2] igt: Move read_rc6_residency function to lib

[Ewelina Musial]

Gem_mocs_settings and pm_rc6_residency tests are defining
the same functionality to read residency from sysfs.
Moving that function to lib/igt_aux and updating tests.

Signed-off-by: Ewelina Musial 
---
 lib/igt_aux.c |  8 
 lib/igt_aux.h |  5 +
 tests/gem_mocs_settings.c | 10 ++
 tests/pm_rc6_residency.c  | 19 ---
 4 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index 86a213c2..224da4b6 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -1680,3 +1680,11 @@ double igt_stop_siglatency(struct igt_mean *result)
 
return mean;
 }
+
+uint32_t read_residency(int dir, const char *name)
+{
+   char path[128];
+
+   sprintf(path, "power/%s_residency_ms", name);
+   return igt_sysfs_get_u32(dir, path);
+}
diff --git a/lib/igt_aux.h b/lib/igt_aux.h
index 499a1679..8cc06f8c 100644
--- a/lib/igt_aux.h
+++ b/lib/igt_aux.h
@@ -386,4 +386,9 @@ static inline bool igt_list_empty(const struct igt_list 
*list)
 >member != (head);\
 pos = tmp, tmp = igt_list_next_entry(pos, member))
 
+/**
+ * Helper to read RC6 and MC6 residencies from sysfs
+ */
+uint32_t read_residency(int dir, const char *name);
+
 #endif /* IGT_AUX_H */
diff --git a/tests/gem_mocs_settings.c b/tests/gem_mocs_settings.c
index 05dfc637..67a52f50 100644
--- a/tests/gem_mocs_settings.c
+++ b/tests/gem_mocs_settings.c
@@ -328,12 +328,6 @@ static void check_l3cc_registers(int fd,
gem_close(fd, dst_handle);
 }
 
-
-static uint32_t rc6_residency(int dir)
-{
-   return igt_sysfs_get_u32(dir, "power/rc6_residency_ms");
-}
-
 static void rc6_wait(int fd)
 {
int sysfs;
@@ -342,8 +336,8 @@ static void rc6_wait(int fd)
sysfs = igt_sysfs_open(fd, NULL);
igt_assert_lte(0, sysfs);
 
-   residency = rc6_residency(sysfs);
-   igt_require(igt_wait(rc6_residency(sysfs) != residency, 1, 2));
+   residency = read_residency(sysfs, "rc6");
+   igt_require(igt_wait(read_residency(sysfs, "rc6") != residency, 1, 
2));
 
close(sysfs);
 }
diff --git a/tests/pm_rc6_residency.c b/tests/pm_rc6_residency.c
index bdb9747a..ac6e019a 100644
--- a/tests/pm_rc6_residency.c
+++ b/tests/pm_rc6_residency.c
@@ -61,17 +61,6 @@ static unsigned long get_rc6_enabled_mask(void)
return rc6_mask;
 }
 
-static unsigned long read_rc6_residency(const char *name)
-{
-   unsigned long residency;
-   char path[128];
-
-   residency = 0;
-   sprintf(path, "power/%s_residency_ms", name);
-   igt_assert(igt_sysfs_scanf(sysfs, path, "%lu", ) == 1);
-   return residency;
-}
-
 static void residency_accuracy(unsigned int diff,
   unsigned int duration,
   const char *name_of_rc6_residency)
@@ -90,17 +79,17 @@ static void read_residencies(int devid, unsigned int 
rc6_mask,
 struct residencies *res)
 {
if (rc6_mask & RC6_ENABLED)
-   res->rc6 = read_rc6_residency("rc6");
+   res->rc6 = read_residency(sysfs, "rc6");
 
if ((rc6_mask & RC6_ENABLED) &&
(IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)))
-   res->media_rc6 = read_rc6_residency("media_rc6");
+   res->media_rc6 = read_residency(sysfs, "media_rc6");
 
if (rc6_mask & RC6P_ENABLED)
-   res->rc6p = read_rc6_residency("rc6p");
+   res->rc6p = read_residency(sysfs, "rc6p");
 
if (rc6_mask & RC6PP_ENABLED)
-   res->rc6pp = read_rc6_residency("rc6pp");
+   res->rc6pp = read_residency(sysfs, "rc6pp");
 }
 
 static unsigned long gettime_ms(void)
-- 
2.13.3

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Re: [Intel-gfx] [PATCH i-g-t v3 0/5] Add Y-tiling support into IGTs

[Paulo Zanoni]

Em Ter, 2017-07-18 às 22:52 +0530, Praveen Paneri escreveu:
> This series adds Y-tiled buffer creation support into IGT libraries
> and
> goes on to use this capability to add support into FBC tests to use
> Y-tiled buffers.

Everything reviewed & merged. Thanks for the patches.

Patch 5 contained a few coding style problems, which I fixed before
merging. Please try to keep the coding style used by the files touched.

> 
> v2: Adressed review comments
> v3: Included original patches from Paulo and addressed more comments
> 
> Paulo Zanoni (2):
>   lib/igt_draw: add support for Y tiling
>   tests/kms_draw_crc: add support for Y tiling
> 
> Praveen Paneri (3):
>   lib/igt_fb: Let others use igt_get_fb_tile_size
>   lib/igt_fb: Add helper function for tile_to_mod
>   igt/kms_fbc_crc.c : Add Y-tile tests
> 
>  lib/igt_draw.c   | 171 -
> --
>  lib/igt_fb.c |  41 +++-
>  lib/igt_fb.h |   3 +
>  tests/kms_draw_crc.c |  55 -
>  tests/kms_fbc_crc.c  |  73 +-
>  5 files changed, 246 insertions(+), 97 deletions(-)
> 
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Re: [Intel-gfx] [PATCH 7/8] drm: Nuke drm_atomic_helper_connector_dpms

[Shawn Guo]

On Tue, Jul 25, 2017 at 10:01:21AM +0200, Daniel Vetter wrote:
> It's dead code, the core handles all this directly now.
> 
> The only special case is nouveau and tda988x which used one function
> for both legacy modeset code and -nv50 atomic world instead of 2
> vtables. But amounts to exactly the same.
> 
> v2: Rebase over the panel/brideg refactorings in stm/ltdc.
> 
> Signed-off-by: Daniel Vetter 
...
>  drivers/gpu/drm/zte/zx_hdmi.c  |  1 -
>  drivers/gpu/drm/zte/zx_tvenc.c |  1 -
>  drivers/gpu/drm/zte/zx_vga.c   |  1 -

Acked-by: Shawn Guo 
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Fix kbuild error

[Chris Wilson]

Quoting Chris Wilson (2017-07-25 13:53:36)
> After rebasing af2788925ae0 ("drm/i915: Squelch reset messages during
> selftests"), I missed fixing up a call to i915_reset().
> 
> Reported-by: kbuild test robot 
> Fixes: af2788925ae0 ("drm/i915: Squelch reset messages during selftests")
> Signed-off-by: Chris Wilson 

Pushed with an irc r-b David Weinehall 
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Fix kbuild error

[David Weinehall]

On Tue, Jul 25, 2017 at 01:53:36PM +0100, Chris Wilson wrote:
> After rebasing af2788925ae0 ("drm/i915: Squelch reset messages during
> selftests"), I missed fixing up a call to i915_reset().
> 
> Reported-by: kbuild test robot 
> Fixes: af2788925ae0 ("drm/i915: Squelch reset messages during selftests")
> Signed-off-by: Chris Wilson 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
> b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 6896751ee919..7c55a4c7f4c9 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -842,7 +842,7 @@ static int igt_render_engine_reset_fallback(void *arg)
>  
>   mutex_lock(>drm.struct_mutex);
>   set_bit(I915_RESET_HANDOFF, >gpu_error.flags);
> - i915_reset(i915);
> + i915_reset(i915, I915_RESET_QUIET);
>   GEM_BUG_ON(test_bit(I915_RESET_HANDOFF,
>   >gpu_error.flags));
>   mutex_unlock(>drm.struct_mutex);
> -- 
> 2.13.3
> 
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[Intel-gfx] [PATCH i-g-t] igt: Move read_rc6_residency function to lib

[Ewelina Musial]

Gem_mocs_settings and pm_rc6_residency tests are defining
the same functionality to read residency from sysfs.
Moving that function to lib/igt_aux and updating tests.

Signed-off-by: Ewelina Musial 
---
 lib/igt_aux.c |  8 
 lib/igt_aux.h |  5 +
 tests/gem_mocs_settings.c | 10 ++
 tests/pm_rc6_residency.c  | 19 ---
 4 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index 86a213c2..224da4b6 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -1680,3 +1680,11 @@ double igt_stop_siglatency(struct igt_mean *result)
 
return mean;
 }
+
+uint32_t read_residency(int dir, const char *name)
+{
+   char path[128];
+
+   sprintf(path, "power/%s_residency_ms", name);
+   return igt_sysfs_get_u32(dir, path);
+}
diff --git a/lib/igt_aux.h b/lib/igt_aux.h
index 499a1679..8cc06f8c 100644
--- a/lib/igt_aux.h
+++ b/lib/igt_aux.h
@@ -386,4 +386,9 @@ static inline bool igt_list_empty(const struct igt_list 
*list)
 >member != (head);\
 pos = tmp, tmp = igt_list_next_entry(pos, member))
 
+/**
+ * Helper to read RC6 and MC6 residencies from sysfs
+ */
+uint32_t read_residency(int dir, const char *name);
+
 #endif /* IGT_AUX_H */
diff --git a/tests/gem_mocs_settings.c b/tests/gem_mocs_settings.c
index 05dfc637..67a52f50 100644
--- a/tests/gem_mocs_settings.c
+++ b/tests/gem_mocs_settings.c
@@ -328,12 +328,6 @@ static void check_l3cc_registers(int fd,
gem_close(fd, dst_handle);
 }
 
-
-static uint32_t rc6_residency(int dir)
-{
-   return igt_sysfs_get_u32(dir, "power/rc6_residency_ms");
-}
-
 static void rc6_wait(int fd)
 {
int sysfs;
@@ -342,8 +336,8 @@ static void rc6_wait(int fd)
sysfs = igt_sysfs_open(fd, NULL);
igt_assert_lte(0, sysfs);
 
-   residency = rc6_residency(sysfs);
-   igt_require(igt_wait(rc6_residency(sysfs) != residency, 1, 2));
+   residency = read_residency(sysfs, "rc6");
+   igt_require(igt_wait(read_residency(sysfs, "rc6") != residency, 1, 
2));
 
close(sysfs);
 }
diff --git a/tests/pm_rc6_residency.c b/tests/pm_rc6_residency.c
index bdb9747a..ac6e019a 100644
--- a/tests/pm_rc6_residency.c
+++ b/tests/pm_rc6_residency.c
@@ -61,17 +61,6 @@ static unsigned long get_rc6_enabled_mask(void)
return rc6_mask;
 }
 
-static unsigned long read_rc6_residency(const char *name)
-{
-   unsigned long residency;
-   char path[128];
-
-   residency = 0;
-   sprintf(path, "power/%s_residency_ms", name);
-   igt_assert(igt_sysfs_scanf(sysfs, path, "%lu", ) == 1);
-   return residency;
-}
-
 static void residency_accuracy(unsigned int diff,
   unsigned int duration,
   const char *name_of_rc6_residency)
@@ -90,17 +79,17 @@ static void read_residencies(int devid, unsigned int 
rc6_mask,
 struct residencies *res)
 {
if (rc6_mask & RC6_ENABLED)
-   res->rc6 = read_rc6_residency("rc6");
+   res->rc6 = read_residency(sysfs, "rc6");
 
if ((rc6_mask & RC6_ENABLED) &&
(IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)))
-   res->media_rc6 = read_rc6_residency("media_rc6");
+   res->media_rc6 = read_residency(sysfs, "media_rc6");
 
if (rc6_mask & RC6P_ENABLED)
-   res->rc6p = read_rc6_residency("rc6p");
+   res->rc6p = read_residency(sysfs, "rc6p");
 
if (rc6_mask & RC6PP_ENABLED)
-   res->rc6pp = read_rc6_residency("rc6pp");
+   res->rc6pp = read_residency(sysfs, "rc6pp");
 }
 
 static unsigned long gettime_ms(void)
-- 
2.13.3

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Re: [Intel-gfx] [PATCH 7/8] drm: Nuke drm_atomic_helper_connector_dpms

[Laurent Pinchart]

Hi Daniel,

Thank you for the patch.

On Tuesday 25 Jul 2017 10:01:21 Daniel Vetter wrote:
> It's dead code, the core handles all this directly now.
> 
> The only special case is nouveau and tda988x which used one function
> for both legacy modeset code and -nv50 atomic world instead of 2
> vtables. But amounts to exactly the same.
> 
> v2: Rebase over the panel/brideg refactorings in stm/ltdc.
> 
> Signed-off-by: Daniel Vetter 

[snip]

> ---
>  drivers/gpu/drm/bridge/adv7511/adv7511_drv.c   |  1 -
>  drivers/gpu/drm/bridge/dumb-vga-dac.c  |  1 -
>  drivers/gpu/drm/bridge/panel.c |  1 -
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c  |  1 -
>  drivers/gpu/drm/drm_atomic_helper.c| 79 ---
>  drivers/gpu/drm/omapdrm/omap_connector.c   |  1 -
>  drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c  |  1 -

For the above,

Reviewed-by: Laurent Pinchart 

-- 
Regards,

Laurent Pinchart

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/sdvo: Shut up state checker with hdmi cards on gen3

[Patchwork]

== Series Details ==

Series: drm/i915/sdvo: Shut up state checker with hdmi cards on gen3
URL   : https://patchwork.freedesktop.org/series/27860/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_hangcheck.o
In file included from drivers/gpu/drm/i915/intel_hangcheck.c:485:0:
drivers/gpu/drm/i915/selftests/intel_hangcheck.c: In function 
‘igt_render_engine_reset_fallback’:
drivers/gpu/drm/i915/selftests/intel_hangcheck.c:845:3: error: too few 
arguments to function ‘i915_reset’
   i915_reset(i915);
   ^~
In file included from drivers/gpu/drm/i915/intel_hangcheck.c:25:0:
drivers/gpu/drm/i915/i915_drv.h:3115:13: note: declared here
 extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
 ^~
scripts/Makefile.build:302: recipe for target 
'drivers/gpu/drm/i915/intel_hangcheck.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_hangcheck.o] Error 1
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] [PATCH] drm/i915/sdvo: Shut up state checker with hdmi cards on gen3

[Daniel Vetter]

The hdmi bits simply don't exist, so nerf them. I think audio doesn't
work on gen3 at all, and for the limited color range we should
probably use the colorimetry sdvo paramater instead of the bit in the
port.

But fixing sdvo isn't my goal, I just want to get the backtrace out of
the way, and this takes care of that.

Still, while at it fix the missing read-out of the gen4 audio bit,
maybe that part even works ...

Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/intel_sdvo.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
b/drivers/gpu/drm/i915/intel_sdvo.c
index bea8152ae859..0403e30dfabc 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1113,6 +1113,7 @@ static bool intel_sdvo_compute_config(struct 
intel_encoder *encoder,
  struct intel_crtc_state *pipe_config,
  struct drm_connector_state *conn_state)
 {
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
struct intel_sdvo_connector_state *intel_sdvo_state =
to_intel_sdvo_connector_state(conn_state);
@@ -1174,6 +1175,12 @@ static bool intel_sdvo_compute_config(struct 
intel_encoder *encoder,
pipe_config->limited_color_range = true;
}
 
+   /* gen3 doesn't do the hdmi bits in the SDVO register */
+   if (INTEL_GEN(dev_priv) < 4) {
+   pipe_config->limited_color_range = false;
+   pipe_config->has_audio = false;
+   }
+
/* Clock computation needs to happen after pixel multiplier. */
if (intel_sdvo->is_tv)
i9xx_adjust_sdvo_tv_clock(pipe_config);
@@ -1480,6 +1487,9 @@ static void intel_sdvo_get_config(struct intel_encoder 
*encoder,
if (sdvox & HDMI_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
 
+   if (sdvox & SDVO_AUDIO_ENABLE)
+   pipe_config->has_audio = true;
+
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
 , 1)) {
if (val == SDVO_ENCODE_HDMI)
-- 
2.13.3

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix kbuild error

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Fix kbuild error
URL   : https://patchwork.freedesktop.org/series/27856/
State : success

== Summary ==

Series 27856v1 drm/i915/selftests: Fix kbuild error
https://patchwork.freedesktop.org/api/1.0/series/27856/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-n2820) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:448s
fi-bdw-gvtdvmtotal:280  pass:265  dwarn:1   dfail:0   fail:0   skip:14  
time:432s
fi-blb-e6850 total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  
time:365s
fi-bsw-n3050 total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  
time:537s
fi-bxt-j4205 total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:513s
fi-byt-j1900 total:280  pass:256  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-byt-n2820 total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:497s
fi-glk-2atotal:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:613s
fi-hsw-4770  total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:438s
fi-hsw-4770r total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:414s
fi-ilk-650   total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  
time:411s
fi-ivb-3520m total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:518s
fi-ivb-3770  total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:479s
fi-kbl-7500u total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:470s
fi-kbl-7560u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:589s
fi-kbl-r total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:584s
fi-pnv-d510  total:280  pass:224  dwarn:1   dfail:0   fail:0   skip:55  
time:573s
fi-skl-6260u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:470s
fi-skl-6700hqtotal:280  pass:263  dwarn:0   dfail:0   fail:0   skip:17  
time:591s
fi-skl-6700k total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-skl-6770hqtotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:479s
fi-skl-gvtdvmtotal:280  pass:266  dwarn:1   dfail:0   fail:0   skip:13  
time:440s
fi-skl-x1585ltotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:493s
fi-snb-2520m total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:556s
fi-snb-2600  total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  
time:410s

f1e5e209a462434e59ebd292de05bdf82c0c8b05 drm-tip: 2017y-07m-25d-11h-27m-38s UTC 
integration manifest
c8683271dbcb drm/i915/selftests: Fix kbuild error

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5273/
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Re: [Intel-gfx] [PATCH] drm/i915: Use AUX for backlight only if eDP 1.4 or later

[David Weinehall]

On Tue, Jul 25, 2017 at 03:41:46PM +0300, David Weinehall wrote:
> On 2017-07-25 02:15, Puthikorn Voravootivat wrote:
> > I saw a DP 1.3 panel that advertise AUX backlight brightness control
> > but not working properly. So it should work but not in real world.
> > I think that is good reason enough to add this as a heuristic.
> > 
> > 
> Either key it on eDP 1.4 and hope that it's a reasonable expectation,
> or employ a whitelist (potentially lots of effort adding all displays that
> supports AUX backlight, but safe from regressions) or a blacklist
> (potentially fewer displays need to be added, but risks introducing
> regressions for end users).

Sorry for the blurb in the previous mail, I replied from my official
Intel address by mistake :S


Kind regards, David
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Re: [Intel-gfx] [PATCH] drm/i915: Enforce that CS packets are qword aligned

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-07-24 09:06:28)
> 
> 
> On 21/07/2017 17:11, Chris Wilson wrote:
> > We require the caller to ensure that the packets they wish to emit into
> > the CS ring are qword aligned (i.e. have an even number of dwords).
> > Double check this.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > Cc: Joonas Lahtinen 
> > ---
> >   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
> >   1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index aa59290cb8bf..0b06f66507a0 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1397,6 +1397,9 @@ u32 *intel_ring_begin(struct drm_i915_gem_request 
> > *req,
> >   unsigned int total_bytes;
> >   u32 *cs;
> >   
> > + /* Packets must be qword aligned. */
> > + GEM_BUG_ON(num_dwords & 1);
> > +
> >   total_bytes = bytes + req->reserved_space;
> >   GEM_BUG_ON(total_bytes > ring->effective_size);
> >   
> > 
> 
> Reviewed-by: Tvrtko Ursulin 

And pushed! Still looking for takers to review a regression fix or
two... :-p
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Fix kbuild error

[Chris Wilson]

Quoting Chris Wilson (2017-07-25 13:53:36)
> After rebasing af2788925ae0 ("drm/i915: Squelch reset messages during
> selftests"), I missed fixing up a call to i915_reset().

s/rebasing/applying patches out of order due to review timing/

> Reported-by: kbuild test robot 
> Fixes: af2788925ae0 ("drm/i915: Squelch reset messages during selftests")
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
> b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 6896751ee919..7c55a4c7f4c9 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -842,7 +842,7 @@ static int igt_render_engine_reset_fallback(void *arg)
>  
> mutex_lock(>drm.struct_mutex);
> set_bit(I915_RESET_HANDOFF, >gpu_error.flags);
> -   i915_reset(i915);
> +   i915_reset(i915, I915_RESET_QUIET);
> GEM_BUG_ON(test_bit(I915_RESET_HANDOFF,
> >gpu_error.flags));
> mutex_unlock(>drm.struct_mutex);
> -- 
> 2.13.3
> 
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[Intel-gfx] [PATCH] drm/i915/selftests: Fix kbuild error

[Chris Wilson]

After rebasing af2788925ae0 ("drm/i915: Squelch reset messages during
selftests"), I missed fixing up a call to i915_reset().

Reported-by: kbuild test robot 
Fixes: af2788925ae0 ("drm/i915: Squelch reset messages during selftests")
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 6896751ee919..7c55a4c7f4c9 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -842,7 +842,7 @@ static int igt_render_engine_reset_fallback(void *arg)
 
mutex_lock(>drm.struct_mutex);
set_bit(I915_RESET_HANDOFF, >gpu_error.flags);
-   i915_reset(i915);
+   i915_reset(i915, I915_RESET_QUIET);
GEM_BUG_ON(test_bit(I915_RESET_HANDOFF,
>gpu_error.flags));
mutex_unlock(>drm.struct_mutex);
-- 
2.13.3

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[Intel-gfx] [PATCH i-g-t 2/3] configure.ac: Disable chamelium by default and add enable argument

[Paul Kocialkowski]

Since the chamelium is not a very usual piece of hardware and requires
pulling-in lots of specific dependencies, it makes sense to keep it
disabled by default.

An explicit --enable-chamelium argument is provided to enable it when
necessary. This also leads to more predictable results than
automatically enabling it when its dependencies are met.

Finally, whether chamelium support is enabled is printed by the
information summary at end of the configure run.

Signed-off-by: Paul Kocialkowski 
---
 configure.ac | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/configure.ac b/configure.ac
index a6ab9e4a..17a226de 100644
--- a/configure.ac
+++ b/configure.ac
@@ -185,23 +185,23 @@ PKG_CHECK_MODULES(GSL, [gsl], [gsl=yes], [gsl=no])
 AM_CONDITIONAL(HAVE_GSL, [test "x$gsl" = xyes])
 
 # for chamelium
-AC_ARG_ENABLE(chamelium, AS_HELP_STRING([--disable-chamelium],
- [Enable building of chamelium libraries and tests (default: 
yes)]),
- [enable_chamelium=no], [enable_chamelium=yes])
+AC_ARG_ENABLE(chamelium, AS_HELP_STRING([--enable-chamelium],
+ [Enable building of chamelium libraries and tests (default: no)]),
+ [enable_chamelium=yes], [enable_chamelium=no])
 AM_CONDITIONAL(HAVE_CHAMELIUM, [test "x$enable_chamelium" = xyes])
 if test "x$enable_chamelium" = xyes; then
PKG_CHECK_MODULES(XMLRPC, xmlrpc xmlrpc_util xmlrpc_client, [],
- [AC_MSG_ERROR([Failed to find xmlrpc, required by 
chamelium. Use --disable-chamelium to disable chamelium support.])])
+ [AC_MSG_ERROR([Failed to find xmlrpc, required by 
chamelium.])])
PKG_CHECK_MODULES(PIXMAN, pixman-1, [],
- [AC_MSG_ERROR([Failed to find pixman, required by 
chamelium. Use --disable-chamelium to disable chamelium support.])])
+ [AC_MSG_ERROR([Failed to find pixman, required by 
chamelium.])])
if test x"$udev" != xyes; then
-   AC_MSG_ERROR([Failed to find udev, required by chamelium. Use 
--disable-chamelium to disable chamelium support.])
+   AC_MSG_ERROR([Failed to find udev, required by chamelium.])
fi
if test x"$glib" != xyes; then
-   AC_MSG_ERROR([Failed to find glib, required by chamelium. Use 
--disable-chamelium to disable chamelium support.])
+   AC_MSG_ERROR([Failed to find glib, required by chamelium.])
fi
if test x"$gsl" != xyes; then
-   AC_MSG_ERROR([Failed to find gsl, required by chamelium. Use 
--disable-chamelium to disable chamelium support.])
+   AC_MSG_ERROR([Failed to find gsl, required by chamelium.])
fi
 
AC_DEFINE(HAVE_CHAMELIUM, 1, [Enable Chamelium support])
@@ -404,6 +404,7 @@ echo "Intel GPU tools"
 echo ""
 echo " • Tests:"
 echo "   Build tests: ${BUILD_TESTS}"
+echo "   Chamelium tests: ${enable_chamelium}"
 echo "   Compile prime tests: ${NOUVEAU}"
 echo "   Print stack traces : ${with_libunwind}"
 echo "   Debug flags: ${DEBUG_CFLAGS}"
-- 
2.13.2

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[Intel-gfx] [PATCH i-g-t 1/3] configure.ac: Make udev a dependency for chamelium

[Paul Kocialkowski]

Chamelium testing has a hard dependency on udev. This makes this
dependency explicit in configure instead of failing the build when it
is missing.

Signed-off-by: Paul Kocialkowski 
---
 configure.ac | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configure.ac b/configure.ac
index dec3e923..a6ab9e4a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -194,6 +194,9 @@ if test "x$enable_chamelium" = xyes; then
  [AC_MSG_ERROR([Failed to find xmlrpc, required by 
chamelium. Use --disable-chamelium to disable chamelium support.])])
PKG_CHECK_MODULES(PIXMAN, pixman-1, [],
  [AC_MSG_ERROR([Failed to find pixman, required by 
chamelium. Use --disable-chamelium to disable chamelium support.])])
+   if test x"$udev" != xyes; then
+   AC_MSG_ERROR([Failed to find udev, required by chamelium. Use 
--disable-chamelium to disable chamelium support.])
+   fi
if test x"$glib" != xyes; then
AC_MSG_ERROR([Failed to find glib, required by chamelium. Use 
--disable-chamelium to disable chamelium support.])
fi
-- 
2.13.2

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[Intel-gfx] [PATCH i-g-t 3/3] README: Add information about chamelium dependencies

[Paul Kocialkowski]

This adds a list of dependencies required to build chamelium support,
so that what needs to be installed to get it going is more obvious.

As done previously in the file, the list is relevant for Debian and its
derivatives but should provide a template for other systems as well.

Signed-off-by: Paul Kocialkowski 
---
 README | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/README b/README
index 26171a17..d1ea9529 100644
--- a/README
+++ b/README
@@ -131,7 +131,7 @@ Requirements
 
 
 This is a non-exhaustive list of package dependencies required for building
-everything (package names may vary):
+the default configuration (package names may vary):
 
gtk-doc-tools
libcairo2-dev
@@ -144,6 +144,15 @@ everything (package names may vary):
x11proto-dri2-dev
xutils-dev
 
+The following dependencies are required for building chamelium support
+(package names may vary):
+
+   libxmlrpc-core-c3-dev
+   libpixman-1-dev
+   libudev-dev
+   libglib2.0-dev
+   libgsl-dev
+
 Releases for maintainers
 
 
-- 
2.13.2

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Re: [Intel-gfx] [PATCH] drm/i915: Use AUX for backlight only if eDP 1.4 or later

[David Weinehall]

On 2017-07-25 02:15, Puthikorn Voravootivat wrote:

I saw a DP 1.3 panel that advertise AUX backlight brightness control
but not working properly. So it should work but not in real world.
I think that is good reason enough to add this as a heuristic.



Either key it on eDP 1.4 and hope that it's a reasonable expectation,
or employ a whitelist (potentially lots of effort adding all displays that
supports AUX backlight, but safe from regressions) or a blacklist
(potentially fewer displays need to be added, but risks introducing
regressions for end users).


Kind regards, David
-
Intel Finland Oy
Registered Address: PL 281, 00181 Helsinki 
Business Identity Code: 0357606 - 4 
Domiciled in Helsinki 


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Re: [Intel-gfx] [RFC v3] drm/hdcp: drm enum property for CP State

[Sean Paul]

On Mon, Jul 24, 2017 at 2:12 PM, Ramalingam C  wrote:
> DRM connector property is created to represent the content protection
> state of the connector and to configure the same.
>
> Content protection states defined:
> DRM_MODE_CONTENT_PROTECTION_UNSUPPORTED - Unsupported
> DRM_MODE_CONTENT_PROTECTION_DISABLE - Disabled
> DRM_MODE_CONTENT_PROTECTION_ENABLE  - Enabled
>
> v2: Redesigned the property to match with CP needs of CrOS [Sean].
>
> v3: Renamed the state names. Header is removed [sean].
>
> Signed-off-by: Ramalingam C 
> ---
>  drivers/gpu/drm/drm_connector.c | 14 ++
>  include/drm/drm_mode_config.h   |  5 +
>  include/uapi/drm/drm_mode.h |  5 +
>  3 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 5cd61af..d6aaa08 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -617,6 +617,13 @@ static const struct drm_prop_enum_list 
> drm_link_status_enum_list[] = {
>  };
>  DRM_ENUM_NAME_FN(drm_get_link_status_name, drm_link_status_enum_list)
>
> +static const struct drm_prop_enum_list drm_cp_enum_list[] = {
> +   { DRM_MODE_CONTENT_PROTECTION_UNSUPPORTED,  "Unsupported" },

You're still changing the enum names from the original patch/CrOS
implementation.

https://lists.freedesktop.org/archives/dri-devel/2014-December/073336.html

https://cs.chromium.org/chromium/src/ui/ozone/platform/drm/gpu/drm_display.cc?l=27



> +   { DRM_MODE_CONTENT_PROTECTION_DISABLE,  "Disabled" },
> +   { DRM_MODE_CONTENT_PROTECTION_ENABLE,   "Enabled" },
> +};
> +DRM_ENUM_NAME_FN(drm_get_cp_status_name, drm_cp_enum_list)
> +
>  /**
>   * drm_display_info_set_bus_formats - set the supported bus formats
>   * @info: display info to store bus formats in
> @@ -789,6 +796,13 @@ int drm_connector_create_standard_properties(struct 
> drm_device *dev)
> return -ENOMEM;
> dev->mode_config.link_status_property = prop;
>
> +   prop = drm_property_create_enum(dev, 0, "Content Protection",
> +   drm_cp_enum_list,
> +   ARRAY_SIZE(drm_cp_enum_list));
> +   if (!prop)
> +   return -ENOMEM;
> +   dev->mode_config.cp_property = prop;
> +
> return 0;
>  }
>
> diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
> index 4298171..7acb8b2 100644
> --- a/include/drm/drm_mode_config.h
> +++ b/include/drm/drm_mode_config.h
> @@ -538,6 +538,11 @@ struct drm_mode_config {
>  */
> struct drm_property *link_status_property;
> /**
> +* @cp_property: Default connector property for CP
> +* of a connector

Can you please elaborate on this, so readers can understand how this
property works? Perhaps just copy the docs from the original patch?

> +*/
> +   struct drm_property *cp_property;
> +   /**
>  * @plane_type_property: Default plane property to differentiate
>  * CURSOR, PRIMARY and OVERLAY legacy uses of planes.
>  */
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 403339f..554a770 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -127,6 +127,11 @@ extern "C" {
>  #define DRM_MODE_LINK_STATUS_GOOD  0
>  #define DRM_MODE_LINK_STATUS_BAD   1
>
> +/* Content Protection options */
> +#define DRM_MODE_CONTENT_PROTECTION_UNSUPPORTED0
> +#define DRM_MODE_CONTENT_PROTECTION_DISABLE1
> +#define DRM_MODE_CONTENT_PROTECTION_ENABLE 2
> +
>  /*
>   * DRM_MODE_ROTATE_
>   *
> --
> 2.7.4
>
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[Intel-gfx] [drm-intel:for-linux-next 4/4] drivers/gpu/drm/i915/selftests/intel_hangcheck.c:845:3: error: too few arguments to function 'i915_reset'

[kbuild test robot]

tree:   git://anongit.freedesktop.org/drm-intel for-linux-next
head:   af2788925ae0b83737ee847c5b2e9f19c5bf3630
commit: af2788925ae0b83737ee847c5b2e9f19c5bf3630 [4/4] drm/i915: Squelch reset 
messages during selftests
config: i386-randconfig-x013-201730 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
git checkout af2788925ae0b83737ee847c5b2e9f19c5bf3630
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/intel_hangcheck.c:485:0:
   drivers/gpu/drm/i915/selftests/intel_hangcheck.c: In function 
'igt_render_engine_reset_fallback':
>> drivers/gpu/drm/i915/selftests/intel_hangcheck.c:845:3: error: too few 
>> arguments to function 'i915_reset'
  i915_reset(i915);
  ^~
   In file included from drivers/gpu/drm/i915/intel_hangcheck.c:25:0:
   drivers/gpu/drm/i915/i915_drv.h:3115:13: note: declared here
extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
^~

vim +/i915_reset +845 drivers/gpu/drm/i915/selftests/intel_hangcheck.c

496b575e Chris Wilson   2017-02-13  772  
abeb4def Michel Thierry 2017-06-20  773  static int 
igt_render_engine_reset_fallback(void *arg)
abeb4def Michel Thierry 2017-06-20  774  {
abeb4def Michel Thierry 2017-06-20  775 struct drm_i915_private *i915 = 
arg;
abeb4def Michel Thierry 2017-06-20  776 struct intel_engine_cs *engine 
= i915->engine[RCS];
abeb4def Michel Thierry 2017-06-20  777 struct hang h;
abeb4def Michel Thierry 2017-06-20  778 struct drm_i915_gem_request *rq;
abeb4def Michel Thierry 2017-06-20  779 unsigned int reset_count, 
reset_engine_count;
abeb4def Michel Thierry 2017-06-20  780 int err = 0;
abeb4def Michel Thierry 2017-06-20  781  
abeb4def Michel Thierry 2017-06-20  782 /* Check that we can issue a 
global GPU and engine reset */
abeb4def Michel Thierry 2017-06-20  783  
abeb4def Michel Thierry 2017-06-20  784 if 
(!intel_has_reset_engine(i915))
abeb4def Michel Thierry 2017-06-20  785 return 0;
abeb4def Michel Thierry 2017-06-20  786  
5b3d2c87 Chris Wilson   2017-07-21  787 global_reset_lock(i915);
5b3d2c87 Chris Wilson   2017-07-21  788  
abeb4def Michel Thierry 2017-06-20  789 
mutex_lock(>drm.struct_mutex);
abeb4def Michel Thierry 2017-06-20  790  
abeb4def Michel Thierry 2017-06-20  791 err = hang_init(, i915);
abeb4def Michel Thierry 2017-06-20  792 if (err)
774eed4a Chris Wilson   2017-06-23  793 goto err_unlock;
abeb4def Michel Thierry 2017-06-20  794  
abeb4def Michel Thierry 2017-06-20  795 rq = hang_create_request(, 
engine, i915->kernel_context);
abeb4def Michel Thierry 2017-06-20  796 if (IS_ERR(rq)) {
abeb4def Michel Thierry 2017-06-20  797 err = PTR_ERR(rq);
774eed4a Chris Wilson   2017-06-23  798 goto err_fini;
abeb4def Michel Thierry 2017-06-20  799 }
abeb4def Michel Thierry 2017-06-20  800  
abeb4def Michel Thierry 2017-06-20  801 i915_gem_request_get(rq);
abeb4def Michel Thierry 2017-06-20  802 __i915_add_request(rq, true);
abeb4def Michel Thierry 2017-06-20  803  
abeb4def Michel Thierry 2017-06-20  804 /* make reset engine fail */
abeb4def Michel Thierry 2017-06-20  805 rq->fence.error = -EIO;
abeb4def Michel Thierry 2017-06-20  806  
abeb4def Michel Thierry 2017-06-20  807 if (!wait_for_hang(, rq)) {
abeb4def Michel Thierry 2017-06-20  808 pr_err("Failed to start 
request %x\n", rq->fence.seqno);
abeb4def Michel Thierry 2017-06-20  809 err = -EIO;
774eed4a Chris Wilson   2017-06-23  810 goto err_request;
abeb4def Michel Thierry 2017-06-20  811 }
abeb4def Michel Thierry 2017-06-20  812  
abeb4def Michel Thierry 2017-06-20  813 reset_engine_count = 
i915_reset_engine_count(>gpu_error, engine);
abeb4def Michel Thierry 2017-06-20  814 reset_count = 
fake_hangcheck(rq);
abeb4def Michel Thierry 2017-06-20  815  
abeb4def Michel Thierry 2017-06-20  816 /* unlock since we'll call 
handle_error */
abeb4def Michel Thierry 2017-06-20  817 
mutex_unlock(>drm.struct_mutex);
5b3d2c87 Chris Wilson   2017-07-21  818 global_reset_unlock(i915);
abeb4def Michel Thierry 2017-06-20  819  
abeb4def Michel Thierry 2017-06-20  820 i915_handle_error(i915, 
intel_engine_flag(engine), "live test");
abeb4def Michel Thierry 2017-06-20  821  
abeb4def Michel Thierry 2017-06-20  822 if 
(i915_reset_engine_count(>gpu_error, engine) !=
abeb4def Michel Thierry 2017-06-20  823 reset_engine_count) {
abeb4def Michel Thierry 2017-06-20  824 pr_err("render engine 
reset recorded! (full reset expected)\n");
abeb4def Michel Thierry 2017-06-20  825 err = -EINVAL;
abeb4def Michel Thierry 

Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add helper to detect whether EDID changed

[Paul Kocialkowski]

On Tue, 2017-07-25 at 10:16 +0200, Daniel Vetter wrote:
> On Tue, Jul 25, 2017 at 10:58:55AM +0300, Paul Kocialkowski wrote:
> > On Tue, 2017-07-25 at 09:34 +0200, Daniel Vetter wrote:
> > > On Tue, Jul 25, 2017 at 9:25 AM, Paul Kocialkowski
> > >  wrote:
> > > > On Tue, 2017-07-25 at 08:53 +0200, Daniel Vetter wrote:
> > > > > On Mon, Jul 24, 2017 at 05:54:46PM +0300, Paul Kocialkowski
> > > > > wrote:
> > > > > > This adds a common drm helper to detect whether the EDID
> > > > > > changed
> > > > > > from
> > > > > > the last known cached one. This is useful help detect that a
> > > > > > monitor
> > > > > > was
> > > > > > changed during a suspend/resume cycle.
> > > > > > 
> > > > > > When that happens (a monitor is replaced by another one
> > > > > > during
> > > > > > suspend),
> > > > > > no hotplug event will be triggered so the change will not be
> > > > > > caught
> > > > > > at
> > > > > > resume time. Detecting that the EDID changed allows
> > > > > > detecting
> > > > > > it.
> > > > > > 
> > > > > > Signed-off-by: Paul Kocialkowski  > > > > > tel.
> > > > > > com>
> > > > > 
> > > > > I can't find the older mails I've typed about this, but the
> > > > > plan
> > > > > we've
> > > > > discussed a while back was:
> > > > > - Add a generational counter to each connector, maybe even
> > > > > expose
> > > > > it
> > > > > to
> > > > >   userspace.
> > > > > 
> > > > > - Increment that counter every time something changed, e.g.
> > > > >   connector->status in the propbe helpers, or when attaching a
> > > > > new
> > > > > edid
> > > > >   with the set_edid helper.
> > > > > 
> > > > > - Tada, no changes needed to drivers, and easily extensible to
> > > > > other
> > > > >   things than edid!
> > > > 
> > > > I don't see how it solves the problem here though. After a
> > > > suspend/resume cycle, there is simply no indication that
> > > > anything
> > > > has
> > > > changed when a monitor was replaced by another one, so I don't
> > > > see
> > > > how
> > > > adding a counter in the mix would help.
> > > > 
> > > > Could you provide more details about the reasoning? I feel like
> > > > I'm
> > > > missing something here.
> > > 
> > > Your bug doesn't just exist over s/r, it's just much easier to
> > > observe
> > > in s/r since users can take however long they want to with
> > > plugging in
> > > a different monitor. But the same issue exists e.g. when we go
> > > from
> > > hpd to polling because too much noise on the line.
> > > 
> > > Wrt the suspend/resume issue: What we need to do on resume is do a
> > > full reprobe of all outputs, in an async worker. Telling userspace
> > > to
> > > do this by sending an uevent was the cheapest way, but it'd be
> > > better
> > > if the kernel could do that asynchronously and inform userspace
> > > about
> > > the exact changes. And there's more to reprobe than just the edid,
> > > and
> > > we don't want to re-invent a separate reprobe path just for resume
> > > like you start in your patch series. So yeah my plan was missing:
> > > 
> > > - force a full async reprobe after resume (maybe we could reuse
> > > the
> > > poll worker for that as a one-shot).
> > 
> > First off, I definitely agree we need a way to tell userspace
> > exactly
> > what has happened. I wanted to start a discussion about that in i-g-
> > t
> > patch "Unrelated hotplug uevent masking out actual test result" but
> > it
> > didn't get much traction. For testing purposes, it is unacceptable
> > that
> > userspace only gets notified that "something happened".
> > 
> > Still, as far as I know, userspace is expected to ask for a full
> > reprobe
> > when something has changed, and that is apparently part of the DRM
> > spec,
> > so we can't expect that it could query for an update on "only the
> > things
> > that changed".
> 
> We can update that spec in a backwards compatible way. E.g. we can ask
> for
> the current properties without forcing a reprobe (won't even call down
> into the driver), and userspace could use that to check which
> connector
> has an incremented epoche counter since the last time it sampled
> things.
> Then it can reprobe just that one.
> 
> Old userspace wouldn't know about this, and would keep working as-is.

So the level of detail you're aiming at providing userspace is
"connector foo changed" then? I agree it is better than the current
"some connector(s) changed", but what I'd like to see for proper testing
is a way to find out "bar for connector foo changed".

> > However, one way to mitigate this is to make sure that the driver
> > knows
> > what changed and only updates these things when a full reprobe is
> > requested. Is this the approach that you have in mind?
> > 
> > The methodology behind my series follows what is currently done:
> > detect
> > change in whatever way necessary, inform userspace and let it
> > trigger
> > full reprobe. If I'm understanding correctly, what you're 

Re: [Intel-gfx] [PATCH i-g-t] lib/drmtest: Decode driver flags on failure

[Daniel Vetter]

On Tue, Jul 25, 2017 at 12:49:11PM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2017-07-25 12:37:08)
> > I spent too much time going wtf why does this test not run until
> > realizing that vgem is missing. This should help a lot for tests that
> > need multiple different drm drivers.
> > 
> > Signed-off-by: Daniel Vetter 
> > ---
> >  lib/drmtest.c | 21 -
> >  1 file changed, 20 insertions(+), 1 deletion(-)
> > 
> > diff --git a/lib/drmtest.c b/lib/drmtest.c
> > index 480bd0b132cd..944c6e02fd31 100644
> > --- a/lib/drmtest.c
> > +++ b/lib/drmtest.c
> > @@ -341,6 +341,24 @@ static void quiescent_gpu_at_exit_render(int sig)
> > at_exit_drm_render_fd = -1;
> >  }
> >  
> > +static const char *chipset_to_str(int chipset)
> > +{
> > +   switch (chipset) {
> > +   case DRIVER_INTEL:
> > +   return "intel";
> > +   case DRIVER_VC4:
> > +   return "vc4";
> > +   case DRIVER_VGEM:
> > +   return "vgem";
> > +   case DRIVER_VIRTIO:
> > +   return "virtio";
> > +   case DRIVER_AMDGPU:
> > +   return "amdgpu";
> case DRIVER_ANY:
> > +   return "any";
> > +   default:
>   return "other";

Revised and pushed with Chris' irc-r-b.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.BAT: failure for acquire ctx for everyone! (rev3)

[Patchwork]

== Series Details ==

Series: acquire ctx for everyone! (rev3)
URL   : https://patchwork.freedesktop.org/series/27835/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_hangcheck.o
In file included from drivers/gpu/drm/i915/intel_hangcheck.c:485:0:
drivers/gpu/drm/i915/selftests/intel_hangcheck.c: In function 
‘igt_render_engine_reset_fallback’:
drivers/gpu/drm/i915/selftests/intel_hangcheck.c:845:3: error: too few 
arguments to function ‘i915_reset’
   i915_reset(i915);
   ^~
In file included from drivers/gpu/drm/i915/intel_hangcheck.c:25:0:
drivers/gpu/drm/i915/i915_drv.h:3115:13: note: declared here
 extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
 ^~
scripts/Makefile.build:302: recipe for target 
'drivers/gpu/drm/i915/intel_hangcheck.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_hangcheck.o] Error 1
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] [PATCH] drm: Handle properties in the core for atomic drivers

[Daniel Vetter]

The reason behind the original indirection through the helper
functions was to allow existing drivers to overwrite how they handle
properties. For example when a vendor-specific userspace had
expectations that didn't match atomic. That seemed likely, since
atomic is standardizing a _lot_ more of the behaviour of a kms driver.

But 20 drivers later there's no such need at all. Worse, this forces
all drivers to hook up the default behaviour, breaking userspace if
they forget to do that. And it forces us to export a bunch of core
function just for those helpers.

And finally, these helpers are the last places using
drm_atomic_legacy_backoff() and the implicit acquire_ctx.

This patch here just implements the new behaviour and updates the
docs. Follow-up patches will garbage-collect all the dead code.

v2: Fixup docs even better!

v3: Make it actually work ...

v4: Drop the uses_atomic_modeset() checks from the previous patch
again, since they're now moved up in the callchain.

Cc: Maarten Lankhorst 
Reviewed-by: Archit Taneja  (v3)
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_atomic.c|  60 ++--
 drivers/gpu/drm/drm_connector.c |   8 +--
 drivers/gpu/drm/drm_crtc.c  |   2 +-
 drivers/gpu/drm/drm_crtc_helper.c   |   3 +-
 drivers/gpu/drm/drm_crtc_internal.h |   7 +++
 drivers/gpu/drm/drm_mode_object.c   | 110 +++-
 drivers/gpu/drm/drm_plane.c |   2 +-
 include/drm/drm_connector.h |  10 ++--
 include/drm/drm_crtc.h  |   6 +-
 include/drm/drm_plane.h |   6 +-
 10 files changed, 161 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 01192dd3ed79..0fd14aff7add 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1864,9 +1864,60 @@ static struct drm_pending_vblank_event 
*create_vblank_event(
return e;
 }
 
-static int atomic_set_prop(struct drm_atomic_state *state,
-   struct drm_mode_object *obj, struct drm_property *prop,
-   uint64_t prop_value)
+int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state,
+struct drm_connector *connector,
+int mode)
+{
+   struct drm_connector *tmp_connector;
+   struct drm_connector_state *new_conn_state;
+   struct drm_crtc *crtc;
+   struct drm_crtc_state *crtc_state;
+   int i, ret, old_mode = connector->dpms;
+   bool active = false;
+
+   ret = drm_modeset_lock(>dev->mode_config.connection_mutex,
+  state->acquire_ctx);
+   if (ret)
+   return ret;
+
+   if (mode != DRM_MODE_DPMS_ON)
+   mode = DRM_MODE_DPMS_OFF;
+   connector->dpms = mode;
+
+   crtc = connector->state->crtc;
+   if (!crtc)
+   goto out;
+   ret = drm_atomic_add_affected_connectors(state, crtc);
+   if (ret)
+   goto out;
+
+   crtc_state = drm_atomic_get_crtc_state(state, crtc);
+   if (IS_ERR(crtc_state)) {
+   ret = PTR_ERR(crtc_state);
+   goto out;
+   }
+
+   for_each_new_connector_in_state(state, tmp_connector, new_conn_state, 
i) {
+   if (new_conn_state->crtc != crtc)
+   continue;
+   if (tmp_connector->dpms == DRM_MODE_DPMS_ON) {
+   active = true;
+   break;
+   }
+   }
+
+   crtc_state->active = active;
+   ret = drm_atomic_commit(state);
+out:
+   if (ret != 0)
+   connector->dpms = old_mode;
+   return ret;
+}
+
+int drm_atomic_set_property(struct drm_atomic_state *state,
+   struct drm_mode_object *obj,
+   struct drm_property *prop,
+   uint64_t prop_value)
 {
struct drm_mode_object *ref;
int ret;
@@ -2286,7 +2337,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
goto out;
}
 
-   ret = atomic_set_prop(state, obj, prop, prop_value);
+   ret = drm_atomic_set_property(state, obj, prop,
+ prop_value);
if (ret) {
drm_mode_object_put(obj);
goto out;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 0e9e3161bdd0..ba9f36cef68c 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -717,9 +717,9 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
  * drivers, it remaps to controlling the "ACTIVE" property on the CRTC the
  * connector is linked to. Drivers should never set this property directly,
  * it is 

[Intel-gfx] [PATCH] drm: Don't update property values for atomic drivers

[Daniel Vetter]

Atomic drivers only use the property value store for immutable (i.e.
can't be set by userspace, but the kernel can still adjust it)
properties. The only tricky part is the removal of the update in
drm_atomic_helper_update_legacy_modeset_state().

This was added in

commit 8c10342cb48f3140d9abeadcfd2fa6625d447282 (tag: topic/drm-misc-2015-07-28)
Author: Maarten Lankhorst 
Date:   Mon Jul 27 13:24:29 2015 +0200

drm/atomic: Update legacy DPMS state during modesets, v3.

by copying it from the i915 code, where it was originally added in

commit 68d3472047a572936551f8ff0b6f4016c5a1fdef
Author: Daniel Vetter 
Date:   Thu Sep 6 22:08:35 2012 +0200

drm/i915: update dpms property in set_mode

for the legacy modeset code. The reason we needed this hack was that
i915 didn't yet set DRIVER_ATOMIC, and we checked for that instead of
the newer-ish drm_drv_uses_atomic_modeset(), which avoids such
troubles. With the correct feature checks this isn't needed anymore at
all.

Also make sure that drivers don't accidentally get this wrong by
making the exported version of drm_object_property_get_value() only
work for legacy drivers. Only gma500 uses it anyway.

v2: Fixup the uses_atomic_modeset() checks (Maarten)

Cc: Maarten Lankhorst 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_atomic_helper.c |  4 ---
 drivers/gpu/drm/drm_connector.c |  3 +--
 drivers/gpu/drm/drm_crtc.c  |  2 +-
 drivers/gpu/drm/drm_mode_object.c   | 49 +++--
 drivers/gpu/drm/drm_plane.c |  2 +-
 5 files changed, 33 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 7582bbc5decc..4a960c741e35 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -921,16 +921,12 @@ drm_atomic_helper_update_legacy_modeset_state(struct 
drm_device *dev,
crtc = new_conn_state->crtc;
if ((!crtc && old_conn_state->crtc) ||
(crtc && drm_atomic_crtc_needs_modeset(crtc->state))) {
-   struct drm_property *dpms_prop =
-   dev->mode_config.dpms_property;
int mode = DRM_MODE_DPMS_OFF;
 
if (crtc && crtc->state->active)
mode = DRM_MODE_DPMS_ON;
 
connector->dpms = mode;
-   drm_object_property_set_value(>base,
- dpms_prop, mode);
}
}
 
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 8072e6e4c62c..0e9e3161bdd0 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1225,8 +1225,7 @@ int drm_mode_connector_set_obj_prop(struct 
drm_mode_object *obj,
} else if (connector->funcs->set_property)
ret = connector->funcs->set_property(connector, property, 
value);
 
-   /* store the property value if successful */
-   if (!ret)
+   if (!ret && !drm_drv_uses_atomic_modeset(property->dev))
drm_object_property_set_value(>base, property, 
value);
return ret;
 }
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 5af25ce5bf7c..9271235d84b0 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -736,7 +736,7 @@ int drm_mode_crtc_set_obj_prop(struct drm_mode_object *obj,
 
if (crtc->funcs->set_property)
ret = crtc->funcs->set_property(crtc, property, value);
-   if (!ret)
+   if (!ret && !drm_drv_uses_atomic_modeset(property->dev))
drm_object_property_set_value(obj, property, value);
 
return ret;
diff --git a/drivers/gpu/drm/drm_mode_object.c 
b/drivers/gpu/drm/drm_mode_object.c
index da9a9adbcc98..92743a796bf0 100644
--- a/drivers/gpu/drm/drm_mode_object.c
+++ b/drivers/gpu/drm/drm_mode_object.c
@@ -233,6 +233,9 @@ int drm_object_property_set_value(struct drm_mode_object 
*obj,
 {
int i;
 
+   WARN_ON(drm_drv_uses_atomic_modeset(property->dev) &&
+   !(property->flags & DRM_MODE_PROP_IMMUTABLE));
+
for (i = 0; i < obj->properties->count; i++) {
if (obj->properties->properties[i] == property) {
obj->properties->values[i] = val;
@@ -244,24 +247,7 @@ int drm_object_property_set_value(struct drm_mode_object 
*obj,
 }
 EXPORT_SYMBOL(drm_object_property_set_value);
 
-/**
- * drm_object_property_get_value - retrieve the value of a property
- * @obj: drm mode object to get property value from
- * @property: property to retrieve
- * @val: storage for the property value
- *
- * This function retrieves the softare state of the given property for the 

Re: [Intel-gfx] [PATCH i-g-t] lib/drmtest: Decode driver flags on failure

[Chris Wilson]

Quoting Daniel Vetter (2017-07-25 12:37:08)
> I spent too much time going wtf why does this test not run until
> realizing that vgem is missing. This should help a lot for tests that
> need multiple different drm drivers.
> 
> Signed-off-by: Daniel Vetter 
> ---
>  lib/drmtest.c | 21 -
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/drmtest.c b/lib/drmtest.c
> index 480bd0b132cd..944c6e02fd31 100644
> --- a/lib/drmtest.c
> +++ b/lib/drmtest.c
> @@ -341,6 +341,24 @@ static void quiescent_gpu_at_exit_render(int sig)
> at_exit_drm_render_fd = -1;
>  }
>  
> +static const char *chipset_to_str(int chipset)
> +{
> +   switch (chipset) {
> +   case DRIVER_INTEL:
> +   return "intel";
> +   case DRIVER_VC4:
> +   return "vc4";
> +   case DRIVER_VGEM:
> +   return "vgem";
> +   case DRIVER_VIRTIO:
> +   return "virtio";
> +   case DRIVER_AMDGPU:
> +   return "amdgpu";
case DRIVER_ANY:
> +   return "any";
> +   default:
return "other";
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[Intel-gfx] [PATCH i-g-t] lib/drmtest: Decode driver flags on failure

[Daniel Vetter]

I spent too much time going wtf why does this test not run until
realizing that vgem is missing. This should help a lot for tests that
need multiple different drm drivers.

Signed-off-by: Daniel Vetter 
---
 lib/drmtest.c | 21 -
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/lib/drmtest.c b/lib/drmtest.c
index 480bd0b132cd..944c6e02fd31 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -341,6 +341,24 @@ static void quiescent_gpu_at_exit_render(int sig)
at_exit_drm_render_fd = -1;
 }
 
+static const char *chipset_to_str(int chipset)
+{
+   switch (chipset) {
+   case DRIVER_INTEL:
+   return "intel";
+   case DRIVER_VC4:
+   return "vc4";
+   case DRIVER_VGEM:
+   return "vgem";
+   case DRIVER_VIRTIO:
+   return "virtio";
+   case DRIVER_AMDGPU:
+   return "amdgpu";
+   default:
+   return "any";
+   }
+}
+
 /**
  * drm_open_driver:
  * @chipset: OR'd flags for each chipset to search, eg. #DRIVER_INTEL
@@ -356,7 +374,8 @@ int drm_open_driver(int chipset)
int fd;
 
fd = __drm_open_driver(chipset);
-   igt_skip_on_f(fd<0, "No known gpu found\n");
+   igt_skip_on_f(fd<0, "No known gpu found for chipset flags 0x%u (%s)\n",
+ chipset, chipset_to_str(chipset));
 
/* For i915, at least, we ensure that the driver is idle before
 * starting a test and we install an exit handler to wait until
-- 
2.13.3

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Re: [Intel-gfx] [PATCH v7 3/3] drm/i915: Implement I915_PERF_ADD/REMOVE_CONFIG interface

[Datczuk, Andrzej]

I think you looked only at the changes prepared previously by Matthew and just 
ported by me. I made a change on top of it in a third patch to alight the 
whitelist with MDAPI needs. 
The change you're looking for is "Subject: [PATCH 3/3] drm/i915: extended oa 
reg addresses whitelist". To make it easier below is the list:

Perf modified   Perf modified 
Name 
<0x2710,2b00), 0x2b04   b_counter
0xE458, 0xE45C, 0xE558, 0xE55C, 0xE658, 0xE65C, 0xE758  flex
<0x9800,0x9ec0> mux 
<0x25100,0x2ff90>   mux 
<0xD04,0xD2C>, 0xE180   mux 
<0x182300,0x1823A4> mux 
0x20CC  mux 
<0x91B8,0x91C8> mux

Regards,
Andrzej

-Original Message-
From: Landwerlin, Lionel G 
Sent: Tuesday, July 25, 2017 12:52 PM
To: Datczuk, Andrzej ; 
intel-gfx@lists.freedesktop.org
Cc: Auld, Matthew ; ch...@chris-wilson.co.uk
Subject: Re: [PATCH v7 3/3] drm/i915: Implement I915_PERF_ADD/REMOVE_CONFIG 
interface

Hi Andrzej,

Thanks for the feedback. Can you tell me if that following changes are correct?

Cheers,

-
Lionel

On 25/07/17 10:06, Datczuk, Andrzej wrote:
> Hi Lionel,
>
> What about the corrected whitelist I sent you before? Without allowing those 
> registers the patch for MDAPI is basically useless.
> FYI The whitelist from the patches I sent you contained merged ranges for 
> gen7-9 platforms.
>
> Regards,
> Andrzej
>
>   
> +static bool gen8_is_valid_flex_addr(struct drm_i915_private 
> +*dev_priv,
> +u32 addr) {
> + static const i915_reg_t flex_eu_regs[] = {
> + EU_PERF_CNTL0,
> + EU_PERF_CNTL1,
> + EU_PERF_CNTL2,
> + EU_PERF_CNTL3,
> + EU_PERF_CNTL4,
> + EU_PERF_CNTL5,
> + EU_PERF_CNTL6,
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
> + if (flex_eu_regs[i].reg == addr)
> + return true;
> + }
> + return false;
> +}
> +
> +static bool gen7_is_valid_b_counter_addr(struct drm_i915_private 
> +*dev_priv, u32 addr) {
> + return (addr >= 0x2380 && addr <= 0x27ac); }

Here I dropped 0x2b20 because it's an interruption register. It probably should 
be left to its default value and only managed by the kernel.

Though I made a mistake as this should be addr >= 0x2374 && addr <= 0x27ac.

> +
> +static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv,
> +u32 addr) {
> + return addr == NOA_WRITE.reg ||
> + (addr >= 0xd0c && addr <= 0xd3c) ||

Arg, missing 0xd24/0xd28 here...

> + (addr >= 0x25100 && addr <= 0x2FB9C); }
> +
> +static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv,
> +u32 addr) {
> + return (addr >= 0x25100 && addr <= 0x2FF90) ||
> + gen7_is_valid_mux_addr(dev_priv, addr); }
> +
> +static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv,
> +u32 addr) {
> + return (addr >= 0x182300 && addr <= 0x1823A4) ||
> + gen7_is_valid_mux_addr(dev_priv, addr); }
> +
> +



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Re: [Intel-gfx] [PATCH 15/20] drm/i915: Don't touch fence->error when resetting an innocent request

[Chris Wilson]

Quoting Michel Thierry (2017-07-24 20:32:21)
> On 7/24/2017 6:32 AM, Chris Wilson wrote:
> > Quoting Chris Wilson (2017-07-21 13:32:33)
> >> If the request has been completed before the reset took effect, we don't
> >> need to mark it up as being a victim. Touching fence->error after the
> >> fence has been signaled is detected by dma_fence_set_error() and
> >> triggers a BUG:
> >>
> >> [  231.743133] kernel BUG at ./include/linux/dma-fence.h:434!
> >> [  231.743156] invalid opcode:  [#1] SMP KASAN
> >> [  231.743172] Modules linked in: i915 drm_kms_helper drm iptable_nat 
> >> nf_nat_ipv4 nf_nat x86_pkg_temp_thermal iosf_mbi i2c_algo_bit cfbfillrect 
> >> syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea fb 
> >> font fbdev [last unloaded: drm]
> >> [  231.743221] CPU: 2 PID: 20 Comm: kworker/2:0 Tainted: G U  
> >> 4.13.0-rc1+ #52
> >> [  231.743236] Hardware name: Hewlett-Packard HP EliteBook 8460p/161C, 
> >> BIOS 68SCF Ver. F.01 03/11/2011
> >> [  231.743363] Workqueue: events_long i915_hangcheck_elapsed [i915]
> >> [  231.743382] task: 8801f42e9780 task.stack: 8801f42f8000
> >> [  231.743489] RIP: 0010:i915_gem_reset_engine+0x45a/0x460 [i915]
> >> [  231.743505] RSP: 0018:8801f42ff770 EFLAGS: 00010202
> >> [  231.743521] RAX: 0007 RBX: 8801bf6b1880 RCX: 
> >> a02881a6
> >> [  231.743537] RDX: dc00 RSI: dc00 RDI: 
> >> 8801bf6b18c8
> >> [  231.743551] RBP: 8801f42ff7c8 R08: 0001 R09: 
> >> 
> >> [  231.743566] R10:  R11:  R12: 
> >> 8801edb02d00
> >> [  231.743581] R13: 8801e19d4200 R14: 001d R15: 
> >> 8801ce2a4000
> >> [  231.743599] FS:  () GS:8801f5a8() 
> >> knlGS:
> >> [  231.743614] CS:  0010 DS:  ES:  CR0: 80050033
> >> [  231.743629] CR2: 7f0ebd1add10 CR3: 02621000 CR4: 
> >> 000406e0
> >> [  231.743643] Call Trace:
> >> [  231.743752]  i915_gem_reset+0x6c/0x150 [i915]
> >> [  231.743853]  i915_reset+0x175/0x210 [i915]
> >> [  231.743958]  i915_reset_device+0x33b/0x350 [i915]
> >> [  231.744061]  ? valleyview_pipestat_irq_handler+0xe0/0xe0 [i915]
> >> [  231.744081]  ? trace_hardirqs_off_caller+0x70/0x110
> >> [  231.744102]  ? _raw_spin_unlock_irqrestore+0x46/0x50
> >> [  231.744120]  ? find_held_lock+0x119/0x150
> >> [  231.744138]  ? mark_lock+0x6d/0x850
> >> [  231.744241]  ? gen8_gt_irq_ack+0x1f0/0x1f0 [i915]
> >> [  231.744262]  ? work_on_cpu_safe+0x60/0x60
> >> [  231.744284]  ? rcu_read_lock_sched_held+0x57/0xa0
> >> [  231.744400]  ? gen6_read32+0x2ba/0x320 [i915]
> >> [  231.744506]  i915_handle_error+0x382/0x5f0 [i915]
> >> [  231.744611]  ? gen6_rps_reset_ei+0x20/0x20 [i915]
> >> [  231.744630]  ? vsnprintf+0x128/0x8e0
> >> [  231.744649]  ? pointer+0x6b0/0x6b0
> >> [  231.744667]  ? debug_check_no_locks_freed+0x1a0/0x1a0
> >> [  231.744688]  ? scnprintf+0x92/0xe0
> >> [  231.744706]  ? snprintf+0xb0/0xb0
> >> [  231.744820]  hangcheck_declare_hang+0x15a/0x1a0 [i915]
> >> [  231.744932]  ? engine_stuck+0x440/0x440 [i915]
> >> [  231.744951]  ? rcu_read_lock_sched_held+0x57/0xa0
> >> [  231.745062]  ? gen6_read32+0x2ba/0x320 [i915]
> >> [  231.745173]  ? gen6_read16+0x320/0x320 [i915]
> >> [  231.745284]  ? intel_engine_get_active_head+0x91/0x170 [i915]
> >> [  231.745401]  i915_hangcheck_elapsed+0x3d8/0x400 [i915]
> >> [  231.745424]  process_one_work+0x3e8/0xac0
> >> [  231.745444]  ? pwq_dec_nr_in_flight+0x110/0x110
> >> [  231.745464]  ? do_raw_spin_lock+0x8e/0x120
> >> [  231.745484]  worker_thread+0x8d/0x720
> >> [  231.745506]  kthread+0x19e/0x1f0
> >> [  231.745524]  ? process_one_work+0xac0/0xac0
> >> [  231.745541]  ? kthread_create_on_node+0xa0/0xa0
> >> [  231.745560]  ret_from_fork+0x27/0x40
> >> [  231.745581] Code: 8b 7d c8 e8 49 0d 02 e1 49 8b 7f 38 48 8b 75 b8 48 83 
> >> c7 10 e8 b8 89 be e1 e9 95 fc ff ff 4c 89 e7 e8 4b b9 ff ff e9 30 ff ff ff 
> >> <0f> 0b 0f 1f 40 00 55 48 89 e5 41 57 41 56 41 55 41 54 49 89 fe
> >> [  231.745767] RIP: i915_gem_reset_engine+0x45a/0x460 [i915] RSP: 
> >> 8801f42ff770
> >>
> >> At first glance this looks to be related to commit c64992e035d7
> >> ("drm/i915: Look for active requests earlier in the reset path"), but it
> >> could easily happen before as well. On the other hand, we no longer
> >> logged victims due to the active_request being dropped earlier.
> >>
> >> v2: Be trickier to unwind the incomplete request as we cannot rely on
> >> request retirement for the lockless per-engine reset.
> >> v3: Reprobe the active request at the time of the reset.
> >>
> >> Reported-by: Daniel Vetter 
> >> Fixes: c64992e035d7 ("drm/i915: Look for active requests earlier in the 
> >> reset path")
> >> Signed-off-by: Chris Wilson 
> >> Cc: Michel Thierry 
> >> Cc: Mika Kuoppala 

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add perf property support for context HW id

[Lionel Landwerlin]

On 25/07/17 05:26, Zhenyu Wang wrote:

On 2017.07.21 14:01:01 +0100, Lionel Landwerlin wrote:

I think Chris' comments show this isn't actually tested.

It turned out that's true...so currently Pengyuan just tried to
filter by exposed vGPU ctx_hw_id with global mode in gputop. Would
that be ok with you? If yes, then we don't need i915 perf change.


If that works for you, it's great.
I kind of like to have the hw_id in userspace too, it's pretty handy to 
debug IGT tests :)

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Re: [Intel-gfx] [PATCH v7 3/3] drm/i915: Implement I915_PERF_ADD/REMOVE_CONFIG interface

[Lionel Landwerlin]

Hi Andrzej,

Thanks for the feedback. Can you tell me if that following changes are 
correct?


Cheers,

-
Lionel

On 25/07/17 10:06, Datczuk, Andrzej wrote:

Hi Lionel,

What about the corrected whitelist I sent you before? Without allowing those 
registers the patch for MDAPI is basically useless.
FYI The whitelist from the patches I sent you contained merged ranges for 
gen7-9 platforms.

Regards,
Andrzej

  
+static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv,

+u32 addr) {
+   static const i915_reg_t flex_eu_regs[] = {
+   EU_PERF_CNTL0,
+   EU_PERF_CNTL1,
+   EU_PERF_CNTL2,
+   EU_PERF_CNTL3,
+   EU_PERF_CNTL4,
+   EU_PERF_CNTL5,
+   EU_PERF_CNTL6,
+   };
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
+   if (flex_eu_regs[i].reg == addr)
+   return true;
+   }
+   return false;
+}
+
+static bool gen7_is_valid_b_counter_addr(struct drm_i915_private
+*dev_priv, u32 addr) {
+   return (addr >= 0x2380 && addr <= 0x27ac); }


Here I dropped 0x2b20 because it's an interruption register. It probably 
should be left to its default value and only managed by the kernel.


Though I made a mistake as this should be addr >= 0x2374 && addr <= 0x27ac.


+
+static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+   return addr == NOA_WRITE.reg ||
+   (addr >= 0xd0c && addr <= 0xd3c) ||


Arg, missing 0xd24/0xd28 here...


+   (addr >= 0x25100 && addr <= 0x2FB9C); }
+
+static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+   return (addr >= 0x25100 && addr <= 0x2FF90) ||
+   gen7_is_valid_mux_addr(dev_priv, addr); }
+
+static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+   return (addr >= 0x182300 && addr <= 0x1823A4) ||
+   gen7_is_valid_mux_addr(dev_priv, addr); }
+
+


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Re: [Intel-gfx] [PATCH v2 2/7] drm/atomic: Clean up drm_atomic_helper_async_check

[Maarten Lankhorst]

Op 25-07-17 om 11:27 schreef Daniel Vetter:
> On Tue, Jul 25, 2017 at 11:11 AM, Maarten Lankhorst
>  wrote:
>> Op 25-07-17 om 10:23 schreef Daniel Vetter:
>>> On Wed, Jul 19, 2017 at 04:39:15PM +0200, Maarten Lankhorst wrote:
  /*
 - * Don't do an async update if there is an outstanding commit 
 modifying
 - * the plane.  This prevents our async update's changes from getting
 - * overridden by a previous synchronous update's state.
 + * FIXME: We should prevent an async update if there is an outstanding
 + * commit modifying the plane.  This prevents our async update's
 + * changes from getting overwritten by a previous synchronous update's
 + * state.
   */
 -for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 -if (plane->crtc != crtc)
 -continue;
 -
 -spin_lock(>commit_lock);
 -commit = list_first_entry_or_null(>commit_list,
 -  struct drm_crtc_commit,
 -  commit_entry);
 -if (!commit) {
 -spin_unlock(>commit_lock);
 -continue;
 -}
 -spin_unlock(>commit_lock);
 -
 -if (!crtc->state->state)
 -continue;
 -
 -for_each_plane_in_state(crtc->state->state, __plane,
 -__plane_state, j) {
>>> I'm pretty sure this oopses, because crtc->state->state is NULL after
>>> commit. I think Gustavo needs to review this first (and write a nasty igt
>>> testcase to catch it) before we remove this. I think the correct check is
>>> to simply bail out if our current crtc has a pending commit (i.e.
>>> !list_empty(>commit_list) should be all we need to check.
>> It didn't oops. Right above it was a null check. It was never executed. :)
>>
>> obj->state->state is always NULL. Excluding a brief moment during swap_state 
>> where this may oops,  this code willl never do a thing.
> Oh right. It's still completely buggy, and I'd like to fix that first,
> testcase included. Can you pls poke Gustavo a bit (or maybe he's on
> vacation)?
> -Daniel

The only thing we have atm excercising it is kms_cursor_legacy, but that 
doesn't check if flips can be overwritten.
Perhaps we should make IGT tests a requirement for features in the future?

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Re: [Intel-gfx] [PATCH 0/4] [v2] Blobifiers (FKA GET_PLANE2)

[Philippe CORNU]

On 07/24/2017 05:46 AM, Ben Widawsky wrote:
> Second attempt (although most patches are much further along than that) and 
> the
> blob property for modifiers.
> 
> This small series adds the DRM blob property that allows clients to be made
> aware of per plane modifiers and the formats which are supported in 
> conjunction
> with  those modifiers. This interface will allow clients to create buffers for
> scanout with a good set of modifiers, and later import those buffers (through
> EGL already, and Vulkan WSI later) into a graphics runtime. EGL/WSI will 
> provide
> similar interfaces for rendering - modifiers which can be used for rendering.
> 
> Ben Widawsky (4):
>drm: Plumb modifiers through plane init
>drm: Create a format/modifier blob
>drm/i915: Add format modifiers for Intel
>drm/i915: Add support for CCS modifiers
> 
>   drivers/gpu/drm/arc/arcpgu_crtc.c   |   1 +
>   drivers/gpu/drm/arm/hdlcd_crtc.c|   1 +
>   drivers/gpu/drm/arm/malidp_planes.c |   2 +-
>   drivers/gpu/drm/armada/armada_crtc.c|   1 +
>   drivers/gpu/drm/armada/armada_overlay.c |   1 +
>   drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |   3 +-
>   drivers/gpu/drm/drm_mode_config.c   |   7 +
>   drivers/gpu/drm/drm_modeset_helper.c|   1 +
>   drivers/gpu/drm/drm_plane.c | 120 +-
>   drivers/gpu/drm/drm_simple_kms_helper.c |   3 +
>   drivers/gpu/drm/exynos/exynos_drm_plane.c   |   2 +-
>   drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c |   2 +-
>   drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c  |   1 +
>   drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c |   2 +-
>   drivers/gpu/drm/i915/intel_display.c| 148 +-
>   drivers/gpu/drm/i915/intel_drv.h|   1 -
>   drivers/gpu/drm/i915/intel_sprite.c | 162 
> +++-
>   drivers/gpu/drm/imx/ipuv3-plane.c   |   4 +-
>   drivers/gpu/drm/mediatek/mtk_drm_plane.c|   2 +-
>   drivers/gpu/drm/meson/meson_plane.c |   1 +
>   drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c   |   2 +-
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |   4 +-
>   drivers/gpu/drm/mxsfb/mxsfb_drv.c   |   2 +-
>   drivers/gpu/drm/nouveau/nv50_display.c  |   5 +-
>   drivers/gpu/drm/omapdrm/omap_plane.c|   2 +-
>   drivers/gpu/drm/pl111/pl111_display.c   |   2 +-
>   drivers/gpu/drm/qxl/qxl_display.c   |   2 +-
>   drivers/gpu/drm/rcar-du/rcar_du_plane.c |   4 +-
>   drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |   4 +-
>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   4 +-
>   drivers/gpu/drm/sti/sti_cursor.c|   2 +-
>   drivers/gpu/drm/sti/sti_gdp.c   |   2 +-
>   drivers/gpu/drm/sti/sti_hqvdp.c |   2 +-
>   drivers/gpu/drm/stm/ltdc.c  |   2 +-

for stm,

Acked-by: Philippe Cornu 
Tested-by: Philippe Cornu 

Many thanks
Philippe :-)

>   drivers/gpu/drm/sun4i/sun4i_layer.c |   2 +-
>   drivers/gpu/drm/tegra/dc.c  |  12 +-
>   drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c |   2 +-
>   drivers/gpu/drm/vc4/vc4_plane.c |   2 +-
>   drivers/gpu/drm/virtio/virtgpu_plane.c  |   2 +-
>   drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c |   4 +-
>   drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c|   4 +-
>   drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c|   4 +-
>   drivers/gpu/drm/zte/zx_plane.c  |   2 +-
>   include/drm/drm_mode_config.h   |   6 +
>   include/drm/drm_plane.h |  22 +++-
>   include/drm/drm_simple_kms_helper.h |   1 +
>   include/uapi/drm/drm_fourcc.h   |  11 ++
>   include/uapi/drm/drm_mode.h |  50 
>   48 files changed, 576 insertions(+), 52 deletions(-)
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 7/8] drm: Nuke drm_atomic_helper_connector_dpms

[Philippe CORNU]

On 07/25/2017 10:01 AM, Daniel Vetter wrote:
> It's dead code, the core handles all this directly now.
> 
> The only special case is nouveau and tda988x which used one function
> for both legacy modeset code and -nv50 atomic world instead of 2
> vtables. But amounts to exactly the same.
> 
> v2: Rebase over the panel/brideg refactorings in stm/ltdc.
> 
> Signed-off-by: Daniel Vetter 
> Cc: Archit Taneja 
> Cc: Andrzej Hajda 
> Cc: Laurent Pinchart 
> Cc: Peter Senna Tschudin 
> Cc: Martin Donnelly 
> Cc: Martyn Welch 
> Cc: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: Sean Paul 
> Cc: David Airlie 
> Cc: Inki Dae 
> Cc: Joonyoung Shim 
> Cc: Seung-Woo Kim 
> Cc: Kyungmin Park 
> Cc: Kukjin Kim 
> Cc: Krzysztof Kozlowski 
> Cc: Stefan Agner 
> Cc: Alison Wang 
> Cc: Russell King 
> Cc: Philipp Zabel 
> Cc: CK Hu 
> Cc: Matthias Brugger 
> Cc: Neil Armstrong 
> Cc: Carlo Caione 
> Cc: Kevin Hilman 
> Cc: Marek Vasut 
> Cc: Ben Skeggs 
> Cc: Tomi Valkeinen 
> Cc: Eric Anholt 
> Cc: Mark Yao 
> Cc: Heiko Stuebner 
> Cc: Benjamin Gaignard 
> Cc: Vincent Abriou 
> Cc: Yannick Fertre 
> Cc: Philippe Cornu 

Tested-by: Philippe Cornu  (on stm)

Many thanks
Philippe :-)

> Cc: Maxime Ripard 
> Cc: Chen-Yu Tsai 
> Cc: Thierry Reding 
> Cc: Jonathan Hunter 
> Cc: Jyri Sarha 
> Cc: Gerd Hoffmann 
> Cc: Shawn Guo 
> Cc: John Stultz 
> Cc: Lars-Peter Clausen 
> Cc: Sergei Shtylyov 
> Cc: Jeffy Chen 
> Cc: Tomeu Vizoso 
> Cc: Yakir Yang 
> Cc: Marek Szyprowski 
> Cc: Jose Abreu 
> Cc: Romain Perier 
> Cc: Kieran Bingham 
> Cc: Xinliang Liu 
> Cc: Alexey Brodkin 
> Cc: Alex Deucher 
> Cc: Rongrong Zou 
> Cc: Rob Clark 
> Cc: Hai Li 
> Cc: "Noralf Trønnes" 
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-samsung-...@vger.kernel.org
> Cc: intel-gfx@lists.freedesktop.org
> Cc: linux-media...@lists.infradead.org
> Cc: linux-amlo...@lists.infradead.org
> Cc: nouv...@lists.freedesktop.org
> Cc: linux-renesas-...@vger.kernel.org
> Cc: linux-rockc...@lists.infradead.org
> Cc: linux-te...@vger.kernel.org
> Cc: virtualizat...@lists.linux-foundation.org
> Cc: zain wang 
> Cc: Baoyou Xie 
> Cc: Boris Brezillon 
> ---
>   drivers/gpu/drm/bridge/adv7511/adv7511_drv.c   |  1 -
>   drivers/gpu/drm/bridge/analogix-anx78xx.c  |  1 -
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c |  1 -
>   drivers/gpu/drm/bridge/dumb-vga-dac.c  |  1 -
>   .../drm/bridge/megachips-stdp-ge-b850v3-fw.c   |  1 -
>   drivers/gpu/drm/bridge/nxp-ptn3460.c   |  1 -
>   drivers/gpu/drm/bridge/panel.c |  1 -
>   drivers/gpu/drm/bridge/parade-ps8622.c |  1 -
>   drivers/gpu/drm/bridge/sii902x.c   |  1 -
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.c  |  1 -
>   drivers/gpu/drm/bridge/tc358767.c  |  1 -
>   drivers/gpu/drm/bridge/ti-tfp410.c |  1 -
>   drivers/gpu/drm/drm_atomic_helper.c| 79 
> --
>   drivers/gpu/drm/exynos/exynos_drm_dpi.c|  1 -
>   drivers/gpu/drm/exynos/exynos_drm_dsi.c|  1 -
>   drivers/gpu/drm/exynos/exynos_drm_vidi.c   |  1 -
>   drivers/gpu/drm/exynos/exynos_hdmi.c   |  1 -
>   drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c  |  1 -
>   drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c   |  1 -
>   drivers/gpu/drm/i2c/tda998x_drv.c  | 10 +--
>   drivers/gpu/drm/i915/intel_crt.c   |  1 -
>   

Re: [Intel-gfx] [PATCH 4/8] drm: Nuke drm_atomic_helper_crtc_set_property

[Philippe CORNU]

On 07/25/2017 10:01 AM, Daniel Vetter wrote:
> It's dead code because this is now handled in the core.
> 
> Signed-off-by: Daniel Vetter 
> Cc: Boris Brezillon 
> Cc: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: Sean Paul 
> Cc: David Airlie 
> Cc: Ben Skeggs 
> Cc: Tomi Valkeinen 
> Cc: Laurent Pinchart 
> Cc: Alexey Brodkin 
> Cc: Shawn Guo 
> Cc: Eric Engestrom 
> Cc: Chris Wilson 
> Cc: "Ville Syrjälä" 
> Cc: Rob Clark 
> Cc: Philippe Cornu 

Tested-by: Philippe Cornu 

Many thanks
Philippe :-)

> Cc: Masahiro Yamada 
> Cc: Sushmita Susheelendra 
> Cc: Archit Taneja 
> Cc: intel-gfx@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: Philipp Zabel 
> Cc: Maxime Ripard 
> Cc: Thomas Hellstrom 
> ---
>   drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c  |  1 -
>   drivers/gpu/drm/drm_atomic_helper.c | 55 
> -
>   drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c |  1 -
>   drivers/gpu/drm/i915/intel_display.c|  1 -
>   drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c|  1 -
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  2 -
>   drivers/gpu/drm/nouveau/nv50_display.c  |  1 -
>   drivers/gpu/drm/omapdrm/omap_crtc.c |  1 -
>   include/drm/drm_atomic_helper.h |  3 --
>   9 files changed, 66 deletions(-)
> 
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 4fbbeab5c5d4..d73281095fac 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -431,7 +431,6 @@ static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs 
> = {
>   .atomic_destroy_state = atmel_hlcdc_crtc_destroy_state,
>   .enable_vblank = atmel_hlcdc_crtc_enable_vblank,
>   .disable_vblank = atmel_hlcdc_crtc_disable_vblank,
> - .set_property = drm_atomic_helper_crtc_set_property,
>   .gamma_set = drm_atomic_helper_legacy_gamma_set,
>   };
>   
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 4a960c741e35..22245aa8b1aa 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -2968,61 +2968,6 @@ int drm_atomic_helper_resume(struct drm_device *dev,
>   EXPORT_SYMBOL(drm_atomic_helper_resume);
>   
>   /**
> - * drm_atomic_helper_crtc_set_property - helper for crtc properties
> - * @crtc: DRM crtc
> - * @property: DRM property
> - * @val: value of property
> - *
> - * Provides a default crtc set_property handler using the atomic driver
> - * interface.
> - *
> - * RETURNS:
> - * Zero on success, error code on failure
> - */
> -int
> -drm_atomic_helper_crtc_set_property(struct drm_crtc *crtc,
> - struct drm_property *property,
> - uint64_t val)
> -{
> - struct drm_atomic_state *state;
> - struct drm_crtc_state *crtc_state;
> - int ret = 0;
> -
> - state = drm_atomic_state_alloc(crtc->dev);
> - if (!state)
> - return -ENOMEM;
> -
> - /* ->set_property is always called with all locks held. */
> - state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
> -retry:
> - crtc_state = drm_atomic_get_crtc_state(state, crtc);
> - if (IS_ERR(crtc_state)) {
> - ret = PTR_ERR(crtc_state);
> - goto fail;
> - }
> -
> - ret = drm_atomic_crtc_set_property(crtc, crtc_state,
> - property, val);
> - if (ret)
> - goto fail;
> -
> - ret = drm_atomic_commit(state);
> -fail:
> - if (ret == -EDEADLK)
> - goto backoff;
> -
> - drm_atomic_state_put(state);
> - return ret;
> -
> -backoff:
> - drm_atomic_state_clear(state);
> - drm_atomic_legacy_backoff(state);
> -
> - goto retry;
> -}
> -EXPORT_SYMBOL(drm_atomic_helper_crtc_set_property);
> -
> -/**
>* drm_atomic_helper_plane_set_property - helper for plane properties
>* @plane: DRM plane
>* @property: DRM property
> diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 
> b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
> index 706efd0c4190..961551135a39 100644
> --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
> +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
> @@ -567,7 +567,6 @@ static const struct drm_crtc_funcs ade_crtc_funcs = {
>   .set_config = 

Re: [Intel-gfx] [PATCH 5/8] drm: Nuke drm_atomic_helper_plane_set_property

[Philippe CORNU]

On 07/25/2017 10:01 AM, Daniel Vetter wrote:
> It's dead code, the core handles all this directly now. This also
> allows us to unexport drm_atomic_helper_plane_set_property.
> 
> Signed-off-by: Daniel Vetter 
> Cc: Liviu Dudau 
> Cc: Brian Starkey 
> Cc: Mali DP Maintainers 
> Cc: Boris Brezillon 
> Cc: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: Sean Paul 
> Cc: David Airlie 
> Cc: Inki Dae 
> Cc: Joonyoung Shim 
> Cc: Seung-Woo Kim 
> Cc: Kyungmin Park 
> Cc: Kukjin Kim 
> Cc: Krzysztof Kozlowski 
> Cc: Ben Skeggs 
> Cc: Tomi Valkeinen 
> Cc: Laurent Pinchart 
> Cc: Benjamin Gaignard 
> Cc: Vincent Abriou 
> Cc: Yannick Fertre 
> Cc: Philippe Cornu 

for stm,

Acked-by: Philippe Cornu 
Tested-by: Philippe Cornu 

Many thanks
Philippe :-)

> Cc: Jyri Sarha 
> Cc: "Ville Syrjälä" 
> Cc: Rongrong Zou 
> Cc: Shawn Guo 
> Cc: Alexey Brodkin 
> Cc: Eric Engestrom 
> Cc: Chris Wilson 
> Cc: Rob Clark 
> Cc: Archit Taneja 
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-samsung-...@vger.kernel.org
> Cc: intel-gfx@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: linux-renesas-...@vger.kernel.org
> Cc: Thomas Hellstrom 
> Cc: Maxime Ripard 
> ---
>   drivers/gpu/drm/arm/malidp_planes.c |  1 -
>   drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |  1 -
>   drivers/gpu/drm/drm_atomic.c|  3 +-
>   drivers/gpu/drm/drm_atomic_helper.c | 55 
> -
>   drivers/gpu/drm/exynos/exynos_drm_plane.c   |  1 -
>   drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c  |  1 -
>   drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c |  1 -
>   drivers/gpu/drm/i915/intel_display.c|  2 -
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |  2 -
>   drivers/gpu/drm/nouveau/nv50_display.c  |  1 -
>   drivers/gpu/drm/omapdrm/omap_plane.c|  1 -
>   drivers/gpu/drm/rcar-du/rcar_du_plane.c |  1 -
>   drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |  1 -
>   drivers/gpu/drm/sti/sti_cursor.c|  1 -
>   drivers/gpu/drm/sti/sti_gdp.c   |  1 -
>   drivers/gpu/drm/sti/sti_hqvdp.c |  1 -
>   drivers/gpu/drm/stm/ltdc.c  |  1 -
>   drivers/gpu/drm/tilcdc/tilcdc_plane.c   |  1 -
>   include/drm/drm_atomic.h|  3 --
>   include/drm/drm_atomic_helper.h |  3 --
>   20 files changed, 1 insertion(+), 81 deletions(-)
> 
> diff --git a/drivers/gpu/drm/arm/malidp_planes.c 
> b/drivers/gpu/drm/arm/malidp_planes.c
> index 600fa7bd7f52..0f0f8234fe21 100644
> --- a/drivers/gpu/drm/arm/malidp_planes.c
> +++ b/drivers/gpu/drm/arm/malidp_planes.c
> @@ -128,7 +128,6 @@ static void malidp_plane_atomic_print_state(struct 
> drm_printer *p,
>   static const struct drm_plane_funcs malidp_de_plane_funcs = {
>   .update_plane = drm_atomic_helper_update_plane,
>   .disable_plane = drm_atomic_helper_disable_plane,
> - .set_property = drm_atomic_helper_plane_set_property,
>   .destroy = malidp_de_plane_destroy,
>   .reset = malidp_plane_reset,
>   .atomic_duplicate_state = malidp_duplicate_plane_state,
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> index b5bd9b005225..9cd9e23e75c6 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> @@ -1052,7 +1052,6 @@ static void 
> atmel_hlcdc_plane_atomic_destroy_state(struct drm_plane *p,
>   static struct drm_plane_funcs layer_plane_funcs = {
>   .update_plane = drm_atomic_helper_update_plane,
>   .disable_plane = drm_atomic_helper_disable_plane,
> - .set_property = drm_atomic_helper_plane_set_property,
>   .destroy = atmel_hlcdc_plane_destroy,
>   .reset = atmel_hlcdc_plane_reset,
>   .atomic_duplicate_state = atmel_hlcdc_plane_atomic_duplicate_state,
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 0fd14aff7add..395438a7a576 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -713,7 +713,7 @@ 

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/gvt: Dma-buf support for GVT-g

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: Dma-buf support for GVT-g
URL   : https://patchwork.freedesktop.org/series/27844/
State : warning

== Summary ==

Series 27844v1 drm/i915/gvt: Dma-buf support for GVT-g
https://patchwork.freedesktop.org/api/1.0/series/27844/revisions/1/mbox/

Test gem_ringfill:
Subgroup basic-default:
pass   -> SKIP   (fi-bsw-n3050)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-n2820) fdo#101705

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:444s
fi-bdw-gvtdvmtotal:280  pass:265  dwarn:1   dfail:0   fail:0   skip:14  
time:430s
fi-blb-e6850 total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  
time:352s
fi-bsw-n3050 total:280  pass:243  dwarn:0   dfail:0   fail:0   skip:37  
time:529s
fi-bxt-j4205 total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:512s
fi-byt-j1900 total:280  pass:256  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:489s
fi-glk-2atotal:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  
time:600s
fi-hsw-4770  total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:440s
fi-hsw-4770r total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-ilk-650   total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  
time:417s
fi-ivb-3520m total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:504s
fi-ivb-3770  total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7500u total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:469s
fi-kbl-7560u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:575s
fi-kbl-r total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:587s
fi-pnv-d510  total:280  pass:223  dwarn:2   dfail:0   fail:0   skip:55  
time:566s
fi-skl-6260u total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:456s
fi-skl-6700hqtotal:280  pass:263  dwarn:0   dfail:0   fail:0   skip:17  
time:585s
fi-skl-6700k total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-skl-6770hqtotal:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  
time:482s
fi-skl-gvtdvmtotal:280  pass:266  dwarn:1   dfail:0   fail:0   skip:13  
time:440s
fi-skl-x1585ltotal:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  
time:472s
fi-snb-2520m total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-snb-2600  total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  
time:399s

9e377e5fc2f8360c01787ebfe16e1bea778b4d9d drm-tip: 2017y-07m-25d-07h-06m-30s UTC 
integration manifest
35d5cd644bed drm/i915/gvt: Dmabuf support for GVT-g
9b4dfe796c3c drm/i915: Introduce GEM proxy
1399f4fa4e78 vfio: ABI for mdev display dma-buf operation
bcf25e9eb909 drm/i915/gvt: Add opregion support
1297435bc1a6 drm/i915/gvt: Add RGB 64-bit 16:16:16:16 float format support
aea01e3fd71a drm: Introduce RGB 64-bit 16:16:16:16 float format
833445cae249 drm/i915/gvt: Add framebuffer decoder support

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5271/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/8] drm: Nuke drm_atomic_helper_plane_set_property

[Archit Taneja]

On 07/25/2017 01:31 PM, Daniel Vetter wrote:

It's dead code, the core handles all this directly now. This also
allows us to unexport drm_atomic_helper_plane_set_property.



Reviewed-by: Archit Taneja 


Signed-off-by: Daniel Vetter 
Cc: Liviu Dudau 
Cc: Brian Starkey 
Cc: Mali DP Maintainers 
Cc: Boris Brezillon 
Cc: Daniel Vetter 
Cc: Jani Nikula 
Cc: Sean Paul 
Cc: David Airlie 
Cc: Inki Dae 
Cc: Joonyoung Shim 
Cc: Seung-Woo Kim 
Cc: Kyungmin Park 
Cc: Kukjin Kim 
Cc: Krzysztof Kozlowski 
Cc: Ben Skeggs 
Cc: Tomi Valkeinen 
Cc: Laurent Pinchart 
Cc: Benjamin Gaignard 
Cc: Vincent Abriou 
Cc: Yannick Fertre 
Cc: Philippe Cornu 
Cc: Jyri Sarha 
Cc: "Ville Syrjälä" 
Cc: Rongrong Zou 
Cc: Shawn Guo 
Cc: Alexey Brodkin 
Cc: Eric Engestrom 
Cc: Chris Wilson 
Cc: Rob Clark 
Cc: Archit Taneja 
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-samsung-...@vger.kernel.org
Cc: intel-gfx@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
Cc: linux-renesas-...@vger.kernel.org
Cc: Thomas Hellstrom 
Cc: Maxime Ripard 
---
  drivers/gpu/drm/arm/malidp_planes.c |  1 -
  drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |  1 -
  drivers/gpu/drm/drm_atomic.c|  3 +-
  drivers/gpu/drm/drm_atomic_helper.c | 55 -
  drivers/gpu/drm/exynos/exynos_drm_plane.c   |  1 -
  drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c  |  1 -
  drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c |  1 -
  drivers/gpu/drm/i915/intel_display.c|  2 -
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |  2 -
  drivers/gpu/drm/nouveau/nv50_display.c  |  1 -
  drivers/gpu/drm/omapdrm/omap_plane.c|  1 -
  drivers/gpu/drm/rcar-du/rcar_du_plane.c |  1 -
  drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |  1 -
  drivers/gpu/drm/sti/sti_cursor.c|  1 -
  drivers/gpu/drm/sti/sti_gdp.c   |  1 -
  drivers/gpu/drm/sti/sti_hqvdp.c |  1 -
  drivers/gpu/drm/stm/ltdc.c  |  1 -
  drivers/gpu/drm/tilcdc/tilcdc_plane.c   |  1 -
  include/drm/drm_atomic.h|  3 --
  include/drm/drm_atomic_helper.h |  3 --
  20 files changed, 1 insertion(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/arm/malidp_planes.c 
b/drivers/gpu/drm/arm/malidp_planes.c
index 600fa7bd7f52..0f0f8234fe21 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -128,7 +128,6 @@ static void malidp_plane_atomic_print_state(struct 
drm_printer *p,
  static const struct drm_plane_funcs malidp_de_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
-   .set_property = drm_atomic_helper_plane_set_property,
.destroy = malidp_de_plane_destroy,
.reset = malidp_plane_reset,
.atomic_duplicate_state = malidp_duplicate_plane_state,
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
index b5bd9b005225..9cd9e23e75c6 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
@@ -1052,7 +1052,6 @@ static void atmel_hlcdc_plane_atomic_destroy_state(struct 
drm_plane *p,
  static struct drm_plane_funcs layer_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
-   .set_property = drm_atomic_helper_plane_set_property,
.destroy = atmel_hlcdc_plane_destroy,
.reset = atmel_hlcdc_plane_reset,
.atomic_duplicate_state = atmel_hlcdc_plane_atomic_duplicate_state,
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 0fd14aff7add..395438a7a576 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -713,7 +713,7 @@ EXPORT_SYMBOL(drm_atomic_get_plane_state);
   * RETURNS:
   * Zero on success, error code on failure
   */
-int drm_atomic_plane_set_property(struct drm_plane *plane,
+static int drm_atomic_plane_set_property(struct drm_plane *plane,
struct drm_plane_state *state, struct 

Re: [Intel-gfx] [PATCH 4/8] drm: Nuke drm_atomic_helper_crtc_set_property

[Archit Taneja]

On 07/25/2017 01:31 PM, Daniel Vetter wrote:

It's dead code because this is now handled in the core.


Reviewed-by: Archit Taneja 



Signed-off-by: Daniel Vetter 
Cc: Boris Brezillon 
Cc: Daniel Vetter 
Cc: Jani Nikula 
Cc: Sean Paul 
Cc: David Airlie 
Cc: Ben Skeggs 
Cc: Tomi Valkeinen 
Cc: Laurent Pinchart 
Cc: Alexey Brodkin 
Cc: Shawn Guo 
Cc: Eric Engestrom 
Cc: Chris Wilson 
Cc: "Ville Syrjälä" 
Cc: Rob Clark 
Cc: Philippe Cornu 
Cc: Masahiro Yamada 
Cc: Sushmita Susheelendra 
Cc: Archit Taneja 
Cc: intel-gfx@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
Cc: Philipp Zabel 
Cc: Maxime Ripard 
Cc: Thomas Hellstrom 
---
  drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c  |  1 -
  drivers/gpu/drm/drm_atomic_helper.c | 55 -
  drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c |  1 -
  drivers/gpu/drm/i915/intel_display.c|  1 -
  drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c|  1 -
  drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  2 -
  drivers/gpu/drm/nouveau/nv50_display.c  |  1 -
  drivers/gpu/drm/omapdrm/omap_crtc.c |  1 -
  include/drm/drm_atomic_helper.h |  3 --
  9 files changed, 66 deletions(-)

diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index 4fbbeab5c5d4..d73281095fac 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -431,7 +431,6 @@ static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = 
{
.atomic_destroy_state = atmel_hlcdc_crtc_destroy_state,
.enable_vblank = atmel_hlcdc_crtc_enable_vblank,
.disable_vblank = atmel_hlcdc_crtc_disable_vblank,
-   .set_property = drm_atomic_helper_crtc_set_property,
.gamma_set = drm_atomic_helper_legacy_gamma_set,
  };
  
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c

index 4a960c741e35..22245aa8b1aa 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2968,61 +2968,6 @@ int drm_atomic_helper_resume(struct drm_device *dev,
  EXPORT_SYMBOL(drm_atomic_helper_resume);
  
  /**

- * drm_atomic_helper_crtc_set_property - helper for crtc properties
- * @crtc: DRM crtc
- * @property: DRM property
- * @val: value of property
- *
- * Provides a default crtc set_property handler using the atomic driver
- * interface.
- *
- * RETURNS:
- * Zero on success, error code on failure
- */
-int
-drm_atomic_helper_crtc_set_property(struct drm_crtc *crtc,
-   struct drm_property *property,
-   uint64_t val)
-{
-   struct drm_atomic_state *state;
-   struct drm_crtc_state *crtc_state;
-   int ret = 0;
-
-   state = drm_atomic_state_alloc(crtc->dev);
-   if (!state)
-   return -ENOMEM;
-
-   /* ->set_property is always called with all locks held. */
-   state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
-retry:
-   crtc_state = drm_atomic_get_crtc_state(state, crtc);
-   if (IS_ERR(crtc_state)) {
-   ret = PTR_ERR(crtc_state);
-   goto fail;
-   }
-
-   ret = drm_atomic_crtc_set_property(crtc, crtc_state,
-   property, val);
-   if (ret)
-   goto fail;
-
-   ret = drm_atomic_commit(state);
-fail:
-   if (ret == -EDEADLK)
-   goto backoff;
-
-   drm_atomic_state_put(state);
-   return ret;
-
-backoff:
-   drm_atomic_state_clear(state);
-   drm_atomic_legacy_backoff(state);
-
-   goto retry;
-}
-EXPORT_SYMBOL(drm_atomic_helper_crtc_set_property);
-
-/**
   * drm_atomic_helper_plane_set_property - helper for plane properties
   * @plane: DRM plane
   * @property: DRM property
diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 
b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
index 706efd0c4190..961551135a39 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
@@ -567,7 +567,6 @@ static const struct drm_crtc_funcs ade_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.page_flip  = drm_atomic_helper_page_flip,
.reset  = drm_atomic_helper_crtc_reset,
-   .set_property = drm_atomic_helper_crtc_set_property,

[Intel-gfx] [PATCH v13 7/7] drm/i915/gvt: Dmabuf support for GVT-g

[Tina Zhang]

This patch introduces a guest's framebuffer sharing mechanism based on
dma-buf subsystem. With this sharing mechanism, guest's framebuffer can
be shared between guest VM and host.

Signed-off-by: Tina Zhang 
---
 drivers/gpu/drm/i915/gvt/Makefile  |   2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c  | 380 +
 drivers/gpu/drm/i915/gvt/dmabuf.h  |  58 +
 drivers/gpu/drm/i915/gvt/gvt.c |   1 +
 drivers/gpu/drm/i915/gvt/gvt.h |   9 +
 drivers/gpu/drm/i915/gvt/hypercall.h   |   2 +
 drivers/gpu/drm/i915/gvt/kvmgt.c   |  42 
 drivers/gpu/drm/i915/gvt/mpt.h |  30 +++
 drivers/gpu/drm/i915/gvt/vgpu.c|   2 +-
 drivers/gpu/drm/i915/i915_gem_object.h |   2 +
 10 files changed, 526 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h

diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
index 019d596..18f43cb 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -2,7 +2,7 @@ GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
-   fb_decoder.o
+   fb_decoder.o dmabuf.o
 
 ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR)
 i915-y += $(addprefix $(GVT_DIR)/, 
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c 
b/drivers/gpu/drm/i915/gvt/dmabuf.c
new file mode 100644
index 000..b6ccd61f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Zhiyuan Lv 
+ *
+ * Contributors:
+ *Xiaoguang Chen 
+ *Tina Zhang 
+ */
+
+#include 
+#include 
+#include 
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
+
+#define VBLNAK_TIMER_PERIOD 1600
+
+static struct sg_table *intel_vgpu_gem_get_pages(
+   struct drm_i915_gem_object *obj)
+{
+   struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+   struct sg_table *st;
+   struct scatterlist *sg;
+   int i, ret;
+   gen8_pte_t __iomem *gtt_entries;
+   struct intel_vgpu_fb_info *fb_info;
+
+   fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info;
+   if (WARN_ON(!fb_info))
+   return ERR_PTR(-ENODEV);
+
+   st = kmalloc(sizeof(*st), GFP_KERNEL);
+   if (!st)
+   return ERR_PTR(-ENOMEM);
+
+   ret = sg_alloc_table(st, fb_info->size, GFP_KERNEL);
+   if (ret) {
+   kfree(st);
+   return ERR_PTR(ret);
+   }
+   gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+   (fb_info->start >> PAGE_SHIFT);
+   for_each_sg(st->sgl, sg, fb_info->size, i) {
+   sg->offset = 0;
+   sg->length = PAGE_SIZE;
+   sg_dma_address(sg) =
+   GEN8_DECODE_PTE(readq(_entries[i]));
+   sg_dma_len(sg) = PAGE_SIZE;
+   }
+
+   return st;
+}
+
+static void intel_vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
+   struct sg_table *pages)
+{
+   sg_free_table(pages);
+   kfree(pages);
+}
+
+static void intel_vgpu_gem_release(struct drm_i915_gem_object *obj)
+{
+   struct intel_vgpu_dmabuf_obj *dmabuf_obj;
+   struct intel_vgpu_fb_info *fb_info;
+   struct intel_vgpu *vgpu;
+   struct list_head *pos;
+
+   fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info;
+   if (WARN_ON(!fb_info || !fb_info->vgpu)) {
+   

Re: [Intel-gfx] [PATCH 3/8] drm: Handle properties in the core for atomic drivers

[Archit Taneja]

On 07/25/2017 01:31 PM, Daniel Vetter wrote:

The reason behind the original indirection through the helper
functions was to allow existing drivers to overwrite how they handle
properties. For example when a vendor-specific userspace had
expectations that didn't match atomic. That seemed likely, since
atomic is standardizing a _lot_ more of the behaviour of a kms driver.

But 20 drivers later there's no such need at all. Worse, this forces
all drivers to hook up the default behaviour, breaking userspace if
they forget to do that. And it forces us to export a bunch of core
function just for those helpers.

And finally, these helpers are the last places using
drm_atomic_legacy_backoff() and the implicit acquire_ctx.

This patch here just implements the new behaviour and updates the
docs. Follow-up patches will garbage-collect all the dead code.

v2: Fixup docs even better!

v3: Make it actually work ...


Reviewed-by: Archit Taneja 



Signed-off-by: Daniel Vetter 
---
  drivers/gpu/drm/drm_atomic.c|  60 ++--
  drivers/gpu/drm/drm_connector.c |   6 +-
  drivers/gpu/drm/drm_crtc_helper.c   |   3 +-
  drivers/gpu/drm/drm_crtc_internal.h |   7 +++
  drivers/gpu/drm/drm_mode_object.c   | 110 +++-
  include/drm/drm_connector.h |  10 ++--
  include/drm/drm_crtc.h  |   6 +-
  include/drm/drm_plane.h |   6 +-
  8 files changed, 158 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 01192dd3ed79..0fd14aff7add 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1864,9 +1864,60 @@ static struct drm_pending_vblank_event 
*create_vblank_event(
return e;
  }
  
-static int atomic_set_prop(struct drm_atomic_state *state,

-   struct drm_mode_object *obj, struct drm_property *prop,
-   uint64_t prop_value)
+int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state,
+struct drm_connector *connector,
+int mode)
+{
+   struct drm_connector *tmp_connector;
+   struct drm_connector_state *new_conn_state;
+   struct drm_crtc *crtc;
+   struct drm_crtc_state *crtc_state;
+   int i, ret, old_mode = connector->dpms;
+   bool active = false;
+
+   ret = drm_modeset_lock(>dev->mode_config.connection_mutex,
+  state->acquire_ctx);
+   if (ret)
+   return ret;
+
+   if (mode != DRM_MODE_DPMS_ON)
+   mode = DRM_MODE_DPMS_OFF;
+   connector->dpms = mode;
+
+   crtc = connector->state->crtc;
+   if (!crtc)
+   goto out;
+   ret = drm_atomic_add_affected_connectors(state, crtc);
+   if (ret)
+   goto out;
+
+   crtc_state = drm_atomic_get_crtc_state(state, crtc);
+   if (IS_ERR(crtc_state)) {
+   ret = PTR_ERR(crtc_state);
+   goto out;
+   }
+
+   for_each_new_connector_in_state(state, tmp_connector, new_conn_state, 
i) {
+   if (new_conn_state->crtc != crtc)
+   continue;
+   if (tmp_connector->dpms == DRM_MODE_DPMS_ON) {
+   active = true;
+   break;
+   }
+   }
+
+   crtc_state->active = active;
+   ret = drm_atomic_commit(state);
+out:
+   if (ret != 0)
+   connector->dpms = old_mode;
+   return ret;
+}
+
+int drm_atomic_set_property(struct drm_atomic_state *state,
+   struct drm_mode_object *obj,
+   struct drm_property *prop,
+   uint64_t prop_value)
  {
struct drm_mode_object *ref;
int ret;
@@ -2286,7 +2337,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
goto out;
}
  
-			ret = atomic_set_prop(state, obj, prop, prop_value);

+   ret = drm_atomic_set_property(state, obj, prop,
+ prop_value);
if (ret) {
drm_mode_object_put(obj);
goto out;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 349104eadefe..12371f184019 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -717,9 +717,9 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
   *drivers, it remaps to controlling the "ACTIVE" property on the CRTC the
   *connector is linked to. Drivers should never set this property directly,
   *it is handled by the DRM core by calling the _connector_funcs.dpms
- * callback. Atomic drivers should implement this hook using
- * drm_atomic_helper_connector_dpms(). This is the only property standard
- * connector 

[Intel-gfx] [PATCH v13 6/7] drm/i915: Introduce GEM proxy

[Tina Zhang]

GEM proxy is a kind of GEM, whose backing physical memory is pinned
and produced by guest VM and is used by host as read only. With GEM
proxy, host is able to access guest physical memory through GEM object
interface. As GEM proxy is such a special kind of GEM, a new flag
I915_GEM_OBJECT_IS_PROXY is introduced to ban host from changing the
backing storage of GEM proxy.

Signed-off-by: Tina Zhang 
---
 drivers/gpu/drm/i915/i915_gem.c| 24 +++-
 drivers/gpu/drm/i915/i915_gem_object.h |  7 +++
 drivers/gpu/drm/i915/i915_gem_tiling.c |  8 
 3 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1b2dfa8..75530fb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1624,6 +1624,16 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void 
*data,
if (err)
goto out;
 
+   /* Proxy objects do not control access to the backing storage, ergo
+* they cannot be used as a means to manipulate the cache domain
+* tracking for that backing storage. The proxy object is always
+* considered to be outside of any cache domain.
+*/
+   if (i915_gem_object_is_proxy(obj)) {
+   err = -EPERM;
+   goto out;
+   }
+
/* Flush and acquire obj->pages so that we are coherent through
 * direct access in memory with previous cached writes through
 * shmemfs and that our cache domain tracking remains valid.
@@ -1680,6 +1690,10 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void 
*data,
if (!obj)
return -ENOENT;
 
+   /* Proxy objects are barred from CPU access, so there is no
+* need to ban sw_finish as it is a nop.
+*/
+
/* Pinned buffers may be scanout, so flush the cache */
i915_gem_object_flush_if_display(obj);
i915_gem_object_put(obj);
@@ -1730,7 +1744,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 */
if (!obj->base.filp) {
i915_gem_object_put(obj);
-   return -EINVAL;
+   return -EPERM;
}
 
addr = vm_mmap(obj->base.filp, 0, args->size,
@@ -3764,6 +3778,14 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, 
void *data,
if (!obj)
return -ENOENT;
 
+   /* The caching mode of proxy object is handled by its generator, and not
+* expected to be changed by user mode.
+*/
+   if (i915_gem_object_is_proxy(obj)) {
+   ret = -EPERM;
+   goto out;
+   }
+
if (obj->cache_level == level)
goto out;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h 
b/drivers/gpu/drm/i915/i915_gem_object.h
index 5b19a49..f3b382a 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -39,6 +39,7 @@ struct drm_i915_gem_object_ops {
unsigned int flags;
 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
 #define I915_GEM_OBJECT_IS_SHRINKABLE   BIT(1)
+#define I915_GEM_OBJECT_IS_PROXY   BIT(2)
 
/* Interface between the GEM object and its backing storage.
 * get_pages() is called once prior to the use of the associated set
@@ -300,6 +301,12 @@ i915_gem_object_is_shrinkable(const struct 
drm_i915_gem_object *obj)
 }
 
 static inline bool
+i915_gem_object_is_proxy(const struct drm_i915_gem_object *obj)
+{
+   return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
+}
+
+static inline bool
 i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
 {
return obj->active_count;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c 
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index fb5231f..d12859d 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -345,6 +345,14 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void 
*data,
if (!obj)
return -ENOENT;
 
+   /* The tiling mode of proxy objects is handled by its generator, and not
+* expected to be changed by user mode.
+*/
+   if (i915_gem_object_is_proxy(obj)) {
+   err = -EPERM;
+   goto err;
+   }
+
if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
err = -EINVAL;
goto err;
-- 
2.7.4

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[Intel-gfx] [PATCH v13 5/7] vfio: ABI for mdev display dma-buf operation

[Tina Zhang]

Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user mode query and
get the plan and its related information.

The dma-buf's life cycle is handled by user mode and tracked by kernel.
The returned fd in struct vfio_device_query_gfx_plane can be a new
fd or an old fd of a re-exported dma-buf. Host User mode can check the
value of fd and to see if it needs to create new resource according to
the new fd or just use the existed resource related to the old fd.

Signed-off-by: Tina Zhang 
---
 include/uapi/linux/vfio.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
index ae46105..827a230 100644
--- a/include/uapi/linux/vfio.h
+++ b/include/uapi/linux/vfio.h
@@ -502,6 +502,34 @@ struct vfio_pci_hot_reset {
 
 #define VFIO_DEVICE_PCI_HOT_RESET  _IO(VFIO_TYPE, VFIO_BASE + 13)
 
+/**
+ * VFIO_DEVICE_QUERY_GFX_PLANE - _IOW(VFIO_TYPE, VFIO_BASE + 14, struct 
vfio_device_query_gfx_plane)
+ *
+ * Set the drm_plane_type and retrieve information about the gfx plane.
+ *
+ * Return: 0 on success, -errno on failure.
+ */
+struct vfio_device_gfx_plane_info {
+   __u32 argsz;
+   __u32 flags;
+   /* in */
+   __u32 drm_plane_type;   /* type of plane: DRM_PLANE_TYPE_* */
+   /* out */
+   __u32 drm_format;   /* drm format of plane */
+   __u64 drm_format_mod;   /* tiled mode */
+   __u32 width;/* width of plane */
+   __u32 height;   /* height of plane */
+   __u32 stride;   /* stride of plane */
+   __u32 size; /* size of plane in bytes, align on page*/
+   __u32 x_pos;/* horizontal position of cursor plane, upper left 
corner in pixels */
+   __u32 y_pos;/* vertical position of cursor plane, upper left corner 
in lines*/
+   __u32 region_index;
+   __s32 fd;   /* dma-buf fd */
+};
+
+#define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14)
+
+
 /*  API for Type1 VFIO IOMMU  */
 
 /**
-- 
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Re: [Intel-gfx] [PATCH 8/8] drm: Nuke drm_atomic_legacy_backoff

[Maarten Lankhorst]

Op 25-07-17 om 10:01 schreef Daniel Vetter:
> Finally all users are gone!
>
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/drm_atomic.c | 32 
>  include/drm/drm_atomic.h |  2 --
>  2 files changed, 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 306fdca92abf..1b755439f591 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1588,38 +1588,6 @@ drm_atomic_add_affected_planes(struct drm_atomic_state 
> *state,
>  EXPORT_SYMBOL(drm_atomic_add_affected_planes);
>  
>  /**
> - * drm_atomic_legacy_backoff - locking backoff for legacy ioctls
> - * @state: atomic state
> - *
> - * This function should be used by legacy entry points which don't understand
> - * -EDEADLK semantics. For simplicity this one will grab all modeset locks 
> after
> - * the slowpath completed.
> - */
> -void drm_atomic_legacy_backoff(struct drm_atomic_state *state)
> -{
> - struct drm_device *dev = state->dev;
> - int ret;
> - bool global = false;
> -
> - if (WARN_ON(dev->mode_config.acquire_ctx == state->acquire_ctx)) {
> - global = true;
> -
> - dev->mode_config.acquire_ctx = NULL;
> - }
> -
> -retry:
> - drm_modeset_backoff(state->acquire_ctx);
> -
> - ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
> - if (ret)
> - goto retry;
> -
> - if (global)
> - dev->mode_config.acquire_ctx = state->acquire_ctx;
> -}
> -EXPORT_SYMBOL(drm_atomic_legacy_backoff);
You're missing one patch here. We should also mark dev->mode_config.acquire_ctx 
__private. That way atomic commits will never be able to use lock_all. :)

Though I think it requires fixing vmwgfx_fb.c and i915 first.

Otherwise series looks good, so with review comments addressed.

Reviewed-by: Maarten Lankhorst 
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[Intel-gfx] [PATCH v13 4/7] drm/i915/gvt: Add opregion support

[Tina Zhang]

Windows guest UPT driver can use operegion to configure the setting
for display. Without the opregion support, the display registers won't
be set and this blocks display model to get the correct information
of the guest display plane.

Signed-off-by: Bing Niu 
Signed-off-by: Xiaoguang Chen 
Signed-off-by: Tina Zhang 
---
 drivers/gpu/drm/i915/gvt/hypercall.h |   1 +
 drivers/gpu/drm/i915/gvt/kvmgt.c | 109 ++-
 drivers/gpu/drm/i915/gvt/mpt.h   |  15 +
 drivers/gpu/drm/i915/gvt/opregion.c  |  26 +++--
 drivers/gpu/drm/i915/gvt/vgpu.c  |   4 ++
 5 files changed, 146 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h 
b/drivers/gpu/drm/i915/gvt/hypercall.h
index df7f33a..32c345c 100644
--- a/drivers/gpu/drm/i915/gvt/hypercall.h
+++ b/drivers/gpu/drm/i915/gvt/hypercall.h
@@ -55,6 +55,7 @@ struct intel_gvt_mpt {
  unsigned long mfn, unsigned int nr, bool map);
int (*set_trap_area)(unsigned long handle, u64 start, u64 end,
 bool map);
+   int (*set_opregion)(void *vgpu);
 };
 
 extern struct intel_gvt_mpt xengt_mpt;
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index fd0c85f..6b0a330 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,11 +53,23 @@ static const struct intel_gvt_ops *intel_gvt_ops;
 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
 #define VFIO_PCI_OFFSET_MASK(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
 
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
+struct vfio_region;
+struct intel_vgpu_regops {
+   size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
+   size_t count, loff_t *ppos, bool iswrite);
+   void (*release)(struct intel_vgpu *vgpu,
+   struct vfio_region *region);
+};
+
 struct vfio_region {
u32 type;
u32 subtype;
size_t  size;
u32 flags;
+   const struct intel_vgpu_regops  *ops;
+   void*data;
 };
 
 struct kvmgt_pgfn {
@@ -430,6 +442,91 @@ static void kvmgt_protect_table_del(struct 
kvmgt_guest_info *info,
}
 }
 
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+   size_t count, loff_t *ppos, bool iswrite)
+{
+   unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+   VFIO_PCI_NUM_REGIONS;
+   void *base = vgpu->vdev.region[i].data;
+   loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+   if (pos >= vgpu->vdev.region[i].size || iswrite) {
+   gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+   return -EINVAL;
+   }
+   count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+   memcpy(buf, base + pos, count);
+
+   return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+   struct vfio_region *region)
+{
+   memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+   .rw = intel_vgpu_reg_rw_opregion,
+   .release = intel_vgpu_reg_release_opregion,
+};
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+   unsigned int type, unsigned int subtype,
+   const struct intel_vgpu_regops *ops,
+   size_t size, u32 flags, void *data)
+{
+   struct vfio_region *region;
+
+   region = krealloc(vgpu->vdev.region,
+   (vgpu->vdev.num_regions + 1) * sizeof(*region),
+   GFP_KERNEL);
+   if (!region)
+   return -ENOMEM;
+
+   vgpu->vdev.region = region;
+   vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+   vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+   vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+   vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+   vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+   vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+   vgpu->vdev.num_regions++;
+
+   return 0;
+}
+
+static int kvmgt_set_opregion(void *p_vgpu)
+{
+   struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu;
+   unsigned int addr;
+   void *base;
+   int ret;
+
+   addr = vgpu->gvt->opregion.opregion_pa;
+   if (!addr || !(~addr))
+   return -ENODEV;
+
+   base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
+   if (!base)
+   return -ENOMEM;
+
+   if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+   memunmap(base);
+   return -EINVAL;
+   }
+
+   ret = intel_vgpu_register_reg(vgpu,
+   PCI_VENDOR_ID_INTEL | 

[Intel-gfx] [PATCH v13 3/7] drm/i915/gvt: Add RGB 64-bit 16:16:16:16 float format support

[Tina Zhang]

The RGB 64-bit 16:16:16:16 float pixel format is needed by windows 10
guest VM. This patch is to add this pixel format support to gvt device
model. Without this patch, some Apps, e.g. "DXGIGammaVM.exe", will crash
and make guest screen black.

Signed-off-by: Xiaoguang Chen 
Signed-off-by: Tina Zhang 
---
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c 
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 2bd5b3c..739ca81 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -54,6 +54,8 @@ static struct pixel_format 
bdw_pixel_formats[PRIMARY_FORMAT_NUM] = {
"32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
[0xa] = {DRM_FORMAT_XRGB2101010, 32,
"32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+   [0xc] = {DRM_FORMAT_XRGB161616, 64,
+   "64-bit RGBX Floating Point(16:16:16:16 MSB-X:B:G:R)"},
[0xe] = {DRM_FORMAT_XBGR, 32,
"32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
 };
@@ -75,6 +77,10 @@ static struct pixel_format skl_pixel_formats[] = {
{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
 
+   {DRM_FORMAT_XRGB161616, 64,
+   "64-bit XRGB (16:16:16:16 MSB-X:R:G:B)"},
+   {DRM_FORMAT_XBGR161616, 64,
+   "64-bit XBGR (16:16:16:16 MSB-X:B:G:R)"},
 
/* non-supported format has bpp default to 0 */
{0, 0, NULL},
@@ -101,6 +107,9 @@ static int skl_format_to_drm(int format, bool rgb_order, 
bool alpha,
case PLANE_CTL_FORMAT_XRGB_2101010:
skl_pixel_formats_index = rgb_order ? 10 : 11;
break;
+   case PLANE_CTL_FORMAT_XRGB_16161616F:
+   skl_pixel_formats_index = rgb_order ? 12 : 13;
+   break;
case PLANE_CTL_FORMAT_YUV422:
skl_pixel_formats_index = yuv_order >> 16;
if (skl_pixel_formats_index > 3)
@@ -321,6 +330,8 @@ static struct pixel_format 
sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
[0x0]  = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
[0x1]  = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
[0x2]  = {DRM_FORMAT_XRGB, 32, "RGB 32-bit 8:8:8:8"},
+   [0x3]  = {DRM_FORMAT_XRGB161616, 64,
+   "RGB 64-bit 16:16:16:16 Floating Point"},
[0x4] = {DRM_FORMAT_AYUV, 32,
"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
 };
-- 
2.7.4

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[Intel-gfx] [PATCH v13 2/7] drm: Introduce RGB 64-bit 16:16:16:16 float format

[Tina Zhang]

The RGB 64-bit 16:16:16:16 float pixel format is needed by windows
guest VM. This patch is to introduce the format to drm.

v1:
Suggested by Ville to submit this patch to dri-devel.

Signed-off-by: Xiaoguang Chen 
Signed-off-by: Tina Zhang 
---
 include/uapi/drm/drm_fourcc.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7586c46..3e002e3 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -113,6 +113,10 @@ extern "C" {
 
 #define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /* 
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
 
+/* 64 bpp RGB */
+#define DRM_FORMAT_XRGB161616  fourcc_code('X', 'R', '4', '8') /* [63:0] 
x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR161616  fourcc_code('X', 'B', '4', '8') /* [63:0] 
x:B:G:R 16:16:16:16 little endian */
+
 /*
  * 2 plane RGB + A
  * index 0 = RGB plane, same format as the corresponding non _A8 format has
-- 
2.7.4

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[Intel-gfx] [PATCH v13 1/7] drm/i915/gvt: Add framebuffer decoder support

[Tina Zhang]

Framebuffer decoder returns guest framebuffer information.
Guest framebuffer includes primary, cursor and sprite plane.

Signed-off-by: Xiaoguang Chen 
Signed-off-by: Tina Zhang 
---
 drivers/gpu/drm/i915/gvt/Makefile |   3 +-
 drivers/gpu/drm/i915/gvt/display.c|   2 +-
 drivers/gpu/drm/i915/gvt/display.h|   2 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 429 ++
 drivers/gpu/drm/i915/gvt/fb_decoder.h | 175 ++
 drivers/gpu/drm/i915/gvt/gvt.h|   1 +
 6 files changed, 610 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
index f5486cb9..019d596 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -1,7 +1,8 @@
 GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
-   execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+   execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
+   fb_decoder.o
 
 ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR)
 i915-y += $(addprefix $(GVT_DIR)/, 
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/display.c 
b/drivers/gpu/drm/i915/gvt/display.c
index 2deb05f..58d90cf 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
return 1;
 }
 
-static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
 {
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 
diff --git a/drivers/gpu/drm/i915/gvt/display.h 
b/drivers/gpu/drm/i915/gvt/display.h
index d73de22..b46b868 100644
--- a/drivers/gpu/drm/i915/gvt/display.h
+++ b/drivers/gpu/drm/i915/gvt/display.h
@@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 
resolution);
 void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
 void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
 
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
+
 #endif
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c 
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
new file mode 100644
index 000..2bd5b3c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *Kevin Tian 
+ *
+ * Contributors:
+ *Bing Niu 
+ *Xu Han 
+ *Ping Gao 
+ *Xiaoguang Chen 
+ *Yang Liu 
+ *Tina Zhang 
+ *
+ */
+
+#include 
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define PRIMARY_FORMAT_NUM 16
+struct pixel_format {
+   int drm_format; /* Pixel format in DRM definition */
+   int bpp;/* Bits per pixel, 0 indicates invalid */
+   char *desc; /* The description */
+};
+
+/* non-supported format has bpp default to 0 */
+static struct pixel_format bdw_pixel_formats[PRIMARY_FORMAT_NUM] = {
+   [0x2] = {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+   [0x5] = {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+   [0x6] = {DRM_FORMAT_XRGB, 32,
+   "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+   [0x8] = {DRM_FORMAT_XBGR2101010, 32,
+   "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
+   [0xa] = {DRM_FORMAT_XRGB2101010, 32,
+   "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+   

[Intel-gfx] [PATCH v13 0/7] drm/i915/gvt: Dma-buf support for GVT-g

[Tina Zhang]

v12->v13:
1) add comments to GEM proxy. (Chris)
2) don't ban GEM proxy in i915_gem_sw_finish_ioctl. (Chris)
3) check GEM proxy bar after finishing i915_gem_object_wait. (Chris)
4) remove GEM proxy bar in i915_gem_madvise_ioctl.

v11->v12:
1) add drm_format_mod back. (Gerd and Zhenyu)
2) add region_index. (Gerd)
3) refine the lifecycle of dmabuf.
4) send to dri-de...@lists.freedesktop.org. (Ville) 

v10->v11:
1) rename plane_type to drm_plane_type. (Gerd)
2) move fields of vfio_device_query_gfx_plane to
   vfio_device_gfx_plane_info. (Gerd)
3) remove drm_format_mod, start fields. (Daniel)
4) remove plane_id.

v9->v10:
1) remove dma-buf management
2) refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE
3) track the dma-buf create and release in kernel mode

v8->v9:
1) refine the dma-buf ioctl definition
2) add a lock to protect the dmabuf list
3) move drm format change to a separate patch
4) codes cleanup

v7->v8:
1) refine framebuffer decoder code
2) fix a bug in decoding primary plane

v6->v7:
1) release dma-buf related allocations in dma-buf's associated release
   function.
2) refine ioctl interface for querying plane info or create dma-buf
3) refine framebuffer decoder code
4) the patch series is based on 4.12.0-rc1

v5->v6:
1) align the dma-buf life cycle with the vfio device.
2) add the dma-buf releated operations in a separate patch.
3) i915 releated changes.

v4->v5:
1) fix bug while checking whether the gem obj is gvt's dma-buf when user
   change caching mode or domains. Add a helper function to do it.
2) add definition for the query plane and create dma-buf.

v3->v4:
1) fix bug while checking whether the gem obj is gvt's dma-buf when set
   caching mode or doamins.

v2->v3:
1) add a field gvt_plane_info in the drm_i915_gem_obj structure to save
   the decoded plane information to avoid look up while need the plane info.
2) declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
   to represent the gem obj for gvt's dma-buf. The tiling mode, caching mode
   and domains can not be changed for this kind of gem object.
3) change dma-buf related information to be more generic. So other vendor
   can use the same interface.

v1->v2:
1) create a management fd for dma-buf operations.
2) alloc gem object's backing storage in gem obj's get_pages() callback.

This patch set adds the dma-buf support for intel GVT-g.
dma-buf is a uniform mechanism to share DMA buffers across different
devices and sub-systems.
dma-buf for intel GVT-g is mainly used to share the vgpu's framebuffer
to other users or sub-systems so they can use the dma-buf to show the
desktop of a vm which uses intel vgpu.

The main idea is we create a gem object and set vgpu's framebuffer as
the backing storage of this gem object. And associate this gem obj
to a dma-buf object then export this dma-buf at the meantime
generate a file descriptor for this dma-buf. Finally deliver this file
descriptor to user space. And user can use this dma-buf fd to do render
or other operations.


Tina Zhang (7):
  drm/i915/gvt: Add framebuffer decoder support
  drm: Introduce RGB 64-bit 16:16:16:16 float format
  drm/i915/gvt: Add RGB 64-bit 16:16:16:16 float format support
  drm/i915/gvt: Add opregion support
  vfio: ABI for mdev display dma-buf operation
  drm/i915: Introduce GEM proxy
  drm/i915/gvt: Dmabuf support for GVT-g

 drivers/gpu/drm/i915/gvt/Makefile  |   3 +-
 drivers/gpu/drm/i915/gvt/display.c |   2 +-
 drivers/gpu/drm/i915/gvt/display.h |   2 +
 drivers/gpu/drm/i915/gvt/dmabuf.c  | 380 
 drivers/gpu/drm/i915/gvt/dmabuf.h  |  58 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c  | 440 +
 drivers/gpu/drm/i915/gvt/fb_decoder.h  | 175 +
 drivers/gpu/drm/i915/gvt/gvt.c |   1 +
 drivers/gpu/drm/i915/gvt/gvt.h |  10 +
 drivers/gpu/drm/i915/gvt/hypercall.h   |   3 +
 drivers/gpu/drm/i915/gvt/kvmgt.c   | 151 ++-
 drivers/gpu/drm/i915/gvt/mpt.h |  45 
 drivers/gpu/drm/i915/gvt/opregion.c|  26 +-
 drivers/gpu/drm/i915/gvt/vgpu.c|   6 +-
 drivers/gpu/drm/i915/i915_gem.c|  24 +-
 drivers/gpu/drm/i915/i915_gem_object.h |   9 +
 drivers/gpu/drm/i915/i915_gem_tiling.c |   8 +
 include/uapi/drm/drm_fourcc.h  |   4 +
 include/uapi/linux/vfio.h  |  28 +++
 19 files changed, 1362 insertions(+), 13 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

-- 
2.7.4

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Re: [Intel-gfx] [PATCH 7/8] drm: Nuke drm_atomic_helper_connector_dpms

[Archit Taneja]

On 07/25/2017 01:31 PM, Daniel Vetter wrote:

It's dead code, the core handles all this directly now.

The only special case is nouveau and tda988x which used one function
for both legacy modeset code and -nv50 atomic world instead of 2
vtables. But amounts to exactly the same.

v2: Rebase over the panel/brideg refactorings in stm/ltdc.


s/brideg/bridge





---
  drivers/gpu/drm/bridge/adv7511/adv7511_drv.c   |  1 -
  drivers/gpu/drm/bridge/analogix-anx78xx.c  |  1 -
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c |  1 -
  drivers/gpu/drm/bridge/dumb-vga-dac.c  |  1 -
  .../drm/bridge/megachips-stdp-ge-b850v3-fw.c   |  1 -
  drivers/gpu/drm/bridge/nxp-ptn3460.c   |  1 -
  drivers/gpu/drm/bridge/panel.c |  1 -
  drivers/gpu/drm/bridge/parade-ps8622.c |  1 -
  drivers/gpu/drm/bridge/sii902x.c   |  1 -
  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c  |  1 -
  drivers/gpu/drm/bridge/tc358767.c  |  1 -
  drivers/gpu/drm/bridge/ti-tfp410.c |  1 -


For bridge changes:

Acked-by: Archit Taneja 

Archit

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a Linux Foundation Collaborative Project
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