[Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc : Fix flip tests for sprite plane
This test was flipping the primary plane instead of the sprite plane.
Flip the correct plane to make the test pass properly.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102691
Signed-off-by: Maarten Lankhorst
---
Resend for CI.
tests/kms_rotation_crc.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 21e264addc09..69301252bda1 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -332,6 +332,9 @@ static void test_plane_rotation(data_t *data, int
plane_type)
enum igt_commit_style commit = COMMIT_LEGACY;
int ret;
+ if (data->flips && plane_type != DRM_PLANE_TYPE_PRIMARY)
+ igt_require(data->display.is_atomic);
+
if (plane_type == DRM_PLANE_TYPE_PRIMARY || plane_type ==
DRM_PLANE_TYPE_CURSOR)
commit = COMMIT_UNIVERSAL;
@@ -390,12 +393,20 @@ static void test_plane_rotation(data_t *data, int
plane_type)
* check CRC against that one as well.
*/
if (data->flips) {
- ret = drmModePageFlip(data->gfx_fd,
-
output->config.crtc->crtc_id,
- data->fb_flip.fb_id,
- DRM_MODE_PAGE_FLIP_EVENT,
- NULL);
- igt_assert_eq(ret, 0);
+ igt_plane_set_fb(plane, &data->fb_flip);
+ if (data->rotation == IGT_ROTATION_90 ||
data->rotation == IGT_ROTATION_270)
+ igt_plane_set_size(plane,
data->fb.height, data->fb.width);
+
+ if (plane_type != DRM_PLANE_TYPE_PRIMARY) {
+ igt_display_commit_atomic(display,
DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
+ } else {
+ ret = drmModePageFlip(data->gfx_fd,
+
output->config.crtc->crtc_id,
+ data->fb_flip.fb_id,
+
DRM_MODE_PAGE_FLIP_EVENT,
+ NULL);
+ igt_assert_eq(ret, 0);
+ }
wait_for_pageflip(data->gfx_fd);
igt_pipe_crc_collect_crc(data->pipe_crc,
&crc_output);
--
2.14.1
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[Intel-gfx] igt/kms_rotation_crc: Add horizontal flip subtest.
Test that horizontal flip works with supported rotations. Includes
a fix for the unrotated fb which was not being positioned correctly
with portrait and landscape rectangles.
Signed-off-by: Joseph Garvey
---
lib/igt_kms.c| 2 +-
lib/igt_kms.h| 4 +
tests/kms_rotation_crc.c | 197 ++-
3 files changed, 166 insertions(+), 37 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 7bcafc0..ec6ffd2 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -3054,7 +3054,7 @@ void igt_fb_set_size(struct igt_fb *fb, igt_plane_t
*plane,
static const char *rotation_name(igt_rotation_t rotation)
{
- switch (rotation) {
+ switch (rotation & IGT_ROTATION_MASK) {
case IGT_ROTATION_0:
return "0??";
case IGT_ROTATION_90:
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 3d1061f..61393d1 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -281,8 +281,12 @@ typedef enum {
IGT_ROTATION_90 = 1 << 1,
IGT_ROTATION_180 = 1 << 2,
IGT_ROTATION_270 = 1 << 3,
+ IGT_REFLECT_X= 1 << 4,
} igt_rotation_t;
+#define IGT_ROTATION_MASK \
+ (IGT_ROTATION_0 | IGT_ROTATION_90 | IGT_ROTATION_180 | IGT_ROTATION_270)
+
typedef struct {
/*< private >*/
igt_pipe_t *pipe;
diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 21e264a..0e2df96 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -32,6 +32,7 @@ typedef struct {
igt_display_t display;
struct igt_fb fb;
struct igt_fb fb_reference;
+ struct igt_fb fb_unrotated;
struct igt_fb fb_modeset;
struct igt_fb fb_flip;
igt_crc_t ref_crc;
@@ -43,8 +44,62 @@ typedef struct {
uint32_t override_fmt;
uint64_t override_tiling;
bool flips;
+ int devid;
} data_t;
+typedef struct {
+ float r;
+ float g;
+ float b;
+} rgb_color_t;
+
+static void set_color(rgb_color_t *color, float r, float g, float b)
+{
+ color->r = r;
+ color->g = g;
+ color->b = b;
+}
+
+static void rotate_colors(rgb_color_t *tl, rgb_color_t *tr, rgb_color_t *br,
+ rgb_color_t *bl, igt_rotation_t rotation)
+{
+ rgb_color_t bl_tmp, br_tmp, tl_tmp, tr_tmp;
+
+ if (rotation & IGT_REFLECT_X) {
+ bl_tmp = *bl;
+ br_tmp = *br;
+ tl_tmp = *tl;
+ tr_tmp = *tr;
+ *tl = tr_tmp;
+ *bl = br_tmp;
+ *tr = tl_tmp;
+ *br = bl_tmp;
+ }
+
+ if (rotation & IGT_ROTATION_90) {
+ bl_tmp = *bl;
+ br_tmp = *br;
+ tl_tmp = *tl;
+ tr_tmp = *tr;
+ *tl = tr_tmp;
+ *bl = tl_tmp;
+ *tr = br_tmp;
+ *br = bl_tmp;
+ } else if (rotation & IGT_ROTATION_270) {
+ bl_tmp = *bl;
+ br_tmp = *br;
+ tl_tmp = *tl;
+ tr_tmp = *tr;
+ *tl = bl_tmp;
+ *bl = br_tmp;
+ *tr = tl_tmp;
+ *br = tr_tmp;
+ }
+}
+
+#define RGB_COLOR(color) \
+ color.r, color.g, color.b
+
static void
paint_squares(data_t *data, igt_rotation_t rotation,
struct igt_fb *fb, float o)
@@ -52,35 +107,26 @@ paint_squares(data_t *data, igt_rotation_t rotation,
cairo_t *cr;
unsigned int w = fb->width;
unsigned int h = fb->height;
+ rgb_color_t tl, tr, bl, br;
cr = igt_get_cairo_ctx(data->gfx_fd, fb);
- if (rotation == IGT_ROTATION_180) {
+ set_color(&tl, o, 0, 0);
+ set_color(&tr, 0, o, 0);
+ set_color(&br, o, o, o);
+ set_color(&bl, 0, 0, o);
+
+ rotate_colors(&tl, &tr, &br, &bl, rotation);
+
+ if (rotation & IGT_ROTATION_180) {
cairo_translate(cr, w, h);
cairo_rotate(cr, M_PI);
}
- if (rotation == IGT_ROTATION_90) {
- /* Paint 4 squares with width == height in Green, White,
- Blue, Red Clockwise order to look like 270 degree rotated*/
- igt_paint_color(cr, 0, 0, w / 2, h / 2, 0.0, o, 0.0);
- igt_paint_color(cr, w / 2, 0, w / 2, h / 2, o, o, o);
- igt_paint_color(cr, 0, h / 2, w / 2, h / 2, o, 0.0, 0.0);
- igt_paint_color(cr, w / 2, h / 2, w / 2, h / 2, 0.0, 0.0, o);
- } else if (rotation == IGT_ROTATION_270) {
- /* Paint 4 squares with width == height in Blue, Red,
- Green, White Clockwise order to look like 90 degree rotated*/
- igt_paint_color(cr, 0, 0, w / 2, h / 2, 0.0, 0.0, o);
- igt_paint_color(cr, w / 2, 0, w / 2, h / 2, o, 0.0, 0.0);
- igt_paint_color(cr, 0, h / 2, w / 2, h / 2, o, o, o);
- igt_paint_color(cr, w / 2, h / 2, w / 2, h / 2, 0.0, o, 0.0);
- } else
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for GuC Fixes, Minor restructuring changes and v9+ logging change
Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) https://bugs.freedesktop.org/show_bug.cgi?id=102917 -Original Message- From: Patchwork [mailto:patchw...@emeril.freedesktop.org] Sent: Thursday, September 21, 2017 2:25 AM To: Kamble, Sagar A Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.IGT: failure for GuC Fixes, Minor restructuring changes and v9+ logging change == Series Details == Series: GuC Fixes, Minor restructuring changes and v9+ logging change URL : https://patchwork.freedesktop.org/series/30666/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 +1 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2317 pass:1247 dwarn:2 dfail:0 fail:11 skip:1057 time:9646s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5770/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for igt/kms_psr_sink_crc: Fix regression in psr_drrs subtest
== Series Details == Series: igt/kms_psr_sink_crc: Fix regression in psr_drrs subtest URL : https://patchwork.freedesktop.org/series/30683/ State : warning == Summary == IGT patchset tested on top of latest successful build 6e2622564dc85875ee9e2f22874f9607cf0cdd9c meson: share the configuration_data object with latest DRM-Tip kernel build CI_DRM_3117 bed15796ff69 drm-tip: 2017y-09m-20d-20h-05m-31s UTC integration manifest Test gem_ringfill: Subgroup basic-default-hang: pass -> DMESG-WARN (fi-pnv-d510) fdo#101600 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_force_connector_basic: Subgroup prune-stale-modes: pass -> SKIP (fi-snb-2520m) fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:445s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:473s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:421s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:525s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:514s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:504s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:497s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:544s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:568s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:440s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:411s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:444s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:489s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:464s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:477s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:594s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:540s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:457s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:755s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:497s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:568s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:417s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_235/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [igt] igt/kms_psr_sink_crc: Fix regression in psr_drrs subtest
The substring to be matched is modified to reflect kernel code. Fixes: 33355210a43e (igt/kms_psr_sink_crc: Add psr_drrs subtest) Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: Radhakrishna Sripada --- tests/kms_psr_sink_crc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c index 1c25f2c81a34..f023b12c0131 100644 --- a/tests/kms_psr_sink_crc.c +++ b/tests/kms_psr_sink_crc.c @@ -290,7 +290,7 @@ static bool drrs_disabled(data_t *data) igt_debugfs_read(data->drm_fd, "i915_drrs_status", buf); - return strstr(buf, "DRRS Support: No\n"); + return !strstr(buf, "DRRS Supported: Yes\n"); } static void run_test(data_t *data) -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for scripts/run-tests.sh: Look for test-lists.txt in 'build' as well
== Series Details == Series: scripts/run-tests.sh: Look for test-lists.txt in 'build' as well URL : https://patchwork.freedesktop.org/series/30665/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test kms_atomic: Subgroup plane_invalid_params_fence: skip -> PASS (shard-hsw) Test kms_universal_plane: Subgroup disable-primary-vs-flip-pipe-A: skip -> PASS (shard-hsw) Test kms_plane: Subgroup plane-panning-bottom-right-suspend-pipe-C-planes: skip -> PASS (shard-hsw) Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 +1 Test kms_cursor_legacy: Subgroup short-flip-before-cursor-toggle: skip -> PASS (shard-hsw) Test kms_chv_cursor_fail: Subgroup pipe-A-64x64-bottom-edge: skip -> PASS (shard-hsw) Test gem_eio: Subgroup in-flight-contexts: pass -> DMESG-WARN (shard-hsw) fdo#102886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886 shard-hswtotal:2317 pass:1247 dwarn:3 dfail:0 fail:10 skip:1057 time:9629s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_234/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status
On Wed, Sep 20, 2017 at 3:47 PM, Pandiyan, Dhinakaran
wrote:
> On Wed, 2017-09-20 at 13:02 -0700, Ausmus, James wrote:
>> On Wed, Sep 20, 2017 at 12:55 PM, Pandiyan, Dhinakaran
>> wrote:
>> > On Wed, 2017-09-20 at 12:11 -0700, Ausmus, James wrote:
>> >> On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan
>> >> wrote:
>> >> > Rewriting this code without the goto, I believe, makes it more readable.
>> >> > One functional change that has been included is the handling of failed
>> >> > ESI
>> >> > register reads. Instead of disabling MST only for the first failed
>> >> > read, we
>> >> > now disable MST on subsequent failed reads too. A failed ESI read is
>> >> > problematic irrespective of whether it is the first or not.
>> >> >
>> >> > Cc: James Ausmus
>> >> > Cc: Jani Nikula
>> >> > Cc: Ville Syrjälä
>> >> > Signed-off-by: Dhinakaran Pandiyan
>> >> > ---
>> >> > drivers/gpu/drm/i915/intel_dp.c | 75
>> >> > +
>> >> > 1 file changed, 31 insertions(+), 44 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> >> > b/drivers/gpu/drm/i915/intel_dp.c
>> >> > index 98e7b96ca826..cc129aa444ac 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_dp.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_dp.c
>> >> > @@ -4191,57 +4191,44 @@ static void intel_dp_handle_test_request(struct
>> >> > intel_dp *intel_dp)
>> >> > static int
>> >> > intel_dp_check_mst_status(struct intel_dp *intel_dp)
>> >> > {
>> >> > - bool bret;
>> >> > + u8 esi[DP_DPRX_ESI_LEN] = { 0 };
>> >> > + struct intel_digital_port *intel_dig_port =
>> >> > dp_to_dig_port(intel_dp);
>> >> >
>> >> > - if (intel_dp->is_mst) {
>> >> > - u8 esi[DP_DPRX_ESI_LEN] = { 0 };
>> >> > - int ret = 0;
>> >> > - int retry;
>> >> > + if (!intel_dp->is_mst)
>> >> > + return -EINVAL;
>> >> > +
>> >> > + while (intel_dp_get_sink_irq_esi(intel_dp, esi)) {
>> >>
>> >> It looks like if the underlying drm_dp_dpcd_read fails and returns
>> >> -EIO, for instance, you'll get true back from
>> >> intel_dp_get_sink_irq_esi,
>> >
>> > Wait, anything other than 14 from that dpcd read is a false, isn't it?
>>
>> D'oh! You're right - I completely glossed over the whole " ==
>> DP_DPRX_ESI_LEN" bit - sorry for the noise...
>>
>> >
>> >> and you'll still go in to the while, but
>> >> with a potentially invalid esi. Granted, this is a problem in the
>> >> original code as well, but it seems like something that should be
>> >> fixed during the refactoring.
>> >>
>> >>
>> >> > + int ret, retry;
>> >> > bool handled;
>> >> > - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
>> >> > -go_again:
>> >> > - if (bret == true) {
>> >> > -
>> >> > - /* check link status - esi[10] = 0x200c */
>> >> > - if (intel_dp->active_mst_links &&
>> >> > - !drm_dp_channel_eq_ok(&esi[10],
>> >> > intel_dp->lane_count)) {
>> >> > - DRM_DEBUG_KMS("channel EQ not ok,
>> >> > retraining\n");
>> >> > - intel_dp_start_link_train(intel_dp);
>> >> > - intel_dp_stop_link_train(intel_dp);
>> >> > - }
>> >> >
>> >> > - DRM_DEBUG_KMS("got esi %3ph\n", esi);
>> >> > - ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr,
>> >> > esi, &handled);
>> >> > -
>> >> > - if (handled) {
>> >> > - for (retry = 0; retry < 3; retry++) {
>> >> > - int wret;
>> >> > - wret =
>> >> > drm_dp_dpcd_write(&intel_dp->aux,
>> >> > -
>> >> > DP_SINK_COUNT_ESI+1,
>> >> > -
>> >> > &esi[1], 3);
>> >> > - if (wret == 3) {
>> >> > - break;
>> >> > - }
>> >> > - }
>> >> > + DRM_DEBUG_KMS("ESI %3ph\n", esi);
>> >> >
>> >> > - bret =
>> >> > intel_dp_get_sink_irq_esi(intel_dp, esi);
>> >> > - if (bret == true) {
>> >> > - DRM_DEBUG_KMS("got esi2
>> >> > %3ph\n", esi);
>> >> > - goto go_again;
>> >> > - }
>> >> > - } else
>> >> > - ret = 0;
>> >> > + /* check link status - esi[10] = 0x200c */
>> >> > + if (intel_dp->active_mst_links &&
>> >> > + !drm_dp_channel_eq_ok(&esi[10],
>> >> > intel_dp->lane_count)) {
>> >> > + in
Re: [Intel-gfx] [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly
On 2017.09.19 19:35:23 -0700, Joe Perches wrote:
> On Wed, 2017-09-20 at 05:46 +0800, Zhenyu Wang wrote:
> > On 2017.09.19 16:55:34 +0100, Colin King wrote:
> > > From: Colin Ian King
> > >
> > > An earlier fix changed the return type from find_bb_size however the
> > > integer return is being assigned to a unsigned int so the -ve error
> > > check will never be detected. Make bb_size an int to fix this.
> > >
> > > Detected by CoverityScan CID#1456886 ("Unsigned compared against 0")
> > >
> > > Fixes: 1e3197d6ad73 ("drm/i915/gvt: Refine error handling for
> > > perform_bb_shadow")
> > > Signed-off-by: Colin Ian King
> > > ---
> > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> > > b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> > > index 2c0ccbb817dc..f41cbf664b69 100644
> > > --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> > > +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> > > @@ -1628,7 +1628,7 @@ static int perform_bb_shadow(struct
> > > parser_exec_state *s)
> > > struct intel_shadow_bb_entry *entry_obj;
> > > struct intel_vgpu *vgpu = s->vgpu;
> > > unsigned long gma = 0;
> > > - uint32_t bb_size;
> > > + int bb_size;
> > > void *dst = NULL;
> > > int ret = 0;
> > >
> >
> > Applied this, thanks!
>
> Is it possible for bb_size to be both >= 2g and valid?
Never be possible in practise and if really that big I think something
is already insane indeed.
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status
On Wed, 2017-09-20 at 13:02 -0700, Ausmus, James wrote:
> On Wed, Sep 20, 2017 at 12:55 PM, Pandiyan, Dhinakaran
> wrote:
> > On Wed, 2017-09-20 at 12:11 -0700, Ausmus, James wrote:
> >> On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan
> >> wrote:
> >> > Rewriting this code without the goto, I believe, makes it more readable.
> >> > One functional change that has been included is the handling of failed
> >> > ESI
> >> > register reads. Instead of disabling MST only for the first failed read,
> >> > we
> >> > now disable MST on subsequent failed reads too. A failed ESI read is
> >> > problematic irrespective of whether it is the first or not.
> >> >
> >> > Cc: James Ausmus
> >> > Cc: Jani Nikula
> >> > Cc: Ville Syrjälä
> >> > Signed-off-by: Dhinakaran Pandiyan
> >> > ---
> >> > drivers/gpu/drm/i915/intel_dp.c | 75
> >> > +
> >> > 1 file changed, 31 insertions(+), 44 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> >> > b/drivers/gpu/drm/i915/intel_dp.c
> >> > index 98e7b96ca826..cc129aa444ac 100644
> >> > --- a/drivers/gpu/drm/i915/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> > @@ -4191,57 +4191,44 @@ static void intel_dp_handle_test_request(struct
> >> > intel_dp *intel_dp)
> >> > static int
> >> > intel_dp_check_mst_status(struct intel_dp *intel_dp)
> >> > {
> >> > - bool bret;
> >> > + u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> >> > + struct intel_digital_port *intel_dig_port =
> >> > dp_to_dig_port(intel_dp);
> >> >
> >> > - if (intel_dp->is_mst) {
> >> > - u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> >> > - int ret = 0;
> >> > - int retry;
> >> > + if (!intel_dp->is_mst)
> >> > + return -EINVAL;
> >> > +
> >> > + while (intel_dp_get_sink_irq_esi(intel_dp, esi)) {
> >>
> >> It looks like if the underlying drm_dp_dpcd_read fails and returns
> >> -EIO, for instance, you'll get true back from
> >> intel_dp_get_sink_irq_esi,
> >
> > Wait, anything other than 14 from that dpcd read is a false, isn't it?
>
> D'oh! You're right - I completely glossed over the whole " ==
> DP_DPRX_ESI_LEN" bit - sorry for the noise...
>
> >
> >> and you'll still go in to the while, but
> >> with a potentially invalid esi. Granted, this is a problem in the
> >> original code as well, but it seems like something that should be
> >> fixed during the refactoring.
> >>
> >>
> >> > + int ret, retry;
> >> > bool handled;
> >> > - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> >> > -go_again:
> >> > - if (bret == true) {
> >> > -
> >> > - /* check link status - esi[10] = 0x200c */
> >> > - if (intel_dp->active_mst_links &&
> >> > - !drm_dp_channel_eq_ok(&esi[10],
> >> > intel_dp->lane_count)) {
> >> > - DRM_DEBUG_KMS("channel EQ not ok,
> >> > retraining\n");
> >> > - intel_dp_start_link_train(intel_dp);
> >> > - intel_dp_stop_link_train(intel_dp);
> >> > - }
> >> >
> >> > - DRM_DEBUG_KMS("got esi %3ph\n", esi);
> >> > - ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr,
> >> > esi, &handled);
> >> > -
> >> > - if (handled) {
> >> > - for (retry = 0; retry < 3; retry++) {
> >> > - int wret;
> >> > - wret =
> >> > drm_dp_dpcd_write(&intel_dp->aux,
> >> > -
> >> > DP_SINK_COUNT_ESI+1,
> >> > -
> >> > &esi[1], 3);
> >> > - if (wret == 3) {
> >> > - break;
> >> > - }
> >> > - }
> >> > + DRM_DEBUG_KMS("ESI %3ph\n", esi);
> >> >
> >> > - bret =
> >> > intel_dp_get_sink_irq_esi(intel_dp, esi);
> >> > - if (bret == true) {
> >> > - DRM_DEBUG_KMS("got esi2 %3ph\n",
> >> > esi);
> >> > - goto go_again;
> >> > - }
> >> > - } else
> >> > - ret = 0;
> >> > + /* check link status - esi[10] = 0x200c */
> >> > + if (intel_dp->active_mst_links &&
> >> > + !drm_dp_channel_eq_ok(&esi[10],
> >> > intel_dp->lane_count)) {
> >> > + intel_dp_start_link_train(intel_dp);
> >> > + intel_dp_stop_link_train(intel_dp);
> >> > + }
> >> >
> >> > - return r
Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink
On Wed, Sep 20, 2017 at 02:32:34PM +, vathsala nagaraju wrote: > Add defines for dpcd register 2009 (synchronization latency > in sink). > > Cc: Rodrigo Vivi > CC: Puthikorn Voravootivat > Signed-off-by: Vathsala Nagaraju > --- > include/drm/drm_dp_helper.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 11c39f1..846004e6 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -735,6 +735,9 @@ > # define DP_PSR_SINK_INTERNAL_ERROR 7 > # define DP_PSR_SINK_STATE_MASK 0x07 > > +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 > +# define DP_MAX_RESYNC_FRAME_CNT_MASK0xf where did you get that? eDP 1.4 teels 2009h is a debug register. > + > #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ > # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) > > -- > 1.9.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 6/9] drm/i915/guc: Fix GuC cleanup in unload path
On Wed, 20 Sep 2017 19:38:21 +0200, Sagar Arun Kamble
wrote:
We ensure that GuC is completely suspended and client is destroyed
in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw
should just take care of cleanup,
hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly
we also updated as s/i915_guc_submission_fini/i915_guc_submission_cleanup
Other functionality to disable communication, disable interrupts and
update of ggtt.invalidate is taken care by intel_uc_suspend.
With this patch we are also doing guc_free_load_err_log only
if i915.enable_guc_loading is set.
Created intel_guc_cleanup function to wrap the cleanup functions
specific to GuC.
This last step seems to be one too far. Try again without it.
Michal
v2: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 21 +++--
drivers/gpu/drm/i915/intel_uc.h| 4 ++--
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 8635f40..6f36ced 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -602,7 +602,7 @@ static void i915_gem_fini(struct drm_i915_private
*dev_priv)
i915_gem_drain_workqueue(dev_priv);
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_uc_fini_hw(dev_priv);
+ intel_uc_cleanup(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 94efe32..12f1195 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1050,7 +1050,7 @@ int i915_guc_submission_init(struct
drm_i915_private *dev_priv)
return ret;
}
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index aac8526..8c42344 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -418,7 +418,7 @@ int intel_uc_init_hw(struct drm_i915_private
*dev_priv)
guc_capture_load_err_log(guc);
err_submission:
if (i915.enable_guc_submission)
- i915_guc_submission_fini(dev_priv);
+ i915_guc_submission_cleanup(dev_priv);
err_guc:
i915_ggtt_disable_guc(dev_priv);
@@ -439,21 +439,22 @@ int intel_uc_init_hw(struct drm_i915_private
*dev_priv)
return ret;
}
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
+static void intel_guc_cleanup(struct intel_guc *guc)
{
- guc_free_load_err_log(&dev_priv->guc);
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ if (i915.enable_guc_submission)
+ i915_guc_submission_cleanup(dev_priv);
+}
+void intel_uc_cleanup(struct drm_i915_private *dev_priv)
+{
if (!i915.enable_guc_loading)
return;
- guc_disable_communication(&dev_priv->guc);
-
- if (i915.enable_guc_submission) {
- gen9_disable_guc_interrupts(dev_priv);
- i915_guc_submission_fini(dev_priv);
- }
+ guc_free_load_err_log(&dev_priv->guc);
- i915_ggtt_disable_guc(dev_priv);
+ intel_guc_cleanup(&dev_priv->guc);
}
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
diff --git a/drivers/gpu/drm/i915/intel_uc.h
b/drivers/gpu/drm/i915/intel_uc.h
index 069c2b2..8557e33 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -207,7 +207,7 @@ struct intel_huc {
void intel_uc_init_fw(struct drm_i915_private *dev_priv);
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_uc_cleanup(struct drm_i915_private *dev_priv);
int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv);
int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
@@ -236,7 +236,7 @@ static inline void intel_guc_notify(struct intel_guc
*guc)
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32
size);
/* intel_guc_log.c */
Re: [Intel-gfx] [PATCH v4 5/9] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset
On Wed, 20 Sep 2017 19:38:20 +0200, Sagar Arun Kamble
wrote:
Before i915 reset we need to disable GuC submission and suspend GuC
operarions as it is recreated during intel_uc_init_hw. We can't reuse the
^^
intel_uc_suspend functionality as reset path already holds struct_mutex.
v2: Rebase w.r.t removal of GuC code restructuring. Updated reset_prepare
function as struct_mutex is not needed.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
drivers/gpu/drm/i915/intel_uc.c | 14 ++
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index dd56d45..76e1bb2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2847,6 +2847,8 @@ int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv)
i915_gem_revoke_fences(dev_priv);
+ intel_uc_reset_prepare(dev_priv);
+
return err;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 0c7e45c7..aac8526 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -671,3 +671,17 @@ int intel_uc_resume(struct drm_i915_private
*dev_priv)
{
return 0;
}
+
+int intel_uc_reset_prepare(struct drm_i915_private *dev_priv)
+{
+ int ret;
+
+ if (i915.enable_guc_submission)
+ i915_guc_submission_disable(dev_priv);
+
+ ret = intel_uc_runtime_suspend(dev_priv);
+ if (ret)
+ return ret;
+
+ return 0;
Make it trivial:
return intel_uc_runtime_suspend(dev_priv);
With above fixed, you can add my r-b
Michal
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h
b/drivers/gpu/drm/i915/intel_uc.h
index 5f49d13..069c2b2 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -212,6 +212,7 @@ struct intel_huc {
int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
int intel_uc_resume(struct drm_i915_private *dev_priv);
+int intel_uc_reset_prepare(struct drm_i915_private *dev_priv);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32
len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32
len);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs URL : https://patchwork.freedesktop.org/series/30669/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) Test kms_busy: Subgroup extended-modeset-hang-oldfb-with-reset-render-B: pass -> SKIP (shard-hsw) fdo#102249 Test kms_universal_plane: Subgroup universal-plane-pipe-A-sanity: pass -> SKIP (shard-hsw) fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249 shard-hswtotal:2317 pass:1245 dwarn:2 dfail:0 fail:11 skip:1059 time:9578s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5771/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5
On Wed, Sep 20, 2017 at 2:34 PM, Rodrigo Vivi wrote: > On Wed, Sep 20, 2017 at 08:31:26PM +, Anuj Phogat wrote: >> See Mesa commit 9c588ff >> >> Cc: Matt Turner >> Cc: Rodrigo Vivi >> Signed-off-by: Anuj Phogat > > Reviewed-by: Rodrigo Vivi > Thanks Rodrigo. Can you push it for me? >> --- >> include/drm/i915_pciids.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h >> index 1257e15c1a03..972a25633525 100644 >> --- a/include/drm/i915_pciids.h >> +++ b/include/drm/i915_pciids.h >> @@ -339,7 +339,6 @@ >> #define INTEL_KBL_GT1_IDS(info) \ >> INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ >> INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ >> - INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \ >> INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ >> INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ >> INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ >> @@ -349,6 +348,7 @@ >> >> #define INTEL_KBL_GT2_IDS(info) \ >> INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ >> + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ >> INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ >> INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ >> INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ >> -- >> 2.13.5 >> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH libdrm V2 2/2] intel: Change a KBL pci id to GT2 from GT1.5
On Wed, Sep 20, 2017 at 07:11:03PM +, Anuj Phogat wrote: > See Mesa commit 9c588ff > > Cc: Matt Turner > Cc: Rodrigo Vivi > Signed-off-by: Anuj Phogat Reviewed-by: Rodrigo Vivi > --- > intel/intel_chipset.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h > index 3ff59ada..d81b1646 100644 > --- a/intel/intel_chipset.h > +++ b/intel/intel_chipset.h > @@ -202,7 +202,7 @@ > #define PCI_CHIP_KABYLAKE_ULX_GT10x590E > #define PCI_CHIP_KABYLAKE_ULX_GT20x591E > #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 > -#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 > +#define PCI_CHIP_KABYLAKE_M_GT2 0x5917 > #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 > #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B > #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B > @@ -434,7 +434,6 @@ > > #define IS_KBL_GT1(devid)((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ >(devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ > - (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ >(devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ >(devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ >(devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ > @@ -446,6 +445,7 @@ >(devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ >(devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ >(devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ > + (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ >(devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ >(devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ >(devid) == PCI_CHIP_KABYLAKE_WKS_GT2) > -- > 2.13.5 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5
On Wed, Sep 20, 2017 at 08:31:26PM +, Anuj Phogat wrote: > See Mesa commit 9c588ff > > Cc: Matt Turner > Cc: Rodrigo Vivi > Signed-off-by: Anuj Phogat Reviewed-by: Rodrigo Vivi > --- > include/drm/i915_pciids.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index 1257e15c1a03..972a25633525 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -339,7 +339,6 @@ > #define INTEL_KBL_GT1_IDS(info) \ > INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ > INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ > - INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \ > INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ > INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ > INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ > @@ -349,6 +348,7 @@ > > #define INTEL_KBL_GT2_IDS(info) \ > INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ > + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ > INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ > INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ > INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ > -- > 2.13.5 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 3/9] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume
On Wed, 20 Sep 2017 19:38:18 +0200, Sagar Arun Kamble
wrote:
Apart from configuring interrupts, we need to update the ggtt invalidate
interface and GuC communication on suspend. This functionality can be
reused for other suspend and reset paths.
Prepared GuC specific helpers to handle these suspend/resume tasks
namely - intel_guc_runtime_suspend, intel_guc_runtime_resume.
v2: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 66
-
1 file changed, 59 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 0dbb4b9..fa698db 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -551,8 +551,6 @@ static int intel_guc_enter_sleep(struct intel_guc
*guc)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_disable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
@@ -577,9 +575,6 @@ static int intel_guc_exit_sleep(struct intel_guc
*guc)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
@@ -590,14 +585,71 @@ static int intel_guc_exit_sleep(struct intel_guc
*guc)
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}
+int intel_guc_runtime_suspend(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int ret;
+
+ ret = intel_guc_enter_sleep(guc);
+ if (ret) {
+ DRM_ERROR("GuC enter sleep failed (%d)\n", ret);
+ return ret;
+ }
+
+ i915_ggtt_disable_guc(dev_priv);
+ gen9_disable_guc_interrupts(dev_priv);
To match existing approach in intel_uc_init_hw() move interrupts
control to uc_runtime_suspend()
+
+ return 0;
+}
+
+int intel_guc_runtime_resume(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int ret;
+
+ if (i915.guc_log_level >= 0)
+ gen9_enable_guc_interrupts(dev_priv);
Similar here
+ i915_ggtt_enable_guc(dev_priv);
+
+ ret = intel_guc_exit_sleep(guc);
+ if (ret) {
+ DRM_ERROR("GuC exit sleep failed (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv)
{
- return intel_guc_enter_sleep(&dev_priv->guc);
+ int ret;
+
+ if (!i915.enable_guc_loading)
+ return 0;
+
+ ret = intel_guc_runtime_suspend(&dev_priv->guc);
+ if (ret)
+ return ret;
+
+ guc_disable_communication(&dev_priv->guc);
+
+ return 0;
}
int intel_uc_runtime_resume(struct drm_i915_private *dev_priv)
{
- return intel_guc_exit_sleep(&dev_priv->guc);
+ int ret;
+
+ if (!i915.enable_guc_loading)
+ return 0;
+
+ ret = guc_enable_communication(&dev_priv->guc);
+ if (ret) {
+ DRM_ERROR("GuC enable communication failed (%d)\n", ret);
+ return ret;
+ }
+
+ return intel_guc_runtime_resume(&dev_priv->guc);
}
int intel_uc_suspend(struct drm_i915_private *dev_priv)
___
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Re: [Intel-gfx] [PATCH v4 2/9] drm/i915/guc: Update prototype/name of GuC suspend/resume fns and move to intel_uc.c
On Wed, 20 Sep 2017 19:38:17 +0200, Sagar Arun Kamble
wrote:
Renamed intel_guc_suspend to intel_guc_enter_sleep and intel_guc_resume
to intel_guc_exit_sleep to match GuC nomenclature compatibility.
We plan to use intel_guc_suspend and intel_guc_resume through
intel_uc_suspend and intel_uc_resume in the path i915_drm_suspend and
i915_drm_resume respectively for better naming.
Also, with this patch we pass intel_guc struct as parameter to
enter_sleep
and exit_sleep functions as they are GuC specific and they are moved to
intel_uc.c as static functions called from uc generic functions.
I'm not sure that we need this semi-refactoring right now.
We can return to this later and do it right at once.
Michal
v2: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 52
---
drivers/gpu/drm/i915/intel_uc.c| 58
--
drivers/gpu/drm/i915/intel_uc.h| 2 --
3 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e191d56..94efe32 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1205,55 +1205,3 @@ void i915_guc_submission_disable(struct
drm_i915_private *dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
}
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- gen9_disable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
- /* any value greater than GUC_POWER_D0 */
- data[1] = GUC_POWER_D1;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
-
-/**
- * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- data[1] = GUC_POWER_D0;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 8e4d8b0..0dbb4b9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -538,19 +538,71 @@ int intel_guc_sample_forcewake(struct intel_guc
*guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
+/**
+ * intel_guc_enter_sleep() - notify GuC entering sleep state
+ * @guc: guc structure
+ */
+static int intel_guc_enter_sleep(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct i915_gem_context *ctx;
+ u32 data[3];
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ gen9_disable_guc_interrupts(dev_priv);
+
+ ctx = dev_priv->kernel_context;
+
+ data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
+ /* any value greater than GUC_POWER_D0 */
+ data[1] = GUC_POWER_D1;
+ /* first page is shared data with GuC */
+ data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
+
+ return intel_guc_send(guc, data, ARRAY_SIZE(data));
+}
+
+/**
+ * intel_guc_exit_sleep() - notify GuC exit from sleep state
+ * @guc: guc structure
+ */
+static int intel_guc_exit_sleep(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct i915_gem_context *ctx;
+ u32 data[3];
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ if (i915.guc_log_level >= 0)
+ gen9_enable_guc_interrupts(dev_priv);
+
+ ctx = dev_priv->kernel_context;
+
+ data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
+ data[1] = GUC_POWER_D0;
+ /* first page is shared data with GuC */
+ data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
+
+ return intel_guc_send(g
Re: [Intel-gfx] [PATCH v4 7/9] drm/i915/guc: Remove i915_guc_log_unregister
On Wed, 20 Sep 2017 19:38:22 +0200, Sagar Arun Kamble
wrote:
Functionality needed to disable GuC interrupts and cleanup the
runtime/relay data structures is already covered in the unload path
via intel_guc_fini_hw and intel_guc_cleanup hence remove
i915_guc_log_unregister
v2: Removed the function i915_guc_log_unregister.
v3: Rebase as intel_guc.h is removed.
v4: Rebase as intel_guc.h is created again. :)
v5: Rebase as intel_guc.h is removed.
Cc: Michal Wajdeczko
Reviewed-by: Michal Wajdeczko
I'm afraid I've to revoke my r-b as with removal of the log_unregister()
we will loose symmetry with log_register() where relay_late_setup_files()
was hidden, and we should still clean it up in i915_driver_unregister()
Michal
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm/i915/intel_guc_log.c | 12
drivers/gpu/drm/i915/intel_uc.h | 1 -
3 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 6f36ced..c69a30a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1252,7 +1252,6 @@ static void i915_driver_unregister(struct
drm_i915_private *dev_priv)
i915_perf_unregister(dev_priv);
i915_teardown_sysfs(dev_priv);
- i915_guc_log_unregister(dev_priv);
drm_dev_unregister(&dev_priv->drm);
i915_gem_shrinker_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..3c45681 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -648,15 +648,3 @@ void i915_guc_log_register(struct drm_i915_private
*dev_priv)
guc_log_late_setup(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
-
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
-{
- if (!i915.enable_guc_submission)
- return;
-
- mutex_lock(&dev_priv->drm.struct_mutex);
- /* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_disable_guc_interrupts(dev_priv);
- guc_log_runtime_destroy(&dev_priv->guc);
- mutex_unlock(&dev_priv->drm.struct_mutex);
-}
diff --git a/drivers/gpu/drm/i915/intel_uc.h
b/drivers/gpu/drm/i915/intel_uc.h
index 8557e33..c2c104a 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -244,7 +244,6 @@ static inline void intel_guc_notify(struct intel_guc
*guc)
void intel_guc_log_destroy(struct intel_guc *guc);
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64
control_val);
void i915_guc_log_register(struct drm_i915_private *dev_priv);
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
static inline u32 guc_ggtt_offset(struct i915_vma *vma)
{
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for GuC Fixes, Minor restructuring changes and v9+ logging change
== Series Details == Series: GuC Fixes, Minor restructuring changes and v9+ logging change URL : https://patchwork.freedesktop.org/series/30666/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 +1 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2317 pass:1247 dwarn:2 dfail:0 fail:11 skip:1057 time:9646s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5770/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/kbl: Remove unused Kabylake pci ids (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915/kbl: Remove unused Kabylake pci ids
(rev2)
URL : https://patchwork.freedesktop.org/series/30151/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALLscripts/checksyscalls.sh
CHK scripts/mod/devicetable-offsets.h
CHK include/generated/compile.h
CC arch/x86/kernel/early-quirks.o
In file included from ./include/drm/i915_drm.h:29:0,
from arch/x86/kernel/early-quirks.c:19:
./include/drm/i915_pciids.h:38:36: error: expected identifier or ‘(’ before ‘{’
token
#define INTEL_VGA_DEVICE(id, info) { \
^
./include/drm/i915_pciids.h:341:2: note: in expansion of macro
‘INTEL_VGA_DEVICE’
INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
^~~~
./include/drm/i915_pciids.h:341:32: error: expected identifier or ‘(’ before
‘,’ token
INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
^
./include/drm/i915_pciids.h:343:32: error: expected identifier or ‘(’ before
‘,’ token
INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
^
./include/drm/i915_pciids.h:344:32: error: expected identifier or ‘(’ before
‘,’ token
INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
^
./include/drm/i915_pciids.h:346:32: error: expected identifier or ‘(’ before
‘,’ token
INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
^
./include/drm/i915_pciids.h:347:32: error: expected identifier or ‘(’ before
‘,’ token
INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
^
./include/drm/i915_pciids.h:340:1: error: expected expression before ‘<<’ token
<<< HEAD
^
./include/drm/i915_pciids.h:364:2: note: in expansion of macro
‘INTEL_KBL_GT1_IDS’
INTEL_KBL_GT1_IDS(info), \
^
arch/x86/kernel/early-quirks.c:528:2: note: in expansion of macro
‘INTEL_KBL_IDS’
INTEL_KBL_IDS(&gen9_early_ops),
^
scripts/Makefile.build:311: recipe for target 'arch/x86/kernel/early-quirks.o'
failed
make[2]: *** [arch/x86/kernel/early-quirks.o] Error 1
scripts/Makefile.build:570: recipe for target 'arch/x86/kernel' failed
make[1]: *** [arch/x86/kernel] Error 2
Makefile:1019: recipe for target 'arch/x86' failed
make: *** [arch/x86] Error 2
___
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[Intel-gfx] [PATCH v2 2/2] drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5
See Mesa commit 9c588ff Cc: Matt Turner Cc: Rodrigo Vivi Signed-off-by: Anuj Phogat --- include/drm/i915_pciids.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 1257e15c1a03..972a25633525 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -339,7 +339,6 @@ #define INTEL_KBL_GT1_IDS(info)\ INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ - INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ @@ -349,6 +348,7 @@ #define INTEL_KBL_GT2_IDS(info)\ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH libdrm 2/2] intel: Change a KBL pci id to GT2 from GT1.5
On Wed, Sep 20, 2017 at 12:13 PM, Anuj Phogat wrote: > Any comments on this one. Sent out v2 after dropping > [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids Correction. Dropped patch for libdrm is: [PATCH libdrm 1/2] intel: Remove unused Kabylake pci ids > > On Mon, Sep 11, 2017 at 9:22 AM, Anuj Phogat wrote: >> See Mesa commit 9c588ff >> >> Cc: Matt Turner >> Cc: Rodrigo Vivi >> Signed-off-by: Anuj Phogat >> --- >> intel/intel_chipset.h | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h >> index 77a9ca6..6bd8ae2 100644 >> --- a/intel/intel_chipset.h >> +++ b/intel/intel_chipset.h >> @@ -198,7 +198,7 @@ >> #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 >> #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E >> #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 >> -#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 >> +#define PCI_CHIP_KABYLAKE_M_GT20x5917 >> #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 >> #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B >> #define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B >> @@ -424,8 +424,7 @@ >> (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ >> (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) >> >> -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ >> -(devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ >> +#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ >> (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ >> (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1) >> >> @@ -433,6 +432,7 @@ >> (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ >> (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ >> (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ >> +(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ >> (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ >> (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) >> >> -- >> 2.9.4 >> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH libdrm 1/2] intel: Remove unused Kabylake pci ids
Dropping this patch. On Mon, Sep 11, 2017 at 9:22 AM, Anuj Phogat wrote: > These PCI IDs are not used in any Kabylake SKUs. > See Mesa commits: ebc5ccf and b2dae9f > > Cc: Matt Turner > Cc: Rodrigo Vivi > Signed-off-by: Anuj Phogat > --- > intel/intel_chipset.h | 26 -- > 1 file changed, 4 insertions(+), 22 deletions(-) > > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h > index 3ff59ad..77a9ca6 100644 > --- a/intel/intel_chipset.h > +++ b/intel/intel_chipset.h > @@ -192,24 +192,16 @@ > #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D > > #define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 > -#define PCI_CHIP_KABYLAKE_ULT_GT1_50x5913 > #define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 > -#define PCI_CHIP_KABYLAKE_ULT_GT3_00x5923 > #define PCI_CHIP_KABYLAKE_ULT_GT3_10x5926 > #define PCI_CHIP_KABYLAKE_ULT_GT3_20x5927 > #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 > -#define PCI_CHIP_KABYLAKE_ULX_GT1_50x5915 > -#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E > #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E > #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 > #define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 > #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 > #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B > -#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B > -#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908 > #define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B > -#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A > -#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A > #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D > > #define PCI_CHIP_BROXTON_0 0x0A84 > @@ -432,34 +424,24 @@ > (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ > (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) > > -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ > -(devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ > -(devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ > +#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ > (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ > -(devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ > (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ > -(devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \ > -(devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \ > -(devid) == PCI_CHIP_KABYLAKE_SRV_GT1) > +(devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1) > > #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ > (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ > (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ > (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ > (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ > -(devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ > (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) > > -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ > -(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ > +#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ > (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) > > -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) > - > #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ > IS_KBL_GT2(devid) || \ > -IS_KBL_GT3(devid) || \ > -IS_KBL_GT4(devid)) > +IS_KBL_GT3(devid)) > > #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ > IS_SKL_GT2(devid) || \ > -- > 2.9.4 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 04/10] drm/i915: Expose a PMU interface for perf queries
Hi Peter, could you, please, comment on below? -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Rogozhkin, Dmitry V Sent: Wednesday, September 13, 2017 4:06 PM To: pet...@infradead.org Cc: Intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [RFC 04/10] drm/i915: Expose a PMU interface for perf queries On Tue, 2017-08-29 at 21:21 +0200, Peter Zijlstra wrote: > On Tue, Aug 29, 2017 at 07:16:31PM +, Rogozhkin, Dmitry V wrote: > > > Pretty strict, people tend to get fairly upset every time we leak stuff. > > > In fact Debian and Android carry a perf_event_paranoid patch that > > > default disables _everything_ :-( > > > > Can you say more on that for Debian and Android? What exactly they do? > > What is the value of perf_event_paranoid there? They disable > > everything even for root and CAP_SYS_ADMIN? But still they don't > > remove this from kernel on compilation stage, right? So users can > > explicitly change perf_event_paranoid to the desired value? > > They introduce (and default to) perf_event_paranoid = 3. Which > disallows everything for unpriv user, root can still do things IIRC, > I'd have to dig out the patch. > > This way apps have no access to the syscall, but you can enable it > using ADB by lowering the setting. So developers still have access, > but regular apps do not. > Hi, Peter. How you would feel about the following idea (or close to it): 1. We introduce one more level for perf_event_paranoid=4 (or =3, I am not sure whether Debian/Android =3 is considered uAPI) which would mean: "disallow kernel profiling for unpriv, but let individual kernel modules to have their own settings". 2. We will have i915 PMU custom setting "/sys/module/i915/parameters/perf_event_paranoid" which will be in effect only if global perf_event_paranoid=4 (or =3) and prevail over a global setting Would anything like that be acceptable upstream? This would permit customers to configure i915 PMU support for unpriv users separately from the rest of PMU subsystem. Regards, Dmitry. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for scripts/run-tests.sh: Look for test-lists.txt in 'build' as well
== Series Details == Series: scripts/run-tests.sh: Look for test-lists.txt in 'build' as well URL : https://patchwork.freedesktop.org/series/30665/ State : success == Summary == IGT patchset tested on top of latest successful build 6e2622564dc85875ee9e2f22874f9607cf0cdd9c meson: share the configuration_data object with latest DRM-Tip kernel build CI_DRM_3116 1f49c0573152 drm-tip: 2017y-09m-20d-19h-18m-41s UTC integration manifest Test chamelium: Subgroup dp-crc-fast: dmesg-warn -> PASS (fi-kbl-7500u) fdo#102514 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 Test pm_rpm: Subgroup basic-rte: pass -> DMESG-WARN (fi-cfl-s) fdo#102294 Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (fi-glk-1) fdo#102777 +1 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:450s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:423s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:519s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:511s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:502s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:500s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:543s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:422s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:565s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:431s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:408s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:436s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:494s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:478s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:574s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:550s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:496s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:571s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:422s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_234/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status
On Wed, Sep 20, 2017 at 12:55 PM, Pandiyan, Dhinakaran
wrote:
> On Wed, 2017-09-20 at 12:11 -0700, Ausmus, James wrote:
>> On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan
>> wrote:
>> > Rewriting this code without the goto, I believe, makes it more readable.
>> > One functional change that has been included is the handling of failed ESI
>> > register reads. Instead of disabling MST only for the first failed read, we
>> > now disable MST on subsequent failed reads too. A failed ESI read is
>> > problematic irrespective of whether it is the first or not.
>> >
>> > Cc: James Ausmus
>> > Cc: Jani Nikula
>> > Cc: Ville Syrjälä
>> > Signed-off-by: Dhinakaran Pandiyan
>> > ---
>> > drivers/gpu/drm/i915/intel_dp.c | 75
>> > +
>> > 1 file changed, 31 insertions(+), 44 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> > b/drivers/gpu/drm/i915/intel_dp.c
>> > index 98e7b96ca826..cc129aa444ac 100644
>> > --- a/drivers/gpu/drm/i915/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/intel_dp.c
>> > @@ -4191,57 +4191,44 @@ static void intel_dp_handle_test_request(struct
>> > intel_dp *intel_dp)
>> > static int
>> > intel_dp_check_mst_status(struct intel_dp *intel_dp)
>> > {
>> > - bool bret;
>> > + u8 esi[DP_DPRX_ESI_LEN] = { 0 };
>> > + struct intel_digital_port *intel_dig_port =
>> > dp_to_dig_port(intel_dp);
>> >
>> > - if (intel_dp->is_mst) {
>> > - u8 esi[DP_DPRX_ESI_LEN] = { 0 };
>> > - int ret = 0;
>> > - int retry;
>> > + if (!intel_dp->is_mst)
>> > + return -EINVAL;
>> > +
>> > + while (intel_dp_get_sink_irq_esi(intel_dp, esi)) {
>>
>> It looks like if the underlying drm_dp_dpcd_read fails and returns
>> -EIO, for instance, you'll get true back from
>> intel_dp_get_sink_irq_esi,
>
> Wait, anything other than 14 from that dpcd read is a false, isn't it?
D'oh! You're right - I completely glossed over the whole " ==
DP_DPRX_ESI_LEN" bit - sorry for the noise...
>
>> and you'll still go in to the while, but
>> with a potentially invalid esi. Granted, this is a problem in the
>> original code as well, but it seems like something that should be
>> fixed during the refactoring.
>>
>>
>> > + int ret, retry;
>> > bool handled;
>> > - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
>> > -go_again:
>> > - if (bret == true) {
>> > -
>> > - /* check link status - esi[10] = 0x200c */
>> > - if (intel_dp->active_mst_links &&
>> > - !drm_dp_channel_eq_ok(&esi[10],
>> > intel_dp->lane_count)) {
>> > - DRM_DEBUG_KMS("channel EQ not ok,
>> > retraining\n");
>> > - intel_dp_start_link_train(intel_dp);
>> > - intel_dp_stop_link_train(intel_dp);
>> > - }
>> >
>> > - DRM_DEBUG_KMS("got esi %3ph\n", esi);
>> > - ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi,
>> > &handled);
>> > -
>> > - if (handled) {
>> > - for (retry = 0; retry < 3; retry++) {
>> > - int wret;
>> > - wret =
>> > drm_dp_dpcd_write(&intel_dp->aux,
>> > -
>> > DP_SINK_COUNT_ESI+1,
>> > -&esi[1],
>> > 3);
>> > - if (wret == 3) {
>> > - break;
>> > - }
>> > - }
>> > + DRM_DEBUG_KMS("ESI %3ph\n", esi);
>> >
>> > - bret = intel_dp_get_sink_irq_esi(intel_dp,
>> > esi);
>> > - if (bret == true) {
>> > - DRM_DEBUG_KMS("got esi2 %3ph\n",
>> > esi);
>> > - goto go_again;
>> > - }
>> > - } else
>> > - ret = 0;
>> > + /* check link status - esi[10] = 0x200c */
>> > + if (intel_dp->active_mst_links &&
>> > + !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count))
>> > {
>> > + intel_dp_start_link_train(intel_dp);
>> > + intel_dp_stop_link_train(intel_dp);
>> > + }
>> >
>> > - return ret;
>> > - } else {
>> > - struct intel_digital_port *intel_dig_port =
>> > dp_to_dig_port(intel_dp);
>> > - DRM_DEBUG_KMS("failed to get ESI - device may have
>> > failed\n");
>> > - intel_dp->is_mst = false;
>> > -
Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status
On Wed, 2017-09-20 at 12:11 -0700, Ausmus, James wrote:
> On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan
> wrote:
> > Rewriting this code without the goto, I believe, makes it more readable.
> > One functional change that has been included is the handling of failed ESI
> > register reads. Instead of disabling MST only for the first failed read, we
> > now disable MST on subsequent failed reads too. A failed ESI read is
> > problematic irrespective of whether it is the first or not.
> >
> > Cc: James Ausmus
> > Cc: Jani Nikula
> > Cc: Ville Syrjälä
> > Signed-off-by: Dhinakaran Pandiyan
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 75
> > +
> > 1 file changed, 31 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 98e7b96ca826..cc129aa444ac 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4191,57 +4191,44 @@ static void intel_dp_handle_test_request(struct
> > intel_dp *intel_dp)
> > static int
> > intel_dp_check_mst_status(struct intel_dp *intel_dp)
> > {
> > - bool bret;
> > + u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> > + struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> >
> > - if (intel_dp->is_mst) {
> > - u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> > - int ret = 0;
> > - int retry;
> > + if (!intel_dp->is_mst)
> > + return -EINVAL;
> > +
> > + while (intel_dp_get_sink_irq_esi(intel_dp, esi)) {
>
> It looks like if the underlying drm_dp_dpcd_read fails and returns
> -EIO, for instance, you'll get true back from
> intel_dp_get_sink_irq_esi,
Wait, anything other than 14 from that dpcd read is a false, isn't it?
> and you'll still go in to the while, but
> with a potentially invalid esi. Granted, this is a problem in the
> original code as well, but it seems like something that should be
> fixed during the refactoring.
>
>
> > + int ret, retry;
> > bool handled;
> > - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> > -go_again:
> > - if (bret == true) {
> > -
> > - /* check link status - esi[10] = 0x200c */
> > - if (intel_dp->active_mst_links &&
> > - !drm_dp_channel_eq_ok(&esi[10],
> > intel_dp->lane_count)) {
> > - DRM_DEBUG_KMS("channel EQ not ok,
> > retraining\n");
> > - intel_dp_start_link_train(intel_dp);
> > - intel_dp_stop_link_train(intel_dp);
> > - }
> >
> > - DRM_DEBUG_KMS("got esi %3ph\n", esi);
> > - ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi,
> > &handled);
> > -
> > - if (handled) {
> > - for (retry = 0; retry < 3; retry++) {
> > - int wret;
> > - wret =
> > drm_dp_dpcd_write(&intel_dp->aux,
> > -
> > DP_SINK_COUNT_ESI+1,
> > -&esi[1],
> > 3);
> > - if (wret == 3) {
> > - break;
> > - }
> > - }
> > + DRM_DEBUG_KMS("ESI %3ph\n", esi);
> >
> > - bret = intel_dp_get_sink_irq_esi(intel_dp,
> > esi);
> > - if (bret == true) {
> > - DRM_DEBUG_KMS("got esi2 %3ph\n",
> > esi);
> > - goto go_again;
> > - }
> > - } else
> > - ret = 0;
> > + /* check link status - esi[10] = 0x200c */
> > + if (intel_dp->active_mst_links &&
> > + !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
> > + intel_dp_start_link_train(intel_dp);
> > + intel_dp_stop_link_train(intel_dp);
> > + }
> >
> > - return ret;
> > - } else {
> > - struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > - DRM_DEBUG_KMS("failed to get ESI - device may have
> > failed\n");
> > - intel_dp->is_mst = false;
> > - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> > intel_dp->is_mst);
> > - /* send a hotplug event */
> > -
> > drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
> > + ret = drm_dp_mst_hpd_i
Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.
On 09/20/2017 11:35 AM, Rodrigo Vivi wrote:
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
v3: Consider s_max = 6 and ss_max=4 to run over all possible
slices and subslices possible by spec. Although no real
hardware will have that many slices/subslices.
To match with sseu info init.
Even better :)
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
Reviewed-by: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +++--
drivers/gpu/drm/i915/i915_reg.h | 6 +
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e197e5d99277 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c257797c583..ac5c8e08878d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8020,11 +8020,17 @@ enum {
#define CHV_EU311_PG_ENABLE (1<<1)
I'm afraid the following now requires extra defines for slice = 4 and 5:
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8080) : \
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for tests/kms_cursor_legacy: Use gem_mmap__gtt() rather than gem_mmap__wc()
== Series Details == Series: tests/kms_cursor_legacy: Use gem_mmap__gtt() rather than gem_mmap__wc() URL : https://patchwork.freedesktop.org/series/30664/ State : failure == Summary == IGT patchset tested on top of latest successful build 6e2622564dc85875ee9e2f22874f9607cf0cdd9c meson: share the configuration_data object with latest DRM-Tip kernel build CI_DRM_3115 939fdb0533e7 drm-tip: 2017y-09m-20d-17h-36m-21s UTC integration manifest Test chamelium: Subgroup hdmi-crc-fast: pass -> DMESG-WARN (fi-skl-6700k) Test gem_mmap_gtt: Subgroup basic-read: pass -> INCOMPLETE (fi-cfl-s) Test gem_ringfill: Subgroup basic-default-hang: incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600 Test gem_sync: Subgroup basic-each: dmesg-warn -> PASS (fi-kbl-7500u) Test kms_addfb_basic: Subgroup bad-pitch-256: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup invalid-get-prop-any: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup unused-offsets: dmesg-warn -> PASS (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 +1 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: incomplete -> PASS (fi-kbl-7500u) fdo#102850 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (fi-glk-1) fdo#102777 fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:451s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:469s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:422s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:519s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:279s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:514s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:508s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:497s fi-cfl-s total:130 pass:108 dwarn:1 dfail:0 fail:0 skip:20 fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:425s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:571s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:437s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:409s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:430s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:494s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:470s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:471s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:580s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:587s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:541s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:456s fi-skl-6700k total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:754s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:488s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:576s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:419s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_233/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH libdrm 2/2] intel: Change a KBL pci id to GT2 from GT1.5
Any comments on this one. Sent out v2 after dropping [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids On Mon, Sep 11, 2017 at 9:22 AM, Anuj Phogat wrote: > See Mesa commit 9c588ff > > Cc: Matt Turner > Cc: Rodrigo Vivi > Signed-off-by: Anuj Phogat > --- > intel/intel_chipset.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h > index 77a9ca6..6bd8ae2 100644 > --- a/intel/intel_chipset.h > +++ b/intel/intel_chipset.h > @@ -198,7 +198,7 @@ > #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 > #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E > #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 > -#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 > +#define PCI_CHIP_KABYLAKE_M_GT20x5917 > #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 > #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B > #define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B > @@ -424,8 +424,7 @@ > (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ > (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) > > -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ > -(devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ > +#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ > (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ > (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1) > > @@ -433,6 +432,7 @@ > (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ > (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ > (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ > +(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ > (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ > (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) > > -- > 2.9.4 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status
On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan
wrote:
> Rewriting this code without the goto, I believe, makes it more readable.
> One functional change that has been included is the handling of failed ESI
> register reads. Instead of disabling MST only for the first failed read, we
> now disable MST on subsequent failed reads too. A failed ESI read is
> problematic irrespective of whether it is the first or not.
>
> Cc: James Ausmus
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/intel_dp.c | 75
> +
> 1 file changed, 31 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 98e7b96ca826..cc129aa444ac 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4191,57 +4191,44 @@ static void intel_dp_handle_test_request(struct
> intel_dp *intel_dp)
> static int
> intel_dp_check_mst_status(struct intel_dp *intel_dp)
> {
> - bool bret;
> + u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>
> - if (intel_dp->is_mst) {
> - u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> - int ret = 0;
> - int retry;
> + if (!intel_dp->is_mst)
> + return -EINVAL;
> +
> + while (intel_dp_get_sink_irq_esi(intel_dp, esi)) {
It looks like if the underlying drm_dp_dpcd_read fails and returns
-EIO, for instance, you'll get true back from
intel_dp_get_sink_irq_esi, and you'll still go in to the while, but
with a potentially invalid esi. Granted, this is a problem in the
original code as well, but it seems like something that should be
fixed during the refactoring.
> + int ret, retry;
> bool handled;
> - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> -go_again:
> - if (bret == true) {
> -
> - /* check link status - esi[10] = 0x200c */
> - if (intel_dp->active_mst_links &&
> - !drm_dp_channel_eq_ok(&esi[10],
> intel_dp->lane_count)) {
> - DRM_DEBUG_KMS("channel EQ not ok,
> retraining\n");
> - intel_dp_start_link_train(intel_dp);
> - intel_dp_stop_link_train(intel_dp);
> - }
>
> - DRM_DEBUG_KMS("got esi %3ph\n", esi);
> - ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi,
> &handled);
> -
> - if (handled) {
> - for (retry = 0; retry < 3; retry++) {
> - int wret;
> - wret =
> drm_dp_dpcd_write(&intel_dp->aux,
> -
> DP_SINK_COUNT_ESI+1,
> -&esi[1], 3);
> - if (wret == 3) {
> - break;
> - }
> - }
> + DRM_DEBUG_KMS("ESI %3ph\n", esi);
>
> - bret = intel_dp_get_sink_irq_esi(intel_dp,
> esi);
> - if (bret == true) {
> - DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
> - goto go_again;
> - }
> - } else
> - ret = 0;
> + /* check link status - esi[10] = 0x200c */
> + if (intel_dp->active_mst_links &&
> + !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
> + intel_dp_start_link_train(intel_dp);
> + intel_dp_stop_link_train(intel_dp);
> + }
>
> - return ret;
> - } else {
> - struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> - DRM_DEBUG_KMS("failed to get ESI - device may have
> failed\n");
> - intel_dp->is_mst = false;
> - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> intel_dp->is_mst);
> - /* send a hotplug event */
> -
> drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
> + ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
You're no longer using the value returned by drm_dp_mst_hpd_irq
> + if (!handled)
> + return 0;
> +
> + for (retry = 0; retry < 3; retry++) {
> + int wret;
> +
> + wret = drm_dp_dpcd_write(&intel_dp->aux,
> +
[Intel-gfx] [PATCH libdrm V2 2/2] intel: Change a KBL pci id to GT2 from GT1.5
See Mesa commit 9c588ff Cc: Matt Turner Cc: Rodrigo Vivi Signed-off-by: Anuj Phogat --- intel/intel_chipset.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3ff59ada..d81b1646 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -202,7 +202,7 @@ #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 +#define PCI_CHIP_KABYLAKE_M_GT20x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B @@ -434,7 +434,6 @@ #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ -(devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ @@ -446,6 +445,7 @@ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ +(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] force yuv 4:2:0 output
I've tried v4.14-rc1. Now I do not have 4k@60 anymore. dmesg with drm.debug: http://sprunge.us/TKbO Best Regards, Wolfgang Jani Nikula schrieb am Di., 19. Sep. 2017 um 12:08 Uhr: > On Mon, 18 Sep 2017, Wolfgang Haupt wrote: > > Hello everyone, > > > > recently I played around with my kabylake i5 nuc box and found that on > some > > TV's > > the screen stays black as soon as I go to 4k@60. > > The TV only accepts 4k@60 at yuv 4:2:0 (I also saw hdmi range extenders > and > > stuff that don't support yuv 4:4:4 on 4k@60). > > I tried to force limited mode through xrandr or by overriding the edid > > information, but nothing worked so far. > > Now I wonder if there is a way to force yuv 4:2:0 ouptut on the kernel > > level. > > Thanks. > > Please try v4.14-rc1. > > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Technology Center > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids
Dropping this patch.
On Tue, Sep 12, 2017 at 5:31 PM, Rodrigo Vivi wrote:
> On Tue, Sep 12, 2017 at 08:30:47PM +, Paulo Zanoni wrote:
>> Em Seg, 2017-09-11 às 10:10 -0700, Rodrigo Vivi escreveu:
>> > On Mon, Sep 11, 2017 at 04:11:33PM +, Anuj Phogat wrote:
>> > > See Mesa commits: ebc5ccf and b2dae9f
>> >
>> > I believe we need to be in sync between multiple gfx stack
>> > components,
>> > but I don't believe we should remove ids.
>> >
>> > In the past we had cases where we noticed a product group using a
>> > listed
>> > id to do a product and we just noticed the id after a user reported
>> > at fd.o.
>>
>> On the other hand, don't we have the risk that someone is going to see
>> that these IDs are unused for KBL and them repurpose them om some
>> future non-KBL product?
>
> There is only risk if the id was removed from Spec. But when that happens I'm
> in favor
> of removing from the components as well.
> While it is listed there even without POR it is reserved.
>
>>
>> >
>> > For us in kernel the cycle until that id gets into a stable release
>> > propagated to OSVs distros can be a bit long.
>> >
>> > Also Xserver ids are nowadays in sync with Mesa ones and I believe
>> > some
>> > OSVs might take a while to upgrade the Xserver as well in case of a
>> > new
>> > found product with some "new" id.
>> >
>> > For this reason I was always in favor of adding all possible reserved
>> > ids from the
>> > beginning.
>> >
>> > And this approach worked well on BDW and SKL, where we've seeing
>> > later some
>> > reserved ids becoming real product and we didn't have to do any extra
>> > step.
>> >
>> > For this same reason I believe the right solution is to
>> > add those ids back to mesa instead of removing from kernel and
>> > libdrm.
>> >
>> > Thanks,
>> > Rodrigo.
>> >
>> > >
>> > > Cc: Matt Turner
>> > > Cc: Rodrigo Vivi
>> > > Signed-off-by: Anuj Phogat
>> > > ---
>> > > drivers/gpu/drm/i915/i915_pci.c | 1 -
>> > > include/drm/i915_pciids.h | 15 ++-
>> > > 2 files changed, 2 insertions(+), 14 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> > > b/drivers/gpu/drm/i915/i915_pci.c
>> > > index 129877b..ecf6d4c 100644
>> > > --- a/drivers/gpu/drm/i915/i915_pci.c
>> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
>> > > @@ -613,7 +613,6 @@ static const struct pci_device_id pciidlist[] =
>> > > {
>> > > INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
>> > > INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
>> > > INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
>> > > - INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
>> > > INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
>> > > INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
>> > > INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
>> > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> > > index 1257e15..a1bf90e 100644
>> > > --- a/include/drm/i915_pciids.h
>> > > +++ b/include/drm/i915_pciids.h
>> > > @@ -337,15 +337,10 @@
>> > > INTEL_VGA_DEVICE(0x3185, info)
>> > >
>> > > #define INTEL_KBL_GT1_IDS(info) \
>> > > - INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
>> > > - INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
>> > > INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
>> > > INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
>> > > - INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
>> > > INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
>> > > - INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
>> > > - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
>> > > - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
>> > > + INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
>> > >
>> > > #define INTEL_KBL_GT2_IDS(info) \
>> > > INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
>> > > @@ -353,22 +348,16 @@
>> > > INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
>> > > INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
>> > > INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
>> > > - INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
>> > > INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
>> > >
>> > > #define INTEL_KBL_GT3_IDS(info) \
>> > > - INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
>> > > INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
>> > > INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
>> > >
>> > > -#define INTEL_KBL_GT4_IDS(info) \
>> > > - INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
>> > > -
>> > > #define INTEL_KBL_IDS(info) \
>> > > INTEL_KBL_GT1_IDS(info), \
>> > > INTEL_KBL_GT2_IDS(info), \
>> > > - INTEL_KBL_GT3_IDS(info), \
>> > > - INTEL_KBL_GT4_IDS(info)
>> > > + INTEL_KBL_GT3_IDS(info)
>> > >
>> > > /* CFL S */
>> > > #define INTEL_CFL_S_GT1_IDS(info) \
>> > > --
>> > > 2.9.4
>> > >
>> > > ___
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >
>> > ___
>> > Intel-gfx mailing list
>> >
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs
== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs URL : https://patchwork.freedesktop.org/series/30669/ State : success == Summary == Series 30669v1 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs https://patchwork.freedesktop.org/api/1.0/series/30669/revisions/1/mbox/ Test gem_ringfill: Subgroup basic-default-hang: incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600 Test gem_sync: Subgroup basic-each: dmesg-warn -> PASS (fi-kbl-7500u) Test kms_addfb_basic: Subgroup bad-pitch-256: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup invalid-get-prop-any: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup unused-offsets: dmesg-warn -> PASS (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: incomplete -> PASS (fi-kbl-7500u) fdo#102850 fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:436s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:474s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:421s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:512s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:501s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:493s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:488s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:539s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:564s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:409s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:487s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:467s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:471s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:543s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:447s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:748s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:563s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:412s fi-hsw-4770 failed to connect after reboot 939fdb0533e7b2cb97a192864fc18005072f6739 drm-tip: 2017y-09m-20d-17h-36m-21s UTC integration manifest 9889139163ec drm/i915/cnl: Fix SSEU Device Status. 0ef12da59396 drm/i915/cnl: Add support slice/subslice/eu configs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5771/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for GuC Fixes, Minor restructuring changes and v9+ logging change
== Series Details == Series: GuC Fixes, Minor restructuring changes and v9+ logging change URL : https://patchwork.freedesktop.org/series/30666/ State : success == Summary == Series 30666v1 GuC Fixes, Minor restructuring changes and v9+ logging change https://patchwork.freedesktop.org/api/1.0/series/30666/revisions/1/mbox/ Test gem_ringfill: Subgroup basic-default-hang: incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600 Test gem_sync: Subgroup basic-each: dmesg-warn -> PASS (fi-kbl-7500u) Test kms_addfb_basic: Subgroup bad-pitch-256: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup invalid-get-prop-any: dmesg-warn -> PASS (fi-kbl-7500u) Subgroup unused-offsets: dmesg-warn -> PASS (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 +1 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: incomplete -> PASS (fi-kbl-7500u) fdo#102850 fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:442s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:476s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:423s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:518s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:498s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:492s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:492s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:539s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:422s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:562s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:401s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:490s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:457s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:469s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:583s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:541s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:450s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:750s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:482s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:473s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:423s 939fdb0533e7b2cb97a192864fc18005072f6739 drm-tip: 2017y-09m-20d-17h-36m-21s UTC integration manifest 8d090da1d0f2 drm/i915: Reorganize HuC authentication c192fa0005fe drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9 d8d0cddfa0d9 drm/i915/guc: Remove i915_guc_log_unregister 351d0a34f71b drm/i915/guc: Fix GuC cleanup in unload path 84d348c5a970 drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset d534d9fecfa8 drm/i915/guc: Update suspend functionality in intel_uc_suspend path f02b0b985159 drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume d71299f76d10 drm/i915/guc: Update prototype/name of GuC suspend/resume fns and move to intel_uc.c 94e8ceb4ae5f drm/i915: Create uc runtime and system suspend/resume helpers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5770/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-misc-next
On Wed, Sep 20, 2017 at 07:33:35PM +0200, Daniel Vetter wrote: > include/uapi/drm/drm_mode.h| 4 +- In case you wonder why Daniel didn't say anything about uapi changes: It's a comment/documentation fix :-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
v3: Consider s_max = 6 and ss_max=4 to run over all possible
slices and subslices possible by spec. Although no real
hardware will have that many slices/subslices.
To match with sseu info init.
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
Reviewed-by: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +++--
drivers/gpu/drm/i915/i915_reg.h | 6 +
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e197e5d99277 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c257797c583..ac5c8e08878d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8020,11 +8020,17 @@ enum {
#define CHV_EU311_PG_ENABLE (1<<1)
#define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8080) : \
+GEN9_SLICE_PGCTL_ACK((slice)))
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
#define GEN9_PGCTL_SS_ACK(subslice) (1
[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs
From: Ben Widawsky
Cannonlake Slice and Subslice information has changed.
This patch initially provided by Ben adds the proper sseu
initialization.
v2: This v2 done by Rodrigo includes:
- Fix on Total slices count by avoiding [1][2] and [2][2].
- Inclusion of EU Per Subslice.
- Commit message.
v3: This v3 done by Rodrigo includes:
- Handle all possible bits and extra fuse register.
- Use INTEL_GEN macro.
- Fully assume uniform distribution so remove union
with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
- Consider all bits available: 6 bits for slices [27:22]
and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
- sseu->subslice_mask = (1 << 4) - 1 - missed on previous
versions and noticed by Oscar.
Cc: Oscar Mateo
Signed-off-by: Ben Widawsky
Signed-off-by: Rodrigo Vivi
Reviewed-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++
drivers/gpu/drm/i915/intel_device_info.c | 37 +++-
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd0cd94..1c257797c583 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
#define GEN9_F2_SS_DIS_SHIFT 20
#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
+#define GEN10_F2_S_ENA_SHIFT 22
+#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define GEN10_F2_SS_DIS_SHIFT18
+#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
+
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
#define GEN8_EU_DIS0_S0_MASK 0xff
#define GEN8_EU_DIS0_S1_SHIFT24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
+#define GEN10_EU_DISABLE3 _MMIO(0x9140)
+#define GEN10_EU_DIS_SS_MASK 0xff
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..d2e7ae61775d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private
*dev_priv)
#undef PRINT_FLAG
}
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+ sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+ GEN10_F2_S_ENA_SHIFT;
+ sseu->subslice_mask = (1 << 4) - 1;
+ sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+GEN10_F2_SS_DIS_SHIFT);
+
+ sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+ sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+ sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+ sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+GEN10_EU_DIS_SS_MASK));
+
+ /*
+* CNL is expected to always have a uniform distribution
+* of EU across subslices with the exception that any one
+* EU in any one subslice may be fused off for die
+* recovery.
+*/
+ sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+ DIV_ROUND_UP(sseu->eu_total,
+sseu_subslice_total(sseu)) : 0;
+
+ /* No restrictions on Power Gating */
+ sseu->has_slice_pg = 1;
+ sseu->has_subslice_pg = 1;
+ sseu->has_eu_pg = 1;
+}
+
static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
- else if (INTEL_INFO(dev_priv)->gen >= 9)
+ else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 10)
+ gen10_sseu_info_init(dev_priv);
DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
--
2.13.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.
On 09/19/2017 03:06 PM, Rodrigo Vivi wrote:
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
Reviewed-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +++--
drivers/gpu/drm/i915/i915_reg.h | 6 +
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e86d2be4b815 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 4, ss_max = 3;
Now the two patches are misaligned in the sense that the other one
considers s_max = 6 and ss_max = 4
It's not very important because this is only debugfs and we know from
the specs that s_max = 4 and ss_max = 3 are enough to cover all
real-life scenarios, but can we explain this in a comment before merging?
Thanks!
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f4b8faf2982..93b688666419 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8018,11 +8018,17 @@ enum {
#define CHV_EU311_PG_ENABLE (1<<1)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8080) : \
+G
Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs
On 09/19/2017 03:06 PM, Rodrigo Vivi wrote:
From: Ben Widawsky
Cannonlake Slice and Subslice information has changed.
This patch initially provided by Ben adds the proper sseu
initialization.
v2: This v2 done by Rodrigo includes:
- Fix on Total slices count by avoiding [1][2] and [2][2].
- Inclusion of EU Per Subslice.
- Commit message.
v3: This v3 done by Rodrigo includes:
- Handle all possible bits and extra fuse register.
- Use INTEL_GEN macro.
- Fully assume uniform distribution so remove union
with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
- Consider all bits available: 6 bits for slices [27:22]
and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
- sseu->subslice_mask = (1 << 4) - 1 - missed on previous
versions and noticed by Oscar.
Cc: Oscar Mateo
Signed-off-by: Ben Widawsky
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++
drivers/gpu/drm/i915/intel_device_info.c | 37 +++-
2 files changed, 44 insertions(+), 1 deletion(-)
Reviewed-by: Oscar Mateo
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..9f4b8faf2982 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
#define GEN9_F2_SS_DIS_SHIFT20
#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
+#define GEN10_F2_S_ENA_SHIFT 22
+#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define GEN10_F2_SS_DIS_SHIFT18
+#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
+
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
#define GEN8_EU_DIS0_S0_MASK0xff
#define GEN8_EU_DIS0_S1_SHIFT 24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
+#define GEN10_EU_DISABLE3 _MMIO(0x9140)
+#define GEN10_EU_DIS_SS_MASK 0xff
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..d2e7ae61775d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private
*dev_priv)
#undef PRINT_FLAG
}
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+ sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+ GEN10_F2_S_ENA_SHIFT;
+ sseu->subslice_mask = (1 << 4) - 1;
+ sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+GEN10_F2_SS_DIS_SHIFT);
+
+ sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+ sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+ sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+ sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+GEN10_EU_DIS_SS_MASK));
+
+ /*
+* CNL is expected to always have a uniform distribution
+* of EU across subslices with the exception that any one
+* EU in any one subslice may be fused off for die
+* recovery.
+*/
+ sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+ DIV_ROUND_UP(sseu->eu_total,
+sseu_subslice_total(sseu)) : 0;
+
+ /* No restrictions on Power Gating */
+ sseu->has_slice_pg = 1;
+ sseu->has_subslice_pg = 1;
+ sseu->has_eu_pg = 1;
+}
+
static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
- else if (INTEL_INFO(dev_priv)->gen >= 9)
+ else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 10)
+ gen10_sseu_info_init(dev_priv);
DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 4/9] drm/i915/guc: Update suspend functionality in intel_uc_suspend path
With this patch we disable GuC submission in i915_drm_suspend. This will
destroy the client which will be setup back again. We also reuse the
complete sanitization done via intel_uc_runtime_suspend in this path.
Post drm resume this state is recreated by intel_uc_init_hw hence we need
not have similar reuse for intel_uc_resume.
This also fixes issue where intel_uc_fini_hw was being called after GPU
reset happening in i915_gem_suspend in i915_driver_unload.
v2: Rebase w.r.t removal of GuC code restructuring. Added struct_mutex
protection for i915_guc_submission_disable.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index fa698db..0c7e45c7 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -446,9 +446,6 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (!i915.enable_guc_loading)
return;
- if (i915.enable_guc_submission)
- i915_guc_submission_disable(dev_priv);
-
guc_disable_communication(&dev_priv->guc);
if (i915.enable_guc_submission) {
@@ -654,7 +651,20 @@ int intel_uc_runtime_resume(struct drm_i915_private
*dev_priv)
int intel_uc_suspend(struct drm_i915_private *dev_priv)
{
- return intel_guc_enter_sleep(&dev_priv->guc);
+ struct drm_device *dev = &dev_priv->drm;
+ int ret;
+
+ if (i915.enable_guc_submission) {
+ mutex_lock(&dev->struct_mutex);
+ i915_guc_submission_disable(dev_priv);
+ mutex_unlock(&dev->struct_mutex);
+ }
+
+ ret = intel_uc_runtime_suspend(dev_priv);
+ if (ret)
+ return ret;
+
+ return 0;
}
int intel_uc_resume(struct drm_i915_private *dev_priv)
--
1.9.1
___
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[Intel-gfx] [PATCH v4 6/9] drm/i915/guc: Fix GuC cleanup in unload path
We ensure that GuC is completely suspended and client is destroyed
in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw
should just take care of cleanup,
hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly
we also updated as s/i915_guc_submission_fini/i915_guc_submission_cleanup
Other functionality to disable communication, disable interrupts and
update of ggtt.invalidate is taken care by intel_uc_suspend.
With this patch we are also doing guc_free_load_err_log only
if i915.enable_guc_loading is set.
Created intel_guc_cleanup function to wrap the cleanup functions
specific to GuC.
v2: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 21 +++--
drivers/gpu/drm/i915/intel_uc.h| 4 ++--
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8635f40..6f36ced 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -602,7 +602,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_uc_fini_hw(dev_priv);
+ intel_uc_cleanup(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 94efe32..12f1195 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1050,7 +1050,7 @@ int i915_guc_submission_init(struct drm_i915_private
*dev_priv)
return ret;
}
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index aac8526..8c42344 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -418,7 +418,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
guc_capture_load_err_log(guc);
err_submission:
if (i915.enable_guc_submission)
- i915_guc_submission_fini(dev_priv);
+ i915_guc_submission_cleanup(dev_priv);
err_guc:
i915_ggtt_disable_guc(dev_priv);
@@ -439,21 +439,22 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
return ret;
}
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
+static void intel_guc_cleanup(struct intel_guc *guc)
{
- guc_free_load_err_log(&dev_priv->guc);
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ if (i915.enable_guc_submission)
+ i915_guc_submission_cleanup(dev_priv);
+}
+void intel_uc_cleanup(struct drm_i915_private *dev_priv)
+{
if (!i915.enable_guc_loading)
return;
- guc_disable_communication(&dev_priv->guc);
-
- if (i915.enable_guc_submission) {
- gen9_disable_guc_interrupts(dev_priv);
- i915_guc_submission_fini(dev_priv);
- }
+ guc_free_load_err_log(&dev_priv->guc);
- i915_ggtt_disable_guc(dev_priv);
+ intel_guc_cleanup(&dev_priv->guc);
}
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 069c2b2..8557e33 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -207,7 +207,7 @@ struct intel_huc {
void intel_uc_init_fw(struct drm_i915_private *dev_priv);
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_uc_cleanup(struct drm_i915_private *dev_priv);
int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv);
int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
@@ -236,7 +236,7 @@ static inline void intel_guc_notify(struct intel_guc *guc)
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
/* intel_guc_log.c */
--
1.9.1
___
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[Intel-gfx] [PATCH v4 9/9] drm/i915: Reorganize HuC authentication
Prepared intel_auth_huc to separate HuC specific functionality
from GuC send action. Created new header intel_huc.h to group
HuC specific declarations.
v2: Changed argument preparation for AUTHENTICATE_HUC.
s/intel_auth_huc/intel_huc_auth. Deferred creation of intel_huc.h
to later patch.
v3: Rebase as intel_guc.h is removed. Added param description to
intel_huc_auth. (Michal)
v4: Rebase as intel_guc.h is added again. :)
v5: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_huc.c | 22 +++---
drivers/gpu/drm/i915/intel_uc.c | 20 +++-
drivers/gpu/drm/i915/intel_uc.h | 3 ++-
3 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 6145fa0..d3da4d3 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -225,19 +225,16 @@ void intel_huc_init_hw(struct intel_huc *huc)
}
/**
- * intel_guc_auth_huc() - authenticate ucode
- * @dev_priv: the drm_i915_device
- *
- * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
- * authenticate_huc interface.
+ * intel_huc_auth() - authenticate ucode
+ * @huc: intel_huc structure
*/
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+void intel_huc_auth(struct intel_huc *huc)
{
+ struct drm_i915_private *dev_priv = huc_to_i915(huc);
struct intel_guc *guc = &dev_priv->guc;
- struct intel_huc *huc = &dev_priv->huc;
struct i915_vma *vma;
+ u32 offset;
int ret;
- u32 data[2];
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return;
@@ -250,11 +247,8 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
return;
}
- /* Specify auth action and where public signature is. */
- data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
- data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
-
- ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+ offset = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
+ ret = intel_guc_auth_huc(guc, offset);
if (ret) {
DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
goto out;
@@ -266,7 +260,6 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
HUC_FW_VERIFIED,
HUC_FW_VERIFIED,
50);
-
if (ret) {
DRM_ERROR("HuC: Authentication failed %d\n", ret);
goto out;
@@ -275,4 +268,3 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
out:
i915_vma_unpin(vma);
}
-
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8c42344..6a64cd0 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -328,6 +328,24 @@ static void guc_disable_communication(struct intel_guc
*guc)
guc->send = intel_guc_send_nop;
}
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @guc: struct intel_guc*
+ * @offset: rsa offset w.r.t ggtt base of huc vma
+ *
+ * triggers a huc fw authentication request to the guc via intel_guc_send
+ * authenticate_huc interface.
+ */
+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
+{
+ u32 action[] = {
+ INTEL_GUC_ACTION_AUTHENTICATE_HUC,
+ rsa_offset
+ };
+
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
+}
+
int intel_uc_init_hw(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
@@ -390,7 +408,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto err_log_capture;
- intel_guc_auth_huc(dev_priv);
+ intel_huc_auth(&dev_priv->huc);
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index c2c104a..cc2ee4f 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -216,6 +216,7 @@ struct intel_huc {
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32
len)
{
@@ -256,6 +257,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
/* intel_huc.c */
void intel_huc_select_fw(struct intel_huc *huc);
void intel_huc_init_hw(struct intel_huc *huc);
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
+void intel_huc_auth(struct intel_huc *huc);
#endif
--
[Intel-gfx] [PATCH v4 0/9] GuC Fixes, Minor restructuring changes and v9+ logging change
This series is based on reviews from https://patchwork.freedesktop.org/series/30351/. Due to changing priority and complexity of restructuring, this patch series has gone through >5 revisions but would want to maintain the series w.r.t above base series. W.r.t above series this is rev4. Older series can be found at https://patchwork.freedesktop.org/series/30502/. Sagar Arun Kamble (9): drm/i915: Create uc runtime and system suspend/resume helpers drm/i915/guc: Update prototype/name of GuC suspend/resume fns and move to intel_uc.c drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume drm/i915/guc: Update suspend functionality in intel_uc_suspend path drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset drm/i915/guc: Fix GuC cleanup in unload path drm/i915/guc: Remove i915_guc_log_unregister drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9 drm/i915: Reorganize HuC authentication drivers/gpu/drm/i915/i915_drv.c| 26 +++- drivers/gpu/drm/i915/i915_gem.c| 9 +- drivers/gpu/drm/i915/i915_guc_submission.c | 54 +--- drivers/gpu/drm/i915/intel_guc_fwif.h | 4 +- drivers/gpu/drm/i915/intel_guc_log.c | 25 ++-- drivers/gpu/drm/i915/intel_huc.c | 22 ++-- drivers/gpu/drm/i915/intel_uc.c| 195 ++--- drivers/gpu/drm/i915/intel_uc.h| 15 ++- 8 files changed, 241 insertions(+), 109 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 7/9] drm/i915/guc: Remove i915_guc_log_unregister
Functionality needed to disable GuC interrupts and cleanup the
runtime/relay data structures is already covered in the unload path
via intel_guc_fini_hw and intel_guc_cleanup hence remove
i915_guc_log_unregister
v2: Removed the function i915_guc_log_unregister.
v3: Rebase as intel_guc.h is removed.
v4: Rebase as intel_guc.h is created again. :)
v5: Rebase as intel_guc.h is removed.
Cc: Michal Wajdeczko
Reviewed-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm/i915/intel_guc_log.c | 12
drivers/gpu/drm/i915/intel_uc.h | 1 -
3 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6f36ced..c69a30a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1252,7 +1252,6 @@ static void i915_driver_unregister(struct
drm_i915_private *dev_priv)
i915_perf_unregister(dev_priv);
i915_teardown_sysfs(dev_priv);
- i915_guc_log_unregister(dev_priv);
drm_dev_unregister(&dev_priv->drm);
i915_gem_shrinker_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..3c45681 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -648,15 +648,3 @@ void i915_guc_log_register(struct drm_i915_private
*dev_priv)
guc_log_late_setup(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
-
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
-{
- if (!i915.enable_guc_submission)
- return;
-
- mutex_lock(&dev_priv->drm.struct_mutex);
- /* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_disable_guc_interrupts(dev_priv);
- guc_log_runtime_destroy(&dev_priv->guc);
- mutex_unlock(&dev_priv->drm.struct_mutex);
-}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 8557e33..c2c104a 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -244,7 +244,6 @@ static inline void intel_guc_notify(struct intel_guc *guc)
void intel_guc_log_destroy(struct intel_guc *guc);
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
void i915_guc_log_register(struct drm_i915_private *dev_priv);
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
static inline u32 guc_ggtt_offset(struct i915_vma *vma)
{
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/9] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume
Apart from configuring interrupts, we need to update the ggtt invalidate
interface and GuC communication on suspend. This functionality can be
reused for other suspend and reset paths.
Prepared GuC specific helpers to handle these suspend/resume tasks
namely - intel_guc_runtime_suspend, intel_guc_runtime_resume.
v2: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 66 -
1 file changed, 59 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0dbb4b9..fa698db 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -551,8 +551,6 @@ static int intel_guc_enter_sleep(struct intel_guc *guc)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_disable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
@@ -577,9 +575,6 @@ static int intel_guc_exit_sleep(struct intel_guc *guc)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
@@ -590,14 +585,71 @@ static int intel_guc_exit_sleep(struct intel_guc *guc)
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}
+int intel_guc_runtime_suspend(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int ret;
+
+ ret = intel_guc_enter_sleep(guc);
+ if (ret) {
+ DRM_ERROR("GuC enter sleep failed (%d)\n", ret);
+ return ret;
+ }
+
+ i915_ggtt_disable_guc(dev_priv);
+ gen9_disable_guc_interrupts(dev_priv);
+
+ return 0;
+}
+
+int intel_guc_runtime_resume(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int ret;
+
+ if (i915.guc_log_level >= 0)
+ gen9_enable_guc_interrupts(dev_priv);
+ i915_ggtt_enable_guc(dev_priv);
+
+ ret = intel_guc_exit_sleep(guc);
+ if (ret) {
+ DRM_ERROR("GuC exit sleep failed (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv)
{
- return intel_guc_enter_sleep(&dev_priv->guc);
+ int ret;
+
+ if (!i915.enable_guc_loading)
+ return 0;
+
+ ret = intel_guc_runtime_suspend(&dev_priv->guc);
+ if (ret)
+ return ret;
+
+ guc_disable_communication(&dev_priv->guc);
+
+ return 0;
}
int intel_uc_runtime_resume(struct drm_i915_private *dev_priv)
{
- return intel_guc_exit_sleep(&dev_priv->guc);
+ int ret;
+
+ if (!i915.enable_guc_loading)
+ return 0;
+
+ ret = guc_enable_communication(&dev_priv->guc);
+ if (ret) {
+ DRM_ERROR("GuC enable communication failed (%d)\n", ret);
+ return ret;
+ }
+
+ return intel_guc_runtime_resume(&dev_priv->guc);
}
int intel_uc_suspend(struct drm_i915_private *dev_priv)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 8/9] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9
With GuC v9, new type of Default/critical logging in GuC to enable
capturing minimal important logs in production systems efficiently.
This patch enables this logging in GuC by default always. It should
be noted that streaming support with half-full interrupt mechanism
that is present for normal logging is not present for this type of
logging.
v2: Emulated GuC critical logging through i915.guc_log_level.
v3: Commit message update. Enable default/critical logging in GuC always.
Fixed RPM wake during guc_log_unregister in the unload path.
v4: Moved RPM wake change to separate patch. Removed GUC_DEBUG_RESERVED
and updated name of new bit to be version agnostic. Updated parameter to
struct intel_guc * and name of macro NEEDS_GUC_CRITICAL_LOGGING.
Removed explicit clearing of GUC_CRITICAL_LOGGING_DISABLED from
params[GUC_CTL_DEBUG] as it is unnecessary. (Michal Wajdeczko)
v5: Removed GUC_CRITICAL_LOGGING_DISABLED. Added HAS_GUC check to
GUC_NEEDS_CRITICAL_LOGGING. (Michal Wajdeczko)
v6: More refined version of GUC_NEEDS_CRITICAL_LOGGING. Commit message
update. (Michal Wajdeczko)
Cc: Chheda Harsh J
Cc: Fry Gregory P
Cc: Spotswood John A
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Michal Wajdeczko
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 4 ++--
drivers/gpu/drm/i915/intel_guc_log.c | 13 -
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 7eb6b4f..fed875a 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -127,7 +127,6 @@
#define GUC_PROFILE_ENABLED (1 << 7)
#define GUC_WQ_TRACK_ENABLED (1 << 8)
#define GUC_ADS_ENABLED (1 << 9)
-#define GUC_DEBUG_RESERVED (1 << 10)
#define GUC_ADS_ADDR_SHIFT 11
#define GUC_ADS_ADDR_MASK0xf800
@@ -539,7 +538,8 @@ struct guc_log_buffer_state {
u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
- u32 reserved2:24;
+ u32 critical_logging_enabled:1;
+ u32 reserved2:23;
};
u32 value;
} __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 3c45681..b820175 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -586,10 +586,18 @@ void intel_guc_log_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(&guc->log.vma);
}
+/*
+ * Critical logging in GuC is to be enabled always from GuC v9+.
+ * (for KBL - v9.39+)
+ */
+#define GUC_NEEDS_CRITICAL_LOGGING(guc)\
+ (HAS_GUC(guc_to_i915(guc)) && \
+(guc->fw.major_ver_found >= 9) && \
+(guc->fw.minor_ver_found >= (IS_KABYLAKE(guc_to_i915(guc)) ? 39 : 0)))
+
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
{
struct intel_guc *guc = &dev_priv->guc;
-
union guc_log_control log_param;
int ret;
@@ -603,6 +611,9 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv,
u64 control_val)
if (!log_param.logging_enabled && (i915.guc_log_level < 0))
return 0;
+ if (GUC_NEEDS_CRITICAL_LOGGING(guc))
+ log_param.critical_logging_enabled = 1;
+
ret = guc_log_control(guc, log_param.value);
if (ret < 0) {
DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/9] drm/i915/guc: Update prototype/name of GuC suspend/resume fns and move to intel_uc.c
Renamed intel_guc_suspend to intel_guc_enter_sleep and intel_guc_resume
to intel_guc_exit_sleep to match GuC nomenclature compatibility.
We plan to use intel_guc_suspend and intel_guc_resume through
intel_uc_suspend and intel_uc_resume in the path i915_drm_suspend and
i915_drm_resume respectively for better naming.
Also, with this patch we pass intel_guc struct as parameter to enter_sleep
and exit_sleep functions as they are GuC specific and they are moved to
intel_uc.c as static functions called from uc generic functions.
v2: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 52 ---
drivers/gpu/drm/i915/intel_uc.c| 58 --
drivers/gpu/drm/i915/intel_uc.h| 2 --
3 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e191d56..94efe32 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1205,55 +1205,3 @@ void i915_guc_submission_disable(struct drm_i915_private
*dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
}
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- gen9_disable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
- /* any value greater than GUC_POWER_D0 */
- data[1] = GUC_POWER_D1;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
-
-/**
- * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- data[1] = GUC_POWER_D0;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8e4d8b0..0dbb4b9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -538,19 +538,71 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
+/**
+ * intel_guc_enter_sleep() - notify GuC entering sleep state
+ * @guc: guc structure
+ */
+static int intel_guc_enter_sleep(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct i915_gem_context *ctx;
+ u32 data[3];
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ gen9_disable_guc_interrupts(dev_priv);
+
+ ctx = dev_priv->kernel_context;
+
+ data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
+ /* any value greater than GUC_POWER_D0 */
+ data[1] = GUC_POWER_D1;
+ /* first page is shared data with GuC */
+ data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
+
+ return intel_guc_send(guc, data, ARRAY_SIZE(data));
+}
+
+/**
+ * intel_guc_exit_sleep() - notify GuC exit from sleep state
+ * @guc: guc structure
+ */
+static int intel_guc_exit_sleep(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct i915_gem_context *ctx;
+ u32 data[3];
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ if (i915.guc_log_level >= 0)
+ gen9_enable_guc_interrupts(dev_priv);
+
+ ctx = dev_priv->kernel_context;
+
+ data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
+ data[1] = GUC_POWER_D0;
+ /* first page is shared data with GuC */
+ data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN *
PAGE_SIZE;
+
+ return intel_guc_send(guc, data, ARRAY_SIZE(data));
+}
+
int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv)
{
- return intel_guc_suspend(dev_priv);
+ return intel_guc_enter_sleep(&dev_pri
[Intel-gfx] [PATCH v4 5/9] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset
Before i915 reset we need to disable GuC submission and suspend GuC
operarions as it is recreated during intel_uc_init_hw. We can't reuse the
intel_uc_suspend functionality as reset path already holds struct_mutex.
v2: Rebase w.r.t removal of GuC code restructuring. Updated reset_prepare
function as struct_mutex is not needed.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
drivers/gpu/drm/i915/intel_uc.c | 14 ++
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dd56d45..76e1bb2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2847,6 +2847,8 @@ int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv)
i915_gem_revoke_fences(dev_priv);
+ intel_uc_reset_prepare(dev_priv);
+
return err;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0c7e45c7..aac8526 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -671,3 +671,17 @@ int intel_uc_resume(struct drm_i915_private *dev_priv)
{
return 0;
}
+
+int intel_uc_reset_prepare(struct drm_i915_private *dev_priv)
+{
+ int ret;
+
+ if (i915.enable_guc_submission)
+ i915_guc_submission_disable(dev_priv);
+
+ ret = intel_uc_runtime_suspend(dev_priv);
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 5f49d13..069c2b2 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -212,6 +212,7 @@ struct intel_huc {
int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
int intel_uc_resume(struct drm_i915_private *dev_priv);
+int intel_uc_reset_prepare(struct drm_i915_private *dev_priv);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/9] drm/i915: Create uc runtime and system suspend/resume helpers
Prepared generic helpers intel_uc_suspend, intel_uc_resume,
intel_uc_runtime_suspend, intel_uc_runtime_resume. Added
error handling to all the calls for suspend/resume.
v2: Rebase w.r.t removal of GuC code restructuring.
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 23 ---
drivers/gpu/drm/i915/i915_gem.c | 7 ++-
drivers/gpu/drm/i915/intel_uc.c | 20
drivers/gpu/drm/i915/intel_uc.h | 4
4 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5c111ea..8635f40 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1691,7 +1691,15 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(&dev->struct_mutex);
- intel_guc_resume(dev_priv);
+ /*
+* NB: Full gem reinitialization is being done above, hence
+* intel_uc_resume will be of no use. Currently intel_uc_resume
+* is nop. If full reinitialization is removed, will need to put
+* functionality to resume from sleep in intel_uc_resume.
+*/
+ ret = intel_uc_resume(dev_priv);
+ if (ret)
+ DRM_ERROR("failed to resume uc\n");
intel_modeset_init_hw(dev);
@@ -2493,7 +2501,12 @@ static int intel_runtime_suspend(struct device *kdev)
*/
i915_gem_runtime_suspend(dev_priv);
- intel_guc_suspend(dev_priv);
+ ret = intel_uc_runtime_suspend(dev_priv);
+ if (ret) {
+ DRM_ERROR("uc runtime suspend failed, disabling it(%d)\n", ret);
+ enable_rpm_wakeref_asserts(dev_priv);
+ return ret;
+ }
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2578,7 +2591,11 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
- intel_guc_resume(dev_priv);
+ ret = intel_uc_runtime_resume(dev_priv);
+ if (ret) {
+ DRM_ERROR("uc runtime resume failed (%d)\n", ret);
+ return ret;
+ }
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c4bf348..dd56d45 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4539,7 +4539,11 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(&dev->struct_mutex);
- intel_guc_suspend(dev_priv);
+ ret = intel_uc_suspend(dev_priv);
+ if (ret) {
+ DRM_ERROR("uc suspend failed (%d)\n", ret);
+ goto out;
+ }
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(&dev_priv->gt.retire_work);
@@ -4583,6 +4587,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
err_unlock:
mutex_unlock(&dev->struct_mutex);
+out:
intel_runtime_pm_put(dev_priv);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..8e4d8b0 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -537,3 +537,23 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
+
+int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv)
+{
+ return intel_guc_suspend(dev_priv);
+}
+
+int intel_uc_runtime_resume(struct drm_i915_private *dev_priv)
+{
+ return intel_guc_resume(dev_priv);
+}
+
+int intel_uc_suspend(struct drm_i915_private *dev_priv)
+{
+ return intel_guc_suspend(dev_priv);
+}
+
+int intel_uc_resume(struct drm_i915_private *dev_priv)
+{
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 7703c9a..3d33a51 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -208,6 +208,10 @@ struct intel_huc {
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv);
+int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
+int intel_uc_suspend(struct drm_i915_private *dev_priv);
+int intel_uc_resume(struct drm_i915_private *dev_priv);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
--
1.9.1
___
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[Intel-gfx] [PULL] drm-misc-next
Hi Dave, I heard you're nicely sleep-deprived again, so perfect time to send you a pull request. First pile of drm-misc for 4.15, busy as usual (but still well less than half the patch activity drm-intel.git has seen in the same time). drm-misc-next-2017-09-20: UAPI Changes: Cross-subsystem Changes: Core Changes: - DP SDP defines (Ville) - polish for scdc helpers (Thierry Reding) - fix lifetimes for connector/plane state across crtc changes (Maarten Lankhorst). - sparse fixes (Ville+Thierry) - make legacy kms ioctls all interruptible (Maarten) - push edid override into the edid helpers (out of probe helpers) (Jani) - DP ESI defines for link status (DK) Driver Changes: - drm-panel is now in drm-misc! - minor panel-simple cleanups/refactoring by various folks - drm_bridge_add cleanup (Inki Dea) - constify a few i2c_device_id structs (Arvind Yadav) - More patches from Noralf's fb/gem helper cleanup - bridge/synopsis: reset fix (Philippe Cornu) - fix tracepoint include handling in drivers (Thierry) - rockchip: lvds support (Sandy Huang) - move sun4i into drm-misc fold (Maxime Ripard) - sun4i: refactor driver load + support TCON backend/layer muxing (Chen-Yu Tsai) - pl111: support more pl11x variants (Linus Walleij) - bridge/adv7511: robustify probing/edid handling (Lars-Petersen Clausen) New hw support: - S6E63J0X03 panel (Hoegeun Kwon) - OTM8009A panel (Philippe CORNU) - Seiko 43WVF1G panel (Marco Franchi) - tve200 driver (Linus Walleij) Plus assorted of tiny patches all over, including our first outreachy patches from applicants for the winter round! Cheers, Daniel The following changes since commit 0e8841ec7ee5b1ffe416c3be7743985b1896ec00: Merge airlied/drm-next into drm-misc-next (2017-08-18 10:52:44 -0400) are available in the git repository at: git://anongit.freedesktop.org/git/drm-misc tags/drm-misc-next-2017-09-20 for you to fetch changes up to ac6c35a4d8c77083525044a192cb1a8711381e94: drm: add backwards compatibility support for drm_kms_helper.edid_firmware (2017-09-19 18:11:45 +0300) UAPI Changes: Cross-subsystem Changes: Core Changes: - DP SDP defines (Ville) - polish for scdc helpers (Thierry Reding) - fix lifetimes for connector/plane state across crtc changes (Maarten Lankhorst). - sparse fixes (Ville+Thierry) - make legacy kms ioctls all interruptible (Maarten) - push edid override into the edid helpers (out of probe helpers) (Jani) - DP ESI defines for link status (DK) Driver Changes: - drm-panel is now in drm-misc! - minor panel-simple cleanups/refactoring by various folks - drm_bridge_add cleanup (Inki Dea) - constify a few i2c_device_id structs (Arvind Yadav) - More patches from Noralf's fb/gem helper cleanup - bridge/synopsis: reset fix (Philippe Cornu) - fix tracepoint include handling in drivers (Thierry) - rockchip: lvds support (Sandy Huang) - move sun4i into drm-misc fold (Maxime Ripard) - sun4i: refactor driver load + support TCON backend/layer muxing (Chen-Yu Tsai) - pl111: support more pl11x variants (Linus Walleij) - bridge/adv7511: robustify probing/edid handling (Lars-Petersen Clausen) New hw support: - S6E63J0X03 panel (Hoegeun Kwon) - OTM8009A panel (Philippe CORNU) - Seiko 43WVF1G panel (Marco Franchi) - tve200 driver (Linus Walleij) Plus assorted of tiny patches all over, including our first outreachy patches from applicants for the winter round! Arnd Bergmann (2): drm: gma500: fix logic error drm/stm: fix warning about multiplication in condition Arvind Yadav (3): drm: i2c: ch7006: constify i2c_device_id drm: i2c: sil164: constify i2c_device_id drm: i2c: tda998x: constify i2c_device_id Chen-Yu Tsai (7): drm/sun4i: tcon: Unconditionally reset the TCON drm/sun4i: add components in breadth first traversal order drm/sun4i: tcon: Check for multiple paths between TCONs and backends drm/sun4i: tcon: get TCON ID and matching engine with remote endpoint ID drm/sun4i: tcon: Simplify sun4i_tcon_find_engine_traverse for one input drm/sun4i: tcon: Support backend input mux drm/sun4i: call drm_vblank_init with correct number of crtcs Chris Wilson (1): drm: Release driver tracking before making the object available again Colin Ian King (1): drm/vc4: clean up error handling on devm_kzalloc failure Daniel Vetter (2): drm/doc: Document ioctl errno value patterns drm/doc: Update todo.rst Dhinakaran Pandiyan (2): drm/dp/mst: Sideband message transaction to power up/down nodes drm/dp: DPCD register defines for link status within ESI field Dominik Behr (1): dma-buf/sw_sync: force signal all unsignaled fences on dying timeline Fabio Estevam (2): drm/panel: simple: Skip error message on deferred probe drm/panel: simple: Remove unneeded gpiod NULL check Gabriel Krisman Bertazi (1): drm: Fi
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3)
== Series Details == Series: series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3) URL : https://patchwork.freedesktop.org/series/30543/ State : success == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2317 pass:1246 dwarn:2 dfail:0 fail:12 skip:1057 time:9551s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5768/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reorganize .disable hooks for pre-DDI DP
On Mon, Sep 18, 2017 at 01:45:50PM -0700, Rodrigo Vivi wrote:
> On Mon, Sep 18, 2017 at 05:31:28PM +, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Most of our DP encoder hooks are split into per-platform variants.
> > .disable() an exception, and thus it's a bit messy. Let's split it
> > up as well. We'll leave the common parts in a helper called by
> > each platform specific hook.
> >
> > There is a subtle change on VLV/CHV where we now disable PSR before
> > audio, whereas before we disabled PSR after audio. That should be
> > totally fine, and PSR is disabled by default anyway.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 44
> > +
> > 1 file changed, 36 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index d0ea9c4f87c8..dcdefd986569 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2692,23 +2692,46 @@ static void intel_disable_dp(struct intel_encoder
> > *encoder,
> > const struct drm_connector_state *old_conn_state)
> > {
> > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >
> > if (old_crtc_state->has_audio)
> > intel_audio_codec_disable(encoder);
> >
> > - intel_psr_disable(intel_dp, old_crtc_state);
> > -
> > /* Make sure the panel is off before trying to change the mode. But also
> > * ensure that we have vdd while we switch off the panel. */
> > intel_edp_panel_vdd_on(intel_dp);
> > intel_edp_backlight_off(old_conn_state);
> > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > intel_edp_panel_off(intel_dp);
> > +}
> > +
> > +static void g4x_disable_dp(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *old_crtc_state,
> > + const struct drm_connector_state *old_conn_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > +
> > + intel_disable_dp(encoder, old_crtc_state, old_conn_state);
> >
> > /* disable the port before the pipe on g4x */
> > - if (INTEL_GEN(dev_priv) < 5)
> > - intel_dp_link_down(intel_dp);
> > + intel_dp_link_down(intel_dp);
> > +}
> > +
> > +static void ilk_disable_dp(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *old_crtc_state,
> > + const struct drm_connector_state *old_conn_state)
> > +{
> > + intel_disable_dp(encoder, old_crtc_state, old_conn_state);
> > +}
> > +
> > +static void vlv_disable_dp(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *old_crtc_state,
> > + const struct drm_connector_state *old_conn_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > +
> > + intel_psr_disable(intel_dp, old_crtc_state);
>
> oh! not it makes sense...
> please move the that removal of !HAS_DDI from the first patch to this patch
> and feel free to ad my rv-b on both patches.
Updated patches pushed pushed to dinq. Thanks for the review.
>
> > +
> > + intel_disable_dp(encoder, old_crtc_state, old_conn_state);
> > }
> >
> > static void ilk_post_disable_dp(struct intel_encoder *encoder,
> > @@ -6144,7 +6167,6 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > goto err_encoder_init;
> >
> > intel_encoder->compute_config = intel_dp_compute_config;
> > - intel_encoder->disable = intel_disable_dp;
> > intel_encoder->get_hw_state = intel_dp_get_hw_state;
> > intel_encoder->get_config = intel_dp_get_config;
> > intel_encoder->suspend = intel_dp_encoder_suspend;
> > @@ -6152,18 +6174,24 @@ bool intel_dp_init(struct drm_i915_private
> > *dev_priv,
> > intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
> > intel_encoder->pre_enable = chv_pre_enable_dp;
> > intel_encoder->enable = vlv_enable_dp;
> > + intel_encoder->disable = vlv_disable_dp;
> > intel_encoder->post_disable = chv_post_disable_dp;
> > intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
> > } else if (IS_VALLEYVIEW(dev_priv)) {
> > intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
> > intel_encoder->pre_enable = vlv_pre_enable_dp;
> > intel_encoder->enable = vlv_enable_dp;
> > + intel_encoder->disable = vlv_disable_dp;
> > intel_encoder->post_disable = vlv_post_disable_dp;
> > + } else if (INTEL_GEN(dev_priv) >= 5) {
> > + intel_encoder->pre_enable = g4x_pre_enable_dp;
> > + intel_encoder->enable = g4x_enable_dp;
> > + intel_encoder->disable = ilk_disable_dp;
> > + intel_encoder->post_disable = ilk_post_disable_dp;
> > } else {
> >
[Intel-gfx] ✗ Fi.CI.BAT: warning for IGT PMU support (rev3)
== Series Details == Series: IGT PMU support (rev3) URL : https://patchwork.freedesktop.org/series/28253/ State : warning == Summary == IGT patchset tested on top of latest successful build 1043c09ccbcba8e5c2ec5f2a358a442346348bd8 tests/kms_cursor_legacy: Do not start collecting CRC after making FB busy with latest DRM-Tip kernel build CI_DRM_3113 ed7a99bf23ce drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest Test gem_exec_reloc: Subgroup basic-write-cpu: pass -> DMESG-WARN (fi-kbl-r) Subgroup basic-write-gtt: pass -> DMESG-WARN (fi-kbl-r) Subgroup basic-gtt-noreloc: pass -> DMESG-WARN (fi-kbl-r) Subgroup basic-write-gtt-noreloc: pass -> DMESG-WARN (fi-kbl-r) Subgroup basic-write-read-noreloc: pass -> DMESG-WARN (fi-kbl-r) Subgroup basic-cpu-active: pass -> DMESG-WARN (fi-kbl-r) Subgroup basic-write-gtt-active: pass -> DMESG-WARN (fi-kbl-r) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-kbl-r) fdo#102850 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-ivb-3520m) Subgroup force-edid: skip -> PASS (fi-ivb-3520m) Subgroup force-load-detect: skip -> PASS (fi-ivb-3520m) Subgroup prune-stale-modes: skip -> PASS (fi-ivb-3520m) Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (fi-glk-1) fdo#102777 +1 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:477s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:425s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:520s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:507s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:498s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:493s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:545s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:423s fi-glk-1 total:289 pass:258 dwarn:2 dfail:0 fail:0 skip:29 time:569s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:433s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:407s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:438s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:490s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:118 pass:100 dwarn:1 dfail:0 fail:0 skip:16 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s fi-kbl-r total:118 pass:90 dwarn:7 dfail:0 fail:0 skip:20 fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:544s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:451s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:753s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:501s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:479s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:573s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:419s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_232/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests/kms_cursor_legacy: Use gem_mmap__gtt() rather than gem_mmap__wc()
From: Ville Syrjälä WC mmaps aren't universally supported, so let's not depend on them when any kind of mmap will do. Signed-off-by: Ville Syrjälä --- tests/kms_cursor_legacy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_cursor_legacy.c b/tests/kms_cursor_legacy.c index 1aa4518c361c..9c63fb1944d2 100644 --- a/tests/kms_cursor_legacy.c +++ b/tests/kms_cursor_legacy.c @@ -506,7 +506,7 @@ static uint32_t *make_busy(int fd, uint32_t target) memset(obj, 0, sizeof(obj)); obj[0].handle = target; obj[1].handle = gem_create(fd, 4096); - batch = gem_mmap__wc(fd, obj[1].handle, 0, 4096, PROT_WRITE); + batch = gem_mmap__gtt(fd, obj[1].handle, 4096, PROT_WRITE); gem_set_domain(fd, obj[1].handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] scripts/run-tests.sh: Look for test-lists.txt in 'build' as well
From: Ville Syrjälä Meson always uses a separate build directotry. Adjust the assumptions in run-tests.sh to work in that environment. For now I'll just hardcode it to look for a directly called 'build'. I suppose we might want to let the user pass that in, but for now I can't be bothered to do that. Signed-off-by: Ville Syrjälä --- scripts/run-tests.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/run-tests.sh b/scripts/run-tests.sh index a28dd8760a63..11e65d492fa1 100755 --- a/scripts/run-tests.sh +++ b/scripts/run-tests.sh @@ -34,6 +34,8 @@ if [ ! -d "$IGT_TEST_ROOT" ]; then exit 1 fi +[ -f "$IGT_TEST_ROOT/test-list.txt" ] || IGT_TEST_ROOT="$ROOT/build/tests" + if [ ! -f "$IGT_TEST_ROOT/test-list.txt" ]; then echo "Error: test list not found." echo "Please run make in the tests directory to generate the test list." -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Support for more than two execlist ports (rev2)
== Series Details == Series: Support for more than two execlist ports (rev2) URL : https://patchwork.freedesktop.org/series/30183/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2317 pass:1245 dwarn:2 dfail:0 fail:13 skip:1057 time:9584s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5766/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 2/3] meson: align test-list.txt generation with automake
On Fri, Sep 08, 2017 at 05:14:47PM +0200, Daniel Vetter wrote: > - I forgot the chamelium tests > - Order tests the same way in both build systems. Since testdisplay is > special, it's easier to put that at the end in meson, so adjusted > automake to suit. > > With this you can diff the 2 test lists and end up with 0 differences, > which will be useful to CI meson vs. automake. > > Signed-off-by: Daniel Vetter I needed an actually working test-list.txt (run-tests.sh didn't like what were producing previously) so I've gone pushed this. I also pushed patch 3/3 since it looked all right to me. There were a few rebase conflicts but nothing major. > --- > tests/Makefile.am | 1 + > tests/Makefile.sources | 2 -- > tests/generate_testlist.sh | 9 +++-- > tests/meson.build | 20 ++-- > 4 files changed, 22 insertions(+), 10 deletions(-) > > diff --git a/tests/Makefile.am b/tests/Makefile.am > index 8c70f6f1aa35..39ca3960355c 100644 > --- a/tests/Makefile.am > +++ b/tests/Makefile.am > @@ -26,6 +26,7 @@ TESTS_progs += \ > $(NULL) > endif > > +TESTS_progs += testdisplay > > if BUILD_TESTS > test-list.txt: Makefile.sources > diff --git a/tests/Makefile.sources b/tests/Makefile.sources > index 0f4e39af10a1..caec5486e49f 100644 > --- a/tests/Makefile.sources > +++ b/tests/Makefile.sources > @@ -281,8 +281,6 @@ testdisplay_SOURCES = \ > testdisplay_hotplug.c \ > $(NULL) > > -TESTS_progs += testdisplay > - > check_SCRIPTS = igt_command_line.sh \ > $(NULL) > > diff --git a/tests/generate_testlist.sh b/tests/generate_testlist.sh > index 6ea78655daca..e3cb87f98842 100755 > --- a/tests/generate_testlist.sh > +++ b/tests/generate_testlist.sh > @@ -2,9 +2,14 @@ > > echo TESTLIST > $MESON_BUILD_ROOT/tests/test-list.txt > > +if [[ $# -gt 0 ]] ; then > + echo -n $1 >> $MESON_BUILD_ROOT/tests/test-list.txt > + shift > +fi > + > while [[ $# -gt 0 ]] ; do > - echo $1 >> $MESON_BUILD_ROOT/tests/test-list.txt > + echo -n " $1" >> $MESON_BUILD_ROOT/tests/test-list.txt > shift > done > > -echo END TESTLIST >> $MESON_BUILD_ROOT/tests/test-list.txt > +echo -e "\nEND TESTLIST" >> $MESON_BUILD_ROOT/tests/test-list.txt > diff --git a/tests/meson.build b/tests/meson.build > index 4dd5a9c9d4c7..1a323f7c51d6 100644 > --- a/tests/meson.build > +++ b/tests/meson.build > @@ -218,6 +218,17 @@ test_progs = [ > ] > > test_deps = [ igt_deps ] > + > +if libdrm_amdgpu.found() > + # FIXME meson/ninja really doesn't like build targets with paths in them > + test_progs += [ > + 'amdgpu/amd_basic', > + 'amdgpu/amd_cs_nop', > + 'amdgpu/amd_prime', > + ] > + test_deps += libdrm_amdgpu > +endif > + > if libdrm_nouveau.found() > test_progs += [ > 'prime_nv_api', > @@ -238,14 +249,11 @@ if libdrm_vc4.found() > test_deps += libdrm_vc4 > endif > > -if libdrm_amdgpu.found() > - # FIXME meson/ninja really doesn't like build targets with paths in them > +if chamelium.found() > test_progs += [ > - 'amdgpu/amd_basic', > - 'amdgpu/amd_cs_nop', > - 'amdgpu/amd_prime', > + 'chamelium', > ] > - test_deps += libdrm_amdgpu > + test_deps += chamelium > endif > > if alsa.found() and gsl.found() > -- > 2.14.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for i915 PMU and engine busy stats (rev11)
== Series Details == Series: i915 PMU and engine busy stats (rev11) URL : https://patchwork.freedesktop.org/series/27488/ State : warning == Summary == Series 27488v11 i915 PMU and engine busy stats https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/11/mbox/ Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Subgroup hdmi-crc-fast: pass -> DMESG-WARN (fi-skl-6700k) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-ivb-3520m) Subgroup force-edid: skip -> PASS (fi-ivb-3520m) Subgroup force-load-detect: skip -> PASS (fi-ivb-3520m) Subgroup prune-stale-modes: skip -> PASS (fi-ivb-3520m) Test kms_frontbuffer_tracking: Subgroup basic: pass -> DMESG-WARN (fi-bdw-5557u) fdo#102473 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fi-bdw-5557u total:289 pass:267 dwarn:1 dfail:0 fail:0 skip:21 time:437s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:473s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:416s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:514s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:498s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:489s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:482s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:545s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:565s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:404s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:478s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:461s fi-kbl-7500u total:118 pass:99 dwarn:1 dfail:0 fail:1 skip:16 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:542s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:449s fi-skl-6700k total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:750s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:488s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:480s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:562s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:415s ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest d36bbe6311d5 drm/i915: Gate engine stats collection with a static key 1673147befe1 drm/i915/pmu: Wire up engine busy stats to PMU 034aa97921b4 drm/i915: Engine busy time tracking 99ed43be4f06 drm/i915: Wrap context schedule notification b357130dbdb3 drm/i915/pmu: Suspend sampling when GPU is idle ca3894412465 drm/i915/pmu: Expose a PMU interface for perf queries f9d3637a269a drm/i915: Extract intel_get_cagf 88319bdc951c drm/i915: Convert intel_rc6_residency_us to ns == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5769/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 i-g-t 5/5] tests/perf_pmu: Tests for i915 PMU API
From: Tvrtko Ursulin
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and
all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Dmitry Rogozhkin
---
lib/igt_gt.c | 50 +++
lib/igt_gt.h | 38 +++
lib/igt_perf.h | 9 +-
tests/Makefile.sources | 1 +
tests/perf_pmu.c | 840 +
5 files changed, 930 insertions(+), 8 deletions(-)
create mode 100644 tests/perf_pmu.c
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b3809eee..4c75811fb1b3 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -568,3 +568,53 @@ bool gem_can_store_dword(int fd, unsigned int engine)
return true;
}
+
+const struct intel_execution_engine2 intel_execution_engines2[] = {
+ { "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
+ { "bcs0", I915_ENGINE_CLASS_COPY, 0 },
+ { "vcs0", I915_ENGINE_CLASS_VIDEO, 0 },
+ { "vcs1", I915_ENGINE_CLASS_VIDEO, 1 },
+ { "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0 },
+};
+
+unsigned int
+gem_class_instance_to_eb_flags(int gem_fd,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance)
+{
+ if (class != I915_ENGINE_CLASS_VIDEO)
+ igt_assert(instance == 0);
+ else
+ igt_assert(instance >= 0 && instance <= 1);
+
+ switch (class) {
+ case I915_ENGINE_CLASS_RENDER:
+ return I915_EXEC_RENDER;
+ case I915_ENGINE_CLASS_COPY:
+ return I915_EXEC_BLT;
+ case I915_ENGINE_CLASS_VIDEO:
+ if (instance == 0) {
+ if (gem_has_bsd2(gem_fd))
+ return I915_EXEC_BSD | I915_EXEC_BSD_RING1;
+ else
+ return I915_EXEC_BSD;
+
+ } else {
+ return I915_EXEC_BSD | I915_EXEC_BSD_RING2;
+ }
+ case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ return I915_EXEC_VEBOX;
+ case I915_ENGINE_CLASS_OTHER:
+ default:
+ igt_assert(0);
+ };
+}
+
+bool gem_has_engine(int gem_fd,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance)
+{
+ return gem_has_ring(gem_fd,
+ gem_class_instance_to_eb_flags(gem_fd, class,
+ instance));
+}
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 2579cbd37be7..fb67ae1a7d1f 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -25,6 +25,7 @@
#define IGT_GT_H
#include "igt_debugfs.h"
+#include "igt_core.h"
void igt_require_hang_ring(int fd, int ring);
@@ -80,4 +81,41 @@ extern const struct intel_execution_engine {
bool gem_can_store_dword(int fd, unsigned int engine);
+extern const struct intel_execution_engine2 {
+ const char *name;
+ int class;
+ int instance;
+} intel_execution_engines2[];
+
+#define for_each_engine_class_instance(fd__, e__) \
+ for ((e__) = intel_execution_engines2;\
+(e__)->name; \
+(e__)++)
+
+enum drm_i915_gem_engine_class {
+ I915_ENGINE_CLASS_OTHER = 0,
+ I915_ENGINE_CLASS_RENDER = 1,
+ I915_ENGINE_CLASS_COPY = 2,
+ I915_ENGINE_CLASS_VIDEO = 3,
+ I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+ I915_ENGINE_CLASS_MAX /* non-ABI */
+};
+
+unsigned int
+gem_class_instance_to_eb_flags(int gem_fd,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance);
+
+bool gem_has_engine(int gem_fd,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance);
+
+static inline
+void gem_require_engine(int gem_fd,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance)
+{
+ igt_require(gem_has_engine(gem_fd, class, instance));
+}
+
#endif /* IGT_GT_H */
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e29216f0500a..d64e0bd7a06a 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -29,14 +29,7 @@
#include
-enum drm_i915_gem_engine_class {
- I915_ENGINE_CLASS_OTHER
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3)
== Series Details == Series: series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3) URL : https://patchwork.freedesktop.org/series/30543/ State : success == Summary == Series 30543v3 series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check https://patchwork.freedesktop.org/api/1.0/series/30543/revisions/3/mbox/ Test gem_exec_suspend: Subgroup basic-s3: incomplete -> PASS (fi-kbl-7500u) fdo#102850 +1 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-ivb-3520m) Subgroup force-edid: skip -> PASS (fi-ivb-3520m) Subgroup force-load-detect: skip -> PASS (fi-ivb-3520m) Subgroup prune-stale-modes: skip -> PASS (fi-ivb-3520m) fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:467s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:419s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:528s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:284s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:489s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:494s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:543s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:418s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:563s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:490s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:464s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:482s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:572s fi-kbl-r total:118 pass:97 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:457s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:473s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:422s fi-pnv-d510 failed to connect after reboot ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest b830aa113ed4 drm/i915: Reorganize .disable hooks for pre-DDI DP 9fb36cda67cb drm/i915: Drop useless HAS_PSR() check == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5768/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 3/8] drm/i915/pmu: Expose a PMU interface for perf queries
From: Tvrtko Ursulin From: Chris Wilson From: Tvrtko Ursulin From: Dmitry Rogozhkin The first goal is to be able to measure GPU (and invidual ring) busyness without having to poll registers from userspace. (Which not only incurs holding the forcewake lock indefinitely, perturbing the system, but also runs the risk of hanging the machine.) As an alternative we can use the perf event counter interface to sample the ring registers periodically and send those results to userspace. To be able to do so, we need to export the two symbols from kernel/events/core.c to register and unregister a PMU device. v1-v2 (Chris Wilson): v2: Use a common timer for the ring sampling. v3: (Tvrtko Ursulin) * Decouple uAPI from i915 engine ids. * Complete uAPI defines. * Refactor some code to helpers for clarity. * Skip sampling disabled engines. * Expose counters in sysfs. * Pass in fake regs to avoid null ptr deref in perf core. * Convert to class/instance uAPI. * Use shared driver code for rc6 residency, power and frequency. v4: (Dmitry Rogozhkin) * Register PMU with .task_ctx_nr=perf_invalid_context * Expose cpumask for the PMU with the single CPU in the mask * Properly support pmu->stop(): it should call pmu->read() * Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE) * Introduce refcounting of event subscriptions. * Make pmu.busy_stats a refcounter to avoid busy stats going away with some deleted event. * Expose cpumask for i915 PMU to avoid multiple events creation of the same type followed by counter aggregation by perf-stat. * Track CPUs getting online/offline to migrate perf context. If (likely) cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be needed to see effect of CPU status tracking. * End result is that only global events are supported and perf stat works correctly. * Deny perf driver level sampling - it is prohibited for uncore PMU. v5: (Tvrtko Ursulin) * Don't hardcode number of engine samplers. * Rewrite event ref-counting for correctness and simplicity. * Store initial counter value when starting already enabled events to correctly report values to all listeners. * Fix RC6 residency readout. * Comments, GPL header. v6: * Add missing entry to v4 changelog. * Fix accounting in CPU hotplug case by copying the approach from arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin) v7: * Log failure message only on failure. * Remove CPU hotplug notification state on unregister. v8: * Fix error unwind on failed registration. * Checkpatch cleanup. v9: * Drop the energy metric, it is available via intel_rapl_perf. (Ville Syrjälä) * Use HAS_RC6(p). (Chris Wilson) * Handle unsupported non-engine events. (Dmitry Rogozhkin) * Rebase for intel_rc6_residency_ns needing caller managed runtime pm. * Drop HAS_RC6 checks from the read callback since creating those events will be rejected at init time already. * Add counter units to sysfs so perf stat output is nicer. * Cleanup the attribute tables for brevity and readability. v10: * Fixed queued accounting. Signed-off-by: Chris Wilson Signed-off-by: Tvrtko Ursulin Signed-off-by: Dmitry Rogozhkin Cc: Tvrtko Ursulin Cc: Chris Wilson Cc: Dmitry Rogozhkin Cc: Peter Zijlstra --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 78 drivers/gpu/drm/i915/i915_pmu.c | 707 drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_engine_cs.c | 10 + drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 25 ++ include/uapi/drm/i915_drm.h | 57 +++ 9 files changed, 908 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_pmu.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5182e3d5557d..5c6013961b3b 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -26,6 +26,7 @@ i915-y := i915_drv.o \ i915-$(CONFIG_COMPAT) += i915_ioc32.o i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o +i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o # GEM code i915-y += i915_cmd_parser.o \ diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5c111ea96e80..b1f96eb1be16 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1196,6 +1196,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) struct drm_device *dev = &dev_priv->drm; i915_gem_shrinker_init(dev_priv); + i915_pmu_register(dev_priv); /* * Notify a valid surface after modesetting, @@ -1250,6 +1251,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) intel_opregion_unregister(dev_priv); i915_perf_unregister(dev_priv); + i915_pmu_unregister(dev_priv); i915_teardown_
[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/dp: Add defines for latency in sink
== Series Details == Series: series starting with [1/2] drm/dp: Add defines for latency in sink URL : https://patchwork.freedesktop.org/series/30658/ State : warning == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 +1 Test kms_plane: Subgroup plane-panning-bottom-right-suspend-pipe-A-planes: pass -> DMESG-WARN (shard-hsw) fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2317 pass:1244 dwarn:3 dfail:0 fail:13 skip:1057 time:9583s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5765/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Eliminate DDI encoder->type frobbery redux (rev2)
On Wed, Sep 20, 2017 at 03:40:06PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Eliminate DDI encoder->type frobbery redux (rev2) > URL : https://patchwork.freedesktop.org/series/30548/ > State : failure > > == Summary == > > Series 30548v2 drm/i915: Eliminate DDI encoder->type frobbery redux > https://patchwork.freedesktop.org/api/1.0/series/30548/revisions/2/mbox/ > > Test chamelium: > Subgroup dp-crc-fast: > pass -> FAIL (fi-kbl-7500u) fdo#102514 > Test gem_exec_suspend: > Subgroup basic-s3: > pass -> INCOMPLETE (fi-bxt-j4205) > pass -> INCOMPLETE (fi-glk-1) 3 out of 3. I guess I'll have to believe that there's a real problem somewhere :( -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Eliminate DDI encoder->type frobbery redux (rev2)
== Series Details == Series: drm/i915: Eliminate DDI encoder->type frobbery redux (rev2) URL : https://patchwork.freedesktop.org/series/30548/ State : failure == Summary == Series 30548v2 drm/i915: Eliminate DDI encoder->type frobbery redux https://patchwork.freedesktop.org/api/1.0/series/30548/revisions/2/mbox/ Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-bxt-j4205) incomplete -> PASS (fi-kbl-7500u) fdo#102850 pass -> INCOMPLETE (fi-glk-1) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 +1 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-ivb-3520m) Subgroup force-edid: skip -> PASS (fi-ivb-3520m) Subgroup force-load-detect: skip -> PASS (fi-ivb-3520m) Subgroup prune-stale-modes: skip -> PASS (fi-ivb-3520m) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: pass -> INCOMPLETE (fi-kbl-r) Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:470s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:421s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:508s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:118 pass:97 dwarn:0 dfail:0 fail:0 skip:20 fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:489s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:491s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:544s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-glk-1 total:118 pass:96 dwarn:0 dfail:0 fail:0 skip:21 fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:407s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:498s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:465s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:456s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s fi-kbl-r total:247 pass:222 dwarn:0 dfail:0 fail:0 skip:24 fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:552s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:454s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:752s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:485s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:562s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:419s ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest 890d6dc6b2aa drm/i915: Pass a crtc state to ddi post_disable from MST code 7b7455924657 drm/i915: Replace most intel_ddi_get_encoder_port() alls with encoder->port 978b911cca2d drm/i915: Clear up the types we use for DDI buf trans level/n_entries fb971aa20d2a drm/i915: Unify error handling for missing DDI buf trans tables 694adc37f601 drm/i915: Stop frobbing with DDI encoder->type eb1e0a33a9cf drm/i915: Centralize the SKL DDI A/E vs. B/C/D buf trans handling e381f6681ece drm/i915: Stop using encoder->type in intel_ddi_enable_transcoder_func() b55f585b033b drm/i915: Start using output_types for DPLL selection b22c723225d8 drm/i915: Pass crtc state to intel_prepare_dp_ddi_buffers() e6166993c1a5 drm/i915: Don't use encoder->type in intel_ddi_set_pipe_settings() fb0aac2a617e drm/i915: Kill off the BXT buf_trans default_index c5c8d13588ba drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitly 80c0dd1f3c9a drm/i915: Integrate BXT into intel_ddi_dp_voltage_max() 0
[Intel-gfx] ✓ Fi.CI.BAT: success for Support for more than two execlist ports (rev2)
== Series Details == Series: Support for more than two execlist ports (rev2) URL : https://patchwork.freedesktop.org/series/30183/ State : success == Summary == Series 30183v2 Support for more than two execlist ports https://patchwork.freedesktop.org/api/1.0/series/30183/revisions/2/mbox/ Test gem_exec_suspend: Subgroup basic-s3: incomplete -> PASS (fi-kbl-7500u) fdo#102850 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-ivb-3520m) Subgroup force-edid: skip -> PASS (fi-ivb-3520m) Subgroup force-load-detect: skip -> PASS (fi-ivb-3520m) Subgroup prune-stale-modes: skip -> PASS (fi-ivb-3520m) Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (fi-glk-1) fdo#102777 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:427s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:531s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:498s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:495s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:492s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:540s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:425s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:566s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:407s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:477s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:461s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:473s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:588s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:542s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:446s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:490s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:560s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:413s ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest 03b7a2df3fd1 drm/i915: Improve GuC request coalescing 582ba31b7a9f drm/i915: Keep track of reserved execlist ports 02b6dae25461 drm/i915: Introduce execlist_port_* accessors 202cc6c2b792 drm/i915: Make execlist port count variable 3853e558bdd7 drm/i915: Add execlist_port_complete 9dd456d33cc9 drm/i915: Wrap port cancellation into a function 830307905e9c drm/i915: Move execlist initialization into intel_engine_cs.c 791be2cd0de1 drm/i915: Make own struct for execlist items == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5766/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
> On Sep 20, 2017, at 7:33 AM, Nagaraju, Vathsala
> wrote:
>
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> Cc: Rodrigo Vivi
> CC: Puthikorn Voravootivat
> Signed-off-by: Vathsala Nagaraju
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
>uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>uint32_t val;
> +uint8_t sink_latency;
>
>val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
>val |= EDP_PSR2_ENABLE |
> -EDP_SU_TRACK_ENABLE |
> -EDP_FRAMES_BEFORE_SU_ENTRY;
Please also remove the definition of this su_entry since it was not following
the new standards anyway...
Probably good to replace with function macro style for better use below...
> +EDP_SU_TRACK_ENABLE;
> +
> +if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> +&sink_latency)) {
> +sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> +val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
... so you could use
val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency +1);
> +} else {
> +val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> +}
>
>if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
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[Intel-gfx] [PATCH v2 2/2] drm/i915: Reorganize .disable hooks for pre-DDI DP
From: Ville Syrjälä
Most of our DP encoder hooks are split into per-platform variants.
.disable() an exception, and thus it's a bit messy. Let's split it
up as well. We'll leave the common parts in a helper called by
each platform specific hook. Now each platform has mostly its own
hooks. Some hooks are still shared between vlv and chv, and between
g4x and ilk. None of the remaining shared hooks have any platform
checks in them however so duplicating them doesn't seem particularly
useful.
There is a subtle change on VLV/CHV where we now disable PSR before
audio, whereas before we disabled PSR after audio. That should be
totally fine, and PSR is disabled by default anyway. Jani also pointed
out to me that PSR + audio doesn't seem like a particularly realistic
combination.
v2: Drop the PSR HAS_DDI check here (Rodrigo)
Pimp up the commit message a bit based on a chat with Jani
Cc: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 45 -
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e536f5942d7f..1e0bfbe6b4f3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2692,24 +2692,46 @@ static void intel_disable_dp(struct intel_encoder
*encoder,
const struct drm_connector_state *old_conn_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (old_crtc_state->has_audio)
intel_audio_codec_disable(encoder);
- if (!HAS_DDI(dev_priv))
- intel_psr_disable(intel_dp, old_crtc_state);
-
/* Make sure the panel is off before trying to change the mode. But also
* ensure that we have vdd while we switch off the panel. */
intel_edp_panel_vdd_on(intel_dp);
intel_edp_backlight_off(old_conn_state);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
intel_edp_panel_off(intel_dp);
+}
+
+static void g4x_disable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ intel_disable_dp(encoder, old_crtc_state, old_conn_state);
/* disable the port before the pipe on g4x */
- if (INTEL_GEN(dev_priv) < 5)
- intel_dp_link_down(intel_dp);
+ intel_dp_link_down(intel_dp);
+}
+
+static void ilk_disable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
+{
+ intel_disable_dp(encoder, old_crtc_state, old_conn_state);
+}
+
+static void vlv_disable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ intel_psr_disable(intel_dp, old_crtc_state);
+
+ intel_disable_dp(encoder, old_crtc_state, old_conn_state);
}
static void ilk_post_disable_dp(struct intel_encoder *encoder,
@@ -6145,7 +6167,6 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
goto err_encoder_init;
intel_encoder->compute_config = intel_dp_compute_config;
- intel_encoder->disable = intel_disable_dp;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
intel_encoder->suspend = intel_dp_encoder_suspend;
@@ -6153,18 +6174,24 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
intel_encoder->pre_enable = chv_pre_enable_dp;
intel_encoder->enable = vlv_enable_dp;
+ intel_encoder->disable = vlv_disable_dp;
intel_encoder->post_disable = chv_post_disable_dp;
intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
} else if (IS_VALLEYVIEW(dev_priv)) {
intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
intel_encoder->pre_enable = vlv_pre_enable_dp;
intel_encoder->enable = vlv_enable_dp;
+ intel_encoder->disable = vlv_disable_dp;
intel_encoder->post_disable = vlv_post_disable_dp;
+ } else if (INTEL_GEN(dev_priv) >= 5) {
+ intel_encoder->pre_enable = g4x_pre_enable_dp;
+ intel_encoder->enable = g4x_enable_dp;
+ intel_encoder->disable = ilk_disable_dp;
+ intel_encoder->post_disable = ilk_post_disable_dp;
} else {
intel_enc
[Intel-gfx] [PATCH v2 1/2] drm/i915: Drop useless HAS_PSR() check
From: Ville Syrjälä It is safe to call intel_psr_disable() on a platform without PSR. We don't have such a check when calling intel_psr_enable() either. v2: Don't drop the HAS_DDI check quite yet (Rodrigo) Reviewed-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8db6b11f103f..e536f5942d7f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2697,7 +2697,7 @@ static void intel_disable_dp(struct intel_encoder *encoder, if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder); - if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) + if (!HAS_DDI(dev_priv)) intel_psr_disable(intel_dp, old_crtc_state); /* Make sure the panel is off before trying to change the mode. But also -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink
== Series Details == Series: series starting with [1/2] drm/dp: Add defines for latency in sink URL : https://patchwork.freedesktop.org/series/30658/ State : success == Summary == Series 30658v1 series starting with [1/2] drm/dp: Add defines for latency in sink https://patchwork.freedesktop.org/api/1.0/series/30658/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: incomplete -> PASS (fi-kbl-7500u) fdo#102850 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-ivb-3520m) Subgroup force-edid: skip -> PASS (fi-ivb-3520m) Subgroup force-load-detect: skip -> PASS (fi-ivb-3520m) Subgroup prune-stale-modes: skip -> PASS (fi-ivb-3520m) Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:469s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:420s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:515s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:502s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:488s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:493s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:548s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:425s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:568s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:423s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:484s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:467s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:475s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:568s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:540s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:441s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:411s ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest 8dc01494eee9 drm/i915/psr: Set frames before SU entry for psr2 568cf132cf88 drm/dp: Add defines for latency in sink == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5765/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
On Wed, Sep 20, 2017 at 08:02:35PM +0530, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> Cc: Rodrigo Vivi
> CC: Puthikorn Voravootivat
> Signed-off-by: Vathsala Nagaraju
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>*/
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>* mesh at all with our frontbuffer tracking. And the hw alone isn't
>* good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency)) {
== 1
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> + val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
> + } else {
> + val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> + }
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH 3/8] drm/i915: Wrap port cancellation into a function
On reset and wedged path, we want to release the requests
that are tied to ports and then mark the ports to be unset.
Introduce a function for this.
v2: rebase
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a4ece4c4f291..ffb9c900328b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -568,6 +568,16 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists_submit_ports(engine);
}
+static void execlist_cancel_port_requests(struct intel_engine_execlist *el)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(el->port); i++)
+ i915_gem_request_put(port_request(&el->port[i]));
+
+ memset(el->port, 0, sizeof(el->port));
+}
+
static void execlists_cancel_requests(struct intel_engine_cs *engine)
{
struct intel_engine_execlist * const el = &engine->execlist;
@@ -575,14 +585,11 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
struct drm_i915_gem_request *rq, *rn;
struct rb_node *rb;
unsigned long flags;
- unsigned long n;
spin_lock_irqsave(&engine->timeline->lock, flags);
/* Cancel the requests on the HW and clear the ELSP tracker. */
- for (n = 0; n < ARRAY_SIZE(el->port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(el->port, 0, sizeof(el->port));
+ execlist_cancel_port_requests(el);
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->timeline->requests, link) {
@@ -1372,11 +1379,9 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
struct drm_i915_gem_request *request)
{
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = el->port;
struct drm_i915_gem_request *rq, *rn;
struct intel_context *ce;
unsigned long flags;
- unsigned int n;
spin_lock_irqsave(&engine->timeline->lock, flags);
@@ -1389,9 +1394,7 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
* guessing the missed context-switch events by looking at what
* requests were completed.
*/
- for (n = 0; n < ARRAY_SIZE(el->port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(el->port, 0, sizeof(el->port));
+ execlist_cancel_port_requests(el);
/* Push back any incomplete requests for replay after the reset. */
list_for_each_entry_safe_reverse(rq, rn,
--
2.11.0
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[Intel-gfx] [PATCH 7/8] drm/i915: Keep track of reserved execlist ports
To further enchance port processing, keep track of
reserved ports. This way we can iterate only the used subset
of port space. Note that we lift the responsibility of
execlists_submit_request() to inspect hw availability and
always do dequeuing. This is to ensure that only the irq
handler will be responsible for keeping track of available ports.
v2: rebase, comment fix, READ_ONCE only outside of irq handler (Chris)
Cc: Chris Wilson
Cc: Michał Winiarski
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_guc_submission.c | 51 +
drivers/gpu/drm/i915/i915_irq.c| 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 7 ++-
drivers/gpu/drm/i915/intel_lrc.c | 90 ++
drivers/gpu/drm/i915/intel_ringbuffer.h| 55 +-
5 files changed, 129 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 25c9bac94c39..359f57a59cba 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -487,7 +487,7 @@ static void guc_ring_doorbell(struct i915_guc_client
*client)
* @engine: engine associated with the commands
*
* The only error here arises if the doorbell hardware isn't functioning
- * as expected, which really shouln't happen.
+ * as expected, which really shouldn't happen.
*/
static void i915_guc_submit(struct intel_engine_cs *engine)
{
@@ -495,17 +495,19 @@ static void i915_guc_submit(struct intel_engine_cs
*engine)
struct intel_guc *guc = &dev_priv->guc;
struct i915_guc_client *client = guc->execbuf_client;
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = el->port;
const unsigned int engine_id = engine->id;
unsigned int n;
- for (n = 0; n < ARRAY_SIZE(el->port); n++) {
+ for (n = 0; n < execlist_active_ports(el); n++) {
+ struct execlist_port *port;
struct drm_i915_gem_request *rq;
unsigned int count;
- rq = port_unpack(&port[n], &count);
+ port = execlist_port_index(el, n);
+
+ rq = port_unpack(port, &count);
if (rq && count == 0) {
- port_set(&port[n], port_pack(rq, ++count));
+ port_set(port, port_pack(rq, ++count));
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -560,25 +562,27 @@ static void port_assign(struct execlist_port *port,
static void i915_guc_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = el->port;
+ struct execlist_port *port;
struct drm_i915_gem_request *last = NULL;
- const struct execlist_port * const last_port = execlist_port_tail(el);
bool submit = false;
struct rb_node *rb;
- if (port_isset(port))
- port++;
-
spin_lock_irq(&engine->timeline->lock);
rb = el->first;
GEM_BUG_ON(rb_first(&el->queue) != rb);
- while (rb) {
+
+ if (unlikely(!rb))
+ goto done;
+
+ port = execlist_request_port(el);
+
+ do {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
struct drm_i915_gem_request *rq, *rn;
list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
if (last && rq->ctx != last->ctx) {
- if (port == last_port) {
+ if (!execlist_inactive_ports(el)) {
__list_del_many(&p->requests,
&rq->priotree.link);
goto done;
@@ -587,7 +591,8 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
if (submit)
port_assign(port, last);
- port = execlist_port_next(el, port);
+ port = execlist_request_port(el);
+ GEM_BUG_ON(port_isset(port));
}
INIT_LIST_HEAD(&rq->priotree.link);
@@ -604,7 +609,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
INIT_LIST_HEAD(&p->requests);
if (p->priority != I915_PRIORITY_NORMAL)
kmem_cache_free(engine->i915->priorities, p);
- }
+ } while (rb);
done:
el->first = rb;
if (submit) {
@@ -618,21 +623,21 @@ static void i915_guc_irq_handler(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
struct intel_engine_execlist * const el = &engine->execlist;
[Intel-gfx] [PATCH 5/8] drm/i915: Make execlist port count variable
As we emulate execlists on top of the GuC workqueue, it is not
restricted to just 2 ports and we can increase that number arbitrarily
to trade-off queue depth (i.e. scheduling latency) against pipeline
bubbles.
v2: rebase. better commit msg (Chris)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c| 8
drivers/gpu/drm/i915/i915_drv.h| 3 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 17 -
drivers/gpu/drm/i915/i915_guc_submission.c | 8 ++--
drivers/gpu/drm/i915/intel_engine_cs.c | 4
drivers/gpu/drm/i915/intel_lrc.c | 6 --
drivers/gpu/drm/i915/intel_ringbuffer.h| 21 +
7 files changed, 49 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7648ff207670..dbeb6f08ab79 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3313,6 +3313,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
if (i915.enable_execlists) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ struct intel_engine_execlist * const el =
&engine->execlist;
u32 ptr, read, write;
unsigned int idx;
@@ -3346,11 +3347,10 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- for (idx = 0; idx < ARRAY_SIZE(engine->execlist.port);
idx++) {
+ for (idx = 0; idx < execlist_num_ports(el); idx++) {
unsigned int count;
- rq = port_unpack(&engine->execlist.port[idx],
-&count);
+ rq = port_unpack(&el->port[idx], &count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
idx, count);
@@ -3363,7 +3363,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_unlock();
spin_lock_irq(&engine->timeline->lock);
- for (rb = engine->execlist.first; rb; rb = rb_next(rb))
{
+ for (rb = el->first; rb; rb = rb_next(rb)) {
struct i915_priolist *p =
rb_entry(rb, typeof(*p), node);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6d7d871b32ad..f4dd53eef61b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1000,7 +1000,8 @@ struct i915_gpu_state {
u32 seqno;
u32 head;
u32 tail;
- } *requests, execlist[2];
+ } *requests, execlist[EXECLIST_MAX_PORTS];
+ unsigned int num_ports;
struct drm_i915_error_waiter {
char comm[TASK_COMM_LEN];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 8710fbdbbcb1..0a803d76256b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -396,6 +396,8 @@ static void error_print_context(struct
drm_i915_error_state_buf *m,
static void error_print_engine(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ int n;
+
err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
err_printf(m, " START: 0x%08x\n", ee->start);
err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
@@ -465,8 +467,11 @@ static void error_print_engine(struct
drm_i915_error_state_buf *m,
jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
err_printf(m, " engine reset count: %u\n", ee->reset_count);
- error_print_request(m, " ELSP[0]: ", &ee->execlist[0]);
- error_print_request(m, " ELSP[1]: ", &ee->execlist[1]);
+ for (n = 0; n < ee->num_ports; n++) {
+ err_printf(m, " ELSP[%d]:", n);
+ error_print_request(m, " ", &ee->execlist[n]);
+ }
+
error_print_context(m, " Active context: ", &ee->context);
}
@@ -1327,17 +1332,19 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
static void error_record_engine_execlists(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
{
- const struct execlist_port *port = engine->execlist.port;
+ const struct intel_engine_execlist * const el = &engine->execlist;
unsigned int n;
- for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++) {
- struct drm_i915
[Intel-gfx] [PATCH 8/8] drm/i915: Improve GuC request coalescing
Now that we can keep track of what ports we have
dequeued, coalesce only those ports instead of iterating
through all ports.
Cc: Michał Winiarski
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_guc_submission.c | 31 +-
drivers/gpu/drm/i915/intel_ringbuffer.h| 9 +
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 359f57a59cba..1057a0fb9f27 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -485,11 +485,13 @@ static void guc_ring_doorbell(struct i915_guc_client
*client)
/**
* i915_guc_submit() - Submit commands through GuC
* @engine: engine associated with the commands
+ * @first: index of first execlist port to start coalescing from
*
* The only error here arises if the doorbell hardware isn't functioning
* as expected, which really shouldn't happen.
*/
-static void i915_guc_submit(struct intel_engine_cs *engine)
+static void i915_guc_submit(struct intel_engine_cs *engine,
+ const unsigned int first)
{
struct drm_i915_private *dev_priv = engine->i915;
struct intel_guc *guc = &dev_priv->guc;
@@ -498,7 +500,7 @@ static void i915_guc_submit(struct intel_engine_cs *engine)
const unsigned int engine_id = engine->id;
unsigned int n;
- for (n = 0; n < execlist_active_ports(el); n++) {
+ for (n = first; n < execlist_active_ports(el); n++) {
struct execlist_port *port;
struct drm_i915_gem_request *rq;
unsigned int count;
@@ -506,21 +508,22 @@ static void i915_guc_submit(struct intel_engine_cs
*engine)
port = execlist_port_index(el, n);
rq = port_unpack(port, &count);
- if (rq && count == 0) {
- port_set(port, port_pack(rq, ++count));
+ GEM_BUG_ON(!rq);
+ GEM_BUG_ON(count);
- if (i915_vma_is_map_and_fenceable(rq->ring->vma))
- POSTING_READ_FW(GUC_STATUS);
+ port_set(port, port_pack(rq, ++count));
- spin_lock(&client->wq_lock);
+ if (i915_vma_is_map_and_fenceable(rq->ring->vma))
+ POSTING_READ_FW(GUC_STATUS);
- guc_wq_item_append(client, rq);
- guc_ring_doorbell(client);
+ spin_lock(&client->wq_lock);
- client->submissions[engine_id] += 1;
+ guc_wq_item_append(client, rq);
+ guc_ring_doorbell(client);
- spin_unlock(&client->wq_lock);
- }
+ client->submissions[engine_id] += 1;
+
+ spin_unlock(&client->wq_lock);
}
}
@@ -566,6 +569,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
struct drm_i915_gem_request *last = NULL;
bool submit = false;
struct rb_node *rb;
+ unsigned int first_idx;
spin_lock_irq(&engine->timeline->lock);
rb = el->first;
@@ -575,6 +579,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
goto done;
port = execlist_request_port(el);
+ first_idx = execlist_get_port_index(el, port);
do {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
@@ -614,7 +619,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
el->first = rb;
if (submit) {
port_assign(port, last);
- i915_guc_submit(engine);
+ i915_guc_submit(engine, first_idx);
}
spin_unlock_irq(&engine->timeline->lock);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index efa5a8ea1ecb..f2eb32539300 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -556,6 +556,15 @@ execlist_port_index(struct intel_engine_execlist * const
el,
return &el->port[__port_idx(el->port_head, n, el->port_mask)];
}
+static inline unsigned int
+execlist_get_port_index(const struct intel_engine_execlist * const el,
+ const struct execlist_port * const port)
+{
+ const unsigned int n = port_index(port, el);
+
+ return __port_idx(n, -el->port_head, el->port_mask);
+}
+
static inline struct execlist_port *
execlist_port_head(struct intel_engine_execlist * const el)
{
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915: Add execlist_port_complete
When first execlist entry is processed, we move the port (contents).
Introduce function for this as execlist and guc use this common
operation.
v2: rebase. s/GEM_DEBUG_BUG/GEM_BUG (Chris)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_guc_submission.c | 8
drivers/gpu/drm/i915/intel_lrc.c | 22 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h| 14 +-
3 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e967d266bc3c..d9f6dedae0d7 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -592,7 +592,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
rq->priotree.priority = INT_MAX;
__i915_gem_request_submit(rq);
- trace_i915_gem_request_in(rq, port_index(port, engine));
+ trace_i915_gem_request_in(rq, port_index(port, el));
last = rq;
submit = true;
}
@@ -615,7 +615,8 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
static void i915_guc_irq_handler(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
- struct execlist_port *port = engine->execlist.port;
+ struct intel_engine_execlist * const el = &engine->execlist;
+ struct execlist_port *port = el->port;
struct drm_i915_gem_request *rq;
rq = port_request(&port[0]);
@@ -623,8 +624,7 @@ static void i915_guc_irq_handler(unsigned long data)
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
- port[0] = port[1];
- memset(&port[1], 0, sizeof(port[1]));
+ execlist_port_complete(el, port);
rq = port_request(&port[0]);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ffb9c900328b..3008e13f9c47 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -454,7 +454,8 @@ static void port_assign(struct execlist_port *port,
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *last;
- struct execlist_port *port = engine->execlist.port;
+ struct intel_engine_execlist * const el = &engine->execlist;
+ struct execlist_port *port = el->port;
struct rb_node *rb;
bool submit = false;
@@ -468,8 +469,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*/
last->tail = last->wa_tail;
- GEM_BUG_ON(port_isset(&port[1]));
-
/* Hardware submission is through 2 ports. Conceptually each port
* has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
* static for a context, and unique to each, so we only execute
@@ -492,8 +491,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*/
spin_lock_irq(&engine->timeline->lock);
- rb = engine->execlist.first;
- GEM_BUG_ON(rb_first(&engine->execlist.queue) != rb);
+ rb = el->first;
+ GEM_BUG_ON(rb_first(&el->queue) != rb);
while (rb) {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
struct drm_i915_gem_request *rq, *rn;
@@ -516,7 +515,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* combine this request with the last, then we
* are done.
*/
- if (port != engine->execlist.port) {
+ if (port != el->port) {
__list_del_many(&p->requests,
&rq->priotree.link);
goto done;
@@ -541,25 +540,27 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (submit)
port_assign(port, last);
port++;
+
+ GEM_BUG_ON(port_isset(port));
}
INIT_LIST_HEAD(&rq->priotree.link);
rq->priotree.priority = INT_MAX;
__i915_gem_request_submit(rq);
- trace_i915_gem_request_in(rq, port_index(port, engine));
+ trace_i915_gem_request_in(rq, port_index(port, el));
last = rq;
submit = true;
}
rb = rb_next(rb);
- rb_erase(&p->node, &engine->execlist.queue);
+ rb_erase(&p->node, &el->queue);
INIT_LIST_HEAD(&p->requests);
[Intel-gfx] [PATCH 1/8] drm/i915: Make own struct for execlist items
Engine's execlist related items have been increasing to
a point where a separate struct is warranted. Carve execlist
specific items to a dedicated struct to add clarity.
v2: add kerneldoc and fix whitespace (Joonas, Chris)
v3: csb_mmio changes, rebase
Suggested-by: Chris Wilson
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Mika Kuoppala
Acked-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 8 +--
drivers/gpu/drm/i915/i915_gem.c| 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 31 +
drivers/gpu/drm/i915/i915_irq.c| 5 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++--
drivers/gpu/drm/i915/intel_lrc.c | 100 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h| 100 +++--
8 files changed, 167 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..7648ff207670 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3324,7 +3324,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
read = GEN8_CSB_READ_PTR(ptr);
write = GEN8_CSB_WRITE_PTR(ptr);
seq_printf(m, "\tExeclist CSB read %d [%d cached],
write %d [%d from hws], interrupt posted? %s\n",
- read, engine->csb_head,
+ read, engine->execlist.csb_head,
write,
intel_read_status_page(engine,
intel_hws_csb_write_index(engine->i915)),
yesno(test_bit(ENGINE_IRQ_EXECLIST,
@@ -3346,10 +3346,10 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port);
idx++) {
+ for (idx = 0; idx < ARRAY_SIZE(engine->execlist.port);
idx++) {
unsigned int count;
- rq = port_unpack(&engine->execlist_port[idx],
+ rq = port_unpack(&engine->execlist.port[idx],
&count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
@@ -3363,7 +3363,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_unlock();
spin_lock_irq(&engine->timeline->lock);
- for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
+ for (rb = engine->execlist.first; rb; rb = rb_next(rb))
{
struct i915_priolist *p =
rb_entry(rb, typeof(*p), node);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c4bf34865fa3..7934bafab081 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2815,8 +2815,8 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine)
* Turning off the engine->irq_tasklet until the reset is over
* prevents the race.
*/
- tasklet_kill(&engine->irq_tasklet);
- tasklet_disable(&engine->irq_tasklet);
+ tasklet_kill(&engine->execlist.irq_tasklet);
+ tasklet_disable(&engine->execlist.irq_tasklet);
if (engine->irq_seqno_barrier)
engine->irq_seqno_barrier(engine);
@@ -2995,7 +2995,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
{
- tasklet_enable(&engine->irq_tasklet);
+ tasklet_enable(&engine->execlist.irq_tasklet);
kthread_unpark(engine->breadcrumbs.signaler);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0c779671fe2d..8710fbdbbcb1 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1327,10 +1327,10 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
static void error_record_engine_execlists(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
{
- const struct execlist_port *port = engine->execlist_port;
+ const struct execlist_port *port = engine->execlist.port;
unsigned int n;
- for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
+ for (n = 0; n < ARRAY_SIZE(engine->execlist.port); n++) {
struct drm_i915_gem_request *rq = port_request(&port[n]);
if (!rq)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e191d56fc990..e967
[Intel-gfx] [PATCH 2/8] drm/i915: Move execlist initialization into intel_engine_cs.c
Move execlist init into a common engine setup. As it is
common to both guc and hw execlists.
v2: rebase with csb changes
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_engine_cs.c | 31 ---
drivers/gpu/drm/i915/intel_lrc.c | 19 ---
2 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index eb6feaf69a3b..d58e17efd243 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -380,6 +380,33 @@ static void intel_engine_init_timeline(struct
intel_engine_cs *engine)
engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
}
+static bool csb_force_mmio(struct drm_i915_private *i915)
+{
+ /* GVT emulation depends upon intercepting CSB mmio */
+ if (intel_vgpu_active(i915))
+ return true;
+
+ /*
+* IOMMU adds unpredictable latency causing the CSB write (from the
+* GPU into the HWSP) to only be visible some time after the interrupt
+* (missed breadcrumb syndrome).
+*/
+ if (intel_vtd_active())
+ return true;
+
+ return false;
+}
+
+static void intel_engine_init_execlist(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlist * const el = &engine->execlist;
+
+ el->csb_use_mmio = csb_force_mmio(engine->i915);
+
+ el->queue = RB_ROOT;
+ el->first = NULL;
+}
+
/**
* intel_engines_setup_common - setup engine state not requiring hw access
* @engine: Engine to setup.
@@ -391,9 +418,7 @@ static void intel_engine_init_timeline(struct
intel_engine_cs *engine)
*/
void intel_engine_setup_common(struct intel_engine_cs *engine)
{
- engine->execlist.queue = RB_ROOT;
- engine->execlist.first = NULL;
-
+ intel_engine_init_execlist(engine);
intel_engine_init_timeline(engine);
intel_engine_init_hangcheck(engine);
i915_gem_batch_pool_init(engine, &engine->batch_pool);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c2fcc4936ba..a4ece4c4f291 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1784,23 +1784,6 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
}
-static bool irq_handler_force_mmio(struct drm_i915_private *i915)
-{
- /* GVT emulation depends upon intercepting CSB mmio */
- if (intel_vgpu_active(i915))
- return true;
-
- /*
-* IOMMU adds unpredictable latency causing the CSB write (from the
-* GPU into the HWSP) to only be visible some time after the interrupt
-* (missed breadcrumb syndrome).
-*/
- if (intel_vtd_active())
- return true;
-
- return false;
-}
-
static void
logical_ring_setup(struct intel_engine_cs *engine)
{
@@ -1812,8 +1795,6 @@ logical_ring_setup(struct intel_engine_cs *engine)
/* Intentionally left blank. */
engine->buffer = NULL;
- engine->execlist.csb_use_mmio = irq_handler_force_mmio(dev_priv);
-
fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
RING_ELSP(engine),
FW_REG_WRITE);
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/8] Support for more than two execlist ports (v2)
Hi, HWSP context status buffer handling and guc cleanup and request coalescing series were merged and those triggered non trivial rebase. So I had to drop reviewed-by's from the patches :( First 4 should be tasting more or less the same though. Thankyou for review and comments! -Mika Mika Kuoppala (8): drm/i915: Make own struct for execlist items drm/i915: Move execlist initialization into intel_engine_cs.c drm/i915: Wrap port cancellation into a function drm/i915: Add execlist_port_complete drm/i915: Make execlist port count variable drm/i915: Introduce execlist_port_* accessors drm/i915: Keep track of reserved execlist ports drm/i915: Improve GuC request coalescing drivers/gpu/drm/i915/i915_debugfs.c| 24 ++-- drivers/gpu/drm/i915/i915_drv.h| 3 +- drivers/gpu/drm/i915/i915_gem.c| 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 17 ++- drivers/gpu/drm/i915/i915_guc_submission.c | 102 -- drivers/gpu/drm/i915/i915_irq.c| 5 +- drivers/gpu/drm/i915/intel_engine_cs.c | 48 +-- drivers/gpu/drm/i915/intel_lrc.c | 214 - drivers/gpu/drm/i915/intel_ringbuffer.h| 197 +++--- 9 files changed, 424 insertions(+), 192 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/8] drm/i915: Introduce execlist_port_* accessors
Instead of trusting that first available port is at index 0,
use accessor to hide this. This is a preparation for a
following patches where head can be at arbitrary location
in the port array.
v2: improved commit message, elsp_ready readability (Chris)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c| 16 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +--
drivers/gpu/drm/i915/i915_guc_submission.c | 17 ++-
drivers/gpu/drm/i915/i915_irq.c| 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 42 +++
drivers/gpu/drm/i915/intel_ringbuffer.h| 46 ++
7 files changed, 87 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index dbeb6f08ab79..af8cc2eab1b1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3348,16 +3348,20 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_lock();
for (idx = 0; idx < execlist_num_ports(el); idx++) {
- unsigned int count;
+ const struct execlist_port *port;
+ unsigned int count, n;
- rq = port_unpack(&el->port[idx], &count);
+ port = execlist_port_index(el, idx);
+ n = port_index(port, el);
+
+ rq = port_unpack(port, &count);
if (rq) {
- seq_printf(m, "\t\tELSP[%d] count=%d, ",
- idx, count);
+ seq_printf(m, "\t\tELSP[%d:%d]
count=%d, ",
+ idx, n, count);
print_request(m, rq, "rq: ");
} else {
- seq_printf(m, "\t\tELSP[%d] idle\n",
- idx);
+ seq_printf(m, "\t\tELSP[%d:%d] idle\n",
+ idx, n);
}
}
rcu_read_unlock();
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0a803d76256b..19e4c297c857 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1332,11 +1332,11 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
static void error_record_engine_execlists(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
{
- const struct intel_engine_execlist * const el = &engine->execlist;
+ struct intel_engine_execlist * const el = &engine->execlist;
unsigned int n;
for (n = 0; n < execlist_num_ports(el); n++) {
- struct drm_i915_gem_request *rq = port_request(&el->port[n]);
+ struct drm_i915_gem_request *rq =
port_request(execlist_port_index(el, n));
if (!rq)
break;
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 3a4f875d5930..25c9bac94c39 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -562,8 +562,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
struct intel_engine_execlist * const el = &engine->execlist;
struct execlist_port *port = el->port;
struct drm_i915_gem_request *last = NULL;
- const struct execlist_port * const last_port =
- &el->port[el->port_mask];
+ const struct execlist_port * const last_port = execlist_port_tail(el);
bool submit = false;
struct rb_node *rb;
@@ -587,7 +586,8 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
if (submit)
port_assign(port, last);
- port++;
+
+ port = execlist_port_next(el, port);
}
INIT_LIST_HEAD(&rq->priotree.link);
@@ -618,19 +618,18 @@ static void i915_guc_irq_handler(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
struct intel_engine_execlist * const el = &engine->execlist;
- struct execlist_port *port = el->port;
- const struct execlist_port * const last_port =
- &el->port[el->port_mask];
+ struct execlist_port *port = execlist_port_head(el);
+ const struct execlist_port * const last_port = execlist_port
[Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink
Add defines for dpcd register 2009 (synchronization latency in sink). Cc: Rodrigo Vivi CC: Puthikorn Voravootivat Signed-off-by: Vathsala Nagaraju --- include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07 +#define DP_SINK_SYNCHRONIZATION_LATENCY0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf + #define DP_RECEIVER_ALPM_STATUS0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR(1 << 0) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
Cc: Rodrigo Vivi
CC: Puthikorn Voravootivat
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/intel_psr.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index acb5094..04b253f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+ &sink_latency)) {
+ sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
+ val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
+ } else {
+ val |= EDP_FRAMES_BEFORE_SU_ENTRY;
+ }
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
1.9.1
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Eliminate DDI encoder->type frobbery redux (rev2)
== Series Details ==
Series: drm/i915: Eliminate DDI encoder->type frobbery redux (rev2)
URL : https://patchwork.freedesktop.org/series/30548/
State : failure
== Summary ==
Series 30548v2 drm/i915: Eliminate DDI encoder->type frobbery redux
https://patchwork.freedesktop.org/api/1.0/series/30548/revisions/2/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> INCOMPLETE (fi-bxt-j4205)
incomplete -> PASS (fi-kbl-7500u) fdo#102850
pass -> INCOMPLETE (fi-glk-1)
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip -> PASS (fi-ivb-3520m)
Subgroup force-edid:
skip -> PASS (fi-ivb-3520m)
Subgroup force-load-detect:
skip -> PASS (fi-ivb-3520m)
Subgroup prune-stale-modes:
skip -> PASS (fi-ivb-3520m)
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (fi-cfl-s) fdo#102294
fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21
time:450s
fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24
time:467s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64
time:422s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46
time:517s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105
time:280s
fi-bxt-j4205 total:118 pass:97 dwarn:0 dfail:0 fail:0 skip:20
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34
time:500s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38
time:494s
fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32
time:540s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59
time:418s
fi-glk-1 total:118 pass:96 dwarn:0 dfail:0 fail:0 skip:21
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26
time:428s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26
time:406s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60
time:434s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28
time:492s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28
time:462s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24
time:476s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19
time:580s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27
time:588s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65
time:541s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20
time:454s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24
time:757s
fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20
time:495s
fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23
time:474s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38
time:581s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39
time:422s
ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC
integration manifest
1a3cc94fd8a2 drm/i915: Pass a crtc state to ddi post_disable from MST code
fe29fba4c99a drm/i915: Replace most intel_ddi_get_encoder_port() alls with
encoder->port
16cf6a4a256f drm/i915: Clear up the types we use for DDI buf trans
level/n_entries
4879849898e3 drm/i915: Unify error handling for missing DDI buf trans tables
a268529d63e0 drm/i915: Stop frobbing with DDI encoder->type
08833641db2d drm/i915: Centralize the SKL DDI A/E vs. B/C/D buf trans handling
2eac6ef17b52 drm/i915: Stop using encoder->type in
intel_ddi_enable_transcoder_func()
50dfaa9fe719 drm/i915: Start using output_types for DPLL selection
22a4439a1fc3 drm/i915: Pass crtc state to intel_prepare_dp_ddi_buffers()
225af3872bee drm/i915: Don't use encoder->type in intel_ddi_set_pipe_settings()
57076a4e4999 drm/i915: Kill off the BXT buf_trans default_index
c54c4ebe5188 drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitly
2da510f28eea drm/i915: Integrate BXT into intel_ddi_dp_voltage_max()
732f6537f3c7 drm/i915: Pass the level to intel_prepare_hdmi_ddi_buffers()
64ddfd7839a0 drm/i915: Pass the encoder type explicitly to skl_set_iboost()
7ec30a4df53d drm/i915: Extract intel_ddi_get_buf_trans_hdmi()
0414a981af1d drm/i915: Relocate intel_ddi_get_buf_trans_*() functions
9dc0432deb03 drm/i915: Split intel_enable_ddi() into DP and HDMI variants
0273999dbbc4 drm/i915: Plump crtc_state etc. directly to
intel_ddi_pre_enable_{dp, hdmi}()
f0128eeec610 drm/i915: Split intel_disable_ddi()
[Intel-gfx] [PATCH v2 04/29] drm/i915: Dump 'output_types' in crtc state dump
From: Ville Syrjälä
To make it easier to debug things let's dump the output types bitmask in
the crtc state dump. And to make life that much better, let's pretty
print it as a a human reaadable string as well.
v2: Have the caller pass in the buffer (Chris)
#undef OUTPUT_TYPE (Jani)
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 51
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8599e425abb1..9221f613643a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10683,6 +10683,52 @@ intel_dump_m_n_config(struct intel_crtc_state
*pipe_config, char *id,
m_n->link_m, m_n->link_n, m_n->tu);
}
+#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
+
+static const char * const output_type_str[] = {
+ OUTPUT_TYPE(UNUSED),
+ OUTPUT_TYPE(ANALOG),
+ OUTPUT_TYPE(DVO),
+ OUTPUT_TYPE(SDVO),
+ OUTPUT_TYPE(LVDS),
+ OUTPUT_TYPE(TVOUT),
+ OUTPUT_TYPE(HDMI),
+ OUTPUT_TYPE(DP),
+ OUTPUT_TYPE(EDP),
+ OUTPUT_TYPE(DSI),
+ OUTPUT_TYPE(UNKNOWN),
+ OUTPUT_TYPE(DP_MST),
+};
+
+#undef OUTPUT_TYPE
+
+static void snprintf_output_types(char *buf, size_t len,
+ unsigned int output_types)
+{
+ char *str = buf;
+ int i;
+
+ str[0] = '\0';
+
+ for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
+ int r;
+
+ if ((output_types & BIT(i)) == 0)
+ continue;
+
+ r = snprintf(str, len, "%s%s",
+str != buf ? "," : "", output_type_str[i]);
+ if (r >= len)
+ break;
+ str += r;
+ len -= r;
+
+ output_types &= ~BIT(i);
+ }
+
+ WARN_ON_ONCE(output_types != 0);
+}
+
static void intel_dump_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config,
const char *context)
@@ -10693,10 +10739,15 @@ static void intel_dump_pipe_config(struct intel_crtc
*crtc,
struct intel_plane *intel_plane;
struct intel_plane_state *state;
struct drm_framebuffer *fb;
+ char buf[64];
DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
crtc->base.base.id, crtc->base.name, context);
+ snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
+ DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
+ buf, pipe_config->output_types);
+
DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
transcoder_name(pipe_config->cpu_transcoder),
pipe_config->pipe_bpp, pipe_config->dither);
--
2.13.5
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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Set our shrinker->batch to 4096 (~16MiB)
On Wed, 2017-08-16 at 14:55 +0100, Chris Wilson wrote: > Quoting Joonas Lahtinen (2017-08-16 14:39:00) > > On Sat, 2017-08-12 at 12:51 +0100, Chris Wilson wrote: > > > Prefer to defer activating our GEM shrinker until we have a few > > > megabytes to free; or we have accumulated sufficient mempressure by > > > deferring the reclaim to force a shrink. The intent is that because our > > > objects may typically be large, we are too effective at shrinking and > > > are not rewarded for freeing more pages than the batch. It will also > > > defer the initial shrinking to hopefully put it at a lower priority than > > > say the buffer cache (although it will balance out over a number of > > > reclaims, with GEM being more bursty). > > > > > > Signed-off-by: Chris Wilson > > > --- > > > drivers/gpu/drm/i915/i915_gem_shrinker.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c > > > b/drivers/gpu/drm/i915/i915_gem_shrinker.c > > > index 5b8bc0e4f336..8bb17e9a52de 100644 > > > --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c > > > +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c > > > @@ -461,6 +461,7 @@ void i915_gem_shrinker_init(struct drm_i915_private > > > *dev_priv) > > > dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; > > > dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; > > > dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; > > > + dev_priv->mm.shrinker.batch = 4096; > > > > Did you try how this alone effects the runtime of two consequtive > > gem.testlist runs? Is there some specific test/usecase that benefits > > from this. We'd be the first one to set this, md/raid5.c sets it to 128 > > which is the default (0). > > My testing was trying to play a game that was hitting swap on an old > hdd. So not very quantifiable, and vmscan is very unintuitive. > > Note also that we are special in that we don't report objects but pages. > Not that it makes any difference, upon reclaim every slab is basically > asked to give up some %% of what it reports, with some hysteresis thrown > in on top. > > The only way we can do anything here is to throw it at lots of systems > and see how that helps. My gut feeling says that the batch size should > be approximately the typical object size in the freeable list, to try to > reduce the amount of inefficient work. Now, the value is read before > scan->count is called, but we can always improve the estimate for the > next pass. For documentation purposes, from IRC, this is; Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const
On Wed, 2017-09-20 at 15:01 +0300, Jani Nikula wrote: > On Wed, 20 Sep 2017, Joonas Lahtinen wrote: > > On Tue, 2017-09-19 at 19:38 +, Michal Wajdeczko wrote: > > > We should discourage developers from modifying modparams. > > > Introduce special macro for easier tracking of changes done > > > in modparams and enforce its use by defining existing modparams > > > members as const. Note that defining whole modparams struct > > > as const makes checkpatch unhappy. > > > > > > v2: rebased > > > > > > Credits-to: Coccinelle > > > > > > @@ > > > identifier n; > > > expression e; > > > @@ > > > ( > > > - i915_modparams.n = e; > > > + i915_modparams_set(n, e); > > > > Not cool with such a brief name, it really needs to be something more > > standing out to make the developer think they've failed design if > > they're calling the function. > > > > 'i915_modparams_force_write' is my current favourite. > > > > And we need huge kerneldoc comment for the function about the concerns > > expressed by Jani, me and Ville. There must be no potential readers for > > the variables while they're being changed, compiler optimizations need > > to be watched for etc. > > > > Because really, if we change a module parameter variable while somebody > > is for example running a loop based on it, we're in deep problems. > > > > Might be worthwhile having a i915_modparams_lock to be taken when > > sanitization of options begins, and asserting that lock is held when > > _force_write() is being called. rw_semaphore sounds like the right > > choice here. Many can read but only one can write. > > > > Any opinions on that? > > It can't protect against users changing the parameters via sysfs, and I > think fixing that at the moment would have an air of overengineering. > > I'm thinking review and merge patch 1 to fix the i915 name collision, > and forget about the rest for now. Agreed on merging, disagreeing on forgetting next steps. > Too much controversy, no real rush or > pressure to do anything right now beyond patch 1. Don't just do > something, stand there. The controversy seemed to be around compiler optimizations, and that doesn't seem to be a worry. The other thing is how to name the function, and that's not too bad discussion. It naturally shouldn't block merging the first patch. Reviewing the places where the modparams get written/read may only lead to improvements as I see it. Any troublesome variables should get moved to device state instead of module state. For example while sanitizing enable_ppgtt and other user requested kernel parameters, we should copy the state to relevant dynamic structures where it'll have an effect, if we actually intend to support changing the parameters on the fly. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/kms_cursor_legacy: Do not start collecting CRC after making FB busy
Op 19-09-17 om 13:49 schreef Ville Syrjälä:
> On Tue, Sep 19, 2017 at 01:31:13PM +0200, Maarten Lankhorst wrote:
>> Collecting CRC may force a modeset, which is a bad idea after we just
>> forced a hang. The hang is intended to make sure the page flip doesn't
>> complete before the cursor, making sure that works.
>>
>> Signed-off-by: Maarten Lankhorst
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102259
>> Cc: Marta Lofstedt
>> ---
>> tests/kms_cursor_legacy.c | 25 +
>> 1 file changed, 21 insertions(+), 4 deletions(-)
>>
>> diff --git a/tests/kms_cursor_legacy.c b/tests/kms_cursor_legacy.c
>> index 2d32d3a91570..c3149535b838 100644
>> --- a/tests/kms_cursor_legacy.c
>> +++ b/tests/kms_cursor_legacy.c
>> @@ -1334,7 +1334,7 @@ static void flip_vs_cursor_busy_crc(igt_display_t
>> *display, bool atomic)
>> igt_pipe_crc_t *pipe_crc;
>> igt_pipe_t *pipe_connected = &display->pipes[pipe];
>> igt_plane_t *plane_primary = igt_pipe_get_plane_type(pipe_connected,
>> DRM_PLANE_TYPE_PRIMARY);
>> -igt_crc_t crcs[3];
>> +igt_crc_t crcs[2];
>>
>> if (atomic)
>> igt_require(display->is_atomic);
>> @@ -1348,7 +1348,7 @@ static void flip_vs_cursor_busy_crc(igt_display_t
>> *display, bool atomic)
>>
>> igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC :
>> COMMIT_LEGACY);
>>
>> -pipe_crc = igt_pipe_crc_new(display->drm_fd, pipe,
>> INTEL_PIPE_CRC_SOURCE_AUTO);
>> +pipe_crc = igt_pipe_crc_new_nonblock(display->drm_fd, pipe,
>> INTEL_PIPE_CRC_SOURCE_AUTO);
>>
>> set_cursor_on_pipe(display, pipe, &cursor_fb);
>> igt_display_commit2(display, COMMIT_UNIVERSAL);
>> @@ -1371,9 +1371,17 @@ static void flip_vs_cursor_busy_crc(igt_display_t
>> *display, bool atomic)
>> igt_plane_set_fb(plane_primary, &fb_info[0]);
>> igt_display_commit2(display, COMMIT_UNIVERSAL);
>>
>> +/*
>> + * We must enable CRC collecting here since this may force
>> + * a modeset, and this loop is timing sensitive.
>> + */
>> +igt_pipe_crc_start(pipe_crc);
>> +
>> /* Disable cursor, and immediately queue a flip. Check if resulting crc
>> is correct. */
>> for (int i = 1; i >= 0; i--) {
>> uint32_t *busy;
>> +igt_crc_t *received_crcs = NULL;
>> +int ncrcs;
>>
>> busy = make_fb_busy(display->drm_fd, &fb_info[1]);
>>
>> @@ -1384,7 +1392,7 @@ static void flip_vs_cursor_busy_crc(igt_display_t
>> *display, bool atomic)
>>
>> igt_assert_eq(get_vblank(display->drm_fd, pipe, 0),
>> vblank_start);
>>
>> -igt_pipe_crc_collect_crc(pipe_crc, &crcs[2]);
>> +ncrcs = igt_pipe_crc_get_crcs(pipe_crc, 8, &received_crcs);
>>
>> finish_fb_busy(busy);
>>
>> @@ -1397,13 +1405,22 @@ static void flip_vs_cursor_busy_crc(igt_display_t
>> *display, bool atomic)
>> igt_plane_set_fb(plane_primary, &fb_info[0]);
>> igt_display_commit2(display, COMMIT_UNIVERSAL);
>>
>> -igt_assert_crc_equal(&crcs[i], &crcs[2]);
>> +igt_assert(ncrcs > 0);
> Should we perhaps assign some arbitrary upper limit on the crcs we get?
> If the kernel already buffered 8 or more crcs, we may get a crc mismatch
> even though the problem is that the test blocked for too long and we're
> now looking at a stale crc rather than the current crc being wrong.
> Might make it slightly easier to diagnose the failure correctly.
>
> Anyways
> Reviewed-by: Ville Syrjälä
>
>> +
>> +igt_assert_crc_equal(&crcs[i], &received_crcs[ncrcs - 1]);
>> +free(received_crcs);
>> }
>>
>> do_cleanup_display(display);
>> igt_remove_fb(display->drm_fd, &fb_info[1]);
>> igt_remove_fb(display->drm_fd, &fb_info[0]);
>> igt_remove_fb(display->drm_fd, &cursor_fb);
>> +
>> +/*
>> + * igt_pipe_crc_stop() may force a modeset for workarounds, call
>> + * it after do_cleanup_display since we disable the display anyway.
>> + */
>> +igt_pipe_crc_stop(pipe_crc);
>> igt_pipe_crc_free(pipe_crc);
>> }
>>
>> --
>> 2.14.1
>>
>> ___
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Thanks, pushed with a limit in place to prevent overflow. :)
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[Intel-gfx] [PATCH] dim: Accept author x signed-off based on email.
It seems Patchwork or SMTP servers are messing some patches and changing the original git's author name on git per "Last, First". So we end up with a mismatch were signed-off uses one name format and author is using another format. So, let's check for email addresses instead. v2: Avoid useles warning and only check for email. Cc: Jani Nikula Cc: Joonas Lahtinen Signed-off-by: Rodrigo Vivi --- dim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dim b/dim index dbaeb1ec944d..a63000fb67a8 100755 --- a/dim +++ b/dim @@ -689,7 +689,7 @@ function checkpatch_commit_push sha1=$1 # use real names for people with many different email addresses - author=$(git show -s $sha1 --format="format:%an") + author=$(git show -s $sha1 --format="format:%ae") committer=$(git show -s $sha1 --format="format:%cn") # check for author sign-off -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] dim: Accept author x signed-off based on email, but warn.
On Wed, Sep 20, 2017 at 11:51:50AM +, Jani Nikula wrote: > On Wed, 20 Sep 2017, Joonas Lahtinen wrote: > > On Tue, 2017-09-19 at 10:48 -0700, Rodrigo Vivi wrote: > >> It seems Patchwork or SMTP servers are messing some patches > >> and changing the original git's author name on git per "Last, First". > >> So we end up with a mismatch were signed-off uses one name format > >> and author is using another format. > > > > + Arek, > > > > Wasn't this trouble supposed to be fixed? > > Maybe in patchwork context, but it can still happen for people applying > patches from their MUA. And I doubt it can be reliably "fixed" if the > author intentionally or inadvertently has differing author and sob > lines. hmm... if this is possible we do need to only check for email and move one. But anyways what I'm seeing a lot recently is this patchwork issue joonas mentioned. I had to edit few of my patches recently because something on the way changed my "name last" per "last, name".. and this seems exactly the case with one Manasi's and one Lee's patch that was impacting the pull request flow. So if the patchwork is fixed now I believe we can just change the check to email instead of the name and move on... Thanks, Rodrigo. > > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes v2
Hi Dave, I'm sorry for the previous version generated on wrong base. I believe this one looks sane now. drm/i915 fixes for 4.14-rc1 Couple fixes for stable: - Fix MIPI panels on BXT. - Fix PCI BARs information on GVT. Plus other fixes: - Fix minimal brightness for BXT, GLK, CFL and CNL. - Fix compilation warning: unused in_vbl - Fix error handling in intel_framebuffer_init The following changes since commit 134dd2e616b9cd8300c08cd1b38987ded74f662f: Merge tag 'drm-amdkfd-next-2017-09-02' of git://people.freedesktop.org/~gabbayo/linux into drm-fixes (2017-09-18 16:29:47 +1000) are available in the git repository at: git://anongit.freedesktop.org/git/drm-intel tags/drm-intel-fixes-2017-09-20 for you to fetch changes up to 99df13b6ea811a63eeacb278d05a5b914ce28073: drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos() (2017-09-18 15:22:37 -0700) drm/i915 fixes for 4.14-rc1 Couple fixes for stable: - Fix MIPI panels on BXT. - Fix PCI BARs information on GVT. Plus other fixes: - Fix minimal brightness for BXT, GLK, CFL and CNL. - Fix compilation warning: unused in_vbl - Fix error handling in intel_framebuffer_init Changbin Du (1): drm/i915/gvt: Fix incorrect PCI BARs reporting Chris Wilson (1): drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos() Christophe JAILLET (1): drm/i915: Fix an error handling in 'intel_framebuffer_init()' Lee, Shawn C (2): drm/i915/bxt: set min brightness from VBT drm/i915/cnp: set min brightness from VBT Uma Shankar (1): Revert "drm/i915/bxt: Disable device ready before shutdown command" drivers/gpu/drm/i915/gvt/cfg_space.c | 113 +++ drivers/gpu/drm/i915/i915_irq.c | 3 - drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_dsi.c | 11 drivers/gpu/drm/i915/intel_panel.c | 4 ++ 5 files changed, 53 insertions(+), 80 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/31] drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm"
On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > Will be using pm for state containing RPS/RC6 state in the next patch. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble Reviewed-by: Radoslaw Szwichtenberg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/31] drm/i915: Separate RPS and RC6 handling for CHV
On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > This patch separates enable/disable of RC6 and RPS for CHV. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble Reviewed-by: Radoslaw Szwichtenberg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/31] drm/i915: Separate RPS and RC6 handling for BDW
On Wed, 2017-09-20 at 11:14 +, Szwichtenberg, Radoslaw wrote:
> On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote:
> > This patch separates RC6 and RPS enabling for BDW.
> > RC6/RPS Disabling are handled through gen6 functions.
> >
> > Cc: Imre Deak
> > Cc: Chris Wilson
> > Signed-off-by: Sagar Arun Kamble
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 27 +++
> > 1 file changed, 15 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index f78a1e8..6de69ae 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6613,7 +6613,7 @@ static void gen9_enable_rc6(struct drm_i915_private
> > *dev_priv)
> > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> > }
> >
> > -static void gen8_enable_rps(struct drm_i915_private *dev_priv)
> > +static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
> > {
> > struct intel_engine_cs *engine;
> > enum intel_engine_id id;
> > @@ -6645,16 +6645,18 @@ static void gen8_enable_rps(struct drm_i915_private
> > *dev_priv)
> > if (intel_enable_rc6() & INTEL_RC6_ENABLE)
> > rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> > intel_print_rc6_info(dev_priv, rc6_mask);
> > - if (IS_BROADWELL(dev_priv))
> > - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> > - GEN7_RC_CTL_TO_MODE |
> > - rc6_mask);
> > - else
> > - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> > - GEN6_RC_CTL_EI_MODE(1) |
> > - rc6_mask);
> > + I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> > + GEN7_RC_CTL_TO_MODE |
> > + rc6_mask);
> >
> > - /* 4 Program defaults and thresholds for RPS*/
> > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> > +}
> > +
> > +static void gen8_enable_rps(struct drm_i915_private *dev_priv)
> > +{
> > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> > +
> > + /* 1 Program defaults and thresholds for RPS*/
> > I915_WRITE(GEN6_RPNSWREQ,
> > HSW_FREQUENCY(dev_priv->rps.rp1_freq));
> > I915_WRITE(GEN6_RC_VIDEO_FREQ,
> > @@ -6674,7 +6676,7 @@ static void gen8_enable_rps(struct drm_i915_private
> > *dev_priv)
> >
> > I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> >
> > - /* 5: Enable RPS */
> > + /* 2: Enable RPS */
> > I915_WRITE(GEN6_RP_CONTROL,
> > GEN6_RP_MEDIA_TURBO |
> > GEN6_RP_MEDIA_HW_NORMAL_MODE |
> > @@ -6683,7 +6685,7 @@ static void gen8_enable_rps(struct drm_i915_private
> > *dev_priv)
> > GEN6_RP_UP_BUSY_AVG |
> > GEN6_RP_DOWN_IDLE_AVG);
> >
> > - /* 6: Ring frequency + overclocking (our driver does this later */
> > + /* 3: Ring frequency + overclocking (our driver does this later */
>
> This comment looks invalid (no overclocking done here). Also closing bracket
> missing and maybe one white line to be removed :)
>
> -Radek
Forgot to mention - beside this comment all changes look good to me (you can
have my r-b after this is fixed).
> >
> > reset_rps(dev_priv, gen6_set_rps);
> >
> > @@ -7976,6 +7978,7 @@ void intel_enable_gt_powersave(struct drm_i915_private
> > *dev_priv)
> > if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > gen6_update_ring_freq(dev_priv);
> > } else if (IS_BROADWELL(dev_priv)) {
> > + gen8_enable_rc6(dev_priv);
> > gen8_enable_rps(dev_priv);
> > gen6_update_ring_freq(dev_priv);
> > } else if (INTEL_GEN(dev_priv) >= 6) {
>
> ___
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Re: [Intel-gfx] [PATCH 04/31] drm/i915: Separate RPS and RC6 handling for VLV
On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > This patch separates enable/disable of RC6 and RPS for VLV. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble Reviewed-by: Radoslaw Szwichtenberg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/31] drm/i915: Separate RPS and RC6 handling for gen6+
On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > This patch separates enable/disable of RC6 and RPS for gen6+ > platforms prior to VLV. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble Reviewed-by: Radoslaw Szwichtenberg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const
On Wed, 2017-09-20 at 15:06 +0300, Joonas Lahtinen wrote: > On Wed, 2017-09-20 at 11:34 +0300, Jani Nikula wrote: > > On Tue, 19 Sep 2017, Michal Wajdeczko wrote: > > > We should discourage developers from modifying modparams. > > > Introduce special macro for easier tracking of changes done > > > in modparams and enforce its use by defining existing modparams > > > members as const. Note that defining whole modparams struct > > > as const makes checkpatch unhappy. > > > > Checkpatch is the least of all reasons to not make the modparams struct > > const. > > > > We can get away with having some fields (such as device info within > > dev_priv) const, even if that's dubious. > > > > IIUC modifying const data is undefined behaviour at best, could cause > > subtle bugs through compiler optimizing reads of the data away because > > it assumes no modifications, and the data gets placed in rodata at > > worst. > > > > I kinda like the union trick in this patch, but IMO we need to double > > check what the standard says about it. Making the fellow developers > > check the standard is always a bad sign, even if it turns out to be fine > > after all. > > Here's the snippet to describe the three discussed behaviors. Michal's > code seems to do the right thing: > > https://gcc.godbolt.org/g/6MCNC3 > > We just need to make the write function stand out more and have a > kerneldoc for it. > Umm, and when I don't typo a missing "&", it's more obvious (now with --Wall -Wextra -Werror): https://gcc.godbolt.org/g/HszLnw Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const
On Wed, 2017-09-20 at 11:34 +0300, Jani Nikula wrote: > On Tue, 19 Sep 2017, Michal Wajdeczko wrote: > > We should discourage developers from modifying modparams. > > Introduce special macro for easier tracking of changes done > > in modparams and enforce its use by defining existing modparams > > members as const. Note that defining whole modparams struct > > as const makes checkpatch unhappy. > > Checkpatch is the least of all reasons to not make the modparams struct > const. > > We can get away with having some fields (such as device info within > dev_priv) const, even if that's dubious. > > IIUC modifying const data is undefined behaviour at best, could cause > subtle bugs through compiler optimizing reads of the data away because > it assumes no modifications, and the data gets placed in rodata at > worst. > > I kinda like the union trick in this patch, but IMO we need to double > check what the standard says about it. Making the fellow developers > check the standard is always a bad sign, even if it turns out to be fine > after all. Here's the snippet to describe the three discussed behaviors. Michal's code seems to do the right thing: https://gcc.godbolt.org/g/6MCNC3 We just need to make the write function stand out more and have a kerneldoc for it. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const
On Wed, 20 Sep 2017, Joonas Lahtinen wrote: > On Tue, 2017-09-19 at 19:38 +, Michal Wajdeczko wrote: >> We should discourage developers from modifying modparams. >> Introduce special macro for easier tracking of changes done >> in modparams and enforce its use by defining existing modparams >> members as const. Note that defining whole modparams struct >> as const makes checkpatch unhappy. >> >> v2: rebased >> >> Credits-to: Coccinelle >> >> @@ >> identifier n; >> expression e; >> @@ >> ( >> -i915_modparams.n = e; >> +i915_modparams_set(n, e); > > Not cool with such a brief name, it really needs to be something more > standing out to make the developer think they've failed design if > they're calling the function. > > 'i915_modparams_force_write' is my current favourite. > > And we need huge kerneldoc comment for the function about the concerns > expressed by Jani, me and Ville. There must be no potential readers for > the variables while they're being changed, compiler optimizations need > to be watched for etc. > > Because really, if we change a module parameter variable while somebody > is for example running a loop based on it, we're in deep problems. > > Might be worthwhile having a i915_modparams_lock to be taken when > sanitization of options begins, and asserting that lock is held when > _force_write() is being called. rw_semaphore sounds like the right > choice here. Many can read but only one can write. > > Any opinions on that? It can't protect against users changing the parameters via sysfs, and I think fixing that at the moment would have an air of overengineering. I'm thinking review and merge patch 1 to fix the i915 name collision, and forget about the rest for now. Too much controversy, no real rush or pressure to do anything right now beyond patch 1. Don't just do something, stand there. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
