[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/dp: Add defines for latency in sink
== Series Details == Series: series starting with [1/2] drm/dp: Add defines for latency in sink URL : https://patchwork.freedesktop.org/series/30797/ State : success == Summary == shard-hswtotal:2429 pass:1329 dwarn:5 dfail:0 fail:12 skip:1083 time:9777s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5798/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink
== Series Details == Series: series starting with [1/2] drm/dp: Add defines for latency in sink URL : https://patchwork.freedesktop.org/series/30797/ State : success == Summary == Series 30797v1 series starting with [1/2] drm/dp: Add defines for latency in sink https://patchwork.freedesktop.org/api/1.0/series/30797/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: incomplete -> PASS (fi-kbl-7500u) fdo#102850 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:445s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:419s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:520s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:504s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:490s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:496s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:544s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:414s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:558s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:420s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:403s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:431s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:486s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:457s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:466s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:574s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:593s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:536s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:447s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:747s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:479s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:412s 6aa0df37d3fc238146f0445f71bb0738490cb6dc drm-tip: 2017y-09m-22d-21h-24m-10s UTC integration manifest 11fe95fd5633 drm/i915/psr: Set frames before SU entry for psr2 7bd1f311bec4 drm/dp: Add defines for latency in sink == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5798/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink
Add defines for dpcd register 2009 (synchronization latency in sink). Cc: Rodrigo Vivi CC: Puthikorn Voravootivat Reviewed-by: Rodrigo Vivi Signed-off-by: Vathsala Nagaraju --- include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07 +#define DP_SINK_SYNCHRONIZATION_LATENCY0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf + #define DP_RECEIVER_ALPM_STATUS0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR(1 << 0) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
v3 : (Rodrigo)
- move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
- replace with &=
Cc: Rodrigo Vivi
CC: Puthikorn Voravootivat
Reviewed-by: Rodrigo Vivi
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_psr.c | 12 ++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..b880c84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4047,7 +4047,7 @@ enum {
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK(0xf<<4)
#define EDP_PSR2_IDLE_MASK 0xf
-#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
#define EDP_PSR2_STATUS_CTL_MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..adf7abc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+ &sink_latency) == 1) {
+ sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
+ } else {
+ sink_latency = 0;
+ }
+ val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
1.9.1
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
On Fri, Sep 22, 2017 at 03:58:36PM +, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
> - add check ==1 for dpcd_read call (ville)
>
> Cc: Rodrigo Vivi
> CC: Puthikorn Voravootivat
> Signed-off-by: Vathsala Nagaraju
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 12 ++--
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..89c5249 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> (mask) << 16 | (value); })
> #define _MASKED_BIT_ENABLE(a)({ typeof(a) _a = (a);
> _MASKED_FIELD(_a, _a); })
> #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
not here
>
> /* Engine ID */
>
> @@ -4047,7 +4048,6 @@ enum {
> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
> #define EDP_PSR2_IDLE_MASK 0xf
> -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
move here
>
> #define EDP_PSR2_STATUS_CTL_MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..e505fa6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>*/
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>* mesh at all with our frontbuffer tracking. And the hw alone isn't
>* good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency) == 1) {
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
with those changes
Reviewed-by: Rodrigo Vivi
> + } else {
> + sink_latency = 0;
> + }
> + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
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[Intel-gfx] ✗ Fi.CI.IGT: failure for huge gtt pages (rev8)
== Series Details == Series: huge gtt pages (rev8) URL : https://patchwork.freedesktop.org/series/25118/ State : failure == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 Test kms_flip: Subgroup plain-flip-ts-check-interruptible: pass -> FAIL (shard-hsw) Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: skip -> PASS (shard-hsw) Test gem_flink_race: Subgroup flink_close: fail -> PASS (shard-hsw) fdo#102655 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655 shard-hswtotal:2429 pass:1334 dwarn:1 dfail:0 fail:11 skip:1083 time:9812s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5796/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] lib/igt_kms: Don't assert on non-existent plane
== Series Details == Series: series starting with [1/6] lib/igt_kms: Don't assert on non-existent plane URL : https://patchwork.freedesktop.org/series/30706/ State : success == Summary == Test gem_eio: Subgroup throttle: pass -> DMESG-WARN (shard-hsw) fdo#102886 +3 Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: skip -> PASS (shard-hsw) fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2429 pass:1329 dwarn:5 dfail:0 fail:12 skip:1083 time:9889s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_241/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Add missing BXT/CNL DPLL debugging/checking code
== Series Details == Series: Add missing BXT/CNL DPLL debugging/checking code URL : https://patchwork.freedesktop.org/series/30790/ State : failure == Summary == Series 30790v1 Add missing BXT/CNL DPLL debugging/checking code https://patchwork.freedesktop.org/api/1.0/series/30790/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-kbl-7500u) fdo#102850 Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-b-frame-sequence: dmesg-warn -> DMESG-FAIL (fi-cfl-s) fdo#102294 Subgroup nonblocking-crc-pipe-c: skip -> INCOMPLETE (fi-cfl-s) Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (fi-glk-1) fdo#102777 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:476s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:416s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:280s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:496s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:493s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:492s fi-cfl-s total:237 pass:188 dwarn:21 dfail:1 fail:0 skip:26 fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:421s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:565s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:423s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:402s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:480s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:460s fi-kbl-7500u total:118 pass:100 dwarn:1 dfail:0 fail:0 skip:16 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:539s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:752s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:573s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:419s fi-skl-gvtdvm failed to connect after reboot e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest 23ab30003948 drm/i915: add missing DPLL fields to i915_shared_dplls_info bcc58581aa9e drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5797/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code
These 2 patches just add the missing struct fields to the relevant parts of the code. Future patches could probably break those structs into per-platform struct inside an unions or something like that, but let's get this part done first. Paulo Zanoni (2): drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare drm/i915: add missing DPLL fields to i915_shared_dplls_info drivers/gpu/drm/i915/i915_debugfs.c | 16 drivers/gpu/drm/i915/intel_display.c | 12 2 files changed, 28 insertions(+) -- 2.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
Looks like we were missing them. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 026fa54..64a4105 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); + PIPE_CONF_CHECK_X(dpll_hw_state.pll0); + PIPE_CONF_CHECK_X(dpll_hw_state.pll1); + PIPE_CONF_CHECK_X(dpll_hw_state.pll2); + PIPE_CONF_CHECK_X(dpll_hw_state.pll3); + PIPE_CONF_CHECK_X(dpll_hw_state.pll6); + PIPE_CONF_CHECK_X(dpll_hw_state.pll8); + PIPE_CONF_CHECK_X(dpll_hw_state.pll9); + PIPE_CONF_CHECK_X(dpll_hw_state.pll10); + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); PIPE_CONF_CHECK_X(dsi_pll.ctrl); PIPE_CONF_CHECK_X(dsi_pll.div); -- 2.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info
Looks like we've been forgetting to add these since a long time ago. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_debugfs.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 13fc259..2b2faa6 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3481,6 +3481,22 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); + seq_printf(m, " spll:0x%08x\n", pll->state.hw_state.spll); + seq_printf(m, " ctrl1: 0x%08x\n", pll->state.hw_state.ctrl1); + seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); + seq_printf(m, " cfgcr2: 0x%08x\n", pll->state.hw_state.cfgcr2); + seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); + seq_printf(m, " ebb0:0x%08x\n", pll->state.hw_state.ebb0); + seq_printf(m, " ebb4:0x%08x\n", pll->state.hw_state.ebb4); + seq_printf(m, " pll0:0x%08x\n", pll->state.hw_state.pll0); + seq_printf(m, " pll1:0x%08x\n", pll->state.hw_state.pll1); + seq_printf(m, " pll2:0x%08x\n", pll->state.hw_state.pll2); + seq_printf(m, " pll3:0x%08x\n", pll->state.hw_state.pll3); + seq_printf(m, " pll6:0x%08x\n", pll->state.hw_state.pll6); + seq_printf(m, " pll8:0x%08x\n", pll->state.hw_state.pll8); + seq_printf(m, " pll9:0x%08x\n", pll->state.hw_state.pll9); + seq_printf(m, " pll10: 0x%08x\n", pll->state.hw_state.pll10); + seq_printf(m, " pcsdw12: 0x%08x\n", pll->state.hw_state.pcsdw12); } drm_modeset_unlock_all(dev); -- 2.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: enable userspace to program slice/subslice programming (rev2)
== Series Details == Series: drm/i915: enable userspace to program slice/subslice programming (rev2) URL : https://patchwork.freedesktop.org/series/29715/ State : failure == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: skip -> PASS (shard-hsw) Test gem_ctx_param: Subgroup invalid-param-set: pass -> FAIL (shard-hsw) Test kms_atomic_transition: Subgroup plane-all-transition-nonblocking-fencing: pass -> FAIL (shard-hsw) Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 Test gem_exec_parallel: Subgroup render-fds: pass -> INCOMPLETE (shard-hsw) fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1308 dwarn:1 dfail:0 fail:13 skip:1058 time:9646s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5795/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
Sending to intel-gfx.
>-Original Message-
>From: Ursulin, Tvrtko
>Sent: Thursday, September 21, 2017 8:16 AM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedektop.org
>Cc: Chris Wilson ; Vetter, Daniel
>; Sundaresan, Sujaritha
>; Mateo Lozano, Oscar
>; Wajdeczko, Michal
>Subject: RE: [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
>
>
>Hi,
>
>For some reason this email hasn't appeared on the mailing list so apologies
>for a
>lame Outlook reply.
Thanks Tvrtko. I corrected the address.
>I thought we agreed to use a better time source than jiffies (ktime_get()) and
>also
>that DRM_NOTE would get emitted only in the case of load time being over some
>threshold. If it is in realm of normal it should be a normal DRM_DEBUG_DRIVER.
If it is over 20 ms (the threshold) wont DRM_ERROR be a better option? If it is
within that limit, then the info will be in DRM_DEBUG_DRIVER from which the QA
can pick it.
Anusha
>Tvrtko
>
>-Original Message-
>From: Srivatsa, Anusha
>Sent: Thursday, September 21, 2017 1:44 AM
>To: intel-...@lists.freedektop.org
>Cc: Srivatsa, Anusha ; Chris Wilson wilson.co.uk>; Ursulin, Tvrtko ; Vetter, Daniel
>; Sundaresan, Sujaritha
>; Mateo Lozano, Oscar
>; Wajdeczko, Michal
>Subject: [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
>
>Calculate the time that GuC takes to load using jiffies. This information
>could be
>very useful in determining if GuC is taking unreasonably long time to load in a
>certain platforms.
>
>v2: Calculate time before logs are collected.
>Move the guc_load_time variable as a part of intel_uc_fw struct. Store only
>final
>result which is to be exported to debugfs. (Michal) Add the load time in the
>print
>message as well.
>
>v3: Remove debugfs entry. Remove local variable guc_finish_load. (Daniel,
>Tvrtko)
>
>Cc: Chris Wilson
>Cc: Tvrtko ursulin
>Cc: Daniel Vetter
>Cc: Sujaritha Sundaresan
>Cc: Oscar Mateo
>Cc: Michal Wajdeczko
>Signed-off-by: Anusha Srivatsa
>---
> drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
> drivers/gpu/drm/i915/intel_uc.h | 1 +
> 2 files changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>b/drivers/gpu/drm/i915/intel_guc_loader.c
>index 8b0ae7f..4b1fc55 100644
>--- a/drivers/gpu/drm/i915/intel_guc_loader.c
>+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>@@ -199,6 +199,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
>*dev_priv,
> struct sg_table *sg = vma->pages;
> u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> int i, ret = 0;
>+ unsigned long guc_start_load;
>
> /* where RSA signature starts */
> offset = guc_fw->rsa_offset;
>@@ -226,6 +227,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
>*dev_priv,
>
> /* Finally start the DMA */
> I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
>START_DMA));
>+ guc_start_load = jiffies;
>
> /*
>* Wait for the DMA to complete & the GuC to start up.
>@@ -237,6 +239,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
>*dev_priv,
>*/
> ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
>
>+ guc_fw->load_time = jiffies_to_msecs(jiffies - guc_start_load);
>+
> DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
> I915_READ(DMA_CTRL), status);
>
>@@ -372,6 +376,9 @@ int intel_guc_init_hw(struct intel_guc *guc)
>guc->fw.path,
>guc->fw.major_ver_found, guc->fw.minor_ver_found);
>
>+ DRM_NOTE("Time taken to load GuC is %lu ms\n",
>+ guc->fw.load_time);
>+
> return 0;
> }
>
>diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
>index 7703c9a..749b069 100644
>--- a/drivers/gpu/drm/i915/intel_uc.h
>+++ b/drivers/gpu/drm/i915/intel_uc.h
>@@ -136,6 +136,7 @@ struct intel_uc_fw {
> uint32_t rsa_offset;
> uint32_t ucode_size;
> uint32_t ucode_offset;
>+ unsigned long load_time;
> };
>
> struct intel_guc_log {
>--
>2.7.4
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [RFC,1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible
== Series Details == Series: series starting with [RFC,1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible URL : https://patchwork.freedesktop.org/series/30768/ State : failure == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: skip -> PASS (shard-hsw) Test kms_atomic_transition: Subgroup plane-all-transition-nonblocking-fencing: pass -> FAIL (shard-hsw) Test kms_draw_crc: Subgroup draw-method-xrgb-mmap-wc-xtiled: pass -> SKIP (shard-hsw) fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1330 dwarn:1 dfail:0 fail:14 skip:1084 time:9861s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5794/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 2/3] drm/i915: Extend I915_PARAMS_FOR_EACH with default member value
On Fri, 22 Sep 2017, Chris Wilson wrote: > Quoting Michal Wajdeczko (2017-09-22 15:27:25) >> By combining default value into helper macro we can initialize >> modparams struct in the same automatic way as it was declared. >> This will initialize members in the same order as declared >> and additionally will disallow declaring new member without >> proper default value for it. >> >> Signed-off-by: Michal Wajdeczko >> Cc: Chris Wilson >> Cc: Jani Nikula >> Cc: Joonas Lahtinen > > Overall, I think this is a positive change. I'm not completely happy > that the param() macro is more readable than the struct assignment, but > that is offset by the reduction in duplication. I'm also not completely happy that the default values get moved away from the param descriptions. (Hmm, what next, putting the permissions and descriptions in I915_PARAMS_FOR_EACH too?! :o) There's also the benefit of being able to highlight the changed values and displaying the defaults in debugfs if desired. On the series, Acked-by: Jani Nikula -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2) URL : https://patchwork.freedesktop.org/series/30669/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-blt: skip -> PASS (shard-hsw) Test gem_flink_race: Subgroup flink_close: fail -> PASS (shard-hsw) fdo#102655 Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2429 pass:1333 dwarn:1 dfail:0 fail:12 skip:1083 time:9808s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5793/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix SSEU Device Status.
On Fri, Sep 22, 2017 at 04:44:38PM +, Oscar Mateo wrote:
>
>
> On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
> > CNL adds an extra register for slice/subslice information.
> > Although no SKU is planed with an extra slice let's already
> > handle this extra piece of information so we don't have the
> > risk in future of getting a part that might have chosen this
> > part of the die instead of other slices or anything like that.
> >
> > Also if subslice is disabled the information of eu ack for that
> > is garbage, so let's skip checks for eu if subslice is disabled
> > as we skip the subslice if slice is disabled.
> >
> > The rest is pretty much like gen9.
> >
> > v2: Remove IS_CANNONLAKE from gen9 status function.
> >
> > v3: Consider s_max = 6 and ss_max=4 to run over all possible
> > slices and subslices possible by spec. Although no real
> > hardware will have that many slices/subslices.
> > To match with sseu info init.
> > v4: Fix offset calculation for slices 4 and 5.
> > Removed Oscar's rv-b since this change also needs review.
> >
> > Cc: Oscar Mateo
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 54
> > +++--
> > drivers/gpu/drm/i915/i915_reg.h | 6 +
> > 2 files changed, 58 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index ca6fa6d122c6..e197e5d99277 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct
> > drm_i915_private *dev_priv,
> > }
> > }
> > +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> > +struct sseu_dev_info *sseu)
> > +{
> > + const struct intel_device_info *info = INTEL_INFO(dev_priv);
> > + int s_max = 6, ss_max = 4;
> > + int s, ss;
> > + u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> > +
> > + for (s = 0; s < s_max; s++) {
> > + s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> > + eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> > + eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> > + }
> > +
> > + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> > +GEN9_PGCTL_SSA_EU19_ACK |
> > +GEN9_PGCTL_SSA_EU210_ACK |
> > +GEN9_PGCTL_SSA_EU311_ACK;
> > + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> > +GEN9_PGCTL_SSB_EU19_ACK |
> > +GEN9_PGCTL_SSB_EU210_ACK |
> > +GEN9_PGCTL_SSB_EU311_ACK;
> > +
> > + for (s = 0; s < s_max; s++) {
> > + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> > + /* skip disabled slice */
> > + continue;
> > +
> > + sseu->slice_mask |= BIT(s);
> > + sseu->subslice_mask = info->sseu.subslice_mask;
> > +
> > + for (ss = 0; ss < ss_max; ss++) {
> > + unsigned int eu_cnt;
> > +
> > + if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
> > + /* skip disabled subslice */
> > + continue;
>
> You are going to hate me, but I found something else:
Should I hate you for being a good reviewer? ;)
You should hate me for not noticing that before...
Thanks a lot for the patience
>
> SLICE0_PGCTL_ACK has powergate acknowledge bits for subslices 0, 1 & 2, but
> not for subslice 3
> SLICEn_PGCTL_ACK (where n = 1-5) has powergate acknowledge bits for
> subslices 0 & 1, but not for subslices 2 & 3
hmmm... :(
I will check...
>
> I have no idea where the missing bits went (maybe the BSpec is wrong?).
Do you know anyone at your end that could help us to clarify that?
Thanks,
Rodrigo.
>
> > +
> > + eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> > + eu_mask[ss % 2]);
> > + sseu->eu_total += eu_cnt;
> > + sseu->eu_per_subslice = max_t(unsigned int,
> > + sseu->eu_per_subslice,
> > + eu_cnt);
> > + }
> > + }
> > +}
> > +
> > static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> > struct sseu_dev_info *sseu)
> > {
> > @@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct
> > drm_i915_private *dev_priv,
> > sseu->slice_mask |= BIT(s);
> > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> > + if (IS_GEN9_BC(dev_priv))
> > sseu->subslice_mask =
> > INTEL_INFO(dev_priv)->sseu.subslice_mask;
> > @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void
> > *unused)
> > cherryview_sseu_device_status(dev_priv, &sseu);
>
Re: [Intel-gfx] [PATCH 19/21] drm/i915: disable platform support for vGPU huge gtt pages
On 2017.09.22 18:32:50 +0100, Matthew Auld wrote:
> Currently gvt gtt handling doesn't support huge page entries, so disable
> for now.
>
> v2: remove useless 48b PPGTT check
>
> Suggested-by: Zhenyu Wang
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Zhenyu Wang
> ---
> drivers/gpu/drm/i915/i915_gem.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 750c04002304..f98d8a08167b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>
> mutex_lock(&dev_priv->drm.struct_mutex);
>
> + /* We need to fallback to 4K pages since gvt gtt handling doesn't
> + * support huge page entries - we will need to check either hypervisor
> + * mm can support huge guest page or just do emulation in gvt.
> + */
> + if (intel_vgpu_active(dev_priv))
> + mkwrite_device_info(dev_priv)->page_sizes =
> + I915_GTT_PAGE_SIZE_4K;
> +
> dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
>
> if (!i915_modparams.enable_execlists) {
> --
> 2.13.5
>
Reviewed-by: Zhenyu Wang
thanks
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[Intel-gfx] ✓ Fi.CI.BAT: success for huge gtt pages (rev8)
== Series Details == Series: huge gtt pages (rev8) URL : https://patchwork.freedesktop.org/series/25118/ State : success == Summary == Series 25118v8 huge gtt pages https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/8/mbox/ Test chamelium: Subgroup common-hpd-after-suspend: dmesg-warn -> INCOMPLETE (fi-kbl-7500u) fdo#102505 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (fi-glk-1) fdo#102777 fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:422s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:524s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:273s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:497s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:490s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:538s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:567s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:431s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:493s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:9pass:3dwarn:0 dfail:0 fail:0 skip:5 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:579s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:583s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:541s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:458s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:752s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:473s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:568s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:418s e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest fafcc7641de1 drm/i915: enable platform support for 2M pages 0843fe3f3920 drm/i915: enable platform support for 64K pages 4789d9fc4867 drm/i915: disable platform support for vGPU huge gtt pages 6fd60979baf8 drm/i915/selftests: mix huge pages f55bd2a1bc16 drm/i915/selftests: huge page tests 9d27d66adbaa drm/i915/debugfs: include some gtt page size metrics 78507af39439 drm/i915: accurate page size tracking for the ppgtt b9d8182acd0e drm/i915: support 64K pages for the 48b PPGTT ad258a420212 drm/i915: add support for 64K scratch page c85ffe144db8 drm/i915: support 2M pages for the 48b PPGTT b2a0ef69b032 drm/i915: disable GTT cache for 2M pages 3ecbcf4bae2e drm/i915: enable IPS bit for 64K pages 921f83b3b726 drm/i915: align 64K objects to 2M 3bc740d468a9 drm/i915: align the vma start to the largest gtt page size 406d01e9a408 drm/i915: introduce vm set_pages/clear_pages 4f583f3fa7d3 drm/i915: introduce page_size members 1d8bc4028cc3 drm/i915: push set_pages down to the callers a4a00da9f6e4 drm/i915: introduce page_sizes field to dev_info 2b4997d0cf32 drm/i915/gemfs: enable THP 34579418914a drm/i915: introduce simple gemfs a20198f8fbe2 mm/shmem: introduce shmem_file_setup_with_mnt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5796/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/dp: Clean up intel_dp_check_mst_status
On Thu, Sep 21, 2017 at 11:54 AM, Dhinakaran Pandiyan
wrote:
> Rewriting this code without the goto, I believe, makes it more readable.
> One functional change that has been included is the handling of failed ESI
> register reads. Instead of disabling MST only for the first failed read, we
> now disable MST on subsequent failed reads too. A failed ESI read is
> problematic irrespective of whether it is the first or not.
>
> v2: Don't ignore return from _mst_hpd_irq() (James)
>
> Cc: James Ausmus
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: James Ausmus
> ---
> drivers/gpu/drm/i915/intel_dp.c | 78
> ++---
> 1 file changed, 34 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 98e7b96ca826..aa97bd825369 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4191,57 +4191,47 @@ static void intel_dp_handle_test_request(struct
> intel_dp *intel_dp)
> static int
> intel_dp_check_mst_status(struct intel_dp *intel_dp)
> {
> - bool bret;
> + u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>
> - if (intel_dp->is_mst) {
> - u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> - int ret = 0;
> - int retry;
> + if (!intel_dp->is_mst)
> + return -EINVAL;
> +
> + while (intel_dp_get_sink_irq_esi(intel_dp, esi)) {
> + int ret, retry;
> bool handled;
> - bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> -go_again:
> - if (bret == true) {
> -
> - /* check link status - esi[10] = 0x200c */
> - if (intel_dp->active_mst_links &&
> - !drm_dp_channel_eq_ok(&esi[10],
> intel_dp->lane_count)) {
> - DRM_DEBUG_KMS("channel EQ not ok,
> retraining\n");
> - intel_dp_start_link_train(intel_dp);
> - intel_dp_stop_link_train(intel_dp);
> - }
>
> - DRM_DEBUG_KMS("got esi %3ph\n", esi);
> - ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi,
> &handled);
> -
> - if (handled) {
> - for (retry = 0; retry < 3; retry++) {
> - int wret;
> - wret =
> drm_dp_dpcd_write(&intel_dp->aux,
> -
> DP_SINK_COUNT_ESI+1,
> -&esi[1], 3);
> - if (wret == 3) {
> - break;
> - }
> - }
> + DRM_DEBUG_KMS("ESI %3ph\n", esi);
>
> - bret = intel_dp_get_sink_irq_esi(intel_dp,
> esi);
> - if (bret == true) {
> - DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
> - goto go_again;
> - }
> - } else
> - ret = 0;
> + /* check link status - esi[10] = 0x200c */
> + if (intel_dp->active_mst_links &&
> + !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
> + intel_dp_start_link_train(intel_dp);
> + intel_dp_stop_link_train(intel_dp);
> + }
>
> - return ret;
> - } else {
> - struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> - DRM_DEBUG_KMS("failed to get ESI - device may have
> failed\n");
> - intel_dp->is_mst = false;
> - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> intel_dp->is_mst);
> - /* send a hotplug event */
> -
> drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
> + ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
> + if (!handled)
> + return 0;
> +
> + if (ret)
> + DRM_DEBUG_KMS("error handling MST IRQ_HPD %d\n", ret);
> +
> + for (retry = 0; retry < 3; retry++) {
> + int wret;
> +
> + wret = drm_dp_dpcd_write(&intel_dp->aux,
> +DP_SINK_COUNT_ESI + 1,
> &esi[1],
> +3);
> + if (wret == 3)
> + break;
> }
>
Re: [Intel-gfx] [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly
Thanks for the reply. Learned a lot. :) GEM_BUG_ON is new to me since it wasn't there at the beginning of GVT-g upstream. It showed up later. So I left a lot of WARN_ON in the code and some of them should be GEM_BUG_ON now. Now I can figure out those differences. We can discuss with our QA to see if they would like to enable I915_GEM_DEBUG and then we can move to GEM_BUG_ON also, or maybe we can have a dedicated GVT_BUG_ON. :) Thank you so much. Have a great weekend. Thanks, Zhi. -Original Message- From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] Sent: Friday, September 22, 2017 2:11 PM To: Wang, Zhi A ; Zhenyu Wang ; Joe Perches Cc: Gao, Fred ; David Airlie ; intel-gfx@lists.freedesktop.org; kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org; Jani Nikula ; dri-de...@lists.freedesktop.org; Vivi, Rodrigo ; Colin King ; intel-gvt-...@lists.freedesktop.org Subject: Re: [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly On Thu, 2017-09-21 at 16:17 +, Wang, Zhi A wrote: > Hi Joonas: > > Thanks for the introduction. I have been thinking about the > possibility of introducing GEM_BUG_ON into GVT-g recently and > investigating on it. I'm just a bit confused about the usage between > GEM_BUG_ON and WARN_ON. GEM_BUG_ON is basically there to catch things that we do not expect ever to happen within the driver. So we often list the function preconditions as GEM_BUG_ON. It's there for the same reason as the lockdep_assert_held and KASAN. It's sometimes heavy checks that we really want to run when functionally validating kernel. GEM_BUG_ON became to existence because adding checks for obvious conditions at the critical command submission path GEM is not sustainable for performance in production. The expectation is that each GEM_BUG_ON has a testcase in I-G-T that has the potential to hit it if driver was modified not to respect those preconditions. So once our testest passes, we can disable the GEM_BUG_ONs and be confident of the internal driver quality and get the release performance. WARN_ON is mostly used for the cases when the hardware is behaving differently than we expect. We can't remove them as we don't have all the hardware in the world to test, but we try to exercise them too through I-G-Ts. The test will often be the subtest that was written to reproduce the problem with our expectations of hardware in case of hangs and other bugs. After we've corrected the driver behaviour, or got a hardware W/A assigned, we keep the test and add a WARN_ON to make sure there will be no regression back to the same situation. This is at least what should happen, given time constraints, there may be variations. User behaving unexpectedly should never result in WARN_ON (or even worse, BUG_ON), should always just be debug messages displayed (not to trigger the CI) and errors propagated back to user: https://01.org/linuxgraphics/gfx-docs/drm/gpu/drm-uapi.html#recommended -ioctl-return-values Bare BUG_ON should only be used when there's the danger of corrupting system memory or filesystems, so from graphics driver, that's not very often. Controlled propagation of errors and maybe WARN_ON is always preferred if possible. > GEM_BUG_ON is only enabled when kernel debug is enabled, which mostly > is disabled in a production kernel. In the case of i915, I'm sure it > will be enabled in CI test so that it can catch broken code path. > Looking into GVT-g, the similar scenario is we enable it in QA test. > > Let's say GEM_BUG_ON can do its work very well in QA test but QA test > is not fully covered all the condition, then something might be still > broken when it comes to the production kernel for user and GEM_BUG_ON > will be disabled and will not catch that, I guess. > > That's my confusion which scratched my mind during the investigation: > If GEM_BUG_ON is not always working, then it looks WARN_ON should > always be used Expected to learn more about the story behind. :) So if the saying is some object is "never going to be bigger than 2G", there should be either: 1. GEM_BUG_ON like assertion for it and a test that tries to hit it, by trying to allocate a huge object for example, and should get rejection as -EINVAL 2. Test to see if the object is bigger, and propagate back the error if it is. Either resulting in user reported error if the origin of the object is outside of kernel <-> hardware. Or a WARN_ON if it's strange hardware or kernel driver behavior. You should choose depending on how often your function gets called, and how critical the execution time is. Hopefully this clarified things. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/21] drm/i915: enable IPS bit for 64K pages
Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.
v2: add comment mentioning that 64K is BDW+
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 16
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ae7b683437f1..2fab70ad169e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4755,6 +4755,22 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
+ /* To support 64K PTEs we need to first enable the use of the
+* Intermediate-Page-Size(IPS) bit of the PDE field via some magical
+* mmio, otherwise the page-walker will simply ignore the IPS bit. This
+* shouldn't be needed after GEN10.
+*
+* 64K pages were first introduced from BDW+, although technically they
+* only *work* from gen9+. For pre-BDW we instead have the option for
+* 32K pages, but we don't currently have any support for it in our
+* driver.
+*/
+ if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
+ INTEL_GEN(dev_priv) <= 10)
+ I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
+ I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
+ GAMW_ECO_ENABLE_64K_IPS_FIELD);
+
i915_gem_init_swizzling(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd0cd94..6fdcaec0e2ee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2371,6 +2371,9 @@ enum i915_power_well_id {
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
+#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
+#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
+
#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
--
2.13.5
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[Intel-gfx] [PATCH 14/21] drm/i915: support 64K pages for the 48b PPGTT
Support inserting 64K pages into the 48b PPGTT.
v2: check for 64K scratch
v3: we should only have to re-adjust maybe_64K at every sg interval
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 30 ++
drivers/gpu/drm/i915/i915_gem_gtt.h | 7 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e4d59a592a88..252e36b3ca02 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1068,6 +1068,7 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
unsigned int page_size;
+ bool maybe_64K = false;
gen8_pte_t encode = pte_encode;
gen8_pte_t *vaddr;
u16 index, max;
@@ -1089,6 +1090,13 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
max = GEN8_PTES;
page_size = I915_GTT_PAGE_SIZE;
+ if (!index &&
+ vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
+ IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
+ (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
+rem >= (max - index) << PAGE_SHIFT))
+ maybe_64K = true;
+
vaddr = kmap_atomic_px(pt);
}
@@ -1108,6 +1116,12 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
iter->dma = sg_dma_address(iter->sg);
iter->max = iter->dma + rem;
+ if (maybe_64K && index < max &&
+ !(IS_ALIGNED(iter->dma,
I915_GTT_PAGE_SIZE_64K) &&
+ (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K)
||
+ rem >= (max - index) << PAGE_SHIFT)))
+ maybe_64K = false;
+
if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
break;
}
@@ -1116,6 +1130,22 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
kunmap_atomic(vaddr);
+ /* Is it safe to mark the 2M block as 64K? -- Either we have
+* filled whole page-table with 64K entries, or filled part of
+* it and have reached the end of the sg table and we have
+* enough padding.
+*/
+ if (maybe_64K &&
+ (index == max ||
+(i915_vm_has_scratch_64K(vma->vm) &&
+ !iter->sg && IS_ALIGNED(vma->node.start +
+ vma->node.size,
+ I915_GTT_PAGE_SIZE_2M {
+ vaddr = kmap_atomic_px(pd);
+ vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
+ kunmap_atomic(vaddr);
+ }
+
} while (iter->sg);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 0a31dc369c28..475e4cf042be 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -153,6 +153,7 @@ typedef u64 gen8_ppgtt_pml4e_t;
#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
+#define GEN8_PDE_IPS_64K BIT(11)
#define GEN8_PDE_PS_2M BIT(7)
struct sg_table;
@@ -351,6 +352,12 @@ i915_vm_is_48bit(const struct i915_address_space *vm)
return (vm->total - 1) >> 32;
}
+static inline bool
+i915_vm_has_scratch_64K(struct i915_address_space *vm)
+{
+ return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K);
+}
+
/* The Graphics Translation Table is the way in which GEN hardware translates a
* Graphics Virtual Address into a Physical Address. In addition to the normal
* collateral associated with any va->pa translations GEN hardware also has a
--
2.13.5
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[Intel-gfx] [PATCH 20/21] drm/i915: enable platform support for 64K pages
For gen9+ enable platform level support for 64K pages. Also enable for
mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 84cdab3c5f09..9da69cb55302 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -434,7 +434,8 @@ static const struct intel_device_info intel_cherryview_info
__initconst = {
};
#define GEN9_DEFAULT_PAGE_SIZES \
- .page_sizes = I915_GTT_PAGE_SIZE_4K
+ .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_64K
#define SKL_PLATFORM \
BDW_FEATURES, \
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 1785c63ad797..8a5a42ea1c98 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -175,7 +175,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->gen = -1;
mkwrite_device_info(i915)->page_sizes =
- I915_GTT_PAGE_SIZE_4K;
+ I915_GTT_PAGE_SIZE_4K |
+ I915_GTT_PAGE_SIZE_64K;
spin_lock_init(&i915->mm.object_stat_lock);
mock_uncore_init(i915);
--
2.13.5
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[Intel-gfx] [PATCH 21/21] drm/i915: enable platform support for 2M pages
For gen8+ platforms which support the 48b PPGTT, enable platform level
support for 2M pages. Also enable for mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9da69cb55302..ad07f7075f29 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -374,7 +374,8 @@ static const struct intel_device_info
intel_haswell_gt3_info __initconst = {
#define BDW_FEATURES \
HSW_FEATURES, \
BDW_COLORS, \
- GEN_DEFAULT_PAGE_SIZES, \
+ .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1, \
@@ -435,7 +436,8 @@ static const struct intel_device_info intel_cherryview_info
__initconst = {
#define GEN9_DEFAULT_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_64K
+ I915_GTT_PAGE_SIZE_64K | \
+ I915_GTT_PAGE_SIZE_2M
#define SKL_PLATFORM \
BDW_FEATURES, \
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8a5a42ea1c98..39556a5979d4 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -176,7 +176,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->page_sizes =
I915_GTT_PAGE_SIZE_4K |
- I915_GTT_PAGE_SIZE_64K;
+ I915_GTT_PAGE_SIZE_64K |
+ I915_GTT_PAGE_SIZE_2M;
spin_lock_init(&i915->mm.object_stat_lock);
mock_uncore_init(i915);
--
2.13.5
___
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[Intel-gfx] [PATCH 17/21] drm/i915/selftests: huge page tests
v2: mock test page support configurations and add MI_STORE_DWORD test
v3: run all mockable huge page tests on all platforms via the mock_device
v4: add pin_update regression test
various improvements suggested by Chris
v5: fix issues reported by kbuild
test single sg spanning multiple page sizes
don't explode when running the live-tests through the appgtt
v6: lots of improvements from Chris
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c|1 +
drivers/gpu/drm/i915/i915_gem_object.h |2 +
drivers/gpu/drm/i915/selftests/huge_pages.c| 1636
.../gpu/drm/i915/selftests/i915_live_selftests.h |1 +
.../gpu/drm/i915/selftests/i915_mock_selftests.h |1 +
5 files changed, 1641 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/huge_pages.c
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2fab70ad169e..750c04002304 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5419,6 +5419,7 @@ int i915_gem_object_attach_phys(struct
drm_i915_gem_object *obj, int align)
#include "selftests/scatterlist.c"
#include "selftests/mock_gem_device.c"
#include "selftests/huge_gem_object.c"
+#include "selftests/huge_pages.c"
#include "selftests/i915_gem_object.c"
#include "selftests/i915_gem_coherency.c"
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index e4e6dd93889d..956c911c2cbf 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -196,6 +196,8 @@ struct drm_i915_gem_object {
unsigned int gtt;
} page_sizes;
+ I915_SELFTEST_DECLARE(unsigned int page_mask);
+
struct i915_gem_object_page_iter {
struct scatterlist *sg_pos;
unsigned int sg_idx; /* in pages, but 32bit eek! */
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
new file mode 100644
index ..8e670405a1f9
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -0,0 +1,1636 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "../i915_selftest.h"
+
+#include
+
+#include "mock_drm.h"
+
+static const unsigned int page_sizes[] = {
+ I915_GTT_PAGE_SIZE_2M,
+ I915_GTT_PAGE_SIZE_64K,
+ I915_GTT_PAGE_SIZE_4K,
+};
+
+static unsigned int get_largest_page_size(struct drm_i915_private *i915,
+ size_t rem)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(page_sizes); ++i) {
+ unsigned int page_size = page_sizes[i];
+
+ if (HAS_PAGE_SIZES(i915, page_size) && rem >= page_size)
+ return page_size;
+ }
+
+ return 0;
+}
+
+static void huge_pages_free_pages(struct sg_table *st)
+{
+ struct scatterlist *sg;
+
+ for (sg = st->sgl; sg; sg = __sg_next(sg)) {
+ if (sg_page(sg))
+ __free_pages(sg_page(sg), get_order(sg->length));
+ }
+
+ sg_free_table(st);
+ kfree(st);
+}
+
+static int get_huge_pages(struct drm_i915_gem_object *obj)
+{
+#define GFP (GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY)
+ unsigned int page_mask = obj->mm.page_mask;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_mask;
+ u64 rem;
+
+ st = kmalloc(sizeof(*st), GFP);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, obj->base.size >> PAGE_SHIFT, GFP)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ rem = obj->base.size;
+ sg = st->sgl;
+ st->nents = 0;
+ s
[Intel-gfx] [PATCH 16/21] drm/i915/debugfs: include some gtt page size metrics
Good to know, mostly for debugging purposes.
v2: some improvements from Chris
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 61 ++---
1 file changed, 57 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13fc25997d65..083ef6354ace 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -118,6 +118,36 @@ static u64 i915_gem_obj_total_ggtt_size(struct
drm_i915_gem_object *obj)
return size;
}
+static const char *
+stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
+{
+ size_t x = 0;
+
+ switch (page_sizes) {
+ case 0:
+ return "";
+ case I915_GTT_PAGE_SIZE_4K:
+ return "4K";
+ case I915_GTT_PAGE_SIZE_64K:
+ return "64K";
+ case I915_GTT_PAGE_SIZE_2M:
+ return "2M";
+ default:
+ if (!buf)
+ return "M";
+
+ if (page_sizes & I915_GTT_PAGE_SIZE_2M)
+ x += snprintf(buf + x, len - x, "2M, ");
+ if (page_sizes & I915_GTT_PAGE_SIZE_64K)
+ x += snprintf(buf + x, len - x, "64K, ");
+ if (page_sizes & I915_GTT_PAGE_SIZE_4K)
+ x += snprintf(buf + x, len - x, "4K, ");
+ buf[x-2] = '\0';
+
+ return buf;
+ }
+}
+
static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
@@ -155,9 +185,10 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
if (!drm_mm_node_allocated(&vma->node))
continue;
- seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
+ seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
i915_vma_is_ggtt(vma) ? "g" : "pp",
- vma->node.start, vma->node.size);
+ vma->node.start, vma->node.size,
+ stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
if (i915_vma_is_ggtt(vma)) {
switch (vma->ggtt_view.type) {
case I915_GGTT_VIEW_NORMAL:
@@ -402,10 +433,12 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_device *dev = &dev_priv->drm;
struct i915_ggtt *ggtt = &dev_priv->ggtt;
- u32 count, mapped_count, purgeable_count, dpy_count;
- u64 size, mapped_size, purgeable_size, dpy_size;
+ u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
+ u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
struct drm_i915_gem_object *obj;
+ unsigned int page_sizes = 0;
struct drm_file *file;
+ char buf[80];
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -419,6 +452,7 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
size = count = 0;
mapped_size = mapped_count = 0;
purgeable_size = purgeable_count = 0;
+ huge_size = huge_count = 0;
list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
size += obj->base.size;
++count;
@@ -432,6 +466,12 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
mapped_count++;
mapped_size += obj->base.size;
}
+
+ if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
+ huge_count++;
+ huge_size += obj->base.size;
+ page_sizes |= obj->mm.page_sizes.sg;
+ }
}
seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
@@ -454,6 +494,12 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
mapped_count++;
mapped_size += obj->base.size;
}
+
+ if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
+ huge_count++;
+ huge_size += obj->base.size;
+ page_sizes |= obj->mm.page_sizes.sg;
+ }
}
seq_printf(m, "%u bound objects, %llu bytes\n",
count, size);
@@ -461,11 +507,18 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
purgeable_count, purgeable_size);
seq_printf(m, "%u mapped objects, %llu bytes\n",
mapped_count, mapped_size);
+ seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
+ huge_count,
+ stringify_page_sizes(page_sizes, buf, sizeof(buf)),
+ huge_size);
seq_printf(m, "%u display objects (
[Intel-gfx] [PATCH 18/21] drm/i915/selftests: mix huge pages
Try to mix sg page sizes for 4K, 64K and 2M pages.
v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/scatterlist.c
b/drivers/gpu/drm/i915/selftests/scatterlist.c
index 1cc5d2931753..cd6d2a16071f 100644
--- a/drivers/gpu/drm/i915/selftests/scatterlist.c
+++ b/drivers/gpu/drm/i915/selftests/scatterlist.c
@@ -189,6 +189,20 @@ static unsigned int random(unsigned long n,
return 1 + (prandom_u32_state(rnd) % 1024);
}
+static unsigned int random_page_size_pages(unsigned long n,
+ unsigned long count,
+ struct rnd_state *rnd)
+{
+ /* 4K, 64K, 2M */
+ static unsigned int page_count[] = {
+ BIT(12) >> PAGE_SHIFT,
+ BIT(16) >> PAGE_SHIFT,
+ BIT(21) >> PAGE_SHIFT,
+ };
+
+ return page_count[(prandom_u32_state(rnd) % 3)];
+}
+
static inline bool page_contiguous(struct page *first,
struct page *last,
unsigned long npages)
@@ -252,6 +266,7 @@ static const npages_fn_t npages_funcs[] = {
grow,
shrink,
random,
+ random_page_size_pages,
NULL,
};
--
2.13.5
___
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[Intel-gfx] [PATCH 19/21] drm/i915: disable platform support for vGPU huge gtt pages
Currently gvt gtt handling doesn't support huge page entries, so disable
for now.
v2: remove useless 48b PPGTT check
Suggested-by: Zhenyu Wang
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Zhenyu Wang
---
drivers/gpu/drm/i915/i915_gem.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 750c04002304..f98d8a08167b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
+ /* We need to fallback to 4K pages since gvt gtt handling doesn't
+* support huge page entries - we will need to check either hypervisor
+* mm can support huge guest page or just do emulation in gvt.
+*/
+ if (intel_vgpu_active(dev_priv))
+ mkwrite_device_info(dev_priv)->page_sizes =
+ I915_GTT_PAGE_SIZE_4K;
+
dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
if (!i915_modparams.enable_execlists) {
--
2.13.5
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[Intel-gfx] [PATCH 11/21] drm/i915: disable GTT cache for 2M pages
When SW enables the use of 2M/1G pages, it must disable the GTT cache. v2: don't disable for Cherryview which doesn't even support 48b PPGTT! v3: explicitly check that the system does support 2M/1G pages Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c66af09e27a7..719a1c5f1ffa 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8483,10 +8483,12 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) /* * WaGttCachingOffByDefault:bdw -* GTT cache may not work with big pages, so if those -* are ever enabled GTT cache may need to be disabled. +* The GTT cache must be disabled if the system is planning to use +* 2M/1G pages. */ - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); + I915_WRITE(HSW_GTT_CACHE_EN, + HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M) ? 0 : + GTT_CACHE_EN_ALL); /* WaKVMNotificationOnConfigChange:bdw */ I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/21] drm/i915: accurate page size tracking for the ppgtt
Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 11 +++
drivers/gpu/drm/i915/i915_gem_object.h | 10 ++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 252e36b3ca02..631baa67dc9a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1052,6 +1052,8 @@ static void gen8_ppgtt_insert_3lvl(struct
i915_address_space *vm,
gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
cache_level);
+
+ vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
}
static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
@@ -1144,8 +1146,11 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
vaddr = kmap_atomic_px(pd);
vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
kunmap_atomic(vaddr);
+ page_size = I915_GTT_PAGE_SIZE_64K;
}
+ vma->page_sizes.gtt |= page_size;
+
} while (iter->sg);
}
@@ -1170,6 +1175,8 @@ static void gen8_ppgtt_insert_4lvl(struct
i915_address_space *vm,
while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
&iter, &idx, cache_level))
GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+
+ vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
}
}
@@ -1891,6 +1898,8 @@ static void gen6_ppgtt_insert_entries(struct
i915_address_space *vm,
}
} while (1);
kunmap_atomic(vaddr);
+
+ vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
}
static int gen6_alloc_va_range(struct i915_address_space *vm,
@@ -2581,6 +2590,8 @@ static int ggtt_bind_vma(struct i915_vma *vma,
vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
intel_runtime_pm_put(i915);
+ vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+
/*
* Without aliasing PPGTT there's no difference between
* GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index 110672952a1c..e4e6dd93889d 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -169,6 +169,7 @@ struct drm_i915_gem_object {
struct sg_table *pages;
void *mapping;
+ /* TODO: whack some of this into the error state */
struct i915_page_sizes {
/**
* The sg mask of the pages sg_table. i.e the mask of
@@ -184,6 +185,15 @@ struct drm_i915_gem_object {
* to use opportunistically.
*/
unsigned int sg;
+
+ /**
+* The actual gtt page size usage. Since we can have
+* multiple vma associated with this object we need to
+* prevent any trampling of state, hence a copy of this
+* struct also lives in each vma, therefore the gtt
+* value here should only be read/write through the vma.
+*/
+ unsigned int gtt;
} page_sizes;
struct i915_gem_object_page_iter {
--
2.13.5
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[Intel-gfx] [PATCH 13/21] drm/i915: add support for 64K scratch page
Before we can fully enable 64K pages, we need to first support a 64K
scratch page if we intend to support the case where we have object sizes
< 2M, since any scratch PTE must also point to a 64K region. Without
this our 64K usage is limited to objects which completely fill the
page-table, and therefore don't need any scratch.
v2: add reminder about why 48b PPGTT
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 60 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 50 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8cdb5361b582..e4d59a592a88 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -522,22 +522,59 @@ static void fill_page_dma_32(struct i915_address_space
*vm,
static int
setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
- struct page *page;
+ struct page *page = NULL;
dma_addr_t addr;
+ int order;
- page = alloc_page(gfp | __GFP_ZERO);
- if (unlikely(!page))
- return -ENOMEM;
+ /* In order to utilize 64K pages for an object with a size < 2M, we will
+* need to support a 64K scratch page, given that every 16th entry for a
+* page-table operating in 64K mode must point to a properly aligned 64K
+* region, including any PTEs which happen to point to scratch.
+*
+* This is only relevant for the 48b PPGTT where we support
+* huge-gtt-pages, see also i915_vma_insert().
+*/
+ if (i915_vm_is_48bit(vm) &&
+ HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
+ order = get_order(I915_GTT_PAGE_SIZE_64K);
+ page = alloc_pages(gfp | __GFP_ZERO, order);
+ if (page) {
+ addr = dma_map_page(vm->dma, page, 0,
+ I915_GTT_PAGE_SIZE_64K,
+ PCI_DMA_BIDIRECTIONAL);
+ if (unlikely(dma_mapping_error(vm->dma, addr))) {
+ __free_pages(page, order);
+ page = NULL;
+ }
- addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE,
- PCI_DMA_BIDIRECTIONAL);
- if (unlikely(dma_mapping_error(vm->dma, addr))) {
- __free_page(page);
- return -ENOMEM;
+ if (!IS_ALIGNED(addr, I915_GTT_PAGE_SIZE_64K)) {
+ dma_unmap_page(vm->dma, addr,
+ I915_GTT_PAGE_SIZE_64K,
+ PCI_DMA_BIDIRECTIONAL);
+ __free_pages(page, order);
+ page = NULL;
+ }
+ }
+ }
+
+ if (!page) {
+ order = 0;
+ page = alloc_page(gfp | __GFP_ZERO);
+ if (unlikely(!page))
+ return -ENOMEM;
+
+ addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE,
+ PCI_DMA_BIDIRECTIONAL);
+ if (unlikely(dma_mapping_error(vm->dma, addr))) {
+ __free_page(page);
+ return -ENOMEM;
+ }
}
vm->scratch_page.page = page;
vm->scratch_page.daddr = addr;
+ vm->scratch_page.order = order;
+
return 0;
}
@@ -545,8 +582,9 @@ static void cleanup_scratch_page(struct i915_address_space
*vm)
{
struct i915_page_dma *p = &vm->scratch_page;
- dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- __free_page(p->page);
+ dma_unmap_page(vm->dma, p->daddr, BIT(p->order) << PAGE_SHIFT,
+ PCI_DMA_BIDIRECTIONAL);
+ __free_pages(p->page, p->order);
}
static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index e9e66abbe532..0a31dc369c28 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -214,6 +214,7 @@ struct i915_vma;
struct i915_page_dma {
struct page *page;
+ int order;
union {
dma_addr_t daddr;
--
2.13.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/21] mm/shmem: introduce shmem_file_setup_with_mnt
We are planning to use our own tmpfs mnt in i915 in place of the
shm_mnt, such that we can control the mount options, in particular
huge=, which we require to support huge-gtt-pages. So rather than roll
our own version of __shmem_file_setup, it would be preferred if we could
just give shmem our mnt, and let it do the rest.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Dave Hansen
Cc: Kirill A. Shutemov
Cc: Hugh Dickins
Cc: linux...@kvack.org
Acked-by: Andrew Morton
Acked-by: Kirill A. Shutemov
Reviewed-by: Joonas Lahtinen
---
include/linux/shmem_fs.h | 2 ++
mm/shmem.c | 30 ++
2 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h
index b6c3540e07bc..0937d9a7d8fb 100644
--- a/include/linux/shmem_fs.h
+++ b/include/linux/shmem_fs.h
@@ -53,6 +53,8 @@ extern struct file *shmem_file_setup(const char *name,
loff_t size, unsigned long flags);
extern struct file *shmem_kernel_file_setup(const char *name, loff_t size,
unsigned long flags);
+extern struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt,
+ const char *name, loff_t size, unsigned long flags);
extern int shmem_zero_setup(struct vm_area_struct *);
extern unsigned long shmem_get_unmapped_area(struct file *, unsigned long addr,
unsigned long len, unsigned long pgoff, unsigned long flags);
diff --git a/mm/shmem.c b/mm/shmem.c
index 07a1d22807be..3229d27503ec 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -4183,7 +4183,7 @@ static const struct dentry_operations anon_ops = {
.d_dname = simple_dname
};
-static struct file *__shmem_file_setup(const char *name, loff_t size,
+static struct file *__shmem_file_setup(struct vfsmount *mnt, const char *name,
loff_t size,
unsigned long flags, unsigned int
i_flags)
{
struct file *res;
@@ -4192,8 +4192,8 @@ static struct file *__shmem_file_setup(const char *name,
loff_t size,
struct super_block *sb;
struct qstr this;
- if (IS_ERR(shm_mnt))
- return ERR_CAST(shm_mnt);
+ if (IS_ERR(mnt))
+ return ERR_CAST(mnt);
if (size < 0 || size > MAX_LFS_FILESIZE)
return ERR_PTR(-EINVAL);
@@ -4205,8 +4205,8 @@ static struct file *__shmem_file_setup(const char *name,
loff_t size,
this.name = name;
this.len = strlen(name);
this.hash = 0; /* will go */
- sb = shm_mnt->mnt_sb;
- path.mnt = mntget(shm_mnt);
+ sb = mnt->mnt_sb;
+ path.mnt = mntget(mnt);
path.dentry = d_alloc_pseudo(sb, &this);
if (!path.dentry)
goto put_memory;
@@ -4251,7 +4251,7 @@ static struct file *__shmem_file_setup(const char *name,
loff_t size,
*/
struct file *shmem_kernel_file_setup(const char *name, loff_t size, unsigned
long flags)
{
- return __shmem_file_setup(name, size, flags, S_PRIVATE);
+ return __shmem_file_setup(shm_mnt, name, size, flags, S_PRIVATE);
}
/**
@@ -4262,11 +4262,25 @@ struct file *shmem_kernel_file_setup(const char *name,
loff_t size, unsigned lon
*/
struct file *shmem_file_setup(const char *name, loff_t size, unsigned long
flags)
{
- return __shmem_file_setup(name, size, flags, 0);
+ return __shmem_file_setup(shm_mnt, name, size, flags, 0);
}
EXPORT_SYMBOL_GPL(shmem_file_setup);
/**
+ * shmem_file_setup_with_mnt - get an unlinked file living in tmpfs
+ * @mnt: the tmpfs mount where the file will be created
+ * @name: name for dentry (to be seen in /proc//maps
+ * @size: size to be set for the file
+ * @flags: VM_NORESERVE suppresses pre-accounting of the entire object size
+ */
+struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt, const char *name,
+ loff_t size, unsigned long flags)
+{
+ return __shmem_file_setup(mnt, name, size, flags, 0);
+}
+EXPORT_SYMBOL_GPL(shmem_file_setup_with_mnt);
+
+/**
* shmem_zero_setup - setup a shared anonymous mapping
* @vma: the vma to be mmapped is prepared by do_mmap_pgoff
*/
@@ -4281,7 +4295,7 @@ int shmem_zero_setup(struct vm_area_struct *vma)
* accessible to the user through its mapping, use S_PRIVATE flag to
* bypass file security, in the same way as shmem_kernel_file_setup().
*/
- file = __shmem_file_setup("dev/zero", size, vma->vm_flags, S_PRIVATE);
+ file = shmem_kernel_file_setup("dev/zero", size, vma->vm_flags);
if (IS_ERR(file))
return PTR_ERR(file);
--
2.13.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/21] drm/i915: support 2M pages for the 48b PPGTT
Support inserting 2M gtt pages into the 48b PPGTT.
v2: sanity check sg->length against page_size
v3: don't recalculate rem on each loop
whitespace breakup
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 78 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a3897676e0bc..8cdb5361b582 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1016,6 +1016,71 @@ static void gen8_ppgtt_insert_3lvl(struct
i915_address_space *vm,
cache_level);
}
+static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
+ struct i915_page_directory_pointer
**pdps,
+ struct sgt_dma *iter,
+ enum i915_cache_level cache_level)
+{
+ const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
+ u64 start = vma->node.start;
+ dma_addr_t rem = iter->sg->length;
+
+ do {
+ struct gen8_insert_pte idx = gen8_insert_pte(start);
+ struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
+ struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
+ unsigned int page_size;
+ gen8_pte_t encode = pte_encode;
+ gen8_pte_t *vaddr;
+ u16 index, max;
+
+ if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
+ IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
+ rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
+ index = idx.pde;
+ max = I915_PDES;
+ page_size = I915_GTT_PAGE_SIZE_2M;
+
+ encode |= GEN8_PDE_PS_2M;
+
+ vaddr = kmap_atomic_px(pd);
+ } else {
+ struct i915_page_table *pt = pd->page_table[idx.pde];
+
+ index = idx.pte;
+ max = GEN8_PTES;
+ page_size = I915_GTT_PAGE_SIZE;
+
+ vaddr = kmap_atomic_px(pt);
+ }
+
+ do {
+ GEM_BUG_ON(iter->sg->length < page_size);
+ vaddr[index++] = encode | iter->dma;
+
+ start += page_size;
+ iter->dma += page_size;
+ rem -= page_size;
+ if (iter->dma >= iter->max) {
+ iter->sg = __sg_next(iter->sg);
+ if (!iter->sg)
+ break;
+
+ rem = iter->sg->length;
+ iter->dma = sg_dma_address(iter->sg);
+ iter->max = iter->dma + rem;
+
+ if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
+ break;
+ }
+
+ } while (rem >= page_size && index < max);
+
+ kunmap_atomic(vaddr);
+
+ } while (iter->sg);
+}
+
static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
struct i915_vma *vma,
enum i915_cache_level cache_level,
@@ -1028,11 +1093,16 @@ static void gen8_ppgtt_insert_4lvl(struct
i915_address_space *vm,
.max = iter.dma + iter.sg->length,
};
struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
- struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
- while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter,
-&idx, cache_level))
- GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+ if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
+ gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level);
+ } else {
+ struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
+
+ while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
+&iter, &idx, cache_level))
+ GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+ }
}
static void gen8_free_page_tables(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 87f3ceaca5a8..e9e66abbe532 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -153,6 +153,8 @@ typedef u64 gen8_ppgtt_pml4e_t;
#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
+#define GEN8_PDE_PS_2M BIT(7)
+
struct sg
[Intel-gfx] [PATCH 00/21] huge gtt pages
Bunch of changes all round, mostly in the kselftest department, of note we drop support for 1G pages for the time being, since testing has proven to be a pita, and instead focus on getting the 64K and 2M support landed. Matthew Auld (21): mm/shmem: introduce shmem_file_setup_with_mnt drm/i915: introduce simple gemfs drm/i915/gemfs: enable THP drm/i915: introduce page_sizes field to dev_info drm/i915: push set_pages down to the callers drm/i915: introduce page_size members drm/i915: introduce vm set_pages/clear_pages drm/i915: align the vma start to the largest gtt page size drm/i915: align 64K objects to 2M drm/i915: enable IPS bit for 64K pages drm/i915: disable GTT cache for 2M pages drm/i915: support 2M pages for the 48b PPGTT drm/i915: add support for 64K scratch page drm/i915: support 64K pages for the 48b PPGTT drm/i915: accurate page size tracking for the ppgtt drm/i915/debugfs: include some gtt page size metrics drm/i915/selftests: huge page tests drm/i915/selftests: mix huge pages drm/i915: disable platform support for vGPU huge gtt pages drm/i915: enable platform support for 64K pages drm/i915: enable platform support for 2M pages drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/i915_debugfs.c| 61 +- drivers/gpu/drm/i915/i915_drv.h| 11 +- drivers/gpu/drm/i915/i915_gem.c| 137 +- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 22 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 257 ++- drivers/gpu/drm/i915/i915_gem_gtt.h| 19 +- drivers/gpu/drm/i915/i915_gem_internal.c | 18 +- drivers/gpu/drm/i915/i915_gem_object.h | 31 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 16 +- drivers/gpu/drm/i915/i915_gem_userptr.c| 19 +- drivers/gpu/drm/i915/i915_gemfs.c | 66 + drivers/gpu/drm/i915/i915_gemfs.h | 34 + drivers/gpu/drm/i915/i915_pci.c| 23 + drivers/gpu/drm/i915/i915_reg.h|3 + drivers/gpu/drm/i915/i915_vma.c| 47 +- drivers/gpu/drm/i915/i915_vma.h|1 + drivers/gpu/drm/i915/intel_pm.c|8 +- drivers/gpu/drm/i915/selftests/huge_gem_object.c | 14 +- drivers/gpu/drm/i915/selftests/huge_pages.c| 1636 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 15 +- .../gpu/drm/i915/selftests/i915_live_selftests.h |1 + .../gpu/drm/i915/selftests/i915_mock_selftests.h |1 + drivers/gpu/drm/i915/selftests/mock_gem_device.c |9 + drivers/gpu/drm/i915/selftests/mock_gtt.c | 11 +- drivers/gpu/drm/i915/selftests/scatterlist.c | 15 + include/linux/shmem_fs.h |2 + mm/shmem.c | 30 +- 28 files changed, 2374 insertions(+), 134 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gemfs.c create mode 100644 drivers/gpu/drm/i915/i915_gemfs.h create mode 100644 drivers/gpu/drm/i915/selftests/huge_pages.c -- 2.13.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/21] drm/i915: introduce simple gemfs
Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
moves us away from the shmemfs shm_mnt, and gives us the much needed
flexibility to do things like set our own mount options, namely huge=
which should allow us to enable the use of transparent-huge-pages for
our shmem backed objects.
v2: various improvements suggested by Joonas
v3: move gemfs instance to i915.mm and simplify now that we have
file_setup_with_mnt
v4: fallback to tmpfs shm_mnt upon failure to setup gemfs
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Dave Hansen
Cc: Kirill A. Shutemov
Cc: Hugh Dickins
Cc: linux...@kvack.org
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_drv.h | 5 +++
drivers/gpu/drm/i915/i915_gem.c | 30 +-
drivers/gpu/drm/i915/i915_gemfs.c| 52
drivers/gpu/drm/i915/i915_gemfs.h| 34
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 4 ++
6 files changed, 125 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_gemfs.c
create mode 100644 drivers/gpu/drm/i915/i915_gemfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5182e3d5557d..980c41568f46 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -47,6 +47,7 @@ i915-y += i915_cmd_parser.o \
i915_gem_tiling.o \
i915_gem_timeline.o \
i915_gem_userptr.o \
+ i915_gemfs.o \
i915_trace_points.o \
i915_vma.o \
intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f5d0e816008d..b59714f0c1bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1500,6 +1500,11 @@ struct i915_gem_mm {
/** Usable portion of the GTT for GEM */
dma_addr_t stolen_base; /* limited to low memory (32-bit) */
+ /**
+* tmpfs instance used for shmem backed objects
+*/
+ struct vfsmount *gemfs;
+
/** PPGTT used for aliasing the PPGTT with the GTT */
struct i915_hw_ppgtt *aliasing_ppgtt;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a650f92aa74..e5718ac9166d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,6 +35,7 @@
#include "intel_drv.h"
#include "intel_frontbuffer.h"
#include "intel_mocs.h"
+#include "i915_gemfs.h"
#include
#include
#include
@@ -4251,6 +4252,29 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_ops = {
.pwrite = i915_gem_object_pwrite_gtt,
};
+static int i915_gem_object_create_shmem(struct drm_device *dev,
+ struct drm_gem_object *obj,
+ size_t size)
+{
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct file *filp;
+
+ drm_gem_private_object_init(dev, obj, size);
+
+ if (i915->mm.gemfs)
+ filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,
+VM_NORESERVE);
+ else
+ filp = shmem_file_setup("i915", size, VM_NORESERVE);
+
+ if (IS_ERR(filp))
+ return PTR_ERR(filp);
+
+ obj->filp = filp;
+
+ return 0;
+}
+
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
{
@@ -4275,7 +4299,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv,
u64 size)
if (obj == NULL)
return ERR_PTR(-ENOMEM);
- ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
+ ret = i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size);
if (ret)
goto fail;
@@ -4914,6 +4938,8 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->fb_tracking.lock);
+ WARN_ON(i915_gemfs_init(dev_priv));
+
return 0;
err_priorities:
@@ -4952,6 +4978,8 @@ void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv)
/* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
rcu_barrier();
+
+ i915_gemfs_fini(dev_priv);
}
int i915_gem_freeze(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c
b/drivers/gpu/drm/i915/i915_gemfs.c
new file mode 100644
index ..168d0bd98f60
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit
[Intel-gfx] [PATCH 08/21] drm/i915: align the vma start to the largest gtt page size
For the 48b PPGTT try to align the vma start address to the required
page size boundary to guarantee we use said page size in the gtt. If we
are dealing with multiple page sizes, we can't guarantee anything and
just align to the largest. For soft pinning and objects which need to be
tightly packed into the lower 32bits we don't force any alignment.
v2: various improvements suggested by Chris
v3: use set_pages and better placement of page_sizes
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8
drivers/gpu/drm/i915/i915_vma.c | 12
drivers/gpu/drm/i915/i915_vma.h | 1 +
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5e0ac4c5a81c..a3897676e0bc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -226,6 +226,9 @@ static int ppgtt_set_pages(struct i915_vma *vma)
vma->pages = vma->obj->mm.pages;
+ vma->page_sizes.phys = vma->obj->mm.page_sizes.phys;
+ vma->page_sizes.sg = vma->obj->mm.page_sizes.sg;
+
return 0;
}
@@ -238,6 +241,8 @@ static void clear_pages(struct i915_vma *vma)
kfree(vma->pages);
}
vma->pages = NULL;
+
+ memset(&vma->page_sizes, 0, sizeof(struct i915_page_sizes));
}
static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
@@ -2540,6 +2545,9 @@ static int ggtt_set_pages(struct i915_vma *vma)
if (ret)
return ret;
+ vma->page_sizes.phys = vma->obj->mm.page_sizes.phys;
+ vma->page_sizes.sg = vma->obj->mm.page_sizes.sg;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 49bf49571e47..102c2f184486 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -493,6 +493,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
if (ret)
goto err_clear;
} else {
+ /* We only support huge gtt pages through the 48b PPGTT,
+* however we also don't want to force any alignment for
+* objects which need to be tightly packed into the low 32bits.
+*/
+ if (end > (1ULL << 32) &&
+ vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
+ u64 page_alignment =
+ rounddown_pow_of_two(vma->page_sizes.sg);
+
+ alignment = max(alignment, page_alignment);
+ }
+
ret = i915_gem_gtt_insert(vma->vm, &vma->node,
size, alignment, obj->cache_level,
start, end, flags);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index e811067c7724..c59ba76613a3 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -55,6 +55,7 @@ struct i915_vma {
void __iomem *iomap;
u64 size;
u64 display_alignment;
+ struct i915_page_sizes page_sizes;
u32 fence_size;
u32 fence_alignment;
--
2.13.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/21] drm/i915: introduce vm set_pages/clear_pages
Move the setting/clearing of the vma->pages to a vm operation. Doing so
neatens things up a little, but more importantly gives us a sane place
to also set/clear the vma->pages_sizes, which we introduce later in
preparation for supporting huge-pages.
v2: remove redundant vma->pages check
v3: GEM_BUG_ON(vma->pages) following i915_vma_remove
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +++
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +
drivers/gpu/drm/i915/i915_vma.c | 27 +++-
drivers/gpu/drm/i915/selftests/mock_gtt.c | 11 ++---
4 files changed, 66 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 64d785262d14..5e0ac4c5a81c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -205,8 +205,6 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
return ret;
}
- vma->pages = vma->obj->mm.pages;
-
/* Currently applicable only to VLV */
pte_flags = 0;
if (vma->obj->gt_ro)
@@ -222,6 +220,26 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
}
+static int ppgtt_set_pages(struct i915_vma *vma)
+{
+ GEM_BUG_ON(vma->pages);
+
+ vma->pages = vma->obj->mm.pages;
+
+ return 0;
+}
+
+static void clear_pages(struct i915_vma *vma)
+{
+ GEM_BUG_ON(!vma->pages);
+
+ if (vma->pages != vma->obj->mm.pages) {
+ sg_free_table(vma->pages);
+ kfree(vma->pages);
+ }
+ vma->pages = NULL;
+}
+
static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level)
{
@@ -1454,6 +1472,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.cleanup = gen8_ppgtt_cleanup;
ppgtt->base.unbind_vma = ppgtt_unbind_vma;
ppgtt->base.bind_vma = ppgtt_bind_vma;
+ ppgtt->base.set_pages = ppgtt_set_pages;
+ ppgtt->base.clear_pages = clear_pages;
ppgtt->debug_dump = gen8_dump_ppgtt;
return 0;
@@ -1896,6 +1916,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.unbind_vma = ppgtt_unbind_vma;
ppgtt->base.bind_vma = ppgtt_bind_vma;
+ ppgtt->base.set_pages = ppgtt_set_pages;
+ ppgtt->base.clear_pages = clear_pages;
ppgtt->base.cleanup = gen6_ppgtt_cleanup;
ppgtt->debug_dump = gen6_dump_ppgtt;
@@ -2407,12 +2429,6 @@ static int ggtt_bind_vma(struct i915_vma *vma,
struct drm_i915_gem_object *obj = vma->obj;
u32 pte_flags;
- if (unlikely(!vma->pages)) {
- int ret = i915_get_ggtt_vma_pages(vma);
- if (ret)
- return ret;
- }
-
/* Currently applicable only to VLV */
pte_flags = 0;
if (obj->gt_ro)
@@ -2449,12 +2465,6 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
u32 pte_flags;
int ret;
- if (unlikely(!vma->pages)) {
- ret = i915_get_ggtt_vma_pages(vma);
- if (ret)
- return ret;
- }
-
/* Currently applicable only to VLV */
pte_flags = 0;
if (vma->obj->gt_ro)
@@ -2469,7 +2479,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
vma->node.start,
vma->size);
if (ret)
- goto err_pages;
+ return ret;
}
appgtt->base.insert_entries(&appgtt->base, vma, cache_level,
@@ -2483,17 +2493,6 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
}
return 0;
-
-err_pages:
- if (!(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND))) {
- if (vma->pages != vma->obj->mm.pages) {
- GEM_BUG_ON(!vma->pages);
- sg_free_table(vma->pages);
- kfree(vma->pages);
- }
- vma->pages = NULL;
- }
- return ret;
}
static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
@@ -2531,6 +2530,19 @@ void i915_gem_gtt_finish_pages(struct
drm_i915_gem_object *obj,
dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL);
}
+static int ggtt_set_pages(struct i915_vma *vma)
+{
+ int ret;
+
+ GEM_BUG_ON(vma->pages);
+
+ ret = i915_get_ggtt_vma_pages(vma);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static void i915_gtt_color_adjust(const struct drm_mm_node *node,
unsigned long color,
[Intel-gfx] [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info
In preparation for huge gtt pages expose page_sizes as part of the
device info, to indicate the page sizes supported by the HW. Currently
only 4K is supported.
v2: s/page_size_mask/page_sizes/
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 7 ++-
drivers/gpu/drm/i915/i915_pci.c | 20
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +++
4 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b59714f0c1bf..869e46306c49 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -862,6 +862,7 @@ struct intel_device_info {
u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
+ unsigned int page_sizes; /* page sizes supported by the HW */
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f62fb903dc24..88e9724d5fc7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,7 +42,12 @@
#include "i915_gem_request.h"
#include "i915_selftest.h"
-#define I915_GTT_PAGE_SIZE 4096UL
+#define I915_GTT_PAGE_SIZE_4K BIT(12)
+#define I915_GTT_PAGE_SIZE_64K BIT(16)
+#define I915_GTT_PAGE_SIZE_2M BIT(21)
+
+#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
+
#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
#define I915_FENCE_REG_NONE -1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da60866b6628..84cdab3c5f09 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -56,6 +56,10 @@
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
/* Keep in gen based order, and chronological order within a gen */
+
+#define GEN_DEFAULT_PAGE_SIZES \
+ .page_sizes = I915_GTT_PAGE_SIZE_4K
+
#define GEN2_FEATURES \
.gen = 2, .num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
@@ -65,6 +69,7 @@
.ring_mask = RENDER_RING, \
.has_snoop = true, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_i830_info __initconst = {
@@ -98,6 +103,7 @@ static const struct intel_device_info intel_i865g_info
__initconst = {
.ring_mask = RENDER_RING, \
.has_snoop = true, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_i915g_info __initconst = {
@@ -161,6 +167,7 @@ static const struct intel_device_info intel_pineview_info
__initconst = {
.ring_mask = RENDER_RING, \
.has_snoop = true, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_i965g_info __initconst = {
@@ -203,6 +210,7 @@ static const struct intel_device_info intel_gm45_info
__initconst = {
.ring_mask = RENDER_RING | BSD_RING, \
.has_snoop = true, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_ironlake_d_info __initconst = {
@@ -226,6 +234,7 @@ static const struct intel_device_info intel_ironlake_m_info
__initconst = {
.has_rc6p = 1, \
.has_aliasing_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
#define SNB_D_PLATFORM \
@@ -269,6 +278,7 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info __initconst =
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
#define IVB_D_PLATFORM \
@@ -325,6 +335,7 @@ static const struct intel_device_info intel_valleyview_info
__initconst = {
.has_snoop = true,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.display_mmio_offset = VLV_DISPLAY_BASE,
+ GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_PIPEOFFSETS,
CURSOR_OFFSETS
};
@@ -363,6 +374,7 @@ static const struct intel_device_info
intel_haswell_gt3_info __initconst = {
#define BDW_FEATURES \
HSW_FEATURES, \
BDW_COLORS, \
+ GEN_DEFAULT_PAGE_SIZES, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1, \
@@ -415,13 +427,18 @@ static const struct intel_device_info
intel_cherryview_info __initconst = {
.has_reset_engine = 1,
.has_snoop = true,
.display_mmio_offset = VLV_DISPLAY_BASE,
+ GEN_DEFAULT_PAGE_SIZES,
GEN_CHV_PIPEOFFSETS,
[Intel-gfx] [PATCH 09/21] drm/i915: align 64K objects to 2M
We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.
v2: don't separate logically connected ops
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_vma.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 102c2f184486..b97843fe6338 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -500,9 +500,17 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
if (end > (1ULL << 32) &&
vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
u64 page_alignment =
- rounddown_pow_of_two(vma->page_sizes.sg);
+ rounddown_pow_of_two(vma->page_sizes.sg |
+I915_GTT_PAGE_SIZE_2M);
alignment = max(alignment, page_alignment);
+
+ /* We can't mix 64K and 4K PTEs in the same page-table
(2M
+* block), and so to avoid the ugliness and complexity
of
+* coloring we opt for just aligning 64K objects to 2M.
+*/
+ if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
+ size = round_up(size, I915_GTT_PAGE_SIZE_2M);
}
ret = i915_gem_gtt_insert(vma->vm, &vma->node,
--
2.13.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/21] drm/i915: introduce page_size members
In preparation for supporting huge gtt pages for the ppgtt, we introduce
page size members for gem objects. We fill in the page sizes by
scanning the sg table.
v2: pass the sg_mask to set_pages
v3: calculate the sg_mask inline with populating the sg_table where
possible, and pass to set_pages along with the pages.
v4: bunch of improvements from Joonas
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Daniel Vetter
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++-
drivers/gpu/drm/i915/i915_gem.c | 41 +---
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 9 +-
drivers/gpu/drm/i915/i915_gem_internal.c | 5 ++-
drivers/gpu/drm/i915/i915_gem_object.h | 17 ++
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 9 +-
drivers/gpu/drm/i915/selftests/huge_gem_object.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c| 5 ++-
9 files changed, 83 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 869e46306c49..a3bd510c434d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3084,6 +3084,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)(i915_modparams.enable_ppgtt ==
3)
+#define HAS_PAGE_SIZES(dev_priv, sizes) \
+ ((sizes) && (((sizes) & ~(dev_priv)->info.page_sizes)) == 0)
#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
@@ -3498,7 +3500,8 @@ i915_gem_object_get_dma_address(struct
drm_i915_gem_object *obj,
unsigned long n);
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
-struct sg_table *pages);
+struct sg_table *pages,
+unsigned int sg_mask);
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
static inline int __must_check
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9c46f1f91f7d..ae7b683437f1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -228,7 +228,7 @@ static int i915_gem_object_get_pages_phys(struct
drm_i915_gem_object *obj)
obj->phys_handle = phys;
- __i915_gem_object_set_pages(obj, st);
+ __i915_gem_object_set_pages(obj, st, sg->length);
return 0;
@@ -2266,6 +2266,8 @@ void __i915_gem_object_put_pages(struct
drm_i915_gem_object *obj,
if (!IS_ERR(pages))
obj->ops->put_pages(obj, pages);
+ obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
+
unlock:
mutex_unlock(&obj->mm.lock);
}
@@ -2308,6 +2310,7 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
struct page *page;
unsigned long last_pfn = 0; /* suppress gcc warning */
unsigned int max_segment = i915_sg_segment_size();
+ unsigned int sg_mask;
gfp_t noreclaim;
int ret;
@@ -2339,6 +2342,7 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
sg = st->sgl;
st->nents = 0;
+ sg_mask = 0;
for (i = 0; i < page_count; i++) {
const unsigned int shrink[] = {
I915_SHRINK_BOUND | I915_SHRINK_UNBOUND |
I915_SHRINK_PURGEABLE,
@@ -2391,8 +2395,10 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
if (!i ||
sg->length >= max_segment ||
page_to_pfn(page) != last_pfn + 1) {
- if (i)
+ if (i) {
+ sg_mask |= sg->length;
sg = sg_next(sg);
+ }
st->nents++;
sg_set_page(sg, page, PAGE_SIZE, 0);
} else {
@@ -2403,8 +2409,10 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
/* Check that the i965g/gm workaround works. */
WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x0010UL));
}
- if (sg) /* loop terminated early; short sg table */
+ if (sg) { /* loop terminated early; short sg table */
+ sg_mask |= sg->length;
sg_mark_end(sg);
+ }
/* Trim unused sg entries to avoid wasting memory. */
i915_sg_trim(st);
@@ -2433,7 +2441,7 @@ static int i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
if (i915_gem_object_needs_bit17_swizzle(obj))
i915_gem_object_do_bit_17_swizzle(o
[Intel-gfx] [PATCH 05/21] drm/i915: push set_pages down to the callers
Each backend is now responsible for calling __i915_gem_object_set_pages
upon successfully gathering its backing storage. This eliminates the
inconsistency between the async and sync paths, which stands out even
more when we start throwing around an sg_mask in a later patch.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 45 +---
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 15 +---
drivers/gpu/drm/i915/i915_gem_internal.c | 15
drivers/gpu/drm/i915/i915_gem_object.h | 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 16 ++---
drivers/gpu/drm/i915/i915_gem_userptr.c | 12 +++
drivers/gpu/drm/i915/selftests/huge_gem_object.c | 14
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c| 12 ---
8 files changed, 77 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5718ac9166d..9c46f1f91f7d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -162,8 +162,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void
*data,
return 0;
}
-static struct sg_table *
-i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
+static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
{
struct address_space *mapping = obj->base.filp->f_mapping;
drm_dma_handle_t *phys;
@@ -171,9 +170,10 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj)
struct scatterlist *sg;
char *vaddr;
int i;
+ int err;
if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
- return ERR_PTR(-EINVAL);
+ return -EINVAL;
/* Always aligning to the object size, allows a single allocation
* to handle all possible callers, and given typical object sizes,
@@ -183,7 +183,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj)
roundup_pow_of_two(obj->base.size),
roundup_pow_of_two(obj->base.size));
if (!phys)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
vaddr = phys->vaddr;
for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
@@ -192,7 +192,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj)
page = shmem_read_mapping_page(mapping, i);
if (IS_ERR(page)) {
- st = ERR_CAST(page);
+ err = PTR_ERR(page);
goto err_phys;
}
@@ -209,13 +209,13 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj)
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st) {
- st = ERR_PTR(-ENOMEM);
+ err = -ENOMEM;
goto err_phys;
}
if (sg_alloc_table(st, 1, GFP_KERNEL)) {
kfree(st);
- st = ERR_PTR(-ENOMEM);
+ err = -ENOMEM;
goto err_phys;
}
@@ -227,11 +227,15 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj)
sg_dma_len(sg) = obj->base.size;
obj->phys_handle = phys;
- return st;
+
+ __i915_gem_object_set_pages(obj, st);
+
+ return 0;
err_phys:
drm_pci_free(obj->base.dev, phys);
- return st;
+
+ return err;
}
static void __start_cpu_write(struct drm_i915_gem_object *obj)
@@ -2292,8 +2296,7 @@ static bool i915_sg_trim(struct sg_table *orig_st)
return true;
}
-static struct sg_table *
-i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
+static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
const unsigned long page_count = obj->base.size / PAGE_SIZE;
@@ -2317,12 +2320,12 @@ i915_gem_object_get_pages_gtt(struct
drm_i915_gem_object *obj)
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (st == NULL)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
rebuild_st:
if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
kfree(st);
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
}
/* Get the list of pages out of our struct file. They'll be pinned
@@ -2430,7 +2433,9 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj)
if (i915_gem_object_needs_bit17_swizzle(obj))
i915_gem_object_do_bit_17_swizzle(obj, st);
- return st;
+ __i915_gem_object_set_pages(obj, st);
+
+ return 0;
err_sg:
sg_mark_end(sg);
@@ -2451,7 +2456,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj)
if (ret == -ENOSPC)
ret = -ENOMEM;
- return
[Intel-gfx] [PATCH 03/21] drm/i915/gemfs: enable THP
Enable transparent-huge-pages through gemfs by mounting with
huge=within_size.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gemfs.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c
b/drivers/gpu/drm/i915/i915_gemfs.c
index 168d0bd98f60..98533260e398 100644
--- a/drivers/gpu/drm/i915/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -24,6 +24,7 @@
#include
#include
+#include
#include "i915_drv.h"
#include "i915_gemfs.h"
@@ -41,6 +42,19 @@ int i915_gemfs_init(struct drm_i915_private *i915)
if (IS_ERR(gemfs))
return PTR_ERR(gemfs);
+ if (has_transparent_hugepage()) {
+ struct super_block *sb = gemfs->mnt_sb;
+ char options[] = "huge=within_size";
+ int flags = 0;
+ int err;
+
+ err = sb->s_op->remount_fs(sb, &flags, options);
+ if (err) {
+ kern_unmount(gemfs);
+ return err;
+ }
+ }
+
i915->mm.gemfs = gemfs;
return 0;
--
2.13.5
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Make i915_spin_request() static
== Series Details == Series: drm/i915: Make i915_spin_request() static URL : https://patchwork.freedesktop.org/series/30757/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test kms_flip: Subgroup flip-vs-modeset-interruptible: pass -> DMESG-WARN (shard-hsw) fdo#102557 Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#102557 https://bugs.freedesktop.org/show_bug.cgi?id=102557 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1334 dwarn:3 dfail:0 fail:9 skip:1083 time:9909s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5791/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix SSEU Device Status.
On 09/22/2017 06:15 AM, Rodrigo Vivi wrote:
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
v3: Consider s_max = 6 and ss_max=4 to run over all possible
slices and subslices possible by spec. Although no real
hardware will have that many slices/subslices.
To match with sseu info init.
v4: Fix offset calculation for slices 4 and 5.
Removed Oscar's rv-b since this change also needs review.
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +++--
drivers/gpu/drm/i915/i915_reg.h | 6 +
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e197e5d99277 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ /* skip disabled subslice */
+ continue;
You are going to hate me, but I found something else:
SLICE0_PGCTL_ACK has powergate acknowledge bits for subslices 0, 1 & 2,
but not for subslice 3
SLICEn_PGCTL_ACK (where n = 1-5) has powergate acknowledge bits for
subslices 0 & 1, but not for subslices 2 & 3
I have no idea where the missing bits went (maybe the BSpec is wrong?).
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c257797c583..9729145e6c03 100644
--- a/drivers/gpu/drm/i915/i9
[Intel-gfx] ✗ Fi.CI.BAT: failure for tests: add slice power programming test (rev2)
== Series Details == Series: tests: add slice power programming test (rev2) URL : https://patchwork.freedesktop.org/series/29717/ State : failure == Summary == IGT patchset build failed on latest successful build b94a17d13fb5e03bbc7ef50ce88352b37ad06c85 tests/psr: Don't strcmp CRCs that are not NULL terminated. Making check in lib make check-recursive Making check in . Making check in tests make igt_no_exit igt_no_exit_list_only igt_fork_helper igt_list_only igt_no_subtest igt_simulation igt_simple_test_subtests igt_stats igt_timeout igt_invalid_subtest_name igt_segfault igt_subtest_group igt_assert igt_exit_handler igt_hdmi_inject igt_can_fail igt_can_fail_simple CC igt_no_exit.o CC igt_no_exit_list_only.o CC igt_fork_helper.o CC igt_list_only.o CC igt_no_subtest.o CC igt_simulation.o CC igt_simple_test_subtests.o CC igt_timeout.o CC igt_stats.o CC igt_invalid_subtest_name.o CC igt_segfault.o CC igt_subtest_group.o CC igt_assert.o CC igt_hdmi_inject.o CC igt_exit_handler.o CC igt_can_fail.o CC igt_can_fail_simple.o CCLD igt_timeout CCLD igt_simple_test_subtests CCLD igt_can_fail CCLD igt_can_fail_simple CCLD igt_no_exit CCLD igt_list_only CCLD igt_no_subtest CCLD igt_no_exit_list_only CCLD igt_exit_handler CCLD igt_subtest_group CCLD igt_invalid_subtest_name CCLD igt_stats CCLD igt_simulation CCLD igt_segfault CCLD igt_assert CCLD igt_hdmi_inject CCLD igt_fork_helper make check-TESTS PASS: igt_list_only ../../build-aux/test-driver: line 107: 14570 Aborted (core dumped) "$@" > $log_file 2>&1 XFAIL: igt_no_exit_list_only PASS: igt_can_fail PASS: igt_hdmi_inject PASS: igt_can_fail_simple PASS: igt_subtest_group PASS: igt_stats PASS: igt_assert PASS: igt_exit_handler PASS: igt_simulation PASS: igt_fork_helper ../../build-aux/test-driver: line 107: 14583 Aborted (core dumped) "$@" > $log_file 2>&1 XFAIL: igt_simple_test_subtests ../../build-aux/test-driver: line 107: 14561 Aborted (core dumped) "$@" > $log_file 2>&1 XFAIL: igt_no_exit ../../build-aux/test-driver: line 107: 14605 Aborted (core dumped) "$@" > $log_file 2>&1 ../../build-aux/test-driver: line 107: 14566 Aborted (core dumped) "$@" > $log_file 2>&1 XFAIL: igt_invalid_subtest_name XFAIL: igt_no_subtest PASS: igt_segfault XFAIL: igt_timeout Testsuite summary for intel-gpu-tools 1.19 # TOTAL: 17 # PASS: 11 # SKIP: 0 # XFAIL: 6 # FAIL: 0 # XPASS: 0 # ERROR: 0 Making check in man make[1]: Nothing to be done for 'check'. Making check in tools Making check in null_state_gen make[2]: Nothing to be done for 'check'. Making check in registers make[2]: Nothing to be done for 'check'. make[2]: Nothing to be done for 'check-am'. Making check in scripts make[1]: Nothing to be done for 'check'. Making check in benchmarks make[1]: Nothing to be done for 'check'. Making check in tests Making check in intel-ci make[2]: Nothing to be done for 'check'. make igt_command_line.sh make[3]: Nothing to be done for 'igt_command_line.sh'. make check-TESTS FAIL: igt_command_line.sh Testsuite summary for intel-gpu-tools 1.19 # TOTAL: 1 # PASS: 0 # SKIP: 0 # XFAIL: 0 # FAIL: 1 # XPASS: 0 # ERROR: 0 See tests/test-suite.log Please report to https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=IGT Makefile:4556: recipe for target 'test-suite.log' failed make[4]: *** [test-suite.log] Error 1 Makefile:4662: recipe for target 'check-TESTS' failed make[3]: *** [check-TESTS] Error 2 Makefile:4760: recipe for target 'check-am' failed make[2]: *** [check-am] Error 2 Makefile:4449: recipe for target 'check-recursive' failed make[1]: *** [check-recursive] Error 1 Makefile:528: recipe for target 'check-recursive' failed make: *** [check-recursive] Error 1 intel-gpu-tools 1.19: lib/tests/test-suite.log # TOTAL: 17 # PASS: 11 # SKIP: 0 # XFAIL: 6 # FAIL: 0 # XPASS: 0 # ERROR: 0 .. contents:: :depth: 2 XFAIL: igt_no_exit == IGT-Version: 1.19-gc366c367 (x86_64) (Linux: 4.10.0-28-generic x86_64) Subtest A: SUCCESS (0.000s) igt_no_exit: igt_core.c:571: common_exit_handler: Assertion `sig
[Intel-gfx] ✗ Fi.CI.BAT: failure for igt/gem_exec_schedule: Fix up too deep reorder-wide()
== Series Details == Series: igt/gem_exec_schedule: Fix up too deep reorder-wide() URL : https://patchwork.freedesktop.org/series/30765/ State : failure == Summary == Series 30765 revision 1 was fully merged or fully failed: no git log ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for tests/kms_frontbuffer_tracking: Try harder to collect CRC's
== Series Details == Series: tests/kms_frontbuffer_tracking: Try harder to collect CRC's URL : https://patchwork.freedesktop.org/series/30760/ State : warning == Summary == IGT patchset tested on top of latest successful build b94a17d13fb5e03bbc7ef50ce88352b37ad06c85 tests/psr: Don't strcmp CRCs that are not NULL terminated. with latest DRM-Tip kernel build CI_DRM_3124 e0e308721fd2 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Test gem_ringfill: Subgroup basic-default-hang: dmesg-warn -> PASS (fi-pnv-d510) fdo#101600 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 +1 Test kms_force_connector_basic: Subgroup force-connector-state: pass -> SKIP (fi-ivb-3520m) Subgroup force-edid: pass -> SKIP (fi-ivb-3520m) Subgroup force-load-detect: pass -> SKIP (fi-ivb-3520m) Subgroup prune-stale-modes: pass -> SKIP (fi-ivb-3520m) Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (fi-glk-1) fdo#102777 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:472s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:416s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:523s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:508s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:502s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:506s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:541s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:569s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:430s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:407s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:438s fi-ivb-3520m total:289 pass:257 dwarn:0 dfail:0 fail:0 skip:32 time:487s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:467s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:471s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:586s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:597s fi-pnv-d510 total:289 pass:224 dwarn:0 dfail:0 fail:0 skip:65 time:541s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:451s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:757s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:496s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:471s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:576s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:421s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_242/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6] drm/i915: Enable scanline read based on frame timestamps
From: Uma Shankar
For certain platforms on certain encoders, timings are driven
from port instead of pipe. Thus, we can't rely on pipe scanline
registers to get the timing information. Some cases scanline
register read will not be functional.
This is causing vblank evasion logic to fail since it relies on
scanline, causing atomic update failure warnings.
This patch uses pipe framestamp and current timestamp registers
to calculate scanline. This is an indirect way to get the scanline.
It helps resolve atomic update failure for gen9 dsi platforms.
v2: Addressed Ville and Daniel's review comments. Updated the
register MACROs, handled race condition for register reads,
extracted timings from the hwmode. Removed the dependency on
crtc->config to get the encoder type.
v3: Made get scanline function generic
v4: Addressed Ville's review comments. Added a flag to decide timestamp
based scanline reporting. Changed 64bit variables to u32
v5: Adressed Ville's review comments. Put the scanline compute function
at the place of caller. Removed hwmode flags from uapi and used a local
i915 data structure instead.
v6: Used vblank hwmode to get the timings.
Credits-to: Ville Syrjälä
Signed-off-by: Uma Shankar
Signed-off-by: Chandra Konduru
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_irq.c | 53 ++
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_drv.h |2 ++
drivers/gpu/drm/i915/intel_dsi.c |7 +
4 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 91a2c5d..4e44d59 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -772,6 +772,56 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev,
unsigned int pipe)
return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
}
+/*
+ * On certain encoders on certain platforms, pipe
+ * scanline register will not work to get the scanline,
+ * since the timings are driven from the PORT or issues
+ * with scanline register updates.
+ * This function will use Framestamp and current
+ * timestamp registers to calculate the scanline.
+ */
+u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_vblank_crtc *vblank =
+ &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
+ const struct drm_display_mode *mode = &vblank->hwmode;
+ u32 vblank_start = mode->crtc_vblank_start;
+ u32 vtotal = mode->crtc_vtotal;
+ u32 htotal = mode->crtc_htotal;
+ u32 clock = mode->crtc_clock;
+ u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
+
+ /* To avoid the race condition where we might cross into the
+* next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
+* reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
+* during the same frame.
+*/
+ do {
+ /*
+* This field provides read back of the display
+* pipe frame time stamp. The time stamp value
+* is sampled at every start of vertical blank.
+*/
+ scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
+
+ /*
+* The TIMESTAMP_CTR register has the current
+* time stamp value.
+*/
+ scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
+
+ scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
+ } while (scan_post_time != scan_prev_time);
+
+ scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
+ clock), 1000 * htotal);
+ scanline = min(scanline, vtotal - 1);
+ scanline = (scanline + vblank_start) % vtotal;
+
+ return scanline;
+}
+
/* I915_READ_FW, only for fast reads of display block, no need for forcewake
etc. */
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
@@ -788,6 +838,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
mode = &vblank->hwmode;
+ if (mode->private_flags & DRM_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
+ return __intel_get_crtc_scanline_from_timestamp(crtc);
+
vtotal = mode->crtc_vtotal;
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f03cd0..fbd00cc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8804,6 +8804,15 @@ enum skl_power_gate {
#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
+/* Gen4+ Timestamp and Pipe Frame time stamp registers */
+#define GEN4_TIMESTAMP _MMIO(
[Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
Cc: Rodrigo Vivi
CC: Puthikorn Voravootivat
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_psr.c | 12 ++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..89c5249 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
(mask) << 16 | (value); })
#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
/* Engine ID */
@@ -4047,7 +4048,6 @@ enum {
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK(0xf<<4)
#define EDP_PSR2_IDLE_MASK 0xf
-#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
#define EDP_PSR2_STATUS_CTL_MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..e505fa6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+ &sink_latency) == 1) {
+ sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
+ } else {
+ sink_latency = 0;
+ }
+ val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] lib/igt_kms: Don't assert on non-existent plane
== Series Details == Series: series starting with [1/6] lib/igt_kms: Don't assert on non-existent plane URL : https://patchwork.freedesktop.org/series/30706/ State : success == Summary == IGT patchset tested on top of latest successful build b94a17d13fb5e03bbc7ef50ce88352b37ad06c85 tests/psr: Don't strcmp CRCs that are not NULL terminated. with latest DRM-Tip kernel build CI_DRM_3124 e0e308721fd2 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (fi-glk-1) fdo#102777 +1 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:447s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:474s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:420s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:519s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:499s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:494s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:548s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:568s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:439s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:409s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:496s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:475s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:470s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:600s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:542s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:448s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:753s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:473s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:569s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:419s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_241/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: Enable scanline read based on frame timestamps
On Fri, Sep 22, 2017 at 09:11:30PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For certain platforms on certain encoders, timings are driven
> from port instead of pipe. Thus, we can't rely on pipe scanline
> registers to get the timing information. Some cases scanline
> register read will not be functional.
> This is causing vblank evasion logic to fail since it relies on
> scanline, causing atomic update failure warnings.
>
> This patch uses pipe framestamp and current timestamp registers
> to calculate scanline. This is an indirect way to get the scanline.
> It helps resolve atomic update failure for gen9 dsi platforms.
>
> v2: Addressed Ville and Daniel's review comments. Updated the
> register MACROs, handled race condition for register reads,
> extracted timings from the hwmode. Removed the dependency on
> crtc->config to get the encoder type.
>
> v3: Made get scanline function generic
>
> v4: Addressed Ville's review comments. Added a flag to decide timestamp
> based scanline reporting. Changed 64bit variables to u32
>
> v5: Adressed Ville's review comments. Put the scanline compute function
> at the place of caller. Removed hwmode flag from uapi and used a local
> private_flag instead.
>
> Credits-to: Ville Syrjälä
> Signed-off-by: Uma Shankar
> Signed-off-by: Chandra Konduru
> Signed-off-by: Vidya Srinivas
> ---
> drivers/gpu/drm/i915/i915_irq.c | 50
> ++
> drivers/gpu/drm/i915/i915_reg.h |9 +++
> drivers/gpu/drm/i915/intel_drv.h |2 ++
> drivers/gpu/drm/i915/intel_dsi.c |7 ++
> 4 files changed, 68 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 91a2c5d..6d7cd20 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -772,6 +772,53 @@ static u32 g4x_get_vblank_counter(struct drm_device
> *dev, unsigned int pipe)
> return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
> }
>
> +/*
> + * On certain encoders on certain platforms, pipe
> + * scanline register will not work to get the scanline,
> + * since the timings are driven from the PORT or issues
> + * with scanline register updates.
> + * This function will use Framestamp and current
> + * timestamp registers to calculate the scanline.
> + */
> +u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
static
I think sparse would have caught that. Please compile w/ C=1 to make sure
sparse stays happy. (+ run checkpatch ofc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 vblank_start = crtc->base.hwmode.crtc_vblank_start;
> + u32 vtotal = crtc->base.hwmode.crtc_vtotal;
> + u32 htotal = crtc->base.hwmode.crtc_htotal;
> + u32 clock = crtc->base.hwmode.crtc_clock;
> + u32 scanline = 0, scan_prev_time, scan_curr_time, scan_post_time;
> +
> + /* To avoid the race condition where we might cross into the
> + * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
> + * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
> + * during the same frame.
> + */
> + do {
> + /*
> + * This field provides read back of the display
> + * pipe frame time stamp. The time stamp value
> + * is sampled at every start of vertical blank.
> + */
> + scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
> +
> + /*
> + * The TIMESTAMP_CTR register has the current
> + * time stamp value.
> + */
> + scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
> +
> + scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
> + } while (scan_post_time != scan_prev_time);
> +
> + scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
> +clock), 1000 * htotal);
> + scanline = min(scanline, vtotal - 1);
> + scanline = (scanline + vblank_start) % vtotal;
> +
> + return scanline;
> +}
> +
> /* I915_READ_FW, only for fast reads of display block, no need for forcewake
> etc. */
> static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> {
> @@ -788,6 +835,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
> mode = &vblank->hwmode;
>
> + if (mode->private_flags & DRM_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
> + return __intel_get_crtc_scanline_from_timestamp(crtc);
> +
> vtotal = mode->crtc_vtotal;
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> vtotal /= 2;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9f03cd0..fbd00cc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8804,6 +8804,15 @@ enum skl_power_gate {
> #define MIPIO_TXESC_CLK_DIV2 _MM
Re: [Intel-gfx] Intel-gfx related suspend-to-ram issues on IBM R31
On Thu, Sep 21, 2017 at 08:36:33PM +0200, Thomas Richter wrote:
> Hi Daniel, hi Ville,
>
> thanks for integrating my patches of the DVO chip of my old IBM R31.
> With this patch in place, dithering on the laptop works now.
>
> However, I recently upgraded to Debian Stretch, and since then, I'm
> having either issues with 3D acceleration or with suspend-to-RAM.
>
> Details are as follows: The machine comes with the infamous i830M
> chipset, to be precise:
>
> 00:00.0 Host bridge: Intel Corporation 82830M/MG/MP Host Bridge (rev 04)
> 00:02.0 VGA compatible controller: Intel Corporation 82830M/MG
> Integrated Graphics Controller (rev 04)
> 00:02.1 Display controller: Intel Corporation 82830M/MG Integrated
> Graphics Controller
>
> I previously run the machine on a 4.1.38 kernel and Debian jessie, and
> everything (almost) worked. 3D acceleration worked (stable), and
> suspend-to-ram and suspend-to-disk worked. I had to disable the S3 state
> by a custom dsdt, but except that, everything was ok.
>
> Now, after upgrading to stretch, something must have changed in the
> userland. Even after booting with the identical 4.1.38 kernel, 3D
> acceleration broke.
>
> *Q1: What changed in userland, and is there a way to revert the changes?*
>
> I tried now the system with various other kernels. Here is what happens:
>
> - Under 4.9.49 (longterm), 3D acceleration works, the machine enters the
> S1 state, but does not wake up anymore. Trying a suspend-trace, the
> machine claims to hang in power/main.c:
>
> [0.952198] Magic number: 0:791:321
> [0.967849] hash matches drivers/base/power/main.c:742
>
> This is the same location the machine hangs at when allowing it to enter
> S3 (and there does not wake up). A code analysis is inconclusive.
>
> - linux-4.1.38: (The old kernel): With new userland, 3D acceleration
> does not work at all. S1 standby and resume work. With old userland, 3D
> acceleration works before and after resume to S1 state (no issues).
>
> - linux-4.1.44: 3d acceleration with new userland hangs, then stops
> working with a GPU lockup, S1 works as in 4.1.38.
>
> - linux-4.2.8: 3d acceleration with new userland unstable, breaks down
> sooner or later, S1 standby and resume works, but GPU hangs after wakeup
> and is then disabled.
>
> - linux-4.3.6: 3d acceleration works, suspend to ram does not work at
> all, i.e. the system does not even enter the S1 state.
>
> - linux-4.14.0-rc1 (the latest release candidate on www.kernel.org): 3d
> acceleration works, suspend does not work at all, the machine does not
> enter the S1 state.
>
> - linux 4.13.5-rc5+ (intel-drm, head branch): quite the same (machine
> does not enter S1 state)
>
> - linux 4.14.0-rc1+ (intel-drm-nightly): quite the same (machine does
> not enter S1 state).
>
> Enter S1 state: The IBM R31 has a status LED (a moon) that is lit
> whenever the machine is in S1 or S3 state.
>
> Any other hints or pointers I should try - or to help you debugging? It
> is quite unsatisfying that the machine worked perfectly with jessie, but
> 3D broke with the latest userland.
drm-tip + https://patchwork.freedesktop.org/patch/176870/ works rather
well on my 830 machine (Fujitu-Siemens Lifebook S6010). Without that
things gets stuck on account of vblank interrupts getting disabled at
random times. Xonotic has been pretty good at reproducing that bug for
me. Apart from that S3 works, S4 works, never tried S1 and probably
never will since I have S3 ;)
There are some bugs in Mesa though. One at least (a missing workaround)
can cause the GPU to die. I think the current upstream Mesa doesn't hit
it very reliably because it inlines the vertex data into the batch.
I've been working on making it use vertex buffers instead, and I think
that made me hit it more reliably. I have a pile of patches for Mesa
that I need to clean up at some point. In the meantime here's the diff
for that one fix (probably won't apply as is since I have it sitting
on top a pile of other stuff atm):
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 0da5a8118c7f..a9d5a6f37067 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -416,7 +416,7 @@ get_state_size(struct i830_hw_state *state)
sz += sizeof(state->Ctx);
if (dirty & I830_UPLOAD_BUFFERS)
- sz += sizeof(state->Buffer) + 2 * 4; /* 2 relocs */
+ sz += sizeof(state->Buffer) + (2+7) * 4; /* 2 relocs + w/a */
if (dirty & I830_UPLOAD_STIPPLE)
sz += sizeof(state->Stipple);
@@ -514,9 +514,14 @@ i830_emit_state(struct intel_context *intel)
}
if (dirty & I830_UPLOAD_BUFFERS) {
+ /* 830: 3DSTATE_BUFFER_INFO must not straddle two cachlines */
+ int align = (8 - (intel->batch.used & 7)) & 7;
+
DBG("I830_UPLOAD_BUFFERS:\n");
- BEGIN_BATCH(18);
+ BEGIN_BATCH(18+align);
+ while (align--)
+ OUT_BATCH(MI_NOOP);
OUT_BATCH(state->Buffer[I830_DEST
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: enable userspace to program slice/subslice programming (rev2)
== Series Details == Series: drm/i915: enable userspace to program slice/subslice programming (rev2) URL : https://patchwork.freedesktop.org/series/29715/ State : success == Summary == Series 29715v2 drm/i915: enable userspace to program slice/subslice programming https://patchwork.freedesktop.org/api/1.0/series/29715/revisions/2/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (fi-glk-1) fdo#102777 +1 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:418s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:521s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:488s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:493s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:537s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:417s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:627s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:423s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:404s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:430s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:488s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:465s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:472s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:581s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:545s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:449s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:752s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:486s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:471s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:417s e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest debf519bdb29 drm/i915: Expose RPCS (SSEU) configuration to userspace dd07f41f81a8 drm/i915: Record the sseu configuration per-context & engine ce6c3d3f3fbb drm/i915: Program RPCS for Broadwell 806471214773 drm/i915: Record both min/max eu_per_subslice in sseu_dev_info 1039526a05a7 drm/i915: expose helper mapping exec flag engine to intel_engine_cs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5795/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5] drm/i915: Enable scanline read based on frame timestamps
From: Uma Shankar
For certain platforms on certain encoders, timings are driven
from port instead of pipe. Thus, we can't rely on pipe scanline
registers to get the timing information. Some cases scanline
register read will not be functional.
This is causing vblank evasion logic to fail since it relies on
scanline, causing atomic update failure warnings.
This patch uses pipe framestamp and current timestamp registers
to calculate scanline. This is an indirect way to get the scanline.
It helps resolve atomic update failure for gen9 dsi platforms.
v2: Addressed Ville and Daniel's review comments. Updated the
register MACROs, handled race condition for register reads,
extracted timings from the hwmode. Removed the dependency on
crtc->config to get the encoder type.
v3: Made get scanline function generic
v4: Addressed Ville's review comments. Added a flag to decide timestamp
based scanline reporting. Changed 64bit variables to u32
v5: Adressed Ville's review comments. Put the scanline compute function
at the place of caller. Removed hwmode flag from uapi and used a local
private_flag instead.
Credits-to: Ville Syrjälä
Signed-off-by: Uma Shankar
Signed-off-by: Chandra Konduru
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_irq.c | 50 ++
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_drv.h |2 ++
drivers/gpu/drm/i915/intel_dsi.c |7 ++
4 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 91a2c5d..6d7cd20 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -772,6 +772,53 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev,
unsigned int pipe)
return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
}
+/*
+ * On certain encoders on certain platforms, pipe
+ * scanline register will not work to get the scanline,
+ * since the timings are driven from the PORT or issues
+ * with scanline register updates.
+ * This function will use Framestamp and current
+ * timestamp registers to calculate the scanline.
+ */
+u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 vblank_start = crtc->base.hwmode.crtc_vblank_start;
+ u32 vtotal = crtc->base.hwmode.crtc_vtotal;
+ u32 htotal = crtc->base.hwmode.crtc_htotal;
+ u32 clock = crtc->base.hwmode.crtc_clock;
+ u32 scanline = 0, scan_prev_time, scan_curr_time, scan_post_time;
+
+ /* To avoid the race condition where we might cross into the
+* next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
+* reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
+* during the same frame.
+*/
+ do {
+ /*
+* This field provides read back of the display
+* pipe frame time stamp. The time stamp value
+* is sampled at every start of vertical blank.
+*/
+ scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
+
+ /*
+* The TIMESTAMP_CTR register has the current
+* time stamp value.
+*/
+ scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
+
+ scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
+ } while (scan_post_time != scan_prev_time);
+
+ scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
+ clock), 1000 * htotal);
+ scanline = min(scanline, vtotal - 1);
+ scanline = (scanline + vblank_start) % vtotal;
+
+ return scanline;
+}
+
/* I915_READ_FW, only for fast reads of display block, no need for forcewake
etc. */
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
@@ -788,6 +835,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
mode = &vblank->hwmode;
+ if (mode->private_flags & DRM_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
+ return __intel_get_crtc_scanline_from_timestamp(crtc);
+
vtotal = mode->crtc_vtotal;
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f03cd0..fbd00cc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8804,6 +8804,15 @@ enum skl_power_gate {
#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
+/* Gen4+ Timestamp and Pipe Frame time stamp registers */
+#define GEN4_TIMESTAMP _MMIO(0x2358)
+#define ILK_TIMESTAMP_HI _MMIO(0x70070)
+#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
+
+#define _PIPE_FRMTMSTMP_A 0x70048
+#define PIPE_FRMTMST
Re: [Intel-gfx] [PATCH i-g-t] tests/kms_frontbuffer_tracking: Try harder to collect CRC's
Maybe we are missing a vblank wait somewhere on kernel CRC code?!
Or maybe o kernel we read and discard the first for GLK?! :/
Also this is pipe crc right?! Shouldn't it be independent of the panel at
the end?! Does it only happen with MIPI/DSI ?! Or it just happen on that
particular unity on CI that coincidentally has this panel?!
On Fri, Sep 22, 2017 at 5:40 AM Mika Kahola wrote:
> It seems that at least with GLK with MIPI/DSI display, the first collected
> CRC is bogus. To fix this, try to collect two CRC's instead of one.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101309
> Signed-off-by: Mika Kahola
> ---
> tests/kms_frontbuffer_tracking.c | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/tests/kms_frontbuffer_tracking.c
> b/tests/kms_frontbuffer_tracking.c
> index a068c8a..df7cc6e 100644
> --- a/tests/kms_frontbuffer_tracking.c
> +++ b/tests/kms_frontbuffer_tracking.c
> @@ -1239,8 +1239,18 @@ static void print_crc(const char *str, struct
> both_crcs *crc)
>
> static void collect_crcs(struct both_crcs *crcs, bool mandatory_sink_crc)
> {
> - igt_pipe_crc_collect_crc(pipe_crc, &crcs->pipe);
> + int n;
> + igt_crc_t *crc = NULL;
> +
> + igt_pipe_crc_start(pipe_crc);
> + n = igt_pipe_crc_get_crcs(pipe_crc, 2, &crc);
> + igt_pipe_crc_stop(pipe_crc);
> + igt_assert(n > 0);
> + igt_assert_crc_equal(&crc[0], &crc[1]);
> + crcs->pipe = crc[0];
> +
> get_sink_crc(&crcs->sink, mandatory_sink_crc);
> + free(crc);
> }
>
> static void init_blue_crc(enum pixel_format format, bool
> mandatory_sink_crc)
> --
> 2.7.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH i-g-t v2] tests: add slice power programming test
Quoting Lionel Landwerlin (2017-09-22 16:11:33) > Verifies that the kernel programs slices correctly based by reading > the value of PWR_CLK_STATE register. > > v2: Add subslice tests (Lionel) > Use MI_SET_PREDICATE for further verification when available (Lionel) Since this is being created from scratch, prefer the igt routines over libdrm. We don't have to suffer the impedance mismatch in the libdrm_intel interface... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 3/3] drm/i915: Fix default values of some modparams
Quoting Michal Wajdeczko (2017-09-22 15:27:26) > Members should be initialized with values of matching types. > > Signed-off-by: Michal Wajdeczko > Cc: Chris Wilson > Cc: Jani Nikula > Cc: Joonas Lahtinen Reviewed-by: Chris Wilson Perhaps typecheck(T, value) could sneak in somewhere. Add a sanitycheck to i915_params.c? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 2/3] drm/i915: Extend I915_PARAMS_FOR_EACH with default member value
Quoting Michal Wajdeczko (2017-09-22 15:27:25) > By combining default value into helper macro we can initialize > modparams struct in the same automatic way as it was declared. > This will initialize members in the same order as declared > and additionally will disallow declaring new member without > proper default value for it. > > Signed-off-by: Michal Wajdeczko > Cc: Chris Wilson > Cc: Jani Nikula > Cc: Joonas Lahtinen Overall, I think this is a positive change. I'm not completely happy that the param() macro is more readable than the struct assignment, but that is offset by the reduction in duplication. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible
Quoting Michal Wajdeczko (2017-09-22 15:27:24) > We should not add trailing ; after each member allow other > than statements-style uses of this helper macro. > While here s/func/param for clarity. > > Signed-off-by: Michal Wajdeczko > Cc: Chris Wilson > Cc: Jani Nikula Ok, looks like the trailing ; already snuck into the other users. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible
== Series Details == Series: series starting with [RFC,1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible URL : https://patchwork.freedesktop.org/series/30768/ State : success == Summary == Series 30768v1 series starting with [RFC,1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible https://patchwork.freedesktop.org/api/1.0/series/30768/revisions/1/mbox/ Test chamelium: Subgroup dp-edid-read: pass -> FAIL (fi-kbl-7500u) fdo#102672 Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-kbl-r) fdo#102850 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (fi-glk-1) fdo#102777 fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:467s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:414s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:510s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:504s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:490s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:486s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:539s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:413s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:565s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:423s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:404s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:485s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:462s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:465s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s fi-kbl-r total:118 pass:97 dwarn:0 dfail:0 fail:0 skip:20 fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:537s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:468s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:417s e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest 60390eec06dc drm/i915: Fix default values of some modparams 2505ec2c4681 drm/i915: Extend I915_PARAMS_FOR_EACH with default member value b16f668e9734 drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5794/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2] tests: add slice power programming test
Verifies that the kernel programs slices correctly based by reading
the value of PWR_CLK_STATE register.
v2: Add subslice tests (Lionel)
Use MI_SET_PREDICATE for further verification when available (Lionel)
Signed-off-by: Lionel Landwerlin
---
tests/Makefile.sources | 1 +
tests/ctx_rpcs.c | 453 +
tests/meson.build | 1 +
3 files changed, 455 insertions(+)
create mode 100644 tests/ctx_rpcs.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0adc28a0..18d18f08 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -26,6 +26,7 @@ TESTS_progs = \
core_getversion \
core_prop_blob \
core_setmaster_vs_auth \
+ ctx_rpcs \
debugfs_test \
drm_import_export \
drm_mm \
diff --git a/tests/ctx_rpcs.c b/tests/ctx_rpcs.c
new file mode 100644
index ..a127084e
--- /dev/null
+++ b/tests/ctx_rpcs.c
@@ -0,0 +1,453 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Lionel Landwerlin
+ *
+ */
+
+#define _GNU_SOURCE
+#include "igt.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_bufmgr.h"
+
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
+
+#define MI_SET_PREDICATE (0x1 << 23)
+#define MI_SET_PREDICATE_NOOP_NEVER (0)
+#define MI_SET_PREDICATE_1_SLICES (5)
+#define MI_SET_PREDICATE_2_SLICES (6)
+#define MI_SET_PREDICATE_3_SLICES (7)
+
+#define GEN8_R_PWR_CLK_STATE 0x20C8
+#define GEN8_RPCS_ENABLE (1 << 31)
+#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
+#define GEN8_RPCS_S_CNT_SHIFT15
+#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
+#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
+#define GEN8_RPCS_SS_CNT_SHIFT 8
+#define GEN8_RPCS_SS_CNT_MASK(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
+#define GEN8_RPCS_EU_MAX_SHIFT 4
+#define GEN8_RPCS_EU_MAX_MASK(0xf << GEN8_RPCS_EU_MAX_SHIFT)
+#define GEN8_RPCS_EU_MIN_SHIFT 0
+#define GEN8_RPCS_EU_MIN_MASK(0xf << GEN8_RPCS_EU_MIN_SHIFT)
+
+#ifndef I915_PARAM_SLICE_MASK
+#define I915_PARAM_SLICE_MASK (46)
+#define I915_PARAM_SUBSLICE_MASK (47)
+#endif /* I915_PARAM_SLICE_MASK */
+
+#ifndef I915_CONTEXT_PARAM_SSEU
+#define I915_CONTEXT_PARAM_SSEU0x6
+
+struct drm_i915_gem_context_param_sseu {
+ /*
+* Engine to be configured or queried. Same value you would use with
+* drm_i915_gem_execbuffer2.
+*/
+ __u64 flags;
+
+ union {
+ struct {
+ __u8 slice_mask;
+ __u8 subslice_mask;
+ __u8 min_eu_per_subslice;
+ __u8 max_eu_per_subslice;
+ } packed;
+ __u64 value;
+ };
+};
+#endif /* I915_CONTEXT_PARAM_SSEU */
+
+static int drm_fd;
+static int devid;
+static uint64_t device_slice_mask = 0;
+static uint64_t device_subslice_mask = 0;
+static uint32_t device_slice_count = 0;
+static uint32_t device_subslice_count = 0;
+
+static uint64_t mask_minus(uint64_t mask)
+{
+ int i;
+
+ for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
+ if ((1UL << i) & mask) {
+ return mask & ~(1UL << i);
+ }
+ }
+
+ igt_assert(!"reached");
+ return 0;
+}
+
+static uint32_t
+read_rpcs_reg(drm_intel_bufmgr *bufmgr,
+ drm_intel_context *context,
+ uint64_t engine,
+ uint32_t expected_slices)
+{
+ struct intel_batchbuffer *batch;
+ drm_intel_bo *bo;
+ uint32_t rpcs;
+ int ret;
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ intel_batchbuffer_s
[Intel-gfx] [RFC PATCH v2 1/5] drm/i915: expose helper mapping exec flag engine to intel_engine_cs
This function will be used later by the per (context,engine) power
programming interface.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h| 3 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 18 +-
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f5d0e816008d..60c63f141a47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3380,6 +3380,9 @@ int i915_gem_set_domain_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+struct intel_engine_cs *i915_gem_engine_from_flags(struct drm_i915_private
*dev_priv,
+ struct drm_file *file,
+ u64 flags);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d733c4d5a500..6120d22ac145 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2008,12 +2008,12 @@ static const enum intel_engine_id
user_ring_map[I915_USER_RINGS + 1] = {
[I915_EXEC_VEBOX] = VECS
};
-static struct intel_engine_cs *
-eb_select_engine(struct drm_i915_private *dev_priv,
-struct drm_file *file,
-struct drm_i915_gem_execbuffer2 *args)
+struct intel_engine_cs *
+i915_gem_engine_from_flags(struct drm_i915_private *dev_priv,
+ struct drm_file *file,
+ u64 flags)
{
- unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
+ unsigned int user_ring_id = flags & I915_EXEC_RING_MASK;
struct intel_engine_cs *engine;
if (user_ring_id > I915_USER_RINGS) {
@@ -2022,14 +2022,14 @@ eb_select_engine(struct drm_i915_private *dev_priv,
}
if ((user_ring_id != I915_EXEC_BSD) &&
- ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
+ ((flags & I915_EXEC_BSD_MASK) != 0)) {
DRM_DEBUG("execbuf with non bsd ring but with invalid "
- "bsd dispatch flags: %d\n", (int)(args->flags));
+ "bsd dispatch flags: %d\n", (int)(flags));
return NULL;
}
if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
- unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
+ unsigned int bsd_idx = flags & I915_EXEC_BSD_MASK;
if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
@@ -2220,7 +2220,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
- eb.engine = eb_select_engine(eb.i915, file, args);
+ eb.engine = i915_gem_engine_from_flags(eb.i915, file, args->flags);
if (!eb.engine)
return -EINVAL;
--
2.14.1
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[Intel-gfx] [RFC PATCH v2 5/5] drm/i915: Expose RPCS (SSEU) configuration to userspace
From: Chris Wilson
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
first use, the adjustment is for "free"; otherwise if the context is
active we flush the context off the GPU (stalling all users) and forcing
the GPU to save the context to memory where we can modify it and so
ensure that the register is reloaded on next execution.
The overhead of managing additional EU subslices can be significant,
especially in multi-context workloads. Non-GPGPU contexts should
preferably disable the subslices it is not using, and others should
fine-tune the number to match their workload.
We expose complete control over the RPCS register, allowing
configuration of slice/subslice, via masks packed into a u64 for
simplicity. For example,
struct drm_i915_gem_context_param arg;
struct drm_i915_gem_context_param_sseu sseu = { .flags =
I915_EXEC_RENDER };
memset(&arg, 0, sizeof(arg));
arg.ctx_id = ctx;
arg.param = I915_CONTEXT_PARAM_SSEU;
arg.value = (uintptr_t) &sseu;
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg) == 0) {
sseu.packed.subslice_mask = 0;
drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg);
}
could be used to disable all subslices where supported.
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
v3: Add ability to program this per engine (Chris)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
c: Dmitry Rogozhkin
CC: Tvrtko Ursulin
CC: Zhipeng Gong
CC: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_context.c | 49
drivers/gpu/drm/i915/intel_lrc.c| 82 +
drivers/gpu/drm/i915/intel_lrc.h| 5 ++
include/uapi/drm/i915_drm.h | 28 +++
4 files changed, 164 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b386574259a1..088b5035c3a6 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1042,6 +1042,30 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
case I915_CONTEXT_PARAM_BANNABLE:
args->value = i915_gem_context_is_bannable(ctx);
break;
+ case I915_CONTEXT_PARAM_SSEU: {
+ struct drm_i915_gem_context_param_sseu param_sseu;
+ struct intel_engine_cs *engine;
+
+ if (copy_from_user(¶m_sseu, u64_to_user_ptr(args->value),
+ sizeof(param_sseu))) {
+ ret = -EFAULT;
+ break;
+ }
+
+ engine = i915_gem_engine_from_flags(to_i915(dev), file,
+ param_sseu.flags);
+ if (!engine) {
+ ret = -EINVAL;
+ break;
+ }
+
+ param_sseu.value = intel_lr_context_get_sseu(ctx, engine);
+
+ if (copy_to_user(u64_to_user_ptr(args->value), ¶m_sseu,
+sizeof(param_sseu)))
+ ret = -EFAULT;
+ break;
+ }
default:
ret = -EINVAL;
break;
@@ -1097,6 +1121,31 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
else
i915_gem_context_clear_bannable(ctx);
break;
+ case I915_CONTEXT_PARAM_SSEU:
+ if (args->size)
+ ret = -EINVAL;
+ else if (!i915_modparams.enable_execlists)
+ ret = -ENODEV;
+ else {
+ struct drm_i915_gem_context_param_sseu param_sseu;
+ struct intel_engine_cs *engine;
+
+ if (copy_from_user(¶m_sseu,
u64_to_user_ptr(args->value),
+ sizeof(param_sseu))) {
+ ret = -EFAULT;
+ break;
+ }
+
+ engine = i915_gem_engine_from_flags(to_i915(dev), file,
+ param_sseu.flags);
+ if (!engine) {
+ ret = -EINVAL;
+ break;
+ }
+
+ ret = intel_lr_context_set_sseu(ctx, engine,
param_sseu.value);
+ }
+ break;
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/in
[Intel-gfx] [RFC PATCH v2 0/5] drm/i915: enable userspace to program slice/subslice programming
Hi, A small update to all userspace to select the engine to which the slice/subslice configuration applies (as suggested by Chris). Cheers, Chris Wilson (4): drm/i915: Record both min/max eu_per_subslice in sseu_dev_info drm/i915: Program RPCS for Broadwell drm/i915: Record the sseu configuration per-context & engine drm/i915: Expose RPCS (SSEU) configuration to userspace Lionel Landwerlin (1): drm/i915: expose helper mapping exec flag engine to intel_engine_cs drivers/gpu/drm/i915/i915_debugfs.c| 36 +++--- drivers/gpu/drm/i915/i915_drv.h| 21 +- drivers/gpu/drm/i915/i915_gem_context.c| 55 ++ drivers/gpu/drm/i915/i915_gem_context.h| 21 ++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 18 ++--- drivers/gpu/drm/i915/intel_device_info.c | 32 + drivers/gpu/drm/i915/intel_lrc.c | 112 +++-- drivers/gpu/drm/i915/intel_lrc.h | 5 ++ include/uapi/drm/i915_drm.h| 28 9 files changed, 258 insertions(+), 70 deletions(-) -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH v2 3/5] drm/i915: Program RPCS for Broadwell
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may want to
opt out of the "always-enabled" setting.
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 341a4205f480..699398257c37 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1894,13 +1894,6 @@ make_rpcs(struct drm_i915_private *dev_priv)
{
u32 rpcs = 0;
- /*
-* No explicit RPCS request is needed to ensure full
-* slice/subslice/EU enablement prior to Gen9.
- */
- if (INTEL_GEN(dev_priv) < 9)
- return 0;
-
/*
* Starting in Gen9, render power gating can leave
* slice/subslice/EU in a partially enabled state. We
--
2.14.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH v2 2/5] drm/i915: Record both min/max eu_per_subslice in sseu_dev_info
From: Chris Wilson
When we query the available eu on each subslice, we currently only
report the max. It would also be useful to report the minimum found as
well.
When we set RPCS (power gating over the EU), we can also specify both
the min and max number of eu to configure on each slice; currently we
just set it to a single value, but the flexibility may be beneficial in
future.
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 +++-
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_device_info.c | 32 +---
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
4 files changed, 50 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13fc25997d65..fb77ad49d327 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4547,6 +4547,7 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ unsigned int min_eu_per_subslice, max_eu_per_subslice;
int ss_max = 2;
int ss;
u32 sig1[ss_max], sig2[ss_max];
@@ -4556,6 +4557,9 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
+ min_eu_per_subslice = ~0u;
+ max_eu_per_subslice = 0;
+
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4570,14 +4574,18 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
sseu->eu_total += eu_cnt;
- sseu->eu_per_subslice = max_t(unsigned int,
- sseu->eu_per_subslice, eu_cnt);
+ min_eu_per_subslice = min(min_eu_per_subslice, eu_cnt);
+ max_eu_per_subslice = max(max_eu_per_subslice, eu_cnt);
}
+
+ sseu->min_eu_per_subslice = min_eu_per_subslice;
+ sseu->max_eu_per_subslice = max_eu_per_subslice;
}
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ unsigned int min_eu_per_subslice, max_eu_per_subslice;
int s_max = 3, ss_max = 4;
int s, ss;
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
@@ -4603,6 +4611,9 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
GEN9_PGCTL_SSB_EU210_ACK |
GEN9_PGCTL_SSB_EU311_ACK;
+ min_eu_per_subslice = ~0u;
+ max_eu_per_subslice = 0;
+
for (s = 0; s < s_max; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
@@ -4628,11 +4639,14 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
eu_mask[ss%2]);
sseu->eu_total += eu_cnt;
- sseu->eu_per_subslice = max_t(unsigned int,
- sseu->eu_per_subslice,
- eu_cnt);
+
+ min_eu_per_subslice = min(min_eu_per_subslice, eu_cnt);
+ max_eu_per_subslice = max(max_eu_per_subslice, eu_cnt);
}
}
+
+ sseu->min_eu_per_subslice = min_eu_per_subslice;
+ sseu->max_eu_per_subslice = max_eu_per_subslice;
}
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
@@ -4645,9 +4659,11 @@ static void broadwell_sseu_device_status(struct
drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
- sseu->eu_per_subslice =
- INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
- sseu->eu_total = sseu->eu_per_subslice *
+ sseu->min_eu_per_subslice =
+ INTEL_INFO(dev_priv)->sseu.min_eu_per_subslice;
+ sseu->max_eu_per_subslice =
+ INTEL_INFO(dev_priv)->sseu.max_eu_per_subslice;
+ sseu->eu_total = sseu->max_eu_per_subslice *
sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
@@ -4678,8 +4694,8 @@ static void i915_print_sseu_info(struct seq_file *m, bool
is_available_info,
hweight8(sseu->subslice_mask));
seq_printf(m, "
[Intel-gfx] [RFC PATCH v2 4/5] drm/i915: Record the sseu configuration per-context & engine
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration per context & engine (Chris)
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 19 ---
drivers/gpu/drm/i915/i915_gem_context.c | 6 ++
drivers/gpu/drm/i915/i915_gem_context.h | 21 +
drivers/gpu/drm/i915/intel_lrc.c| 23 +--
4 files changed, 36 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2902a0251484..b7ee84317f49 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -799,25 +799,6 @@ struct intel_csr {
func(supports_tv); \
func(has_ipc);
-struct sseu_dev_info {
- u8 slice_mask;
- u8 subslice_mask;
- u8 eu_total;
- u8 min_eu_per_subslice;
- u8 max_eu_per_subslice;
- u8 min_eu_in_pool;
- /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
- u8 subslice_7eu[3];
- u8 has_slice_pg:1;
- u8 has_subslice_pg:1;
- u8 has_eu_pg:1;
-};
-
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
-{
- return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
-}
-
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
INTEL_PLATFORM_UNINITIALIZED = 0,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 921ee369c74d..b386574259a1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -257,6 +257,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *file_priv)
{
struct i915_gem_context *ctx;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
int ret;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
@@ -305,6 +307,10 @@ __create_hw_context(struct drm_i915_private *dev_priv,
* is no remap info, it will be a NOP. */
ctx->remap_slice = ALL_L3_SLICES(dev_priv);
+ /* On all engines, use the whole device by default */
+ for_each_engine(engine, dev_priv, id)
+ ctx->engine[id].sseu = INTEL_INFO(dev_priv)->sseu;
+
i915_gem_context_set_bannable(ctx);
ctx->ring_size = 4 * PAGE_SIZE;
ctx->desc_template =
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index 44688e22a5c2..727b3b5bced1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -40,6 +40,25 @@ struct i915_hw_ppgtt;
struct i915_vma;
struct intel_ring;
+struct sseu_dev_info {
+ u8 slice_mask;
+ u8 subslice_mask;
+ u8 eu_total;
+ u8 min_eu_per_subslice;
+ u8 max_eu_per_subslice;
+ u8 min_eu_in_pool;
+ /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
+ u8 subslice_7eu[3];
+ u8 has_slice_pg:1;
+ u8 has_subslice_pg:1;
+ u8 has_eu_pg:1;
+};
+
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
+{
+ return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
+}
+
#define DEFAULT_CONTEXT_HANDLE 0
/**
@@ -158,6 +177,8 @@ struct i915_gem_context {
u64 lrc_desc;
int pin_count;
bool initialised;
+ /** sseu: Control eu/slice partitioning */
+ struct sseu_dev_info sseu;
} engine[I915_NUM_ENGINES];
/** ring_size: size for allocating the per-engine ring buffer */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 699398257c37..f5e9caf4913c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1889,8 +1889,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
return logical_ring_init(engine);
}
-static u32
-make_rpcs(struct drm_i915_private *dev_priv)
+static u32 make_rpcs(const struct sseu_dev_info *sseu)
{
u32 rpcs = 0;
@@ -1900,25 +1899,21 @@ make_rpcs(struct drm_i915_private *dev_priv)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+ if (sseu->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
- GEN8_RPCS_S_CNT_SHIFT;
+ rpcs |= hweight8(sseu->slice_mask) << GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev_priv)->sseu.has_su
Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read based on frame timestamps
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, September 22, 2017 6:58 PM
>To: Srinivas, Vidya
>Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika ;
>Kamath, Sunil ; Shankar, Uma
>; Konduru, Chandra
>Subject: Re: [PATCH] drm/i915: Enable scanline read based on frame timestamps
>
>On Tue, Sep 19, 2017 at 02:50:03PM +0530, Vidya Srinivas wrote:
>> From: Uma Shankar
>>
>> For certain platforms on certain encoders, timings are driven from
>> port instead of pipe. Thus, we can't rely on pipe scanline registers
>> to get the timing information. Some cases scanline register read may
>> not be functional due to certain hw issues.
>> This is causing vblank evasion logic to fail since it relies on
>> scanline, causing atomic update failure warnings.
>>
>> This patch uses pipe framestamp and current timestamp registers to
>> calculate scanline. This is an indirect way to get the scanline.
>> It helps resolve atomic update failure for gen9 dsi platforms.
>>
>> v2: Addressed Ville and Daniel's review comments. Updated the register
>> MACROs, handled race condition for register reads, extracted timings
>> from the hwmode. Removed the dependency on
>> crtc->config to get the encoder type.
>>
>> v3: Made get scanline function generic
>>
>> v4: Addressed Ville and Maarten's review comments. Used vblank hwmode
>> to get the timings. Added a flag to decide timestamp based scanline
>> reporting. Changed 64bit variables to u32
>
>The patch subject is missing the 'v4'. Which is perhaps why I didn't even
>notice
>this sitting in my inbox. Hint for next time ;)
>
Ok, will be careful next time :)
>>
>> Credits-to: Ville Syrjälä
>> Signed-off-by: Uma Shankar
>> Signed-off-by: Chandra Konduru
>> Signed-off-by: Vidya Srinivas
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> drivers/gpu/drm/i915/i915_irq.c | 4 +++
>> drivers/gpu/drm/i915/i915_reg.h | 9 +++
>> drivers/gpu/drm/i915/intel_display.c | 51
>
>> drivers/gpu/drm/i915/intel_dsi.c | 9 +++
>> include/uapi/drm/drm_mode.h | 3 +++
>> 6 files changed, 78 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 28ad5da..eea374d 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private
>> *dev_priv, u16 reg, u32 value,
>> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32
>> val);
>>
>> +u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc
>> +*crtc);
>
>We have just one caller for this, so it should just live next to that caller.
>
Will remove this.
>> +
>> /* intel_dpio_phy.c */
>> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port
>port,
>> enum dpio_phy *phy, enum dpio_channel *ch); diff --
>git
>> a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 003a928..ccde6c2 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -825,6 +825,10 @@ static int __intel_get_crtc_scanline(struct intel_crtc
>*crtc)
>> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>> vtotal /= 2;
>>
>> +if (mode->flags &
>> +DRM_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
>
>Ahem, private_flags. The fact that you had to modify a uapi header for a flag
>that's only used internally should have have been a red flag (no pun
>intentded).
>
Yeah, while adding only was not 100% sure about this change. Missed that a
private_flag
also exists. Will correct this.
>Also indentation is off.
>
>> +return __intel_get_crtc_scanline_from_timestamp(crtc);
>
>We don't need the vtotal value we computed above, so I think it would be less
>confusing if you do this while thing before we compute vtotal.
>
Will do.
>> +
>> if (IS_GEN2(dev_priv))
>> position = I915_READ_FW(PIPEDSL(pipe)) &
>DSL_LINEMASK_GEN2;
>> else
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 94b40a4..8afb14d 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8806,6 +8806,15 @@ enum skl_power_gate {
>> #define MIPIO_TXESC_CLK_DIV2_MMIO(0x160008)
>> #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
>>
>> +/* Gen4+ Timestamp and Pipe Frame time stamp registers */
>> +#define GEN4_TIMESTAMP 0x2358
>> +#define ILK_TIMESTAMP_HI0x70070
>
>_MMIO missing from those two.
>
Will rectify this.
>> +#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
>> +
>> +#define _PIPE_FRMTMSTMP_A 0x70048
>> +#define PIPE_FRMTMSTMP(pipe)\
>> +_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
>> +
>> /* BXT MIPI clock controls */
>> #define BXT_MAX_VA
[Intel-gfx] [PATCH v8 1/1] drm/i915/huc: Reorganize HuC authentication
Prepared intel_auth_huc to separate HuC specific functionality
from GuC send action. Created new header intel_huc.h to group
HuC specific declarations.
v2: Changed argument preparation for AUTHENTICATE_HUC.
s/intel_auth_huc/intel_huc_auth. Deferred creation of intel_huc.h
to later patch.
v3: Rebase as intel_guc.h is removed. Added param description to
intel_huc_auth. (Michal)
v4: Rebase as intel_guc.h is added again. :)
v5: Rebase w.r.t removal of GuC code restructuring.
v6-v7: Rebase.
v8: Tagged subject as drm/i915/huc. (Michal Wajdeczko)
Added kernel-doc description to intel_huc_auth and intel_guc_auth_huc.
s/dev_priv/i915 and removed unnecessary variable offset. (Joonas)
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_huc.c | 38 ++
drivers/gpu/drm/i915/intel_uc.c | 23 ++-
drivers/gpu/drm/i915/intel_uc.h | 3 ++-
3 files changed, 42 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 6145fa0..821aca4 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -225,19 +225,22 @@ void intel_huc_init_hw(struct intel_huc *huc)
}
/**
- * intel_guc_auth_huc() - authenticate ucode
- * @dev_priv: the drm_i915_device
+ * intel_huc_auth() - Authenticate HuC uCode
+ * @huc: intel_huc structure
+ *
+ * Called after HuC and GuC firmware loading during intel_uc_init_hw().
*
- * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
- * authenticate_huc interface.
+ * This function pins HuC firmware image object into GGTT.
+ * Then it invokes GuC action to authenticate passing the offset to RSA
+ * signature through intel_guc_auth_huc(). It then waits for 50ms for
+ * firmware verification ACK and unpins the object.
*/
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+void intel_huc_auth(struct intel_huc *huc)
{
- struct intel_guc *guc = &dev_priv->guc;
- struct intel_huc *huc = &dev_priv->huc;
+ struct drm_i915_private *i915 = huc_to_i915(huc);
+ struct intel_guc *guc = &i915->guc;
struct i915_vma *vma;
int ret;
- u32 data[2];
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return;
@@ -250,23 +253,19 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
return;
}
- /* Specify auth action and where public signature is. */
- data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
- data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
-
- ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+ ret = intel_guc_auth_huc(guc,
+guc_ggtt_offset(vma) + huc->fw.rsa_offset);
if (ret) {
DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
goto out;
}
/* Check authentication status, it should be done by now */
- ret = intel_wait_for_register(dev_priv,
- HUC_STATUS2,
- HUC_FW_VERIFIED,
- HUC_FW_VERIFIED,
- 50);
-
+ ret = intel_wait_for_register(i915,
+ HUC_STATUS2,
+ HUC_FW_VERIFIED,
+ HUC_FW_VERIFIED,
+ 50);
if (ret) {
DRM_ERROR("HuC: Authentication failed %d\n", ret);
goto out;
@@ -275,4 +274,3 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
out:
i915_vma_unpin(vma);
}
-
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..5752c0f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -328,6 +328,27 @@ static void guc_disable_communication(struct intel_guc
*guc)
guc->send = intel_guc_send_nop;
}
+/**
+ * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
+ * @guc: intel_guc structure
+ * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
+ *
+ * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
+ * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
+ * intel_huc_auth().
+ *
+ * Return: non-zero code on error
+ */
+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
+{
+ u32 action[] = {
+ INTEL_GUC_ACTION_AUTHENTICATE_HUC,
+ rsa_offset
+ };
+
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
+}
+
int intel_uc_init_hw(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
@@ -390,7 +411,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto err_log_capture;
- intel_guc_aut
Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9
On 9/22/2017 5:34 PM, Joonas Lahtinen wrote: On Fri, 2017-09-22 at 15:37 +0530, Sagar Arun Kamble wrote: With GuC v9, new type of Default/critical logging in GuC to enable capturing minimal important logs in production systems efficiently. This patch enables this logging in GuC by default always. It should be noted that streaming support with half-full interrupt mechanism that is present for normal logging is not present for this type of logging. The commit message would be a good place to debrief the user impact. Do we have the tools to capture the new style of log? This has been verified to have minor impact by GuC team. Greg, Harsh can clarify further. Goal was to allow to get GuC logs from production systems. These are the subset of same GuC logs available currently at all GuC log levels and are needed to be captured always whenever we want to capture GuC logs at i915.guc_log_level >=0 and <=3. Chris had suggested on why this is not made on of the log levels and on discussion with Harsh it is concluded that this will not be supported as log level as GuC is using fast functions to log the new critical logs. Also there will not be half-full streaming support for these type of logs. I did have a patch earlier to disable this by default or emulate it as log level to the end user but recommendation from GuC team is to always turn this ON. And question is why do we enable any logging by default, let it have much or little impact on performance? This flag should probably be set through debugfs or some other means when we know we're going to want debugging output. In my earlier patch we did have ability to turn this ON/OFF https://patchwork.freedesktop.org/patch/173884/ v2: Emulated GuC critical logging through i915.guc_log_level. v3: Commit message update. Enable default/critical logging in GuC always. Fixed RPM wake during guc_log_unregister in the unload path. v4: Moved RPM wake change to separate patch. Removed GUC_DEBUG_RESERVED and updated name of new bit to be version agnostic. Updated parameter to struct intel_guc * and name of macro NEEDS_GUC_CRITICAL_LOGGING. Removed explicit clearing of GUC_CRITICAL_LOGGING_DISABLED from params[GUC_CTL_DEBUG] as it is unnecessary. (Michal Wajdeczko) v5: Removed GUC_CRITICAL_LOGGING_DISABLED. Added HAS_GUC check to GUC_NEEDS_CRITICAL_LOGGING. (Michal Wajdeczko) v6: More refined version of GUC_NEEDS_CRITICAL_LOGGING. Commit message update. (Michal Wajdeczko) Cc: Chheda Harsh J Cc: Fry Gregory P Cc: Spotswood John A Cc: Anusha Srivatsa Cc: Michal Wajdeczko Cc: Michał Winiarski Reviewed-by: Michal Wajdeczko Signed-off-by: Jeff McGee Signed-off-by: Sagar Arun Kamble @@ -586,10 +586,18 @@ void intel_guc_log_destroy(struct intel_guc *guc) i915_vma_unpin_and_release(&guc->log.vma); } +/* + * Critical logging in GuC is to be enabled always from GuC v9+. + * (for KBL - v9.39+) + */ +#define GUC_NEEDS_CRITICAL_LOGGING(guc)\ + (HAS_GUC(guc_to_i915(guc)) && \ +(guc->fw.major_ver_found >= 9) && \ +(guc->fw.minor_ver_found >= (IS_KABYLAKE(guc_to_i915(guc)) ? 39 : 0))) I'd like to avoid this kind of conditionals as much as possible, to the extent that we must consider just not loading GuC at all if we're not finding an at least the firmware version we specify our code needs. That's what the distros are going to package, so we don't have to be backwards compatible. So this would be a question of IS_PLATFORM()s like elsewhere in the code once the increased firmware version is specified in the kernel code. Agree that if we make major-wanted = 9 we can avoid this check all together. Currently GuC firmware versions in 01.org are pre version 9 and I have verified that this change is not backward compatible w.r.t v9. Verified that logging does not work for pre-v9 GuC firmwares if we set log_param.critical_logging_enabled unconditionally. @@ -603,6 +611,9 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) if (!log_param.logging_enabled && (i915.guc_log_level < 0)) return 0; + if (GUC_NEEDS_CRITICAL_LOGGING(guc)) + log_param.critical_logging_enabled = 1; + This would then become an "if (INTEL_GEN() >= XYZ)". And it would be highly preferrable to get a backport to all older versions, too. They could even ignore the value if it has no visible effect. I have to admit I think this would be a variable that we read and maybe print a debug if it's up, if the firmware knows it 'needs this flag up always'. Anyway, we just got to organize that CI has both firmware versions (current and desired) in-place, then patches like this just have the 'increase required GuC version number' patch as as a gating in in front of this. Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2) URL : https://patchwork.freedesktop.org/series/30669/ State : success == Summary == Series 30669v2 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs https://patchwork.freedesktop.org/api/1.0/series/30669/revisions/2/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 Test pm_rpm: Subgroup basic-rte: pass -> DMESG-WARN (fi-cfl-s) fdo#102294 Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (fi-glk-1) fdo#102777 +1 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:418s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:527s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:276s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:491s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:497s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:537s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:423s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:565s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:404s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:489s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:461s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:474s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:542s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:450s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:745s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:563s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:419s e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest ddbc734357a9 drm/i915/cnl: Fix SSEU Device Status. 1e3256153139 drm/i915/cnl: Add support slice/subslice/eu configs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5793/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9
On 9/22/2017 3:54 PM, Michal Wajdeczko wrote:
On Fri, 22 Sep 2017 12:07:47 +0200, Sagar Arun Kamble
wrote:
With GuC v9, new type of Default/critical logging in GuC to enable
capturing minimal important logs in production systems efficiently.
This patch enables this logging in GuC by default always. It should
be noted that streaming support with half-full interrupt mechanism
that is present for normal logging is not present for this type of
logging.
v2: Emulated GuC critical logging through i915.guc_log_level.
v3: Commit message update. Enable default/critical logging in GuC
always.
Fixed RPM wake during guc_log_unregister in the unload path.
v4: Moved RPM wake change to separate patch. Removed GUC_DEBUG_RESERVED
and updated name of new bit to be version agnostic. Updated parameter to
struct intel_guc * and name of macro NEEDS_GUC_CRITICAL_LOGGING.
Removed explicit clearing of GUC_CRITICAL_LOGGING_DISABLED from
params[GUC_CTL_DEBUG] as it is unnecessary. (Michal Wajdeczko)
v5: Removed GUC_CRITICAL_LOGGING_DISABLED. Added HAS_GUC check to
GUC_NEEDS_CRITICAL_LOGGING. (Michal Wajdeczko)
v6: More refined version of GUC_NEEDS_CRITICAL_LOGGING. Commit message
update. (Michal Wajdeczko)
Cc: Chheda Harsh J
Cc: Fry Gregory P
Cc: Spotswood John A
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Reviewed-by: Michal Wajdeczko
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 4 ++--
drivers/gpu/drm/i915/intel_guc_log.c | 13 -
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 7eb6b4f..fed875a 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -127,7 +127,6 @@
#define GUC_PROFILE_ENABLED (1 << 7)
#define GUC_WQ_TRACK_ENABLED (1 << 8)
#define GUC_ADS_ENABLED (1 << 9)
-#define GUC_DEBUG_RESERVED (1 << 10)
#define GUC_ADS_ADDR_SHIFT 11
#define GUC_ADS_ADDR_MASK 0xf800
@@ -539,7 +538,8 @@ struct guc_log_buffer_state {
u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
- u32 reserved2:24;
+ u32 critical_logging_enabled:1;
+ u32 reserved2:23;
};
u32 value;
} __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..677ec3d 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -586,10 +586,18 @@ void intel_guc_log_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(&guc->log.vma);
}
+/*
+ * Critical logging in GuC is to be enabled always from GuC v9+.
+ * (for KBL - v9.39+)
+ */
+#define GUC_NEEDS_CRITICAL_LOGGING(guc) \
+ (HAS_GUC(guc_to_i915(guc)) && \
Nitpick: As this macro is now used locally in function that is
called only for platforms with HAS_GUC() then maybe we can drop
that check completely as it is redundant and only check version?
Michal
Yes. Will update.
+ (guc->fw.major_ver_found >= 9) && \
+ (guc->fw.minor_ver_found >= (IS_KABYLAKE(guc_to_i915(guc)) ? 39
: 0)))
+
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64
control_val)
{
struct intel_guc *guc = &dev_priv->guc;
-
union guc_log_control log_param;
int ret;
@@ -603,6 +611,9 @@ int i915_guc_log_control(struct drm_i915_private
*dev_priv, u64 control_val)
if (!log_param.logging_enabled && (i915.guc_log_level < 0))
return 0;
+ if (GUC_NEEDS_CRITICAL_LOGGING(guc))
+ log_param.critical_logging_enabled = 1;
+
ret = guc_log_control(guc, log_param.value);
if (ret < 0) {
DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n",
ret);
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible
We should not add trailing ; after each member allow other
than statements-style uses of this helper macro.
While here s/func/param for clarity.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_params.h | 84 +++---
1 file changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index a2cbb47..0116bb9 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -27,50 +27,50 @@
#include /* for __read_mostly */
-#define I915_PARAMS_FOR_EACH(func) \
- func(char *, vbt_firmware); \
- func(int, modeset); \
- func(int, panel_ignore_lid); \
- func(int, semaphores); \
- func(int, lvds_channel_mode); \
- func(int, panel_use_ssc); \
- func(int, vbt_sdvo_panel_type); \
- func(int, enable_rc6); \
- func(int, enable_dc); \
- func(int, enable_fbc); \
- func(int, enable_ppgtt); \
- func(int, enable_execlists); \
- func(int, enable_psr); \
- func(int, disable_power_well); \
- func(int, enable_ips); \
- func(int, invert_brightness); \
- func(int, enable_guc_loading); \
- func(int, enable_guc_submission); \
- func(int, guc_log_level); \
- func(char *, guc_firmware_path); \
- func(char *, huc_firmware_path); \
- func(int, use_mmio_flip); \
- func(int, mmio_debug); \
- func(int, edp_vswing); \
- func(int, reset); \
- func(unsigned int, inject_load_failure); \
+#define I915_PARAMS_FOR_EACH(param) \
+ param(char *, vbt_firmware) \
+ param(int, modeset) \
+ param(int, panel_ignore_lid) \
+ param(int, semaphores) \
+ param(int, lvds_channel_mode) \
+ param(int, panel_use_ssc) \
+ param(int, vbt_sdvo_panel_type) \
+ param(int, enable_rc6) \
+ param(int, enable_dc) \
+ param(int, enable_fbc) \
+ param(int, enable_ppgtt) \
+ param(int, enable_execlists) \
+ param(int, enable_psr) \
+ param(int, disable_power_well) \
+ param(int, enable_ips) \
+ param(int, invert_brightness) \
+ param(int, enable_guc_loading) \
+ param(int, enable_guc_submission) \
+ param(int, guc_log_level) \
+ param(char *, guc_firmware_path) \
+ param(char *, huc_firmware_path) \
+ param(int, use_mmio_flip) \
+ param(int, mmio_debug) \
+ param(int, edp_vswing) \
+ param(int, reset) \
+ param(unsigned int, inject_load_failure) \
/* leave bools at the end to not create holes */ \
- func(bool, alpha_support); \
- func(bool, enable_cmd_parser); \
- func(bool, enable_hangcheck); \
- func(bool, fastboot); \
- func(bool, prefault_disable); \
- func(bool, load_detect_test); \
- func(bool, force_reset_modeset_test); \
- func(bool, error_capture); \
- func(bool, disable_display); \
- func(bool, verbose_state_checks); \
- func(bool, nuclear_pageflip); \
- func(bool, enable_dp_mst); \
- func(bool, enable_dpcd_backlight); \
- func(bool, enable_gvt)
+ param(bool, alpha_support) \
+ param(bool, enable_cmd_parser) \
+ param(bool, enable_hangcheck) \
+ param(bool, fastboot) \
+ param(bool, prefault_disable) \
+ param(bool, load_detect_test) \
+ param(bool, force_reset_modeset_test) \
+ param(bool, error_capture) \
+ param(bool, disable_display) \
+ param(bool, verbose_state_checks) \
+ param(bool, nuclear_pageflip) \
+ param(bool, enable_dp_mst) \
+ param(bool, enable_dpcd_backlight) \
+ param(bool, enable_gvt)
-#define MEMBER(T, member) T member
+#define MEMBER(T, member) T member;
struct i915_params {
I915_PARAMS_FOR_EACH(MEMBER);
};
--
2.7.4
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 3/3] drm/i915: Fix default values of some modparams
Members should be initialized with values of matching types. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Jani Nikula Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_params.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index da59939..4f3f8d6 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -58,14 +58,14 @@ param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \ param(bool, enable_cmd_parser, true) \ param(bool, enable_hangcheck, true) \ - param(bool, fastboot, 0) \ - param(bool, prefault_disable, 0) \ - param(bool, load_detect_test, 0) \ - param(bool, force_reset_modeset_test, 0) \ + param(bool, fastboot, false) \ + param(bool, prefault_disable, false) \ + param(bool, load_detect_test, false) \ + param(bool, force_reset_modeset_test, false) \ param(bool, error_capture, true) \ - param(bool, disable_display, 0) \ - param(bool, verbose_state_checks, 1) \ - param(bool, nuclear_pageflip, 0) \ + param(bool, disable_display, false) \ + param(bool, verbose_state_checks, true) \ + param(bool, nuclear_pageflip, false) \ param(bool, enable_dp_mst, true) \ param(bool, enable_dpcd_backlight, false) \ param(bool, enable_gvt, false) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/3] drm/i915: Extend I915_PARAMS_FOR_EACH with default member value
By combining default value into helper macro we can initialize
modparams struct in the same automatic way as it was declared.
This will initialize members in the same order as declared
and additionally will disallow declaring new member without
proper default value for it.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Jani Nikula
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 6 +--
drivers/gpu/drm/i915/i915_params.c| 42 ++
drivers/gpu/drm/i915/i915_params.h| 82 +--
4 files changed, 48 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13fc259..29c2299 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -67,7 +67,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
#undef PRINT_FLAG
kernel_param_lock(THIS_MODULE);
-#define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915_modparams.x);
+#define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
I915_PARAMS_FOR_EACH(PRINT_PARAM);
#undef PRINT_PARAM
kernel_param_unlock(THIS_MODULE);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c7aaf62..c76b036 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -567,7 +567,7 @@ static __always_inline void err_print_param(struct
drm_i915_error_state_buf *m,
static void err_print_params(struct drm_i915_error_state_buf *m,
const struct i915_params *p)
{
-#define PRINT(T, x) err_print_param(m, #x, #T, &p->x);
+#define PRINT(T, x, ...) err_print_param(m, #x, #T, &p->x);
I915_PARAMS_FOR_EACH(PRINT);
#undef PRINT
}
@@ -861,7 +861,7 @@ void __i915_gpu_state_free(struct kref *error_ref)
kfree(error->overlay);
kfree(error->display);
-#define FREE(T, x) free_param(#T, &error->params.x);
+#define FREE(T, x, ...) free_param(#T, &error->params.x);
I915_PARAMS_FOR_EACH(FREE);
#undef FREE
@@ -1697,7 +1697,7 @@ static int capture(void *data)
error->i915->gt.last_init_time));
error->params = i915_modparams;
-#define DUP(T, x) dup_param(#T, &error->params.x);
+#define DUP(T, x, ...) dup_param(#T, &error->params.x);
I915_PARAMS_FOR_EACH(DUP);
#undef DUP
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index ec65341..46eab92 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -33,45 +33,9 @@
MODULE_PARM_DESC(name, desc)
struct i915_params i915_modparams __read_mostly = {
- .modeset = -1,
- .panel_ignore_lid = 1,
- .semaphores = -1,
- .lvds_channel_mode = 0,
- .panel_use_ssc = -1,
- .vbt_sdvo_panel_type = -1,
- .enable_rc6 = -1,
- .enable_dc = -1,
- .enable_fbc = -1,
- .enable_execlists = -1,
- .enable_hangcheck = true,
- .enable_ppgtt = -1,
- .enable_psr = -1,
- .alpha_support = IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT),
- .disable_power_well = -1,
- .enable_ips = 1,
- .fastboot = 0,
- .prefault_disable = 0,
- .load_detect_test = 0,
- .force_reset_modeset_test = 0,
- .reset = 2,
- .error_capture = true,
- .invert_brightness = 0,
- .disable_display = 0,
- .enable_cmd_parser = true,
- .use_mmio_flip = 0,
- .mmio_debug = 0,
- .verbose_state_checks = 1,
- .nuclear_pageflip = 0,
- .edp_vswing = 0,
- .enable_guc_loading = 0,
- .enable_guc_submission = 0,
- .guc_log_level = -1,
- .guc_firmware_path = NULL,
- .huc_firmware_path = NULL,
- .enable_dp_mst = true,
- .inject_load_failure = 0,
- .enable_dpcd_backlight = false,
- .enable_gvt = false,
+#define MEMBER(T, member, value) .member = value,
+ I915_PARAMS_FOR_EACH(MEMBER)
+#undef MEMBER
};
i915_param_named(modeset, int, 0400,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 0116bb9..da59939 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -28,49 +28,49 @@
#include /* for __read_mostly */
#define I915_PARAMS_FOR_EACH(param) \
- param(char *, vbt_firmware) \
- param(int, modeset) \
- param(int, panel_ignore_lid) \
- param(int, semaphores) \
- param(int, lvds_channel_mode) \
- param(int, panel_use_ssc) \
- param(int, vbt_sdvo_panel_type) \
- param(int, enable_rc6) \
- param(int, enable_dc) \
- param(int, enable_fbc) \
- param(int, enable_ppgtt) \
- param(int, enable_execlists) \
- param(int, enable_psr) \
- param(int, disable_power_well) \
- param(int, enable_ips)
[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/5] drm/i915: Make own struct for execlist items
== Series Details == Series: series starting with [CI,1/5] drm/i915: Make own struct for execlist items URL : https://patchwork.freedesktop.org/series/30761/ State : warning == Summary == Series 30761v1 series starting with [CI,1/5] drm/i915: Make own struct for execlist items https://patchwork.freedesktop.org/api/1.0/series/30761/revisions/1/mbox/ Test gem_mmap_gtt: Subgroup basic-write-cpu-read-gtt: pass -> DMESG-WARN (fi-kbl-7500u) Test gem_pread: Subgroup basic: pass -> DMESG-WARN (fi-kbl-7500u) Test gem_sync: Subgroup basic-store-all: pass -> DMESG-WARN (fi-kbl-7500u) Test kms_addfb_basic: Subgroup bad-pitch-32: pass -> DMESG-WARN (fi-kbl-7500u) Test kms_busy: Subgroup basic-flip-a: pass -> DMESG-WARN (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> INCOMPLETE (fi-kbl-7500u) fdo#102850 Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (fi-glk-1) fdo#102777 +1 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:437s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:469s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:415s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:500s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:490s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:492s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:541s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:414s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:568s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:424s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:430s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:488s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:462s fi-kbl-7500u total:245 pass:218 dwarn:6 dfail:0 fail:0 skip:20 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:574s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:588s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:539s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:747s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:492s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:469s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:566s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:420s e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest 2fd2949c33c1 drm/i915: Make execlist port count variable 869653ef354d drm/i915: Add execlist_port_complete 0362499b6132 drm/i915: Wrap port cancellation into a function 43f2486ca3d6 drm/i915: Move execlist initialization into intel_engine_cs.c f0df0ae37cca drm/i915: Make own struct for execlist items == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5792/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for igt/kms_psr_sink_crc: Fix the bug in psr_drrs subtest
== Series Details == Series: igt/kms_psr_sink_crc: Fix the bug in psr_drrs subtest URL : https://patchwork.freedesktop.org/series/30727/ State : success == Summary == Test gem_eio: Subgroup in-flight-contexts: dmesg-warn -> PASS (shard-hsw) fdo#102886 +3 Test prime_self_import: Subgroup reimport-vs-gem_close-race: pass -> FAIL (shard-hsw) fdo#102655 Test kms_busy: Subgroup extended-modeset-hang-oldfb-with-reset-render-A: dmesg-warn -> PASS (shard-hsw) fdo#102249 fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886 fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655 fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249 shard-hswtotal:2429 pass:1328 dwarn:5 dfail:0 fail:13 skip:1083 time:9805s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_240/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add Gen10 LRC size
On Fri, Sep 22, 2017 at 6:31 AM Rodrigo Vivi wrote:
> On Thu, Sep 21, 2017 at 11:19:49PM +, Oscar Mateo wrote:
> > The total size of the context has decreased with the removal of the
> > URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
> > one page for PPHWSP, and I'm throwing an extra page for precaution.
>
> I could never find this info on bspec... could you please point that to
> me?
Michal already pointed the doc to me!
Now I know where that comes from! :)
Patch Merges to dinq.
Thanks
>
> Anyways this value matches with other HW engineers had told me a while
> ago, and we now have CNL on CI, so:
>
> Acked-by: Rodrigo Vivi
>
> >
> > Signed-off-by: Oscar Mateo
> > Cc: Rodrigo Vivi
> > Cc: Daniele Ceraolo Spurio
> > Cc: Ben Widawsky
> > ---
> > drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 3d135c3..a3115f3 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -39,6 +39,7 @@
> >
> > #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
> > #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
> > +#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * PAGE_SIZE)
> >
> > #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
> >
> > @@ -150,6 +151,7 @@ struct engine_info {
> > default:
> > MISSING_CASE(INTEL_GEN(dev_priv));
> > case 10:
> > + return GEN10_LR_CONTEXT_RENDER_SIZE;
> > case 9:
> > return GEN9_LR_CONTEXT_RENDER_SIZE;
> > case 8:
> > --
> > 1.9.1
> >
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Fix up too deep reorder-wide()
Like wide(), reorder-wide() didn't check the ring size before flooding
and so would exhaust its available space and block (causing a GPU hang
to recover), thus failing the test. Also, since we use a new context for
each iteration of the test, the available ring space is reduced (due to
the overhead in setting up that context via the ring), so make sure that
when we measure the available ring space we also use a new context.
Signed-off-by: Chris Wilson
---
tests/gem_exec_schedule.c | 225 +++---
1 file changed, 73 insertions(+), 152 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 40f2ebd8..e9b928f1 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -123,96 +123,6 @@ static void store_dword(int fd, uint32_t ctx, unsigned
ring,
gem_close(fd, obj[2].handle);
}
-static uint32_t *make_busy(int fd, uint32_t target, unsigned ring)
-{
- const int gen = intel_gen(intel_get_drm_devid(fd));
- struct drm_i915_gem_exec_object2 obj[2];
- struct drm_i915_gem_relocation_entry reloc[2];
- struct drm_i915_gem_execbuffer2 execbuf;
- uint32_t *batch;
- int i;
-
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(obj + !target);
- execbuf.buffer_count = 1 + !!target;
-
- memset(obj, 0, sizeof(obj));
- obj[0].handle = target;
- obj[1].handle = gem_create(fd, 4096);
- batch = gem_mmap__wc(fd, obj[1].handle, 0, 4096, PROT_WRITE);
- gem_set_domain(fd, obj[1].handle,
- I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
-
- obj[1].relocs_ptr = to_user_pointer(reloc);
- obj[1].relocation_count = 1 + !!target;
- memset(reloc, 0, sizeof(reloc));
-
- reloc[0].target_handle = obj[1].handle; /* recurse */
- reloc[0].presumed_offset = 0;
- reloc[0].offset = sizeof(uint32_t);
- reloc[0].delta = 0;
- reloc[0].read_domains = I915_GEM_DOMAIN_COMMAND;
- reloc[0].write_domain = 0;
-
- reloc[1].target_handle = target;
- reloc[1].presumed_offset = 0;
- reloc[1].offset = 1024;
- reloc[1].delta = 0;
- reloc[1].read_domains = I915_GEM_DOMAIN_COMMAND;
- reloc[1].write_domain = 0;
-
- i = 0;
- batch[i] = MI_BATCH_BUFFER_START;
- if (gen >= 8) {
- batch[i] |= 1 << 8 | 1;
- batch[++i] = 0;
- batch[++i] = 0;
- } else if (gen >= 6) {
- batch[i] |= 1 << 8;
- batch[++i] = 0;
- } else {
- batch[i] |= 2 << 6;
- batch[++i] = 0;
- if (gen < 4) {
- batch[i] |= 1;
- reloc[0].delta = 1;
- }
- }
- i++;
-
- if (ring != -1) {
- execbuf.flags = ring;
- for (int n = 0; n < BUSY_QLEN; n++)
- gem_execbuf(fd, &execbuf);
- } else {
- for_each_engine(fd, ring) {
- if (ring == 0)
- continue;
-
- execbuf.flags = ring;
- for (int n = 0; n < BUSY_QLEN; n++)
- gem_execbuf(fd, &execbuf);
- igt_assert(execbuf.flags == ring);
- }
- }
-
- if (target) {
- execbuf.flags = 0;
- reloc[1].write_domain = I915_GEM_DOMAIN_COMMAND;
- gem_execbuf(fd, &execbuf);
- }
-
- gem_close(fd, obj[1].handle);
-
- return batch;
-}
-
-static void finish_busy(uint32_t *busy)
-{
- *busy = MI_BATCH_BUFFER_END;
- munmap(busy, 4096);
-}
-
struct cork {
int device;
uint32_t handle;
@@ -242,25 +152,50 @@ static void unplug(struct cork *c)
close(c->device);
}
+static void unplug_show_queue(int fd, struct cork *c, unsigned int engine)
+{
+ igt_spin_t *spin;
+ uint32_t ctx;
+
+ ctx = gem_context_create(fd);
+ ctx_set_priority(fd, ctx, MAX_PRIO);
+
+ spin = igt_spin_batch_new(fd, ctx, engine, 0);
+ for (int n = 0; n < BUSY_QLEN; n++) {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = engine,
+ };
+ gem_execbuf(fd, &execbuf);
+ }
+
+ unplug(c); /* batches will now be queued on the engine */
+
+ igt_debugfs_dump(fd, "i915_engine_info");
+ igt_spin_batch_free(fd, spin);
+
+ gem_context_destroy(fd, ctx);
+}
+
static void fifo(int fd, unsigned ring)
{
struct cork cork;
- uint32_t *busy;
uint32_t scratch;
uint32_t *ptr;
scratch = gem_create(fd,
[Intel-gfx] ✗ Fi.CI.IGT: warning for GuC Fixes, HuC auth. reorg and v9+ logging change (rev2)
== Series Details == Series: GuC Fixes, HuC auth. reorg and v9+ logging change (rev2) URL : https://patchwork.freedesktop.org/series/30715/ State : warning == Summary == Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 Test kms_flip: Subgroup wf_vblank-vs-modeset-interruptible: pass -> DMESG-WARN (shard-hsw) fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1328 dwarn:7 dfail:0 fail:11 skip:1083 time:9726s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5789/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add Gen10 LRC size
On Thu, Sep 21, 2017 at 11:19:49PM +, Oscar Mateo wrote:
> The total size of the context has decreased with the removal of the
> URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus
> one page for PPHWSP, and I'm throwing an extra page for precaution.
I could never find this info on bspec... could you please point that to
me?
Anyways this value matches with other HW engineers had told me a while
ago, and we now have CNL on CI, so:
Acked-by: Rodrigo Vivi
>
> Signed-off-by: Oscar Mateo
> Cc: Rodrigo Vivi
> Cc: Daniele Ceraolo Spurio
> Cc: Ben Widawsky
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 3d135c3..a3115f3 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -39,6 +39,7 @@
>
> #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
> #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
> +#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * PAGE_SIZE)
>
> #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
>
> @@ -150,6 +151,7 @@ struct engine_info {
> default:
> MISSING_CASE(INTEL_GEN(dev_priv));
> case 10:
> + return GEN10_LR_CONTEXT_RENDER_SIZE;
> case 9:
> return GEN9_LR_CONTEXT_RENDER_SIZE;
> case 8:
> --
> 1.9.1
>
___
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Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read based on frame timestamps
On Tue, Sep 19, 2017 at 02:50:03PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For certain platforms on certain encoders, timings are driven
> from port instead of pipe. Thus, we can't rely on pipe scanline
> registers to get the timing information. Some cases scanline
> register read may not be functional due to certain hw issues.
> This is causing vblank evasion logic to fail since it relies on
> scanline, causing atomic update failure warnings.
>
> This patch uses pipe framestamp and current timestamp registers
> to calculate scanline. This is an indirect way to get the scanline.
> It helps resolve atomic update failure for gen9 dsi platforms.
>
> v2: Addressed Ville and Daniel's review comments. Updated the
> register MACROs, handled race condition for register reads,
> extracted timings from the hwmode. Removed the dependency on
> crtc->config to get the encoder type.
>
> v3: Made get scanline function generic
>
> v4: Addressed Ville and Maarten's review comments. Used vblank
> hwmode to get the timings. Added a flag to decide timestamp
> based scanline reporting. Changed 64bit variables to u32
The patch subject is missing the 'v4'. Which is perhaps why
I didn't even notice this sitting in my inbox. Hint for next time ;)
>
> Credits-to: Ville Syrjälä
> Signed-off-by: Uma Shankar
> Signed-off-by: Chandra Konduru
> Signed-off-by: Vidya Srinivas
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_irq.c | 4 +++
> drivers/gpu/drm/i915/i915_reg.h | 9 +++
> drivers/gpu/drm/i915/intel_display.c | 51
>
> drivers/gpu/drm/i915/intel_dsi.c | 9 +++
> include/uapi/drm/drm_mode.h | 3 +++
> 6 files changed, 78 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 28ad5da..eea374d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
> u16 reg, u32 value,
> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>
> +u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc);
We have just one caller for this, so it should just live next to that
caller.
> +
> /* intel_dpio_phy.c */
> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port
> port,
>enum dpio_phy *phy, enum dpio_channel *ch);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 003a928..ccde6c2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -825,6 +825,10 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> vtotal /= 2;
>
> + if (mode->flags &
> + DRM_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
Ahem, private_flags. The fact that you had to modify a uapi header for
a flag that's only used internally should have have been a red flag
(no pun intentded).
Also indentation is off.
> + return __intel_get_crtc_scanline_from_timestamp(crtc);
We don't need the vtotal value we computed above, so I think it would
be less confusing if you do this while thing before we compute vtotal.
> +
> if (IS_GEN2(dev_priv))
> position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
> else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94b40a4..8afb14d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8806,6 +8806,15 @@ enum skl_power_gate {
> #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
> #define GLK_TX_ESC_CLK_DIV2_MASK0x3FF
>
> +/* Gen4+ Timestamp and Pipe Frame time stamp registers */
> +#define GEN4_TIMESTAMP 0x2358
> +#define ILK_TIMESTAMP_HI 0x70070
_MMIO missing from those two.
> +#define IVB_TIMESTAMP_CTR_MMIO(0x44070)
> +
> +#define _PIPE_FRMTMSTMP_A0x70048
> +#define PIPE_FRMTMSTMP(pipe) \
> + _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
> +
> /* BXT MIPI clock controls */
> #define BXT_MAX_VAR_OUTPUT_KHZ 39500
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8599e42..c3e86f3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10353,6 +10353,57 @@ static bool needs_scaling(const struct
> intel_plane_state *state)
> return (src_w != dst_w || src_h != dst_h);
> }
>
> +/*
> + * On certain encoders on certain platforms, pipe
> + * scanline register will not work to get the scanline,
> + * since the timings are driven from the PORT or issues
> + * with scanline register updates.
> + * This funct
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make i915_spin_request() static
== Series Details == Series: drm/i915: Make i915_spin_request() static URL : https://patchwork.freedesktop.org/series/30757/ State : success == Summary == Series 30757v1 drm/i915: Make i915_spin_request() static https://patchwork.freedesktop.org/api/1.0/series/30757/revisions/1/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_frontbuffer_tracking: Subgroup basic: pass -> DMESG-WARN (fi-bdw-5557u) fdo#102473 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (fi-glk-1) fdo#102777 +1 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777 fi-bdw-5557u total:289 pass:267 dwarn:1 dfail:0 fail:0 skip:21 time:433s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:470s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:417s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:519s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:502s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:494s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:493s fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:573s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:418s fi-glk-1 total:289 pass:258 dwarn:2 dfail:0 fail:0 skip:29 time:627s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:421s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:403s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:430s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:492s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:466s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:473s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:578s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:583s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:540s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:450s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:753s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:488s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:469s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:570s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:415s d44d1ff55796a6f5e00170948f97fda709d894f4 drm-tip: 2017y-09m-22d-12h-21m-59s UTC integration manifest bc94788ce3d6 drm/i915: Make i915_spin_request() static == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5791/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cnl: Fix SSEU Device Status.
CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.
Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.
The rest is pretty much like gen9.
v2: Remove IS_CANNONLAKE from gen9 status function.
v3: Consider s_max = 6 and ss_max=4 to run over all possible
slices and subslices possible by spec. Although no real
hardware will have that many slices/subslices.
To match with sseu info init.
v4: Fix offset calculation for slices 4 and 5.
Removed Oscar's rv-b since this change also needs review.
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +++--
drivers/gpu/drm/i915/i915_reg.h | 6 +
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e197e5d99277 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
}
}
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+ eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
cherryview_sseu_device_status(dev_priv, &sseu);
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
}
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c257797c583..9729145e6c03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8020,11 +8020,17 @@ enum {
#define CHV_EU311_PG_ENABLE (1<<1)
#define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
+ ((slice) % 3) * 0x4)
#define GEN9_PGCTL_SLICE_ACK
[Intel-gfx] [CI 5/5] drm/i915: Make execlist port count variable
As we emulate execlists on top of the GuC workqueue, it is not
restricted to just 2 ports and we can increase that number arbitrarily
to trade-off queue depth (i.e. scheduling latency) against pipeline
bubbles.
v2: rebase. better commit msg (Chris)
v3: rebase
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c| 10 +-
drivers/gpu/drm/i915/i915_drv.h| 3 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 17 -
drivers/gpu/drm/i915/i915_guc_submission.c | 8 ++--
drivers/gpu/drm/i915/intel_engine_cs.c | 4
drivers/gpu/drm/i915/intel_lrc.c | 6 --
drivers/gpu/drm/i915/intel_ringbuffer.h| 21 +
7 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1470754e53d2..847f8e8d6b58 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3313,6 +3313,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
if (i915_modparams.enable_execlists) {
const u32 *hws =
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ struct intel_engine_execlists * const execlists =
&engine->execlists;
u32 ptr, read, write;
unsigned int idx;
@@ -3324,7 +3325,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
read = GEN8_CSB_READ_PTR(ptr);
write = GEN8_CSB_WRITE_PTR(ptr);
seq_printf(m, "\tExeclist CSB read %d [%d cached],
write %d [%d from hws], interrupt posted? %s\n",
- read, engine->execlists.csb_head,
+ read, execlists->csb_head,
write,
intel_read_status_page(engine,
intel_hws_csb_write_index(engine->i915)),
yesno(test_bit(ENGINE_IRQ_EXECLIST,
@@ -3346,11 +3347,10 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- for (idx = 0; idx < ARRAY_SIZE(engine->execlists.port);
idx++) {
+ for (idx = 0; idx < execlists_num_ports(execlists);
idx++) {
unsigned int count;
- rq = port_unpack(&engine->execlists.port[idx],
-&count);
+ rq = port_unpack(&execlists->port[idx], &count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
idx, count);
@@ -3363,7 +3363,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_unlock();
spin_lock_irq(&engine->timeline->lock);
- for (rb = engine->execlists.first; rb; rb =
rb_next(rb)) {
+ for (rb = execlists->first; rb; rb = rb_next(rb)) {
struct i915_priolist *p =
rb_entry(rb, typeof(*p), node);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f5d0e816008d..c1e93a61d81b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1000,7 +1000,8 @@ struct i915_gpu_state {
u32 seqno;
u32 head;
u32 tail;
- } *requests, execlist[2];
+ } *requests, execlist[EXECLIST_MAX_PORTS];
+ unsigned int num_ports;
struct drm_i915_error_waiter {
char comm[TASK_COMM_LEN];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 45189795be35..12146d70a62e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -396,6 +396,8 @@ static void error_print_context(struct
drm_i915_error_state_buf *m,
static void error_print_engine(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ int n;
+
err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
err_printf(m, " START: 0x%08x\n", ee->start);
err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
@@ -465,8 +467,11 @@ static void error_print_engine(struct
drm_i915_error_state_buf *m,
jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
err_printf(m, " engine reset count: %u\n", ee->reset_count);
- error_print_request(m, " ELSP[0]: ", &ee->execlist[0]);
- error_print_request(m, " ELSP[1]: ", &ee->execlis
[Intel-gfx] [CI 4/5] drm/i915: Add execlist_port_complete
When first execlist entry is processed, we move the port (contents).
Introduce function for this as execlist and guc use this common
operation.
v2: rebase. s/GEM_DEBUG_BUG/GEM_BUG (Chris)
v3: rebase
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submission.c | 8
drivers/gpu/drm/i915/intel_lrc.c | 22 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h| 14 +-
3 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index bce3f1b5892b..55e15a57c3d9 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -592,7 +592,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
rq->priotree.priority = INT_MAX;
__i915_gem_request_submit(rq);
- trace_i915_gem_request_in(rq, port_index(port, engine));
+ trace_i915_gem_request_in(rq, port_index(port,
execlists));
last = rq;
submit = true;
}
@@ -615,7 +615,8 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
static void i915_guc_irq_handler(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
- struct execlist_port *port = engine->execlists.port;
+ struct intel_engine_execlists * const execlists = &engine->execlists;
+ struct execlist_port *port = execlists->port;
struct drm_i915_gem_request *rq;
rq = port_request(&port[0]);
@@ -623,8 +624,7 @@ static void i915_guc_irq_handler(unsigned long data)
trace_i915_gem_request_out(rq);
i915_gem_request_put(rq);
- port[0] = port[1];
- memset(&port[1], 0, sizeof(port[1]));
+ execlists_port_complete(execlists, port);
rq = port_request(&port[0]);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4f625371b5fe..3b03f19f1395 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -454,7 +454,8 @@ static void port_assign(struct execlist_port *port,
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *last;
- struct execlist_port *port = engine->execlists.port;
+ struct intel_engine_execlists * const execlists = &engine->execlists;
+ struct execlist_port *port = execlists->port;
struct rb_node *rb;
bool submit = false;
@@ -468,8 +469,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*/
last->tail = last->wa_tail;
- GEM_BUG_ON(port_isset(&port[1]));
-
/* Hardware submission is through 2 ports. Conceptually each port
* has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
* static for a context, and unique to each, so we only execute
@@ -492,8 +491,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*/
spin_lock_irq(&engine->timeline->lock);
- rb = engine->execlists.first;
- GEM_BUG_ON(rb_first(&engine->execlists.queue) != rb);
+ rb = execlists->first;
+ GEM_BUG_ON(rb_first(&execlists->queue) != rb);
while (rb) {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
struct drm_i915_gem_request *rq, *rn;
@@ -516,7 +515,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* combine this request with the last, then we
* are done.
*/
- if (port != engine->execlists.port) {
+ if (port != execlists->port) {
__list_del_many(&p->requests,
&rq->priotree.link);
goto done;
@@ -541,25 +540,27 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (submit)
port_assign(port, last);
port++;
+
+ GEM_BUG_ON(port_isset(port));
}
INIT_LIST_HEAD(&rq->priotree.link);
rq->priotree.priority = INT_MAX;
__i915_gem_request_submit(rq);
- trace_i915_gem_request_in(rq, port_index(port, engine));
+ trace_i915_gem_request_in(rq, port_index(port,
execlists));
last = rq;
submit = true;
}
rb = rb_next(rb);
- rb_erase(&p->node, &engine->e
[Intel-gfx] [CI 3/5] drm/i915: Wrap port cancellation into a function
On reset and wedged path, we want to release the requests
that are tied to ports and then mark the ports to be unset.
Introduce a function for this.
v2: rebase
v3: drop local, keep GEM_BUG_ON (Michał, Chris)
v4: rebase
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Michał Winiarski
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3186be54bbd8..4f625371b5fe 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -568,21 +568,27 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists_submit_ports(engine);
}
+static void execlist_cancel_port_requests(struct intel_engine_execlists
*execlists)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(execlists->port); i++)
+ i915_gem_request_put(port_request(&execlists->port[i]));
+
+ memset(execlists->port, 0, sizeof(execlists->port));
+}
+
static void execlists_cancel_requests(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- struct execlist_port *port = execlists->port;
struct drm_i915_gem_request *rq, *rn;
struct rb_node *rb;
unsigned long flags;
- unsigned long n;
spin_lock_irqsave(&engine->timeline->lock, flags);
/* Cancel the requests on the HW and clear the ELSP tracker. */
- for (n = 0; n < ARRAY_SIZE(execlists->port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(execlists->port, 0, sizeof(execlists->port));
+ execlist_cancel_port_requests(execlists);
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->timeline->requests, link) {
@@ -613,9 +619,10 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
/* Remaining _unready_ requests will be nop'ed when submitted */
+
execlists->queue = RB_ROOT;
execlists->first = NULL;
- GEM_BUG_ON(port_isset(&port[0]));
+ GEM_BUG_ON(port_isset(&execlists->port[0]));
/*
* The port is checked prior to scheduling a tasklet, but
@@ -1372,11 +1379,9 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
struct drm_i915_gem_request *request)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- struct execlist_port *port = execlists->port;
struct drm_i915_gem_request *rq, *rn;
struct intel_context *ce;
unsigned long flags;
- unsigned int n;
spin_lock_irqsave(&engine->timeline->lock, flags);
@@ -1389,9 +1394,7 @@ static void reset_common_ring(struct intel_engine_cs
*engine,
* guessing the missed context-switch events by looking at what
* requests were completed.
*/
- for (n = 0; n < ARRAY_SIZE(execlists->port); n++)
- i915_gem_request_put(port_request(&port[n]));
- memset(execlists->port, 0, sizeof(execlists->port));
+ execlist_cancel_port_requests(execlists);
/* Push back any incomplete requests for replay after the reset. */
list_for_each_entry_safe_reverse(rq, rn,
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/5] drm/i915: Move execlist initialization into intel_engine_cs.c
Move execlist init into a common engine setup. As it is
common to both guc and hw execlists.
v2: rebase with csb changes
v3: rebase
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 30 --
drivers/gpu/drm/i915/intel_lrc.c | 19 ---
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 957b0d47f635..9e4edd170bed 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -380,6 +380,33 @@ static void intel_engine_init_timeline(struct
intel_engine_cs *engine)
engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
}
+static bool csb_force_mmio(struct drm_i915_private *i915)
+{
+ /* GVT emulation depends upon intercepting CSB mmio */
+ if (intel_vgpu_active(i915))
+ return true;
+
+ /*
+* IOMMU adds unpredictable latency causing the CSB write (from the
+* GPU into the HWSP) to only be visible some time after the interrupt
+* (missed breadcrumb syndrome).
+*/
+ if (intel_vtd_active())
+ return true;
+
+ return false;
+}
+
+static void intel_engine_init_execlist(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists * const execlists = &engine->execlists;
+
+ execlists->csb_use_mmio = csb_force_mmio(engine->i915);
+
+ execlists->queue = RB_ROOT;
+ execlists->first = NULL;
+}
+
/**
* intel_engines_setup_common - setup engine state not requiring hw access
* @engine: Engine to setup.
@@ -391,8 +418,7 @@ static void intel_engine_init_timeline(struct
intel_engine_cs *engine)
*/
void intel_engine_setup_common(struct intel_engine_cs *engine)
{
- engine->execlists.queue = RB_ROOT;
- engine->execlists.first = NULL;
+ intel_engine_init_execlist(engine);
intel_engine_init_timeline(engine);
intel_engine_init_hangcheck(engine);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4f202b840e3d..3186be54bbd8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1784,23 +1784,6 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
}
-static bool irq_handler_force_mmio(struct drm_i915_private *i915)
-{
- /* GVT emulation depends upon intercepting CSB mmio */
- if (intel_vgpu_active(i915))
- return true;
-
- /*
-* IOMMU adds unpredictable latency causing the CSB write (from the
-* GPU into the HWSP) to only be visible some time after the interrupt
-* (missed breadcrumb syndrome).
-*/
- if (intel_vtd_active())
- return true;
-
- return false;
-}
-
static void
logical_ring_setup(struct intel_engine_cs *engine)
{
@@ -1812,8 +1795,6 @@ logical_ring_setup(struct intel_engine_cs *engine)
/* Intentionally left blank. */
engine->buffer = NULL;
- engine->execlists.csb_use_mmio = irq_handler_force_mmio(dev_priv);
-
fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
RING_ELSP(engine),
FW_REG_WRITE);
--
2.11.0
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bios: ignore HDMI on port A (rev2)
== Series Details == Series: drm/i915/bios: ignore HDMI on port A (rev2) URL : https://patchwork.freedesktop.org/series/30700/ State : success == Summary == Test drv_module_reload: Subgroup basic-no-display: dmesg-warn -> PASS (shard-hsw) fdo#102707 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 shard-hswtotal:2429 pass:1333 dwarn:3 dfail:0 fail:10 skip:1083 time:9769s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5781/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] i915_pciids: Change a KBL pci id to GT2 from GT1.5
On Fri, Sep 22, 2017 at 11:23:34AM +, Jani Nikula wrote:
> On Fri, 22 Sep 2017, Jani Nikula wrote:
> > On Fri, 22 Sep 2017, Rodrigo Vivi wrote:
> >> On Thu, Sep 21, 2017 at 10:03:48PM +, Anuj Phogat wrote:
> >>> On Thu, Sep 21, 2017 at 2:58 PM, Rodrigo Vivi
> >>> wrote:
> >>> > In sync with 41693fd52373 ("drm/i915/kbl: Change a KBL pci id
> >>> > to GT2 from GT1.5")
> >>> >
> >>> > "See Mesa commit 9c588ff"
> >>> >
> >>> > Cc: Anuj Phogat
> >>> > Signed-off-by: Rodrigo Vivi
> >>> > ---
> >>> > lib/i915_pciids.h | 2 +-
> >>> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >>> >
> >>> > diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> >>> > index 3e4f9614..0d2b125c 100644
> >>> > --- a/lib/i915_pciids.h
> >>> > +++ b/lib/i915_pciids.h
> >>> > @@ -303,7 +303,6 @@
> >>> > #define INTEL_KBL_GT1_IDS(info)\
> >>> > INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> >>> > INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> >>> > - INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
> >>> > INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> >>> > INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> >>> > INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> >>> > @@ -313,6 +312,7 @@
> >>> >
> >>> > #define INTEL_KBL_GT2_IDS(info)\
> >>> > INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> >>> > + INTEL_VGA_DEVICE(0x5917, info), /* DT GT2 */ \
> >>> Mobile GT2
> >>> > INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
> >>> > INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
> >>> > INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> >>> > --
> >>> > 2.13.5
> >>> >
> >>> With above change:
> >>> Reviewed-by: Anuj Phogat
> >>
> >> Fixed and merged.
> >> Thanks for starting this and for the review.
> >
> > Should it have been Cc: stable? Fixes:?
>
> ...was the kernel patch...?
Hmm... It din't occur to me to add since it was merely informative
and the commit that added here was right by that time.
But for consistency and coherency that should've been :(
>
> J.
>
> >
> > BR,
> > Jani.
> >
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [CI 1/5] drm/i915: Make own struct for execlist items
Engine's execlist related items have been increasing to
a point where a separate struct is warranted. Carve execlist
specific items to a dedicated struct to add clarity.
v2: add kerneldoc and fix whitespace (Joonas, Chris)
v3: csb_mmio changes, rebase
v4: s/\b(el|execlist)\b/execlists/ (Joonas)
Suggested-by: Chris Wilson
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Mika Kuoppala
Acked-by: Joonas Lahtinen
Reviewed-by: Michał Winiarski (v3)
Reviewed-by: Chris Wilson (v3)
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 8 +--
drivers/gpu/drm/i915/i915_gem.c| 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 31 +
drivers/gpu/drm/i915/i915_irq.c| 5 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++--
drivers/gpu/drm/i915/intel_lrc.c | 100 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h| 100 +++--
8 files changed, 167 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13fc25997d65..1470754e53d2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3324,7 +3324,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
read = GEN8_CSB_READ_PTR(ptr);
write = GEN8_CSB_WRITE_PTR(ptr);
seq_printf(m, "\tExeclist CSB read %d [%d cached],
write %d [%d from hws], interrupt posted? %s\n",
- read, engine->csb_head,
+ read, engine->execlists.csb_head,
write,
intel_read_status_page(engine,
intel_hws_csb_write_index(engine->i915)),
yesno(test_bit(ENGINE_IRQ_EXECLIST,
@@ -3346,10 +3346,10 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port);
idx++) {
+ for (idx = 0; idx < ARRAY_SIZE(engine->execlists.port);
idx++) {
unsigned int count;
- rq = port_unpack(&engine->execlist_port[idx],
+ rq = port_unpack(&engine->execlists.port[idx],
&count);
if (rq) {
seq_printf(m, "\t\tELSP[%d] count=%d, ",
@@ -3363,7 +3363,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_unlock();
spin_lock_irq(&engine->timeline->lock);
- for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
+ for (rb = engine->execlists.first; rb; rb =
rb_next(rb)) {
struct i915_priolist *p =
rb_entry(rb, typeof(*p), node);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a650f92aa74..73eeb6b1f1cd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2815,8 +2815,8 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine)
* Turning off the engine->irq_tasklet until the reset is over
* prevents the race.
*/
- tasklet_kill(&engine->irq_tasklet);
- tasklet_disable(&engine->irq_tasklet);
+ tasklet_kill(&engine->execlists.irq_tasklet);
+ tasklet_disable(&engine->execlists.irq_tasklet);
if (engine->irq_seqno_barrier)
engine->irq_seqno_barrier(engine);
@@ -2995,7 +2995,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
{
- tasklet_enable(&engine->irq_tasklet);
+ tasklet_enable(&engine->execlists.irq_tasklet);
kthread_unpark(engine->breadcrumbs.signaler);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c7aaf628e7e0..45189795be35 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1327,10 +1327,10 @@ static void engine_record_requests(struct
intel_engine_cs *engine,
static void error_record_engine_execlists(struct intel_engine_cs *engine,
struct drm_i915_error_engine *ee)
{
- const struct execlist_port *port = engine->execlist_port;
+ const struct execlist_port *port = engine->execlists.port;
unsigned int n;
- for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
+ for (n = 0; n < ARRAY_SIZE(engine->execlists.port); n++) {
struct drm_i915_gem_request *rq = port_request(&port[n]);
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: Add Gen10 LRC size
== Series Details == Series: drm/i915/cnl: Add Gen10 LRC size URL : https://patchwork.freedesktop.org/series/30724/ State : success == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 shard-hswtotal:2429 pass:1329 dwarn:6 dfail:0 fail:11 skip:1083 time:9748s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5787/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests/kms_frontbuffer_tracking: Try harder to collect CRC's
It seems that at least with GLK with MIPI/DSI display, the first collected
CRC is bogus. To fix this, try to collect two CRC's instead of one.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101309
Signed-off-by: Mika Kahola
---
tests/kms_frontbuffer_tracking.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index a068c8a..df7cc6e 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -1239,8 +1239,18 @@ static void print_crc(const char *str, struct both_crcs
*crc)
static void collect_crcs(struct both_crcs *crcs, bool mandatory_sink_crc)
{
- igt_pipe_crc_collect_crc(pipe_crc, &crcs->pipe);
+ int n;
+ igt_crc_t *crc = NULL;
+
+ igt_pipe_crc_start(pipe_crc);
+ n = igt_pipe_crc_get_crcs(pipe_crc, 2, &crc);
+ igt_pipe_crc_stop(pipe_crc);
+ igt_assert(n > 0);
+ igt_assert_crc_equal(&crc[0], &crc[1]);
+ crcs->pipe = crc[0];
+
get_sink_crc(&crcs->sink, mandatory_sink_crc);
+ free(crc);
}
static void init_blue_crc(enum pixel_format format, bool mandatory_sink_crc)
--
2.7.4
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Re: [Intel-gfx] [PATCH i-g-t 3/6] lib/igt_fb: Add igt_cairo_image_surface_create_from_png()
On Fri, Sep 22, 2017 at 03:05:44PM +0300, Ville Syrjälä wrote: > On Fri, Sep 22, 2017 at 12:52:59PM +0300, Petri Latvala wrote: > > On Thu, Sep 21, 2017 at 05:39:30PM +0300, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > Raw usage of cairo_image_surface_create_from_png() doesn't work > > > since it doesn't know about IGT_DATADIR and IGT_SRCDIR. Let's extract > > > the helper from igt_paint_image() that uses igt_fopen_data() + > > > cairo_image_surface_create_from_png_stream() and call it > > > igt_cairo_image_surface_create_from_png_file(). > > > > > > s/from_png_file/from_png/ > > Argh, still one left. My brain kept subconsciously adding the _file() > (to match the _stream() I suppose). In fact at one point I was scratching > my head for quite a while wondering why it wasn't compiling... > > > > > > > > Signed-off-by: Ville Syrjälä > > > > Thanks for fixing this. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92248 > > (Not sure if this patch fixes it yet or if CI switch to make install > > -deployment is also needed) > > Hmm. The asserts I see there seem to be about display commits failing. Oh, gah. The bug report has changed meaning. I was looking at the original description that had Failed assertion: cairo_surface_status(image) == CAIRO_STATUS_SUCCESS > > > kms_plane_fitting doesn't seem to have a separate bug report. > > I'm pretty sure such a bug report did exist in the past. But I > wasn't able to find it either. I guess it was closed for some reason. (For those following along, I did search for kms_panel_fitting too, not just that brainfart of a misname.) I suppose kms_panel_fitting failure is bundled up in #92248 along with kms_plane_scaling. -- Petri Latvala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const
On Thu, 21 Sep 2017, Michal Wajdeczko wrote: > If there is an agreement on merging first patch, can someone give it > r-b and merge ? Note that this patch is prone to rebase conflicts. Pushed the first patch, thanks. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for igt/kms_psr_sink_crc: Fix the bug in psr_drrs subtest
== Series Details == Series: igt/kms_psr_sink_crc: Fix the bug in psr_drrs subtest URL : https://patchwork.freedesktop.org/series/30727/ State : success == Summary == IGT patchset tested on top of latest successful build 3a01e58858e6068f75356e798fd90c80cccb37d6 tests/gem_flink_basic: Add documentation for subtests with latest DRM-Tip kernel build CI_DRM_3121 b32248fc0bd8 drm-tip: 2017y-09m-21d-22h-36m-39s UTC integration manifest Test chamelium: Subgroup common-hpd-after-suspend: dmesg-warn -> INCOMPLETE (fi-kbl-7500u) fdo#102505 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 Test pm_rpm: Subgroup basic-rte: pass -> DMESG-WARN (fi-cfl-s) fdo#102294 fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:439s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:419s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:507s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:505s fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:491s fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:543s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:424s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:572s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:430s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:406s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:437s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:485s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:468s fi-kbl-7500u total:9pass:3dwarn:0 dfail:0 fail:0 skip:5 fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:596s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:539s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:752s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:422s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_240/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Make i915_spin_request() static
On Fri, 2017-09-22 at 13:03 +0100, Chris Wilson wrote: > No users now outside of i915_wait_request(), so we can make it private to > i915_gem_request.c, and assume the caller knows the seqno. In the > process, also remove i915_gem_request_started() as that was only ever > used by i915_spin_request(). > > Signed-off-by: Chris Wilson > Cc: Michal Winiarski > Cc: Tvrtko Ursulin > Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 3/6] lib/igt_fb: Add igt_cairo_image_surface_create_from_png()
On Fri, Sep 22, 2017 at 12:52:59PM +0300, Petri Latvala wrote:
> On Thu, Sep 21, 2017 at 05:39:30PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Raw usage of cairo_image_surface_create_from_png() doesn't work
> > since it doesn't know about IGT_DATADIR and IGT_SRCDIR. Let's extract
> > the helper from igt_paint_image() that uses igt_fopen_data() +
> > cairo_image_surface_create_from_png_stream() and call it
> > igt_cairo_image_surface_create_from_png_file().
>
>
> s/from_png_file/from_png/
Argh, still one left. My brain kept subconsciously adding the _file()
(to match the _stream() I suppose). In fact at one point I was scratching
my head for quite a while wondering why it wasn't compiling...
>
>
> > Signed-off-by: Ville Syrjälä
>
> Thanks for fixing this.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92248
> (Not sure if this patch fixes it yet or if CI switch to make install
> -deployment is also needed)
Hmm. The asserts I see there seem to be about display commits failing.
> kms_plane_fitting doesn't seem to have a separate bug report.
I'm pretty sure such a bug report did exist in the past. But I
wasn't able to find it either. I guess it was closed for some reason.
>
> Reviewed-by: Petri Latvala
Thanks.
>
>
>
>
>
>
> > ---
> > lib/igt_fb.c | 21 ++---
> > lib/igt_fb.h | 1 +
> > 2 files changed, 15 insertions(+), 7 deletions(-)
> >
> > diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> > index 95434a699dcf..d4eaed71acef 100644
> > --- a/lib/igt_fb.c
> > +++ b/lib/igt_fb.c
> > @@ -583,6 +583,18 @@ stdio_read_func(void *closure, unsigned char* data,
> > unsigned int size)
> > return CAIRO_STATUS_SUCCESS;
> > }
> >
> > +cairo_surface_t *igt_cairo_image_surface_create_from_png(const char
> > *filename)
> > +{
> > + cairo_surface_t *image;
> > + FILE *f;
> > +
> > + f = igt_fopen_data(filename);
> > + image = cairo_image_surface_create_from_png_stream(&stdio_read_func, f);
> > + fclose(f);
> > +
> > + return image;
> > +}
> > +
> > /**
> > * igt_paint_image:
> > * @cr: cairo drawing context
> > @@ -601,11 +613,8 @@ void igt_paint_image(cairo_t *cr, const char *filename,
> > cairo_surface_t *image;
> > int img_width, img_height;
> > double scale_x, scale_y;
> > - FILE* f;
> > -
> > - f = igt_fopen_data(filename);
> >
> > - image = cairo_image_surface_create_from_png_stream(&stdio_read_func, f);
> > + image = igt_cairo_image_surface_create_from_png(filename);
> > igt_assert(cairo_surface_status(image) == CAIRO_STATUS_SUCCESS);
> >
> > img_width = cairo_image_surface_get_width(image);
> > @@ -624,8 +633,6 @@ void igt_paint_image(cairo_t *cr, const char *filename,
> > cairo_surface_destroy(image);
> >
> > cairo_restore(cr);
> > -
> > - fclose(f);
> > }
> >
> > /**
> > @@ -877,7 +884,7 @@ unsigned int igt_create_image_fb(int fd, int width, int
> > height,
> > uint32_t fb_id;
> > cairo_t *cr;
> >
> > - image = cairo_image_surface_create_from_png(filename);
> > + image = igt_cairo_image_surface_create_from_png(filename);
> > igt_assert(cairo_surface_status(image) == CAIRO_STATUS_SUCCESS);
> > if (width == 0)
> > width = cairo_image_surface_get_width(image);
> > diff --git a/lib/igt_fb.h b/lib/igt_fb.h
> > index a193a1e7572d..3f549036abc5 100644
> > --- a/lib/igt_fb.h
> > +++ b/lib/igt_fb.h
> > @@ -136,6 +136,7 @@ uint64_t igt_fb_tiling_to_mod(uint64_t tiling);
> >
> > /* cairo-based painting */
> > cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb);
> > +cairo_surface_t *igt_cairo_image_surface_create_from_png(const char
> > *filename);
> > cairo_t *igt_get_cairo_ctx(int fd, struct igt_fb *fb);
> > void igt_paint_color(cairo_t *cr, int x, int y, int w, int h,
> > double r, double g, double b);
> > --
> > 2.13.5
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] i915 Geminilake firmware
On Wed, 20 Sep 2017, Daniel Drake wrote: > We are looking at a geminilake board and i915 is trying to load > glk_dmc_ver1_04.bin. It looks like there isn't any glk firmware in > linux-firmware, would now be a good time to add it? Fail. We're working on resolving this. > ( not sure if it's related to missing firmware but we're also facing > an i915 crash on boot - > filed https://bugs.freedesktop.org/show_bug.cgi?id=102889 ) Unrelated, as you must have guessed by now. ;) BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
