date:20171103

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: implemented dynamic WOPCM partition.

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915: implemented dynamic WOPCM 
partition.
URL   : https://patchwork.freedesktop.org/series/33166/
State : failure

== Summary ==

Series 33166v1 series starting with [1/2] drm/i915: implemented dynamic WOPCM 
partition.
https://patchwork.freedesktop.org/api/1.0/series/33166/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test gem_sync:
Subgroup basic-many-each:
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-skl-6700k)
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS   (fi-bsw-n3050)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-cnl-y)
Subgroup basic-no-display:
pass   -> DMESG-WARN (fi-cnl-y)
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (fi-cnl-y)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:451s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:533s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:514s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:501s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:492s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:560s
fi-cnl-y total:289  pass:259  dwarn:3   dfail:0   fail:0   skip:27  
time:623s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:428s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:262s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:583s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:429s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:426s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:493s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-kbl-7500u total:289  pass:262  dwarn:1   dfail:0   fail:2   skip:24  
time:484s
fi-kbl-7560u total:289  pass:269  dwarn:0   dfail:0   fail:1   skip:19  
time:578s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:585s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:576s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:647s
fi-skl-6700k total:289  pass:264  dwarn:0   dfail:0   fail:1   skip:24  
time:534s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:506s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:456s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:572s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:418s

8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC 
integration manifest
cefdb54d87e8 HAX enable guc submission for CI
3b3d7b841574 drm/i915: implemented dynamic WOPCM partition.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6957/
___
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: implemented dynamic WOPCM partition.

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915: implemented dynamic WOPCM 
partition.
URL   : https://patchwork.freedesktop.org/series/33165/
State : warning

== Summary ==

Series 33165v1 series starting with [1/2] drm/i915: implemented dynamic WOPCM 
partition.
https://patchwork.freedesktop.org/api/1.0/series/33165/revisions/1/mbox/

Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS   (fi-bsw-n3050)
Subgroup suspend-read-crc-pipe-a:
pass   -> SKIP   (fi-hsw-4770r)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-cnl-y)
Subgroup basic-no-display:
pass   -> DMESG-WARN (fi-bsw-n3050)
pass   -> DMESG-WARN (fi-cnl-y)
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (fi-cnl-y)

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:456s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:386s
fi-bsw-n3050 total:289  pass:242  dwarn:1   dfail:0   fail:0   skip:46  
time:556s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:506s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:505s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:486s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:556s
fi-cnl-y total:289  pass:259  dwarn:3   dfail:0   fail:0   skip:27  
time:612s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:263s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:595s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:433s
fi-hsw-4770r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:417s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:503s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:489s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:576s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:567s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:649s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:521s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:463s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:571s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:419s

8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC 
integration manifest
febf0ac24d41 HAX enable guc submission for CI
5d9e2e09e6de drm/i915: implemented dynamic WOPCM partition.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6956/
___
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[Intel-gfx] [PATCH 1/2] drm/i915: implemented dynamic WOPCM partition.

2017-11-03 Thread Jackie Li

Static WOPCM partitioning would lead to GuC loading failure
if the GuC/HuC firmware size exceeded current static 512KB
partition boundary.

This patch enabled the dynamical calculation of the WOPCM aperture
used by GuC/HuC firmware. GuC WOPCM offset was set to
HuC size + reserved WOPCM size. GuC WOPCM size was set to
total WOPCM size - GuC WOPCM offset - RC6CTX size.

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Sujaritha Sundaresan 
Cc: Daniele Ceraolo Spurio 
Cc: John Spotswood 
Cc: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.c |  15 
 drivers/gpu/drm/i915/i915_drv.h |  13 
 drivers/gpu/drm/i915/i915_gem_context.c |   4 +-
 drivers/gpu/drm/i915/i915_guc_reg.h |  18 -
 drivers/gpu/drm/i915/intel_guc.c|  46 ++--
 drivers/gpu/drm/i915/intel_guc.h|  18 +
 drivers/gpu/drm/i915/intel_huc.c|   3 +-
 drivers/gpu/drm/i915/intel_uc.c | 128 +++-
 drivers/gpu/drm/i915/intel_uc_fw.c  |  12 ++-
 9 files changed, 223 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7e9e06..19509fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -623,6 +623,15 @@ static void i915_gem_fini(struct drm_i915_private 
*dev_priv)
WARN_ON(!list_empty(_priv->contexts.list));
 }
 
+static void i915_wopcm_init(struct drm_i915_private *dev_priv)
+{
+   struct intel_wopcm_info *wopcm = _priv->wopcm;
+
+   wopcm->size = WOPCM_DEFAULT_SIZE;
+
+   DRM_DEBUG_DRIVER("WOPCM size: %dKB\n", wopcm->size >> 10);
+}
+
 static int i915_load_modeset_init(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -670,6 +679,12 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
 
+   /*
+* Get the wopcm memory info.
+* NOTE: this need to be called before init FW.
+*/
+   i915_wopcm_init(dev_priv);
+
intel_uc_init_fw(dev_priv);
 
ret = i915_gem_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72bb5b5..61cd290 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2235,6 +2235,16 @@ struct intel_cdclk_state {
u8 voltage_level;
 };
 
+struct intel_wopcm_info {
+   u32 size;
+};
+
+struct intel_wopcm_partition {
+   u32 guc_wopcm_offset;
+   u32 guc_wopcm_size;
+   u32 guc_wopcm_top;
+};
+
 struct drm_i915_private {
struct drm_device drm;
 
@@ -2258,6 +2268,9 @@ struct drm_i915_private {
struct intel_huc huc;
struct intel_guc guc;
 
+   struct intel_wopcm_info wopcm;
+   struct intel_wopcm_partition wopcm_partition;
+
struct intel_csr csr;
 
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 10affb3..7347fd7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -312,12 +312,12 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->desc_template =
default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-   /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
+   /* GuC requires the ring to be placed above guc wopcm top. If GuC is not
 * present or not in use we still need a small bias as ring wraparound
 * at offset 0 sometimes hangs. No idea why.
 */
if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
-   ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+   ctx->ggtt_offset_bias = intel_guc_wopcm_top(dev_priv);
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
 
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 35cf991..d309884 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -67,17 +67,27 @@
 #define DMA_GUC_WOPCM_OFFSET   _MMIO(0xc340)
 #define   HUC_LOADING_AGENT_VCR  (0<<1)
 #define   HUC_LOADING_AGENT_GUC  (1<<1)
-#define   GUC_WOPCM_OFFSET_VALUE 0x8   /* 512KB */
 #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
 
 #define HUC_STATUS2 _MMIO(0xD3B0)
 #define   HUC_FW_VERIFIED   (1<<7)
 
 /* Defines WOPCM space available to GuC firmware */
+/* default WOPCM size 1MB */
+#define WOPCM_DEFAULT_SIZE (0x1 << 20)
+/* reserved WOPCM size 16KB */
+#define WOPCM_RESERVED_SIZE(0x4000)
+/* GUC WOPCM Offset need to be 16KB aligned */
+#define WOPCM_OFFSET_ALIGNMENT

[Intel-gfx] [PATCH 2/2] HAX enable guc submission for CI

2017-11-03 Thread Jackie Li

Signed-off-by: Jackie Li 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
 drivers/gpu/drm/i915/i915_params.h  | 4 ++--
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0684d5d..a351ddf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3562,17 +3562,13 @@ int i915_ggtt_enable_hw(struct drm_i915_private 
*dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-   GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
i915->ggtt.invalidate = guc_ggtt_invalidate;
 }
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
-   /* We should only be called after i915_ggtt_enable_guc() */
-   GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
-   i915->ggtt.invalidate = gen6_ggtt_invalidate;
+   if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+   i915->ggtt.invalidate = gen6_ggtt_invalidate;
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c729226..c38cef0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -44,8 +44,8 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc_loading, 0) \
-   param(int, enable_guc_submission, 0) \
+   param(int, enable_guc_loading, 1) \
+   param(int, enable_guc_submission, 1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 1/2] drm/i915: implemented dynamic WOPCM partition.

2017-11-03 Thread Yaodong Li




On 11/03/2017 05:01 PM, Jackie Li wrote:

Static WOPCM partitioning would lead to GuC loading failure
if the GuC/HuC firmware size exceeded current static 512KB
partition boundary.

This patch enabled the dynamical calculation of the WOPCM aperture
used by GuC/HuC firmware. GuC WOPCM offset was set to
HuC size + reserved WOPCM size. GuC WOPCM size was set to
total WOPCM size - GuC WOPCM offset - RC6CTX size.

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Sujaritha Sundaresan 
Reviewed-by: Daniele Ceraolo Spurio 
Reviewed-by: John Spotswood 
Reviewed-by: Oscar Mateo 


Sorry, these Reviewed-by should be Cc. I will resend the patch.


---
  drivers/gpu/drm/i915/i915_drv.c |  15 
  drivers/gpu/drm/i915/i915_drv.h |  13 
  drivers/gpu/drm/i915/i915_gem_context.c |   4 +-
  drivers/gpu/drm/i915/i915_guc_reg.h |  18 -
  drivers/gpu/drm/i915/intel_guc.c|  46 ++--
  drivers/gpu/drm/i915/intel_guc.h|  18 +
  drivers/gpu/drm/i915/intel_huc.c|   3 +-
  drivers/gpu/drm/i915/intel_uc.c | 128 +++-
  drivers/gpu/drm/i915/intel_uc_fw.c  |  12 ++-
  9 files changed, 223 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7e9e06..19509fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -623,6 +623,15 @@ static void i915_gem_fini(struct drm_i915_private 
*dev_priv)
WARN_ON(!list_empty(_priv->contexts.list));
  }
  
+static void i915_wopcm_init(struct drm_i915_private *dev_priv)

+{
+   struct intel_wopcm_info *wopcm = _priv->wopcm;
+
+   wopcm->size = WOPCM_DEFAULT_SIZE;
+
+   DRM_DEBUG_DRIVER("WOPCM size: %dKB\n", wopcm->size >> 10);
+}
+
  static int i915_load_modeset_init(struct drm_device *dev)
  {
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -670,6 +679,12 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
  
+	/*

+* Get the wopcm memory info.
+* NOTE: this need to be called before init FW.
+*/
+   i915_wopcm_init(dev_priv);
+
intel_uc_init_fw(dev_priv);
  
  	ret = i915_gem_init(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72bb5b5..61cd290 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2235,6 +2235,16 @@ struct intel_cdclk_state {
u8 voltage_level;
  };
  
+struct intel_wopcm_info {

+   u32 size;
+};
+
+struct intel_wopcm_partition {
+   u32 guc_wopcm_offset;
+   u32 guc_wopcm_size;
+   u32 guc_wopcm_top;
+};
+
  struct drm_i915_private {
struct drm_device drm;
  
@@ -2258,6 +2268,9 @@ struct drm_i915_private {

struct intel_huc huc;
struct intel_guc guc;
  
+	struct intel_wopcm_info wopcm;

+   struct intel_wopcm_partition wopcm_partition;
+
struct intel_csr csr;
  
  	struct intel_gmbus gmbus[GMBUS_NUM_PINS];

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 10affb3..7347fd7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -312,12 +312,12 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->desc_template =
default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
  
-	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not

+   /* GuC requires the ring to be placed above guc wopcm top. If GuC is not
 * present or not in use we still need a small bias as ring wraparound
 * at offset 0 sometimes hangs. No idea why.
 */
if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
-   ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+   ctx->ggtt_offset_bias = intel_guc_wopcm_top(dev_priv);
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
  
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h

index 35cf991..d309884 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -67,17 +67,27 @@
  #define DMA_GUC_WOPCM_OFFSET  _MMIO(0xc340)
  #define   HUC_LOADING_AGENT_VCR (0<<1)
  #define   HUC_LOADING_AGENT_GUC (1<<1)
-#define   GUC_WOPCM_OFFSET_VALUE 0x8   /* 512KB */
  #define GUC_MAX_IDLE_COUNT_MMIO(0xC3E4)
  
  #define HUC_STATUS2 _MMIO(0xD3B0)

  #define   HUC_FW_VERIFIED   (1<<7)
  
  /* Defines WOPCM space available to GuC firmware */

+/* default WOPCM size 1MB */
+#define WOPCM_DEFAULT_SIZE (0x1 << 20)
+/*

[Intel-gfx] [PATCH 2/2] HAX enable guc submission for CI

2017-11-03 Thread Jackie Li

Signed-off-by: Jackie Li 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
 drivers/gpu/drm/i915/i915_params.h  | 4 ++--
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0684d5d..a351ddf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3562,17 +3562,13 @@ int i915_ggtt_enable_hw(struct drm_i915_private 
*dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-   GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
i915->ggtt.invalidate = guc_ggtt_invalidate;
 }
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
-   /* We should only be called after i915_ggtt_enable_guc() */
-   GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
-   i915->ggtt.invalidate = gen6_ggtt_invalidate;
+   if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+   i915->ggtt.invalidate = gen6_ggtt_invalidate;
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c729226..c38cef0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -44,8 +44,8 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc_loading, 0) \
-   param(int, enable_guc_submission, 0) \
+   param(int, enable_guc_loading, 1) \
+   param(int, enable_guc_submission, 1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

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[Intel-gfx] [PATCH 1/2] drm/i915: implemented dynamic WOPCM partition.

2017-11-03 Thread Jackie Li

Static WOPCM partitioning would lead to GuC loading failure
if the GuC/HuC firmware size exceeded current static 512KB
partition boundary.

This patch enabled the dynamical calculation of the WOPCM aperture
used by GuC/HuC firmware. GuC WOPCM offset was set to
HuC size + reserved WOPCM size. GuC WOPCM size was set to
total WOPCM size - GuC WOPCM offset - RC6CTX size.

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Sujaritha Sundaresan 
Reviewed-by: Daniele Ceraolo Spurio 
Reviewed-by: John Spotswood 
Reviewed-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.c |  15 
 drivers/gpu/drm/i915/i915_drv.h |  13 
 drivers/gpu/drm/i915/i915_gem_context.c |   4 +-
 drivers/gpu/drm/i915/i915_guc_reg.h |  18 -
 drivers/gpu/drm/i915/intel_guc.c|  46 ++--
 drivers/gpu/drm/i915/intel_guc.h|  18 +
 drivers/gpu/drm/i915/intel_huc.c|   3 +-
 drivers/gpu/drm/i915/intel_uc.c | 128 +++-
 drivers/gpu/drm/i915/intel_uc_fw.c  |  12 ++-
 9 files changed, 223 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7e9e06..19509fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -623,6 +623,15 @@ static void i915_gem_fini(struct drm_i915_private 
*dev_priv)
WARN_ON(!list_empty(_priv->contexts.list));
 }
 
+static void i915_wopcm_init(struct drm_i915_private *dev_priv)
+{
+   struct intel_wopcm_info *wopcm = _priv->wopcm;
+
+   wopcm->size = WOPCM_DEFAULT_SIZE;
+
+   DRM_DEBUG_DRIVER("WOPCM size: %dKB\n", wopcm->size >> 10);
+}
+
 static int i915_load_modeset_init(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -670,6 +679,12 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
 
+   /*
+* Get the wopcm memory info.
+* NOTE: this need to be called before init FW.
+*/
+   i915_wopcm_init(dev_priv);
+
intel_uc_init_fw(dev_priv);
 
ret = i915_gem_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72bb5b5..61cd290 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2235,6 +2235,16 @@ struct intel_cdclk_state {
u8 voltage_level;
 };
 
+struct intel_wopcm_info {
+   u32 size;
+};
+
+struct intel_wopcm_partition {
+   u32 guc_wopcm_offset;
+   u32 guc_wopcm_size;
+   u32 guc_wopcm_top;
+};
+
 struct drm_i915_private {
struct drm_device drm;
 
@@ -2258,6 +2268,9 @@ struct drm_i915_private {
struct intel_huc huc;
struct intel_guc guc;
 
+   struct intel_wopcm_info wopcm;
+   struct intel_wopcm_partition wopcm_partition;
+
struct intel_csr csr;
 
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 10affb3..7347fd7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -312,12 +312,12 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->desc_template =
default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-   /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
+   /* GuC requires the ring to be placed above guc wopcm top. If GuC is not
 * present or not in use we still need a small bias as ring wraparound
 * at offset 0 sometimes hangs. No idea why.
 */
if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
-   ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+   ctx->ggtt_offset_bias = intel_guc_wopcm_top(dev_priv);
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
 
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 35cf991..d309884 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -67,17 +67,27 @@
 #define DMA_GUC_WOPCM_OFFSET   _MMIO(0xc340)
 #define   HUC_LOADING_AGENT_VCR  (0<<1)
 #define   HUC_LOADING_AGENT_GUC  (1<<1)
-#define   GUC_WOPCM_OFFSET_VALUE 0x8   /* 512KB */
 #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
 
 #define HUC_STATUS2 _MMIO(0xD3B0)
 #define   HUC_FW_VERIFIED   (1<<7)
 
 /* Defines WOPCM space available to GuC firmware */
+/* default WOPCM size 1MB */
+#define WOPCM_DEFAULT_SIZE (0x1 << 20)
+/* reserved WOPCM size 16KB */
+#define WOPCM_RESERVED_SIZE(0x4000)
+/* GUC WOPCM Offset need to be 16KB aligned */

Re: [Intel-gfx] [PATCH 06/11] drm/i915: Save all MMIO WAs and apply them at a later time

2017-11-03 Thread Oscar Mateo




On 10/16/2017 03:34 AM, Joonas Lahtinen wrote:

On Fri, 2017-10-13 at 13:49 -0700, Oscar Mateo wrote:

On 10/12/2017 03:35 AM, Joonas Lahtinen wrote:

On Wed, 2017-10-11 at 11:15 -0700, Oscar Mateo wrote:

By doing this, we can dump these workarounds in debugfs for
validation (which,
at the moment, we are only able to do for the contexts WAs).

v2:
- Wrong macro used for MMIO set bit masked
- Improved naming
- Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 




+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1960,12 +1960,16 @@ struct i915_wa_reg {
u32 mask;
   };
   
-#define I915_MAX_WA_REGS 16

+#define I915_MAX_CTX_WA_REGS 16
+#define I915_MAX_MMIO_WA_REGS 32
   
   struct i915_workarounds {

-   struct i915_wa_reg ctx_wa_reg[I915_MAX_WA_REGS];
+   struct i915_wa_reg ctx_wa_reg[I915_MAX_CTX_WA_REGS];
u32 ctx_wa_count;
   
+	struct i915_wa_reg mmio_wa_reg[I915_MAX_MMIO_WA_REGS];

+   u32 mmio_wa_count;
+
u32 hw_whitelist_count[I915_NUM_ENGINES];
   };

Could we instead consider a constant structure with platform bitmasks?
If that's not dynamic enough, then a bitmap which is initialized by the
platform bitmasks as a default. So instead of running code to add to
list, make it bit more declarative. Pseudo-code;


struct i915_workaround {
u16 gen_mask;
enum {
I915_WA_CTX,
I915_WA_MMIO,
I915_WA_WHITELIST,
} type;
u32 reg;
}

... elsewhere in .c file

static const struct i915_workaround i915_workarounds[] = { {
/* WaSomethingSomewhereUMDFoo:skl */
.gen_mask = INTEL_GEN_MASK(X, Y),
.type = I915_WA_CTX,
.reg = ...
} };

Regards, Joonas

I considered it, but we have some workarounds that are even more dynamic
than that. E.g.:

* WaCompressedResourceSamplerPbeMediaNewHashMode depends on
HAS_LLC(dev_priv)
* skl_tune_iz_hashing depends on number of subslices (although maybe
this is not technically a WA?)
* WaGttCachingOffByDefault needs HAS_PAGE_SIZES(dev_priv,
I915_GTT_PAGE_SIZE_2M)
* WaPsrDPRSUnmaskVBlankInSRD is applied for_each_pipe

Could be multiple Wa lines each with HAS_PIPE() condition.


* Wa #1181 needs HAS_PCH_CNP(dev_priv)
* ...

We even have a WA (WaTempDisableDOPClkGating) where the new design is
not dynamic enough :(

I was thinking the array would cover the simple register writes, I
think most of the detection problems could be covered by a simple probe
function. One could consider caching the probing result to a bitmap.


I guess we could add a callback pointer to the table for those WAs that
need extra information. Maybe even a "pre" and a "post" callback
pointers (to cover that pesky WaTempDisableDOPClkGating).

You'd still have to keep some state between pre and post. Maybe just
have I915_WA_FUNC and then a callback to apply the ones not fitting the
"detection" + "simple register write" scheme.



It took me some time, but I found the flaw in this design: I cannot use 
a callback to apply the ones not fitting the"detection" + "simple 
register write" scheme as you mention, because then debugfs will not 
know about those (which was the point of this whole exercise).


I tried something like this:

typedef bool (* wa_pre_hook_func)(struct drm_i915_private *dev_priv,
                  const struct i915_wa_reg *wa,
                  u32 *mask, u32 *value, u32 *data);
typedef void (* wa_post_hook_func)(struct drm_i915_private *dev_priv,
                   const struct i915_wa_reg *wa,
                   u32 data);

In case mask/value need to be recalculated (e.g. skl_tune_iz_hashing or 
WaGttCachingOffByDefault) but then I need to call the pre_hook on 
debugfs, which I might not want to do in all cases (see 
WaProgramL3SqcReg1Default).
I can special-case the problematic WAs, or even left them out of the 
array, but somehow that seems worse than what we already had...


Thoughts?


If this is where we want to go, I can write a patch, but I believe it
would be better to land this first (code review is critical for these
kind of changes, and it is easier to first review that all WAs make it
to i915_workarounds.c correctly, and then review that they are all
transformed to a static table correctly).

First collecting the WA code to same source file is a good idea if that
can be made conveniently, but I would not transform them to arrays or
some other intermediate form like this patch proposes. Instead after
the initial code motion, convert straight to the agreed format.

This is a good clarification to the WAs, so I like the general idea.

Regards, Joonas


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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,01/10] drm/i915: Define an engine class enum for the uABI

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v3,01/10] drm/i915: Define an engine class enum 
for the uABI
URL   : https://patchwork.freedesktop.org/series/33159/
State : failure

== Summary ==

Series 33159v1 series starting with [v3,01/10] drm/i915: Define an engine class 
enum for the uABI
https://patchwork.freedesktop.org/api/1.0/series/33159/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Subgroup common-hpd-after-suspend:
pass   -> INCOMPLETE (fi-skl-6700k)
dmesg-warn -> INCOMPLETE (fi-kbl-7500u) fdo#102505
Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> DMESG-WARN (fi-snb-2520m)
pass   -> DMESG-WARN (fi-snb-2600) fdo#102365
pass   -> DMESG-WARN (fi-ivb-3520m)
pass   -> DMESG-WARN (fi-ivb-3770)
pass   -> DMESG-WARN (fi-byt-j1900)
pass   -> DMESG-WARN (fi-byt-n2820)
pass   -> DMESG-WARN (fi-hsw-4770)
pass   -> DMESG-WARN (fi-hsw-4770r)
pass   -> INCOMPLETE (fi-bdw-5557u)
pass   -> INCOMPLETE (fi-bdw-gvtdvm)
pass   -> INCOMPLETE (fi-bsw-n3050)
pass   -> INCOMPLETE (fi-skl-6260u)
pass   -> INCOMPLETE (fi-skl-6600u)
pass   -> INCOMPLETE (fi-skl-6700hq)
pass   -> INCOMPLETE (fi-skl-6770hq)
pass   -> INCOMPLETE (fi-skl-gvtdvm)
pass   -> INCOMPLETE (fi-bxt-dsi)
pass   -> INCOMPLETE (fi-bxt-j4205)
pass   -> INCOMPLETE (fi-kbl-7560u) fdo#103039
pass   -> INCOMPLETE (fi-kbl-7567u) fdo#102846 +1
pass   -> INCOMPLETE (fi-glk-1)
pass   -> INCOMPLETE (fi-cfl-s) fdo#103186
pass   -> INCOMPLETE (fi-cnl-y)
Subgroup basic-s4-devices:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
pass   -> DMESG-WARN (fi-snb-2520m)
pass   -> DMESG-WARN (fi-snb-2600)
pass   -> DMESG-WARN (fi-ivb-3520m)
pass   -> DMESG-WARN (fi-ivb-3770)
pass   -> DMESG-WARN (fi-byt-j1900)
pass   -> DMESG-WARN (fi-byt-n2820)
pass   -> DMESG-WARN (fi-hsw-4770)
pass   -> DMESG-WARN (fi-hsw-4770r)
Test gem_linear_blits:
Subgroup basic:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
Test gem_render_linear_blits:
Subgroup basic:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
Test gem_render_tiled_blits:
Subgroup basic:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
Test gem_ringfill:
Subgroup basic-default:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
Subgroup basic-default-interruptible:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
Subgroup basic-default-forked:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
Subgroup basic-default-fd:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-default-hang:
dmesg-warn -> SKIP   (fi-blb-e6850) fdo#101600 +1
pass   -> SKIP   (fi-elk-e7500)
Test gem_sync:
Subgroup basic-all:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
Subgroup basic-each:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
Subgroup basic-many-each:
pass   -> SKIP   (fi-blb-e6850)
pass   -> SKIP   (fi-pnv-d510)
pass   -> SKIP   (fi-elk-e7500)
Subgroup basic-store-all:

[Intel-gfx] ✗ Fi.CI.BAT: failure for HAX drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Patchwork

== Series Details ==

Series: HAX drm/i915: Move init_clock_gating() back to where it was
URL   : https://patchwork.freedesktop.org/series/33158/
State : failure

== Summary ==

Series 33158v1 HAX drm/i915: Move init_clock_gating() back to where it was
https://patchwork.freedesktop.org/api/1.0/series/33158/revisions/1/mbox/

Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test gem_exec_reloc:
Subgroup basic-gtt-cpu-active:
pass   -> FAIL   (fi-gdg-551) fdo#102582 +3
Subgroup basic-write-cpu-active:
pass   -> FAIL   (fi-gdg-551)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS   (fi-bsw-n3050)

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:442s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:454s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:378s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:505s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:506s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:489s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:555s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:426s
fi-gdg-551   total:289  pass:173  dwarn:1   dfail:0   fail:6   skip:109 
time:263s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:580s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:429s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:430s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:488s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:574s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:572s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:645s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:520s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:507s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:459s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:595s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:419s
fi-cnl-y failed to connect after reboot

8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC 
integration manifest
967aa5648a14 HAX drm/i915: Move init_clock_gating() back to where it was

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6954/
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[Intel-gfx] [PATCH v3 10/10] drm/i915: Stop caching the "golden" renderstate

2017-11-03 Thread Chris Wilson

As we now record the default HW state and so only emit the "golden"
renderstate once to prepare the HW, there is no advantage in keeping the
renderstate batch around as it will never be used again.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h  |   1 -
 drivers/gpu/drm/i915/i915_gem_render_state.c | 135 +--
 drivers/gpu/drm/i915/i915_gem_render_state.h |   4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   |   9 +-
 drivers/gpu/drm/i915/intel_lrc.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   5 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 -
 7 files changed, 51 insertions(+), 106 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 466ee055030b..71747131c444 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,7 +67,6 @@
 #include "i915_gem_fence_reg.h"
 #include "i915_gem_object.h"
 #include "i915_gem_gtt.h"
-#include "i915_gem_render_state.h"
 #include "i915_gem_request.h"
 #include "i915_gem_timeline.h"
 
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 3703dc91eeda..69621d887975 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -26,10 +26,12 @@
  */
 
 #include "i915_drv.h"
+#include "i915_gem_render_state.h"
 #include "intel_renderstate.h"
 
 struct intel_render_state {
const struct intel_renderstate_rodata *rodata;
+   struct drm_i915_gem_object *obj;
struct i915_vma *vma;
u32 batch_offset;
u32 batch_size;
@@ -74,17 +76,16 @@ static int render_state_setup(struct intel_render_state *so,
  struct drm_i915_private *i915)
 {
const struct intel_renderstate_rodata *rodata = so->rodata;
-   struct drm_i915_gem_object *obj = so->vma->obj;
unsigned int i = 0, reloc_index = 0;
unsigned int needs_clflush;
u32 *d;
int ret;
 
-   ret = i915_gem_obj_prepare_shmem_write(obj, _clflush);
+   ret = i915_gem_obj_prepare_shmem_write(so->obj, _clflush);
if (ret)
return ret;
 
-   d = kmap_atomic(i915_gem_object_get_dirty_page(obj, 0));
+   d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0));
 
while (i < rodata->batch_items) {
u32 s = rodata->batch[i];
@@ -112,7 +113,7 @@ static int render_state_setup(struct intel_render_state *so,
goto err;
}
 
-   so->batch_offset = so->vma->node.start;
+   so->batch_offset = i915_ggtt_offset(so->vma);
so->batch_size = rodata->batch_items * sizeof(u32);
 
while (i % CACHELINE_DWORDS)
@@ -160,9 +161,9 @@ static int render_state_setup(struct intel_render_state *so,
drm_clflush_virt_range(d, i * sizeof(u32));
kunmap_atomic(d);
 
-   ret = i915_gem_object_set_to_gtt_domain(obj, false);
+   ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
 out:
-   i915_gem_obj_finish_shmem_access(obj);
+   i915_gem_obj_finish_shmem_access(so->obj);
return ret;
 
 err:
@@ -173,112 +174,64 @@ static int render_state_setup(struct intel_render_state 
*so,
 
 #undef OUT_BATCH
 
-int i915_gem_render_state_init(struct intel_engine_cs *engine)
+int i915_gem_render_state_emit(struct drm_i915_gem_request *rq)
 {
-   struct intel_render_state *so;
-   const struct intel_renderstate_rodata *rodata;
-   struct drm_i915_gem_object *obj;
-   int ret;
+   struct intel_engine_cs *engine = rq->engine;
+   struct intel_render_state so;
+   int err;
 
if (engine->id != RCS)
return 0;
 
-   rodata = render_state_get_rodata(engine);
-   if (!rodata)
+   so.rodata = render_state_get_rodata(engine);
+   if (!so.rodata)
return 0;
 
-   if (rodata->batch_items * 4 > PAGE_SIZE)
+   if (so.rodata->batch_items * 4 > PAGE_SIZE)
return -EINVAL;
 
-   so = kmalloc(sizeof(*so), GFP_KERNEL);
-   if (!so)
-   return -ENOMEM;
+   so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+   if (IS_ERR(so.obj))
+   return PTR_ERR(so.obj);
 
-   obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
-   if (IS_ERR(obj)) {
-   ret = PTR_ERR(obj);
-   goto err_free;
-   }
-
-   so->vma = i915_vma_instance(obj, >i915->ggtt.base, NULL);
-   if (IS_ERR(so->vma)) {
-   ret = PTR_ERR(so->vma);
+   so.vma = i915_vma_instance(so.obj, >i915->ggtt.base, NULL);
+   if (IS_ERR(so.vma)) {
+   err = PTR_ERR(so.vma);
goto err_obj;
}
 
-   so->rodata = rodata;
-   engine->render_state = so;
-   return 0;
-
-err_obj:
-

[Intel-gfx] [PATCH v3 08/10] drm/i915: Report whether we have true context isolation

2017-11-03 Thread Chris Wilson

Let userspace know if they can trust that new contexts are created using
HW default values; and avoid inheriting state from existing contexts.

Note: I intend to squash this into the bugfix once we agree on the uabi.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c | 11 +++
 include/uapi/drm/i915_drm.h | 14 ++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1b440f2b90a5..fa4839bcdd63 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -406,6 +406,17 @@ static int i915_getparam(struct drm_device *dev, void 
*data,
 */
value = 1;
break;
+   case I915_PARAM_HAS_CONTEXT_ISOLATION:
+   {
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   value = 0;
+   for_each_engine(engine, dev_priv, id)
+   if (engine->default_state)
+   value |= BIT(engine->uabi_class);
+   }
+   break;
case I915_PARAM_SLICE_MASK:
value = INTEL_INFO(dev_priv)->sseu.slice_mask;
if (!value)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 65d06da62599..cce3c7b6a4ab 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -465,6 +465,20 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY  49
 
+/*
+ * Query whether every context (both per-file default and user created) is
+ * isolated (insofar as HW supports). If this parameter is not true, then
+ * freshly created contexts may inherit values from an existing context,
+ * rather than default HW values. If true, it also ensures (insofar as HW
+ * supports) that all state set by this context will not leak to any other
+ * context.
+ *
+ * As not every engine support contexts, the returned value reports the
+ * support of context isolation for individual engines by returning
+ * a bitmask of each engine class set to true if that class supports isolation.
+ */
+#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
+
 typedef struct drm_i915_getparam {
__s32 param;
/*
-- 
2.15.0

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[Intel-gfx] [PATCH v3 09/10] drm/i915: Remove redundant intel_autoenable_gt_powersave()

2017-11-03 Thread Chris Wilson

Now that we always execute a context switch upon module load, there is
no need to queue a delayed task for doing so. The purpose of the delayed
task is to enable GT powersaving, for which we need the HW state to be
valid (i.e. having loaded a context and initialised basic state). We
used to defer this operation as historically it was slow (due to slow
register polling, fixed with commit 1758b90e38f5 ("drm/i915: Use a hybrid
scheme for fast register waits")) but now we have a requirement to save
the default HW state.

v2: Load the kernel context (to provide the power context) upon resume.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c  |  2 --
 drivers/gpu/drm/i915/i915_drv.h  |  1 -
 drivers/gpu/drm/i915/i915_gem.c  | 19 ++--
 drivers/gpu/drm/i915/intel_drv.h |  1 -
 drivers/gpu/drm/i915/intel_pm.c  | 66 
 5 files changed, 10 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fa4839bcdd63..ba54bf1e806f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1754,8 +1754,6 @@ static int i915_drm_resume(struct drm_device *dev)
 
intel_opregion_notify_adapter(dev_priv, PCI_D0);
 
-   intel_autoenable_gt_powersave(dev_priv);
-
enable_rpm_wakeref_asserts(dev_priv);
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 593714fe5c5e..466ee055030b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1388,7 +1388,6 @@ struct intel_gen6_power_mgmt {
struct intel_rps rps;
struct intel_rc6 rc6;
struct intel_llc_pstate llc_pstate;
-   struct delayed_work autoenable_work;
 };
 
 /* defined intel_pm.c */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d055db1a68c5..b7fafcf8d7a6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4793,23 +4793,24 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
return ret;
 }
 
-void i915_gem_resume(struct drm_i915_private *dev_priv)
+void i915_gem_resume(struct drm_i915_private *i915)
 {
-   struct drm_device *dev = _priv->drm;
-
-   WARN_ON(dev_priv->gt.awake);
+   WARN_ON(i915->gt.awake);
 
-   mutex_lock(>struct_mutex);
-   i915_gem_restore_gtt_mappings(dev_priv);
-   i915_gem_restore_fences(dev_priv);
+   mutex_lock(>drm.struct_mutex);
+   i915_gem_restore_gtt_mappings(i915);
+   i915_gem_restore_fences(i915);
 
/* As we didn't flush the kernel context before suspend, we cannot
 * guarantee that the context image is complete. So let's just reset
 * it and start again.
 */
-   dev_priv->gt.resume(dev_priv);
+   i915->gt.resume(i915);
 
-   mutex_unlock(>struct_mutex);
+   /* Always reload a context for powersaving. */
+   i915_gem_switch_to_kernel_context(i915);
+
+   mutex_unlock(>drm.struct_mutex);
 }
 
 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 00b488688042..76b12fb1a35f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1881,7 +1881,6 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv);
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
 void gen6_rps_busy(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e1358d4e764..308439dd89d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7941,8 +7941,6 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
rps->boost_freq = rps->max_freq;
 
mutex_unlock(_priv->pcu_lock);
-
-   intel_autoenable_gt_powersave(dev_priv);
 }
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
@@ -7967,9 +7965,6 @@ void intel_suspend_gt_powersave(struct drm_i915_private 
*dev_priv)
if (INTEL_GEN(dev_priv) < 6)
return;
 
-   if (cancel_delayed_work_sync(_priv->gt_pm.autoenable_work))
-   intel_runtime_pm_put(dev_priv);
-
/* gen6_rps_idle() will be called later to disable interrupts */
 }
 
@@ -8128,65 +8123,6 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
mutex_unlock(_priv->pcu_lock);
 }
 
-static void __intel_autoenable_gt_powersave(struct

[Intel-gfx] [PATCH v3 05/10] drm/i915: Inline intel_modeset_gem_init()

2017-11-03 Thread Chris Wilson

intel_modeset_gem_init() now only sets up the legacy overlay, so let's
remove the function and call the setup directly during driver load. This
should help us find a better point in the initialisation sequence for it
later.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.c  | 2 +-
 drivers/gpu/drm/i915/i915_drv.h  | 1 -
 drivers/gpu/drm/i915/intel_display.c | 7 ---
 3 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7e9e061073b..1b440f2b90a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -676,7 +676,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_uc;
 
-   intel_modeset_gem_init(dev);
+   intel_setup_overlay(dev_priv);
 
if (INTEL_INFO(dev_priv)->num_pipes == 0)
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72bb5b51035a..593714fe5c5e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4118,7 +4118,6 @@ void intel_device_info_dump(struct drm_i915_private 
*dev_priv);
 /* modesetting */
 extern void intel_modeset_init_hw(struct drm_device *dev);
 extern int intel_modeset_init(struct drm_device *dev);
-extern void intel_modeset_gem_init(struct drm_device *dev);
 extern void intel_modeset_cleanup(struct drm_device *dev);
 extern int intel_connector_register(struct drm_connector *);
 extern void intel_connector_unregister(struct drm_connector *);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c3bf87c2036c..5debb79540a2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15170,13 +15170,6 @@ void intel_display_resume(struct drm_device *dev)
drm_atomic_state_put(state);
 }
 
-void intel_modeset_gem_init(struct drm_device *dev)
-{
-   struct drm_i915_private *dev_priv = to_i915(dev);
-
-   intel_setup_overlay(dev_priv);
-}
-
 int intel_connector_register(struct drm_connector *connector)
 {
struct intel_connector *intel_connector = to_intel_connector(connector);
-- 
2.15.0

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[Intel-gfx] [PATCH v3 01/10] drm/i915: Define an engine class enum for the uABI

2017-11-03 Thread Chris Wilson

From: Tvrtko Ursulin 

We want to be able to report back to userspace details about an engine's
class, and in return for userspace to be able to request actions
regarding certain classes of engines. To isolate the uABI from any
variations between hw generations, we define an abstract class for the
engines and internally map onto the hw.

v2: Remove MAX from the uABI; keep it internal if we need it, but don't
let userspace make the mistake of using it themselves.

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 10 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 -
 include/uapi/drm/i915_drm.h | 15 +++
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ddbe5c9bf45a..0987768c311d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -50,6 +50,8 @@ struct engine_class_info {
const char *name;
int (*init_legacy)(struct intel_engine_cs *engine);
int (*init_execlists)(struct intel_engine_cs *engine);
+
+   u8 uabi_class;
 };
 
 static const struct engine_class_info intel_engine_classes[] = {
@@ -57,21 +59,25 @@ static const struct engine_class_info 
intel_engine_classes[] = {
.name = "rcs",
.init_execlists = logical_render_ring_init,
.init_legacy = intel_init_render_ring_buffer,
+   .uabi_class = I915_ENGINE_CLASS_RENDER,
},
[COPY_ENGINE_CLASS] = {
.name = "bcs",
.init_execlists = logical_xcs_ring_init,
.init_legacy = intel_init_blt_ring_buffer,
+   .uabi_class = I915_ENGINE_CLASS_COPY,
},
[VIDEO_DECODE_CLASS] = {
.name = "vcs",
.init_execlists = logical_xcs_ring_init,
.init_legacy = intel_init_bsd_ring_buffer,
+   .uabi_class = I915_ENGINE_CLASS_VIDEO,
},
[VIDEO_ENHANCEMENT_CLASS] = {
.name = "vecs",
.init_execlists = logical_xcs_ring_init,
.init_legacy = intel_init_vebox_ring_buffer,
+   .uabi_class = I915_ENGINE_CLASS_VIDEO_ENHANCE,
},
 };
 
@@ -213,13 +219,15 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s%u",
 class_info->name, info->instance) >=
sizeof(engine->name));
-   engine->uabi_id = info->uabi_id;
engine->hw_id = engine->guc_id = info->hw_id;
engine->mmio_base = info->mmio_base;
engine->irq_shift = info->irq_shift;
engine->class = info->class;
engine->instance = info->instance;
 
+   engine->uabi_id = info->uabi_id;
+   engine->uabi_class = class_info->uabi_class;
+
engine->context_size = __intel_engine_context_size(dev_priv,
   engine->class);
if (WARN_ON(engine->context_size > BIT(20)))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 69ad875fd011..f3dbfe7ae6e4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -289,11 +289,14 @@ struct intel_engine_execlists {
 struct intel_engine_cs {
struct drm_i915_private *i915;
char name[INTEL_ENGINE_CS_MAX_NAME];
+
enum intel_engine_id id;
-   unsigned int uabi_id;
unsigned int hw_id;
unsigned int guc_id;
 
+   u8 uabi_id;
+   u8 uabi_class;
+
u8 class;
u8 instance;
u32 context_size;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ac3c6503ca27..65d06da62599 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -86,6 +86,21 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
 };
 
+/*
+ * Different engines serve different roles, and there may be more than one
+ * engine serving each role. enum drm_i915_gem_engine_class provides a
+ * classification of the role of the engine, which may be used when requesting
+ * operations to be performed on a certain subset of engines, or for providing
+ * information about that group.
+ */
+enum drm_i915_gem_engine_class {
+   I915_ENGINE_CLASS_OTHER = 0,
+   I915_ENGINE_CLASS_RENDER = 1,
+   I915_ENGINE_CLASS_COPY = 2,
+   I915_ENGINE_CLASS_VIDEO = 3,
+   I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+};
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255/* table size 2k - maximum due to use
-- 
2.15.0

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[Intel-gfx] [PATCH v3 07/10] drm/i915: Record the default hw state after reset upon load

2017-11-03 Thread Chris Wilson

Take a copy of the HW state after a reset upon module loading by
executing a context switch from a blank context to the kernel context,
thus saving the default hw state over the blank context image.
We can then use the default hw state to initialise any future context,
ensuring that each starts with the default view of hw state.

v2: Unmap our default state from the GTT after stealing it from the
context. This should stop us from accidentally overwriting it via the
GTT (and frees up some precious GTT space).

Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/gvt/scheduler.c|   2 -
 drivers/gpu/drm/i915/i915_debugfs.c |   1 -
 drivers/gpu/drm/i915/i915_gem.c | 100 
 drivers/gpu/drm/i915/i915_gem_context.c |  55 --
 drivers/gpu/drm/i915/i915_gem_context.h |   4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c  |   3 +
 drivers/gpu/drm/i915/intel_lrc.c|  39 -
 drivers/gpu/drm/i915/intel_ringbuffer.c |  45 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 9 files changed, 177 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index f6ded475bb2c..42cc61230ca7 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -723,8 +723,6 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
if (IS_ERR(vgpu->shadow_ctx))
return PTR_ERR(vgpu->shadow_ctx);
 
-   vgpu->shadow_ctx->engine[RCS].initialised = true;
-
bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES);
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 39883cd915db..cfcef1899da8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1974,7 +1974,6 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
struct intel_context *ce = >engine[engine->id];
 
seq_printf(m, "%s: ", engine->name);
-   seq_putc(m, ce->initialised ? 'I' : 'i');
if (ce->state)
describe_obj(m, ce->state->obj);
if (ce->ring)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ec96b81e08b3..d055db1a68c5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4977,6 +4977,102 @@ bool intel_sanitize_semaphores(struct drm_i915_private 
*dev_priv, int value)
return true;
 }
 
+static int __intel_engines_record_defaults(struct drm_i915_private *i915)
+{
+   struct i915_gem_context *ctx;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   int err;
+
+   /*
+* As we reset the gpu during very early sanitisation, the current
+* register state on the GPU should reflect its defaults values.
+* We load a context onto the hw (with restore-inhibit), then switch
+* over to a second context to save that default register state. We
+* can then prime every new context with that state so they all start
+* from the same default HW values.
+*/
+
+   ctx = i915_gem_context_create_kernel(i915, 0);
+   if (IS_ERR(ctx))
+   return PTR_ERR(ctx);
+
+   for_each_engine(engine, i915, id) {
+   struct drm_i915_gem_request *rq;
+
+   rq = i915_gem_request_alloc(engine, ctx);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   goto out_ctx;
+   }
+
+   err = i915_switch_context(rq);
+   if (engine->init_context)
+   err = engine->init_context(rq);
+
+   __i915_add_request(rq, true);
+   if (err)
+   goto err_active;
+   }
+
+   err = i915_gem_switch_to_kernel_context(i915);
+   if (err)
+   goto err_active;
+
+   err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED);
+   if (err)
+   goto err_active;
+
+   assert_kernel_context_is_current(i915);
+
+   for_each_engine(engine, i915, id) {
+   struct i915_vma *state;
+
+   state = ctx->engine[id].state;
+   if (!state)
+   continue;
+
+   /*
+* As we will hold a reference to the logical state, it will
+* not be torn down with the context, and importantly the
+* object will hold onto its vma (making it possible for a
+* stray GTT write to corrupt our defaults). Unmap the vma
+* from the GTT to prevent such accidents and

[Intel-gfx] [PATCH v3 06/10] drm/i915: Mark the context state as dirty/written

2017-11-03 Thread Chris Wilson

In the next few patches, we will want to both copy out of the context
image and write a valid image into a new context. To be completely safe,
we should then couple in our domain tracking to ensure that we don't
have any issues with stale data remaining in unwanted cachelines.

Historically, we omitted the .write=true from the call to set-gtt-domain
in i915_switch_context() in order to avoid a stall between every request
as we would want to wait for the previous context write from the gpu.
Since then, we limit the set-gtt-domain to only occur when we first bind
the vma, so once in use we will never stall, and we are sure to flush
the context following a load from swap.

Equally we never applied the lessons learnt from ringbuffer submission
to execlists; so time to apply the flush of the lrc after load as well.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Acked-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c| 32 
 drivers/gpu/drm/i915/intel_ringbuffer.c |  6 +++---
 2 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6840ec8db037..9b4e74151ace 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1060,12 +1060,34 @@ static void execlists_schedule(struct 
drm_i915_gem_request *request, int prio)
spin_unlock_irq(>timeline->lock);
 }
 
+static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
+{
+   unsigned int flags;
+   int err;
+
+   /*
+* Clear this page out of any CPU caches for coherent swap-in/out.
+* We only want to do this on the first bind so that we do not stall
+* on an active context (which by nature is already on the GPU).
+*/
+   if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
+   err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+   if (err)
+   return err;
+   }
+
+   flags = PIN_GLOBAL | PIN_HIGH;
+   if (ctx->ggtt_offset_bias)
+   flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
+
+   return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
+}
+
 static struct intel_ring *
 execlists_context_pin(struct intel_engine_cs *engine,
  struct i915_gem_context *ctx)
 {
struct intel_context *ce = >engine[engine->id];
-   unsigned int flags;
void *vaddr;
int ret;
 
@@ -1082,11 +1104,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
}
GEM_BUG_ON(!ce->state);
 
-   flags = PIN_GLOBAL | PIN_HIGH;
-   if (ctx->ggtt_offset_bias)
-   flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
-
-   ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
+   ret = __context_pin(ctx, ce->state);
if (ret)
goto err;
 
@@ -1106,9 +1124,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
i915_ggtt_offset(ce->ring->vma);
 
-   ce->state->obj->mm.dirty = true;
ce->state->obj->pin_global++;
-
i915_gem_context_get(ctx);
 out:
return ce->ring;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 47fadf8da84e..7e2a671882fb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1363,12 +1363,13 @@ static int context_pin(struct i915_gem_context *ctx)
struct i915_vma *vma = ctx->engine[RCS].state;
int ret;
 
-   /* Clear this page out of any CPU caches for coherent swap-in/out.
+   /*
+* Clear this page out of any CPU caches for coherent swap-in/out.
 * We only want to do this on the first bind so that we do not stall
 * on an active context (which by nature is already on the GPU).
 */
if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
-   ret = i915_gem_object_set_to_gtt_domain(vma->obj, false);
+   ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
if (ret)
return ret;
}
@@ -1445,7 +1446,6 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
if (ret)
goto err;
 
-   ce->state->obj->mm.dirty = true;
ce->state->obj->pin_global++;
}
 
-- 
2.15.0

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[Intel-gfx] [PATCH v3 04/10] drm/i915: Always sanitize GT wakeref before restarting engines

2017-11-03 Thread Chris Wilson

The first request submitted to an engine will take the prolonged GT
wakeref. If we discard that wakeref to issue a reset/suspend/etc, then
before restarting the engines, reacquire the GT's wakeref.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 46e26064f3cf..ec96b81e08b3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3099,13 +3099,6 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
}
 
i915_gem_restore_fences(dev_priv);
-
-   if (dev_priv->gt.awake) {
-   intel_sanitize_gt_powersave(dev_priv);
-   intel_enable_gt_powersave(dev_priv);
-   if (INTEL_GEN(dev_priv) >= 6)
-   gen6_rps_busy(dev_priv);
-   }
 }
 
 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
@@ -4874,6 +4867,24 @@ static int __i915_gem_restart_engines(void *data)
enum intel_engine_id id;
int err;
 
+   /*
+* If we are holding a wakeref from a previous cycle, e.g. from
+* before a reset, scrub the GT powersaving and reacquire. This is
+* just to make sure that the HW matches our SW tracking,
+* irrespective of whether or not it was preserved over the
+* restart.
+*/
+   if (i915->gt.awake) {
+   intel_sanitize_gt_powersave(i915);
+   intel_enable_gt_powersave(i915);
+   if (INTEL_GEN(i915) >= 6)
+   gen6_rps_busy(i915);
+
+   queue_delayed_work(i915->wq,
+  >gt.retire_work,
+  round_jiffies_up_relative(HZ));
+   }
+
for_each_engine(engine, i915, id) {
err = engine->init_hw(engine);
if (err)
-- 
2.15.0

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[Intel-gfx] [PATCH v3 02/10] drm/i915: Force the switch to the i915->kernel_context

2017-11-03 Thread Chris Wilson

In the next few patches, we will have a hard requirement that we emit a
context-switch to the perma-pinned i915->kernel_context (so that we can
save the HW state using that context-switch). As the first context
itself may be classed as a kernel context, we want to be explicit in our
comparison. For an extra-layer of finesse, we can check the last
unretired context on the engine; as well as the last retired context
when idle.

v2: verbose verbosity
v3: Always force the switch, even when the engine is idle, and update
the assert that this happens before suspend.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen  #v1
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c| 10 ++
 drivers/gpu/drm/i915/intel_engine_cs.c | 26 --
 2 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6a71805be389..1c1b0906cb18 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4687,14 +4687,16 @@ void __i915_gem_object_release_unless_active(struct 
drm_i915_gem_object *obj)
i915_gem_object_put(obj);
 }
 
-static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
+static void assert_kernel_context_is_current(struct drm_i915_private *i915)
 {
+   struct i915_gem_context *kernel_context = i915->kernel_context;
struct intel_engine_cs *engine;
enum intel_engine_id id;
 
-   for_each_engine(engine, dev_priv, id)
-   GEM_BUG_ON(engine->last_retired_context &&
-  
!i915_gem_context_is_kernel(engine->last_retired_context));
+   for_each_engine(engine, i915, id) {
+   
GEM_BUG_ON(__i915_gem_active_peek(>timeline->last_request));
+   GEM_BUG_ON(engine->last_retired_context != kernel_context);
+   }
 }
 
 void i915_gem_sanitize(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0987768c311d..374e398e867a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1593,10 +1593,32 @@ bool intel_engines_are_idle(struct drm_i915_private 
*dev_priv)
return true;
 }
 
+/**
+ * intel_engine_has_kernel_context:
+ * @engine: the engine
+ *
+ * Returns true if the last context to be executed on this engine, or has been
+ * executed if the engine is already idle, is the kernel context
+ * (#i915.kernel_context).
+ */
 bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine)
 {
-   return (!engine->last_retired_context ||
-   i915_gem_context_is_kernel(engine->last_retired_context));
+   const struct i915_gem_context * const kernel_context =
+   engine->i915->kernel_context;
+   struct drm_i915_gem_request *rq;
+
+   lockdep_assert_held(>i915->drm.struct_mutex);
+
+   /*
+* Check the last context seen by the engine. If active, it will be
+* the last request that remains in the timeline. When idle, it is
+* the last executed context as tracked by retirement.
+*/
+   rq = __i915_gem_active_peek(>timeline->last_request);
+   if (rq)
+   return rq->ctx == kernel_context;
+   else
+   return engine->last_retired_context == kernel_context;
 }
 
 void intel_engines_reset_default_submission(struct drm_i915_private *i915)
-- 
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[Intel-gfx] [PATCH v3 03/10] drm/i915: Move GT powersaving init to i915_gem_init()

2017-11-03 Thread Chris Wilson

GT powersaving is tightly coupled to the request infrastructure. To
avoid complications with the order of initialisation in the next patch
(where we want to send requests to hw during GEM init) move the
powersaving initialisation into the purview of i915_gem_init().

Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c  | 7 ++-
 drivers/gpu/drm/i915/intel_display.c | 2 --
 drivers/gpu/drm/i915/intel_pm.c  | 2 --
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1c1b0906cb18..46e26064f3cf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5016,6 +5016,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto out_unlock;
 
ret = i915_gem_init_hw(dev_priv);
+   if (ret)
+   goto out_unlock;
+
+   intel_init_gt_powersave(dev_priv);
+
+out_unlock:
if (ret == -EIO) {
/* Allow engine initialisation to fail by marking the GPU as
 * wedged. But we only want to do this where the GPU is angry,
@@ -5028,7 +5034,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
ret = 0;
}
 
-out_unlock:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..c3bf87c2036c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15174,8 +15174,6 @@ void intel_modeset_gem_init(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
 
-   intel_init_gt_powersave(dev_priv);
-
intel_setup_overlay(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07118c0b69d3..6e1358d4e764 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7900,7 +7900,6 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
intel_runtime_pm_get(dev_priv);
}
 
-   mutex_lock(_priv->drm.struct_mutex);
mutex_lock(_priv->pcu_lock);
 
/* Initialize RPS limits (for userspace) */
@@ -7942,7 +7941,6 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
rps->boost_freq = rps->max_freq;
 
mutex_unlock(_priv->pcu_lock);
-   mutex_unlock(_priv->drm.struct_mutex);
 
intel_autoenable_gt_powersave(dev_priv);
 }
-- 
2.15.0

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[Intel-gfx] [PATCH] HAX drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Chris Wilson

From: Ville Syrjälä 

Apparently setting up a bunch of GT registers before we've properly
initialized the rest of the GT hardware leads to these setting being
lost. So looks like I broke HSW with commit b7048ea12fbb ("drm/i915:
Do .init_clock_gating() earlier to avoid it clobbering watermarks")
by doing init_clock_gating() too early. This should actually affect
other platforms as well, but apparently not to such a great degree.

What I was ultimately after in that commit was to move the
ilk_init_lp_watermarks() call earlier. So let's undo the damage and
move init_clock_gating() back to where it was, and call
ilk_init_lp_watermarks() just before the watermark state readout.

This highlights how fragile and messed up our init order really is.
I wonder why we even initialize the display before gem. The opposite
order would make much more sense to me...

REVERT THE REVERT, just do the ilk_init_lp_watermarks() motion.
---
 drivers/gpu/drm/i915/intel_display.c |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 40 
 2 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..bd198bd3e10d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3676,6 +3676,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
 
intel_pps_unlock_regs_wa(dev_priv);
intel_modeset_init_hw(dev);
+   intel_init_clock_gating(dev_priv);
 
spin_lock_irq(_priv->irq_lock);
if (dev_priv->display.hpd_irq_setup)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07118c0b69d3..352a6739ed70 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5754,12 +5754,30 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
mutex_unlock(_priv->wm.wm_mutex);
 }
 
+/*
+ * FIXME should probably kill this and improve
+ * the real watermark readout/sanitation instead
+ */
+static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
+{
+   I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
+   I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
+   I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
+
+   /*
+* Don't touch WM1S_LP_EN here.
+* Doing so could cause underruns.
+*/
+}
+
 void ilk_wm_get_hw_state(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
struct ilk_wm_values *hw = _priv->wm.hw;
struct drm_crtc *crtc;
 
+   ilk_init_lp_watermarks(dev_priv);
+
for_each_crtc(dev, crtc)
ilk_pipe_wm_get_hw_state(crtc);
 
@@ -8213,18 +8231,6 @@ static void g4x_disable_trickle_feed(struct 
drm_i915_private *dev_priv)
}
 }
 
-static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
-{
-   I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
-   I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
-   I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
-
-   /*
-* Don't touch WM1S_LP_EN here.
-* Doing so could cause underruns.
-*/
-}
-
 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
 {
uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
@@ -8258,8 +8264,6 @@ static void ilk_init_clock_gating(struct drm_i915_private 
*dev_priv)
   (I915_READ(DISP_ARB_CTL) |
DISP_FBC_WM_DIS));
 
-   ilk_init_lp_watermarks(dev_priv);
-
/*
 * Based on the document from hardware guys the following bits
 * should be set unconditionally in order to enable FBC.
@@ -8372,8 +8376,6 @@ static void gen6_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN6_GT_MODE,
   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
 
-   ilk_init_lp_watermarks(dev_priv);
-
I915_WRITE(CACHE_MODE_0,
   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 
@@ -8600,8 +8602,6 @@ static void bdw_init_clock_gating(struct drm_i915_private 
*dev_priv)
 I915_GTT_PAGE_SIZE_2M);
enum pipe pipe;
 
-   ilk_init_lp_watermarks(dev_priv);
-
/* WaSwitchSolVfFArbitrationPriority:bdw */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 
@@ -8652,8 +8652,6 @@ static void bdw_init_clock_gating(struct drm_i915_private 
*dev_priv)
 
 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   ilk_init_lp_watermarks(dev_priv);
-
/* L3 caching of data atomics doesn't work -- disable it. */
I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
I915_WRITE(HSW_ROW_CHICKEN3,
@@ -8708,8 +8706,6 @@

Re: [Intel-gfx] [RFC PATCH v5 00/20] Refactor HW workaround code

2017-11-03 Thread Oscar Mateo




On 11/03/2017 11:09 AM, Oscar Mateo wrote:

New approach using static tables instead of a programmatic one. This is RFC for
two reasons: firstly because I still need to re-review everything myself (I
wanted to get it out ther asap), and secondly because I'm not 100% convinced
by this approach.

While writing the patches, the approach seemed forceful: I couldn't use const
structs


Or, in other words, this whole thing I just sent is broken and not 
better that using global variables. I'll try to cache things somewhere 
else and resend, sorry for even sending this stupid respin.



because there are a good deal of things that need calculations (e.g.
skl_tune_iz_hashing), or need to pass data between the pre- and the post- hooks
(e.g. disable/enable_dop_clock_gating), or cannot be done in tables (e.g. assert
the values make sense for those registers that are masked), or need to extract
fields from structs (whitelist registers). I also cannot predict how 
future-proof
this thing is.

Furthermote, this is going to be much more difficult to review than the previous
approach, if only because the delta is much bigger. If this approach is 
preferred,
I stronly suggest we do it in top of the previous one (that way we have the 
debugfs
output much earlier in the game to make sure we are missing anything).

 From previous cover letters:

Currently, deciding how/where to apply new workarounds is challenging. Often,
workarounds end up applied incorrectly and get lost under certain circumstances
(e.g. a context switch or a GPU reset). This is a proposal to attempt to
eliminate some of this pain, by clarifying the current classification of
workarounds (context saved/restored, global registers, whitelisting, BB),
putting them together on the same file, and improving the existing validation
infrastructure (debugfs/i-g-t).

Oscar Mateo (20):
   drm/i915: Remove Gen9 WAs with no effect
   drm/i915: Move a bunch of workaround-related code to its own file
   drm/i915: Split out functions for different kinds of workarounds
   drm/i915: Transform context WAs into static tables
   drm/i915: Transform GT WAs into static tables
   drm/i915: Transform Whitelist WAs into static tables
   drm/i915: Create a new category of display WAs
   drm/i915: Print all workaround types correctly in debugfs
   drm/i915: Do not store the total counts of WAs
   drm/i915: Move WA BB stuff to the workarounds file as well
   drm/i915/cnl: Move GT and Display workarounds from init_clock_gating
   drm/i915/gen9: Move GT and Display workarounds from init_clock_gating
   drm/i915/cfl: Move GT and Display workarounds from init_clock_gating
   drm/i915/glk: Move GT and Display workarounds from init_clock_gating
   drm/i915/kbl: Move GT and Display workarounds from init_clock_gating
   drm/i915/bxt: Move GT and Display workarounds from init_clock_gating
   drm/i915/skl: Move GT and Display workarounds from init_clock_gating
   drm/i915/chv: Move GT and Display workarounds from init_clock_gating
   drm/i915/bdw: Move GT and Display workarounds from init_clock_gating
   drm/i915: Document the i915_workarounds file

  drivers/gpu/drm/i915/Makefile|3 +-
  drivers/gpu/drm/i915/i915_debugfs.c  |  117 ++-
  drivers/gpu/drm/i915/i915_drv.h  |   40 +-
  drivers/gpu/drm/i915/i915_gem.c  |3 +
  drivers/gpu/drm/i915/i915_gem_context.c  |1 +
  drivers/gpu/drm/i915/i915_reg.h  |3 -
  drivers/gpu/drm/i915/intel_engine_cs.c   |  682 
  drivers/gpu/drm/i915/intel_lrc.c |  264 +
  drivers/gpu/drm/i915/intel_pm.c  |  312 +-
  drivers/gpu/drm/i915/intel_ringbuffer.c  |5 +-
  drivers/gpu/drm/i915/intel_ringbuffer.h  |3 -
  drivers/gpu/drm/i915/intel_workarounds.c | 1663 ++
  drivers/gpu/drm/i915/intel_workarounds.h |   51 +
  13 files changed, 1867 insertions(+), 1280 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/intel_workarounds.c
  create mode 100644 drivers/gpu/drm/i915/intel_workarounds.h



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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+ (rev3)

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+ (rev3)
URL   : https://patchwork.freedesktop.org/series/33087/
State : failure

== Summary ==

Series 33087v3 drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+
https://patchwork.freedesktop.org/api/1.0/series/33087/revisions/3/mbox/

Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test gem_exec_reloc:
Subgroup basic-cpu-active:
pass   -> FAIL   (fi-gdg-551) fdo#102582 +6
Subgroup basic-write-cpu-active:
pass   -> FAIL   (fi-gdg-551)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS   (fi-bsw-n3050)
Subgroup suspend-read-crc-pipe-a:
pass   -> FAIL   (fi-skl-6700k)

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:442s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:456s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:378s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:534s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:505s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:505s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:496s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:557s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-gdg-551   total:289  pass:170  dwarn:1   dfail:0   fail:9   skip:109 
time:260s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:588s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:430s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:435s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:431s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:499s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:490s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:573s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:588s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:564s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:654s
fi-skl-6700k total:289  pass:264  dwarn:0   dfail:0   fail:1   skip:24  
time:522s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:460s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:564s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:421s

8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC 
integration manifest
d714b22fcb5b drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6953/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor HW workaround code (rev6)

2017-11-03 Thread Patchwork

== Series Details ==

Series: Refactor HW workaround code (rev6)
URL   : https://patchwork.freedesktop.org/series/31611/
State : failure

== Summary ==

Series 31611v6 Refactor HW workaround code
https://patchwork.freedesktop.org/api/1.0/series/31611/revisions/6/mbox/

Test chamelium:
Subgroup dp-hpd-fast:
skip   -> INCOMPLETE (fi-skl-6260u) fdo#102332
skip   -> INCOMPLETE (fi-skl-6700k)
skip   -> INCOMPLETE (fi-skl-6770hq)
skip   -> INCOMPLETE (fi-skl-gvtdvm)
Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test gem_workarounds:
Subgroup basic-read:
pass   -> SKIP   (fi-bdw-5557u)
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-bsw-n3050)
pass   -> SKIP   (fi-bxt-dsi)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-kbl-7500u)
pass   -> SKIP   (fi-kbl-7560u)
pass   -> SKIP   (fi-kbl-7567u)
pass   -> SKIP   (fi-kbl-r)
pass   -> SKIP   (fi-glk-1)
pass   -> SKIP   (fi-cfl-s)
pass   -> SKIP   (fi-cnl-y)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS   (fi-bsw-n3050)

fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332

fi-bdw-5557u total:289  pass:267  dwarn:0   dfail:0   fail:0   skip:22  
time:443s
fi-bdw-gvtdvmtotal:289  pass:264  dwarn:0   dfail:0   fail:0   skip:25  
time:454s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:382s
fi-bsw-n3050 total:289  pass:242  dwarn:0   dfail:0   fail:0   skip:47  
time:550s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:274s
fi-bxt-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:0   skip:31  
time:508s
fi-bxt-j4205 total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:507s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:528s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:499s
fi-cfl-s total:289  pass:253  dwarn:3   dfail:0   fail:0   skip:33  
time:557s
fi-cnl-y total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:612s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:265s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:587s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:446s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:438s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:0   skip:25  
time:490s
fi-kbl-7560u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:574s
fi-kbl-7567u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:479s
fi-kbl-r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:582s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:570s
fi-skl-6260u total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-skl-6700k total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-skl-6770hqtotal:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-skl-gvtdvmtotal:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:579s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:432s

8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC 
integration manifest
f2669847fa75 drm/i915: Document the i915_workarounds file
38aa0f69abf7 drm/i915/bdw: Move GT and Display workarounds from 
init_clock_gating
8421f2af7194 drm/i915/chv: Move GT and Display workarounds from 
init_clock_gating
22d162368c95 drm/i915/skl: Move GT and Display workarounds from 
init_clock_gating
1a1d677877b5 drm/i915/bxt: Move GT and Display workarounds from 
init_clock_gating
2d47c83c1f56 drm/i915/kbl: Move GT and Display workarounds from 
init_clock_gating
fb168c1de5aa drm/i915/glk: Move GT and Display workarounds from 
init_clock_gating
9e43fbf90189 drm/i915/cfl: Move GT and Display workarounds from 
init_clock_gating
c43c4633394c drm/i915/gen9: Move GT and Display workarounds from

[Intel-gfx] [PATCH v3] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

2017-11-03 Thread James Ausmus

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

Signed-off-by: James Ausmus 
Cc: Paulo Zanoni 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 --
 drivers/gpu/drm/i915/intel_display.c | 71 +---
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 11 +++---
 4 files changed, 76 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0f8f6059652..ecd6b236e005 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6263,7 +6263,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6273,7 +6273,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6286,13 +6286,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6332,6 +6332,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..214c0c119002 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3436,17 +3436,10 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB:
return PLANE_CTL_FORMAT_XRGB_;
-   /*
-* XXX: For ARBG/ABGR formats we default to expecting scanout buffers
-* to be already pre-multiplied. We need to add a knob (or a different
-* DRM_FORMAT) for user-space to configure that.
-*/
case DRM_FORMAT_ABGR:
-   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX |
-   PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_ARGB:
-   return PLANE_CTL_FORMAT_XRGB_ |
-   PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+   return PLANE_CTL_FORMAT_XRGB_;
case DRM_FORMAT_XRGB2101010:

[Intel-gfx] [RFC PATCH v2] drm/i915: Transform Whitelist WAs into static tables

2017-11-03 Thread Oscar Mateo

This is for WAs that whitelist a register.

v2: Warn about olden GENs in the apply, not in the get function

Suggested-by: Joonas Lahtinen 
Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/intel_workarounds.c | 251 ---
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +
 3 files changed, 131 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e68edf18..441d92e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1991,6 +1991,8 @@ struct i915_wa_reg {
u8 since;
u8 until;
 
+   i915_reg_t whitelist_addr;
+
i915_reg_t addr;
u32 mask;
u32 value;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index b07fbd0..efa6bc2 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -33,6 +33,10 @@
.name = (wa),   \
.type = I915_WA_TYPE_GT
 
+#define WA_WHITELIST(wa)   \
+   .name = (wa),   \
+   .type = I915_WA_TYPE_WHITELIST
+
 #define ALL_REVS   \
.since = 0, \
.until = REVID_FOREVER
@@ -75,6 +79,9 @@
.value = MASK(m, v),\
.is_masked_reg = true
 
+#define WHITELIST(reg) \
+   .whitelist_addr = reg
+
 static struct i915_wa_reg gen8_ctx_was[] = {
{ WA_CTX(""),
  ALL_REVS, REG(INSTPM),
@@ -861,160 +868,154 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
DRM_DEBUG_DRIVER("Number of GT specific w/a: %u\n", total_count);
 }
 
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-   struct i915_workarounds *wa = _priv->workarounds;
-   const uint32_t index = wa->hw_whitelist_count[engine->id];
-
-   if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
-   return -EINVAL;
+static struct i915_wa_reg gen9_whitelist_was[] = {
+   { WA_WHITELIST("WaVFEStateAfterPipeControlwithMediaStateClear"),
+ ALL_REVS, WHITELIST(GEN9_CTX_PREEMPT_REG) },
 
-   I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
-  i915_mmio_reg_offset(reg));
-   wa->hw_whitelist_count[engine->id]++;
+   { WA_WHITELIST("WaEnablePreemptionGranularityControlByUMD"),
+ ALL_REVS, WHITELIST(GEN8_CS_CHICKEN1) },
 
-   return 0;
-}
-
-static int gen9_whitelist_workarounds_apply(struct intel_engine_cs *engine)
-{
-   int ret;
+   { WA_WHITELIST("WaAllowUMDToModifyHDCChicken1"),
+ ALL_REVS, WHITELIST(GEN8_HDC_CHICKEN1) },
+};
 
-   /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
-   ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
-   if (ret)
-   return ret;
+static struct i915_wa_reg skl_whitelist_was[] = {
+   { WA_WHITELIST("WaDisableLSQCROPERFforOCL"),
+ ALL_REVS, WHITELIST(GEN8_L3SQCREG4) },
+};
 
-   /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
-   ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
-   if (ret)
-   return ret;
+static struct i915_wa_reg bxt_whitelist_was[] = {
+   { WA_WHITELIST("WaDisableObjectLevelPreemptionForTrifanOrPolygon +"
+  "WaDisableObjectLevelPreemptionForInstancedDraw +"
+  "WaDisableObjectLevelPreemtionForInstanceId +"
+  "WaDisableLSQCROPERFforOCL"),
+ REVS(0, BXT_REVID_A1), WHITELIST(GEN9_CS_DEBUG_MODE1) },
 
-   /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
-   ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
-   if (ret)
-   return ret;
+   { WA_WHITELIST("WaDisableObjectLevelPreemptionForTrifanOrPolygon +"
+  "WaDisableObjectLevelPreemptionForInstancedDraw +"
+  "WaDisableObjectLevelPreemtionForInstanceId +"
+  "WaDisableLSQCROPERFforOCL"),
+ REVS(0, BXT_REVID_A1), WHITELIST(GEN8_L3SQCREG4) },
+};
 
-   return 0;
-}
+static struct i915_wa_reg kbl_whitelist_was[] = {
+   { WA_WHITELIST("WaDisableLSQCROPERFforOCL"),
+ ALL_REVS, WHITELIST(GEN8_L3SQCREG4) },
+};
 
-static int skl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
-{
-   int ret = gen9_whitelist_workarounds_apply(engine);
-   if (ret)
-   return ret;
+static struct i915_wa_reg cnl_whitelist_was[] = {
+   { WA_WHITELIST("WaEnablePreemptionGranularityControlByUMD"),
+ ALL_REVS, WHITELIST(GEN8_CS_CHICKEN1) },
+};
 
-   /*

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)
URL   : https://patchwork.freedesktop.org/series/32991/
State : warning

== Summary ==

Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
fail   -> DMESG-FAIL (shard-hsw) fdo#103375
Test kms_plane_lowres:
Subgroup pipe-B-tiling-none:
pass   -> SKIP   (shard-hsw)
Test kms_flip:
Subgroup wf_vblank-vs-dpms-interruptible:
pass   -> INCOMPLETE (shard-hsw) fdo#102614

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2528 pass:1426 dwarn:0   dfail:1   fail:7   skip:1093 
time:9021s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6950/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: i915: remove timeval users

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm: i915: remove timeval users
URL   : https://patchwork.freedesktop.org/series/33147/
State : failure

== Summary ==

Series 33147v1 drm: i915: remove timeval users
https://patchwork.freedesktop.org/api/1.0/series/33147/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test gem_exec_reloc:
Subgroup basic-write-cpu-active:
pass   -> FAIL   (fi-gdg-551)
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-legacy:
pass   -> SKIP   (fi-hsw-4770r)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-c-frame-sequence:
pass   -> DMESG-WARN (fi-skl-6700k)
Subgroup read-crc-pipe-a:
pass   -> INCOMPLETE (fi-skl-6700k)
Subgroup read-crc-pipe-b:
pass   -> SKIP   (fi-hsw-4770r)
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS   (fi-bsw-n3050)
Subgroup read-crc-pipe-c-frame-sequence:
pass   -> INCOMPLETE (fi-cnl-y)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:456s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:275s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:490s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:561s
fi-cnl-y total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:24 
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-gdg-551   total:289  pass:177  dwarn:1   dfail:0   fail:2   skip:109 
time:260s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:593s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:429s
fi-hsw-4770r total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:438s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:431s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:496s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:481s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:582s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:481s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:569s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:647s
fi-skl-6700k total:239  pass:217  dwarn:1   dfail:0   fail:0   skip:20 
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:462s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:568s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:416s

8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC 
integration manifest
ee005a5bc201 drm: i915: remove timeval users

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6951/
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[Intel-gfx] [PATCH] drm: i915: remove timeval users

2017-11-03 Thread Arnd Bergmann

struct timeval is deprecated because it cannot represent times
past 2038. In this driver, the only use of this structure is
to capture debug information. This is easily changed to ktime_t,
which we then format as needed when printing it later.

Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/i915/i915_drv.h   |  6 +++---
 drivers/gpu/drm/i915/i915_gpu_error.c | 25 ++---
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72bb5b51035a..a407c673dd10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -896,9 +896,9 @@ struct intel_display_error_state;
 
 struct i915_gpu_state {
struct kref ref;
-   struct timeval time;
-   struct timeval boottime;
-   struct timeval uptime;
+   ktime_t time;
+   ktime_t boottime;
+   ktime_t uptime;
 
struct drm_i915_private *i915;
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 653fb69e7ecb..65f781e3b63f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -594,6 +594,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
 {
struct drm_i915_private *dev_priv = m->i915;
struct drm_i915_error_object *obj;
+   struct timespec64 ts;
int i, j;
 
if (!error) {
@@ -604,12 +605,15 @@ int i915_error_state_to_str(struct 
drm_i915_error_state_buf *m,
if (*error->error_msg)
err_printf(m, "%s\n", error->error_msg);
err_printf(m, "Kernel: " UTS_RELEASE "\n");
-   err_printf(m, "Time: %ld s %ld us\n",
-  error->time.tv_sec, error->time.tv_usec);
-   err_printf(m, "Boottime: %ld s %ld us\n",
-  error->boottime.tv_sec, error->boottime.tv_usec);
-   err_printf(m, "Uptime: %ld s %ld us\n",
-  error->uptime.tv_sec, error->uptime.tv_usec);
+   ts = ktime_to_timespec64(error->time);
+   err_printf(m, "Time: %lld s %ld us\n",
+  (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
+   ts = ktime_to_timespec64(error->boottime);
+   err_printf(m, "Boottime: %lld s %ld us\n",
+  (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
+   ts = ktime_to_timespec64(error->uptime);
+   err_printf(m, "Uptime: %lld s %ld us\n",
+  (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
if (error->engine[i].hangcheck_stalled &&
@@ -1699,11 +1703,10 @@ static int capture(void *data)
 {
struct i915_gpu_state *error = data;
 
-   do_gettimeofday(>time);
-   error->boottime = ktime_to_timeval(ktime_get_boottime());
-   error->uptime =
-   ktime_to_timeval(ktime_sub(ktime_get(),
-  error->i915->gt.last_init_time));
+   error->time = ktime_get_real();
+   error->boottime = ktime_get_boottime();
+   error->uptime = ktime_sub(ktime_get(),
+ error->i915->gt.last_init_time);
 
error->params = i915_modparams;
 #define DUP(T, x, ...) dup_param(#T, >params.x);
-- 
2.9.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)
URL   : https://patchwork.freedesktop.org/series/32991/
State : success

== Summary ==

Series 32991v2 drm/i915: Implement ReadHitWriteOnlyDisable.
https://patchwork.freedesktop.org/api/1.0/series/32991/revisions/2/mbox/

Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS   (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS   (fi-cfl-s)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS   (fi-bsw-n3050)

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:455s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:382s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:504s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:502s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:504s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:491s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:559s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:608s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:266s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:583s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:430s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:489s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:492s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:574s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:484s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:589s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:563s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:652s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:522s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:498s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:463s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:567s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:420s

8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC 
integration manifest
d367636c14d1 drm/i915: Implement ReadHitWriteOnlyDisable.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6950/
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Re: [Intel-gfx] Pushing commits to drm-intel-next-queued and questions about CI

2017-11-03 Thread Hans de Goede


Hi,

On 03-11-17 19:51, Hans de Goede wrote:

Hi,

On 03-11-17 18:40, Rodrigo Vivi wrote:

Hi Hans,

On Fri, Nov 03, 2017 at 10:41:55AM +, Hans de Goede wrote:

Hi Daniel,

A while ago I was granted commit rights to the drm-intel repo.
So far I've not used these, but since no-one seems to be
pushing these 2 sets, I guess now might be a good time to
learn how to push things myself.

I'm talking about these 2 patch-sets:

https://patchwork.freedesktop.org/series/32274/


For this one we got the ack from Ingo, but I missed the reviewed-by
on the second one that is the i915 part of it.
Do we need it or just that ack was enough for both patches?


With "this one" I assume you mean the one below:


https://patchwork.freedesktop.org/series/32288/


As that is the one which has an ack from Ingo, the second
one has had a reviewed-by from Imre Deak for a few
versions already, it is right there in patch work.

Thank you for rescheduling the tests, this one passes
Fi.CI.BAT now, but I did not see Fi.CI.IGD getting run?


Ok I just got a success report for Fi.CI.IGD too, so I
guess I can go and push this now ?

Regards,

Hans
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/2] x86/platform/intel/iosf_mbi: Add unlocked PMIC bus access notifier unregister

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v5,1/2] x86/platform/intel/iosf_mbi: Add unlocked 
PMIC bus access notifier unregister
URL   : https://patchwork.freedesktop.org/series/32288/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2539 pass:1434 dwarn:0   dfail:1   fail:7   skip:1097 
time:9241s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6947/shards.html
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Re: [Intel-gfx] Pushing commits to drm-intel-next-queued and questions about CI

2017-11-03 Thread Hans de Goede


Hi,

On 03-11-17 18:40, Rodrigo Vivi wrote:

Hi Hans,

On Fri, Nov 03, 2017 at 10:41:55AM +, Hans de Goede wrote:

Hi Daniel,

A while ago I was granted commit rights to the drm-intel repo.
So far I've not used these, but since no-one seems to be
pushing these 2 sets, I guess now might be a good time to
learn how to push things myself.

I'm talking about these 2 patch-sets:

https://patchwork.freedesktop.org/series/32274/


For this one we got the ack from Ingo, but I missed the reviewed-by
on the second one that is the i915 part of it.
Do we need it or just that ack was enough for both patches?


With "this one" I assume you mean the one below:


https://patchwork.freedesktop.org/series/32288/


As that is the one which has an ack from Ingo, the second
one has had a reviewed-by from Imre Deak for a few
versions already, it is right there in patch work.

Thank you for rescheduling the tests, this one passes
Fi.CI.BAT now, but I did not see Fi.CI.IGD getting run?


As for the other series:

https://patchwork.freedesktop.org/series/32274/

That one passed Fi.CI.BAT before (and had warnings
in Fi.CI.IGD which seem to be normal as they happen more
often) but now failed in Fi.CI.BAT, with almost all tests
for fi-gdg-551 failing and everything else succeeeding.


... I just triggered both retests for you here...


This means the other tests never ran, so I guess
I should reschedule the tests for this set.

Given that all the patches have been reviewed and acked can
I simply push these to drm-intel-next-queued once the
tests results are sorted out?


If you have permission and if you are follow the guidelines
and docs, you know what you are doing ;)


I'm not entirely sure I know what I'm doing, hence this mail :)

My understanding is: that once all patches are reviewed and
a set passes Fi.CI.BAT and Fi.CI.IGD it can be pushed to
drm-intel-next-queued, is that correct?

And what about pesky CI failures ?  Note I do see the usefulness
of CI, it did catch a real bug in another patch-set of mine,
just wondering how to deal with CI given that its results
seem to be varying...

Regards,

Hans
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor HW workaround code (rev5)

2017-11-03 Thread Patchwork

== Series Details ==

Series: Refactor HW workaround code (rev5)
URL   : https://patchwork.freedesktop.org/series/31611/
State : failure

== Summary ==

Series 31611v5 Refactor HW workaround code
https://patchwork.freedesktop.org/api/1.0/series/31611/revisions/5/mbox/

Test chamelium:
Subgroup dp-hpd-fast:
skip   -> INCOMPLETE (fi-skl-6260u) fdo#102332
skip   -> INCOMPLETE (fi-skl-6700k)
skip   -> INCOMPLETE (fi-skl-6770hq)
skip   -> INCOMPLETE (fi-skl-gvtdvm)
Test debugfs_test:
Subgroup read_all_entries:
pass   -> DMESG-WARN (fi-gdg-551)
pass   -> DMESG-WARN (fi-blb-e6850)
pass   -> DMESG-WARN (fi-pnv-d510)
pass   -> DMESG-WARN (fi-bwr-2160)
pass   -> DMESG-WARN (fi-elk-e7500)
pass   -> DMESG-WARN (fi-ilk-650)
pass   -> DMESG-WARN (fi-snb-2520m)
pass   -> DMESG-WARN (fi-snb-2600)
pass   -> DMESG-WARN (fi-ivb-3520m)
pass   -> DMESG-WARN (fi-ivb-3770)
pass   -> DMESG-WARN (fi-byt-j1900)
pass   -> DMESG-WARN (fi-byt-n2820)
pass   -> DMESG-WARN (fi-hsw-4770)
pass   -> DMESG-WARN (fi-hsw-4770r)
pass   -> DMESG-WARN (fi-bdw-5557u)
pass   -> DMESG-WARN (fi-bdw-gvtdvm)
pass   -> DMESG-WARN (fi-bsw-n3050)
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test gem_workarounds:
Subgroup basic-read:
pass   -> SKIP   (fi-bdw-5557u)
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-bsw-n3050)
pass   -> SKIP   (fi-bxt-dsi)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-kbl-7500u)
pass   -> SKIP   (fi-kbl-7560u)
pass   -> SKIP   (fi-kbl-7567u)
pass   -> SKIP   (fi-kbl-r)
pass   -> SKIP   (fi-glk-1)
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:266  dwarn:1   dfail:0   fail:0   skip:22  
time:448s
fi-bdw-gvtdvmtotal:289  pass:263  dwarn:1   dfail:0   fail:0   skip:25  
time:454s
fi-blb-e6850 total:289  pass:222  dwarn:2   dfail:0   fail:0   skip:65  
time:379s
fi-bsw-n3050 total:289  pass:241  dwarn:1   dfail:0   fail:0   skip:47  
time:554s
fi-bwr-2160  total:289  pass:182  dwarn:1   dfail:0   fail:0   skip:106 
time:275s
fi-bxt-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:0   skip:31  
time:506s
fi-bxt-j4205 total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:510s
fi-byt-j1900 total:289  pass:252  dwarn:2   dfail:0   fail:0   skip:35  
time:526s
fi-byt-n2820 total:289  pass:248  dwarn:2   dfail:0   fail:0   skip:39  
time:503s
fi-cfl-s total:289  pass:253  dwarn:3   dfail:0   fail:0   skip:33  
time:552s
fi-elk-e7500 total:289  pass:228  dwarn:1   dfail:0   fail:0   skip:60  
time:435s
fi-gdg-551   total:289  pass:177  dwarn:2   dfail:0   fail:1   skip:109 
time:263s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:581s
fi-hsw-4770  total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  
time:441s
fi-hsw-4770r total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  
time:442s
fi-ilk-650   total:289  pass:227  dwarn:1   dfail:0   fail:0   skip:61  
time:431s
fi-ivb-3520m total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:511s
fi-ivb-3770  total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:472s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:0   skip:25  
time:494s
fi-kbl-7560u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:576s
fi-kbl-7567u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:480s
fi-kbl-r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:590s
fi-pnv-d510  total:289  pass:221  dwarn:2   dfail:0   fail:0   skip:66  
time:573s
fi-skl-6260u total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-skl-6700k total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-skl-6770hqtotal:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-skl-gvtdvmtotal:1pass:0dwarn:0   dfail:0   fail:0

[Intel-gfx] [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable.

2017-11-03 Thread Rafael Antognolli

The workaround for this is described as:

"if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"

Further documentation in the internal bug referenced by the bspec
suggest that any of the above suggestions should suffice to fix the
issue. We are going with disabling RCC clock gating.

Unfortunately, what we are doing doesn't match the name of the
workaround, but at least it matches its description.

This change improves CNL stability by avoiding some of the hangs seen in
the platform.

v2: Only disable RCC clock gating.

Signed-off-by: Rafael Antognolli 
---
 drivers/gpu/drm/i915/i915_reg.h| 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c775e96b4e4..bd36ec9bc93f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3837,6 +3837,7 @@ enum {
  */
 #define SLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS  (1 << 5)
+#define  RCCUNIT_CLKGATE_DIS   (1 << 7)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index f31f2d6384c3..3af0dcb91e9c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 
+   /* ReadHitWriteOnlyDisable: cnl */
+   WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
-- 
2.13.6

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+ (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+ (rev2)
URL   : https://patchwork.freedesktop.org/series/33087/
State : failure

== Summary ==

Test kms_flip:
Subgroup flip-vs-dpms-interruptible:
pass   -> INCOMPLETE (shard-hsw)

shard-hswtotal:2526 pass:1425 dwarn:0   dfail:1   fail:8   skip:1091 
time:9248s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6945/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: Move init_clock_gating() back to where it was
URL   : https://patchwork.freedesktop.org/series/33124/
State : failure

== Summary ==

Series 33124v1 drm/i915: Move init_clock_gating() back to where it was
https://patchwork.freedesktop.org/api/1.0/series/33124/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
pass   -> INCOMPLETE (fi-hsw-4770)
pass   -> INCOMPLETE (fi-hsw-4770r)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:442s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:453s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:539s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:274s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:506s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:491s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:551s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:265s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:584s
fi-hsw-4770  total:207  pass:187  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:207  pass:187  dwarn:0   dfail:0   fail:0   skip:19 
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:424s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:497s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:482s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:575s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:570s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:599s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:645s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:524s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:507s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:462s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:576s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:430s

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
638ed9079681 drm/i915: Move init_clock_gating() back to where it was

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6948/
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[Intel-gfx] ✓ Fi.CI.IGT: success for igt/kms_rotation_crc: Add RGB565 90 degree test for gen>9

2017-11-03 Thread Patchwork

== Series Details ==

Series: igt/kms_rotation_crc: Add RGB565 90 degree test for gen>9
URL   : https://patchwork.freedesktop.org/series/33132/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
dmesg-fail -> FAIL   (shard-hsw) fdo#103375

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2540 pass:1434 dwarn:0   dfail:0   fail:8   skip:1098 
time:9298s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_475/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [v4,1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v4,1/5] drm/i915/guc: Split GuC firmware xfer 
function into clear steps
URL   : https://patchwork.freedesktop.org/series/33135/
State : warning

== Summary ==

Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-A:
pass   -> DMESG-WARN (shard-hsw)
Subgroup extended-modeset-hang-oldfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw)
Test kms_plane_lowres:
Subgroup pipe-B-tiling-none:
pass   -> SKIP   (shard-hsw)
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
pass   -> SKIP   (shard-hsw)
Subgroup plane-panning-bottom-right-suspend-pipe-B-planes:
pass   -> SKIP   (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-B-128x128-bottom-edge:
pass   -> SKIP   (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2539 pass:1428 dwarn:2   dfail:1   fail:7   skip:1101 
time:9235s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6943/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for kms_atomic_transition: Split out modeset tests on internal panels (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: kms_atomic_transition: Split out modeset tests on internal panels (rev2)
URL   : https://patchwork.freedesktop.org/series/33052/
State : failure

== Summary ==

Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-B:
pass   -> DMESG-WARN (shard-hsw)
Subgroup extended-modeset-hang-oldfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
dmesg-fail -> FAIL   (shard-hsw) fdo#103375
Subgroup debugfs-reader:
pass   -> INCOMPLETE (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2492 pass:1408 dwarn:2   dfail:0   fail:8   skip:1073 
time:9100s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_474/shards.html
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[Intel-gfx] [RFC PATCH 13/20] drm/i915/cfl: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2: Static tables

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 23 +--
 drivers/gpu/drm/i915/intel_workarounds.c |  8 
 2 files changed, 9 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f712b02..a85a001 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8466,25 +8466,6 @@ static void gen8_set_l3sqc_credits(struct 
drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   if (!HAS_PCH_CNP(dev_priv))
-   return;
-
-   /* Wa #1181 */
-   I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
-  CNP_PWM_CGE_GATING_DISABLE);
-}
-
-static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   cnp_init_clock_gating(dev_priv);
-
-   /* WaFbcNukeOnHostModify:cfl */
-   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
-}
-
 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
/* WaDisableSDEUnitClockGating:kbl */
@@ -8961,10 +8942,8 @@ static void nop_init_clock_gating(struct 
drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-   if (IS_CANNONLAKE(dev_priv))
+   if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = nop_init_clock_gating;
-   else if (IS_COFFEELAKE(dev_priv))
-   dev_priv->display.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index d5cbda1..4fe1dd0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -938,6 +938,14 @@ static bool has_pch_cnp(struct drm_i915_private *dev_priv,
 }
 
 static struct i915_wa_reg cfl_disp_was[] = {
+   { WA_DISP("Wa #1181"),
+ ALL_REVS, REG(SOUTH_DSPCLK_GATE_D),
+ SET_BIT(CNP_PWM_CGE_GATING_DISABLE),
+ .pre_hook = has_pch_cnp },
+
+   { WA_DISP("WaFbcNukeOnHostModify"),
+ ALL_REVS, REG(ILK_DPFC_CHICKEN),
+ SET_BIT(ILK_DPFC_NUKE_ON_ANY_MODIFICATION) },
 };
 
 static struct i915_wa_reg cnl_disp_was[] = {
-- 
1.9.1

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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: This set enables 90/270 degree rotation on 16bpp planes on gen10

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: This set enables 90/270 degree rotation on 16bpp planes on 
gen10
URL   : https://patchwork.freedesktop.org/series/33133/
State : warning

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw)
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
dmesg-fail -> FAIL   (shard-hsw) fdo#103375

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2539 pass:1433 dwarn:1   dfail:0   fail:8   skip:1097 
time:9296s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6942/shards.html
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[Intel-gfx] [RFC PATCH 06/20] drm/i915: Transform Whitelist WAs into static tables

2017-11-03 Thread Oscar Mateo

This is for WAs that whitelist a register.

Suggested-by: Joonas Lahtinen 
Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/intel_workarounds.c | 249 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +
 3 files changed, 128 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72b5d80..6a62a7b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1989,6 +1989,8 @@ struct i915_wa_reg {
u8 since;
u8 until;
 
+   i915_reg_t whitelist_addr;
+
i915_reg_t addr;
u32 mask;
u32 value;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index b07fbd0..849e70a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -33,6 +33,10 @@
.name = (wa),   \
.type = I915_WA_TYPE_GT
 
+#define WA_WHITELIST(wa)   \
+   .name = (wa),   \
+   .type = I915_WA_TYPE_WHITELIST
+
 #define ALL_REVS   \
.since = 0, \
.until = REVID_FOREVER
@@ -75,6 +79,9 @@
.value = MASK(m, v),\
.is_masked_reg = true
 
+#define WHITELIST(reg) \
+   .whitelist_addr = reg
+
 static struct i915_wa_reg gen8_ctx_was[] = {
{ WA_CTX(""),
  ALL_REVS, REG(INSTPM),
@@ -861,160 +868,150 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
DRM_DEBUG_DRIVER("Number of GT specific w/a: %u\n", total_count);
 }
 
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-   struct i915_workarounds *wa = _priv->workarounds;
-   const uint32_t index = wa->hw_whitelist_count[engine->id];
-
-   if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
-   return -EINVAL;
-
-   I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
-  i915_mmio_reg_offset(reg));
-   wa->hw_whitelist_count[engine->id]++;
-
-   return 0;
-}
-
-static int gen9_whitelist_workarounds_apply(struct intel_engine_cs *engine)
-{
-   int ret;
-
-   /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
-   ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
-   if (ret)
-   return ret;
+static struct i915_wa_reg gen9_whitelist_was[] = {
+   { WA_WHITELIST("WaVFEStateAfterPipeControlwithMediaStateClear"),
+ ALL_REVS, WHITELIST(GEN9_CTX_PREEMPT_REG) },
 
-   /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
-   ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
-   if (ret)
-   return ret;
+   { WA_WHITELIST("WaEnablePreemptionGranularityControlByUMD"),
+ ALL_REVS, WHITELIST(GEN8_CS_CHICKEN1) },
 
-   /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
-   ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
-   if (ret)
-   return ret;
+   { WA_WHITELIST("WaAllowUMDToModifyHDCChicken1"),
+ ALL_REVS, WHITELIST(GEN8_HDC_CHICKEN1) },
+};
 
-   return 0;
-}
+static struct i915_wa_reg skl_whitelist_was[] = {
+   { WA_WHITELIST("WaDisableLSQCROPERFforOCL"),
+ ALL_REVS, WHITELIST(GEN8_L3SQCREG4) },
+};
 
-static int skl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
-{
-   int ret = gen9_whitelist_workarounds_apply(engine);
-   if (ret)
-   return ret;
+static struct i915_wa_reg bxt_whitelist_was[] = {
+   { WA_WHITELIST("WaDisableObjectLevelPreemptionForTrifanOrPolygon +"
+  "WaDisableObjectLevelPreemptionForInstancedDraw +"
+  "WaDisableObjectLevelPreemtionForInstanceId +"
+  "WaDisableLSQCROPERFforOCL"),
+ REVS(0, BXT_REVID_A1), WHITELIST(GEN9_CS_DEBUG_MODE1) },
 
-   /* WaDisableLSQCROPERFforOCL:skl */
-   ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
-   if (ret)
-   return ret;
+   { WA_WHITELIST("WaDisableObjectLevelPreemptionForTrifanOrPolygon +"
+  "WaDisableObjectLevelPreemptionForInstancedDraw +"
+  "WaDisableObjectLevelPreemtionForInstanceId +"
+  "WaDisableLSQCROPERFforOCL"),
+ REVS(0, BXT_REVID_A1), WHITELIST(GEN8_L3SQCREG4) },
+};
 
-   return 0;
-}
+static struct i915_wa_reg kbl_whitelist_was[] = {
+   { WA_WHITELIST("WaDisableLSQCROPERFforOCL"),
+ ALL_REVS, WHITELIST(GEN8_L3SQCREG4) },
+};
 
-static int bxt_whitelist_workarounds_apply(struct intel_engine_cs *engine)
-{
-   struct

[Intel-gfx] [RFC PATCH 12/20] drm/i915/gen9: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2:
  - Rebase on WA removed
  - Rebased to carry the init_early nomenclature over (Chris)

v3: Static tables

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 48 
 drivers/gpu/drm/i915/intel_workarounds.c | 28 +++
 2 files changed, 28 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ff3ac6c..f712b02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -57,50 +57,8 @@
 #define INTEL_RC6p_ENABLE  (1<<1)
 #define INTEL_RC6pp_ENABLE (1<<2)
 
-static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   if (HAS_LLC(dev_priv)) {
-   /*
-* WaCompressedResourceDisplayNewHashMode:skl,kbl
-* Display WA#0390: skl,kbl
-*
-* Must match Sampler, Pixel Back End, and Media. See
-* WaCompressedResourceSamplerPbeMediaNewHashMode.
-*/
-   I915_WRITE(CHICKEN_PAR1_1,
-  I915_READ(CHICKEN_PAR1_1) |
-  SKL_DE_COMPRESSED_HASH_MODE);
-   }
-
-   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
-   I915_WRITE(CHICKEN_PAR1_1,
-  I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
-
-   /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
-   I915_WRITE(GEN8_CHICKEN_DCPR_1,
-  I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
-   /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
-   /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
-   I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-  DISP_FBC_WM_DIS |
-  DISP_FBC_MEMORY_WAKE);
-
-   /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
-   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-  ILK_DPFC_DISABLE_DUMMY0);
-
-   if (IS_SKYLAKE(dev_priv)) {
-   /* WaDisableDopClockGating */
-   I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
-  & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-   }
-}
-
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   gen9_init_clock_gating(dev_priv);
-
/* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -123,7 +81,6 @@ static void bxt_init_clock_gating(struct drm_i915_private 
*dev_priv)
 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 {
u32 val;
-   gen9_init_clock_gating(dev_priv);
 
/*
 * WaDisablePWMClockGating:glk
@@ -8522,7 +8479,6 @@ static void cnp_init_clock_gating(struct drm_i915_private 
*dev_priv)
 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
cnp_init_clock_gating(dev_priv);
-   gen9_init_clock_gating(dev_priv);
 
/* WaFbcNukeOnHostModify:cfl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
@@ -8531,8 +8487,6 @@ static void cfl_init_clock_gating(struct drm_i915_private 
*dev_priv)
 
 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   gen9_init_clock_gating(dev_priv);
-
/* WaDisableSDEUnitClockGating:kbl */
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
@@ -8550,8 +8504,6 @@ static void kbl_init_clock_gating(struct drm_i915_private 
*dev_priv)
 
 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   gen9_init_clock_gating(dev_priv);
-
/* WAC6entrylatency:skl */
I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
   FBC_LLC_FULLY_OPEN);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a0b34d9..d5cbda1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -889,9 +889,37 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
 };
 
 static struct i915_wa_reg gen9_disp_was[] = {
+   /*
+* Must match Sampler, Pixel Back End, and Media. See
+* WaCompressedResourceSamplerPbeMediaNewHashMode.
+*/
+   { WA_DISP("WaCompressedResourceDisplayNewHashMode + Display WA#0390"),
+ ALL_REVS, REG(CHICKEN_PAR1_1),
+ SET_BIT(SKL_DE_COMPRESSED_HASH_MODE),
+ .pre_hook = has_llc },
+
+   /* See Bspec note for PSR2_CTL bit 31 */
+   { WA_DISP("Wa#828"),
+ ALL_REVS, REG(CHICKEN_PAR1_1),
+

[Intel-gfx] [RFC PATCH 04/20] drm/i915: Transform context WAs into static tables

2017-11-03 Thread Oscar Mateo

This is for WAs that need to touch registers that get saved/restored
together with the logical context. The idea is that WAs are "pretty"
static, so a table is more declarative than a programmatic approah.
Note however that some amount is caching is needed for those things
that are dynamic (e.g. things that need some calculation, or have
a criteria different than the more obvious GEN + stepping).

Also, this makes very explicit which WAs live in the context.

Suggested-by: Joonas Lahtinen 
Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  40 +-
 drivers/gpu/drm/i915/i915_drv.h  |  35 +-
 drivers/gpu/drm/i915/i915_gem_context.c  |   4 -
 drivers/gpu/drm/i915/intel_workarounds.c | 754 +--
 drivers/gpu/drm/i915/intel_workarounds.h |   4 +-
 5 files changed, 466 insertions(+), 371 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 39883cd..12c4330 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include "intel_drv.h"
+#include "intel_workarounds.h"
 #include "i915_guc_submission.h"
 
 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
@@ -3357,13 +3358,16 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
 
 static int i915_wa_registers(struct seq_file *m, void *unused)
 {
-   int i;
-   int ret;
struct intel_engine_cs *engine;
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_device *dev = _priv->drm;
struct i915_workarounds *workarounds = _priv->workarounds;
+   const struct i915_wa_reg_table *wa_table;
+   uint table_count;
enum intel_engine_id id;
+   int i, j, ret;
+
+   intel_ctx_workarounds_get(dev_priv, _table, _count);
 
ret = mutex_lock_interruptible(>struct_mutex);
if (ret)
@@ -3371,22 +3375,28 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
 
intel_runtime_pm_get(dev_priv);
 
-   seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
+   seq_printf(m, "Workarounds applied: %d\n", workarounds->ctx_count);
for_each_engine(engine, dev_priv, id)
seq_printf(m, "HW whitelist count for %s: %d\n",
   engine->name, workarounds->hw_whitelist_count[id]);
-   for (i = 0; i < workarounds->count; ++i) {
-   i915_reg_t addr;
-   u32 mask, value, read;
-   bool ok;
-
-   addr = workarounds->reg[i].addr;
-   mask = workarounds->reg[i].mask;
-   value = workarounds->reg[i].value;
-   read = I915_READ(addr);
-   ok = (value & mask) == (read & mask);
-   seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, 
status: %s\n",
-  i915_mmio_reg_offset(addr), value, mask, read, ok ? 
"OK" : "FAIL");
+
+   for (i = 0; i < table_count; i++) {
+   const struct i915_wa_reg *wa = wa_table[i].table;
+
+   for (j = 0; j < wa_table[i].count; j++) {
+   u32 read;
+   bool ok;
+
+   if (!wa[j].applied)
+   continue;
+
+   read = I915_READ(wa[j].addr);
+   ok = (wa[j].value & wa[j].mask) == (read & wa[j].mask);
+   seq_printf(m,
+  "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, 
status: %s, name: %s\n",
+  i915_mmio_reg_offset(wa[j].addr), 
wa[j].value,
+  wa[j].mask, read, ok ? "OK" : "FAIL", 
wa[j].name);
+   }
}
 
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4a7325c..1c73fec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1970,18 +1970,43 @@ struct i915_frontbuffer_tracking {
unsigned flip_bits;
 };
 
+struct i915_wa_reg;
+
+typedef bool (* wa_pre_hook_func)(struct drm_i915_private *dev_priv,
+ struct i915_wa_reg *wa);
+typedef void (* wa_post_hook_func)(struct drm_i915_private *dev_priv,
+  struct i915_wa_reg *wa);
+
 struct i915_wa_reg {
+   const char *name;
+   enum wa_type {
+   I915_WA_TYPE_CONTEXT = 0,
+   I915_WA_TYPE_GT,
+   I915_WA_TYPE_DISPLAY,
+   I915_WA_TYPE_WHITELIST
+   } type;
+
+   u8 since;
+   u8 until;
+
i915_reg_t addr;
-   u32 value;
-   /* bitmask representing WA bits */
u32 mask;
+   u32 value;
+   bool

[Intel-gfx] [RFC PATCH v5 00/20] Refactor HW workaround code

2017-11-03 Thread Oscar Mateo

New approach using static tables instead of a programmatic one. This is RFC for
two reasons: firstly because I still need to re-review everything myself (I
wanted to get it out ther asap), and secondly because I'm not 100% convinced
by this approach.

While writing the patches, the approach seemed forceful: I couldn't use const
structs because there are a good deal of things that need calculations (e.g.
skl_tune_iz_hashing), or need to pass data between the pre- and the post- hooks
(e.g. disable/enable_dop_clock_gating), or cannot be done in tables (e.g. assert
the values make sense for those registers that are masked), or need to extract
fields from structs (whitelist registers). I also cannot predict how 
future-proof
this thing is.

Furthermote, this is going to be much more difficult to review than the previous
approach, if only because the delta is much bigger. If this approach is 
preferred,
I stronly suggest we do it in top of the previous one (that way we have the 
debugfs
output much earlier in the game to make sure we are missing anything).

From previous cover letters:

Currently, deciding how/where to apply new workarounds is challenging. Often,
workarounds end up applied incorrectly and get lost under certain circumstances
(e.g. a context switch or a GPU reset). This is a proposal to attempt to
eliminate some of this pain, by clarifying the current classification of
workarounds (context saved/restored, global registers, whitelisting, BB),
putting them together on the same file, and improving the existing validation
infrastructure (debugfs/i-g-t).

Oscar Mateo (20):
  drm/i915: Remove Gen9 WAs with no effect
  drm/i915: Move a bunch of workaround-related code to its own file
  drm/i915: Split out functions for different kinds of workarounds
  drm/i915: Transform context WAs into static tables
  drm/i915: Transform GT WAs into static tables
  drm/i915: Transform Whitelist WAs into static tables
  drm/i915: Create a new category of display WAs
  drm/i915: Print all workaround types correctly in debugfs
  drm/i915: Do not store the total counts of WAs
  drm/i915: Move WA BB stuff to the workarounds file as well
  drm/i915/cnl: Move GT and Display workarounds from init_clock_gating
  drm/i915/gen9: Move GT and Display workarounds from init_clock_gating
  drm/i915/cfl: Move GT and Display workarounds from init_clock_gating
  drm/i915/glk: Move GT and Display workarounds from init_clock_gating
  drm/i915/kbl: Move GT and Display workarounds from init_clock_gating
  drm/i915/bxt: Move GT and Display workarounds from init_clock_gating
  drm/i915/skl: Move GT and Display workarounds from init_clock_gating
  drm/i915/chv: Move GT and Display workarounds from init_clock_gating
  drm/i915/bdw: Move GT and Display workarounds from init_clock_gating
  drm/i915: Document the i915_workarounds file

 drivers/gpu/drm/i915/Makefile|3 +-
 drivers/gpu/drm/i915/i915_debugfs.c  |  117 ++-
 drivers/gpu/drm/i915/i915_drv.h  |   40 +-
 drivers/gpu/drm/i915/i915_gem.c  |3 +
 drivers/gpu/drm/i915/i915_gem_context.c  |1 +
 drivers/gpu/drm/i915/i915_reg.h  |3 -
 drivers/gpu/drm/i915/intel_engine_cs.c   |  682 
 drivers/gpu/drm/i915/intel_lrc.c |  264 +
 drivers/gpu/drm/i915/intel_pm.c  |  312 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |5 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |3 -
 drivers/gpu/drm/i915/intel_workarounds.c | 1663 ++
 drivers/gpu/drm/i915/intel_workarounds.h |   51 +
 13 files changed, 1867 insertions(+), 1280 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.c
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.h

-- 
1.9.1

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[Intel-gfx] [RFC PATCH 16/20] drm/i915/bxt: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2: Classify WaDisableSDEUnitClockGating as GT WA
v3: Static tables (Joonas)

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 26 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 19 +++
 2 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 046553b..98e976e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -57,27 +57,6 @@
 #define INTEL_RC6p_ENABLE  (1<<1)
 #define INTEL_RC6pp_ENABLE (1<<2)
 
-static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   /* WaDisableSDEUnitClockGating:bxt */
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-   /*
-* FIXME:
-* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
-*/
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
-
-   /*
-* Wa: Backlight PWM may stop in the asserted state, causing backlight
-* to stay fully on.
-*/
-   I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
-  PWM1_GATING_DIS | PWM2_GATING_DIS);
-}
-
 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 {
u32 tmp;
@@ -8898,12 +8877,11 @@ static void nop_init_clock_gating(struct 
drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
-   IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+   IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv)   ||
+   IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = nop_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skl_init_clock_gating;
-   else if (IS_BROXTON(dev_priv))
-   dev_priv->display.init_clock_gating = bxt_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.init_clock_gating = bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 396399b..1ebe56d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -723,6 +723,10 @@ static uint mmio_workarounds_apply(struct drm_i915_private 
*dev_priv,
{ WA_GT("WaInPlaceDecompressionHang"),
  REVS(BXT_REVID_C0, REVID_FOREVER), REG(GEN9_GAMT_ECO_REG_RW_IA),
  SET_BIT(GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS) },
+
+   { WA_GT("WaDisableSDEUnitClockGating"),
+ ALL_REVS, REG(GEN8_UCGCTL6),
+ SET_BIT(GEN8_SDEUNIT_CLOCK_GATE_DISABLE) },
 };
 
 static struct i915_wa_reg kbl_gt_was[] = {
@@ -931,6 +935,21 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
 };
 
 static struct i915_wa_reg bxt_disp_was[] = {
+   /*
+* FIXME:
+* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
+*/
+   { WA_DISP(""),
+ ALL_REVS, REG(GEN8_UCGCTL6),
+ SET_BIT(GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ) },
+
+   /*
+* Backlight PWM may stop in the asserted state, causing backlight
+* to stay fully on.
+*/
+   { WA_DISP(""),
+ ALL_REVS, REG(GEN9_CLKGATE_DIS_0),
+ SET_BIT(PWM1_GATING_DIS | PWM2_GATING_DIS) },
 };
 
 static struct i915_wa_reg kbl_disp_was[] = {
-- 
1.9.1

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[Intel-gfx] [RFC PATCH 02/20] drm/i915: Move a bunch of workaround-related code to its own file

2017-11-03 Thread Oscar Mateo

This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.

v2: Use intel_ prefix for code that deals with the hardware (Chris)
v3: Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/Makefile|   3 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   | 682 -
 drivers/gpu/drm/i915/intel_lrc.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   3 -
 drivers/gpu/drm/i915/intel_workarounds.c | 708 +++
 drivers/gpu/drm/i915/intel_workarounds.h |  31 ++
 7 files changed, 743 insertions(+), 686 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.c
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1bbc544..0eabc9e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -41,7 +41,8 @@ i915-y := i915_drv.o \
  intel_csr.o \
  intel_device_info.o \
  intel_pm.o \
- intel_runtime_pm.o
+ intel_runtime_pm.o \
+ intel_workarounds.o
 
 i915-$(CONFIG_COMPAT)   += i915_ioc32.o
 i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index f31f2d6..6e4440f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -818,688 +818,6 @@ void intel_engine_get_instdone(struct intel_engine_cs 
*engine,
}
 }
 
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
-{
-   const u32 idx = dev_priv->workarounds.count;
-
-   if (WARN_ON(idx >= I915_MAX_WA_REGS))
-   return -ENOSPC;
-
-   dev_priv->workarounds.reg[idx].addr = addr;
-   dev_priv->workarounds.reg[idx].value = val;
-   dev_priv->workarounds.reg[idx].mask = mask;
-
-   dev_priv->workarounds.count++;
-
-   return 0;
-}
-
-#define WA_REG(addr, mask, val) do { \
-   const int r = wa_add(dev_priv, (addr), (mask), (val)); \
-   if (r) \
-   return r; \
-   } while (0)
-
-#define WA_SET_BIT_MASKED(addr, mask) \
-   WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
-
-#define WA_CLR_BIT_MASKED(addr, mask) \
-   WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
-
-#define WA_SET_FIELD_MASKED(addr, mask, value) \
-   WA_REG(addr, mask, _MASKED_FIELD(mask, value))
-
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-   struct i915_workarounds *wa = _priv->workarounds;
-   const uint32_t index = wa->hw_whitelist_count[engine->id];
-
-   if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
-   return -EINVAL;
-
-   I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
-  i915_mmio_reg_offset(reg));
-   wa->hw_whitelist_count[engine->id]++;
-
-   return 0;
-}
-
-static int gen8_init_workarounds(struct intel_engine_cs *engine)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-
-   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
-   /* WaDisableAsyncFlipPerfMode:bdw,chv */
-   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
-   /* WaDisablePartialInstShootdown:bdw,chv */
-   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
-
-   /* Use Force Non-Coherent whenever executing a 3D context. This is a
-* workaround for for a possible hang in the unlikely event a TLB
-* invalidation occurs during a PSD flush.
-*/
-   /* WaForceEnableNonCoherent:bdw,chv */
-   /* WaHdcDisableFetchWhenMasked:bdw,chv */
-   WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_DONOT_FETCH_MEM_WHEN_MASKED |
- HDC_FORCE_NON_COHERENT);
-
-   /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
-* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
-*  polygons in the same 8x4 pixel/sample area to be processed without
-*  stalling waiting for the earlier ones to write to Hierarchical Z
-*  buffer."
-*
-* This optimization is off by default for BDW and CHV; turn it on.
-*/
-   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
-   /* Wa4x4STCOptimizationDisable:bdw,chv */
-   WA_SET_BIT_MASKED(CACHE_MODE_1,

[Intel-gfx] [RFC PATCH 10/20] drm/i915: Move WA BB stuff to the workarounds file as well

2017-11-03 Thread Oscar Mateo

Since we are trying to put all WA stuff together, do not forget about the BB 
WAs.

v2: s/intel_bb_workarounds_init/intel_engine_init_bb_workarounds (Chris)

v3: Rebased

Signed-off-by: Oscar Mateo 
Cc: Mika Kuoppala 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 253 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 254 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +
 3 files changed, 259 insertions(+), 251 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f0b4d2f..7f731d0 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1181,255 +1181,6 @@ static int execlists_request_alloc(struct 
drm_i915_gem_request *request)
return 0;
 }
 
-/*
- * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
- * PIPE_CONTROL instruction. This is required for the flush to happen correctly
- * but there is a slight complication as this is applied in WA batch where the
- * values are only initialized once so we cannot take register value at the
- * beginning and reuse it further; hence we save its value to memory, upload a
- * constant value with bit21 set and then we restore it back with the saved 
value.
- * To simplify the WA, a constant value is formed by using the default value
- * of this register. This shouldn't be a problem because we are only modifying
- * it for a short period and this batch in non-premptible. We can ofcourse
- * use additional instructions that read the actual value of the register
- * at that time and set our bit of interest but it makes the WA complicated.
- *
- * This WA is also required for Gen9 so extracting as a function avoids
- * code duplication.
- */
-static u32 *
-gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
-{
-   *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
-   *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-   *batch++ = i915_ggtt_offset(engine->scratch) + 256;
-   *batch++ = 0;
-
-   *batch++ = MI_LOAD_REGISTER_IMM(1);
-   *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-   *batch++ = 0x4040 | GEN8_LQSC_FLUSH_COHERENT_LINES;
-
-   batch = gen8_emit_pipe_control(batch,
-  PIPE_CONTROL_CS_STALL |
-  PIPE_CONTROL_DC_FLUSH_ENABLE,
-  0);
-
-   *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
-   *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-   *batch++ = i915_ggtt_offset(engine->scratch) + 256;
-   *batch++ = 0;
-
-   return batch;
-}
-
-/*
- * Typically we only have one indirect_ctx and per_ctx batch buffer which are
- * initialized at the beginning and shared across all contexts but this field
- * helps us to have multiple batches at different offsets and select them based
- * on a criteria. At the moment this batch always start at the beginning of 
the page
- * and at this point we don't have multiple wa_ctx batch buffers.
- *
- * The number of WA applied are not known at the beginning; we use this field
- * to return the no of DWORDS written.
- *
- * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
- * so it adds NOOPs as padding to make it cacheline aligned.
- * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
- * makes a complete batch buffer.
- */
-static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 
*batch)
-{
-   /* WaDisableCtxRestoreArbitration:bdw,chv */
-   *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-
-   /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
-   if (IS_BROADWELL(engine->i915))
-   batch = gen8_emit_flush_coherentl3_wa(engine, batch);
-
-   /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
-   /* Actual scratch location is at 128 bytes offset */
-   batch = gen8_emit_pipe_control(batch,
-  PIPE_CONTROL_FLUSH_L3 |
-  PIPE_CONTROL_GLOBAL_GTT_IVB |
-  PIPE_CONTROL_CS_STALL |
-  PIPE_CONTROL_QW_WRITE,
-  i915_ggtt_offset(engine->scratch) +
-  2 * CACHELINE_BYTES);
-
-   *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-
-   /* Pad to end of cacheline */
-   while ((unsigned long)batch % CACHELINE_BYTES)
-   *batch++ = MI_NOOP;
-
-   /*
-* MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
-* execution depends on the length specified in terms of cache lines
-* in the register CTX_RCS_INDIRECT_CTX
-*/
-
-   return batch;
-}
-
-static u32 *gen9_init_indirectctx_bb(struct

[Intel-gfx] [RFC PATCH 01/20] drm/i915: Remove Gen9 WAs with no effect

2017-11-03 Thread Oscar Mateo

GEN8_CONFIG0 (0xD00) is a protected by a lock (bit 31) which is set by
the BIOS, so there is no way we can enable the three chicken bits
mandated by the WA (the BIOS should be doing it instead).

v2: Rebased
v3: Standalone patch

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 ---
 drivers/gpu/drm/i915/intel_pm.c | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c775e9..9c57e0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -355,9 +355,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ECOCHK_PPGTT_WT_HSW  (0x2<<3)
 #define   ECOCHK_PPGTT_WB_HSW  (0x3<<3)
 
-#define GEN8_CONFIG0   _MMIO(0xD00)
-#define  GEN9_DEFAULT_FIXES(1 << 3 | 1 << 2 | 1 << 1)
-
 #define GAC_ECO_BITS   _MMIO(0x14090)
 #define   ECOBITS_SNB_BIT  (1<<13)
 #define   ECOBITS_PPGTT_CACHE64B   (3<<8)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07118c0..acd0cbb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -75,9 +75,6 @@ static void gen9_init_clock_gating(struct drm_i915_private 
*dev_priv)
I915_WRITE(CHICKEN_PAR1_1,
   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
-   I915_WRITE(GEN8_CONFIG0,
-  I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
-
/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
I915_WRITE(GEN8_CHICKEN_DCPR_1,
   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-- 
1.9.1

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[Intel-gfx] [RFC PATCH 03/20] drm/i915: Split out functions for different kinds of workarounds

2017-11-03 Thread Oscar Mateo

There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
be easier to decide where a new workaround should go.

v2:
  - Add multiple MISSING_CASE
  - Rebased

v3:
  - Rename mmio_workarounds to gt_workarounds (Chris, Mika)
  - Create empty placeholders for BDW and CHV GT WAs
  - Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_gem.c  |   3 +
 drivers/gpu/drm/i915/i915_gem_context.c  |   5 +
 drivers/gpu/drm/i915/intel_lrc.c |  10 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   4 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 714 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   8 +-
 6 files changed, 458 insertions(+), 286 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e43688f..750e014 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,6 +35,7 @@
 #include "intel_drv.h"
 #include "intel_frontbuffer.h"
 #include "intel_mocs.h"
+#include "intel_workarounds.h"
 #include "i915_gemfs.h"
 #include 
 #include 
@@ -4916,6 +4917,8 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
 
+   intel_gt_workarounds_apply(dev_priv);
+
i915_gem_init_swizzling(dev_priv);
 
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 10affb3..8548e571 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_trace.h"
+#include "intel_workarounds.h"
 
 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
 
@@ -456,6 +457,10 @@ int i915_gem_contexts_init(struct drm_i915_private 
*dev_priv)
 
GEM_BUG_ON(dev_priv->kernel_context);
 
+   err = intel_ctx_workarounds_init(dev_priv);
+   if (err)
+   goto err;
+
INIT_LIST_HEAD(_priv->contexts.list);
INIT_WORK(_priv->contexts.free_work, contexts_free_worker);
init_llist_head(_priv->contexts.free_list);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 911df0c..f0b4d2f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1503,7 +1503,7 @@ static int gen8_init_render_ring(struct intel_engine_cs 
*engine)
 
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-   return init_workarounds_ring(engine);
+   return 0;
 }
 
 static int gen9_init_render_ring(struct intel_engine_cs *engine)
@@ -1514,7 +1514,11 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   return init_workarounds_ring(engine);
+   ret = intel_whitelist_workarounds_apply(engine);
+   if (ret)
+   return ret;
+
+   return 0;
 }
 
 static void reset_common_ring(struct intel_engine_cs *engine,
@@ -1830,7 +1834,7 @@ static int gen8_init_rcs_context(struct 
drm_i915_gem_request *req)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(req);
+   ret = intel_ctx_workarounds_emit(req);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1c721b2..b053fed 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -649,7 +649,7 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request 
*req)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(req);
+   ret = intel_ctx_workarounds_emit(req);
if (ret != 0)
return ret;
 
@@ -708,7 +708,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (INTEL_INFO(dev_priv)->gen >= 6)
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 
-   return init_workarounds_ring(engine);
+   return 0;
 }
 
 static void render_ring_cleanup(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5f597d1..0a8f265 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -58,27 +58,8 @@ static int wa_add(struct drm_i915_private *dev_priv,
 #define WA_SET_FIELD_MASKED(addr, mask, value) \
WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-   struct i915_workarounds

[Intel-gfx] [RFC PATCH 08/20] drm/i915: Print all workaround types correctly in debugfs

2017-11-03 Thread Oscar Mateo

Let's try to make sure that all WAs are applied correctly and survive
resumes, resets, etc... (with some help from a companion i-g-t patch).

v2:
  - Rebased
  - Print display WAs as well (Ville)

v3:
  - Grab the forcewake once for everyone, so that all reads are from
the same powercontext (Chris)

v4: Rebase on top of static tables

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 79 +
 1 file changed, 63 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 12c4330..8a6fef4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3356,48 +3356,95 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
return 0;
 }
 
+static void check_wa_register(struct seq_file *m,
+ const struct i915_wa_reg *wa_reg)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   u32 read;
+   bool ok;
+
+   assert_forcewakes_active(dev_priv, FORCEWAKE_ALL);
+
+   read = I915_READ_FW(wa_reg->addr);
+   ok = (wa_reg->value & wa_reg->mask) == (read & wa_reg->mask);
+   seq_printf(m,
+  "0x%X: 0x%08x, mask: 0x%08x, read: 0x%08x, status: %s, name: 
%s\n",
+  i915_mmio_reg_offset(wa_reg->addr),
+  wa_reg->value, wa_reg->mask, read,
+  ok ? "OK" : "FAIL", wa_reg->name);
+}
+
+static void check_wa_registers(struct seq_file *m,
+  const struct i915_wa_reg_table *wa_table,
+  uint table_count)
+{
+   int i, j;
+
+   for (i = 0; i < table_count; i++) {
+   const struct i915_wa_reg *wa = wa_table[i].table;
+
+   for (j = 0; j < wa_table[i].count; j++) {
+   if (!wa[j].applied)
+   continue;
+
+   check_wa_register(m, [j]);
+   }
+   }
+}
+
 static int i915_wa_registers(struct seq_file *m, void *unused)
 {
-   struct intel_engine_cs *engine;
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_device *dev = _priv->drm;
struct i915_workarounds *workarounds = _priv->workarounds;
const struct i915_wa_reg_table *wa_table;
uint table_count;
-   enum intel_engine_id id;
int i, j, ret;
 
-   intel_ctx_workarounds_get(dev_priv, _table, _count);
-
ret = mutex_lock_interruptible(>struct_mutex);
if (ret)
return ret;
 
intel_runtime_pm_get(dev_priv);
 
-   seq_printf(m, "Workarounds applied: %d\n", workarounds->ctx_count);
-   for_each_engine(engine, dev_priv, id)
-   seq_printf(m, "HW whitelist count for %s: %d\n",
-  engine->name, workarounds->hw_whitelist_count[id]);
-
+   seq_printf(m, "Context workarounds applied: %d\n",
+  workarounds->ctx_count);
+   intel_ctx_workarounds_get(dev_priv, _table, _count);
for (i = 0; i < table_count; i++) {
const struct i915_wa_reg *wa = wa_table[i].table;
 
for (j = 0; j < wa_table[i].count; j++) {
-   u32 read;
-   bool ok;
-
if (!wa[j].applied)
continue;
 
-   read = I915_READ(wa[j].addr);
-   ok = (wa[j].value & wa[j].mask) == (read & wa[j].mask);
seq_printf(m,
-  "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, 
status: %s, name: %s\n",
+  "0x%X: 0x%08X, mask: 0x%08X, name: %s\n",
   i915_mmio_reg_offset(wa[j].addr), 
wa[j].value,
-  wa[j].mask, read, ok ? "OK" : "FAIL", 
wa[j].name);
+  wa[j].mask, wa[j].name);
}
}
+   seq_putc(m, '\n');
+
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   seq_printf(m, "GT workarounds applied: %d\n", workarounds->gt_count);
+   intel_gt_workarounds_get(dev_priv, _table, _count);
+   check_wa_registers(m, wa_table, table_count);
+   seq_putc(m, '\n');
+
+   seq_printf(m, "Display workarounds applied: %d\n",
+  workarounds->disp_count);
+   intel_display_workarounds_get(dev_priv, _table, _count);
+   check_wa_registers(m, wa_table, table_count);
+   seq_putc(m, '\n');
+
+   seq_printf(m, "Whitelist workarounds applied: %d\n",
+  workarounds->hw_whitelist_count[RCS]);
+   intel_whitelist_workarounds_get(dev_priv, _table, _count);
+   check_wa_registers(m, wa_table,

[Intel-gfx] [RFC PATCH 17/20] drm/i915/skl: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2: Static tables (Joonas)

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 15 +--
 drivers/gpu/drm/i915/intel_workarounds.c |  8 
 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 98e976e..eb5bac0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8417,17 +8417,6 @@ static void gen8_set_l3sqc_credits(struct 
drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   /* WAC6entrylatency:skl */
-   I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
-  FBC_LLC_FULLY_OPEN);
-
-   /* WaFbcNukeOnHostModify:skl */
-   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
-}
-
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
/* The GTT cache must be disabled if the system is using 2M pages. */
@@ -8878,10 +8867,8 @@ void intel_init_clock_gating_hooks(struct 
drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv)   ||
-   IS_BROXTON(dev_priv))
+   IS_BROXTON(dev_priv)|| IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = nop_init_clock_gating;
-   else if (IS_SKYLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = skl_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.init_clock_gating = bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 1ebe56d..0e3f7c3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -932,6 +932,14 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
{ WA_DISP("WaDisableDopClockGating"),
  ALL_REVS, REG(GEN7_MISCCPCTL),
  CLEAR_BIT(GEN7_DOP_CLOCK_GATE_ENABLE) },
+
+   { WA_DISP("WAC6entrylatency"),
+ ALL_REVS, REG(FBC_LLC_READ_CTRL),
+ SET_BIT(FBC_LLC_FULLY_OPEN) },
+
+   { WA_DISP("WaFbcNukeOnHostModify"),
+ ALL_REVS, REG(ILK_DPFC_CHICKEN),
+ SET_BIT(ILK_DPFC_NUKE_ON_ANY_MODIFICATION) },
 };
 
 static struct i915_wa_reg bxt_disp_was[] = {
-- 
1.9.1

___
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[Intel-gfx] [RFC PATCH 07/20] drm/i915: Create a new category of display WAs

2017-11-03 Thread Oscar Mateo

Display workarounds do not need to be re-applied on a GPU reset
(this is, in Ville's words: "at the very least wasted effort [...]
and could even be actively harmful in case we end up clobbering
something the current display configuration depends on"). Therefore,
they have to be applied in a different place that GT ones so they
deserve their own category.

Actually populating this is left for future patches: we have to
start moving WAs from init_clock_gating into either GT or
Display functions, and this requires a good deal of careful code
reviewing.

v2: Rebased to carry the init_early nomenclature over (Chris)

v3: Static tables version (Joonas)

Suggested-by: Ville Syrjälä 
Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v2)
Cc: Mika Kuoppala 
Cc: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_drv.h  |   1 +
 drivers/gpu/drm/i915/intel_pm.c  |   2 +
 drivers/gpu/drm/i915/intel_workarounds.c | 124 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   5 ++
 4 files changed, 132 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6a62a7b..f781d1c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2010,6 +2010,7 @@ struct i915_wa_reg_table {
 struct i915_workarounds {
u32 ctx_count;
u32 gt_count;
+   u32 disp_count;
u32 hw_whitelist_count[I915_NUM_ENGINES];
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index acd0cbb..0d0e84b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -29,6 +29,7 @@
 #include 
 #include "i915_drv.h"
 #include "intel_drv.h"
+#include "intel_workarounds.h"
 #include "../../../platform/x86/intel_ips.h"
 #include 
 #include 
@@ -9013,6 +9014,7 @@ static void i830_init_clock_gating(struct 
drm_i915_private *dev_priv)
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
dev_priv->display.init_clock_gating(dev_priv);
+   intel_display_workarounds_apply(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 849e70a..5a532a0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -33,6 +33,10 @@
.name = (wa),   \
.type = I915_WA_TYPE_GT
 
+#define WA_DISP(wa)\
+   .name = (wa),   \
+   .type = I915_WA_TYPE_DISPLAY
+
 #define WA_WHITELIST(wa)   \
.name = (wa),   \
.type = I915_WA_TYPE_WHITELIST
@@ -868,6 +872,126 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
DRM_DEBUG_DRIVER("Number of GT specific w/a: %u\n", total_count);
 }
 
+static struct i915_wa_reg gen8_disp_was[] = {
+};
+
+static struct i915_wa_reg bdw_disp_was[] = {
+};
+
+static struct i915_wa_reg chv_disp_was[] = {
+};
+
+static struct i915_wa_reg gen9_disp_was[] = {
+};
+
+static struct i915_wa_reg skl_disp_was[] = {
+};
+
+static struct i915_wa_reg bxt_disp_was[] = {
+};
+
+static struct i915_wa_reg kbl_disp_was[] = {
+};
+
+static struct i915_wa_reg glk_disp_was[] = {
+};
+
+static struct i915_wa_reg cfl_disp_was[] = {
+};
+
+static struct i915_wa_reg cnl_disp_was[] = {
+};
+
+static const struct i915_wa_reg_table bdw_disp_wa_tbl[] = {
+   { gen8_disp_was, ARRAY_SIZE(gen8_disp_was) },
+   { bdw_disp_was,  ARRAY_SIZE(bdw_disp_was) },
+};
+
+static const struct i915_wa_reg_table chv_disp_wa_tbl[] = {
+   { gen8_disp_was, ARRAY_SIZE(gen8_disp_was) },
+   { chv_disp_was,  ARRAY_SIZE(chv_disp_was) },
+};
+
+static const struct i915_wa_reg_table skl_disp_wa_tbl[] = {
+   { gen9_disp_was, ARRAY_SIZE(gen9_disp_was) },
+   { skl_disp_was,  ARRAY_SIZE(skl_disp_was) },
+};
+
+static const struct i915_wa_reg_table bxt_disp_wa_tbl[] = {
+   { gen9_disp_was, ARRAY_SIZE(gen9_disp_was) },
+   { bxt_disp_was,  ARRAY_SIZE(bxt_disp_was) },
+};
+
+static const struct i915_wa_reg_table kbl_disp_wa_tbl[] = {
+   { gen9_disp_was, ARRAY_SIZE(gen9_disp_was) },
+   { kbl_disp_was,  ARRAY_SIZE(kbl_disp_was) },
+};
+
+static const struct i915_wa_reg_table glk_disp_wa_tbl[] = {
+   { gen9_disp_was, ARRAY_SIZE(gen9_disp_was) },
+   { glk_disp_was,  ARRAY_SIZE(glk_disp_was) },
+};
+
+static const struct i915_wa_reg_table cfl_disp_wa_tbl[] = {
+   { gen9_disp_was, ARRAY_SIZE(gen9_disp_was) },
+   { cfl_disp_was,  ARRAY_SIZE(cfl_disp_was) },
+};
+
+static const struct i915_wa_reg_table cnl_disp_wa_tbl[] = {
+   { cnl_disp_was,  ARRAY_SIZE(cnl_disp_was) },
+};
+
+void intel_display_workarounds_get(struct drm_i915_private *dev_priv,
+  const struct i915_wa_reg_table

[Intel-gfx] [RFC PATCH 09/20] drm/i915: Do not store the total counts of WAs

2017-11-03 Thread Oscar Mateo

Simply recalculate as needed so that we can remove the
workarounds structure in dev_priv.

Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 34 
 drivers/gpu/drm/i915/i915_drv.h  |  9 -
 drivers/gpu/drm/i915/intel_workarounds.c |  4 
 3 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8a6fef4..8fa8c68 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3392,11 +3392,28 @@ static void check_wa_registers(struct seq_file *m,
}
 }
 
+static uint count_wa_registers(const struct i915_wa_reg_table *wa_table,
+  uint table_count)
+{
+   uint total = 0;
+   int i, j;
+
+   for (i = 0; i < table_count; i++) {
+   const struct i915_wa_reg *wa = wa_table[i].table;
+
+   for (j = 0; j < wa_table[i].count; j++) {
+   if (wa[j].applied)
+   total++;
+   }
+   }
+
+   return total;
+}
+
 static int i915_wa_registers(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_device *dev = _priv->drm;
-   struct i915_workarounds *workarounds = _priv->workarounds;
const struct i915_wa_reg_table *wa_table;
uint table_count;
int i, j, ret;
@@ -3407,9 +3424,9 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
 
intel_runtime_pm_get(dev_priv);
 
-   seq_printf(m, "Context workarounds applied: %d\n",
-  workarounds->ctx_count);
intel_ctx_workarounds_get(dev_priv, _table, _count);
+   seq_printf(m, "Context workarounds applied: %d\n",
+  count_wa_registers(wa_table, table_count));
for (i = 0; i < table_count; i++) {
const struct i915_wa_reg *wa = wa_table[i].table;
 
@@ -3427,20 +3444,21 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
 
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-   seq_printf(m, "GT workarounds applied: %d\n", workarounds->gt_count);
intel_gt_workarounds_get(dev_priv, _table, _count);
+   seq_printf(m, "GT workarounds applied: %d\n",
+  count_wa_registers(wa_table, table_count));
check_wa_registers(m, wa_table, table_count);
seq_putc(m, '\n');
 
-   seq_printf(m, "Display workarounds applied: %d\n",
-  workarounds->disp_count);
intel_display_workarounds_get(dev_priv, _table, _count);
+   seq_printf(m, "Display workarounds applied: %d\n",
+  count_wa_registers(wa_table, table_count));
check_wa_registers(m, wa_table, table_count);
seq_putc(m, '\n');
 
-   seq_printf(m, "Whitelist workarounds applied: %d\n",
-  workarounds->hw_whitelist_count[RCS]);
intel_whitelist_workarounds_get(dev_priv, _table, _count);
+   seq_printf(m, "Whitelist workarounds applied: %d\n",
+  count_wa_registers(wa_table, table_count));
check_wa_registers(m, wa_table, table_count);
seq_putc(m, '\n');
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f781d1c..7efb59b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2007,13 +2007,6 @@ struct i915_wa_reg_table {
int count;
 };
 
-struct i915_workarounds {
-   u32 ctx_count;
-   u32 gt_count;
-   u32 disp_count;
-   u32 hw_whitelist_count[I915_NUM_ENGINES];
-};
-
 struct i915_virtual_gpu {
bool active;
u32 caps;
@@ -2452,8 +2445,6 @@ struct drm_i915_private {
 
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
-   struct i915_workarounds workarounds;
-
struct i915_frontbuffer_tracking fb_tracking;
 
struct intel_atomic_helper {
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5a532a0..74e59bb 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -551,7 +551,6 @@ static uint ctx_workarounds_init(struct drm_i915_private 
*dev_priv,
}
}
 
-   dev_priv->workarounds.ctx_count = total_count;
DRM_DEBUG_DRIVER("Number of context specific w/a: %u\n", total_count);
 
return total_count;
@@ -868,7 +867,6 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
intel_gt_workarounds_get(dev_priv, _table, _count);
total_count = mmio_workarounds_apply(dev_priv, wa_table, table_count);
 
-   dev_priv->workarounds.gt_count = total_count;
DRM_DEBUG_DRIVER("Number of GT specific w/a: %u\n", total_count);
 }
 
@@ -988,7 +986,6 @@ void intel_display_workarounds_apply(struct 
drm_i915_private *dev_priv)

[Intel-gfx] [RFC PATCH 19/20] drm/i915/bdw: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

TODO2: Decide what to do with lpt_init_clock_gating (shouldn't
WADPOClockGatingDisable be marked as "bdw"? shouldn't it be
protected by HAS_PCH_LPT_LP? do we want to move the whole thing
to the workarounds file or not?).

v2: Classify WaDisableSDEUnitClockGating as GT WA
v3:
  - Static tables (Joonas)
  - Also move WaProgramL3SqcReg1Default/WaTempDisableDOPClkGating

Signed-off-by: Oscar Mateo 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
Cc: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c  | 76 --
 drivers/gpu/drm/i915/intel_workarounds.c | 81 +---
 2 files changed, 74 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aef0aee..0fc0670 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8391,87 +8391,11 @@ static void lpt_suspend_hw(struct drm_i915_private 
*dev_priv)
}
 }
 
-static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
-  int general_prio_credits,
-  int high_prio_credits)
-{
-   u32 misccpctl;
-   u32 val;
-
-   /* WaTempDisableDOPClkGating:bdw */
-   misccpctl = I915_READ(GEN7_MISCCPCTL);
-   I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-
-   val = I915_READ(GEN8_L3SQCREG1);
-   val &= ~L3_PRIO_CREDITS_MASK;
-   val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
-   val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
-   I915_WRITE(GEN8_L3SQCREG1, val);
-
-   /*
-* Wait at least 100 clocks before re-enabling clock gating.
-* See the definition of L3SQCREG1 in BSpec.
-*/
-   POSTING_READ(GEN8_L3SQCREG1);
-   udelay(1);
-   I915_WRITE(GEN7_MISCCPCTL, misccpctl);
-}
-
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   /* The GTT cache must be disabled if the system is using 2M pages. */
-   bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
-I915_GTT_PAGE_SIZE_2M);
-   enum pipe pipe;
-
ilk_init_lp_watermarks(dev_priv);
 
-   /* WaSwitchSolVfFArbitrationPriority:bdw */
-   I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
-
-   /* WaPsrDPAMaskVBlankInSRD:bdw */
-   I915_WRITE(CHICKEN_PAR1_1,
-  I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
-
-   /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
-   for_each_pipe(dev_priv, pipe) {
-   I915_WRITE(CHICKEN_PIPESL_1(pipe),
-  I915_READ(CHICKEN_PIPESL_1(pipe)) |
-  BDW_DPRS_MASK_VBLANK_SRD);
-   }
-
-   /* WaVSRefCountFullforceMissDisable:bdw */
-   /* WaDSRefCountFullforceMissDisable:bdw */
-   I915_WRITE(GEN7_FF_THREAD_MODE,
-  I915_READ(GEN7_FF_THREAD_MODE) &
-  ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
-
-   I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
-  _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-
-   /* WaDisableSDEUnitClockGating:bdw */
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-   /* WaProgramL3SqcReg1Default:bdw */
-   gen8_set_l3sqc_credits(dev_priv, 30, 2);
-
-   /* WaGttCachingOffByDefault:bdw */
-   I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
-
-   /* WaKVMNotificationOnConfigChange:bdw */
-   I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
-  | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
-
lpt_init_clock_gating(dev_priv);
-
-   /* WaDisableDopClockGating:bdw
-*
-* Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
-* clock gating.
-*/
-   I915_WRITE(GEN6_UCGCTL1,
-  I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 1ebce4f..a8fe655 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -643,9 +643,6 @@ static uint mmio_workarounds_apply(struct drm_i915_private 
*dev_priv,
return total_count;
 }
 
-static struct i915_wa_reg gen8_gt_was[] = {
-};
-
 /* WaTempDisableDOPClkGating */
 static bool disable_dop_clock_gating(struct drm_i915_private *dev_priv,
 struct i915_wa_reg *wa)
@@ -673,7 +670,45 @@ static void enable_dop_clock_gating(struct 
drm_i915_private

[Intel-gfx] [RFC PATCH 05/20] drm/i915: Transform GT WAs into static tables

2017-11-03 Thread Oscar Mateo

This is for WAs that need to touch global MMIO registers
related to GT.

Suggested-by: Joonas Lahtinen 
Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h  |   1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 404 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +
 3 files changed, 253 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c73fec..72b5d80 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2007,6 +2007,7 @@ struct i915_wa_reg_table {
 
 struct i915_workarounds {
u32 ctx_count;
+   u32 gt_count;
u32 hw_whitelist_count[I915_NUM_ENGINES];
 };
 
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index b00899e..b07fbd0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -29,6 +29,10 @@
.name = (wa),   \
.type = I915_WA_TYPE_CONTEXT
 
+#define WA_GT(wa)  \
+   .name = (wa),   \
+   .type = I915_WA_TYPE_GT
+
 #define ALL_REVS   \
.since = 0, \
.until = REVID_FOREVER
@@ -40,6 +44,18 @@
 #define REG(a) \
.addr = (a)
 
+#define SET_BIT(m) \
+   .mask = (m),\
+   .value = (m)
+
+#define CLEAR_BIT(m)   \
+   .mask = (m),\
+   .value = 0
+
+#define SET_FIELD(m, v)\
+   .mask = (m),\
+   .value = (v)
+
 #define MASK(mask, value)  ((mask) << 16 | (value))
 #define MASK_ENABLE(x) (MASK((x), (x)))
 #define MASK_DISABLE(x)(MASK((x), 0))
@@ -575,196 +591,274 @@ int intel_ctx_workarounds_emit(struct 
drm_i915_gem_request *req)
return 0;
 }
 
-static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+static uint mmio_workarounds_apply(struct drm_i915_private *dev_priv,
+  const struct i915_wa_reg_table *wa_table,
+  uint table_count)
 {
-}
+   uint total_count = 0;
+   int i, j;
 
-static void chv_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-{
-}
+   for (i = 0; i < table_count; i++) {
+   struct i915_wa_reg *wa = wa_table[i].table;
 
-static void gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-{
-   if (HAS_LLC(dev_priv)) {
-   /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
-*
-* Must match Display Engine. See
-* WaCompressedResourceDisplayNewHashMode.
-*/
-   I915_WRITE(MMCD_MISC_CTRL,
-  I915_READ(MMCD_MISC_CTRL) |
-  MMCD_PCLA |
-  MMCD_HOTSPOT_EN);
-   }
+   for (j = 0; j < wa_table[i].count; j++) {
+   wa[j].applied =
+   IS_REVID(dev_priv, wa[j].since, wa[j].until);
 
-   /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
-   I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
-  _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
+   if (wa[j].applied && wa[j].pre_hook)
+   wa[j].applied = wa[j].pre_hook(dev_priv, 
[j]);
 
-   /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
-   I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
-  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+   if (wa[j].applied) {
+   i915_reg_t addr = wa[j].addr;
+   u32 value = wa[j].value;
+   u32 mask = wa[j].mask;
 
-   /* WaDisableKillLogic:bxt,skl,kbl */
-   if (!IS_COFFEELAKE(dev_priv))
-   I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-  ECOCHK_DIS_TLB);
+   if (wa[j].is_masked_reg) {
+   GEM_BUG_ON(mask & 0x);
+   I915_WRITE(addr, value);
+   } else {
+   I915_WRITE(addr,
+   (I915_READ(addr) & ~mask) |
+   value);
+   }
 
-   /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
-   I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-  BDW_DISABLE_HDC_INVALIDATION);
+   if (wa[j].post_hook)
+   wa[j].post_hook(dev_priv, [j]);
 
-   /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */

[Intel-gfx] [RFC PATCH 20/20] drm/i915: Document the i915_workarounds file

2017-11-03 Thread Oscar Mateo

Does what it says on the tin (plus a few fixes in some old comments).

v2: Include display WAs as a separate category.
v3: Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  |  4 +---
 drivers/gpu/drm/i915/intel_workarounds.c | 40 
 2 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0fc0670..98c2ac8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8749,9 +8749,7 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
  * @dev_priv: device private
  *
  * Setup the hooks that configure which clocks of a given platform can be
- * gated and also apply various GT and display specific workarounds for these
- * platforms. Note that some GT specific workarounds are applied separately
- * when GPU contexts or batchbuffers start their execution.
+ * gated.
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a8fe655..005cff7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -25,6 +25,37 @@
 #include "i915_drv.h"
 #include "intel_workarounds.h"
 
+/**
+ * DOC: Hardware workarounds
+ *
+ * This file is a central place to implement most* of the required workarounds
+ * required for HW to work as originally intended. They fall in five basic
+ * categories depending on how/when they are applied:
+ *
+ * - Workarounds that touch registers that are saved/restored to/from the HW
+ *   context image. The list is emitted (via Load Register Immediate commands)
+ *   everytime a new context is created.
+ * - GT workarounds. The list of these WAs is applied whenever these registers
+ *   revert to default values (on GPU reset, suspend/resume**, etc..).
+ * - Display workarounds. The list is applied during display clock-gating
+ *   initialization.
+ * - Workarounds that whitelist a privileged register, so that UMDs can manage
+ *   them directly. This is just a special case of a MMMIO workaround (as we
+ *   write the list of these to/be-whitelisted registers to some special HW
+ *   registers).
+ * - Workaround batchbuffers, that get executed automatically by the hardware
+ *   on every HW context restore.
+ *
+ * * Please notice that there are other WAs that, due to their nature, cannot 
be
+ *   applied from a central place. Those are peppered around the rest of the
+ *   code, as needed).
+ *
+ * ** Technically, some registers are powercontext saved & restored, so they
+ *survive a suspend/resume. In practice, writing them again is not too
+ *costly and simplifies things. We can revisit this in the future.
+ *
+ */
+
 #define WA_CTX(wa) \
.name = (wa),   \
.type = I915_WA_TYPE_CONTEXT
@@ -1382,10 +1413,11 @@ int intel_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
  * but there is a slight complication as this is applied in WA batch where the
  * values are only initialized once so we cannot take register value at the
  * beginning and reuse it further; hence we save its value to memory, upload a
- * constant value with bit21 set and then we restore it back with the saved 
value.
+ * constant value with bit21 set and then we restore it back with the saved
+ * value.
  * To simplify the WA, a constant value is formed by using the default value
  * of this register. This shouldn't be a problem because we are only modifying
- * it for a short period and this batch in non-premptible. We can ofcourse
+ * it for a short period and this batch in non-premptible. We can of course
  * use additional instructions that read the actual value of the register
  * at that time and set our bit of interest but it makes the WA complicated.
  *
@@ -1421,8 +1453,8 @@ int intel_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
  * Typically we only have one indirect_ctx and per_ctx batch buffer which are
  * initialized at the beginning and shared across all contexts but this field
  * helps us to have multiple batches at different offsets and select them based
- * on a criteria. At the moment this batch always start at the beginning of 
the page
- * and at this point we don't have multiple wa_ctx batch buffers.
+ * on a criteria. At the moment this batch always start at the beginning of the
+ * page and at this point we don't have multiple wa_ctx batch buffers.
  *
  * The number of WA applied are not known at the beginning; we use this field
  * to return the no of DWORDS written.
-- 
1.9.1

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[Intel-gfx] [RFC PATCH 14/20] drm/i915/glk: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2: Static tables

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 33 ++--
 drivers/gpu/drm/i915/intel_workarounds.c | 16 
 2 files changed, 18 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a85a001..b5e7432 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -78,34 +78,6 @@ static void bxt_init_clock_gating(struct drm_i915_private 
*dev_priv)
   PWM1_GATING_DIS | PWM2_GATING_DIS);
 }
 
-static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   u32 val;
-
-   /*
-* WaDisablePWMClockGating:glk
-* Backlight PWM may stop in the asserted state, causing backlight
-* to stay fully on.
-*/
-   I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
-  PWM1_GATING_DIS | PWM2_GATING_DIS);
-
-   /* WaDDIIOTimeout:glk */
-   if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
-   u32 val = I915_READ(CHICKEN_MISC_2);
-   val &= ~(GLK_CL0_PWR_DOWN |
-GLK_CL1_PWR_DOWN |
-GLK_CL2_PWR_DOWN);
-   I915_WRITE(CHICKEN_MISC_2, val);
-   }
-
-   /* Display WA #1133: WaFbcSkipSegments:glk */
-   val = I915_READ(ILK_DPFC_CHICKEN);
-   val &= ~GLK_SKIP_SEG_COUNT_MASK;
-   val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
-   I915_WRITE(ILK_DPFC_CHICKEN, val);
-}
-
 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 {
u32 tmp;
@@ -8942,7 +8914,8 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-   if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
+   if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
+   IS_GEMINILAKE(dev_priv))
dev_priv->display.init_clock_gating = nop_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skl_init_clock_gating;
@@ -8950,8 +8923,6 @@ void intel_init_clock_gating_hooks(struct 
drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
-   else if (IS_GEMINILAKE(dev_priv))
-   dev_priv->display.init_clock_gating = glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.init_clock_gating = bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 4fe1dd0..a438ce3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -929,6 +929,22 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
 };
 
 static struct i915_wa_reg glk_disp_was[] = {
+   /*
+* Backlight PWM may stop in the asserted state, causing backlight
+* to stay fully on.
+*/
+   { WA_DISP("WaDisablePWMClockGating"),
+ ALL_REVS, REG(GEN9_CLKGATE_DIS_0),
+ SET_BIT(PWM1_GATING_DIS | PWM2_GATING_DIS) },
+
+   { WA_DISP("WaDDIIOTimeout"),
+ REVS(0, GLK_REVID_A1), REG(CHICKEN_MISC_2),
+ CLEAR_BIT(GLK_CL0_PWR_DOWN | GLK_CL1_PWR_DOWN | GLK_CL2_PWR_DOWN) },
+
+   { WA_DISP("Display WA #1133: WaFbcSkipSegments"),
+ ALL_REVS, REG(ILK_DPFC_CHICKEN),
+ SET_FIELD(GLK_SKIP_SEG_COUNT_MASK,
+   GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1)) },
 };
 
 static bool has_pch_cnp(struct drm_i915_private *dev_priv,
-- 
1.9.1

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[Intel-gfx] [RFC PATCH 11/20] drm/i915/cnl: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2: classify WaSarbUnitClockGatingDisable as GT WA (Ville)
v3: Static tables

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 32 +---
 drivers/gpu/drm/i915/intel_workarounds.c | 32 
 2 files changed, 33 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0d0e84b..ff3ac6c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8519,36 +8519,6 @@ static void cnp_init_clock_gating(struct 
drm_i915_private *dev_priv)
   CNP_PWM_CGE_GATING_DISABLE);
 }
 
-static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   u32 val;
-   cnp_init_clock_gating(dev_priv);
-
-   /* This is not an Wa. Enable for better image quality */
-   I915_WRITE(_3D_CHICKEN3,
-  _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
-
-   /* WaEnableChickenDCPR:cnl */
-   I915_WRITE(GEN8_CHICKEN_DCPR_1,
-  I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
-   /* WaFbcWakeMemOn:cnl */
-   I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-  DISP_FBC_MEMORY_WAKE);
-
-   /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
-   if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
-   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
-  I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
-  SARBUNIT_CLKGATE_DIS);
-
-   /* Display WA #1133: WaFbcSkipSegments:cnl */
-   val = I915_READ(ILK_DPFC_CHICKEN);
-   val &= ~GLK_SKIP_SEG_COUNT_MASK;
-   val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
-   I915_WRITE(ILK_DPFC_CHICKEN, val);
-}
-
 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
cnp_init_clock_gating(dev_priv);
@@ -9040,7 +9010,7 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = cnl_init_clock_gating;
+   dev_priv->display.init_clock_gating = nop_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 72e8d90..a0b34d9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -779,6 +779,15 @@ static uint mmio_workarounds_apply(struct drm_i915_private 
*dev_priv,
{ WA_GT("WaEnablePreemptionGranularityControlByUMD"),
  ALL_REVS, REG(GEN7_FF_SLICE_CS_CHICKEN1),
  SET_BIT_MASKED(GEN9_FFSC_PERCTX_PREEMPT_CTRL) },
+
+   /* This is not an Wa. Enable for better image quality */
+   { WA_GT(""),
+ ALL_REVS, REG(_3D_CHICKEN3),
+ SET_BIT_MASKED(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE) },
+
+   { WA_GT("WaSarbUnitClockGatingDisable (pre-prod)"),
+ REVS(CNL_REVID_A0, CNL_REVID_B0), REG(SLICE_UNIT_LEVEL_CLKGATE),
+ SET_BIT(SARBUNIT_CLKGATE_DIS) },
 };
 
 static const struct i915_wa_reg_table bdw_gt_wa_tbl[] = {
@@ -894,10 +903,33 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
 static struct i915_wa_reg glk_disp_was[] = {
 };
 
+static bool has_pch_cnp(struct drm_i915_private *dev_priv,
+   struct i915_wa_reg *wa)
+{
+   return HAS_PCH_CNP(dev_priv);
+}
+
 static struct i915_wa_reg cfl_disp_was[] = {
 };
 
 static struct i915_wa_reg cnl_disp_was[] = {
+   { WA_DISP("Wa #1181"),
+ ALL_REVS, REG(SOUTH_DSPCLK_GATE_D),
+ SET_BIT(CNP_PWM_CGE_GATING_DISABLE),
+ .pre_hook = has_pch_cnp },
+
+   { WA_DISP("WaEnableChickenDCPR"),
+ ALL_REVS, REG(GEN8_CHICKEN_DCPR_1),
+ SET_BIT(MASK_WAKEMEM) },
+
+   { WA_DISP("WaFbcWakeMemOn"),
+ ALL_REVS, REG(DISP_ARB_CTL),
+ SET_BIT(DISP_FBC_MEMORY_WAKE) },
+
+   { WA_DISP("Display WA #1133: WaFbcSkipSegments"),
+ ALL_REVS, REG(ILK_DPFC_CHICKEN),
+ SET_FIELD(GLK_SKIP_SEG_COUNT_MASK,
+   GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1)) },
 };
 
 static const struct i915_wa_reg_table bdw_disp_wa_tbl[] = {
-- 
1.9.1

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[Intel-gfx] [RFC PATCH 15/20] drm/i915/kbl: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2: Classify WaDisableSDEUnitClockGating and WaDisableGamClockGating
as GT WAs

v3: Static tables (Joonas)

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 21 +
 drivers/gpu/drm/i915/intel_workarounds.c | 11 +++
 2 files changed, 12 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b5e7432..046553b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8438,23 +8438,6 @@ static void gen8_set_l3sqc_credits(struct 
drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   /* WaDisableSDEUnitClockGating:kbl */
-   if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-   /* WaDisableGamClockGating:kbl */
-   if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
-   I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
-  GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
-
-   /* WaFbcNukeOnHostModify:kbl */
-   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
-}
-
 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
/* WAC6entrylatency:skl */
@@ -8915,12 +8898,10 @@ static void nop_init_clock_gating(struct 
drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
-   IS_GEMINILAKE(dev_priv))
+   IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = nop_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skl_init_clock_gating;
-   else if (IS_KABYLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a438ce3..396399b 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,14 @@ static uint mmio_workarounds_apply(struct drm_i915_private 
*dev_priv,
{ WA_GT("WaInPlaceDecompressionHang"),
  ALL_REVS, REG(GEN9_GAMT_ECO_REG_RW_IA),
  SET_BIT(GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS) },
+
+   { WA_GT("WaDisableSDEUnitClockGating"),
+ REVS(0, KBL_REVID_B0), REG(GEN8_UCGCTL6),
+ SET_BIT(GEN8_SDEUNIT_CLOCK_GATE_DISABLE) },
+
+   { WA_GT("WaDisableGamClockGating"),
+ REVS(0, KBL_REVID_B0), REG(GEN6_UCGCTL1),
+ SET_BIT(GEN6_GAMUNIT_CLOCK_GATE_DISABLE) },
 };
 
 static struct i915_wa_reg glk_gt_was[] = {
@@ -926,6 +934,9 @@ void intel_gt_workarounds_apply(struct drm_i915_private 
*dev_priv)
 };
 
 static struct i915_wa_reg kbl_disp_was[] = {
+   { WA_DISP("WaFbcNukeOnHostModify"),
+ ALL_REVS, REG(ILK_DPFC_CHICKEN),
+ SET_BIT(ILK_DPFC_NUKE_ON_ANY_MODIFICATION) },
 };
 
 static struct i915_wa_reg glk_disp_was[] = {
-- 
1.9.1

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[Intel-gfx] [RFC PATCH 18/20] drm/i915/chv: Move GT and Display workarounds from init_clock_gating

2017-11-03 Thread Oscar Mateo

To their rightful place inside intel_workarounds.c

v2: Classify WaDisableCSUnitClockGating and WaDisableSDEUnitClockGating
as GT WAs

v3:
  - Static tables (Joonas)
  - Also move WaProgramL3SqcReg1Default/WaTempDisableDOPClkGating

Signed-off-by: Oscar Mateo 
Reviewed-by: Chris Wilson  (v1)
Cc: Rodrigo Vivi 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c  | 39 +---
 drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
 2 files changed, 59 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb5bac0..aef0aee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8705,40 +8705,6 @@ static void vlv_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
-static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   /* WaVSRefCountFullforceMissDisable:chv */
-   /* WaDSRefCountFullforceMissDisable:chv */
-   I915_WRITE(GEN7_FF_THREAD_MODE,
-  I915_READ(GEN7_FF_THREAD_MODE) &
-  ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
-
-   /* WaDisableSemaphoreAndSyncFlipWait:chv */
-   I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
-  _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-
-   /* WaDisableCSUnitClockGating:chv */
-   I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
-  GEN6_CSUNIT_CLOCK_GATE_DISABLE);
-
-   /* WaDisableSDEUnitClockGating:chv */
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-   /*
-* WaProgramL3SqcReg1Default:chv
-* See gfxspecs/Related Documents/Performance Guide/
-* LSQC Setting Recommendations.
-*/
-   gen8_set_l3sqc_credits(dev_priv, 38, 2);
-
-   /*
-* GTT cache may not work with big pages, so if those
-* are ever enabled GTT cache may need to be disabled.
-*/
-   I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
-}
-
 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
 {
uint32_t dspclk_gate;
@@ -8867,12 +8833,11 @@ void intel_init_clock_gating_hooks(struct 
drm_i915_private *dev_priv)
 {
if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv)   ||
-   IS_BROXTON(dev_priv)|| IS_SKYLAKE(dev_priv))
+   IS_BROXTON(dev_priv)|| IS_SKYLAKE(dev_priv)||
+   IS_CHERRYVIEW(dev_priv))
dev_priv->display.init_clock_gating = nop_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.init_clock_gating = bdw_init_clock_gating;
-   else if (IS_CHERRYVIEW(dev_priv))
-   dev_priv->display.init_clock_gating = chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
dev_priv->display.init_clock_gating = hsw_init_clock_gating;
else if (IS_IVYBRIDGE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 0e3f7c3..1ebce4f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -646,10 +646,67 @@ static uint mmio_workarounds_apply(struct 
drm_i915_private *dev_priv,
 static struct i915_wa_reg gen8_gt_was[] = {
 };
 
+/* WaTempDisableDOPClkGating */
+static bool disable_dop_clock_gating(struct drm_i915_private *dev_priv,
+struct i915_wa_reg *wa)
+{
+   u32 misccpctl = I915_READ(GEN7_MISCCPCTL);
+
+   wa->hook_data = misccpctl;
+   I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+
+   return true;
+}
+
+/* WaTempDisableDOPClkGating */
+static void enable_dop_clock_gating(struct drm_i915_private *dev_priv,
+   struct i915_wa_reg *wa)
+{
+   u32 misccpctl = wa->hook_data;
+
+   /*
+* Wait at least 100 clocks before re-enabling clock
+* gating. See the definition of L3SQCREG1 in BSpec.
+*/
+   POSTING_READ(GEN8_L3SQCREG1);
+   udelay(1);
+   I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+}
+
 static struct i915_wa_reg bdw_gt_was[] = {
 };
 
 static struct i915_wa_reg chv_gt_was[] = {
+   { WA_GT("WaVSRefCountFullforceMissDisable + 
WaDSRefCountFullforceMissDisable"),
+ ALL_REVS, REG(GEN7_FF_THREAD_MODE),
+ CLEAR_BIT(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME) },
+
+   { WA_GT("WaDisableSemaphoreAndSyncFlipWait"),
+ ALL_REVS, REG(GEN6_RC_SLEEP_PSMI_CONTROL),
+ SET_BIT_MASKED(GEN8_RC_SEMA_IDLE_MSG_DISABLE) },
+
+   { WA_GT("WaDisableCSUnitClockGating"),
+ ALL_REVS,

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v3] drm/i915: Define an engine class enum for the 
uABI (rev2)
URL   : https://patchwork.freedesktop.org/series/33126/
State : failure

== Summary ==

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-B:
pass   -> DMESG-WARN (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test pm_rpm:
Subgroup i2c:
pass   -> FAIL   (shard-hsw)
Subgroup system-suspend-modeset:
pass   -> FAIL   (shard-hsw)
Subgroup cursor:
pass   -> FAIL   (shard-hsw)
Subgroup debugfs-forcewake-user:
pass   -> FAIL   (shard-hsw)
Subgroup gem-pread:
pass   -> FAIL   (shard-hsw)
Subgroup gem-execbuf:
pass   -> FAIL   (shard-hsw)
Subgroup system-suspend-execbuf:
pass   -> DMESG-FAIL (shard-hsw)
Subgroup drm-resources-equal:
pass   -> FAIL   (shard-hsw)
Subgroup dpms-mode-unset-non-lpsp:
pass   -> FAIL   (shard-hsw)
Subgroup gem-idle:
pass   -> FAIL   (shard-hsw)
Subgroup system-suspend:
pass   -> DMESG-FAIL (shard-hsw)
Subgroup dpms-mode-unset-lpsp:
skip   -> FAIL   (shard-hsw)
Subgroup cursor-dpms:
pass   -> FAIL   (shard-hsw)
Subgroup basic-pci-d3-state:
pass   -> FAIL   (shard-hsw)
Subgroup universal-planes:
pass   -> FAIL   (shard-hsw)
Subgroup dpms-lpsp:
skip   -> FAIL   (shard-hsw)
Subgroup modeset-stress-extra-wait:
pass   -> FAIL   (shard-hsw)
Subgroup legacy-planes-dpms:
pass   -> FAIL   (shard-hsw)
Subgroup modeset-lpsp-stress:
skip   -> FAIL   (shard-hsw)
Subgroup modeset-non-lpsp:
pass   -> FAIL   (shard-hsw)
Subgroup gem-evict-pwrite:
pass   -> FAIL   (shard-hsw)
Test kms_flip:
Subgroup vblank-vs-modeset-rpm:
pass   -> FAIL   (shard-hsw)
Subgroup vblank-vs-dpms-rpm-interruptible:
pass   -> FAIL   (shard-hsw)
Subgroup vblank-vs-suspend-interruptible:
pass   -> DMESG-WARN (shard-hsw) fdo#100368
Subgroup vblank-vs-dpms-suspend:
pass   -> DMESG-WARN (shard-hsw)
Subgroup vblank-vs-dpms-rpm:
pass   -> FAIL   (shard-hsw)
Subgroup vblank-vs-modeset-rpm-interruptible:
pass   -> FAIL   (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass   -> DMESG-WARN (shard-hsw)
Subgroup cursor-64x64-suspend:
pass   -> DMESG-WARN (shard-hsw)
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
dmesg-fail -> FAIL   (shard-hsw) fdo#103375

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2539 pass:1407 dwarn:5   dfail:2   fail:31  skip:1094 
time:9101s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6940/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/2] x86/platform/intel/iosf_mbi: Add unlocked PMIC bus access notifier unregister

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v5,1/2] x86/platform/intel/iosf_mbi: Add unlocked 
PMIC bus access notifier unregister
URL   : https://patchwork.freedesktop.org/series/32288/
State : success

== Summary ==

Series 32288v1 series starting with [v5,1/2] x86/platform/intel/iosf_mbi: Add 
unlocked PMIC bus access notifier unregister
https://patchwork.freedesktop.org/api/1.0/series/32288/revisions/1/mbox/

Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
none   -> INCOMPLETE (fi-cfl-s)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:446s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:452s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:504s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:504s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:509s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:491s
fi-cfl-s total:240  pass:211  dwarn:0   dfail:0   fail:0   skip:28 
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:264s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:584s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:431s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:433s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:423s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:458s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:497s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:576s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:587s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:572s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:443s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:653s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:524s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:503s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:459s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:571s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:432s

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
9d0815239328 drm/i915: Acquire PUNIT->PMIC bus for 
intel_uncore_forcewake_reset()
94acab084274 x86/platform/intel/iosf_mbi: Add unlocked PMIC bus access notifier 
unregister

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6947/
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Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

2017-11-03 Thread Ville Syrjälä

On Fri, Nov 03, 2017 at 10:45:30AM -0700, James Ausmus wrote:
> On Fri, Nov 03, 2017 at 07:31:44PM +0200, Ville Syrjälä wrote:
> > On Fri, Nov 03, 2017 at 09:58:48AM -0700, James Ausmus wrote:
> > > Since GLK, some plane configuration settings have moved to the
> > > PLANE_COLOR_CTL register. Refactor handling of the register to work like
> > > PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
> > > Mode for GLK+.
> > > 
> > > v2: Adjust ordering of platform checks to be newest->oldest, drop
> > > redundant comment about alpha blending. (Ville)
> > > 
> > > Signed-off-by: James Ausmus 
> > > Cc: Paulo Zanoni 
> > > Cc: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h  | 12 +---
> > >  drivers/gpu/drm/i915/intel_display.c | 55 
> > > 
> > >  drivers/gpu/drm/i915/intel_drv.h |  5 
> > >  drivers/gpu/drm/i915/intel_sprite.c  | 14 +
> > >  4 files changed, 71 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index f0f8f6059652..ecd6b236e005 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6263,7 +6263,7 @@ enum {
> > >  #define _PLANE_CTL_2_A   0x70280
> > >  #define _PLANE_CTL_3_A   0x70380
> > >  #define   PLANE_CTL_ENABLE   (1 << 31)
> > > -#define   PLANE_CTL_PIPE_GAMMA_ENABLE(1 << 30)
> > > +#define   PLANE_CTL_PIPE_GAMMA_ENABLE(1 << 30)   /* Pre-GLK 
> > > */
> > >  #define   PLANE_CTL_FORMAT_MASK  (0xf << 24)
> > >  #define   PLANE_CTL_FORMAT_YUV422(  0 << 24)
> > >  #define   PLANE_CTL_FORMAT_NV12  (  1 << 24)
> > > @@ -6273,7 +6273,7 @@ enum {
> > >  #define   PLANE_CTL_FORMAT_AYUV  (  8 << 24)
> > >  #define   PLANE_CTL_FORMAT_INDEXED   ( 12 << 24)
> > >  #define   PLANE_CTL_FORMAT_RGB_565   ( 14 << 24)
> > > -#define   PLANE_CTL_PIPE_CSC_ENABLE  (1 << 23)
> > > +#define   PLANE_CTL_PIPE_CSC_ENABLE  (1 << 23) /* Pre-GLK */
> > >  #define   PLANE_CTL_KEY_ENABLE_MASK  (0x3 << 21)
> > >  #define   PLANE_CTL_KEY_ENABLE_SOURCE(  1 << 21)
> > >  #define   PLANE_CTL_KEY_ENABLE_DESTINATION   (  2 << 21)
> > > @@ -6286,13 +6286,13 @@ enum {
> > >  #define   PLANE_CTL_YUV422_VYUY  (  3 << 16)
> > >  #define   PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
> > >  #define   PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> > > -#define   PLANE_CTL_PLANE_GAMMA_DISABLE  (1 << 13)
> > > +#define   PLANE_CTL_PLANE_GAMMA_DISABLE  (1 << 13) /* Pre-GLK */
> > >  #define   PLANE_CTL_TILED_MASK   (0x7 << 10)
> > >  #define   PLANE_CTL_TILED_LINEAR (  0 << 10)
> > >  #define   PLANE_CTL_TILED_X  (  1 << 10)
> > >  #define   PLANE_CTL_TILED_Y  (  4 << 10)
> > >  #define   PLANE_CTL_TILED_YF (  5 << 10)
> > > -#define   PLANE_CTL_ALPHA_MASK   (0x3 << 4)
> > > +#define   PLANE_CTL_ALPHA_MASK   (0x3 << 4) /* Pre-GLK */
> > >  #define   PLANE_CTL_ALPHA_DISABLE(  0 << 4)
> > >  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY (  2 << 4)
> > >  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY (  3 << 4)
> > > @@ -6332,6 +6332,10 @@ enum {
> > >  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE  (1 << 30)
> > >  #define   PLANE_COLOR_PIPE_CSC_ENABLE(1 << 23)
> > >  #define   PLANE_COLOR_PLANE_GAMMA_DISABLE(1 << 13)
> > > +#define   PLANE_COLOR_ALPHA_MASK (0x3 << 4)
> > > +#define   PLANE_COLOR_ALPHA_DISABLE  (0 << 4)
> > > +#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY   (2 << 4)
> > > +#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY   (3 << 4)
> > >  #define _PLANE_BUF_CFG_1_A   0x7027c
> > >  #define _PLANE_BUF_CFG_2_A   0x7037c
> > >  #define _PLANE_NV12_BUF_CFG_1_A  0x70278
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 737de251d0f8..39453276dad1 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3466,6 +3466,23 @@ static u32 skl_plane_ctl_format(uint32_t 
> > > pixel_format)
> > >   return 0;
> > >  }
> > >  
> > > +static u32 glk_plane_ctl_format(uint32_t pixel_format)
> > > +{
> > > + /* GLK+ moves the alpha mask to a different register */
> > > + return skl_plane_ctl_format(pixel_format) & ~PLANE_CTL_ALPHA_MASK;
> > 
> > I think it would be less confusing to extract the alpha stuff
> > from skl_plane_ctl_format() into skl_plane_ctl_alpha().
> > 
> > I guess with that we wouldn't even need glk_plane_ctl_format()?
> 
> Yeah, I like that

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Misc. PMIC bus access notifier fixes

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: Misc. PMIC bus access notifier fixes
URL   : https://patchwork.freedesktop.org/series/32274/
State : failure

== Summary ==

Series 32274v1 drm/i915: Misc. PMIC bus access notifier fixes
https://patchwork.freedesktop.org/api/1.0/series/32274/revisions/1/mbox/

Test gem_exec_reloc:
Subgroup basic-cpu-active:
pass   -> FAIL   (fi-gdg-551) fdo#102582 +4
Subgroup basic-write-cpu-active:
pass   -> FAIL   (fi-gdg-551)
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:453s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:546s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:506s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:507s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:506s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:496s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:546s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-gdg-551   total:289  pass:173  dwarn:1   dfail:0   fail:6   skip:109 
time:263s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:590s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:428s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:492s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:495s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:576s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:481s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:589s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:574s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:648s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:517s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:498s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:463s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:575s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:419s

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
1e41acb9f5cc drm/i915: Call uncore_suspend before platform suspend handlers
87a5d26f71b5 drm/i915: Re-register PMIC bus access notifier on runtime resume
65eaada483c7 drm/i915: Fix false-positive assert_rpm_wakelock_held in 
i915_pmic_bus_access_notifier

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6946/
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Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

2017-11-03 Thread James Ausmus

On Fri, Nov 03, 2017 at 07:31:44PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 03, 2017 at 09:58:48AM -0700, James Ausmus wrote:
> > Since GLK, some plane configuration settings have moved to the
> > PLANE_COLOR_CTL register. Refactor handling of the register to work like
> > PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
> > Mode for GLK+.
> > 
> > v2: Adjust ordering of platform checks to be newest->oldest, drop
> > redundant comment about alpha blending. (Ville)
> > 
> > Signed-off-by: James Ausmus 
> > Cc: Paulo Zanoni 
> > Cc: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 12 +---
> >  drivers/gpu/drm/i915/intel_display.c | 55 
> > 
> >  drivers/gpu/drm/i915/intel_drv.h |  5 
> >  drivers/gpu/drm/i915/intel_sprite.c  | 14 +
> >  4 files changed, 71 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f0f8f6059652..ecd6b236e005 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6263,7 +6263,7 @@ enum {
> >  #define _PLANE_CTL_2_A 0x70280
> >  #define _PLANE_CTL_3_A 0x70380
> >  #define   PLANE_CTL_ENABLE (1 << 31)
> > -#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
> > +#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK 
> > */
> >  #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
> >  #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
> >  #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
> > @@ -6273,7 +6273,7 @@ enum {
> >  #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
> >  #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
> >  #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
> > -#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
> > +#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
> >  #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
> > @@ -6286,13 +6286,13 @@ enum {
> >  #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
> >  #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
> >  #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
> > -#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
> > +#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
> >  #define   PLANE_CTL_TILED_MASK (0x7 << 10)
> >  #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
> >  #define   PLANE_CTL_TILED_X(  1 << 10)
> >  #define   PLANE_CTL_TILED_Y(  4 << 10)
> >  #define   PLANE_CTL_TILED_YF   (  5 << 10)
> > -#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
> > +#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> >  #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
> >  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
> >  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
> > @@ -6332,6 +6332,10 @@ enum {
> >  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
> >  #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
> >  #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
> > +#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
> > +#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
> > +#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
> > +#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
> >  #define _PLANE_BUF_CFG_1_A 0x7027c
> >  #define _PLANE_BUF_CFG_2_A 0x7037c
> >  #define _PLANE_NV12_BUF_CFG_1_A0x70278
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 737de251d0f8..39453276dad1 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3466,6 +3466,23 @@ static u32 skl_plane_ctl_format(uint32_t 
> > pixel_format)
> > return 0;
> >  }
> >  
> > +static u32 glk_plane_ctl_format(uint32_t pixel_format)
> > +{
> > +   /* GLK+ moves the alpha mask to a different register */
> > +   return skl_plane_ctl_format(pixel_format) & ~PLANE_CTL_ALPHA_MASK;
> 
> I think it would be less confusing to extract the alpha stuff
> from skl_plane_ctl_format() into skl_plane_ctl_alpha().
> 
> I guess with that we wouldn't even need glk_plane_ctl_format()?

Yeah, I like that better. As a matter of fact, the mask and definitions
are the same between PLANE_CTL and PLANE_COLOR_CTL - would it be cleaner
to just rename the defines to PLANE_ALPHA_*, name the function
skl_plane_alpha, and then be able to use the single

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Stop caching the "golden" renderstate

2017-11-03 Thread Rodrigo Vivi

On Fri, Nov 03, 2017 at 08:39:21AM +, Joonas Lahtinen wrote:
> On Thu, 2017-11-02 at 16:34 -0700, Rodrigo Vivi wrote:
> > On Thu, Nov 02, 2017 at 10:36:26PM +, Oscar Mateo wrote:
> > > 
> > > 
> > > On 11/02/2017 07:56 AM, Joonas Lahtinen wrote:
> > > > On Thu, 2017-11-02 at 07:54 -0700, Rodrigo Vivi wrote:
> > > > > On Thu, Nov 02, 2017 at 02:43:16PM +, Joonas Lahtinen wrote:
> > > > > > On Thu, 2017-11-02 at 12:42 +, Chris Wilson wrote:
> > > > > > > As we now record the default HW state and so only emit the 
> > > > > > > "golden"
> > > > > > > renderstate once to prepare the HW, there is no advantage in 
> > > > > > > keeping the
> > > > > > > renderstate batch around as it will never be used again.
> > > > > 
> > > > > So, with this in place we really don't need that null context for CNL.
> > > > > to fullfill all Mesa needs, right?!
> > > > 
> > > > Separate issue, this only fixes isolation. This patch just releases it
> > > > from memory after it's been applied to the default context states to be
> > > > stored.
> > > > 
> > > > But yes, we also decided not to have null context for new platforms.
> > > 
> > > At last until, two years from now, we find out that there is a very subtle
> > > reason why we need it :)
> > 
> > :( - Yeap, for me just to be on the safe side and start with a clean context
> > would be a good reason already...
> 
> Indeed, we are starting with a clean context now. If the HW division
> messes a new design so badly that it won't be able to execute without
> null render state, we shall reiterate :) But I have high hopes that we
> don't need to.

Well, yeah!
That makes sense and also it makes the platform enabling easier.
Thanks for the work and explanations.

> 
> Regards, Joonas
> -- 
> Joonas Lahtinen
> Open Source Technology Center
> Intel Corporation
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Re: [Intel-gfx] Pushing commits to drm-intel-next-queued and questions about CI

2017-11-03 Thread Rodrigo Vivi

Hi Hans,

On Fri, Nov 03, 2017 at 10:41:55AM +, Hans de Goede wrote:
> Hi Daniel,
> 
> A while ago I was granted commit rights to the drm-intel repo.
> So far I've not used these, but since no-one seems to be
> pushing these 2 sets, I guess now might be a good time to
> learn how to push things myself.
> 
> I'm talking about these 2 patch-sets:
> 
> https://patchwork.freedesktop.org/series/32274/

For this one we got the ack from Ingo, but I missed the reviewed-by
on the second one that is the i915 part of it.
Do we need it or just that ack was enough for both patches?

> https://patchwork.freedesktop.org/series/32288/
> 
> Both have all the necessary reviews, etc.
> 
> The first series triggers some new warnings in Fi.CI.IGT,
> looking at the history of the tests triggering new warnings,
> e.g. I see a "new" warning on kbl in:
> https://intel-gfx-ci.01.org/tree/drm-tip/igt@kms_b...@extended-modeset-hang-oldfb-render-a.html
> it seems that some tests simply sometimes trigger some warnings,
> if that is the case can I ignore these ?

Ideally it is good to retest. CI is getting better day by day.
So if you run today and it was yesterday's false positive it will
probably not be there anymore.

> 
> Also it seems that the 3261 tip chosen to run the tests against
> was a poor one according to the per test histories many
> tests were skipped against it. How can I reschedule tests?

Or someone with patchwork admin can do that for you
or you need to resend the series... but...

> 
> Likewise the 2nd patchset failed 1 test in
> Fi.CI.BAT, which seems unrelated to the patch-set.

... I just triggered both retests for you here...

> 
> This means the other tests never ran, so I guess
> I should reschedule the tests for this set.
> 
> Given that all the patches have been reviewed and acked can
> I simply push these to drm-intel-next-queued once the
> tests results are sorted out?

If you have permission and if you are follow the guidelines
and docs, you know what you are doing ;)

Thanks,
Rodrigo.

> 
> Regards,
> 
> Hans
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Ville Syrjälä

On Fri, Nov 03, 2017 at 05:08:07PM +, Chris Wilson wrote:
> Quoting Patchwork (2017-11-03 17:05:20)
> > == Series Details ==
> > 
> > Series: drm/i915: Move init_clock_gating() back to where it was
> > URL   : https://patchwork.freedesktop.org/series/33124/
> > State : failure
> > 
> > == Summary ==
> > 
> > Series 33124v1 drm/i915: Move init_clock_gating() back to where it was
> > https://patchwork.freedesktop.org/api/1.0/series/33124/revisions/1/mbox/
> > 
> > Test chamelium:
> > Subgroup dp-crc-fast:
> > pass   -> FAIL   (fi-kbl-7500u) fdo#102514
> > Test gem_exec_reloc:
> > Subgroup basic-write-gtt-active:
> > fail   -> PASS   (fi-gdg-551) fdo#102582
> > Test kms_busy:
> > Subgroup basic-flip-b:
> > fail   -> PASS   (fi-bwr-2160)
> > pass   -> INCOMPLETE (fi-hsw-4770r)
> > Subgroup basic-flip-c:
> > pass   -> INCOMPLETE (fi-hsw-4770)
> 
> Darn persistent. Third time lucky?

Let's find out.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

2017-11-03 Thread Ville Syrjälä

On Fri, Nov 03, 2017 at 09:58:48AM -0700, James Ausmus wrote:
> Since GLK, some plane configuration settings have moved to the
> PLANE_COLOR_CTL register. Refactor handling of the register to work like
> PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
> Mode for GLK+.
> 
> v2: Adjust ordering of platform checks to be newest->oldest, drop
> redundant comment about alpha blending. (Ville)
> 
> Signed-off-by: James Ausmus 
> Cc: Paulo Zanoni 
> Cc: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 12 +---
>  drivers/gpu/drm/i915/intel_display.c | 55 
> 
>  drivers/gpu/drm/i915/intel_drv.h |  5 
>  drivers/gpu/drm/i915/intel_sprite.c  | 14 +
>  4 files changed, 71 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f0f8f6059652..ecd6b236e005 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6263,7 +6263,7 @@ enum {
>  #define _PLANE_CTL_2_A   0x70280
>  #define _PLANE_CTL_3_A   0x70380
>  #define   PLANE_CTL_ENABLE   (1 << 31)
> -#define   PLANE_CTL_PIPE_GAMMA_ENABLE(1 << 30)
> +#define   PLANE_CTL_PIPE_GAMMA_ENABLE(1 << 30)   /* Pre-GLK 
> */
>  #define   PLANE_CTL_FORMAT_MASK  (0xf << 24)
>  #define   PLANE_CTL_FORMAT_YUV422(  0 << 24)
>  #define   PLANE_CTL_FORMAT_NV12  (  1 << 24)
> @@ -6273,7 +6273,7 @@ enum {
>  #define   PLANE_CTL_FORMAT_AYUV  (  8 << 24)
>  #define   PLANE_CTL_FORMAT_INDEXED   ( 12 << 24)
>  #define   PLANE_CTL_FORMAT_RGB_565   ( 14 << 24)
> -#define   PLANE_CTL_PIPE_CSC_ENABLE  (1 << 23)
> +#define   PLANE_CTL_PIPE_CSC_ENABLE  (1 << 23) /* Pre-GLK */
>  #define   PLANE_CTL_KEY_ENABLE_MASK  (0x3 << 21)
>  #define   PLANE_CTL_KEY_ENABLE_SOURCE(  1 << 21)
>  #define   PLANE_CTL_KEY_ENABLE_DESTINATION   (  2 << 21)
> @@ -6286,13 +6286,13 @@ enum {
>  #define   PLANE_CTL_YUV422_VYUY  (  3 << 16)
>  #define   PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
>  #define   PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> -#define   PLANE_CTL_PLANE_GAMMA_DISABLE  (1 << 13)
> +#define   PLANE_CTL_PLANE_GAMMA_DISABLE  (1 << 13) /* Pre-GLK */
>  #define   PLANE_CTL_TILED_MASK   (0x7 << 10)
>  #define   PLANE_CTL_TILED_LINEAR (  0 << 10)
>  #define   PLANE_CTL_TILED_X  (  1 << 10)
>  #define   PLANE_CTL_TILED_Y  (  4 << 10)
>  #define   PLANE_CTL_TILED_YF (  5 << 10)
> -#define   PLANE_CTL_ALPHA_MASK   (0x3 << 4)
> +#define   PLANE_CTL_ALPHA_MASK   (0x3 << 4) /* Pre-GLK */
>  #define   PLANE_CTL_ALPHA_DISABLE(  0 << 4)
>  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY (  2 << 4)
>  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY (  3 << 4)
> @@ -6332,6 +6332,10 @@ enum {
>  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE  (1 << 30)
>  #define   PLANE_COLOR_PIPE_CSC_ENABLE(1 << 23)
>  #define   PLANE_COLOR_PLANE_GAMMA_DISABLE(1 << 13)
> +#define   PLANE_COLOR_ALPHA_MASK (0x3 << 4)
> +#define   PLANE_COLOR_ALPHA_DISABLE  (0 << 4)
> +#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY   (2 << 4)
> +#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY   (3 << 4)
>  #define _PLANE_BUF_CFG_1_A   0x7027c
>  #define _PLANE_BUF_CFG_2_A   0x7037c
>  #define _PLANE_NV12_BUF_CFG_1_A  0x70278
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 737de251d0f8..39453276dad1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3466,6 +3466,23 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>   return 0;
>  }
>  
> +static u32 glk_plane_ctl_format(uint32_t pixel_format)
> +{
> + /* GLK+ moves the alpha mask to a different register */
> + return skl_plane_ctl_format(pixel_format) & ~PLANE_CTL_ALPHA_MASK;

I think it would be less confusing to extract the alpha stuff
from skl_plane_ctl_format() into skl_plane_ctl_alpha().

I guess with that we wouldn't even need glk_plane_ctl_format()?

> +}
> +
> +static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
> +{
> + switch (pixel_format) {
> + case DRM_FORMAT_ABGR:
> + case DRM_FORMAT_ARGB:
> + return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
> + default:
> + return PLANE_COLOR_ALPHA_DISABLE;
> + }
> +}
> +
>  static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
>  {
>   switch (fb_modifier) {
> @@ -3522,14 +3539,16 @@ u32 skl_plane_ctl(const struct

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+ (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+ (rev2)
URL   : https://patchwork.freedesktop.org/series/33087/
State : success

== Summary ==

Series 33087v2 drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+
https://patchwork.freedesktop.org/api/1.0/series/33087/revisions/2/mbox/

Test gem_exec_reloc:
Subgroup basic-cpu-active:
pass   -> FAIL   (fi-gdg-551) fdo#102582 +4
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:446s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:453s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:540s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:506s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:503s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:504s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:494s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:565s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:174  dwarn:1   dfail:0   fail:5   skip:109 
time:261s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:584s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:430s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:426s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:499s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:490s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:576s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:482s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:588s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:573s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:653s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:520s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:460s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:584s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:424s

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
3f6947568e46 drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6945/
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Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake

2017-11-03 Thread Srivatsa, Anusha



>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Daniel Stone
>Sent: Friday, November 3, 2017 6:40 AM
>To: Pandiyan, Dhinakaran 
>Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo 
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake
>
>Hi,
>
>On 2 November 2017 at 18:04, Pandiyan, Dhinakaran
> wrote:
>> On Thu, 2017-11-02 at 07:27 -0700, Rodrigo Vivi wrote:
>>> That's intentional. The idea is to send to linux-firmware only after
>>> it passes our CI. So, prepare already in a way that it is easy to
>>> just forward when that happens.
>>>
>>> But what I believe we can change is to send that in the cover-letter
>>> of the series.
>>> So cover-letter with pull-request that CI would get automatically,
>>> all related patches on the series, so right now it could be:
>>> patch 0: pull-request
>>> patch 1: kbl dmc 1.04
>>> patch 2: skl dmc 1.27
>> This patch updates only KBL firmware. Is there an upcoming 1.27
>> release for SKL?
>
>If there is, it hasn't yet made it to 01.org either.

Daniel,
The plan is to release the firmware to 01.org once we get ack from CI. Once we 
get ack, I will also send pull request to linux-firmware.

I actually need your help in setting up a shared repo on freedesktop from where 
I can send pull requests I am currently doing that through my private 
github account. 

Regards,
Anusha
>Cheers,
>Daniel
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Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/guc : Removing i915_modparams.enable_guc_loading module

2017-11-03 Thread Rodrigo Vivi

On Fri, Nov 03, 2017 at 08:36:01AM +, Joonas Lahtinen wrote:
> On Fri, 2017-11-03 at 00:03 +, Chris Wilson wrote:
> > Quoting Rodrigo Vivi (2017-11-02 23:52:45)
> > > On Wed, Oct 4, 2017 at 6:07 AM, Joonas Lahtinen
> > >  wrote:
> > > > On Tue, 2017-10-03 at 15:56 -0700, Sujaritha Sundaresan wrote:
> > > > > We currently have two module parameters that control GuC: 
> > > > > "enable_guc_loading" and "enable_guc_submission".
> > > > > Whenever we need i915_modparams.enable_guc_submission=1, we also need 
> > > > > enable_guc_loading=1.
> > > > > We also need enable_guc_loading=1 when we want to verify the HuC,
> > > > > which is every time we have a HuC (but all platforms with HuC have a 
> > > > > GuC and viceversa).
> > > > 
> > > > Long lines in commit message, please give a look at:
> > > > 
> > > > https://www.kernel.org/doc/html/v4.13/process/submitting-patches.html
> > > > 
> > > > Section "14) The canonical patch format".
> > > > 
> > > > Then, about the patch. I think the commit message should be more clear
> > > > about the fact that if we have HuC firmware to be loaded, we need to
> > > > have GuC to actually load it. So if an user wants to avoid the GuC from
> > > > getting loaded, they must not have a HuC firmware to be loaded, in
> > > > addition to not using GuC submission.
> > > > 
> > > > > 
> > > > > v2: Clarifying the commit message (Anusha)
> > > > > 
> > > > > v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
> > > > > 
> > > > > v4: Rebase
> > > > > 
> > > > > v5: Separating message unification into a separate patch
> > > > > 
> > > > > Cc: Michal Wajdeczko 
> > > > > Cc: Anusha Srivatsa 
> > > > > Cc: Oscar Mateo 
> > > > > Cc: Sagar Arun Kamble 
> > > > > Signed-off-by: Sujaritha Sundaresan 
> > > > 
> > > > Try to keep the tags in chronological order, so start with Suggested-
> > > > by: (if any), Signed-off-by:, Cc: and so on.
> > > 
> > > Could we agree on have
> > > Suggested-by:
> > > Cc:
> > > Signed-off-by:
> > > as the initial chronological order and then follow the chronological
> > 
> > But CCs come after a s-o-b, because they are added after the commit. (I
> > write some code, then think who might be interested; usually by looking
> > at who previously worked on the same code). Then you also add new CCs
> > later on based on review feedback; a comment on v1 gets a CC on v2.
> > Bugzilla/reported-by/suggested-by are before since they presumably
> > prompted the commit to be written in the first place (plus also they
> > deserve extra credit for their effort in alerting us to the issue).
> 
> Yeah, this is my reasoning too.

So it seems the chronological order differs from case to case
from person to person.
When I write a patch most of the times I have people in mind
that I will cc. Like when I'm writing an email.
cc: people that touch this code from last time
cc: people that can help on review
cc: people that introduced this error
cc: people that will be futurely impacted by this change

and then I sign-off on the end of the patch as I sign off in the
end of a message.

> 
> Also, when you add the machine assistance from Patchwork to
> automatically spread tags from the cover letter (Acked-by, Reviewed-by
> etc. and it's in the works, I understand). I don't quite see why we
> would have only a portion of the tags in chronological order.
> 
> If I respin a patch, it might already have:
> 
> Bugzilla:
> Suggested-by:
> Signed-off-by:
> Cc:
> Cc:
> Acked-by:
> Reviewed-by:

I really would like to have something like:

Bugzilla:
Suggested-by:
Cc:
Cc:
Signed-off-by:
Acked-by:
Reviewed-by:

This seems to be the most used in kernel.
the most intuitive and the easier to read.

The worst case this approach is creating is

Signed-off:
Cc:
Cc:
Cc:

really ugly on the first patch imho.

So, I doubt we can reach to an agreement. So let's
agree at least in not enforce this chronological thing
as a rule and let people use what ever they feel better.

Specially because I don't see any other place where
this is trying to get enforced like this.

Thanks
Signed-off: Rodrigo.

> 
> By adding my Signed-off-by at the end and that's the only way to retain
> that history information correctly.
> 
> And it's an easy convention to follow for a developer. You only need to
> to write above the automatically generated S-o-b, if you reference a
> bug or attribute credit (because that's literally what happened first
> in chronological order, too). From then on, you just append at the end.
> 
> All the minutes spent thinking how to correctly order the tags can be
> recouped as moar patches.
> 
> Regards, Joonas
> -- 
> Joonas Lahtinen
> Open Source Technology Center
> Intel Corporation
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Chris Wilson

Quoting Patchwork (2017-11-03 17:05:20)
> == Series Details ==
> 
> Series: drm/i915: Move init_clock_gating() back to where it was
> URL   : https://patchwork.freedesktop.org/series/33124/
> State : failure
> 
> == Summary ==
> 
> Series 33124v1 drm/i915: Move init_clock_gating() back to where it was
> https://patchwork.freedesktop.org/api/1.0/series/33124/revisions/1/mbox/
> 
> Test chamelium:
> Subgroup dp-crc-fast:
> pass   -> FAIL   (fi-kbl-7500u) fdo#102514
> Test gem_exec_reloc:
> Subgroup basic-write-gtt-active:
> fail   -> PASS   (fi-gdg-551) fdo#102582
> Test kms_busy:
> Subgroup basic-flip-b:
> fail   -> PASS   (fi-bwr-2160)
> pass   -> INCOMPLETE (fi-hsw-4770r)
> Subgroup basic-flip-c:
> pass   -> INCOMPLETE (fi-hsw-4770)

Darn persistent. Third time lucky?
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: Move init_clock_gating() back to where it was
URL   : https://patchwork.freedesktop.org/series/33124/
State : failure

== Summary ==

Series 33124v1 drm/i915: Move init_clock_gating() back to where it was
https://patchwork.freedesktop.org/api/1.0/series/33124/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
pass   -> INCOMPLETE (fi-hsw-4770r)
Subgroup basic-flip-c:
pass   -> INCOMPLETE (fi-hsw-4770)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:441s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:456s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:380s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:279s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:504s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:504s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:504s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:485s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:265s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:584s
fi-hsw-4770  total:208  pass:188  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:207  pass:187  dwarn:0   dfail:0   fail:0   skip:19 
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:428s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:505s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:460s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:477s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:572s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:589s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:571s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:592s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:654s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:516s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:459s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:568s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:426s
fi-cfl-s failed to connect after reboot

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
0c75534fbce0 drm/i915: Move init_clock_gating() back to where it was

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6944/
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Re: [Intel-gfx] [PATCH] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

2017-11-03 Thread James Ausmus

On Fri, Nov 03, 2017 at 12:12:09PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 02, 2017 at 04:00:49PM -0700, James Ausmus wrote:
> > Since GLK, some plane configuration settings have moved to the
> > PLANE_COLOR_CTL register. Refactor handling of the register to work like
> > PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
> > Mode for GLK+.
> > 
> > Signed-off-by: James Ausmus 
> > Cc: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 12 +---
> >  drivers/gpu/drm/i915/intel_display.c | 60 
> > +---
> >  drivers/gpu/drm/i915/intel_drv.h |  5 +++
> >  drivers/gpu/drm/i915/intel_sprite.c  | 14 +
> >  4 files changed, 76 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 68a58cce6ab1..520ff9a15222 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6263,7 +6263,7 @@ enum {
> >  #define _PLANE_CTL_2_A 0x70280
> >  #define _PLANE_CTL_3_A 0x70380
> >  #define   PLANE_CTL_ENABLE (1 << 31)
> > -#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
> > +#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK 
> > */
> >  #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
> >  #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
> >  #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
> > @@ -6273,7 +6273,7 @@ enum {
> >  #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
> >  #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
> >  #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
> > -#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
> > +#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
> >  #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
> > @@ -6286,13 +6286,13 @@ enum {
> >  #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
> >  #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
> >  #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
> > -#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
> > +#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
> >  #define   PLANE_CTL_TILED_MASK (0x7 << 10)
> >  #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
> >  #define   PLANE_CTL_TILED_X(  1 << 10)
> >  #define   PLANE_CTL_TILED_Y(  4 << 10)
> >  #define   PLANE_CTL_TILED_YF   (  5 << 10)
> > -#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
> > +#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> >  #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
> >  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
> >  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
> > @@ -6332,6 +6332,10 @@ enum {
> >  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
> >  #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
> >  #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
> > +#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
> > +#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
> > +#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
> > +#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
> >  #define _PLANE_BUF_CFG_1_A 0x7027c
> >  #define _PLANE_BUF_CFG_2_A 0x7037c
> >  #define _PLANE_NV12_BUF_CFG_1_A0x70278
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index e2ac976844d8..0883e857dda9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3466,6 +3466,29 @@ static u32 skl_plane_ctl_format(uint32_t 
> > pixel_format)
> > return 0;
> >  }
> >  
> > +static u32 glk_plane_ctl_format(uint32_t pixel_format)
> > +{
> > +   /* GLK+ moves the alpha mask to a different register */
> > +   return skl_plane_ctl_format(pixel_format) & ~PLANE_CTL_ALPHA_MASK;
> > +}
> > +
> > +static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
> > +{
> > +   switch (pixel_format) {
> > +   /*
> > +* XXX: For ARBG/ABGR formats we default to expecting scanout buffers
> > +* to be already pre-multiplied. We need to add a knob (or a different
> > +* DRM_FORMAT) for user-space to configure that.
> > +*/
> 
> Why is this comment getting added to the glk function? It's a generic
> issue that affects all platforms with alpha blending.

Copy-pasta from the skl_plane_ctl_format function - I'll drop it.

Thanks for the review!

-James

> 
> > +   case DRM_FORMAT_ABGR:
> > +

[Intel-gfx] [PATCH v2] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

2017-11-03 Thread James Ausmus

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

Signed-off-by: James Ausmus 
Cc: Paulo Zanoni 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 +---
 drivers/gpu/drm/i915/intel_display.c | 55 
 drivers/gpu/drm/i915/intel_drv.h |  5 
 drivers/gpu/drm/i915/intel_sprite.c  | 14 +
 4 files changed, 71 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0f8f6059652..ecd6b236e005 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6263,7 +6263,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6273,7 +6273,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6286,13 +6286,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6332,6 +6332,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..39453276dad1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3466,6 +3466,23 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return 0;
 }
 
+static u32 glk_plane_ctl_format(uint32_t pixel_format)
+{
+   /* GLK+ moves the alpha mask to a different register */
+   return skl_plane_ctl_format(pixel_format) & ~PLANE_CTL_ALPHA_MASK;
+}
+
+static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
+{
+   switch (pixel_format) {
+   case DRM_FORMAT_ABGR:
+   case DRM_FORMAT_ARGB:
+   return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
+   default:
+   return PLANE_COLOR_ALPHA_DISABLE;
+   }
+}
+
 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
 {
switch (fb_modifier) {
@@ -3522,14 +3539,16 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
 
plane_ctl = PLANE_CTL_ENABLE;
 
-   if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+   plane_ctl |= glk_plane_ctl_format(fb->format->format);
+   } else {
plane_ctl |=
PLANE_CTL_PIPE_GAMMA_ENABLE |

Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake

2017-11-03 Thread Srivatsa, Anusha



>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Daniel Stone
>Sent: Friday, November 3, 2017 6:40 AM
>To: Pandiyan, Dhinakaran 
>Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo 
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake
>
>Hi,
>
>On 2 November 2017 at 18:04, Pandiyan, Dhinakaran
> wrote:
>> On Thu, 2017-11-02 at 07:27 -0700, Rodrigo Vivi wrote:
>>> That's intentional. The idea is to send to linux-firmware only after
>>> it passes our CI. So, prepare already in a way that it is easy to
>>> just forward when that happens.
>>>
>>> But what I believe we can change is to send that in the cover-letter
>>> of the series.
>>> So cover-letter with pull-request that CI would get automatically,
>>> all related patches on the series, so right now it could be:
>>> patch 0: pull-request
>>> patch 1: kbl dmc 1.04
>>> patch 2: skl dmc 1.27
>> This patch updates only KBL firmware. Is there an upcoming 1.27
>> release for SKL?

1.27 to be sent out to public soon.

Anusha 
>If there is, it hasn't yet made it to 01.org either.
>
>Cheers,
>Daniel
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Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add RGB565 90 degree test for gen>9

2017-11-03 Thread Ville Syrjälä

On Fri, Nov 03, 2017 at 04:26:30PM +0200, Juha-Pekka Heikkila wrote:
> Gen10 onwards 90 and 270 degree rotations are supported for RGB565 format.
> 
> Signed-off-by: Juha-Pekka Heikkila 
> ---
>  tests/kms_rotation_crc.c | 30 +++---
>  1 file changed, 27 insertions(+), 3 deletions(-)
> 
> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
> index 27d1f80..f22bcb5 100644
> --- a/tests/kms_rotation_crc.c
> +++ b/tests/kms_rotation_crc.c
> @@ -423,11 +423,10 @@ static void test_plane_rotation(data_t *data, int 
> plane_type)
>  
>  static void test_plane_rotation_ytiled_obj(data_t *data,
>  igt_output_t *output,
> -int plane_type)
> +int plane_type, uint32_t format)
>  {
>   igt_display_t *display = >display;
>   uint64_t tiling = LOCAL_I915_FORMAT_MOD_Y_TILED;
> - uint32_t format = DRM_FORMAT_XRGB;
>   int bpp = igt_drm_format_to_bpp(format);
>   enum igt_commit_style commit = COMMIT_LEGACY;
>   int fd = data->gfx_fd;
> @@ -709,6 +708,29 @@ igt_main
>   test_plane_rotation(, DRM_PLANE_TYPE_PRIMARY);
>   }
>  
> + igt_subtest_f("primary-rotation-90-Y-tiled-16bpp") {
> + enum pipe pipe;
> + igt_output_t *output;
> + int valid_tests = 0;
> +
> + igt_require(gen > 9);
> + data.rotation = IGT_ROTATION_90;
> +
> + for_each_pipe_with_valid_output(, pipe, output) {
> + igt_output_set_pipe(output, pipe);
> +
> + test_plane_rotation_ytiled_obj(, output,
> +DRM_PLANE_TYPE_PRIMARY,
> +DRM_FORMAT_RGB565);

This will fail on pre-gen10, so you'll need to adjust something else as
well. Also you'll want to change the bad-format test to use maybe C8.

Looks like kms_rotation_crc as a whole could use some refactoring.
I don't understand why we have test_plane_rotation() and
test_plane_rotation_ytiled_obj(). One function really should be
enough.

> +
> + valid_tests++;
> + break;
> + }
> +
> + igt_require_f(valid_tests,
> +   "no valid crtc/connector combinations found\n");
> + }
> +
>   igt_subtest_f("primary-rotation-90-Y-tiled") {
>   enum pipe pipe;
>   igt_output_t *output;
> @@ -720,7 +742,9 @@ igt_main
>   for_each_pipe_with_valid_output(, pipe, output) {
>   igt_output_set_pipe(output, pipe);
>  
> - test_plane_rotation_ytiled_obj(, output, 
> DRM_PLANE_TYPE_PRIMARY);
> + test_plane_rotation_ytiled_obj(, output,
> +DRM_PLANE_TYPE_PRIMARY,
> +DRM_FORMAT_XRGB);
>  
>   valid_tests++;
>   break;
> -- 
> 2.7.4
> 
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-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL

2017-11-03 Thread Sagar Arun Kamble




On 11/3/2017 8:48 PM, Michal Wajdeczko wrote:

We can program GUC_SHIM_CONTROL register with all expected
bits without use of extra macro defined in fwif.h

v2: rebased without pre-prod code
v3: fixed typo

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 

Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/i915_guc_reg.h | 7 ---
  drivers/gpu/drm/i915/intel_guc_fw.c | 9 +++--
  2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 35cf991..bc1ae7d 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -102,13 +102,6 @@
  #define   GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
  #define   GUC_GEN10_SHIM_WC_ENABLE(1<<21)
  
-#define GUC_SHIM_CONTROL_VALUE	(GUC_DISABLE_SRAM_INIT_TO_ZEROES	| \

-GUC_ENABLE_READ_CACHE_LOGIC| \
-GUC_ENABLE_MIA_CACHING | \
-GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA| \
-GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA   | \
-GUC_ENABLE_MIA_CLOCK_GATING)
-
  #define GUC_SEND_INTERRUPT_MMIO(0xc4c8)
  #define   GUC_SEND_TRIGGER  (1<<0)
  
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c

index a63b5cf..69ba015 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -101,8 +101,13 @@ static void guc_prepare_xfer(struct intel_guc *guc)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
  
-	/* Enable MIA caching. GuC clock gating is disabled. */

-   I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
+   /* Must program this register before loading the ucode with DMA */
+   I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+GUC_ENABLE_READ_CACHE_LOGIC |
+GUC_ENABLE_MIA_CACHING |
+GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
+GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
+GUC_ENABLE_MIA_CLOCK_GATING);
  
  	if (IS_GEN9_LP(dev_priv))

I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);


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Re: [Intel-gfx] [PATCH v4 3/5] drm/i915/guc: Drop legacy workarounds from guc_prepare_xfer

2017-11-03 Thread Sagar Arun Kamble




On 11/3/2017 8:48 PM, Michal Wajdeczko wrote:

We don't keep the workarounds for pre-production hardware
(see intel_detect_preproduction_hw) thus we can drop some
extra steps during firmware upload needed only for unsupported
platforms.

Suggested-by: Chris Wilson 
Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 

Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/intel_guc_fw.c | 10 --
  1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 74a61fe..a63b5cf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -104,16 +104,6 @@ static void guc_prepare_xfer(struct intel_guc *guc)
/* Enable MIA caching. GuC clock gating is disabled. */
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
  
-	/* WaDisableMinuteIaClockGating:bxt */

-   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
-   I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
- ~GUC_ENABLE_MIA_CLOCK_GATING));
-   }
-
-   /* WaC6DisallowByGfxPause:bxt */
-   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
-   I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
-
if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
else


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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/kms_rotation_crc: Add RGB565 90 degree test for gen>9

2017-11-03 Thread Patchwork

== Series Details ==

Series: igt/kms_rotation_crc: Add RGB565 90 degree test for gen>9
URL   : https://patchwork.freedesktop.org/series/33132/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c8d1ea24d3bfaf11b223bbe22407aeca196d0d89 tests/debugfs_test: Pretty print 
subdirectories

with latest DRM-Tip kernel build CI_DRM_3312
de359919ae46 drm-tip: 2017y-11m-03d-14h-00m-37s UTC integration manifest

Testlist changes:
+igt@kms_rotation_crc@primary-rotation-90-Y-tiled-16bpp

Test gem_exec_flush:
Subgroup basic-wb-set-default:
incomplete -> PASS   (fi-glk-dsi)
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:446s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:460s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:383s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:551s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:507s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:512s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:489s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:556s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:616s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:434s
fi-gdg-551   total:289  pass:177  dwarn:1   dfail:0   fail:2   skip:109 
time:263s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:588s
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:497s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:433s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:431s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:429s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:498s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:498s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:577s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:597s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:576s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:654s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:523s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:506s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:464s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:582s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:420s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_475/
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable 16bpp 90/270 plane rotation for gen10 onwards.

2017-11-03 Thread Ville Syrjälä

On Fri, Nov 03, 2017 at 04:37:58PM +0200, Juha-Pekka Heikkila wrote:
> From gen10 onwards 16bpp 90/270 rotation is supported on hardware.
> 
> Signed-off-by: Juha-Pekka Heikkila 
> Testcase: https://patchwork.freedesktop.org/patch/186179/
> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 17 -
>  1 file changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 6c4c82e2d..502d27a 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -107,7 +107,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
>   drm_atomic_helper_plane_destroy_state(plane, state);
>  }
>  
> -static bool intel_valid_rotation(const struct drm_plane_state *state)
> +static bool intel_valid_rotation(const struct drm_plane_state *state,
> +  const struct drm_i915_private *dev_priv)
>  {

I wouldn't pass the dev_priv. We can dig it out here, eg:

struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

When we do pass dev_priv, it's usually the first parameter to the
function.

>   struct drm_format_name_buf format_name;
>  
> @@ -118,13 +119,19 @@ static bool intel_valid_rotation(const struct 
> drm_plane_state *state)
>   }
>  
>   /*
> -  * 90/270 is not allowed with RGB64 16:16:16:16,
> -  * RGB 16-bit 5:6:5, and Indexed 8-bit.
> +  * 90/270 is not allowed with RGB64 16:16:16:16 and Indexed 8-bit.
> +  * RGB 16-bit 5:6:5 is allowed gen10 onwards.
>* TBD: Add RGB64 case once its added in supported format list.
>*/
>   switch (state->fb->format->format) {
> - case DRM_FORMAT_C8:
>   case DRM_FORMAT_RGB565:
> + /*
> +  * gen10 onwards supports 16bpp 90/270 rotation
> +  */

This comment looks rather redundant.

> + if (INTEL_GEN(dev_priv) >= 10)
> + break;
> +

+   /* fall through */

I believe we have -Wimplicit-fallthrough now enabled, and I think that
would warn about this w/o the comment if you have a recent enough gcc.

> + case DRM_FORMAT_C8:
>   DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
> drm_get_format_name(state->fb->format->format,
> _name));
> @@ -167,7 +174,7 @@ int intel_plane_atomic_check_with_state(const struct 
> intel_crtc_state *old_crtc_
>   crtc_state->base.enable ? crtc_state->pipe_src_h : 0;
>  
>   if (state->fb && drm_rotation_90_or_270(state->rotation)) {
> - if (!intel_valid_rotation(state))
> + if (!intel_valid_rotation(state, dev_priv))
>   return -EINVAL;
>   }
>  
> -- 
> 2.7.4
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Move 90/270 rotation validity check into its own function

2017-11-03 Thread Ville Syrjälä

On Fri, Nov 03, 2017 at 05:50:17PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 03, 2017 at 04:37:57PM +0200, Juha-Pekka Heikkila wrote:
> > This makes intel_plane_atomic_check_with_state() generally shorter.
> > 
> > Signed-off-by: Juha-Pekka Heikkila 
> > ---
> >  drivers/gpu/drm/i915/intel_atomic_plane.c | 53 
> > +--
> >  1 file changed, 30 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
> > b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index 8e6dc15..6c4c82e2d 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -107,6 +107,35 @@ intel_plane_destroy_state(struct drm_plane *plane,
> > drm_atomic_helper_plane_destroy_state(plane, state);
> >  }
> >  
> > +static bool intel_valid_rotation(const struct drm_plane_state *state)

Oh and please name this parameter 'plane_state'. We're trying to slowly
clean up the mess with inconsistent naming of things.

> > +{
> > +   struct drm_format_name_buf format_name;
> > +
> > +   if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> > +   state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> > +   DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
> > +   return false;
> > +   }
> > +
> > +   /*
> > +* 90/270 is not allowed with RGB64 16:16:16:16,
> > +* RGB 16-bit 5:6:5, and Indexed 8-bit.
> > +* TBD: Add RGB64 case once its added in supported format list.
> > +*/
> > +   switch (state->fb->format->format) {
> > +   case DRM_FORMAT_C8:
> > +   case DRM_FORMAT_RGB565:
> > +   DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
> > + drm_get_format_name(state->fb->format->format,
> > + _name));
> > +   return false;
> > +
> > +   default:
> > +   break;
> > +   }
> 
> Usually there's an empty line after the final return.
> 
> > +   return true;
> > +}
> > +
> >  int intel_plane_atomic_check_with_state(const struct intel_crtc_state 
> > *old_crtc_state,
> > struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state 
> > *old_plane_state,
> > @@ -138,30 +167,8 @@ int intel_plane_atomic_check_with_state(const struct 
> > intel_crtc_state *old_crtc_
> > crtc_state->base.enable ? crtc_state->pipe_src_h : 0;
> >  
> > if (state->fb && drm_rotation_90_or_270(state->rotation)) {
> 
> I'd pull these checks into the new function as well (as an early
> return so that we don't have to needlessly indent the whole
> function body). Otherwise the function name doesn't really match
> the implementation.
> 
> > -   struct drm_format_name_buf format_name;
> > -
> > -   if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> > -   state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> > -   DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
> > +   if (!intel_valid_rotation(state))
> > return -EINVAL;
> > -   }
> > -
> > -   /*
> > -* 90/270 is not allowed with RGB64 16:16:16:16,
> > -* RGB 16-bit 5:6:5, and Indexed 8-bit.
> > -* TBD: Add RGB64 case once its added in supported format list.
> > -*/
> > -   switch (state->fb->format->format) {
> > -   case DRM_FORMAT_C8:
> > -   case DRM_FORMAT_RGB565:
> > -   DRM_DEBUG_KMS("Unsupported pixel format %s for 
> > 90/270!\n",
> > - 
> > drm_get_format_name(state->fb->format->format,
> > - _name));
> > -   return -EINVAL;
> > -
> > -   default:
> > -   break;
> > -   }
> > }
> >  
> > /* CHV ignores the mirror bit when the rotate bit is set :( */
> > -- 
> > 2.7.4
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v4,1/5] drm/i915/guc: Split GuC firmware xfer 
function into clear steps
URL   : https://patchwork.freedesktop.org/series/33135/
State : success

== Summary ==

Series 33135v1 series starting with [v4,1/5] drm/i915/guc: Split GuC firmware 
xfer function into clear steps
https://patchwork.freedesktop.org/api/1.0/series/33135/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-wb-set-default:
incomplete -> PASS   (fi-glk-dsi)
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test gem_sync:
Subgroup basic-many-each:
pass   -> FAIL   (fi-kbl-7567u) fdo#103165
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103165 https://bugs.freedesktop.org/show_bug.cgi?id=103165
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:465s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:379s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:556s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:280s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:516s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:520s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:515s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:491s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:559s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:262s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:586s
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:496s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:434s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:431s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:433s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:500s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:467s
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time:494s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:580s
fi-kbl-7567u total:289  pass:268  dwarn:0   dfail:0   fail:1   skip:20  
time:484s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:587s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:568s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:599s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:655s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:528s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:505s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:466s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:582s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:428s

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
3ecbf3a018bf HAX enable GuC submission for CI
dc2ae4c18fdc drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL
df9e25cc0636 drm/i915/guc: Drop legacy workarounds from guc_prepare_xfer
42cba2806413 drm/i915/guc: Wait for ucode DMA transfer completion
c0b68e0fb242 drm/i915/guc: Split GuC firmware xfer function into clear steps

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6943/
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Move 90/270 rotation validity check into its own function

2017-11-03 Thread Ville Syrjälä

On Fri, Nov 03, 2017 at 04:37:57PM +0200, Juha-Pekka Heikkila wrote:
> This makes intel_plane_atomic_check_with_state() generally shorter.
> 
> Signed-off-by: Juha-Pekka Heikkila 
> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 53 
> +--
>  1 file changed, 30 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 8e6dc15..6c4c82e2d 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -107,6 +107,35 @@ intel_plane_destroy_state(struct drm_plane *plane,
>   drm_atomic_helper_plane_destroy_state(plane, state);
>  }
>  
> +static bool intel_valid_rotation(const struct drm_plane_state *state)
> +{
> + struct drm_format_name_buf format_name;
> +
> + if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> + state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> + DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
> + return false;
> + }
> +
> + /*
> +  * 90/270 is not allowed with RGB64 16:16:16:16,
> +  * RGB 16-bit 5:6:5, and Indexed 8-bit.
> +  * TBD: Add RGB64 case once its added in supported format list.
> +  */
> + switch (state->fb->format->format) {
> + case DRM_FORMAT_C8:
> + case DRM_FORMAT_RGB565:
> + DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
> +   drm_get_format_name(state->fb->format->format,
> +   _name));
> + return false;
> +
> + default:
> + break;
> + }

Usually there's an empty line after the final return.

> + return true;
> +}
> +
>  int intel_plane_atomic_check_with_state(const struct intel_crtc_state 
> *old_crtc_state,
>   struct intel_crtc_state *crtc_state,
>   const struct intel_plane_state 
> *old_plane_state,
> @@ -138,30 +167,8 @@ int intel_plane_atomic_check_with_state(const struct 
> intel_crtc_state *old_crtc_
>   crtc_state->base.enable ? crtc_state->pipe_src_h : 0;
>  
>   if (state->fb && drm_rotation_90_or_270(state->rotation)) {

I'd pull these checks into the new function as well (as an early
return so that we don't have to needlessly indent the whole
function body). Otherwise the function name doesn't really match
the implementation.

> - struct drm_format_name_buf format_name;
> -
> - if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> - state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> - DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
> + if (!intel_valid_rotation(state))
>   return -EINVAL;
> - }
> -
> - /*
> -  * 90/270 is not allowed with RGB64 16:16:16:16,
> -  * RGB 16-bit 5:6:5, and Indexed 8-bit.
> -  * TBD: Add RGB64 case once its added in supported format list.
> -  */
> - switch (state->fb->format->format) {
> - case DRM_FORMAT_C8:
> - case DRM_FORMAT_RGB565:
> - DRM_DEBUG_KMS("Unsupported pixel format %s for 
> 90/270!\n",
> -   
> drm_get_format_name(state->fb->format->format,
> -   _name));
> - return -EINVAL;
> -
> - default:
> - break;
> - }
>   }
>  
>   /* CHV ignores the mirror bit when the rotate bit is set :( */
> -- 
> 2.7.4
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.BAT: success for kms_atomic_transition: Split out modeset tests on internal panels (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: kms_atomic_transition: Split out modeset tests on internal panels (rev2)
URL   : https://patchwork.freedesktop.org/series/33052/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c8d1ea24d3bfaf11b223bbe22407aeca196d0d89 tests/debugfs_test: Pretty print 
subdirectories

with latest DRM-Tip kernel build CI_DRM_3312
de359919ae46 drm-tip: 2017y-11m-03d-14h-00m-37s UTC integration manifest

Testlist changes:
+igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels
+igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels

Test gem_exec_flush:
Subgroup basic-wb-set-default:
incomplete -> PASS   (fi-glk-dsi)
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:446s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:467s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:383s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:552s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:502s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:504s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:507s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:496s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:555s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:427s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:266s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:592s
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:497s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:434s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:425s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:500s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:496s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:578s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:576s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:577s
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time:457s
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time:595s
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time:652s
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time:526s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:510s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:461s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:575s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:434s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_474/
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[Intel-gfx] [PATCH v4 4/5] drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL

2017-11-03 Thread Michal Wajdeczko

We can program GUC_SHIM_CONTROL register with all expected
bits without use of extra macro defined in fwif.h

v2: rebased without pre-prod code
v3: fixed typo

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_guc_reg.h | 7 ---
 drivers/gpu/drm/i915/intel_guc_fw.c | 9 +++--
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 35cf991..bc1ae7d 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -102,13 +102,6 @@
 #define   GUC_ENABLE_MIA_CLOCK_GATING  (1<<15)
 #define   GUC_GEN10_SHIM_WC_ENABLE (1<<21)
 
-#define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES| \
-GUC_ENABLE_READ_CACHE_LOGIC| \
-GUC_ENABLE_MIA_CACHING | \
-GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA| \
-GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA   | \
-GUC_ENABLE_MIA_CLOCK_GATING)
-
 #define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
 #define   GUC_SEND_TRIGGER   (1<<0)
 
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
b/drivers/gpu/drm/i915/intel_guc_fw.c
index a63b5cf..69ba015 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -101,8 +101,13 @@ static void guc_prepare_xfer(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
-   /* Enable MIA caching. GuC clock gating is disabled. */
-   I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
+   /* Must program this register before loading the ucode with DMA */
+   I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+GUC_ENABLE_READ_CACHE_LOGIC |
+GUC_ENABLE_MIA_CACHING |
+GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
+GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
+GUC_ENABLE_MIA_CLOCK_GATING);
 
if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
-- 
2.7.4

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[Intel-gfx] [PATCH v4 3/5] drm/i915/guc: Drop legacy workarounds from guc_prepare_xfer

2017-11-03 Thread Michal Wajdeczko

We don't keep the workarounds for pre-production hardware
(see intel_detect_preproduction_hw) thus we can drop some
extra steps during firmware upload needed only for unsupported
platforms.

Suggested-by: Chris Wilson 
Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_fw.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 74a61fe..a63b5cf 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -104,16 +104,6 @@ static void guc_prepare_xfer(struct intel_guc *guc)
/* Enable MIA caching. GuC clock gating is disabled. */
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 
-   /* WaDisableMinuteIaClockGating:bxt */
-   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
-   I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
- ~GUC_ENABLE_MIA_CLOCK_GATING));
-   }
-
-   /* WaC6DisallowByGfxPause:bxt */
-   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
-   I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
-
if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
else
-- 
2.7.4

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[Intel-gfx] [PATCH v4 5/5] HAX enable GuC submission for CI

2017-11-03 Thread Michal Wajdeczko

Also revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions"

Signed-off-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
 drivers/gpu/drm/i915/i915_params.h  | 4 ++--
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0684d5d..a351ddf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3562,17 +3562,13 @@ int i915_ggtt_enable_hw(struct drm_i915_private 
*dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-   GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
i915->ggtt.invalidate = guc_ggtt_invalidate;
 }
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
-   /* We should only be called after i915_ggtt_enable_guc() */
-   GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
-   i915->ggtt.invalidate = gen6_ggtt_invalidate;
+   if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+   i915->ggtt.invalidate = gen6_ggtt_invalidate;
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c729226..c38cef0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -44,8 +44,8 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc_loading, 0) \
-   param(int, enable_guc_submission, 0) \
+   param(int, enable_guc_loading, 1) \
+   param(int, enable_guc_submission, 1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

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[Intel-gfx] [PATCH v4 2/5] drm/i915/guc: Wait for ucode DMA transfer completion

2017-11-03 Thread Michal Wajdeczko

We silently assumed that DMA transfer will be completed
within assumed timeout and thus we were waiting only at
last step for GuC to become ready. Add intermediate wait
to catch unexpected delays in DMA transfer.

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_fw.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
b/drivers/gpu/drm/i915/intel_guc_fw.c
index c4f4526..74a61fe 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -160,6 +160,8 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct 
i915_vma *vma)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_uc_fw *guc_fw = >fw;
unsigned long offset;
+   u32 status;
+   int ret;
 
/*
 * The header plus uCode will be copied to WOPCM via DMA, excluding any
@@ -182,7 +184,12 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct 
i915_vma *vma)
/* Finally start the DMA */
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 
-   return 0;
+   /* Wait for DMA to finish */
+   ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
+  2, 100, );
+   DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
+
+   return ret;
 }
 
 /*
-- 
2.7.4

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[Intel-gfx] [PATCH v4 1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps

2017-11-03 Thread Michal Wajdeczko

Transfer of GuC firmware requires few steps that currently
are implemented in two large functions. Split this code into
smaller functions to make these steps small and clear.
Also be prepared for potential DMA xfer step failure.

v2: rename function steps (Sagar)

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_fw.c | 172 +---
 1 file changed, 103 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c 
b/drivers/gpu/drm/i915/intel_guc_fw.c
index ef67a36..c4f4526 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -97,23 +97,55 @@ int intel_guc_fw_select(struct intel_guc *guc)
return 0;
 }
 
-/*
- * Read the GuC status register (GUC_STATUS) and store it in the
- * specified location; then return a boolean indicating whether
- * the value matches either of two values representing completion
- * of the GuC boot process.
- *
- * This is used for polling the GuC status in a wait_for()
- * loop below.
- */
-static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
- u32 *status)
+static void guc_prepare_xfer(struct intel_guc *guc)
 {
-   u32 val = I915_READ(GUC_STATUS);
-   u32 uk_val = val & GS_UKERNEL_MASK;
-   *status = val;
-   return (uk_val == GS_UKERNEL_READY ||
-   ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   /* Enable MIA caching. GuC clock gating is disabled. */
+   I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
+
+   /* WaDisableMinuteIaClockGating:bxt */
+   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
+   I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
+ ~GUC_ENABLE_MIA_CLOCK_GATING));
+   }
+
+   /* WaC6DisallowByGfxPause:bxt */
+   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+   I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
+
+   if (IS_GEN9_LP(dev_priv))
+   I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
+   else
+   I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
+
+   if (IS_GEN9(dev_priv)) {
+   /* DOP Clock Gating Enable for GuC clocks */
+   I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
+   I915_READ(GEN7_MISCCPCTL)));
+
+   /* allows for 5us (in 10ns units) before GT can go to RC6 */
+   I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
+   }
+}
+
+/* Copy RSA signature from the fw image to HW for verification */
+static int guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   struct intel_uc_fw *guc_fw = >fw;
+   struct sg_table *sg = vma->pages;
+   u32 rsa[UOS_RSA_SCRATCH_MAX_COUNT];
+   int i;
+
+   if (sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa),
+  guc_fw->rsa_offset) != sizeof(rsa))
+   return -EINVAL;
+
+   for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
+   I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
+
+   return 0;
 }
 
 /*
@@ -122,29 +154,17 @@ static inline bool guc_ucode_response(struct 
drm_i915_private *dev_priv,
  * Architecturally, the DMA engine is bidirectional, and can potentially even
  * transfer between GTT locations. This functionality is left out of the API
  * for now as there is no need for it.
- *
- * Note that GuC needs the CSS header plus uKernel code to be copied by the
- * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
  */
-static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
- struct i915_vma *vma)
+static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
 {
-   struct intel_uc_fw *guc_fw = _priv->guc.fw;
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   struct intel_uc_fw *guc_fw = >fw;
unsigned long offset;
-   struct sg_table *sg = vma->pages;
-   u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
-   int i, ret = 0;
-
-   /* where RSA signature starts */
-   offset = guc_fw->rsa_offset;
 
-   /* Copy RSA signature from the fw image to HW for verification */
-   sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
-   for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
-   I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
-
-   /* The header plus uCode will be copied to WOPCM via DMA, excluding any
-* other components */
+   /*
+* The header plus uCode will be

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: This set enables 90/270 degree rotation on 16bpp planes on gen10

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: This set enables 90/270 degree rotation on 16bpp planes on 
gen10
URL   : https://patchwork.freedesktop.org/series/33133/
State : success

== Summary ==

Series 33133v1 drm/i915: This set enables 90/270 degree rotation on 16bpp 
planes on gen10
https://patchwork.freedesktop.org/api/1.0/series/33133/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-wb-set-default:
incomplete -> PASS   (fi-glk-dsi)
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Subgroup basic-flip-c:
notrun -> INCOMPLETE (fi-glk-dsi)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:449s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:449s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:377s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:549s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:505s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:503s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:505s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:490s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:555s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:428s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:263s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:583s
fi-glk-dsi   total:208  pass:185  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:435s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:426s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:499s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:494s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:575s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:585s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:564s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:600s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:647s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:517s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:454s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:588s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:425s

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
0f5c0cbf06bf drm/i915: Enable 16bpp 90/270 plane rotation for gen10 onwards.
523e634c3ba8 drm/i915: Move 90/270 rotation validity check into its own function

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6942/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v3,1/5] drm/i915/guc: Split GuC firmware xfer 
function into clear steps
URL   : https://patchwork.freedesktop.org/series/33131/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_guc_fw.o
In file included from drivers/gpu/drm/i915/intel_guc_fw.c:31:0:
drivers/gpu/drm/i915/intel_guc_fw.c: In function ‘guc_prepare_xfer’:
drivers/gpu/drm/i915/intel_guc_fw.c:110:37: error: expected ‘)’ before ‘;’ token
  GUC_ENABLE_MIA_CLOCK_GATING;);
 ^
drivers/gpu/drm/i915/i915_drv.h:4224:83: note: in definition of macro 
‘I915_WRITE’
 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, 
(reg), (val), true)

   ^~~
scripts/Makefile.build:313: recipe for target 
'drivers/gpu/drm/i915/intel_guc_fw.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_guc_fw.o] Error 1
scripts/Makefile.build:572: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:572: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:572: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1023: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [Intel-gfx] [PATCH] drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Chris Wilson

Quoting Ville Syrjala (2017-11-03 13:03:37)
> From: Ville Syrjälä 
> 
> Apparently setting up a bunch of GT registers before we've properly
> initialized the rest of the GT hardware leads to these setting being
> lost. So looks like I broke HSW with commit b7048ea12fbb ("drm/i915:
> Do .init_clock_gating() earlier to avoid it clobbering watermarks")
> by doing init_clock_gating() too early. This should actually affect
> other platforms as well, but apparently not to such a great degree.
> 
> What I was ultimately after in that commit was to move the
> ilk_init_lp_watermarks() call earlier. So let's undo the damage and
> move init_clock_gating() back to where it was, and call
> ilk_init_lp_watermarks() just before the watermark state readout.
> 
> This highlights how fragile and messed up our init order really is.
> I wonder why we even initialize the display before gem. The opposite
> order would make much more sense to me...
> 
> Cc: sta...@vger.kernel.org
> Cc: Chris Wilson 
> Cc: Mark Janes 
> Cc: Maarten Lankhorst 
> Cc: Daniel Vetter 
> Cc: Joonas Lahtinen 
> Cc: Oscar Mateo 
> Cc: Mika Kuoppala 
> Reported-by: Mark Janes 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103549
> Fixes: b7048ea12fbb ("drm/i915: Do .init_clock_gating() earlier to avoid it 
> clobbering watermarks")
> References: 
> https://lists.freedesktop.org/archives/intel-gfx/2017-November/145432.html
> Signed-off-by: Ville Syrjälä 

Wrt to the reported CTS regressions, they are fixed.
Tested-by: Chris Wilson 
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3] drm/i915: Define an engine class enum for the uABI (rev2)

2017-11-03 Thread Patchwork

== Series Details ==

Series: series starting with [v3] drm/i915: Define an engine class enum for the 
uABI (rev2)
URL   : https://patchwork.freedesktop.org/series/33126/
State : success

== Summary ==

Series 33126v2 series starting with [v3] drm/i915: Define an engine class enum 
for the uABI
https://patchwork.freedesktop.org/api/1.0/series/33126/revisions/2/mbox/

Test gem_exec_flush:
Subgroup basic-wb-set-default:
incomplete -> PASS   (fi-glk-dsi)
Test gem_exec_reloc:
Subgroup basic-write-gtt-active:
fail   -> PASS   (fi-gdg-551) fdo#102582
Test kms_busy:
Subgroup basic-flip-b:
fail   -> PASS   (fi-bwr-2160)
Test drv_module_reload:
Subgroup basic-no-display:
fail   -> PASS   (fi-hsw-4770r) fdo#103534

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103534 https://bugs.freedesktop.org/show_bug.cgi?id=103534

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:450s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:453s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:381s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:550s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:511s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:507s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:494s
fi-cfl-s total:289  pass:254  dwarn:3   dfail:0   fail:0   skip:32  
time:557s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:261s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:592s
fi-glk-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  
time:491s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:432s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:433s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:425s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:491s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:491s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:573s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:589s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:573s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:655s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:519s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:460s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:570s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:417s

de359919ae463cdaef6bc6890156df84e19dee2a drm-tip: 2017y-11m-03d-14h-00m-37s UTC 
integration manifest
5212a26f9347 drm/i915: Stop caching the "golden" renderstate
487541f6719d drm/i915: Remove redundant intel_autoenable_gt_powersave()
4c78fcebc2a4 drm/i915: Report whether we have true context isolation
f252a2305dc3 drm/i915: Record the default hw state after reset upon load
5a4daa465e8e drm/i915: Mark the context state as dirty/written
221f5015aa7d drm/i915: Inline intel_modeset_gem_init()
412e87887b69 drm/i915: Move GT powersaving init to i915_gem_init()
de4168ba7608 drm/i915: Force the switch to the i915->kernel_context
a695d588d8ed drm/i915: Define an engine class enum for the uABI

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6940/
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Re: [Intel-gfx] [PATCH] drm/i915: Move init_clock_gating() back to where it was

2017-11-03 Thread Chris Wilson

Quoting Ville Syrjälä (2017-11-03 14:20:33)
> On Fri, Nov 03, 2017 at 01:27:55PM +, Chris Wilson wrote:
> > Quoting Ville Syrjala (2017-11-03 13:03:37)
> > > From: Ville Syrjälä 
> > > 
> > > Apparently setting up a bunch of GT registers before we've properly
> > > initialized the rest of the GT hardware leads to these setting being
> > > lost. So looks like I broke HSW with commit b7048ea12fbb ("drm/i915:
> > > Do .init_clock_gating() earlier to avoid it clobbering watermarks")
> > > by doing init_clock_gating() too early. This should actually affect
> > > other platforms as well, but apparently not to such a great degree.
> > > 
> > > What I was ultimately after in that commit was to move the
> > > ilk_init_lp_watermarks() call earlier. So let's undo the damage and
> > > move init_clock_gating() back to where it was, and call
> > > ilk_init_lp_watermarks() just before the watermark state readout.
> > > 
> > > This highlights how fragile and messed up our init order really is.
> > > I wonder why we even initialize the display before gem. The opposite
> > > order would make much more sense to me...
> > 
> > Indeed this will cause some fun for me momentarily as I will have to
> > move init_clock_gating() to i915_gem_init(). We can only wish for that
> > magic wand to be waved sooner.
> > 
> > Does that make sense, or will I have to start carving up
> > init_clock_gating()?
> 
> i915_gem_init() should be fine as far as the display is concerned
> at least, albeit a bit unexpected. Do we need to do that already in
> this patch, or a followup?

After this.

> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 07118c0b69d3..352a6739ed70 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5754,12 +5754,30 @@ void vlv_wm_sanitize(struct drm_i915_private 
> > > *dev_priv)
> > > mutex_unlock(_priv->wm.wm_mutex);
> > >  }
> > >  
> > > +/*
> > > + * FIXME should probably kill this and improve
> > > + * the real watermark readout/sanitation instead
> > > + */
> > > +static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
> > > +{
> > > +   I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
> > > +   I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
> > > +   I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
> > > +
> > > +   /*
> > > +* Don't touch WM1S_LP_EN here.
> > > +* Doing so could cause underruns.
> > > +*/
> > > +}
> > > +
> > >  void ilk_wm_get_hw_state(struct drm_device *dev)
> > >  {
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > struct ilk_wm_values *hw = _priv->wm.hw;
> > > struct drm_crtc *crtc;
> > >  
> > > +   ilk_init_lp_watermarks(dev_priv);
> > 
> > Wasn't expecting this, but the rest lgtm. Could you explain you decision
> > to put it here in a bit more detail?
> 
> The original problem was that this guy turned off the LP1+ watermarks
> after we'd already done the state readout in ilk_wm_get_hw_state(). So
> the state we had read out no longer matched the hardware state.

Ah. Dim light bulb flickers.
 
> To keep the software and hardware states in sync we just need to make
> sure ilk_init_lp_watermarks() is called before the readout. And the
> obvious thing to do then is to call it immediately before to the
> readout.

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Simplify mmio_reg_cmp

2017-11-03 Thread Patchwork

== Series Details ==

Series: drm/i915: Simplify mmio_reg_cmp
URL   : https://patchwork.freedesktop.org/series/33125/
State : success

== Summary ==

Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
dmesg-fail -> FAIL   (shard-hsw) fdo#103375

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2539 pass:1433 dwarn:0   dfail:0   fail:9   skip:1097 
time:9265s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6938/shards.html
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[Intel-gfx] [PATCH 0/2] drm/i915: This set enables 90/270 degree rotation on 16bpp planes on gen10

2017-11-03 Thread Juha-Pekka Heikkila

90/270 16bpp rotation is supported in hadrware from Gen10 onwards. I modified
kms_rotation_crc igt test to test this feature:
https://patchwork.freedesktop.org/patch/186179/

/Juha-Pekka

Juha-Pekka Heikkila (2):
  drm/i915: Move 90/270 rotation validity check into its own function
  drm/i915: Enable 16bpp 90/270 plane rotation for gen10 onwards.

 drivers/gpu/drm/i915/intel_atomic_plane.c | 60 +++
 1 file changed, 37 insertions(+), 23 deletions(-)

-- 
2.7.4

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