Re: [Intel-gfx] [PATCH 0/5] drm: drm_plane_helper_check_state() related stuff

[Daniel Vetter]

On Fri, Nov 10, 2017 at 11:42:59PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 10, 2017 at 01:26:47PM -0800, Sinclair Yeh wrote:
> > Sorry this took so long.
> 
> No worries.
> 
> > 
> > The vmwgfx part:  Reviewed-by: Sinclair Yeh 
> > 
> > I've done some testing and the vmwgfx part looks good.  Has Daniel
> > already taken these or should I put them in my next request?
> 
> You can take them, or I can push them to drm-misc-next. Whatever
> works best for you.
> 
> And I'll want to revisit this topic soonish and move the clip
> handling into the helper as discussed with Daniel. But that can
> wait a bit until we get this round merged somewhere.

Because we're still in the merge window I think it's probably best if we
push the entire series in through drm-misc. Tree-coordination in the merge
window is always a bit a pain.
-Daniel

> 
> > 
> > Sinclair
> > 
> > On Wed, Nov 01, 2017 at 08:29:15PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > > 
> > > While trawling the tree I spotted some issues with the way vmwgfx
> > > uses drm_plane_helper_check_state(). Here's my attempt at fixing it.
> > > Do note that I haven't actually tested the resulting code at all,
> > > but it does build at least.
> > > 
> > > And while touching that general area I took up Daniel's suggestion from
> > > long ago that drm_plane_helper_check_state() should be renamed and
> > > relocated to better reflect its status.
> > > 
> > > Here's a branch with the entire series:
> > > git://github.com/vsyrjala/linux.git atomic_helper_plane_stuff
> > > 
> > > Cc: VMware Graphics 
> > > Cc: Sinclair Yeh 
> > > Cc: Thomas Hellstrom 
> > > Cc: Daniel Vetter 
> > > 
> > > Ville Syrjälä (5):
> > >   drm/vmwgfx: Remove bogus crtc coords vs fb size check
> > >   drm/vmwgfx: Use drm_plane_helper_check_state()
> > >   drm/vmwgfx: Try to fix plane clipping
> > >   drm: Check crtc_state->enable rather than crtc->enabled in
> > > drm_plane_helper_check_state()
> > >   drm: Move drm_plane_helper_check_state() into drm_atomic_helper.c
> > > 
> > >  drivers/gpu/drm/arm/hdlcd_crtc.c|   8 +-
> > >  drivers/gpu/drm/arm/malidp_planes.c |   3 +-
> > >  drivers/gpu/drm/drm_atomic_helper.c |  95 
> > > 
> > >  drivers/gpu/drm/drm_plane_helper.c  | 111 
> > > +++-
> > >  drivers/gpu/drm/drm_simple_kms_helper.c |   9 ++-
> > >  drivers/gpu/drm/i915/intel_display.c|  20 ++---
> > >  drivers/gpu/drm/imx/ipuv3-plane.c   |   8 +-
> > >  drivers/gpu/drm/mediatek/mtk_drm_plane.c|   8 +-
> > >  drivers/gpu/drm/meson/meson_plane.c |   8 +-
> > >  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |   5 +-
> > >  drivers/gpu/drm/nouveau/nv50_display.c  |  18 +++--
> > >  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   6 +-
> > >  drivers/gpu/drm/tegra/dc.c  |   4 +-
> > >  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |  40 --
> > >  drivers/gpu/drm/zte/zx_plane.c  |  15 ++--
> > >  include/drm/drm_atomic_helper.h |   7 ++
> > >  include/drm/drm_plane_helper.h  |   5 --
> > >  17 files changed, 187 insertions(+), 183 deletions(-)
> > > 
> > > -- 
> > > 2.13.6
> > > 
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v2,1/2] drm/i915: Runtime disable for eDP DRRS (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915: Runtime disable for eDP DRRS 
(rev4)
URL   : https://patchwork.freedesktop.org/series/32887/
State : warning

== Summary ==

Series 32887v4 series starting with [v2,1/2] drm/i915: Runtime disable for eDP 
DRRS
https://patchwork.freedesktop.org/api/1.0/series/32887/revisions/4/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test pm_rpm:
Subgroup basic-rte:
pass   -> SKIP   (fi-hsw-4770r)

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:442s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:463s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:379s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:542s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:501s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:497s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:429s
fi-hsw-4770r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:441s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:433s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:457s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:486s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:518s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:535s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:581s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:549s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:573s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:527s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:497s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:460s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:557s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:422s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:607s
fi-glk-dsi   total:156  pass:133  dwarn:0   dfail:0   fail:0   skip:22 

b4da24717364bc69bb981a1536be64413a582f3a drm-tip: 2017y-11m-17d-22h-46m-53s UTC 
integration manifest
6141dfec7eab i915/drrs/debugfs: psr status info addition
3907c7962b59 drm/i915: Runtime disable for eDP DRRS

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7196/
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[Intel-gfx] [PATCH v3] i915/drrs/debugfs: psr status info addition

[Ramalingam C]

From: "C, Ramalingam" 

Existing debugfs entry i915_drrs_status is updated with whether PSR
is the cause for DRRS disabled state.

[v2]: Dropped the module parameter details as ctl moved from module
  parameter to debugfs. [Rodrigo]

[v3]: Crtc ID information is dropped as there is no immediate usecase.
  [Rodrigo].

Signed-off-by: C, Ramalingam 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0c1501fe4c9f..ea36d4e4d881 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3567,7 +3567,10 @@ static void drrs_status_per_crtc(struct seq_file *m,
 
/* disable_drrs() will make drrs->dp NULL */
if (!drrs->dp) {
-   seq_puts(m, "Idleness DRRS: Disabled");
+   seq_puts(m, "Idleness DRRS: Disabled\n");
+   if (dev_priv->psr.enabled)
+   seq_puts(m,
+   "\tAs PSR is enabled, DRRS is not enabled\n");
mutex_unlock(>mutex);
return;
}
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: remove skl_misc_ctl_write handler

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: remove skl_misc_ctl_write handler
URL   : https://patchwork.freedesktop.org/series/34076/
State : success

== Summary ==

Test kms_flip:
Subgroup wf_vblank-vs-modeset-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Subgroup vblank-vs-suspend-interruptible:
pass   -> SKIP   (shard-hsw) fdo#100368
Test drv_selftest:
Subgroup mock_sanitycheck:
pass   -> DMESG-WARN (shard-snb) fdo#103717
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623

fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103717 https://bugs.freedesktop.org/show_bug.cgi?id=103717
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hswtotal:2585 pass:1474 dwarn:1   dfail:1   fail:9   skip:1100 
time:9429s
shard-snbtotal:2585 pass:1260 dwarn:2   dfail:1   fail:11  skip:1311 
time:8086s
Blacklisted hosts:
shard-apltotal:2490 pass:1555 dwarn:2   dfail:0   fail:23  skip:909 
time:12411s
shard-kbltotal:2493 pass:1651 dwarn:4   dfail:0   fail:21  skip:816 
time:10180s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7195/shards.html
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Re: [Intel-gfx] [PATCH v2 2/2] i915/drrs/debugfs: crtc id and psr status

[C, Ramalingam]

> -Original Message-
> From: Vivi, Rodrigo
> Sent: Saturday, November 18, 2017 12:26 AM
> To: C, Ramalingam 
> Cc: Zanoni, Paulo R ; ch...@chris-wilson.co.uk;
> intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 2/2] i915/drrs/debugfs: crtc id and psr 
> status
> 
> On Tue, Nov 07, 2017 at 06:40:08PM +, Ramalingam C wrote:
> > From: "C, Ramalingam" 
> >
> > Existing debugfs entry i915_drrs_status is updated with crtc id and if
> > PSR is cause for DRRS disabled state.
> >
> > [v2]: Dropped the module parameter details as ctl moved from module
> >   parameter to debugfs. [Rodrigo]
> >
> > Signed-off-by: C, Ramalingam 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 7 +--
> >  1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 0c1501fe4c9f..6c2e8346b9a7 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -3567,7 +3567,10 @@ static void drrs_status_per_crtc(struct
> > seq_file *m,
> >
> > /* disable_drrs() will make drrs->dp NULL */
> > if (!drrs->dp) {
> > -   seq_puts(m, "Idleness DRRS: Disabled");
> > +   seq_puts(m, "Idleness DRRS: Disabled\n");
> > +   if (dev_priv->psr.enabled)
> > +   seq_puts(m,
> > +   "\tAs PSR is enabled, DRRS is not enabled\n");
> 
> this seems good...
> 
> > mutex_unlock(>mutex);
> > return;
> > }
> > @@ -3611,7 +3614,7 @@ static int i915_drrs_status(struct seq_file *m, void
> *unused)
> > for_each_intel_crtc(dev, intel_crtc) {
> > if (intel_crtc->base.state->active) {
> > active_crtc_cnt++;
> > -   seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
> > +   seq_printf(m, "\nCRTC %d: ", intel_crtc->base.base.id);
> 
> this seems for a separated patch...
> or at least missing an explanation why...
This changes not needed for debugfs control of drrs. As of now debugfs provides 
the crtc index in the active crtc list. Instead providing the crtc id might 
help to identify the crtc, that the debuginfo is associated to.

Anyway as there is no usecase that need this change, I will remove it from this 
patch.

Thanks
-Ram
> 
> >
> > drrs_status_per_crtc(m, dev, intel_crtc);
> > }
> > --
> > 2.7.4
> >
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: remove skl_misc_ctl_write handler

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: remove skl_misc_ctl_write handler
URL   : https://patchwork.freedesktop.org/series/34076/
State : success

== Summary ==

Series 34076v1 drm/i915/gvt: remove skl_misc_ctl_write handler
https://patchwork.freedesktop.org/api/1.0/series/34076/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:442s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:452s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:382s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:277s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:507s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:490s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:266s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:426s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:437s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:429s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:485s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:532s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:579s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:544s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:565s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:513s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:459s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:569s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:428s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:604s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:494s
fi-byt-n2820 failed to collect. IGT log at Patchwork_7195/fi-byt-n2820/igt.log

b4da24717364bc69bb981a1536be64413a582f3a drm-tip: 2017y-11m-17d-22h-46m-53s UTC 
integration manifest
1d53d6f53a95 drm/i915/gvt: remove skl_misc_ctl_write handler

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7195/
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[Intel-gfx] [PATCH] drm/i915/gvt: remove skl_misc_ctl_write handler

[Weinan Li]

With different settings of compressed data hash mode between VMs and host
may cause gpu issues.

Commit: 1999f108c ("drm/i915/gvt: Disable compression workaround for Gen9")
disable compression workaround of guest in gvt host to align with host.

Commit: 93564044f ("drm/i915: Switch over to the LLC/eLLC hotspot avoidance
hash mode for CCS") add compression workaround, then we can remove the
skl_misc_ctl_write hanlder.

Better solution should be always keeping same settings as host, and bypass
the write request from VMs, but it need to fetch data from host's
"Context".

Cc: Zhi Wang 
Signed-off-by: Weinan Li 
Signed-off-by: Xiong Zhang 
---
 drivers/gpu/drm/i915/gvt/handlers.c | 45 +
 1 file changed, 5 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 880448d..94fc0421 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1420,40 +1420,6 @@ static int skl_power_well_ctl_write(struct intel_vgpu 
*vgpu,
return intel_vgpu_default_mmio_write(vgpu, offset, , bytes);
 }
 
-static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
-   void *p_data, unsigned int bytes)
-{
-   struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
-   u32 v = *(u32 *)p_data;
-
-   if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
-   return intel_vgpu_default_mmio_write(vgpu,
-   offset, p_data, bytes);
-
-   switch (offset) {
-   case 0x4ddc:
-   /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-   vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
-   break;
-   case 0x42080:
-   /* bypass WaCompressedResourceDisplayNewHashMode */
-   vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
-   break;
-   case 0xe194:
-   /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-   vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
-   break;
-   case 0x7014:
-   /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-   vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
-   break;
-   default:
-   return -EINVAL;
-   }
-
-   return 0;
-}
-
 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
 {
@@ -1740,8 +1706,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
NULL, NULL);
-   MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
-skl_misc_ctl_write);
+   MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+NULL, NULL);
MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
@@ -2633,8 +2599,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
MMIO_D(0x6e570, D_BDW_PLUS);
MMIO_D(0x65f10, D_BDW_PLUS);
 
-   MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
-skl_misc_ctl_write);
+   MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 
NULL, NULL);
MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
@@ -2684,8 +2649,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-   MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write);
-   MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write);
+   MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(0x42080, D_SKL_PLUS, NULL, NULL);
MMIO_D(0x45504, D_SKL_PLUS);
MMIO_D(0x45520, D_SKL_PLUS);
MMIO_D(0x46000, D_SKL_PLUS);
-- 
1.9.1

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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [CI,01/21] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/21] drm/i915/execlists: Listen to COMPLETE 
context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34069/
State : warning

== Summary ==

Test gem_busy:
Subgroup extended-semaphore-render:
pass   -> SKIP   (shard-snb)
Subgroup extended-semaphore-blt:
pass   -> SKIP   (shard-snb)
Subgroup extended-semaphore-bsd:
pass   -> SKIP   (shard-snb)
Test gem_eio:
Subgroup in-flight-internal:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup flip-vs-absolute-wf_vblank:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup wf_vblank-vs-modeset-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test drv_module_reload:
Subgroup basic-no-display:
pass   -> DMESG-WARN (shard-snb) fdo#102707
Test pm_rc6_residency:
Subgroup rc6p-accuracy:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hswtotal:2585 pass:1473 dwarn:1   dfail:1   fail:11  skip:1099 
time:9450s
shard-snbtotal:2585 pass:1257 dwarn:2   dfail:1   fail:13  skip:1312 
time:8004s
Blacklisted hosts:
shard-apltotal:2585 pass:1624 dwarn:2   dfail:1   fail:22  skip:936 
time:13334s
shard-kbltotal:2565 pass:1681 dwarn:20  dfail:7   fail:22  skip:834 
time:10770s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7194/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/21] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/21] drm/i915/execlists: Listen to COMPLETE 
context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34069/
State : success

== Summary ==

Series 34069v1 series starting with [CI,01/21] drm/i915/execlists: Listen to 
COMPLETE context event not ACTIVE_IDLE
https://patchwork.freedesktop.org/api/1.0/series/34069/revisions/1/mbox/

Test gem_ctx_basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_create:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-files:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_exec:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_param:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_switch:
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default-heavy:
skip   -> PASS   (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:446s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:383s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:539s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:278s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:522s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:501s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:498s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:264s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:438s
fi-ilk-650   total:289  pass:236  dwarn:0   dfail:0   fail:0   skip:53  
time:471s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:479s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:491s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:535s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:590s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:467s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:546s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:523s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:464s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:562s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:421s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:604s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:492s

b4da24717364bc69bb981a1536be64413a582f3a drm-tip: 2017y-11m-17d-22h-46m-53s UTC 
integration manifest
0631567da6ba drm/i915: Enable rc6 for Ironlake
c4219c53a919 drm/i915: Remove unsafe i915.enable_rc6
ee5bbb4aaf54 drm/i915: Add is-wedged flag to intel_engine_dump()
fe9c5f192e18 drm/i915: Include the global reset count for intel_engine_dump()
eb56851a4d14 drm/i915: Include engine state on detecting a missed 
breadcrumb/seqno
c4923d6d856d drm/i915: Make engine state pretty-printer header configurable
e511c4937ae7 drm/i915: Use snprintf to avoid line-break when pretty-printing 
engines
ba2af04fe5aa drm/printer: Add drm_vprintf()
019218a1f462 drm/i915: Enable render context support for Ironlake
d250cb40175e move-switch-ctx
8ad1e511caea drm/i915: Unwind incomplete legacy context switches
167049b451d3 drm/i915: Remove i915.semaphores modparam
a79bd51b4c8e drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info
f00e39742cee drm/i915: Disable semaphores on Sandybridge
7d496667465f drm/i915: Remove 

[Intel-gfx] [CI 21/21] drm/i915: Enable rc6 for Ironlake

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_pci.c |  3 +--
 drivers/gpu/drm/i915/intel_pm.c | 28 
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f1c6756440a9..e0458dff0371 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -216,8 +216,7 @@ static const struct intel_device_info intel_gm45_info 
__initconst = {
 static const struct intel_device_info intel_ironlake_d_info __initconst = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
-   /* ilk does support rc6, but we do not implement [power] contexts */
-   .has_rc6 = 0,
+   .has_rc6 = true,
 
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1d46b7ed2cf..345127b55afd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6378,6 +6378,30 @@ static void gen9_disable_rps(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
+static void gen5_enable_rc6(struct drm_i915_private *dev_priv)
+{
+   u32 offset =
+   i915_ggtt_offset(dev_priv->kernel_context->engine[RCS].state);
+
+   I915_WRITE(PWRCTXA, offset | PWRCTX_EN);
+   I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+}
+
+static void gen5_disable_rc6(struct drm_i915_private *dev_priv)
+{
+   /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
+   I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
+   intel_wait_for_register(dev_priv,
+   RSTDBYCTL,
+   RSX_STATUS_MASK, RSX_STATUS_ON,
+   50);
+   I915_WRITE(PWRCTXA, 0);
+   POSTING_READ(PWRCTXA);
+
+   I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+   POSTING_READ(RSTDBYCTL);
+}
+
 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
 {
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7982,6 +8006,8 @@ static void intel_disable_rc6(struct drm_i915_private 
*dev_priv)
valleyview_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 5)
+   gen5_disable_rc6(dev_priv);
 
dev_priv->gt_pm.rc6.enabled = false;
 }
@@ -8048,6 +8074,8 @@ static void intel_enable_rc6(struct drm_i915_private 
*dev_priv)
gen8_enable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_enable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 5)
+   gen5_enable_rc6(dev_priv);
 
dev_priv->gt_pm.rc6.enabled = true;
 }
-- 
2.15.0

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[Intel-gfx] [CI 09/21] drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info

[Chris Wilson]

As the semaphores is just part of the engine, include it with the
general pretty printer universally used for debugging.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 32 
 drivers/gpu/drm/i915/intel_engine_cs.c |  9 +
 2 files changed, 9 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9cef1463d411..41d49a4d25d3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3235,37 +3235,6 @@ static int i915_shrinker_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static int i915_semaphore_status(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   int num_rings = INTEL_INFO(dev_priv)->num_rings;
-   enum intel_engine_id id;
-   int j, ret;
-
-   if (!i915_modparams.semaphores) {
-   seq_puts(m, "Semaphores are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-   intel_runtime_pm_get(dev_priv);
-
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-
-   intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
-   return 0;
-}
-
 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4745,7 +4714,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
-   {"i915_semaphore_status", i915_semaphore_status, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1fca7ac3b059..ef8e101ebd98 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1713,6 +1713,15 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
   I915_READ(RING_MI_MODE(engine->mmio_base)),
   I915_READ(RING_MI_MODE(engine->mmio_base)) & 
(MODE_IDLE) ? " [idle]" : "");
}
+   if (i915_modparams.semaphores) {
+   drm_printf(m, "\tSYNC_0: 0x%08x\n",
+  I915_READ(RING_SYNC_0(engine->mmio_base)));
+   drm_printf(m, "\tSYNC_1: 0x%08x\n",
+  I915_READ(RING_SYNC_1(engine->mmio_base)));
+   if (HAS_VEBOX(dev_priv))
+   drm_printf(m, "\tSYNC_2: 0x%08x\n",
+  I915_READ(RING_SYNC_2(engine->mmio_base)));
+   }
 
rcu_read_unlock();
 
-- 
2.15.0

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[Intel-gfx] [CI 14/21] drm/printer: Add drm_vprintf()

[Chris Wilson]

Simple va_args equivalent to the existing drm_printf() for use with the
drm_printer.

Signed-off-by: Chris Wilson 
Cc: Rob Clark 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_print.c |  5 +
 include/drm/drm_print.h | 15 +++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index 82ff327eb2df..781518fd88e3 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -55,13 +55,10 @@ EXPORT_SYMBOL(__drm_printfn_debug);
  */
 void drm_printf(struct drm_printer *p, const char *f, ...)
 {
-   struct va_format vaf;
va_list args;
 
va_start(args, f);
-   vaf.fmt = f;
-   vaf.va = 
-   p->printfn(p, );
+   drm_vprintf(p, f, );
va_end(args);
 }
 EXPORT_SYMBOL(drm_printf);
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 0968e411f562..e04d99cdc8d2 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -80,6 +80,21 @@ void __drm_printfn_debug(struct drm_printer *p, struct 
va_format *vaf);
 __printf(2, 3)
 void drm_printf(struct drm_printer *p, const char *f, ...);
 
+/*
+ * drm_vprintf - print to a _printer stream
+ * @p: the _printer
+ * @f: format string
+ * @args: the va_list
+ */
+__printf(2, 0)
+static inline void
+drm_vprintf(struct drm_printer *p, const char *fmt, va_list *va)
+{
+   struct va_format vaf = { .fmt = fmt, .va = va };
+
+   p->printfn(p, );
+}
+
 /**
  * drm_printf_indent - Print to a _printer stream with indentation
  * @printer: DRM printer
-- 
2.15.0

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[Intel-gfx] [CI 18/21] drm/i915: Include the global reset count for intel_engine_dump()

[Chris Wilson]

Since a global reset affects the engine, include that along side the
per-engine reset counter when pretty printing the engine state in
intel_engine_dump().

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index b4282ac6a4a7..e3070199e7df 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1682,8 +1682,9 @@ void intel_engine_dump(struct intel_engine_cs *engine,
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
   engine->timeline->inflight_seqnos);
-   drm_printf(m, "\tReset count: %d\n",
-  i915_reset_engine_count(error, engine));
+   drm_printf(m, "\tReset count: %d (global %d)\n",
+  i915_reset_engine_count(error, engine),
+  i915_reset_count(error));
 
rcu_read_lock();
 
-- 
2.15.0

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[Intel-gfx] [CI 19/21] drm/i915: Add is-wedged flag to intel_engine_dump()

[Chris Wilson]

Comparing the state tested by intel_engine_is_idle() and printed by
intel_engine_dump(), the only bit not shown is whether or not the device
is wedged. Add that little bit of information to the pretty printer so
that if the engine fails to idle we can see why.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e3070199e7df..21290e62699d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1676,6 +1676,9 @@ void intel_engine_dump(struct intel_engine_cs *engine,
va_end(ap);
}
 
+   if (i915_terminally_wedged(>i915->gpu_error))
+   drm_printf(m, "*** WEDGED ***\n");
+
drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
-- 
2.15.0

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[Intel-gfx] [CI 20/21] drm/i915: Remove unsafe i915.enable_rc6

[Chris Wilson]

It has been many years since the last confirmed sighting (and fix) of an
RC6 related bug (usually a system hang). Remove the parameter to stop
users from setting dangerous values, as they often set it during triage
and end up disabling the entire runtime pm instead (the option is not a
fine scalpel!).

Furthermore, it allows users to set known dangerous values which were
intended for testing and not for production use. For testing, we can
always patch in the required setting without having to expose ourselves
to random abuse.

v2: Fixup NEEDS_WaRsDisableCoarsePowerGating fumble, and document the
lack of ilk support better.
v3: Clear intel_info->rc6p if we don't support rc6 itself.

Signed-off-by: Chris Wilson 
Cc: Rodrigo Vivi 
Cc: Joonas Lahtinen 
Cc: Jani Nikula 
Cc: Imre Deak 
Cc: Daniel Vetter 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_drv.c |   2 +-
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_params.c  |   7 --
 drivers/gpu/drm/i915/i915_params.h  |   1 -
 drivers/gpu/drm/i915/i915_pci.c |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c   |  13 +++-
 drivers/gpu/drm/i915/intel_drv.h|   5 --
 drivers/gpu/drm/i915/intel_guc.c|   3 +-
 drivers/gpu/drm/i915/intel_pm.c | 134 +++-
 drivers/gpu/drm/i915/intel_uncore.c |   3 -
 10 files changed, 57 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 36fc99324b9d..81c68494d712 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2500,7 +2500,7 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
 
-   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled(
+   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv
return -ENODEV;
 
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 24ce5d89e07e..0c10f442977a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3210,6 +3210,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_PSR(dev_priv)   ((dev_priv)->info.has_psr)
 #define HAS_RC6(dev_priv)   ((dev_priv)->info.has_rc6)
 #define HAS_RC6p(dev_priv)  ((dev_priv)->info.has_rc6p)
+#define HAS_RC6pp(dev_priv) (false)
 
 #define HAS_CSR(dev_priv)  ((dev_priv)->info.has_csr)
 
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 3328147b4863..7bc538687871 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,13 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600,
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
-i915_param_named_unsafe(enable_rc6, int, 0400,
-   "Enable power-saving render C-state 6. "
-   "Different stages can be selected via bitmask values "
-   "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest 
rc6). "
-   "For example, 3 would enable rc6 and deep rc6, and 7 would enable 
everything. "
-   "default: -1 (use per-chip default)");
-
 i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 8321bd86cba5..c48c88bb95e8 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -34,7 +34,6 @@
param(int, lvds_channel_mode, 0) \
param(int, panel_use_ssc, -1) \
param(int, vbt_sdvo_panel_type, -1) \
-   param(int, enable_rc6, -1) \
param(int, enable_dc, -1) \
param(int, enable_fbc, -1) \
param(int, enable_ppgtt, -1) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6458c309c039..f1c6756440a9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -216,6 +216,9 @@ static const struct intel_device_info intel_gm45_info 
__initconst = {
 static const struct intel_device_info intel_ironlake_d_info __initconst = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
+   /* ilk does support rc6, but we do not implement [power] contexts */
+   .has_rc6 = 0,
+
 };
 
 static const struct intel_device_info intel_ironlake_m_info __initconst = {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 791759f632e1..1c95c2167d10 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ 

[Intel-gfx] [CI 15/21] drm/i915: Use snprintf to avoid line-break when pretty-printing engines

[Chris Wilson]

When printing the execlist ports, we first print the ELSP header then
follow it with the pretty-printed request. Since switching to
drm_printer and show the output via printk, it automatically appends a
newline to each call (unlike the old seq_printf output). To avoid the
unwanted line break, construct the ELSP request header in a temporary
buffer.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index f2dfa3f9fbdf..959064607fb4 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1663,6 +1663,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_gem_request *rq;
struct rb_node *rb;
+   char hdr[80];
u64 addr;
 
drm_printf(m, "%s\n", engine->name);
@@ -1775,12 +1776,12 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
 
rq = port_unpack(>port[idx], );
if (rq) {
-   drm_printf(m, "\t\tELSP[%d] count=%d, ",
-  idx, count);
-   print_request(m, rq, "rq: ");
+   snprintf(hdr, sizeof(hdr),
+"\t\tELSP[%d] count=%d, rq: ",
+idx, count);
+   print_request(m, rq, hdr);
} else {
-   drm_printf(m, "\t\tELSP[%d] idle\n",
-  idx);
+   drm_printf(m, "\t\tELSP[%d] idle\n", idx);
}
}
drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
-- 
2.15.0

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[Intel-gfx] [CI 17/21] drm/i915: Include engine state on detecting a missed breadcrumb/seqno

[Chris Wilson]

Now that we have a common engine state pretty printer, we can use that
instead of the adhoc information printed when we miss a breadcrumb.

v2: Rearrange intel_engine_disarm_breadcrumbs() to avoid calling
intel_engine_dump() under the rb spinlock (Mika) and to pretty-print the
error state early so that we include the full list of waiters.
v3: Pass missed breadcrumb msg to pretty-printer as the header
v4: Preserve DRM_DEBUG_DRIVER filtering.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 25 ++---
 drivers/gpu/drm/i915/intel_engine_cs.c   |  6 ++
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 5ae2d276f7f3..24c6fefdd0b1 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -64,12 +64,13 @@ static unsigned long wait_timeout(void)
 
 static noinline void missed_breadcrumb(struct intel_engine_cs *engine)
 {
-   DRM_DEBUG_DRIVER("%s missed breadcrumb at %pS, irq posted? %s, current 
seqno=%x, last=%x\n",
-engine->name, __builtin_return_address(0),
-yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
-   >irq_posted)),
-intel_engine_get_seqno(engine),
-intel_engine_last_submit(engine));
+   if (drm_debug & DRM_UT_DRIVER) {
+   struct drm_printer p = drm_debug_printer(__func__);
+
+   intel_engine_dump(engine, ,
+ "%s missed breadcrumb at %pS\n",
+ engine->name, __builtin_return_address(0));
+   }
 
set_bit(engine->id, >i915->gpu_error.missed_irq_rings);
 }
@@ -213,28 +214,30 @@ void intel_engine_unpin_breadcrumbs_irq(struct 
intel_engine_cs *engine)
 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
 {
struct intel_breadcrumbs *b = >breadcrumbs;
-   struct intel_wait *wait, *n, *first;
+   struct intel_wait *wait, *n;
 
if (!b->irq_armed)
return;
 
-   /* We only disarm the irq when we are idle (all requests completed),
+   /*
+* We only disarm the irq when we are idle (all requests completed),
 * so if the bottom-half remains asleep, it missed the request
 * completion.
 */
+   if (intel_engine_wakeup(engine) & ENGINE_WAKEUP_ASLEEP)
+   missed_breadcrumb(engine);
 
spin_lock_irq(>rb_lock);
 
spin_lock(>irq_lock);
-   first = fetch_and_zero(>irq_wait);
+   b->irq_wait = NULL;
if (b->irq_armed)
__intel_engine_disarm_breadcrumbs(engine);
spin_unlock(>irq_lock);
 
rbtree_postorder_for_each_entry_safe(wait, n, >waiters, node) {
RB_CLEAR_NODE(>node);
-   if (wake_up_process(wait->tsk) && wait == first)
-   missed_breadcrumb(engine);
+   wake_up_process(wait->tsk);
}
b->waiters = RB_ROOT;
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e51e90270d31..b4282ac6a4a7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1825,6 +1825,12 @@ void intel_engine_dump(struct intel_engine_cs *engine,
}
spin_unlock_irq(>rb_lock);
 
+   drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s) (execlists? %s)\n",
+  engine->irq_posted,
+  yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
+ >irq_posted)),
+  yesno(test_bit(ENGINE_IRQ_EXECLIST,
+ >irq_posted)));
drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
drm_printf(m, "\n");
 }
-- 
2.15.0

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[Intel-gfx] [CI 11/21] drm/i915: Unwind incomplete legacy context switches

[Chris Wilson]

The legacy context switch for ringbuffer submission is multistaged,
where each of those stages may fail. However, we were updating global
state after some stages, and so we had to force the incomplete request
to be submitted because we could not unwind. Save the global state
before performing the switches, and so enable us to unwind back to the
previous global state should any phase fail. We then must cancel the
request instead of submitting it should the construction fail.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 168 ++--
 drivers/gpu/drm/i915/i915_gem_request.c |  18 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 4 files changed, 62 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 6ca56e482d79..f63bec08cc85 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -507,6 +507,7 @@ void i915_gem_contexts_lost(struct drm_i915_private 
*dev_priv)
 
for_each_engine(engine, dev_priv, id) {
engine->legacy_active_context = NULL;
+   engine->legacy_active_ppgtt = NULL;
 
if (!engine->last_retired_context)
continue;
@@ -681,68 +682,48 @@ static int remap_l3(struct drm_i915_gem_request *req, int 
slice)
return 0;
 }
 
-static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
-  struct intel_engine_cs *engine,
-  struct i915_gem_context *to)
-{
-   if (to->remap_slice)
-   return false;
-
-   if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   return to == engine->legacy_active_context;
-}
-
-static bool
-needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine)
-{
-   struct i915_gem_context *from = engine->legacy_active_context;
-
-   if (!ppgtt)
-   return false;
-
-   /* Always load the ppgtt on first use */
-   if (!from)
-   return true;
-
-   /* Same context without new entries, skip */
-   if ((!from->ppgtt || from->ppgtt == ppgtt) &&
-   !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   if (engine->id != RCS)
-   return true;
-
-   return true;
-}
-
-static int do_rcs_switch(struct drm_i915_gem_request *req)
+/**
+ * i915_switch_context() - perform a GPU context switch.
+ * @rq: request for which we'll execute the context switch
+ *
+ * The context life cycle is simple. The context refcount is incremented and
+ * decremented by 1 and create and destroy. If the context is in use by the 
GPU,
+ * it will have a refcount > 1. This allows us to destroy the context abstract
+ * object while letting the normal object tracking destroy the backing BO.
+ *
+ * This function should not be used in execlists mode.  Instead the context is
+ * switched by writing to the ELSP and requests keep a reference to their
+ * context.
+ */
+int i915_switch_context(struct drm_i915_gem_request *rq)
 {
-   struct i915_gem_context *to = req->ctx;
-   struct intel_engine_cs *engine = req->engine;
-   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
-   struct i915_gem_context *from = engine->legacy_active_context;
-   u32 hw_flags;
+   struct intel_engine_cs *engine = rq->engine;
+   struct i915_gem_context *to = rq->ctx;
+   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
+   struct i915_gem_context *saved_ctx = engine->legacy_active_context;
+   struct i915_hw_ppgtt *saved_mm = engine->legacy_active_ppgtt;
+   u32 hw_flags = 0;
int ret, i;
 
-   GEM_BUG_ON(engine->id != RCS);
-
-   if (skip_rcs_switch(ppgtt, engine, to))
-   return 0;
+   lockdep_assert_held(>i915->drm.struct_mutex);
+   GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
-   if (needs_pd_load_pre(ppgtt, engine)) {
-   /* Older GENs and non render rings still want the load first,
-* "PP_DCLV followed by PP_DIR_BASE register through Load
-* Register Immediate commands in Ring Buffer before submitting
-* a context."*/
+   if (ppgtt != saved_mm ||
+   (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) {
trace_switch_mm(engine, to);
-   ret = ppgtt->switch_mm(ppgtt, req);
+   ret = ppgtt->switch_mm(ppgtt, rq);
if (ret)
-   return ret;
+   goto err;
+
+   ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
+   engine->legacy_active_ppgtt = ppgtt;
+   hw_flags = 

[Intel-gfx] [CI 12/21] move-switch-ctx

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem_context.c | 197 
 drivers/gpu/drm/i915/intel_ringbuffer.c | 185 +-
 2 files changed, 184 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index f63bec08cc85..aee0f6d72d33 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -567,203 +567,6 @@ void i915_gem_context_close(struct drm_file *file)
idr_destroy(_priv->context_idr);
 }
 
-static inline int
-mi_set_context(struct drm_i915_gem_request *req, u32 flags)
-{
-   struct drm_i915_private *dev_priv = req->i915;
-   struct intel_engine_cs *engine = req->engine;
-   enum intel_engine_id id;
-   const int num_rings =
-   /* Use an extended w/a on gen7 if signalling from other rings */
-   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
-   INTEL_INFO(dev_priv)->num_rings - 1 :
-   0;
-   int len;
-   u32 *cs;
-
-   flags |= MI_MM_SPACE_GTT;
-   if (IS_HASWELL(dev_priv))
-   /* These flags are for resource streamer on HSW+ */
-   flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
-   else
-   flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
-
-   len = 4;
-   if (IS_GEN7(dev_priv))
-   len += 2 + (num_rings ? 4*num_rings + 6 : 0);
-
-   cs = intel_ring_begin(req, len);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
-   if (IS_GEN7(dev_priv)) {
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   *cs++ = i915_mmio_reg_offset(
-  RING_PSMI_CTL(signaller->mmio_base));
-   *cs++ = _MASKED_BIT_ENABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-   }
-   }
-
-   *cs++ = MI_NOOP;
-   *cs++ = MI_SET_CONTEXT;
-   *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
-   /*
-* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
-* WaMiSetContext_Hang:snb,ivb,vlv
-*/
-   *cs++ = MI_NOOP;
-
-   if (IS_GEN7(dev_priv)) {
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-   i915_reg_t last_reg = {}; /* keep gcc quiet */
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   last_reg = RING_PSMI_CTL(signaller->mmio_base);
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = _MASKED_BIT_DISABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-
-   /* Insert a delay before the next switch! */
-   *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = i915_ggtt_offset(engine->scratch);
-   *cs++ = MI_NOOP;
-   }
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-   }
-
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-static int remap_l3(struct drm_i915_gem_request *req, int slice)
-{
-   u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
-   int i;
-
-   if (!remap_info)
-   return 0;
-
-   cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /*
-* Note: We do not worry about the concurrent register cacheline hang
-* here because no other code should access these registers other than
-* at initialization time.
-*/
-   *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
-   for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
-   *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
-   *cs++ = remap_info[i];
-   }
-   *cs++ = MI_NOOP;
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-/**
- * i915_switch_context() - perform a GPU context switch.
- * @rq: request for which we'll execute the context switch
- *
- * The context life cycle is simple. The context refcount is 

[Intel-gfx] [CI 13/21] drm/i915: Enable render context support for Ironlake

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 22c095035539..f2dfa3f9fbdf 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -29,6 +29,8 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
+#define GEN5_CXT_TOTAL_SIZE( 1 * PAGE_SIZE)
+
 /* Haswell does have the CXT_SIZE register however it does not appear to be
  * valid. Now, docs explain in dwords what is in the context object. The full
  * size is 70720 bytes, however, the power context and execlist context will
@@ -175,6 +177,7 @@ __intel_engine_context_size(struct drm_i915_private 
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+   return GEN5_CXT_TOTAL_SIZE;
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index deb3cc7e08a8..4e9f2c546bb1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1408,6 +1408,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
len = 4;
if (IS_GEN7(i915))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+   if (IS_GEN5(i915))
+   len += 2;
 
cs = intel_ring_begin(rq, len);
if (IS_ERR(cs))
@@ -1430,6 +1432,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
 
*cs++ = MI_NOOP;
@@ -1464,6 +1468,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH;
}
 
intel_ring_advance(rq, cs);
-- 
2.15.0

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[Intel-gfx] [CI 10/21] drm/i915: Remove i915.semaphores modparam

[Chris Wilson]

Having disabled the broken semaphores on Sandybridge, there is no need
for a modparam any more, so remove it in favour of a simple
HAS_LEGACY_SEMAPHORES() guard.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Maarten Lankhorst 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c |  7 +--
 drivers/gpu/drm/i915/i915_drv.h |  4 ++--
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  4 ++--
 8 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 779a6f0785c7..36fc99324b9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,7 +321,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = USES_PPGTT(dev_priv);
break;
case I915_PARAM_HAS_SEMAPHORES:
-   value = i915_modparams.semaphores;
+   value = HAS_LEGACY_SEMAPHORES(dev_priv);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
@@ -1066,11 +1066,6 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
i915_modparams.enable_ppgtt);
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-   i915_modparams.semaphores =
-   intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
-   DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
-yesno(i915_modparams.semaphores));
-
intel_uc_sanitize_options(dev_priv);
 
intel_gvt_sanitize_options(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 953867d9171e..24ce5d89e07e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3140,6 +3140,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_BLT(dev_priv)  HAS_ENGINE(dev_priv, BCS)
 #define HAS_VEBOX(dev_priv)HAS_ENGINE(dev_priv, VECS)
 
+#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
+
 #define HAS_LLC(dev_priv)  ((dev_priv)->info.has_llc)
 #define HAS_SNOOP(dev_priv)((dev_priv)->info.has_snoop)
 #define HAS_EDRAM(dev_priv)(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
@@ -3303,8 +3305,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
int enable_ppgtt);
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
-
 /* i915_drv.c */
 void __printf(3, 4)
 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d53bb8e872ba..792e6dc7e19b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4997,17 +4997,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
-{
-   if (!IS_GEN7(dev_priv))
-   return false;
-
-   if (value >= 0)
-   return value;
-
-   return true;
-}
-
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 {
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0704d9af261b..6ca56e482d79 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -574,7 +574,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags)
enum intel_engine_id id;
const int num_rings =
/* Use an extended w/a on gen7 if signalling from other rings */
-   (i915_modparams.semaphores && IS_GEN7(dev_priv)) ?
+   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
INTEL_INFO(dev_priv)->num_rings - 1 :
0;
int len;
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index d61c1787c164..3328147b4863 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,10 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600,
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
-i915_param_named_unsafe(semaphores, int, 0400,
-   "Use semaphores for inter-ring sync "
-   "(default: -1 (use per-chip defaults))");
-
 

[Intel-gfx] [CI 16/21] drm/i915: Make engine state pretty-printer header configurable

[Chris Wilson]

Pass in a format string (and args) to specify the header to be emitted
along with the engine state when pretty-printing. This allows the header
to be emitted inside the drm_printer stream, so sharing the same prefix
and output characteristics (e.g. debug level and filtering).

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   | 15 ---
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  5 -
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c |  7 ---
 4 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 41d49a4d25d3..823fc6a74b98 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3218,7 +3218,7 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
 
p = drm_seq_file_printer(m);
for_each_engine(engine, dev_priv, id)
-   intel_engine_dump(engine, );
+   intel_engine_dump(engine, , "%s\n", engine->name);
 
intel_runtime_pm_put(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 959064607fb4..e51e90270d31 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1585,7 +1585,7 @@ void intel_engines_park(struct drm_i915_private *i915)
dev_err(i915->drm.dev,
"%s is not idle before parking\n",
engine->name);
-   intel_engine_dump(engine, );
+   intel_engine_dump(engine, , NULL);
}
 
if (engine->park)
@@ -1655,7 +1655,9 @@ static void print_request(struct drm_printer *m,
   rq->timeline->common->name);
 }
 
-void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m)
+void intel_engine_dump(struct intel_engine_cs *engine,
+  struct drm_printer *m,
+  const char *header, ...)
 {
struct intel_breadcrumbs * const b = >breadcrumbs;
const struct intel_engine_execlists * const execlists = 
>execlists;
@@ -1666,7 +1668,14 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
char hdr[80];
u64 addr;
 
-   drm_printf(m, "%s\n", engine->name);
+   if (header) {
+   va_list ap;
+
+   va_start(ap, header);
+   drm_vprintf(m, header, );
+   va_end(ap);
+   }
+
drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbc9c36f675e..41ac69dbe554 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -926,6 +926,9 @@ unsigned int intel_engines_has_context_isolation(struct 
drm_i915_private *i915);
 
 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
 
-void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p);
+__printf(3, 4)
+void intel_engine_dump(struct intel_engine_cs *engine,
+  struct drm_printer *m,
+  const char *header, ...);
 
 #endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 1bbb8c46e2d9..f98546b8a7fa 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -619,7 +619,7 @@ static int igt_wait_reset(void *arg)
 
pr_err("Failed to start request %x, at %x\n",
   rq->fence.seqno, hws_seqno(, rq));
-   intel_engine_dump(rq->engine, );
+   intel_engine_dump(rq->engine, , "%s\n", rq->engine->name);
 
i915_reset(i915, 0);
i915_gem_set_wedged(i915);
@@ -714,7 +714,8 @@ static int igt_reset_queue(void *arg)
 
pr_err("Failed to start request %x, at %x\n",
   prev->fence.seqno, hws_seqno(, prev));
-   intel_engine_dump(rq->engine, );
+   intel_engine_dump(prev->engine, ,
+ "%s\n", prev->engine->name);
 
i915_gem_request_put(rq);
i915_gem_request_put(prev);
@@ -820,7 +821,7 @@ static int igt_handle_error(void *arg)
 
pr_err("Failed to start request %x, at %x\n",
   rq->fence.seqno, hws_seqno(, rq));
-   

[Intel-gfx] [CI 01/21] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Since commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c
Author: Oscar Mateo 
Date:   Thu Jul 24 17:04:40 2014 +0100

drm/i915/bdw: Avoid non-lite-restore preemptions

execlists has listened to (ACTIVE_IDLE | ELEMENT_SWITCH) for detecting
when one context completed and it either continued onto the next (in port
1) or idled. We would always see COMPLETE | ACTIVE_IDLE on the final
context-switch event, but on recent gen it appears that we now get
separate ACTIVE_IDLE and COMPLETE events. In particular, the ACTIVE_IDLE
events may not be coupled to a context (since it is a general state rather
than a specific context completion event).

v2: Update the history, execlists did originally start out by listening
to the COMPLETE event not ACTIVE_IDLE.
v3: Update preempt completion test to also use COMPLETE not ACTIVE_IDLE.

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Acked-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..c2cfdfdc0722 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
 #define GEN8_CTX_STATUS_LITE_RESTORE   (1 << 15)
 
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
 
@@ -876,7 +876,7 @@ static void execlists_submission_tasklet(unsigned long data)
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
-   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE &&
+   if (status & GEN8_CTX_STATUS_COMPLETE &&
buf[2*head + 1] == PREEMPT_ID) {
execlists_cancel_port_requests(execlists);
execlists_unwind_incomplete_requests(execlists);
-- 
2.15.0

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[Intel-gfx] [CI 07/21] drm/i915: Remove obsolete ringbuffer emission for gen8+

[Chris Wilson]

Since removing the module parameter to force selection of ringbuffer
emission for gen8, the code is defunct. Remove it.

To put the difference into perspective, a couple of microbenchmarks
(bdw i7-5557u, 20170324):
ring  execlists
exec continuous nops on all rings:   1.491us2.223us
exec sequential nops on each ring:  12.508us   53.682us
single nop + sync:   9.272us   30.291us

vblank_mode=0 glxgears:~11000fps   ~9000fps

Since the earlier submission, gen8 ringbuffer submission has fallen
further and further behind in features. So while ringbuffer may hold the
throughput crown, in terms of interactive latency, execlists is much
better. Alas, we have no convenient metrics for such, other than
demonstrating things we can do with execlists but can not using
legacy ringbuffer submission.

We have made a few improvements to lowlevel execlists throughput,
and ringbuffer currently panics on boot! (bdw i7-5557u, 20171026):

ring  execlists
exec continuous nops on all rings:   n/a1.921us
exec sequential nops on each ring:   n/a   44.621us
single nop + sync:   n/a   21.953us

vblank_mode=0 glxgears:  n/a  ~18500fps

References: https://bugs.freedesktop.org/show_bug.cgi?id=87725
Signed-off-by: Chris Wilson 
Once-upon-a-time-Reviewed-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  44 +---
 drivers/gpu/drm/i915/i915_drv.h |   2 -
 drivers/gpu/drm/i915/i915_gem.c |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  47 +---
 drivers/gpu/drm/i915/i915_gpu_error.c   |  36 ---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  14 --
 drivers/gpu/drm/i915/intel_hangcheck.c  |  44 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 431 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  25 +-
 9 files changed, 94 insertions(+), 551 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5e2a6e18771f..9cef1463d411 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3254,44 +3254,12 @@ static int i915_semaphore_status(struct seq_file *m, 
void *unused)
return ret;
intel_runtime_pm_get(dev_priv);
 
-   if (IS_BROADWELL(dev_priv)) {
-   struct page *page;
-   uint64_t *seqno;
-
-   page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
-
-   seqno = (uint64_t *)kmap_atomic(page);
-   for_each_engine(engine, dev_priv, id) {
-   uint64_t offset;
-
-   seq_printf(m, "%s\n", engine->name);
-
-   seq_puts(m, "  Last signal:");
-   for (j = 0; j < num_rings; j++) {
-   offset = id * I915_NUM_ENGINES + j;
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   seq_puts(m, "  Last wait:  ");
-   for (j = 0; j < num_rings; j++) {
-   offset = id + (j * I915_NUM_ENGINES);
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   }
-   kunmap_atomic(seqno);
-   } else {
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  
I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-   }
+   seq_puts(m, "  Last signal:");
+   for_each_engine(engine, dev_priv, id)
+   for (j = 0; j < num_rings; j++)
+   seq_printf(m, "0x%08x\n",
+  I915_READ(engine->semaphore.mbox.signal[j]));
+   seq_putc(m, '\n');
 
intel_runtime_pm_put(dev_priv);
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a21544b62866..953867d9171e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -942,7 +942,6 @@ struct i915_gpu_state {
u64 fence[I915_MAX_NUM_FENCES];
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
-   struct drm_i915_error_object *semaphore;
 
struct drm_i915_error_engine {

[Intel-gfx] [CI 05/21] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   |  4 
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 10 +++---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  5 -
 10 files changed, 14 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b7895788bc75..14d9e61a1e06 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 91eae1b20c42..86e2346357cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00be015e01df..d8952ff8e6b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private 

[Intel-gfx] [CI 03/21] drm/i915/execlists: Skip a lite-restore immediately prior to a context-completion

[Chris Wilson]

If we are about to do another context-switch in the near future skip
doing performing a lite-restore now. (Forcing a lite-restore just before
a context-switch effectively doubles the cost of that context-switch, so
long as we can handle the interrupt and resubmit before the GPU powers
down, which under normal conditions is expected.)

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6191a2e59e8a..2edd57b3d53e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -628,6 +628,19 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
if (port_count([1]))
goto unlock;
 
+   /*
+* If we are about to do another context-switch in
+* the near future skip doing performing a lite-restore
+* now. (Forcing a lite-restore just before a
+* context-switch effectively doubles the cost of that
+* context-switch, so long as we can handle the
+* interrupt and resubmit before the GPU powers down,
+* which under normal conditions is expected.)
+*/
+   if (i915_seqno_passed(intel_engine_get_seqno(engine),
+ last->global_seqno - 1))
+   goto unlock;
+
/* WaIdleLiteRestore:bdw,skl
 * Apply the wa NOOPs to prevent
 * ring:HEAD == req:TAIL as we resubmit the
-- 
2.15.0

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[Intel-gfx] [CI 02/21] drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write

[Chris Wilson]

The hardware needs some time to process the information received in the
ExecList Submission Port, and expects us to don't write anything new until
it has 'acknowledged' this new execlist by sending an IDLE_ACTIVE or
PREEMPTED CSB event.

If we do not follow this, the driver could write new data into the ELSP
before HW had finishing fetching the previous one, putting us in
'undefined behaviour' space.

This seems to be the problem causing the spurious PREEMPTED & COMPLETE
events after a COMPLETE like the one below:

[] vcs0: sw rd pointer = 2, hw wr pointer = 0, current 'head' = 3.
[] vcs0:  Execlist CSB[0]: 0x0018 _ 0x0007
[] vcs0:  Execlist CSB[1]: 0x0001 _ 0x
[] vcs0:  Execlist CSB[2]: 0x0018 _ 0x0007  <<< COMPLETE
[] vcs0:  Execlist CSB[3]: 0x0012 _ 0x0007  <<< PREEMPTED & COMPLETE
[] vcs0:  Execlist CSB[4]: 0x8002 _ 0x0006
[] vcs0:  Execlist CSB[5]: 0x0014 _ 0x0006

The ELSP writes that lead to this CSB sequence show that the HW hadn't
started executing the previous execlist (the one with only ctx 0x6) by the
time the new one was submitted; this is a bit more clear in the data
show in the EXECLIST_STATUS register at the time of the ELSP write.

[] vcs0: ELSP[0] = 0x0_0[execlist1] - status_reg = 0x0_302
[] vcs0: ELSP[1] = 0x6_fedb2119 [execlist0] - status_reg = 0x0_8302

[] vcs0: ELSP[2] = 0x7_fedaf119 [execlist1] - status_reg = 0x0_8308
[] vcs0: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308

Note that having to wait for this ack does not disable lite-restores,
although it may reduce their numbers.

v2: Rewrote Michel's patch, his digging and his fix, my spelling.
v3: Reorder to ack early to allow preemption

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Suggested-by: Michel Thierry 
Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c| 22 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2cfdfdc0722..6191a2e59e8a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -479,6 +479,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
elsp_write(desc, elsp);
}
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
@@ -531,6 +532,7 @@ static void inject_preempt_context(struct intel_engine_cs 
*engine)
elsp_write(0, elsp);
 
elsp_write(ce->lrc_desc, elsp);
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static void execlists_dequeue(struct intel_engine_cs *engine)
@@ -577,9 +579,20 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * know the next preemption status we see corresponds
 * to this ELSP update.
 */
+   GEM_BUG_ON(!port_count([0]));
if (port_count([0]) > 1)
goto unlock;
 
+   /*
+* If we write to ELSP a second time before the HW has had
+* a chance to respond to the previous write, we can confuse
+* the HW and hit "undefined behaviour". After writing to ELSP,
+* we must then wait until we see a context-switch event from
+* the HW to indicate that it has had a chance to respond.
+*/
+   if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
+   goto unlock;
+
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) &&
rb_entry(rb, struct i915_priolist, node)->priority >
max(last->priotree.priority, 0)) {
@@ -873,6 +886,15 @@ static void execlists_submission_tasklet(unsigned long 
data)
GEM_TRACE("%s csb[%dd]: status=0x%08x:0x%08x\n",
  engine->name, head,
  status, buf[2*head + 1]);
+
+   if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
+ GEN8_CTX_STATUS_PREEMPTED))
+   execlists_set_active(execlists,
+EXECLISTS_ACTIVE_HWACK);
+   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
+   execlists_clear_active(execlists,
+  EXECLISTS_ACTIVE_HWACK);
+
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f867aa6c31fc..add7a30c1a61 100644
--- 

[Intel-gfx] [CI 08/21] drm/i915: Disable semaphores on Sandybridge

[Chris Wilson]

I should have admitted defeat long ago as there has been a rare but
persistent error on Sandybridge where semaphore signaling did not
propagate to the waiter, leading to a GPU hang.

With the work on fence signaling for v4.9, the impact of using CPU driven
signaling was greatly reduced wrt to the latency of GPU semaphores,
though without logical rings support, the benefit of reordering work to
avoid bubbles is not realised (i.e. as it stands fence signaling is just
a slower, more costly version of HW semaphores; but works more
consistently). As a rough indicator of the difference,

with semaphores:
Sequential (3 engines, 1 processes): average 5.470us per cycle [expected 
4.988us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 15.771us per cycle [expected 
4.923us]

In comparison, v3.4:
with semaphores:
Sequential (3 engines, 1 processes): average 16.066us per cycle [expected 
11.842us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 23.460us per cycle [expected 
11.839us]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54226 #and 100+ dupes
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Acked-by: Mika Kuoppala 
Reviewed-by: Joonas Lahtinen = 0)
return value;
 
-   /* Enable semaphores on SNB when IO remapping is off */
-   if (IS_GEN6(dev_priv) && intel_vtd_active())
-   return false;
-
return true;
 }
 
-- 
2.15.0

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[Intel-gfx] [CI 06/21] drm/i915: Remove i915.enable_execlists module parameter

[Chris Wilson]

Execlists and legacy ringbuffer submission are no longer feature
comparable (execlists now offer greater functionality that should
overcome their performance hit) and obsoletes the unsafe module
parameter, i.e. comparing the two modes of execution is no longer
useful, so remove the debug tool.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Lionel Landwerlin  #i915_perf.c
---
 drivers/gpu/drm/i915/gvt/render.c   |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c | 70 -
 drivers/gpu/drm/i915/i915_drv.c |  8 +---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++
 drivers/gpu/drm/i915/i915_gem.c | 10 ++---
 drivers/gpu/drm/i915/i915_gem_context.c | 10 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 --
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/i915_perf.c|  8 ++--
 drivers/gpu/drm/i915/intel_engine_cs.c  |  8 ++--
 drivers/gpu/drm/i915/intel_gvt.c|  5 ---
 drivers/gpu/drm/i915/intel_lrc.c| 31 ---
 drivers/gpu/drm/i915/intel_lrc.h|  4 --
 14 files changed, 20 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 0672178548ef..dac12c25f349 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -294,8 +294,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, 
int ring_id)
 * write.
 */
if (mmio->in_context &&
-   ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-   i915_modparams.enable_execlists)
+   (ctx_ctrl & inhibit_mask) != inhibit_mask)
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index df3852c02a35..5e2a6e18771f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1989,75 +1989,6 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static void i915_dump_lrc_obj(struct seq_file *m,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
-   struct i915_vma *vma = ctx->engine[engine->id].state;
-   struct page *page;
-   int j;
-
-   seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
-
-   if (!vma) {
-   seq_puts(m, "\tFake context\n");
-   return;
-   }
-
-   if (vma->flags & I915_VMA_GLOBAL_BIND)
-   seq_printf(m, "\tBound in GGTT at 0x%08x\n",
-  i915_ggtt_offset(vma));
-
-   if (i915_gem_object_pin_pages(vma->obj)) {
-   seq_puts(m, "\tFailed to get pages for context object\n\n");
-   return;
-   }
-
-   page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
-   if (page) {
-   u32 *reg_state = kmap_atomic(page);
-
-   for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
-   seq_printf(m,
-  "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-  j * 4,
-  reg_state[j], reg_state[j + 1],
-  reg_state[j + 2], reg_state[j + 3]);
-   }
-   kunmap_atomic(reg_state);
-   }
-
-   i915_gem_object_unpin_pages(vma->obj);
-   seq_putc(m, '\n');
-}
-
-static int i915_dump_lrc(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   struct i915_gem_context *ctx;
-   enum intel_engine_id id;
-   int ret;
-
-   if (!i915_modparams.enable_execlists) {
-   seq_printf(m, "Logical Ring Contexts are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   list_for_each_entry(ctx, _priv->contexts.list, link)
-   for_each_engine(engine, dev_priv, id)
-   i915_dump_lrc_obj(m, ctx, engine);
-
-   mutex_unlock(>struct_mutex);
-
-   return 0;
-}
-
 static const char *swizzle_string(unsigned swizzle)
 {
switch (swizzle) {
@@ -4833,7 +4764,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_vbt", i915_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
-   {"i915_dump_lrc", i915_dump_lrc, 0},
{"i915_forcewake_domains", i915_forcewake_domains, 0},

[Intel-gfx] [CI 04/21] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..b7895788bc75 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return 0;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [CI,01/13] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/13] drm/i915/execlists: Listen to COMPLETE 
context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34068/
State : warning

== Summary ==

Test gem_busy:
Subgroup extended-semaphore-bsd:
pass   -> SKIP   (shard-snb)
Subgroup extended-semaphore-blt:
pass   -> SKIP   (shard-snb)
Subgroup extended-semaphore-render:
pass   -> SKIP   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Test gem_eio:
Subgroup in-flight-internal:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup wf_vblank-vs-modeset-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2567 pass:1457 dwarn:1   dfail:0   fail:9   skip:1099 
time:9364s
shard-snbtotal:2567 pass:1241 dwarn:1   dfail:0   fail:11  skip:1313 
time:7894s
Blacklisted hosts:
shard-apltotal:2567 pass:1605 dwarn:1   dfail:0   fail:24  skip:936 
time:13018s
shard-kbltotal:2534 pass:1674 dwarn:7   dfail:1   fail:25  skip:825 
time:10217s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7193/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/13] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/13] drm/i915/execlists: Listen to COMPLETE 
context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34068/
State : success

== Summary ==

Series 34068v1 series starting with [CI,01/13] drm/i915/execlists: Listen to 
COMPLETE context event not ACTIVE_IDLE
https://patchwork.freedesktop.org/api/1.0/series/34068/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#103163
Test gem_ctx_basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_create:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-files:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_exec:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_param:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_switch:
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default-heavy:
skip   -> PASS   (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:454s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:382s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:544s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  
time:501s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:485s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:267s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:429s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:438s
fi-ilk-650   total:289  pass:236  dwarn:0   dfail:0   fail:0   skip:53  
time:460s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:470s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:531s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:486s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:574s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:542s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:518s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:498s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:460s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:556s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:425s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:609s
fi-cnl-y total:253  pass:227  dwarn:0   dfail:0   fail:0   skip:25 
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:498s

b4da24717364bc69bb981a1536be64413a582f3a drm-tip: 2017y-11m-17d-22h-46m-53s UTC 
integration manifest
c7e3a668d770 drm/i915: Enable render context support for Ironlake
34b4fb0d521b move-switch-ctx
7aec96278be9 drm/i915: Unwind incomplete legacy context switches
fa6a2a34896f drm/i915: Remove i915.semaphores modparam
e1525f412dc5 drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info
f921c9238739 drm/i915: Disable semaphores on Sandybridge
6c785d4f0bfa drm/i915: Remove obsolete ringbuffer emission for gen8+
356745b10d55 drm/i915: Remove i915.enable_execlists module parameter
c3410b632ef6 drm/i915: Automatic i915_switch_context for legacy
48fce006e22b drm/i915: Pull 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,01/21] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/21] drm/i915/execlists: Listen to COMPLETE 
context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34067/
State : failure

== Summary ==

Series 34067v1 series starting with [CI,01/21] drm/i915/execlists: Listen to 
COMPLETE context event not ACTIVE_IDLE
https://patchwork.freedesktop.org/api/1.0/series/34067/revisions/1/mbox/

Test chamelium:
Subgroup dp-hpd-fast:
skip   -> INCOMPLETE (fi-ivb-3520m)
skip   -> INCOMPLETE (fi-ivb-3770)
skip   -> INCOMPLETE (fi-byt-j1900)
skip   -> INCOMPLETE (fi-hsw-4770)
skip   -> INCOMPLETE (fi-hsw-4770r) fdo#102332
Test gem_ctx_basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_create:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-files:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_exec:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_param:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_switch:
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default-heavy:
skip   -> PASS   (fi-ilk-650)
Test gem_exec_flush:
Subgroup basic-wb-rw-default:
pass   -> FAIL   (fi-bxt-j4205)

fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:457s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:383s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:542s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:279s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:506s
fi-bxt-j4205 total:289  pass:259  dwarn:0   dfail:0   fail:1   skip:29  
time:509s
fi-byt-j1900 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:264s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-hsw-4770  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-hsw-4770r total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-ilk-650   total:289  pass:236  dwarn:0   dfail:0   fail:0   skip:53  
time:461s
fi-ivb-3520m total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-ivb-3770  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:484s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:528s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:586s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:545s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:522s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:457s
fi-snb-2520m total:246  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:426s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:608s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:581s
fi-glk-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:494s

b4da24717364bc69bb981a1536be64413a582f3a drm-tip: 2017y-11m-17d-22h-46m-53s UTC 
integration manifest
5b0f048db5a7 drm/i915: Enable rc6 for Ironlake
e8b5b48a1f37 drm/i915: Remove unsafe i915.enable_rc6
bc1b8d03e142 drm/i915: Add is-wedged flag to intel_engine_dump()
48be6a97c427 drm/i915: Include the global reset count for intel_engine_dump()
7926f7de8533 drm/i915: Include engine state on detecting a missed 
breadcrumb/seqno
4f5adf0692f1 drm/i915: Make engine state pretty-printer header configurable
8cc1d8ba5fcd drm/i915: Use snprintf to avoid line-break when pretty-printing 
engines
49b9c5bee2cb drm/printer: Add drm_vprintf()
0a18f58eea83 drm/i915: Enable render context 

[Intel-gfx] [CI 11/13] drm/i915: Unwind incomplete legacy context switches

[Chris Wilson]

The legacy context switch for ringbuffer submission is multistaged,
where each of those stages may fail. However, we were updating global
state after some stages, and so we had to force the incomplete request
to be submitted because we could not unwind. Save the global state
before performing the switches, and so enable us to unwind back to the
previous global state should any phase fail. We then must cancel the
request instead of submitting it should the construction fail.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 168 ++--
 drivers/gpu/drm/i915/i915_gem_request.c |  18 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 4 files changed, 62 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 6ca56e482d79..f63bec08cc85 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -507,6 +507,7 @@ void i915_gem_contexts_lost(struct drm_i915_private 
*dev_priv)
 
for_each_engine(engine, dev_priv, id) {
engine->legacy_active_context = NULL;
+   engine->legacy_active_ppgtt = NULL;
 
if (!engine->last_retired_context)
continue;
@@ -681,68 +682,48 @@ static int remap_l3(struct drm_i915_gem_request *req, int 
slice)
return 0;
 }
 
-static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
-  struct intel_engine_cs *engine,
-  struct i915_gem_context *to)
-{
-   if (to->remap_slice)
-   return false;
-
-   if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   return to == engine->legacy_active_context;
-}
-
-static bool
-needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine)
-{
-   struct i915_gem_context *from = engine->legacy_active_context;
-
-   if (!ppgtt)
-   return false;
-
-   /* Always load the ppgtt on first use */
-   if (!from)
-   return true;
-
-   /* Same context without new entries, skip */
-   if ((!from->ppgtt || from->ppgtt == ppgtt) &&
-   !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   if (engine->id != RCS)
-   return true;
-
-   return true;
-}
-
-static int do_rcs_switch(struct drm_i915_gem_request *req)
+/**
+ * i915_switch_context() - perform a GPU context switch.
+ * @rq: request for which we'll execute the context switch
+ *
+ * The context life cycle is simple. The context refcount is incremented and
+ * decremented by 1 and create and destroy. If the context is in use by the 
GPU,
+ * it will have a refcount > 1. This allows us to destroy the context abstract
+ * object while letting the normal object tracking destroy the backing BO.
+ *
+ * This function should not be used in execlists mode.  Instead the context is
+ * switched by writing to the ELSP and requests keep a reference to their
+ * context.
+ */
+int i915_switch_context(struct drm_i915_gem_request *rq)
 {
-   struct i915_gem_context *to = req->ctx;
-   struct intel_engine_cs *engine = req->engine;
-   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
-   struct i915_gem_context *from = engine->legacy_active_context;
-   u32 hw_flags;
+   struct intel_engine_cs *engine = rq->engine;
+   struct i915_gem_context *to = rq->ctx;
+   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
+   struct i915_gem_context *saved_ctx = engine->legacy_active_context;
+   struct i915_hw_ppgtt *saved_mm = engine->legacy_active_ppgtt;
+   u32 hw_flags = 0;
int ret, i;
 
-   GEM_BUG_ON(engine->id != RCS);
-
-   if (skip_rcs_switch(ppgtt, engine, to))
-   return 0;
+   lockdep_assert_held(>i915->drm.struct_mutex);
+   GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
-   if (needs_pd_load_pre(ppgtt, engine)) {
-   /* Older GENs and non render rings still want the load first,
-* "PP_DCLV followed by PP_DIR_BASE register through Load
-* Register Immediate commands in Ring Buffer before submitting
-* a context."*/
+   if (ppgtt != saved_mm ||
+   (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) {
trace_switch_mm(engine, to);
-   ret = ppgtt->switch_mm(ppgtt, req);
+   ret = ppgtt->switch_mm(ppgtt, rq);
if (ret)
-   return ret;
+   goto err;
+
+   ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
+   engine->legacy_active_ppgtt = ppgtt;
+   hw_flags = 

[Intel-gfx] [CI 12/13] move-switch-ctx

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem_context.c | 197 
 drivers/gpu/drm/i915/intel_ringbuffer.c | 185 +-
 2 files changed, 184 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index f63bec08cc85..aee0f6d72d33 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -567,203 +567,6 @@ void i915_gem_context_close(struct drm_file *file)
idr_destroy(_priv->context_idr);
 }
 
-static inline int
-mi_set_context(struct drm_i915_gem_request *req, u32 flags)
-{
-   struct drm_i915_private *dev_priv = req->i915;
-   struct intel_engine_cs *engine = req->engine;
-   enum intel_engine_id id;
-   const int num_rings =
-   /* Use an extended w/a on gen7 if signalling from other rings */
-   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
-   INTEL_INFO(dev_priv)->num_rings - 1 :
-   0;
-   int len;
-   u32 *cs;
-
-   flags |= MI_MM_SPACE_GTT;
-   if (IS_HASWELL(dev_priv))
-   /* These flags are for resource streamer on HSW+ */
-   flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
-   else
-   flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
-
-   len = 4;
-   if (IS_GEN7(dev_priv))
-   len += 2 + (num_rings ? 4*num_rings + 6 : 0);
-
-   cs = intel_ring_begin(req, len);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
-   if (IS_GEN7(dev_priv)) {
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   *cs++ = i915_mmio_reg_offset(
-  RING_PSMI_CTL(signaller->mmio_base));
-   *cs++ = _MASKED_BIT_ENABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-   }
-   }
-
-   *cs++ = MI_NOOP;
-   *cs++ = MI_SET_CONTEXT;
-   *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
-   /*
-* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
-* WaMiSetContext_Hang:snb,ivb,vlv
-*/
-   *cs++ = MI_NOOP;
-
-   if (IS_GEN7(dev_priv)) {
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-   i915_reg_t last_reg = {}; /* keep gcc quiet */
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   last_reg = RING_PSMI_CTL(signaller->mmio_base);
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = _MASKED_BIT_DISABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-
-   /* Insert a delay before the next switch! */
-   *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = i915_ggtt_offset(engine->scratch);
-   *cs++ = MI_NOOP;
-   }
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-   }
-
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-static int remap_l3(struct drm_i915_gem_request *req, int slice)
-{
-   u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
-   int i;
-
-   if (!remap_info)
-   return 0;
-
-   cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /*
-* Note: We do not worry about the concurrent register cacheline hang
-* here because no other code should access these registers other than
-* at initialization time.
-*/
-   *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
-   for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
-   *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
-   *cs++ = remap_info[i];
-   }
-   *cs++ = MI_NOOP;
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-/**
- * i915_switch_context() - perform a GPU context switch.
- * @rq: request for which we'll execute the context switch
- *
- * The context life cycle is simple. The context refcount is 

[Intel-gfx] [CI 08/13] drm/i915: Disable semaphores on Sandybridge

[Chris Wilson]

I should have admitted defeat long ago as there has been a rare but
persistent error on Sandybridge where semaphore signaling did not
propagate to the waiter, leading to a GPU hang.

With the work on fence signaling for v4.9, the impact of using CPU driven
signaling was greatly reduced wrt to the latency of GPU semaphores,
though without logical rings support, the benefit of reordering work to
avoid bubbles is not realised (i.e. as it stands fence signaling is just
a slower, more costly version of HW semaphores; but works more
consistently). As a rough indicator of the difference,

with semaphores:
Sequential (3 engines, 1 processes): average 5.470us per cycle [expected 
4.988us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 15.771us per cycle [expected 
4.923us]

In comparison, v3.4:
with semaphores:
Sequential (3 engines, 1 processes): average 16.066us per cycle [expected 
11.842us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 23.460us per cycle [expected 
11.839us]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54226 #and 100+ dupes
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Acked-by: Mika Kuoppala 
Reviewed-by: Joonas Lahtinen = 0)
return value;
 
-   /* Enable semaphores on SNB when IO remapping is off */
-   if (IS_GEN6(dev_priv) && intel_vtd_active())
-   return false;
-
return true;
 }
 
-- 
2.15.0

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[Intel-gfx] [CI 09/13] drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info

[Chris Wilson]

As the semaphores is just part of the engine, include it with the
general pretty printer universally used for debugging.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 32 
 drivers/gpu/drm/i915/intel_engine_cs.c |  9 +
 2 files changed, 9 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9cef1463d411..41d49a4d25d3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3235,37 +3235,6 @@ static int i915_shrinker_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static int i915_semaphore_status(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   int num_rings = INTEL_INFO(dev_priv)->num_rings;
-   enum intel_engine_id id;
-   int j, ret;
-
-   if (!i915_modparams.semaphores) {
-   seq_puts(m, "Semaphores are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-   intel_runtime_pm_get(dev_priv);
-
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-
-   intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
-   return 0;
-}
-
 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4745,7 +4714,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
-   {"i915_semaphore_status", i915_semaphore_status, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1fca7ac3b059..ef8e101ebd98 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1713,6 +1713,15 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
   I915_READ(RING_MI_MODE(engine->mmio_base)),
   I915_READ(RING_MI_MODE(engine->mmio_base)) & 
(MODE_IDLE) ? " [idle]" : "");
}
+   if (i915_modparams.semaphores) {
+   drm_printf(m, "\tSYNC_0: 0x%08x\n",
+  I915_READ(RING_SYNC_0(engine->mmio_base)));
+   drm_printf(m, "\tSYNC_1: 0x%08x\n",
+  I915_READ(RING_SYNC_1(engine->mmio_base)));
+   if (HAS_VEBOX(dev_priv))
+   drm_printf(m, "\tSYNC_2: 0x%08x\n",
+  I915_READ(RING_SYNC_2(engine->mmio_base)));
+   }
 
rcu_read_unlock();
 
-- 
2.15.0

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[Intel-gfx] [CI 13/13] drm/i915: Enable render context support for Ironlake

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 22c095035539..f2dfa3f9fbdf 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -29,6 +29,8 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
+#define GEN5_CXT_TOTAL_SIZE( 1 * PAGE_SIZE)
+
 /* Haswell does have the CXT_SIZE register however it does not appear to be
  * valid. Now, docs explain in dwords what is in the context object. The full
  * size is 70720 bytes, however, the power context and execlist context will
@@ -175,6 +177,7 @@ __intel_engine_context_size(struct drm_i915_private 
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+   return GEN5_CXT_TOTAL_SIZE;
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index deb3cc7e08a8..4e9f2c546bb1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1408,6 +1408,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
len = 4;
if (IS_GEN7(i915))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+   if (IS_GEN5(i915))
+   len += 2;
 
cs = intel_ring_begin(rq, len);
if (IS_ERR(cs))
@@ -1430,6 +1432,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
 
*cs++ = MI_NOOP;
@@ -1464,6 +1468,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH;
}
 
intel_ring_advance(rq, cs);
-- 
2.15.0

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[Intel-gfx] [CI 10/13] drm/i915: Remove i915.semaphores modparam

[Chris Wilson]

Having disabled the broken semaphores on Sandybridge, there is no need
for a modparam any more, so remove it in favour of a simple
HAS_LEGACY_SEMAPHORES() guard.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Maarten Lankhorst 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c |  7 +--
 drivers/gpu/drm/i915/i915_drv.h |  4 ++--
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  4 ++--
 8 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 779a6f0785c7..36fc99324b9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,7 +321,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = USES_PPGTT(dev_priv);
break;
case I915_PARAM_HAS_SEMAPHORES:
-   value = i915_modparams.semaphores;
+   value = HAS_LEGACY_SEMAPHORES(dev_priv);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
@@ -1066,11 +1066,6 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
i915_modparams.enable_ppgtt);
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-   i915_modparams.semaphores =
-   intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
-   DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
-yesno(i915_modparams.semaphores));
-
intel_uc_sanitize_options(dev_priv);
 
intel_gvt_sanitize_options(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 953867d9171e..24ce5d89e07e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3140,6 +3140,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_BLT(dev_priv)  HAS_ENGINE(dev_priv, BCS)
 #define HAS_VEBOX(dev_priv)HAS_ENGINE(dev_priv, VECS)
 
+#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
+
 #define HAS_LLC(dev_priv)  ((dev_priv)->info.has_llc)
 #define HAS_SNOOP(dev_priv)((dev_priv)->info.has_snoop)
 #define HAS_EDRAM(dev_priv)(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
@@ -3303,8 +3305,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
int enable_ppgtt);
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
-
 /* i915_drv.c */
 void __printf(3, 4)
 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d53bb8e872ba..792e6dc7e19b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4997,17 +4997,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
-{
-   if (!IS_GEN7(dev_priv))
-   return false;
-
-   if (value >= 0)
-   return value;
-
-   return true;
-}
-
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 {
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0704d9af261b..6ca56e482d79 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -574,7 +574,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags)
enum intel_engine_id id;
const int num_rings =
/* Use an extended w/a on gen7 if signalling from other rings */
-   (i915_modparams.semaphores && IS_GEN7(dev_priv)) ?
+   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
INTEL_INFO(dev_priv)->num_rings - 1 :
0;
int len;
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index d61c1787c164..3328147b4863 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,10 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600,
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
-i915_param_named_unsafe(semaphores, int, 0400,
-   "Use semaphores for inter-ring sync "
-   "(default: -1 (use per-chip defaults))");
-
 

[Intel-gfx] [CI 04/13] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..b7895788bc75 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return 0;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] [CI 02/13] drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write

[Chris Wilson]

The hardware needs some time to process the information received in the
ExecList Submission Port, and expects us to don't write anything new until
it has 'acknowledged' this new execlist by sending an IDLE_ACTIVE or
PREEMPTED CSB event.

If we do not follow this, the driver could write new data into the ELSP
before HW had finishing fetching the previous one, putting us in
'undefined behaviour' space.

This seems to be the problem causing the spurious PREEMPTED & COMPLETE
events after a COMPLETE like the one below:

[] vcs0: sw rd pointer = 2, hw wr pointer = 0, current 'head' = 3.
[] vcs0:  Execlist CSB[0]: 0x0018 _ 0x0007
[] vcs0:  Execlist CSB[1]: 0x0001 _ 0x
[] vcs0:  Execlist CSB[2]: 0x0018 _ 0x0007  <<< COMPLETE
[] vcs0:  Execlist CSB[3]: 0x0012 _ 0x0007  <<< PREEMPTED & COMPLETE
[] vcs0:  Execlist CSB[4]: 0x8002 _ 0x0006
[] vcs0:  Execlist CSB[5]: 0x0014 _ 0x0006

The ELSP writes that lead to this CSB sequence show that the HW hadn't
started executing the previous execlist (the one with only ctx 0x6) by the
time the new one was submitted; this is a bit more clear in the data
show in the EXECLIST_STATUS register at the time of the ELSP write.

[] vcs0: ELSP[0] = 0x0_0[execlist1] - status_reg = 0x0_302
[] vcs0: ELSP[1] = 0x6_fedb2119 [execlist0] - status_reg = 0x0_8302

[] vcs0: ELSP[2] = 0x7_fedaf119 [execlist1] - status_reg = 0x0_8308
[] vcs0: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308

Note that having to wait for this ack does not disable lite-restores,
although it may reduce their numbers.

v2: Rewrote Michel's patch, his digging and his fix, my spelling.
v3: Reorder to ack early to allow preemption

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Suggested-by: Michel Thierry 
Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c| 22 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2cfdfdc0722..6191a2e59e8a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -479,6 +479,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
elsp_write(desc, elsp);
}
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
@@ -531,6 +532,7 @@ static void inject_preempt_context(struct intel_engine_cs 
*engine)
elsp_write(0, elsp);
 
elsp_write(ce->lrc_desc, elsp);
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static void execlists_dequeue(struct intel_engine_cs *engine)
@@ -577,9 +579,20 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * know the next preemption status we see corresponds
 * to this ELSP update.
 */
+   GEM_BUG_ON(!port_count([0]));
if (port_count([0]) > 1)
goto unlock;
 
+   /*
+* If we write to ELSP a second time before the HW has had
+* a chance to respond to the previous write, we can confuse
+* the HW and hit "undefined behaviour". After writing to ELSP,
+* we must then wait until we see a context-switch event from
+* the HW to indicate that it has had a chance to respond.
+*/
+   if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
+   goto unlock;
+
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) &&
rb_entry(rb, struct i915_priolist, node)->priority >
max(last->priotree.priority, 0)) {
@@ -873,6 +886,15 @@ static void execlists_submission_tasklet(unsigned long 
data)
GEM_TRACE("%s csb[%dd]: status=0x%08x:0x%08x\n",
  engine->name, head,
  status, buf[2*head + 1]);
+
+   if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
+ GEN8_CTX_STATUS_PREEMPTED))
+   execlists_set_active(execlists,
+EXECLISTS_ACTIVE_HWACK);
+   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
+   execlists_clear_active(execlists,
+  EXECLISTS_ACTIVE_HWACK);
+
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f867aa6c31fc..add7a30c1a61 100644
--- 

[Intel-gfx] [CI 07/13] drm/i915: Remove obsolete ringbuffer emission for gen8+

[Chris Wilson]

Since removing the module parameter to force selection of ringbuffer
emission for gen8, the code is defunct. Remove it.

To put the difference into perspective, a couple of microbenchmarks
(bdw i7-5557u, 20170324):
ring  execlists
exec continuous nops on all rings:   1.491us2.223us
exec sequential nops on each ring:  12.508us   53.682us
single nop + sync:   9.272us   30.291us

vblank_mode=0 glxgears:~11000fps   ~9000fps

Since the earlier submission, gen8 ringbuffer submission has fallen
further and further behind in features. So while ringbuffer may hold the
throughput crown, in terms of interactive latency, execlists is much
better. Alas, we have no convenient metrics for such, other than
demonstrating things we can do with execlists but can not using
legacy ringbuffer submission.

We have made a few improvements to lowlevel execlists throughput,
and ringbuffer currently panics on boot! (bdw i7-5557u, 20171026):

ring  execlists
exec continuous nops on all rings:   n/a1.921us
exec sequential nops on each ring:   n/a   44.621us
single nop + sync:   n/a   21.953us

vblank_mode=0 glxgears:  n/a  ~18500fps

References: https://bugs.freedesktop.org/show_bug.cgi?id=87725
Signed-off-by: Chris Wilson 
Once-upon-a-time-Reviewed-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  44 +---
 drivers/gpu/drm/i915/i915_drv.h |   2 -
 drivers/gpu/drm/i915/i915_gem.c |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  47 +---
 drivers/gpu/drm/i915/i915_gpu_error.c   |  36 ---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  14 --
 drivers/gpu/drm/i915/intel_hangcheck.c  |  44 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 431 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  25 +-
 9 files changed, 94 insertions(+), 551 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5e2a6e18771f..9cef1463d411 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3254,44 +3254,12 @@ static int i915_semaphore_status(struct seq_file *m, 
void *unused)
return ret;
intel_runtime_pm_get(dev_priv);
 
-   if (IS_BROADWELL(dev_priv)) {
-   struct page *page;
-   uint64_t *seqno;
-
-   page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
-
-   seqno = (uint64_t *)kmap_atomic(page);
-   for_each_engine(engine, dev_priv, id) {
-   uint64_t offset;
-
-   seq_printf(m, "%s\n", engine->name);
-
-   seq_puts(m, "  Last signal:");
-   for (j = 0; j < num_rings; j++) {
-   offset = id * I915_NUM_ENGINES + j;
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   seq_puts(m, "  Last wait:  ");
-   for (j = 0; j < num_rings; j++) {
-   offset = id + (j * I915_NUM_ENGINES);
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   }
-   kunmap_atomic(seqno);
-   } else {
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  
I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-   }
+   seq_puts(m, "  Last signal:");
+   for_each_engine(engine, dev_priv, id)
+   for (j = 0; j < num_rings; j++)
+   seq_printf(m, "0x%08x\n",
+  I915_READ(engine->semaphore.mbox.signal[j]));
+   seq_putc(m, '\n');
 
intel_runtime_pm_put(dev_priv);
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a21544b62866..953867d9171e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -942,7 +942,6 @@ struct i915_gpu_state {
u64 fence[I915_MAX_NUM_FENCES];
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
-   struct drm_i915_error_object *semaphore;
 
struct drm_i915_error_engine {

[Intel-gfx] [CI 03/13] drm/i915/execlists: Skip a lite-restore immediately prior to a context-completion

[Chris Wilson]

If we are about to do another context-switch in the near future skip
doing performing a lite-restore now. (Forcing a lite-restore just before
a context-switch effectively doubles the cost of that context-switch, so
long as we can handle the interrupt and resubmit before the GPU powers
down, which under normal conditions is expected.)

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6191a2e59e8a..2edd57b3d53e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -628,6 +628,19 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
if (port_count([1]))
goto unlock;
 
+   /*
+* If we are about to do another context-switch in
+* the near future skip doing performing a lite-restore
+* now. (Forcing a lite-restore just before a
+* context-switch effectively doubles the cost of that
+* context-switch, so long as we can handle the
+* interrupt and resubmit before the GPU powers down,
+* which under normal conditions is expected.)
+*/
+   if (i915_seqno_passed(intel_engine_get_seqno(engine),
+ last->global_seqno - 1))
+   goto unlock;
+
/* WaIdleLiteRestore:bdw,skl
 * Apply the wa NOOPs to prevent
 * ring:HEAD == req:TAIL as we resubmit the
-- 
2.15.0

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[Intel-gfx] [CI 05/13] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   |  4 
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 10 +++---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  6 --
 10 files changed, 14 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b7895788bc75..14d9e61a1e06 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 91eae1b20c42..86e2346357cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00be015e01df..d8952ff8e6b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private 

[Intel-gfx] [CI 06/13] drm/i915: Remove i915.enable_execlists module parameter

[Chris Wilson]

Execlists and legacy ringbuffer submission are no longer feature
comparable (execlists now offer greater functionality that should
overcome their performance hit) and obsoletes the unsafe module
parameter, i.e. comparing the two modes of execution is no longer
useful, so remove the debug tool.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Lionel Landwerlin  #i915_perf.c
---
 drivers/gpu/drm/i915/gvt/render.c   |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c | 70 -
 drivers/gpu/drm/i915/i915_drv.c |  8 +---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++
 drivers/gpu/drm/i915/i915_gem.c | 10 ++---
 drivers/gpu/drm/i915/i915_gem_context.c | 10 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 --
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/i915_perf.c|  8 ++--
 drivers/gpu/drm/i915/intel_engine_cs.c  |  8 ++--
 drivers/gpu/drm/i915/intel_gvt.c|  5 ---
 drivers/gpu/drm/i915/intel_lrc.c| 31 ---
 drivers/gpu/drm/i915/intel_lrc.h|  4 --
 14 files changed, 20 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 0672178548ef..dac12c25f349 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -294,8 +294,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, 
int ring_id)
 * write.
 */
if (mmio->in_context &&
-   ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-   i915_modparams.enable_execlists)
+   (ctx_ctrl & inhibit_mask) != inhibit_mask)
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index df3852c02a35..5e2a6e18771f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1989,75 +1989,6 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static void i915_dump_lrc_obj(struct seq_file *m,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
-   struct i915_vma *vma = ctx->engine[engine->id].state;
-   struct page *page;
-   int j;
-
-   seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
-
-   if (!vma) {
-   seq_puts(m, "\tFake context\n");
-   return;
-   }
-
-   if (vma->flags & I915_VMA_GLOBAL_BIND)
-   seq_printf(m, "\tBound in GGTT at 0x%08x\n",
-  i915_ggtt_offset(vma));
-
-   if (i915_gem_object_pin_pages(vma->obj)) {
-   seq_puts(m, "\tFailed to get pages for context object\n\n");
-   return;
-   }
-
-   page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
-   if (page) {
-   u32 *reg_state = kmap_atomic(page);
-
-   for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
-   seq_printf(m,
-  "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-  j * 4,
-  reg_state[j], reg_state[j + 1],
-  reg_state[j + 2], reg_state[j + 3]);
-   }
-   kunmap_atomic(reg_state);
-   }
-
-   i915_gem_object_unpin_pages(vma->obj);
-   seq_putc(m, '\n');
-}
-
-static int i915_dump_lrc(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   struct i915_gem_context *ctx;
-   enum intel_engine_id id;
-   int ret;
-
-   if (!i915_modparams.enable_execlists) {
-   seq_printf(m, "Logical Ring Contexts are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   list_for_each_entry(ctx, _priv->contexts.list, link)
-   for_each_engine(engine, dev_priv, id)
-   i915_dump_lrc_obj(m, ctx, engine);
-
-   mutex_unlock(>struct_mutex);
-
-   return 0;
-}
-
 static const char *swizzle_string(unsigned swizzle)
 {
switch (swizzle) {
@@ -4833,7 +4764,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_vbt", i915_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
-   {"i915_dump_lrc", i915_dump_lrc, 0},
{"i915_forcewake_domains", i915_forcewake_domains, 0},

[Intel-gfx] [CI 01/13] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Since commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c
Author: Oscar Mateo 
Date:   Thu Jul 24 17:04:40 2014 +0100

drm/i915/bdw: Avoid non-lite-restore preemptions

execlists has listened to (ACTIVE_IDLE | ELEMENT_SWITCH) for detecting
when one context completed and it either continued onto the next (in port
1) or idled. We would always see COMPLETE | ACTIVE_IDLE on the final
context-switch event, but on recent gen it appears that we now get
separate ACTIVE_IDLE and COMPLETE events. In particular, the ACTIVE_IDLE
events may not be coupled to a context (since it is a general state rather
than a specific context completion event).

v2: Update the history, execlists did originally start out by listening
to the COMPLETE event not ACTIVE_IDLE.
v3: Update preempt completion test to also use COMPLETE not ACTIVE_IDLE.

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Acked-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..c2cfdfdc0722 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
 #define GEN8_CTX_STATUS_LITE_RESTORE   (1 << 15)
 
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
 
@@ -876,7 +876,7 @@ static void execlists_submission_tasklet(unsigned long data)
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
-   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE &&
+   if (status & GEN8_CTX_STATUS_COMPLETE &&
buf[2*head + 1] == PREEMPT_ID) {
execlists_cancel_port_requests(execlists);
execlists_unwind_incomplete_requests(execlists);
-- 
2.15.0

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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Runtime disable for eDP DRRS

[C, Ramalingam]

Thanks for reviewing these changes Rodrigo.

> -Original Message-
> From: Vivi, Rodrigo
> Sent: Saturday, November 18, 2017 12:24 AM
> To: C, Ramalingam 
> Cc: Zanoni, Paulo R ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Runtime disable for eDP DRRS
> 
> On Tue, Nov 07, 2017 at 06:38:23PM +, Ramalingam C wrote:
> > From: "C, Ramalingam" 
> >
> > Debugfs called i915_drrs_ctl is added to enable and disable the eDP
> > DRRS. Writing 0 will disable the feature, whereas non-zero will enable
> > the feature.
> >
> > Possibility of disabling the DRRS, enables the testing of the
> > frontbuffer tracking based features (FBC, DRRS and PSR) as standalone
> > or any combination of the set.
> >
> > [v2]: ctl interface is moved from module parameter to debugfs
> > [Rodrigo]
> 
> Thanks
> 
> >
> > Signed-off-by: C, Ramalingam 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 43
> > -
> >  1 file changed, 42 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 0bb6e01121fc..0c1501fe4c9f 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4747,6 +4747,46 @@ static const struct file_operations
> i915_hpd_storm_ctl_fops = {
> > .write = i915_hpd_storm_ctl_write
> >  };
> >
> > +static int i915_drrs_ctl_set(void *data, u64 val) {
> > +   struct drm_i915_private *dev_priv = data;
> > +   struct drm_device *dev = _priv->drm;
> > +   struct intel_crtc *intel_crtc;
> > +   struct intel_encoder *encoder;
> > +   struct intel_dp *intel_dp;
> > +
> > +   if (INTEL_GEN(dev_priv) < 7)
> 
> I believe we need to define a HAS_DRRS(dev_priv) which based on what is on
> intel_cpu_transcoder_set_m_n would be
> (IS_CHERRYVIEW(dev_priv) || INTEL_GEN(dev_priv) < 8)

Actually programming of pll divider m and n changes between platforms. Hence 
this check was there.
But all the platforms from Gen 7 has the DRRS support. Do we still need a macro 
for this check?

-Ram
> 
> > +   return -ENODEV;
> > +
> > +   drm_modeset_lock_all(dev);
> 
> my first reaction to this was: "why do you need to lock all modeset?!"
> But this simplify a lot the logic here...
> This assure that drrs is really not getting changed from other places.
> 
> > +   for_each_intel_crtc(dev, intel_crtc) {
> > +   if (!intel_crtc->base.state->active ||
> > +   !intel_crtc->config->has_drrs)
> 
> I was going to say that this check already happens inside enable and disable
> functions... But I see the reason why to check before the unecessary noise.
> 
> > +   continue;
> > +
> > +   for_each_encoder_on_crtc(dev, _crtc->base, encoder) {
> > +   if (encoder->type != INTEL_OUTPUT_EDP)
> > +   continue;
> > +
> > +   DRM_DEBUG_DRIVER("Manually %sabling DRRS.
> %llu\n",
> > +   val ? "en" : "dis", val);
> > +
> > +   intel_dp = enc_to_intel_dp(>base);
> > +   if (val)
> > +   intel_edp_drrs_enable(intel_dp,
> > +   intel_crtc->config);
> > +   else
> > +   intel_edp_drrs_disable(intel_dp,
> > +   intel_crtc->config);
> > +   }
> > +   }
> > +   drm_modeset_unlock_all(dev);
> > +
> > +   return 0;
> > +}
> 
> It seems simple and effective. Simpler than I imagined...
> My only question is about that HAS_DRRS and when to skip here...
> 
> > +
> > +DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set,
> > +"%llu\n");
> > +
> >  static const struct drm_info_list i915_debugfs_list[] = {
> > {"i915_capabilities", i915_capabilities, 0},
> > {"i915_gem_objects", i915_gem_object_info, 0}, @@ -4828,7 +4868,8
> @@
> > static const struct i915_debugfs_files {
> > {"i915_dp_test_active", _displayport_test_active_fops},
> > {"i915_guc_log_control", _guc_log_control_fops},
> > {"i915_hpd_storm_ctl", _hpd_storm_ctl_fops},
> > -   {"i915_ipc_status", _ipc_status_fops}
> > +   {"i915_ipc_status", _ipc_status_fops},
> > +   {"i915_drrs_ctl", _drrs_ctl_fops}
> >  };
> >
> >  int i915_debugfs_register(struct drm_i915_private *dev_priv)
> > --
> > 2.7.4
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,01/13] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/13] drm/i915/execlists: Listen to COMPLETE 
context event not ACTIVE_IDLE
URL   : https://patchwork.freedesktop.org/series/34066/
State : failure

== Summary ==

Series 34066v1 series starting with [CI,01/13] drm/i915/execlists: Listen to 
COMPLETE context event not ACTIVE_IDLE
https://patchwork.freedesktop.org/api/1.0/series/34066/revisions/1/mbox/

Test chamelium:
Subgroup dp-hpd-fast:
skip   -> INCOMPLETE (fi-ivb-3520m)
skip   -> INCOMPLETE (fi-ivb-3770)
skip   -> INCOMPLETE (fi-byt-j1900)
skip   -> INCOMPLETE (fi-byt-n2820)
skip   -> INCOMPLETE (fi-hsw-4770)
skip   -> INCOMPLETE (fi-hsw-4770r) fdo#102332
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#103163
Test gem_ctx_basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_create:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-files:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_exec:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_param:
Subgroup basic:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Test gem_ctx_switch:
Subgroup basic-default:
skip   -> PASS   (fi-ilk-650)
Subgroup basic-default-heavy:
skip   -> PASS   (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332
fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:455s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:382s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:542s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:276s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:508s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-byt-j1900 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-byt-n2820 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:265s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-hsw-4770  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-hsw-4770r total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-ilk-650   total:289  pass:236  dwarn:0   dfail:0   fail:0   skip:53  
time:467s
fi-ivb-3520m total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-ivb-3770  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:468s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:530s
fi-kbl-7567u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:577s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6600u total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:545s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:521s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:461s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:555s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:423s
Blacklisted hosts:
fi-cfl-s2total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:608s
fi-glk-dsi   total:156  pass:133  dwarn:0   dfail:0   fail:0   skip:22 

b4da24717364bc69bb981a1536be64413a582f3a drm-tip: 2017y-11m-17d-22h-46m-53s UTC 
integration manifest
daecefc70a13 drm/i915: Enable render context support for Ironlake
01b95f537849 move-switch-ctx
bf65de35fc20 drm/i915: Unwind incomplete legacy context switches
7f19f1f9869f drm/i915: Remove i915.semaphores modparam
8331cdeab6a9 drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info

[Intel-gfx] [CI 17/21] drm/i915: Include engine state on detecting a missed breadcrumb/seqno

[Chris Wilson]

Now that we have a common engine state pretty printer, we can use that
instead of the adhoc information printed when we miss a breadcrumb.

v2: Rearrange intel_engine_disarm_breadcrumbs() to avoid calling
intel_engine_dump() under the rb spinlock (Mika) and to pretty-print the
error state early so that we include the full list of waiters.
v3: Pass missed breadcrumb msg to pretty-printer as the header
v4: Preserve DRM_DEBUG_DRIVER filtering.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 25 ++---
 drivers/gpu/drm/i915/intel_engine_cs.c   |  6 ++
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 5ae2d276f7f3..24c6fefdd0b1 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -64,12 +64,13 @@ static unsigned long wait_timeout(void)
 
 static noinline void missed_breadcrumb(struct intel_engine_cs *engine)
 {
-   DRM_DEBUG_DRIVER("%s missed breadcrumb at %pS, irq posted? %s, current 
seqno=%x, last=%x\n",
-engine->name, __builtin_return_address(0),
-yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
-   >irq_posted)),
-intel_engine_get_seqno(engine),
-intel_engine_last_submit(engine));
+   if (drm_debug & DRM_UT_DRIVER) {
+   struct drm_printer p = drm_debug_printer(__func__);
+
+   intel_engine_dump(engine, ,
+ "%s missed breadcrumb at %pS\n",
+ engine->name, __builtin_return_address(0));
+   }
 
set_bit(engine->id, >i915->gpu_error.missed_irq_rings);
 }
@@ -213,28 +214,30 @@ void intel_engine_unpin_breadcrumbs_irq(struct 
intel_engine_cs *engine)
 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
 {
struct intel_breadcrumbs *b = >breadcrumbs;
-   struct intel_wait *wait, *n, *first;
+   struct intel_wait *wait, *n;
 
if (!b->irq_armed)
return;
 
-   /* We only disarm the irq when we are idle (all requests completed),
+   /*
+* We only disarm the irq when we are idle (all requests completed),
 * so if the bottom-half remains asleep, it missed the request
 * completion.
 */
+   if (intel_engine_wakeup(engine) & ENGINE_WAKEUP_ASLEEP)
+   missed_breadcrumb(engine);
 
spin_lock_irq(>rb_lock);
 
spin_lock(>irq_lock);
-   first = fetch_and_zero(>irq_wait);
+   b->irq_wait = NULL;
if (b->irq_armed)
__intel_engine_disarm_breadcrumbs(engine);
spin_unlock(>irq_lock);
 
rbtree_postorder_for_each_entry_safe(wait, n, >waiters, node) {
RB_CLEAR_NODE(>node);
-   if (wake_up_process(wait->tsk) && wait == first)
-   missed_breadcrumb(engine);
+   wake_up_process(wait->tsk);
}
b->waiters = RB_ROOT;
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e51e90270d31..b4282ac6a4a7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1825,6 +1825,12 @@ void intel_engine_dump(struct intel_engine_cs *engine,
}
spin_unlock_irq(>rb_lock);
 
+   drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s) (execlists? %s)\n",
+  engine->irq_posted,
+  yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
+ >irq_posted)),
+  yesno(test_bit(ENGINE_IRQ_EXECLIST,
+ >irq_posted)));
drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
drm_printf(m, "\n");
 }
-- 
2.15.0

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[Intel-gfx] [CI 20/21] drm/i915: Remove unsafe i915.enable_rc6

[Chris Wilson]

It has been many years since the last confirmed sighting (and fix) of an
RC6 related bug (usually a system hang). Remove the parameter to stop
users from setting dangerous values, as they often set it during triage
and end up disabling the entire runtime pm instead (the option is not a
fine scalpel!).

Furthermore, it allows users to set known dangerous values which were
intended for testing and not for production use. For testing, we can
always patch in the required setting without having to expose ourselves
to random abuse.

v2: Fixup NEEDS_WaRsDisableCoarsePowerGating fumble, and document the
lack of ilk support better.
v3: Clear intel_info->rc6p if we don't support rc6 itself.

Signed-off-by: Chris Wilson 
Cc: Rodrigo Vivi 
Cc: Joonas Lahtinen 
Cc: Jani Nikula 
Cc: Imre Deak 
Cc: Daniel Vetter 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_drv.c |   2 +-
 drivers/gpu/drm/i915/i915_drv.h |   1 +
 drivers/gpu/drm/i915/i915_params.c  |   7 --
 drivers/gpu/drm/i915/i915_params.h  |   1 -
 drivers/gpu/drm/i915/i915_pci.c |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c   |  13 +++-
 drivers/gpu/drm/i915/intel_drv.h|   5 --
 drivers/gpu/drm/i915/intel_guc.c|   3 +-
 drivers/gpu/drm/i915/intel_pm.c | 134 +++-
 drivers/gpu/drm/i915/intel_uncore.c |   3 -
 10 files changed, 57 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 36fc99324b9d..81c68494d712 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2500,7 +2500,7 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
 
-   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled(
+   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv
return -ENODEV;
 
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 24ce5d89e07e..0c10f442977a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3210,6 +3210,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_PSR(dev_priv)   ((dev_priv)->info.has_psr)
 #define HAS_RC6(dev_priv)   ((dev_priv)->info.has_rc6)
 #define HAS_RC6p(dev_priv)  ((dev_priv)->info.has_rc6p)
+#define HAS_RC6pp(dev_priv) (false)
 
 #define HAS_CSR(dev_priv)  ((dev_priv)->info.has_csr)
 
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 3328147b4863..7bc538687871 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,13 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600,
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
-i915_param_named_unsafe(enable_rc6, int, 0400,
-   "Enable power-saving render C-state 6. "
-   "Different stages can be selected via bitmask values "
-   "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest 
rc6). "
-   "For example, 3 would enable rc6 and deep rc6, and 7 would enable 
everything. "
-   "default: -1 (use per-chip default)");
-
 i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 8321bd86cba5..c48c88bb95e8 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -34,7 +34,6 @@
param(int, lvds_channel_mode, 0) \
param(int, panel_use_ssc, -1) \
param(int, vbt_sdvo_panel_type, -1) \
-   param(int, enable_rc6, -1) \
param(int, enable_dc, -1) \
param(int, enable_fbc, -1) \
param(int, enable_ppgtt, -1) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6458c309c039..f1c6756440a9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -216,6 +216,9 @@ static const struct intel_device_info intel_gm45_info 
__initconst = {
 static const struct intel_device_info intel_ironlake_d_info __initconst = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
+   /* ilk does support rc6, but we do not implement [power] contexts */
+   .has_rc6 = 0,
+
 };
 
 static const struct intel_device_info intel_ironlake_m_info __initconst = {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 791759f632e1..1c95c2167d10 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ 

[Intel-gfx] [CI 21/21] drm/i915: Enable rc6 for Ironlake

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_pci.c |  3 +--
 drivers/gpu/drm/i915/intel_pm.c | 28 
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f1c6756440a9..e0458dff0371 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -216,8 +216,7 @@ static const struct intel_device_info intel_gm45_info 
__initconst = {
 static const struct intel_device_info intel_ironlake_d_info __initconst = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
-   /* ilk does support rc6, but we do not implement [power] contexts */
-   .has_rc6 = 0,
+   .has_rc6 = true,
 
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1d46b7ed2cf..345127b55afd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6378,6 +6378,30 @@ static void gen9_disable_rps(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
+static void gen5_enable_rc6(struct drm_i915_private *dev_priv)
+{
+   u32 offset =
+   i915_ggtt_offset(dev_priv->kernel_context->engine[RCS].state);
+
+   I915_WRITE(PWRCTXA, offset | PWRCTX_EN);
+   I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+}
+
+static void gen5_disable_rc6(struct drm_i915_private *dev_priv)
+{
+   /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
+   I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
+   intel_wait_for_register(dev_priv,
+   RSTDBYCTL,
+   RSX_STATUS_MASK, RSX_STATUS_ON,
+   50);
+   I915_WRITE(PWRCTXA, 0);
+   POSTING_READ(PWRCTXA);
+
+   I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+   POSTING_READ(RSTDBYCTL);
+}
+
 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
 {
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7982,6 +8006,8 @@ static void intel_disable_rc6(struct drm_i915_private 
*dev_priv)
valleyview_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 5)
+   gen5_disable_rc6(dev_priv);
 
dev_priv->gt_pm.rc6.enabled = false;
 }
@@ -8048,6 +8074,8 @@ static void intel_enable_rc6(struct drm_i915_private 
*dev_priv)
gen8_enable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_enable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 5)
+   gen5_enable_rc6(dev_priv);
 
dev_priv->gt_pm.rc6.enabled = true;
 }
-- 
2.15.0

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[Intel-gfx] [CI 19/21] drm/i915: Add is-wedged flag to intel_engine_dump()

[Chris Wilson]

Comparing the state tested by intel_engine_is_idle() and printed by
intel_engine_dump(), the only bit not shown is whether or not the device
is wedged. Add that little bit of information to the pretty printer so
that if the engine fails to idle we can see why.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e3070199e7df..21290e62699d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1676,6 +1676,9 @@ void intel_engine_dump(struct intel_engine_cs *engine,
va_end(ap);
}
 
+   if (i915_terminally_wedged(>i915->gpu_error))
+   drm_printf(m, "*** WEDGED ***\n");
+
drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
-- 
2.15.0

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[Intel-gfx] [CI 09/21] drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info

[Chris Wilson]

As the semaphores is just part of the engine, include it with the
general pretty printer universally used for debugging.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 32 
 drivers/gpu/drm/i915/intel_engine_cs.c |  9 +
 2 files changed, 9 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9cef1463d411..41d49a4d25d3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3235,37 +3235,6 @@ static int i915_shrinker_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static int i915_semaphore_status(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   int num_rings = INTEL_INFO(dev_priv)->num_rings;
-   enum intel_engine_id id;
-   int j, ret;
-
-   if (!i915_modparams.semaphores) {
-   seq_puts(m, "Semaphores are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-   intel_runtime_pm_get(dev_priv);
-
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-
-   intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
-   return 0;
-}
-
 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4745,7 +4714,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
-   {"i915_semaphore_status", i915_semaphore_status, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1fca7ac3b059..ef8e101ebd98 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1713,6 +1713,15 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
   I915_READ(RING_MI_MODE(engine->mmio_base)),
   I915_READ(RING_MI_MODE(engine->mmio_base)) & 
(MODE_IDLE) ? " [idle]" : "");
}
+   if (i915_modparams.semaphores) {
+   drm_printf(m, "\tSYNC_0: 0x%08x\n",
+  I915_READ(RING_SYNC_0(engine->mmio_base)));
+   drm_printf(m, "\tSYNC_1: 0x%08x\n",
+  I915_READ(RING_SYNC_1(engine->mmio_base)));
+   if (HAS_VEBOX(dev_priv))
+   drm_printf(m, "\tSYNC_2: 0x%08x\n",
+  I915_READ(RING_SYNC_2(engine->mmio_base)));
+   }
 
rcu_read_unlock();
 
-- 
2.15.0

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[Intel-gfx] [CI 08/21] drm/i915: Disable semaphores on Sandybridge

[Chris Wilson]

I should have admitted defeat long ago as there has been a rare but
persistent error on Sandybridge where semaphore signaling did not
propagate to the waiter, leading to a GPU hang.

With the work on fence signaling for v4.9, the impact of using CPU driven
signaling was greatly reduced wrt to the latency of GPU semaphores,
though without logical rings support, the benefit of reordering work to
avoid bubbles is not realised (i.e. as it stands fence signaling is just
a slower, more costly version of HW semaphores; but works more
consistently). As a rough indicator of the difference,

with semaphores:
Sequential (3 engines, 1 processes): average 5.470us per cycle [expected 
4.988us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 15.771us per cycle [expected 
4.923us]

In comparison, v3.4:
with semaphores:
Sequential (3 engines, 1 processes): average 16.066us per cycle [expected 
11.842us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 23.460us per cycle [expected 
11.839us]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54226 #and 100+ dupes
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Acked-by: Mika Kuoppala 
Reviewed-by: Joonas Lahtinen = 0)
return value;
 
-   /* Enable semaphores on SNB when IO remapping is off */
-   if (IS_GEN6(dev_priv) && intel_vtd_active())
-   return false;
-
return true;
 }
 
-- 
2.15.0

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[Intel-gfx] [CI 10/21] drm/i915: Remove i915.semaphores modparam

[Chris Wilson]

Having disabled the broken semaphores on Sandybridge, there is no need
for a modparam any more, so remove it in favour of a simple
HAS_LEGACY_SEMAPHORES() guard.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Maarten Lankhorst 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c |  7 +--
 drivers/gpu/drm/i915/i915_drv.h |  4 ++--
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  4 ++--
 8 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 779a6f0785c7..36fc99324b9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,7 +321,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = USES_PPGTT(dev_priv);
break;
case I915_PARAM_HAS_SEMAPHORES:
-   value = i915_modparams.semaphores;
+   value = HAS_LEGACY_SEMAPHORES(dev_priv);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
@@ -1066,11 +1066,6 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
i915_modparams.enable_ppgtt);
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-   i915_modparams.semaphores =
-   intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
-   DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
-yesno(i915_modparams.semaphores));
-
intel_uc_sanitize_options(dev_priv);
 
intel_gvt_sanitize_options(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 953867d9171e..24ce5d89e07e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3140,6 +3140,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_BLT(dev_priv)  HAS_ENGINE(dev_priv, BCS)
 #define HAS_VEBOX(dev_priv)HAS_ENGINE(dev_priv, VECS)
 
+#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
+
 #define HAS_LLC(dev_priv)  ((dev_priv)->info.has_llc)
 #define HAS_SNOOP(dev_priv)((dev_priv)->info.has_snoop)
 #define HAS_EDRAM(dev_priv)(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
@@ -3303,8 +3305,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
int enable_ppgtt);
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
-
 /* i915_drv.c */
 void __printf(3, 4)
 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d53bb8e872ba..792e6dc7e19b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4997,17 +4997,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
-{
-   if (!IS_GEN7(dev_priv))
-   return false;
-
-   if (value >= 0)
-   return value;
-
-   return true;
-}
-
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 {
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0704d9af261b..6ca56e482d79 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -574,7 +574,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags)
enum intel_engine_id id;
const int num_rings =
/* Use an extended w/a on gen7 if signalling from other rings */
-   (i915_modparams.semaphores && IS_GEN7(dev_priv)) ?
+   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
INTEL_INFO(dev_priv)->num_rings - 1 :
0;
int len;
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index d61c1787c164..3328147b4863 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,10 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600,
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
-i915_param_named_unsafe(semaphores, int, 0400,
-   "Use semaphores for inter-ring sync "
-   "(default: -1 (use per-chip defaults))");
-
 

[Intel-gfx] [CI 12/21] move-switch-ctx

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem_context.c | 197 
 drivers/gpu/drm/i915/intel_ringbuffer.c | 185 +-
 2 files changed, 184 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index f63bec08cc85..aee0f6d72d33 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -567,203 +567,6 @@ void i915_gem_context_close(struct drm_file *file)
idr_destroy(_priv->context_idr);
 }
 
-static inline int
-mi_set_context(struct drm_i915_gem_request *req, u32 flags)
-{
-   struct drm_i915_private *dev_priv = req->i915;
-   struct intel_engine_cs *engine = req->engine;
-   enum intel_engine_id id;
-   const int num_rings =
-   /* Use an extended w/a on gen7 if signalling from other rings */
-   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
-   INTEL_INFO(dev_priv)->num_rings - 1 :
-   0;
-   int len;
-   u32 *cs;
-
-   flags |= MI_MM_SPACE_GTT;
-   if (IS_HASWELL(dev_priv))
-   /* These flags are for resource streamer on HSW+ */
-   flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
-   else
-   flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
-
-   len = 4;
-   if (IS_GEN7(dev_priv))
-   len += 2 + (num_rings ? 4*num_rings + 6 : 0);
-
-   cs = intel_ring_begin(req, len);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
-   if (IS_GEN7(dev_priv)) {
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   *cs++ = i915_mmio_reg_offset(
-  RING_PSMI_CTL(signaller->mmio_base));
-   *cs++ = _MASKED_BIT_ENABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-   }
-   }
-
-   *cs++ = MI_NOOP;
-   *cs++ = MI_SET_CONTEXT;
-   *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
-   /*
-* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
-* WaMiSetContext_Hang:snb,ivb,vlv
-*/
-   *cs++ = MI_NOOP;
-
-   if (IS_GEN7(dev_priv)) {
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-   i915_reg_t last_reg = {}; /* keep gcc quiet */
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   last_reg = RING_PSMI_CTL(signaller->mmio_base);
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = _MASKED_BIT_DISABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-
-   /* Insert a delay before the next switch! */
-   *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = i915_ggtt_offset(engine->scratch);
-   *cs++ = MI_NOOP;
-   }
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-   }
-
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-static int remap_l3(struct drm_i915_gem_request *req, int slice)
-{
-   u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
-   int i;
-
-   if (!remap_info)
-   return 0;
-
-   cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /*
-* Note: We do not worry about the concurrent register cacheline hang
-* here because no other code should access these registers other than
-* at initialization time.
-*/
-   *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
-   for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
-   *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
-   *cs++ = remap_info[i];
-   }
-   *cs++ = MI_NOOP;
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-/**
- * i915_switch_context() - perform a GPU context switch.
- * @rq: request for which we'll execute the context switch
- *
- * The context life cycle is simple. The context refcount is 

[Intel-gfx] [CI 04/21] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..b7895788bc75 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return 0;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] [CI 06/21] drm/i915: Remove i915.enable_execlists module parameter

[Chris Wilson]

Execlists and legacy ringbuffer submission are no longer feature
comparable (execlists now offer greater functionality that should
overcome their performance hit) and obsoletes the unsafe module
parameter, i.e. comparing the two modes of execution is no longer
useful, so remove the debug tool.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Lionel Landwerlin  #i915_perf.c
---
 drivers/gpu/drm/i915/gvt/render.c   |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c | 70 -
 drivers/gpu/drm/i915/i915_drv.c |  8 +---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++
 drivers/gpu/drm/i915/i915_gem.c | 10 ++---
 drivers/gpu/drm/i915/i915_gem_context.c | 10 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 --
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/i915_perf.c|  8 ++--
 drivers/gpu/drm/i915/intel_engine_cs.c  |  8 ++--
 drivers/gpu/drm/i915/intel_gvt.c|  5 ---
 drivers/gpu/drm/i915/intel_lrc.c| 31 ---
 drivers/gpu/drm/i915/intel_lrc.h|  4 --
 14 files changed, 20 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 0672178548ef..dac12c25f349 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -294,8 +294,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, 
int ring_id)
 * write.
 */
if (mmio->in_context &&
-   ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-   i915_modparams.enable_execlists)
+   (ctx_ctrl & inhibit_mask) != inhibit_mask)
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index df3852c02a35..5e2a6e18771f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1989,75 +1989,6 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static void i915_dump_lrc_obj(struct seq_file *m,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
-   struct i915_vma *vma = ctx->engine[engine->id].state;
-   struct page *page;
-   int j;
-
-   seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
-
-   if (!vma) {
-   seq_puts(m, "\tFake context\n");
-   return;
-   }
-
-   if (vma->flags & I915_VMA_GLOBAL_BIND)
-   seq_printf(m, "\tBound in GGTT at 0x%08x\n",
-  i915_ggtt_offset(vma));
-
-   if (i915_gem_object_pin_pages(vma->obj)) {
-   seq_puts(m, "\tFailed to get pages for context object\n\n");
-   return;
-   }
-
-   page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
-   if (page) {
-   u32 *reg_state = kmap_atomic(page);
-
-   for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
-   seq_printf(m,
-  "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-  j * 4,
-  reg_state[j], reg_state[j + 1],
-  reg_state[j + 2], reg_state[j + 3]);
-   }
-   kunmap_atomic(reg_state);
-   }
-
-   i915_gem_object_unpin_pages(vma->obj);
-   seq_putc(m, '\n');
-}
-
-static int i915_dump_lrc(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   struct i915_gem_context *ctx;
-   enum intel_engine_id id;
-   int ret;
-
-   if (!i915_modparams.enable_execlists) {
-   seq_printf(m, "Logical Ring Contexts are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   list_for_each_entry(ctx, _priv->contexts.list, link)
-   for_each_engine(engine, dev_priv, id)
-   i915_dump_lrc_obj(m, ctx, engine);
-
-   mutex_unlock(>struct_mutex);
-
-   return 0;
-}
-
 static const char *swizzle_string(unsigned swizzle)
 {
switch (swizzle) {
@@ -4833,7 +4764,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_vbt", i915_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
-   {"i915_dump_lrc", i915_dump_lrc, 0},
{"i915_forcewake_domains", i915_forcewake_domains, 0},

[Intel-gfx] [CI 05/21] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   |  4 
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 10 +++---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  6 --
 10 files changed, 14 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b7895788bc75..14d9e61a1e06 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 91eae1b20c42..86e2346357cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00be015e01df..d8952ff8e6b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private 

[Intel-gfx] [CI 13/21] drm/i915: Enable render context support for Ironlake

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 22c095035539..f2dfa3f9fbdf 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -29,6 +29,8 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
+#define GEN5_CXT_TOTAL_SIZE( 1 * PAGE_SIZE)
+
 /* Haswell does have the CXT_SIZE register however it does not appear to be
  * valid. Now, docs explain in dwords what is in the context object. The full
  * size is 70720 bytes, however, the power context and execlist context will
@@ -175,6 +177,7 @@ __intel_engine_context_size(struct drm_i915_private 
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+   return GEN5_CXT_TOTAL_SIZE;
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index deb3cc7e08a8..d0c2dcb4c7ee 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1408,6 +1408,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
len = 4;
if (IS_GEN7(i915))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+   if (IS_GEN5(i915))
+   len += 2;
 
cs = intel_ring_begin(rq, len);
if (IS_ERR(cs))
@@ -1430,6 +1432,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
 
*cs++ = MI_NOOP;
@@ -1463,7 +1467,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
*cs++ = i915_ggtt_offset(engine->scratch);
*cs++ = MI_NOOP;
}
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH;
}
 
intel_ring_advance(rq, cs);
-- 
2.15.0

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[Intel-gfx] [CI 16/21] drm/i915: Make engine state pretty-printer header configurable

[Chris Wilson]

Pass in a format string (and args) to specify the header to be emitted
along with the engine state when pretty-printing. This allows the header
to be emitted inside the drm_printer stream, so sharing the same prefix
and output characteristics (e.g. debug level and filtering).

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   | 15 ---
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  5 -
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c |  7 ---
 4 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 41d49a4d25d3..823fc6a74b98 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3218,7 +3218,7 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
 
p = drm_seq_file_printer(m);
for_each_engine(engine, dev_priv, id)
-   intel_engine_dump(engine, );
+   intel_engine_dump(engine, , "%s\n", engine->name);
 
intel_runtime_pm_put(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 959064607fb4..e51e90270d31 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1585,7 +1585,7 @@ void intel_engines_park(struct drm_i915_private *i915)
dev_err(i915->drm.dev,
"%s is not idle before parking\n",
engine->name);
-   intel_engine_dump(engine, );
+   intel_engine_dump(engine, , NULL);
}
 
if (engine->park)
@@ -1655,7 +1655,9 @@ static void print_request(struct drm_printer *m,
   rq->timeline->common->name);
 }
 
-void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m)
+void intel_engine_dump(struct intel_engine_cs *engine,
+  struct drm_printer *m,
+  const char *header, ...)
 {
struct intel_breadcrumbs * const b = >breadcrumbs;
const struct intel_engine_execlists * const execlists = 
>execlists;
@@ -1666,7 +1668,14 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
char hdr[80];
u64 addr;
 
-   drm_printf(m, "%s\n", engine->name);
+   if (header) {
+   va_list ap;
+
+   va_start(ap, header);
+   drm_vprintf(m, header, );
+   va_end(ap);
+   }
+
drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbc9c36f675e..41ac69dbe554 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -926,6 +926,9 @@ unsigned int intel_engines_has_context_isolation(struct 
drm_i915_private *i915);
 
 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
 
-void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p);
+__printf(3, 4)
+void intel_engine_dump(struct intel_engine_cs *engine,
+  struct drm_printer *m,
+  const char *header, ...);
 
 #endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index f91e8c3e4ad8..8b51bf2becf1 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -618,7 +618,7 @@ static int igt_wait_reset(void *arg)
 
pr_err("Failed to start request %x, at %x\n",
   rq->fence.seqno, hws_seqno(, rq));
-   intel_engine_dump(rq->engine, );
+   intel_engine_dump(rq->engine, , "%s\n", rq->engine->name);
 
i915_reset(i915, 0);
i915_gem_set_wedged(i915);
@@ -713,7 +713,8 @@ static int igt_reset_queue(void *arg)
 
pr_err("Failed to start request %x, at %x\n",
   prev->fence.seqno, hws_seqno(, prev));
-   intel_engine_dump(rq->engine, );
+   intel_engine_dump(prev->engine, ,
+ "%s\n", prev->engine->name);
 
i915_gem_request_put(rq);
i915_gem_request_put(prev);
@@ -819,7 +820,7 @@ static int igt_handle_error(void *arg)
 
pr_err("Failed to start request %x, at %x\n",
   rq->fence.seqno, hws_seqno(, rq));
-   

[Intel-gfx] [CI 15/21] drm/i915: Use snprintf to avoid line-break when pretty-printing engines

[Chris Wilson]

When printing the execlist ports, we first print the ELSP header then
follow it with the pretty-printed request. Since switching to
drm_printer and show the output via printk, it automatically appends a
newline to each call (unlike the old seq_printf output). To avoid the
unwanted line break, construct the ELSP request header in a temporary
buffer.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index f2dfa3f9fbdf..959064607fb4 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1663,6 +1663,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_gem_request *rq;
struct rb_node *rb;
+   char hdr[80];
u64 addr;
 
drm_printf(m, "%s\n", engine->name);
@@ -1775,12 +1776,12 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
 
rq = port_unpack(>port[idx], );
if (rq) {
-   drm_printf(m, "\t\tELSP[%d] count=%d, ",
-  idx, count);
-   print_request(m, rq, "rq: ");
+   snprintf(hdr, sizeof(hdr),
+"\t\tELSP[%d] count=%d, rq: ",
+idx, count);
+   print_request(m, rq, hdr);
} else {
-   drm_printf(m, "\t\tELSP[%d] idle\n",
-  idx);
+   drm_printf(m, "\t\tELSP[%d] idle\n", idx);
}
}
drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
-- 
2.15.0

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[Intel-gfx] [CI 18/21] drm/i915: Include the global reset count for intel_engine_dump()

[Chris Wilson]

Since a global reset affects the engine, include that along side the
per-engine reset counter when pretty printing the engine state in
intel_engine_dump().

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index b4282ac6a4a7..e3070199e7df 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1682,8 +1682,9 @@ void intel_engine_dump(struct intel_engine_cs *engine,
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
   engine->timeline->inflight_seqnos);
-   drm_printf(m, "\tReset count: %d\n",
-  i915_reset_engine_count(error, engine));
+   drm_printf(m, "\tReset count: %d (global %d)\n",
+  i915_reset_engine_count(error, engine),
+  i915_reset_count(error));
 
rcu_read_lock();
 
-- 
2.15.0

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[Intel-gfx] [CI 11/21] drm/i915: Unwind incomplete legacy context switches

[Chris Wilson]

The legacy context switch for ringbuffer submission is multistaged,
where each of those stages may fail. However, we were updating global
state after some stages, and so we had to force the incomplete request
to be submitted because we could not unwind. Save the global state
before performing the switches, and so enable us to unwind back to the
previous global state should any phase fail. We then must cancel the
request instead of submitting it should the construction fail.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 168 ++--
 drivers/gpu/drm/i915/i915_gem_request.c |  18 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 4 files changed, 62 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 6ca56e482d79..f63bec08cc85 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -507,6 +507,7 @@ void i915_gem_contexts_lost(struct drm_i915_private 
*dev_priv)
 
for_each_engine(engine, dev_priv, id) {
engine->legacy_active_context = NULL;
+   engine->legacy_active_ppgtt = NULL;
 
if (!engine->last_retired_context)
continue;
@@ -681,68 +682,48 @@ static int remap_l3(struct drm_i915_gem_request *req, int 
slice)
return 0;
 }
 
-static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
-  struct intel_engine_cs *engine,
-  struct i915_gem_context *to)
-{
-   if (to->remap_slice)
-   return false;
-
-   if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   return to == engine->legacy_active_context;
-}
-
-static bool
-needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine)
-{
-   struct i915_gem_context *from = engine->legacy_active_context;
-
-   if (!ppgtt)
-   return false;
-
-   /* Always load the ppgtt on first use */
-   if (!from)
-   return true;
-
-   /* Same context without new entries, skip */
-   if ((!from->ppgtt || from->ppgtt == ppgtt) &&
-   !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   if (engine->id != RCS)
-   return true;
-
-   return true;
-}
-
-static int do_rcs_switch(struct drm_i915_gem_request *req)
+/**
+ * i915_switch_context() - perform a GPU context switch.
+ * @rq: request for which we'll execute the context switch
+ *
+ * The context life cycle is simple. The context refcount is incremented and
+ * decremented by 1 and create and destroy. If the context is in use by the 
GPU,
+ * it will have a refcount > 1. This allows us to destroy the context abstract
+ * object while letting the normal object tracking destroy the backing BO.
+ *
+ * This function should not be used in execlists mode.  Instead the context is
+ * switched by writing to the ELSP and requests keep a reference to their
+ * context.
+ */
+int i915_switch_context(struct drm_i915_gem_request *rq)
 {
-   struct i915_gem_context *to = req->ctx;
-   struct intel_engine_cs *engine = req->engine;
-   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
-   struct i915_gem_context *from = engine->legacy_active_context;
-   u32 hw_flags;
+   struct intel_engine_cs *engine = rq->engine;
+   struct i915_gem_context *to = rq->ctx;
+   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
+   struct i915_gem_context *saved_ctx = engine->legacy_active_context;
+   struct i915_hw_ppgtt *saved_mm = engine->legacy_active_ppgtt;
+   u32 hw_flags = 0;
int ret, i;
 
-   GEM_BUG_ON(engine->id != RCS);
-
-   if (skip_rcs_switch(ppgtt, engine, to))
-   return 0;
+   lockdep_assert_held(>i915->drm.struct_mutex);
+   GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
-   if (needs_pd_load_pre(ppgtt, engine)) {
-   /* Older GENs and non render rings still want the load first,
-* "PP_DCLV followed by PP_DIR_BASE register through Load
-* Register Immediate commands in Ring Buffer before submitting
-* a context."*/
+   if (ppgtt != saved_mm ||
+   (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) {
trace_switch_mm(engine, to);
-   ret = ppgtt->switch_mm(ppgtt, req);
+   ret = ppgtt->switch_mm(ppgtt, rq);
if (ret)
-   return ret;
+   goto err;
+
+   ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
+   engine->legacy_active_ppgtt = ppgtt;
+   hw_flags = 

[Intel-gfx] [CI 14/21] drm/printer: Add drm_vprintf()

[Chris Wilson]

Simple va_args equivalent to the existing drm_printf() for use with the
drm_printer.

Signed-off-by: Chris Wilson 
Cc: Rob Clark 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_print.c |  5 +
 include/drm/drm_print.h | 15 +++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index 82ff327eb2df..781518fd88e3 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -55,13 +55,10 @@ EXPORT_SYMBOL(__drm_printfn_debug);
  */
 void drm_printf(struct drm_printer *p, const char *f, ...)
 {
-   struct va_format vaf;
va_list args;
 
va_start(args, f);
-   vaf.fmt = f;
-   vaf.va = 
-   p->printfn(p, );
+   drm_vprintf(p, f, );
va_end(args);
 }
 EXPORT_SYMBOL(drm_printf);
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 0968e411f562..e04d99cdc8d2 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -80,6 +80,21 @@ void __drm_printfn_debug(struct drm_printer *p, struct 
va_format *vaf);
 __printf(2, 3)
 void drm_printf(struct drm_printer *p, const char *f, ...);
 
+/*
+ * drm_vprintf - print to a _printer stream
+ * @p: the _printer
+ * @f: format string
+ * @args: the va_list
+ */
+__printf(2, 0)
+static inline void
+drm_vprintf(struct drm_printer *p, const char *fmt, va_list *va)
+{
+   struct va_format vaf = { .fmt = fmt, .va = va };
+
+   p->printfn(p, );
+}
+
 /**
  * drm_printf_indent - Print to a _printer stream with indentation
  * @printer: DRM printer
-- 
2.15.0

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[Intel-gfx] [CI 07/21] drm/i915: Remove obsolete ringbuffer emission for gen8+

[Chris Wilson]

Since removing the module parameter to force selection of ringbuffer
emission for gen8, the code is defunct. Remove it.

To put the difference into perspective, a couple of microbenchmarks
(bdw i7-5557u, 20170324):
ring  execlists
exec continuous nops on all rings:   1.491us2.223us
exec sequential nops on each ring:  12.508us   53.682us
single nop + sync:   9.272us   30.291us

vblank_mode=0 glxgears:~11000fps   ~9000fps

Since the earlier submission, gen8 ringbuffer submission has fallen
further and further behind in features. So while ringbuffer may hold the
throughput crown, in terms of interactive latency, execlists is much
better. Alas, we have no convenient metrics for such, other than
demonstrating things we can do with execlists but can not using
legacy ringbuffer submission.

We have made a few improvements to lowlevel execlists throughput,
and ringbuffer currently panics on boot! (bdw i7-5557u, 20171026):

ring  execlists
exec continuous nops on all rings:   n/a1.921us
exec sequential nops on each ring:   n/a   44.621us
single nop + sync:   n/a   21.953us

vblank_mode=0 glxgears:  n/a  ~18500fps

References: https://bugs.freedesktop.org/show_bug.cgi?id=87725
Signed-off-by: Chris Wilson 
Once-upon-a-time-Reviewed-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  44 +---
 drivers/gpu/drm/i915/i915_drv.h |   2 -
 drivers/gpu/drm/i915/i915_gem.c |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  47 +---
 drivers/gpu/drm/i915/i915_gpu_error.c   |  36 ---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  14 --
 drivers/gpu/drm/i915/intel_hangcheck.c  |  44 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 431 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  25 +-
 9 files changed, 94 insertions(+), 551 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5e2a6e18771f..9cef1463d411 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3254,44 +3254,12 @@ static int i915_semaphore_status(struct seq_file *m, 
void *unused)
return ret;
intel_runtime_pm_get(dev_priv);
 
-   if (IS_BROADWELL(dev_priv)) {
-   struct page *page;
-   uint64_t *seqno;
-
-   page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
-
-   seqno = (uint64_t *)kmap_atomic(page);
-   for_each_engine(engine, dev_priv, id) {
-   uint64_t offset;
-
-   seq_printf(m, "%s\n", engine->name);
-
-   seq_puts(m, "  Last signal:");
-   for (j = 0; j < num_rings; j++) {
-   offset = id * I915_NUM_ENGINES + j;
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   seq_puts(m, "  Last wait:  ");
-   for (j = 0; j < num_rings; j++) {
-   offset = id + (j * I915_NUM_ENGINES);
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   }
-   kunmap_atomic(seqno);
-   } else {
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  
I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-   }
+   seq_puts(m, "  Last signal:");
+   for_each_engine(engine, dev_priv, id)
+   for (j = 0; j < num_rings; j++)
+   seq_printf(m, "0x%08x\n",
+  I915_READ(engine->semaphore.mbox.signal[j]));
+   seq_putc(m, '\n');
 
intel_runtime_pm_put(dev_priv);
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a21544b62866..953867d9171e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -942,7 +942,6 @@ struct i915_gpu_state {
u64 fence[I915_MAX_NUM_FENCES];
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
-   struct drm_i915_error_object *semaphore;
 
struct drm_i915_error_engine {

[Intel-gfx] [CI 03/21] drm/i915/execlists: Skip a lite-restore immediately prior to a context-completion

[Chris Wilson]

If we are about to do another context-switch in the near future skip
doing performing a lite-restore now. (Forcing a lite-restore just before
a context-switch effectively doubles the cost of that context-switch, so
long as we can handle the interrupt and resubmit before the GPU powers
down, which under normal conditions is expected.)

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6191a2e59e8a..2edd57b3d53e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -628,6 +628,19 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
if (port_count([1]))
goto unlock;
 
+   /*
+* If we are about to do another context-switch in
+* the near future skip doing performing a lite-restore
+* now. (Forcing a lite-restore just before a
+* context-switch effectively doubles the cost of that
+* context-switch, so long as we can handle the
+* interrupt and resubmit before the GPU powers down,
+* which under normal conditions is expected.)
+*/
+   if (i915_seqno_passed(intel_engine_get_seqno(engine),
+ last->global_seqno - 1))
+   goto unlock;
+
/* WaIdleLiteRestore:bdw,skl
 * Apply the wa NOOPs to prevent
 * ring:HEAD == req:TAIL as we resubmit the
-- 
2.15.0

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[Intel-gfx] [CI 02/21] drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write

[Chris Wilson]

The hardware needs some time to process the information received in the
ExecList Submission Port, and expects us to don't write anything new until
it has 'acknowledged' this new execlist by sending an IDLE_ACTIVE or
PREEMPTED CSB event.

If we do not follow this, the driver could write new data into the ELSP
before HW had finishing fetching the previous one, putting us in
'undefined behaviour' space.

This seems to be the problem causing the spurious PREEMPTED & COMPLETE
events after a COMPLETE like the one below:

[] vcs0: sw rd pointer = 2, hw wr pointer = 0, current 'head' = 3.
[] vcs0:  Execlist CSB[0]: 0x0018 _ 0x0007
[] vcs0:  Execlist CSB[1]: 0x0001 _ 0x
[] vcs0:  Execlist CSB[2]: 0x0018 _ 0x0007  <<< COMPLETE
[] vcs0:  Execlist CSB[3]: 0x0012 _ 0x0007  <<< PREEMPTED & COMPLETE
[] vcs0:  Execlist CSB[4]: 0x8002 _ 0x0006
[] vcs0:  Execlist CSB[5]: 0x0014 _ 0x0006

The ELSP writes that lead to this CSB sequence show that the HW hadn't
started executing the previous execlist (the one with only ctx 0x6) by the
time the new one was submitted; this is a bit more clear in the data
show in the EXECLIST_STATUS register at the time of the ELSP write.

[] vcs0: ELSP[0] = 0x0_0[execlist1] - status_reg = 0x0_302
[] vcs0: ELSP[1] = 0x6_fedb2119 [execlist0] - status_reg = 0x0_8302

[] vcs0: ELSP[2] = 0x7_fedaf119 [execlist1] - status_reg = 0x0_8308
[] vcs0: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308

Note that having to wait for this ack does not disable lite-restores,
although it may reduce their numbers.

v2: Rewrote Michel's patch, his digging and his fix, my spelling.
v3: Reorder to ack early to allow preemption

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Suggested-by: Michel Thierry 
Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c| 22 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2cfdfdc0722..6191a2e59e8a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -479,6 +479,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
elsp_write(desc, elsp);
}
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
@@ -531,6 +532,7 @@ static void inject_preempt_context(struct intel_engine_cs 
*engine)
elsp_write(0, elsp);
 
elsp_write(ce->lrc_desc, elsp);
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static void execlists_dequeue(struct intel_engine_cs *engine)
@@ -577,9 +579,20 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * know the next preemption status we see corresponds
 * to this ELSP update.
 */
+   GEM_BUG_ON(!port_count([0]));
if (port_count([0]) > 1)
goto unlock;
 
+   /*
+* If we write to ELSP a second time before the HW has had
+* a chance to respond to the previous write, we can confuse
+* the HW and hit "undefined behaviour". After writing to ELSP,
+* we must then wait until we see a context-switch event from
+* the HW to indicate that it has had a chance to respond.
+*/
+   if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
+   goto unlock;
+
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) &&
rb_entry(rb, struct i915_priolist, node)->priority >
max(last->priotree.priority, 0)) {
@@ -873,6 +886,15 @@ static void execlists_submission_tasklet(unsigned long 
data)
GEM_TRACE("%s csb[%dd]: status=0x%08x:0x%08x\n",
  engine->name, head,
  status, buf[2*head + 1]);
+
+   if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
+ GEN8_CTX_STATUS_PREEMPTED))
+   execlists_set_active(execlists,
+EXECLISTS_ACTIVE_HWACK);
+   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
+   execlists_clear_active(execlists,
+  EXECLISTS_ACTIVE_HWACK);
+
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f867aa6c31fc..add7a30c1a61 100644
--- 

[Intel-gfx] [CI 01/21] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Since commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c
Author: Oscar Mateo 
Date:   Thu Jul 24 17:04:40 2014 +0100

drm/i915/bdw: Avoid non-lite-restore preemptions

execlists has listened to (ACTIVE_IDLE | ELEMENT_SWITCH) for detecting
when one context completed and it either continued onto the next (in port
1) or idled. We would always see COMPLETE | ACTIVE_IDLE on the final
context-switch event, but on recent gen it appears that we now get
separate ACTIVE_IDLE and COMPLETE events. In particular, the ACTIVE_IDLE
events may not be coupled to a context (since it is a general state rather
than a specific context completion event).

v2: Update the history, execlists did originally start out by listening
to the COMPLETE event not ACTIVE_IDLE.
v3: Update preempt completion test to also use COMPLETE not ACTIVE_IDLE.

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Acked-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..c2cfdfdc0722 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
 #define GEN8_CTX_STATUS_LITE_RESTORE   (1 << 15)
 
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
 
@@ -876,7 +876,7 @@ static void execlists_submission_tasklet(unsigned long data)
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
-   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE &&
+   if (status & GEN8_CTX_STATUS_COMPLETE &&
buf[2*head + 1] == PREEMPT_ID) {
execlists_cancel_port_requests(execlists);
execlists_unwind_incomplete_requests(execlists);
-- 
2.15.0

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[Intel-gfx] [CI 11/13] drm/i915: Unwind incomplete legacy context switches

[Chris Wilson]

The legacy context switch for ringbuffer submission is multistaged,
where each of those stages may fail. However, we were updating global
state after some stages, and so we had to force the incomplete request
to be submitted because we could not unwind. Save the global state
before performing the switches, and so enable us to unwind back to the
previous global state should any phase fail. We then must cancel the
request instead of submitting it should the construction fail.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 168 ++--
 drivers/gpu/drm/i915/i915_gem_request.c |  18 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |   1 +
 4 files changed, 62 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 6ca56e482d79..f63bec08cc85 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -507,6 +507,7 @@ void i915_gem_contexts_lost(struct drm_i915_private 
*dev_priv)
 
for_each_engine(engine, dev_priv, id) {
engine->legacy_active_context = NULL;
+   engine->legacy_active_ppgtt = NULL;
 
if (!engine->last_retired_context)
continue;
@@ -681,68 +682,48 @@ static int remap_l3(struct drm_i915_gem_request *req, int 
slice)
return 0;
 }
 
-static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
-  struct intel_engine_cs *engine,
-  struct i915_gem_context *to)
-{
-   if (to->remap_slice)
-   return false;
-
-   if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   return to == engine->legacy_active_context;
-}
-
-static bool
-needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine)
-{
-   struct i915_gem_context *from = engine->legacy_active_context;
-
-   if (!ppgtt)
-   return false;
-
-   /* Always load the ppgtt on first use */
-   if (!from)
-   return true;
-
-   /* Same context without new entries, skip */
-   if ((!from->ppgtt || from->ppgtt == ppgtt) &&
-   !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
-   return false;
-
-   if (engine->id != RCS)
-   return true;
-
-   return true;
-}
-
-static int do_rcs_switch(struct drm_i915_gem_request *req)
+/**
+ * i915_switch_context() - perform a GPU context switch.
+ * @rq: request for which we'll execute the context switch
+ *
+ * The context life cycle is simple. The context refcount is incremented and
+ * decremented by 1 and create and destroy. If the context is in use by the 
GPU,
+ * it will have a refcount > 1. This allows us to destroy the context abstract
+ * object while letting the normal object tracking destroy the backing BO.
+ *
+ * This function should not be used in execlists mode.  Instead the context is
+ * switched by writing to the ELSP and requests keep a reference to their
+ * context.
+ */
+int i915_switch_context(struct drm_i915_gem_request *rq)
 {
-   struct i915_gem_context *to = req->ctx;
-   struct intel_engine_cs *engine = req->engine;
-   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
-   struct i915_gem_context *from = engine->legacy_active_context;
-   u32 hw_flags;
+   struct intel_engine_cs *engine = rq->engine;
+   struct i915_gem_context *to = rq->ctx;
+   struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
+   struct i915_gem_context *saved_ctx = engine->legacy_active_context;
+   struct i915_hw_ppgtt *saved_mm = engine->legacy_active_ppgtt;
+   u32 hw_flags = 0;
int ret, i;
 
-   GEM_BUG_ON(engine->id != RCS);
-
-   if (skip_rcs_switch(ppgtt, engine, to))
-   return 0;
+   lockdep_assert_held(>i915->drm.struct_mutex);
+   GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
-   if (needs_pd_load_pre(ppgtt, engine)) {
-   /* Older GENs and non render rings still want the load first,
-* "PP_DCLV followed by PP_DIR_BASE register through Load
-* Register Immediate commands in Ring Buffer before submitting
-* a context."*/
+   if (ppgtt != saved_mm ||
+   (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) {
trace_switch_mm(engine, to);
-   ret = ppgtt->switch_mm(ppgtt, req);
+   ret = ppgtt->switch_mm(ppgtt, rq);
if (ret)
-   return ret;
+   goto err;
+
+   ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
+   engine->legacy_active_ppgtt = ppgtt;
+   hw_flags = 

[Intel-gfx] [CI 13/13] drm/i915: Enable render context support for Ironlake

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 22c095035539..f2dfa3f9fbdf 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -29,6 +29,8 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
+#define GEN5_CXT_TOTAL_SIZE( 1 * PAGE_SIZE)
+
 /* Haswell does have the CXT_SIZE register however it does not appear to be
  * valid. Now, docs explain in dwords what is in the context object. The full
  * size is 70720 bytes, however, the power context and execlist context will
@@ -175,6 +177,7 @@ __intel_engine_context_size(struct drm_i915_private 
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+   return GEN5_CXT_TOTAL_SIZE;
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index deb3cc7e08a8..d0c2dcb4c7ee 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1408,6 +1408,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
len = 4;
if (IS_GEN7(i915))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+   if (IS_GEN5(i915))
+   len += 2;
 
cs = intel_ring_begin(rq, len);
if (IS_ERR(cs))
@@ -1430,6 +1432,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
 
*cs++ = MI_NOOP;
@@ -1463,7 +1467,8 @@ static inline int mi_set_context(struct 
drm_i915_gem_request *rq, u32 flags)
*cs++ = i915_ggtt_offset(engine->scratch);
*cs++ = MI_NOOP;
}
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+   } else if (IS_GEN5(i915)) {
+   *cs++ = MI_SUSPEND_FLUSH;
}
 
intel_ring_advance(rq, cs);
-- 
2.15.0

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[Intel-gfx] [CI 09/13] drm/i915: Move debugfs/i915_semaphore_status to i915_engine_info

[Chris Wilson]

As the semaphores is just part of the engine, include it with the
general pretty printer universally used for debugging.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 32 
 drivers/gpu/drm/i915/intel_engine_cs.c |  9 +
 2 files changed, 9 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9cef1463d411..41d49a4d25d3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3235,37 +3235,6 @@ static int i915_shrinker_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static int i915_semaphore_status(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   int num_rings = INTEL_INFO(dev_priv)->num_rings;
-   enum intel_engine_id id;
-   int j, ret;
-
-   if (!i915_modparams.semaphores) {
-   seq_puts(m, "Semaphores are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-   intel_runtime_pm_get(dev_priv);
-
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-
-   intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
-   return 0;
-}
-
 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4745,7 +4714,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
-   {"i915_semaphore_status", i915_semaphore_status, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1fca7ac3b059..ef8e101ebd98 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1713,6 +1713,15 @@ void intel_engine_dump(struct intel_engine_cs *engine, 
struct drm_printer *m)
   I915_READ(RING_MI_MODE(engine->mmio_base)),
   I915_READ(RING_MI_MODE(engine->mmio_base)) & 
(MODE_IDLE) ? " [idle]" : "");
}
+   if (i915_modparams.semaphores) {
+   drm_printf(m, "\tSYNC_0: 0x%08x\n",
+  I915_READ(RING_SYNC_0(engine->mmio_base)));
+   drm_printf(m, "\tSYNC_1: 0x%08x\n",
+  I915_READ(RING_SYNC_1(engine->mmio_base)));
+   if (HAS_VEBOX(dev_priv))
+   drm_printf(m, "\tSYNC_2: 0x%08x\n",
+  I915_READ(RING_SYNC_2(engine->mmio_base)));
+   }
 
rcu_read_unlock();
 
-- 
2.15.0

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[Intel-gfx] [CI 12/13] move-switch-ctx

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem_context.c | 197 
 drivers/gpu/drm/i915/intel_ringbuffer.c | 185 +-
 2 files changed, 184 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index f63bec08cc85..aee0f6d72d33 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -567,203 +567,6 @@ void i915_gem_context_close(struct drm_file *file)
idr_destroy(_priv->context_idr);
 }
 
-static inline int
-mi_set_context(struct drm_i915_gem_request *req, u32 flags)
-{
-   struct drm_i915_private *dev_priv = req->i915;
-   struct intel_engine_cs *engine = req->engine;
-   enum intel_engine_id id;
-   const int num_rings =
-   /* Use an extended w/a on gen7 if signalling from other rings */
-   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
-   INTEL_INFO(dev_priv)->num_rings - 1 :
-   0;
-   int len;
-   u32 *cs;
-
-   flags |= MI_MM_SPACE_GTT;
-   if (IS_HASWELL(dev_priv))
-   /* These flags are for resource streamer on HSW+ */
-   flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
-   else
-   flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
-
-   len = 4;
-   if (IS_GEN7(dev_priv))
-   len += 2 + (num_rings ? 4*num_rings + 6 : 0);
-
-   cs = intel_ring_begin(req, len);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
-   if (IS_GEN7(dev_priv)) {
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   *cs++ = i915_mmio_reg_offset(
-  RING_PSMI_CTL(signaller->mmio_base));
-   *cs++ = _MASKED_BIT_ENABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-   }
-   }
-
-   *cs++ = MI_NOOP;
-   *cs++ = MI_SET_CONTEXT;
-   *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
-   /*
-* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
-* WaMiSetContext_Hang:snb,ivb,vlv
-*/
-   *cs++ = MI_NOOP;
-
-   if (IS_GEN7(dev_priv)) {
-   if (num_rings) {
-   struct intel_engine_cs *signaller;
-   i915_reg_t last_reg = {}; /* keep gcc quiet */
-
-   *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-   for_each_engine(signaller, dev_priv, id) {
-   if (signaller == engine)
-   continue;
-
-   last_reg = RING_PSMI_CTL(signaller->mmio_base);
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = _MASKED_BIT_DISABLE(
-   GEN6_PSMI_SLEEP_MSG_DISABLE);
-   }
-
-   /* Insert a delay before the next switch! */
-   *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
-   *cs++ = i915_mmio_reg_offset(last_reg);
-   *cs++ = i915_ggtt_offset(engine->scratch);
-   *cs++ = MI_NOOP;
-   }
-   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-   }
-
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-static int remap_l3(struct drm_i915_gem_request *req, int slice)
-{
-   u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
-   int i;
-
-   if (!remap_info)
-   return 0;
-
-   cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
-   if (IS_ERR(cs))
-   return PTR_ERR(cs);
-
-   /*
-* Note: We do not worry about the concurrent register cacheline hang
-* here because no other code should access these registers other than
-* at initialization time.
-*/
-   *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
-   for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
-   *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
-   *cs++ = remap_info[i];
-   }
-   *cs++ = MI_NOOP;
-   intel_ring_advance(req, cs);
-
-   return 0;
-}
-
-/**
- * i915_switch_context() - perform a GPU context switch.
- * @rq: request for which we'll execute the context switch
- *
- * The context life cycle is simple. The context refcount is 

[Intel-gfx] [CI 08/13] drm/i915: Disable semaphores on Sandybridge

[Chris Wilson]

I should have admitted defeat long ago as there has been a rare but
persistent error on Sandybridge where semaphore signaling did not
propagate to the waiter, leading to a GPU hang.

With the work on fence signaling for v4.9, the impact of using CPU driven
signaling was greatly reduced wrt to the latency of GPU semaphores,
though without logical rings support, the benefit of reordering work to
avoid bubbles is not realised (i.e. as it stands fence signaling is just
a slower, more costly version of HW semaphores; but works more
consistently). As a rough indicator of the difference,

with semaphores:
Sequential (3 engines, 1 processes): average 5.470us per cycle [expected 
4.988us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 15.771us per cycle [expected 
4.923us]

In comparison, v3.4:
with semaphores:
Sequential (3 engines, 1 processes): average 16.066us per cycle [expected 
11.842us]
w/o semaphores:
Sequential (3 engines, 1 processes): average 23.460us per cycle [expected 
11.839us]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54226 #and 100+ dupes
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Acked-by: Mika Kuoppala 
Reviewed-by: Joonas Lahtinen = 0)
return value;
 
-   /* Enable semaphores on SNB when IO remapping is off */
-   if (IS_GEN6(dev_priv) && intel_vtd_active())
-   return false;
-
return true;
 }
 
-- 
2.15.0

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[Intel-gfx] [CI 06/13] drm/i915: Remove i915.enable_execlists module parameter

[Chris Wilson]

Execlists and legacy ringbuffer submission are no longer feature
comparable (execlists now offer greater functionality that should
overcome their performance hit) and obsoletes the unsafe module
parameter, i.e. comparing the two modes of execution is no longer
useful, so remove the debug tool.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Lionel Landwerlin  #i915_perf.c
---
 drivers/gpu/drm/i915/gvt/render.c   |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c | 70 -
 drivers/gpu/drm/i915/i915_drv.c |  8 +---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++
 drivers/gpu/drm/i915/i915_gem.c | 10 ++---
 drivers/gpu/drm/i915/i915_gem_context.c | 10 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 --
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/i915_perf.c|  8 ++--
 drivers/gpu/drm/i915/intel_engine_cs.c  |  8 ++--
 drivers/gpu/drm/i915/intel_gvt.c|  5 ---
 drivers/gpu/drm/i915/intel_lrc.c| 31 ---
 drivers/gpu/drm/i915/intel_lrc.h|  4 --
 14 files changed, 20 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 0672178548ef..dac12c25f349 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -294,8 +294,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, 
int ring_id)
 * write.
 */
if (mmio->in_context &&
-   ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-   i915_modparams.enable_execlists)
+   (ctx_ctrl & inhibit_mask) != inhibit_mask)
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index df3852c02a35..5e2a6e18771f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1989,75 +1989,6 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static void i915_dump_lrc_obj(struct seq_file *m,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
-   struct i915_vma *vma = ctx->engine[engine->id].state;
-   struct page *page;
-   int j;
-
-   seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
-
-   if (!vma) {
-   seq_puts(m, "\tFake context\n");
-   return;
-   }
-
-   if (vma->flags & I915_VMA_GLOBAL_BIND)
-   seq_printf(m, "\tBound in GGTT at 0x%08x\n",
-  i915_ggtt_offset(vma));
-
-   if (i915_gem_object_pin_pages(vma->obj)) {
-   seq_puts(m, "\tFailed to get pages for context object\n\n");
-   return;
-   }
-
-   page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
-   if (page) {
-   u32 *reg_state = kmap_atomic(page);
-
-   for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
-   seq_printf(m,
-  "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-  j * 4,
-  reg_state[j], reg_state[j + 1],
-  reg_state[j + 2], reg_state[j + 3]);
-   }
-   kunmap_atomic(reg_state);
-   }
-
-   i915_gem_object_unpin_pages(vma->obj);
-   seq_putc(m, '\n');
-}
-
-static int i915_dump_lrc(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   struct i915_gem_context *ctx;
-   enum intel_engine_id id;
-   int ret;
-
-   if (!i915_modparams.enable_execlists) {
-   seq_printf(m, "Logical Ring Contexts are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   list_for_each_entry(ctx, _priv->contexts.list, link)
-   for_each_engine(engine, dev_priv, id)
-   i915_dump_lrc_obj(m, ctx, engine);
-
-   mutex_unlock(>struct_mutex);
-
-   return 0;
-}
-
 static const char *swizzle_string(unsigned swizzle)
 {
switch (swizzle) {
@@ -4833,7 +4764,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_vbt", i915_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
-   {"i915_dump_lrc", i915_dump_lrc, 0},
{"i915_forcewake_domains", i915_forcewake_domains, 0},

[Intel-gfx] [CI 10/13] drm/i915: Remove i915.semaphores modparam

[Chris Wilson]

Having disabled the broken semaphores on Sandybridge, there is no need
for a modparam any more, so remove it in favour of a simple
HAS_LEGACY_SEMAPHORES() guard.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Maarten Lankhorst 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c |  7 +--
 drivers/gpu/drm/i915/i915_drv.h |  4 ++--
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  4 ++--
 8 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 779a6f0785c7..36fc99324b9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,7 +321,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = USES_PPGTT(dev_priv);
break;
case I915_PARAM_HAS_SEMAPHORES:
-   value = i915_modparams.semaphores;
+   value = HAS_LEGACY_SEMAPHORES(dev_priv);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
@@ -1066,11 +1066,6 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
i915_modparams.enable_ppgtt);
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-   i915_modparams.semaphores =
-   intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
-   DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
-yesno(i915_modparams.semaphores));
-
intel_uc_sanitize_options(dev_priv);
 
intel_gvt_sanitize_options(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 953867d9171e..24ce5d89e07e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3140,6 +3140,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_BLT(dev_priv)  HAS_ENGINE(dev_priv, BCS)
 #define HAS_VEBOX(dev_priv)HAS_ENGINE(dev_priv, VECS)
 
+#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
+
 #define HAS_LLC(dev_priv)  ((dev_priv)->info.has_llc)
 #define HAS_SNOOP(dev_priv)((dev_priv)->info.has_snoop)
 #define HAS_EDRAM(dev_priv)(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
@@ -3303,8 +3305,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
int enable_ppgtt);
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
-
 /* i915_drv.c */
 void __printf(3, 4)
 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d53bb8e872ba..792e6dc7e19b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4997,17 +4997,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
-bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
-{
-   if (!IS_GEN7(dev_priv))
-   return false;
-
-   if (value >= 0)
-   return value;
-
-   return true;
-}
-
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 {
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0704d9af261b..6ca56e482d79 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -574,7 +574,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags)
enum intel_engine_id id;
const int num_rings =
/* Use an extended w/a on gen7 if signalling from other rings */
-   (i915_modparams.semaphores && IS_GEN7(dev_priv)) ?
+   (HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
INTEL_INFO(dev_priv)->num_rings - 1 :
0;
int len;
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index d61c1787c164..3328147b4863 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,10 +46,6 @@ i915_param_named_unsafe(panel_ignore_lid, int, 0600,
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
-i915_param_named_unsafe(semaphores, int, 0400,
-   "Use semaphores for inter-ring sync "
-   "(default: -1 (use per-chip defaults))");
-
 

[Intel-gfx] [CI 07/13] drm/i915: Remove obsolete ringbuffer emission for gen8+

[Chris Wilson]

Since removing the module parameter to force selection of ringbuffer
emission for gen8, the code is defunct. Remove it.

To put the difference into perspective, a couple of microbenchmarks
(bdw i7-5557u, 20170324):
ring  execlists
exec continuous nops on all rings:   1.491us2.223us
exec sequential nops on each ring:  12.508us   53.682us
single nop + sync:   9.272us   30.291us

vblank_mode=0 glxgears:~11000fps   ~9000fps

Since the earlier submission, gen8 ringbuffer submission has fallen
further and further behind in features. So while ringbuffer may hold the
throughput crown, in terms of interactive latency, execlists is much
better. Alas, we have no convenient metrics for such, other than
demonstrating things we can do with execlists but can not using
legacy ringbuffer submission.

We have made a few improvements to lowlevel execlists throughput,
and ringbuffer currently panics on boot! (bdw i7-5557u, 20171026):

ring  execlists
exec continuous nops on all rings:   n/a1.921us
exec sequential nops on each ring:   n/a   44.621us
single nop + sync:   n/a   21.953us

vblank_mode=0 glxgears:  n/a  ~18500fps

References: https://bugs.freedesktop.org/show_bug.cgi?id=87725
Signed-off-by: Chris Wilson 
Once-upon-a-time-Reviewed-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  44 +---
 drivers/gpu/drm/i915/i915_drv.h |   2 -
 drivers/gpu/drm/i915/i915_gem.c |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  47 +---
 drivers/gpu/drm/i915/i915_gpu_error.c   |  36 ---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  14 --
 drivers/gpu/drm/i915/intel_hangcheck.c  |  44 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 431 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  25 +-
 9 files changed, 94 insertions(+), 551 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5e2a6e18771f..9cef1463d411 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3254,44 +3254,12 @@ static int i915_semaphore_status(struct seq_file *m, 
void *unused)
return ret;
intel_runtime_pm_get(dev_priv);
 
-   if (IS_BROADWELL(dev_priv)) {
-   struct page *page;
-   uint64_t *seqno;
-
-   page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
-
-   seqno = (uint64_t *)kmap_atomic(page);
-   for_each_engine(engine, dev_priv, id) {
-   uint64_t offset;
-
-   seq_printf(m, "%s\n", engine->name);
-
-   seq_puts(m, "  Last signal:");
-   for (j = 0; j < num_rings; j++) {
-   offset = id * I915_NUM_ENGINES + j;
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   seq_puts(m, "  Last wait:  ");
-   for (j = 0; j < num_rings; j++) {
-   offset = id + (j * I915_NUM_ENGINES);
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   }
-   kunmap_atomic(seqno);
-   } else {
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  
I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-   }
+   seq_puts(m, "  Last signal:");
+   for_each_engine(engine, dev_priv, id)
+   for (j = 0; j < num_rings; j++)
+   seq_printf(m, "0x%08x\n",
+  I915_READ(engine->semaphore.mbox.signal[j]));
+   seq_putc(m, '\n');
 
intel_runtime_pm_put(dev_priv);
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a21544b62866..953867d9171e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -942,7 +942,6 @@ struct i915_gpu_state {
u64 fence[I915_MAX_NUM_FENCES];
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
-   struct drm_i915_error_object *semaphore;
 
struct drm_i915_error_engine {

[Intel-gfx] [CI 04/13] drm/i915: Pull the unconditional GPU cache invalidation into request construction

[Chris Wilson]

As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the TLB invalidate, do it unconditionally on
request allocation and so we can remove it from all other paths.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  7 +--
 drivers/gpu/drm/i915/i915_gem_render_state.c  |  4 
 drivers/gpu/drm/i915/i915_gem_request.c   | 24 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  4 
 7 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 53ccb27bfe91..b7895788bc75 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
@@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
/* Unconditionally flush any chipset caches (for streaming writes). */
i915_gem_chipset_flush(eb->i915);
 
-   /* Unconditionally invalidate GPU caches and TLBs. */
-   return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
+   return 0;
 }
 
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index c2723a06fbb4..f7fc0df251ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -208,10 +208,6 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request 
*rq)
if (err)
goto err_unpin;
 
-   err = engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_unpin;
-
err = engine->emit_bb_start(rq,
so.batch_offset, so.batch_size,
I915_DISPATCH_SECURE);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e0d6221022a8..91eae1b20c42 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
 
-   ret = engine->request_alloc(req);
-   if (ret)
-   goto err_ctx;
-
-   /* Record the position of the start of the request so that
+   /*
+* Record the position of the start of the request so that
 * should we detect the updated seqno part-way through the
 * GPU processing the request, we never over-estimate the
 * position of the head.
 */
req->head = req->ring->emit;
 
+   /* Unconditionally invalidate GPU caches and TLBs. */
+   ret = engine->emit_flush(req, EMIT_INVALIDATE);
+   if (ret)
+   goto err_ctx;
+
+   ret = engine->request_alloc(req);
+   if (ret) {
+   /*
+* Past the point-of-no-return. Since we may have updated
+* global state after partially completing the request alloc,
+* we need to commit any commands so far emitted in the
+* request to the HW.
+*/
+   __i915_add_request(req, false);
+   return ERR_PTR(ret);
+   }
+
/* Check that we didn't interrupt ourselves with a new request */
GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
return req;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 01af540b6ef9..159a2cb68765 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -989,10 +989,6 @@ static int gpu_write(struct i915_vma *vma,
i915_vma_unpin(batch);
i915_vma_close(batch);
 
-   err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-   if (err)
-   goto err_request;
-
err = i915_switch_context(rq);
if (err)
goto err_request;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 

[Intel-gfx] [CI 05/13] drm/i915: Automatic i915_switch_context for legacy

[Chris Wilson]

During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.

v2: Always submit the request if we emitted some commands during request
construction, as typically it also involves changes in global state.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  7 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  8 
 drivers/gpu/drm/i915/i915_gem_request.c   |  4 
 drivers/gpu/drm/i915/i915_perf.c  |  3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  4 
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 10 +++---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  4 
 drivers/gpu/drm/i915/selftests/i915_gem_request.c | 10 --
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c  |  6 --
 10 files changed, 14 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61ba321e9970..e07eb0beef13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5045,7 +5045,7 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto out_ctx;
}
 
-   err = i915_switch_context(rq);
+   err = 0;
if (engine->init_context)
err = engine->init_context(rq);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2db040695035..c1efbaf02bf2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,8 +842,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
 
lockdep_assert_held(>i915->drm.struct_mutex);
-   if (i915_modparams.enable_execlists)
-   return 0;
+   GEM_BUG_ON(i915_modparams.enable_execlists);
 
if (!req->ctx->engine[engine->id].state) {
struct i915_gem_context *to = req->ctx;
@@ -899,7 +898,6 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 
for_each_engine(engine, dev_priv, id) {
struct drm_i915_gem_request *req;
-   int ret;
 
if (engine_has_idle_kernel_context(engine))
continue;
@@ -922,10 +920,7 @@ int i915_gem_switch_to_kernel_context(struct 
drm_i915_private *dev_priv)
 GFP_KERNEL);
}
 
-   ret = i915_switch_context(req);
i915_add_request(req);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b7895788bc75..14d9e61a1e06 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -,10 +,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_request;
 
-   err = i915_switch_context(rq);
-   if (err)
-   goto err_request;
-
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
cache->gen > 5 ? 0 : 
I915_DISPATCH_SECURE);
@@ -1960,10 +1956,6 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
 
-   err = i915_switch_context(eb->request);
-   if (err)
-   return err;
-
if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
err = i915_reset_gen7_sol_offsets(eb->request);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 91eae1b20c42..86e2346357cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -624,6 +624,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unpin;
 
+   ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
+   if (ret)
+   goto err_unreserve;
+
/* Move the oldest request to the slab-cache (if not in use!) */
req = list_first_entry_or_null(>timeline->requests,
   typeof(*req), link);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00be015e01df..d8952ff8e6b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1726,10 +1726,9 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private 

[Intel-gfx] [CI 03/13] drm/i915/execlists: Skip a lite-restore immediately prior to a context-completion

[Chris Wilson]

If we are about to do another context-switch in the near future skip
doing performing a lite-restore now. (Forcing a lite-restore just before
a context-switch effectively doubles the cost of that context-switch, so
long as we can handle the interrupt and resubmit before the GPU powers
down, which under normal conditions is expected.)

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6191a2e59e8a..2edd57b3d53e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -628,6 +628,19 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
if (port_count([1]))
goto unlock;
 
+   /*
+* If we are about to do another context-switch in
+* the near future skip doing performing a lite-restore
+* now. (Forcing a lite-restore just before a
+* context-switch effectively doubles the cost of that
+* context-switch, so long as we can handle the
+* interrupt and resubmit before the GPU powers down,
+* which under normal conditions is expected.)
+*/
+   if (i915_seqno_passed(intel_engine_get_seqno(engine),
+ last->global_seqno - 1))
+   goto unlock;
+
/* WaIdleLiteRestore:bdw,skl
 * Apply the wa NOOPs to prevent
 * ring:HEAD == req:TAIL as we resubmit the
-- 
2.15.0

___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 02/13] drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write

[Chris Wilson]

The hardware needs some time to process the information received in the
ExecList Submission Port, and expects us to don't write anything new until
it has 'acknowledged' this new execlist by sending an IDLE_ACTIVE or
PREEMPTED CSB event.

If we do not follow this, the driver could write new data into the ELSP
before HW had finishing fetching the previous one, putting us in
'undefined behaviour' space.

This seems to be the problem causing the spurious PREEMPTED & COMPLETE
events after a COMPLETE like the one below:

[] vcs0: sw rd pointer = 2, hw wr pointer = 0, current 'head' = 3.
[] vcs0:  Execlist CSB[0]: 0x0018 _ 0x0007
[] vcs0:  Execlist CSB[1]: 0x0001 _ 0x
[] vcs0:  Execlist CSB[2]: 0x0018 _ 0x0007  <<< COMPLETE
[] vcs0:  Execlist CSB[3]: 0x0012 _ 0x0007  <<< PREEMPTED & COMPLETE
[] vcs0:  Execlist CSB[4]: 0x8002 _ 0x0006
[] vcs0:  Execlist CSB[5]: 0x0014 _ 0x0006

The ELSP writes that lead to this CSB sequence show that the HW hadn't
started executing the previous execlist (the one with only ctx 0x6) by the
time the new one was submitted; this is a bit more clear in the data
show in the EXECLIST_STATUS register at the time of the ELSP write.

[] vcs0: ELSP[0] = 0x0_0[execlist1] - status_reg = 0x0_302
[] vcs0: ELSP[1] = 0x6_fedb2119 [execlist0] - status_reg = 0x0_8302

[] vcs0: ELSP[2] = 0x7_fedaf119 [execlist1] - status_reg = 0x0_8308
[] vcs0: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308

Note that having to wait for this ack does not disable lite-restores,
although it may reduce their numbers.

v2: Rewrote Michel's patch, his digging and his fix, my spelling.
v3: Reorder to ack early to allow preemption

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Suggested-by: Michel Thierry 
Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c| 22 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2cfdfdc0722..6191a2e59e8a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -479,6 +479,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
elsp_write(desc, elsp);
}
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
@@ -531,6 +532,7 @@ static void inject_preempt_context(struct intel_engine_cs 
*engine)
elsp_write(0, elsp);
 
elsp_write(ce->lrc_desc, elsp);
+   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static void execlists_dequeue(struct intel_engine_cs *engine)
@@ -577,9 +579,20 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * know the next preemption status we see corresponds
 * to this ELSP update.
 */
+   GEM_BUG_ON(!port_count([0]));
if (port_count([0]) > 1)
goto unlock;
 
+   /*
+* If we write to ELSP a second time before the HW has had
+* a chance to respond to the previous write, we can confuse
+* the HW and hit "undefined behaviour". After writing to ELSP,
+* we must then wait until we see a context-switch event from
+* the HW to indicate that it has had a chance to respond.
+*/
+   if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
+   goto unlock;
+
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) &&
rb_entry(rb, struct i915_priolist, node)->priority >
max(last->priotree.priority, 0)) {
@@ -873,6 +886,15 @@ static void execlists_submission_tasklet(unsigned long 
data)
GEM_TRACE("%s csb[%dd]: status=0x%08x:0x%08x\n",
  engine->name, head,
  status, buf[2*head + 1]);
+
+   if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
+ GEN8_CTX_STATUS_PREEMPTED))
+   execlists_set_active(execlists,
+EXECLISTS_ACTIVE_HWACK);
+   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
+   execlists_clear_active(execlists,
+  EXECLISTS_ACTIVE_HWACK);
+
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f867aa6c31fc..add7a30c1a61 100644
--- 

[Intel-gfx] [CI 01/13] drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE

[Chris Wilson]

Since commit e1fee72c2ea2e9c0c6e6743d32a6832f21337d6c
Author: Oscar Mateo 
Date:   Thu Jul 24 17:04:40 2014 +0100

drm/i915/bdw: Avoid non-lite-restore preemptions

execlists has listened to (ACTIVE_IDLE | ELEMENT_SWITCH) for detecting
when one context completed and it either continued onto the next (in port
1) or idled. We would always see COMPLETE | ACTIVE_IDLE on the final
context-switch event, but on recent gen it appears that we now get
separate ACTIVE_IDLE and COMPLETE events. In particular, the ACTIVE_IDLE
events may not be coupled to a context (since it is a general state rather
than a specific context completion event).

v2: Update the history, execlists did originally start out by listening
to the COMPLETE event not ACTIVE_IDLE.
v3: Update preempt completion test to also use COMPLETE not ACTIVE_IDLE.

References: https://bugs.freedesktop.org/show_bug.cgi?id=103800
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Acked-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index be6c39adebdf..c2cfdfdc0722 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -154,7 +154,7 @@
 #define GEN8_CTX_STATUS_LITE_RESTORE   (1 << 15)
 
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
-(GEN8_CTX_STATUS_ACTIVE_IDLE | \
+(GEN8_CTX_STATUS_COMPLETE | \
  GEN8_CTX_STATUS_PREEMPTED | \
  GEN8_CTX_STATUS_ELEMENT_SWITCH)
 
@@ -876,7 +876,7 @@ static void execlists_submission_tasklet(unsigned long data)
if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
continue;
 
-   if (status & GEN8_CTX_STATUS_ACTIVE_IDLE &&
+   if (status & GEN8_CTX_STATUS_COMPLETE &&
buf[2*head + 1] == PREEMPT_ID) {
execlists_cancel_port_requests(execlists);
execlists_unwind_incomplete_requests(execlists);
-- 
2.15.0

___
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Re: [Intel-gfx] 4.9.62: intermittent flicker after upgrade from 4.9.61

[Greg KH]

On Sun, Nov 19, 2017 at 01:44:06PM +0100, Rainer Fiebig wrote:
> Greg KH wrote:
> > On Sun, Nov 19, 2017 at 12:56:26PM +0100, Rainer Fiebig wrote:
> >> Greg KH wrote:
> >>> On Sat, Nov 18, 2017 at 05:08:20PM +0100, Rainer Fiebig wrote:
>  Greg KH wrote:
> > On Sat, Nov 18, 2017 at 01:47:32PM +0100, Rainer Fiebig wrote:
> >> Hi!
> >>
> >> Hopefully the right addressee.
> >>
> >> Encountered two bad backports which cause screen-flicker.
> >> dmesg shows:
> >>
> >> ...
> >> [drm:ironlake_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
> >> [drm:ironlake_irq_handler [i915]] *ERROR* PCH transcoder A FIFO 
> >> underrun
> >> [drm:ironlake_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
> >> [drm:ironlake_irq_handler [i915]] *ERROR* PCH transcoder B FIFO 
> >> underrun
> >> ...
> >>
> >> CPU: Intel Core i3 (Clarkdale/Ironlake)
> >>
> >> The backports are:
> >>
> >> - diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >> b/drivers/gpu/drm/i915/intel_pm.c
> >> index 49de476..277a802 100644
> >> - diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >> b/drivers/gpu/drm/i915/intel_drv.h
> >> index a19ec06..3ce9ba3 100644
> >>
> >> After reversing them the flicker is gone, no more messages in dmesg. 
> >> All
> >> else OK so far.
> >
> > So which commit was the one that caused the problem?  I will be glad to
> > revert it.
> >
> > thanks,
> >
> > greg k-h
> >
> >
> 
>  I started by reverting the more complex one first ("index
>  49de476..277a802100644"). But the kernel wouldn't compile then.
> >>>
> >>> What git commit id is that?  I don't see those ids in the 4.9-stable
> >>> tree.
> >>>
>  So I also reverted "index a19ec06..3ce9ba3 100644". After that the
>  kernel compiled just fine and the problems were gone (still are).
> >>>
> >>> Same here, what git commit id was this?
> >>>
> >>> thanks,
> >>>
> >>> greg k-h
> >>>
> >>
> >> OK, no mistake. IIRC, I took the patches (and the IDs) from the
> >> changelog for patch-4.9.62. I've attached both, so you can check yourself.
> >>
> >> I've also applied a freshly downloaded patch-4.9.62 to a freshly
> >> expanded 4.9 and re-compiled. The flicker is there. I haven't yet
> >> reverted the two patches but I'm confident that after having done so the
> >> flicker will be gone. If not I'll let you know.
> >>
> >> As a good news: 4.14 is *not* affected. So to me it seems those two
> >> patches are part of sort of a package and can not be backported alone.
> >>
> >> So long!
> >> Rainer Fiebig
> > 
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> >> b/drivers/gpu/drm/i915/intel_pm.c
> >> index 49de476..277a802 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -27,6 +27,7 @@
> >>  
> >>  #include 
> >>  #include 
> >> +#include 
> >>  #include "i915_drv.h"
> >>  #include "intel_drv.h"
> >>  #include "../../../platform/x86/intel_ips.h"
> >> @@ -2017,9 +2018,9 @@ static void ilk_compute_wm_level(const struct 
> >> drm_i915_private *dev_priv,
> >> const struct intel_crtc *intel_crtc,
> >> int level,
> >> struct intel_crtc_state *cstate,
> >> -   struct intel_plane_state *pristate,
> >> -   struct intel_plane_state *sprstate,
> >> -   struct intel_plane_state *curstate,
> >> +   const struct intel_plane_state *pristate,
> >> +   const struct intel_plane_state *sprstate,
> >> +   const struct intel_plane_state *curstate,
> >> struct intel_wm_level *result)
> >>  {
> >>uint16_t pri_latency = dev_priv->wm.pri_latency[level];
> >> @@ -2341,28 +2342,24 @@ static int ilk_compute_pipe_wm(struct 
> >> intel_crtc_state *cstate)
> >>struct intel_pipe_wm *pipe_wm;
> >>struct drm_device *dev = state->dev;
> >>const struct drm_i915_private *dev_priv = to_i915(dev);
> >> -  struct intel_plane *intel_plane;
> >> -  struct intel_plane_state *pristate = NULL;
> >> -  struct intel_plane_state *sprstate = NULL;
> >> -  struct intel_plane_state *curstate = NULL;
> >> +  struct drm_plane *plane;
> >> +  const struct drm_plane_state *plane_state;
> >> +  const struct intel_plane_state *pristate = NULL;
> >> +  const struct intel_plane_state *sprstate = NULL;
> >> +  const struct intel_plane_state *curstate = NULL;
> >>int level, max_level = ilk_wm_max_level(dev), usable_level;
> >>struct ilk_wm_maximums max;
> >>  
> >>pipe_wm = >wm.ilk.optimal;
> >>  
> >> -  for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> >> -  struct intel_plane_state *ps;
> >> +  drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, 
> >> >base) {
> >> +  const struct 

Re: [Intel-gfx] 4.9.62: intermittent flicker after upgrade from 4.9.61

[Greg KH]

On Sun, Nov 19, 2017 at 12:56:26PM +0100, Rainer Fiebig wrote:
> Greg KH wrote:
> > On Sat, Nov 18, 2017 at 05:08:20PM +0100, Rainer Fiebig wrote:
> >> Greg KH wrote:
> >>> On Sat, Nov 18, 2017 at 01:47:32PM +0100, Rainer Fiebig wrote:
>  Hi!
> 
>  Hopefully the right addressee.
> 
>  Encountered two bad backports which cause screen-flicker.
>  dmesg shows:
> 
>  ...
>  [drm:ironlake_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
>  [drm:ironlake_irq_handler [i915]] *ERROR* PCH transcoder A FIFO underrun
>  [drm:ironlake_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>  [drm:ironlake_irq_handler [i915]] *ERROR* PCH transcoder B FIFO underrun
>  ...
> 
>  CPU: Intel Core i3 (Clarkdale/Ironlake)
> 
>  The backports are:
> 
>  - diff --git a/drivers/gpu/drm/i915/intel_pm.c
>  b/drivers/gpu/drm/i915/intel_pm.c
>  index 49de476..277a802 100644
>  - diff --git a/drivers/gpu/drm/i915/intel_drv.h
>  b/drivers/gpu/drm/i915/intel_drv.h
>  index a19ec06..3ce9ba3 100644
> 
>  After reversing them the flicker is gone, no more messages in dmesg. All
>  else OK so far.
> >>>
> >>> So which commit was the one that caused the problem?  I will be glad to
> >>> revert it.
> >>>
> >>> thanks,
> >>>
> >>> greg k-h
> >>>
> >>>
> >>
> >> I started by reverting the more complex one first ("index
> >> 49de476..277a802100644"). But the kernel wouldn't compile then.
> > 
> > What git commit id is that?  I don't see those ids in the 4.9-stable
> > tree.
> > 
> >> So I also reverted "index a19ec06..3ce9ba3 100644". After that the
> >> kernel compiled just fine and the problems were gone (still are).
> > 
> > Same here, what git commit id was this?
> > 
> > thanks,
> > 
> > greg k-h
> > 
> 
> OK, no mistake. IIRC, I took the patches (and the IDs) from the
> changelog for patch-4.9.62. I've attached both, so you can check yourself.
> 
> I've also applied a freshly downloaded patch-4.9.62 to a freshly
> expanded 4.9 and re-compiled. The flicker is there. I haven't yet
> reverted the two patches but I'm confident that after having done so the
> flicker will be gone. If not I'll let you know.
> 
> As a good news: 4.14 is *not* affected. So to me it seems those two
> patches are part of sort of a package and can not be backported alone.
> 
> So long!
> Rainer Fiebig

> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 49de476..277a802 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -27,6 +27,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include "i915_drv.h"
>  #include "intel_drv.h"
>  #include "../../../platform/x86/intel_ips.h"
> @@ -2017,9 +2018,9 @@ static void ilk_compute_wm_level(const struct 
> drm_i915_private *dev_priv,
>const struct intel_crtc *intel_crtc,
>int level,
>struct intel_crtc_state *cstate,
> -  struct intel_plane_state *pristate,
> -  struct intel_plane_state *sprstate,
> -  struct intel_plane_state *curstate,
> +  const struct intel_plane_state *pristate,
> +  const struct intel_plane_state *sprstate,
> +  const struct intel_plane_state *curstate,
>struct intel_wm_level *result)
>  {
>   uint16_t pri_latency = dev_priv->wm.pri_latency[level];
> @@ -2341,28 +2342,24 @@ static int ilk_compute_pipe_wm(struct 
> intel_crtc_state *cstate)
>   struct intel_pipe_wm *pipe_wm;
>   struct drm_device *dev = state->dev;
>   const struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_plane *intel_plane;
> - struct intel_plane_state *pristate = NULL;
> - struct intel_plane_state *sprstate = NULL;
> - struct intel_plane_state *curstate = NULL;
> + struct drm_plane *plane;
> + const struct drm_plane_state *plane_state;
> + const struct intel_plane_state *pristate = NULL;
> + const struct intel_plane_state *sprstate = NULL;
> + const struct intel_plane_state *curstate = NULL;
>   int level, max_level = ilk_wm_max_level(dev), usable_level;
>   struct ilk_wm_maximums max;
>  
>   pipe_wm = >wm.ilk.optimal;
>  
> - for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> - struct intel_plane_state *ps;
> + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, 
> >base) {
> + const struct intel_plane_state *ps = 
> to_intel_plane_state(plane_state);
>  
> - ps = intel_atomic_get_existing_plane_state(state,
> -intel_plane);
> - if (!ps)
> - continue;
> -
> - if (intel_plane->base.type ==