[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/guc : Decoupling ADS and logs from submission

2017-12-27 Thread Patchwork 
== Series Details ==

Series: series starting with [1/2] drm/i915/guc : Decoupling ADS and logs from 
submission
URL   : https://patchwork.freedesktop.org/series/35811/
State : warning

== Summary ==

Series 35811v1 series starting with [1/2] drm/i915/guc : Decoupling ADS and 
logs from submission
https://patchwork.freedesktop.org/api/1.0/series/35811/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 +1
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_busy:
Subgroup basic-flip-b:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144 +36
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-6700hq)
Subgroup basic-flip-vs-wf_vblank:
pass   -> SKIP   (fi-skl-6700hq)
Subgroup basic-plain-flip:
pass   -> SKIP   (fi-skl-6700hq)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> SKIP   (fi-skl-6700hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> SKIP   (fi-skl-6700hq)
Subgroup basic-rte:
pass   -> SKIP   (fi-skl-6700hq)
Test pm_rps:
Subgroup basic-api:
pass   -> DMESG-WARN (fi-skl-6700hq)

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:436s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:384s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:493s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:274s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:491s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:494s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:475s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:465s
fi-elk-e7500 total:224  pass:164  dwarn:14  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:264s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:528s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:407s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:412s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:426s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:479s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:522s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:470s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:523s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:581s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:530s
fi-skl-6700hqtotal:288  pass:218  dwarn:2   dfail:1   fail:29  skip:33  
time:317s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:501s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:440s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:413s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:591s
fi-glk-dsi   total:151  pass:137  dwarn:0   dfail:0   fail:0   skip:13 

42a41a56eb45fc94c3beec3968faffb97ba3e375 drm-tip: 2017y-12m-27d-14h-36m-54s UTC 
integration manifest
26c3132af4e0 drm/i915/guc : GEM_BUG_ON on invoking GuC reset function
eb3a3a8b0480 drm/i915/guc : Decoupling ADS and logs from submission

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7586/issues.html

[Intel-gfx] [v2 PATCH 2/2] drm/i915/guc : GEM_BUG_ON on invoking GuC reset function

2017-12-27 Thread Sujaritha Sundaresan 
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.

v2: re-wording commit message and subject (Sagar)

Signed-off-by: Sujaritha Sundaresan 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_uncore.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 89547b61..94e1fb3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1936,8 +1936,7 @@ int intel_reset_guc(struct drm_i915_private *dev_priv)
 {
int ret;
 
-   if (!HAS_GUC(dev_priv))
-   return -EINVAL;
+   GEM_BUG_ON(!HAS_GUC(dev_priv));
 
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 1/2] drm/i915/guc : Decoupling ADS and logs from submission

2017-12-27 Thread Sujaritha Sundaresan 
The Additional Data Struct (ADS) contains objects that are required by
GuC post FW load and are not necessarily submission-only. Even with
submission disabled we may require something inside the ADS, so it
makes more sense for them to be always created.

Similarly, we still want to access GuC logs and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.

Signed-off-by: Sujaritha Sundaresan 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/Makefile   |   1 +
 drivers/gpu/drm/i915/intel_guc.c|  18 
 drivers/gpu/drm/i915/intel_guc_ads.c| 151 
 drivers/gpu/drm/i915/intel_guc_ads.h|  33 ++
 drivers/gpu/drm/i915/intel_guc_submission.c | 134 
 5 files changed, 203 insertions(+), 134 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef2..4d9e2f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += i915_cmd_parser.o \
 i915-y += intel_uc.o \
  intel_uc_fw.o \
  intel_guc.o \
+ intel_guc_ads.o \
  intel_guc_ct.o \
  intel_guc_fw.o \
  intel_guc_log.o \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3c6bf5a..50b4725 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -23,6 +23,7 @@
  */
 
 #include "intel_guc.h"
+#include "intel_guc_ads.h"
 #include "intel_guc_submission.h"
 #include "i915_drv.h"
 
@@ -163,10 +164,25 @@ int intel_guc_init(struct intel_guc *guc)
return ret;
GEM_BUG_ON(!guc->shared_data);
 
+   ret = intel_guc_log_create(guc);
+   if (ret)
+   goto err_shared;
+
+   ret = intel_guc_ads_create(guc);
+   if (ret)
+   goto err_log;
+   GEM_BUG_ON(!guc->ads_vma);
+
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
 
return 0;
+
+err_log:
+   intel_guc_log_destroy(guc);
+err_shared:
+   guc_shared_data_destroy(guc);
+   return ret;
 }
 
 void intel_guc_fini(struct intel_guc *guc)
@@ -174,6 +190,8 @@ void intel_guc_fini(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
i915_ggtt_disable_guc(dev_priv);
+   intel_guc_ads_destroy(guc);
+   intel_guc_log_destroy(guc);
guc_shared_data_destroy(guc);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c 
b/drivers/gpu/drm/i915/intel_guc_ads.c
new file mode 100644
index 000..f6066bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright © 2014-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_ads.h"
+#include "intel_uc.h"
+#include "i915_drv.h"
+
+/*
+ * The Additional Data Struct (ADS) has pointers for different buffers used by
+ * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
+ * scheduling policies (guc_policies), a structure describing a collection of
+ * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
+ * its internal state for sleep.
+ */
+
+static void guc_policy_init(struct guc_policy *policy)
+{
+   policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
+   policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
+   policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
+

Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK

2017-12-27 Thread Michal Wajdeczko 
On Sat, 23 Dec 2017 01:05:14 +0100, Anusha Srivatsa  
 wrote:



Since the firmwares are released yet to public repo,

^^^
s/released/not released


disable them on Geminilake.

v2: Remove the firmware versions (Michal)

Cc: Michal Wajdeczko 
Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
---

Reviewed-by: Michal Wajdeczko 

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [v2 PATCH 2/2] drm/i915/guc : GEM_BUG_ON on invoking GuC reset function

2017-12-27 Thread Sujaritha Sundaresan 
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.

v2: re-wording commit message and subject (Sagar)

Signed-off-by: Sujaritha Sundaresan 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_uncore.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 89547b61..94e1fb3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1936,8 +1936,7 @@ int intel_reset_guc(struct drm_i915_private *dev_priv)
 {
int ret;
 
-   if (!HAS_GUC(dev_priv))
-   return -EINVAL;
+   GEM_BUG_ON(!HAS_GUC(dev_priv));
 
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

2017-12-27 Thread Rogozhkin, Dmitry V 
>> I definitely asked what will be if GT request will be bigger than IA 
>> request. But that was a year ago and I don't remember the answer. Let me ask 
>> again. I will mail back in few days.

Hi Chris, here is the response.

Question was: "Whether we can meet with the RING transition penalty (at least 
theoretically) if we will have GT request higher than IA request with the 
dominant IA load and tiny GT load, i.e. reverted situation of what we have 
actually faced? For example, if we will try to pin IA frequency to 800MHz (x1 
multiplier) and GT frequency to 700MHz (x2 multiplier): in that case we will 
have requests for ring 800 vs. 1400."

Answer is: "In this case, if the GT will toggle between RC0 and RC6, it will 
force ring frequency to toggle between 800 and 1400, which in the toggling time 
will stall IA execution. This will lead to performance loss." However, this is 
a case if we have really few toggle events within few milliseconds. It is quite 
probable that GT driver will not allow such behavior to happen if it simply 
doesn't often toggle between RC0 and RC6. Considering that GT driver probably 
handles much less interrupts than IA, this can be the case. So, I think Chris, 
that's now question to you: how often you toggle between RC0 and RC6 to see the 
reverted issue to happen? If you don't toggle much, then RING will simply 
remain on 1400 almost all the time and you will see no issue.

Again, I remind that's the talk about Gen9 only.

Dmitry.

-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of 
Rogozhkin, Dmitry V
Sent: Tuesday, December 26, 2017 9:39 AM
To: Chris Wilson ; Li, Yaodong 
; intel-gfx@lists.freedesktop.org
Cc: Widawsky, Benjamin 
Subject: Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring 
multiplier

>> To clarify, the HW will flip between the two GT/IA requests rather than 
>> stick to the highest?

Yes, it will flip on Gen9. On Gen8 there was some mechanism (HW) which 
flattened that. But it was removed/substituted in Gen9. In Gen10 it was tuned  
to close the mentioned issue.

>> Do you know anything about the opposite position. I heard a suggestion that 
>> simply increasing the ringfreq universally caused thermal throttling in some 
>> other workloads. Do you have any knowledge of those?

Initially we tried to just increase GT multiplier to x3 and stepped into the 
throttling. Thus, we introduced parameter to be able to mitigate all that 
depending on the SKU and user needs. I definitely asked what will be if GT 
request will be bigger than IA request. But that was a year ago and I don't 
remember the answer. Let me ask again. I will mail back in few days.

>> You are thinking of plugging into intel_pstate to make it smarter for ia 
>> freq transitions?

Yep. This seems a correct step to give some automatic support instead of 
parameter/hardcoded multiplier.

Dmitry.

-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] 
Sent: Tuesday, December 26, 2017 8:59 AM
To: Rogozhkin, Dmitry V ; Li, Yaodong 
; intel-gfx@lists.freedesktop.org
Cc: Gong, Zhipeng ; Widawsky, Benjamin 
; Mateo Lozano, Oscar ; 
Kamble, Sagar A ; Li, Yaodong 
Subject: RE: [RFC] drm/i915: Add a new modparam for customized ring multiplier

Quoting Rogozhkin, Dmitry V (2017-12-26 16:39:23)
> Clarification on the issue. Consider that you have a massive load on GT and 
> just tiny one on IA. If GT will program the RING frequency to be lower than 
> IA frequency, then you will fall into the situation when RING frequency 
> constantly transits from GT to IA level and back. Each transition of a RING 
> frequency is a full system stall. If you will have "good" transition rate 
> with few transitions per few milliseconds you will lose ~10% of performance. 
> That's the case for media workloads when you easily can step into this since 
> 1) media utilizes few GPU engines and with few parallel workloads you can 
> make sure that at least 1 engine is _always_ doing something, 2) media BB are 
> relatively small, so you have regular wakeups of the IA to manage requests. 
> This will affect Gen9 platforms due to HW design change (we've spot this in 
> SKL). This will not happen in Gen8 (old HW design). This will be fixed in 
> Gen10+ (CNL+).

To clarify, the HW will flip between the two GT/IA requests rather than stick 
to the highest? Iirc, the expectation was that we were setting a requested 
minimum frequency for the ring/ia based off the gpu freq.

> On SKL we ran into this with the GPU frequency pinned to 700MHz, CPU to 2GHz. 
> Multipliers were x2 for GT, x1 for IA.

Basically, with the GPU clocked to mid frequency, memory throughput is 
insufficient to keep

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Remove the pipe/plane ID checks from skl_check_ccs_aux_surface()

2017-12-27 Thread Mika Kahola 
On Fri, 2017-12-22 at 21:22 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> The core now checks that the plane supports the fb's format+modifier
> combination, so we can drop the related checks from
> skl_check_ccs_aux_surface(). These checks were specific to
> SKL/KBL/BXT anyway.
> 
> Cc: Ben Widawsky 
> Cc: Jason Ekstrand 
> Cc: Daniel Stone 

Reviewed-by: Mika Kahola 

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index df29e33a2355..a037892ec92b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3033,9 +3033,6 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
>  
>  static int skl_check_ccs_aux_surface(struct intel_plane_state
> *plane_state)
>  {
> - struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(plane_state-
> >base.crtc);
>   const struct drm_framebuffer *fb = plane_state->base.fb;
>   int src_x = plane_state->base.src.x1 >> 16;
>   int src_y = plane_state->base.src.y1 >> 16;
> @@ -3045,11 +3042,6 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
>   int y = src_y / vsub;
>   u32 offset;
>  
> - if (!skl_plane_has_ccs(dev_priv, crtc->pipe, plane->id)) {
> - DRM_DEBUG_KMS("No RC support on %s\n", plane-
> >base.name);
> - return -EINVAL;
> - }
> -
>   if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 |
> DRM_MODE_ROTATE_180)) {
>   DRM_DEBUG_KMS("RC support only with 0/180 degree
> rotation %x\n",
>     plane_state->base.rotation);
-- 
Mika Kahola - Intel OTC

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Add CCS capability for sprites

2017-12-27 Thread Mika Kahola 
On Fri, 2017-12-22 at 21:22 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Allow sprites to scan out compressed framebuffers.
> 
> Since different platforms have a different set of planes that
> support CCS let's add a small helper to determine whether a
> specific plane supports CCS or not. Currently that information
> is spread around in many places, and not all the pieces of
> code even agree with each other.
> 
> In addition to allowing sprites to scan out compressed fbs,
> the other fix here is that we stop rejecting them on pipe C
> on CNL.
> 
> Cc: Ben Widawsky 
> Cc: Jason Ekstrand 
> Cc: Daniel Stone 

Reviewed-by: Mika Kahola 

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 25 --
>  drivers/gpu/drm/i915/intel_drv.h |  2 ++
>  drivers/gpu/drm/i915/intel_sprite.c  | 50
> ++--
>  3 files changed, 44 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 0dd37c854820..df29e33a2355 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3034,6 +3034,7 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
>  static int skl_check_ccs_aux_surface(struct intel_plane_state
> *plane_state)
>  {
>   struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane-
> >base.dev);
>   struct intel_crtc *crtc = to_intel_crtc(plane_state-
> >base.crtc);
>   const struct drm_framebuffer *fb = plane_state->base.fb;
>   int src_x = plane_state->base.src.x1 >> 16;
> @@ -3044,17 +3045,8 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
>   int y = src_y / vsub;
>   u32 offset;
>  
> - switch (plane->id) {
> - case PLANE_PRIMARY:
> - case PLANE_SPRITE0:
> - break;
> - default:
> - DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
> - return -EINVAL;
> - }
> -
> - if (crtc->pipe == PIPE_C) {
> - DRM_DEBUG_KMS("No RC support on pipe C\n");
> + if (!skl_plane_has_ccs(dev_priv, crtc->pipe, plane->id)) {
> + DRM_DEBUG_KMS("No RC support on %s\n", plane-
> >base.name);
>   return -EINVAL;
>   }
>  
> @@ -13161,18 +13153,11 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>   primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
>   primary->check_plane = intel_check_primary_plane;
>  
> - if (INTEL_GEN(dev_priv) >= 10) {
> + if (INTEL_GEN(dev_priv) >= 9) {
>   intel_primary_formats = skl_primary_formats;
>   num_formats = ARRAY_SIZE(skl_primary_formats);
> - modifiers = skl_format_modifiers_ccs;
>  
> - primary->update_plane = skl_update_plane;
> - primary->disable_plane = skl_disable_plane;
> - primary->get_hw_state = skl_plane_get_hw_state;
> - } else if (INTEL_GEN(dev_priv) >= 9) {
> - intel_primary_formats = skl_primary_formats;
> - num_formats = ARRAY_SIZE(skl_primary_formats);
> - if (pipe < PIPE_C)
> + if (skl_plane_has_ccs(dev_priv, pipe,
> PLANE_PRIMARY))
>   modifiers = skl_format_modifiers_ccs;
>   else
>   modifiers = skl_format_modifiers_noccs;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 30f791f89d64..059cabdcc026 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1932,6 +1932,8 @@ void skl_update_plane(struct intel_plane
> *plane,
>     const struct intel_plane_state *plane_state);
>  void skl_disable_plane(struct intel_plane *plane, struct intel_crtc
> *crtc);
>  bool skl_plane_get_hw_state(struct intel_plane *plane);
> +bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> +    enum pipe pipe, enum plane_id plane_id);
>  
>  /* intel_tv.c */
>  void intel_tv_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 349be8134c76..cb06acff283d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1161,7 +1161,17 @@ static uint32_t skl_plane_formats[] = {
>   DRM_FORMAT_VYUY,
>  };
>  
> -static const uint64_t skl_plane_format_modifiers[] = {
> +static const uint64_t skl_plane_format_modifiers_noccs[] = {
> + I915_FORMAT_MOD_Yf_TILED,
> + I915_FORMAT_MOD_Y_TILED,
> + I915_FORMAT_MOD_X_TILED,
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_FORMAT_MOD_INVALID
> +};
> +
> +static const uint64_t

Re: [Intel-gfx] [PATCH igt] lib: Convert sw_sync to use sync_file uapi imported from the kernel

2017-12-27 Thread Arkadiusz Hiler 
On Tue, Dec 19, 2017 at 03:00:03PM +, Chris Wilson wrote:
> Similar to how we are now importing the drm uapi directly into igt, we
> also would like to have a copy of auxiliary uAPI such as sync_file.
> 
> Signed-off-by: Chris Wilson 
Reviewed-by: Arkadiusz Hiler 

and pushed
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] igt/gem_busy: Remove repeated use of igt_spin_batch_new

2017-12-27 Thread Patchwork 
== Series Details ==

Series: series starting with [1/2] igt/gem_busy: Remove repeated use of 
igt_spin_batch_new
URL   : https://patchwork.freedesktop.org/series/35760/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
6d27acafa3a2d80b6330e2380a3548bc98dcc3e5 igt/gem_exec_await: Flush the WCB 
before attempting to queue more work

with latest DRM-Tip kernel build CI_DRM_3583
05590c37f480 drm-tip: 2017y-12m-25d-22h-10m-10s UTC integration manifest

No testlist changes.

Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS   (fi-snb-2520m) fdo#103713 +1
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test gem_ringfill:
Subgroup basic-default-hang:
pass   -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq) fdo#101144

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:419s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:489s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:457s
fi-elk-e7500 total:224  pass:163  dwarn:15  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:261s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:518s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:465s
fi-kbl-7560u total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  
time:509s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:563s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:428s
fi-skl-6600u total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:519s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:544s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-cnl-y total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:598s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_733/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx