Re: [Intel-gfx] [PATCH v3 4/6] drm/i915: add rcs topology to error state

[Lionel Landwerlin]

On 12/01/18 18:22, Michal Wajdeczko wrote:
On Fri, 12 Jan 2018 17:00:34 +0100, Lionel Landwerlin 
 wrote:



This might be useful information for developers looking at an error
state.

v2: Place topology towards the end of the error state (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 40 
+++

 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c

index 944059322daa..cc7f53cc9a77 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -605,6 +605,45 @@ static void err_print_uc(struct 
drm_i915_error_state_buf *m,

 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
 }
+static void err_print_rcs_topology(struct drm_i915_error_state_buf *m,
+   const struct sseu_dev_info *sseu)


As this function is similar to i915_rcs_topology from patch 3/6
maybe you should consider defining single function that will be
based on drm_printer mechanism (like already done in few places)

Michal


Thanks, will do.




+{
+    int s, ss;
+    int subslice_stride =
+    DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+
+    /* Unavailable prior to Gen 8. */
+    if (sseu->max_slices == 0)
+    return;
+
+    err_printf(m, "RCS topology:\n");
+
+    for (s = 0; s < sseu->max_slices; s++) {
+    err_printf(m, "  slice%i %u subslice(s) (0x%hhx):\n",
+   s, hweight8(sseu->subslice_mask[s]),
+   sseu->subslice_mask[s]);
+
+    for (ss = 0; ss < sseu->max_subslices; ss++) {
+    int eu_group, n_subslice_eus = 0;
+
+    for (eu_group = 0; eu_group < subslice_stride; 
eu_group++) {

+    n_subslice_eus +=
+    hweight8(sseu_eu_mask(sseu, s, ss, eu_group));
+    }
+
+    err_printf(m, "    subslice%i: %u EUs (", ss, 
n_subslice_eus);

+    for (eu_group = 0;
+ eu_group < max(0, subslice_stride - 1);
+ eu_group++) {
+    u8 val = sseu_eu_mask(sseu, s, ss, eu_group);
+    err_printf(m, " 0x%hhx", val);
+    }
+    err_printf(m, "0x%hhx)\n",
+   sseu_eu_mask(sseu, s, ss, subslice_stride - 1));
+    }
+    }
+}
+
 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 const struct i915_gpu_state *error)
 {
@@ -787,6 +826,7 @@ int i915_error_state_to_str(struct 
drm_i915_error_state_buf *m,

 intel_display_print_error_state(m, error->display);
err_print_capabilities(m, >device_info);
+    err_print_rcs_topology(m, _INFO(dev_priv)->sseu);
 err_print_params(m, >params);
 err_print_uc(m, >uc);




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Re: [Intel-gfx] [PATCH 3/3] drm/i915/psr: Avoid initializing PSR if there is no sink support.

[Rodrigo Vivi]

On Fri, Jan 12, 2018 at 11:33:08PM +, Rodrigo Vivi wrote:
> On Wed, Jan 03, 2018 at 09:38:24PM +, Dhinakaran Pandiyan wrote:
> > DPCD read for the eDP is complete by the time intel_psr_init() is
> > called, which means we can avoid initializing PSR structures and state
> > if there is no sink support.
> > 
> > Cc: Rodrigo Vivi 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Dhinakaran Pandiyan 
> 
> sorry for the delay on this. you had responded to my questions on previous
> thread and after reading your response again and applying the code it made 
> sense
> why to use sink_support instead of CAN_PSR on init.
> 
> Reviewed-by: Rodrigo Vivi 

now merged, thanks.

> 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 7 ++-
> >  drivers/gpu/drm/i915/intel_psr.c| 9 +
> >  2 files changed, 15 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 6890340387b7..cc659b4b2a45 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2521,14 +2521,19 @@ static int i915_edp_psr_status(struct seq_file *m, 
> > void *data)
> > u32 stat[3];
> > enum pipe pipe;
> > bool enabled = false;
> > +   bool sink_support;
> >  
> > if (!HAS_PSR(dev_priv))
> > return -ENODEV;
> >  
> > +   sink_support = dev_priv->psr.sink_support;
> > +   seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
> > +   if (!sink_support)
> > +   return 0;
> > +
> > intel_runtime_pm_get(dev_priv);
> >  
> > mutex_lock(_priv->psr.lock);
> > -   seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
> > seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
> > seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
> > seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index df9b1d7baefb..863650366425 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -503,6 +503,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> > if (!crtc_state->has_psr)
> > return;
> >  
> > +   if (WARN_ON(!CAN_PSR(dev_priv)))
> > +   return;
> > +
> > WARN_ON(dev_priv->drrs.dp);
> > mutex_lock(_priv->psr.lock);
> > if (dev_priv->psr.enabled) {
> > @@ -633,6 +636,9 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> > if (!old_crtc_state->has_psr)
> > return;
> >  
> > +   if (WARN_ON(!CAN_PSR(dev_priv)))
> > +   return;
> > +
> > mutex_lock(_priv->psr.lock);
> > if (!dev_priv->psr.enabled) {
> > mutex_unlock(_priv->psr.lock);
> > @@ -913,6 +919,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> > dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
> > HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
> >  
> > +   if (!dev_priv->psr.sink_support)
> > +   return;
> > +
> > /* Per platform default: all disabled. */
> > if (i915_modparams.enable_psr == -1)
> > i915_modparams.enable_psr = 0;
> > -- 
> > 2.11.0
> > 
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/psr: Avoid initializing PSR if there is no sink support.

[Rodrigo Vivi]

On Wed, Jan 03, 2018 at 09:38:24PM +, Dhinakaran Pandiyan wrote:
> DPCD read for the eDP is complete by the time intel_psr_init() is
> called, which means we can avoid initializing PSR structures and state
> if there is no sink support.
> 
> Cc: Rodrigo Vivi 
> Cc: Ville Syrjälä 
> Signed-off-by: Dhinakaran Pandiyan 

sorry for the delay on this. you had responded to my questions on previous
thread and after reading your response again and applying the code it made sense
why to use sink_support instead of CAN_PSR on init.

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 ++-
>  drivers/gpu/drm/i915/intel_psr.c| 9 +
>  2 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6890340387b7..cc659b4b2a45 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2521,14 +2521,19 @@ static int i915_edp_psr_status(struct seq_file *m, 
> void *data)
>   u32 stat[3];
>   enum pipe pipe;
>   bool enabled = false;
> + bool sink_support;
>  
>   if (!HAS_PSR(dev_priv))
>   return -ENODEV;
>  
> + sink_support = dev_priv->psr.sink_support;
> + seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
> + if (!sink_support)
> + return 0;
> +
>   intel_runtime_pm_get(dev_priv);
>  
>   mutex_lock(_priv->psr.lock);
> - seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
>   seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
>   seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
>   seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index df9b1d7baefb..863650366425 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -503,6 +503,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>   if (!crtc_state->has_psr)
>   return;
>  
> + if (WARN_ON(!CAN_PSR(dev_priv)))
> + return;
> +
>   WARN_ON(dev_priv->drrs.dp);
>   mutex_lock(_priv->psr.lock);
>   if (dev_priv->psr.enabled) {
> @@ -633,6 +636,9 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>   if (!old_crtc_state->has_psr)
>   return;
>  
> + if (WARN_ON(!CAN_PSR(dev_priv)))
> + return;
> +
>   mutex_lock(_priv->psr.lock);
>   if (!dev_priv->psr.enabled) {
>   mutex_unlock(_priv->psr.lock);
> @@ -913,6 +919,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
>   dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
>   HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
>  
> + if (!dev_priv->psr.sink_support)
> + return;
> +
>   /* Per platform default: all disabled. */
>   if (i915_modparams.enable_psr == -1)
>   i915_modparams.enable_psr = 0;
> -- 
> 2.11.0
> 
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/vblank: Fix return type for drm_vblank_count()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/vblank: Fix return type for 
drm_vblank_count()
URL   : https://patchwork.freedesktop.org/series/36435/
State : failure

== Summary ==

Test gem_caching:
Subgroup writes:
pass   -> INCOMPLETE (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-pri-indfb-multidraw:
pass   -> FAIL   (shard-snb) fdo#103167
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Test kms_flip:
Subgroup vblank-vs-suspend-interruptible:
incomplete -> PASS   (shard-hsw) fdo#100368 +1
Subgroup vblank-vs-suspend:
pass   -> SKIP   (shard-snb) fdo#102365

fdo#103167 
fdo#101623 
fdo#100368 
fdo#102365 

shard-hswtotal:2713 pass:1537 dwarn:1   dfail:0   fail:10  skip:1165 
time:9012s
shard-snbtotal:2683 pass:1294 dwarn:1   dfail:0   fail:12  skip:1375 
time:7610s
Blacklisted hosts:
shard-apltotal:2713 pass:1687 dwarn:1   dfail:0   fail:24  skip:1001 
time:13691s
shard-kbltotal:2708 pass:1804 dwarn:5   dfail:0   fail:24  skip:874 
time:10328s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7660/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/vblank: Fix return type for drm_vblank_count()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/vblank: Fix return type for 
drm_vblank_count()
URL   : https://patchwork.freedesktop.org/series/36435/
State : success

== Summary ==

Series 36435v1 series starting with [1/5] drm/vblank: Fix return type for 
drm_vblank_count()
https://patchwork.freedesktop.org/api/1.0/series/36435/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-skl-6700k2) fdo#104108

fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:424s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:370s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:487s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:461s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:273s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:467s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:578s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:431s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:108  pass:96   dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:538s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:395s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:573s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:472s

fcf7fdfd2db6cfe8e529c79c5822f555a8b38fd4 drm-tip: 2018y-01m-12d-17h-40m-49s UTC 
integration manifest
ef67bfb35c68 drm/i915: Estimate and update missed vblanks.
b1edcc47812a drm/vblank: Restoring vblank counts after device PM events.
365390c83462 drm/vblank: Do not update vblank count if interrupts are already 
disabled.
18e5209cfde5 drm/vblank: Fix data type width for drm_crtc_arm_vblank_event()
60165b22a0be drm/vblank: Fix return type for drm_vblank_count()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7660/issues.html
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[Intel-gfx] [PATCH 2/5] drm/vblank: Fix data type width for drm_crtc_arm_vblank_event()

[Dhinakaran Pandiyan]

Now that drm_vblank_count() returns all bits of the vblank count, update
drm_crtc_arm_vblank_event() so that it queues the correct sequence.
Otherwise, this leads to prolonged waits for a vblank sequence when the
current count is >=2^32.

Cc: Keith Packard 
Cc: Michel Dänzer 
Cc: Daniel Vetter 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/drm_vblank.c | 4 ++--
 include/drm/drm_vblank.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 768a8e44d99b..f2bf1f5dbaa5 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -292,11 +292,11 @@ static u64 drm_vblank_count(struct drm_device *dev, 
unsigned int pipe)
  * This is mostly useful for hardware that can obtain the scanout position, but
  * doesn't have a hardware frame counter.
  */
-u32 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc)
+u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc)
 {
struct drm_device *dev = crtc->dev;
unsigned int pipe = drm_crtc_index(crtc);
-   u32 vblank;
+   u64 vblank;
unsigned long flags;
 
WARN_ONCE(drm_debug & DRM_UT_VBL && !dev->driver->get_vblank_timestamp,
diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h
index 848b463a0af5..a4c3b0a0a197 100644
--- a/include/drm/drm_vblank.h
+++ b/include/drm/drm_vblank.h
@@ -179,7 +179,7 @@ void drm_crtc_wait_one_vblank(struct drm_crtc *crtc);
 void drm_crtc_vblank_off(struct drm_crtc *crtc);
 void drm_crtc_vblank_reset(struct drm_crtc *crtc);
 void drm_crtc_vblank_on(struct drm_crtc *crtc);
-u32 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);
+u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);
 
 bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
   unsigned int pipe, int *max_error,
-- 
2.11.0

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[Intel-gfx] [PATCH 5/5] drm/i915: Estimate and update missed vblanks.

[Dhinakaran Pandiyan]

The frame counter may have got reset between disabling and enabling vblank
interrupts due to DMC putting the hardware to DC5/6 state if PSR was
active. The frame counter also could have stalled if PSR is active in cases
where there is no DMC. The frame counter resetting as a user visible impact
of screen freezes. Use drm_vblank_restore() to compute missed vblanks
in the duration for which vblank interrupts are disabled. There's no need
particularly check if PSR was active in the interrupt disabled duration.

Enabling vblank interrupts wakes up the hardware from DC5/6 and prevents it
from going back again as long as the there are pending interrupts. So, we
don't have to explicity disallow DC5/6 after enabling vblank interrupts
to keep the counter running.

Let's not apply this to CHV for now, as enabling interrupts does not
prevent the hardware from activating PSR and thereby stalling the counter.

Cc: Rodrigo Vivi 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_irq.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..db3466ec6faa 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2956,6 +2956,9 @@ static int ironlake_enable_vblank(struct drm_device *dev, 
unsigned int pipe)
ilk_enable_display_irq(dev_priv, bit);
spin_unlock_irqrestore(_priv->irq_lock, irqflags);
 
+   if (HAS_PSR(dev_priv))
+   drm_vblank_restore(dev, pipe);
+
return 0;
 }
 
@@ -2968,6 +2971,9 @@ static int gen8_enable_vblank(struct drm_device *dev, 
unsigned int pipe)
bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
spin_unlock_irqrestore(_priv->irq_lock, irqflags);
 
+   if (HAS_PSR(dev_priv))
+   drm_vblank_restore(dev, pipe);
+
return 0;
 }
 
-- 
2.11.0

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[Intel-gfx] [PATCH 1/5] drm/vblank: Fix return type for drm_vblank_count()

[Dhinakaran Pandiyan]

drm_vblank_count() has a u32 type returning what is a 64-bit vblank count.
The effect of this is when drm_wait_vblank_ioctl() tries to widen the user
space requested vblank sequence using this clipped 32-bit count(when the
value is >= 2^32) as reference, the requested sequence remains a 32-bit
value and gets queued like that. However, the code that checks if the
requested sequence has passed compares this against the 64-bit vblank
count.

Cc: Keith Packard 
Cc: Michel Dänzer 
Cc: Daniel Vetter 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/drm_vblank.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 32d9bcf5be7f..768a8e44d99b 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -271,7 +271,7 @@ static void drm_update_vblank_count(struct drm_device *dev, 
unsigned int pipe,
store_vblank(dev, pipe, diff, t_vblank, cur_vblank);
 }
 
-static u32 drm_vblank_count(struct drm_device *dev, unsigned int pipe)
+static u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe)
 {
struct drm_vblank_crtc *vblank = >vblank[pipe];
 
-- 
2.11.0

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[Intel-gfx] [PATCH 4/5] drm/vblank: Restoring vblank counts after device PM events.

[Dhinakaran Pandiyan]

The HW frame counter can get reset if device enters a low power state after
vblank interrupts were disabled. This messes up any following vblank count
update as a negative diff (huge unsigned diff) is calculated from the HW
frame counter change. We cannot ignore negative diffs altogther as there
could be legitimate wrap arounds. So, allow drivers to update vblank->count
with missed vblanks for the time interrupts were disabled. This is similar
to _crtc_vblank_on() except that vblanks interrupts are not enabled at the
end as this function is expected to be called from the driver
_enable_vblank() vfunc.

v2: drm_crtc_vblank_restore should take crtc as arg. (Chris)
Add docs and sprinkle some asserts.

Cc: Daniel Vetter 
Cc: Chris Wilson 
Cc: Michel Dänzer 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/drm_vblank.c | 59 
 include/drm/drm_vblank.h |  2 ++
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 2559d2d7b907..2690966694f0 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -1237,6 +1237,65 @@ void drm_crtc_vblank_on(struct drm_crtc *crtc)
 }
 EXPORT_SYMBOL(drm_crtc_vblank_on);
 
+/**
+ * drm_vblank_restore - estimated vblanks using timestamps and update it.
+ *
+ * Power manamement features can cause frame counter resets between vblank
+ * disable and enable. Drivers can then use this function in their
+ * _crtc_funcs.enable_vblank implementation to estimate the vblanks since
+ * the last _crtc_funcs.disable_vblank.
+ *
+ * This function is the legacy version of drm_crtc_vblank_restore().
+ */
+void drm_vblank_restore(struct drm_device *dev, unsigned int pipe)
+{
+   ktime_t t_vblank;
+   struct drm_vblank_crtc *vblank;
+   int framedur_ns;
+   u64 diff_ns;
+   u32 cur_vblank, diff = 1;
+   int count = DRM_TIMESTAMP_MAXRETRIES;
+
+   if (WARN_ON(pipe >= dev->num_crtcs))
+   return;
+
+   assert_spin_locked(>vbl_lock);
+   assert_spin_locked(>vblank_time_lock);
+
+   vblank = >vblank[pipe];
+   WARN_ONCE((drm_debug & DRM_UT_VBL) && !vblank->framedur_ns,
+ "Cannot compute missed vblanks without frame duration\n");
+   framedur_ns = vblank->framedur_ns;
+
+   do {
+   cur_vblank = __get_vblank_counter(dev, pipe);
+   drm_get_last_vbltimestamp(dev, pipe, _vblank, false);
+   } while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);
+
+   diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
+   if (framedur_ns)
+   diff = DIV_ROUND_CLOSEST_ULL(diff_ns, framedur_ns);
+
+
+   DRM_DEBUG_VBL("missed %d vblanks in %lld ns, frame duration=%d ns, 
hw_diff=%d\n",
+ diff, diff_ns, framedur_ns, cur_vblank - vblank->last);
+   store_vblank(dev, pipe, diff, t_vblank, cur_vblank);
+}
+EXPORT_SYMBOL(drm_vblank_restore);
+
+/**
+ * drm_crtc_vblank_restore - estimate vblanks using timestamps and update it.
+ * Power manamement features can cause frame counter resets between vblank
+ * disable and enable. Drivers can then use this function in their
+ * _crtc_funcs.enable_vblank implementation to estimate the vblanks since
+ * the last _crtc_funcs.disable_vblank.
+ */
+void drm_crtc_vblank_restore(struct drm_crtc *crtc)
+{
+   drm_vblank_restore(crtc->dev, drm_crtc_index(crtc));
+}
+EXPORT_SYMBOL(drm_crtc_vblank_restore);
+
 static void drm_legacy_vblank_pre_modeset(struct drm_device *dev,
  unsigned int pipe)
 {
diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h
index a4c3b0a0a197..16d46e2a6854 100644
--- a/include/drm/drm_vblank.h
+++ b/include/drm/drm_vblank.h
@@ -180,6 +180,8 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc);
 void drm_crtc_vblank_reset(struct drm_crtc *crtc);
 void drm_crtc_vblank_on(struct drm_crtc *crtc);
 u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);
+void drm_vblank_restore(struct drm_device *dev, unsigned int pipe);
+void drm_crtc_vblank_restore(struct drm_crtc *crtc);
 
 bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
   unsigned int pipe, int *max_error,
-- 
2.11.0

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[Intel-gfx] [PATCH 3/5] drm/vblank: Do not update vblank count if interrupts are already disabled.

[Dhinakaran Pandiyan]

Updating vblank counts requires register reads and these reads may not
return meaningful values if the device was in a low power state after
vblank interrupts were last disabled. So, update the count only if vblank
interrupts are enabled. Secondly, this means the registers should be read
before disabling vblank interrupts.

v2: Don't check vblank->enabled outside it's lock (Chris)

Cc: Chris Wilson 
Cc: Daniel Vetter 
Cc: Michel Dänzer 
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/drm_vblank.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index f2bf1f5dbaa5..2559d2d7b907 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -347,23 +347,25 @@ void drm_vblank_disable_and_save(struct drm_device *dev, 
unsigned int pipe)
spin_lock_irqsave(>vblank_time_lock, irqflags);
 
/*
-* Only disable vblank interrupts if they're enabled. This avoids
-* calling the ->disable_vblank() operation in atomic context with the
-* hardware potentially runtime suspended.
+* Update vblank count and disable vblank interrupts only if the
+* interrupts were enabled. This avoids calling the ->disable_vblank()
+* operation in atomic context with the hardware potentially runtime
+* suspended.
 */
-   if (vblank->enabled) {
-   __disable_vblank(dev, pipe);
-   vblank->enabled = false;
-   }
+   if (!vblank->enabled)
+   goto out;
 
/*
-* Always update the count and timestamp to maintain the
+* Update the count and timestamp to maintain the
 * appearance that the counter has been ticking all along until
 * this time. This makes the count account for the entire time
 * between drm_crtc_vblank_on() and drm_crtc_vblank_off().
 */
drm_update_vblank_count(dev, pipe, false);
+   __disable_vblank(dev, pipe);
+   vblank->enabled = false;
 
+out:
spin_unlock_irqrestore(>vblank_time_lock, irqflags);
 }
 
-- 
2.11.0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Convert intel_hpd_irq_event() into an encoder hotplug hook

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Convert intel_hpd_irq_event() into 
an encoder hotplug hook
URL   : https://patchwork.freedesktop.org/series/36431/
State : failure

== Summary ==

Series 36431v1 series starting with [1/3] drm/i915: Convert 
intel_hpd_irq_event() into an encoder hotplug hook
https://patchwork.freedesktop.org/api/1.0/series/36431/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup hdmi-hpd-fast:
skip   -> FAIL   (fi-kbl-7500u) fdo#102672
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-flip-after-cursor-atomic:
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-flip-after-cursor-legacy:
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-flip-before-cursor-atomic:
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-flip-before-cursor-legacy:
pass   -> FAIL   (fi-skl-6770hq)
Subgroup basic-flip-before-cursor-varying-size:
pass   -> FAIL   (fi-skl-6770hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> INCOMPLETE (fi-hsw-4770) fdo#103375

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:434s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:489s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:468s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:276s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:468s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:1   skip:23  
time:463s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:501s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:506s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:578s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:425s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:515s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-skl-6770hqtotal:288  pass:260  dwarn:0   dfail:0   fail:8   skip:20  
time:483s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:534s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:395s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:577s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:469s

fcf7fdfd2db6cfe8e529c79c5822f555a8b38fd4 drm-tip: 2018y-01m-12d-17h-40m-49s UTC 
integration manifest
7d0c0ca1a0de drm/i915: Move SST DP link retraining into the 

[Intel-gfx] [PATCH 3/3] drm/i915: Move SST DP link retraining into the ->post_hotplug() hook

[Ville Syrjala]

From: Ville Syrjälä 

Doing link retraining from the short pulse handler is problematic since
that might introduce deadlocks with MST sideband processing. Currently
we don't retrain MST links from this code, but we want to change that.
So better to move the entire thing to the hotplug work. We can utilize
the new encoder->hotplug() hook for this.

The only thing we leave in the short pulse handler is the link status
check. That one still depends on the link parameters stored under
intel_dp, so no locking around that but races should be mostly harmless
as the actual retraining code will recheck the link state if we
end up there by mistake.

v2: Rebase due to ->post_hotplug() now being just ->hotplug()
Check the connector type to figure out if we should do
the HDMI thing or the DP think for DDI

Cc: Manasi Navare 
Cc: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c |  10 +-
 drivers/gpu/drm/i915/intel_dp.c  | 196 ++-
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 3 files changed, 120 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 25793bdc692f..5f3d58f1ae6e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2880,7 +2880,10 @@ static bool intel_ddi_hotplug(struct intel_encoder 
*encoder,
drm_modeset_acquire_init(, 0);
 
for (;;) {
-   ret = intel_hdmi_reset_link(encoder, );
+   if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
+   ret = intel_hdmi_reset_link(encoder, );
+   else
+   ret = intel_dp_retrain_link(encoder, );
 
if (ret == -EDEADLK) {
drm_modeset_backoff();
@@ -3007,10 +3010,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
drm_encoder_init(_priv->drm, encoder, _ddi_funcs,
 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
 
-   if (init_hdmi)
-   intel_encoder->hotplug = intel_ddi_hotplug;
-   else
-   intel_encoder->hotplug = intel_encoder_hotplug;
+   intel_encoder->hotplug = intel_ddi_hotplug;
intel_encoder->compute_output_type = intel_ddi_compute_output_type;
intel_encoder->compute_config = intel_ddi_compute_config;
intel_encoder->enable = intel_enable_ddi;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6bbf14410c2a..152016e09a11 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4275,12 +4275,83 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
return -EINVAL;
 }
 
-static void
-intel_dp_retrain_link(struct intel_dp *intel_dp)
+static bool
+intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
+{
+   u8 link_status[DP_LINK_STATUS_SIZE];
+
+   if (!intel_dp_get_link_status(intel_dp, link_status)) {
+   DRM_ERROR("Failed to get link status\n");
+   return false;
+   }
+
+   /*
+* Validate the cached values of intel_dp->link_rate and
+* intel_dp->lane_count before attempting to retrain.
+*/
+   if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
+   intel_dp->lane_count))
+   return false;
+
+   /* Retrain if Channel EQ or CR not ok */
+   return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
+}
+
+/*
+ * If display is now connected check links status,
+ * there has been known issues of link loss triggering
+ * long pulse.
+ *
+ * Some sinks (eg. ASUS PB287Q) seem to perform some
+ * weird HPD ping pong during modesets. So we can apparently
+ * end up with HPD going low during a modeset, and then
+ * going back up soon after. And once that happens we must
+ * retrain the link to get a picture. That's in case no
+ * userspace component reacted to intermittent HPD dip.
+ */
+int intel_dp_retrain_link(struct intel_encoder *encoder,
+ struct drm_modeset_acquire_ctx *ctx)
 {
-   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+   struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+   struct intel_connector *connector = intel_dp->attached_connector;
+   struct drm_connector_state *conn_state;
+   struct intel_crtc_state *crtc_state;
+   struct intel_crtc *crtc;
+   int ret;
+
+   /* FIXME handle the MST connectors as well */
+
+   if (!connector || connector->base.status != connector_status_connected)
+   return 0;
+
+   ret = 

[Intel-gfx] [PATCH 1/3] drm/i915: Convert intel_hpd_irq_event() into an encoder hotplug hook

[Ville Syrjala]

From: Ville Syrjälä 

Allow encoders to customize their hotplug processing by moving the
intel_hpd_irq_event() code into an encoder hotplug vfunc. Currently
only SDVO needs this to re-enable hotplug signalling in the SDVO
chip. We'll use this same hook for DP/HDMI link management later.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_crt.c |  4 +++-
 drivers/gpu/drm/i915/intel_ddi.c |  1 +
 drivers/gpu/drm/i915/intel_dp.c  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  6 --
 drivers/gpu/drm/i915/intel_hdmi.c|  1 +
 drivers/gpu/drm/i915/intel_hotplug.c | 24 
 drivers/gpu/drm/i915/intel_sdvo.c| 12 ++--
 7 files changed, 32 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9f31aea51dff..9bc47cff5409 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -966,8 +966,10 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
 
if (I915_HAS_HOTPLUG(dev_priv) &&
-   !dmi_check_system(intel_spurious_crt_detect))
+   !dmi_check_system(intel_spurious_crt_detect)) {
crt->base.hpd_pin = HPD_CRT;
+   crt->base.hotplug = intel_encoder_hotplug;
+   }
 
if (HAS_DDI(dev_priv)) {
crt->base.port = PORT_E;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6260a882fbe4..1aeae3e97013 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2866,6 +2866,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
drm_encoder_init(_priv->drm, encoder, _ddi_funcs,
 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
 
+   intel_encoder->hotplug = intel_encoder_hotplug;
intel_encoder->compute_output_type = intel_ddi_compute_output_type;
intel_encoder->compute_config = intel_ddi_compute_config;
intel_encoder->enable = intel_enable_ddi;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 68229f53d5b8..6bbf14410c2a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6400,6 +6400,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 "DP %c", port_name(port)))
goto err_encoder_init;
 
+   intel_encoder->hotplug = intel_encoder_hotplug;
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 731dc36d7129..7537b2d542fd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -214,7 +214,8 @@ struct intel_encoder {
enum intel_output_type type;
enum port port;
unsigned int cloneable;
-   void (*hot_plug)(struct intel_encoder *);
+   bool (*hotplug)(struct intel_encoder *encoder,
+   struct intel_connector *connector);
enum intel_output_type (*compute_output_type)(struct intel_encoder *,
  struct intel_crtc_state *,
  struct 
drm_connector_state *);
@@ -1690,7 +1691,8 @@ int intel_dsi_dcs_init_backlight_funcs(struct 
intel_connector *intel_connector);
 void intel_dvo_init(struct drm_i915_private *dev_priv);
 /* intel_hotplug.c */
 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
-
+bool intel_encoder_hotplug(struct intel_encoder *encoder,
+  struct intel_connector *connector);
 
 /* legacy fbdev emulation in intel_fbdev.c */
 #ifdef CONFIG_DRM_FBDEV_EMULATION
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 691f15b59124..4a93cfd7a28e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2348,6 +2348,7 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv,
 _hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
 "HDMI %c", port_name(port));
 
+   intel_encoder->hotplug = intel_encoder_hotplug;
intel_encoder->compute_config = intel_hdmi_compute_config;
if (HAS_PCH_SPLIT(dev_priv)) {
intel_encoder->disable = pch_disable_hdmi;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c 
b/drivers/gpu/drm/i915/intel_hotplug.c
index 875d5d218d5c..0191c7831a06 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -263,24 +263,25 @@ static void intel_hpd_irq_storm_reenable_work(struct 
work_struct *work)
intel_runtime_pm_put(dev_priv);
 }
 
-static bool intel_hpd_irq_event(struct drm_device *dev,

[Intel-gfx] [PATCH 2/3] drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD

[Ville Syrjala]

From: Ville Syrjälä 

The LG 4k TV I have doesn't deassert HPD when I turn the TV off, but
when I turn it back on it will pulse the HPD line. By that time it has
forgotten everything we told it about scrambling and the clock ratio.
Hence if we want to get a picture out if it again we have to tell it
whether we're currently sending scrambled data or not. Implement
that via the encoder->hotplug() hook.

v2: Force a full modeset to not follow the HDMI 2.0 spec more
closely (Shashank)

Cc: Shashank Sharma 
Cc: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c | 146 ++-
 1 file changed, 145 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1aeae3e97013..25793bdc692f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -25,6 +25,7 @@
  *
  */
 
+#include 
 #include "i915_drv.h"
 #include "intel_drv.h"
 
@@ -2756,6 +2757,146 @@ intel_ddi_init_dp_connector(struct intel_digital_port 
*intel_dig_port)
return connector;
 }
 
+static int modeset_pipe(struct drm_crtc *crtc,
+   struct drm_modeset_acquire_ctx *ctx)
+{
+   struct drm_atomic_state *state;
+   struct drm_crtc_state *crtc_state;
+   int ret;
+
+   state = drm_atomic_state_alloc(crtc->dev);
+   if (!state)
+   return -ENOMEM;
+
+   state->acquire_ctx = ctx;
+
+   crtc_state = drm_atomic_get_crtc_state(state, crtc);
+   if (IS_ERR(crtc_state)) {
+   ret = PTR_ERR(crtc_state);
+   goto out;
+   }
+
+   crtc_state->mode_changed = true;
+
+   ret = drm_atomic_add_affected_connectors(state, crtc);
+   if (ret)
+   goto out;
+
+   ret = drm_atomic_add_affected_planes(state, crtc);
+   if (ret)
+   goto out;
+
+   ret = drm_atomic_commit(state);
+   if (ret)
+   goto out;
+
+   return 0;
+
+ out:
+   drm_atomic_state_put(state);
+
+   return ret;
+}
+
+static int intel_hdmi_reset_link(struct intel_encoder *encoder,
+struct drm_modeset_acquire_ctx *ctx)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_hdmi *hdmi = enc_to_intel_hdmi(>base);
+   struct intel_connector *connector = hdmi->attached_connector;
+   struct i2c_adapter *adapter =
+   intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
+   struct drm_connector_state *conn_state;
+   struct intel_crtc_state *crtc_state;
+   struct intel_crtc *crtc;
+   u8 config;
+   int ret;
+
+   if (!connector || connector->base.status != connector_status_connected)
+   return 0;
+
+   ret = drm_modeset_lock(_priv->drm.mode_config.connection_mutex, 
ctx);
+   if (ret)
+   return ret;
+
+   conn_state = connector->base.state;
+
+   crtc = to_intel_crtc(conn_state->crtc);
+   if (!crtc)
+   return 0;
+
+   ret = drm_modeset_lock(>base.mutex, ctx);
+   if (ret)
+   return ret;
+
+   crtc_state = to_intel_crtc_state(crtc->base.state);
+
+   WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
+
+   if (!crtc_state->base.active)
+   return 0;
+
+   if (!crtc_state->hdmi_high_tmds_clock_ratio &&
+   !crtc_state->hdmi_scrambling)
+   return 0;
+
+   if (conn_state->commit &&
+   !try_wait_for_completion(_state->commit->hw_done))
+   return 0;
+
+   ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, );
+   if (ret < 0) {
+   DRM_ERROR("Failed to read TMDS config: %d\n", ret);
+   return 0;
+   }
+
+   if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
+   crtc_state->hdmi_high_tmds_clock_ratio &&
+   !!(config & SCDC_SCRAMBLING_ENABLE) ==
+   crtc_state->hdmi_scrambling)
+   return 0;
+
+   /*
+* HDMI 2.0 says that one should not send scrambled data
+* prior to configuring the sink scrambling, and that
+* TMDS clock/data transmission should be suspended when
+* changing the TMDS clock rate in the sink. So let's
+* just do a full modeset here, even though some sinks
+* would be perfectly happy if were to just reconfigure
+* the SCDC settings on the fly.
+*/
+   return modeset_pipe(>base, ctx);
+}
+
+static bool intel_ddi_hotplug(struct intel_encoder *encoder,
+ struct intel_connector *connector)
+{
+   struct drm_modeset_acquire_ctx ctx;
+   bool changed;
+   int ret;
+
+   changed = intel_encoder_hotplug(encoder, connector);
+
+   drm_modeset_acquire_init(, 0);
+
+   for (;;) {
+   

Re: [Intel-gfx] [PATCH v2] drm/i915: Use the engine name directly in the error_state file

[Michel Thierry]

On 1/9/2018 5:21 PM, Michel Thierry wrote:

Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.

v2: Better invalid engine_id handling, capture_bo will not be able know
the engine_id and end up with -1 (Michal).


Hi,

Fi.CI.IGT didn't catch any failure, apart from intel_error_decode (which 
didn't complain), I'm not sure which other tool could be using these names.


And now that there are icl patches, this will help there too.



Suggested-by: Michal Wajdeczko 
Signed-off-by: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_gpu_error.c | 33 -
  1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 94499c24f279..422e302161e5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -34,16 +34,22 @@

  #include "i915_drv.h"

-static const char *engine_str(int engine)
-{
-   switch (engine) {
-   case RCS: return "render";
-   case VCS: return "bsd";
-   case BCS: return "blt";
-   case VECS: return "vebox";
-   case VCS2: return "bsd2";
-   default: return "";
-   }
+static inline const char *intel_engine_name(struct intel_engine_cs *engine)
+{
+   return engine ? engine->name : "";
+}
+
+static inline struct intel_engine_cs *
+intel_engine_lookup(struct drm_i915_private *i915, int engine_id)
+{
+   if (engine_id < 0 || engine_id >= I915_NUM_ENGINES)
+   return NULL;
+   return i915->engine[engine_id];
+}
+
+static const char *engine_str(struct drm_i915_private *i915, int engine_id)
+{
+   return intel_engine_name(intel_engine_lookup(i915, engine_id));
  }

  static const char *tiling_flag(int tiling)
@@ -345,7 +351,7 @@ static void print_error_buffers(struct 
drm_i915_error_state_buf *m,
 err_puts(m, purgeable_flag(err->purgeable));
 err_puts(m, err->userptr ? " userptr" : "");
 err_puts(m, err->engine != -1 ? " " : "");
-   err_puts(m, engine_str(err->engine));
+   err_puts(m, engine_str(m->i915, err->engine));
 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));

 if (err->name)
@@ -417,7 +423,8 @@ static void error_print_engine(struct 
drm_i915_error_state_buf *m,
  {
 int n;

-   err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
+   err_printf(m, "%s command stream:\n", engine_str(m->i915,
+ee->engine_id));
 err_printf(m, "  IDLE?: %s\n", yesno(ee->idle));
 err_printf(m, "  START: 0x%08x\n", ee->start);
 err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
@@ -633,7 +640,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
 if (error->engine[i].hangcheck_stalled &&
 error->engine[i].context.pid) {
 err_printf(m, "Active process (on ring %s): %s [%d], score 
%d\n",
-  engine_str(i),
+  engine_str(m->i915, i),
error->engine[i].context.comm,
error->engine[i].context.pid,
error->engine[i].context.ban_score);
--
2.15.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pmu: fix sizeof on attr, should be *attr

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: fix sizeof on attr, should be *attr
URL   : https://patchwork.freedesktop.org/series/36423/
State : failure

== Summary ==

Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-hsw) fdo#104218 +1
Test gem_eio:
Subgroup in-flight-contexts:
dmesg-warn -> PASS   (shard-snb) fdo#104058 +1
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
pass   -> SKIP   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass   -> FAIL   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Test kms_flip:
Subgroup vblank-vs-modeset-suspend:
pass   -> INCOMPLETE (shard-hsw)
Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb) fdo#104600
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104600 https://bugs.freedesktop.org/show_bug.cgi?id=104600

shard-hswtotal:2642 pass:1488 dwarn:1   dfail:0   fail:10  skip:1142 
time:8481s
shard-snbtotal:2713 pass:1310 dwarn:1   dfail:0   fail:11  skip:1391 
time:7870s
Blacklisted hosts:
shard-apltotal:2691 pass:1662 dwarn:1   dfail:0   fail:25  skip:1001 
time:13211s
shard-kbltotal:2713 pass:1793 dwarn:20  dfail:0   fail:24  skip:876 
time:10674s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7658/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/pmu: fix noderef.cocci warnings

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/pmu: fix noderef.cocci warnings
URL   : https://patchwork.freedesktop.org/series/36421/
State : success

== Summary ==

Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> SKIP   (shard-hsw) fdo#103540
Test gem_eio:
Subgroup in-flight-contexts:
dmesg-warn -> PASS   (shard-snb) fdo#104058 +1
Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb) fdo#104600
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup blt-wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-snb) fdo#104218

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104600 https://bugs.freedesktop.org/show_bug.cgi?id=104600
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218

shard-hswtotal:2655 pass:1506 dwarn:1   dfail:0   fail:11  skip:1136 
time:8859s
shard-snbtotal:2713 pass:1309 dwarn:1   dfail:0   fail:12  skip:1391 
time:7857s
Blacklisted hosts:
shard-apltotal:2713 pass:1686 dwarn:1   dfail:0   fail:24  skip:1001 
time:13521s
shard-kbltotal:2713 pass:1809 dwarn:1   dfail:1   fail:24  skip:878 
time:10629s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7657/shards.html
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Re: [Intel-gfx] [PATCH v3 4/6] drm/i915: add rcs topology to error state

[Michal Wajdeczko]

On Fri, 12 Jan 2018 17:00:34 +0100, Lionel Landwerlin  
 wrote:



This might be useful information for developers looking at an error
state.

v2: Place topology towards the end of the error state (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 40  
+++

 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c  
b/drivers/gpu/drm/i915/i915_gpu_error.c

index 944059322daa..cc7f53cc9a77 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -605,6 +605,45 @@ static void err_print_uc(struct  
drm_i915_error_state_buf *m,

print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
 }
+static void err_print_rcs_topology(struct drm_i915_error_state_buf *m,
+  const struct sseu_dev_info *sseu)


As this function is similar to i915_rcs_topology from patch 3/6
maybe you should consider defining single function that will be
based on drm_printer mechanism (like already done in few places)

Michal


+{
+   int s, ss;
+   int subslice_stride =
+   DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+
+   /* Unavailable prior to Gen 8. */
+   if (sseu->max_slices == 0)
+   return;
+
+   err_printf(m, "RCS topology:\n");
+
+   for (s = 0; s < sseu->max_slices; s++) {
+   err_printf(m, "  slice%i %u subslice(s) (0x%hhx):\n",
+  s, hweight8(sseu->subslice_mask[s]),
+  sseu->subslice_mask[s]);
+
+   for (ss = 0; ss < sseu->max_subslices; ss++) {
+   int eu_group, n_subslice_eus = 0;
+
+   for (eu_group = 0; eu_group < subslice_stride; 
eu_group++) {
+   n_subslice_eus +=
+   hweight8(sseu_eu_mask(sseu, s, ss, 
eu_group));
+   }
+
+   err_printf(m, "subslice%i: %u EUs (", ss, 
n_subslice_eus);
+   for (eu_group = 0;
+eu_group < max(0, subslice_stride - 1);
+eu_group++) {
+   u8 val = sseu_eu_mask(sseu, s, ss, eu_group);
+   err_printf(m, " 0x%hhx", val);
+   }
+   err_printf(m, "0x%hhx)\n",
+  sseu_eu_mask(sseu, s, ss, subslice_stride - 
1));
+   }
+   }
+}
+
 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
const struct i915_gpu_state *error)
 {
@@ -787,6 +826,7 @@ int i915_error_state_to_str(struct  
drm_i915_error_state_buf *m,

intel_display_print_error_state(m, error->display);
err_print_capabilities(m, >device_info);
+   err_print_rcs_topology(m, _INFO(dev_priv)->sseu);
err_print_params(m, >params);
err_print_uc(m, >uc);

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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36415/
State : warning

== Summary ==

Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> DMESG-WARN (shard-hsw) fdo#104218 +1
Test kms_frontbuffer_tracking:
Subgroup psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
notrun -> INCOMPLETE (shard-hsw)
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Test kms_flip:
Subgroup vblank-vs-modeset-suspend:
pass   -> SKIP   (shard-hsw)
Test drv_hangman:
Subgroup error-state-capture-blt:
dmesg-warn -> PASS   (shard-snb) fdo#104058 +1
Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb) fdo#104600
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)
Test drv_suspend:
Subgroup debugfs-reader:
pass   -> SKIP   (shard-snb)
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104600 https://bugs.freedesktop.org/show_bug.cgi?id=104600
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2656 pass:1507 dwarn:2   dfail:0   fail:10  skip:1136 
time:8898s
shard-snbtotal:2713 pass:1310 dwarn:1   dfail:0   fail:10  skip:1392 
time:7908s
Blacklisted hosts:
shard-apltotal:2713 pass:1688 dwarn:1   dfail:0   fail:23  skip:1001 
time:13532s
shard-kbltotal:2713 pass:1806 dwarn:1   dfail:0   fail:26  skip:880 
time:10456s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7656/shards.html
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Re: [Intel-gfx] [PATCH][next] drm/i915/pmu: fix sizeof on attr, should be *attr

[Colin Ian King]

On 12/01/18 17:48, Tvrtko Ursulin wrote:
> 
> Hi,
> 
> On 12/01/2018 17:36, Colin King wrote:
>> From: Colin Ian King 
>>
>> I believe the sizeof(attr) should be in fact sizeof(*attr), fortunately
>> the current code works because sizeof(struct attribute **) is the same
>> as sizeof(struct attribute *) for x86.
> 
> Thanks, kbuild also reported it and I just pushed a fix.
> 
> Out of curiosity, there are platforms where size of pointer is different
> from the size of a pointer to a pointer?

None that I know of.

> 
> Regards,
> 
> Tvrtko
> 
>>
>> Detected by CoverityScan, CID#1463854 ("Sizeof not portable")
>>
>> Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters
>> in sysfs")
>> Signed-off-by: Colin Ian King 
>> ---
>>   drivers/gpu/drm/i915/i915_pmu.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
>> b/drivers/gpu/drm/i915/i915_pmu.c
>> index 95ab5e28f5be..9be4f5201e41 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -794,7 +794,7 @@ create_event_attributes(struct drm_i915_private
>> *i915)
>>   goto err_alloc;
>>     /* Max one pointer of each attribute type plus a termination
>> entry. */
>> -    attr = kzalloc((count * 2 + 1) * sizeof(attr), GFP_KERNEL);
>> +    attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
>>   if (!attr)
>>   goto err_alloc;
>>  

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: fix sizeof on attr, should be *attr

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: fix sizeof on attr, should be *attr
URL   : https://patchwork.freedesktop.org/series/36423/
State : success

== Summary ==

Series 36423v1 drm/i915/pmu: fix sizeof on attr, should be *attr
https://patchwork.freedesktop.org/api/1.0/series/36423/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:484s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:279s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:273s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:451s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:462s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:502s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:590s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:435s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:516s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s

353fa2d3aef324005ed2553da6eb174a2f0b drm-tip: 2018y-01m-12d-09h-21m-50s UTC 
integration manifest
c151aa46f025 drm/i915/pmu: fix sizeof on attr, should be *attr

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7658/issues.html
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Re: [Intel-gfx] [PATCH][next] drm/i915/pmu: fix sizeof on attr, should be *attr

[Tvrtko Ursulin]

Hi,

On 12/01/2018 17:36, Colin King wrote:

From: Colin Ian King 

I believe the sizeof(attr) should be in fact sizeof(*attr), fortunately
the current code works because sizeof(struct attribute **) is the same
as sizeof(struct attribute *) for x86.


Thanks, kbuild also reported it and I just pushed a fix.

Out of curiosity, there are platforms where size of pointer is different 
from the size of a pointer to a pointer?


Regards,

Tvrtko



Detected by CoverityScan, CID#1463854 ("Sizeof not portable")

Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Signed-off-by: Colin Ian King 
---
  drivers/gpu/drm/i915/i915_pmu.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 95ab5e28f5be..9be4f5201e41 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -794,7 +794,7 @@ create_event_attributes(struct drm_i915_private *i915)
goto err_alloc;
  
  	/* Max one pointer of each attribute type plus a termination entry. */

-   attr = kzalloc((count * 2 + 1) * sizeof(attr), GFP_KERNEL);
+   attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
if (!attr)
goto err_alloc;
  


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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

[Tvrtko Ursulin]

On 12/01/2018 13:53, Lionel Landwerlin wrote:

On 12/01/18 12:01, Tvrtko Ursulin wrote:


On 12/01/2018 10:58, Lionel Landwerlin wrote:

On 12/01/18 10:15, Tvrtko Ursulin wrote:




[snip]


+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+  int slice, int subslice, int eu_group)


What is eu_group for? Will it be used at some point?


In case we ever have more than 8 EUs per subslice.


I am thinking if we could hide that from the call sites, to avoid it 
being passed as zeros, and to avoid having to write loops in other 
patches which reference eu_groups, when it is not immediately obvious 
what that means.


Could we for instance have a helper which would clear/set numbered EUs 
in sseu_dev_info, and so hide all the implementation details?


sseu_enable_eus(sseu, slice, subslice, start, end);

Then when you have code like:

 sseu->eu_mask[sseu_eu_idx(sseu, s, ss, 0)] = ~eu_disabled_mask;

You would write it as:

 /* On this slice/subslice mark EUs 0 to N as enabled. */
 sseu_enable_eus(sseu, s, ss, 0, fls(~eu_disabled_mask));


Hmm... I don't think that works if you have gaps, right?
Like a BXT 2x6 where a row of EUs has been fused off. It would be 
something like 0b01110111 or 0b10111011.


Oops, you are right. I just don't like having this eu_group field which 
is internal data storage detail, leaked out, is always zero, and even 
unused today. So I am trying to come up with a nicer api.


What about sseu_set_eus(sseu, slice, subslice, mask)?

Then you can replace call sites like:

 sseu->eu_mask[sseu_eu_idx(sseu, 0, 0, 0)] =
~((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
CHV_FGT_EU_DIS_SS0_R0_SHIFT);
 sseu->eu_mask[sseu_eu_idx(sseu, 0, 0, 0)] |=
~(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);

With:

 mask = (fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
CHV_FGT_EU_DIS_SS0_R0_SHIFT;
 mask |= ((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);

 sseu_set_eus(sseu, 0, 0, ~mask);

sseu_set_eus can then be the only place which understand the storage 
format. You can even later extend the mask size past u8 and it can still 
do the magic inside it.




Helper would internally know the size of the underlying storage and 
dtrt. There would be no need to manually manage eu_groups. In the 
initial implementation you could simply GEM_BUG_ON if the EU range 
does not fit into the current storage. Later u8 could be turned into 
u16 or similar. You also wouldn't have any iteration over eu_groups in 
this version.


I think that would be cleaner and easier to extend in the future. 
Unless I overlooked some important detail?


Or even simplify it by passing bitmask instead of start/end, and just 
have no support for more than 8 EUs in this version? No eu_group etc. 
When the need arises to have more, bump the eu_mask type to u16. That 
would require you to put back the stride parameter in the uAPI I think.


I'm not really a fan of having the data field in userspace be 
reinterpreted (as u16 or u32) based on one of the other field.

It might be easier on the kernel side, but complicates userspace.

I would prefer to stick to u8 and have everybody think of 
slice/subslice/eus availability as array of u8 bit fields which you 
might need to iterate more than one if there are more than 8 elements.


You are thinking about bit-ordering? Yeah, if it is easier keep the 
formats the same. Even though strictly speaking internal and ABI data 
representation do not need to be the same. As said above, I am just 
looking for a solution which hides the eu_group parameter from the 
callers and also is a bit shorter to read.


Regards,

Tvrtko
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[Intel-gfx] [PATCH][next] drm/i915/pmu: fix sizeof on attr, should be *attr

[Colin King]

From: Colin Ian King 

I believe the sizeof(attr) should be in fact sizeof(*attr), fortunately
the current code works because sizeof(struct attribute **) is the same
as sizeof(struct attribute *) for x86.

Detected by CoverityScan, CID#1463854 ("Sizeof not portable")

Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/i915/i915_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 95ab5e28f5be..9be4f5201e41 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -794,7 +794,7 @@ create_event_attributes(struct drm_i915_private *i915)
goto err_alloc;
 
/* Max one pointer of each attribute type plus a termination entry. */
-   attr = kzalloc((count * 2 + 1) * sizeof(attr), GFP_KERNEL);
+   attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
if (!attr)
goto err_alloc;
 
-- 
2.15.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: fix noderef.cocci warnings

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/pmu: fix noderef.cocci warnings
URL   : https://patchwork.freedesktop.org/series/36421/
State : success

== Summary ==

Series 36421v1 series starting with [1/2] drm/i915/pmu: fix noderef.cocci 
warnings
https://patchwork.freedesktop.org/api/1.0/series/36421/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:425s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:489s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:284s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:479s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:275s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:466s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:494s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:584s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:244  dwarn:0   dfail:0   fail:0   skip:44  
time:521s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:408s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:475s

353fa2d3aef324005ed2553da6eb174a2f0b drm-tip: 2018y-01m-12d-09h-21m-50s UTC 
integration manifest
4ab53646a746 drm/i915/pmu: Use kcalloc instead of kzalloc
e55379036539 drm/i915/pmu: fix noderef.cocci warnings

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7657/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] kms_plane: Remove redundant modeset after CRC capture

[Patchwork]

== Series Details ==

Series: series starting with [1/4] kms_plane: Remove redundant modeset after 
CRC capture
URL   : https://patchwork.freedesktop.org/series/36409/
State : success

== Summary ==

Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)
Test drv_hangman:
Subgroup error-state-capture-blt:
dmesg-warn -> PASS   (shard-snb) fdo#104058 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-suspend:
pass   -> SKIP   (shard-hsw) fdo#103540
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-hsw) fdo#104218 +1
Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup modeset-vs-vblank-race:
pass   -> DMESG-WARN (shard-hsw) fdo#103060
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb) fdo#104600
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)

fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#104600 https://bugs.freedesktop.org/show_bug.cgi?id=104600

shard-hswtotal:2719 pass:1539 dwarn:2   dfail:0   fail:10  skip:1168 
time:8996s
shard-snbtotal:2719 pass:1313 dwarn:1   dfail:0   fail:11  skip:1394 
time:7922s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_773/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/i915: Add display WA #1175 for planes ending close to right screen edge

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Add display WA #1175 for planes 
ending close to right screen edge
URL   : https://patchwork.freedesktop.org/series/36408/
State : warning

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Subgroup fbc-rgb101010-draw-mmap-gtt:
pass   -> SKIP   (shard-snb)
Test gem_eio:
Subgroup in-flight-contexts:
dmesg-warn -> PASS   (shard-snb) fdo#104058 +1
Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb) fdo#104600
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)
Test kms_flip:
Subgroup blt-wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-snb) fdo#104218 +1
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
pass   -> INCOMPLETE (shard-hsw) fdo#104152
Test kms_rotation_crc:
Subgroup cursor-rotation-180:
pass   -> SKIP   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-128x128-sliding:
pass   -> SKIP   (shard-snb)

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104600 https://bugs.freedesktop.org/show_bug.cgi?id=104600
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#104152 https://bugs.freedesktop.org/show_bug.cgi?id=104152

shard-hswtotal:2641 pass:1500 dwarn:1   dfail:0   fail:10  skip:1129 
time:8880s
shard-snbtotal:2713 pass:1306 dwarn:1   dfail:0   fail:12  skip:1394 
time:7895s
Blacklisted hosts:
shard-apltotal:2637 pass:1640 dwarn:1   dfail:1   fail:24  skip:971 
time:12916s
shard-kbltotal:2713 pass:1808 dwarn:1   dfail:0   fail:26  skip:878 
time:10504s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7655/shards.html
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use kcalloc instead of kzalloc

[Ville Syrjälä]

On Fri, Jan 12, 2018 at 05:03:40PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> kcalloc is preffered for allocating arrays.
> 
> Signed-off-by: Tvrtko Ursulin 
> Suggested-by: Ville Syrjälä 
> Cc: Ville Syrjälä 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_pmu.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 9be4f5201e41..065a28c713c4 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -785,16 +785,16 @@ create_event_attributes(struct drm_i915_private *i915)
>   }
>  
>   /* Allocate attribute objects and table. */
> - i915_attr = kzalloc(count * sizeof(*i915_attr), GFP_KERNEL);
> + i915_attr = kcalloc(count, sizeof(*i915_attr), GFP_KERNEL);
>   if (!i915_attr)
>   goto err_alloc;
>  
> - pmu_attr = kzalloc(count * sizeof(*pmu_attr), GFP_KERNEL);
> + pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
>   if (!pmu_attr)
>   goto err_alloc;
>  
>   /* Max one pointer of each attribute type plus a termination entry. */
> - attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
> + attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
>   if (!attr)
>   goto err_alloc;
>  
> -- 
> 2.14.1

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use kcalloc instead of kzalloc

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

kcalloc is preffered for allocating arrays.

Signed-off-by: Tvrtko Ursulin 
Suggested-by: Ville Syrjälä 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_pmu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 9be4f5201e41..065a28c713c4 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -785,16 +785,16 @@ create_event_attributes(struct drm_i915_private *i915)
}
 
/* Allocate attribute objects and table. */
-   i915_attr = kzalloc(count * sizeof(*i915_attr), GFP_KERNEL);
+   i915_attr = kcalloc(count, sizeof(*i915_attr), GFP_KERNEL);
if (!i915_attr)
goto err_alloc;
 
-   pmu_attr = kzalloc(count * sizeof(*pmu_attr), GFP_KERNEL);
+   pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
if (!pmu_attr)
goto err_alloc;
 
/* Max one pointer of each attribute type plus a termination entry. */
-   attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
+   attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
if (!attr)
goto err_alloc;
 
-- 
2.14.1

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[Intel-gfx] [PATCH 1/2] drm/i915/pmu: fix noderef.cocci warnings

[Tvrtko Ursulin]

From: Fengguang Wu 

drivers/gpu/drm/i915/i915_pmu.c:795:34-40: ERROR: application of sizeof to 
pointer

 sizeof when applied to a pointer typed expression gives the size of
 the pointer

Generated by: scripts/coccinelle/misc/noderef.cocci

Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Signed-off-by: Fengguang Wu 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 95ab5e28f5be..9be4f5201e41 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -794,7 +794,7 @@ create_event_attributes(struct drm_i915_private *i915)
goto err_alloc;
 
/* Max one pointer of each attribute type plus a termination entry. */
-   attr = kzalloc((count * 2 + 1) * sizeof(attr), GFP_KERNEL);
+   attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
if (!attr)
goto err_alloc;
 
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36415/
State : success

== Summary ==

Series 36415v1 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/36415/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:376s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:486s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:471s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:463s
fi-elk-e7500 total:224  pass:169  dwarn:8   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:275s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:514s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:395s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:418s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:468s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:505s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:580s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:431s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:533s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-glk-dsi   total:51   pass:43   dwarn:0   dfail:0   fail:0   skip:7  

353fa2d3aef324005ed2553da6eb174a2f0b drm-tip: 2018y-01m-12d-09h-21m-50s UTC 
integration manifest
e3277d14d999 drm/i915: expose rcs topology through query uAPI
a7d7054fe7f2 drm/i915: add query uAPI
6e5e5ba80fcf drm/i915: add rcs topology to error state
b68156908eb3 drm/i915/debugfs: add rcs topology entry
47e871478cfd drm/i915/debugfs: reuse max slice/subslices already stored in sseu
61b15f2a8637 drm/i915: store all subslice masks

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7656/issues.html
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Re: [Intel-gfx] 282dbf9b "drm/i915: Pass intel_plane and intel_crtc to plane hooks" breaks i945GM in 4.13 and above

[Ville Syrjälä]

On Fri, Jan 12, 2018 at 11:50:06AM +0200, Jani Nikula wrote:
> On Thu, 11 Jan 2018, Karl-Johan Karlsson  
> wrote:
> > Hello,
> >
> > I have an old Lenovo Thinkpad X60 laptop with a Core 2 Duo T7200 CPU and 
> > i945GM integrated graphics whose graphics broke when I tried to update the 
> > kernel to get the Meltdown fixes.
> >
> > GRUB2 shows a graphical boot menu, and Linux displays the Tux boot logos 
> > correctly at first. However, almost immediately after displaying the Tuxes, 
> > the actively scrolling area of the display shifts about two text lines 
> > downward, so that two decapitated penguin heads are left at the top of the 
> > screen and new text appears below the lower edge of the screen. When X 
> > starts, 
> > it too is shifted down the same amount, and only shows a black screen with 
> > a 
> > (working) mouse cursor. My display manager (SDDM) never shows up. 
> > Sometimes, 
> > while X is running, random pixels appear in the non-active area at the top 
> > of 
> > the screen containing the decapitated penguin heads.
> >
> > My hardware is:
> >
> > $ grep name /proc/cpuinfo
> > model name  : Intel(R) Core(TM)2 CPU T7200  @ 2.00GHz
> > model name  : Intel(R) Core(TM)2 CPU T7200  @ 2.00GHz
> >
> > # lspci | grep VGA
> > 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 
> > 943/940GML Express Integrated Graphics Controller (rev 03)
> >
> > # grep Chipset: /var/log/Xorg.0.log
> > [33.085] (--) intel(0): Integrated Graphics Chipset: Intel(R) 945GM
> >
> > $ xrandr | grep primary
> > LVDS1 connected primary 1024x768+0+0 (normal left inverted right x axis y 
> > axis) 250mm x 180mm
> >
> > Kernel 4.12.14 does not have the bug. 4.13 and 4.14.11 have the bug in 
> > console 
> > and X mode. 4.15-rc7 has the bug in console mode, but crashes (completely 
> > black screen, Magic SysRq to reboot is the only thing that works) when 
> > starting X.
> >
> > Bisecting from 4.12 to 4.13 pointed to this as the first bad commit:
> >
> > commit 282dbf9b017bc6d5fdaeadf14e534c2fe22fee2d
> > Author: Ville Syrjälä 
> > Date:   Mon Mar 27 21:55:33 2017 +0300
> >
> > drm/i915: Pass intel_plane and intel_crtc to plane hooks
> >
> > But I know nothing about the driver internals to explain why.
> 
> I'm afraid that bisect result doesn't seem plausible. Eyeballing through
> it, it's just straightforward mechanical non-functional changes.

The bisect reslut is actually correct. We have one or more bugs open
about this. https://bugs.freedesktop.org/show_bug.cgi?id=102929 at
least.

We need these commits to fix it:
51f5a0963984 ("drm/i915: Add .get_hw_state() method for planes")
b1e01595a66d ("drm/i915: Redo plane sanitation during readout")
5816d9cbc0a0 ("drm/i915: Fix deadlock in i830_disable_pipe()")

Now I recall that my plan was to get those into 4.15-rc but then
Christmas/etc. happened. Is there still a way to get those into
4.15 or has that ship sailed already?

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/1] tools/intel_guc_logger: Send GuC log level in new i915 expected format

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/1] tools/intel_guc_logger: Send GuC log 
level in new i915 expected format
URL   : https://patchwork.freedesktop.org/series/36404/
State : failure

== Summary ==

Test kms_flip:
Subgroup vblank-vs-modeset-suspend:
pass   -> SKIP   (shard-hsw)
Subgroup blt-wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-snb) fdo#104218 +1
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)
Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)
Test gem_eio:
Subgroup in-flight-contexts:
dmesg-warn -> PASS   (shard-snb) fdo#104058 +1
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb) fdo#104600
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test pm_rpm:
Subgroup gem-execbuf-stress:
pass   -> INCOMPLETE (shard-hsw)

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104600 https://bugs.freedesktop.org/show_bug.cgi?id=104600
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2663 pass:1514 dwarn:1   dfail:0   fail:9   skip:1138 
time:8667s
shard-snbtotal:2713 pass:1311 dwarn:1   dfail:0   fail:10  skip:1391 
time:7896s
Blacklisted hosts:
shard-apltotal:2713 pass:1686 dwarn:1   dfail:0   fail:25  skip:1001 
time:13538s
shard-kbltotal:2695 pass:1788 dwarn:1   dfail:0   fail:26  skip:879 
time:10400s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_772/shards.html
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[Intel-gfx] [PATCH v3 6/6] drm/i915: expose rcs topology through query uAPI

[Lionel Landwerlin]

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
Add uapi macros to read data from *_info structs (Tvrtko)

v3: Use !!(v & BIT()) for uapi macros instead of custom shifts (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_query.c | 134 ++
 include/uapi/drm/i915_drm.h   |  51 +++
 2 files changed, 185 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 5694cfea4553..465ec18a472f 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,129 @@
 #include "i915_drv.h"
 #include 
 
+static int query_slices_info(struct drm_i915_private *dev_priv,
+struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_slices_info slices_info;
+   u32 data_length, length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   data_length = sizeof(sseu->slice_mask);
+   length = sizeof(slices_info) + data_length;
+
+   /*
+* If we ever change the internal slice mask data type, we'll need to
+* update this function.
+*/
+   BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+   if (query_item->length == 0) {
+   query_item->length = length;
+   return 0;
+   }
+
+   if (query_item->length != length)
+   return -EINVAL;
+
+   memset(_info, 0, sizeof(slices_info));
+   slices_info.max_slices = sseu->max_slices;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), _info,
+sizeof(slices_info)))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+offsetof(struct 
drm_i915_query_slices_info, data)),
+>slice_mask, data_length))
+   return -EFAULT;
+
+   return 0;
+}
+
+static int query_subslices_info(struct drm_i915_private *dev_priv,
+   struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_subslices_info subslices_info;
+   u32 data_length, length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(subslices_info));
+   subslices_info.max_slices = sseu->max_slices;
+   subslices_info.max_subslices = sseu->max_subslices;
+
+   data_length = subslices_info.max_slices *
+   DIV_ROUND_UP(subslices_info.max_subslices,
+sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
+   length = sizeof(subslices_info) + data_length;
+
+   if (query_item->length == 0) {
+   query_item->length = length;
+   return 0;
+   }
+
+   if (query_item->length != length)
+   return -EINVAL;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), _info,
+sizeof(subslices_info)))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+offsetof(struct 
drm_i915_query_subslices_info, data)),
+sseu->subslice_mask, data_length))
+   return -EFAULT;
+
+   return 0;
+}
+
+static int query_eus_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_eus_info eus_info;
+   u32 data_length, length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(eus_info));
+   eus_info.max_slices = sseu->max_slices;
+   eus_info.max_subslices = sseu->max_subslices;
+   eus_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
+
+   data_length = eus_info.max_slices * eus_info.max_subslices *
+   DIV_ROUND_UP(eus_info.max_eus_per_subslice, BITS_PER_BYTE);
+   length = sizeof(eus_info) + data_length;
+
+   if (query_item->length == 0) {
+   query_item->length = length;
+   

[Intel-gfx] [PATCH v3 3/6] drm/i915/debugfs: add rcs topology entry

[Lionel Landwerlin]

While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.

slice0: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice1: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice2: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)

v2: Reformat debugfs printing (Tvrtko)
Use the new EU mask helper (Tvrtko)

Suggested-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 42 +
 1 file changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2d1c9cce5fe4..83af1029b907 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3162,6 +3162,47 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static int i915_rcs_topology(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   int s, ss;
+   int subslice_stride =
+   DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+
+   if (sseu->max_slices == 0) {
+   seq_printf(m, "Unavailable\n");
+   return 0;
+   }
+
+   for (s = 0; s < sseu->max_slices; s++) {
+   seq_printf(m, "slice%i: %u subslice(s) (0x%hhx):\n",
+  s, hweight8(sseu->subslice_mask[s]),
+  sseu->subslice_mask[s]);
+
+   for (ss = 0; ss < sseu->max_subslices; ss++) {
+   int eu_group, n_subslice_eus = 0;
+
+   for (eu_group = 0; eu_group < subslice_stride; 
eu_group++) {
+   n_subslice_eus +=
+   hweight8(sseu_eu_mask(sseu, s, ss, 
eu_group));
+   }
+
+   seq_printf(m, "\tsubslice%i: %u EUs (", ss, 
n_subslice_eus);
+   for (eu_group = 0;
+eu_group < max(0, subslice_stride - 1);
+eu_group++) {
+   u8 val = sseu_eu_mask(sseu, s, ss, eu_group);
+   seq_printf(m, "0x%hhx, ", val);
+   }
+   seq_printf(m, "0x%hhx)\n",
+  sseu_eu_mask(sseu, s, ss, subslice_stride - 
1));
+   }
+   }
+
+   return 0;
+}
+
 static int i915_shrinker_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -4692,6 +4733,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dmc_info", i915_dmc_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
+   {"i915_rcs_topology", i915_rcs_topology, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
-- 
2.15.1

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[Intel-gfx] [PATCH v3 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

[Lionel Landwerlin]

Now that we have that information in topology fields, let's just reused it.

v2: Style tweaks (Tvrtko)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 27 +++
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 463029f72a0b..2d1c9cce5fe4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4300,11 +4300,11 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 struct sseu_dev_info *sseu)
 {
const struct intel_device_info *info = INTEL_INFO(dev_priv);
-   int s_max = 6, ss_max = 4;
int s, ss;
-   u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+   u32 s_reg[info->sseu.max_slices];
+   u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
/*
 * FIXME: Valid SS Mask respects the spec and read
 * only valid bits for those registers, excluding reserverd
@@ -4326,7 +4326,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4334,7 +4334,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
@@ -4354,17 +4354,12 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
 {
-   int s_max = 3, ss_max = 4;
+   const struct intel_device_info *info = INTEL_INFO(dev_priv);
int s, ss;
-   u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
-
-   /* BXT has a single slice and at most 3 subslices. */
-   if (IS_GEN9_LP(dev_priv)) {
-   s_max = 1;
-   ss_max = 3;
-   }
+   u32 s_reg[info->sseu.max_slices];
+   u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
@@ -4379,7 +4374,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4390,7 +4385,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->subslice_mask[s] =
INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (IS_GEN9_LP(dev_priv)) {
-- 
2.15.1

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[Intel-gfx] [PATCH v3 5/6] drm/i915: add query uAPI

[Lionel Landwerlin]

There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die recovery).

At the moment the GET_PARAM ioctl covers some basic needs, but
generally is only able to return a single value for each defined
parameter. This is a bit problematic with topology descriptions which
are array/maps of available units.

This change introduces a new ioctl that can deal with requests to fill
structures of potentially variable lengths. The user is expected fill
a query with length fields set at 0 on the first call, the kernel then
sets the length fields to the their expected values. A second call to
the kernel with length fields at their expected values will trigger a
copy of the data to the pointed memory locations.

The scope of this uAPI is only to provide information to userspace,
not to allow configuration of the device.

v2: Simplify dispatcher code iteration (Tvrtko)
Tweak uapi drm_i915_query_item structure (Tvrtko)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/i915_drv.c   |  1 +
 drivers/gpu/drm/i915/i915_drv.h   |  3 +++
 drivers/gpu/drm/i915/i915_query.c | 51 +++
 include/uapi/drm/i915_drm.h   | 31 
 5 files changed, 87 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3bddd8a06806..b0415a3e2d59 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -69,6 +69,7 @@ i915-y += i915_cmd_parser.o \
  i915_gem_timeline.o \
  i915_gem_userptr.o \
  i915_gemfs.o \
+ i915_query.o \
  i915_trace_points.o \
  i915_vma.o \
  intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 969835d3cbcd..d92e1b7236fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2824,6 +2824,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, 
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, 
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
 };
 
 static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a689396d0ff6..de0eb6ce2fcd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3623,6 +3623,9 @@ extern void i915_perf_fini(struct drm_i915_private 
*dev_priv);
 extern void i915_perf_register(struct drm_i915_private *dev_priv);
 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
 
+/* i915_query.c */
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
*file);
+
 /* i915_suspend.c */
 extern int i915_save_state(struct drm_i915_private *dev_priv);
 extern int i915_restore_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
new file mode 100644
index ..5694cfea4553
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+#include 
+
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+   

[Intel-gfx] [PATCH v3 4/6] drm/i915: add rcs topology to error state

[Lionel Landwerlin]

This might be useful information for developers looking at an error
state.

v2: Place topology towards the end of the error state (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 40 +++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 944059322daa..cc7f53cc9a77 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -605,6 +605,45 @@ static void err_print_uc(struct drm_i915_error_state_buf 
*m,
print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
 }
 
+static void err_print_rcs_topology(struct drm_i915_error_state_buf *m,
+  const struct sseu_dev_info *sseu)
+{
+   int s, ss;
+   int subslice_stride =
+   DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+
+   /* Unavailable prior to Gen 8. */
+   if (sseu->max_slices == 0)
+   return;
+
+   err_printf(m, "RCS topology:\n");
+
+   for (s = 0; s < sseu->max_slices; s++) {
+   err_printf(m, "  slice%i %u subslice(s) (0x%hhx):\n",
+  s, hweight8(sseu->subslice_mask[s]),
+  sseu->subslice_mask[s]);
+
+   for (ss = 0; ss < sseu->max_subslices; ss++) {
+   int eu_group, n_subslice_eus = 0;
+
+   for (eu_group = 0; eu_group < subslice_stride; 
eu_group++) {
+   n_subslice_eus +=
+   hweight8(sseu_eu_mask(sseu, s, ss, 
eu_group));
+   }
+
+   err_printf(m, "subslice%i: %u EUs (", ss, 
n_subslice_eus);
+   for (eu_group = 0;
+eu_group < max(0, subslice_stride - 1);
+eu_group++) {
+   u8 val = sseu_eu_mask(sseu, s, ss, eu_group);
+   err_printf(m, " 0x%hhx", val);
+   }
+   err_printf(m, "0x%hhx)\n",
+  sseu_eu_mask(sseu, s, ss, subslice_stride - 
1));
+   }
+   }
+}
+
 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
const struct i915_gpu_state *error)
 {
@@ -787,6 +826,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
intel_display_print_error_state(m, error->display);
 
err_print_capabilities(m, >device_info);
+   err_print_rcs_topology(m, _INFO(dev_priv)->sseu);
err_print_params(m, >params);
err_print_uc(m, >uc);
 
-- 
2.15.1

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[Intel-gfx] [PATCH v3 1/6] drm/i915: store all subslice masks

[Lionel Landwerlin]

Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.

v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
Readability changes (Tvrtko)
Add EU index helper (Tvrtko)

v3: Turn ALIGN(v, 8) / 8 into DIV_ROUND_UP(v, BITS_PER_BYTE) (Tvrtko)
Reuse sseu_eu_idx() for setting eu_mask on CHV (Tvrtko)
Reformat debug prints for subslices (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  25 ++--
 drivers/gpu/drm/i915/i915_drv.c  |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c | 200 +++
 drivers/gpu/drm/i915/intel_device_info.h |  37 +-
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 6 files changed, 205 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2bb63073d73f..463029f72a0b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4285,7 +4285,7 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask = BIT(0);
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslice_mask[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4332,7 +4332,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask |= BIT(s);
-   sseu->subslice_mask = info->sseu.subslice_mask;
+   sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4387,8 +4387,8 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
 
if (IS_GEN9_BC(dev_priv))
-   sseu->subslice_mask =
-   INTEL_INFO(dev_priv)->sseu.subslice_mask;
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4398,7 +4398,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
/* skip disabled subslice */
continue;
 
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslice_mask[s] |= BIT(ss);
}
 
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4420,9 +4420,12 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
 
if (sseu->slice_mask) {
-   sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
sseu->eu_per_subslice =
INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+   }
sseu->eu_total = sseu->eu_per_subslice *
 sseu_subslice_total(sseu);
 
@@ -4441,6 +,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool 
is_available_info,
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const char *type = is_available_info ? "Available" : "Enabled";
+   int s;
 
seq_printf(m, "  %s Slice Mask: %04x\n", type,
   sseu->slice_mask);
@@ -4448,10 +4452,11 @@ static void i915_print_sseu_info(struct seq_file *m, 
bool is_available_info,
   hweight8(sseu->slice_mask));
seq_printf(m, "  %s Subslice Total: %u\n", type,
   sseu_subslice_total(sseu));
-   seq_printf(m, "  %s Subslice Mask: %04x\n", type,
-  sseu->subslice_mask);
-   seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
-  hweight8(sseu->subslice_mask));
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   seq_printf(m, "  %s Slice%i %u subslices, mask=%04x\n", type,
+  s, hweight8(sseu->subslice_mask[s]),
+  sseu->subslice_mask[s]);

[Intel-gfx] [PATCH v3 0/6] drm/i915: expose RCS topology to userspace

[Lionel Landwerlin]

Hi all,

Another update, mostly style.

Cheers,

Lionel Landwerlin (6):
  drm/i915: store all subslice masks
  drm/i915/debugfs: reuse max slice/subslices already stored in sseu
  drm/i915/debugfs: add rcs topology entry
  drm/i915: add rcs topology to error state
  drm/i915: add query uAPI
  drm/i915: expose rcs topology through query uAPI

 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_debugfs.c  |  94 +++
 drivers/gpu/drm/i915/i915_drv.c  |   3 +-
 drivers/gpu/drm/i915/i915_drv.h  |   3 +
 drivers/gpu/drm/i915/i915_gpu_error.c|  40 +++
 drivers/gpu/drm/i915/i915_query.c| 185 
 drivers/gpu/drm/i915/intel_device_info.c | 200 +++
 drivers/gpu/drm/i915/intel_device_info.h |  37 +-
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 include/uapi/drm/i915_drm.h  |  82 +
 11 files changed, 570 insertions(+), 79 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c

--
2.15.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] kms_plane: Remove redundant modeset after CRC capture

[Patchwork]

== Series Details ==

Series: series starting with [1/4] kms_plane: Remove redundant modeset after 
CRC capture
URL   : https://patchwork.freedesktop.org/series/36409/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
b64c093fe5a2b65201ebf8305491ea923151d6e7 tools: Update .gitignore

with latest DRM-Tip kernel build CI_DRM_3624
353fa2d3afff drm-tip: 2018y-01m-12d-09h-21m-50s UTC integration manifest

Testlist changes:
+igt@kms_plane@plane-clipping-pipe-a-planes
+igt@kms_plane@plane-clipping-pipe-b-planes
+igt@kms_plane@plane-clipping-pipe-c-planes
+igt@kms_plane@plane-clipping-pipe-d-planes
+igt@kms_plane@plane-clipping-pipe-e-planes
+igt@kms_plane@plane-clipping-pipe-f-planes

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +1
incomplete -> PASS   (fi-snb-2520m) fdo#103713 +1
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:492s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:482s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:463s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:274s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:516s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:414s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:419s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:464s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:503s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:505s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:587s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:435s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:478s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_773/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Add display WA #1175 for planes ending close to right screen edge

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Add display WA #1175 for planes 
ending close to right screen edge
URL   : https://patchwork.freedesktop.org/series/36408/
State : success

== Summary ==

Series 36408v1 series starting with [1/2] drm/i915: Add display WA #1175 for 
planes ending close to right screen edge
https://patchwork.freedesktop.org/api/1.0/series/36408/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:425s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:491s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:279s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:480s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:462s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:275s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:453s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:465s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:500s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:583s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:437s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:515s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:532s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:492s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:524s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:396s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:575s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:477s

353fa2d3aef324005ed2553da6eb174a2f0b drm-tip: 2018y-01m-12d-09h-21m-50s UTC 
integration manifest
0459db82b73b drm/i915: Add WA for planes ending close to left screen edge
cb1f35d93de0 drm/i915: Add display WA #1175 for planes ending close to right 
screen edge

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7655/issues.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add display WA #1175 for planes ending close to right screen edge

[Chris Wilson]

Quoting Imre Deak (2018-01-12 14:54:36)
> As described in the WA on GLK and CNL planes on the right edge of the
> screen that have less than 4 pixels visible from the beginning of the
> plane to the edge of the screen can cause FIFO underflow and display
> corruption.
> 
> On GLK/CNL I could trigger the problem only if the plane was at the same
> time also aligned to the top edge of the screen (after clipping) and
> there were exactly 2 pixels visible from the start of the plane to the
> right edge of the screen (so couldn't trigger it with 1 or 3 pixels
> visible). Nevertheless, to be sure, I also applied the WA for these cases.
> 
> I also couldn't see any problem with the cursor plane and later Art
> confirmed that it's not affected, so the WA is applied only for the
> other plane types.
> 
> Signed-off-by: Imre Deak 
> ---
> +   /*
> +* Display WA #1175: cnl,glk
> +* Planes other than the cursor may cause FIFO underflow and display
> +* corruption if starting less than 4 pixels from the right edge of
> +* the screen.
> +*/
> +   if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> +   dst_x > pipe_src_w - 4) {
> +   DRM_DEBUG_KMS("requested plane X start position %d invalid 
> (valid range %d-%d)\n",
> + dst_x,
> + 0, pipe_src_w - 4);
> +   return -EINVAL;

Should this be -ERANGE or -ENOSPC?
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add display WA #1175 for planes ending close to right screen edge

[Chris Wilson]

Quoting Imre Deak (2018-01-12 14:54:36)
> As described in the WA on GLK and CNL planes on the right edge of the
> screen that have less than 4 pixels visible from the beginning of the
> plane to the edge of the screen can cause FIFO underflow and display
> corruption.
> 
> On GLK/CNL I could trigger the problem only if the plane was at the same
> time also aligned to the top edge of the screen (after clipping) and
> there were exactly 2 pixels visible from the start of the plane to the
> right edge of the screen (so couldn't trigger it with 1 or 3 pixels
> visible). Nevertheless, to be sure, I also applied the WA for these cases.
> 
> I also couldn't see any problem with the cursor plane and later Art
> confirmed that it's not affected, so the WA is applied only for the
> other plane types.
> 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 28 
>  drivers/gpu/drm/i915/intel_drv.h |  3 ++-
>  drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
>  3 files changed, 27 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 221e3a183d36..3d931b652795 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2917,14 +2917,19 @@ static bool skl_check_main_ccs_coordinates(struct 
> intel_plane_state *plane_state
> return true;
>  }
>  
> -static int skl_check_main_surface(struct intel_plane_state *plane_state)
> +static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state)
>  {
> +   struct drm_i915_private *dev_priv =
> +   to_i915(plane_state->base.plane->dev);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> unsigned int rotation = plane_state->base.rotation;
> int x = plane_state->base.src.x1 >> 16;
> int y = plane_state->base.src.y1 >> 16;
> int w = drm_rect_width(_state->base.src) >> 16;
> int h = drm_rect_height(_state->base.src) >> 16;
> +   int dst_x = plane_state->base.dst.x1;
> +   int pipe_src_w = crtc_state->pipe_src_w;
> int max_width = skl_max_plane_width(fb, 0, rotation);
> int max_height = 4096;
> u32 alignment, offset, aux_offset = plane_state->aux.offset;
> @@ -2935,6 +2940,20 @@ static int skl_check_main_surface(struct 
> intel_plane_state *plane_state)
> return -EINVAL;
> }
>  
> +   /*
> +* Display WA #1175: cnl,glk
> +* Planes other than the cursor may cause FIFO underflow and display
> +* corruption if starting less than 4 pixels from the right edge of
> +* the screen.
> +*/
> +   if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> +   dst_x > pipe_src_w - 4) {
> +   DRM_DEBUG_KMS("requested plane X start position %d invalid 
> (valid range %d-%d)\n",
> + dst_x,
> + 0, pipe_src_w - 4);

You are rejecting user input, so this should be DRM_DEBUG() (or whatever
the future user channel will be).
-Chris
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[Intel-gfx] [PATCH i-g-t 3/4] kms_plane: Split helpers creating reference FB and capturing CRC

[Imre Deak]

Split creating a reference FB and capturing the CRC for it into separate
functions, so in a follow-up patch we can reuse the CRC capture function
for a reference FB created in a different way.

Signed-off-by: Imre Deak 
---
 tests/kms_plane.c | 50 --
 1 file changed, 32 insertions(+), 18 deletions(-)

diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index 0ebf4577..358126b6 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -61,11 +61,9 @@ static void test_fini(data_t *data)
 }
 
 static void
-test_grab_crc(data_t *data, igt_output_t *output, enum pipe pipe,
- color_t *fb_color, igt_crc_t *crc /* out */)
+test_grab_crc_for_fb(data_t *data, igt_output_t *output, enum pipe pipe,
+igt_fb_t *fb, igt_crc_t *crc /* out */)
 {
-   struct igt_fb fb;
-   drmModeModeInfo *mode;
igt_plane_t *primary;
char *crc_str;
int ret;
@@ -74,13 +72,7 @@ test_grab_crc(data_t *data, igt_output_t *output, enum pipe 
pipe,
 
primary = igt_output_get_plane(output, 0);
 
-   mode = igt_output_get_mode(output);
-   igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
-   DRM_FORMAT_XRGB,
-   LOCAL_DRM_FORMAT_MOD_NONE,
-   fb_color->red, fb_color->green, fb_color->blue,
-   );
-   igt_plane_set_fb(primary, );
+   igt_plane_set_fb(primary, fb);
 
ret = igt_display_try_commit2(>display, COMMIT_LEGACY);
igt_skip_on(ret != 0);
@@ -89,14 +81,24 @@ test_grab_crc(data_t *data, igt_output_t *output, enum pipe 
pipe,
 
igt_plane_set_fb(primary, NULL);
 
-   igt_remove_fb(data->drm_fd, );
-
crc_str = igt_crc_to_string(crc);
-   igt_debug("CRC for a (%.02f,%.02f,%.02f) fb: %s\n", fb_color->red,
- fb_color->green, fb_color->blue, crc_str);
+   igt_debug("CRC for fb: %s\n", crc_str);
free(crc_str);
 }
 
+static void
+test_create_fb_for_output(data_t *data, igt_output_t *output, color_t 
*fb_color,
+ igt_fb_t *fb)
+{
+   drmModeModeInfo *mode = igt_output_get_mode(output);
+
+   igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+   DRM_FORMAT_XRGB,
+   LOCAL_DRM_FORMAT_MOD_NONE,
+   fb_color->red, fb_color->green, fb_color->blue,
+   fb);
+}
+
 /*
  * Plane position test.
  *   - We start by grabbing a reference CRC of a full green fb being scanned
@@ -223,11 +225,15 @@ test_plane_position(data_t *data, enum pipe pipe, 
unsigned int flags)
 
for_each_valid_output_on_pipe(>display, pipe, output) {
int n_planes = data->display.pipes[pipe].n_planes;
+   igt_fb_t reference_fb;
igt_crc_t reference_crc;
 
test_init(data, pipe);
 
-   test_grab_crc(data, output, pipe, , _crc);
+   test_create_fb_for_output(data, output, , _fb);
+   test_grab_crc_for_fb(data, output, pipe, _fb,
+_crc);
+   igt_remove_fb(data->drm_fd, _fb);
 
for (int plane = 1; plane < n_planes; plane++)
test_plane_position_with_output(data, pipe, plane,
@@ -345,13 +351,21 @@ test_plane_panning(data_t *data, enum pipe pipe, unsigned 
int flags)
 
for_each_valid_output_on_pipe(>display, pipe, output) {
int n_planes = data->display.pipes[pipe].n_planes;
+   igt_fb_t red_fb;
+   igt_fb_t blue_fb;
igt_crc_t red_crc;
igt_crc_t blue_crc;
 
test_init(data, pipe);
 
-   test_grab_crc(data, output, pipe, , _crc);
-   test_grab_crc(data, output, pipe, , _crc);
+   test_create_fb_for_output(data, output, , _fb);
+   test_create_fb_for_output(data, output, , _fb);
+
+   test_grab_crc_for_fb(data, output, pipe, _fb, _crc);
+   test_grab_crc_for_fb(data, output, pipe, _fb, _crc);
+
+   igt_remove_fb(data->drm_fd, _fb);
+   igt_remove_fb(data->drm_fd, _fb);
 
for (int plane = 1; plane < n_planes; plane++)
test_plane_panning_with_output(data, pipe, plane,
-- 
2.13.2

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[Intel-gfx] [PATCH i-g-t 4/4] kms_plane: Add clipping subtests

[Imre Deak]

Add plane clipping subtests displaying a single clipped plane, with the
following test cases:
a) plane covering the whole screen, so that clipping is done at all 4
   screen edges
b) plane at either of the 4 corners of the screen clipped, so that a
   4x4 pixel part of the plane is visible
c) plane at either of the 4 corners of the screen clipped, so that a
   2x2 pixel part of the plane is visible

Each of the above cases are tested with all supported planes, tiling
modes, rotation degrees and differing pixel format sizes (only 16 bpp
and 32 bpp for now). While the a) and b) cases above are supported on
all platforms c) is not fully supported on GLK and CNL (which was the
primary motivation for this testcase).

Signed-off-by: Imre Deak 
---
 tests/kms_plane.c | 441 ++
 1 file changed, 441 insertions(+)

diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index 358126b6..0d32f9ef 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -41,11 +41,34 @@ typedef struct {
int drm_fd;
igt_display_t display;
igt_pipe_crc_t *pipe_crc;
+   uint32_t devid;
+   uint64_t max_curw;
+   uint64_t max_curh;
 } data_t;
 
 static color_t red   = { 1.0f, 0.0f, 0.0f };
 static color_t green = { 0.0f, 1.0f, 0.0f };
+static color_t yellow = { 1.0f, 1.0f, 0.0f };
 static color_t blue  = { 0.0f, 0.0f, 1.0f };
+static color_t white = { 1.0f, 1.0f, 1.0f };
+
+
+/*
+ * Size of a square plane used to test clipping at the 4 courners of the
+ * display.
+ */
+#define CLIPPED_PLANE_SMALL_SIZE   64
+
+/*
+ * Visible plane size after clipping that works on all platforms for all plane
+ * positions.
+ * The exceptions are GLK/CNL where there must be at least this many pixels
+ * visible from the plane after it's clipped to the left/right edge of the
+ * screen. Not meeting this condition may trigger FIFO underflows and screen
+ * corruption. The cursor plane is an exception that doesn't have this problem
+ * even on GLK/CNL.
+ */
+#define CLIPPED_PLANE_MIN_VALID4
 
 /*
  * Common code across all tests, acting on data_t
@@ -143,6 +166,111 @@ create_fb_for_mode__position(data_t *data, 
drmModeModeInfo *mode,
cairo_destroy(cr);
 }
 
+/*
+ * Create a square FB for the plane in the clipping test, divided into 4
+ * quarters solid filled with different colors. Use the given tiling, format
+ * and size and rotate the FB clockwise with the given rotation degrees, so
+ * that the counterclockwise rotation with the same degrees done by the HW
+ * will always result in the same reference FB image.
+ */
+static void
+create_fb_for_mode__clipping_plane(data_t *data, igt_rotation_t rotation,
+  uint64_t tiling,
+  uint32_t format,
+  int size,
+  struct igt_fb *fb /* out */)
+{
+   color_t corners[] = { red, white, yellow, blue };
+   color_t color;
+   unsigned int fb_id;
+   cairo_t *cr;
+   const int qsize = size / 2;
+   int idx;
+
+   fb_id = igt_create_fb(data->drm_fd, size, size, format, tiling, fb);
+   igt_assert(fb_id);
+
+   cr = igt_get_cairo_ctx(data->drm_fd, fb);
+
+   switch (rotation) {
+   case IGT_ROTATION_0:
+   idx = 0;
+   break;
+   case IGT_ROTATION_90:
+   idx = 3;
+   break;
+   case IGT_ROTATION_180:
+   idx = 2;
+   break;
+   case IGT_ROTATION_270:
+   idx = 1;
+   break;
+   default:
+   igt_assert(0);
+   }
+
+   color = corners[idx];
+   igt_paint_color(cr, 0, 0, qsize, qsize,
+   color.red, color.green, color.blue);
+
+   color = corners[(++idx) % 4];
+   igt_paint_color(cr, qsize, 0, qsize, qsize,
+   color.red, color.green, color.blue);
+
+   color = corners[(++idx) % 4];
+   igt_paint_color(cr, qsize, qsize, qsize, qsize,
+   color.red, color.green, color.blue);
+
+   color = corners[(++idx) % 4];
+   igt_paint_color(cr, 0, qsize, qsize, qsize,
+   color.red, color.green, color.blue);
+
+   igt_assert(cairo_status(cr) == 0);
+   cairo_destroy(cr);
+}
+
+/*
+ * Create a square reference FB for the whole screen in the clipping test,
+ * with the given test plane position and size. See
+ * create_fb_for_mode__clipping_plane() for the layout of the test plane.
+ */
+static void
+create_fb_for_mode__clipping_display(data_t *data, drmModeModeInfo *mode,
+int plane_x, int plane_y,
+int plane_size,
+struct igt_fb *fb /* out */)
+{
+   struct igt_fb plane_fb;
+   unsigned int fb_id;
+   cairo_t *cr;
+   cairo_surface_t *src;
+
+   fb_id = 

[Intel-gfx] [PATCH i-g-t 1/4] kms_plane: Remove redundant modeset after CRC capture

[Imre Deak]

The null modeset after capturing the CRC is redundant; detaching the FB
from the plane is enough for the next modeset to work properly. This
speed things up especially on slow panels.

Signed-off-by: Imre Deak 
---
 tests/kms_plane.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index 92bf67f1..0ebf4577 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -88,7 +88,6 @@ test_grab_crc(data_t *data, igt_output_t *output, enum pipe 
pipe,
igt_pipe_crc_collect_crc(data->pipe_crc, crc);
 
igt_plane_set_fb(primary, NULL);
-   igt_display_commit(>display);
 
igt_remove_fb(data->drm_fd, );
 
-- 
2.13.2

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[Intel-gfx] [PATCH i-g-t 2/4] lib: Export helpers to get rotation/tiling strings

[Imre Deak]

This is needed for the next patch for some debug prints.

Signed-off-by: Imre Deak 
---
 lib/igt_fb.c  | 23 +++
 lib/igt_fb.h  |  3 +++
 lib/igt_kms.c | 11 +--
 lib/igt_kms.h |  1 +
 4 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index ded639e8..e35fda82 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1307,6 +1307,29 @@ const char *igt_format_str(uint32_t drm_format)
 }
 
 /**
+ * igt_tiling_str:
+ * @tiling: tiling ID
+ *
+ * Returns:
+ * Human-readable tiling string for @tiling.
+ */
+const char *igt_tiling_str(uint64_t tiling)
+{
+   switch (tiling) {
+   case LOCAL_DRM_FORMAT_MOD_NONE:
+   return "linear";
+   case LOCAL_I915_FORMAT_MOD_X_TILED:
+   return "X-tiled";
+   case LOCAL_I915_FORMAT_MOD_Y_TILED:
+   return "Y-tiled";
+   case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+   return "Yf-tiled";
+   default:
+   return "N/A";
+   }
+}
+
+/**
  * igt_get_all_cairo_formats:
  * @formats: pointer to pointer to store the allocated formats array
  * @format_count: pointer to integer to store the size of the allocated array
diff --git a/lib/igt_fb.h b/lib/igt_fb.h
index d30a7340..c39caa6b 100644
--- a/lib/igt_fb.h
+++ b/lib/igt_fb.h
@@ -151,6 +151,9 @@ int igt_cairo_printf_line(cairo_t *cr, enum igt_text_align 
align,
 uint32_t igt_bpp_depth_to_drm_format(int bpp, int depth);
 uint32_t igt_drm_format_to_bpp(uint32_t drm_format);
 const char *igt_format_str(uint32_t drm_format);
+
+const char *igt_tiling_str(uint64_t tiling);
+
 void igt_get_all_cairo_formats(const uint32_t **formats, int *format_count);
 
 #endif /* __IGT_FB_H__ */
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index eb57f4a9..f8acdfc8 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -3435,7 +3435,14 @@ void igt_fb_set_size(struct igt_fb *fb, igt_plane_t 
*plane,
igt_plane_set_prop_value(plane, IGT_PLANE_SRC_H, IGT_FIXED(h, 0));
 }
 
-static const char *rotation_name(igt_rotation_t rotation)
+/**
+ * igt_rotation_degrees_str:
+ * @rotation: rotation degrees/reflect mask
+ *
+ * Returns:
+ * Human-readable string for the rotation degrees part in @rotation.
+ */
+const char *igt_rotation_degrees_str(igt_rotation_t rotation)
 {
switch (rotation & IGT_ROTATION_MASK) {
case IGT_ROTATION_0:
@@ -3458,7 +3465,7 @@ void igt_plane_set_rotation(igt_plane_t *plane, 
igt_rotation_t rotation)
 
LOG(display, "%s.%d: plane_set_rotation(%s)\n",
kmstest_pipe_name(pipe->pipe),
-   plane->index, rotation_name(rotation));
+   plane->index, igt_rotation_degrees_str(rotation));
 
igt_plane_set_prop_value(plane, IGT_PLANE_ROTATION, rotation);
 }
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 7b1ae8b5..f4047d3e 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -387,6 +387,7 @@ void igt_plane_set_fence_fd(igt_plane_t *plane, int 
fence_fd);
 void igt_plane_set_position(igt_plane_t *plane, int x, int y);
 void igt_plane_set_size(igt_plane_t *plane, int w, int h);
 void igt_plane_set_rotation(igt_plane_t *plane, igt_rotation_t rotation);
+const char *igt_rotation_degrees_str(igt_rotation_t rotation);
 void igt_fb_set_position(struct igt_fb *fb, igt_plane_t *plane,
uint32_t x, uint32_t y);
 void igt_fb_set_size(struct igt_fb *fb, igt_plane_t *plane,
-- 
2.13.2

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[Intel-gfx] [PATCH 1/2] drm/i915: Add display WA #1175 for planes ending close to right screen edge

[Imre Deak]

As described in the WA on GLK and CNL planes on the right edge of the
screen that have less than 4 pixels visible from the beginning of the
plane to the edge of the screen can cause FIFO underflow and display
corruption.

On GLK/CNL I could trigger the problem only if the plane was at the same
time also aligned to the top edge of the screen (after clipping) and
there were exactly 2 pixels visible from the start of the plane to the
right edge of the screen (so couldn't trigger it with 1 or 3 pixels
visible). Nevertheless, to be sure, I also applied the WA for these cases.

I also couldn't see any problem with the cursor plane and later Art
confirmed that it's not affected, so the WA is applied only for the
other plane types.

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/intel_display.c | 28 
 drivers/gpu/drm/i915/intel_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 221e3a183d36..3d931b652795 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2917,14 +2917,19 @@ static bool skl_check_main_ccs_coordinates(struct 
intel_plane_state *plane_state
return true;
 }
 
-static int skl_check_main_surface(struct intel_plane_state *plane_state)
+static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
 {
+   struct drm_i915_private *dev_priv =
+   to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
int x = plane_state->base.src.x1 >> 16;
int y = plane_state->base.src.y1 >> 16;
int w = drm_rect_width(_state->base.src) >> 16;
int h = drm_rect_height(_state->base.src) >> 16;
+   int dst_x = plane_state->base.dst.x1;
+   int pipe_src_w = crtc_state->pipe_src_w;
int max_width = skl_max_plane_width(fb, 0, rotation);
int max_height = 4096;
u32 alignment, offset, aux_offset = plane_state->aux.offset;
@@ -2935,6 +2940,20 @@ static int skl_check_main_surface(struct 
intel_plane_state *plane_state)
return -EINVAL;
}
 
+   /*
+* Display WA #1175: cnl,glk
+* Planes other than the cursor may cause FIFO underflow and display
+* corruption if starting less than 4 pixels from the right edge of
+* the screen.
+*/
+   if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
+   dst_x > pipe_src_w - 4) {
+   DRM_DEBUG_KMS("requested plane X start position %d invalid 
(valid range %d-%d)\n",
+ dst_x,
+ 0, pipe_src_w - 4);
+   return -EINVAL;
+   }
+
intel_add_fb_offsets(, , plane_state, 0);
offset = intel_compute_tile_offset(, , plane_state, 0);
alignment = intel_surf_alignment(fb, 0);
@@ -3067,7 +3086,8 @@ static int skl_check_ccs_aux_surface(struct 
intel_plane_state *plane_state)
return 0;
 }
 
-int skl_check_plane_surface(struct intel_plane_state *plane_state)
+int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
+   struct intel_plane_state *plane_state)
 {
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
@@ -3107,7 +3127,7 @@ int skl_check_plane_surface(struct intel_plane_state 
*plane_state)
plane_state->aux.y = 0;
}
 
-   ret = skl_check_main_surface(plane_state);
+   ret = skl_check_main_surface(crtc_state, plane_state);
if (ret)
return ret;
 
@@ -12766,7 +12786,7 @@ intel_check_primary_plane(struct intel_plane *plane,
return 0;
 
if (INTEL_GEN(dev_priv) >= 9) {
-   ret = skl_check_plane_surface(state);
+   ret = skl_check_plane_surface(crtc_state, state);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 731dc36d7129..5e23da04837e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1588,7 +1588,8 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
  const struct intel_plane_state *plane_state);
 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
 unsigned int rotation);
-int skl_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
+   struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
 
 /* intel_csr.c */
diff 

[Intel-gfx] [PATCH 2/2] drm/i915: Add WA for planes ending close to left screen edge

[Imre Deak]

While running the kms_plane clipping test I noticed a similar problem to
the one described in Display WA #1175. In this case, similarly for
planes other than the cursor, with 1 or 3 pixels visible from the left
edge of the screen to the end of the plane and an odd plane X offset
used for clipping causes the same kind of underflow and display
corruption as described for WA #1175. Fix this in a similar way as that
WA rejecting planes ending <4 pixels from the left screen edge.

Testcase: igt/kms_plane/plane-clipping-pipe-*-planes
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/intel_display.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3d931b652795..ab04ef471921 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2945,12 +2945,16 @@ static int skl_check_main_surface(const struct 
intel_crtc_state *crtc_state,
 * Planes other than the cursor may cause FIFO underflow and display
 * corruption if starting less than 4 pixels from the right edge of
 * the screen.
+* Besides the above WA fix the similar problem, where planes other
+* than the cursor ending less than 4 pixels from the left edge of the
+* screen may cause FIFO underflow and display corruption.
 */
if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
-   dst_x > pipe_src_w - 4) {
-   DRM_DEBUG_KMS("requested plane X start position %d invalid 
(valid range %d-%d)\n",
- dst_x,
- 0, pipe_src_w - 4);
+   (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
+   DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid 
range %d-%d)\n",
+ dst_x + w < 4 ? "end" : "start",
+ dst_x + w < 4 ? dst_x + w : dst_x,
+ 4, pipe_src_w - 4);
return -EINVAL;
}
 
-- 
2.13.2

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Re: [Intel-gfx] [PATCH] drm/i915/pmu: fix noderef.cocci warnings

[Ville Syrjälä]

On Fri, Jan 12, 2018 at 09:31:16PM +0800, kbuild test robot wrote:
> From: Fengguang Wu 
> 
> drivers/gpu/drm/i915/i915_pmu.c:795:34-40: ERROR: application of sizeof to 
> pointer
> 
>  sizeof when applied to a pointer typed expression gives the size of
>  the pointer
> 
> Generated by: scripts/coccinelle/misc/noderef.cocci
> 
> Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in 
> sysfs")
> Signed-off-by: Fengguang Wu 
> ---
> 
>  i915_pmu.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -792,7 +792,7 @@ create_event_attributes(struct drm_i915_
>   goto err_alloc;
>  
>   /* Max one pointer of each attribute type plus a termination entry. */
> - attr = kzalloc((count * 2 + 1) * sizeof(attr), GFP_KERNEL);
> + attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);

kcalloc()?

>   if (!attr)
>   goto err_alloc;
>  
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: fix noderef.cocci warnings

[Tvrtko Ursulin]

On 12/01/2018 13:31, kbuild test robot wrote:

From: Fengguang Wu 

drivers/gpu/drm/i915/i915_pmu.c:795:34-40: ERROR: application of sizeof to 
pointer

  sizeof when applied to a pointer typed expression gives the size of
  the pointer

Generated by: scripts/coccinelle/misc/noderef.cocci

Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Signed-off-by: Fengguang Wu 
---

  i915_pmu.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -792,7 +792,7 @@ create_event_attributes(struct drm_i915_
goto err_alloc;
  
  	/* Max one pointer of each attribute type plus a termination entry. */

-   attr = kzalloc((count * 2 + 1) * sizeof(attr), GFP_KERNEL);
+   attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
if (!attr)
goto err_alloc;
  


Luckily it is the same size so no actual bug, but fix is still valid. 
Will merge it once it passes CI, thanks!


Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/1] tools/intel_guc_logger: Send GuC log level in new i915 expected format

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/1] tools/intel_guc_logger: Send GuC log 
level in new i915 expected format
URL   : https://patchwork.freedesktop.org/series/36404/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
b64c093fe5a2b65201ebf8305491ea923151d6e7 tools: Update .gitignore

with latest DRM-Tip kernel build CI_DRM_3624
353fa2d3afff drm-tip: 2018y-01m-12d-09h-21m-50s UTC integration manifest

No testlist changes.

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172 +1

fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:494s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:472s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:274s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:415s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:457s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:470s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:506s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:506s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:579s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:531s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:495s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:406s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:575s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:474s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_772/issues.html
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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Tvrtko Ursulin]

On 12/01/2018 13:24, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 13:19:30)


On 12/01/2018 13:03, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 11:43:11)


On 12/01/2018 10:35, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 10:30:26)



On 12/01/2018 09:51, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 09:40:40)

So submit side doesn't work in either case, unless I am missing
something. Would need the pair of port manipulation and context_in to be
atomic.


Sure, there is a small window with the result that we either never turn
off the stats, or turn them off one too early (and then recover if the
my understanding of the underflow protection holds). The same problem as
existed before the reconstruction, except now the window is much
smaller. I'm not that scared by this (it should not explode, nor result
in hopelessly wrong stats) so it can wait until stats enabling doesn't
need to peek at execlists. I think you will need to postpone enabling
until the next context-switch if we wanted to avoid the atomics; except
that poses a problem with the igt expecting busy-start to be accurate. A
dilemma for later.


My analysis was partially incorrect, yes, there is underflow protection
already.

But I don't see that there is a race window where we end up with
permanent 100% busyness before the reconstruction patch. Where do you
see that?

The worst I see without the reconstruction is to miss the accounting of
the batch currently in progress when stats get enabled. Which is a much
less serious, totally ignorable event.


One is observable via pmu, the other not. If we fail to turn off
busy-stats accounting, nothing is lost except for a few wasted cycles.
Except on the next pmu, it starts from the previous cs instead of the
enabling -- but that is a problem that also exists with the second user.


I don't follow, I am talking about permanent 100%. Let me copy what I
wrote earlier:

port0 context complete
context_out - not enabled, no-op
stats enable - port0 busy, active = 1
port0 clear
submit
context_in - active = 2 !!! BAD
port0 set

That leads to permanent 100% until busy stats are disabled. I think that
is hugely less desirable than just failing to account for the currently
running batch, which was the case before reconstruction on enable, and
is 99.9% only a problem for IGTs.

Do you think there is a flaw in this analysis or something else?


No, I don't think it's a huge problem, an improbable race for which the
quick-and-dirty cure may worse than the disease:

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 25360ce0353f..62d9ee9d45a6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1980,16 +1980,22 @@ intel_engine_lookup_user(struct drm_i915_private *i915, 
u8 class, u8 instance)
*/
   int intel_enable_engine_stats(struct intel_engine_cs *engine)
   {
+   struct intel_engine_execlists *execlists = >execlists;
  unsigned long flags;
+   int err = 0;
   
  if (!intel_engine_supports_stats(engine))

  return -ENODEV;
   
+   tasklet_disable(>tasklet);

  spin_lock_irqsave(>stats.lock, flags);
-   if (engine->stats.enabled == ~0)
-   goto busy;
+
+   if (unlikely(engine->stats.enabled == ~0)) {
+   err = -EBUSY;
+   goto unlock;
+   }
+
  if (engine->stats.enabled++ == 0) {
-   struct intel_engine_execlists *execlists = >execlists;
  const struct execlist_port *port = execlists->port;
  unsigned int num_ports = execlists_num_ports(execlists);
   
@@ -2004,14 +2010,12 @@ int intel_enable_engine_stats(struct intel_engine_cs *engine)

  if (engine->stats.active)
  engine->stats.start = engine->stats.enabled_at;
  }
-   spin_unlock_irqrestore(>stats.lock, flags);
   
-   return 0;

-
-busy:
+unlock:
  spin_unlock_irqrestore(>stats.lock, flags);
+   tasklet_enable(>tasklet);
   
-   return -EBUSY;

+   return err;
   }
   
   static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)


using the tasklet control as a spinlock. Whereas the previous race did
not take much effort to observe.


By the previous race you are referring to the missed currently running
batch, or the permanent 100% with active state reconstruction?

You are against reverting the reconstruction? Even if it is unlikely, I
see it as very severe, while the missed current batch is more likely but
not at all severe. So I would be really for the revert. Unfortunately I
did not spot this issue during review. :(


I am against it since we can demonstrate one race very easily in igt,
and the other requires a stress test to be written, when I expect it to
be fixed. We both saw it as a temporary measure as it is poking in places
it should, and the above patch would 

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: expose rcs topology through query uAPI

[Lionel Landwerlin]

On 12/01/18 12:27, Tvrtko Ursulin wrote:


On 11/01/2018 19:53, Lionel Landwerlin wrote:

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

 https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
 Report max_slice/subslice/eus_per_subslice rather than strides 
(Tvrtko)

 Add uapi macros to read data from *_info structs (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_query.c   | 133 


  drivers/gpu/drm/i915/intel_query_info.c |  88 +
  include/uapi/drm/i915_drm.h |  51 
  3 files changed, 272 insertions(+)
  create mode 100644 drivers/gpu/drm/i915/intel_query_info.c

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c

index 5694cfea4553..1d9f5a15323c 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,128 @@
  #include "i915_drv.h"
  #include 
  +static int query_slices_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+    const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+    struct drm_i915_query_slices_info slices_info;
+    u32 data_length, length;
+
+    if (sseu->max_slices == 0)
+    return -ENODEV;
+
+    data_length = sizeof(u8);


sizeof(sseu->slice_mask) ?


Sure.




+    length = sizeof(slices_info) + data_length;
+
+    /*
+ * If we ever change the internal slice mask data type, we'll 
need to

+ * update this function.
+ */
+    BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+    if (query_item->length == 0) {
+    query_item->length = length;
+    return 0;
+    }
+
+    if (query_item->length != length)
+    return -EINVAL;
+
+    memset(_info, 0, sizeof(slices_info));
+    slices_info.max_slices = sseu->max_slices;
+
+    if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), 
_info,

+ sizeof(slices_info)))
+    return -EFAULT;
+
+    if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+ offsetof(struct drm_i915_query_slices_info, 
data)),

+ >slice_mask, data_length))
+    return -EFAULT;
+
+    return 0;
+}
+
+static int query_subslices_info(struct drm_i915_private *dev_priv,
+    struct drm_i915_query_item *query_item)
+{
+    const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+    struct drm_i915_query_subslices_info subslices_info;
+    u32 data_length, length;
+
+    if (sseu->max_slices == 0)
+    return -ENODEV;
+
+    memset(_info, 0, sizeof(subslices_info));
+    subslices_info.max_slices = sseu->max_slices;
+    subslices_info.max_subslices = sseu->max_subslices;
+
+    data_length = subslices_info.max_slices *
+    DIV_ROUND_UP(subslices_info.max_subslices, BITS_PER_BYTE);


s/BITS_PER_BYTE/sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE/ ?


Okay.




+    length = sizeof(subslices_info) + data_length;
+
+    if (query_item->length == 0) {
+    query_item->length = length;
+    return 0;
+    }
+
+    if (query_item->length != length)
+    return -EINVAL;
+
+    if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), 
_info,

+ sizeof(subslices_info)))
+    return -EFAULT;
+
+    if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+ offsetof(struct drm_i915_query_subslices_info, 
data)),

+ sseu->subslice_mask, data_length))
+    return -EFAULT;
+
+    return 0;
+}
+
+static int query_eus_info(struct drm_i915_private *dev_priv,
+  struct drm_i915_query_item *query_item)
+{
+    const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+    struct drm_i915_query_eus_info eus_info;
+    u32 data_length, length;
+
+    if (sseu->max_slices == 0)
+    return -ENODEV;
+
+    memset(_info, 0, sizeof(eus_info));
+    eus_info.max_slices = sseu->max_slices;
+    eus_info.max_subslices = sseu->max_subslices;
+    eus_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
+
+    data_length = eus_info.max_slices * eus_info.max_subslices *
+    DIV_ROUND_UP(eus_info.max_eus_per_subslice, BITS_PER_BYTE);
+    length = sizeof(eus_info) + data_length;
+
+    if (query_item->length == 0) {
+    query_item->length = length;
+    return 0;
+    }
+
+    if (query_item->length != length)
+    return -EINVAL;
+
+    if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), _info,
+   

[Intel-gfx] [PATCH i-g-t v2 1/1] tools/intel_guc_logger: Send GuC log level in new i915 expected format

[Sagar Arun Kamble]

i915 expects GuC log level to be specified as:
0: disabled
1: enabled (verbosity level 0 = min)
2: enabled (verbosity level 1)
3: enabled (verbosity level 2)
4: enabled (verbosity level 3 = max)

Remove the earlier internal layout based logging control from
guc_log_control and send new expected values.

v2: log_level assert in guc_log_control, cleaner level setup (Michal)
added missing copyright header. (Sagar)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 
Reviewed-by: Michal Wajdeczko 
---
 tools/intel_guc_logger.c | 41 +
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
index 031fd84..5f1de8d 100644
--- a/tools/intel_guc_logger.c
+++ b/tools/intel_guc_logger.c
@@ -1,3 +1,26 @@
+/*
+ * Copyright © 2014-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
 
 #include 
 #include 
@@ -51,17 +74,27 @@ uint32_t test_duration, max_filesize;
 pthread_cond_t underflow_cond, overflow_cond;
 bool stop_logging, discard_oldlogs, capturing_stopped;
 
-static void guc_log_control(bool enable_logging)
+static void guc_log_control(bool enable, uint32_t log_level)
 {
int control_fd;
char data[19];
uint64_t val;
int ret;
 
+   igt_assert_lte(log_level, 3);
+
control_fd = igt_debugfs_open(-1, CONTROL_FILE_NAME, O_WRONLY);
igt_assert_f(control_fd >= 0, "couldn't open the guc log control 
file\n");
 
-   val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
+   /*
+* i915 expects GuC log level to be specified as:
+* 0: disabled
+* 1: enabled (verbosity level 0 = min)
+* 2: enabled (verbosity level 1)
+* 3: enabled (verbosity level 2)
+* 4: enabled (verbosity level 3 = max)
+*/
+   val = enable ? log_level + 1 : 0;
 
ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);
igt_assert(ret > 2 && ret < sizeof(data));
@@ -288,7 +321,7 @@ static void init_main_thread(void)
/* Enable the logging, it may not have been enabled from boot and so
 * the relay file also wouldn't have been created.
 */
-   guc_log_control(true);
+   guc_log_control(true, verbosity_level);
 
open_relay_file();
open_output_file();
@@ -420,7 +453,7 @@ int main(int argc, char **argv)
} while (!stop_logging);
 
/* Pause logging on the GuC side */
-   guc_log_control(false);
+   guc_log_control(false, 0);
 
/* Signal flusher thread to make an exit */
capturing_stopped = 1;
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for kms plane scaling tests.

[Patchwork]

== Series Details ==

Series: kms plane scaling tests.
URL   : https://patchwork.freedesktop.org/series/36388/
State : success

== Summary ==

Test gem_softpin:
Subgroup noreloc-s3:
pass   -> SKIP   (shard-snb) fdo#103375
Test kms_flip:
Subgroup blt-wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-snb) fdo#104218 +1
Subgroup basic-flip-vs-modeset:
pass   -> INCOMPLETE (shard-hsw) fdo#102614
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Test gem_eio:
Subgroup in-flight-contexts:
dmesg-warn -> PASS   (shard-snb) fdo#104058 +1
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb) fdo#104600
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-a-planes:
pass   -> SKIP   (shard-snb) fdo#102365
Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104600 https://bugs.freedesktop.org/show_bug.cgi?id=104600
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365

shard-hswtotal:2658 pass:1490 dwarn:1   dfail:0   fail:16  skip:1150 
time:8314s
shard-snbtotal:2743 pass:1310 dwarn:1   dfail:0   fail:15  skip:1417 
time:7775s
Blacklisted hosts:
shard-apltotal:2743 pass:1697 dwarn:3   dfail:0   fail:24  skip:1019 
time:13550s
shard-kbltotal:2743 pass:1821 dwarn:3   dfail:0   fail:23  skip:896 
time:10543s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_771/shards.html
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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

[Lionel Landwerlin]

On 12/01/18 12:01, Tvrtko Ursulin wrote:


On 12/01/2018 10:58, Lionel Landwerlin wrote:

On 12/01/18 10:15, Tvrtko Ursulin wrote:




[snip]


+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+  int slice, int subslice, int eu_group)


What is eu_group for? Will it be used at some point?


In case we ever have more than 8 EUs per subslice.


I am thinking if we could hide that from the call sites, to avoid it 
being passed as zeros, and to avoid having to write loops in other 
patches which reference eu_groups, when it is not immediately obvious 
what that means.


Could we for instance have a helper which would clear/set numbered EUs 
in sseu_dev_info, and so hide all the implementation details?


sseu_enable_eus(sseu, slice, subslice, start, end);

Then when you have code like:

 sseu->eu_mask[sseu_eu_idx(sseu, s, ss, 0)] = ~eu_disabled_mask;

You would write it as:

 /* On this slice/subslice mark EUs 0 to N as enabled. */
 sseu_enable_eus(sseu, s, ss, 0, fls(~eu_disabled_mask));


Hmm... I don't think that works if you have gaps, right?
Like a BXT 2x6 where a row of EUs has been fused off. It would be 
something like 0b01110111 or 0b10111011.




Helper would internally know the size of the underlying storage and 
dtrt. There would be no need to manually manage eu_groups. In the 
initial implementation you could simply GEM_BUG_ON if the EU range 
does not fit into the current storage. Later u8 could be turned into 
u16 or similar. You also wouldn't have any iteration over eu_groups in 
this version.


I think that would be cleaner and easier to extend in the future. 
Unless I overlooked some important detail?


Or even simplify it by passing bitmask instead of start/end, and just 
have no support for more than 8 EUs in this version? No eu_group etc. 
When the need arises to have more, bump the eu_mask type to u16. That 
would require you to put back the stride parameter in the uAPI I think.


I'm not really a fan of having the data field in userspace be 
reinterpreted (as u16 or u32) based on one of the other field.

It might be easier on the kernel side, but complicates userspace.

I would prefer to stick to u8 and have everybody think of 
slice/subslice/eus availability as array of u8 bit fields which you 
might need to iterate more than one if there are more than 8 elements.




Regards,

Tvrtko



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Re: [Intel-gfx] [PATCH i-g-t v2 1/9] tests/kms_plane: Run test for all supported pixel formats, v2.

[Mika Kahola]

On Fri, 2018-01-12 at 11:21 +0100, Maarten Lankhorst wrote:
> From: Mahesh Kumar 
> 
> This patch adds a subtest related to pixel format testing. The test
> tries to create framebuffer with all supported pixel formats on every
> plane,
> and tries to draw them using cairo and commits the same on display.
> 
> Changes since v1:
> - Make the test more generic and try on all planes, including legacy
> cursor.
> 

Reviewed-by: Mika Kahola 

> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Jyoti Yadav 
> Signed-off-by: Vidya Srinivas 
> Signed-off-by: Maarten Lankhorst 
> ---
>  tests/kms_plane.c | 103
> ++
>  1 file changed, 103 insertions(+)
> 
> diff --git a/tests/kms_plane.c b/tests/kms_plane.c
> index 92bf67f1018c..9672763fe619 100644
> --- a/tests/kms_plane.c
> +++ b/tests/kms_plane.c
> @@ -368,6 +368,105 @@ test_plane_panning(data_t *data, enum pipe
> pipe, unsigned int flags)
>   igt_skip_on(connected_outs == 0);
>  }
>  
> +static bool can_draw(uint32_t drm_format)
> +{
> + const uint32_t *drm_formats;
> + int format_count, i;
> +
> + igt_get_all_cairo_formats(_formats, _count);
> +
> + for (i = 0; i < format_count; i++)
> + if (drm_formats[i] == drm_format)
> + return true;
> +
> + return false;
> +}
> +
> +static void test_format_plane(data_t *data, enum pipe pipe,
> +   igt_output_t *output, igt_plane_t
> *plane)
> +{
> + igt_plane_t *primary;
> + struct igt_fb primary_fb, fb;
> + drmModeModeInfo *mode;
> + cairo_t *cr;
> + int i;
> + uint32_t format;
> + uint64_t width, height;
> +
> + mode = igt_output_get_mode(output);
> + if (plane->type != DRM_PLANE_TYPE_CURSOR) {
> + width = mode->hdisplay;
> + height = mode->vdisplay;
> + } else {
> + if (!plane->drm_plane) {
> + igt_debug("Only legacy cursor ioctl
> supported, skipping cursor plane\n");
> + return;
> + }
> + do_or_die(drmGetCap(data->drm_fd,
> DRM_CAP_CURSOR_WIDTH, ));
> + do_or_die(drmGetCap(data->drm_fd,
> DRM_CAP_CURSOR_HEIGHT, ));
> + }
> +
> + igt_debug("Testing connector %s on %s plane %s.%u\n",
> +   igt_output_name(output),
> kmstest_plane_type_name(plane->type),
> +   kmstest_pipe_name(pipe), plane->index);
> +
> + igt_create_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> +   DRM_FORMAT_XRGB,
> LOCAL_DRM_FORMAT_MOD_NONE, _fb);
> +
> + igt_output_set_pipe(output, pipe);
> + primary = igt_output_get_plane_type(output,
> DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, _fb);
> +
> + igt_display_commit2(>display, data->display.is_atomic
> ? COMMIT_ATOMIC : COMMIT_LEGACY);
> +
> + for (i = 0; i < plane->drm_plane->count_formats; i++) {
> + format = plane->drm_plane->formats[i];
> +
> + if (!can_draw(format))
> + continue;
> +
> + igt_debug("Testing format 0x%x on %s.%u\n",
> +   format, kmstest_pipe_name(pipe), plane-
> >index);
> +
> + igt_create_fb(data->drm_fd, width, height,
> +   format, LOCAL_DRM_FORMAT_MOD_NONE,
> );
> +
> + cr = igt_get_cairo_ctx(data->drm_fd, );
> + igt_paint_color(cr, 0, 0, width, height,
> + 0.0, 1.0, 0.0);
> + if (width >= 164 && height >= 164)
> + igt_paint_color(cr, 100, 100, 64, 64, 0.0,
> 0.0, 0.0);
> + igt_assert(cairo_status(cr) == 0);
> + cairo_destroy(cr);
> +
> + igt_plane_set_fb(plane, );
> + igt_display_commit2(>display,
> COMMIT_UNIVERSAL);
> +
> + igt_remove_fb(data->drm_fd, );
> + }
> +
> + igt_plane_set_fb(primary, NULL);
> + igt_plane_set_fb(plane, NULL);
> + igt_remove_fb(data->drm_fd, _fb);
> +}
> +
> +static void
> +test_pixel_formats(data_t *data, enum pipe pipe)
> +{
> + igt_output_t *output;
> +
> + igt_display_require_output_on_pipe(>display, pipe);
> +
> + for_each_valid_output_on_pipe(>display, pipe, output)
> {
> + igt_plane_t *plane;
> +
> + for_each_plane_on_pipe(>display, pipe, plane)
> + test_format_plane(data, pipe, output,
> plane);
> +
> + igt_output_set_pipe(output, PIPE_ANY);
> + }
> +}
> +
>  static void
>  run_tests_for_pipe_plane(data_t *data, enum pipe pipe)
>  {
> @@ -376,6 +475,10 @@ run_tests_for_pipe_plane(data_t *data, enum pipe
> pipe)
>   igt_require(data->display.pipes[pipe].n_planes > 0);
>   }
>  
> + igt_subtest_f("pixel-format-pipe-%s-planes",
> +   

[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL basic enabling + GEM (rev24)

[Patchwork]

== Series Details ==

Series: ICL basic enabling + GEM (rev24)
URL   : https://patchwork.freedesktop.org/series/36230/
State : failure

== Summary ==

Applying: drm/i915/icl: Add initial Icelake definitions.
Applying: drm/i915/icl: Add the ICL PCI IDs
Applying: drm/i915/icl: add icelake_init_clock_gating()
Applying: drm/i915/icl: Icelake interrupt register addresses and bits
Applying: drm/i915/icl: Show interrupt registers in debugfs
Applying: drm/i915/icl: Prepare for more rings
Applying: drm/i915/icl: Interrupt handling
Applying: drm/i915/icl: Ringbuffer interrupt handling
Applying: drm/i915/icl: Correctly initialize the Gen11 engines
Applying: drm/i915/icl: Gen11 render context size
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/intel_engine_cs.c).
error: could not build fake ancestor
Patch failed at 0010 drm/i915/icl: Gen11 render context size
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36353/
State : success

== Summary ==

Series 36353v1 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/36353/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:492s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:485s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:454s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:274s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:418s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:468s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:499s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:504s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:585s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:513s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:490s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:533s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:565s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

353fa2d3aef324005ed2553da6eb174a2f0b drm-tip: 2018y-01m-12d-09h-21m-50s UTC 
integration manifest
23b30dea8c0e drm/i915: expose rcs topology through query uAPI
beeda81a3f3c drm/i915: add query uAPI
09de4f4c4d5f drm/i915: add rcs topology to error state
cef5aec09af7 drm/i915/debugfs: add rcs topology entry
e4220f75ba30 drm/i915/debugfs: reuse max slice/subslices already stored in sseu
aac15151dddb drm/i915: store all subslice masks

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7653/issues.html
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Re: [Intel-gfx] [PATCH i-g-t 1/1] tools/intel_guc_logger: Send GuC log level in new i915 expected format

[Sagar Arun Kamble]

On 1/12/2018 6:51 PM, Michal Wajdeczko wrote:
On Fri, 12 Jan 2018 07:52:04 +0100, Sagar Arun Kamble 
 wrote:



i915 expects GuC log level to be specified as:
0: disabled
1: enabled (verbosity level 0 = min)
2: enabled (verbosity level 1)
3: enabled (verbosity level 2)
4: enabled (verbosity level 3 = max)

Remove the earlier internal layout based logging control from
guc_log_control and send new expected values.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 
---


Reviewed-by: Michal Wajdeczko 

Thanks for the review. Will shared updated rev.


with small bikeshedding below...


 tools/intel_guc_logger.c | 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
index 031fd84..e695497 100644
--- a/tools/intel_guc_logger.c
+++ b/tools/intel_guc_logger.c
@@ -51,18 +51,27 @@ uint32_t test_duration, max_filesize;
 pthread_cond_t underflow_cond, overflow_cond;
 bool stop_logging, discard_oldlogs, capturing_stopped;
-static void guc_log_control(bool enable_logging)
+static void guc_log_control(bool enable, uint32_t log_level)
 {
 int control_fd;
 char data[19];
-    uint64_t val;
+    uint64_t val = 0;
 int ret;


Btw, this shouldn't hurt:

igt_assert_lte(log_level, 3);


Yes

+    /*
+ * i915 expects GuC log level to be specified as:
+ * 0: disabled
+ * 1: enabled (verbosity level 0 = min)
+ * 2: enabled (verbosity level 1)
+ * 3: enabled (verbosity level 2)
+ * 4: enabled (verbosity level 3 = max)
+ */
+    if (enable)
+    val = log_level + 1;


control = enable ? log_level + 1 : 0;


Ok

+
 control_fd = igt_debugfs_open(-1, CONTROL_FILE_NAME, O_WRONLY);
 igt_assert_f(control_fd >= 0, "couldn't open the guc log control 
file\n");

-    val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
-
 ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);


Btw, I'm wondering why we didn't use "fprintf(control_fd, ...)" here

I remember that using read instead of fread was optimization to speed up 
the buffering of logs.

For consistency I believe write is used instead fwrite.

 igt_assert(ret > 2 && ret < sizeof(data));
@@ -288,7 +297,7 @@ static void init_main_thread(void)
 /* Enable the logging, it may not have been enabled from boot 
and so

  * the relay file also wouldn't have been created.
  */
-    guc_log_control(true);
+    guc_log_control(true, verbosity_level);
open_relay_file();
 open_output_file();
@@ -420,7 +429,7 @@ int main(int argc, char **argv)
 } while (!stop_logging);
/* Pause logging on the GuC side */
-    guc_log_control(false);
+    guc_log_control(false, 0);
/* Signal flusher thread to make an exit */
 capturing_stopped = 1;


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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Tvrtko Ursulin]

On 12/01/2018 10:35, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 10:30:26)



On 12/01/2018 09:51, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 09:40:40)

So submit side doesn't work in either case, unless I am missing
something. Would need the pair of port manipulation and context_in to be
atomic.


Sure, there is a small window with the result that we either never turn
off the stats, or turn them off one too early (and then recover if the
my understanding of the underflow protection holds). The same problem as
existed before the reconstruction, except now the window is much
smaller. I'm not that scared by this (it should not explode, nor result
in hopelessly wrong stats) so it can wait until stats enabling doesn't
need to peek at execlists. I think you will need to postpone enabling
until the next context-switch if we wanted to avoid the atomics; except
that poses a problem with the igt expecting busy-start to be accurate. A
dilemma for later.


My analysis was partially incorrect, yes, there is underflow protection
already.

But I don't see that there is a race window where we end up with
permanent 100% busyness before the reconstruction patch. Where do you
see that?

The worst I see without the reconstruction is to miss the accounting of
the batch currently in progress when stats get enabled. Which is a much
less serious, totally ignorable event.


One is observable via pmu, the other not. If we fail to turn off
busy-stats accounting, nothing is lost except for a few wasted cycles.
Except on the next pmu, it starts from the previous cs instead of the
enabling -- but that is a problem that also exists with the second user.


I don't follow, I am talking about permanent 100%. Let me copy what I 
wrote earlier:


port0 context complete
context_out - not enabled, no-op
stats enable - port0 busy, active = 1
port0 clear
submit
context_in - active = 2 !!! BAD
port0 set

That leads to permanent 100% until busy stats are disabled. I think that 
is hugely less desirable than just failing to account for the currently 
running batch, which was the case before reconstruction on enable, and 
is 99.9% only a problem for IGTs.


Do you think there is a flaw in this analysis or something else?

Regards,

Tvrtko




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Re: [Intel-gfx] [PATCH i-g-t 1/1] tools/intel_guc_logger: Send GuC log level in new i915 expected format

[Michal Wajdeczko]

On Fri, 12 Jan 2018 07:52:04 +0100, Sagar Arun Kamble  
 wrote:



i915 expects GuC log level to be specified as:
0: disabled
1: enabled (verbosity level 0 = min)
2: enabled (verbosity level 1)
3: enabled (verbosity level 2)
4: enabled (verbosity level 3 = max)

Remove the earlier internal layout based logging control from
guc_log_control and send new expected values.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 
---


Reviewed-by: Michal Wajdeczko 

with small bikeshedding below...


 tools/intel_guc_logger.c | 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
index 031fd84..e695497 100644
--- a/tools/intel_guc_logger.c
+++ b/tools/intel_guc_logger.c
@@ -51,18 +51,27 @@ uint32_t test_duration, max_filesize;
 pthread_cond_t underflow_cond, overflow_cond;
 bool stop_logging, discard_oldlogs, capturing_stopped;
-static void guc_log_control(bool enable_logging)
+static void guc_log_control(bool enable, uint32_t log_level)
 {
int control_fd;
char data[19];
-   uint64_t val;
+   uint64_t val = 0;
int ret;


Btw, this shouldn't hurt:

igt_assert_lte(log_level, 3);


+   /*
+* i915 expects GuC log level to be specified as:
+* 0: disabled
+* 1: enabled (verbosity level 0 = min)
+* 2: enabled (verbosity level 1)
+* 3: enabled (verbosity level 2)
+* 4: enabled (verbosity level 3 = max)
+*/
+   if (enable)
+   val = log_level + 1;


control = enable ? log_level + 1 : 0;


+
control_fd = igt_debugfs_open(-1, CONTROL_FILE_NAME, O_WRONLY);
 	igt_assert_f(control_fd >= 0, "couldn't open the guc log control  
file\n");

-   val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
-
ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);


Btw, I'm wondering why we didn't use "fprintf(control_fd, ...)" here


igt_assert(ret > 2 && ret < sizeof(data));
@@ -288,7 +297,7 @@ static void init_main_thread(void)
/* Enable the logging, it may not have been enabled from boot and so
 * the relay file also wouldn't have been created.
 */
-   guc_log_control(true);
+   guc_log_control(true, verbosity_level);
open_relay_file();
open_output_file();
@@ -420,7 +429,7 @@ int main(int argc, char **argv)
} while (!stop_logging);
/* Pause logging on the GuC side */
-   guc_log_control(false);
+   guc_log_control(false, 0);
/* Signal flusher thread to make an exit */
capturing_stopped = 1;

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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

[Tvrtko Ursulin]

On 12/01/2018 10:58, Lionel Landwerlin wrote:

On 12/01/18 10:15, Tvrtko Ursulin wrote:


[snip]




--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -80,12 +80,17 @@ void intel_device_info_dump_flags(const struct 
intel_device_info *info,
    static void sseu_dump(const struct sseu_dev_info *sseu, struct 
drm_printer *p)

  {
+    int s;
+
  drm_printf(p, "slice mask: %04x\n", sseu->slice_mask);
  drm_printf(p, "slice total: %u\n", hweight8(sseu->slice_mask));
  drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
-    drm_printf(p, "subslice mask %04x\n", sseu->subslice_mask);
-    drm_printf(p, "subslice per slice: %u\n",
-   hweight8(sseu->subslice_mask));
+    for (s = 0; s < ARRAY_SIZE(sseu->subslice_mask); s++) {
+    drm_printf(p, "slice%d subslice mask %04x\n",
+   s, sseu->subslice_mask[s]);
+    drm_printf(p, "slice%d subslice per slice: %u\n",
+   s, hweight8(sseu->subslice_mask[s]));


Cosmetic only but consider condensing this into one line if you don't 
have a preference to either.


Sure, just conscious about the 80characters.


I wasn't 100% clear here - I meant the kernel log messages, not the 
source code. I think there is no point in logging two lines per slice 
where one only contains a mask, and second a count.


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

[Lionel Landwerlin]

On 12/01/18 10:15, Tvrtko Ursulin wrote:


On 11/01/2018 19:53, Lionel Landwerlin wrote:

Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.

v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
 Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
 Readability changes (Tvrtko)
 Add EU index helper (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_debugfs.c  |  25 ++--
  drivers/gpu/drm/i915/i915_drv.c  |   2 +-
  drivers/gpu/drm/i915/intel_device_info.c | 196 
+++

  drivers/gpu/drm/i915/intel_device_info.h |  36 +-
  drivers/gpu/drm/i915/intel_lrc.c |   2 +-
  drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
  6 files changed, 200 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c

index 2bb63073d73f..463029f72a0b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4285,7 +4285,7 @@ static void 
cherryview_sseu_device_status(struct drm_i915_private *dev_priv,

  continue;
    sseu->slice_mask = BIT(0);
-    sseu->subslice_mask |= BIT(ss);
+    sseu->subslice_mask[0] |= BIT(ss);
  eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
   ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
   ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4332,7 +4332,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,

  continue;
    sseu->slice_mask |= BIT(s);
-    sseu->subslice_mask = info->sseu.subslice_mask;
+    sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
    for (ss = 0; ss < ss_max; ss++) {
  unsigned int eu_cnt;
@@ -4387,8 +4387,8 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,

  sseu->slice_mask |= BIT(s);
    if (IS_GEN9_BC(dev_priv))
-    sseu->subslice_mask =
-    INTEL_INFO(dev_priv)->sseu.subslice_mask;
+    sseu->subslice_mask[s] =
+    INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
    for (ss = 0; ss < ss_max; ss++) {
  unsigned int eu_cnt;
@@ -4398,7 +4398,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,

  /* skip disabled subslice */
  continue;
  -    sseu->subslice_mask |= BIT(ss);
+    sseu->subslice_mask[s] |= BIT(ss);
  }
    eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4420,9 +4420,12 @@ static void 
broadwell_sseu_device_status(struct drm_i915_private *dev_priv,

  sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
    if (sseu->slice_mask) {
-    sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
  sseu->eu_per_subslice =
  INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+    for (s = 0; s < fls(sseu->slice_mask); s++) {
+    sseu->subslice_mask[s] =
+    INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+    }
  sseu->eu_total = sseu->eu_per_subslice *
   sseu_subslice_total(sseu);
  @@ -4441,6 +,7 @@ static void i915_print_sseu_info(struct 
seq_file *m, bool is_available_info,

  {
  struct drm_i915_private *dev_priv = node_to_i915(m->private);
  const char *type = is_available_info ? "Available" : "Enabled";
+    int s;
    seq_printf(m, "  %s Slice Mask: %04x\n", type,
 sseu->slice_mask);
@@ -4448,10 +4452,11 @@ static void i915_print_sseu_info(struct 
seq_file *m, bool is_available_info,

 hweight8(sseu->slice_mask));
  seq_printf(m, "  %s Subslice Total: %u\n", type,
 sseu_subslice_total(sseu));
-    seq_printf(m, "  %s Subslice Mask: %04x\n", type,
-   sseu->subslice_mask);
-    seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
-   hweight8(sseu->subslice_mask));
+    for (s = 0; s < fls(sseu->slice_mask); s++) {
+    seq_printf(m, "  %s Slice%i %u subslices, mask=%04x\n", type,
+   s, hweight8(sseu->subslice_mask[s]),
+   sseu->subslice_mask[s]);
+    }
  seq_printf(m, "  %s EU Total: %u\n", type,
 sseu->eu_total);
  seq_printf(m, "  %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c

index 6c8da9d20c33..969835d3cbcd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -414,7 +414,7 @@ static int i915_getparam(struct drm_device *dev, 
void *data,

  return -ENODEV;
  break;
  case I915_PARAM_SUBSLICE_MASK:
-  

Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Tvrtko Ursulin]

On 11/01/2018 07:30, Chris Wilson wrote:

We have a hole in our busy-stat accounting if the pmu is enabled during
a long running batch, the pmu will not start accumulating busy-time
until the next context switch. This then fails tests that are only
sampling a single batch.

v2: Count each active port just once (context in/out events are only on
the first and last assigment to a port).
v3: Avoid hardcoding knowlege of 2 submission ports

Fixes: 30e17b7847f5 ("drm/i915: Engine busy time tracking")
Testcase: igt/perf_pmu/busy-start
Testcase: igt/perf_pmu/busy-double-start
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++-
  1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6bb51a502b8b..d790bdc227ff 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1951,8 +1951,22 @@ int intel_enable_engine_stats(struct intel_engine_cs 
*engine)
spin_lock_irqsave(>stats.lock, flags);
if (engine->stats.enabled == ~0)
goto busy;
-   if (engine->stats.enabled++ == 0)
+   if (engine->stats.enabled++ == 0) {
+   struct intel_engine_execlists *execlists = >execlists;
+   const struct execlist_port *port = execlists->port;
+   unsigned int num_ports = execlists_num_ports(execlists);
+
engine->stats.enabled_at = ktime_get();
+
+   /* XXX submission method oblivious? */
+   while (num_ports-- && port_isset(port)) {
+   engine->stats.active++;
+   port++;
+   }


Argh, engine->timeline->lock is required to safely to this. But it needs 
to be outside the engine->stats.lock. I can't think of any problems 
doing it at the moment. What do you think?


Regards,

Tvrtko


+
+   if (engine->stats.active)
+   engine->stats.start = engine->stats.enabled_at;
+   }
spin_unlock_irqrestore(>stats.lock, flags);
  
  	return 0;



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Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: expose rcs topology through query uAPI

[Tvrtko Ursulin]

On 11/01/2018 19:53, Lionel Landwerlin wrote:

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

 https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
 Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
 Add uapi macros to read data from *_info structs (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_query.c   | 133 
  drivers/gpu/drm/i915/intel_query_info.c |  88 +
  include/uapi/drm/i915_drm.h |  51 
  3 files changed, 272 insertions(+)
  create mode 100644 drivers/gpu/drm/i915/intel_query_info.c

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 5694cfea4553..1d9f5a15323c 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,128 @@
  #include "i915_drv.h"
  #include 
  
+static int query_slices_info(struct drm_i915_private *dev_priv,

+struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_slices_info slices_info;
+   u32 data_length, length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   data_length = sizeof(u8);


sizeof(sseu->slice_mask) ?


+   length = sizeof(slices_info) + data_length;
+
+   /*
+* If we ever change the internal slice mask data type, we'll need to
+* update this function.
+*/
+   BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+   if (query_item->length == 0) {
+   query_item->length = length;
+   return 0;
+   }
+
+   if (query_item->length != length)
+   return -EINVAL;
+
+   memset(_info, 0, sizeof(slices_info));
+   slices_info.max_slices = sseu->max_slices;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), _info,
+sizeof(slices_info)))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+offsetof(struct 
drm_i915_query_slices_info, data)),
+>slice_mask, data_length))
+   return -EFAULT;
+
+   return 0;
+}
+
+static int query_subslices_info(struct drm_i915_private *dev_priv,
+   struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_subslices_info subslices_info;
+   u32 data_length, length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(subslices_info));
+   subslices_info.max_slices = sseu->max_slices;
+   subslices_info.max_subslices = sseu->max_subslices;
+
+   data_length = subslices_info.max_slices *
+   DIV_ROUND_UP(subslices_info.max_subslices, BITS_PER_BYTE);


s/BITS_PER_BYTE/sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE/ ?


+   length = sizeof(subslices_info) + data_length;
+
+   if (query_item->length == 0) {
+   query_item->length = length;
+   return 0;
+   }
+
+   if (query_item->length != length)
+   return -EINVAL;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), _info,
+sizeof(subslices_info)))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+offsetof(struct 
drm_i915_query_subslices_info, data)),
+sseu->subslice_mask, data_length))
+   return -EFAULT;
+
+   return 0;
+}
+
+static int query_eus_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_eus_info eus_info;
+   u32 data_length, length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(eus_info));
+   eus_info.max_slices = sseu->max_slices;
+   eus_info.max_subslices = sseu->max_subslices;
+   eus_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
+
+   data_length = eus_info.max_slices * eus_info.max_subslices *
+   DIV_ROUND_UP(eus_info.max_eus_per_subslice, BITS_PER_BYTE);
+   

Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Tvrtko Ursulin]

On 12/01/2018 13:03, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 11:43:11)


On 12/01/2018 10:35, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 10:30:26)



On 12/01/2018 09:51, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 09:40:40)

So submit side doesn't work in either case, unless I am missing
something. Would need the pair of port manipulation and context_in to be
atomic.


Sure, there is a small window with the result that we either never turn
off the stats, or turn them off one too early (and then recover if the
my understanding of the underflow protection holds). The same problem as
existed before the reconstruction, except now the window is much
smaller. I'm not that scared by this (it should not explode, nor result
in hopelessly wrong stats) so it can wait until stats enabling doesn't
need to peek at execlists. I think you will need to postpone enabling
until the next context-switch if we wanted to avoid the atomics; except
that poses a problem with the igt expecting busy-start to be accurate. A
dilemma for later.


My analysis was partially incorrect, yes, there is underflow protection
already.

But I don't see that there is a race window where we end up with
permanent 100% busyness before the reconstruction patch. Where do you
see that?

The worst I see without the reconstruction is to miss the accounting of
the batch currently in progress when stats get enabled. Which is a much
less serious, totally ignorable event.


One is observable via pmu, the other not. If we fail to turn off
busy-stats accounting, nothing is lost except for a few wasted cycles.
Except on the next pmu, it starts from the previous cs instead of the
enabling -- but that is a problem that also exists with the second user.


I don't follow, I am talking about permanent 100%. Let me copy what I
wrote earlier:

port0 context complete
context_out - not enabled, no-op
stats enable - port0 busy, active = 1
port0 clear
submit
context_in - active = 2 !!! BAD
port0 set

That leads to permanent 100% until busy stats are disabled. I think that
is hugely less desirable than just failing to account for the currently
running batch, which was the case before reconstruction on enable, and
is 99.9% only a problem for IGTs.

Do you think there is a flaw in this analysis or something else?


No, I don't think it's a huge problem, an improbable race for which the
quick-and-dirty cure may worse than the disease:

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 25360ce0353f..62d9ee9d45a6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1980,16 +1980,22 @@ intel_engine_lookup_user(struct drm_i915_private *i915, 
u8 class, u8 instance)
   */
  int intel_enable_engine_stats(struct intel_engine_cs *engine)
  {
+   struct intel_engine_execlists *execlists = >execlists;
 unsigned long flags;
+   int err = 0;
  
 if (!intel_engine_supports_stats(engine))

 return -ENODEV;
  
+   tasklet_disable(>tasklet);

 spin_lock_irqsave(>stats.lock, flags);
-   if (engine->stats.enabled == ~0)
-   goto busy;
+
+   if (unlikely(engine->stats.enabled == ~0)) {
+   err = -EBUSY;
+   goto unlock;
+   }
+
 if (engine->stats.enabled++ == 0) {
-   struct intel_engine_execlists *execlists = >execlists;
 const struct execlist_port *port = execlists->port;
 unsigned int num_ports = execlists_num_ports(execlists);
  
@@ -2004,14 +2010,12 @@ int intel_enable_engine_stats(struct intel_engine_cs *engine)

 if (engine->stats.active)
 engine->stats.start = engine->stats.enabled_at;
 }
-   spin_unlock_irqrestore(>stats.lock, flags);
  
-   return 0;

-
-busy:
+unlock:
 spin_unlock_irqrestore(>stats.lock, flags);
+   tasklet_enable(>tasklet);
  
-   return -EBUSY;

+   return err;
  }
  
  static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)


using the tasklet control as a spinlock. Whereas the previous race did
not take much effort to observe.


By the previous race you are referring to the missed currently running 
batch, or the permanent 100% with active state reconstruction?


You are against reverting the reconstruction? Even if it is unlikely, I 
see it as very severe, while the missed current batch is more likely but 
not at all severe. So I would be really for the revert. Unfortunately I 
did not spot this issue during review. :(


Regards,

Tvrtko
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[Intel-gfx] [PATCH] drm/i915/pmu: fix noderef.cocci warnings

[kbuild test robot]

From: Fengguang Wu 

drivers/gpu/drm/i915/i915_pmu.c:795:34-40: ERROR: application of sizeof to 
pointer

 sizeof when applied to a pointer typed expression gives the size of
 the pointer

Generated by: scripts/coccinelle/misc/noderef.cocci

Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Signed-off-by: Fengguang Wu 
---

 i915_pmu.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -792,7 +792,7 @@ create_event_attributes(struct drm_i915_
goto err_alloc;
 
/* Max one pointer of each attribute type plus a termination entry. */
-   attr = kzalloc((count * 2 + 1) * sizeof(attr), GFP_KERNEL);
+   attr = kzalloc((count * 2 + 1) * sizeof(*attr), GFP_KERNEL);
if (!attr)
goto err_alloc;
 
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Re: [Intel-gfx] [PATCH i-g-t 2/6] Makefile.meson: use $(error ...) for errors

[Petri Latvala]

On Tue, Oct 24, 2017 at 12:52:52PM +0300, Jani Nikula wrote:
> This is the usual way of flagging fatal errors in Makefiles, and gives
> you the error exit code too.
> 
> Signed-off-by: Jani Nikula 


Regardless of where this change is done (meson.sh output or
Makefile.meson, see reply to patch 1),

Reviewed-by: Petri Latvala 




> ---
>  Makefile.meson | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/Makefile.meson b/Makefile.meson
> index 2ed642bdab37..6955e6a9a694 100644
> --- a/Makefile.meson
> +++ b/Makefile.meson
> @@ -24,10 +24,10 @@ reconfigure: build/build.ninja
>   ninja -C build reconfigure
>  
>  check distcheck dist distclean:
> - echo "This is the meson wrapper, not automake" && false
> + $(error This is the meson wrapper, not automake)
>  
>  install uninstall:
> - echo "meson install support not yet completed" && false
> + $(error meson install support not yet completed)
>  
>  docs:
> - echo "meson gtkdoc support not yet completed" && false
> + $(error meson gtkdoc support not yet completed)
> -- 
> 2.11.0
> 
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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-12 08:16:19)
> 
> On 11/01/2018 07:30, Chris Wilson wrote:
> > We have a hole in our busy-stat accounting if the pmu is enabled during
> > a long running batch, the pmu will not start accumulating busy-time
> > until the next context switch. This then fails tests that are only
> > sampling a single batch.
> > 
> > v2: Count each active port just once (context in/out events are only on
> > the first and last assigment to a port).
> > v3: Avoid hardcoding knowlege of 2 submission ports
> > 
> > Fixes: 30e17b7847f5 ("drm/i915: Engine busy time tracking")
> > Testcase: igt/perf_pmu/busy-start
> > Testcase: igt/perf_pmu/busy-double-start
> > Signed-off-by: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > Reviewed-by: Tvrtko Ursulin 
> > ---
> >   drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++-
> >   1 file changed, 15 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 6bb51a502b8b..d790bdc227ff 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1951,8 +1951,22 @@ int intel_enable_engine_stats(struct intel_engine_cs 
> > *engine)
> >   spin_lock_irqsave(>stats.lock, flags);
> >   if (engine->stats.enabled == ~0)
> >   goto busy;
> > - if (engine->stats.enabled++ == 0)
> > + if (engine->stats.enabled++ == 0) {
> > + struct intel_engine_execlists *execlists = >execlists;
> > + const struct execlist_port *port = execlists->port;
> > + unsigned int num_ports = execlists_num_ports(execlists);
> > +
> >   engine->stats.enabled_at = ktime_get();
> > +
> > + /* XXX submission method oblivious? */
> > + while (num_ports-- && port_isset(port)) {
> > + engine->stats.active++;
> > + port++;
> > + }
> 
> Argh, engine->timeline->lock is required to safely to this. But it needs 
> to be outside the engine->stats.lock. I can't think of any problems 
> doing it at the moment. What do you think?

This isn't even protected by engine->timeline->lock. Writes to the ports
are serialised by the tasklet alone. Note that this is a pure read, so
it won't explode, just potentially miscalculate active and never end.
However, if you look at the other side, update of stats.active by the
tasklet is serialised by stats.lock, is that enough to argue with?
-Chris
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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-12 13:19:30)
> 
> On 12/01/2018 13:03, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-01-12 11:43:11)
> >>
> >> On 12/01/2018 10:35, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-01-12 10:30:26)
> 
> 
>  On 12/01/2018 09:51, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-01-12 09:40:40)
> >> So submit side doesn't work in either case, unless I am missing
> >> something. Would need the pair of port manipulation and context_in to 
> >> be
> >> atomic.
> >
> > Sure, there is a small window with the result that we either never turn
> > off the stats, or turn them off one too early (and then recover if the
> > my understanding of the underflow protection holds). The same problem as
> > existed before the reconstruction, except now the window is much
> > smaller. I'm not that scared by this (it should not explode, nor result
> > in hopelessly wrong stats) so it can wait until stats enabling doesn't
> > need to peek at execlists. I think you will need to postpone enabling
> > until the next context-switch if we wanted to avoid the atomics; except
> > that poses a problem with the igt expecting busy-start to be accurate. A
> > dilemma for later.
> 
>  My analysis was partially incorrect, yes, there is underflow protection
>  already.
> 
>  But I don't see that there is a race window where we end up with
>  permanent 100% busyness before the reconstruction patch. Where do you
>  see that?
> 
>  The worst I see without the reconstruction is to miss the accounting of
>  the batch currently in progress when stats get enabled. Which is a much
>  less serious, totally ignorable event.
> >>>
> >>> One is observable via pmu, the other not. If we fail to turn off
> >>> busy-stats accounting, nothing is lost except for a few wasted cycles.
> >>> Except on the next pmu, it starts from the previous cs instead of the
> >>> enabling -- but that is a problem that also exists with the second user.
> >>
> >> I don't follow, I am talking about permanent 100%. Let me copy what I
> >> wrote earlier:
> >>
> >> port0 context complete
> >> context_out - not enabled, no-op
> >> stats enable - port0 busy, active = 1
> >> port0 clear
> >> submit
> >> context_in - active = 2 !!! BAD
> >> port0 set
> >>
> >> That leads to permanent 100% until busy stats are disabled. I think that
> >> is hugely less desirable than just failing to account for the currently
> >> running batch, which was the case before reconstruction on enable, and
> >> is 99.9% only a problem for IGTs.
> >>
> >> Do you think there is a flaw in this analysis or something else?
> > 
> > No, I don't think it's a huge problem, an improbable race for which the
> > quick-and-dirty cure may worse than the disease:
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 25360ce0353f..62d9ee9d45a6 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1980,16 +1980,22 @@ intel_engine_lookup_user(struct drm_i915_private 
> > *i915, u8 class, u8 instance)
> >*/
> >   int intel_enable_engine_stats(struct intel_engine_cs *engine)
> >   {
> > +   struct intel_engine_execlists *execlists = >execlists;
> >  unsigned long flags;
> > +   int err = 0;
> >   
> >  if (!intel_engine_supports_stats(engine))
> >  return -ENODEV;
> >   
> > +   tasklet_disable(>tasklet);
> >  spin_lock_irqsave(>stats.lock, flags);
> > -   if (engine->stats.enabled == ~0)
> > -   goto busy;
> > +
> > +   if (unlikely(engine->stats.enabled == ~0)) {
> > +   err = -EBUSY;
> > +   goto unlock;
> > +   }
> > +
> >  if (engine->stats.enabled++ == 0) {
> > -   struct intel_engine_execlists *execlists = 
> > >execlists;
> >  const struct execlist_port *port = execlists->port;
> >  unsigned int num_ports = execlists_num_ports(execlists);
> >   
> > @@ -2004,14 +2010,12 @@ int intel_enable_engine_stats(struct 
> > intel_engine_cs *engine)
> >  if (engine->stats.active)
> >  engine->stats.start = engine->stats.enabled_at;
> >  }
> > -   spin_unlock_irqrestore(>stats.lock, flags);
> >   
> > -   return 0;
> > -
> > -busy:
> > +unlock:
> >  spin_unlock_irqrestore(>stats.lock, flags);
> > +   tasklet_enable(>tasklet);
> >   
> > -   return -EBUSY;
> > +   return err;
> >   }
> >   
> >   static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs 
> > *engine)
> > 
> > using the tasklet control as a spinlock. Whereas the previous race did
> > not take much effort to observe.
> 
> By the previous race you are referring to the missed currently running 
> batch, or the permanent 100% with active state 

Re: [Intel-gfx] [PATCH i-g-t 6/6] Makefile.meson: add distclean target to remove Makefile and build dir

[Petri Latvala]

On Tue, Oct 24, 2017 at 12:52:56PM +0300, Jani Nikula wrote:
> Useful for forcing a clean meson build from scratch.
> 
> Signed-off-by: Jani Nikula 
> ---
>  Makefile.meson | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/Makefile.meson b/Makefile.meson
> index c7a87f37f47d..2e09c11052da 100644
> --- a/Makefile.meson
> +++ b/Makefile.meson
> @@ -16,13 +16,16 @@ build/build.ninja: Makefile
>  clean: build/build.ninja
>   ninja -C build clean
>  
> +distclean:
> + rm -rf build Makefile
> +


If patch 1 is applied, there is no Makefile to remove. Adjusted
accordingly, this patch and 3-5 as well are

Reviewed-by: Petri Latvala 





>  test: build/build.ninja
>   ninja -C build test
>  
>  reconfigure: build/build.ninja
>   ninja -C build reconfigure
>  
> -check distcheck dist distclean:
> +check distcheck dist:
>   $(error This is the meson wrapper, not automake)
>  
>  install uninstall:
> -- 
> 2.11.0
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 1/7] drm/i915: Disable preemption and sleeping while using the punit sideband

[Mika Kuoppala]

Hans de Goede  writes:

> Hi,
>
> On 11-01-18 22:42, Hans de Goede wrote:
>> Hi,
>> 
>> On 11-01-18 22:17, Ville Syrjälä wrote:
>>> On Thu, Jan 11, 2018 at 08:53:42PM +, Chris Wilson wrote:
 Quoting Ville Syrjälä (2018-01-11 20:10:45)
> On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote:
>> While we talk to the punit over its sideband, we need to prevent the cpu
>> from sleeping in order to prevent a potential machine hang.
>>
>> Note that by itself, it appears that pm_qos_update_request (via
>> intel_idle) doesn't provide a sufficient barrier to ensure that all core
>> are indeed awake (out of Cstate) and that the package is awake. To do so,
>> we need to supplement the pm_qos with a manual ping on_each_cpu.
>>
>> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=109051
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=102657
>> References: https://bugzilla.kernel.org/show_bug.cgi?id=195255
>> Signed-off-by: Chris Wilson 
>> Cc: Mika Kuoppala 
>> Cc: Hans de Goede 
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c   |  6 
>>   drivers/gpu/drm/i915/i915_drv.h   |  1 +
>>   drivers/gpu/drm/i915/intel_sideband.c | 61 
>> ---
>>   3 files changed, 50 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 6c8da9d20c33..d4b90cc0130b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -902,6 +902,9 @@ static int i915_driver_init_early(struct 
>> drm_i915_private *dev_priv,
>>    spin_lock_init(_priv->uncore.lock);
>>    mutex_init(_priv->sb_lock);
>> + pm_qos_add_request(_priv->sb_qos,
>> +    PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
>> +
>>    mutex_init(_priv->modeset_restore_lock);
>>    mutex_init(_priv->av_mutex);
>>    mutex_init(_priv->wm.wm_mutex);
>> @@ -953,6 +956,9 @@ static void i915_driver_cleanup_early(struct 
>> drm_i915_private *dev_priv)
>>    intel_irq_fini(dev_priv);
>>    i915_workqueues_cleanup(dev_priv);
>>    i915_engines_cleanup(dev_priv);
>> +
>> + pm_qos_remove_request(_priv->sb_qos);
>> + mutex_destroy(_priv->sb_lock);
>>   }
>>   static int i915_mmio_setup(struct drm_i915_private *dev_priv)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index a689396d0ff6..ff3f9effc0bb 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1887,6 +1887,7 @@ struct drm_i915_private {
>>    /* Sideband mailbox protection */
>>    struct mutex sb_lock;
>> + struct pm_qos_request sb_qos;
>>    /** Cached value of IMR to avoid reads in updating the bitfield */
>>    union {
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
>> b/drivers/gpu/drm/i915/intel_sideband.c
>> index 75c872bb8cc9..02bdd2e2cef6 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>> @@ -22,6 +22,8 @@
>>    *
>>    */
>> +#include 
>> +
>>   #include "i915_drv.h"
>>   #include "intel_drv.h"
>> @@ -39,18 +41,20 @@
>>   /* Private register write, double-word addressing, non-posted */
>>   #define SB_CRWRDA_NP 0x07
>> -static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
>> -    u32 port, u32 opcode, u32 addr, u32 *val)
>> +static void ping(void *info)
>>   {
>> - u32 cmd, be = 0xf, bar = 0;
>> - bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
>> +}
>> - cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
>> - (port << IOSF_PORT_SHIFT) | (be << 
>> IOSF_BYTE_ENABLES_SHIFT) |
>> - (bar << IOSF_BAR_SHIFT);
>> +static int vlv_sideband_rw(struct drm_i915_private *dev_priv,
>> +    u32 devfn, u32 port, u32 opcode,
>> +    u32 addr, u32 *val)
>> +{
>> + const bool is_read = (opcode == SB_MRD_NP || opcode == 
>> SB_CRRDDA_NP);
>> + int err;
>> - WARN_ON(!mutex_is_locked(_priv->sb_lock));
>> + lockdep_assert_held(_priv->sb_lock);
>> + /* Flush the previous comms, just in case it failed last time. */
>>    if (intel_wait_for_register(dev_priv,
>>    VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 
>> 0,
>>    5)) {
>> @@ -59,22 +63,43 @@ static int vlv_sideband_rw(struct drm_i915_private 
>> *dev_priv, u32 devfn,
>>    

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: add query uAPI

[Tvrtko Ursulin]

On 11/01/2018 19:53, Lionel Landwerlin wrote:

There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die recovery).

At the moment the GET_PARAM ioctl covers some basic needs, but
generally is only able to return a single value for each defined
parameter. This is a bit problematic with topology descriptions which
are array/maps of available units.

This change introduces a new ioctl that can deal with requests to fill
structures of potentially variable lengths. The user is expected fill
a query with length fields set at 0 on the first call, the kernel then
sets the length fields to the their expected values. A second call to
the kernel with length fields at their expected values will trigger a
copy of the data to the pointed memory locations.

The scope of this uAPI is only to provide information to userspace,
not to allow configuration of the device.

v2: Simplify dispatcher code iteration (Tvrtko)
 Tweak uapi drm_i915_query_item structure (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/Makefile |  1 +
  drivers/gpu/drm/i915/i915_drv.c   |  1 +
  drivers/gpu/drm/i915/i915_drv.h   |  3 +++
  drivers/gpu/drm/i915/i915_query.c | 51 +++
  include/uapi/drm/i915_drm.h   | 31 
  5 files changed, 87 insertions(+)
  create mode 100644 drivers/gpu/drm/i915/i915_query.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3bddd8a06806..b0415a3e2d59 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -69,6 +69,7 @@ i915-y += i915_cmd_parser.o \
  i915_gem_timeline.o \
  i915_gem_userptr.o \
  i915_gemfs.o \
+ i915_query.o \
  i915_trace_points.o \
  i915_vma.o \
  intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 969835d3cbcd..d92e1b7236fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2824,6 +2824,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, 
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, 
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
  };
  
  static struct drm_driver driver = {

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a689396d0ff6..de0eb6ce2fcd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3623,6 +3623,9 @@ extern void i915_perf_fini(struct drm_i915_private 
*dev_priv);
  extern void i915_perf_register(struct drm_i915_private *dev_priv);
  extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
  
+/* i915_query.c */

+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
*file);
+
  /* i915_suspend.c */
  extern int i915_save_state(struct drm_i915_private *dev_priv);
  extern int i915_restore_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
new file mode 100644
index ..5694cfea4553
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+#include 
+
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] tools/intel_guc_logger: Send GuC log level in new i915 expected format

[Patchwork]

== Series Details ==

Series: series starting with [1/1] tools/intel_guc_logger: Send GuC log level 
in new i915 expected format
URL   : https://patchwork.freedesktop.org/series/36384/
State : success

== Summary ==

Test kms_atomic_transition:
Subgroup plane-all-modeset-transition-fencing:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup flip-vs-panning-vs-hang:
dmesg-warn -> PASS   (shard-snb) fdo#103821
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS   (shard-snb) fdo#104058
Test gem_tiled_swapping:
Subgroup non-threaded:
pass   -> INCOMPLETE (shard-hsw) fdo#104218
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
skip   -> FAIL   (shard-hsw) fdo#103375

fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-hswtotal:2638 pass:1498 dwarn:1   dfail:0   fail:8   skip:1130 
time:8963s
shard-snbtotal:2713 pass:1311 dwarn:1   dfail:0   fail:10  skip:1391 
time:7902s
Blacklisted hosts:
shard-apltotal:2713 pass:1686 dwarn:1   dfail:0   fail:25  skip:1001 
time:13553s
shard-kbltotal:2689 pass:1793 dwarn:1   dfail:0   fail:24  skip:870 
time:10366s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_770/shards.html
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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

[Tvrtko Ursulin]

On 11/01/2018 19:53, Lionel Landwerlin wrote:

Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.

v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
 Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
 Readability changes (Tvrtko)
 Add EU index helper (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_debugfs.c  |  25 ++--
  drivers/gpu/drm/i915/i915_drv.c  |   2 +-
  drivers/gpu/drm/i915/intel_device_info.c | 196 +++
  drivers/gpu/drm/i915/intel_device_info.h |  36 +-
  drivers/gpu/drm/i915/intel_lrc.c |   2 +-
  drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
  6 files changed, 200 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2bb63073d73f..463029f72a0b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4285,7 +4285,7 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
  
  		sseu->slice_mask = BIT(0);

-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslice_mask[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4332,7 +4332,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
  
  		sseu->slice_mask |= BIT(s);

-   sseu->subslice_mask = info->sseu.subslice_mask;
+   sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
  
  		for (ss = 0; ss < ss_max; ss++) {

unsigned int eu_cnt;
@@ -4387,8 +4387,8 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
  
  		if (IS_GEN9_BC(dev_priv))

-   sseu->subslice_mask =
-   INTEL_INFO(dev_priv)->sseu.subslice_mask;
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
  
  		for (ss = 0; ss < ss_max; ss++) {

unsigned int eu_cnt;
@@ -4398,7 +4398,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
/* skip disabled subslice */
continue;
  
-sseu->subslice_mask |= BIT(ss);

+   sseu->subslice_mask[s] |= BIT(ss);
}
  
  			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &

@@ -4420,9 +4420,12 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
  
  	if (sseu->slice_mask) {

-   sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
sseu->eu_per_subslice =
INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+   }
sseu->eu_total = sseu->eu_per_subslice *
 sseu_subslice_total(sseu);
  
@@ -4441,6 +,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,

  {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const char *type = is_available_info ? "Available" : "Enabled";
+   int s;
  
  	seq_printf(m, "  %s Slice Mask: %04x\n", type,

   sseu->slice_mask);
@@ -4448,10 +4452,11 @@ static void i915_print_sseu_info(struct seq_file *m, 
bool is_available_info,
   hweight8(sseu->slice_mask));
seq_printf(m, "  %s Subslice Total: %u\n", type,
   sseu_subslice_total(sseu));
-   seq_printf(m, "  %s Subslice Mask: %04x\n", type,
-  sseu->subslice_mask);
-   seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
-  hweight8(sseu->subslice_mask));
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   seq_printf(m, "  %s Slice%i %u subslices, mask=%04x\n", type,
+  s, hweight8(sseu->subslice_mask[s]),
+  sseu->subslice_mask[s]);
+   }
seq_printf(m, "  %s EU Total: %u\n", type,
   sseu->eu_total);
seq_printf(m, "  %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/i915_drv.c 

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/debugfs: add rcs topology entry

[Lionel Landwerlin]

On 12/01/18 10:21, Tvrtko Ursulin wrote:


On 11/01/2018 19:53, Lionel Landwerlin wrote:

While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.

slice0: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice1: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice2: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)

v2: Reformat debugfs printing (Tvrtko)
 Use the new EU mask helper (Tvrtko)

Suggested-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_debugfs.c | 42 
+

  1 file changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c

index 2d1c9cce5fe4..83af1029b907 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3162,6 +3162,47 @@ static int i915_engine_info(struct seq_file 
*m, void *unused)

  return 0;
  }
  +static int i915_rcs_topology(struct seq_file *m, void *unused)
+{
+    struct drm_i915_private *dev_priv = node_to_i915(m->private);
+    const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+    int s, ss;
+    int subslice_stride =
+    DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);


BITS_PER_BYTE is sizeof(eu_mask[0]) * BITS_PER_BYTE ?


If you have 8 or less EUs per subslice, yes.




+
+    if (sseu->max_slices == 0) {
+    seq_printf(m, "Unavailable\n");
+    return 0;
+    }
+
+    for (s = 0; s < sseu->max_slices; s++) {
+    seq_printf(m, "slice%i: %u subslice(s) (0x%hhx):\n",
+   s, hweight8(sseu->subslice_mask[s]),
+   sseu->subslice_mask[s]);
+
+    for (ss = 0; ss < sseu->max_subslices; ss++) {
+    int eu_group, n_subslice_eus = 0;
+
+    for (eu_group = 0; eu_group < subslice_stride; 
eu_group++) {

+    n_subslice_eus +=
+    hweight8(sseu_eu_mask(sseu, s, ss, eu_group));
+    }


Still trying to understand eu_group concept - is this just to handle 
more than 8 EUs couple with the fact you chose eu_mask to be u8? Or is 
a hw concept?


It's not a hw concept. I just wanted to make sure we had a plan if one 
day we end up with more than 8 EUs per subslice.




Regards,

Tvrtko


+
+    seq_printf(m, "\tsubslice%i: %u EUs (", ss, 
n_subslice_eus);

+    for (eu_group = 0;
+ eu_group < max(0, subslice_stride - 1);
+ eu_group++) {
+    u8 val = sseu_eu_mask(sseu, s, ss, eu_group);
+    seq_printf(m, "0x%hhx, ", val);
+    }
+    seq_printf(m, "0x%hhx)\n",
+   sseu_eu_mask(sseu, s, ss, subslice_stride - 1));
+    }
+    }
+
+    return 0;
+}
+
  static int i915_shrinker_info(struct seq_file *m, void *unused)
  {
  struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -4692,6 +4733,7 @@ static const struct drm_info_list 
i915_debugfs_list[] = {

  {"i915_dmc_info", i915_dmc_info, 0},
  {"i915_display_info", i915_display_info, 0},
  {"i915_engine_info", i915_engine_info, 0},
+    {"i915_rcs_topology", i915_rcs_topology, 0},
  {"i915_shrinker_info", i915_shrinker_info, 0},
  {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
  {"i915_dp_mst_info", i915_dp_mst_info, 0},





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Re: [Intel-gfx] [PATCH 6/6] drm/i915: expose rcs topology through query uAPI

[Tvrtko Ursulin]

On 11/01/2018 18:38, Lionel Landwerlin wrote:

On 11/01/18 12:45, Tvrtko Ursulin wrote:




[snip]




+    __u32 n_slices;
+
+    __u8 data[];


Is a zero size array a GCC extension or something? I somehow seem to 
remember someone was complaining about this.


[0] is a GNU C extension
[] is a flexible array in C99


Right.. hm.. I was pretty sure both were not acceptable, but, when I 
look into include/uapi I see that there are both actually in at least 
some use. So I don't know.. fine I guess, but don't be surprised if 
someone complains.


Regards,

Tvrtko
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[Intel-gfx] ✓ Fi.CI.BAT: success for kms plane scaling tests.

[Patchwork]

== Series Details ==

Series: kms plane scaling tests.
URL   : https://patchwork.freedesktop.org/series/36388/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
b64c093fe5a2b65201ebf8305491ea923151d6e7 tools: Update .gitignore

with latest DRM-Tip kernel build CI_DRM_3624
353fa2d3afff drm-tip: 2018y-01m-12d-09h-21m-50s UTC integration manifest

Testlist changes:
+igt@kms_plane@pixel-format-pipe-a-planes
+igt@kms_plane@pixel-format-pipe-b-planes
+igt@kms_plane@pixel-format-pipe-c-planes
+igt@kms_plane@pixel-format-pipe-d-planes
+igt@kms_plane@pixel-format-pipe-e-planes
+igt@kms_plane@pixel-format-pipe-f-planes
+igt@kms_plane_scaling@2x-scaler-multi-pipe
+igt@kms_plane_scaling@pipe-a-plane-scaling
+igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-a-scaler-with-rotation
+igt@kms_plane_scaling@pipe-b-plane-scaling
+igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-b-scaler-with-rotation
+igt@kms_plane_scaling@pipe-c-plane-scaling
+igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-c-scaler-with-rotation
+igt@kms_plane_scaling@pipe-d-plane-scaling
+igt@kms_plane_scaling@pipe-d-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-d-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-d-scaler-with-rotation
+igt@kms_plane_scaling@pipe-e-plane-scaling
+igt@kms_plane_scaling@pipe-e-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-e-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-e-scaler-with-rotation
+igt@kms_plane_scaling@pipe-f-plane-scaling
+igt@kms_plane_scaling@pipe-f-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-f-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-f-scaler-with-rotation
-igt@kms_plane_scaling

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:489s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:474s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:461s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:278s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:466s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:504s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:593s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:495s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:492s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:435s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:571s
fi-glk-dsi   total:288  pass:175  dwarn:1   dfail:4   fail:0   skip:108 
time:314s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_771/issues.html
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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-12 09:40:40)
> So submit side doesn't work in either case, unless I am missing 
> something. Would need the pair of port manipulation and context_in to be 
> atomic.

Sure, there is a small window with the result that we either never turn
off the stats, or turn them off one too early (and then recover if the
my understanding of the underflow protection holds). The same problem as
existed before the reconstruction, except now the window is much
smaller. I'm not that scared by this (it should not explode, nor result
in hopelessly wrong stats) so it can wait until stats enabling doesn't
need to peek at execlists. I think you will need to postpone enabling
until the next context-switch if we wanted to avoid the atomics; except
that poses a problem with the igt expecting busy-start to be accurate. A
dilemma for later.
-Chris
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Re: [Intel-gfx] 282dbf9b "drm/i915: Pass intel_plane and intel_crtc to plane hooks" breaks i945GM in 4.13 and above

[Jani Nikula]

On Thu, 11 Jan 2018, Karl-Johan Karlsson  
wrote:
> Hello,
>
> I have an old Lenovo Thinkpad X60 laptop with a Core 2 Duo T7200 CPU and 
> i945GM integrated graphics whose graphics broke when I tried to update the 
> kernel to get the Meltdown fixes.
>
> GRUB2 shows a graphical boot menu, and Linux displays the Tux boot logos 
> correctly at first. However, almost immediately after displaying the Tuxes, 
> the actively scrolling area of the display shifts about two text lines 
> downward, so that two decapitated penguin heads are left at the top of the 
> screen and new text appears below the lower edge of the screen. When X 
> starts, 
> it too is shifted down the same amount, and only shows a black screen with a 
> (working) mouse cursor. My display manager (SDDM) never shows up. Sometimes, 
> while X is running, random pixels appear in the non-active area at the top of 
> the screen containing the decapitated penguin heads.
>
> My hardware is:
>
> $ grep name /proc/cpuinfo
> model name  : Intel(R) Core(TM)2 CPU T7200  @ 2.00GHz
> model name  : Intel(R) Core(TM)2 CPU T7200  @ 2.00GHz
>
> # lspci | grep VGA
> 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 
> 943/940GML Express Integrated Graphics Controller (rev 03)
>
> # grep Chipset: /var/log/Xorg.0.log
> [33.085] (--) intel(0): Integrated Graphics Chipset: Intel(R) 945GM
>
> $ xrandr | grep primary
> LVDS1 connected primary 1024x768+0+0 (normal left inverted right x axis y 
> axis) 250mm x 180mm
>
> Kernel 4.12.14 does not have the bug. 4.13 and 4.14.11 have the bug in 
> console 
> and X mode. 4.15-rc7 has the bug in console mode, but crashes (completely 
> black screen, Magic SysRq to reboot is the only thing that works) when 
> starting X.
>
> Bisecting from 4.12 to 4.13 pointed to this as the first bad commit:
>
> commit 282dbf9b017bc6d5fdaeadf14e534c2fe22fee2d
> Author: Ville Syrjälä 
> Date:   Mon Mar 27 21:55:33 2017 +0300
>
> drm/i915: Pass intel_plane and intel_crtc to plane hooks
>
> But I know nothing about the driver internals to explain why.

I'm afraid that bisect result doesn't seem plausible. Eyeballing through
it, it's just straightforward mechanical non-functional changes.

Please file a bug over at [1]. Please add drm.debug=14 module parameter,
attach dmesg and Xorg.0.log from boot. Please try confirming the bisect
result by running 282dbf9b017b and 282dbf9b017b^.

BR,
Jani.


[1] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI=DRM/Intel



-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36353/
State : warning

== Summary ==

Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-hsw) fdo#104218 +1
Test kms_cursor_crc:
Subgroup cursor-256x85-random:
notrun -> INCOMPLETE (shard-hsw)
Test gem_eio:
Subgroup in-flight-contexts:
dmesg-warn -> PASS   (shard-snb) fdo#104058
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623
Subgroup fbc-1p-primscrn-pri-indfb-draw-pwrite:
fail   -> PASS   (shard-snb) fdo#103167
Test kms_flip:
Subgroup wf_vblank-vs-dpms-interruptible:
pass   -> DMESG-WARN (shard-hsw) fdo#102614
Test drv_suspend:
Subgroup debugfs-reader:
pass   -> SKIP   (shard-snb)
Test drv_hangman:
Subgroup error-state-capture-blt:
dmesg-warn -> PASS   (shard-snb)
Test gem_wait:
Subgroup write-busy-bsd:
skip   -> PASS   (shard-snb)
Test gem_pwrite_snooped:
fail   -> PASS   (shard-snb)
Test perf_pmu:
Subgroup busy-check-all-rcs0:
skip   -> PASS   (shard-snb)
Test gem_exec_parallel:
Subgroup default-fds:
skip   -> PASS   (shard-snb)
Test gem_partial_pwrite_pread:
Subgroup write:
skip   -> PASS   (shard-snb)
Test prime_vgem:
Subgroup fence-wait-blt:
skip   -> PASS   (shard-snb)

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2695 pass:1528 dwarn:2   dfail:0   fail:10  skip:1154 
time:8868s
shard-snbtotal:2713 pass:1309 dwarn:1   dfail:0   fail:11  skip:1392 
time:7849s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7653/shards.html
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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-12 11:43:11)
> 
> On 12/01/2018 10:35, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-01-12 10:30:26)
> >>
> >>
> >> On 12/01/2018 09:51, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-01-12 09:40:40)
>  So submit side doesn't work in either case, unless I am missing
>  something. Would need the pair of port manipulation and context_in to be
>  atomic.
> >>>
> >>> Sure, there is a small window with the result that we either never turn
> >>> off the stats, or turn them off one too early (and then recover if the
> >>> my understanding of the underflow protection holds). The same problem as
> >>> existed before the reconstruction, except now the window is much
> >>> smaller. I'm not that scared by this (it should not explode, nor result
> >>> in hopelessly wrong stats) so it can wait until stats enabling doesn't
> >>> need to peek at execlists. I think you will need to postpone enabling
> >>> until the next context-switch if we wanted to avoid the atomics; except
> >>> that poses a problem with the igt expecting busy-start to be accurate. A
> >>> dilemma for later.
> >>
> >> My analysis was partially incorrect, yes, there is underflow protection
> >> already.
> >>
> >> But I don't see that there is a race window where we end up with
> >> permanent 100% busyness before the reconstruction patch. Where do you
> >> see that?
> >>
> >> The worst I see without the reconstruction is to miss the accounting of
> >> the batch currently in progress when stats get enabled. Which is a much
> >> less serious, totally ignorable event.
> > 
> > One is observable via pmu, the other not. If we fail to turn off
> > busy-stats accounting, nothing is lost except for a few wasted cycles.
> > Except on the next pmu, it starts from the previous cs instead of the
> > enabling -- but that is a problem that also exists with the second user.
> 
> I don't follow, I am talking about permanent 100%. Let me copy what I 
> wrote earlier:
> 
> port0 context complete
> context_out - not enabled, no-op
> stats enable - port0 busy, active = 1
> port0 clear
> submit
> context_in - active = 2 !!! BAD
> port0 set
> 
> That leads to permanent 100% until busy stats are disabled. I think that 
> is hugely less desirable than just failing to account for the currently 
> running batch, which was the case before reconstruction on enable, and 
> is 99.9% only a problem for IGTs.
> 
> Do you think there is a flaw in this analysis or something else?

No, I don't think it's a huge problem, an improbable race for which the
quick-and-dirty cure may worse than the disease:

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 25360ce0353f..62d9ee9d45a6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1980,16 +1980,22 @@ intel_engine_lookup_user(struct drm_i915_private *i915, 
u8 class, u8 instance)
  */
 int intel_enable_engine_stats(struct intel_engine_cs *engine)
 {
+   struct intel_engine_execlists *execlists = >execlists;
unsigned long flags;
+   int err = 0;
 
if (!intel_engine_supports_stats(engine))
return -ENODEV;
 
+   tasklet_disable(>tasklet);
spin_lock_irqsave(>stats.lock, flags);
-   if (engine->stats.enabled == ~0)
-   goto busy;
+
+   if (unlikely(engine->stats.enabled == ~0)) {
+   err = -EBUSY;
+   goto unlock;
+   }
+
if (engine->stats.enabled++ == 0) {
-   struct intel_engine_execlists *execlists = >execlists;
const struct execlist_port *port = execlists->port;
unsigned int num_ports = execlists_num_ports(execlists);
 
@@ -2004,14 +2010,12 @@ int intel_enable_engine_stats(struct intel_engine_cs 
*engine)
if (engine->stats.active)
engine->stats.start = engine->stats.enabled_at;
}
-   spin_unlock_irqrestore(>stats.lock, flags);
 
-   return 0;
-
-busy:
+unlock:
spin_unlock_irqrestore(>stats.lock, flags);
+   tasklet_enable(>tasklet);
 
-   return -EBUSY;
+   return err;
 }
 
 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)

using the tasklet control as a spinlock. Whereas the previous race did
not take much effort to observe.
-Chris
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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Tvrtko Ursulin]

On 12/01/2018 09:09, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-12 08:16:19)


On 11/01/2018 07:30, Chris Wilson wrote:

We have a hole in our busy-stat accounting if the pmu is enabled during
a long running batch, the pmu will not start accumulating busy-time
until the next context switch. This then fails tests that are only
sampling a single batch.

v2: Count each active port just once (context in/out events are only on
the first and last assigment to a port).
v3: Avoid hardcoding knowlege of 2 submission ports

Fixes: 30e17b7847f5 ("drm/i915: Engine busy time tracking")
Testcase: igt/perf_pmu/busy-start
Testcase: igt/perf_pmu/busy-double-start
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
---
   drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++-
   1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6bb51a502b8b..d790bdc227ff 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1951,8 +1951,22 @@ int intel_enable_engine_stats(struct intel_engine_cs 
*engine)
   spin_lock_irqsave(>stats.lock, flags);
   if (engine->stats.enabled == ~0)
   goto busy;
- if (engine->stats.enabled++ == 0)
+ if (engine->stats.enabled++ == 0) {
+ struct intel_engine_execlists *execlists = >execlists;
+ const struct execlist_port *port = execlists->port;
+ unsigned int num_ports = execlists_num_ports(execlists);
+
   engine->stats.enabled_at = ktime_get();
+
+ /* XXX submission method oblivious? */
+ while (num_ports-- && port_isset(port)) {
+ engine->stats.active++;
+ port++;
+ }


Argh, engine->timeline->lock is required to safely to this. But it needs
to be outside the engine->stats.lock. I can't think of any problems
doing it at the moment. What do you think?


This isn't even protected by engine->timeline->lock. Writes to the ports
are serialised by the tasklet alone. Note that this is a pure read, so


Yes, my bad.


it won't explode, just potentially miscalculate active and never end.
However, if you look at the other side, update of stats.active by the
tasklet is serialised by stats.lock, is that enough to argue with?


Nice one for early morning.. :)

port0 context complete
context_out - not enabled, no-op
stats enable - port0 busy, active = 1
port0 clear
submit
context_in - active = 2 !!! BAD
port0 set

So a problem, no? Do we need to change the ordering of port updates vs 
context_in/out calls?


port0 context complete
stats enable - port0 busy, active = 1
a) context_out - enabled, active = 0
port0 clear
b) context_out - enabled, active = 0
submit
context_in - active = 1 GOOD
port0 set

From the submit side, current ordering:

port0 submit
context_in - not enabled, no-op
stats enable - port0 not busy, active = 0
port0 set
port0 context complete
context_out - active = -1 !!! BAD

Opposite ordering:

port0 submit

a) stats enable - port0 not busy, active = 0
a) port0 set
a) context_in - active = 1 OK

b) port0 set
b) stats enable - port0 busy, active = 1
b) context_in - active = 2 !!! BAD

So submit side doesn't work in either case, unless I am missing 
something. Would need the pair of port manipulation and context_in to be 
atomic.


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

[Tvrtko Ursulin]

On 12/01/2018 10:58, Lionel Landwerlin wrote:

On 12/01/18 10:15, Tvrtko Ursulin wrote:




[snip]


+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+  int slice, int subslice, int eu_group)


What is eu_group for? Will it be used at some point?


In case we ever have more than 8 EUs per subslice.


I am thinking if we could hide that from the call sites, to avoid it 
being passed as zeros, and to avoid having to write loops in other 
patches which reference eu_groups, when it is not immediately obvious 
what that means.


Could we for instance have a helper which would clear/set numbered EUs 
in sseu_dev_info, and so hide all the implementation details?


sseu_enable_eus(sseu, slice, subslice, start, end);

Then when you have code like:

 sseu->eu_mask[sseu_eu_idx(sseu, s, ss, 0)] = ~eu_disabled_mask;

You would write it as:

 /* On this slice/subslice mark EUs 0 to N as enabled. */
 sseu_enable_eus(sseu, s, ss, 0, fls(~eu_disabled_mask));

Helper would internally know the size of the underlying storage and 
dtrt. There would be no need to manually manage eu_groups. In the 
initial implementation you could simply GEM_BUG_ON if the EU range does 
not fit into the current storage. Later u8 could be turned into u16 or 
similar. You also wouldn't have any iteration over eu_groups in this 
version.


I think that would be cleaner and easier to extend in the future. Unless 
I overlooked some important detail?


Or even simplify it by passing bitmask instead of start/end, and just 
have no support for more than 8 EUs in this version? No eu_group etc. 
When the need arises to have more, bump the eu_mask type to u16. That 
would require you to put back the stride parameter in the uAPI I think.


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH i-g-t 1/6] meson: split out simple makefile integration into a makefile

[Petri Latvala]

On Tue, Oct 24, 2017 at 12:52:51PM +0300, Jani Nikula wrote:
> A separate makefile is easier to read and maintain than a here
> document. The meson.sh shell script becomes trivial too.
> 
> Signed-off-by: Jani Nikula 
> ---
>  Makefile.meson | 33 +
>  meson.sh   | 38 +++---
>  2 files changed, 36 insertions(+), 35 deletions(-)
>  create mode 100644 Makefile.meson


I believe the goal for the toplevel makefile wrapper was to support
editors that issue straight up 'make'.




-- 
Petri Latvala




> 
> diff --git a/Makefile.meson b/Makefile.meson
> new file mode 100644
> index ..2ed642bdab37
> --- /dev/null
> +++ b/Makefile.meson
> @@ -0,0 +1,33 @@
> +# -*- makefile -*-
> +# Simple makefile integration for meson
> +
> +.PHONY: default docs
> +default: all
> +
> +Makefile: Makefile.meson
> + cp $< $@
> +
> +build/build.ninja: Makefile
> + mkdir -p build
> + meson build
> +
> +all: build/build.ninja
> + ninja -C build
> +
> +clean: build/build.ninja
> + ninja -C build clean
> +
> +test: build/build.ninja
> + ninja -C build test
> +
> +reconfigure: build/build.ninja
> + ninja -C build reconfigure
> +
> +check distcheck dist distclean:
> + echo "This is the meson wrapper, not automake" && false
> +
> +install uninstall:
> + echo "meson install support not yet completed" && false
> +
> +docs:
> + echo "meson gtkdoc support not yet completed" && false
> diff --git a/meson.sh b/meson.sh
> index cbf1a9326dbe..cdb384eb16a6 100755
> --- a/meson.sh
> +++ b/meson.sh
> @@ -1,35 +1,3 @@
> -#!/bin/bash
> -
> -cat > Makefile < -
> -.PHONY: default docs
> -default: all
> -
> -build/build.ninja:
> - mkdir -p build
> - meson build
> -
> -all: build/build.ninja
> - ninja -C build
> -
> -clean: build/build.ninja
> - ninja -C build clean
> -
> -test: build/build.ninja
> - ninja -C build test
> -
> -reconfigure: build/build.ninja
> - ninja -C build reconfigure
> -
> -check distcheck dist distclean:
> - echo "This is the meson wrapper, not automake" && false
> -
> -install uninstall:
> - echo "meson install support not yet completed" && false
> -
> -docs:
> - echo "meson gtkdoc support not yet completed" && false
> -
> -EOF
> -
> -make $@
> +#!/bin/sh
> +# Simple makefile integration for meson
> +make -f Makefile.meson "$@"
> -- 
> 2.11.0
> 
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] tools/intel_guc_logger: Send GuC log level in new i915 expected format

[Patchwork]

== Series Details ==

Series: series starting with [1/1] tools/intel_guc_logger: Send GuC log level 
in new i915 expected format
URL   : https://patchwork.freedesktop.org/series/36384/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d37369c7146a2ceb332592297d311d501c1c748e Revert "build: make meson more 
official" damage

with latest DRM-Tip kernel build CI_DRM_3623
dbc7615897f6 drm-tip: 2018y-01m-11d-16h-49m-38s UTC integration manifest

No testlist changes.

Test debugfs_test:
Subgroup read_all_entries:
fail   -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1
incomplete -> PASS   (fi-snb-2520m) fdo#103713 +1
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:375s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:499s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:473s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:462s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:516s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:467s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:499s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:505s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:576s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:515s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:535s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:497s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:403s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:472s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_770/issues.html
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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

[Lionel Landwerlin]

On 12/01/18 11:05, Tvrtko Ursulin wrote:


On 12/01/2018 10:58, Lionel Landwerlin wrote:

On 12/01/18 10:15, Tvrtko Ursulin wrote:


[snip]




--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -80,12 +80,17 @@ void intel_device_info_dump_flags(const struct 
intel_device_info *info,
    static void sseu_dump(const struct sseu_dev_info *sseu, struct 
drm_printer *p)

  {
+    int s;
+
  drm_printf(p, "slice mask: %04x\n", sseu->slice_mask);
  drm_printf(p, "slice total: %u\n", hweight8(sseu->slice_mask));
  drm_printf(p, "subslice total: %u\n", 
sseu_subslice_total(sseu));

-    drm_printf(p, "subslice mask %04x\n", sseu->subslice_mask);
-    drm_printf(p, "subslice per slice: %u\n",
-   hweight8(sseu->subslice_mask));
+    for (s = 0; s < ARRAY_SIZE(sseu->subslice_mask); s++) {
+    drm_printf(p, "slice%d subslice mask %04x\n",
+   s, sseu->subslice_mask[s]);
+    drm_printf(p, "slice%d subslice per slice: %u\n",
+   s, hweight8(sseu->subslice_mask[s]));


Cosmetic only but consider condensing this into one line if you 
don't have a preference to either.


Sure, just conscious about the 80characters.


I wasn't 100% clear here - I meant the kernel log messages, not the 
source code. I think there is no point in logging two lines per slice 
where one only contains a mask, and second a count.


Regards,

Tvrtko



Ahaha :)

Okay, done.


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Re: [Intel-gfx] [PATCH v3] drm/i915/pmu: Reconstruct active state on starting busy-stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-12 10:30:26)
> 
> 
> On 12/01/2018 09:51, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-01-12 09:40:40)
> >> So submit side doesn't work in either case, unless I am missing
> >> something. Would need the pair of port manipulation and context_in to be
> >> atomic.
> > 
> > Sure, there is a small window with the result that we either never turn
> > off the stats, or turn them off one too early (and then recover if the
> > my understanding of the underflow protection holds). The same problem as
> > existed before the reconstruction, except now the window is much
> > smaller. I'm not that scared by this (it should not explode, nor result
> > in hopelessly wrong stats) so it can wait until stats enabling doesn't
> > need to peek at execlists. I think you will need to postpone enabling
> > until the next context-switch if we wanted to avoid the atomics; except
> > that poses a problem with the igt expecting busy-start to be accurate. A
> > dilemma for later.
> 
> My analysis was partially incorrect, yes, there is underflow protection 
> already.
> 
> But I don't see that there is a race window where we end up with 
> permanent 100% busyness before the reconstruction patch. Where do you 
> see that?
> 
> The worst I see without the reconstruction is to miss the accounting of 
> the batch currently in progress when stats get enabled. Which is a much 
> less serious, totally ignorable event.

One is observable via pmu, the other not. If we fail to turn off
busy-stats accounting, nothing is lost except for a few wasted cycles.
Except on the next pmu, it starts from the previous cs instead of the
enabling -- but that is a problem that also exists with the second user.
-Chris
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[Intel-gfx] [PATCH i-g-t v2 9/9] tests/kms_plane_scaling: test for multi pipe with scaling

[Maarten Lankhorst]

From: Jyoti Yadav 

Add a subtest to display primary and overlay planes on two
connected pipes and runs scaling test on both pipes

Changes since v1:
- Commit first before trying any scaling. (Maarten)
- Use the same logic as kms_cursor_legacy to find a pipe and output. (Maarten)
- Rework test to work with how cleanup is handled. (Maarten)

Signed-off-by: Jyoti Yadav 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 91 ++-
 1 file changed, 90 insertions(+), 1 deletion(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index a0f6db9f96f8..836f711d5bf2 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -40,10 +40,12 @@ typedef struct {
 
int num_scalers;
 
-   struct igt_fb fb[3];
+   struct igt_fb fb[4];
+
igt_plane_t *plane1;
igt_plane_t *plane2;
igt_plane_t *plane3;
+   igt_plane_t *plane4;
 } data_t;
 
 #define FILE_NAME   "1080p-left.png"
@@ -454,6 +456,90 @@ test_scaler_with_clipping_clamping_scenario(data_t *d, 
enum pipe pipe, igt_outpu
igt_display_commit2(>display, COMMIT_ATOMIC);
 }
 
+static void find_connected_pipe(igt_display_t *display, bool second, enum pipe 
*pipe, igt_output_t **output)
+{
+   enum pipe first = PIPE_NONE;
+   igt_output_t *first_output = NULL;
+   bool found = false;
+
+   for_each_pipe_with_valid_output(display, *pipe, *output) {
+   if (first == *pipe || *output == first_output)
+   continue;
+
+   if (second) {
+   first = *pipe;
+   first_output = *output;
+   second = false;
+   continue;
+   }
+
+   return;
+   }
+
+   if (first_output)
+   igt_require_f(found, "No second valid output found\n");
+   else
+   igt_require_f(found, "No valid outputs found\n");
+}
+
+static void test_scaler_with_multi_pipe_plane(data_t *d)
+{
+   igt_display_t *display = >display;
+   igt_output_t *output1, *output2;
+   drmModeModeInfo *mode1, *mode2;
+   enum pipe pipe1, pipe2;
+
+   cleanup_crtc(d);
+
+   find_connected_pipe(display, false, , );
+   find_connected_pipe(display, true, , );
+
+   igt_skip_on(!output1 || !output2);
+
+   igt_output_set_pipe(output1, pipe1);
+   igt_output_set_pipe(output2, pipe2);
+
+   d->plane1 = igt_output_get_plane(output1, 0);
+   d->plane2 = igt_output_get_plane(output1, 1);
+   d->plane3 = igt_output_get_plane(output2, 0);
+   d->plane4 = igt_output_get_plane(output2, 1);
+
+   mode1 = igt_output_get_mode(output1);
+   mode2 = igt_output_get_mode(output2);
+
+   igt_create_pattern_fb(d->drm_fd, 600, 600,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_Y_TILED, >fb[0]);
+
+   igt_create_pattern_fb(d->drm_fd, 500, 500,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_Y_TILED, >fb[1]);
+
+   igt_create_pattern_fb(d->drm_fd, 700, 700,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_Y_TILED, >fb[2]);
+
+   igt_create_pattern_fb(d->drm_fd, 400, 400,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_Y_TILED, >fb[3]);
+
+   igt_plane_set_fb(d->plane1, >fb[0]);
+   igt_plane_set_fb(d->plane2, >fb[1]);
+   igt_plane_set_fb(d->plane3, >fb[2]);
+   igt_plane_set_fb(d->plane4, >fb[3]);
+   igt_display_commit2(display, COMMIT_ATOMIC);
+
+   /* Upscaling Primary */
+   igt_plane_set_size(d->plane1, mode1->hdisplay, mode1->vdisplay);
+   igt_plane_set_size(d->plane3, mode2->hdisplay, mode2->vdisplay);
+   igt_display_commit2(display, COMMIT_ATOMIC);
+
+   /* Upscaling Sprites */
+   igt_plane_set_size(d->plane2, mode1->hdisplay, mode1->vdisplay);
+   igt_plane_set_size(d->plane4, mode2->hdisplay, mode2->vdisplay);
+   igt_display_commit2(display, COMMIT_ATOMIC);
+}
+
 igt_main
 {
data_t data = {};
@@ -493,6 +579,9 @@ igt_main

test_scaler_with_clipping_clamping_scenario(, pipe, output);
}
 
+   igt_subtest_f("2x-scaler-multi-pipe")
+   test_scaler_with_multi_pipe_plane();
+
igt_fixture
igt_display_fini();
 }
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 4/9] tests/kms_plane_scaling: Convert from simple test to full test

[Maarten Lankhorst]

Convert the test to run subtests per pipe, before we start adding
more subtests.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 46 +-
 1 file changed, 21 insertions(+), 25 deletions(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 5487f89e5149..624e20447780 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -170,6 +170,9 @@ test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, 
igt_output_t *output)
drmModeModeInfo *mode;
int primary_plane_scaling = 0; /* For now */
 
+   igt_require(d->num_scalers > 0);
+
+   igt_display_reset(display);
igt_output_set_pipe(output, pipe);
mode = igt_output_get_mode(output);
 
@@ -296,39 +299,32 @@ cleanup:
cleanup_crtc(d, output, d->plane1);
 }
 
-static void test_plane_scaling(data_t *d, enum pipe pipe)
-{
-   igt_output_t *output;
-   int valid_tests = 0;
-
-   igt_require(d->num_scalers);
-
-   for_each_valid_output_on_pipe(>display, pipe, output) {
-   test_plane_scaling_on_pipe(d, pipe, output);
-   igt_output_set_pipe(output, PIPE_ANY);
-   valid_tests++;
-   }
-
-   igt_require_f(valid_tests, "no valid crtc/connector combinations 
found\n");
-}
-
-igt_simple_main
+igt_main
 {
data_t data = {};
enum pipe pipe;
 
igt_skip_on_simulation();
 
+   igt_fixture {
+   data.drm_fd = drm_open_driver(DRIVER_INTEL);
+   igt_require_pipe_crc(data.drm_fd);
+   igt_display_init(, data.drm_fd);
+   data.devid = intel_get_drm_devid(data.drm_fd);
+   data.num_scalers = intel_gen(data.devid) >= 9 ? 2 : 0;
+   }
 
-   data.drm_fd = drm_open_driver(DRIVER_INTEL);
-   igt_require_pipe_crc(data.drm_fd);
-   igt_display_init(, data.drm_fd);
-   data.devid = intel_get_drm_devid(data.drm_fd);
+   for_each_pipe_static(pipe) igt_subtest_group {
+   igt_output_t *output;
 
-   data.num_scalers = intel_gen(data.devid) >= 9 ? 2 : 0;
+   igt_fixture
+   igt_display_require_output_on_pipe(, pipe);
 
-   for_each_pipe_static(pipe)
-   test_plane_scaling(, pipe);
+   igt_subtest_f("pipe-%s-plane-scaling", kmstest_pipe_name(pipe))
+   for_each_valid_output_on_pipe(, pipe, 
output)
+   test_plane_scaling_on_pipe(, pipe, output);
+   }
 
-   igt_display_fini();
+   igt_fixture
+   igt_display_fini();
 }
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 2/9] tests/kms_plane_scaling: Move the actual test to its own function.

[Maarten Lankhorst]

We will add more subtests in the future, it's more clear if we split
out the actual test to its own function first.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 226 --
 1 file changed, 117 insertions(+), 109 deletions(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 403df47e2d3b..37e05158b968 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -163,144 +163,151 @@ static void iterate_plane_scaling(data_t *d, 
drmModeModeInfo *mode)
}
 }
 
-static void test_plane_scaling(data_t *d)
+static void
+test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, igt_output_t *output)
 {
igt_display_t *display = >display;
-   igt_output_t *output;
-   enum pipe pipe;
-   int valid_tests = 0;
+   drmModeModeInfo *mode;
int primary_plane_scaling = 0; /* For now */
 
-   igt_require(d->num_scalers);
+   igt_output_set_pipe(output, pipe);
+   mode = igt_output_get_mode(output);
+
+   /* allocate fb2 with image size */
+   d->fb_id2 = igt_create_image_fb(d->drm_fd, 0, 0,
+   DRM_FORMAT_XRGB,
+   LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled 
*/
+   FILE_NAME, >fb2);
+   igt_assert(d->fb_id2);
+
+   d->fb_id3 = igt_create_pattern_fb(d->drm_fd,
+ mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_X_TILED, /* 
tiled */
+ >fb3);
+   igt_assert(d->fb_id3);
+
+   /* Set up display with plane 1 */
+   d->plane1 = igt_output_get_plane(output, 0);
+   prepare_crtc(d, output, pipe, d->plane1, mode, COMMIT_UNIVERSAL);
+
+   if (primary_plane_scaling) {
+   /* Primary plane upscaling */
+   igt_fb_set_position(>fb1, d->plane1, 100, 100);
+   igt_fb_set_size(>fb1, d->plane1, 500, 500);
+   igt_plane_set_position(d->plane1, 0, 0);
+   igt_plane_set_size(d->plane1, mode->hdisplay, mode->vdisplay);
+   igt_display_commit2(display, COMMIT_UNIVERSAL);
 
-   for_each_pipe_with_valid_output(display, pipe, output) {
-   drmModeModeInfo *mode;
-
-   igt_output_set_pipe(output, pipe);
-
-   mode = igt_output_get_mode(output);
-
-   /* allocate fb2 with image size */
-   d->fb_id2 = igt_create_image_fb(d->drm_fd, 0, 0,
-   DRM_FORMAT_XRGB,
-   LOCAL_I915_FORMAT_MOD_X_TILED, 
/* tiled */
-   FILE_NAME, >fb2);
-   igt_assert(d->fb_id2);
-
-   d->fb_id3 = igt_create_pattern_fb(d->drm_fd,
- mode->hdisplay, 
mode->vdisplay,
- DRM_FORMAT_XRGB,
- 
LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
- >fb3);
-   igt_assert(d->fb_id3);
-
-   /* Set up display with plane 1 */
-   d->plane1 = igt_output_get_plane(output, 0);
-   prepare_crtc(d, output, pipe, d->plane1, mode, 
COMMIT_UNIVERSAL);
-
-   if (primary_plane_scaling) {
-   /* Primary plane upscaling */
-   igt_fb_set_position(>fb1, d->plane1, 100, 100);
-   igt_fb_set_size(>fb1, d->plane1, 500, 500);
-   igt_plane_set_position(d->plane1, 0, 0);
-   igt_plane_set_size(d->plane1, mode->hdisplay, 
mode->vdisplay);
-   igt_display_commit2(display, COMMIT_UNIVERSAL);
+   /* Primary plane 1:1 no scaling */
+   igt_fb_set_position(>fb1, d->plane1, 0, 0);
+   igt_fb_set_size(>fb1, d->plane1, d->fb1.width, 
d->fb1.height);
+   igt_plane_set_position(d->plane1, 0, 0);
+   igt_plane_set_size(d->plane1, mode->hdisplay, mode->vdisplay);
+   igt_display_commit2(display, COMMIT_UNIVERSAL);
+   }
 
-   /* Primary plane 1:1 no scaling */
-   igt_fb_set_position(>fb1, d->plane1, 0, 0);
-   igt_fb_set_size(>fb1, d->plane1, d->fb1.width, 
d->fb1.height);
-   igt_plane_set_position(d->plane1, 0, 0);
-   igt_plane_set_size(d->plane1, mode->hdisplay, 
mode->vdisplay);
-   igt_display_commit2(display, COMMIT_UNIVERSAL);
-   }
+   /* Set up fb2->plane2 mapping. */
+   d->plane2 = igt_output_get_plane(output, 1);
+   

[Intel-gfx] [PATCH i-g-t v2 7/9] tests/kms_plane_scaling: test scaler with clipping clamping, v2.

[Maarten Lankhorst]

From: Jyoti Yadav 

This patch adds subtest to test scaler clipping and clamping
scenario.

Changes since v1:
- Modify test to work with the changes to kms_plane_scaling. (Maarten)

Signed-off-by: Jyoti Yadav 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 45 +
 1 file changed, 45 insertions(+)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 821d0a9c883b..a0f6db9f96f8 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -412,6 +412,48 @@ test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, 
igt_output_t *output)
}
 }
 
+static void
+test_scaler_with_clipping_clamping_scenario(data_t *d, enum pipe pipe, 
igt_output_t *output)
+{
+   drmModeModeInfo *mode;
+   igt_require(d->num_scalers);
+
+   /* Gen9 has single scaler in PIPEC */
+   igt_skip_on(intel_gen(d->devid) == 9 && pipe == PIPE_C);
+
+   mode = igt_output_get_mode(output);
+   d->plane1 = >display.pipes[pipe].planes[0];
+   prepare_crtc(d, output, pipe, d->plane1, mode);
+
+   igt_create_pattern_fb(d->drm_fd,
+ mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_X_TILED, >fb[1]);
+
+   igt_create_pattern_fb(d->drm_fd,
+ mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_Y_TILED, >fb[2]);
+
+   igt_plane_set_fb(d->plane1, >fb[1]);
+   d->plane2 = igt_output_get_plane(output, 1);
+   igt_plane_set_fb(d->plane2, >fb[2]);
+
+   igt_fb_set_position(>fb[1], d->plane1, 0, 0);
+   igt_fb_set_size(>fb[1], d->plane1, 300, 300);
+   igt_plane_set_position(d->plane1, 100, 400);
+   igt_fb_set_position(>fb[2], d->plane2, 0, 0);
+   igt_fb_set_size(>fb[2], d->plane2, 400, 400);
+   igt_plane_set_position(d->plane2, 100, 100);
+
+   /* scaled window size is outside the modeset area.*/
+   igt_plane_set_size(d->plane1, mode->hdisplay + 200,
+   mode->vdisplay + 200);
+   igt_plane_set_size(d->plane2, mode->hdisplay + 100,
+   mode->vdisplay + 100);
+   igt_display_commit2(>display, COMMIT_ATOMIC);
+}
+
 igt_main
 {
data_t data = {};
@@ -446,6 +488,9 @@ igt_main
for_each_valid_output_on_pipe(, pipe, 
output)
test_scaler_with_rotation_pipe(, pipe, 
output);
 
+   igt_subtest_f("pipe-%s-scaler-with-clipping-clamping", 
kmstest_pipe_name(pipe))
+   for_each_valid_output_on_pipe(, pipe, 
output)
+   
test_scaler_with_clipping_clamping_scenario(, pipe, output);
}
 
igt_fixture
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 6/9] tests/kms_plane_scaling: test scaling with tiling rotation and pixel formats, v2.

[Maarten Lankhorst]

From: Jyoti Yadav 

This patch adds subtest for testing scaling in combination with rotation
and pixel formats.

Changes since v1:
- Rework test to work with the other changes to kms_plane_scaling. (Maarten)
- Remove hardcodes for MIN/MAX_SRC_WIDTH, and use the value directly. (Maarten)

Signed-off-by: Jyoti Yadav 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 161 +-
 1 file changed, 160 insertions(+), 1 deletion(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 44ff91d7738f..821d0a9c883b 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -48,10 +48,55 @@ typedef struct {
 
 #define FILE_NAME   "1080p-left.png"
 
+#define MAX_ROTATION   4
+static igt_rotation_t get_rotation_angle(int rot)
+{
+   switch (rot) {
+   case 0:
+   return IGT_ROTATION_0;
+   break;
+   case 1:
+   return IGT_ROTATION_90;
+   break;
+   case 2:
+   return IGT_ROTATION_180;
+   break;
+   case 3:
+   return IGT_ROTATION_270;
+   break;
+   default:
+   igt_info("Unknown/Unsupported Rotation %d\n", rot);
+   return IGT_ROTATION_0;
+   }
+}
+
+#define MAX_TILING 4
+static uint64_t get_tiling(int tiling)
+{
+   switch (tiling) {
+   case 0:
+   return LOCAL_DRM_FORMAT_MOD_NONE;
+   break;
+   case 1:
+   return LOCAL_I915_FORMAT_MOD_X_TILED;
+   break;
+   case 2:
+   return LOCAL_I915_FORMAT_MOD_Y_TILED;
+   break;
+   case 3:
+   return LOCAL_I915_FORMAT_MOD_Yf_TILED;
+   break;
+   default:
+   igt_info("Unknown/Unsupported Tiling %d\n", tiling);
+   return LOCAL_DRM_FORMAT_MOD_NONE;
+   }
+}
+
 static void cleanup_crtc(data_t *data)
 {
int i;
 
+   igt_display_reset(>display);
igt_pipe_crc_free(data->pipe_crc);
data->pipe_crc = NULL;
 
@@ -71,7 +116,6 @@ static void prepare_crtc(data_t *data, igt_output_t *output, 
enum pipe pipe,
 
cleanup_crtc(data);
 
-   igt_display_reset(display);
igt_output_set_pipe(output, pipe);
 
/* create the pipe_crc object for this pipe */
@@ -104,6 +148,112 @@ static void prepare_crtc(data_t *data, igt_output_t 
*output, enum pipe pipe,
igt_display_commit2(display, COMMIT_ATOMIC);
 }
 
+static void paint_fb(data_t *d, struct igt_fb *fb)
+{
+   cairo_t *cr;
+
+   cr = igt_get_cairo_ctx(d->drm_fd, fb);
+   igt_paint_color(cr, 0, 0, fb->width, fb->height, 0.0, 1.0, 0.0);
+   igt_assert(cairo_status(cr) == 0);
+   cairo_destroy(cr);
+}
+
+static void check_scaling_pipe_plane_rot(data_t *d, igt_plane_t *plane,
+uint32_t pixel_format,
+uint64_t tiling, enum pipe pipe,
+igt_output_t *output,
+igt_rotation_t rot)
+{
+   igt_display_t *display = >display;
+   int width, height;
+   drmModeModeInfo *mode;
+
+   cleanup_crtc(d);
+
+   igt_output_set_pipe(output, pipe);
+   mode = igt_output_get_mode(output);
+
+   /* create buffer in the range of  min and max source side limit.*/
+   width = height = 9;
+   igt_create_fb(display->drm_fd, width, height,
+ pixel_format, tiling, >fb[0]);
+   paint_fb(d, >fb[0]);
+   igt_plane_set_fb(plane, >fb[0]);
+
+   /* Check min to full resolution upscaling */
+   igt_fb_set_position(>fb[0], plane, 0, 0);
+   igt_fb_set_size(>fb[0], plane, width, height);
+   igt_plane_set_position(plane, 0, 0);
+   igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+   igt_plane_set_rotation(plane, rot);
+   igt_display_commit2(display, COMMIT_ATOMIC);
+
+   igt_plane_set_fb(plane, NULL);
+   igt_plane_set_position(plane, 0, 0);
+}
+
+static void test_scaler_with_rotation_pipe(data_t *d, enum pipe pipe,
+  igt_output_t *output)
+{
+   igt_display_t *display = >display;
+   igt_plane_t *plane;
+
+   igt_output_set_pipe(output, pipe);
+   for_each_plane_on_pipe(display, pipe, plane) {
+
+   if (plane->type == DRM_PLANE_TYPE_CURSOR)
+   continue;
+
+   for (int i = 0; i < MAX_ROTATION; i++) {
+   igt_rotation_t rot = get_rotation_angle(i);
+   check_scaling_pipe_plane_rot(d, plane, 
DRM_FORMAT_XRGB,
+
LOCAL_I915_FORMAT_MOD_Y_TILED,
+ 

[Intel-gfx] [PATCH i-g-t v2 5/9] tests/kms_plane_scaling: Clean up tests to work better with igt_kms.

[Maarten Lankhorst]

The test only runs on gen9+, so we can safely replace all calls with
COMMIT_ATOMIC.

Also perform some cleanups by making fb an array, and cleaning up in
prepare_crtc. This way failed subtests won't cause failures in other
subtests.

Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 234 --
 1 file changed, 99 insertions(+), 135 deletions(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 624e20447780..44ff91d7738f 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -40,93 +40,68 @@ typedef struct {
 
int num_scalers;
 
-   struct igt_fb fb1;
-   struct igt_fb fb2;
-   struct igt_fb fb3;
-   int fb_id1;
-   int fb_id2;
-   int fb_id3;
-
+   struct igt_fb fb[3];
igt_plane_t *plane1;
igt_plane_t *plane2;
igt_plane_t *plane3;
-   igt_plane_t *plane4;
 } data_t;
 
 #define FILE_NAME   "1080p-left.png"
 
-static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
-   igt_plane_t *plane, drmModeModeInfo *mode, enum 
igt_commit_style s)
+static void cleanup_crtc(data_t *data)
 {
-   igt_display_t *display = >display;
-
-   igt_output_set_pipe(output, pipe);
+   int i;
 
-   /* create the pipe_crc object for this pipe */
igt_pipe_crc_free(data->pipe_crc);
-   data->pipe_crc = igt_pipe_crc_new(data->drm_fd, pipe, 
INTEL_PIPE_CRC_SOURCE_AUTO);
+   data->pipe_crc = NULL;
 
-   /* before allocating, free if any older fb */
-   if (data->fb_id1) {
-   igt_remove_fb(data->drm_fd, >fb1);
-   data->fb_id1 = 0;
-   }
+   for (i = 0; i < ARRAY_SIZE(data->fb); i++) {
+   if (!data->fb[i].fb_id)
+   continue;
 
-   /* allocate fb for plane 1 */
-   data->fb_id1 = igt_create_pattern_fb(data->drm_fd,
-mode->hdisplay, mode->vdisplay,
-DRM_FORMAT_XRGB,
-LOCAL_I915_FORMAT_MOD_X_TILED, /* 
tiled */
->fb1);
-   igt_assert(data->fb_id1);
-
-   /*
-* We always set the primary plane to actually enable the pipe as
-* there's no way (that works) to light up a pipe with only a sprite
-* plane enabled at the moment.
-*/
-   if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
-   igt_plane_t *primary;
-
-   primary = igt_output_get_plane_type(output, 
DRM_PLANE_TYPE_PRIMARY);
-   igt_plane_set_fb(primary, >fb1);
+   igt_remove_fb(data->drm_fd, >fb[i]);
+   data->fb[i].fb_id = 0;
}
-
-   igt_plane_set_fb(plane, >fb1);
-   igt_display_commit2(display, s);
 }
 
-static void cleanup_crtc(data_t *data, igt_output_t *output, igt_plane_t 
*plane)
+static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
+   igt_plane_t *plane, drmModeModeInfo *mode)
 {
igt_display_t *display = >display;
 
-   igt_pipe_crc_free(data->pipe_crc);
-   data->pipe_crc = NULL;
+   cleanup_crtc(data);
 
-   if (data->fb_id1) {
-   igt_remove_fb(data->drm_fd, >fb1);
-   data->fb_id1 = 0;
-   }
-   if (data->fb_id2) {
-   igt_remove_fb(data->drm_fd, >fb2);
-   data->fb_id2 = 0;
-   }
-   if (data->fb_id3) {
-   igt_remove_fb(data->drm_fd, >fb3);
-   data->fb_id3 = 0;
-   }
+   igt_display_reset(display);
+   igt_output_set_pipe(output, pipe);
+
+   /* create the pipe_crc object for this pipe */
+   data->pipe_crc = igt_pipe_crc_new(data->drm_fd, pipe, 
INTEL_PIPE_CRC_SOURCE_AUTO);
+
+   /* allocate fb for plane 1 */
+   igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
+ >fb[0]);
+
+   igt_plane_set_fb(plane, >fb[0]);
 
if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
igt_plane_t *primary;
+   int ret;
 
+   /* Do we succeed without enabling the primary plane? */
+   ret = igt_display_try_commit2(display, COMMIT_ATOMIC);
+   if (!ret)
+   return;
+
+   /*
+* Fallback: set the primary plane to actually enable the pipe.
+* Some drivers always require the primary plane to be enabled.
+*/
primary = igt_output_get_plane_type(output, 
DRM_PLANE_TYPE_PRIMARY);
-   igt_plane_set_fb(primary, NULL);
+   igt_plane_set_fb(primary, >fb[0]);
}
-
-   igt_plane_set_fb(plane, NULL);
-   

[Intel-gfx] [PATCH i-g-t v2 8/9] lib/igt_kms: Add more braces around macros

[Maarten Lankhorst]

The next patch wants to call for_each_pipe_with_valid_output
with *pipe and *output, this fails miserably without these braces.

Signed-off-by: Maarten Lankhorst 
---
 lib/igt_kms.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 1cf9422c0d12..85e9564adf34 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -430,8 +430,8 @@ static inline bool igt_output_is_connected(igt_output_t 
*output)
  */
 #define for_each_connected_output(display, output) \
for (int i__ = 0;  assert(igt_can_fail()), i__ < (display)->n_outputs; 
i__++)   \
-   for_each_if (((output = &(display)->outputs[i__]), \
- igt_output_is_connected(output)))
+   for_each_if output) = &(display)->outputs[i__]), \
+ igt_output_is_connected((output
 
 /**
  * for_each_pipe:
@@ -469,11 +469,11 @@ static inline bool igt_output_is_connected(igt_output_t 
*output)
  * will try every combination of @pipe and @output.
  */
 #define for_each_pipe_with_valid_output(display, pipe, output) \
-   for (int con__ = pipe = 0; \
-assert(igt_can_fail()), pipe < igt_display_get_n_pipes((display)) 
&& con__ < (display)->n_outputs; \
+   for (int con__ = (pipe) = 0; \
+assert(igt_can_fail()), (pipe) < 
igt_display_get_n_pipes((display)) && con__ < (display)->n_outputs; \
 con__ = (con__ + 1 < (display)->n_outputs) ? con__ + 1 : (pipe = 
pipe + 1, 0)) \
-   for_each_if (((output = &(display)->outputs[con__]), \
-igt_pipe_connector_valid(pipe, output)))
+   for_each_if output) = &(display)->outputs[con__]), \
+igt_pipe_connector_valid((pipe), (output
 
 /**
  * for_each_valid_output_on_pipe:
@@ -486,8 +486,8 @@ static inline bool igt_output_is_connected(igt_output_t 
*output)
  * happens.
  */
 #define for_each_valid_output_on_pipe(display, pipe, output) \
-   for_each_connected_output(display, output) \
-   for_each_if (igt_pipe_connector_valid(pipe, output))
+   for_each_connected_output((display), (output)) \
+   for_each_if (igt_pipe_connector_valid((pipe), (output)))
 
 #define for_each_plane_on_pipe(display, pipe, plane)   \
for (int j__ = 0; assert(igt_can_fail()), (plane) = 
&(display)->pipes[(pipe)].planes[j__], \
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 3/9] tests/kms_plane_scaling: Fix basic scaling test, v2.

[Maarten Lankhorst]

From: Mahesh Kumar 

PIPEC doesnt have 3rd plane in GEN9. So, we skip the
3rd plane related scaling test where 2nd OVERLAY
plane is not available.

Restricting downscaling to (9/10)x original size of the
image to avoid "Max pixel rate limitation" of the hardware.

Later patches in this series will cover corner cases of
scaling.

Changes since v1:
- Move out the code reshuffle to a separate commit. (Maarten)
  This makes it more clear what's fixed.

Signed-off-by: Mahesh Kumar 
Signed-off-by: Jyoti Yadav 
Signed-off-by: Vidya Srinivas 
Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 37e05158b968..5487f89e5149 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -231,7 +231,9 @@ test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, 
igt_output_t *output)
igt_fb_set_position(>fb2, d->plane2, 0, 0);
igt_fb_set_size(>fb2, d->plane2, d->fb2.width, d->fb2.height);
igt_plane_set_position(d->plane2, 10, 10);
-   igt_plane_set_size(d->plane2, 500, 500 * d->fb2.height/d->fb2.width);
+
+   /* Downscale (10/9)x of original image */
+   igt_plane_set_size(d->plane2, (d->fb2.width * 10)/9, (d->fb2.height * 
10)/9);
igt_display_commit2(display, COMMIT_UNIVERSAL);
 
if (primary_plane_scaling) {
@@ -247,6 +249,11 @@ test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, 
igt_output_t *output)
d->plane3 = igt_output_get_plane(output, 2);
igt_plane_set_fb(d->plane3, >fb3);
 
+   if(d->plane3->type == DRM_PLANE_TYPE_CURSOR) {
+   igt_debug("Plane-3 doesnt exist on pipe %s\n", 
kmstest_pipe_name(pipe));
+   goto cleanup;
+   }
+
/* 3rd plane windowed - no scaling */
igt_fb_set_position(>fb3, d->plane3, 100, 100);
igt_fb_set_size(>fb3, d->plane3, d->fb3.width-300, 
d->fb3.height-300);
@@ -280,6 +287,7 @@ test_plane_scaling_on_pipe(data_t *d, enum pipe pipe, 
igt_output_t *output)
igt_display_commit2(display, COMMIT_UNIVERSAL);
}
 
+cleanup:
/* back to single plane mode */
igt_plane_set_fb(d->plane2, NULL);
igt_plane_set_fb(d->plane3, NULL);
-- 
2.15.1

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[Intel-gfx] [PATCH i-g-t v2 1/9] tests/kms_plane: Run test for all supported pixel formats, v2.

[Maarten Lankhorst]

From: Mahesh Kumar 

This patch adds a subtest related to pixel format testing. The test
tries to create framebuffer with all supported pixel formats on every plane,
and tries to draw them using cairo and commits the same on display.

Changes since v1:
- Make the test more generic and try on all planes, including legacy cursor.

Signed-off-by: Mahesh Kumar 
Signed-off-by: Jyoti Yadav 
Signed-off-by: Vidya Srinivas 
Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane.c | 103 ++
 1 file changed, 103 insertions(+)

diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index 92bf67f1018c..9672763fe619 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -368,6 +368,105 @@ test_plane_panning(data_t *data, enum pipe pipe, unsigned 
int flags)
igt_skip_on(connected_outs == 0);
 }
 
+static bool can_draw(uint32_t drm_format)
+{
+   const uint32_t *drm_formats;
+   int format_count, i;
+
+   igt_get_all_cairo_formats(_formats, _count);
+
+   for (i = 0; i < format_count; i++)
+   if (drm_formats[i] == drm_format)
+   return true;
+
+   return false;
+}
+
+static void test_format_plane(data_t *data, enum pipe pipe,
+ igt_output_t *output, igt_plane_t *plane)
+{
+   igt_plane_t *primary;
+   struct igt_fb primary_fb, fb;
+   drmModeModeInfo *mode;
+   cairo_t *cr;
+   int i;
+   uint32_t format;
+   uint64_t width, height;
+
+   mode = igt_output_get_mode(output);
+   if (plane->type != DRM_PLANE_TYPE_CURSOR) {
+   width = mode->hdisplay;
+   height = mode->vdisplay;
+   } else {
+   if (!plane->drm_plane) {
+   igt_debug("Only legacy cursor ioctl supported, skipping 
cursor plane\n");
+   return;
+   }
+   do_or_die(drmGetCap(data->drm_fd, DRM_CAP_CURSOR_WIDTH, 
));
+   do_or_die(drmGetCap(data->drm_fd, DRM_CAP_CURSOR_HEIGHT, 
));
+   }
+
+   igt_debug("Testing connector %s on %s plane %s.%u\n",
+ igt_output_name(output), kmstest_plane_type_name(plane->type),
+ kmstest_pipe_name(pipe), plane->index);
+
+   igt_create_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE, 
_fb);
+
+   igt_output_set_pipe(output, pipe);
+   primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+   igt_plane_set_fb(primary, _fb);
+
+   igt_display_commit2(>display, data->display.is_atomic ? 
COMMIT_ATOMIC : COMMIT_LEGACY);
+
+   for (i = 0; i < plane->drm_plane->count_formats; i++) {
+   format = plane->drm_plane->formats[i];
+
+   if (!can_draw(format))
+   continue;
+
+   igt_debug("Testing format 0x%x on %s.%u\n",
+ format, kmstest_pipe_name(pipe), plane->index);
+
+   igt_create_fb(data->drm_fd, width, height,
+ format, LOCAL_DRM_FORMAT_MOD_NONE, );
+
+   cr = igt_get_cairo_ctx(data->drm_fd, );
+   igt_paint_color(cr, 0, 0, width, height,
+   0.0, 1.0, 0.0);
+   if (width >= 164 && height >= 164)
+   igt_paint_color(cr, 100, 100, 64, 64, 0.0, 0.0, 0.0);
+   igt_assert(cairo_status(cr) == 0);
+   cairo_destroy(cr);
+
+   igt_plane_set_fb(plane, );
+   igt_display_commit2(>display, COMMIT_UNIVERSAL);
+
+   igt_remove_fb(data->drm_fd, );
+   }
+
+   igt_plane_set_fb(primary, NULL);
+   igt_plane_set_fb(plane, NULL);
+   igt_remove_fb(data->drm_fd, _fb);
+}
+
+static void
+test_pixel_formats(data_t *data, enum pipe pipe)
+{
+   igt_output_t *output;
+
+   igt_display_require_output_on_pipe(>display, pipe);
+
+   for_each_valid_output_on_pipe(>display, pipe, output) {
+   igt_plane_t *plane;
+
+   for_each_plane_on_pipe(>display, pipe, plane)
+   test_format_plane(data, pipe, output, plane);
+
+   igt_output_set_pipe(output, PIPE_ANY);
+   }
+}
+
 static void
 run_tests_for_pipe_plane(data_t *data, enum pipe pipe)
 {
@@ -376,6 +475,10 @@ run_tests_for_pipe_plane(data_t *data, enum pipe pipe)
igt_require(data->display.pipes[pipe].n_planes > 0);
}
 
+   igt_subtest_f("pixel-format-pipe-%s-planes",
+ kmstest_pipe_name(pipe))
+   test_pixel_formats(data, pipe);
+
igt_subtest_f("plane-position-covered-pipe-%s-planes",
  kmstest_pipe_name(pipe))
test_plane_position(data, pipe, TEST_POSITION_FULLY_COVERED);
-- 
2.15.1