[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to override PWM backlight frequency and duty cycle (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Allow user to override PWM backlight frequency and duty cycle 
(rev2)
URL   : https://patchwork.freedesktop.org/series/36540/
State : success

== Summary ==

Series 36540v2 drm/i915: Allow user to override PWM backlight frequency and 
duty cycle
https://patchwork.freedesktop.org/api/1.0/series/36540/revisions/2/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:419s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:484s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:283s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:485s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:464s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:461s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:276s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:456s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:457s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:573s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:436s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:530s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:486s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:515s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:573s
fi-glk-dsi   total:288  pass:257  dwarn:0   dfail:0   fail:1   skip:30  
time:483s

bf4fa7c9c108a7c8f9a966f940d8df733b4a4b89 drm-tip: 2018y-01m-17d-07h-03m-28s UTC 
integration manifest
c412cd65075d drm/i915: Allow user to override PWM backlight frequency and duty 
cycle

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7691/issues.html
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[Intel-gfx] [PATCH] drm/i915: Allow user to override PWM backlight frequency and duty cycle

[Alex Ivanov]

Fixed to merge against drm-tip branch

Signed-off-by: Alex Ivanov 
---
 drivers/gpu/drm/i915/i915_params.c |  6 ++
 drivers/gpu/drm/i915/i915_params.h |  2 ++
 drivers/gpu/drm/i915/intel_panel.c | 17 +
 3 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index b5f3eb4fa8a3..2a7b0c20f1d0 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -175,6 +175,12 @@ i915_param_named(enable_dpcd_backlight, bool, 0600,
 i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host 
support(default:false)");
 
+i915_param_named_unsafe(backlight_freq, uint, 0400,
+   "Override PWM backlight frequency (set in Hz, 0=ignore [default])");
+
+i915_param_named_unsafe(backlight_min_level, uint, 0400,
+   "Override PWM backlight minimum level (duty cycle, 0=ignore 
[default])");
+
 static __always_inline void _print_param(struct drm_printer *p,
 const char *name,
 const char *type,
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c96360398072..5e2c077c6f2c 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -55,6 +55,8 @@ struct drm_printer;
param(int, edp_vswing, 0) \
param(int, reset, 2) \
param(unsigned int, inject_load_failure, 0) \
+   param(unsigned int, backlight_freq, 0) \
+   param(unsigned int, backlight_min_level, 0) \
/* leave bools at the end to not create holes */ \
param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
param(bool, enable_cmd_parser, true) \
diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index fa6831f8c004..eb5f0665b5f9 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1479,6 +1479,12 @@ static u32 get_backlight_min_vbt(struct intel_connector 
*connector)
 
WARN_ON(panel->backlight.max == 0);
 
+   if (i915_modparams.backlight_min_level) {
+   DRM_DEBUG_KMS("Override backlight duty cycle %u\n",
+   
i915_modparams.backlight_min_level);
+   return i915_modparams.backlight_min_level;
+   }
+
/*
 * XXX: If the vbt value is 255, it makes min equal to max, which leads
 * to problems. There are such machines out there. Either our
@@ -1795,6 +1801,7 @@ int intel_panel_setup_backlight(struct drm_connector 
*connector, enum pipe pipe)
struct intel_connector *intel_connector = to_intel_connector(connector);
struct intel_panel *panel = _connector->panel;
int ret;
+   u32 pwm;
 
if (!dev_priv->vbt.backlight.present) {
if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
@@ -1812,6 +1819,16 @@ int intel_panel_setup_backlight(struct drm_connector 
*connector, enum pipe pipe)
/* set level and max in panel struct */
mutex_lock(_priv->backlight_lock);
ret = panel->backlight.setup(intel_connector, pipe);
+   if (i915_modparams.backlight_freq) {
+   if (panel->backlight.hz_to_pwm &&
+   (pwm = 
panel->backlight.hz_to_pwm(intel_connector, i915_modparams.backlight_freq))) {
+   panel->backlight.max = pwm;
+   DRM_DEBUG_KMS("Override backlight frequency %u Hz\n",
+   
i915_modparams.backlight_freq);
+   } else {
+   DRM_DEBUG_KMS("failed to override backlight 
frequency\n");
+   }
+   }
mutex_unlock(_priv->backlight_lock);
 
if (ret) {
-- 
2.15.1

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Re: [Intel-gfx] [PATCH i-g-t v13] tests/kms_frontbuffer_tracking: Including DRRS test coverage

[Ramalingam C]

Summary from IRC discussions with Rodrigo:

drrs_disable will get called on all test setups(including the drrs 
non-capable). So we cant fail/skip the sub_test based on the return 
value from drrs_set(0)


drrs_enable will get called only when the test setup is capable of drrs. 
And also after the request for enabling drrs, drrs state is verified 
through i915_drrs_status.


So functionally it is not necessary to validate the debugfs_write return 
value. But no harm in double checking the error state for drrs_set(1). 
Rodrigo, as per above understanding i have mentioned the expected deltas 
inline. If you confirm, we will submit the next version. Thanks for the 
time.



On Wednesday 10 January 2018 08:17 PM, Lohith BS wrote:

Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's
refresh rate to the lowest vrefresh supported by panel, when frame is
not flipped for more than a Sec.

In kernel, DRRS uses the front buffer tracking infrastructure.
Hence DRRS test coverage is added along with other frontbuffer tracking
based features such as FBC and PSR tests.

Here, we are testing DRRS with other features in all possible
combinations, in all required test cases, to capture any possible
regression.

v2: Addressed the comments and suggestions from Vlad, Marius.
 The signoff details from the earlier work are also included.

v3: Modified vblank rate calculation by using reply-sequence,
 provided by drmWaitVBlank, as suggested by Chris Wilson.

v4: As suggested from Chris Wilson and Daniel Vetter
 1) Avoided using pthread for calculating vblank refresh rate,
instead used drmWaitVBlank reply sequence.
 2) Avoided using kernel-specific info like transitional delays,
instead polling mechanism with timeout is used.
 3) Included edp-DRRS as a subtest in kms_frontbuffer_tracking.c,
instead of having a separate test.

v5: This patch adds DRRS as a new feature in the
 kms_frontbuffer_tracking IGT.
 DRRS switch to lower vrefresh rate is tested at slow-draw subtest.

 Note:
 1) Currently kernel doesn't have support to enable and disable
the DRRS feature dynamically(as in case of PSR). Hence if the
panel supports DRRS it will be enabled by default.

 This is in continuation of last patch
"https://patchwork.freedesktop.org/patch/162726/;

v6: This patch adds runtime enable and disable feature for testing DRRS

v7: This patch adds runtime enable and disable feature for testing DRRS
 through debugfs entry "i915_drrs_ctl".

v8: Commit message is updated to reflect current implementation.

v9: Addressed Paulo Zanoni comments.
 Check for DRRS_LOW at tests with OFFSCREEN + FBS_INDIVIDUAL.

v10: Corrected DRRS state expectation in suspend related subtests.

v11: Removing the global flag is_psr_drrs_combo [Rodrigo].

v12: Rewriting the DRRS inactive deduction [Rodrigo].

v13: En/Dis-able DRRS only when DRRS is capable on the setup.

Signed-off-by: Lohith BS 
Signed-off-by: aknautiy 
---
  tests/kms_frontbuffer_tracking.c | 172 +--
  1 file changed, 164 insertions(+), 8 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1601cab..6b2299b 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -34,7 +34,7 @@
  
  
  IGT_TEST_DESCRIPTION("Test the Kernel's frontbuffer tracking mechanism and "

-"its related features: FBC and PSR");
+"its related features: FBC, PSR and DRRS");
  
  /*

   * One of the aspects of this test is that, for every subtest, we try 
different
@@ -105,8 +105,9 @@ struct test_mode {
FEATURE_NONE  = 0,
FEATURE_FBC   = 1,
FEATURE_PSR   = 2,
-   FEATURE_COUNT = 4,
-   FEATURE_DEFAULT = 4,
+   FEATURE_DRRS  = 4,
+   FEATURE_COUNT = 8,
+   FEATURE_DEFAULT = 8,
} feature;
  
  	/* Possible pixel formats. We just use FORMAT_DEFAULT for most tests and

@@ -182,6 +183,13 @@ struct {
.can_test = false,
  };
  
+#define MAX_DRRS_STATUS_BUF_LEN 256

+
+struct {
+   bool can_test;
+} drrs = {
+   .can_test = false,
+};
  
  #define SINK_CRC_SIZE 12

  typedef struct {
@@ -790,7 +798,14 @@ static void __debugfs_read(const char *param, char *buf, 
int len)
buf[len] = '\0';
  }
  
+static void __debugfs_write(const char *param, char *buf, int len)

+{
+   igt_assert_eq(igt_sysfs_write(drm.debugfs, param, buf, len - 1),
+ len - 1);
+}
+

redefining the __debugfs_write() as below:

static int __debugfs_write(const char *param, char *buf, int len)
{
return igt_sysfs_write(drm.debugfs, param, buf, len - 1);
}


  #define debugfs_read(p, arr) __debugfs_read(p, arr, sizeof(arr))
+#define debugfs_write(p, arr) __debugfs_write(p, arr, sizeof(arr))
  
  static 

[Intel-gfx] [PULL] gvt-next fixes for 4.16

[Zhenyu Wang]

Hi,

Here's queued gvt-next fixes for 4.16-rc1. Mostly with regression
fixes on vGPU display dmabuf, mmio switch and other misc changes,
details below.

thanks
--
The following changes since commit 4fafba2d73fcaf1b433c26e753a98ad4b231754a:

  drm/i915/gvt: move write protect handler out of mmio emulation function 
(2017-12-22 16:33:50 +0800)

are available in the Git repository at:

  https://github.com/intel/gvt-linux.git tags/gvt-next-2018-01-17

for you to fetch changes up to 0eb582541cfd7a17b6fcf9282c966c0e59efd02f:

  drm/i915/gvt: cancel scheduler timer when no vGPU exists (2018-01-16 10:23:42 
+0800)


gvt-next-2018-01-17:

- mmio switch regression fix (Xiong)
- dmabuf reference fix (Tina)
- one I915_NUM_ENGINES usage fix impacted by new hw enabling change (Michel)
- sanity check for valid gfn when shadow (Henry)
- keep gvt service thread quiet without vGPU (Zhenyu)


Hang Yuan (1):
  drm/i915/gvt: validate gfn before set shadow page entry

Michel Thierry (1):
  drm/i915/gvt: Do not use I915_NUM_ENGINES to iterate over the mocs regs 
array

Pei Zhang (1):
  drm/i915/gvt: add PLANE_KEYMAX regs to mmio track list

Tina Zhang (1):
  drm/i915/gvt: Keep obj->dma_buf link NULL during exporting

Xiong Zhang (1):
  drm/i915/gvt: Fix gen8/9_render_mmio_list[0] don't take effect

Zhenyu Wang (2):
  drm/i915/gvt: cancel virtual vblank timer when no vGPU exists
  drm/i915/gvt: cancel scheduler timer when no vGPU exists

 drivers/gpu/drm/i915/gvt/dmabuf.c   |  1 -
 drivers/gpu/drm/i915/gvt/gtt.c  | 24 +++-
 drivers/gpu/drm/i915/gvt/handlers.c |  3 +++
 drivers/gpu/drm/i915/gvt/hypercall.h|  1 +
 drivers/gpu/drm/i915/gvt/kvmgt.c| 16 
 drivers/gpu/drm/i915/gvt/mmio_context.c | 10 +-
 drivers/gpu/drm/i915/gvt/mpt.h  | 17 +
 drivers/gpu/drm/i915/gvt/sched_policy.c |  7 +++
 drivers/gpu/drm/i915/gvt/vgpu.c |  2 ++
 9 files changed, 70 insertions(+), 11 deletions(-)


-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827


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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Don't enable GuC when vGPU is active

[Du, Changbin]

On Tue, Jan 16, 2018 at 11:17:39AM +0100, Michal Wajdeczko wrote:
> On Tue, 16 Jan 2018 10:53:47 +0100, Joonas Lahtinen
>  wrote:
> 
> > On Mon, 2018-01-15 at 13:10 +0200, Tomi Sarvela wrote:
> > > On 15/01/18 12:28, Zhenyu Wang wrote:
> > > > On 2018.01.15 12:07:28 +0200, Joonas Lahtinen wrote:
> > > > > On Fri, 2018-01-12 at 14:08 +0800, Du, Changbin wrote:
> > > > > > On Fri, Jan 12, 2018 at 11:32:30AM +0530, Sagar Arun Kamble wrote:
> > > > > > > Is skl-gvtdvm not having vGPU active?
> > > > > > >
> > > > > > > It has flag X86_FEATURE_HYPERVISOR set however it might be
> > > set on host too
> > > > > > > so relying intel_vgpu_active().
> > > > > > >
> > > > > >
> > > > > > Do you mean flag X86_FEATURE_HYPERVISOR is set on host, too?
> > > This is weird since this
> > > > > > flag indicates the OS is running on a hypervisor.
> > > > >
> > > > > + CI folks and Zhenyu
> > > > >
> > > > > Somehow, magically, the virtual machine seems to starts skipping all
> > > > > tests when GuC is disabled?
> > > > >
> > > > > Has somebody actually validated that the tests results are valid for
> > > > > the virtual machine? Or is this a one-off CI quirk?
> > > >
> > > > Are these tests really run in VM with GVT-g enabled on host?
> > > 
> > > These tests are ran on VM running on GVT-d (as name implies), not GVT-g.
> > 
> > I don't still understand how explicitly disabling GuC could make all
> > the tests skip on a machine that didn't use GuC to begin with. There
> > must be something wrong in the initialization code.
> > 
> > That intel_vgpu_active() check by my logic should not trigger in GVT-d
> > (because we don't have virtual GPU, we have the real deal, just without
> > stolen etc.), so I'm bit baffled.
> 
> True. This intel_vgpu_active() check added by Sagar is not active in these
> scenarios so we keep turn on GuC on that platform (as default from auto)
> 
> - param(int, enable_guc, 0) \
> + param(int, enable_guc, -1) \
> 
> [drm:intel_uc_sanitize_options [i915]] enable_guc=3 (submission:yes huc:yes)
> 
> but since i915_memcpy_from_wc() check still fails due to running under
> hypervisor (introduced by "drm/i915: Do not enable movntdqa optimization
> in hypervisor guest"), initialization of the GuC log fails
> 
> WARN_ON(!i915_memcpy_from_wc(((void *)0), ((void *)0), 0))
> WARNING: CPU: 0 PID: 228 at drivers/gpu/drm/i915/intel_guc_log.c:527
> intel_guc_log_create
> 
> and that is treated as driver load error (as we no longer support silent
> fallback from GuC to execlist, if GuC was selected using auto(-1) or
> explicit
> load(1) modparam option.
> 
> On the other mail thread there was proposal to make GuC log optional in
> case of running under hypervisor and disable it, but in my opinion it is
> not a solution but just short term fix, as we want to keep GuC log enabled
> since it works as is with other hypervisors.
>
> Michal

To enable Guc logging on hypervisor guest, I think the correct solution is to
fallback to memcpy() after i915_has_memcpy_from_wc(). At least for kvm, it needs
this change considering GPU passthrough.

Thanks,
Changbin Du


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[Intel-gfx] ✓ Fi.CI.IGT: success for tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation (rev3)

[Patchwork]

== Series Details ==

Series: tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation 
(rev3)
URL   : https://patchwork.freedesktop.org/series/35101/
State : success

== Summary ==

Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218 +1
Test gem_softpin:
Subgroup noreloc-s3:
pass   -> SKIP   (shard-snb) fdo#103375
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hswtotal:2665 pass:1514 dwarn:1   dfail:0   fail:10  skip:1139 
time:8980s
shard-snbtotal:2729 pass:1318 dwarn:1   dfail:0   fail:10  skip:1400 
time:7938s
Blacklisted hosts:
shard-apltotal:2657 pass:1646 dwarn:1   dfail:0   fail:24  skip:984 
time:12957s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_787/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait (rev5)

[Patchwork]

== Series Details ==

Series: igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait 
(rev5)
URL   : https://patchwork.freedesktop.org/series/35699/
State : success

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> SKIP   (shard-hsw) fdo#103375
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218

shard-hswtotal:2729 pass:1548 dwarn:1   dfail:0   fail:10  skip:1170 
time:9083s
shard-snbtotal:2729 pass:1319 dwarn:1   dfail:0   fail:10  skip:1399 
time:7874s
Blacklisted hosts:
shard-apltotal:2707 pass:1682 dwarn:1   dfail:0   fail:22  skip:1001 
time:13354s
shard-kbltotal:2729 pass:1826 dwarn:1   dfail:0   fail:24  skip:878 
time:10662s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_786/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Do not WARN_ON with small framebuffers.

[Rodrigo Vivi]

On Tue, Jan 16, 2018 at 03:53:31PM +, Maarten Lankhorst wrote:
> It's perfectly legal to create a fb with stride < 512, and one of
> the kms_plane_scaling subtests creates a very small fb.
> 
> Downgrade the WARN_ON to a simple check check, and because this
> function is potentially called on every atomic update/pageflip,
> downgrade the other WARN_ON to a WARN_ON_ONCE, and do the right
> thing here.
> 
> Cc: Paulo Zanoni 
> Signed-off-by: Maarten Lankhorst 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/intel_fbc.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c 
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 7a64405f4514..c4e924e41db3 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -668,11 +668,13 @@ void intel_fbc_cleanup_cfb(struct drm_i915_private 
> *dev_priv)
>  static bool stride_is_valid(struct drm_i915_private *dev_priv,
>   unsigned int stride)
>  {
> - /* These should have been caught earlier. */
> - WARN_ON(stride < 512);
> - WARN_ON((stride & (64 - 1)) != 0);
> + /* This should have been caught earlier. */
> + if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
> + return false;
>  
>   /* Below are the additional FBC restrictions. */
> + if (stride < 512)
> + return false;
>  
>   if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
>   return stride == 4096 || stride == 8192;
> -- 
> 2.15.1
> 
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36567/
State : success

== Summary ==

Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> SKIP   (shard-snb) fdo#103880 +1
pass   -> SKIP   (shard-hsw) fdo#103540
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218

fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218

shard-hswtotal:2729 pass:1548 dwarn:1   dfail:0   fail:10  skip:1170 
time:9106s
shard-snbtotal:2729 pass:1317 dwarn:1   dfail:0   fail:10  skip:1401 
time:7855s
Blacklisted hosts:
shard-apltotal:2729 pass:1698 dwarn:1   dfail:0   fail:23  skip:1006 
time:13700s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7690/shards.html
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Re: [Intel-gfx] [PATCH v7 6/6] drm/i915: expose rcs topology through query uAPI

[Chris Wilson]

Quoting Lionel Landwerlin (2018-01-16 19:18:24)
> diff --git a/drivers/gpu/drm/i915/i915_query.c 
> b/drivers/gpu/drm/i915/i915_query.c
> index 51736af7f573..038f292e1f2a 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -25,8 +25,102 @@
>  #include "i915_drv.h"
>  #include 
>  
> +static int copy_query_data(struct drm_i915_query_item *query_item,
> +  const void *item_ptr, u32 item_length,
> +  const void *data_ptr, u32 data_length)
> +{
> +   u32 total_length = item_length + data_length;

BUG_ON(add_overflows(item_length, data_length)) ?

> +
> +   if (query_item->length == 0)
> +   return total_length;
> +
> +   if (query_item->length < total_length)
> +   return -EINVAL;
> +
> +   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +item_ptr, item_length))
> +   return -EFAULT;
> +
> +   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
> +data_ptr, data_length))
> +   return -EFAULT;

Unchecked overflow (data_ptr + item_length) here.

if (!access_ok(VERIFY_WRITE, u64_to_user_ptr(query_item->data_ptr), 
total_length))
return -EFAULT;

Would cover it, and then if you wanted you could then use
__copy_to_user().

> +
> +   return total_length;
> +}
> +
> +static int query_slice_info(struct drm_i915_private *dev_priv,
> +   struct drm_i915_query_item *query_item)
> +{
> +   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
> +   struct drm_i915_query_slice_info slice_info;
> +
> +   if (sseu->max_slices == 0)
> +   return -ENODEV;

Brr. This would then abort all queries not just this one, that doesn't
seem very user friendly. EFAULT are definite abort, can't continue, this
is just factual.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t v3] tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation

[Michel Thierry]

On 1/16/2018 12:56 PM, Antonio Argenziano wrote:

The test expected IOCTL 'I915_GET_RESET_STATS' would return an error
when not root. That is no longer true in the driver since commit
4c9c0d09741d ("drm/i915: Fix retrieval of hangcheck stats") and therefore
the test was incorrectly failing.

v2:
- Add the commit that changed the behaviour in the Driver to the
  commit message. (Michel)

v3:
- Reuse get_reset_count instead of implementing a new function.
  (Michel)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Chris Wilson 
Signed-off-by: Antonio Argenziano 
---
  tests/gem_reset_stats.c | 14 ++
  1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index edc40767..17a9b648 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -605,10 +605,7 @@ static void test_reset_count(const struct 
intel_execution_engine *e,
  
  		c2 = get_reset_count(fd, ctx);
  
-		if (ctx == 0)

-   igt_assert(c2 == -EPERM);
-   else
-   igt_assert(c2 == 0);
+   igt_assert(c2 == 0);
}
  
  	igt_waitchildren();

@@ -644,10 +641,11 @@ static void _check_param_ctx(const int fd, const int ctx, 
const cap_t cap)
const uint32_t bad = rand() + 1;
  
  	if (ctx == 0) {

-   if (cap == root)
-   igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
-   else
-   igt_assert_eq(_test_params(fd, ctx, 0, 0), -EPERM);
+   igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
+
+   if (cap != root) {
+   igt_assert(get_reset_count(fd, ctx) == 0);
+   }
}
  
  	igt_assert_eq(_test_params(fd, ctx, 0, bad), -EINVAL);




This matches the driver's current behavior, which is better than testing 
for something that is no longer true. Based on that,


Reviewed-by: Michel Thierry 
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation (rev3)

[Patchwork]

== Series Details ==

Series: tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation 
(rev3)
URL   : https://patchwork.freedesktop.org/series/35101/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
5f5b4a65e672bd10a4422cc1cb3c466659c52db8 igt/gem_linear_blits: Compute GTT size 
using 4G limit

with latest DRM-Tip kernel build CI_DRM_3636
a0ca279440c8 drm-tip: 2018y-01m-16d-10h-49m-51s UTC integration manifest

No testlist changes.

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1

fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:426s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:492s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:283s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:472s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:464s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:278s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:513s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:460s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:582s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:513s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:481s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:525s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:572s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:478s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_787/issues.html
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Re: [Intel-gfx] [PATCH i-g-t 2/2] tests: add i915 query tests

[Chris Wilson]

Quoting Chris Wilson (2018-01-16 21:34:34)
> Quoting Lionel Landwerlin (2018-01-16 16:07:28)
> > Signed-off-by: Lionel Landwerlin 
> > ---
> >  tests/Makefile.sources |   1 +
> >  tests/meson.build  |   1 +
> >  tests/query.c  | 268 
> > +
> >  3 files changed, 270 insertions(+)
> >  create mode 100644 tests/query.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index e4e06d01..390cc82b 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -227,6 +227,7 @@ TESTS_progs = \
> > prime_self_import \
> > prime_udl \
> > prime_vgem \
> > +   query \
> > sw_sync \
> > syncobj_basic \
> > syncobj_wait \
> > diff --git a/tests/meson.build b/tests/meson.build
> > index 4c4bee1d..70df38f3 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -204,6 +204,7 @@ test_progs = [
> > 'prime_self_import',
> > 'prime_udl',
> > 'prime_vgem',
> > +   'query',
> > 'sw_sync',
> > 'syncobj_basic',
> > 'syncobj_wait',
> > diff --git a/tests/query.c b/tests/query.c
> > new file mode 100644
> > index ..cb5aedd4
> > --- /dev/null
> > +++ b/tests/query.c
> > @@ -0,0 +1,268 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the 
> > "Software"),
> > + * to deal in the Software without restriction, including without 
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the 
> > next
> > + * paragraph) shall be included in all copies or substantial portions of 
> > the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
> > OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> > DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include "igt.h"
> > +
> > +IGT_TEST_DESCRIPTION("Testing the query uAPI.");
> > +
> > +static bool has_query_supports(int fd)
> > +{
> > +   struct drm_i915_query query = {};
> > +
> > +   return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, ) == 0;
> > +}
> > +
> > +static void test_query_garbage(int fd)
> > +{
> > +   struct drm_i915_query query;
> > +   struct drm_i915_query_item items[2];
> > +
> > +   memset(, 0, sizeof(query));
> > +   query.num_items = 1;
> > +   query.items_ptr = 0x;
> 
> That might be legal on 64b. I think you mean -1.
> 
> For bonus points. .items_ptr = - num_items * sizeof(query) and variable
> number of items.

There's also a fun one where you

query.items_ptr = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
igt_assert(__i915_query(fd, ) == 0);
munmap(query.items_ptr, 4096);
igt_assert(__i915_query(fd, ) == -EFAULT);

Adjust for compilation :)
-Chris
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Re: [Intel-gfx] [PATCH i-g-t 2/2] tests: add i915 query tests

[Chris Wilson]

Quoting Lionel Landwerlin (2018-01-16 16:07:28)
> Signed-off-by: Lionel Landwerlin 
> ---
>  tests/Makefile.sources |   1 +
>  tests/meson.build  |   1 +
>  tests/query.c  | 268 
> +
>  3 files changed, 270 insertions(+)
>  create mode 100644 tests/query.c
> 
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index e4e06d01..390cc82b 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -227,6 +227,7 @@ TESTS_progs = \
> prime_self_import \
> prime_udl \
> prime_vgem \
> +   query \
> sw_sync \
> syncobj_basic \
> syncobj_wait \
> diff --git a/tests/meson.build b/tests/meson.build
> index 4c4bee1d..70df38f3 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -204,6 +204,7 @@ test_progs = [
> 'prime_self_import',
> 'prime_udl',
> 'prime_vgem',
> +   'query',
> 'sw_sync',
> 'syncobj_basic',
> 'syncobj_wait',
> diff --git a/tests/query.c b/tests/query.c
> new file mode 100644
> index ..cb5aedd4
> --- /dev/null
> +++ b/tests/query.c
> @@ -0,0 +1,268 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "igt.h"
> +
> +IGT_TEST_DESCRIPTION("Testing the query uAPI.");
> +
> +static bool has_query_supports(int fd)
> +{
> +   struct drm_i915_query query = {};
> +
> +   return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, ) == 0;
> +}
> +
> +static void test_query_garbage(int fd)
> +{
> +   struct drm_i915_query query;
> +   struct drm_i915_query_item items[2];
> +
> +   memset(, 0, sizeof(query));
> +   query.num_items = 1;
> +   query.items_ptr = 0x;

That might be legal on 64b. I think you mean -1.

For bonus points. .items_ptr = - num_items * sizeof(query) and variable
number of items.

> +   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EFAULT);

do_ioctl_err() you never want to see the error message.

int __i915_query(int fd, struct drm_i915_query *q); /* returns err */
void i915_query(int fd, struct drm_i915_query *q); /* asserts success */

> +
> +   memset(, 0, sizeof(query));
> +   query.num_items = 1;
> +   query.items_ptr = 0;
> +   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EFAULT);
> +
> +   memset(, 0, sizeof(query));
> +   query.num_items = 2;
> +   query.items_ptr = (uintptr_t) items;

.items_ptr = to_user_pointer(item);

Just reads nicer.

Also check overflow of num_items * items_ptr. So num_items = (INT_MAX,
UINT_MAX, LONG_MAX, ULONG_MAX etc) / sizeof(query) + 1.

> +   memset(items, 0, sizeof(items));
> +   items[0].query_id = 0x;
> +   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EINVAL);
> +
> +   memset(, 0, sizeof(query));
> +   query.num_items = 2;
> +   query.items_ptr = (uintptr_t) items;
> +   memset(items, 0, sizeof(items));
> +   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EINVAL);
> +
> +   memset(, 0, sizeof(query));
> +   query.num_items = 2;
> +   query.items_ptr = (uintptr_t) items;
> +   memset(items, 0, sizeof(items));
> +   items[0].query_id = DRM_I915_QUERY_SLICE_INFO;
> +   items[0].length = 0x;
> +   items[1].query_id = DRM_I915_QUERY_SUBSLICE_INFO;
> +   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EINVAL);
> +}
> +
> +static bool query_topology_supported(int fd)
> +{
> +   struct drm_i915_query query;
> +   struct drm_i915_query_item item;
> +
> +   memset(, 0, sizeof(query));
> +   query.num_items = 1;
> +   query.items_ptr = (uintptr_t) 
> +
> +   memset(, 0, sizeof(item));
> +   item.query_id = DRM_I915_QUERY_SLICE_INFO;

struct drm_i915_query_item item = {
.query_id = 

Re: [Intel-gfx] [PATCH 1/5] drm/vblank: Fix return type for drm_vblank_count()

[Pandiyan, Dhinakaran]

On Mon, 2018-01-15 at 10:38 +0100, Daniel Vetter wrote:
> On Fri, Jan 12, 2018 at 01:57:03PM -0800, Dhinakaran Pandiyan wrote:
> > drm_vblank_count() has a u32 type returning what is a 64-bit vblank count.
> > The effect of this is when drm_wait_vblank_ioctl() tries to widen the user
> > space requested vblank sequence using this clipped 32-bit count(when the
> > value is >= 2^32) as reference, the requested sequence remains a 32-bit
> > value and gets queued like that. However, the code that checks if the
> > requested sequence has passed compares this against the 64-bit vblank
> > count.
> > 
> > Cc: Keith Packard 
> > Cc: Michel Dänzer 
> > Cc: Daniel Vetter 
> > Signed-off-by: Dhinakaran Pandiyan 
> 
> Sounds like the 64bit widening wasn't all that well tested ... do we have
> an igt for this? Iirc the base igt was merged already.

I don't see anything that would particularly trigger this condition
i.e., vblank->count > 2^32 in the IGTs. We'll need to implement
something to force set a very large vblank->count and then request a
vblank sequence.




> -Daniel
> 
> > ---
> >  drivers/gpu/drm/drm_vblank.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
> > index 32d9bcf5be7f..768a8e44d99b 100644
> > --- a/drivers/gpu/drm/drm_vblank.c
> > +++ b/drivers/gpu/drm/drm_vblank.c
> > @@ -271,7 +271,7 @@ static void drm_update_vblank_count(struct drm_device 
> > *dev, unsigned int pipe,
> > store_vblank(dev, pipe, diff, t_vblank, cur_vblank);
> >  }
> >  
> > -static u32 drm_vblank_count(struct drm_device *dev, unsigned int pipe)
> > +static u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe)
> >  {
> > struct drm_vblank_crtc *vblank = >vblank[pipe];
> >  
> > -- 
> > 2.11.0
> > 
> 
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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait (rev5)

[Patchwork]

== Series Details ==

Series: igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait 
(rev5)
URL   : https://patchwork.freedesktop.org/series/35699/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
5f5b4a65e672bd10a4422cc1cb3c466659c52db8 igt/gem_linear_blits: Compute GTT size 
using 4G limit

with latest DRM-Tip kernel build CI_DRM_3636
a0ca279440c8 drm-tip: 2018y-01m-16d-10h-49m-51s UTC integration manifest

No testlist changes.

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> INCOMPLETE (fi-bdw-5557u) fdo#104162

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162

fi-bdw-5557u total:109  pass:105  dwarn:0   dfail:0   fail:0   skip:3  
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:491s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:283s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:471s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:416s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:458s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:495s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:517s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:591s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:532s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:487s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:436s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:527s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:574s
fi-glk-dsi   total:288  pass:189  dwarn:1   dfail:4   fail:0   skip:94  
time:402s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_786/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] include: bump drm uAPI headers

[Patchwork]

== Series Details ==

Series: series starting with [1/2] include: bump drm uAPI headers
URL   : https://patchwork.freedesktop.org/series/36561/
State : warning

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Subgroup vblank-vs-suspend-interruptible:
pass   -> SKIP   (shard-hsw) fdo#100368
Test kms_draw_crc:
Subgroup draw-method-xrgb-render-xtiled:
pass   -> SKIP   (shard-snb)
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252 +1

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2733 pass:1547 dwarn:1   dfail:0   fail:11  skip:1174 
time:8973s
shard-snbtotal:2733 pass:1318 dwarn:1   dfail:0   fail:10  skip:1404 
time:7859s
Blacklisted hosts:
shard-apltotal:2733 pass:1702 dwarn:1   dfail:0   fail:25  skip:1005 
time:13915s
shard-kbltotal:2638 pass:1724 dwarn:33  dfail:0   fail:23  skip:857 
time:10304s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_785/shards.html
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[Intel-gfx] [PATCH i-g-t v3] tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation

[Antonio Argenziano]

The test expected IOCTL 'I915_GET_RESET_STATS' would return an error
when not root. That is no longer true in the driver since commit
4c9c0d09741d ("drm/i915: Fix retrieval of hangcheck stats") and therefore
the test was incorrectly failing.

v2:
- Add the commit that changed the behaviour in the Driver to the
  commit message. (Michel)

v3:
- Reuse get_reset_count instead of implementing a new function.
  (Michel)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Chris Wilson 
Signed-off-by: Antonio Argenziano 
---
 tests/gem_reset_stats.c | 14 ++
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index edc40767..17a9b648 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -605,10 +605,7 @@ static void test_reset_count(const struct 
intel_execution_engine *e,
 
c2 = get_reset_count(fd, ctx);
 
-   if (ctx == 0)
-   igt_assert(c2 == -EPERM);
-   else
-   igt_assert(c2 == 0);
+   igt_assert(c2 == 0);
}
 
igt_waitchildren();
@@ -644,10 +641,11 @@ static void _check_param_ctx(const int fd, const int ctx, 
const cap_t cap)
const uint32_t bad = rand() + 1;
 
if (ctx == 0) {
-   if (cap == root)
-   igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
-   else
-   igt_assert_eq(_test_params(fd, ctx, 0, 0), -EPERM);
+   igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
+
+   if (cap != root) {
+   igt_assert(get_reset_count(fd, ctx) == 0);
+   }
}
 
igt_assert_eq(_test_params(fd, ctx, 0, bad), -EINVAL);
-- 
2.14.2

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[Intel-gfx] [PATCH igt] igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 tests/kms_frontbuffer_tracking.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1601cab45..f35e40593 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -792,11 +792,12 @@ static void __debugfs_read(const char *param, char *buf, 
int len)
 
 #define debugfs_read(p, arr) __debugfs_read(p, arr, sizeof(arr))
 
-static bool fbc_is_enabled(void)
+static bool fbc_is_enabled(int lvl)
 {
char buf[128];
 
debugfs_read("i915_fbc_status", buf);
+   igt_log(IGT_LOG_DOMAIN, lvl, "fbc_is_enabled()?\n%s", buf);
return strstr(buf, "FBC enabled\n");
 }
 
@@ -927,7 +928,7 @@ static bool fbc_stride_not_supported(void)
 
 static bool fbc_wait_until_enabled(void)
 {
-   return igt_wait(fbc_is_enabled(), 2000, 1);
+   return igt_wait(fbc_is_enabled(IGT_LOG_DEBUG), 2000, 1);
 }
 
 static bool psr_wait_until_enabled(void)
@@ -1710,8 +1711,8 @@ static void do_status_assertions(int flags)
igt_require(!fbc_not_enough_stolen());
igt_require(!fbc_stride_not_supported());
if (!fbc_wait_until_enabled()) {
-   fbc_print_status();
-   igt_assert_f(fbc_is_enabled(), "FBC disabled\n");
+   igt_assert_f(fbc_is_enabled(IGT_LOG_INFO),
+"FBC disabled\n");
}
 
if (opt.fbc_check_compression)
-- 
2.15.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait (rev4)

[Patchwork]

== Series Details ==

Series: igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait 
(rev4)
URL   : https://patchwork.freedesktop.org/series/35699/
State : success

== Summary ==

Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623 +1
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2729 pass:1549 dwarn:1   dfail:0   fail:10  skip:1169 
time:9149s
shard-snbtotal:2729 pass:1318 dwarn:1   dfail:0   fail:11  skip:1399 
time:7909s
Blacklisted hosts:
shard-kbltotal:2653 pass:1765 dwarn:1   dfail:0   fail:25  skip:862 
time:10499s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_784/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] igt/gem_ctx_isolation: Check isolation of registers between contexts

[Patchwork]

== Series Details ==

Series: series starting with [1/5] igt/gem_ctx_isolation: Check isolation of 
registers between contexts
URL   : https://patchwork.freedesktop.org/series/36548/
State : failure

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_cursor_crc:
Subgroup cursor-128x128-onscreen:
pass   -> SKIP   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Test kms_universal_plane:
Subgroup cursor-fb-leak-pipe-c:
pass   -> FAIL   (shard-hsw)
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218
Test kms_flip:
Subgroup vblank-vs-modeset-rpm-interruptible:
pass   -> INCOMPLETE (shard-hsw)
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2756 pass:1550 dwarn:1   dfail:0   fail:12  skip:1192 
time:8766s
shard-snbtotal:2769 pass:1328 dwarn:1   dfail:0   fail:12  skip:1428 
time:7978s
Blacklisted hosts:
shard-apltotal:2747 pass:1709 dwarn:2   dfail:0   fail:27  skip:1008 
time:13554s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_783/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36567/
State : success

== Summary ==

Series 36567v1 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/36567/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-hsw-4770r) fdo#100368
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
pass   -> FAIL   (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:425s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:492s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:284s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:484s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:470s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:278s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:260  dwarn:0   dfail:0   fail:1   skip:27  
time:402s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:416s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:422s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:457s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:507s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:505s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:580s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:435s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:263  dwarn:0   dfail:0   fail:1   skip:24  
time:489s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:529s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:405s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:576s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
d723af029365 drm/i915: expose rcs topology through query uAPI
a342e6718d76 drm/i915: add query uAPI
200e28b0503f drm/i915: add rcs topology to error state
e5d95f265987 drm/i915/debugfs: add rcs topology entry
6fe14cb925d0 drm/i915/debugfs: reuse max slice/subslices already stored in sseu
d759a576e487 drm/i915: store all subslice masks

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7690/issues.html
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Introduce a non-blocking power domain for vblank interrupts

[Pandiyan, Dhinakaran]

On Tue, 2018-01-09 at 10:38 +0100, Maarten Lankhorst wrote:
> Op 08-01-18 om 20:59 schreef Pandiyan, Dhinakaran:
> > On Thu, 2018-01-04 at 18:08 -0800, Rodrigo Vivi wrote:

> >> I will probably have more comments later, but just doing a brain dump now
> >> since I end up forgetting to write yesterday...
> >>
> >> The approach here in general is good and much better than that pre,post 
> >> hooks.
> >> But I just believe we can do this here in a more generic approach than 
> >> deviating
> >> the initial power well and domains.
> > I would have liked a generic approach (for display_power_{get,put}), but
> > I think this case is special enough that making it stand out is better.
> Agreed, I can think of no other way myself without making the generic case 
> too complicated. The whole runtime power management became way too complex 
> for a special case.
> 
I found out that DMC keeps the hardware out of DC5/6 when vblank
interrupts are enabled. This simplified the solution a lot
(https://patchwork.freedesktop.org/series/36435/) Thanks for your review
on this series, would appreciate any feedback on the new one too :)

-DK



> ~Maarten
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Allow user to override PWM backlight frequency and duty cycle

[Saarinen, Jani]

HI, 
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> gnido...@ya.ru
> Sent: tiistai 16. tammikuuta 2018 17.36
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Allow user to 
> override
> PWM backlight frequency and duty cycle
> 
> What branch CI tests against?
https://cgit.freedesktop.org/drm-tip

> I've created the patch against current torvalds/linux
> 
> 16.01.2018, 17:42, "Patchwork" :
> > == Series Details ==
> >
> > Series: drm/i915: Allow user to override PWM backlight frequency and
> > duty cycle URL : https://patchwork.freedesktop.org/series/36540/
> > State : failure
> >
> > == Summary ==
> >
> > Applying: drm/i915: Allow user to override PWM backlight frequency and
> > duty cycle
> > error: Failed to merge in the changes.
> > Using index info to reconstruct a base tree...
> > M drivers/gpu/drm/i915/i915_params.c
> > M drivers/gpu/drm/i915/i915_params.h
> > M drivers/gpu/drm/i915/intel_panel.c
> > Falling back to patching base and 3-way merge...
> > Auto-merging drivers/gpu/drm/i915/intel_panel.c
> > Auto-merging drivers/gpu/drm/i915/i915_params.h
> > Auto-merging drivers/gpu/drm/i915/i915_params.c
> > CONFLICT (content): Merge conflict in
> > drivers/gpu/drm/i915/i915_params.c
> > Patch failed at 0001 drm/i915: Allow user to override PWM backlight
> > frequency and duty cycle The copy of the patch that failed is found
> > in: .git/rebase-apply/patch When you have resolved this problem, run "git am
> --continue".
> > If you prefer to skip this patch, run "git am --skip" instead.
> > To restore the original branch and stop patching, run "git am --abort".


Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo



 
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Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: expose rcs topology through query uAPI

[Lionel Landwerlin]

On 16/01/18 17:40, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-16 16:22:52)

On 16/01/2018 16:02, Lionel Landwerlin wrote:

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 6468ca613d27..81367c8224ee 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,100 @@
   #include "i915_drv.h"
   #include 
   
+static int copy_query_data(struct drm_i915_query_item *query_item,

+const void *item_ptr, u32 item_length,
+const void *data_ptr, u32 data_length)
+{
+ u32 total_length = item_length + data_length;
+
+ if (query_item->length == 0)
+ return total_length;
+
+ if (query_item->length != total_length)

Pretty please
if (query_item->length < total_length)


Sorry... something when wrong, I've already changed this 3 times...




+ return -EINVAL;
+
+ if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
+  item_ptr, item_length))
+ return -EFAULT;
+
+ if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
+  data_ptr, data_length))
+ return -EFAULT;
+
+ return total_length;
+}
   for (i = 0; i < args->num_items; i++, user_item_ptr++) {
   struct drm_i915_query_item item;
+ int ret;
   
   if (copy_from_user(, user_item_ptr, sizeof(item)))

   return -EFAULT;
@@ -45,11 +138,24 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
   return -EINVAL;
   
   switch (item.query_id) {

+ case DRM_I915_QUERY_SLICE_INFO:
+ ret = query_slice_info(dev_priv, );
+ break;
+ case DRM_I915_QUERY_SUBSLICE_INFO:
+ ret = query_subslice_info(dev_priv, );
+ break;
+ case DRM_I915_QUERY_EU_INFO:
+ ret = query_eu_info(dev_priv, );
+ break;

I still can't believe Tvrtko hasn't asked this to become an function
pointer array. Tvrtko, I presume you've looked at how engine-info may
fit into this? And engine-stats? And have suggestions for making adding
new queries easier. Or are you happy as is?
-Chris


Done.


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[Intel-gfx] [PATCH v7 5/6] drm/i915: add query uAPI

[Lionel Landwerlin]

There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die recovery).

At the moment the GET_PARAM ioctl covers some basic needs, but
generally is only able to return a single value for each defined
parameter. This is a bit problematic with topology descriptions which
are array/maps of available units.

This change introduces a new ioctl that can deal with requests to fill
structures of potentially variable lengths. The user is expected fill
a query with length fields set at 0 on the first call, the kernel then
sets the length fields to the their expected values. A second call to
the kernel with length fields at their expected values will trigger a
copy of the data to the pointed memory locations.

The scope of this uAPI is only to provide information to userspace,
not to allow configuration of the device.

v2: Simplify dispatcher code iteration (Tvrtko)
Tweak uapi drm_i915_query_item structure (Tvrtko)

v3: Rename pad fields into flags (Chris)
Return error on flags field != 0 (Chris)
Only copy length back to userspace in drm_i915_query_item (Chris)

v4: Use array of functions instead of switch (Chris)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/i915_drv.c   |  1 +
 drivers/gpu/drm/i915/i915_drv.h   |  3 ++
 drivers/gpu/drm/i915/i915_query.c | 69 +++
 include/uapi/drm/i915_drm.h   | 32 ++
 5 files changed, 106 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3bddd8a06806..b0415a3e2d59 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -69,6 +69,7 @@ i915-y += i915_cmd_parser.o \
  i915_gem_timeline.o \
  i915_gem_userptr.o \
  i915_gemfs.o \
+ i915_query.o \
  i915_trace_points.o \
  i915_vma.o \
  intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 969835d3cbcd..d92e1b7236fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2824,6 +2824,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, 
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, 
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
 };
 
 static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c42015b05b47..b2615a88936e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3622,6 +3622,9 @@ extern void i915_perf_fini(struct drm_i915_private 
*dev_priv);
 extern void i915_perf_register(struct drm_i915_private *dev_priv);
 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
 
+/* i915_query.c */
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
*file);
+
 /* i915_suspend.c */
 extern int i915_save_state(struct drm_i915_private *dev_priv);
 extern int i915_restore_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
new file mode 100644
index ..51736af7f573
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH 

[Intel-gfx] [PATCH v7 6/6] drm/i915: expose rcs topology through query uAPI

[Lionel Landwerlin]

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
Add uapi macros to read data from *_info structs (Tvrtko)

v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)

v4: factorize query item writting (Tvrtko)
tweak uapi struct/define names (Tvrtko)

v5: Replace ALIGN() macro (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_query.c | 94 +++
 include/uapi/drm/i915_drm.h   | 68 
 2 files changed, 162 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 51736af7f573..038f292e1f2a 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,102 @@
 #include "i915_drv.h"
 #include 
 
+static int copy_query_data(struct drm_i915_query_item *query_item,
+  const void *item_ptr, u32 item_length,
+  const void *data_ptr, u32 data_length)
+{
+   u32 total_length = item_length + data_length;
+
+   if (query_item->length == 0)
+   return total_length;
+
+   if (query_item->length < total_length)
+   return -EINVAL;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
+item_ptr, item_length))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
+data_ptr, data_length))
+   return -EFAULT;
+
+   return total_length;
+}
+
+static int query_slice_info(struct drm_i915_private *dev_priv,
+   struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_slice_info slice_info;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   /*
+* If we ever change the internal slice mask data type, we'll need to
+* update this function.
+*/
+   BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+   memset(_info, 0, sizeof(slice_info));
+   slice_info.max_slices = sseu->max_slices;
+
+   return copy_query_data(query_item, _info, sizeof(slice_info),
+  >slice_mask, sizeof(sseu->slice_mask));
+}
+
+static int query_subslice_info(struct drm_i915_private *dev_priv,
+  struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_subslice_info subslice_info;
+   u32 data_length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(subslice_info));
+   subslice_info.max_slices = sseu->max_slices;
+   subslice_info.max_subslices = sseu->max_subslices;
+
+   data_length = subslice_info.max_slices *
+   DIV_ROUND_UP(subslice_info.max_subslices,
+sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
+
+   return copy_query_data(query_item,
+  _info, sizeof(subslice_info),
+  sseu->subslice_mask, data_length);
+}
+
+static int query_eu_info(struct drm_i915_private *dev_priv,
+struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_eu_info eu_info;
+   u32 data_length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(eu_info));
+   eu_info.max_slices = sseu->max_slices;
+   eu_info.max_subslices = sseu->max_subslices;
+   eu_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
+
+   data_length = eu_info.max_slices * eu_info.max_subslices *
+   DIV_ROUND_UP(eu_info.max_eus_per_subslice, BITS_PER_BYTE);
+
+   return copy_query_data(query_item,
+  _info, sizeof(eu_info),
+  sseu->eu_mask, data_length);
+}
+
 static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item) 
= {
+   query_slice_info,
+   query_subslice_info,
+   query_eu_info,
 };
 

[Intel-gfx] [PATCH v7 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

[Lionel Landwerlin]

Now that we have that information in topology fields, let's just reused it.

v2: Style tweaks (Tvrtko)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 27 +++
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 684551114965..e41a19b7d7bb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4304,11 +4304,11 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 struct sseu_dev_info *sseu)
 {
const struct intel_device_info *info = INTEL_INFO(dev_priv);
-   int s_max = 6, ss_max = 4;
int s, ss;
-   u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+   u32 s_reg[info->sseu.max_slices];
+   u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
/*
 * FIXME: Valid SS Mask respects the spec and read
 * only valid bits for those registers, excluding reserverd
@@ -4330,7 +4330,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4338,7 +4338,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
@@ -4358,17 +4358,12 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
 {
-   int s_max = 3, ss_max = 4;
+   const struct intel_device_info *info = INTEL_INFO(dev_priv);
int s, ss;
-   u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
-
-   /* BXT has a single slice and at most 3 subslices. */
-   if (IS_GEN9_LP(dev_priv)) {
-   s_max = 1;
-   ss_max = 3;
-   }
+   u32 s_reg[info->sseu.max_slices];
+   u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
@@ -4383,7 +4378,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4394,7 +4389,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->subslice_mask[s] =
INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (IS_GEN9_LP(dev_priv)) {
-- 
2.15.1

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[Intel-gfx] [PATCH v7 4/6] drm/i915: add rcs topology to error state

[Lionel Landwerlin]

This might be useful information for developers looking at an error
state.

v2: Place topology towards the end of the error state (Chris)

v3: Reuse common printing code (Michal)

v4: Make this a one-liner (Chris)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 944059322daa..4e22a7990db2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -568,6 +568,7 @@ static void err_print_capabilities(struct 
drm_i915_error_state_buf *m,
struct drm_printer p = i915_error_printer(m);
 
intel_device_info_dump_flags(info, );
+   intel_device_info_dump_topology(>sseu, );
 }
 
 static void err_print_params(struct drm_i915_error_state_buf *m,
-- 
2.15.1

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[Intel-gfx] [PATCH v7 3/6] drm/i915/debugfs: add rcs topology entry

[Lionel Landwerlin]

While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.

slice0: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice1: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice2: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)

v2: Reformat debugfs printing (Tvrtko)
Use the new EU mask helper (Tvrtko)

v3: Move printing code to intel_device_info.c to be shared with error
state (Michal)

Suggested-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 11 +++
 drivers/gpu/drm/i915/intel_device_info.c | 25 +
 drivers/gpu/drm/i915/intel_device_info.h |  2 ++
 3 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e41a19b7d7bb..c3a44a54a0ba 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3166,6 +3166,16 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static int i915_rcs_topology(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct drm_printer p = drm_seq_file_printer(m);
+
+   intel_device_info_dump_topology(_INFO(dev_priv)->sseu, );
+
+   return 0;
+}
+
 static int i915_shrinker_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -4696,6 +4706,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dmc_info", i915_dmc_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
+   {"i915_rcs_topology", i915_rcs_topology, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index ed14994527fc..bc08a5ef0ba2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -123,6 +123,31 @@ void intel_device_info_dump(const struct intel_device_info 
*info,
intel_device_info_dump_flags(info, p);
 }
 
+void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
+struct drm_printer *p)
+{
+   int s, ss;
+
+   if (sseu->max_slices == 0) {
+   drm_printf(p, "Unavailable\n");
+   return;
+   }
+
+   for (s = 0; s < sseu->max_slices; s++) {
+   drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+  s, hweight8(sseu->subslice_mask[s]),
+  sseu->subslice_mask[s]);
+
+   for (ss = 0; ss < sseu->max_subslices; ss++) {
+   u8 enabled_eus = sseu_get_eus(sseu, s, ss);
+
+   drm_printf(p, "\tsubslice%d: %u EUs (0x%hhx)\n",
+  ss, hweight8(enabled_eus), enabled_eus);
+   }
+   }
+}
+
+
 static u16 compute_eu_total(const struct sseu_dev_info *sseu)
 {
u16 i, total = 0;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 36e0df87862d..701888162944 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -220,5 +220,7 @@ void intel_device_info_dump_flags(const struct 
intel_device_info *info,
  struct drm_printer *p);
 void intel_device_info_dump_runtime(const struct intel_device_info *info,
struct drm_printer *p);
+void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
+struct drm_printer *p);
 
 #endif
-- 
2.15.1

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[Intel-gfx] [PATCH v7 0/6] drm/i915: expose RCS topology to userspace

[Lionel Landwerlin]

A few tweaks following comments from Chris.

Cheers,

Lionel Landwerlin (6):
  drm/i915: store all subslice masks
  drm/i915/debugfs: reuse max slice/subslices already stored in sseu
  drm/i915/debugfs: add rcs topology entry
  drm/i915: add rcs topology to error state
  drm/i915: add query uAPI
  drm/i915: expose rcs topology through query uAPI

 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_debugfs.c  |  63 +
 drivers/gpu/drm/i915/i915_drv.c  |   3 +-
 drivers/gpu/drm/i915/i915_drv.h  |   3 +
 drivers/gpu/drm/i915/i915_gpu_error.c|   1 +
 drivers/gpu/drm/i915/i915_query.c| 163 ++
 drivers/gpu/drm/i915/intel_device_info.c | 226 ---
 drivers/gpu/drm/i915/intel_device_info.h |  49 ++-
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 include/uapi/drm/i915_drm.h  | 100 ++
 11 files changed, 534 insertions(+), 79 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c

--
2.15.1
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[Intel-gfx] [PATCH v7 1/6] drm/i915: store all subslice masks

[Lionel Landwerlin]

Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.

v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
Readability changes (Tvrtko)
Add EU index helper (Tvrtko)

v3: Turn ALIGN(v, 8) / 8 into DIV_ROUND_UP(v, BITS_PER_BYTE) (Tvrtko)
Reuse sseu_eu_idx() for setting eu_mask on CHV (Tvrtko)
Reformat debug prints for subslices (Tvrtko)

v4: Change eu_mask helper into sseu_set_eus() (Tvrtko)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  25 ++--
 drivers/gpu/drm/i915/i915_drv.c  |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c | 201 +++
 drivers/gpu/drm/i915/intel_device_info.h |  47 +++-
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 6 files changed, 216 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index cc659b4b2a45..684551114965 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4289,7 +4289,7 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask = BIT(0);
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslice_mask[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4336,7 +4336,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask |= BIT(s);
-   sseu->subslice_mask = info->sseu.subslice_mask;
+   sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4391,8 +4391,8 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
 
if (IS_GEN9_BC(dev_priv))
-   sseu->subslice_mask =
-   INTEL_INFO(dev_priv)->sseu.subslice_mask;
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4402,7 +4402,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
/* skip disabled subslice */
continue;
 
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslice_mask[s] |= BIT(ss);
}
 
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4424,9 +4424,12 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
 
if (sseu->slice_mask) {
-   sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
sseu->eu_per_subslice =
INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+   }
sseu->eu_total = sseu->eu_per_subslice *
 sseu_subslice_total(sseu);
 
@@ -4445,6 +4448,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool 
is_available_info,
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const char *type = is_available_info ? "Available" : "Enabled";
+   int s;
 
seq_printf(m, "  %s Slice Mask: %04x\n", type,
   sseu->slice_mask);
@@ -4452,10 +4456,11 @@ static void i915_print_sseu_info(struct seq_file *m, 
bool is_available_info,
   hweight8(sseu->slice_mask));
seq_printf(m, "  %s Subslice Total: %u\n", type,
   sseu_subslice_total(sseu));
-   seq_printf(m, "  %s Subslice Mask: %04x\n", type,
-  sseu->subslice_mask);
-   seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
-  hweight8(sseu->subslice_mask));
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   seq_printf(m, "  %s Slice%i %u subslices, mask=%04x\n", type,
+   

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/reset_stats: Only allow root to read reset_stats

[Patchwork]

== Series Details ==

Series: drm/i915/reset_stats: Only allow root to read reset_stats
URL   : https://patchwork.freedesktop.org/series/36562/
State : success

== Summary ==

Test kms_flip:
Subgroup vblank-vs-modeset-suspend-interruptible:
pass   -> SKIP   (shard-hsw) fdo#103540
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hswtotal:2729 pass:1548 dwarn:1   dfail:0   fail:10  skip:1170 
time:8968s
shard-snbtotal:2729 pass:1316 dwarn:1   dfail:0   fail:12  skip:1399 
time:7576s
Blacklisted hosts:
shard-apltotal:2729 pass:1698 dwarn:1   dfail:1   fail:22  skip:1006 
time:13479s
shard-kbltotal:2729 pass:1821 dwarn:1   dfail:0   fail:24  skip:882 
time:10190s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7689/shards.html
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Re: [Intel-gfx] [PATCH i-g-t v2] tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation

[Michel Thierry]

On 1/16/2018 10:44 AM, Antonio Argenziano wrote:

On 13/12/17 16:48, Antonio Argenziano wrote:

The test expected IOCTL 'I915_GET_RESET_STATS' would return an error
when not root. That is no longer true in the driver since commit
4c9c0d09741d ("drm/i915: Fix retrieval of hangcheck stats") and therefore
the test was incorrectly failing.

v2:
- Add the commit that changed the behaviour in the Driver to the
  commit message (Michel)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Chris Wilson 
Signed-off-by: Antonio Argenziano 


Ping.


---
  tests/gem_reset_stats.c | 25 +
  1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index edc40767..0c36a7eb 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -605,10 +605,7 @@ static void test_reset_count(const struct 
intel_execution_engine *e,

  c2 = get_reset_count(fd, ctx);
-    if (ctx == 0)
-    igt_assert(c2 == -EPERM);
-    else
-    igt_assert(c2 == 0);
+    igt_assert(c2 == 0);
  }
  igt_waitchildren();
@@ -619,6 +616,11 @@ static void test_reset_count(const struct 
intel_execution_engine *e,

  close(fd);
  }
+static int __get_reset_stats(int fd, struct 
local_drm_i915_reset_stats *rs)

+{
+    return drmIoctl(fd, GET_RESET_STATS_IOCTL, );
+}
+
  static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad)
  {
  struct local_drm_i915_reset_stats rs;
@@ -644,10 +646,17 @@ static void _check_param_ctx(const int fd, const 
int ctx, const cap_t cap)

  const uint32_t bad = rand() + 1;
  if (ctx == 0) {
-    if (cap == root)
-    igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
-    else
-    igt_assert_eq(_test_params(fd, ctx, 0, 0), -EPERM);
+    igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
+
+    if (cap != root) {
+    struct local_drm_i915_reset_stats rs;
+    rs.ctx_id = ctx;
+    rs.reset_count = rand();
+    rs.batch_active = rand();
+    rs.batch_pending = rand();
+    igt_assert(__get_reset_stats(fd, ));
+    igt_assert(rs.reset_count != 0);
+    }


Probably you only care about reset_count == 0, so I would just reuse 
existing code like this:


if (cap != root)
igt_assert(get_reset_count(fd, cxt) == 0);



  }
  igt_assert_eq(_test_params(fd, ctx, 0, bad), -EINVAL);


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Re: [Intel-gfx] [PATCH i-g-t v2] tests/gem_reset_stats: Fix retrieval of hangcheck stats expectation

[Antonio Argenziano]

On 13/12/17 16:48, Antonio Argenziano wrote:

The test expected IOCTL 'I915_GET_RESET_STATS' would return an error
when not root. That is no longer true in the driver since commit
4c9c0d09741d ("drm/i915: Fix retrieval of hangcheck stats") and therefore
the test was incorrectly failing.

v2:
- Add the commit that changed the behaviour in the Driver to the
  commit message (Michel)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Chris Wilson 
Signed-off-by: Antonio Argenziano 


Ping.


---
  tests/gem_reset_stats.c | 25 +
  1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index edc40767..0c36a7eb 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -605,10 +605,7 @@ static void test_reset_count(const struct 
intel_execution_engine *e,
  
  		c2 = get_reset_count(fd, ctx);
  
-		if (ctx == 0)

-   igt_assert(c2 == -EPERM);
-   else
-   igt_assert(c2 == 0);
+   igt_assert(c2 == 0);
}
  
  	igt_waitchildren();

@@ -619,6 +616,11 @@ static void test_reset_count(const struct 
intel_execution_engine *e,
close(fd);
  }
  
+static int __get_reset_stats(int fd, struct local_drm_i915_reset_stats *rs)

+{
+   return drmIoctl(fd, GET_RESET_STATS_IOCTL, );
+}
+
  static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad)
  {
struct local_drm_i915_reset_stats rs;
@@ -644,10 +646,17 @@ static void _check_param_ctx(const int fd, const int ctx, 
const cap_t cap)
const uint32_t bad = rand() + 1;
  
  	if (ctx == 0) {

-   if (cap == root)
-   igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
-   else
-   igt_assert_eq(_test_params(fd, ctx, 0, 0), -EPERM);
+   igt_assert_eq(_test_params(fd, ctx, 0, 0), 0);
+
+   if (cap != root) {
+   struct local_drm_i915_reset_stats rs;
+   rs.ctx_id = ctx;
+   rs.reset_count = rand();
+   rs.batch_active = rand();
+   rs.batch_pending = rand();
+   igt_assert(__get_reset_stats(fd, ));
+   igt_assert(rs.reset_count != 0);
+   }
}
  
  	igt_assert_eq(_test_params(fd, ctx, 0, bad), -EINVAL);



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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36560/
State : warning

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test kms_universal_plane:
Subgroup disable-primary-vs-flip-pipe-a:
pass   -> SKIP   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-render:
pass   -> SKIP   (shard-snb) fdo#103167
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218
Test gem_eio:
Subgroup in-flight:
pass   -> DMESG-WARN (shard-snb) fdo#104058

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058

shard-hswtotal:2729 pass:1549 dwarn:1   dfail:0   fail:10  skip:1169 
time:9137s
shard-snbtotal:2729 pass:1315 dwarn:2   dfail:0   fail:11  skip:1401 
time:7919s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7688/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/reset_stats: Only allow root to read reset_stats

[Antonio Argenziano]

On 16/01/18 09:27, Chris Wilson wrote:

Quoting Antonio Argenziano (2018-01-16 16:09:35)

Instead of returning a zero value for non root users, return an EPERM
error.


What? reset-stats are per-context, private to the client, with the
exception of the global value which is solely protected by capable().


Completely missed that, thanks. Will ping the change to gem_reset_stats.

-Antonio


There is a genuine debate over how much information leakage of one
guilty reset in another context should affect an innocent, and we have
tried to limit that to being only those directly affected and have a
requirement to know (i.e they were executing at the time of the reset
and their calculations will have been restarted with perturbed state).
-Chris


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Re: [Intel-gfx] [PATCH v2] drm/i915: Use the engine name directly in the error_state file

[Michel Thierry]

On 1/15/2018 9:15 AM, Tvrtko Ursulin wrote:


On 10/01/2018 01:21, Michel Thierry wrote:

Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.

v2: Better invalid engine_id handling, capture_bo will not be able know
the engine_id and end up with -1 (Michal).

Suggested-by: Michal Wajdeczko 
Signed-off-by: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_gpu_error.c | 33 
-

  1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c

index 94499c24f279..422e302161e5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -34,16 +34,22 @@
  #include "i915_drv.h"
-static const char *engine_str(int engine)
-{
-    switch (engine) {
-    case RCS: return "render";
-    case VCS: return "bsd";
-    case BCS: return "blt";
-    case VECS: return "vebox";
-    case VCS2: return "bsd2";
-    default: return "";
-    }
+static inline const char *intel_engine_name(struct intel_engine_cs 
*engine)

+{
+    return engine ? engine->name : "";
+}
+
+static inline struct intel_engine_cs *
+intel_engine_lookup(struct drm_i915_private *i915, int engine_id)
+{
+    if (engine_id < 0 || engine_id >= I915_NUM_ENGINES)
+    return NULL;
+    return i915->engine[engine_id];
+}
+
+static const char *engine_str(struct drm_i915_private *i915, int 
engine_id)

+{
+    return intel_engine_name(intel_engine_lookup(i915, engine_id));
  }


Feels like a bit of an overkill to have three functions to this trivial 
thing but meh. Could also maybe cheat and have engine_id as unsigned int 
and so would only need to check for >= I915_NUM_ENGINES.


Anyway, I peeked in intel_error_decode source and couldn't spot anything 
that looked it would break. You checked it by running it? Assuming you did:




Thanks. Yes, I did and also compared the error state output 
(intel_error_decode also still works). The only change is that the batch 
/ ring / HWSP sections now use the engine->name (e.g. they will use rcs0 
instead of render, vcs0 instead of bsd, etc.).


I didn't see anything in IGT complaining (probably because IGT usually 
reads dmesg and there we already use engine->name), but there must be 
something else out there that will complain.




Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko


  static const char *tiling_flag(int tiling)
@@ -345,7 +351,7 @@ static void print_error_buffers(struct 
drm_i915_error_state_buf *m,

  err_puts(m, purgeable_flag(err->purgeable));
  err_puts(m, err->userptr ? " userptr" : "");
  err_puts(m, err->engine != -1 ? " " : "");
-    err_puts(m, engine_str(err->engine));
+    err_puts(m, engine_str(m->i915, err->engine));
  err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
  if (err->name)
@@ -417,7 +423,8 @@ static void error_print_engine(struct 
drm_i915_error_state_buf *m,

  {
  int n;
-    err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
+    err_printf(m, "%s command stream:\n", engine_str(m->i915,
+ ee->engine_id));
  err_printf(m, "  IDLE?: %s\n", yesno(ee->idle));
  err_printf(m, "  START: 0x%08x\n", ee->start);
  err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
@@ -633,7 +640,7 @@ int i915_error_state_to_str(struct 
drm_i915_error_state_buf *m,

  if (error->engine[i].hangcheck_stalled &&
  error->engine[i].context.pid) {
  err_printf(m, "Active process (on ring %s): %s [%d], 
score %d\n",

-   engine_str(i),
+   engine_str(m->i915, i),
 error->engine[i].context.comm,
 error->engine[i].context.pid,
 error->engine[i].context.ban_score);


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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] include: bump drm uAPI headers

[Patchwork]

== Series Details ==

Series: series starting with [1/2] include: bump drm uAPI headers
URL   : https://patchwork.freedesktop.org/series/36561/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
5f5b4a65e672bd10a4422cc1cb3c466659c52db8 igt/gem_linear_blits: Compute GTT size 
using 4G limit

with latest DRM-Tip kernel build CI_DRM_3636
a0ca279440c8 drm-tip: 2018y-01m-16d-10h-49m-51s UTC integration manifest

Testlist changes:
+igt@query@query-garbage
+igt@query@query-topology-coherent-slice-mask
+igt@query@query-topology-matches-eu-total
+igt@query@query-topology-pre-gen8

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +1
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:493s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:489s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:393s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:465s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:418s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:458s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:503s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:458s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:592s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:536s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:402s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:574s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:473s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_785/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Do not WARN_ON with small framebuffers.

[Patchwork]

== Series Details ==

Series: drm/i915: Do not WARN_ON with small framebuffers.
URL   : https://patchwork.freedesktop.org/series/36558/
State : success

== Summary ==

Test kms_flip:
Subgroup vblank-vs-modeset-suspend:
pass   -> SKIP   (shard-snb) fdo#102365
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> SKIP   (shard-snb) fdo#103880
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2729 pass:1549 dwarn:1   dfail:0   fail:10  skip:1169 
time:9111s
shard-snbtotal:2729 pass:1315 dwarn:1   dfail:0   fail:11  skip:1401 
time:7479s
Blacklisted hosts:
shard-apltotal:2729 pass:1698 dwarn:1   dfail:0   fail:23  skip:1006 
time:13527s
shard-kbltotal:2729 pass:1825 dwarn:1   dfail:0   fail:23  skip:880 
time:10633s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7687/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait (rev4)

[Patchwork]

== Series Details ==

Series: igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait 
(rev4)
URL   : https://patchwork.freedesktop.org/series/35699/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
5f5b4a65e672bd10a4422cc1cb3c466659c52db8 igt/gem_linear_blits: Compute GTT size 
using 4G limit

with latest DRM-Tip kernel build CI_DRM_3636
a0ca279440c8 drm-tip: 2018y-01m-16d-10h-49m-51s UTC integration manifest

No testlist changes.

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:425s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:496s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:283s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:470s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:465s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:518s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:395s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:455s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:499s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:585s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:428s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:530s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:476s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_784/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915: Always call to intel_display_set_init_power() in resume_early.

[Maarten Lankhorst]

Op 16-01-18 om 17:44 schreef Imre Deak:
> On Tue, Jan 16, 2018 at 04:53:24PM +0100, Maarten Lankhorst wrote:
>> intel_power_domains_init_hw() calls set_init_power, but when using
>> runtime power management this call is skipped.
> It's skipped during suspend-to-idle. 
>
>> This prevents hw readout from taking place.
>>
>> Signed-off-by: Maarten Lankhorst 
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104172
>> Cc: imre.d...@intel.com
> Fixes: 4900727d35bb ("drm/i915/skl: enable PC9/10 power states during 
> suspend-to-idle")
>
> Thanks for following up on this,
> Reviewed-by: Imre Deak 
Thanks, your commit id was wrong but pushed with the right $id. :)
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Always call to intel_display_set_init_power() in resume_early.

[Patchwork]

== Series Details ==

Series: drm/i915: Always call to intel_display_set_init_power() in resume_early.
URL   : https://patchwork.freedesktop.org/series/36557/
State : success

== Summary ==

Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> SKIP   (shard-snb) fdo#103880
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614

fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2729 pass:1549 dwarn:1   dfail:0   fail:10  skip:1169 
time:9148s
shard-snbtotal:2729 pass:1317 dwarn:1   dfail:0   fail:10  skip:1400 
time:7551s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7686/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] igt/gem_ctx_isolation: Check isolation of registers between contexts

[Patchwork]

== Series Details ==

Series: series starting with [1/5] igt/gem_ctx_isolation: Check isolation of 
registers between contexts
URL   : https://patchwork.freedesktop.org/series/36548/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
5f5b4a65e672bd10a4422cc1cb3c466659c52db8 igt/gem_linear_blits: Compute GTT size 
using 4G limit

with latest DRM-Tip kernel build CI_DRM_3636
a0ca279440c8 drm-tip: 2018y-01m-16d-10h-49m-51s UTC integration manifest

Testlist changes:
+igt@gem_ctx_isolation@bcs0-clean
+igt@gem_ctx_isolation@bcs0-dirty-create
+igt@gem_ctx_isolation@bcs0-dirty-switch
+igt@gem_ctx_isolation@bcs0-none
+igt@gem_ctx_isolation@bcs0-reset
+igt@gem_ctx_isolation@bcs0-s3
+igt@gem_ctx_isolation@bcs0-s4
+igt@gem_ctx_isolation@rcs0-clean
+igt@gem_ctx_isolation@rcs0-dirty-create
+igt@gem_ctx_isolation@rcs0-dirty-switch
+igt@gem_ctx_isolation@rcs0-none
+igt@gem_ctx_isolation@rcs0-reset
+igt@gem_ctx_isolation@rcs0-s3
+igt@gem_ctx_isolation@rcs0-s4
+igt@gem_ctx_isolation@vcs0-clean
+igt@gem_ctx_isolation@vcs0-dirty-create
+igt@gem_ctx_isolation@vcs0-dirty-switch
+igt@gem_ctx_isolation@vcs0-none
+igt@gem_ctx_isolation@vcs0-reset
+igt@gem_ctx_isolation@vcs0-s3
+igt@gem_ctx_isolation@vcs0-s4
+igt@gem_ctx_isolation@vcs1-clean
+igt@gem_ctx_isolation@vcs1-dirty-create
+igt@gem_ctx_isolation@vcs1-dirty-switch
+igt@gem_ctx_isolation@vcs1-none
+igt@gem_ctx_isolation@vcs1-reset
+igt@gem_ctx_isolation@vcs1-s3
+igt@gem_ctx_isolation@vcs1-s4
+igt@gem_ctx_isolation@vecs0-clean
+igt@gem_ctx_isolation@vecs0-dirty-create
+igt@gem_ctx_isolation@vecs0-dirty-switch
+igt@gem_ctx_isolation@vecs0-none
+igt@gem_ctx_isolation@vecs0-reset
+igt@gem_ctx_isolation@vecs0-s3
+igt@gem_ctx_isolation@vecs0-s4
+igt@gem_ctx_switch@basic-all
+igt@gem_ctx_switch@basic-all-heavy
+igt@gem_exec_capture@userptr
+igt@gem_exec_fence@basic-busy-all
+igt@gem_exec_fence@basic-wait-all
+igt@gem_exec_fence@busy-hang-all
+igt@gem_exec_fence@wait-hang-all

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:492s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:486s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:470s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:277s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:514s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:453s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:580s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:533s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:488s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-glk-dsi   

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: expose rcs topology through query uAPI

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-16 16:22:52)
> 
> On 16/01/2018 16:02, Lionel Landwerlin wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_query.c 
> > b/drivers/gpu/drm/i915/i915_query.c
> > index 6468ca613d27..81367c8224ee 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -25,8 +25,100 @@
> >   #include "i915_drv.h"
> >   #include 
> >   
> > +static int copy_query_data(struct drm_i915_query_item *query_item,
> > +const void *item_ptr, u32 item_length,
> > +const void *data_ptr, u32 data_length)
> > +{
> > + u32 total_length = item_length + data_length;
> > +
> > + if (query_item->length == 0)
> > + return total_length;
> > +
> > + if (query_item->length != total_length)

Pretty please
if (query_item->length < total_length)

> > + return -EINVAL;
> > +
> > + if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> > +  item_ptr, item_length))
> > + return -EFAULT;
> > +
> > + if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
> > +  data_ptr, data_length))
> > + return -EFAULT;
> > +
> > + return total_length;
> > +}
> >   for (i = 0; i < args->num_items; i++, user_item_ptr++) {
> >   struct drm_i915_query_item item;
> > + int ret;
> >   
> >   if (copy_from_user(, user_item_ptr, sizeof(item)))
> >   return -EFAULT;
> > @@ -45,11 +138,24 @@ int i915_query_ioctl(struct drm_device *dev, void 
> > *data, struct drm_file *file)
> >   return -EINVAL;
> >   
> >   switch (item.query_id) {
> > + case DRM_I915_QUERY_SLICE_INFO:
> > + ret = query_slice_info(dev_priv, );
> > + break;
> > + case DRM_I915_QUERY_SUBSLICE_INFO:
> > + ret = query_subslice_info(dev_priv, );
> > + break;
> > + case DRM_I915_QUERY_EU_INFO:
> > + ret = query_eu_info(dev_priv, );
> > + break;

I still can't believe Tvrtko hasn't asked this to become an function
pointer array. Tvrtko, I presume you've looked at how engine-info may
fit into this? And engine-stats? And have suggestions for making adding
new queries easier. Or are you happy as is?
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Shrink the GEM kmem_caches upon idling

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-16 17:25:25)
> 
> On 16/01/2018 15:21, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-01-16 15:12:43)
> >>
> >> On 16/01/2018 13:05, Chris Wilson wrote:
> >>> When we finally decide the gpu is idle, that is a good time to shrink
> >>> our kmem_caches.
> >>>
> >>> v2: Comment upon the random sprinkling of rcu_barrier() inside the idle
> >>> worker.
> >>>
> >>> Signed-off-by: Chris Wilson 
> >>> Cc: Tvrtko Ursulin 
> >>> ---
> >>>drivers/gpu/drm/i915/i915_gem.c | 30 ++
> >>>1 file changed, 30 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> >>> b/drivers/gpu/drm/i915/i915_gem.c
> >>> index 335731c93b4a..61b13fdfaa71 100644
> >>> --- a/drivers/gpu/drm/i915/i915_gem.c
> >>> +++ b/drivers/gpu/drm/i915/i915_gem.c
> >>> @@ -4716,6 +4716,21 @@ i915_gem_retire_work_handler(struct work_struct 
> >>> *work)
> >>>}
> >>>}
> >>>
> >>> +static void shrink_caches(struct drm_i915_private *i915)
> >>> +{
> >>> + /*
> >>> +  * kmem_cache_shrink() discards empty slabs and reorders partially
> >>> +  * filled slabs to prioritise allocating from the mostly full slabs,
> >>> +  * with the aim of reducing fragmentation.
> >>> +  */
> >>> + kmem_cache_shrink(i915->priorities);
> >>> + kmem_cache_shrink(i915->dependencies);
> >>> + kmem_cache_shrink(i915->requests);
> >>> + kmem_cache_shrink(i915->luts);
> >>> + kmem_cache_shrink(i915->vmas);
> >>> + kmem_cache_shrink(i915->objects);
> >>> +}
> >>> +
> >>>static inline bool
> >>>new_requests_since_last_retire(const struct drm_i915_private *i915)
> >>>{
> >>> @@ -4803,6 +4818,21 @@ i915_gem_idle_work_handler(struct work_struct 
> >>> *work)
> >>>GEM_BUG_ON(!dev_priv->gt.awake);
> >>>i915_queue_hangcheck(dev_priv);
> >>>}
> >>> +
> >>> + /*
> >>> +  * We use magical TYPESAFE_BY_RCU kmem_caches whose pages are not
> >>> +  * returned to the system imediately but only after an RCU grace
> >>> +  * period. We want to encourage such pages to be returned and so
> >>> +  * incorporate a RCU barrier here to provide some rate limiting
> >>> +  * of the driver and flush the old pages before we free a new batch
> >>> +  * from the next round of shrinking.
> >>> +  */
> >>> + rcu_barrier();
> >>
> >> Should this go into the conditional below? I don't think it makes a
> >> difference effectively, but may be more logical.
> > 
> > My thinking was to have the check after the sleep as the state is
> > subject to change. I'm not concerned about the random unnecessary pauses
> > on this wq, since it is subject to struct_mutex delays, so was quite
> 
> The delay doesn't worry me, but just that it is random - neither the 
> appearance of new requests, or completion of existing ones, has nothing 
> to do with one RCU grace period.
> 
> > happy to think of this as being "we shall only do one idle pass per RCU
> > grace period".
> 
> Idle worker is probably several orders of magnitude less frequent than 
> RCU grace periods so I don't think that can be a concern.
> 
> Hm..
> 
> >>> +
> >>> + if (!new_requests_since_last_retire(dev_priv)) {
> >>> + __i915_gem_free_work(_priv->mm.free_work);
> 
> ... you wouldn't want to pull this up under the struct mutex section? It 
> would need a different flavour of a function to be called, and some 
> refactoring of the existing ones.

"Some". I don't think that improves anything?

The statement of intent to me is that we only throw away the caches and
excess memory if and only if we are idle. The presumption is that under
active conditions those caches are important, but if we are about to
sleep for long periods of time, we should be proactive in releasing
resources.

I can hear you about to ask if we could add a timer and wake up in 10s to
prove we were idle!
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/reset_stats: Only allow root to read reset_stats

[Chris Wilson]

Quoting Antonio Argenziano (2018-01-16 16:09:35)
> Instead of returning a zero value for non root users, return an EPERM
> error.

What? reset-stats are per-context, private to the client, with the
exception of the global value which is solely protected by capable().
There is a genuine debate over how much information leakage of one
guilty reset in another context should affect an innocent, and we have
tried to limit that to being only those directly affected and have a
requirement to know (i.e they were executing at the time of the reset
and their calculations will have been restarted with perturbed state).
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Shrink the GEM kmem_caches upon idling

[Tvrtko Ursulin]

On 16/01/2018 15:21, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-01-16 15:12:43)


On 16/01/2018 13:05, Chris Wilson wrote:

When we finally decide the gpu is idle, that is a good time to shrink
our kmem_caches.

v2: Comment upon the random sprinkling of rcu_barrier() inside the idle
worker.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
   drivers/gpu/drm/i915/i915_gem.c | 30 ++
   1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 335731c93b4a..61b13fdfaa71 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4716,6 +4716,21 @@ i915_gem_retire_work_handler(struct work_struct *work)
   }
   }
   
+static void shrink_caches(struct drm_i915_private *i915)

+{
+ /*
+  * kmem_cache_shrink() discards empty slabs and reorders partially
+  * filled slabs to prioritise allocating from the mostly full slabs,
+  * with the aim of reducing fragmentation.
+  */
+ kmem_cache_shrink(i915->priorities);
+ kmem_cache_shrink(i915->dependencies);
+ kmem_cache_shrink(i915->requests);
+ kmem_cache_shrink(i915->luts);
+ kmem_cache_shrink(i915->vmas);
+ kmem_cache_shrink(i915->objects);
+}
+
   static inline bool
   new_requests_since_last_retire(const struct drm_i915_private *i915)
   {
@@ -4803,6 +4818,21 @@ i915_gem_idle_work_handler(struct work_struct *work)
   GEM_BUG_ON(!dev_priv->gt.awake);
   i915_queue_hangcheck(dev_priv);
   }
+
+ /*
+  * We use magical TYPESAFE_BY_RCU kmem_caches whose pages are not
+  * returned to the system imediately but only after an RCU grace
+  * period. We want to encourage such pages to be returned and so
+  * incorporate a RCU barrier here to provide some rate limiting
+  * of the driver and flush the old pages before we free a new batch
+  * from the next round of shrinking.
+  */
+ rcu_barrier();


Should this go into the conditional below? I don't think it makes a
difference effectively, but may be more logical.


My thinking was to have the check after the sleep as the state is
subject to change. I'm not concerned about the random unnecessary pauses
on this wq, since it is subject to struct_mutex delays, so was quite


The delay doesn't worry me, but just that it is random - neither the 
appearance of new requests, or completion of existing ones, has nothing 
to do with one RCU grace period.



happy to think of this as being "we shall only do one idle pass per RCU
grace period".


Idle worker is probably several orders of magnitude less frequent than 
RCU grace periods so I don't think that can be a concern.


Hm..


+
+ if (!new_requests_since_last_retire(dev_priv)) {
+ __i915_gem_free_work(_priv->mm.free_work);


... you wouldn't want to pull this up under the struct mutex section? It 
would need a different flavour of a function to be called, and some 
refactoring of the existing ones.


shrink_caches could be left here under the same check and preceded by 
rcu_barrier.



I thought for a bit if re-using the worker from here is completely fine
but I think it is. We expect only one pass when called from here so
need_resched will be correctly neutralized/not-relevant from this path.


At present, I was only thinking about the single path. This was meant to
resemble i915_gem_drain_objects(), without the recursion :)


Hm, unless if we consider mmap_gtt users.. so we could still have new
objects appearing on the free_list after the 1st pass. And then
need_resched might kick us out. What do you think?


Not just mmap_gtt, any user freeing objects (coupled with RCU grace
periods). I don't think it matters if we happen to loop until the
timeslice is consumed as we are doing work that we would be doing
anyway on this i915->wq.


Yeah doesn't matter - I was thinking if we should explicitly not 
consider need_resched when called from the idle worker and only grab the 
first batch - what's currently on the freed list.


Regards,

Tvrtko


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/reset_stats: Only allow root to read reset_stats

[Patchwork]

== Series Details ==

Series: drm/i915/reset_stats: Only allow root to read reset_stats
URL   : https://patchwork.freedesktop.org/series/36562/
State : success

== Summary ==

Series 36562v1 drm/i915/reset_stats: Only allow root to read reset_stats
https://patchwork.freedesktop.org/api/1.0/series/36562/revisions/1/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:489s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:484s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:453s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:273s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:513s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:457s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:465s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:504s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:581s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:483s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:525s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:400s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
0c6aa998dd26 drm/i915/reset_stats: Only allow root to read reset_stats

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7689/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36560/
State : success

== Summary ==

Series 36560v1 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/36560/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172 +1

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:491s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:465s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:409s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:451s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:464s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:507s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:580s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:525s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:396s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
7b726ef7c84e drm/i915: expose rcs topology through query uAPI
4ef084e6a20c drm/i915: add query uAPI
b34f0d587b9b drm/i915: add rcs topology to error state
fdf446255f98 drm/i915/debugfs: add rcs topology entry
8f71ead0bfd6 drm/i915/debugfs: reuse max slice/subslices already stored in sseu
dc5ab92f2d3f drm/i915: store all subslice masks

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7688/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915: Always call to intel_display_set_init_power() in resume_early.

[Imre Deak]

On Tue, Jan 16, 2018 at 04:53:24PM +0100, Maarten Lankhorst wrote:
> intel_power_domains_init_hw() calls set_init_power, but when using
> runtime power management this call is skipped.

It's skipped during suspend-to-idle. 

> This prevents hw readout from taking place.
> 
> Signed-off-by: Maarten Lankhorst 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104172
> Cc: imre.d...@intel.com

Fixes: 4900727d35bb ("drm/i915/skl: enable PC9/10 power states during 
suspend-to-idle")

Thanks for following up on this,
Reviewed-by: Imre Deak 

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9cace8732dcf..4cecf5c01265 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1836,6 +1836,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
>   if (IS_GEN9_LP(dev_priv) ||
>   !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
>   intel_power_domains_init_hw(dev_priv, true);
> + else
> + intel_display_set_init_power(dev_priv, true);
>  
>   i915_gem_sanitize(dev_priv);
>  
> -- 
> 2.15.1
> 
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[Intel-gfx] ✗ Fi.CI.IGT: warning for kms_plane_scaling tests. (rev3)

[Patchwork]

== Series Details ==

Series: kms_plane_scaling tests. (rev3)
URL   : https://patchwork.freedesktop.org/series/36485/
State : warning

== Summary ==

Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Subgroup vblank-vs-dpms-suspend-interruptible:
pass   -> SKIP   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218

fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218

shard-hswtotal:2753 pass:1549 dwarn:1   dfail:0   fail:10  skip:1193 
time:9091s
shard-snbtotal:2753 pass:1318 dwarn:1   dfail:0   fail:10  skip:1424 
time:7835s
Blacklisted hosts:
shard-apltotal:2753 pass:1705 dwarn:3   dfail:0   fail:24  skip:1020 
time:13567s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_782/shards.html
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Re: [Intel-gfx] [PATCH] [v2] drm/i915: use static const array for PICK macro

[Arnd Bergmann]

On Mon, Dec 11, 2017 at 7:40 PM, Chris Wilson  wrote:
> Quoting Chris Wilson (2017-12-11 12:51:42)
>> Quoting Arnd Bergmann (2017-12-11 12:46:22)
>> > v2: rebased after a1986f4174a4 ("drm/i915: Remove unnecessary PORT3 
>> > definition.")
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h | 18 +-
>> >  1 file changed, 9 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> > b/drivers/gpu/drm/i915/i915_reg.h
>> > index 09bf043c1c2e..36f4408503e1 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -139,7 +139,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> > return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
>> >  }
>> >
>> > -#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>> > +#define _PICK(__index, ...) ({static const u32 __arr[] = { __VA_ARGS__ }; 
>> > __arr[__index];})
>>
>> Is gcc smart enough for
>> if (__builtin_context_p(__index)) {
>> ((const u32 []){ __VA_ARGS__ })[__index];
>> } else {
>> static const u32 __arr[] = { __VA_ARGS__ };
>> __arr[__index];
>> }
>> ?
>
> Not really, we don't have enough constants for it to make a substantial
> difference:
>
> add/remove: 1/0 grow/shrink: 3/5 up/down: 617/-604 (13)
> Function old new   delta
> cnl_ddi_vswing_program.isra- 574+574
> bxt_ddi_phy_is_enabled   220 241 +21
> bxt_ddi_phy_set_signal_level 537 556 +19
> i9xx_get_pipe_config14741477  +3
> bxt_ddi_phy_verify_state 411 408  -3
> _bxt_ddi_phy_init956 950  -6
> vlv_display_power_well_init  470 461  -9
> bxt_ddi_pll_get_hw_state 774 762 -12
> cnl_ddi_vswing_sequence 1166 592-574
> Total: Before=13461532, After=13461545, chg +0.00%
>
> Of particular note the size of __arr[] is not reduced, so gcc is already
> eliminating the static[] for constant index, or not eliminating the
> redundant branch here.

I noticed we never concluded here. Did you see anything wrong with my
workaround in the end or could we just apply it to avoid the stack
size regression?

   Arnd
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Do not WARN_ON with small framebuffers.

[Patchwork]

== Series Details ==

Series: drm/i915: Do not WARN_ON with small framebuffers.
URL   : https://patchwork.freedesktop.org/series/36558/
State : success

== Summary ==

Series 36558v1 drm/i915: Do not WARN_ON with small framebuffers.
https://patchwork.freedesktop.org/api/1.0/series/36558/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:370s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:486s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:465s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:503s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:579s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:435s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:530s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:487s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
cc5821b66cc0 drm/i915: Do not WARN_ON with small framebuffers.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7687/issues.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36539/
State : warning

== Summary ==

Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623 +1
Test kms_flip:
Subgroup vblank-vs-modeset-suspend:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2729 pass:1548 dwarn:1   dfail:0   fail:10  skip:1170 
time:9057s
shard-snbtotal:2729 pass:1318 dwarn:1   dfail:0   fail:11  skip:1399 
time:7973s
Blacklisted hosts:
shard-kbltotal:2729 pass:1820 dwarn:1   dfail:0   fail:25  skip:883 
time:10609s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7683/shards.html
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Re: [Intel-gfx] [PATCH i-g-t 3/3] debugger: No longer rely on compatability define in intel_bufmgr.h

[Ben Widawsky]

On 18-01-09 23:25:11, Rhys Kidd wrote:

Symbol rename from dri_* to drm_intel_* introduced a number of
compatability defines within intel_bufmgr.h.

Replace the old function with the new function, consistent with
the balance of this file.

Signed-off-by: Rhys Kidd 
---
debugger/eudb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/debugger/eudb.c b/debugger/eudb.c
index 8384950a..de37be52 100644
--- a/debugger/eudb.c
+++ b/debugger/eudb.c
@@ -562,7 +562,7 @@ int main(int argc, char* argv[]) {
if (fscanf(stdin, "%1d", _handle) == 0)
exit(1);
}
-   scratch_bo = intel_bo_gem_create_from_name(bufmgr, "scratch", 
dh_handle);
+   scratch_bo = drm_intel_bo_gem_create_from_name(bufmgr, 
"scratch", dh_handle);
if (scratch_bo == NULL) {
fprintf(stderr, "Couldn't flink buffer\n");
abort();


The series looks good to me, but keep in mind that we never actually made this
work after Sandybridge, and even there, nobody ever ran it but me :-)
Reviewed-by: Ben Widawsky 

--
Ben Widawsky, Intel Open Source Technology Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Always call to intel_display_set_init_power() in resume_early.

[Patchwork]

== Series Details ==

Series: drm/i915: Always call to intel_display_set_init_power() in resume_early.
URL   : https://patchwork.freedesktop.org/series/36557/
State : success

== Summary ==

Series 36557v1 drm/i915: Always call to intel_display_set_init_power() in 
resume_early.
https://patchwork.freedesktop.org/api/1.0/series/36557/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> FAIL   (fi-elk-e7500) fdo#103989 +1
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:377s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:466s
fi-elk-e7500 total:224  pass:167  dwarn:10  dfail:0   fail:1   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:276s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:408s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:495s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:576s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:486s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:522s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:473s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
fd072d020485 drm/i915: Always call to intel_display_set_init_power() in 
resume_early.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7686/issues.html
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Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: expose rcs topology through query uAPI

[Tvrtko Ursulin]

On 16/01/2018 16:02, Lionel Landwerlin wrote:

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

 https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
 Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
 Add uapi macros to read data from *_info structs (Tvrtko)

v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)

v4: factorize query item writting (Tvrtko)
 tweak uapi struct/define names (Tvrtko)

v5: Replace ALIGN() macro (Chris)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_query.c | 108 +-
  include/uapi/drm/i915_drm.h   |  54 +++
  2 files changed, 161 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 6468ca613d27..81367c8224ee 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,100 @@
  #include "i915_drv.h"
  #include 
  
+static int copy_query_data(struct drm_i915_query_item *query_item,

+  const void *item_ptr, u32 item_length,
+  const void *data_ptr, u32 data_length)
+{
+   u32 total_length = item_length + data_length;
+
+   if (query_item->length == 0)
+   return total_length;
+
+   if (query_item->length != total_length)
+   return -EINVAL;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
+item_ptr, item_length))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
+data_ptr, data_length))
+   return -EFAULT;
+
+   return total_length;
+}
+
+static int query_slice_info(struct drm_i915_private *dev_priv,
+   struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_slice_info slice_info;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   /*
+* If we ever change the internal slice mask data type, we'll need to
+* update this function.
+*/
+   BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+   memset(_info, 0, sizeof(slice_info));
+   slice_info.max_slices = sseu->max_slices;
+
+   return copy_query_data(query_item, _info, sizeof(slice_info),
+  >slice_mask, sizeof(sseu->slice_mask));
+}
+
+static int query_subslice_info(struct drm_i915_private *dev_priv,
+  struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_subslice_info subslice_info;
+   u32 data_length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(subslice_info));
+   subslice_info.max_slices = sseu->max_slices;
+   subslice_info.max_subslices = sseu->max_subslices;
+
+   data_length = subslice_info.max_slices *
+   DIV_ROUND_UP(subslice_info.max_subslices,
+sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
+
+   return copy_query_data(query_item,
+  _info, sizeof(subslice_info),
+  sseu->subslice_mask, data_length);
+}
+
+static int query_eu_info(struct drm_i915_private *dev_priv,
+struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_eu_info eu_info;
+   u32 data_length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(eu_info));
+   eu_info.max_slices = sseu->max_slices;
+   eu_info.max_subslices = sseu->max_subslices;
+   eu_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
+
+   data_length = eu_info.max_slices * eu_info.max_subslices *
+   DIV_ROUND_UP(eu_info.max_eus_per_subslice, BITS_PER_BYTE);
+
+   return copy_query_data(query_item,
+  _info, sizeof(eu_info),
+  sseu->eu_mask, data_length);
+}
+
  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
*file)
  {
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_query 

[Intel-gfx] [PATCH] drm/i915/reset_stats: Only allow root to read reset_stats

[Antonio Argenziano]

Instead of returning a zero value for non root users, return an EPERM
error.

Signed-off-by: Antonio Argenziano 
Cc: Chris Wilson 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c | 2 +-
 drivers/gpu/drm/i915/i915_gem_context.c | 9 -
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c8da9d20c33..23fb4c61163c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2817,7 +2817,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, 
i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, 
i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
-   DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, 
i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, 
i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, 
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, 
i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, 
i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 648e7536ff51..e6872bd8b754 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -842,6 +842,9 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev,
if (args->flags || args->pad)
return -EINVAL;
 
+   if (!capable(CAP_SYS_ADMIN))
+   return -EPERM;
+
ret = -ENOENT;
rcu_read_lock();
ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id);
@@ -855,11 +858,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev,
 * we should wrap the hangstats with a seqlock.
 */
 
-   if (capable(CAP_SYS_ADMIN))
-   args->reset_count = i915_reset_count(_priv->gpu_error);
-   else
-   args->reset_count = 0;
-
+   args->reset_count = i915_reset_count(_priv->gpu_error);
args->batch_active = atomic_read(>guilty_count);
args->batch_pending = atomic_read(>active_count);
 
-- 
2.14.2

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[Intel-gfx] [PATCH i-g-t 2/2] tests: add i915 query tests

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 tests/Makefile.sources |   1 +
 tests/meson.build  |   1 +
 tests/query.c  | 268 +
 3 files changed, 270 insertions(+)
 create mode 100644 tests/query.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index e4e06d01..390cc82b 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -227,6 +227,7 @@ TESTS_progs = \
prime_self_import \
prime_udl \
prime_vgem \
+   query \
sw_sync \
syncobj_basic \
syncobj_wait \
diff --git a/tests/meson.build b/tests/meson.build
index 4c4bee1d..70df38f3 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -204,6 +204,7 @@ test_progs = [
'prime_self_import',
'prime_udl',
'prime_vgem',
+   'query',
'sw_sync',
'syncobj_basic',
'syncobj_wait',
diff --git a/tests/query.c b/tests/query.c
new file mode 100644
index ..cb5aedd4
--- /dev/null
+++ b/tests/query.c
@@ -0,0 +1,268 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+IGT_TEST_DESCRIPTION("Testing the query uAPI.");
+
+static bool has_query_supports(int fd)
+{
+   struct drm_i915_query query = {};
+
+   return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, ) == 0;
+}
+
+static void test_query_garbage(int fd)
+{
+   struct drm_i915_query query;
+   struct drm_i915_query_item items[2];
+
+   memset(, 0, sizeof(query));
+   query.num_items = 1;
+   query.items_ptr = 0x;
+   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EFAULT);
+
+   memset(, 0, sizeof(query));
+   query.num_items = 1;
+   query.items_ptr = 0;
+   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EFAULT);
+
+   memset(, 0, sizeof(query));
+   query.num_items = 2;
+   query.items_ptr = (uintptr_t) items;
+   memset(items, 0, sizeof(items));
+   items[0].query_id = 0x;
+   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EINVAL);
+
+   memset(, 0, sizeof(query));
+   query.num_items = 2;
+   query.items_ptr = (uintptr_t) items;
+   memset(items, 0, sizeof(items));
+   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EINVAL);
+
+   memset(, 0, sizeof(query));
+   query.num_items = 2;
+   query.items_ptr = (uintptr_t) items;
+   memset(items, 0, sizeof(items));
+   items[0].query_id = DRM_I915_QUERY_SLICE_INFO;
+   items[0].length = 0x;
+   items[1].query_id = DRM_I915_QUERY_SUBSLICE_INFO;
+   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , EINVAL);
+}
+
+static bool query_topology_supported(int fd)
+{
+   struct drm_i915_query query;
+   struct drm_i915_query_item item;
+
+   memset(, 0, sizeof(query));
+   query.num_items = 1;
+   query.items_ptr = (uintptr_t) 
+
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_SLICE_INFO;
+
+   return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, ) == 0;
+}
+
+static void test_query_topology_pre_gen8(int fd)
+{
+   struct drm_i915_query query;
+   struct drm_i915_query_item item;
+
+   memset(, 0, sizeof(query));
+   query.num_items = 1;
+   query.items_ptr = (uintptr_t) 
+
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_SLICE_INFO;
+
+   do_ioctl_err(fd, DRM_IOCTL_I915_QUERY, , ENODEV);
+}
+
+static void
+test_query_topology_coherent_slice_mask(int fd)
+{
+   struct drm_i915_query query;
+   struct drm_i915_query_item item;
+   struct drm_i915_query_slice_info *slices_info;
+   struct drm_i915_query_subslice_info *subslices_info;
+   drm_i915_getparam_t gp;
+   int slice_mask, subslice_mask;
+   int i, topology_slices, topology_subslices_slice0;
+
+   gp.param = I915_PARAM_SLICE_MASK;
+   gp.value = _mask;
+

[Intel-gfx] [PATCH i-g-t 1/2] include: bump drm uAPI headers

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 include/drm-uapi/i915_drm.h | 126 
 lib/igt_perf.h  |   7 ---
 2 files changed, 126 insertions(+), 7 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 7f28eea4..80debdf5 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -102,6 +102,46 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_INVALID   = -1
 };
 
+/**
+ * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
+ *
+ */
+
+enum drm_i915_pmu_engine_sample {
+   I915_SAMPLE_BUSY = 0,
+   I915_SAMPLE_WAIT = 1,
+   I915_SAMPLE_SEMA = 2
+};
+
+#define I915_PMU_SAMPLE_BITS (4)
+#define I915_PMU_SAMPLE_MASK (0xf)
+#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
+#define I915_PMU_CLASS_SHIFT \
+   (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
+
+#define __I915_PMU_ENGINE(class, instance, sample) \
+   ((class) << I915_PMU_CLASS_SHIFT | \
+   (instance) << I915_PMU_SAMPLE_BITS | \
+   (sample))
+
+#define I915_PMU_ENGINE_BUSY(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
+
+#define I915_PMU_ENGINE_WAIT(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
+
+#define I915_PMU_ENGINE_SEMA(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
+
+#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
+
+#define I915_PMU_ACTUAL_FREQUENCY  __I915_PMU_OTHER(0)
+#define I915_PMU_REQUESTED_FREQUENCY   __I915_PMU_OTHER(1)
+#define I915_PMU_INTERRUPTS__I915_PMU_OTHER(2)
+#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
+
+#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255/* table size 2k - maximum due to use
@@ -278,6 +318,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_OPEN 0x36
 #define DRM_I915_PERF_ADD_CONFIG   0x37
 #define DRM_I915_PERF_REMOVE_CONFIG0x38
+#define DRM_I915_QUERY 0x39
 
 #define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE + 
DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH   DRM_IO ( DRM_COMMAND_BASE + 
DRM_I915_FLUSH)
@@ -335,6 +376,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_OPEN   DRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG  DRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_PERF_REMOVE_CONFIG, __u64)
+#define DRM_IOCTL_I915_QUERY   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_QUERY, struct drm_i915_query)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -1573,6 +1615,90 @@ struct drm_i915_perf_oa_config {
__u64 flex_regs_ptr;
 };
 
+
+struct drm_i915_query_item {
+   __u64 query_id;
+#define DRM_I915_QUERY_SLICE_INFO  0x01
+#define DRM_I915_QUERY_SUBSLICE_INFO   0x02
+#define DRM_I915_QUERY_EU_INFO 0x03
+
+   /*
+* When set to zero by userspace, this is filled with the size of the
+* data to be written at the data_ptr pointer.
+*/
+   __u32 length;
+
+   __u32 flags;
+
+   /*
+* Data will be written at the location pointed by data_ptr when the
+* value of length matches the length of the data to be written by the
+* kernel.
+*/
+   __u64 data_ptr;
+};
+
+struct drm_i915_query {
+   __u32 num_items;
+   __u32 flags;
+
+   /*
+* This point to an array of num_items drm_i915_query_item structures.
+*/
+   __u64 items_ptr;
+};
+
+#define DRM_I915_BIT(bit) ((__u32)1 << (bit))
+#define DRM_I915_DIV_ROUND_UP(val, div) (((val) + (div) - 1) / (div))
+
+/* Data written by the kernel with query DRM_I915_QUERY_ID_SLICES_INFO :
+ *
+ * data: each bit indicates whether a slice is available (1) or fused off (0).
+ *   Use DRM_I915_QUERY_SLICE_AVAILABLE() to query a given slice's
+ *   availability.
+ */
+struct drm_i915_query_slice_info {
+   __u32 max_slices;
+
+#define DRM_I915_QUERY_SLICE_AVAILABLE(info, slice) \
+   !!((info)->data[(slice) / 8] & DRM_I915_BIT((slice) % 8))
+   __u8 data[];
+};
+
+/* Data written by the kernel with query DRM_I915_QUERY_ID_SUBSLICES_INFO :
+ *
+ * data: each bit indicates whether a subslice is available (1) or fused off
+ *   (0). Use DRM_I915_QUERY_SUBSLICE_AVAILABLE() to query a given
+ *   subslice's availability.
+ */
+struct drm_i915_query_subslice_info {
+   __u32 max_slices;
+   __u32 max_subslices;
+
+#define DRM_I915_QUERY_SUBSLICE_AVAILABLE(info, slice, subslice) 

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/vlv: Ramp up gpu freq gradually

[Patchwork]

== Series Details ==

Series: drm/i915/vlv: Ramp up gpu freq gradually
URL   : https://patchwork.freedesktop.org/series/36550/
State : warning

== Summary ==

Series 36550v1 drm/i915/vlv: Ramp up gpu freq gradually
https://patchwork.freedesktop.org/api/1.0/series/36550/revisions/1/mbox/

Test kms_busy:
Subgroup basic-flip-a:
pass   -> DMESG-WARN (fi-byt-j1900)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-kbl-r) fdo#104172

fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:491s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:287s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:252  dwarn:1   dfail:0   fail:0   skip:35  
time:471s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:278s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:499s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:580s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:531s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cfl-s2total:109  pass:97   dwarn:0   dfail:0   fail:0   skip:11 
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:471s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
11597a3b28d6 drm/i915/vlv: Ramp up gpu freq gradually

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7685/issues.html
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[Intel-gfx] [PATCH v6 4/6] drm/i915: add rcs topology to error state

[Lionel Landwerlin]

This might be useful information for developers looking at an error
state.

v2: Place topology towards the end of the error state (Chris)

v3: Reuse common printing code (Michal)

v4: Make this a one-liner (Chris)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 944059322daa..4e22a7990db2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -568,6 +568,7 @@ static void err_print_capabilities(struct 
drm_i915_error_state_buf *m,
struct drm_printer p = i915_error_printer(m);
 
intel_device_info_dump_flags(info, );
+   intel_device_info_dump_topology(>sseu, );
 }
 
 static void err_print_params(struct drm_i915_error_state_buf *m,
-- 
2.15.1

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[Intel-gfx] [PATCH v6 0/6] drm/i915: expose RCS topology to userspace

[Lionel Landwerlin]

Hi again,

A few more changes following Chris' comments.

Cheers,

Lionel Landwerlin (6):
  drm/i915: store all subslice masks
  drm/i915/debugfs: reuse max slice/subslices already stored in sseu
  drm/i915/debugfs: add rcs topology entry
  drm/i915: add rcs topology to error state
  drm/i915: add query uAPI
  drm/i915: expose rcs topology through query uAPI

 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_debugfs.c  |  63 +
 drivers/gpu/drm/i915/i915_drv.c  |   3 +-
 drivers/gpu/drm/i915/i915_drv.h  |   3 +
 drivers/gpu/drm/i915/i915_gpu_error.c|   1 +
 drivers/gpu/drm/i915/i915_query.c| 163 ++
 drivers/gpu/drm/i915/intel_device_info.c | 226 ---
 drivers/gpu/drm/i915/intel_device_info.h |  49 ++-
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 include/uapi/drm/i915_drm.h  |  86 
 11 files changed, 520 insertions(+), 79 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c

--
2.15.1
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[Intel-gfx] [PATCH v6 3/6] drm/i915/debugfs: add rcs topology entry

[Lionel Landwerlin]

While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.

slice0: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice1: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)
slice2: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff)
subslice3: 0 EUs (0x0)

v2: Reformat debugfs printing (Tvrtko)
Use the new EU mask helper (Tvrtko)

v3: Move printing code to intel_device_info.c to be shared with error
state (Michal)

Suggested-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 11 +++
 drivers/gpu/drm/i915/intel_device_info.c | 25 +
 drivers/gpu/drm/i915/intel_device_info.h |  2 ++
 3 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e41a19b7d7bb..c3a44a54a0ba 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3166,6 +3166,16 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static int i915_rcs_topology(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct drm_printer p = drm_seq_file_printer(m);
+
+   intel_device_info_dump_topology(_INFO(dev_priv)->sseu, );
+
+   return 0;
+}
+
 static int i915_shrinker_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -4696,6 +4706,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dmc_info", i915_dmc_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
+   {"i915_rcs_topology", i915_rcs_topology, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index ed14994527fc..bc08a5ef0ba2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -123,6 +123,31 @@ void intel_device_info_dump(const struct intel_device_info 
*info,
intel_device_info_dump_flags(info, p);
 }
 
+void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
+struct drm_printer *p)
+{
+   int s, ss;
+
+   if (sseu->max_slices == 0) {
+   drm_printf(p, "Unavailable\n");
+   return;
+   }
+
+   for (s = 0; s < sseu->max_slices; s++) {
+   drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+  s, hweight8(sseu->subslice_mask[s]),
+  sseu->subslice_mask[s]);
+
+   for (ss = 0; ss < sseu->max_subslices; ss++) {
+   u8 enabled_eus = sseu_get_eus(sseu, s, ss);
+
+   drm_printf(p, "\tsubslice%d: %u EUs (0x%hhx)\n",
+  ss, hweight8(enabled_eus), enabled_eus);
+   }
+   }
+}
+
+
 static u16 compute_eu_total(const struct sseu_dev_info *sseu)
 {
u16 i, total = 0;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 36e0df87862d..701888162944 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -220,5 +220,7 @@ void intel_device_info_dump_flags(const struct 
intel_device_info *info,
  struct drm_printer *p);
 void intel_device_info_dump_runtime(const struct intel_device_info *info,
struct drm_printer *p);
+void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
+struct drm_printer *p);
 
 #endif
-- 
2.15.1

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[Intel-gfx] [PATCH v6 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

[Lionel Landwerlin]

Now that we have that information in topology fields, let's just reused it.

v2: Style tweaks (Tvrtko)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 27 +++
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 684551114965..e41a19b7d7bb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4304,11 +4304,11 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 struct sseu_dev_info *sseu)
 {
const struct intel_device_info *info = INTEL_INFO(dev_priv);
-   int s_max = 6, ss_max = 4;
int s, ss;
-   u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+   u32 s_reg[info->sseu.max_slices];
+   u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
/*
 * FIXME: Valid SS Mask respects the spec and read
 * only valid bits for those registers, excluding reserverd
@@ -4330,7 +4330,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4338,7 +4338,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
@@ -4358,17 +4358,12 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
 {
-   int s_max = 3, ss_max = 4;
+   const struct intel_device_info *info = INTEL_INFO(dev_priv);
int s, ss;
-   u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
-
-   /* BXT has a single slice and at most 3 subslices. */
-   if (IS_GEN9_LP(dev_priv)) {
-   s_max = 1;
-   ss_max = 3;
-   }
+   u32 s_reg[info->sseu.max_slices];
+   u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
@@ -4383,7 +4378,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 GEN9_PGCTL_SSB_EU210_ACK |
 GEN9_PGCTL_SSB_EU311_ACK;
 
-   for (s = 0; s < s_max; s++) {
+   for (s = 0; s < info->sseu.max_slices; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
@@ -4394,7 +4389,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->subslice_mask[s] =
INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
-   for (ss = 0; ss < ss_max; ss++) {
+   for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
 
if (IS_GEN9_LP(dev_priv)) {
-- 
2.15.1

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[Intel-gfx] [PATCH v6 6/6] drm/i915: expose rcs topology through query uAPI

[Lionel Landwerlin]

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
Add uapi macros to read data from *_info structs (Tvrtko)

v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)

v4: factorize query item writting (Tvrtko)
tweak uapi struct/define names (Tvrtko)

v5: Replace ALIGN() macro (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_query.c | 108 +-
 include/uapi/drm/i915_drm.h   |  54 +++
 2 files changed, 161 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 6468ca613d27..81367c8224ee 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,100 @@
 #include "i915_drv.h"
 #include 
 
+static int copy_query_data(struct drm_i915_query_item *query_item,
+  const void *item_ptr, u32 item_length,
+  const void *data_ptr, u32 data_length)
+{
+   u32 total_length = item_length + data_length;
+
+   if (query_item->length == 0)
+   return total_length;
+
+   if (query_item->length != total_length)
+   return -EINVAL;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
+item_ptr, item_length))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
+data_ptr, data_length))
+   return -EFAULT;
+
+   return total_length;
+}
+
+static int query_slice_info(struct drm_i915_private *dev_priv,
+   struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_slice_info slice_info;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   /*
+* If we ever change the internal slice mask data type, we'll need to
+* update this function.
+*/
+   BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+   memset(_info, 0, sizeof(slice_info));
+   slice_info.max_slices = sseu->max_slices;
+
+   return copy_query_data(query_item, _info, sizeof(slice_info),
+  >slice_mask, sizeof(sseu->slice_mask));
+}
+
+static int query_subslice_info(struct drm_i915_private *dev_priv,
+  struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_subslice_info subslice_info;
+   u32 data_length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(subslice_info));
+   subslice_info.max_slices = sseu->max_slices;
+   subslice_info.max_subslices = sseu->max_subslices;
+
+   data_length = subslice_info.max_slices *
+   DIV_ROUND_UP(subslice_info.max_subslices,
+sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
+
+   return copy_query_data(query_item,
+  _info, sizeof(subslice_info),
+  sseu->subslice_mask, data_length);
+}
+
+static int query_eu_info(struct drm_i915_private *dev_priv,
+struct drm_i915_query_item *query_item)
+{
+   const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+   struct drm_i915_query_eu_info eu_info;
+   u32 data_length;
+
+   if (sseu->max_slices == 0)
+   return -ENODEV;
+
+   memset(_info, 0, sizeof(eu_info));
+   eu_info.max_slices = sseu->max_slices;
+   eu_info.max_subslices = sseu->max_subslices;
+   eu_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
+
+   data_length = eu_info.max_slices * eu_info.max_subslices *
+   DIV_ROUND_UP(eu_info.max_eus_per_subslice, BITS_PER_BYTE);
+
+   return copy_query_data(query_item,
+  _info, sizeof(eu_info),
+  sseu->eu_mask, data_length);
+}
+
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
 {
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_query *args = data;
struct drm_i915_query_item __user 

[Intel-gfx] [PATCH v6 1/6] drm/i915: store all subslice masks

[Lionel Landwerlin]

Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.

v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
Readability changes (Tvrtko)
Add EU index helper (Tvrtko)

v3: Turn ALIGN(v, 8) / 8 into DIV_ROUND_UP(v, BITS_PER_BYTE) (Tvrtko)
Reuse sseu_eu_idx() for setting eu_mask on CHV (Tvrtko)
Reformat debug prints for subslices (Tvrtko)

v4: Change eu_mask helper into sseu_set_eus() (Tvrtko)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  25 ++--
 drivers/gpu/drm/i915/i915_drv.c  |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c | 201 +++
 drivers/gpu/drm/i915/intel_device_info.h |  47 +++-
 drivers/gpu/drm/i915/intel_lrc.c |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 6 files changed, 216 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index cc659b4b2a45..684551114965 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4289,7 +4289,7 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask = BIT(0);
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslice_mask[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4336,7 +4336,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask |= BIT(s);
-   sseu->subslice_mask = info->sseu.subslice_mask;
+   sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4391,8 +4391,8 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
 
if (IS_GEN9_BC(dev_priv))
-   sseu->subslice_mask =
-   INTEL_INFO(dev_priv)->sseu.subslice_mask;
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4402,7 +4402,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
/* skip disabled subslice */
continue;
 
-   sseu->subslice_mask |= BIT(ss);
+   sseu->subslice_mask[s] |= BIT(ss);
}
 
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4424,9 +4424,12 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
 
if (sseu->slice_mask) {
-   sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
sseu->eu_per_subslice =
INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   sseu->subslice_mask[s] =
+   INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+   }
sseu->eu_total = sseu->eu_per_subslice *
 sseu_subslice_total(sseu);
 
@@ -4445,6 +4448,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool 
is_available_info,
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const char *type = is_available_info ? "Available" : "Enabled";
+   int s;
 
seq_printf(m, "  %s Slice Mask: %04x\n", type,
   sseu->slice_mask);
@@ -4452,10 +4456,11 @@ static void i915_print_sseu_info(struct seq_file *m, 
bool is_available_info,
   hweight8(sseu->slice_mask));
seq_printf(m, "  %s Subslice Total: %u\n", type,
   sseu_subslice_total(sseu));
-   seq_printf(m, "  %s Subslice Mask: %04x\n", type,
-  sseu->subslice_mask);
-   seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
-  hweight8(sseu->subslice_mask));
+   for (s = 0; s < fls(sseu->slice_mask); s++) {
+   seq_printf(m, "  %s Slice%i %u subslices, mask=%04x\n", type,
+   

[Intel-gfx] [PATCH v6 5/6] drm/i915: add query uAPI

[Lionel Landwerlin]

There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die recovery).

At the moment the GET_PARAM ioctl covers some basic needs, but
generally is only able to return a single value for each defined
parameter. This is a bit problematic with topology descriptions which
are array/maps of available units.

This change introduces a new ioctl that can deal with requests to fill
structures of potentially variable lengths. The user is expected fill
a query with length fields set at 0 on the first call, the kernel then
sets the length fields to the their expected values. A second call to
the kernel with length fields at their expected values will trigger a
copy of the data to the pointed memory locations.

The scope of this uAPI is only to provide information to userspace,
not to allow configuration of the device.

v2: Simplify dispatcher code iteration (Tvrtko)
Tweak uapi drm_i915_query_item structure (Tvrtko)

v3: Rename pad fields into flags (Chris)
Return error on flags field != 0 (Chris)
Only copy length back to userspace in drm_i915_query_item (Chris)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/i915_drv.c   |  1 +
 drivers/gpu/drm/i915/i915_drv.h   |  3 +++
 drivers/gpu/drm/i915/i915_query.c | 57 +++
 include/uapi/drm/i915_drm.h   | 32 ++
 5 files changed, 94 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3bddd8a06806..b0415a3e2d59 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -69,6 +69,7 @@ i915-y += i915_cmd_parser.o \
  i915_gem_timeline.o \
  i915_gem_userptr.o \
  i915_gemfs.o \
+ i915_query.o \
  i915_trace_points.o \
  i915_vma.o \
  intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 969835d3cbcd..d92e1b7236fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2824,6 +2824,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, 
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, 
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, 
DRM_UNLOCKED|DRM_RENDER_ALLOW),
 };
 
 static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c42015b05b47..b2615a88936e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3622,6 +3622,9 @@ extern void i915_perf_fini(struct drm_i915_private 
*dev_priv);
 extern void i915_perf_register(struct drm_i915_private *dev_priv);
 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
 
+/* i915_query.c */
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
*file);
+
 /* i915_suspend.c */
 extern int i915_save_state(struct drm_i915_private *dev_priv);
 extern int i915_restore_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
new file mode 100644
index ..6468ca613d27
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE 

[Intel-gfx] [PATCH] drm/i915: Do not WARN_ON with small framebuffers.

[Maarten Lankhorst]

It's perfectly legal to create a fb with stride < 512, and one of
the kms_plane_scaling subtests creates a very small fb.

Downgrade the WARN_ON to a simple check check, and because this
function is potentially called on every atomic update/pageflip,
downgrade the other WARN_ON to a WARN_ON_ONCE, and do the right
thing here.

Cc: Paulo Zanoni 
Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_fbc.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 7a64405f4514..c4e924e41db3 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -668,11 +668,13 @@ void intel_fbc_cleanup_cfb(struct drm_i915_private 
*dev_priv)
 static bool stride_is_valid(struct drm_i915_private *dev_priv,
unsigned int stride)
 {
-   /* These should have been caught earlier. */
-   WARN_ON(stride < 512);
-   WARN_ON((stride & (64 - 1)) != 0);
+   /* This should have been caught earlier. */
+   if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
+   return false;
 
/* Below are the additional FBC restrictions. */
+   if (stride < 512)
+   return false;
 
if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
return stride == 4096 || stride == 8192;
-- 
2.15.1

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[Intel-gfx] [PATCH] drm/i915: Always call to intel_display_set_init_power() in resume_early.

[Maarten Lankhorst]

intel_power_domains_init_hw() calls set_init_power, but when using
runtime power management this call is skipped. This prevents hw readout
from taking place.

Signed-off-by: Maarten Lankhorst 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104172
Cc: imre.d...@intel.com
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9cace8732dcf..4cecf5c01265 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1836,6 +1836,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
if (IS_GEN9_LP(dev_priv) ||
!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
intel_power_domains_init_hw(dev_priv, true);
+   else
+   intel_display_set_init_power(dev_priv, true);
 
i915_gem_sanitize(dev_priv);
 
-- 
2.15.1

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Allow user to override PWM backlight frequency and duty cycle

[gnidorah]

What branch CI tests against?
I've created the patch against current torvalds/linux

16.01.2018, 17:42, "Patchwork" :
> == Series Details ==
>
> Series: drm/i915: Allow user to override PWM backlight frequency and duty 
> cycle
> URL : https://patchwork.freedesktop.org/series/36540/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915: Allow user to override PWM backlight frequency and duty 
> cycle
> error: Failed to merge in the changes.
> Using index info to reconstruct a base tree...
> M drivers/gpu/drm/i915/i915_params.c
> M drivers/gpu/drm/i915/i915_params.h
> M drivers/gpu/drm/i915/intel_panel.c
> Falling back to patching base and 3-way merge...
> Auto-merging drivers/gpu/drm/i915/intel_panel.c
> Auto-merging drivers/gpu/drm/i915/i915_params.h
> Auto-merging drivers/gpu/drm/i915/i915_params.c
> CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_params.c
> Patch failed at 0001 drm/i915: Allow user to override PWM backlight frequency 
> and duty cycle
> The copy of the patch that failed is found in: .git/rebase-apply/patch
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/10] drm/i915: Only attempt to scan the requested number of shrinker slabs (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [01/10] drm/i915: Only attempt to scan the 
requested number of shrinker slabs (rev4)
URL   : https://patchwork.freedesktop.org/series/36501/
State : success

== Summary ==

Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Subgroup plain-flip-ts-check:
pass   -> SKIP   (shard-hsw) fdo#100368
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail   -> PASS   (shard-snb) fdo#101623
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252 +1

fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2729 pass:1547 dwarn:1   dfail:0   fail:11  skip:1170 
time:9011s
shard-snbtotal:2729 pass:1319 dwarn:1   dfail:0   fail:10  skip:1399 
time:7938s
Blacklisted hosts:
shard-apltotal:2729 pass:1698 dwarn:1   dfail:0   fail:23  skip:1006 
time:13573s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7682/shards.html
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Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Disable preemption and sleeping while using the punit sideband

[Mika Kuoppala]

Chris Wilson  writes:

> Quoting Mika Kuoppala (2018-01-15 12:04:40)
>> Chris Wilson  writes:
>> 
>> > While we talk to the punit over its sideband, we need to prevent the cpu
>> > from sleeping in order to prevent a potential machine hang.
>> >
>> > Note that by itself, it appears that pm_qos_update_request (via
>> > intel_idle) doesn't provide a sufficient barrier to ensure that all core
>> > are indeed awake (out of Cstate) and that the package is awake. To do so,
>> > we need to supplement the pm_qos with a manual ping on_each_cpu.
>> >
>> > v2: Restrict the heavy-weight wakeup to just the ISOF_PORT_PUNIT, there
>> > is insufficient evidence to implicate a wider problem atm. Similarly,
>> > restrict the w/a to Valleyview, as Cherryview doesn't have an angry cadre
>> > of users.
>> >
>> 
>> One datapoint about the v1 of this patch with the cpu ping in it.
>> The j1900 byt did end up with system hang during weekend with
>> drm-tip + v1.
>
> Not much different (supposedly in v2, especially if we ignore the bits
> after the revert), and v2 ran most of Fri-Mon without incident. (Most
> because I tested a few other things as well, such as eliminating the
> waitboosting for glxgears in the reproducer.)
>
> 1 hang in 100 hours across 2 machines. Certainly the best we've achieved
> so far (while allowing RPS to frequently adjust gpufreq). Any fresh ideas?

Since you asked, I tried to express one idea with a fresh patch:
20180116152116.17900-1-mika.kuopp...@linux.intel.com

-Mika
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Re: [Intel-gfx] [PATCH RFC] drm/i915/vlv: Ramp up gpu freq gradually

[Chris Wilson]

Quoting Mika Kuoppala (2018-01-16 15:21:16)
> There is a suspicion that with aggressive upclocking, power rail
> voltage fluctuations can disrupt c state transition, leading
> to system hang.
> 
> When upclocking with 4 cpu Baytrails, bring up cpus to c1 and then
> go through bins gradually towards target frequency to give leeway
> for hw.
> 
> We go towards requested frequency on 1 millisecond intervals. For
> each 1 millisecond, we increase the frequency by half of bins
> that are in between current frequency and target.

Either this is good for everyone or it is not. Doing more punit accesses
seems counter productive though, and adds 8ms to the initial request?
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Shrink the GEM kmem_caches upon idling

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-01-16 15:12:43)
> 
> On 16/01/2018 13:05, Chris Wilson wrote:
> > When we finally decide the gpu is idle, that is a good time to shrink
> > our kmem_caches.
> > 
> > v2: Comment upon the random sprinkling of rcu_barrier() inside the idle
> > worker.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > ---
> >   drivers/gpu/drm/i915/i915_gem.c | 30 ++
> >   1 file changed, 30 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 335731c93b4a..61b13fdfaa71 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -4716,6 +4716,21 @@ i915_gem_retire_work_handler(struct work_struct 
> > *work)
> >   }
> >   }
> >   
> > +static void shrink_caches(struct drm_i915_private *i915)
> > +{
> > + /*
> > +  * kmem_cache_shrink() discards empty slabs and reorders partially
> > +  * filled slabs to prioritise allocating from the mostly full slabs,
> > +  * with the aim of reducing fragmentation.
> > +  */
> > + kmem_cache_shrink(i915->priorities);
> > + kmem_cache_shrink(i915->dependencies);
> > + kmem_cache_shrink(i915->requests);
> > + kmem_cache_shrink(i915->luts);
> > + kmem_cache_shrink(i915->vmas);
> > + kmem_cache_shrink(i915->objects);
> > +}
> > +
> >   static inline bool
> >   new_requests_since_last_retire(const struct drm_i915_private *i915)
> >   {
> > @@ -4803,6 +4818,21 @@ i915_gem_idle_work_handler(struct work_struct *work)
> >   GEM_BUG_ON(!dev_priv->gt.awake);
> >   i915_queue_hangcheck(dev_priv);
> >   }
> > +
> > + /*
> > +  * We use magical TYPESAFE_BY_RCU kmem_caches whose pages are not
> > +  * returned to the system imediately but only after an RCU grace
> > +  * period. We want to encourage such pages to be returned and so
> > +  * incorporate a RCU barrier here to provide some rate limiting
> > +  * of the driver and flush the old pages before we free a new batch
> > +  * from the next round of shrinking.
> > +  */
> > + rcu_barrier();
> 
> Should this go into the conditional below? I don't think it makes a 
> difference effectively, but may be more logical.

My thinking was to have the check after the sleep as the state is
subject to change. I'm not concerned about the random unnecessary pauses
on this wq, since it is subject to struct_mutex delays, so was quite
happy to think of this as being "we shall only do one idle pass per RCU
grace period".

> > +
> > + if (!new_requests_since_last_retire(dev_priv)) {
> > + __i915_gem_free_work(_priv->mm.free_work);
> 
> I thought for a bit if re-using the worker from here is completely fine 
> but I think it is. We expect only one pass when called from here so 
> need_resched will be correctly neutralized/not-relevant from this path. 

At present, I was only thinking about the single path. This was meant to
resemble i915_gem_drain_objects(), without the recursion :)

> Hm, unless if we consider mmap_gtt users.. so we could still have new 
> objects appearing on the free_list after the 1st pass. And then 
> need_resched might kick us out. What do you think?

Not just mmap_gtt, any user freeing objects (coupled with RCU grace
periods). I don't think it matters if we happen to loop until the
timeslice is consumed as we are doing work that we would be doing
anyway on this i915->wq.
-Chris
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[Intel-gfx] [PATCH RFC] drm/i915/vlv: Ramp up gpu freq gradually

[Mika Kuoppala]

There is a suspicion that with aggressive upclocking, power rail
voltage fluctuations can disrupt c state transition, leading
to system hang.

When upclocking with 4 cpu Baytrails, bring up cpus to c1 and then
go through bins gradually towards target frequency to give leeway
for hw.

We go towards requested frequency on 1 millisecond intervals. For
each 1 millisecond, we increase the frequency by half of bins
that are in between current frequency and target.

This will have an adverse effect on client boosting, delaying
reaching full frequency by about 8ms.

References: https://bugzilla.kernel.org/show_bug.cgi?id=109051
References: https://bugs.freedesktop.org/show_bug.cgi?id=102657
Cc: Chris Wilson 
Cc: Hans de Goede 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  7 
 drivers/gpu/drm/i915/i915_drv.c |  5 +++
 drivers/gpu/drm/i915/i915_drv.h |  4 +++
 drivers/gpu/drm/i915/intel_pm.c | 72 +++--
 4 files changed, 86 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index cc659b4b2a45..9c718c2811b8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1043,6 +1043,13 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
seq_printf(m, "current GPU freq: %d MHz\n",
   intel_gpu_freq(dev_priv, rps->cur_freq));
 
+   if (IS_VALLEYVIEW(dev_priv)) {
+   seq_printf(m, "target GPU freq: %d MHz\n",
+  intel_gpu_freq(dev_priv, rps->target_freq));
+   seq_printf(m, "QOS CPU DMA Latency %d usecs\n",
+  pm_qos_request(PM_QOS_CPU_DMA_LATENCY));
+   }
+
seq_printf(m, "max GPU freq: %d MHz\n",
   intel_gpu_freq(dev_priv, rps->max_freq));
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c8da9d20c33..9718afacfa30 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -896,6 +896,10 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
BITS_PER_BYTE);
device_info->gen_mask = BIT(device_info->gen - 1);
 
+   pm_qos_add_request(_priv->gt_pm.rps.qos,
+  PM_QOS_CPU_DMA_LATENCY,
+  PM_QOS_DEFAULT_VALUE);
+
spin_lock_init(_priv->irq_lock);
spin_lock_init(_priv->gpu_error.lock);
mutex_init(_priv->backlight_lock);
@@ -953,6 +957,7 @@ static void i915_driver_cleanup_early(struct 
drm_i915_private *dev_priv)
intel_irq_fini(dev_priv);
i915_workqueues_cleanup(dev_priv);
i915_engines_cleanup(dev_priv);
+   pm_qos_remove_request(_priv->gt_pm.rps.qos);
 }
 
 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c42015b05b47..90cc2788fbbb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -936,6 +936,10 @@ struct intel_rps {
 
/* manual wa residency calculations */
struct intel_rps_ei ei;
+
+   u8 target_freq; /* vlv target to reach */
+   struct pm_qos_request qos;
+   struct delayed_work vlv_rps_work;
 };
 
 struct intel_rc6 {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db79a860b96..00ef4cb7bd8f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6200,7 +6200,7 @@ static int gen6_set_rps(struct drm_i915_private 
*dev_priv, u8 val)
return 0;
 }
 
-static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
+static int valleyview_set_hw_rps(struct drm_i915_private *dev_priv, u8 val)
 {
int err;
 
@@ -6224,6 +6224,69 @@ static int valleyview_set_rps(struct drm_i915_private 
*dev_priv, u8 val)
return 0;
 }
 
+static void valleyview_queue_rps_change(struct drm_i915_private *dev_priv)
+{
+   struct intel_rps * const rps = _priv->gt_pm.rps;
+   unsigned long delay;
+
+   delay = 1 + msecs_to_jiffies(1);
+   queue_delayed_work(system_wq, >vlv_rps_work, delay);
+}
+
+static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
+{
+   struct intel_rps * const rps = _priv->gt_pm.rps;
+
+   /* 2 cpu Baytrails seems to be safe */
+   if (IS_CHERRYVIEW(dev_priv) || num_online_cpus() <= 2)
+   return valleyview_set_hw_rps(dev_priv, val);
+
+   /*
+* For >2 cpu Baytrails we need to get cpus to C1
+* and limit the freq rampup.
+*/
+   rps->target_freq = val;
+   pm_qos_update_request(_priv->gt_pm.rps.qos, 0);
+
+   valleyview_queue_rps_change(dev_priv);
+

Re: [Intel-gfx] [PATCH v2] drm/i915: Shrink the request kmem_cache on allocation error

[Tvrtko Ursulin]

On 16/01/2018 13:15, Chris Wilson wrote:

If we fail to allocate a new request, make sure we recover the pages
that are in the process of being freed by inserting an RCU barrier.

v2: Comment before the shrink and barrier in the error path.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/i915_gem_request.c | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 72bdc203716f..a0f451b4a4e8 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -696,6 +696,17 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_unreserve;
  
+		/*

+* We've forced the client to stall and catch up with whatever
+* backlog there might have been. As we are assuming that we
+* caused the mempressure, now is an opportune time to
+* recover as much memory from the request pool as is possible.
+* Having already penalized the client to stall, we spend
+* a little extra time to re-optimise page allocation.
+*/
+   kmem_cache_shrink(dev_priv->requests);
+   rcu_barrier(); /* Recover the TYPESAFE_BY_RCU pages */
+
req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
if (!req) {
ret = -ENOMEM;



Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH v2] drm/i915: Shrink the GEM kmem_caches upon idling

[Tvrtko Ursulin]

On 16/01/2018 15:12, Tvrtko Ursulin wrote:


On 16/01/2018 13:05, Chris Wilson wrote:

When we finally decide the gpu is idle, that is a good time to shrink
our kmem_caches.

v2: Comment upon the random sprinkling of rcu_barrier() inside the idle
worker.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/i915_gem.c | 30 ++
  1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c 
b/drivers/gpu/drm/i915/i915_gem.c

index 335731c93b4a..61b13fdfaa71 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4716,6 +4716,21 @@ i915_gem_retire_work_handler(struct work_struct 
*work)

  }
  }
+static void shrink_caches(struct drm_i915_private *i915)
+{
+    /*
+ * kmem_cache_shrink() discards empty slabs and reorders partially
+ * filled slabs to prioritise allocating from the mostly full slabs,
+ * with the aim of reducing fragmentation.
+ */
+    kmem_cache_shrink(i915->priorities);
+    kmem_cache_shrink(i915->dependencies);
+    kmem_cache_shrink(i915->requests);
+    kmem_cache_shrink(i915->luts);
+    kmem_cache_shrink(i915->vmas);
+    kmem_cache_shrink(i915->objects);
+}
+
  static inline bool
  new_requests_since_last_retire(const struct drm_i915_private *i915)
  {
@@ -4803,6 +4818,21 @@ i915_gem_idle_work_handler(struct work_struct 
*work)

  GEM_BUG_ON(!dev_priv->gt.awake);
  i915_queue_hangcheck(dev_priv);
  }
+
+    /*
+ * We use magical TYPESAFE_BY_RCU kmem_caches whose pages are not
+ * returned to the system imediately but only after an RCU grace
+ * period. We want to encourage such pages to be returned and so
+ * incorporate a RCU barrier here to provide some rate limiting
+ * of the driver and flush the old pages before we free a new batch
+ * from the next round of shrinking.
+ */
+    rcu_barrier();


Should this go into the conditional below? I don't think it makes a 
difference effectively, but may be more logical.



+
+    if (!new_requests_since_last_retire(dev_priv)) {
+    __i915_gem_free_work(_priv->mm.free_work);


I thought for a bit if re-using the worker from here is completely fine 
but I think it is. We expect only one pass when called from here so 
need_resched will be correctly neutralized/not-relevant from this path. 
Hm, unless if we consider mmap_gtt users.. so we could still have new 
objects appearing on the free_list after the 1st pass. And then 
need_resched might kick us out. What do you think?


This also ties back to what I wrote in the earlier reply - do we want to 
shrink the obj and vma caches from here? It may be colliding with 
mmap_gtt operations. But it sounds appealing to tidy them, and I can't 
think of any other convenient point. Given how we are de-prioritising 
mmap_gtt its probably fine.




Regards,

Tvrtko


+    shrink_caches(dev_priv);
+    }
  }
  int i915_gem_suspend(struct drm_i915_private *dev_priv)


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Re: [Intel-gfx] [PATCH v2] drm/i915: Shrink the GEM kmem_caches upon idling

[Tvrtko Ursulin]

On 16/01/2018 13:05, Chris Wilson wrote:

When we finally decide the gpu is idle, that is a good time to shrink
our kmem_caches.

v2: Comment upon the random sprinkling of rcu_barrier() inside the idle
worker.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/i915_gem.c | 30 ++
  1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 335731c93b4a..61b13fdfaa71 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4716,6 +4716,21 @@ i915_gem_retire_work_handler(struct work_struct *work)
}
  }
  
+static void shrink_caches(struct drm_i915_private *i915)

+{
+   /*
+* kmem_cache_shrink() discards empty slabs and reorders partially
+* filled slabs to prioritise allocating from the mostly full slabs,
+* with the aim of reducing fragmentation.
+*/
+   kmem_cache_shrink(i915->priorities);
+   kmem_cache_shrink(i915->dependencies);
+   kmem_cache_shrink(i915->requests);
+   kmem_cache_shrink(i915->luts);
+   kmem_cache_shrink(i915->vmas);
+   kmem_cache_shrink(i915->objects);
+}
+
  static inline bool
  new_requests_since_last_retire(const struct drm_i915_private *i915)
  {
@@ -4803,6 +4818,21 @@ i915_gem_idle_work_handler(struct work_struct *work)
GEM_BUG_ON(!dev_priv->gt.awake);
i915_queue_hangcheck(dev_priv);
}
+
+   /*
+* We use magical TYPESAFE_BY_RCU kmem_caches whose pages are not
+* returned to the system imediately but only after an RCU grace
+* period. We want to encourage such pages to be returned and so
+* incorporate a RCU barrier here to provide some rate limiting
+* of the driver and flush the old pages before we free a new batch
+* from the next round of shrinking.
+*/
+   rcu_barrier();


Should this go into the conditional below? I don't think it makes a 
difference effectively, but may be more logical.



+
+   if (!new_requests_since_last_retire(dev_priv)) {
+   __i915_gem_free_work(_priv->mm.free_work);


I thought for a bit if re-using the worker from here is completely fine 
but I think it is. We expect only one pass when called from here so 
need_resched will be correctly neutralized/not-relevant from this path. 
Hm, unless if we consider mmap_gtt users.. so we could still have new 
objects appearing on the free_list after the 1st pass. And then 
need_resched might kick us out. What do you think?


Regards,

Tvrtko


+   shrink_caches(dev_priv);
+   }
  }
  
  int i915_gem_suspend(struct drm_i915_private *dev_priv)



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[Intel-gfx] [PATCH igt] igt/kms_frontbuffer_tracking: Show FBC status at the start of the wait

[Chris Wilson]

Signed-off-by: Chris Wilson 
---
 tests/kms_frontbuffer_tracking.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1601cab45..8b440dadc 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -927,6 +927,10 @@ static bool fbc_stride_not_supported(void)
 
 static bool fbc_wait_until_enabled(void)
 {
+   if (fbc_is_enabled())
+   return true;
+
+   fbc_print_status();
return igt_wait(fbc_is_enabled(), 2000, 1);
 }
 
-- 
2.15.1

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[Intel-gfx] [PATCH igt 3/5] igt/gem_ctx_switch: Exercise all engines at once

[Chris Wilson]

Just a small variant to apply a continuous context-switch load to all
engines.
---
 tests/gem_ctx_switch.c | 76 ++
 1 file changed, 76 insertions(+)

diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index 159554e52..fe919f7d6 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -147,6 +147,77 @@ static void single(int fd, uint32_t handle,
gem_context_destroy(fd, contexts[n]);
 }
 
+static void all(int fd, uint32_t handle, unsigned flags, int timeout)
+{
+   struct drm_i915_gem_execbuffer2 execbuf;
+   struct drm_i915_gem_exec_object2 obj[2];
+   unsigned int engine[16], e;
+   const char *name[16];
+   uint32_t contexts[64];
+   unsigned int nengine;
+   int n;
+
+   nengine = 0;
+   for_each_engine(fd, e) {
+   if (e == 0 || e == I915_EXEC_BSD)
+   continue;
+
+   engine[nengine] = e;
+   name[nengine] = e__->name;
+   nengine++;
+   }
+   igt_require(nengine);
+
+   igt_require(__gem_context_create(fd, [0]) == 0);
+   for (n = 1; n < 64; n++)
+   contexts[n] = gem_context_create(fd);
+
+   memset(obj, 0, sizeof(obj));
+   obj[1].handle = handle;
+
+   memset(, 0, sizeof(execbuf));
+   execbuf.buffers_ptr = to_user_pointer(obj + 1);
+   execbuf.buffer_count = 1;
+   execbuf.rsvd1 = contexts[0];
+   execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
+   execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
+   igt_require(__gem_execbuf(fd, ) == 0);
+   gem_sync(fd, handle);
+   execbuf.buffers_ptr = to_user_pointer(obj);
+   execbuf.buffer_count = 2;
+
+   igt_fork(child, nengine) {
+   struct timespec start, now;
+   unsigned int count = 0;
+
+   obj[0].handle = gem_create(fd, 4096);
+   execbuf.flags |= engine[child];
+   gem_execbuf(fd, );
+   gem_sync(fd, obj[0].handle);
+
+   clock_gettime(CLOCK_MONOTONIC, );
+   do {
+   for (int loop = 0; loop < 64; loop++) {
+   execbuf.rsvd1 = contexts[loop % 64];
+   gem_execbuf(fd, );
+   }
+   count += 64;
+   clock_gettime(CLOCK_MONOTONIC, );
+   } while (elapsed(, ) < timeout);
+   gem_sync(fd, obj[0].handle);
+   clock_gettime(CLOCK_MONOTONIC, );
+   gem_close(fd, obj[0].handle);
+
+   igt_info("[%d] %s: %'u cycles: %.3fus%s\n",
+child, name[child], count, elapsed(, )*1e6 / 
count,
+flags & INTERRUPTIBLE ? " (interruptible)" : "");
+   }
+   igt_waitchildren();
+
+   for (n = 0; n < 64; n++)
+   gem_context_destroy(fd, contexts[n]);
+}
+
 igt_main
 {
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -187,6 +258,11 @@ igt_main
single(fd, light, e, INTERRUPTIBLE, ncpus, 150);
}
 
+   igt_subtest("basic-all")
+   all(fd, light, 0, 20);
+   igt_subtest("basic-all-heavy")
+   all(fd, heavy, 0, 20);
+
igt_fixture {
igt_stop_hang_detector();
gem_close(fd, heavy);
-- 
2.15.1

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[Intel-gfx] [PATCH igt 2/5] igt/gem_ctx_switch: Do a warmup pass over all contexts

[Chris Wilson]

Ensure that we always use every context at least once before we start
running the stress-test.

Signed-off-by: Chris Wilson 
---
 tests/gem_ctx_switch.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index fdd67202f..159554e52 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -115,6 +115,13 @@ static void single(int fd, uint32_t handle,
struct timespec start, now;
unsigned int count = 0;
 
+   /* Warmup */
+   for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
+   execbuf.rsvd1 = contexts[i];
+   gem_execbuf(fd, );
+   }
+   gem_sync(fd, handle);
+
clock_gettime(CLOCK_MONOTONIC, );
do {
igt_while_interruptible(flags & INTERRUPTIBLE) {
-- 
2.15.1

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[Intel-gfx] [PATCH igt 1/5] igt/gem_ctx_isolation: Check isolation of registers between contexts

[Chris Wilson]

A new context assumes that all of its registers are in the default state
when it is created. What may happen is that a register written by one
context may leak into the second, causing mass confusion.

v2: Extend back to Sandybridge (etc)
v3: Check context preserves registers across suspend/hibernate and resets.
v4: Complete the remapping onto the new class:instance
v5: Not like that, like this, try again to use class:instance
v6: Prepare for retrospective gen4 contexts!
v7: Repaint register set name to nonpriv, as this is what bspec calls the
registers that are writable by userspace.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
---
 tests/Makefile.sources|   1 +
 tests/gem_ctx_isolation.c | 677 ++
 tests/gem_exec_fence.c|   2 +-
 3 files changed, 679 insertions(+), 1 deletion(-)
 create mode 100644 tests/gem_ctx_isolation.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index e4e06d01d..d6d176596 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -57,6 +57,7 @@ TESTS_progs = \
gem_ctx_bad_exec \
gem_ctx_create \
gem_ctx_exec \
+   gem_ctx_isolation \
gem_ctx_param \
gem_ctx_switch \
gem_ctx_thrash \
diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
new file mode 100644
index 0..8b69cd33f
--- /dev/null
+++ b/tests/gem_ctx_isolation.c
@@ -0,0 +1,677 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_dummyload.h"
+
+#define MAX_REG 0x4
+#define NUM_REGS (MAX_REG / sizeof(uint32_t))
+
+#define PAGE_ALIGN(x) ALIGN(x, 4096)
+
+#define DIRTY1 0x1
+#define DIRTY2 0x2
+#define RESET 0x4
+
+#define BIT(x) (1ul << (x))
+#define ENGINE(x, y) BIT(4*(x) + (y))
+
+enum {
+   RCS0 = ENGINE(I915_ENGINE_CLASS_RENDER, 0),
+   BCS0 = ENGINE(I915_ENGINE_CLASS_COPY, 0),
+   VCS0 = ENGINE(I915_ENGINE_CLASS_VIDEO, 0),
+   VCS1 = ENGINE(I915_ENGINE_CLASS_VIDEO, 1),
+   VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
+};
+
+#define ALL ~0u
+#define GEN_RANGE(x, y) ((ALL >> (32 - (y - x + 1))) << x)
+#define GEN4 (ALL << 4)
+#define GEN5 (ALL << 5)
+#define GEN6 (ALL << 6)
+#define GEN7 (ALL << 7)
+#define GEN8 (ALL << 8)
+#define GEN9 (ALL << 9)
+
+#define NOCTX 0
+
+#define LAST_KNOWN_GEN 10
+
+static const struct named_register {
+   const char *name;
+   unsigned int gen_mask;
+   unsigned int engine_mask;
+   uint32_t offset;
+   uint32_t count;
+} nonpriv_registers[] = {
+   { "NOPID", NOCTX, RCS0, 0x2094 },
+   { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
+   { "INSTPM", GEN9, RCS0, 0x20c0 },
+   { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
+   { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
+   { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
+   { "HS_INVOCATION_COUNT", GEN4, RCS0, 0x2300, 2 },
+   { "DS_INVOCATION_COUNT", GEN4, RCS0, 0x2308, 2 },
+   { "GS_INVOCATION_COUNT", GEN4, RCS0, 0x2328, 2 },
+   { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
+   { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
+   { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
+   { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+   { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
+   { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
+   { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
+   { "GPUGPU_DISPATCHDIMZ", GEN8, RCS0, 0x2508 },
+   { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
+   { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
+   { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
+   { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+   { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
+   { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },

[Intel-gfx] [PATCH igt 5/5] igt/gem_exec_fence: Exercise merging fences

[Chris Wilson]

Execute the same batch on each engine and check that the composite fence
across all engines completes only after the batch is completed on every
engine.

Signed-off-by: Chris Wilson 
---
 tests/gem_exec_fence.c | 127 +
 1 file changed, 127 insertions(+)

diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
index 0094ca7f0..18d9864f6 100644
--- a/tests/gem_exec_fence.c
+++ b/tests/gem_exec_fence.c
@@ -207,6 +207,113 @@ static void test_fence_busy(int fd, unsigned ring, 
unsigned flags)
gem_quiescent_gpu(fd);
 }
 
+static void test_fence_busy_all(int fd, unsigned flags)
+{
+   const int gen = intel_gen(intel_get_drm_devid(fd));
+   struct drm_i915_gem_exec_object2 obj;
+   struct drm_i915_gem_relocation_entry reloc;
+   struct drm_i915_gem_execbuffer2 execbuf;
+   struct timespec tv;
+   uint32_t *batch;
+   unsigned int engine;
+   int all, i, timeout;
+
+   gem_quiescent_gpu(fd);
+
+   memset(, 0, sizeof(execbuf));
+   execbuf.buffers_ptr = to_user_pointer();
+   execbuf.buffer_count = 1;
+
+   memset(, 0, sizeof(obj));
+   obj.handle = gem_create(fd, 4096);
+
+   obj.relocs_ptr = to_user_pointer();
+   obj.relocation_count = 1;
+   memset(, 0, sizeof(reloc));
+
+   batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+   gem_set_domain(fd, obj.handle,
+  I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+   reloc.target_handle = obj.handle; /* recurse */
+   reloc.presumed_offset = 0;
+   reloc.offset = sizeof(uint32_t);
+   reloc.delta = 0;
+   reloc.read_domains = I915_GEM_DOMAIN_COMMAND;
+   reloc.write_domain = 0;
+
+   i = 0;
+   batch[i] = MI_BATCH_BUFFER_START;
+   if (gen >= 8) {
+   batch[i] |= 1 << 8 | 1;
+   batch[++i] = 0;
+   batch[++i] = 0;
+   } else if (gen >= 6) {
+   batch[i] |= 1 << 8;
+   batch[++i] = 0;
+   } else {
+   batch[i] |= 2 << 6;
+   batch[++i] = 0;
+   if (gen < 4) {
+   batch[i] |= 1;
+   reloc.delta = 1;
+   }
+   }
+   i++;
+
+   all = -1;
+   for_each_engine(fd, engine) {
+   int fence, new;
+
+   execbuf.flags = engine | LOCAL_EXEC_FENCE_OUT;
+   execbuf.rsvd2 = -1;
+   gem_execbuf_wr(fd, );
+   fence = execbuf.rsvd2 >> 32;
+   igt_assert(fence != -1);
+
+   if (all < 0) {
+   all = fence;
+   break;
+   }
+
+   new = sync_fence_merge(all, fence);
+   igt_assert_lte(0, new);
+   close(all);
+   close(fence);
+
+   all = new;
+   }
+
+   igt_assert(gem_bo_busy(fd, obj.handle));
+   igt_assert(fence_busy(all));
+
+   timeout = 120;
+   if ((flags & HANG) == 0) {
+   *batch = MI_BATCH_BUFFER_END;
+   __sync_synchronize();
+   timeout = 1;
+   }
+   munmap(batch, 4096);
+
+   if (flags & WAIT) {
+   struct pollfd pfd = { .fd = all, .events = POLLIN };
+   igt_assert(poll(, 1, timeout*1000) == 1);
+   } else {
+   memset(, 0, sizeof(tv));
+   while (fence_busy(all))
+   igt_assert(igt_seconds_elapsed() < timeout);
+   }
+
+   igt_assert(!gem_bo_busy(fd, obj.handle));
+   igt_assert_eq(sync_fence_status(all),
+ flags & HANG ? -EIO : SYNC_FENCE_OK);
+
+   close(all);
+   gem_close(fd, obj.handle);
+
+   gem_quiescent_gpu(fd);
+}
+
 static void test_fence_await(int fd, unsigned ring, unsigned flags)
 {
const int gen = intel_gen(intel_get_drm_devid(fd));
@@ -1463,6 +1570,26 @@ igt_main
gem_submission_print_method(i915);
}
 
+   igt_subtest_group {
+   igt_fixture {
+   igt_fork_hang_detector(i915);
+   }
+
+   igt_subtest("basic-busy-all")
+   test_fence_busy_all(i915, 0);
+   igt_subtest("basic-wait-all")
+   test_fence_busy_all(i915, WAIT);
+
+   igt_fixture {
+   igt_stop_hang_detector();
+   }
+
+   igt_subtest("busy-hang-all")
+   test_fence_busy_all(i915, HANG);
+   igt_subtest("wait-hang-all")
+   test_fence_busy_all(i915, WAIT | HANG);
+   }
+
for (e = intel_execution_engines; e->name; e++) {
igt_subtest_group {
igt_fixture {
-- 
2.15.1

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[Intel-gfx] [PATCH igt 4/5] igt/gem_exec_capture: Exercise readback of userptr

[Chris Wilson]

EXEC_OBJECT_CAPTURE extends the type of buffers we may read during error
capture. Previously we knew that we would only see batch buffers (which
limited the objects to being from gem_create()), but now we need to
check that any buffer the user can create can be read. The first
alternate buffer type is a userptr.

Signed-off-by: Chris Wilson 
---
 tests/gem_exec_capture.c | 35 ---
 1 file changed, 32 insertions(+), 3 deletions(-)

diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
index a73ece5da..1c7d1e7cb 100644
--- a/tests/gem_exec_capture.c
+++ b/tests/gem_exec_capture.c
@@ -56,7 +56,7 @@ static void check_error_state(int dir, struct 
drm_i915_gem_exec_object2 *obj)
igt_assert(found);
 }
 
-static void capture(int fd, int dir, unsigned ring)
+static void __capture(int fd, int dir, unsigned ring, uint32_t target)
 {
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[4];
@@ -71,7 +71,7 @@ static void capture(int fd, int dir, unsigned ring)
 
memset(obj, 0, sizeof(obj));
obj[SCRATCH].handle = gem_create(fd, 4096);
-   obj[CAPTURE].handle = gem_create(fd, 4096);
+   obj[CAPTURE].handle = target;
obj[CAPTURE].flags = LOCAL_OBJECT_CAPTURE;
obj[NOCAPTURE].handle = gem_create(fd, 4096);
 
@@ -156,10 +156,32 @@ static void capture(int fd, int dir, unsigned ring)
 
gem_close(fd, obj[BATCH].handle);
gem_close(fd, obj[NOCAPTURE].handle);
-   gem_close(fd, obj[CAPTURE].handle);
gem_close(fd, obj[SCRATCH].handle);
 }
 
+static void capture(int fd, int dir, unsigned ring)
+{
+   uint32_t handle;
+
+   handle = gem_create(fd, 4096);
+   __capture(fd, dir, ring, handle);
+   gem_close(fd, handle);
+}
+
+static void userptr(int fd, int dir)
+{
+   uint32_t handle;
+   void *ptr;
+
+   igt_assert(posix_memalign(, 4096, 4096) == 0);
+   igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, ) == 0);
+
+   __capture(fd, dir, 0, handle);
+
+   gem_close(fd, handle);
+   free(ptr);
+}
+
 static bool has_capture(int fd)
 {
drm_i915_getparam_t gp;
@@ -204,6 +226,13 @@ igt_main
}
}
 
+   /* And check we can read from different types of objects */
+
+   igt_subtest_f("userptr") {
+   igt_require(gem_can_store_dword(fd, 0));
+   userptr(fd, dir);
+   }
+
igt_fixture {
close(dir);
igt_disallow_hang(fd, hang);
-- 
2.15.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for kms_plane_scaling tests. (rev3)

[Patchwork]

== Series Details ==

Series: kms_plane_scaling tests. (rev3)
URL   : https://patchwork.freedesktop.org/series/36485/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
7b685d5790c1770eeac43c17d6b207a6df602985 Update NEWS, bump version to 1.21.

with latest DRM-Tip kernel build CI_DRM_3636
a0ca279440c8 drm-tip: 2018y-01m-16d-10h-49m-51s UTC integration manifest

Testlist changes:
+igt@kms_plane_scaling@2x-scaler-multi-pipe
+igt@kms_plane_scaling@pipe-a-plane-scaling
+igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-a-scaler-with-rotation
+igt@kms_plane_scaling@pipe-b-plane-scaling
+igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-b-scaler-with-rotation
+igt@kms_plane_scaling@pipe-c-plane-scaling
+igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-c-scaler-with-rotation
+igt@kms_plane_scaling@pipe-d-plane-scaling
+igt@kms_plane_scaling@pipe-d-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-d-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-d-scaler-with-rotation
+igt@kms_plane_scaling@pipe-e-plane-scaling
+igt@kms_plane_scaling@pipe-e-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-e-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-e-scaler-with-rotation
+igt@kms_plane_scaling@pipe-f-plane-scaling
+igt@kms_plane_scaling@pipe-f-scaler-with-clipping-clamping
+igt@kms_plane_scaling@pipe-f-scaler-with-pixel-format
+igt@kms_plane_scaling@pipe-f-scaler-with-rotation
-igt@kms_plane_scaling

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS   (fi-elk-e7500) fdo#103989 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:490s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:485s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:471s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:518s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:460s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:501s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:579s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:483s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:522s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:402s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:569s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:476s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_782/issues.html
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Re: [Intel-gfx] [PATCH v5 6/6] drm/i915: expose rcs topology through query uAPI

[Lionel Landwerlin]

On 16/01/18 14:22, Chris Wilson wrote:

Quoting Lionel Landwerlin (2018-01-16 13:40:10)

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

 https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
 Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
 Add uapi macros to read data from *_info structs (Tvrtko)

v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)

v4: factorize query item writting (Tvrtko)
 tweak uapi struct/define names (Tvrtko)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_query.c | 107 ++
  include/uapi/drm/i915_drm.h   |  53 +++
  2 files changed, 160 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 5694cfea4553..4d18fbd07cbd 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,102 @@
  #include "i915_drv.h"
  #include 
  
+static int copy_query_data(struct drm_i915_query_item *query_item,

+  const void *item_ptr, u32 item_length,
+  const void *data_ptr, u32 data_length)
+{
+   u32 total_length = item_length + data_length;
+
+   if (query_item->length == 0) {
+   query_item->length = total_length;
+   return 0;
+   }
+
+   if (query_item->length != total_length)
+   return -EINVAL;

Let the user pass in a preallocated buffer of a certain size, and only
have to resort to reallocating if too small. i.e.
if (query_item->length < total_length)
return -EINVAL;


Done.




+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
+item_ptr, item_length))
+   return -EFAULT;
+
+   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
+data_ptr, data_length))
+   return -EFAULT;
+
+   return 0;
+}
+
+static int query_slice_info(struct drm_i915_private *dev_priv,
+   struct drm_i915_query_item *query_item)
+static int query_subslice_info(struct drm_i915_private *dev_priv,
+  struct drm_i915_query_item *query_item)
+static int query_eu_info(struct drm_i915_private *dev_priv,
+struct drm_i915_query_item *query_item)

Couldn't spot any stray leaks.


  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
*file)
  {
+   struct drm_i915_private *dev_priv = to_i915(dev);
 struct drm_i915_query *args = data;
 struct drm_i915_query_item __user *user_item_ptr =
 u64_to_user_ptr(args->items_ptr);
@@ -34,15 +128,28 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
struct drm_file *file)
  
 for (i = 0; i < args->num_items; i++, user_item_ptr++) {

 struct drm_i915_query_item item;
+   int ret;
  
 if (copy_from_user(, user_item_ptr, sizeof(item)))

 return -EFAULT;
  
 switch (item.query_id) {

+   case DRM_I915_QUERY_SLICE_INFO:
+   ret = query_slice_info(dev_priv, );
+   break;
+   case DRM_I915_QUERY_SUBSLICE_INFO:
+   ret = query_subslice_info(dev_priv, );
+   break;
+   case DRM_I915_QUERY_EU_INFO:
+   ret = query_eu_info(dev_priv, );
+   break;
 default:
 return -EINVAL;
 }
  
+   if (ret)

+   return ret;

I would make item const and return the copied length:
if (ret < 0)
return 0;

if (ret != item.length && put_user(ret, _item_ptr->length))
return -EFAULT;


Okay.




+#define DRM_I915_BIT(bit) (1 << (bit))

((__u32)1 << (bit))

Might as well prepare for that 32nd bit.


Done.




+
+/* Data written by the kernel with query DRM_I915_QUERY_ID_SLICES_INFO :
+ *
+ * data: each bit indicates whether a slice is available (1) or fused off (0).
+ *   Use DRM_I915_QUERY_SLICE_AVAILABLE() to query a given slice's
+ *   availability.
+ */
+struct drm_i915_query_slice_info {
+   __u32 max_slices;
+
+#define DRM_I915_QUERY_SLICE_AVAILABLE(info, slice) \
+   !!((info)->data[(slice) / 8] & 

[Intel-gfx] [ANNOUNCE] intel-gpu-tools 1.21

[Petri Latvala]

A new intel-gpu-tools quarterly release is available with the
following changes:

Library changes:

- Added helpers for using DRM syncobj. (Jason Ekstrand)

- Refactored several i915 helpers into library functions.
  (Michał Winiarski)

- Improved the GPU quiescing code to more thoroughly flush old data
  and pending work. (Chris Wilson)

- Reworked DRM property handling to be more suitable for
  atomic commits. (Maarten Lankhorst)

- Removed support for legacy CRC API. The generic API has been
  available since kernel 4.10. (Maarten Lankhorst)

- Opening a DRM device now automatically loads its module. (Chris Wilson)

- Imported the drm-uapi headers as copies instead of using what's
  installed in the system. (Eric Anholt)

- Moved the perf code to its own library from
  intel-gpu-overlay. (Tvrtko Ursulin)

- Removed Android support due to lack of use and
  maintenance. (Arkadiusz Hiler)

- Upgraded meson to official production status, automake is still kept
  around for now.

Tools changes:

- Improved the output of intel_vbt_decode. (Jani Nikula)

- intel_error_decode now prints user buffers if they contain debug
  logs. (Chris Wilson)

- Improved the output of intel_watermark. (Ville Syrjälä,
  Dhinakaran Pandiyan)

- Aubdump can now simulate execlist submission, converting from ring
  buffer submission method. (Scott D Phillips)

- intel-gpu-overlay can now show data from perf PMU. (Tvrtko Ursulin,
  Chris Wilson)

- intel-gpu-overlay now parses tracepoint locations from
  sysfs. (Lionel Landwerlin)

Documentation changes:

- Documentation can now be built with Meson. (Daniel Vetter)


And many other bug fixes, improvements, cleanups and new tests.


And the full changelog follows:

Abdiel Janulgue (3):
  tests/gem_hangcheck_forcewake: Drop gem_hangcheck_forcewake.c
  tests/gem_pin: Drop gem_pin.c
  tests/gem_seqno_wrap: Drop gem_seqno_wrap.c

Antonio Argenziano (2):
  tests/gem_exec_schedule: Add reset on failed preemption test.
  tests/gem_exec_schedule: Add test for resetting preemptive batch

Arkadiusz Hiler (8):
  meson: Add fallback for xmlrpc discovery
  tests: Clean up igt_skip_on_simulation() uses
  tests/intel-ci: Remove fast-feedback-simulation.testlist
  lib/igt_core: Move write_stderr out of LIBUNWIND ifdef
  igt: Remove Android support
  Revert "lib/igt_aux: Make procps optional"
  igt: Make dependency on libunwind mandatory
  test/kms_plane_lowres: Fix display_commit_mode() so it returns the crc

Chris Wilson (93):
  igt/gem_workarounds: Read the workaround registers from the active context
  igt/gem_workarounds: Also exercise fresh contexts not the persistent 
default
  igt/gem_workarounds: Also test new fd (implicit default context)
  igt/gem_workarounds: Reduce manual list to combinatorial loops
  igt/gem_workarounds: Add hibernation coverage
  igt/gem_exec_scheduler: Add small priority sorting smoketest
  igt/gem_fence_thrash: Use streaming reads for verify
  igt/syncobj_wait: Replace open-coded calls to __syncobj_wait()
  igt/syncobj_wait: Close the sw_sync timeline after the test
  igt/drv_hangman: Convert from local recursive batch to igt_spin_t
  benchmark/gem_busy: Compare polling with syncobj_wait
  igt/gem_eio: Check hang/eio recovery during suspend
  igt/gem_mocs_settings: Skip non-existent engines
  igt/prime_mmap_coherency: Only assert correct usage of sync API
  igt/pm_rc6_residency: Allow some leeway on the upper %% bound
  igt/prime_mmap_coherency: Call prime_sync_start before read after write
  lib: Add DROP_IDLE
  lib: Idle the GT when quiescing the GPU
  lib: Flush the driver's internal cache of objects before counting
  lib: Free all internal buffers before measuring available memory
  lib/i915: Add a query for when the guc is enabled.
  igt/drv_misssed_irq: Skip on guc
  igt/prime_mmap_coherency: Remove manual gem_sync() calls
  lib/gt: Always eat the unwanted error state
  igt/gem_fd_exhaustion: Remove stale assert
  igt/gem_exec_nop: Headless requires DRM_MASTER for modesetting
  igt/drv_hangman: Skip aliased I915_EXEC_BSD
  igt/gem_exec_latency: Wire up an interloper for preemption
  lib: Always enable ftrace-dump-on-oops
  lib/i915: Query semaphore status using GETPARAM
  lib/debugfs: Make is_mountpoint() non-fatal
  lib: Attempt to load the module for a missing device
  lib/kmod: Stop reloading i915 after every kselftest
  lib: Dump /sys/kernel/debug/suspend_stats after suspend failure
  lib/i915: Prepare for the loss of i915.enable_execlists parameter
  tools/error_decode: Print ASCII user buffers
  tools: Stop opening the driver just to find the debugfs
  igt/perf_pmu: Test for supported perf before starting test_interrupts
  igt/perf_pmu: Tidy skip message for unsupported kernels
  igt/perf_pmu: Clear errno in between invalid atrr tests
  

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Allow user to override PWM backlight frequency and duty cycle

[Patchwork]

== Series Details ==

Series: drm/i915: Allow user to override PWM backlight frequency and duty cycle
URL   : https://patchwork.freedesktop.org/series/36540/
State : failure

== Summary ==

Applying: drm/i915: Allow user to override PWM backlight frequency and duty 
cycle
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_params.c
M   drivers/gpu/drm/i915/i915_params.h
M   drivers/gpu/drm/i915/intel_panel.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_panel.c
Auto-merging drivers/gpu/drm/i915/i915_params.h
Auto-merging drivers/gpu/drm/i915/i915_params.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_params.c
Patch failed at 0001 drm/i915: Allow user to override PWM backlight frequency 
and duty cycle
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace

[Patchwork]

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/36539/
State : success

== Summary ==

Series 36539v1 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/36539/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:491s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:276s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:517s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:504s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:575s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:530s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:487s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:531s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:472s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
9b89a1775a89 drm/i915: expose rcs topology through query uAPI
2bc667f6a204 drm/i915: add query uAPI
c1eb8d92f783 drm/i915: add rcs topology to error state
e8e690f3b7e8 drm/i915/debugfs: add rcs topology entry
cde94dc0919d drm/i915/debugfs: reuse max slice/subslices already stored in sseu
679358c21a36 drm/i915: store all subslice masks

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7683/issues.html
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Re: [Intel-gfx] [PATCH v5 5/6] drm/i915: add query uAPI

[Lionel Landwerlin]

On 16/01/18 14:08, Chris Wilson wrote:

Quoting Lionel Landwerlin (2018-01-16 13:40:09)

+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+   struct drm_i915_query *args = data;
+   struct drm_i915_query_item __user *user_item_ptr =
+   u64_to_user_ptr(args->items_ptr);
+   u32 i;

You need to reject non-zero pad values. I would just rename them as
flags because that's almost always the first field added later on when
extending the ioctl.


Ah yeah, forgot about that...




+
+   for (i = 0; i < args->num_items; i++, user_item_ptr++) {
+   struct drm_i915_query_item item;
+
+   if (copy_from_user(, user_item_ptr, sizeof(item)))
+   return -EFAULT;
+
+   switch (item.query_id) {
+   default:
+   return -EINVAL;
+   }
+
+   if (copy_to_user(user_item_ptr, , sizeof(item)))
+   return -EFAULT;

I would suggest not doing a blind copy of the entire item. The majority
of it should be unchanged, but copying everything sounds like an easy
accident to leak information (looking at that item_ptr.ptr!). The only
out-param in the item is the length, so just copy that back?
-Chris


Done.

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Re: [Intel-gfx] [PATCH v5 6/6] drm/i915: expose rcs topology through query uAPI

[Chris Wilson]

Quoting Lionel Landwerlin (2018-01-16 13:40:10)
> With the introduction of asymmetric slices in CNL, we cannot rely on
> the previous SUBSLICE_MASK getparam to tell userspace what subslices
> are available. Here we introduce a more detailed way of querying the
> Gen's GPU topology that doesn't aggregate numbers.
> 
> This is essential for monitoring parts of the GPU with the OA unit,
> because counters need to be normalized to the number of
> EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
> not gives us sufficient information.
> 
> As a bonus we can draw representations of the GPU :
> 
> https://imgur.com/a/vuqpa
> 
> v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
> Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
> Add uapi macros to read data from *_info structs (Tvrtko)
> 
> v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts 
> (Tvrtko)
> 
> v4: factorize query item writting (Tvrtko)
> tweak uapi struct/define names (Tvrtko)
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/i915/i915_query.c | 107 
> ++
>  include/uapi/drm/i915_drm.h   |  53 +++
>  2 files changed, 160 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_query.c 
> b/drivers/gpu/drm/i915/i915_query.c
> index 5694cfea4553..4d18fbd07cbd 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -25,8 +25,102 @@
>  #include "i915_drv.h"
>  #include 
>  
> +static int copy_query_data(struct drm_i915_query_item *query_item,
> +  const void *item_ptr, u32 item_length,
> +  const void *data_ptr, u32 data_length)
> +{
> +   u32 total_length = item_length + data_length;
> +
> +   if (query_item->length == 0) {
> +   query_item->length = total_length;
> +   return 0;
> +   }
> +
> +   if (query_item->length != total_length)
> +   return -EINVAL;

Let the user pass in a preallocated buffer of a certain size, and only
have to resort to reallocating if too small. i.e.
if (query_item->length < total_length)
return -EINVAL;

> +
> +   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +item_ptr, item_length))
> +   return -EFAULT;
> +
> +   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length),
> +data_ptr, data_length))
> +   return -EFAULT;
> +
> +   return 0;
> +}
> +
> +static int query_slice_info(struct drm_i915_private *dev_priv,
> +   struct drm_i915_query_item *query_item)

> +static int query_subslice_info(struct drm_i915_private *dev_priv,
> +  struct drm_i915_query_item *query_item)

> +static int query_eu_info(struct drm_i915_private *dev_priv,
> +struct drm_i915_query_item *query_item)

Couldn't spot any stray leaks.

>  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
> *file)
>  {
> +   struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_i915_query *args = data;
> struct drm_i915_query_item __user *user_item_ptr =
> u64_to_user_ptr(args->items_ptr);
> @@ -34,15 +128,28 @@ int i915_query_ioctl(struct drm_device *dev, void *data, 
> struct drm_file *file)
>  
> for (i = 0; i < args->num_items; i++, user_item_ptr++) {
> struct drm_i915_query_item item;
> +   int ret;
>  
> if (copy_from_user(, user_item_ptr, sizeof(item)))
> return -EFAULT;
>  
> switch (item.query_id) {
> +   case DRM_I915_QUERY_SLICE_INFO:
> +   ret = query_slice_info(dev_priv, );
> +   break;
> +   case DRM_I915_QUERY_SUBSLICE_INFO:
> +   ret = query_subslice_info(dev_priv, );
> +   break;
> +   case DRM_I915_QUERY_EU_INFO:
> +   ret = query_eu_info(dev_priv, );
> +   break;
> default:
> return -EINVAL;
> }
>  
> +   if (ret)
> +   return ret;

I would make item const and return the copied length:
if (ret < 0)
return 0;

if (ret != item.length && put_user(ret, _item_ptr->length))
return -EFAULT;

> +#define DRM_I915_BIT(bit) (1 << (bit))

((__u32)1 << (bit))

Might as well prepare for that 32nd bit.

> +
> +/* Data written by the kernel with query DRM_I915_QUERY_ID_SLICES_INFO :
> + *
> + * data: each bit indicates whether a slice is available (1) or fused off 
> (0).
> + *   Use DRM_I915_QUERY_SLICE_AVAILABLE() to query a given slice's
> + *   availability.
> + */
> +struct drm_i915_query_slice_info {
> 

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_scaling: test scaling with tiling rotation and pixel formats, v3.

[Mika Kahola]

On Tue, 2018-01-16 at 15:00 +0100, Maarten Lankhorst wrote:
> From: Jyoti Yadav 
> 
> This patch adds subtest for testing scaling in combination with
> rotation
> and pixel formats.
> 
> Changes since v1:
> - Rework test to work with the other changes to kms_plane_scaling.
> (Maarten)
> - Remove hardcodes for MIN/MAX_SRC_WIDTH, and use the value directly.
> (Maarten)
> Changes since v2:
> - Put rotation and tiling in an array. (Maarten)
> 
> Signed-off-by: Jyoti Yadav 
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Vidya Srinivas 
> Signed-off-by: Maarten Lankhorst 
> ---
>  tests/kms_plane_scaling.c | 130
> +-
>  1 file changed, 129 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
> index a361a00face4..b5d31bbeb0f4 100644
> --- a/tests/kms_plane_scaling.c
> +++ b/tests/kms_plane_scaling.c
> @@ -60,6 +60,7 @@ static void cleanup_crtc(data_t *data)
>  {
>   int i;
>  
> + igt_display_reset(>display);
>   igt_pipe_crc_free(data->pipe_crc);
>   data->pipe_crc = NULL;
>  
> @@ -79,7 +80,6 @@ static void prepare_crtc(data_t *data, igt_output_t
> *output, enum pipe pipe,
>  
>   cleanup_crtc(data);
>  
> - igt_display_reset(display);
>   igt_output_set_pipe(output, pipe);
>  
>   /* create the pipe_crc object for this pipe */
> @@ -112,6 +112,125 @@ static void prepare_crtc(data_t *data,
> igt_output_t *output, enum pipe pipe,
>   igt_display_commit2(display, COMMIT_ATOMIC);
>  }
>  
> +static void paint_fb(data_t *d, struct igt_fb *fb)
> +{
> + cairo_t *cr;
> +
> + cr = igt_get_cairo_ctx(d->drm_fd, fb);
> + igt_paint_color(cr, 0, 0, fb->width, fb->height, 0.0, 1.0,
> 0.0);
> + igt_assert(cairo_status(cr) == 0);
> + cairo_destroy(cr);
> +}
> +
> +static void check_scaling_pipe_plane_rot(data_t *d, igt_plane_t
> *plane,
> +  uint32_t pixel_format,
> +  uint64_t tiling, enum pipe
> pipe,
> +  igt_output_t *output,
> +  igt_rotation_t rot)
> +{
> + igt_display_t *display = >display;
> + int width, height;
> + drmModeModeInfo *mode;
> +
> + cleanup_crtc(d);
> +
> + igt_output_set_pipe(output, pipe);
> + mode = igt_output_get_mode(output);
> +
> + /* create buffer in the range of  min and max source side
> limit.*/
> + width = height = 9;
> + igt_create_fb(display->drm_fd, width, height,
> +   pixel_format, tiling, >fb[0]);
> + paint_fb(d, >fb[0]);
> + igt_plane_set_fb(plane, >fb[0]);
> +
> + /* Check min to full resolution upscaling */
> + igt_fb_set_position(>fb[0], plane, 0, 0);
> + igt_fb_set_size(>fb[0], plane, width, height);
> + igt_plane_set_position(plane, 0, 0);
> + igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
> + igt_plane_set_rotation(plane, rot);
> + igt_display_commit2(display, COMMIT_ATOMIC);
> +
> + igt_plane_set_fb(plane, NULL);
> + igt_plane_set_position(plane, 0, 0);
> +}
> +
> +static const igt_rotation_t rotations[] = {
> + IGT_ROTATION_0,
> + IGT_ROTATION_90,
> + IGT_ROTATION_180,
> + IGT_ROTATION_270,
> +};
It's better this way so that we don't have to keep in sync
MAX_ROTATIONS and the actual rotation options.

Reviewed-by: Mika Kahola 

> +
> +static void test_scaler_with_rotation_pipe(data_t *d, enum pipe
> pipe,
> +    igt_output_t *output)
> +{
> + igt_display_t *display = >display;
> + igt_plane_t *plane;
> +
> + igt_output_set_pipe(output, pipe);
> + for_each_plane_on_pipe(display, pipe, plane) {
> + if (plane->type == DRM_PLANE_TYPE_CURSOR)
> + continue;
> +
> + for (int i = 0; i < ARRAY_SIZE(rotations); i++) {
> + igt_rotation_t rot = rotations[i];
> +
> + check_scaling_pipe_plane_rot(d, plane,
> DRM_FORMAT_XRGB,
> +  LOCAL_I915_FORM
> AT_MOD_Y_TILED,
> +  pipe, output,
> rot);
> + }
> + }
> +}
> +
> +static bool can_draw(uint32_t drm_format)
> +{
> + const uint32_t *drm_formats;
> + int format_count, i;
> +
> + igt_get_all_cairo_formats(_formats, _count);
> +
> + for (i = 0; i < format_count; i++)
> + if (drm_formats[i] == drm_format)
> + return true;
> +
> + return false;
> +}
> +
> +static const uint64_t tilings[] = {
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + LOCAL_I915_FORMAT_MOD_X_TILED,
> + LOCAL_I915_FORMAT_MOD_Y_TILED,
> + LOCAL_I915_FORMAT_MOD_Yf_TILED
> +};
> +
> +static void 

Re: [Intel-gfx] [PATCH v5 4/6] drm/i915: add rcs topology to error state

[Lionel Landwerlin]

On 16/01/18 13:57, Chris Wilson wrote:

Quoting Lionel Landwerlin (2018-01-16 13:40:08)

This might be useful information for developers looking at an error
state.

v2: Place topology towards the end of the error state (Chris)

v3: Reuse common printing code (Michal)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/i915_gpu_error.c | 9 +
  1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 944059322daa..aaa34a2bebe1 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -605,6 +605,14 @@ static void err_print_uc(struct drm_i915_error_state_buf 
*m,
 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
  }
  
+static void err_print_rcs_topology(struct drm_i915_error_state_buf *m,

+  const struct sseu_dev_info *sseu)
+{
+   struct drm_printer p = i915_error_printer(m);
+
+   intel_device_info_dump_topology(sseu, );
+}
+
  int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 const struct i915_gpu_state *error)
  {
@@ -787,6 +795,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
 intel_display_print_error_state(m, error->display);
  
 err_print_capabilities(m, >device_info);

+   err_print_rcs_topology(m, _INFO(dev_priv)->sseu);

Did we not acquire a copy of sseu via error->device_info above? Looks
like this would be a one-liner to print-caps.
-Chris


Sold.

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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] meson: Build cnl_compute_wrpll

[Patchwork]

== Series Details ==

Series: series starting with [1/4] meson: Build cnl_compute_wrpll
URL   : https://patchwork.freedesktop.org/series/36525/
State : failure

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614 +1
Test kms_rotation_crc:
Subgroup sprite-rotation-180-flip:
pass   -> SKIP   (shard-snb)
Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-cpu-untiled:
pass   -> SKIP   (shard-snb)
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218
Test drv_selftest:
Subgroup mock_fence:
pass   -> DMESG-FAIL (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218

shard-hswtotal:2686 pass:1521 dwarn:1   dfail:1   fail:10  skip:1152 
time:8771s
shard-snbtotal:2729 pass:1316 dwarn:1   dfail:0   fail:11  skip:1401 
time:7958s
Blacklisted hosts:
shard-apltotal:2729 pass:1698 dwarn:1   dfail:0   fail:24  skip:1006 
time:13656s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_781/shards.html
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Re: [Intel-gfx] [PATCH v5 5/6] drm/i915: add query uAPI

[Chris Wilson]

Quoting Lionel Landwerlin (2018-01-16 13:40:09)
> +int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file 
> *file)
> +{
> +   struct drm_i915_query *args = data;
> +   struct drm_i915_query_item __user *user_item_ptr =
> +   u64_to_user_ptr(args->items_ptr);
> +   u32 i;

You need to reject non-zero pad values. I would just rename them as
flags because that's almost always the first field added later on when
extending the ioctl.

> +
> +   for (i = 0; i < args->num_items; i++, user_item_ptr++) {
> +   struct drm_i915_query_item item;
> +
> +   if (copy_from_user(, user_item_ptr, sizeof(item)))
> +   return -EFAULT;
> +
> +   switch (item.query_id) {
> +   default:
> +   return -EINVAL;
> +   }
> +
> +   if (copy_to_user(user_item_ptr, , sizeof(item)))
> +   return -EFAULT;

I would suggest not doing a blind copy of the entire item. The majority
of it should be unchanged, but copying everything sounds like an easy
accident to leak information (looking at that item_ptr.ptr!). The only
out-param in the item is the length, so just copy that back?
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915: Add display WA #1175 for planes ending close to right screen edge

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915: Add display WA #1175 for planes 
ending close to right screen edge
URL   : https://patchwork.freedesktop.org/series/36526/
State : failure

== Summary ==

Test drv_selftest:
Subgroup mock_fence:
pass   -> DMESG-FAIL (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup flip-vs-fences-interruptible:
dmesg-warn -> PASS   (shard-hsw) fdo#102614
Subgroup vblank-vs-modeset-suspend:
pass   -> SKIP   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-pri-indfb-multidraw:
pass   -> SKIP   (shard-snb) fdo#103167
Test kms_plane:
Subgroup plane-panning-bottom-right-pipe-b-planes:
pass   -> SKIP   (shard-snb)
Test kms_atomic_transition:
Subgroup plane-all-modeset-transition-fencing:
pass   -> SKIP   (shard-snb)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test gem_eio:
Subgroup in-flight-contexts:
pass   -> DMESG-WARN (shard-snb) fdo#104058
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS   (shard-snb) fdo#104218

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218

shard-hswtotal:2729 pass:1548 dwarn:1   dfail:1   fail:9   skip:1170 
time:8971s
shard-snbtotal:2729 pass:1314 dwarn:2   dfail:0   fail:11  skip:1402 
time:7864s
Blacklisted hosts:
shard-apltotal:2653 pass:1649 dwarn:1   dfail:0   fail:19  skip:983 
time:13071s
shard-kbltotal:2729 pass:1814 dwarn:8   dfail:1   fail:25  skip:880 
time:10194s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7680/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915: Only attempt to scan the requested number of shrinker slabs (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [01/10] drm/i915: Only attempt to scan the 
requested number of shrinker slabs (rev4)
URL   : https://patchwork.freedesktop.org/series/36501/
State : success

== Summary ==

Series 36501v4 series starting with [01/10] drm/i915: Only attempt to scan the 
requested number of shrinker slabs
https://patchwork.freedesktop.org/api/1.0/series/36501/revisions/4/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> FAIL   (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-kbl-r) fdo#104172 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:486s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:0   fail:1   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:275s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:513s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:409s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:448s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:460s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:501s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-kbl-r total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:509s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:579s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:431s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:537s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:488s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:526s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:576s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:477s

a0ca279440c8d7c40d798fed9939a2a25b31434b drm-tip: 2018y-01m-16d-10h-49m-51s UTC 
integration manifest
fbbb7268251d drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list
6cfe09be420a drm/i915: Only signal from interrupt when requested
fbb4ac927391 drm/i915: Move the irq_counter inside the spinlock
433a1fc6d9f8 drm/i915: Reduce spinlock hold time during notify_ring() interrupt
52e71d9d2543 drm/i915/breadcrumbs: Drop request reference for the signaler 
thread
13914d7e2c16 drm/i915: Trim the retired request queue after submitting
d8622789b9c1 drm/i915: Shrink the request kmem_cache on allocation error
9b84813ac938 drm/i915: Shrink the GEM kmem_caches upon idling
31aa3e433b10 drm/i915: Move i915_gem_retire_work_handler
4ca65ba284ca drm/i915: Only attempt to scan the requested number of shrinker 
slabs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7682/issues.html
___
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[Intel-gfx] [PATCH i-g-t] tests/kms_plane_scaling: test scaling with tiling rotation and pixel formats, v3.

[Maarten Lankhorst]

From: Jyoti Yadav 

This patch adds subtest for testing scaling in combination with rotation
and pixel formats.

Changes since v1:
- Rework test to work with the other changes to kms_plane_scaling. (Maarten)
- Remove hardcodes for MIN/MAX_SRC_WIDTH, and use the value directly. (Maarten)
Changes since v2:
- Put rotation and tiling in an array. (Maarten)

Signed-off-by: Jyoti Yadav 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
Signed-off-by: Maarten Lankhorst 
---
 tests/kms_plane_scaling.c | 130 +-
 1 file changed, 129 insertions(+), 1 deletion(-)

diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index a361a00face4..b5d31bbeb0f4 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -60,6 +60,7 @@ static void cleanup_crtc(data_t *data)
 {
int i;
 
+   igt_display_reset(>display);
igt_pipe_crc_free(data->pipe_crc);
data->pipe_crc = NULL;
 
@@ -79,7 +80,6 @@ static void prepare_crtc(data_t *data, igt_output_t *output, 
enum pipe pipe,
 
cleanup_crtc(data);
 
-   igt_display_reset(display);
igt_output_set_pipe(output, pipe);
 
/* create the pipe_crc object for this pipe */
@@ -112,6 +112,125 @@ static void prepare_crtc(data_t *data, igt_output_t 
*output, enum pipe pipe,
igt_display_commit2(display, COMMIT_ATOMIC);
 }
 
+static void paint_fb(data_t *d, struct igt_fb *fb)
+{
+   cairo_t *cr;
+
+   cr = igt_get_cairo_ctx(d->drm_fd, fb);
+   igt_paint_color(cr, 0, 0, fb->width, fb->height, 0.0, 1.0, 0.0);
+   igt_assert(cairo_status(cr) == 0);
+   cairo_destroy(cr);
+}
+
+static void check_scaling_pipe_plane_rot(data_t *d, igt_plane_t *plane,
+uint32_t pixel_format,
+uint64_t tiling, enum pipe pipe,
+igt_output_t *output,
+igt_rotation_t rot)
+{
+   igt_display_t *display = >display;
+   int width, height;
+   drmModeModeInfo *mode;
+
+   cleanup_crtc(d);
+
+   igt_output_set_pipe(output, pipe);
+   mode = igt_output_get_mode(output);
+
+   /* create buffer in the range of  min and max source side limit.*/
+   width = height = 9;
+   igt_create_fb(display->drm_fd, width, height,
+ pixel_format, tiling, >fb[0]);
+   paint_fb(d, >fb[0]);
+   igt_plane_set_fb(plane, >fb[0]);
+
+   /* Check min to full resolution upscaling */
+   igt_fb_set_position(>fb[0], plane, 0, 0);
+   igt_fb_set_size(>fb[0], plane, width, height);
+   igt_plane_set_position(plane, 0, 0);
+   igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+   igt_plane_set_rotation(plane, rot);
+   igt_display_commit2(display, COMMIT_ATOMIC);
+
+   igt_plane_set_fb(plane, NULL);
+   igt_plane_set_position(plane, 0, 0);
+}
+
+static const igt_rotation_t rotations[] = {
+   IGT_ROTATION_0,
+   IGT_ROTATION_90,
+   IGT_ROTATION_180,
+   IGT_ROTATION_270,
+};
+
+static void test_scaler_with_rotation_pipe(data_t *d, enum pipe pipe,
+  igt_output_t *output)
+{
+   igt_display_t *display = >display;
+   igt_plane_t *plane;
+
+   igt_output_set_pipe(output, pipe);
+   for_each_plane_on_pipe(display, pipe, plane) {
+   if (plane->type == DRM_PLANE_TYPE_CURSOR)
+   continue;
+
+   for (int i = 0; i < ARRAY_SIZE(rotations); i++) {
+   igt_rotation_t rot = rotations[i];
+
+   check_scaling_pipe_plane_rot(d, plane, 
DRM_FORMAT_XRGB,
+
LOCAL_I915_FORMAT_MOD_Y_TILED,
+pipe, output, rot);
+   }
+   }
+}
+
+static bool can_draw(uint32_t drm_format)
+{
+   const uint32_t *drm_formats;
+   int format_count, i;
+
+   igt_get_all_cairo_formats(_formats, _count);
+
+   for (i = 0; i < format_count; i++)
+   if (drm_formats[i] == drm_format)
+   return true;
+
+   return false;
+}
+
+static const uint64_t tilings[] = {
+   LOCAL_DRM_FORMAT_MOD_NONE,
+   LOCAL_I915_FORMAT_MOD_X_TILED,
+   LOCAL_I915_FORMAT_MOD_Y_TILED,
+   LOCAL_I915_FORMAT_MOD_Yf_TILED
+};
+
+static void test_scaler_with_pixel_format_pipe(data_t *d, enum pipe pipe, 
igt_output_t *output)
+{
+   igt_display_t *display = >display;
+   igt_plane_t *plane;
+
+   igt_output_set_pipe(output, pipe);
+
+   for_each_plane_on_pipe(display, pipe, plane) {
+   if (plane->type == DRM_PLANE_TYPE_CURSOR)
+   continue;
+
+   for (int i = 0; i <