Re: [Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

[Nagaraju, Vathsala]

-Original Message-
From: Vivi, Rodrigo 
Sent: Friday, April 20, 2018 11:06 PM
To: Nagaraju, Vathsala 
Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran 

Subject: Re: [PATCH] drm/i915/psr : Add psr1 live status

On Fri, Apr 20, 2018 at 03:06:03PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju 
> 
> Prints live state of psr1.Extending the existing
> PSR2 live state function to cover psr1.
> 
> Tested on KBL with psr2 and psr1 panel.

Does it really work?

I mean... I heard DK complaining that any read to these MMIO in some gen9 
platforms were triggering the PSR exit or something like that. So, is this 
really reliable?

https://patchwork.freedesktop.org/patch/218153/ 
https://patchwork.freedesktop.org/patch/218154/
"Writes to pipe related registers will still cause HW to exit PSR."

Or it is one of those info that will misslead users to file non existent bugs?
Google used this heavily for psr2 status during video playback etc,  so far no 
has filed any non-existent bug using this interface.
This status is useful.
> 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> 
> Signed-off-by: Vathsala Nagaraju 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 68 
> -
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  2 files changed, 45 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index e0274f4..3056f04 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2580,25 +2580,42 @@ static int i915_guc_log_relay_release(struct inode 
> *inode, struct file *file)
>   .release = i915_guc_log_relay_release,  };
>  
> -static const char *psr2_live_status(u32 val) -{
> - static const char * const live_status[] = {
> - "IDLE",
> - "CAPTURE",
> - "CAPTURE_FS",
> - "SLEEP",
> - "BUFON_FW",
> - "ML_UP",
> - "SU_STANDBY",
> - "FAST_SLEEP",
> - "DEEP_SLEEP",
> - "BUF_ON",
> - "TG_ON"
> - };
> -
> - val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
> - if (val < ARRAY_SIZE(live_status))
> - return live_status[val];
> +static const char *psr_live_status(bool is_psr2_enabled, u32 val) {
> + if (is_psr2_enabled) {
> + static const char * const live_status[] = {
> + "IDLE",
> + "CAPTURE",
> + "CAPTURE_FS",
> + "SLEEP",
> + "BUFON_FW",
> + "ML_UP",
> + "SU_STANDBY",
> + "FAST_SLEEP",
> + "DEEP_SLEEP",
> + "BUF_ON",
> + "TG_ON"
> + };
> + val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> + EDP_PSR2_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + } else {
> + static const char * const live_status[] = {
> + "IDLE",
> + "SRDONACK",
> + "SRDENT",
> + "BUFOFF",
> + "BUFON",
> + "AUXACK",
> + "SRDOFFACK",
> + "SRDENT_ON",
> + };
> + val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> + EDP_PSR_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + }
>  
>   return "unknown";
>  }
> @@ -2611,6 +2628,7 @@ static int i915_edp_psr_status(struct seq_file *m, void 
> *data)
>   enum pipe pipe;
>   bool enabled = false;
>   bool sink_support;
> + u32 psr_status;
>  
>   if (!HAS_PSR(dev_priv))
>   return -ENODEV;
> @@ -2678,12 +2696,14 @@ static int i915_edp_psr_status(struct seq_file 
> *m, void *data)
>  
>   seq_printf(m, "Performance_Counter: %u\n", psrperf);
>   }
> - if (dev_priv->psr.psr2_enabled) {
> - u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>  
> - seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> -psr2, psr2_live_status(psr2));
> - }
> + psr_status = (dev_priv->psr.psr2_enabled) ? I915_READ(EDP_PSR2_STATUS) :
> + I915_READ(EDP_PSR_STATUS);
> + seq_printf(m, "EDP_PSR%s_STATUS: %x [%s]\n",
> +   dev_priv->psr.psr2_enabled ? "2" : "1",
> +   psr_status,
> +   psr_live_status(dev_priv->psr.psr2_enabled, psr_status));
> +
>   mutex_unlock(_priv->psr.lock);
>  
>   

Re: [Intel-gfx] [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake

[Botello Ortega, Luis]

Hi all:

We tested GLK DMC 1.04 FW in last week of September 2017, using the latest 
drm-tip version for that time (4.14.0-rc2) and according to our results we 
could declare this FW as acceptable and healthy to be used with kernel version 
4.14 . 
However, we cannot guarantee quality and healthy of this FW if it is used in 
top of current drm-tip kernel (4.17-rc0).

Best Regards
Luis Botello


-Original Message-
From: Srivatsa, Anusha 
Sent: Friday, April 20, 2018 1:30 PM
To: Vivi, Rodrigo ; Jani Nikula 
; Botello Ortega, Luis 
; Martinez Monroy, Elio 

Cc: Ian W MORRISON ; airl...@linux.ie; Greg KH 
; intel-gfx@lists.freedesktop.org; 
linux-ker...@vger.kernel.org; sta...@vger.kernel.org; 
dri-de...@lists.freedesktop.org; Wajdeczko, Michal 
Subject: RE: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake



>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, April 20, 2018 11:04 AM
>To: Jani Nikula 
>Cc: Srivatsa, Anusha ; Ian W MORRISON 
>; airl...@linux.ie; Greg KH 
>; intel-gfx@lists.freedesktop.org; linux- 
>ker...@vger.kernel.org; sta...@vger.kernel.org; dri- 
>de...@lists.freedesktop.org; Wajdeczko, Michal 
>
>Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for 
>Geminilake
>
>On Tue, Apr 17, 2018 at 12:02:52PM +0300, Jani Nikula wrote:
>> On Mon, 16 Apr 2018, "Srivatsa, Anusha"  wrote:
>> >>-Original Message-
>> >>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>> >>Sent: Wednesday, April 11, 2018 5:27 AM
>> >>To: Ian W MORRISON 
>> >>Cc: Vivi, Rodrigo ; Srivatsa, Anusha 
>> >>; Wajdeczko, Michal 
>> >>; Greg KH ; 
>> >>airl...@linux.ie; joonas.lahti...@linux.intel.com; 
>> >>linux-ker...@vger.kernel.org; sta...@vger.kernel.org; 
>> >>intel-gfx@lists.freedesktop.org; dri- de...@lists.freedesktop.org
>> >>Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE 
>> >>for Geminilake
>> >>
>> >>On Wed, 11 Apr 2018, Ian W MORRISON  wrote:
>> >>> 
>> >>>
>> 
>>  NAK on indiscriminate Cc: stable. There are zero guarantees that 
>>  older kernels will work with whatever firmware you throw at them.
>> 
>> >>>
>> >>> I included 'Cc: stable' so the patch would get added to the v4.16 
>> >>> and
>> >>> v4.15 kernels which I have tested with the patch. I found that 
>> >>> earlier kernels didn't support the 'linux-firmware' package 
>> >>> required to get wifi working on Intel's new Gemini Lake NUC.
>> >>
>> >>You realize that this patch should have nothing to do with wifi?
>> >>
>> >>Rodrigo, Anusha, if you think Cc: stable is appropriate, please 
>> >>indicate the specific versions of stable it is appropriate for.
>> >
>> > Hi Jani,
>> >
>> > The stable kernel version is 4.12 and beyond.
>> > It is appropriate to add the CC: stable in my opinion
>>
>> Who tested the firmware with v4.12 and later? We only have the CI 
>> results against *current* drm-tip. We don't even know about v4.16.
>>
>
>I understand your concerns, but the problem was that our old process 
>was a bit
>(lot?) messed and there was the unreliable time until the firmware 
>really lands on linux-firmware.git. So MODULE_FIRMWARE call was only 
>added after firmware was really there on firmware repository but it wasn't 
>about the testing.
>
>In other words, the bump version patch was merged after tested, but 
>MODULE_FIRMWARE was left behind because firmware blob took a while to 
>get pulled into linux-firmware.git and we end up forgetting to add it there.
>
>In my opinion it should be safe to add the MODULE_FIRMWARE there based 
>on the tests from when the version was bumped.

Luis, Elio, can you guys confirm that this firmware is tested and healthy? And 
also, give a tested-by to this patch please?

Thanks,
Anusha 
>> I'm not going to ack and take responsibility for the stable backports 
>> unless someone actually comes forward with credible Tested-bys.
>>
>> BR,
>> Jani.
>>
>>
>> >
>> > Anusha
>> >>BR,
>> >>Jani.
>> >>
>> >>>
>> 
>>  PS. How is this a "RESEND"? I haven't seen this before.
>> 
>> >>>
>> >>> It is a 'RESEND' for that very reason. I initially sent the patch 
>> >>> to the same people as a similar patch
>> >>> (https://patchwork.kernel.org/patch/10143637/) however after 
>> >>> realising this omitted required addresses I added them and resent 
>> >>> the
>patch.
>> >>>
>> >>> Best regards,
>> >>> Ian
>> >>
>> >>--
>> >>Jani Nikula, Intel Open Source Technology Center
>>
>> --
>> Jani Nikula, Intel Open Source 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/4] drm/i915/psr/skl+: Print information 
about what caused a PSR exit
URL   : https://patchwork.freedesktop.org/series/42058/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4073_full -> Patchwork_8769_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8769_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8769_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42058/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8769_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  SKIP -> PASS

igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render:
  shard-kbl:  PASS -> SKIP

igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
  shard-glk:  PASS -> SKIP +111

igt@kms_vblank@pipe-c-wait-forked-busy:
  shard-glk:  SKIP -> PASS +85


== Known issues ==

  Here are the changes found in Patchwork_8769_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#102887)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)

igt@kms_sysfs_edid_timing:
  shard-apl:  PASS -> WARN (fdo#100047)

igt@kms_vblank@pipe-a-accuracy-idle:
  shard-hsw:  PASS -> FAIL (fdo#102583)


 Possible fixes 

igt@gem_pwrite_pread@display-pwrite-blt-gtt_mmap-performance:
  shard-kbl:  DMESG-WARN (fdo#105602, fdo#103558) -> PASS

igt@kms_flip@2x-blocking-wf_vblank:
  shard-hsw:  FAIL (fdo#100368) -> PASS

igt@kms_setmode@basic:
  shard-glk:  FAIL (fdo#99912) -> PASS


  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing(1): shard-glkb 


== Build changes ==

* Linux: CI_DRM_4073 -> Patchwork_8769

  CI_DRM_4073: 071ca2e05b60374c8bcac11e181018dc12b101b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4443: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8769: f1c8e186effddd1bfd45adc03da70b5b9535f8ec @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4443: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8769/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/4] drm/i915/psr/skl+: Print information 
about what caused a PSR exit
URL   : https://patchwork.freedesktop.org/series/42058/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4073 -> Patchwork_8769 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42058/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8769 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-cfl-s3:  PASS -> FAIL (fdo#103928, fdo#100368)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


 Possible fixes 

igt@gem_exec_suspend@basic-s4-devices:
  fi-kbl-7500u:   DMESG-WARN (fdo#105128) -> PASS

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-cnl-psr: FAIL (fdo#103928, fdo#100368) -> PASS

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
  fi-cnl-psr: FAIL (fdo#103481) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-ivb-3520m:   DMESG-WARN (fdo#106084) -> PASS +1


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (35 -> 33) ==

  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4073 -> Patchwork_8769

  CI_DRM_4073: 071ca2e05b60374c8bcac11e181018dc12b101b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4443: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8769: f1c8e186effddd1bfd45adc03da70b5b9535f8ec @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4443: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

f1c8e186effd drm/i915/psr/cnl: Set y-coordinate as valid in SDP
60be21d471f0 drm/i915/debugfs: Print sink PSR status
e44dc65462c8 drm/i915/psr: Prevent PSR exit when a non-pipe related register is 
written
ac17ffd9158a drm/i915/psr/skl+: Print information about what caused a PSR exit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8769/issues.html
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Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.
> 
> Bspec: 7721 and 8042
> 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> Signed-off-by: José Roberto de Souza 
> ---
> 
> New patch in this series.
> 
>  drivers/gpu/drm/i915/intel_psr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 0938df48107a..c907282dc82d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -712,7 +712,8 @@ static void hsw_psr_enable_source(struct intel_dp 
> *intel_dp,
>   I915_WRITE(EDP_PSR_DEBUG,
>  EDP_PSR_DEBUG_MASK_MEMUP |
>  EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP);
> +EDP_PSR_DEBUG_MASK_LPSP |
> +EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);

What about only setting this bit before debugfs reads
and unseting it after that?


>   }
>  }
>  
> -- 
> 2.17.0
> 
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Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.

This seems a good idea indeed with the test case on perspective.

But it needs more tests to make sure it doesn't break
"Display WA #0884: all"

Or we might need to revert that patch before moving with this idea.

> 
> Bspec: 7721 and 8042
> 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> Signed-off-by: José Roberto de Souza 
> ---
> 
> New patch in this series.
> 
>  drivers/gpu/drm/i915/intel_psr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 0938df48107a..c907282dc82d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -712,7 +712,8 @@ static void hsw_psr_enable_source(struct intel_dp 
> *intel_dp,
>   I915_WRITE(EDP_PSR_DEBUG,
>  EDP_PSR_DEBUG_MASK_MEMUP |
>  EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP);
> +EDP_PSR_DEBUG_MASK_LPSP |
> +EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
>   }
>  }
>  
> -- 
> 2.17.0
> 
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/4] drm/i915/psr/skl+: Print information 
about what caused a PSR exit
URL   : https://patchwork.freedesktop.org/series/42058/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ac17ffd9158a drm/i915/psr/skl+: Print information about what caused a PSR exit
-:32: WARNING:LONG_LINE: line over 100 characters
#32: FILE: drivers/gpu/drm/i915/i915_reg.h:4103:
+#define PSR_EVENT(trans)   (trans == TRANSCODER_EDP ? 
_MMIO(_PSR_EVENT_TRANS_EDP) : _MMIO_PORT(trans, _PSR_EVENT_TRANS_A, 
_PSR_EVENT_TRANS_B))

-:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible 
side-effects?
#32: FILE: drivers/gpu/drm/i915/i915_reg.h:4103:
+#define PSR_EVENT(trans)   (trans == TRANSCODER_EDP ? 
_MMIO(_PSR_EVENT_TRANS_EDP) : _MMIO_PORT(trans, _PSR_EVENT_TRANS_A, 
_PSR_EVENT_TRANS_B))

total: 0 errors, 1 warnings, 1 checks, 86 lines checked
e44dc65462c8 drm/i915/psr: Prevent PSR exit when a non-pipe related register is 
written
60be21d471f0 drm/i915/debugfs: Print sink PSR status
f1c8e186effd drm/i915/psr/cnl: Set y-coordinate as valid in SDP

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[Intel-gfx] [PATCH v3 4/4] drm/i915/psr/cnl: Set y-coordinate as valid in SDP

[José Roberto de Souza]

This was my bad, spec says that the name of this bit is
'Y-coordinate valid' but the values for it is:
0: Include Y-coordinate valid eDP1.4a
1: Do not include Y-coordinate valid eDP 1.4
So not setting it.

BSpec: 7713

Cc: Rodrigo Vivi 
Reviewed-by: Dhinakaran Pandiyan 
Signed-off-by: José Roberto de Souza 
---

No changes since v2.

 drivers/gpu/drm/i915/intel_psr.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c907282dc82d..7b928eb9ad35 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -508,9 +508,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 * good enough. */
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
-   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
-   val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
-   }
+   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+   val |= EDP_Y_COORDINATE_ENABLE;
 
val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-- 
2.17.0

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[Intel-gfx] [PATCH v3 1/4] drm/i915/psr/skl+: Print information about what caused a PSR exit

[José Roberto de Souza]

This will be helpful to debug what hardware is actually tracking
and causing PSR to exit.

BSpec: 7721

Signed-off-by: José Roberto de Souza 
Cc: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
---

New patch in this series.

 drivers/gpu/drm/i915/i915_reg.h  | 23 
 drivers/gpu/drm/i915/intel_psr.c | 45 
 2 files changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dad655a710c..073b4502b30a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4095,6 +4095,29 @@ enum {
 #define   EDP_PSR2_IDLE_FRAME_MASK 0xf
 #define   EDP_PSR2_IDLE_FRAME_SHIFT0
 
+#define _PSR_EVENT_TRANS_A 0x60848
+#define _PSR_EVENT_TRANS_B 0x61848
+#define _PSR_EVENT_TRANS_C 0x62848
+#define _PSR_EVENT_TRANS_D 0x63848
+#define _PSR_EVENT_TRANS_EDP   0x6F848
+#define PSR_EVENT(trans)   (trans == TRANSCODER_EDP ? 
_MMIO(_PSR_EVENT_TRANS_EDP) : _MMIO_PORT(trans, _PSR_EVENT_TRANS_A, 
_PSR_EVENT_TRANS_B))
+#define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE(1 << 17)
+#define  PSR_EVENT_PSR2_DISABLED   (1 << 16)
+#define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN  (1 << 15)
+#define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN(1 << 14)
+#define  PSR_EVENT_GRAPHICS_RESET  (1 << 12)
+#define  PSR_EVENT_PCH_INTERRUPT   (1 << 11)
+#define  PSR_EVENT_MEMORY_UP   (1 << 10)
+#define  PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
+#define  PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
+#define  PSR_EVENT_PIPE_REGISTERS_UPDATE   (1 << 6)
+#define  PSR_EVENT_REGISTER_UPDATE (1 << 5)
+#define  PSR_EVENT_HDCP_ENABLE (1 << 4)
+#define  PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
+#define  PSR_EVENT_VBI_ENABLE  (1 << 2)
+#define  PSR_EVENT_LPSP_MODE_EXIT  (1 << 1)
+#define  PSR_EVENT_PSR_DISABLE (1 << 0)
+
 #define EDP_PSR2_STATUS_MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
 #define EDP_PSR2_STATUS_STATE_SHIFT28
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0d548292dd09..0938df48107a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -125,6 +125,43 @@ void intel_psr_irq_control(struct drm_i915_private 
*dev_priv, bool debug)
I915_WRITE(EDP_PSR_IMR, ~mask);
 }
 
+static void psr_event_print(u32 val, bool psr2_enabled)
+{
+   DRM_DEBUG_KMS("PSR exit causes: 0x%x\n", val);
+   if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
+   DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
+   if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
+   DRM_DEBUG_KMS("\tPSR2 disabled\n");
+   if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
+   DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
+   if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
+   DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
+   if (val & PSR_EVENT_GRAPHICS_RESET)
+   DRM_DEBUG_KMS("\tGraphics reset\n");
+   if (val & PSR_EVENT_PCH_INTERRUPT)
+   DRM_DEBUG_KMS("\tPCH interrupt\n");
+   if (val & PSR_EVENT_MEMORY_UP)
+   DRM_DEBUG_KMS("\tMemory up\n");
+   if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
+   DRM_DEBUG_KMS("\tFront buffer modification\n");
+   if (val & PSR_EVENT_WD_TIMER_EXPIRE)
+   DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");
+   if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
+   DRM_DEBUG_KMS("\tPIPE registers updated\n");
+   if (val & PSR_EVENT_REGISTER_UPDATE)
+   DRM_DEBUG_KMS("\tRegister updated\n");
+   if (val & PSR_EVENT_HDCP_ENABLE)
+   DRM_DEBUG_KMS("\tHDCP enabled\n");
+   if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
+   DRM_DEBUG_KMS("\tKVMR session enabled\n");
+   if (val & PSR_EVENT_VBI_ENABLE)
+   DRM_DEBUG_KMS("\tVBI enabled\n");
+   if (val & PSR_EVENT_LPSP_MODE_EXIT)
+   DRM_DEBUG_KMS("\tLPSP mode exited\n");
+   if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
+   DRM_DEBUG_KMS("\tPSR disabled\n");
+}
+
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 {
u32 transcoders = BIT(TRANSCODER_EDP);
@@ -152,6 +189,14 @@ void intel_psr_irq_handler(struct drm_i915_private 
*dev_priv, u32 psr_iir)
dev_priv->psr.last_exit = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
  transcoder_name(cpu_transcoder));
+
+   if (INTEL_GEN(dev_priv) >= 9) {
+   u32 val = 

[Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written

[José Roberto de Souza]

Any write in any display register was causing HW to exit PSR,
masking it to allow more power savings. Writes to pipe related
registers will still cause HW to exit PSR.
This is already masked for PSR2.

Bspec: 7721 and 8042

Cc: Rodrigo Vivi 
Cc: Dhinakaran Pandiyan 
Signed-off-by: José Roberto de Souza 
---

New patch in this series.

 drivers/gpu/drm/i915/intel_psr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0938df48107a..c907282dc82d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -712,7 +712,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
I915_WRITE(EDP_PSR_DEBUG,
   EDP_PSR_DEBUG_MASK_MEMUP |
   EDP_PSR_DEBUG_MASK_HPD |
-  EDP_PSR_DEBUG_MASK_LPSP);
+  EDP_PSR_DEBUG_MASK_LPSP |
+  EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
}
 }
 
-- 
2.17.0

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[Intel-gfx] [PATCH v3 3/4] drm/i915/debugfs: Print sink PSR status

[José Roberto de Souza]

IGT tests could be improved with sink status, knowing for sure that
hardware have activate or exit PSR.

Reviewed-by: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---

No changes since v2, Dhinakaran asked to not merge this patch in v2
because reading i915_edp_psr_status was causing PSR to exit but now
with 'drm/i915/psr: Prevent PSR exit when a non-pipe related register
is written' it is fixed.

 drivers/gpu/drm/i915/i915_debugfs.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2f05f5262bba..536d93322451 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
return "unknown";
 }
 
+static const char *psr_sink_status(u8 val)
+{
+   static const char * const sink_status[] = {
+   "inactive",
+   "transition to active, capture and display",
+   "active, display from RFB",
+   "active, capture and display on sink device timings",
+   "transition to inactive, capture and display, timing re-sync",
+   "reserved",
+   "reserved",
+   "sink internal error"
+   };
+
+   val &= DP_PSR_SINK_STATE_MASK;
+   if (val < ARRAY_SIZE(sink_status))
+   return sink_status[val];
+
+   return "unknown";
+}
+
 static int i915_edp_psr_status(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
   psr2, psr2_live_status(psr2));
}
+
+   if (dev_priv->psr.enabled) {
+   struct drm_dp_aux *aux = _priv->psr.enabled->aux;
+   u8 val;
+
+   if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, ) == 1)
+   seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
+  psr_sink_status(val));
+   }
mutex_unlock(_priv->psr.lock);
 
if (READ_ONCE(dev_priv->psr.debug)) {
-- 
2.17.0

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Re: [Intel-gfx] [PATCH v4] drm/i915: Enable edp psr error interrupts on hsw

[Rodrigo Vivi]

On Tue, Apr 17, 2018 at 01:01:39PM -0700, Dhinakaran Pandiyan wrote:
> 
> 
> 
> On Tue, 2018-04-17 at 20:41 +0300, Ville Syrjälä wrote:
> > On Mon, Apr 16, 2018 at 05:43:54PM -0700, Paulo Zanoni wrote:
> > > Em Qui, 2018-04-05 às 15:00 -0700, Dhinakaran Pandiyan escreveu:
> > > > From: Daniel Vetter 
> > > > 
> > > > The definitions for the error register should be valid on bdw/skl
> > > > too,
> > > > but there we haven't even enabled DE_MISC handling yet.
> > > > 
> > > > Somewhat confusing the the moved register offset on bdw is only for
> > > > the _CTL/_AUX register, and that _IIR/IMR stayed where they have been
> > > > on bdw.
> > > > 
> > > > v2: Fixes from Ville.
> > > > 
> > > > v3: From DK
> > > >  * Rebased on drm-tip
> > > >  * Removed BDW IIR bit definition, looks like an unintentional change
> > > > that
> > > > should be in the following patch.
> > > > 
> > > > v4: From DK
> > > >  * Don't mask REG_WRITE.
> > > > 
> > > > References: bspec/11974 [SRD Interrupt Bit Definition DevHSW]
> > > > Cc: Ville Syrjälä 
> > > > Cc: Rodrigo Vivi 
> > > > Cc: Daniel Vetter 
> > > > Signed-off-by: Daniel Vetter 
> > > > Signed-off-by: Dhinakaran Pandiyan 
> > > > Reviewed-by: Jose Roberto de Souza 
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_irq.c | 34
> > > > ++
> > > >  drivers/gpu/drm/i915/i915_reg.h |  8 
> > > >  2 files changed, 42 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > index 27aee25429b7..c2d3f30778ee 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > @@ -2391,6 +2391,26 @@ static void ilk_display_irq_handler(struct
> > > > drm_i915_private *dev_priv,
> > > > ironlake_rps_change_irq_handler(dev_priv);
> > > >  }
> > > >  
> > > > +static void hsw_edp_psr_irq_handler(struct drm_i915_private
> > > > *dev_priv)
> > > > +{
> > > > +   u32 edp_psr_iir = I915_READ(EDP_PSR_IIR);
> > > > +
> > > > +   if (edp_psr_iir & EDP_PSR_ERROR)
> > > > +   DRM_DEBUG_KMS("PSR error\n");
> > > > +
> > > > +   if (edp_psr_iir & EDP_PSR_PRE_ENTRY) {
> > > > +   DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n");
> > > > +   I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY);
> > > 
> > > Why are we masking it here? During these 2 vblanks it's possible that
> > > something will happen (e.g., frontbuffer writing, cursor moving, page
> > > flipping).
> > 
> > The masking was here to avoid seeing a big flood of entry interrupts.
> > 
> > > Are we guaranteed to get a POST_EXIT interrupt even if we
> > > give up entering PSR before it is actually entered?
> > 
> > No. The exit interrupt only happens if you actually reached PSR.
> > 
> > > 
> > > 
> > > > +   }
> > > > +
> > > > +   if (edp_psr_iir & EDP_PSR_POST_EXIT) {
> > > > +   DRM_DEBUG_KMS("PSR exit completed\n");
> > > > +   I915_WRITE(EDP_PSR_IMR, 0);
> > > > +   }
> > > > +
> > > > +   I915_WRITE(EDP_PSR_IIR, edp_psr_iir);
> > > > +}
> > > > +
> > > >  static void ivb_display_irq_handler(struct drm_i915_private
> > > > *dev_priv,
> > > > u32 de_iir)
> > > >  {
> > > > @@ -2403,6 +2423,9 @@ static void ivb_display_irq_handler(struct
> > > > drm_i915_private *dev_priv,
> > > > if (de_iir & DE_ERR_INT_IVB)
> > > > ivb_err_int_handler(dev_priv);
> > > >  
> > > > +   if (de_iir & DE_EDP_PSR_INT_HSW)
> > > > +   hsw_edp_psr_irq_handler(dev_priv);
> > > > +
> > > > if (de_iir & DE_AUX_CHANNEL_A_IVB)
> > > > dp_aux_irq_handler(dev_priv);
> > > >  
> > > > @@ -3260,6 +3283,11 @@ static void ironlake_irq_reset(struct
> > > > drm_device *dev)
> > > > if (IS_GEN7(dev_priv))
> > > > I915_WRITE(GEN7_ERR_INT, 0x);
> > > >  
> > > > +   if (IS_HASWELL(dev_priv)) {
> > > > +   I915_WRITE(EDP_PSR_IMR, 0x);
> > > > +   I915_WRITE(EDP_PSR_IIR, 0x);
> > > > +   }
> > > 
> > > We need another IIR write we do for the other platforms. This is not
> > > cargo cult (as mentioned in previous review emails), this is required
> > > since our hardware is able to store more than one IIR interrupt. Please
> > > do it like we do for the other interrupts.
> > 
> 
> My reply and the review were specifically about the POSTING_READ(). I
> agree on the second IIR write, but that was not what the original review
> comment was about.
> 
> I'm still skeptical about inserting the POSTING_READ() between write's
> There are at commit messages and emails that indicate the
> POSTING_READS() are indeed cargo culted. Let me find more data about
> this and get back.
> 
> > I don't 

Re: [Intel-gfx] [PATCH] gpu: drm: i915: Change return type to vm_fault_t

[Rodrigo Vivi]

On Wed, Apr 18, 2018 at 08:46:44AM +0300, Jani Nikula wrote:
> On Tue, 17 Apr 2018, Souptick Joarder  wrote:
> > On 17-Apr-2018 9:45 PM, "Matthew Wilcox"  wrote:
> >>
> >> On Tue, Apr 17, 2018 at 09:14:32PM +0530, Souptick Joarder wrote:
> >> > Not exactly. The plan for these patches is to introduce new vm_fault_t
> > type
> >> > in vm_operations_struct fault handlers. It's now available in 4.17-rc1.
> > We will
> >> > push all the required drivers/filesystem changes through different
> > maintainers
> >> > to linus tree. Once everything is converted into vm_fault_t type then
> > Changing
> >> > it from a signed to an unsigned int causes GCC to warn about an
> > assignment
> >> > from an incompatible type -- int foo(void) is incompatible with
> >> > unsigned int foo(void).
> >> >
> >> > Please refer 1c8f422059ae ("mm: change return type to vm_fault_t") in
> > 4.17-rc1.
> >>
> >> I think this patch would be clearer if you did
> >>
> >> -   int ret;
> >> +   int err;
> >> +   vm_fault_t ret;
> >>
> >> Then it would be clearer to the maintainer that you're splitting apart the
> >> VM_FAULT and errno codes.
> >>
> >> Sorry for not catching this during initial review.
> >
> > Ok, I will make required changes and send v2. Sorry, even I missed this :)
> 
> I'm afraid Daniel is closer to the truth.

+1.

> My bad, sorry for the noise.

I opened this thread to add exactly question/noise ;).

So my recommendation for some next time is to make the intention clear
on the commit message itself from the begin.

> 
> BR,
> Jani.
> 
> 
> 
> >>
> >> > On Tue, Apr 17, 2018 at 8:59 PM, Jani Nikula
> >> >  wrote:
> >> > > On Tue, 17 Apr 2018, Souptick Joarder  wrote:
> >> > >> Use new return type vm_fault_t for fault handler. For
> >> > >> now, this is just documenting that the function returns
> >> > >> a VM_FAULT value rather than an errno. Once all instances
> >> > >> are converted, vm_fault_t will become a distinct type.
> >> > >>
> >> > >> Reference id -> 1c8f422059ae ("mm: change return type to
> >> > >> vm_fault_t")
> >> > >>
> >> > >> Signed-off-by: Souptick Joarder 
> >> > >> ---
> >> > >>  drivers/gpu/drm/i915/i915_drv.h |  3 ++-
> >> > >>  drivers/gpu/drm/i915/i915_gem.c | 15 ---
> >> > >>  2 files changed, 10 insertions(+), 8 deletions(-)
> >> > >>
> >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> >> > >> index a42deeb..95b0d50 100644
> >> > >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> > >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> > >> @@ -51,6 +51,7 @@
> >> > >>  #include 
> >> > >>  #include 
> >> > >>  #include 
> >> > >> +#include 
> >> > >>
> >> > >>  #include "i915_params.h"
> >> > >>  #include "i915_reg.h"
> >> > >> @@ -3363,7 +3364,7 @@ int i915_gem_wait_for_idle(struct
> > drm_i915_private *dev_priv,
> >> > >>  unsigned int flags);
> >> > >>  int __must_check i915_gem_suspend(struct drm_i915_private
> > *dev_priv);
> >> > >>  void i915_gem_resume(struct drm_i915_private *dev_priv);
> >> > >> -int i915_gem_fault(struct vm_fault *vmf);
> >> > >> +vm_fault_t i915_gem_fault(struct vm_fault *vmf);
> >> > >>  int i915_gem_object_wait(struct drm_i915_gem_object *obj,
> >> > >>unsigned int flags,
> >> > >>long timeout,
> >> > >> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> >> > >> index dd89abd..bdac690 100644
> >> > >> --- a/drivers/gpu/drm/i915/i915_gem.c
> >> > >> +++ b/drivers/gpu/drm/i915/i915_gem.c
> >> > >> @@ -1882,7 +1882,7 @@ int i915_gem_mmap_gtt_version(void)
> >> > >>   * The current feature set supported by i915_gem_fault() and thus
> > GTT mmaps
> >> > >>   * is exposed via I915_PARAM_MMAP_GTT_VERSION (see
> > i915_gem_mmap_gtt_version).
> >> > >>   */
> >> > >> -int i915_gem_fault(struct vm_fault *vmf)
> >> > >> +vm_fault_t i915_gem_fault(struct vm_fault *vmf)
> >> > >>  {
> >> > >>  #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
> >> > >>   struct vm_area_struct *area = vmf->vma;
> >> > >> @@ -1895,6 +1895,7 @@ int i915_gem_fault(struct vm_fault *vmf)
> >> > >>   pgoff_t page_offset;
> >> > >>   unsigned int flags;
> >> > >>   int ret;
> >> > >> + vm_fault_t retval;
> >> > >
> >> > > What's the point of changing the name? An unnecessary change.
> >> > >
> >> > > BR,
> >> > > Jani.
> >> > >
> >> > >>
> >> > >>   /* We don't use vmf->pgoff since that has the fake offset */
> >> > >>   page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
> >> > >> @@ -2000,7 +2001,7 @@ int i915_gem_fault(struct vm_fault *vmf)
> >> > >>* and so needs to be reported.
> >> > >>*/
> >> > >>   if (!i915_terminally_wedged(_priv->gpu_error)) {
> >> > >> - ret = VM_FAULT_SIGBUS;
> >> > >> + 

[Intel-gfx] ✓ Fi.CI.IGT: success for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8768_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8768_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8768_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8768_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  SKIP -> PASS +1

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  PASS -> SKIP

igt@kms_busy@extended-modeset-hang-oldfb-render-a:
  shard-glk:  PASS -> SKIP +76

igt@kms_vblank@pipe-b-wait-forked-busy-hang:
  shard-glk:  SKIP -> PASS +104


== Known issues ==

  Here are the changes found in Patchwork_8768_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_schedule@wide-bsd2:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558)

igt@gem_ppgtt@blt-vs-render-ctxn:
  shard-kbl:  PASS -> INCOMPLETE (fdo#106023, fdo#103665)

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-hsw:  PASS -> FAIL (fdo#102887)

igt@kms_flip@flip-vs-expired-vblank:
  shard-hsw:  PASS -> FAIL (fdo#105707)


 Possible fixes 

igt@kms_flip@dpms-vs-vblank-race-interruptible:
  shard-glk:  FAIL (fdo#103060) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS
  shard-glk:  FAIL (fdo#100368) -> PASS +1

igt@kms_sysfs_edid_timing:
  shard-apl:  WARN (fdo#100047) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023


== Participating hosts (6 -> 5) ==

  Missing(1): shard-glkb 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8768

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8768: b3e83155f6333c0a9db115f82db0290028c52055 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8768/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Use mmio access to context status buffer

[Rodrigo Vivi]

On Thu, Apr 12, 2018 at 05:58:02PM +0300, Mika Kuoppala wrote:
> Evidence indicates that Cannonlake HWSP is not coherent
> as it should. Revert to using mmio access for now.
> 
> Testcase: igt/gem_ctx_switch
> References: https://bugs.freedesktop.org/show_bug.cgi?id=105888
> Cc: Chris Wilson 
> Cc: Rafael Antognolli 
> Cc: Rodrigo Vivi 
> Signed-off-by: Mika Kuoppala 

Acked-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 68898d58dd1e..1a8370779bbb 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -475,6 +475,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
>   if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
>   return true;
>  
> + if (IS_CANNONLAKE(i915))
> + return true;
> +
>   return false;
>  }
>  
> -- 
> 2.14.1
> 
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Re: [Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 02:29:27PM -0700, Oscar Mateo wrote:
> 
> 
> On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
> > > 
> > > On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
> > > > On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> > > > > Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> > > > > power by dynamically changing its clock frequency in low-throughput
> > > > > conditions. This patches enables it by default on Gen11.
> > > > > 
> > > > > v2: Wrong operation to clear the bit (Praveen)
> > > > > v3: Rebased on top of the WA refactoring
> > > > > 
> > > > > Cc: Praveen Paneri 
> > > > > Cc: Mika Kuoppala 
> > > > > Signed-off-by: Oscar Mateo 
> > > > > Reviewed-by: Sagar Arun Kamble 
> > > > > ---
> > > > >drivers/gpu/drm/i915/i915_reg.h  | 3 +++
> > > > >drivers/gpu/drm/i915/intel_workarounds.c | 4 
> > > > >2 files changed, 7 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index f2ee225..4b7e6bc 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -8218,6 +8218,9 @@ enum {
> > > > >#define GEN8_GARBCNTL   _MMIO(0xB004)
> > > > >#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
> > > > > +#define GEN10_DFR_RATIO_EN_AND_CHICKEN   _MMIO(0x9550)
> > > > > +#define   DFR_DISABLE(1 << 9)
> > > > > +
> > > > >/* IVYBRIDGE DPF */
> > > > >#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) 
> > > > > * 0x200) /* L3CD Error Status 1 */
> > > > >#define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
> > > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
> > > > > b/drivers/gpu/drm/i915/intel_workarounds.c
> > > > > index 3f00623..60a5b1d 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > > > > @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
> > > > > drm_i915_private *dev_priv)
> > > > >   I915_WRITE(_3D_CHICKEN3,
> > > > >  
> > > > > _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> > > > > + /* This is not an Wa. Enable to reduce Sampler power */
> > > > First of all it is strange that a feature is under a chicken bit,
> > > There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE
> > Oh, true!
> > 
> > Actually that never got same question from me because that
> > function is called init clock gating, although this function nowadays
> > is basically workarounds related to clock gatings :/)
> > 
> > > > but if it is not an wa, but a PM feature, shouldn't we add it to some 
> > > > sort of
> > > > init clock gating function, or a new specific function called when it 
> > > > makes sense?
> > > I'm open to suggestions
> > moving to clock gating is an option?
> > or needs to be called from context?
> 
> No, moving it to init_clock_gating is definitely an option. It is not truly
> related to clock gating, but at least it is related to Power Management...
> (the _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE thing is more difficult to
> swallow...)

I agree hehe... my bad... :$

> 
> > > > > + I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> > > > > +(I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & 
> > > > > ~DFR_DISABLE));
> > > > > +
> > > > >   /* WaInPlaceDecompressionHang:icl */
> > > > >   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, 
> > > > > (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> > > > >
> > > > > GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> > > > > -- 
> > > > > 1.9.1
> > > > > 
> > > > > ___
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> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > ___
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> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

[Rodrigo Vivi]

On Tue, Apr 10, 2018 at 11:29:09AM -0700, Dhinakaran Pandiyan wrote:
> 
> 
> 
> On Tue, 2018-04-10 at 10:59 -0700, Rodrigo Vivi wrote:
> > On Tue, Apr 10, 2018 at 12:49:25AM -, Patchwork wrote:
> > > == Series Details ==
> > > 
> > > Series: series starting with [v4] drm/i915: Enable edp psr error 
> > > interrupts on hsw (rev3)
> > > URL   : https://patchwork.freedesktop.org/series/41095/
> > > State : warning
> > > 
> > > == Summary ==
> > > 
> > > $ dim checkpatch origin/drm-tip
> > > 0a22dbbae8f8 drm/i915: Enable edp psr error interrupts on hsw
> > > -:111: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
> > > #111: FILE: drivers/gpu/drm/i915/i915_reg.h:4032:
> > > +#define   EDP_PSR_ERROR  (1<<2)
> > > ^
> > > 
> > > -:112: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
> > > #112: FILE: drivers/gpu/drm/i915/i915_reg.h:4033:
> > > +#define   EDP_PSR_POST_EXIT  (1<<1)
> > > ^
> > > 
> > > -:113: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
> > > #113: FILE: drivers/gpu/drm/i915/i915_reg.h:4034:
> > > +#define   EDP_PSR_PRE_ENTRY  (1<<0)
> > > ^
> > > 
> > > -:122: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
> > > #122: FILE: drivers/gpu/drm/i915/i915_reg.h:6847:
> > > +#define DE_EDP_PSR_INT_HSW   (1<<19)
> > > ^
> > > 
> > > total: 0 errors, 0 warnings, 4 checks, 78 lines checked
> > > 7fdf2eed9ed4 drm/i915: Enable edp psr error interrupts on bdw+
> > > -:159: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed 
> > > in parentheses
> > > #159: FILE: drivers/gpu/drm/i915/intel_display.h:221:
> > > +#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
> > > + for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
> > > + for_each_if ((__mask) & (1 << (__t)))
> > 
> > This showed up on red on dim when I was going to push here...
> > 
> > DK, could you please address this one here before we can push?
> > 
> 
> The macros look correct to me, that is how other macros are written too.
> check_patch is confused?

Well, you are right. New macro is just like the other for_each_*

If we need a clean we can do that later, or silent dim on that...

Anyways, pushed this patches to dinq.

Thanks for patches, reviews, patience and extra checks ;)

> 
> > Thanks,
> > Rodrigo.
> > 
> > > 
> > > -:159: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__t' - possible 
> > > side-effects?
> > > #159: FILE: drivers/gpu/drm/i915/intel_display.h:221:
> > > +#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
> > > + for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
> > > + for_each_if ((__mask) & (1 << (__t)))
> > > 
> > > -:160: CHECK:SPACING: No space is necessary after a cast
> > > #160: FILE: drivers/gpu/drm/i915/intel_display.h:222:
> > > + for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
> > > 
> > > -:161: WARNING:SPACING: space prohibited between function name and open 
> > > parenthesis '('
> > > #161: FILE: drivers/gpu/drm/i915/intel_display.h:223:
> > > + for_each_if ((__mask) & (1 << (__t)))
> > > 
> > > total: 1 errors, 1 warnings, 2 checks, 123 lines checked
> > > 003ec0005027 drm/i915/psr: Control PSR interrupts via debugfs
> > > d8186b823b62 drm/i915/psr: Timestamps for PSR entry and exit interrupts.
> > > 
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> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Re: [Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:

On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:


On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:

On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Praveen Paneri 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
Reviewed-by: Sagar Arun Kamble 
---
   drivers/gpu/drm/i915/i915_reg.h  | 3 +++
   drivers/gpu/drm/i915/intel_workarounds.c | 4 
   2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@ enum {
   #define GEN8_GARBCNTL   _MMIO(0xB004)
   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define   DFR_DISABLE  (1 << 9)
+
   /* IVYBRIDGE DPF */
   #define GEN7_L3CDERRST1(slice)   _MMIO(0xB008 + (slice) * 0x200) 
/* L3CD Error Status 1 */
   #define   GEN7_L3CDERRST1_ROW_MASK   (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3f00623..60a5b1d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+   /* This is not an Wa. Enable to reduce Sampler power */

First of all it is strange that a feature is under a chicken bit,

There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE

Oh, true!

Actually that never got same question from me because that
function is called init clock gating, although this function nowadays
is basically workarounds related to clock gatings :/)


but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
init clock gating function, or a new specific function called when it makes 
sense?

I'm open to suggestions

moving to clock gating is an option?
or needs to be called from context?


No, moving it to init_clock_gating is definitely an option. It is not 
truly related to clock gating, but at least it is related to Power 
Management... (the _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE thing is more 
difficult to swallow...)



+   I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+  (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
|
 
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
--
1.9.1

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Re: [Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
> 
> 
> On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> > > Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> > > power by dynamically changing its clock frequency in low-throughput
> > > conditions. This patches enables it by default on Gen11.
> > > 
> > > v2: Wrong operation to clear the bit (Praveen)
> > > v3: Rebased on top of the WA refactoring
> > > 
> > > Cc: Praveen Paneri 
> > > Cc: Mika Kuoppala 
> > > Signed-off-by: Oscar Mateo 
> > > Reviewed-by: Sagar Arun Kamble 
> > > ---
> > >   drivers/gpu/drm/i915/i915_reg.h  | 3 +++
> > >   drivers/gpu/drm/i915/intel_workarounds.c | 4 
> > >   2 files changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index f2ee225..4b7e6bc 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8218,6 +8218,9 @@ enum {
> > >   #define GEN8_GARBCNTL   _MMIO(0xB004)
> > >   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
> > > +#define GEN10_DFR_RATIO_EN_AND_CHICKEN   _MMIO(0x9550)
> > > +#define   DFR_DISABLE(1 << 9)
> > > +
> > >   /* IVYBRIDGE DPF */
> > >   #define GEN7_L3CDERRST1(slice)  _MMIO(0xB008 + (slice) * 0x200) 
> > > /* L3CD Error Status 1 */
> > >   #define   GEN7_L3CDERRST1_ROW_MASK  (0x7ff<<14)
> > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
> > > b/drivers/gpu/drm/i915/intel_workarounds.c
> > > index 3f00623..60a5b1d 100644
> > > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > > @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
> > > drm_i915_private *dev_priv)
> > >   I915_WRITE(_3D_CHICKEN3,
> > >  
> > > _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> > > + /* This is not an Wa. Enable to reduce Sampler power */
> > First of all it is strange that a feature is under a chicken bit,
> 
> There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE

Oh, true!

Actually that never got same question from me because that
function is called init clock gating, although this function nowadays
is basically workarounds related to clock gatings :/)

> 
> > but if it is not an wa, but a PM feature, shouldn't we add it to some sort 
> > of
> > init clock gating function, or a new specific function called when it makes 
> > sense?
> 
> I'm open to suggestions

moving to clock gating is an option?
or needs to be called from context?

> 
> > > + I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> > > +(I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> > > +
> > >   /* WaInPlaceDecompressionHang:icl */
> > >   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, 
> > > (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> > >
> > > GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> > > -- 
> > > 1.9.1
> > > 
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Re: [Intel-gfx] [PATCH v2 6/9] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side

[Rodrigo Vivi]

On Wed, Apr 18, 2018 at 03:43:08PM -0700, José Roberto de Souza wrote:
> Sink can be configured to calculate the CRC over the static frame and
> compare with the CRC calculated and transmited in the VSC SDP by
> source, if there is a mismatch sink will do a short pulse in HPD
> and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.

good idea, but first we need to stop using sink crc for the tests :(

and make sure the interrupts are being handled correct...

(I was going to mention an extra requirement that was to make sure
that you implement the needed Wa, but I noticed you already took care
of this)

> 
> Also spec recommends to disable MAX_SLEEP as a trigger to exit PSR when
> CRC check is enabled to improve power savings.

my first impression was that this should be a separated patch
in case we needed to revert it doesn't revert both functionalities...

however I saw this was Display WA #0388 with a mention:
"This becomes standard required programming for all subsequent projects."

so yeah, it belongs here. Maybe good to at least referrence this wa number.

> 
> Spec: 7723
> 
> Signed-off-by: José Roberto de Souza 
> Cc: Dhinakaran Pandiyan 
> Cc: Rodrigo Vivi 
> ---
> 
> Changes from v1:
> - printing a debug message when sink assert a error
> 
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 24 +---
>  2 files changed, 18 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb106026a1f4..d3efbd654889 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4016,6 +4016,7 @@ enum {
>  #define   EDP_PSR_SKIP_AUX_EXIT  (1<<12)
>  #define   EDP_PSR_TP1_TP2_SEL(0<<11)
>  #define   EDP_PSR_TP1_TP3_SEL(1<<11)
> +#define   EDP_PSR_CRC_ENABLE (1<<10) /* BDW+ */
>  #define   EDP_PSR_TP2_TP3_TIME_500us (0<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_100us (1<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_2500us(2<<8)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 558b08a43f9e..1920e7d03e06 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -290,6 +290,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>   dpcd_val |= DP_PSR_ENABLE_PSR2;
>   if (dev_priv->psr.link_standby)
>   dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> + if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>  
>   drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
> @@ -377,6 +379,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>   else
>   val |= EDP_PSR_TP1_TP2_SEL;
>  
> + if (INTEL_GEN(dev_priv) >= 8)
> + val |= EDP_PSR_CRC_ENABLE;
> +
>   val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
>   I915_WRITE(EDP_PSR_CTL, val);
>  }
> @@ -602,10 +607,12 @@ static void hsw_psr_enable_source(struct intel_dp 
> *intel_dp,
>* preventing  other hw tracking issues now we can rely
>* on frontbuffer tracking.
>*/
> - I915_WRITE(EDP_PSR_DEBUG,
> -EDP_PSR_DEBUG_MASK_MEMUP |
> -EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP);
> + u32 val = EDP_PSR_DEBUG_MASK_MEMUP | EDP_PSR_DEBUG_MASK_HPD
> +   | EDP_PSR_DEBUG_MASK_LPSP;
> +
> + if (INTEL_GEN(dev_priv) >= 8)
> + val |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> + I915_WRITE(EDP_PSR_DEBUG, val);
>   }
>  }
>  
> @@ -1161,14 +1168,17 @@ void intel_psr_hpd_short_pulse_handle(struct intel_dp 
> *intel_dp)
>   goto dpcd_error;
>   }
>  
> - if (val & DP_PSR_RFB_STORAGE_ERROR) {
> - DRM_DEBUG_KMS("PSR RFB storage error, exiting PSR\n");
> + if (val & (DP_PSR_RFB_STORAGE_ERROR | DP_PSR_LINK_CRC_ERROR)) {
> + if (val & DP_PSR_RFB_STORAGE_ERROR)
> + DRM_DEBUG_KMS("PSR RFB storage error, exiting PSR\n");
> + if (val & DP_PSR_LINK_CRC_ERROR)
> + DRM_DEBUG_KMS("PSR Link CRC error, exiting PSR\n");
>   intel_psr_exit(dev_priv);
>   }
>   /* clear status register */
>   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS, val);
>  
> - /* TODO: handle other PSR/PSR2 errors */
> + /* TODO: handle PSR2 errors */
>  dpcd_error:
>   intel_psr_schedule_activate_work(dev_priv);
>  not_enabled:
> -- 
> 2.17.0
> 
> ___
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> 

[Intel-gfx] ✓ Fi.CI.BAT: success for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8768 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8768 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@debugfs_test@read_all_entries:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)

igt@drv_module_reload@basic-no-display:
  fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2

igt@gem_exec_suspend@basic-s4-devices:
  fi-kbl-7500u:   PASS -> DMESG-WARN (fdo#105128)

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-ivb-3520m:   DMESG-WARN (fdo#106084) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (33 -> 33) ==

  Additional (2): fi-kbl-7560u fi-cnl-psr 
  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8768

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8768: b3e83155f6333c0a9db115f82db0290028c52055 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

b3e83155f633 drm/i915/icl: WaAllowUMDToModifySamplerMode
3c8350e7a85b drm/i915/icl: WaAllowUmdWriteTRTTRootTable
a506e91880c4 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
cfbc51ef5c4a drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
1afd609b2026 drm/i915/icl: WaSendPushConstantsFromMMIO
6416305b9e4a drm/i915/icl: WaEnableFloatBlendOptimization
8e678b2a3d72 drm/i915/icl: Wa_2006665173
d397ada30a53 drm/i915/icl: WaEnableStateCacheRedirectToCS
7ddbeb426ced drm/i915/icl: WaDisableImprovedTdlClkGating
c4772140f55f drm/i915/icl: WaForwardProgressSoftReset
9702c4288bac drm/i915/icl: Wa_1406838659
be63d1d1ad53 drm/i915/icl: Wa_1604302699
4adc5c7395a1 drm/i915/icl: Wa_1406680159 and Wa_2201832410
ed2ec7a07267 drm/i915/icl: Wa_1405779004
816ee27c52c2 drm/i915/icl: WaDisCtxReload
614afb61f95c drm/i915/icl: WaCL2SFHalfMaxAlloc
bd0addeea3e4 drm/i915/icl: WaDisableCleanEvicts
f4c1b4bb9090 drm/i915/icl: WaModifyGamTlbPartitioning
363ae679b17f drm/i915/icl: WaL3BankAddressHashing
64f72e593847 drm/i915/icl: WaGAPZPriorityScheme
5ee197f360ed drm/i915/icl: Enable Sampler DFR
abf7b0421b03 drm/i915/icl: Introduce initial Icelake Workarounds

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8768/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Introduce initial Icelake Workarounds
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3656:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3665:16: warning: expression 
using sizeof(void)

Commit: drm/i915/icl: Enable Sampler DFR
Okay!

Commit: drm/i915/icl: WaGAPZPriorityScheme
Okay!

Commit: drm/i915/icl: WaL3BankAddressHashing
Okay!

Commit: drm/i915/icl: WaModifyGamTlbPartitioning
Okay!

Commit: drm/i915/icl: WaDisableCleanEvicts
Okay!

Commit: drm/i915/icl: WaCL2SFHalfMaxAlloc
Okay!

Commit: drm/i915/icl: WaDisCtxReload
Okay!

Commit: drm/i915/icl: Wa_1405779004
Okay!

Commit: drm/i915/icl: Wa_1406680159 and Wa_2201832410
Okay!

Commit: drm/i915/icl: Wa_1604302699
Okay!

Commit: drm/i915/icl: Wa_1406838659
Okay!

Commit: drm/i915/icl: WaForwardProgressSoftReset
Okay!

Commit: drm/i915/icl: WaDisableImprovedTdlClkGating
Okay!

Commit: drm/i915/icl: WaEnableStateCacheRedirectToCS
Okay!

Commit: drm/i915/icl: Wa_2006665173
Okay!

Commit: drm/i915/icl: WaEnableFloatBlendOptimization
Okay!

Commit: drm/i915/icl: WaSendPushConstantsFromMMIO
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
Okay!

Commit: drm/i915/icl: WaAllowUmdWriteTRTTRootTable
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifySamplerMode
Okay!

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] agp/intel-gtt: Drop the code for gen > 1

[Adam Jackson]

On Fri, 2018-04-20 at 20:20 +, Patchwork wrote:

>  Possible regressions 
> 
> igt@drv_module_reload@basic-no-display:
>   fi-elk-e7500:   PASS -> DMESG-FAIL +2
> 
> igt@drv_module_reload@basic-reload:
>   fi-gdg-551: PASS -> DMESG-FAIL +2
>   fi-blb-e6850:   PASS -> DMESG-FAIL +2
>   fi-ilk-650: PASS -> DMESG-FAIL +2
> 
> igt@drv_module_reload@basic-reload-inject:
>   fi-bwr-2160:PASS -> DMESG-FAIL +2

Fun, apparently that code isn't purely gen1. Feel free to ignore this
series.

- ajax
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
abf7b0421b03 drm/i915/icl: Introduce initial Icelake Workarounds
-:48: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#48: FILE: drivers/gpu/drm/i915/i915_drv.h:2471:
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 155 lines checked
5ee197f360ed drm/i915/icl: Enable Sampler DFR
64f72e593847 drm/i915/icl: WaGAPZPriorityScheme
363ae679b17f drm/i915/icl: WaL3BankAddressHashing
f4c1b4bb9090 drm/i915/icl: WaModifyGamTlbPartitioning
bd0addeea3e4 drm/i915/icl: WaDisableCleanEvicts
614afb61f95c drm/i915/icl: WaCL2SFHalfMaxAlloc
816ee27c52c2 drm/i915/icl: WaDisCtxReload
ed2ec7a07267 drm/i915/icl: Wa_1405779004
4adc5c7395a1 drm/i915/icl: Wa_1406680159 and Wa_2201832410
be63d1d1ad53 drm/i915/icl: Wa_1604302699
9702c4288bac drm/i915/icl: Wa_1406838659
c4772140f55f drm/i915/icl: WaForwardProgressSoftReset
7ddbeb426ced drm/i915/icl: WaDisableImprovedTdlClkGating
d397ada30a53 drm/i915/icl: WaEnableStateCacheRedirectToCS
8e678b2a3d72 drm/i915/icl: Wa_2006665173
6416305b9e4a drm/i915/icl: WaEnableFloatBlendOptimization
1afd609b2026 drm/i915/icl: WaSendPushConstantsFromMMIO
cfbc51ef5c4a drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
a506e91880c4 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
3c8350e7a85b drm/i915/icl: WaAllowUmdWriteTRTTRootTable
b3e83155f633 drm/i915/icl: WaAllowUMDToModifySamplerMode

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Re: [Intel-gfx] [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:49:45PM -0700, Oscar Mateo wrote:
> 
> 
> On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
> > > Disable GWL clock gating to prevent two different issues that
> > > might cause hangs.
> > > 
> > > Please notice that one of the issues is pre-production only.
> > > 
> > > v2: Rebased on top of the WA refactoring
> > > 
> > > Cc: Mika Kuoppala 
> > > Signed-off-by: Oscar Mateo 
> > > ---
> > >   drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
> > >   1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
> > > b/drivers/gpu/drm/i915/intel_workarounds.c
> > > index 50d5507..2c792d7 100644
> > > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > > @@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct 
> > > drm_i915_private *dev_priv)
> > >   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> > >  (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> > >   MSCUNIT_CLKGATE_DIS));
> > > +
> > > + /* Wa_1406680159:icl */
> > > + /* Wa_2201832410:icl (pre-prod, only until C0) */
> > what about adding the REVID checks?
> > 
> > but, well, why one is pre-prod and other is forever?
> 
> That's the thing: this is the same workaround for two different HW problems.
> One is fixed post-C0, but the other is not, so I cannot add REVID checks :(

Oh of course... Makes sense. Thanks ;)

> 
> > 
> > > + I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
> > > +(I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
> > > + GWUNIT_CLKGATE_DIS));
> > >   }
> > >   void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> > > -- 
> > > 1.9.1
> > > 
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> ___
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Re: [Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:

On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Praveen Paneri 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
Reviewed-by: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
  drivers/gpu/drm/i915/intel_workarounds.c | 4 
  2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@ enum {
  #define GEN8_GARBCNTL   _MMIO(0xB004)
  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
  
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)

+#define   DFR_DISABLE  (1 << 9)
+
  /* IVYBRIDGE DPF */
  #define GEN7_L3CDERRST1(slice)_MMIO(0xB008 + (slice) * 0x200) 
/* L3CD Error Status 1 */
  #define   GEN7_L3CDERRST1_ROW_MASK(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3f00623..60a5b1d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
  
+	/* This is not an Wa. Enable to reduce Sampler power */

First of all it is strange that a feature is under a chicken bit,


There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE


but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
init clock gating function, or a new specific function called when it makes 
sense?


I'm open to suggestions


+   I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+  (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
|
 
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
--
1.9.1

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Re: [Intel-gfx] [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Oscar Mateo]

On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:

On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:

Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
  drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 50d5507..2c792d7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS));
+
+   /* Wa_1406680159:icl */
+   /* Wa_2201832410:icl (pre-prod, only until C0) */

what about adding the REVID checks?

but, well, why one is pre-prod and other is forever?


That's the thing: this is the same workaround for two different HW 
problems. One is fixed post-C0, but the other is not, so I cannot add 
REVID checks :(





+   I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+  (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+   GWUNIT_CLKGATE_DIS));
  }
  
  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)

--
1.9.1

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Re: [Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> power by dynamically changing its clock frequency in low-throughput
> conditions. This patches enables it by default on Gen11.
> 
> v2: Wrong operation to clear the bit (Praveen)
> v3: Rebased on top of the WA refactoring
> 
> Cc: Praveen Paneri 
> Cc: Mika Kuoppala 
> Signed-off-by: Oscar Mateo 
> Reviewed-by: Sagar Arun Kamble 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
>  drivers/gpu/drm/i915/intel_workarounds.c | 4 
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f2ee225..4b7e6bc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8218,6 +8218,9 @@ enum {
>  #define GEN8_GARBCNTL   _MMIO(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>  
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN   _MMIO(0x9550)
> +#define   DFR_DISABLE(1 << 9)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)   _MMIO(0xB008 + (slice) * 0x200) 
> /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK   (0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 3f00623..60a5b1d 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
> drm_i915_private *dev_priv)
>   I915_WRITE(_3D_CHICKEN3,
>  _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>  
> + /* This is not an Wa. Enable to reduce Sampler power */

First of all it is strange that a feature is under a chicken bit,
but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
init clock gating function, or a new specific function called when it makes 
sense?

> + I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +(I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> +
>   /* WaInPlaceDecompressionHang:icl */
>   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
> |
>
> GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
> Disable GWL clock gating to prevent two different issues that
> might cause hangs.
> 
> Please notice that one of the issues is pre-production only.
> 
> v2: Rebased on top of the WA refactoring
> 
> Cc: Mika Kuoppala 
> Signed-off-by: Oscar Mateo 
> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 50d5507..2c792d7 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct 
> drm_i915_private *dev_priv)
>   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
>  (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
>   MSCUNIT_CLKGATE_DIS));
> +
> + /* Wa_1406680159:icl */
> + /* Wa_2201832410:icl (pre-prod, only until C0) */

what about adding the REVID checks?

but, well, why one is pre-prod and other is forever?

> + I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
> +(I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
> + GWUNIT_CLKGATE_DIS));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
> 
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[Intel-gfx] [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

[Oscar Mateo]

Required to dinamically set 'Trilinear Filter Quality Mode'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index ba2ba63..120e703 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -904,6 +904,9 @@ static void icl_whitelist_build(struct whitelist *w)
 
/* WaAllowUMDToModifyHalfSliceChicken2:icl */
whitelist_reg(w, HALF_SLICE_CHICKEN2);
+
+   /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+   whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[Intel-gfx] [PATCH 09/22] drm/i915/icl: Wa_1405779004

[Oscar Mateo]

Disable MSC clock gating to prevent data corruption.

BSpec: 19257

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 161d04e..9ab5731 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum {
 #define SLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS  (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS   (1 << 7)
+#define  MSCUNIT_CLKGATE_DIS   (1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
 #define  GWUNIT_CLKGATE_DIS(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index dd7f0bd..50d5507 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
+   /* Wa_1405779004:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+  (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+   MSCUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 11/22] drm/i915/icl: Wa_1604302699

[Oscar Mateo]

Disable I2M Write for performance reasons.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 +++-
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ab5731..b462938 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,7 +7192,9 @@ enum {
 #define GEN7_L3CNTLREG3_MMIO(0xB024)
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER  _MMIO(0xB030)
-#define  GEN7_WA_L3_CHICKEN_MODE   0x2000
+#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
+#define  GEN7_WA_L3_CHICKEN_MODE   0x2000
+#define  GEN11_I2M_WRITE_DISABLE   (1 << 28)
 
 #define GEN7_L3SQCREG4 _MMIO(0xb034)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE   (1<<27)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 2c792d7..2364749 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -757,6 +757,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
GWUNIT_CLKGATE_DIS));
+
+   /* Wa_1604302699:icl */
+   I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+  (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+   GEN11_I2M_WRITE_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 08/22] drm/i915/icl: WaDisCtxReload

[Oscar Mateo]

Revert to the legacy implementation to avoid a system hang.

v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43fdd2e..161d04e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8238,6 +8238,9 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
+#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
+#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a0fbcf7..dd7f0bd 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
   
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
+
+   /* Wa_220166154:icl
+* Formerly known as WaDisCtxReload
+*/
+   I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+   GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Oscar Mateo]

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  |  6 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 20 
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6b1f85..5637cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,12 @@ enum {
 #define GEN8_GARBCNTL  _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0(1 << 0)
+
+#define GEN11_GLBLINVL _MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0   (1 << 0)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK   (0x3f << 5)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index ffd27a1..83a53cc 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-   /* Wa_1405543622:icl
-* Formerly known as WaGAPZPriorityScheme
+   I915_WRITE(GEN8_GARBCNTL,
+  /* Wa_1604223664:icl
+   * Formerly known as WaL3BankAddressHashing
+   */
+  ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+   GEN11_HASH_CTRL_EXCL_BIT0 |
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+   /* Wa_1604223664:icl
+* Formerly known as WaL3BankAddressHashing
 */
-   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-  GEN11_ARBITRATION_PRIO_ORDER_MASK));
+   I915_WRITE(GEN11_GLBLINVL,
+  ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+   GEN11_BANK_HASH_ADDR_EXCL_BIT0));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Praveen Paneri 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@ enum {
 #define GEN8_GARBCNTL   _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define   DFR_DISABLE  (1 << 9)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3f00623..60a5b1d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
+   /* This is not an Wa. Enable to reduce Sampler power */
+   I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+  (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
|
 
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-- 
1.9.1

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[Intel-gfx] [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

[Oscar Mateo]

Required to dinamically set 'Small PL Lossless Fix Enable'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index be49c12..ba2ba63 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -901,6 +901,9 @@ static void icl_whitelist_build(struct whitelist *w)
 {
/* WaSendPushConstantsFromMMIO:icl */
whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+   /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+   whitelist_reg(w, HALF_SLICE_CHICKEN2);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[Intel-gfx] [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating

[Oscar Mateo]

Revert to the legacy implementation.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Rebased
  - Renamed to Wa_2006611047
  - A0 and B0 only
v4:
  - Add spaces around '<<' (and fix the surrounding code as well)
  - Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfb9b0d..fca143b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8284,8 +8284,9 @@ enum {
 
 #define GEN7_ROW_CHICKEN2  _MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2  _MMIO(0xf4f4)
-#define   DOP_CLOCK_GATING_DISABLE (1<<0)
-#define   PUSH_CONSTANT_DEREF_DISABLE  (1<<8)
+#define   DOP_CLOCK_GATING_DISABLE (1 << 0)
+#define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index beb98c6..26a77da 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct 
drm_i915_private *dev_priv)
 */
WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
 
+   /* Wa_2006611047:icl (pre-prod)
+* Formerly known as WaDisableImprovedTdlClkGating
+*/
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Oscar Mateo]

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fea85ac..43fdd2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8234,6 +8234,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index efa885c..a0fbcf7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -732,6 +732,13 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization

[Oscar Mateo]

Enables blend optimization for floating point RTs

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 71696dc..127d2a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2663,6 +2663,9 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1<<6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1<<1)
 
+#define GEN10_CACHE_MODE_SS_MMIO(0xe420)
+#define   FLOAT_BLEND_OPTIMIZATION_ENABLE  (1 << 4)
+
 #define GEN6_BLITTER_ECOSKPD   _MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT  16
 #define   GEN6_BLITTER_FBC_NOTIFY  (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 6ca0958..5abd531 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -475,6 +475,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private 
*dev_priv)
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
+   /* WaEnableFloatBlendOptimization:icl */
+   WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme

[Oscar Mateo]

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622

v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b7e6bc..a6b1f85 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8215,8 +8215,9 @@ enum {
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE   (1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
 
-#define GEN8_GARBCNTL   _MMIO(0xB004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN8_GARBCNTL  _MMIO(0xB004)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 60a5b1d..ffd27a1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -703,6 +703,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
/* WaPipelineFlushCoherentLines:icl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+  GEN11_ARBITRATION_PRIO_ORDER_MASK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode

[Oscar Mateo]

Required for Bindless samplers.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: Rebased on top of the WA refactoring (Michel)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d008a70..3394cc0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8258,6 +8258,8 @@ enum {
 #define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
 
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index b32caf6..5965dae 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -911,6 +911,9 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUmdWriteTRTTRootTable:icl */
whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
+
+   /* WaAllowUMDToModifySamplerMode:icl */
+   whitelist_reg(w, GEN10_SAMPLER_MODE);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[Intel-gfx] [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Oscar Mateo]

Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 50d5507..2c792d7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS));
+
+   /* Wa_1406680159:icl */
+   /* Wa_2201832410:icl (pre-prod, only until C0) */
+   I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+  (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+   GWUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Oscar Mateo]

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c |  2 ++
 drivers/gpu/drm/i915/intel_pm.c  |  4 ++-
 drivers/gpu/drm/i915/intel_uncore.c  |  7 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 46 
 7 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0286911..1dc157f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 029901a..2d6572a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
 
switch (INTEL_GEN(engine->i915)) {
+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..3b7d804 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-   if 

[Intel-gfx] [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO

[Oscar Mateo]

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...

v2: Rebased
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the WA whitelist reg refactoring (Michel)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5abd531..be49c12 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -899,6 +899,8 @@ static void cnl_whitelist_build(struct whitelist *w)
 
 static void icl_whitelist_build(struct whitelist *w)
 {
+   /* WaSendPushConstantsFromMMIO:icl */
+   whitelist_reg(w, COMMON_SLICE_CHICKEN2);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[Intel-gfx] [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

[Oscar Mateo]

Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 127d2a3..d008a70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8255,6 +8255,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 120e703..b32caf6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -907,6 +907,10 @@ static void icl_whitelist_build(struct whitelist *w)
 
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+   /* WaAllowUmdWriteTRTTRootTable:icl */
+   whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
+   whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

[Oscar Mateo]

Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5637cd7..fe35785 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8228,6 +8228,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 83a53cc..e8d14a7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -721,6 +721,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GLBLINVL,
   ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH v4 00/22] Workarounds for Icelake

[Oscar Mateo]

List of GT workarounds for Icelake that we have been carrying in internal.
Can we get eyes on these please?

Oscar Mateo (22):
  drm/i915/icl: Introduce initial Icelake Workarounds
  drm/i915/icl: Enable Sampler DFR
  drm/i915/icl: WaGAPZPriorityScheme
  drm/i915/icl: WaL3BankAddressHashing
  drm/i915/icl: WaModifyGamTlbPartitioning
  drm/i915/icl: WaDisableCleanEvicts
  drm/i915/icl: WaCL2SFHalfMaxAlloc
  drm/i915/icl: WaDisCtxReload
  drm/i915/icl: Wa_1405779004
  drm/i915/icl: Wa_1406680159 and Wa_2201832410
  drm/i915/icl: Wa_1604302699
  drm/i915/icl: Wa_1406838659
  drm/i915/icl: WaForwardProgressSoftReset
  drm/i915/icl: WaDisableImprovedTdlClkGating
  drm/i915/icl: WaEnableStateCacheRedirectToCS
  drm/i915/icl: Wa_2006665173
  drm/i915/icl: WaEnableFloatBlendOptimization
  drm/i915/icl: WaSendPushConstantsFromMMIO
  drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
  drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
  drm/i915/icl: WaAllowUmdWriteTRTTRootTable
  drm/i915/icl: WaAllowUMDToModifySamplerMode

 drivers/gpu/drm/i915/i915_drv.h  |   9 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c  |   4 +-
 drivers/gpu/drm/i915/i915_reg.h  |  85 +
 drivers/gpu/drm/i915/intel_lrc.c |   2 +
 drivers/gpu/drm/i915/intel_pm.c  |   4 +-
 drivers/gpu/drm/i915/intel_uncore.c  |   7 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 157 +++
 7 files changed, 245 insertions(+), 23 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH 16/22] drm/i915/icl: Wa_2006665173

[Oscar Mateo]

Disable blend embellishment in RCC.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 18 +++---
 drivers/gpu/drm/i915/intel_workarounds.c |  5 +
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 452e24d..71696dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7157,13 +7157,17 @@ enum {
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE(1<<14)
-#define COMMON_SLICE_CHICKEN2  _MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION(1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE  (1<<0)
+  #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC((1 << 10) | (1 << 26))
+  #define GEN9_RHWO_OPTIMIZATION_DISABLE   (1 << 14)
+
+#define COMMON_SLICE_CHICKEN2  _MMIO(0x7014)
+  #define GEN9_PBE_COMPRESSED_HASH_SELECTION   (1 << 13)
+  #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE   (1 << 12)
+  #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
+  #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC   (1 << 11)
 
 #define HIZ_CHICKEN_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 7ad9454..6ca0958 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -470,6 +470,11 @@ static int icl_ctx_workarounds_init(struct 
drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
  GEN11_STATE_CACHE_REDIRECT_TO_CS);
 
+   /* Wa_2006665173:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

[Oscar Mateo]

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 4 
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fca143b..452e24d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7173,6 +7173,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
 
 #define GEN7_L3SQCREG1 _MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 26a77da..7ad9454 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -466,6 +466,10 @@ static int icl_ctx_workarounds_init(struct 
drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+   /* WaEnableStateCacheRedirectToCS:icl */
+   WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset

[Oscar Mateo]

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 8 
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc09b83..cfb9b0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9711,6 +9711,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers 
*/
 #define GEN9_BLT_MOCS(i)   _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS 
registers */
 
+#define GEN10_SCRATCH_LNCF2_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP   (1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK (1 << 21)
+#define   PMFLUSHDONE_LNEBLK   (1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for 
LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a9868e9..beb98c6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -768,6 +768,14 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
CGPSF_CLKGATE_DIS));
+
+   /* WaForwardProgressSoftReset:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   I915_WRITE(GEN10_SCRATCH_LNCF2,
+  (I915_READ(GEN10_SCRATCH_LNCF2) |
+   PMFLUSHDONE_LNICRSDROP |
+   PMFLUSH_GAPL3UNBLOCK |
+   PMFLUSHDONE_LNEBLK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts

[Oscar Mateo]

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe35785..fea85ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7197,8 +7197,9 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE   (1<<27)
 
 #define GEN8_L3SQCREG4 _MMIO(0xb118)
-#define  GEN8_LQSC_RO_PERF_DIS (1<<27)
-#define  GEN8_LQSC_FLUSH_COHERENT_LINES(1<<21)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE(1 << 6)
+#define  GEN8_LQSC_RO_PERF_DIS (1 << 27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES(1 << 21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index e8d14a7..efa885c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GACB_PERF_CTRL,
   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+   /* Wa_1405733216:icl
+* Formerly known as WaDisableCleanEvicts
+*/
+   I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+   GEN11_LQSC_CLEAN_EVICT_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 12/22] drm/i915/icl: Wa_1406838659

[Oscar Mateo]

Disable CGPSF unit clock gating to prevent an issue.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 13 -
 drivers/gpu/drm/i915/intel_workarounds.c |  6 ++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b462938..fc09b83 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3838,15 +3838,18 @@ enum {
  * GEN10 clock gating regs
  */
 #define SLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x94d4)
-#define  SARBUNIT_CLKGATE_DIS  (1 << 5)
-#define  RCCUNIT_CLKGATE_DIS   (1 << 7)
-#define  MSCUNIT_CLKGATE_DIS   (1 << 10)
+#define   SARBUNIT_CLKGATE_DIS (1 << 5)
+#define   RCCUNIT_CLKGATE_DIS  (1 << 7)
+#define   MSCUNIT_CLKGATE_DIS  (1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
-#define  GWUNIT_CLKGATE_DIS(1 << 16)
+#define   GWUNIT_CLKGATE_DIS   (1 << 16)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS(1 << 20)
+#define   VFUNIT_CLKGATE_DIS   (1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
+#define   CGPSF_CLKGATE_DIS(1 << 3)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 2364749..a9868e9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -762,6 +762,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
GEN11_I2M_WRITE_DISABLE));
+
+   /* Wa_1406838659:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+   I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+  (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+   CGPSF_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [Intel-gfx] [PATCH] drm/i915: Wait for vblank after register read

[Dhinakaran Pandiyan]

On Fri, 2018-04-20 at 11:15 -0700, Rodrigo Vivi wrote:
> On Thu, Apr 19, 2018 at 10:03:05AM +0300, Mika Kahola wrote:
> > On Thu, 2018-04-19 at 09:11 +0300, Lofstedt, Marta wrote:
> > > For the PW results: 
> > > https://patchwork.freedesktop.org/series/41877/
> > > 
> > > it didn't fix the CRC mismatch on:
> > >  https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8731/shard-
> > > snb6/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
> > This was expected that removing one vblank doesn't fix have an effect
> > on crc mismatches. Theres something more in this issue.
> > 
> > > 
> > > but that test has always failed on SNB: 
> > > http://gfx-ci.fi.intel.com/cibuglog/?action_failures_history=-1
> > > res_test=igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-
> > > multidraw_machine=shard-snb
> > > 
> > > so I don't think you brake anything with this patch.
> > > 
> > > Mika, do you know if waiting for the extra vblank was done with some
> > > purpose?
> > That I don't know if it was intentional. I'll try to find out why it
> > was needed.
> 
> sink CRC calculation starts on the next active frame and takes a full
> frame to finish the calculation. So 2 vblanks before the result is ready.
> 
> I don't believe we should move it for after reading it.
> 
> But it is a fact that this sink crc was always only a headache.
> If we manage to move PSR tests to use the interrupts and status bits only
> than we will be able to kill this sink crc code entirely
Yup.

Patch has nothing to do with the bug that it is trying to fix. The test
doesn't read sink-crc's, so I don't think even a References tag is
appropriate here.



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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] agp/intel-gtt: Drop the code for gen > 1

[Patchwork]

== Series Details ==

Series: series starting with [1/2] agp/intel-gtt: Drop the code for gen > 1
URL   : https://patchwork.freedesktop.org/series/42054/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8767 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8767 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8767, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42054/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8767:

  === IGT changes ===

 Possible regressions 

igt@drv_module_reload@basic-no-display:
  fi-elk-e7500:   PASS -> DMESG-FAIL +2

igt@drv_module_reload@basic-reload:
  fi-gdg-551: PASS -> DMESG-FAIL +2
  fi-blb-e6850:   PASS -> DMESG-FAIL +2
  fi-ilk-650: PASS -> DMESG-FAIL +2

igt@drv_module_reload@basic-reload-inject:
  fi-bwr-2160:PASS -> DMESG-FAIL +2


 Warnings 

igt@drv_hangman@error-state-basic:
  fi-elk-e7500:   PASS -> SKIP +212

igt@gem_flink_basic@basic:
  fi-gdg-551: PASS -> SKIP +163

igt@gem_mmap_gtt@basic-write-gtt:
  fi-blb-e6850:   PASS -> SKIP +206

igt@kms_addfb_basic@too-high:
  fi-bwr-2160:PASS -> SKIP +166

igt@kms_flip@basic-flip-vs-dpms:
  fi-ilk-650: PASS -> SKIP +211


== Known issues ==

  Here are the changes found in Patchwork_8767 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_module_reload@basic-no-display:
  fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2

igt@gem_exec_suspend@basic-s3:
  fi-ivb-3520m:   PASS -> DMESG-WARN (fdo#106084)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-cnl-y3:  PASS -> DMESG-FAIL (fdo#103191)


 Possible fixes 

igt@gem_ringfill@basic-default-hang:
  fi-blb-e6850:   DMESG-WARN (fdo#101600) -> SKIP

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-ivb-3520m:   DMESG-WARN (fdo#106084) -> PASS


  fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (33 -> 33) ==

  Additional (2): fi-kbl-7560u fi-cnl-psr 
  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8767

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8767: cb2915b7d6d1a756cbf85160d18982fe9908ff81 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

cb2915b7d6d1 drm/i915: Only build INTEL_GTT on 32-bit x86
4c8f8499a696 agp/intel-gtt: Drop the code for gen > 1

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8767/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] agp/intel-gtt: Drop the code for gen > 1

[Patchwork]

== Series Details ==

Series: series starting with [1/2] agp/intel-gtt: Drop the code for gen > 1
URL   : https://patchwork.freedesktop.org/series/42054/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4c8f8499a696 agp/intel-gtt: Drop the code for gen > 1
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit ebb7c78d358b ("agp/intel-gtt: 
Only register fake agp driver for gen1")'
#8: 
commit ebb7c78d358b2ea45c7d997423e6feb42e5ce4ef

-:295: ERROR:CODE_INDENT: code indent should use tabs where possible
#295: FILE: drivers/char/agp/intel-gtt.c:412:
+intel_private.PGETBL_save |= I810_PGETBL_ENABLED;$

-:295: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#295: FILE: drivers/char/agp/intel-gtt.c:412:
+intel_private.PGETBL_save |= I810_PGETBL_ENABLED;$

total: 2 errors, 1 warnings, 0 checks, 760 lines checked
cb2915b7d6d1 drm/i915: Only build INTEL_GTT on 32-bit x86

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[Intel-gfx] [PATCH 1/2] agp/intel-gtt: Drop the code for gen > 1

[Adam Jackson]

The gen2+ code has been unreachable since:

commit ebb7c78d358b2ea45c7d997423e6feb42e5ce4ef
Author: Daniel Vetter 
Date:   Wed Jan 27 14:38:00 2016 +0100

agp/intel-gtt: Only register fake agp driver for gen1

Signed-off-by: Adam Jackson 
---
 drivers/char/agp/intel-gtt.c | 631 +--
 1 file changed, 18 insertions(+), 613 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index c6271ce250b3..82459b886868 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -40,12 +40,6 @@
 #endif
 
 struct intel_gtt_driver {
-   unsigned int gen : 8;
-   unsigned int is_g33 : 1;
-   unsigned int is_pineview : 1;
-   unsigned int is_ironlake : 1;
-   unsigned int has_pgtbl_enable : 1;
-   unsigned int dma_mask_size : 8;
/* Chipset specific GTT setup */
int (*setup)(void);
/* This should undo anything done in ->setup() save the unmapping
@@ -88,12 +82,6 @@ static struct _intel_private {
unsigned int gtt_mappable_entries;
 } intel_private;
 
-#define INTEL_GTT_GEN  intel_private.driver->gen
-#define IS_G33 intel_private.driver->is_g33
-#define IS_PINEVIEWintel_private.driver->is_pineview
-#define IS_IRONLAKEintel_private.driver->is_ironlake
-#define HAS_PGTBL_EN   intel_private.driver->has_pgtbl_enable
-
 #if IS_ENABLED(CONFIG_AGP_INTEL)
 static int intel_gtt_map_memory(struct page **pages,
unsigned int num_entries,
@@ -335,212 +323,27 @@ static void i810_write_entry(dma_addr_t addr, unsigned 
int entry,
 
 static resource_size_t intel_gtt_stolen_size(void)
 {
-   u16 gmch_ctrl;
-   u8 rdct;
-   int local = 0;
-   static const int ddt[4] = { 0, 16, 32, 64 };
-   resource_size_t stolen_size = 0;
-
-   if (INTEL_GTT_GEN == 1)
-   return 0; /* no stolen mem on i81x */
-
-   pci_read_config_word(intel_private.bridge_dev,
-I830_GMCH_CTRL, _ctrl);
-
-   if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
-   intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
-   switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-   case I830_GMCH_GMS_STOLEN_512:
-   stolen_size = KB(512);
-   break;
-   case I830_GMCH_GMS_STOLEN_1024:
-   stolen_size = MB(1);
-   break;
-   case I830_GMCH_GMS_STOLEN_8192:
-   stolen_size = MB(8);
-   break;
-   case I830_GMCH_GMS_LOCAL:
-   rdct = 
readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
-   stolen_size = (I830_RDRAM_ND(rdct) + 1) *
-   MB(ddt[I830_RDRAM_DDT(rdct)]);
-   local = 1;
-   break;
-   default:
-   stolen_size = 0;
-   break;
-   }
-   } else {
-   switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
-   case I855_GMCH_GMS_STOLEN_1M:
-   stolen_size = MB(1);
-   break;
-   case I855_GMCH_GMS_STOLEN_4M:
-   stolen_size = MB(4);
-   break;
-   case I855_GMCH_GMS_STOLEN_8M:
-   stolen_size = MB(8);
-   break;
-   case I855_GMCH_GMS_STOLEN_16M:
-   stolen_size = MB(16);
-   break;
-   case I855_GMCH_GMS_STOLEN_32M:
-   stolen_size = MB(32);
-   break;
-   case I915_GMCH_GMS_STOLEN_48M:
-   stolen_size = MB(48);
-   break;
-   case I915_GMCH_GMS_STOLEN_64M:
-   stolen_size = MB(64);
-   break;
-   case G33_GMCH_GMS_STOLEN_128M:
-   stolen_size = MB(128);
-   break;
-   case G33_GMCH_GMS_STOLEN_256M:
-   stolen_size = MB(256);
-   break;
-   case INTEL_GMCH_GMS_STOLEN_96M:
-   stolen_size = MB(96);
-   break;
-   case INTEL_GMCH_GMS_STOLEN_160M:
-   stolen_size = MB(160);
-   break;
-   case INTEL_GMCH_GMS_STOLEN_224M:
-   stolen_size = MB(224);
-   break;
-   case INTEL_GMCH_GMS_STOLEN_352M:
-   stolen_size = MB(352);
-   break;
-   default:
-   stolen_size = 0;
-   break;
-   }
-   }
-
-   if (stolen_size > 0) {
-   

[Intel-gfx] [PATCH 2/2] drm/i915: Only build INTEL_GTT on 32-bit x86

[Adam Jackson]

The i810 was attached to Pentium III motherboards, no 64-bit CPU is ever
going to have one.

Signed-off-by: Adam Jackson 
---
 drivers/gpu/drm/i915/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index dfd95889f4b7..0f2a98c9d5af 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -2,7 +2,7 @@ config DRM_I915
tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics"
depends on DRM
depends on X86 && PCI
-   select INTEL_GTT
+   select INTEL_GTT if X86_32
select INTERVAL_TREE
# we need shmfs for the swappable backing store, and in particular
# the shmem_readpage() which depends upon tmpfs
-- 
2.17.0

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Re: [Intel-gfx] [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake

[Srivatsa, Anusha]

>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, April 20, 2018 11:04 AM
>To: Jani Nikula 
>Cc: Srivatsa, Anusha ; Ian W MORRISON
>; airl...@linux.ie; Greg KH
>; intel-gfx@lists.freedesktop.org; linux-
>ker...@vger.kernel.org; sta...@vger.kernel.org; dri-
>de...@lists.freedesktop.org; Wajdeczko, Michal 
>Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for
>Geminilake
>
>On Tue, Apr 17, 2018 at 12:02:52PM +0300, Jani Nikula wrote:
>> On Mon, 16 Apr 2018, "Srivatsa, Anusha"  wrote:
>> >>-Original Message-
>> >>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>> >>Sent: Wednesday, April 11, 2018 5:27 AM
>> >>To: Ian W MORRISON 
>> >>Cc: Vivi, Rodrigo ; Srivatsa, Anusha
>> >>; Wajdeczko, Michal
>> >>; Greg KH ;
>> >>airl...@linux.ie; joonas.lahti...@linux.intel.com;
>> >>linux-ker...@vger.kernel.org; sta...@vger.kernel.org;
>> >>intel-gfx@lists.freedesktop.org; dri- de...@lists.freedesktop.org
>> >>Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE
>> >>for Geminilake
>> >>
>> >>On Wed, 11 Apr 2018, Ian W MORRISON  wrote:
>> >>> 
>> >>>
>> 
>>  NAK on indiscriminate Cc: stable. There are zero guarantees that
>>  older kernels will work with whatever firmware you throw at them.
>> 
>> >>>
>> >>> I included 'Cc: stable' so the patch would get added to the v4.16
>> >>> and
>> >>> v4.15 kernels which I have tested with the patch. I found that
>> >>> earlier kernels didn't support the 'linux-firmware' package
>> >>> required to get wifi working on Intel's new Gemini Lake NUC.
>> >>
>> >>You realize that this patch should have nothing to do with wifi?
>> >>
>> >>Rodrigo, Anusha, if you think Cc: stable is appropriate, please
>> >>indicate the specific versions of stable it is appropriate for.
>> >
>> > Hi Jani,
>> >
>> > The stable kernel version is 4.12 and beyond.
>> > It is appropriate to add the CC: stable in my opinion
>>
>> Who tested the firmware with v4.12 and later? We only have the CI
>> results against *current* drm-tip. We don't even know about v4.16.
>>
>
>I understand your concerns, but the problem was that our old process was a bit
>(lot?) messed and there was the unreliable time until the firmware really 
>lands on
>linux-firmware.git. So MODULE_FIRMWARE call was only added after firmware
>was really there on firmware repository but it wasn't about the testing.
>
>In other words, the bump version patch was merged after tested, but
>MODULE_FIRMWARE was left behind because firmware blob took a while to get
>pulled into linux-firmware.git and we end up forgetting to add it there.
>
>In my opinion it should be safe to add the MODULE_FIRMWARE there based on
>the tests from when the version was bumped.

Luis, Elio, can you guys confirm that this firmware is tested and healthy? And 
also, give a tested-by to this patch please?

Thanks,
Anusha 
>> I'm not going to ack and take responsibility for the stable backports
>> unless someone actually comes forward with credible Tested-bys.
>>
>> BR,
>> Jani.
>>
>>
>> >
>> > Anusha
>> >>BR,
>> >>Jani.
>> >>
>> >>>
>> 
>>  PS. How is this a "RESEND"? I haven't seen this before.
>> 
>> >>>
>> >>> It is a 'RESEND' for that very reason. I initially sent the patch
>> >>> to the same people as a similar patch
>> >>> (https://patchwork.kernel.org/patch/10143637/) however after
>> >>> realising this omitted required addresses I added them and resent the
>patch.
>> >>>
>> >>> Best regards,
>> >>> Ian
>> >>
>> >>--
>> >>Jani Nikula, Intel Open Source Technology Center
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
>> ___
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>> dri-de...@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH] drm/i915: Wait for vblank after register read

[Rodrigo Vivi]

On Thu, Apr 19, 2018 at 10:03:05AM +0300, Mika Kahola wrote:
> On Thu, 2018-04-19 at 09:11 +0300, Lofstedt, Marta wrote:
> > For the PW results: 
> > https://patchwork.freedesktop.org/series/41877/
> > 
> > it didn't fix the CRC mismatch on:
> >  https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8731/shard-
> > snb6/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
> This was expected that removing one vblank doesn't fix have an effect
> on crc mismatches. Theres something more in this issue.
> 
> > 
> > but that test has always failed on SNB: 
> > http://gfx-ci.fi.intel.com/cibuglog/?action_failures_history=-1
> > res_test=igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-
> > multidraw_machine=shard-snb
> > 
> > so I don't think you brake anything with this patch.
> > 
> > Mika, do you know if waiting for the extra vblank was done with some
> > purpose?
> That I don't know if it was intentional. I'll try to find out why it
> was needed.

sink CRC calculation starts on the next active frame and takes a full
frame to finish the calculation. So 2 vblanks before the result is ready.

I don't believe we should move it for after reading it.

But it is a fact that this sink crc was always only a headache.
If we manage to move PSR tests to use the interrupts and status bits only
than we will be able to kill this sink crc code entirely

> 
> > 
> > 
> > > 
> > > -Original Message-
> > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > > Behalf
> > > Of Mika Kahola
> > > Sent: Wednesday, April 18, 2018 10:57 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH] drm/i915: Wait for vblank after
> > > register read
> > > 
> > > When reading out CRC's we  wait for a vblank on
> > > intel_dp_sink_crc_start()
> > > function. When we start reading out CRC's in intel_dp_sink_crc()
> > > loop we
> > > first wait for a vblank yielding that all in all we end up waiting
> > > two vblanks on
> > > the first iteration round. Therefore, let's move the
> > > intel_wait_for_vblank() as the last routine that we do in an
> > > iteration loop in
> > > intel_dp_sink_crc().
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103166
> > > Signed-off-by: Mika Kahola 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 5 +++--
> > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c index 62f82c4..6eb97fa 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -3972,13 +3972,14 @@ int intel_dp_sink_crc(struct intel_dp
> > > *intel_dp,
> > > struct intel_crtc_state *crtc_s
> > >   return ret;
> > > 
> > >   do {
> > > - intel_wait_for_vblank(dev_priv, intel_crtc-
> > > > 
> > > > pipe);
> > > -
> > >   if (drm_dp_dpcd_readb(_dp->aux,
> > > 
> > > DP_TEST_SINK_MISC, ) < 0) {
> > >   ret = -EIO;
> > >   goto stop;
> > >   }
> > > +
> > > + intel_wait_for_vblank(dev_priv, intel_crtc-
> > > > 
> > > > pipe);
> > > +
> > >   count = buf & DP_TEST_COUNT_MASK;
> > > 
> > >   } while (--attempts && count == 0);
> > > --
> > > 2.7.4
> > > 
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -- 
> Mika Kahola - Intel OTC
> 
> ___
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Re: [Intel-gfx] [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake

[Rodrigo Vivi]

On Tue, Apr 17, 2018 at 12:02:52PM +0300, Jani Nikula wrote:
> On Mon, 16 Apr 2018, "Srivatsa, Anusha"  wrote:
> >>-Original Message-
> >>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> >>Sent: Wednesday, April 11, 2018 5:27 AM
> >>To: Ian W MORRISON 
> >>Cc: Vivi, Rodrigo ; Srivatsa, Anusha
> >>; Wajdeczko, Michal
> >>; Greg KH ;
> >>airl...@linux.ie; joonas.lahti...@linux.intel.com; 
> >>linux-ker...@vger.kernel.org;
> >>sta...@vger.kernel.org; intel-gfx@lists.freedesktop.org; dri-
> >>de...@lists.freedesktop.org
> >>Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for
> >>Geminilake
> >>
> >>On Wed, 11 Apr 2018, Ian W MORRISON  wrote:
> >>> 
> >>>
> 
>  NAK on indiscriminate Cc: stable. There are zero guarantees that
>  older kernels will work with whatever firmware you throw at them.
> 
> >>>
> >>> I included 'Cc: stable' so the patch would get added to the v4.16 and
> >>> v4.15 kernels which I have tested with the patch. I found that earlier
> >>> kernels didn't support the 'linux-firmware' package required to get
> >>> wifi working on Intel's new Gemini Lake NUC.
> >>
> >>You realize that this patch should have nothing to do with wifi?
> >>
> >>Rodrigo, Anusha, if you think Cc: stable is appropriate, please indicate 
> >>the specific
> >>versions of stable it is appropriate for.
> >
> > Hi Jani,
> >
> > The stable kernel version is 4.12 and beyond.
> > It is appropriate to add the CC: stable in my opinion
> 
> Who tested the firmware with v4.12 and later? We only have the CI
> results against *current* drm-tip. We don't even know about v4.16.
> 

I understand your concerns, but the problem was that our old process
was a bit (lot?) messed and there was the unreliable time
until the firmware really lands on linux-firmware.git. So MODULE_FIRMWARE
call was only added after firmware was really there on firmware repository
but it wasn't about the testing.

In other words, the bump version patch was merged after tested, but
MODULE_FIRMWARE was left behind because firmware blob took a while to get
pulled into linux-firmware.git and we end up forgetting to add it there.

In my opinion it should be safe to add the MODULE_FIRMWARE there
based on the tests from when the version was bumped.

> I'm not going to ack and take responsibility for the stable backports
> unless someone actually comes forward with credible Tested-bys.
> 
> BR,
> Jani.
> 
> 
> >
> > Anusha
> >>BR,
> >>Jani.
> >>
> >>>
> 
>  PS. How is this a "RESEND"? I haven't seen this before.
> 
> >>>
> >>> It is a 'RESEND' for that very reason. I initially sent the patch to
> >>> the same people as a similar patch
> >>> (https://patchwork.kernel.org/patch/10143637/) however after realising
> >>> this omitted required addresses I added them and resent the patch.
> >>>
> >>> Best regards,
> >>> Ian
> >>
> >>--
> >>Jani Nikula, Intel Open Source Technology Center
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Aspect ratio support in DRM layer

[Patchwork]

== Series Details ==

Series: Aspect ratio support in DRM layer
URL   : https://patchwork.freedesktop.org/series/42030/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8766_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8766_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8766_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42030/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8766_full:

  === IGT changes ===

 Possible regressions 

igt@gem_eio@reset-stress:
  shard-kbl:  PASS -> FAIL

igt@gem_exec_suspend@basic-s3-devices:
  shard-hsw:  PASS -> DMESG-WARN


 Warnings 

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  SKIP -> PASS +1

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  shard-glk:  PASS -> SKIP +96

igt@kms_vblank@pipe-b-wait-forked-busy-hang:
  shard-glk:  SKIP -> PASS +120


== Known issues ==

  Here are the changes found in Patchwork_8766_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-apl:  PASS -> INCOMPLETE (fdo#103927)

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#105707)

igt@kms_flip@absolute-wf_vblank-interruptible:
  shard-glk:  SKIP -> FAIL (fdo#106087)

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#103928)


 Possible fixes 

igt@kms_flip@dpms-vs-vblank-race-interruptible:
  shard-glk:  FAIL (fdo#103060) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS
  shard-glk:  FAIL (fdo#100368) -> SKIP

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing(1): shard-glkb 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8766

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8766: 7908fbad00dea37dea9c50bd54356fd477db9fc6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8766/shards.html
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Re: [Intel-gfx] [PATCH 3/4] drm/vmwgfx: Drop DRM_CONTROL_ALLOW

[Thomas Hellstrom]

On 04/20/2018 08:51 AM, Daniel Vetter wrote:

Control nodes are no more!

Signed-off-by: Daniel Vetter 
Cc: VMware Graphics 
Cc: Sinclair Yeh 
Cc: Thomas Hellstrom 
---
  drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 70e1a8820a7c..97f37c3c16f2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -159,14 +159,14 @@ static const struct drm_ioctl_desc vmw_ioctls[] = {
  DRM_RENDER_ALLOW),
VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
  vmw_kms_cursor_bypass_ioctl,
- DRM_MASTER | DRM_CONTROL_ALLOW),
+ DRM_MASTER),
  
  	VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,

- DRM_MASTER | DRM_CONTROL_ALLOW),
+ DRM_MASTER),
VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
- DRM_MASTER | DRM_CONTROL_ALLOW),
+ DRM_MASTER),
VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
- DRM_MASTER | DRM_CONTROL_ALLOW),
+ DRM_MASTER),
  
  	VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,

  DRM_AUTH | DRM_RENDER_ALLOW),


Reviewed-by: Thomas Hellstrom 

I can queue this on the next -fixes pull.

/Thomas

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Re: [Intel-gfx] [v2] drm/i915/fbdev: Enable late fbdev initial configuration

[Paul Menzel]

Dear Jose,


On 04/19/18 01:41, Souza, Jose wrote:

If the initial fbdev configuration(intel_fbdev_initial_config()) runs and


Nit: Space before (.


there still no sink connected it will cause
drm_fb_helper_initial_config() to return 0 as no error happened(but
internally the return is -EAGAIN).


Nit: Space before (.


Because no framebuffer was allocated, when a sink is connected
intel_fbdev_output_poll_changed() will not execute
drm_fb_helper_hotplug_event() that would trigger another try to do the
initial fbdev configuration.

So here allowing drm_fb_helper_hotplug_event() to be executed when there
is not frambebuffer allocated and fbdev was not setup yet.


s/not/no/
s/setup/set up/


This issue also happens when a MST DP sink is connected since boot, as
the MST topology is discovered in parallel if intel_fbdev_initial_config()
is executed before the first sink MST is discovered it will cause this
same issue.

This is a follow up patch of


follow-up


https://patchwork.freedesktop.org/patch/196089/

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104158
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104425
Cc: Rodrigo Vivi 
Signed-off-by: Chris Wilson 
Signed-off-by: José Roberto de Souza 
---

Changes from v1:
- not creating a dump framebuffer anymore, instead just allowing
drm_fb_helper_hotplug_event() to execute when fbdev is not setup yet.


s/setup/set up/


  drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_fbdev.c 
b/drivers/gpu/drm/i915/intel_fbdev.c
index 7d41d139341b..e9e02b58b7be 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -807,7 +807,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
return;
  
  	intel_fbdev_sync(ifbdev);

-   if (ifbdev->vma)
+   if (ifbdev->vma || ifbdev->helper.deferred_setup)
drm_fb_helper_hotplug_event(>helper);
  }
  


Tested-by: Paul Menzel 


Kind regards,

Paul



smime.p7s
Description: S/MIME Cryptographic Signature
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Re: [Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 03:06:03PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju 
> 
> Prints live state of psr1.Extending the existing
> PSR2 live state function to cover psr1.
> 
> Tested on KBL with psr2 and psr1 panel.

Does it really work?

I mean... I heard DK complaining that any read to these
MMIO in some gen9 platforms were triggering the PSR exit
or something like that. So, is this really reliable?

Or it is one of those info that will misslead users to file
non existent bugs?

> 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> 
> Signed-off-by: Vathsala Nagaraju 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 68 
> -
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  2 files changed, 45 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index e0274f4..3056f04 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2580,25 +2580,42 @@ static int i915_guc_log_relay_release(struct inode 
> *inode, struct file *file)
>   .release = i915_guc_log_relay_release,
>  };
>  
> -static const char *psr2_live_status(u32 val)
> -{
> - static const char * const live_status[] = {
> - "IDLE",
> - "CAPTURE",
> - "CAPTURE_FS",
> - "SLEEP",
> - "BUFON_FW",
> - "ML_UP",
> - "SU_STANDBY",
> - "FAST_SLEEP",
> - "DEEP_SLEEP",
> - "BUF_ON",
> - "TG_ON"
> - };
> -
> - val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
> - if (val < ARRAY_SIZE(live_status))
> - return live_status[val];
> +static const char *psr_live_status(bool is_psr2_enabled, u32 val)
> +{
> + if (is_psr2_enabled) {
> + static const char * const live_status[] = {
> + "IDLE",
> + "CAPTURE",
> + "CAPTURE_FS",
> + "SLEEP",
> + "BUFON_FW",
> + "ML_UP",
> + "SU_STANDBY",
> + "FAST_SLEEP",
> + "DEEP_SLEEP",
> + "BUF_ON",
> + "TG_ON"
> + };
> + val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> + EDP_PSR2_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + } else {
> + static const char * const live_status[] = {
> + "IDLE",
> + "SRDONACK",
> + "SRDENT",
> + "BUFOFF",
> + "BUFON",
> + "AUXACK",
> + "SRDOFFACK",
> + "SRDENT_ON",
> + };
> + val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> + EDP_PSR_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + }
>  
>   return "unknown";
>  }
> @@ -2611,6 +2628,7 @@ static int i915_edp_psr_status(struct seq_file *m, void 
> *data)
>   enum pipe pipe;
>   bool enabled = false;
>   bool sink_support;
> + u32 psr_status;
>  
>   if (!HAS_PSR(dev_priv))
>   return -ENODEV;
> @@ -2678,12 +2696,14 @@ static int i915_edp_psr_status(struct seq_file *m, 
> void *data)
>  
>   seq_printf(m, "Performance_Counter: %u\n", psrperf);
>   }
> - if (dev_priv->psr.psr2_enabled) {
> - u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>  
> - seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> -psr2, psr2_live_status(psr2));
> - }
> + psr_status = (dev_priv->psr.psr2_enabled) ? I915_READ(EDP_PSR2_STATUS) :
> + I915_READ(EDP_PSR_STATUS);
> + seq_printf(m, "EDP_PSR%s_STATUS: %x [%s]\n",
> +   dev_priv->psr.psr2_enabled ? "2" : "1",
> +   psr_status,
> +   psr_live_status(dev_priv->psr.psr2_enabled, psr_status));
> +
>   mutex_unlock(_priv->psr.lock);
>  
>   intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..c9598b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4058,6 +4058,7 @@ enum {
>  #define   EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
>  #define   EDP_PSR_STATUS_SENDING_TP1 (1<<4)
>  #define   EDP_PSR_STATUS_IDLE_MASK   0xf
> +#define   EDP_PSR_STATUS_STATE_SHIFT 29
>  
>  #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
>  #define   EDP_PSR_PERF_CNT_MASK  0xff
> -- 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Stop tracking timeline->inflight_seqnos

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Stop tracking 
timeline->inflight_seqnos
URL   : https://patchwork.freedesktop.org/series/42033/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8765_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8765_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8765_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42033/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8765_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  SKIP -> PASS +1

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  shard-glk:  PASS -> SKIP +57

igt@kms_universal_plane@universal-plane-pipe-b-sanity:
  shard-glk:  SKIP -> PASS +69


== Known issues ==

  Here are the changes found in Patchwork_8765_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_ppgtt@blt-vs-render-ctxn:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665, fdo#106023)

igt@kms_atomic_interruptible@legacy-cursor:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558) +6

igt@kms_flip@flip-vs-wf_vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_rotation_crc@primary-rotation-90:
  shard-apl:  PASS -> FAIL (fdo#103925)

igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
  shard-snb:  PASS -> INCOMPLETE (fdo#105411)


 Possible fixes 

igt@kms_flip@dpms-vs-vblank-race-interruptible:
  shard-glk:  FAIL (fdo#103060) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS
  shard-glk:  FAIL (fdo#100368) -> SKIP

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS +1

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS

igt@kms_sysfs_edid_timing:
  shard-apl:  WARN (fdo#100047) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing(1): shard-glkb 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8765

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8765: 3043c4d13166dd5e199032b557136e1bf4d5a7b0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8765/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

[Souza, Jose]

On Fri, 2018-04-20 at 15:06 +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju 
> 
> Prints live state of psr1.Extending the existing
> PSR2 live state function to cover psr1.
> 
> Tested on KBL with psr2 and psr1 panel.
> 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> 
> Signed-off-by: Vathsala Nagaraju 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 68 ---
> --
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  2 files changed, 45 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index e0274f4..3056f04 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2580,25 +2580,42 @@ static int i915_guc_log_relay_release(struct
> inode *inode, struct file *file)
>   .release = i915_guc_log_relay_release,
>  };
>  
> -static const char *psr2_live_status(u32 val)
> -{
> - static const char * const live_status[] = {
> - "IDLE",
> - "CAPTURE",
> - "CAPTURE_FS",
> - "SLEEP",
> - "BUFON_FW",
> - "ML_UP",
> - "SU_STANDBY",
> - "FAST_SLEEP",
> - "DEEP_SLEEP",
> - "BUF_ON",
> - "TG_ON"
> - };
> -
> - val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> EDP_PSR2_STATUS_STATE_SHIFT;
> - if (val < ARRAY_SIZE(live_status))
> - return live_status[val];
> +static const char *psr_live_status(bool is_psr2_enabled, u32 val)
> +{
> + if (is_psr2_enabled) {
> + static const char * const live_status[] = {
> + "IDLE",
> + "CAPTURE",
> + "CAPTURE_FS",
> + "SLEEP",
> + "BUFON_FW",
> + "ML_UP",
> + "SU_STANDBY",
> + "FAST_SLEEP",
> + "DEEP_SLEEP",
> + "BUF_ON",
> + "TG_ON"
> + };
> + val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> + EDP_PSR2_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + } else {
> + static const char * const live_status[] = {
> + "IDLE",
> + "SRDONACK",
> + "SRDENT",
> + "BUFOFF",
> + "BUFON",
> + "AUXACK",
> + "SRDOFFACK",
> + "SRDENT_ON",
> + };
> + val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> + EDP_PSR_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status))
> + return live_status[val];
> + }
>  
>   return "unknown";
>  }
> @@ -2611,6 +2628,7 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
>   enum pipe pipe;
>   bool enabled = false;
>   bool sink_support;
> + u32 psr_status;
>  
>   if (!HAS_PSR(dev_priv))
>   return -ENODEV;
> @@ -2678,12 +2696,14 @@ static int i915_edp_psr_status(struct
> seq_file *m, void *data)
>  
>   seq_printf(m, "Performance_Counter: %u\n", psrperf);
>   }
> - if (dev_priv->psr.psr2_enabled) {
> - u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>  
> - seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> -psr2, psr2_live_status(psr2));
> - }
> + psr_status = (dev_priv->psr.psr2_enabled) ?
> I915_READ(EDP_PSR2_STATUS) :
> + I915_READ(EDP_PS
> R_STATUS);

Maybe move the read of the PSR or PSR2 status to inside of
psr_live_status()


Other than that looks good to me.

> + seq_printf(m, "EDP_PSR%s_STATUS: %x [%s]\n",
> +   dev_priv->psr.psr2_enabled ? "2" : "1",
> +   psr_status,
> +   psr_live_status(dev_priv->psr.psr2_enabled,
> psr_status));
> +
>   mutex_unlock(_priv->psr.lock);
>  
>   intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..c9598b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4058,6 +4058,7 @@ enum {
>  #define   EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
>  #define   EDP_PSR_STATUS_SENDING_TP1 (1<<4)
>  #define   EDP_PSR_STATUS_IDLE_MASK   0xf
> +#define   EDP_PSR_STATUS_STATE_SHIFT 29
>  
>  #define EDP_PSR_PERF_CNT _MMIO(dev_priv-
> >psr_mmio_base + 0x44)
>  #define   EDP_PSR_PERF_CNT_MASK  0xff
___
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance

[Bloomfield, Jon]

> -Original Message-
> From: Tvrtko Ursulin 
> Sent: Friday, April 20, 2018 9:56 AM
> To: Bloomfield, Jon ; Tvrtko Ursulin
> ; Intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean
> any second VCS instance
> 
> 
> On 20/04/2018 15:19, Bloomfield, Jon wrote:
> >> -Original Message-
> >> From: Tvrtko Ursulin 
> >> Sent: Wednesday, April 18, 2018 2:34 AM
> >> To: Intel-gfx@lists.freedesktop.org
> >> Cc: tursu...@ursulin.net; Ursulin, Tvrtko ; Chris
> >> Wilson ; Bloomfield, Jon
> >> ; Ye, Tony 
> >> Subject: [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean any second
> >> VCS instance
> >>
> >> From: Tvrtko Ursulin 
> >>
> >> Currently our driver assumes BSD2 means hardware engine instance
> number
> >> two. This does not work for Icelake parts with two VCS engines, but which
> >> are hardware instances 0 and 2, and not 0 and 1 as with previous parts.
> >>
> >> This makes the second engine not discoverable via HAS_BSD2 get param,
> nor
> >> it can be targetted by execbuf.
> >>
> >> While we are working on the next generation execbuf put in a hack which
> >> allows discovery and access to this second VCS engine using legacy ABI.
> >>
> >> Signed-off-by: Tvrtko Ursulin 
> >> Cc: Chris Wilson 
> >> Cc: Jon Bloomfield 
> >> Cc: Tony Ye 
> > I would advocate this patch being merged while the new execbuf API is
> being
> > developed. Currently there is no way to submit to 2 engine skus with non-
> sequential
> > engine id's. This doesn't introduce a new ABI, and there is no reason that I
> can see
> > that the new execbuf solution couldn't be made backward compatible with
> this.
> 
> It is a bit of a awkward period to commit to this permanently because it
> only solves a subset of problem space and that makes it a hard sell in
> that context.
> 
> If there was legacy userspace which ran on 2 VCS Gen11 then maybe, but
> otherwise I think best is just wait for the new execbuf API. Or in fact
> would there be _any_ upstream userspace using this before the new
> execbuf API happens?
> 
Fair point. Will you be physically inhibiting this legacy ABI for gen11? If you
intend to allow it it's worth merging, because right now it simply doesn't
work.
If you will never allow the legacy ABI, and will forcibly prevent it (hardcode
HAS_BSD2==0, for gen11+), then I agree we may as well carry the patch as
a delta until the new execbuf lands.
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[Intel-gfx] ✓ Fi.CI.BAT: success for Aspect ratio support in DRM layer

[Patchwork]

== Series Details ==

Series: Aspect ratio support in DRM layer
URL   : https://patchwork.freedesktop.org/series/42030/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8766 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42030/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8766 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)

igt@kms_chamelium@hdmi-hpd-fast:
  fi-kbl-7500u:   SKIP -> FAIL (fdo#102672, fdo#103841)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-ivb-3520m:   DMESG-WARN (fdo#106084) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (33 -> 32) ==

  Additional (1): fi-kbl-7560u 
  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8766

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8766: 7908fbad00dea37dea9c50bd54356fd477db9fc6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

7908fbad00de drm: Add and handle new aspect ratios in DRM layer
bd2199516276 drm: Add aspect ratio parsing in DRM layer
91a9c4be409c drm: Expose modes with aspect ratio, only if requested
f0bda1152c07 drm: Handle aspect ratio info in legacy and atomic modeset paths
2005b3541205 drm: Add helper functions to handle aspect-ratio flag bits
dd8bafc9bdc4 drm: Add DRM client cap for aspect-ratio
e50db7ee7284 video/hdmi: Reject illegal picture aspect ratios
b381ceee1f16 drm/edid: Don't send bogus aspect ratios in AVI infoframes
dcd05d711f36 drm/edid: Fix cea mode aspect ratio handling
0b0dac34cf2c drm/edid: Use drm_mode_match_no_clocks_no_stereo() for consistentcy
004a2f4d2e45 drm/modes: Introduce drm_mode_match()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8766/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance

[Tvrtko Ursulin]

On 20/04/2018 15:19, Bloomfield, Jon wrote:

-Original Message-
From: Tvrtko Ursulin 
Sent: Wednesday, April 18, 2018 2:34 AM
To: Intel-gfx@lists.freedesktop.org
Cc: tursu...@ursulin.net; Ursulin, Tvrtko ; Chris
Wilson ; Bloomfield, Jon
; Ye, Tony 
Subject: [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean any second
VCS instance

From: Tvrtko Ursulin 

Currently our driver assumes BSD2 means hardware engine instance number
two. This does not work for Icelake parts with two VCS engines, but which
are hardware instances 0 and 2, and not 0 and 1 as with previous parts.

This makes the second engine not discoverable via HAS_BSD2 get param, nor
it can be targetted by execbuf.

While we are working on the next generation execbuf put in a hack which
allows discovery and access to this second VCS engine using legacy ABI.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Jon Bloomfield 
Cc: Tony Ye 

I would advocate this patch being merged while the new execbuf API is being
developed. Currently there is no way to submit to 2 engine skus with 
non-sequential
engine id's. This doesn't introduce a new ABI, and there is no reason that I 
can see
that the new execbuf solution couldn't be made backward compatible with this.


It is a bit of a awkward period to commit to this permanently because it 
only solves a subset of problem space and that makes it a hard sell in 
that context.


If there was legacy userspace which ran on 2 VCS Gen11 then maybe, but 
otherwise I think best is just wait for the new execbuf API. Or in fact 
would there be _any_ upstream userspace using this before the new 
execbuf API happens?


Regards,

Tvrtko
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Use ktime on wait_for

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Use ktime on wait_for
URL   : https://patchwork.freedesktop.org/series/42035/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8764_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8764_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8764_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42035/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8764_full:

  === IGT changes ===

 Possible regressions 

igt@gem_exec_suspend@basic-s3-devices:
  shard-hsw:  PASS -> DMESG-WARN


 Warnings 

igt@gem_mocs_settings@mocs-rc6-render:
  shard-kbl:  SKIP -> PASS

igt@kms_vblank@pipe-b-wait-forked-busy-hang:
  shard-glk:  SKIP -> PASS +85

igt@pm_rpm@modeset-non-lpsp:
  shard-glk:  PASS -> SKIP +58


== Known issues ==

  Here are the changes found in Patchwork_8764_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_ppgtt@blt-vs-render-ctxn:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665, fdo#106023)

igt@kms_flip@flip-vs-wf_vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558) +38


 Possible fixes 

igt@kms_flip@dpms-vs-vblank-race-interruptible:
  shard-glk:  FAIL (fdo#103060) -> SKIP

igt@kms_flip@plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS +1

igt@kms_setmode@basic:
  shard-glk:  FAIL (fdo#99912) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing(1): shard-glkb 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8764

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8764: ae064ac61a135c5543fec9fe7a171f68bfc1a28e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8764/shards.html
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Do NOT skip the first 4k of stolen memory for pre-allocated buffers (rev3)

[Hans de Goede]

Hi,

On 04/20/2018 03:52 PM, Patchwork wrote:

== Series Details ==

Series: drm/i915: Do NOT skip the first 4k of stolen memory for pre-allocated 
buffers (rev3)
URL   : https://patchwork.freedesktop.org/series/40929/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8763_full =

== Summary - FAILURE ==

   Serious unknown changes coming with Patchwork_8763_full absolutely need to be
   verified manually.
   
   If you think the reported changes have nothing to do with the changes

   introduced in Patchwork_8763_full, please notify your bug team to allow them
   to document this new failure mode, which will reduce false positives in CI.

   External URL: 
https://patchwork.freedesktop.org/api/1.0/series/40929/revisions/3/mbox/

== Possible new issues ==

   Here are the unknown changes that may have been introduced in 
Patchwork_8763_full:

   === IGT changes ===

  Possible regressions 

 igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
   shard-apl:  PASS -> FAIL


This seems to be a false positive, so unless
someone objects I plan to push this change soonish.

Regards,

Hans


  Warnings 

 igt@gem_exec_schedule@deep-blt:
   shard-kbl:  PASS -> SKIP +1

 igt@gem_exec_schedule@deep-bsd1:
   shard-kbl:  SKIP -> PASS +1

 igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
   shard-glk:  PASS -> SKIP +95

 igt@kms_vblank@pipe-b-wait-forked-busy-hang:
   shard-glk:  SKIP -> PASS +104

 
== Known issues ==


   Here are the changes found in Patchwork_8763_full that come from known 
issues:

   === IGT changes ===

  Issues hit 

 igt@kms_flip@2x-flip-vs-expired-vblank:
   shard-hsw:  PASS -> FAIL (fdo#102887)

 igt@kms_flip@2x-wf_vblank-ts-check:
   shard-hsw:  PASS -> FAIL (fdo#100368)

 igt@pm_rpm@drm-resources-equal:
   shard-kbl:  PASS -> DMESG-FAIL (fdo#103558, fdo#104767)

>

  Possible fixes 

 igt@kms_flip@dpms-vs-vblank-race-interruptible:
   shard-glk:  FAIL (fdo#103060) -> PASS

 igt@kms_flip@plain-flip-fb-recreate:
   shard-hsw:  FAIL (fdo#100368) -> PASS

 igt@kms_flip@plain-flip-ts-check-interruptible:
   shard-glk:  FAIL (fdo#100368) -> PASS +1

 igt@kms_setmode@basic:
   shard-glk:  FAIL (fdo#99912) -> PASS
   shard-kbl:  FAIL (fdo#99912) -> PASS

 igt@perf@blocking:
   shard-hsw:  FAIL (fdo#102252) -> PASS

 
   fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

   fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
   fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
   fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
   fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
   fdo#104767 https://bugs.freedesktop.org/show_bug.cgi?id=104767
   fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

   Missing(1): shard-glkb


== Build changes ==

 * Linux: CI_DRM_4072 -> Patchwork_8763

   CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
   IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
   Patchwork_8763: 4aa49825b5adc90cab8a53d154aa779168348a6c @ 
git://anongit.freedesktop.org/gfx-ci/linux
   piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8763/shards.html


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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Aspect ratio support in DRM layer

[Patchwork]

== Series Details ==

Series: Aspect ratio support in DRM layer
URL   : https://patchwork.freedesktop.org/series/42030/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
004a2f4d2e45 drm/modes: Introduce drm_mode_match()
-:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#39: FILE: drivers/gpu/drm/drm_modes.c:958:
+static bool drm_mode_match_clock(const struct drm_display_mode *mode1,
+ const struct drm_display_mode *mode2)

total: 0 errors, 0 warnings, 1 checks, 190 lines checked
0b0dac34cf2c drm/edid: Use drm_mode_match_no_clocks_no_stereo() for consistentcy
dcd05d711f36 drm/edid: Fix cea mode aspect ratio handling
b381ceee1f16 drm/edid: Don't send bogus aspect ratios in AVI infoframes
e50db7ee7284 video/hdmi: Reject illegal picture aspect ratios
dd8bafc9bdc4 drm: Add DRM client cap for aspect-ratio
2005b3541205 drm: Add helper functions to handle aspect-ratio flag bits
f0bda1152c07 drm: Handle aspect ratio info in legacy and atomic modeset paths
-:77: CHECK:SPACING: No space is necessary after a cast
#77: FILE: drivers/gpu/drm/drm_atomic.c:399:
+   u_mode = (struct drm_mode_modeinfo *) blob->data;

total: 0 errors, 0 warnings, 1 checks, 185 lines checked
91a9c4be409c drm: Expose modes with aspect ratio, only if requested
bd2199516276 drm: Add aspect ratio parsing in DRM layer
-:86: CHECK:SPACING: space preferred before that '|' (ctx:VxE)
#86: FILE: drivers/gpu/drm/drm_modes.c:1052:
+ DRM_MODE_MATCH_3D_FLAGS|
 ^

total: 0 errors, 0 warnings, 1 checks, 77 lines checked
7908fbad00de drm: Add and handle new aspect ratios in DRM layer
-:89: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#89: FILE: include/uapi/drm/drm_mode.h:108:
+   (DRM_MODE_PICTURE_ASPECT_64_27<<19)
  ^

-:91: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#91: FILE: include/uapi/drm/drm_mode.h:110:
+   (DRM_MODE_PICTURE_ASPECT_256_135<<19)
^

total: 0 errors, 0 warnings, 2 checks, 42 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Stop tracking timeline->inflight_seqnos

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Stop tracking 
timeline->inflight_seqnos
URL   : https://patchwork.freedesktop.org/series/42033/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8765 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42033/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8765 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_module_reload@basic-no-display:
  fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: PASS -> FAIL (fdo#104008)


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395


== Participating hosts (33 -> 33) ==

  Additional (2): fi-kbl-7560u fi-cnl-psr 
  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8765

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8765: 3043c4d13166dd5e199032b557136e1bf4d5a7b0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

3043c4d13166 drm/i915: Split i915_gem_timeline into individual timelines
297584394574 drm/i915: Move timeline from GTT to ring
e05e4a7a0bab drm/i915: Retire requests along rings
a9beb7851c63 drm/i915: Stop tracking timeline->inflight_seqnos


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8765/build_32bit_failure.log

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8765/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: Stop tracking timeline->inflight_seqnos

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Stop tracking 
timeline->inflight_seqnos
URL   : https://patchwork.freedesktop.org/series/42033/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Stop tracking timeline->inflight_seqnos
-O:drivers/gpu/drm/i915/i915_request.c:268:13: error: undefined identifier 
'__builtin_add_overflow_p'
-O:drivers/gpu/drm/i915/i915_request.c:268:13: warning: call with no type!
+drivers/gpu/drm/i915/i915_request.c:266:13: error: undefined identifier 
'__builtin_add_overflow_p'
+drivers/gpu/drm/i915/i915_request.c:266:13: warning: call with no type!

Commit: drm/i915: Retire requests along rings
-drivers/gpu/drm/i915/selftests/../i915_drv.h:2208:33: warning: constant 
0xea00 is so big it is unsigned long
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3656:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:2209:33: warning: constant 
0xea00 is so big it is unsigned long
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3657:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Move timeline from GTT to ring
-drivers/gpu/drm/i915/selftests/../i915_drv.h:2209:33: warning: constant 
0xea00 is so big it is unsigned long
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3657:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:2210:33: warning: constant 
0xea00 is so big it is unsigned long
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3648:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Split i915_gem_timeline into individual timelines
-O:drivers/gpu/drm/i915/i915_request.c:266:13: error: undefined identifier 
'__builtin_add_overflow_p'
-O:drivers/gpu/drm/i915/i915_request.c:266:13: warning: call with no type!
+drivers/gpu/drm/i915/i915_request.c:263:13: error: undefined identifier 
'__builtin_add_overflow_p'
+drivers/gpu/drm/i915/i915_request.c:263:13: warning: call with no type!
-drivers/gpu/drm/i915/selftests/../i915_drv.h:2210:33: warning: constant 
0xea00 is so big it is unsigned long
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3648:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:2208:33: warning: constant 
0xea00 is so big it is unsigned long
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3646:16: warning: expression 
using sizeof(void)

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Stop tracking timeline->inflight_seqnos

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Stop tracking 
timeline->inflight_seqnos
URL   : https://patchwork.freedesktop.org/series/42033/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a9beb7851c63 drm/i915: Stop tracking timeline->inflight_seqnos
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit 9b6586ae9f6b ("drm/i915: Keep a 
global seqno per-engine")'
#14: 
References: 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine")

total: 1 errors, 0 warnings, 0 checks, 67 lines checked
e05e4a7a0bab drm/i915: Retire requests along rings
297584394574 drm/i915: Move timeline from GTT to ring
3043c4d13166 drm/i915: Split i915_gem_timeline into individual timelines
-:447: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#447: 
deleted file mode 100644

-:948: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier 
tag in line 1
#948: FILE: drivers/gpu/drm/i915/i915_timeline.c:1:
+/*

total: 0 errors, 2 warnings, 0 checks, 1617 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use ktime on wait_for

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Use ktime on wait_for
URL   : https://patchwork.freedesktop.org/series/42035/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8764 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42035/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8764 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_module_reload@basic-no-display:
  fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2

igt@gem_exec_suspend@basic-s3:
  fi-ivb-3520m:   PASS -> DMESG-WARN (fdo#106084)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-ivb-3520m:   DMESG-WARN (fdo#106084) -> PASS


  fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (33 -> 33) ==

  Additional (2): fi-kbl-7560u fi-cnl-psr 
  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8764

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8764: ae064ac61a135c5543fec9fe7a171f68bfc1a28e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

ae064ac61a13 drm/i915: Add compiler barrier to wait_for
d5e6b76f3037 drm/i915: Use ktime on wait_for

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8764/issues.html
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[Intel-gfx] [PATCH v12 1/3] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar
 - Store default MCR value instead of calculate on the run. (Oscar)
v9:
 - Changed naming and label fixes. (Oscar)
 - Store only the selector instead of whole MCR. (Oscar)
v10:
 - Improved comments, naming and line breaknig. (Oscar)
v11:
 - Moved the comment to most relavent block. (Oscar)
v12:
 - set default s/ss selector to 0 for pre-GEN10. (Oscar)

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 
Reviewed-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_device_info.c | 49 
 drivers/gpu/drm/i915/intel_device_info.h |  3 ++
 drivers/gpu/drm/i915/intel_engine_cs.c   | 10 +++
 3 files changed, 57 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index a32ba72..d917c9b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -719,6 +719,53 @@ static u32 read_timestamp_frequency(struct 
drm_i915_private *dev_priv)
return 0;
 }
 
+static void sanitize_mcr(struct intel_device_info *info)
+{
+   struct drm_i915_private *dev_priv =
+   container_of(info, struct drm_i915_private, info);
+   u32 mcr;
+   u32 mcr_slice_subslice_mask;
+   u32 mcr_slice_subslice_select;
+   u32 slice = fls(info->sseu.slice_mask);
+   u32 subslice = fls(info->sseu.subslice_mask[slice]);
+
+   if (INTEL_GEN(dev_priv) >= 11) {
+   mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+ GEN11_MCR_SUBSLICE_MASK;
+   mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+   GEN11_MCR_SUBSLICE(subslice);
+   } else {
+   mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+ GEN8_MCR_SUBSLICE_MASK;
+   mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+   GEN8_MCR_SUBSLICE(subslice);
+   }
+
+   mcr = I915_READ(GEN8_MCR_SELECTOR);
+   mcr &= ~mcr_slice_subslice_mask;
+
+   info->default_mcr_s_ss_select = 0;
+
+   /*
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+* Before any MMIO read into slice/subslice specific registers, MCR
+* packet control register needs to be programmed to point to any
+* enabled s/ss pair. Otherwise, incorrect values will be returned.
+* This means each subsequent MMIO read will be forwarded to an
+* specific s/ss combination, but this is OK since these registers
+* are consistent across s/ss in almost all cases. In the rare
+* occasions, such as INSTDONE, where this value is dependent
+* on s/ss combo, the read should be done with read_subslice_reg.
+*/
+   if (INTEL_GEN(dev_priv) >= 10) {
+   mcr |= mcr_slice_subslice_select;
+
+   info->default_mcr_s_ss_select = mcr_slice_subslice_select;
+   }
+
+   I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @info: intel device info struct
@@ -851,6 +898,8 @@ void intel_device_info_runtime_init(struct 
intel_device_info *info)
else if (INTEL_INFO(dev_priv)->gen >= 11)
gen11_sseu_info_init(dev_priv);
 
+   sanitize_mcr(info);
+
/* Initialize command stream timestamp frequency */
info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 

Re: [Intel-gfx] [PATCH v5 1/2] drm: content-type property for HDMI connector

[Daniel Vetter]

On Fri, Apr 20, 2018 at 08:31:56AM +, Lisovskiy, Stanislav wrote:
> 
> 
> From: Daniel Vetter [daniel.vet...@ffwll.ch] on behalf of Daniel Vetter 
> [dan...@ffwll.ch]
> 
> > The property documentation to tie all the bits together (property, helper,
> > internals) is missing. It should be in
> 
> > https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#standard-connector-properties
> 
> > Probably want to start with an intro-paragraph for HDMI properties
> > (someone should document the broadcast prop too eventually).
> 
> > Pls also make sure the resulting docs look pretty and that it's all
> > nicely hyperlink:
> 
> >$ make htmldocs
> 
> Thank you for your feedback. The thing is that I actually looked into docs,
> but I think there should have been already some HDMI specific property 
> documentation,
> because this one is actually not a standard connector property, so I've added 
> it only to
> 
> https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#existing-kms-properties 
> table

This table is seriously deprecated, because it's unreadable and
unmaintainable. Quoting from the docs:

"Because this table is very unwieldy, do not add any new properties here.
Instead document them in a section above."

We haven't yet moved all the existing properties over to the new layout
(patches very much welcome, especially if you spot that an entire area
you're touching like HDMI properties isn't moved yet). But the old table
is very much not cool to add stuff to.

Sorry that I didn't notice this earlier, missed it in the diffstat.

> as optional.
> I think it might be a bit misleading, if I add that one to standard connector 
> properties,
> there are probably should be created some HDMI specific property chapter 
> then, as there
> are already plenty of HDMI specific ones(force audio, broadcast rgb, aspect 
> ratio).
> 
> Shouldn't it then go in a separate patch may be? Because this work is surely 
> needed, however
> goes a bit out of scope of this patch.

Don't make it worse by adding more unmaintainable and unreadable entries
to this table. That's the minimum. Moving all the standard hdmi properties
first would obviously be even better. That also makes reviewing easier,
since it's clearer what's there already, and how your new thing fits in.
-Daniel

> 
> Best Regards,
> 
> Lisovskiy Stanislav
> 
> > ---
> >  Documentation/gpu/kms-properties.csv |  1 +
> >  drivers/gpu/drm/drm_atomic.c | 17 ++
> >  drivers/gpu/drm/drm_connector.c  | 51 
> >  drivers/gpu/drm/drm_edid.c   |  2 ++
> >  include/drm/drm_connector.h  | 18 ++
> >  include/drm/drm_mode_config.h|  5 +++
> >  include/uapi/drm/drm_mode.h  |  7 
> >  7 files changed, 101 insertions(+)
> >
> > diff --git a/Documentation/gpu/kms-properties.csv 
> > b/Documentation/gpu/kms-properties.csv
> > index 6b28b014cb7d..a91c9211b8d6 100644
> > --- a/Documentation/gpu/kms-properties.csv
> > +++ b/Documentation/gpu/kms-properties.csv
> > @@ -17,6 +17,7 @@ Owner Module/Drivers,Group,Property Name,Type,Property 
> > Values,Object attached,De
> >  ,Virtual GPU,“suggested X”,RANGE,"Min=0, 
> > Max=0x",Connector,property to suggest an X offset for a connector
> >  ,,“suggested Y”,RANGE,"Min=0, Max=0x",Connector,property to 
> > suggest an Y offset for a connector
> >  ,Optional,"""aspect ratio""",ENUM,"{ ""None"", ""4:3"", ""16:9"" 
> > }",Connector,TDB
> > +,Optional,"""content type""",ENUM,"{ ""No data"", ""Graphics"", ""Photo"", 
> > ""Cinema"", ""Game"" }",Connector,TBD
> >  i915,Generic,"""Broadcast RGB""",ENUM,"{ ""Automatic"", ""Full"", 
> > ""Limited 16:235"" }",Connector,"When this property is set to Limited 
> > 16:235 and CTM is set, the hardware will be programmed with the result of 
> > the multiplication of CTM by the limited range matrix to ensure the pixels 
> > normaly in the range 0..1.0 are remapped to the range 16/255..235/255."
> >  ,,“audio”,ENUM,"{ ""force-dvi"", ""off"", ""auto"", ""on"" }",Connector,TBD
> >  ,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } 
> > etc.",Connector,TBD
> > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > index 7d25c42f22db..479499f5848e 100644
> > --- a/drivers/gpu/drm/drm_atomic.c
> > +++ b/drivers/gpu/drm/drm_atomic.c
> > @@ -1266,6 +1266,15 @@ static int drm_atomic_connector_set_property(struct 
> > drm_connector *connector,
> >   state->link_status = val;
> >   } else if (property == config->aspect_ratio_property) {
> >   state->picture_aspect_ratio = val;
> > + } else if (property == config->content_type_property) {
> > + /*
> > +  * Lowest two bits of content_type property control
> > +  * content_type, bit 2 controls itc bit.
> > +  * It was decided to have a single property called
> > +  * content_type, instead of 

Re: [Intel-gfx] [PATCH v11 09/11] drm: Expose modes with aspect ratio, only if requested

[Ville Syrjälä]

On Fri, Apr 20, 2018 at 07:01:49PM +0530, Nautiyal, Ankit K wrote:
> From: Ankit Nautiyal 
> 
> We parse the EDID and add all the modes in the connector's modelist.
> This adds CEA modes with aspect ratio information too, regardless of
> whether user space requested this information or not.
> 
> This patch prunes the modes with aspect-ratio information, from a
> connector's modelist, if the user-space has not set the aspect ratio
> DRM client cap. However if such a mode is unique in the list, it is
> kept in the list, with aspect-ratio flags reset.
> 
> Cc: Ville Syrjala 
> Cc: Shashank Sharma 
> Cc: Jose Abreu 
> 
> Signed-off-by: Ankit Nautiyal 
> 
> V3: As suggested by Ville, modified the mechanism of pruning of modes
> with aspect-ratio, if the aspect-ratio is not supported. Instead
> of straight away pruning such a mode, the mode is retained with
> aspect ratio bits set to zero, provided it is unique.
> V4: rebase
> V5: Addressed review comments from Ville:
> -used a pointer to store last valid mode.
> -avoided, modifying of picture_aspect_ratio in kernel mode,
>  instead only flags bits of user mode are reset (if aspect-ratio
>  is not supported).
> V6: As suggested by Ville, corrected the mode pruning logic and
> elaborated the mode pruning logic and the assumptions taken.
> V7: rebase
> V8: rebase
> V9: rebase
> V10: rebase
> V11: Fixed the issue caused in kms_3d test, and enhanced the pruning
>  logic to correctly identify and prune modes with aspect-ratio,
>  if aspect-ratio cap is not set.
> ---
>  drivers/gpu/drm/drm_connector.c | 56 
> +++--
>  1 file changed, 48 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index b3cde89..865ee354 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -1531,15 +1531,35 @@ static struct drm_encoder 
> *drm_connector_get_encoder(struct drm_connector *conne
>   return connector->encoder;
>  }
>  
> -static bool drm_mode_expose_to_userspace(const struct drm_display_mode *mode,
> -  const struct drm_file *file_priv)
> +static bool
> +drm_mode_expose_to_userspace(const struct drm_display_mode *mode,
> +  const struct drm_display_mode *modelist,
> +  const struct drm_file *file_priv)
>  {
>   /*
>* If user-space hasn't configured the driver to expose the stereo 3D
>* modes, don't expose them.
>*/
> + struct drm_display_mode *mode_itr;
> +
>   if (!file_priv->stereo_allowed && drm_mode_is_stereo(mode))
>   return false;
> + /*
> +  * If user-space hasn't configured the driver to expose the modes
> +  * with aspect-ratio, don't expose them. However if such a mode
> +  * is unique, let it be exposed, but reset the aspect-ratio flags
> +  * while preparing the list of user-modes.
> +  */
> + if (!file_priv->aspect_ratio_allowed &&
> + mode->picture_aspect_ratio != HDMI_PICTURE_ASPECT_NONE) {
> + list_for_each_entry(mode_itr, >head, head)
> + if (drm_mode_match(mode_itr, mode,
> +DRM_MODE_MATCH_TIMINGS |
> +DRM_MODE_MATCH_CLOCK |
> +DRM_MODE_MATCH_FLAGS |
> +DRM_MODE_MATCH_3D_FLAGS))
> + return false;
> + }
>  
>   return true;
>  }
> @@ -1550,7 +1570,7 @@ int drm_mode_getconnector(struct drm_device *dev, void 
> *data,
>   struct drm_mode_get_connector *out_resp = data;
>   struct drm_connector *connector;
>   struct drm_encoder *encoder;
> - struct drm_display_mode *mode;
> + struct drm_display_mode *mode, *tmp, modelist;
>   int mode_count = 0;
>   int encoders_count = 0;
>   int ret = 0;
> @@ -1605,23 +1625,37 @@ int drm_mode_getconnector(struct drm_device *dev, 
> void *data,
>   out_resp->subpixel = connector->display_info.subpixel_order;
>   out_resp->connection = connector->status;
>  
> + INIT_LIST_HEAD();

Why are we using a struct drm_display_mode to get a simple list_head?

> +
>   /* delayed so we get modes regardless of pre-fill_modes state */
>   list_for_each_entry(mode, >modes, head)
> - if (drm_mode_expose_to_userspace(mode, file_priv))
> + if (drm_mode_expose_to_userspace(mode, ,
> +  file_priv)) {
> + struct drm_display_mode *tmp_mode;
> +
> + tmp_mode = drm_mode_duplicate(dev, mode);

Duplicating every mode seems rather wasteful. I suppose we could
just add another list_head to struct 

Re: [Intel-gfx] [PATCH v11 07/11] drm: Add helper functions to handle aspect-ratio flag bits

[Ville Syrjälä]

On Fri, Apr 20, 2018 at 07:01:47PM +0530, Nautiyal, Ankit K wrote:
> From: Ankit Nautiyal 
> 
> This patch adds helper functions for determining if aspect-ratio is
> expected in user-mode and for allowing/disallowing the aspect-ratio,
> if its not expected.
> 
> Signed-off-by: Ankit Nautiyal 
> ---
>  drivers/gpu/drm/drm_modes.c | 47 
> +
>  include/drm/drm_modes.h |  4 
>  2 files changed, 51 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
> index c395a24..d6133e8 100644
> --- a/drivers/gpu/drm/drm_modes.c
> +++ b/drivers/gpu/drm/drm_modes.c
> @@ -1759,3 +1759,50 @@ bool drm_mode_is_420(const struct drm_display_info 
> *display,
>   drm_mode_is_420_also(display, mode);
>  }
>  EXPORT_SYMBOL(drm_mode_is_420);
> +
> +/**
> + * drm_mode_aspect_ratio_allowed - checks if the aspect-ratio information
> + * is expected from the user-mode.
> + *
> + * If the user has set aspect-ratio cap, then the flag of the user-mode is
> + * allowed to contain aspect-ratio value.
> + * If the user does not set aspect-ratio cap, then the only value allowed in 
> the
> + * flags bits is aspect-ratio NONE.
> + *
> + * @file_priv: file private structure to get the user capabilities
> + * @umode: drm_mode_modeinfo struct, whose flag carry the aspect ratio
> + * information.
> + *
> + * Returns:
> + * true if the aspect-ratio info is allowed in the user-mode flags.
> + * false, otherwise.
> + */
> +bool
> +drm_mode_aspect_ratio_allowed(const struct drm_file *file_priv,
> +   struct drm_mode_modeinfo *umode)
> +{
> + return file_priv->aspect_ratio_allowed || (umode->flags &
> + DRM_MODE_FLAG_PIC_AR_MASK) == DRM_MODE_FLAG_PIC_AR_NONE;

Odd line split here. Makes this a bit hard to read.
I would split after the ||

> +}
> +EXPORT_SYMBOL(drm_mode_aspect_ratio_allowed);

Do we actually need to export these? I don't think so.

But I might be wrong. It's a bit hard to see with the way
you split this patch with the actual users in a different patch.

> +
> +/**
> + * drm_mode_filter_aspect_ratio_flags - filters the aspect-ratio bits in the
> + * user-mode flags.
> + *
> + * Checks if the aspect-ratio information is allowed. Resets the aspect-ratio
> + * bits in the user-mode flags, if aspect-ratio info is not allowed.
> + *
> + * @file_priv: file private structure to get the user capabilities.
> + * @umode: drm_mode_modeinfo struct, whose flags' aspect-ratio bits needs to
> + * be filtered.
> + *
> + */
> +void
> +drm_mode_filter_aspect_ratio_flags(const struct drm_file *file_priv,
> +struct drm_mode_modeinfo *umode)
> +{
> + if (!drm_mode_aspect_ratio_allowed(file_priv, umode))
> + umode->flags &= ~DRM_MODE_FLAG_PIC_AR_MASK;
> +}
> +EXPORT_SYMBOL(drm_mode_filter_aspect_ratio_flags);
> diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
> index 2f78b7e..e0b060d 100644
> --- a/include/drm/drm_modes.h
> +++ b/include/drm/drm_modes.h
> @@ -461,6 +461,10 @@ bool drm_mode_is_420_also(const struct drm_display_info 
> *display,
> const struct drm_display_mode *mode);
>  bool drm_mode_is_420(const struct drm_display_info *display,
>const struct drm_display_mode *mode);
> +bool drm_mode_aspect_ratio_allowed(const struct drm_file *file_priv,
> +struct drm_mode_modeinfo *umode);
> +void drm_mode_filter_aspect_ratio_flags(const struct drm_file *file_priv,
> + struct drm_mode_modeinfo *umode);
>  
>  struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
> int hdisplay, int vdisplay, int vrefresh,
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Add NV12 support to intel_framebuffer_init

[kbuild test robot]

Hi Chandra,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17-rc1 next-20180420]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Vidya-Srinivas/drm-i915-Add-NV12-support-to-intel_framebuffer_init/20180420-184309
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x0-04201646 (attached as .config)
compiler: gcc-5 (Debian 5.5.0-3) 5.4.1 20171010
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_display.c: In function 'intel_framebuffer_init':
   drivers/gpu/drm/i915/intel_display.c:14142:19: error: 
'SKL_MIN_YUV_420_SRC_W' undeclared (first use in this function)
 (fb->width < SKL_MIN_YUV_420_SRC_W ||
  ^
   drivers/gpu/drm/i915/intel_display.c:14142:19: note: each undeclared 
identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_display.c:14143:20: error: 
>> 'SKL_MIN_YUV_420_SRC_H' undeclared (first use in this function)
  fb->height < SKL_MIN_YUV_420_SRC_H ||
   ^

vim +/SKL_MIN_YUV_420_SRC_H +14143 drivers/gpu/drm/i915/intel_display.c

 13968  
 13969  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 13970struct drm_i915_gem_object *obj,
 13971struct drm_mode_fb_cmd2 *mode_cmd)
 13972  {
 13973  struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 13974  struct drm_framebuffer *fb = _fb->base;
 13975  struct drm_format_name_buf format_name;
 13976  u32 pitch_limit;
 13977  unsigned int tiling, stride;
 13978  int ret = -EINVAL;
 13979  int i;
 13980  
 13981  i915_gem_object_lock(obj);
 13982  obj->framebuffer_references++;
 13983  tiling = i915_gem_object_get_tiling(obj);
 13984  stride = i915_gem_object_get_stride(obj);
 13985  i915_gem_object_unlock(obj);
 13986  
 13987  if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
 13988  /*
 13989   * If there's a fence, enforce that
 13990   * the fb modifier and tiling mode match.
 13991   */
 13992  if (tiling != I915_TILING_NONE &&
 13993  tiling != 
intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 13994  DRM_DEBUG_KMS("tiling_mode doesn't match fb 
modifier\n");
 13995  goto err;
 13996  }
 13997  } else {
 13998  if (tiling == I915_TILING_X) {
 13999  mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
 14000  } else if (tiling == I915_TILING_Y) {
 14001  DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
 14002  goto err;
 14003  }
 14004  }
 14005  
 14006  /* Passed in modifier sanity checking. */
 14007  switch (mode_cmd->modifier[0]) {
 14008  case I915_FORMAT_MOD_Y_TILED_CCS:
 14009  case I915_FORMAT_MOD_Yf_TILED_CCS:
 14010  switch (mode_cmd->pixel_format) {
 14011  case DRM_FORMAT_XBGR:
 14012  case DRM_FORMAT_ABGR:
 14013  case DRM_FORMAT_XRGB:
 14014  case DRM_FORMAT_ARGB:
 14015  break;
 14016  default:
 14017  DRM_DEBUG_KMS("RC supported only with RGB 
formats\n");
 14018  goto err;
 14019  }
 14020  /* fall through */
 14021  case I915_FORMAT_MOD_Y_TILED:
 14022  case I915_FORMAT_MOD_Yf_TILED:
 14023  if (INTEL_GEN(dev_priv) < 9) {
 14024  DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
 14025mode_cmd->modifier[0]);
 14026  goto err;
 14027  }
 14028  case DRM_FORMAT_MOD_LINEAR:
 14029  case I915_FORMAT_MOD_X_TILED:
 14030  break;
 14031  default:
 14032  DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
 14033mode_cmd->modifier[0]);
 14034  goto err;
 14035  }
 14036  
 14037  /*
 14038   * gen2/3 display engine uses the fence if present,
 14039   * so the tiling mode must match the fb modifier exactly.
 14040   */
 14041  if (INTEL_GEN(dev_priv) < 4 &&
 140

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add compiler barrier to wait_for

[Chris Wilson]

Quoting Mika Kuoppala (2018-04-20 14:45:50)
> We need to be careful to not let compiler evaluate
> the expiration and the operation on it's terms.
> 
> Document and enforce that COND will be evaluated
> before checking timeout expiration.
> 
> Suggested-by: Chris Wilson 
> Cc: Chris Wilson 
> Signed-off-by: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/intel_drv.h | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index ac7565220aa3..4dc346716bb4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -56,6 +56,8 @@
> for (;;) {  \
> const bool expired__ = ktime_after(ktime_get_raw(), end__); \
> OP; \
> +   /* Guarantee COND check prior to timeout */ \
> +   barrier();  \

Which side of OP is debatable, since OP is caller supplied and our
constraint is targeted at expired__. However, it is likely to be more
useful between OP/COND, so I can see some advantage there.

As Mika noted, moving to a function call should mean that the compiler
has less freedom to reorder/re-evaluate but doesn't completely prevent
it. As such being clear about the order of operations here is just as
important for the reader. There is a long history of gotchas here, and
this patch set continues the trend :)

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PATCH v11 00/11] Aspect ratio support in DRM layer

[Nautiyal, Ankit K]

From: Ankit Nautiyal 

This patch series is a re-attempt to enable aspect ratio support in
DRM layer. Currently the aspect ratio information gets lost in translation
during a user->kernel mode or vice versa.

The old patch series (https://pw-emeril.freedesktop.org/series/10850/) had
4 patches, out of which 2 patches were reverted due to lack of drm client
protection while loading the aspect information.

This patch series also includes 5 patches from Ville Syrjälä's series for
'Info-frame cleanup and fixes':
https://patchwork.freedesktop.org/series/33730/ which fixes the mode
matching mechanism via flags, and also ensures that no bogus aspect-ratios
are sent in the AVI infoframes.

This patch series, adds a DRM client option for aspect ratio, and loads
aspect ratio flags, only when the client sets this cap. 

To test this patch, the testdiplay IGT test is modified to have an option
to do a modeset with only aspect ratio modes.
Also, there is a userspace implementation in Wayland/weston layer:
https://patchwork.freedesktop.org/patch/188125/
(Which is already ACK'ed by wayland community.)

This, helps us in passing HDMI compliance test cases like 7-27, where the
test equipment applies a CEA mode, and expects the exact VIC in the AVI
infoframes.

Ankit Nautiyal (4):
  drm: Add DRM client cap for aspect-ratio
  drm: Add helper functions to handle aspect-ratio flag bits
  drm: Handle aspect ratio info in legacy and atomic modeset paths
  drm: Expose modes with aspect ratio, only if requested

Sharma, Shashank (2):
  drm: Add aspect ratio parsing in DRM layer
  drm: Add and handle new aspect ratios in DRM layer

Ville Syrjälä (5):
  drm/modes: Introduce drm_mode_match()
  drm/edid: Use drm_mode_match_no_clocks_no_stereo() for consistentcy
  drm/edid: Fix cea mode aspect ratio handling
  drm/edid: Don't send bogus aspect ratios in AVI infoframes
  video/hdmi: Reject illegal picture aspect ratios

 drivers/gpu/drm/drm_atomic.c|  34 --
 drivers/gpu/drm/drm_atomic_helper.c |   6 +-
 drivers/gpu/drm/drm_connector.c |  56 +++--
 drivers/gpu/drm/drm_crtc.c  |   8 ++
 drivers/gpu/drm/drm_crtc_internal.h |   3 +-
 drivers/gpu/drm/drm_edid.c  |  41 +--
 drivers/gpu/drm/drm_fb_helper.c |  12 +-
 drivers/gpu/drm/drm_ioctl.c |   9 ++
 drivers/gpu/drm/drm_mode_object.c   |   9 +-
 drivers/gpu/drm/drm_modes.c | 226 +++-
 drivers/video/hdmi.c|   3 +
 include/drm/drm_atomic.h|   5 +-
 include/drm/drm_file.h  |   8 ++
 include/drm/drm_modes.h |  13 +++
 include/uapi/drm/drm.h  |   7 ++
 include/uapi/drm/drm_mode.h |   6 +
 16 files changed, 377 insertions(+), 69 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH v11 11/11] drm: Add and handle new aspect ratios in DRM layer

[Nautiyal, Ankit K]

From: "Sharma, Shashank" 

HDMI 2.0/CEA-861-F introduces two new aspect ratios:
- 64:27
- 256:135

This patch:
-  Adds new DRM flags for to represent these new aspect ratios.
-  Adds new cases to handle these aspect ratios while converting
from user->kernel mode or vise versa.

This patch was once reviewed and merged, and later reverted due
to lack of DRM client protection, while adding aspect ratio bits
in user modes. This is a re-spin of the series, with DRM client
cap protection.

The previous series can be found here:
https://pw-emeril.freedesktop.org/series/10850/

Signed-off-by: Shashank Sharma 
Reviewed-by: Sean Paul  (V2)
Reviewed-by: Jose Abreu  (V2)

Cc: Ville Syrjala 
Cc: Sean Paul 
Cc: Jose Abreu 
Cc: Ankit Nautiyal 

V3: rebase
V4: rebase
V5: corrected the macro name for an aspect ratio, in a switch case.
V6: rebase
V7: rebase
V8: rebase
V9: rebase
V10: rebase
---
 drivers/gpu/drm/drm_modes.c | 12 
 include/uapi/drm/drm_mode.h |  6 ++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 454f2ff..21cc84b 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1656,6 +1656,12 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo 
*out,
case HDMI_PICTURE_ASPECT_16_9:
out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
break;
+   case HDMI_PICTURE_ASPECT_64_27:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_64_27;
+   break;
+   case HDMI_PICTURE_ASPECT_256_135:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_256_135;
+   break;
case HDMI_PICTURE_ASPECT_RESERVED:
default:
out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
@@ -1721,6 +1727,12 @@ int drm_mode_convert_umode(struct drm_device *dev,
case DRM_MODE_FLAG_PIC_AR_16_9:
out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_16_9;
break;
+   case DRM_MODE_FLAG_PIC_AR_64_27:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_64_27;
+   break;
+   case DRM_MODE_FLAG_PIC_AR_256_135:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_256_135;
+   break;
default:
out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
break;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 50bcf42..4b3a1bb 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -93,6 +93,8 @@ extern "C" {
 #define DRM_MODE_PICTURE_ASPECT_NONE   0
 #define DRM_MODE_PICTURE_ASPECT_4_31
 #define DRM_MODE_PICTURE_ASPECT_16_9   2
+#define DRM_MODE_PICTURE_ASPECT_64_27  3
+#define DRM_MODE_PICTURE_ASPECT_256_1354
 
 /* Aspect ratio flag bitmask (4 bits 22:19) */
 #define DRM_MODE_FLAG_PIC_AR_MASK  (0x0F<<19)
@@ -102,6 +104,10 @@ extern "C" {
(DRM_MODE_PICTURE_ASPECT_4_3<<19)
 #define  DRM_MODE_FLAG_PIC_AR_16_9 \
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
+#define  DRM_MODE_FLAG_PIC_AR_64_27 \
+   (DRM_MODE_PICTURE_ASPECT_64_27<<19)
+#define  DRM_MODE_FLAG_PIC_AR_256_135 \
+   (DRM_MODE_PICTURE_ASPECT_256_135<<19)
 
 #define  DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \
 DRM_MODE_FLAG_NHSYNC | \
-- 
2.7.4

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[Intel-gfx] [PATCH 2/4] drm/i915: Retire requests along rings

[Chris Wilson]

In the next patch, rings are the central timeline as requests may jump
between engines. Therefore in the future as we retire in order along the
engine timeline, we may retire out-of-order within a ring (as the ring now
occurs along multiple engines), leading to much hilarity in miscomputing
the position of ring->head.

As an added bonus, retiring along the ring reduces the penalty of having
one execlists client do cleanup for another (old legacy submission
shares a ring between all clients). The downside is that slow and
irregular (off the critical path) process of cleaning up stale requests
after userspace becomes a modicum less efficient.

In the long run, it will become apparent that the ordered
ring->request_list matches the ring->timeline, a fun challenge for the
future will be unifying the two lists to avoid duplication!

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h   |  3 +-
 drivers/gpu/drm/i915/i915_gem.c   |  1 +
 drivers/gpu/drm/i915/i915_request.c   | 43 ---
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  5 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h   |  1 +
 drivers/gpu/drm/i915/selftests/mock_engine.c  | 27 +---
 .../gpu/drm/i915/selftests/mock_gem_device.c  |  2 +
 7 files changed, 50 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 028691108125..e177d2bda87d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2055,8 +2055,9 @@ struct drm_i915_private {
void (*resume)(struct drm_i915_private *);
void (*cleanup_engine)(struct intel_engine_cs *engine);
 
-   struct list_head timelines;
struct i915_gem_timeline global_timeline;
+   struct list_head timelines;
+   struct list_head rings;
u32 active_requests;
 
/**
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 795ca83aed7a..906e2395c245 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5600,6 +5600,7 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
goto err_dependencies;
 
mutex_lock(_priv->drm.struct_mutex);
+   INIT_LIST_HEAD(_priv->gt.rings);
INIT_LIST_HEAD(_priv->gt.timelines);
err = i915_gem_timeline_init__global(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 1437538d5bfa..0bf949ec9f1a 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -292,6 +292,7 @@ void i915_gem_retire_noop(struct i915_gem_active *active,
 
 static void advance_ring(struct i915_request *request)
 {
+   struct intel_ring *ring = request->ring;
unsigned int tail;
 
/*
@@ -303,7 +304,9 @@ static void advance_ring(struct i915_request *request)
 * Note this requires that we are always called in request
 * completion order.
 */
-   if (list_is_last(>ring_link, >ring->request_list)) {
+   GEM_BUG_ON(request != list_first_entry(>request_list,
+  typeof(*request), ring_link));
+   if (list_is_last(>ring_link, >request_list)) {
/*
 * We may race here with execlists resubmitting this request
 * as we retire it. The resubmission will move the ring->tail
@@ -318,7 +321,7 @@ static void advance_ring(struct i915_request *request)
}
list_del(>ring_link);
 
-   request->ring->head = tail;
+   ring->head = tail;
 }
 
 static void free_capture_list(struct i915_request *request)
@@ -424,18 +427,18 @@ static void i915_request_retire(struct i915_request 
*request)
 
 void i915_request_retire_upto(struct i915_request *rq)
 {
-   struct intel_engine_cs *engine = rq->engine;
+   struct intel_ring *ring = rq->ring;
struct i915_request *tmp;
 
lockdep_assert_held(>i915->drm.struct_mutex);
GEM_BUG_ON(!i915_request_completed(rq));
 
-   if (list_empty(>link))
+   if (list_empty(>ring_link))
return;
 
do {
-   tmp = list_first_entry(>timeline->requests,
-  typeof(*tmp), link);
+   tmp = list_first_entry(>request_list,
+  typeof(*tmp), ring_link);
 
i915_request_retire(tmp);
} while (tmp != rq);
@@ -644,9 +647,9 @@ i915_request_alloc(struct intel_engine_cs *engine, struct 
i915_gem_context *ctx)
if (ret)
goto err_unreserve;
 
-   /* Move the oldest request to the slab-cache (if not in use!) */
-   rq = list_first_entry_or_null(>timeline->requests,
-

[Intel-gfx] [PATCH 1/4] drm/i915: Stop tracking timeline->inflight_seqnos

[Chris Wilson]

In commit 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine"), we
moved from a global inflight counter to per-engine counters in the
hope that will be easy to run concurrently in future. However, with the
advent of the desire to move requests between engines, we do need a
global counter to preserve the semantics that no engine wraps in the
middle of a submit. (Although this semantic is now only required for gen7
semaphore support, which only supports greater-then comparisons!)

References: 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine")
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  5 ++---
 drivers/gpu/drm/i915/i915_gem_timeline.h |  6 --
 drivers/gpu/drm/i915/i915_request.c  | 12 +++-
 drivers/gpu/drm/i915/intel_engine_cs.c   |  5 ++---
 4 files changed, 7 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e0274f41bc76..a8b3dba5505b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1340,10 +1340,9 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
struct rb_node *rb;
 
seq_printf(m, "%s:\n", engine->name);
-   seq_printf(m, "\tseqno = %x [current %x, last %x], inflight 
%d\n",
+   seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
   engine->hangcheck.seqno, seqno[id],
-  intel_engine_last_submit(engine),
-  engine->timeline->inflight_seqnos);
+  intel_engine_last_submit(engine));
seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? 
%s\n",
   yesno(intel_engine_has_waiter(engine)),
   yesno(test_bit(engine->id,
diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.h 
b/drivers/gpu/drm/i915/i915_gem_timeline.h
index 33e01bf6aa36..6e82119e2cd8 100644
--- a/drivers/gpu/drm/i915/i915_gem_timeline.h
+++ b/drivers/gpu/drm/i915/i915_gem_timeline.h
@@ -37,12 +37,6 @@ struct intel_timeline {
u64 fence_context;
u32 seqno;
 
-   /**
-* Count of outstanding requests, from the time they are constructed
-* to the moment they are retired. Loosely coupled to hardware.
-*/
-   u32 inflight_seqnos;
-
spinlock_t lock;
 
/**
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index b692a9f7c357..1437538d5bfa 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -260,17 +260,14 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32 
seqno)
 static int reserve_engine(struct intel_engine_cs *engine)
 {
struct drm_i915_private *i915 = engine->i915;
-   u32 active = ++engine->timeline->inflight_seqnos;
-   u32 seqno = engine->timeline->seqno;
int ret;
 
/* Reservation is fine until we need to wrap around */
-   if (unlikely(add_overflows(seqno, active))) {
+   if (unlikely(add_overflows(engine->timeline->seqno,
+  i915->gt.active_requests + 1))) {
ret = reset_all_global_seqno(i915, 0);
-   if (ret) {
-   engine->timeline->inflight_seqnos--;
+   if (ret)
return ret;
-   }
}
 
if (!i915->gt.active_requests++)
@@ -285,9 +282,6 @@ static void unreserve_engine(struct intel_engine_cs *engine)
 
if (!--i915->gt.active_requests)
i915_gem_park(i915);
-
-   GEM_BUG_ON(!engine->timeline->inflight_seqnos);
-   engine->timeline->inflight_seqnos--;
 }
 
 void i915_gem_retire_noop(struct i915_gem_active *active,
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index be608f7111f5..a55a849b81b6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1318,12 +1318,11 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (i915_terminally_wedged(>i915->gpu_error))
drm_printf(m, "*** WEDGED ***\n");
 
-   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d\n",
+   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
   engine->hangcheck.seqno,
-  jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
-  engine->timeline->inflight_seqnos);
+  jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp));
drm_printf(m, "\tReset count: %d (global %d)\n",
   i915_reset_engine_count(error, engine),
   

[Intel-gfx] [PATCH v11 07/11] drm: Add helper functions to handle aspect-ratio flag bits

[Nautiyal, Ankit K]

From: Ankit Nautiyal 

This patch adds helper functions for determining if aspect-ratio is
expected in user-mode and for allowing/disallowing the aspect-ratio,
if its not expected.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/drm_modes.c | 47 +
 include/drm/drm_modes.h |  4 
 2 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index c395a24..d6133e8 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1759,3 +1759,50 @@ bool drm_mode_is_420(const struct drm_display_info 
*display,
drm_mode_is_420_also(display, mode);
 }
 EXPORT_SYMBOL(drm_mode_is_420);
+
+/**
+ * drm_mode_aspect_ratio_allowed - checks if the aspect-ratio information
+ * is expected from the user-mode.
+ *
+ * If the user has set aspect-ratio cap, then the flag of the user-mode is
+ * allowed to contain aspect-ratio value.
+ * If the user does not set aspect-ratio cap, then the only value allowed in 
the
+ * flags bits is aspect-ratio NONE.
+ *
+ * @file_priv: file private structure to get the user capabilities
+ * @umode: drm_mode_modeinfo struct, whose flag carry the aspect ratio
+ * information.
+ *
+ * Returns:
+ * true if the aspect-ratio info is allowed in the user-mode flags.
+ * false, otherwise.
+ */
+bool
+drm_mode_aspect_ratio_allowed(const struct drm_file *file_priv,
+ struct drm_mode_modeinfo *umode)
+{
+   return file_priv->aspect_ratio_allowed || (umode->flags &
+   DRM_MODE_FLAG_PIC_AR_MASK) == DRM_MODE_FLAG_PIC_AR_NONE;
+}
+EXPORT_SYMBOL(drm_mode_aspect_ratio_allowed);
+
+/**
+ * drm_mode_filter_aspect_ratio_flags - filters the aspect-ratio bits in the
+ * user-mode flags.
+ *
+ * Checks if the aspect-ratio information is allowed. Resets the aspect-ratio
+ * bits in the user-mode flags, if aspect-ratio info is not allowed.
+ *
+ * @file_priv: file private structure to get the user capabilities.
+ * @umode: drm_mode_modeinfo struct, whose flags' aspect-ratio bits needs to
+ * be filtered.
+ *
+ */
+void
+drm_mode_filter_aspect_ratio_flags(const struct drm_file *file_priv,
+  struct drm_mode_modeinfo *umode)
+{
+   if (!drm_mode_aspect_ratio_allowed(file_priv, umode))
+   umode->flags &= ~DRM_MODE_FLAG_PIC_AR_MASK;
+}
+EXPORT_SYMBOL(drm_mode_filter_aspect_ratio_flags);
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index 2f78b7e..e0b060d 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -461,6 +461,10 @@ bool drm_mode_is_420_also(const struct drm_display_info 
*display,
  const struct drm_display_mode *mode);
 bool drm_mode_is_420(const struct drm_display_info *display,
 const struct drm_display_mode *mode);
+bool drm_mode_aspect_ratio_allowed(const struct drm_file *file_priv,
+  struct drm_mode_modeinfo *umode);
+void drm_mode_filter_aspect_ratio_flags(const struct drm_file *file_priv,
+   struct drm_mode_modeinfo *umode);
 
 struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
  int hdisplay, int vdisplay, int vrefresh,
-- 
2.7.4

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[Intel-gfx] [PATCH v11 10/11] drm: Add aspect ratio parsing in DRM layer

[Nautiyal, Ankit K]

From: "Sharma, Shashank" 

Current DRM layer functions don't parse aspect ratio information
while converting a user mode->kernel mode or vice versa. This
causes modeset to pick mode with wrong aspect ratio, eventually
causing failures in HDMI compliance test cases, due to wrong VIC.

This patch adds aspect ratio information in DRM's mode conversion
and mode comparision functions, to make sure kernel picks mode
with right aspect ratio (as per the VIC).

Background:
This patch was once reviewed and merged, and later reverted due to
lack of DRM cap protection. This is a re-spin of this patch, this
time with DRM cap protection, to avoid aspect ratio information, when
the client doesn't request for it.

Review link: https://pw-emeril.freedesktop.org/patch/104068/
Background discussion: https://patchwork.kernel.org/patch/9379057/

Signed-off-by: Shashank Sharma 
Signed-off-by: Lin, Jia 
Signed-off-by: Akashdeep Sharma 
Reviewed-by: Jim Bride  (V2)
Reviewed-by: Jose Abreu  (V4)

Cc: Ville Syrjala 
Cc: Jim Bride 
Cc: Jose Abreu 
Cc: Ankit Nautiyal 

V3: modified the aspect-ratio check in drm_mode_equal as per new flags
provided by Ville. https://patchwork.freedesktop.org/patch/188043/
V4: rebase
V5: rebase
V6: As recommended by Ville, avoided matching of aspect-ratio in
drm_fb_helper, while trying to find a common mode among connectors
for the target clone mode.
V7: rebase
V8: rebase
V9: rebase
V10: rebase
---
 drivers/gpu/drm/drm_fb_helper.c | 12 ++--
 drivers/gpu/drm/drm_modes.c | 35 ++-
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 0646b10..2ee1eaa 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2183,7 +2183,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
*fb_helper,
for (j = 0; j < i; j++) {
if (!enabled[j])
continue;
-   if (!drm_mode_equal(modes[j], modes[i]))
+   if (!drm_mode_match(modes[j], modes[i],
+   DRM_MODE_MATCH_TIMINGS |
+   DRM_MODE_MATCH_CLOCK |
+   DRM_MODE_MATCH_FLAGS |
+   DRM_MODE_MATCH_3D_FLAGS))
can_clone = false;
}
}
@@ -2203,7 +2207,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
*fb_helper,
 
fb_helper_conn = fb_helper->connector_info[i];
list_for_each_entry(mode, _helper_conn->connector->modes, 
head) {
-   if (drm_mode_equal(mode, dmt_mode))
+   if (drm_mode_match(mode, dmt_mode,
+  DRM_MODE_MATCH_TIMINGS |
+  DRM_MODE_MATCH_CLOCK |
+  DRM_MODE_MATCH_FLAGS |
+  DRM_MODE_MATCH_3D_FLAGS))
modes[i] = mode;
}
if (!modes[i])
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index d6133e8..454f2ff 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1049,7 +1049,8 @@ bool drm_mode_equal(const struct drm_display_mode *mode1,
  DRM_MODE_MATCH_TIMINGS |
  DRM_MODE_MATCH_CLOCK |
  DRM_MODE_MATCH_FLAGS |
- DRM_MODE_MATCH_3D_FLAGS);
+ DRM_MODE_MATCH_3D_FLAGS|
+ DRM_MODE_MATCH_ASPECT_RATIO);
 }
 EXPORT_SYMBOL(drm_mode_equal);
 
@@ -1647,6 +1648,20 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo 
*out,
out->vrefresh = in->vrefresh;
out->flags = in->flags;
out->type = in->type;
+
+   switch (in->picture_aspect_ratio) {
+   case HDMI_PICTURE_ASPECT_4_3:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_4_3;
+   break;
+   case HDMI_PICTURE_ASPECT_16_9:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
+   break;
+   case HDMI_PICTURE_ASPECT_RESERVED:
+   default:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
+   break;
+   }
+
strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 }
@@ -1693,6 +1708,24 @@ int drm_mode_convert_umode(struct drm_device *dev,
strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);

Re: [Intel-gfx] [PATCH v11 06/11] drm: Add DRM client cap for aspect-ratio

[Ville Syrjälä]

On Fri, Apr 20, 2018 at 07:01:46PM +0530, Nautiyal, Ankit K wrote:
> From: Ankit Nautiyal 
> 
> To enable aspect-ratio support in DRM, blindly exposing the aspect
> ratio information along with mode, can break things in existing
> user-spaces which have no intention or support to use this aspect
> ratio information.
> 
> To avoid this, a new drm client cap is required to enable a
> user-space to advertise if it supports modes with aspect-ratio. Based
> on this cap value, the kernel will take a call on exposing the aspect
> ratio info in modes or not.
> 
> This patch adds the client cap for aspect-ratio.
> 
> Cc: Ville Syrjala 
> Cc: Shashank Sharma 
> Signed-off-by: Ankit Nautiyal 
> 
> V3: rebase
> V4: As suggested by Marteen Lankhorst modified the commit message
> explaining the need to use the DRM cap for aspect-ratio. Also,
> tweaked the comment lines in the code for better understanding and
> clarity, as recommended by Shashank Sharma.
> V5: rebase
> V6: rebase
> V7: rebase
> V8: rebase
> V9: rebase
> V10: added comment explaining that no userspace breaks on aspect-ratio
>  mode bits.
> 
> Reviewed-by: Shashank Sharma 
> ---
>  drivers/gpu/drm/drm_ioctl.c | 9 +
>  include/drm/drm_file.h  | 8 
>  include/uapi/drm/drm.h  | 7 +++
>  3 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> index af78291..39c8eab 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -325,6 +325,15 @@ drm_setclientcap(struct drm_device *dev, void *data, 
> struct drm_file *file_priv)
>   file_priv->atomic = req->value;
>   file_priv->universal_planes = req->value;
>   break;
> + case DRM_CLIENT_CAP_ASPECT_RATIO:
> + if (req->value > 1)
> + return -EINVAL;
> + /*
> +  * No Atomic userspace blows up on aspect ratio mode bits. Checked in
> +  * wayland/weston, xserver, and hardware-composer modeset paths.
> +  */

Bogus indentation.

Also where's the aspect_ratio_allowed handling for the atomic cap?
Or did we decide against it after all?

> + file_priv->aspect_ratio_allowed = req->value;
> + break;
>   default:
>   return -EINVAL;
>   }
> diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
> index 5176c37..02b7dde 100644
> --- a/include/drm/drm_file.h
> +++ b/include/drm/drm_file.h
> @@ -182,6 +182,14 @@ struct drm_file {
>   unsigned atomic:1;
>  
>   /**
> +  * @aspect_ratio_allowed:
> +  *
> +  * True, if client can handle picture aspect ratios, and has requested
> +  * to pass this information along with the mode.
> +  */
> + unsigned aspect_ratio_allowed:1;
> +
> + /**
>* @is_master:
>*
>* This client is the creator of @master. Protected by struct
> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
> index 6fdff59..9c660e1 100644
> --- a/include/uapi/drm/drm.h
> +++ b/include/uapi/drm/drm.h
> @@ -680,6 +680,13 @@ struct drm_get_cap {
>   */
>  #define DRM_CLIENT_CAP_ATOMIC3
>  
> +/**
> + * DRM_CLIENT_CAP_ASPECT_RATIO
> + *
> + * If set to 1, the DRM core will provide aspect ratio information in modes.
> + */
> +#define DRM_CLIENT_CAP_ASPECT_RATIO4
> +
>  /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
>  struct drm_set_client_cap {
>   __u64 capability;
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance

[Bloomfield, Jon]

> -Original Message-
> From: Tvrtko Ursulin 
> Sent: Wednesday, April 18, 2018 2:34 AM
> To: Intel-gfx@lists.freedesktop.org
> Cc: tursu...@ursulin.net; Ursulin, Tvrtko ; Chris
> Wilson ; Bloomfield, Jon
> ; Ye, Tony 
> Subject: [PATCH] drm/i915/icl: Adjust BSD2 semantics to mean any second
> VCS instance
> 
> From: Tvrtko Ursulin 
> 
> Currently our driver assumes BSD2 means hardware engine instance number
> two. This does not work for Icelake parts with two VCS engines, but which
> are hardware instances 0 and 2, and not 0 and 1 as with previous parts.
> 
> This makes the second engine not discoverable via HAS_BSD2 get param, nor
> it can be targetted by execbuf.
> 
> While we are working on the next generation execbuf put in a hack which
> allows discovery and access to this second VCS engine using legacy ABI.
> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Chris Wilson 
> Cc: Jon Bloomfield 
> Cc: Tony Ye 
I would advocate this patch being merged while the new execbuf API is being
developed. Currently there is no way to submit to 2 engine skus with 
non-sequential
engine id's. This doesn't introduce a new ABI, and there is no reason that I 
can see
that the new execbuf solution couldn't be made backward compatible with this.

Reviewed-by: Jon Bloomfield 
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[Intel-gfx] [PATCH v11 02/11] drm/edid: Use drm_mode_match_no_clocks_no_stereo() for consistentcy

[Nautiyal, Ankit K]

From: Ville Syrjälä 

Use drm_mode_equal_no_clocks_no_stereo() in
drm_match_hdmi_mode_clock_tolerance() for consistency as we
also use it in drm_match_hdmi_mode() and the cea mode matching
functions.

This doesn't actually change anything since the input mode
comes from detailed timings and we match it against
edid_4k_modes[] which. So none of those modes can have stereo
flags set.

Signed-off-by: Ville Syrjälä 
Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 134069f..c35d3bc 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3047,7 +3047,7 @@ static u8 drm_match_hdmi_mode_clock_tolerance(const 
struct drm_display_mode *to_
abs(to_match->clock - clock2) > clock_tolerance)
continue;
 
-   if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
+   if (drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
return vic;
}
 
-- 
2.7.4

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[Intel-gfx] [PATCH 3/4] drm/i915: Move timeline from GTT to ring

[Chris Wilson]

In the future, we want to move a request between engines. To achieve
this, we first realise that we have two timelines in effect here. The
first runs through the GTT is required for ordering vma access, which is
tracked currently by engine. The second is implied by sequential
execution of commands inside the ringbuffer. This timeline is one that
maps to userspace's expectations when submitting requests (i.e. given the
same context, batch A is executed before batch B). As the rings's
timelines map to userspace and the GTT timeline an implementation
detail, move the timeline from the GTT into the ring itself (per-context
in logical-ring-contexts/execlists, or a global per-engine timeline for
the shared ringbuffers in legacy submission.

The two timelines are still assumed to be equivalent at the moment (no
migrating requests between engines yet) and so we can simply move from
one to the other without adding extra ordering.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h   | 13 +
 drivers/gpu/drm/i915/i915_gem.c   |  9 ++--
 drivers/gpu/drm/i915/i915_gem_context.c   | 15 +-
 drivers/gpu/drm/i915/i915_gem_context.h   |  2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c   |  3 --
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  1 -
 drivers/gpu/drm/i915/i915_gem_timeline.c  | 54 +--
 drivers/gpu/drm/i915/i915_gem_timeline.h  |  4 ++
 drivers/gpu/drm/i915/i915_request.c   | 15 +++---
 drivers/gpu/drm/i915/intel_engine_cs.c|  3 +-
 drivers/gpu/drm/i915/intel_lrc.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  9 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.h   |  5 +-
 drivers/gpu/drm/i915/selftests/mock_engine.c  |  3 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |  4 +-
 drivers/gpu/drm/i915/selftests/mock_gtt.c |  1 -
 16 files changed, 101 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e177d2bda87d..f3a898feaa91 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2055,7 +2055,8 @@ struct drm_i915_private {
void (*resume)(struct drm_i915_private *);
void (*cleanup_engine)(struct intel_engine_cs *engine);
 
-   struct i915_gem_timeline global_timeline;
+   struct i915_gem_timeline execution_timeline;
+   struct i915_gem_timeline legacy_timeline;
struct list_head timelines;
struct list_head rings;
u32 active_requests;
@@ -3229,16 +3230,6 @@ i915_gem_context_lookup(struct drm_i915_file_private 
*file_priv, u32 id)
return ctx;
 }
 
-static inline struct intel_timeline *
-i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
-struct intel_engine_cs *engine)
-{
-   struct i915_address_space *vm;
-
-   vm = ctx->ppgtt ? >ppgtt->base : >i915->ggtt.base;
-   return >timeline.engine[engine->id];
-}
-
 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file);
 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 906e2395c245..0c5aef67b302 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3109,10 +3109,10 @@ static void engine_skip_context(struct i915_request 
*request)
 {
struct intel_engine_cs *engine = request->engine;
struct i915_gem_context *hung_ctx = request->ctx;
-   struct intel_timeline *timeline;
+   struct intel_timeline *timeline = request->timeline;
unsigned long flags;
 
-   timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
+   GEM_BUG_ON(timeline == engine->timeline);
 
spin_lock_irqsave(>timeline->lock, flags);
spin_lock(>lock);
@@ -3781,7 +3781,7 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915, 
unsigned int flags)
 
ret = wait_for_engines(i915);
} else {
-   ret = wait_for_timeline(>gt.global_timeline, flags);
+   ret = wait_for_timeline(>gt.execution_timeline, flags);
}
 
return ret;
@@ -5650,7 +5650,8 @@ void i915_gem_cleanup_early(struct drm_i915_private 
*dev_priv)
WARN_ON(dev_priv->mm.object_count);
 
mutex_lock(_priv->drm.struct_mutex);
-   i915_gem_timeline_fini(_priv->gt.global_timeline);
+   i915_gem_timeline_fini(_priv->gt.legacy_timeline);
+   i915_gem_timeline_fini(_priv->gt.execution_timeline);
WARN_ON(!list_empty(_priv->gt.timelines));
mutex_unlock(_priv->drm.struct_mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 74435affe23f..58b185abe652 100644
--- 

[Intel-gfx] [PATCH 1/2] drm/i915: Use ktime on wait_for

[Mika Kuoppala]

We use jiffies to determine when wait expires. However
Imre did find out that jiffies can and will do a >1
increments on certain situations [1]. When this happens
in a wait_for loop, we return timeout errorneously
much earlier than what the real wallclock would say.

We can't afford our waits to timeout prematurely.
Discard jiffies and change to ktime to detect timeouts.

v2: added bugzilla entry (Imre), added stable (Chris)

Reported-by: Imre Deak 
References: https://lkml.org/lkml/2018/4/18/798 [1]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Ville Syrjälä 
Cc: 
Signed-off-by: Mika Kuoppala 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_drv.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8b20824e806e..ac7565220aa3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -49,12 +49,12 @@
  * check the condition before the timeout.
  */
 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
-   unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
+   const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
int ret__;  \
might_sleep();  \
for (;;) {  \
-   bool expired__ = time_after(jiffies, timeout__);\
+   const bool expired__ = ktime_after(ktime_get_raw(), end__); \
OP; \
if (COND) { \
ret__ = 0;  \
-- 
2.14.1

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[Intel-gfx] [PATCH v11 05/11] video/hdmi: Reject illegal picture aspect ratios

[Nautiyal, Ankit K]

From: Ville Syrjälä 

AVI infoframe can only carry none, 4:3, or 16:9 picture aspect
ratios. Return an error if the user asked for something different.

Cc: Shashank Sharma 
Cc: "Lin, Jia" 
Cc: Akashdeep Sharma 
Cc: Jim Bride 
Cc: Jose Abreu 
Cc: Daniel Vetter 
Cc: Emil Velikov 
Cc: Thierry Reding 
Cc: Hans Verkuil 
Cc: linux-me...@vger.kernel.org
Signed-off-by: Ville Syrjälä 
Reviewed-by: Jose Abreu 
---
 drivers/video/hdmi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 111a0ab..38716eb5 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -93,6 +93,9 @@ ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe 
*frame, void *buffer,
if (size < length)
return -ENOSPC;
 
+   if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9)
+   return -EINVAL;
+
memset(buffer, 0, size);
 
ptr[0] = frame->type;
-- 
2.7.4

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[Intel-gfx] [PATCH v11 01/11] drm/modes: Introduce drm_mode_match()

[Nautiyal, Ankit K]

From: Ville Syrjälä 

Make mode matching less confusing by allowing the caller to specify
which parts of the modes should match via some flags.

Signed-off-by: Ville Syrjälä 
Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_modes.c | 134 ++--
 include/drm/drm_modes.h |   9 +++
 2 files changed, 112 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index e82b61e..c395a24 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -939,17 +939,68 @@ struct drm_display_mode *drm_mode_duplicate(struct 
drm_device *dev,
 }
 EXPORT_SYMBOL(drm_mode_duplicate);
 
+static bool drm_mode_match_timings(const struct drm_display_mode *mode1,
+  const struct drm_display_mode *mode2)
+{
+   return mode1->hdisplay == mode2->hdisplay &&
+   mode1->hsync_start == mode2->hsync_start &&
+   mode1->hsync_end == mode2->hsync_end &&
+   mode1->htotal == mode2->htotal &&
+   mode1->hskew == mode2->hskew &&
+   mode1->vdisplay == mode2->vdisplay &&
+   mode1->vsync_start == mode2->vsync_start &&
+   mode1->vsync_end == mode2->vsync_end &&
+   mode1->vtotal == mode2->vtotal &&
+   mode1->vscan == mode2->vscan;
+}
+
+static bool drm_mode_match_clock(const struct drm_display_mode *mode1,
+ const struct drm_display_mode *mode2)
+{
+   /*
+* do clock check convert to PICOS
+* so fb modes get matched the same
+*/
+   if (mode1->clock && mode2->clock)
+   return KHZ2PICOS(mode1->clock) == KHZ2PICOS(mode2->clock);
+   else
+   return mode1->clock == mode2->clock;
+}
+
+static bool drm_mode_match_flags(const struct drm_display_mode *mode1,
+const struct drm_display_mode *mode2)
+{
+   return (mode1->flags & ~DRM_MODE_FLAG_3D_MASK) ==
+   (mode2->flags & ~DRM_MODE_FLAG_3D_MASK);
+}
+
+static bool drm_mode_match_3d_flags(const struct drm_display_mode *mode1,
+   const struct drm_display_mode *mode2)
+{
+   return (mode1->flags & DRM_MODE_FLAG_3D_MASK) ==
+   (mode2->flags & DRM_MODE_FLAG_3D_MASK);
+}
+
+static bool drm_mode_match_aspect_ratio(const struct drm_display_mode *mode1,
+   const struct drm_display_mode *mode2)
+{
+   return mode1->picture_aspect_ratio == mode2->picture_aspect_ratio;
+}
+
 /**
- * drm_mode_equal - test modes for equality
+ * drm_mode_match - test modes for (partial) equality
  * @mode1: first mode
  * @mode2: second mode
+ * @match_flags: which parts need to match (DRM_MODE_MATCH_*)
  *
  * Check to see if @mode1 and @mode2 are equivalent.
  *
  * Returns:
- * True if the modes are equal, false otherwise.
+ * True if the modes are (partially) equal, false otherwise.
  */
-bool drm_mode_equal(const struct drm_display_mode *mode1, const struct 
drm_display_mode *mode2)
+bool drm_mode_match(const struct drm_display_mode *mode1,
+   const struct drm_display_mode *mode2,
+   unsigned int match_flags)
 {
if (!mode1 && !mode2)
return true;
@@ -957,15 +1008,48 @@ bool drm_mode_equal(const struct drm_display_mode 
*mode1, const struct drm_displ
if (!mode1 || !mode2)
return false;
 
-   /* do clock check convert to PICOS so fb modes get matched
-* the same */
-   if (mode1->clock && mode2->clock) {
-   if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock))
-   return false;
-   } else if (mode1->clock != mode2->clock)
+   if (match_flags & DRM_MODE_MATCH_TIMINGS &&
+   !drm_mode_match_timings(mode1, mode2))
return false;
 
-   return drm_mode_equal_no_clocks(mode1, mode2);
+   if (match_flags & DRM_MODE_MATCH_CLOCK &&
+   !drm_mode_match_clock(mode1, mode2))
+   return false;
+
+   if (match_flags & DRM_MODE_MATCH_FLAGS &&
+   !drm_mode_match_flags(mode1, mode2))
+   return false;
+
+   if (match_flags & DRM_MODE_MATCH_3D_FLAGS &&
+   !drm_mode_match_3d_flags(mode1, mode2))
+   return false;
+
+   if (match_flags & DRM_MODE_MATCH_ASPECT_RATIO &&
+   !drm_mode_match_aspect_ratio(mode1, mode2))
+   return false;
+
+   return true;
+}
+EXPORT_SYMBOL(drm_mode_match);
+
+/**
+ * drm_mode_equal - test modes for equality
+ * @mode1: first mode
+ * @mode2: second mode
+ *
+ * Check to see if @mode1 and @mode2 are equivalent.
+ *
+ * Returns:
+ * True if the modes are equal, false otherwise.
+ */
+bool drm_mode_equal(const struct drm_display_mode *mode1,
+   const struct drm_display_mode 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Do NOT skip the first 4k of stolen memory for pre-allocated buffers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Do NOT skip the first 4k of stolen memory for pre-allocated 
buffers (rev3)
URL   : https://patchwork.freedesktop.org/series/40929/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8763_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8763_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8763_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/40929/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8763_full:

  === IGT changes ===

 Possible regressions 

igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
  shard-apl:  PASS -> FAIL


 Warnings 

igt@gem_exec_schedule@deep-blt:
  shard-kbl:  PASS -> SKIP +1

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  SKIP -> PASS +1

igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
  shard-glk:  PASS -> SKIP +95

igt@kms_vblank@pipe-b-wait-forked-busy-hang:
  shard-glk:  SKIP -> PASS +104


== Known issues ==

  Here are the changes found in Patchwork_8763_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-hsw:  PASS -> FAIL (fdo#102887)

igt@kms_flip@2x-wf_vblank-ts-check:
  shard-hsw:  PASS -> FAIL (fdo#100368)

igt@pm_rpm@drm-resources-equal:
  shard-kbl:  PASS -> DMESG-FAIL (fdo#103558, fdo#104767)


 Possible fixes 

igt@kms_flip@dpms-vs-vblank-race-interruptible:
  shard-glk:  FAIL (fdo#103060) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS +1

igt@kms_setmode@basic:
  shard-glk:  FAIL (fdo#99912) -> PASS
  shard-kbl:  FAIL (fdo#99912) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#104767 https://bugs.freedesktop.org/show_bug.cgi?id=104767
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing(1): shard-glkb 


== Build changes ==

* Linux: CI_DRM_4072 -> Patchwork_8763

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8763: 4aa49825b5adc90cab8a53d154aa779168348a6c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8763/shards.html
___
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[Intel-gfx] [PATCH 2/2] drm/i915: Add compiler barrier to wait_for

[Mika Kuoppala]

We need to be careful to not let compiler evaluate
the expiration and the operation on it's terms.

Document and enforce that COND will be evaluated
before checking timeout expiration.

Suggested-by: Chris Wilson 
Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_drv.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ac7565220aa3..4dc346716bb4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -56,6 +56,8 @@
for (;;) {  \
const bool expired__ = ktime_after(ktime_get_raw(), end__); \
OP; \
+   /* Guarantee COND check prior to timeout */ \
+   barrier();  \
if (COND) { \
ret__ = 0;  \
break;  \
@@ -96,6 +98,8 @@
u64 now = local_clock(); \
if (!(ATOMIC)) \
preempt_enable(); \
+   /* Guarantee COND check prior to timeout */ \
+   barrier(); \
if (COND) { \
ret = 0; \
break; \
-- 
2.14.1

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[Intel-gfx] [PATCH v11 04/11] drm/edid: Don't send bogus aspect ratios in AVI infoframes

[Nautiyal, Ankit K]

From: Ville Syrjälä 

If the user mode would specify an aspect ratio other than 4:3 or 16:9
we now silently ignore it. Maybe a better apporoach is to return an
error? Let's try that.

Also we must be careful that we don't try to send illegal picture
aspect in the infoframe as it's only capable of signalling none,
4:3, and 16:9. Currently we're sending these bogus infoframes
whenever the cea mode specifies some other aspect ratio.

Cc: Shashank Sharma 
Cc: Sean Paul 
Cc: Jose Abreu 
Cc: Daniel Vetter 
Cc: Emil Velikov 
Signed-off-by: Ville Syrjälä 
Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 23 +--
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 29c88eb..d5757aa 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4840,6 +4840,7 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
hdmi_avi_infoframe *frame,
 const struct drm_display_mode *mode,
 bool is_hdmi2_sink)
 {
+   enum hdmi_picture_aspect picture_aspect;
int err;
 
if (!frame || !mode)
@@ -4882,13 +4883,23 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
hdmi_avi_infoframe *frame,
 * Populate picture aspect ratio from either
 * user input (if specified) or from the CEA mode list.
 */
-   if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
-   mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
-   frame->picture_aspect = mode->picture_aspect_ratio;
-   else if (frame->video_code > 0)
-   frame->picture_aspect = drm_get_cea_aspect_ratio(
-   frame->video_code);
+   picture_aspect = mode->picture_aspect_ratio;
+   if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
+   picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
 
+   /*
+* The infoframe can't convey anything but none, 4:3
+* and 16:9, so if the user has asked for anything else
+* we can only satisfy it by specifying the right VIC.
+*/
+   if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
+   if (picture_aspect !=
+   drm_get_cea_aspect_ratio(frame->video_code))
+   return -EINVAL;
+   picture_aspect = HDMI_PICTURE_ASPECT_NONE;
+   }
+
+   frame->picture_aspect = picture_aspect;
frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
 
-- 
2.7.4

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[Intel-gfx] [PATCH v11 08/11] drm: Handle aspect ratio info in legacy and atomic modeset paths

[Nautiyal, Ankit K]

From: Ankit Nautiyal 

If the user-space does not support aspect-ratio, and requests for a
modeset with mode having aspect ratio bits set, then the given
user-mode must be rejected. Secondly, while preparing a user-mode from
kernel mode, the aspect-ratio info must not be given, if aspect-ratio
is not supported by the user.

Note: In case, a user-space asks for a video-mode blob, from the
getblob ioctl, the aspect-ratio bits in the video-mode blob are passed
to the user as it is, without any filtering. However, no such case is
present in most of the atomic user-spaces. Currently atomic path of
Xserver, Wayland/weston, Hardware-Composer are checked, and none of
them are using getblob ioctl to get the video-mode blob.

This patch:
1. passes the file_priv structure from the drm_mode_atomic_ioctl till
   the drm_mode_crtc_set_mode_prop, to get the user capability.
2. rejects the modes with aspect-ratio info, during modeset, if the
   user does not support aspect ratio.
3. does not load the aspect-ratio info in user-mode structure, if
   aspect ratio is not supported.

Signed-off-by: Ankit Nautiyal 

V3: Addressed review comments from Ville:
Do not corrupt the current crtc state by updating aspect-ratio on
the fly.
V4: rebase
V5: As suggested by Ville, rejected the modeset calls for modes with
aspect ratio, if the user does not set aspect-ratio cap.
V6: Used the helper functions for determining if aspect-ratio is
expected in the user-mode.
V7: rebase
V8: rebase
V9: rebase
v10: Modified the commit-message
---
 drivers/gpu/drm/drm_atomic.c| 34 +-
 drivers/gpu/drm/drm_atomic_helper.c |  6 +++---
 drivers/gpu/drm/drm_crtc.c  |  8 
 drivers/gpu/drm/drm_crtc_internal.h |  3 ++-
 drivers/gpu/drm/drm_mode_object.c   |  9 ++---
 include/drm/drm_atomic.h|  5 +++--
 6 files changed, 47 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 3d9ae05..5acf49d 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -368,6 +368,7 @@ EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc);
  * drm_atomic_set_mode_prop_for_crtc - set mode for CRTC
  * @state: the CRTC whose incoming state to update
  * @blob: pointer to blob property to use for mode
+ * @file_priv: file priv structure, to get the userspace capabilities
  *
  * Set a mode (originating from a blob property) on the desired CRTC state.
  * This function will take a reference on the blob property for the CRTC state,
@@ -378,7 +379,8 @@ EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc);
  * Zero on success, error code on failure. Cannot return -EDEADLK.
  */
 int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
-  struct drm_property_blob *blob)
+ struct drm_property_blob *blob,
+ struct drm_file *file_priv)
 {
if (blob == state->mode_blob)
return 0;
@@ -389,9 +391,21 @@ int drm_atomic_set_mode_prop_for_crtc(struct 
drm_crtc_state *state,
memset(>mode, 0, sizeof(state->mode));
 
if (blob) {
-   if (blob->length != sizeof(struct drm_mode_modeinfo) ||
-   drm_mode_convert_umode(state->crtc->dev, >mode,
-  blob->data))
+   struct drm_mode_modeinfo *u_mode;
+
+   if (blob->length != sizeof(struct drm_mode_modeinfo))
+   return -EINVAL;
+
+   u_mode = (struct drm_mode_modeinfo *) blob->data;
+   if (!drm_mode_aspect_ratio_allowed(file_priv,
+  u_mode)) {
+   DRM_DEBUG_ATOMIC("Unexpected aspect-ratio flag bits\n");
+   return -EINVAL;
+   }
+
+   if (drm_mode_convert_umode(state->crtc->dev, >mode,
+  (const struct drm_mode_modeinfo *)
+  u_mode))
return -EINVAL;
 
state->mode_blob = drm_property_blob_get(blob);
@@ -471,6 +485,7 @@ drm_atomic_replace_property_blob_from_id(struct drm_device 
*dev,
  * @state: the state object to update with the new property value
  * @property: the property to set
  * @val: the new property value
+ * @file_priv: the file private structure, to get the user capabilities
  *
  * This function handles generic/core properties and calls out to driver's
  * _crtc_funcs.atomic_set_property for driver properties. To ensure
@@ -482,7 +497,7 @@ drm_atomic_replace_property_blob_from_id(struct drm_device 
*dev,
  */
 int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
struct drm_crtc_state *state, struct drm_property *property,
-   uint64_t val)
+   uint64_t val, struct drm_file 

[Intel-gfx] [PATCH v11 03/11] drm/edid: Fix cea mode aspect ratio handling

[Nautiyal, Ankit K]

From: Ville Syrjälä 

commit 6dffd431e229 ("drm: Add aspect ratio parsing in DRM layer")
cause us to not send out any VICs in the AVI infoframes. That commit
was since reverted, but if and when we add aspect ratio handing back
we need to be more careful.

Let's handle this by considering the aspect ratio as a requirement
for cea mode matching only if the passed in mode actually has a
non-zero aspect ratio field. This will keep userspace that doesn't
provide an aspect ratio working as before by matching it to the
first otherwise equal cea mode. And once userspace starts to
provide the aspect ratio it will be considerd a hard requirement
for the match.

Also change the hdmi mode matching to use drm_mode_match() for
consistency, but we don't match on aspect ratio there since the
spec doesn't list a specific aspect ratio for those modes.

Cc: Shashank Sharma 
Cc: "Lin, Jia" 
Cc: Akashdeep Sharma 
Cc: Jim Bride 
Cc: Jose Abreu 
Cc: Daniel Vetter 
Cc: Emil Velikov 
Signed-off-by: Ville Syrjälä 
Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c35d3bc..29c88eb 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2930,11 +2930,15 @@ cea_mode_alternate_timings(u8 vic, struct 
drm_display_mode *mode)
 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode 
*to_match,
 unsigned int clock_tolerance)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
return 0;
 
+   if (to_match->picture_aspect_ratio)
+   match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
+
for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
struct drm_display_mode cea_mode = edid_cea_modes[vic];
unsigned int clock1, clock2;
@@ -2948,7 +2952,7 @@ static u8 drm_match_cea_mode_clock_tolerance(const struct 
drm_display_mode *to_m
continue;
 
do {
-   if (drm_mode_equal_no_clocks_no_stereo(to_match, 
_mode))
+   if (drm_mode_match(to_match, _mode, match_flags))
return vic;
} while (cea_mode_alternate_timings(vic, _mode));
}
@@ -2965,11 +2969,15 @@ static u8 drm_match_cea_mode_clock_tolerance(const 
struct drm_display_mode *to_m
  */
 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
return 0;
 
+   if (to_match->picture_aspect_ratio)
+   match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
+
for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
struct drm_display_mode cea_mode = edid_cea_modes[vic];
unsigned int clock1, clock2;
@@ -2983,7 +2991,7 @@ u8 drm_match_cea_mode(const struct drm_display_mode 
*to_match)
continue;
 
do {
-   if (drm_mode_equal_no_clocks_no_stereo(to_match, 
_mode))
+   if (drm_mode_match(to_match, _mode, match_flags))
return vic;
} while (cea_mode_alternate_timings(vic, _mode));
}
@@ -3030,6 +3038,7 @@ hdmi_mode_alternate_clock(const struct drm_display_mode 
*hdmi_mode)
 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode 
*to_match,
  unsigned int clock_tolerance)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
@@ -3047,7 +3056,7 @@ static u8 drm_match_hdmi_mode_clock_tolerance(const 
struct drm_display_mode *to_
abs(to_match->clock - clock2) > clock_tolerance)
continue;
 
-   if (drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
+   if (drm_mode_match(to_match, hdmi_mode, match_flags))
return vic;
}
 
@@ -3064,6 +3073,7 @@ static u8 drm_match_hdmi_mode_clock_tolerance(const 
struct drm_display_mode *to_
  */
 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
@@ -3079,7 +3089,7 @@ static u8 drm_match_hdmi_mode(const struct 
drm_display_mode *to_match)
 
if