[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix CHICKEN_TRANS register offset

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CHICKEN_TRANS register offset
URL   : https://patchwork.freedesktop.org/series/45536/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4392_full -> Patchwork_9456_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_9456_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@mock_scatterlist:
  shard-glk:  NOTRUN -> DMESG-WARN (fdo#103667)

igt@gem_ctx_isolation@rcs0-s3:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665) +1

igt@gem_exec_schedule@pi-ringfull-bsd:
  shard-glk:  NOTRUN -> FAIL (fdo#103158)

igt@gem_exec_schedule@preemptive-hang-render:
  shard-snb:  SKIP -> INCOMPLETE (fdo#105411)

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#105363)

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip@plain-flip-ts-check-interruptible:
  {shard-glk9}:   PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724) +1

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  NOTRUN -> FAIL (fdo#104724, fdo#103822)


 Possible fixes 

igt@gem_exec_big:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-hsw:  FAIL (fdo#105363, fdo#102887) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS
  shard-kbl:  FAIL (fdo#99912) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4392 -> Patchwork_9456

  CI_DRM_4392: fa0510c4f4d6e85cba3068f08a83cb56b9fdf668 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9456: dc2c463beb7c24876f33d086d2fb3c9427fe576e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9456/shards.html
___
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Re: [Intel-gfx] [DIM DOCS PATCH 2/2] doc: clarify what type of changes are acceptable at commit time

[Rodrigo Vivi]

On Wed, Jun 27, 2018 at 06:13:01PM +0300, Jani Nikula wrote:
> As a rule of thumb, don't change patches while committing.
> 
> Cc: Imre Deak 
> Signed-off-by: Jani Nikula 

Acked-by: Rodrigo Vivi 

> ---
>  drm-intel.rst | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drm-intel.rst b/drm-intel.rst
> index baf48f459dd9..ad8ff9739336 100644
> --- a/drm-intel.rst
> +++ b/drm-intel.rst
> @@ -196,6 +196,13 @@ An inexhaustive list of details to check:
>coordinate with maintainers to avoid unnecessary pain with conflicts. 
> Usually
>some explicit merges are needed to avoid git getting lost.
>  
> +* As a general rule, do not modify the patches while applying, apart from the
> +  commit message. If the patch conflicts, or needs to be changed due to 
> review,
> +  have the author rebase, update and resend. Any change at this stage is a
> +  potential issue bypassing CI.
> +
> +  At most, minor comment and whitespace tweaks are acceptable.
> +
>  On Confidence, Complexity, and Transparency
>  ---
>  
> -- 
> 2.11.0
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [DIM DOCS PATCH 1/2] doc: update CI and pre-merge details in committer guidelines

[Rodrigo Vivi]

On Wed, Jun 27, 2018 at 06:13:00PM +0300, Jani Nikula wrote:
> Lots has happened in the CI front since the first version was added.
> 
> Signed-off-by: Jani Nikula 

Acked-by: Rodrigo Vivi 

> ---
>  drm-intel.rst | 45 -
>  1 file changed, 28 insertions(+), 17 deletions(-)
> 
> diff --git a/drm-intel.rst b/drm-intel.rst
> index c68949a41c95..baf48f459dd9 100644
> --- a/drm-intel.rst
> +++ b/drm-intel.rst
> @@ -172,6 +172,8 @@ An inexhaustive list of details to check:
>`details on testing requirements
>`_.
>  
> +* The patch series has passed CI pre-merge testing. See CI details below.
> +
>  * An open source userspace, reviewed and ready for merging by the upstream
>project, must be available for new kernel ABI. Please see `details on
>upstreaming requirements
> @@ -186,11 +188,6 @@ An inexhaustive list of details to check:
>(or the author) stand a chance to fairly quickly understand what goes 
> wrong if
>the commit is reported to cause a regression?
>  
> -* `checkpatch.pl` does not complain. (Some of the more subjective warnings 
> may
> -  be ignored at the committer's discretion.)
> -
> -* The patch does not introduce new `sparse` warnings.
> -
>  * When pushing someone else's patch you must add your own signed-off per
>http://developercertificate.org/. dim apply-branch should do this
>automatically for you.
> @@ -244,8 +241,6 @@ On Confidence, Complexity, and Transparency
>you have involved enough people to feel comfortable if the justification 
> for
>the commit is questioned afterwards.
>  
> -* Make sure pre-merge testing is completed successfully.
> -
>  On Rough Consensus
>  --
>  
> @@ -290,18 +285,34 @@ discussions happen in public forums, and make sure 
> there's a searchable
>  permanent record of any discussions for later reference. This means that for
>  most things internal meetings are not the most suitable venue.
>  
> -Pre-Merge Testing
> --
> +Continuous Integration and Pre-Merge Testing
> +
> +
> +The requirements for CI_ pre-merge testing are:
> +
> +* ``checkpatch.pl`` does not complain. (Some of the more subjective warnings 
> may
> +  be ignored at the committer's discretion.)
> +
> +* The patch does not introduce new ``sparse`` warnings.
> +
> +* Patch series must pass IGT Basic Acceptance Tests (BAT) on all the CI 
> machines
> +  without causing regressions.
> +
> +* Patch series must pass full IGT tests on CI shard machines without causing
> +  regressions.
> +
> +The CI bots will send results to the patch author and intel-gfx for any 
> patches
> +tracked by patchwork. The results are also available on patchwork_ and the 
> CI_
> +site.
> +
> +Check CI failures and make sure any sporadic failures are a) pre-existing,
> +and b) tracked in bugzilla. If there's anything dubious that you can't track
> +down to pre-existing and tracked issues please don't push, but instead figure
> +out what's going on.
>  
> -Our CI infrastructure is being built up and currently requirements for 
> pre-merge
> -testing are fairly simple:
> +.. _CI: https://intel-gfx-ci.01.org/
>  
> -* All patches must past IGT Basic Acceptance Tests (BAT) on all the CI 
> machines
> -  without causing regressions.  The CI bots will send results to intel-gfx 
> for
> -  any patches tracked by patchwork. Check CI failures and make sure any 
> sporadic
> -  failures are a) pre-existing b) tracked in bugzilla. If there's anything
> -  dubious that you can't track down to pre-existing issues please 
> don't
> -  push, but instead figure out what's going on.
> +.. _patchwork: https://patchwork.freedesktop.org/project/intel-gfx/series/
>  
>  Tooling
>  ===
> -- 
> 2.11.0
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/i915: encourage BIT() macro usage in register definitions

[Rodrigo Vivi]

On Wed, Jun 27, 2018 at 05:41:13PM +0300, Jani Nikula wrote:
> There's already some BIT() usage here and there, embrace it.
> 
> Cc: Paulo Zanoni 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 476118f46cf3..64b9c270045d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -65,9 +65,10 @@
>   * but do note that the macros may be needed to read as well as write the
>   * register contents.
>   *
> - * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this 
> in
> - * the future, but this is the prevailing style. Do **not** add ``_BIT`` 
> suffix
> - * to the name.
> + * Define bits using ``BIT(N)`` instead of ``(1 << N)``. Do **not** add 
> ``_BIT``
> + * suffix to the name. Exception to ``BIT()`` usage: Value 1 for a bit field
> + * should be defined using ``(1 << N)`` to be in line with other values such 
> as
> + * ``(2 << N)`` for the same field.
>   *
>   * Group the register and its contents together without blank lines, separate
>   * from other registers and their contents with one blank line.
> @@ -105,7 +106,7 @@
>   *  #define _FOO_A  0xf000
>   *  #define _FOO_B  0xf001
>   *  #define FOO(pipe)   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
> - *  #define   FOO_ENABLE(1 << 31)
> + *  #define   FOO_ENABLEBIT(31)

Oh! I'm sure that I will miss the (1 << n) notation...
and right now we had just converted everything to the documented style...

any chance of get a script modifying all at once?

Anyways:

Acked-by: Rodrigo Vivi 

>   *  #define   FOO_MODE_MASK (0xf << 16)
>   *  #define   FOO_MODE_SHIFT16
>   *  #define   FOO_MODE_BAR  (0 << 16)
> -- 
> 2.11.0
> 
> ___
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Re: [Intel-gfx] [PATCH] drm/i915: Fix CHICKEN_TRANS register offset

[Rodrigo Vivi]

On Wed, Jun 27, 2018 at 04:14:01PM -0700, José Roberto de Souza wrote:
> This registers offsets is not sequential for transcoder D and EDP so
> for EDP transcoder it was writing to 0x420d0 that do not map to
> any register in spec.
> 
> CHICKEN_TRANS is used in PSR2 and intel_enable_ddi_hdmi() to apply
> WA #1143 but I'm not aware of any open issue cause by this offset
> error.
> 
> Spec: 7524
> 
> Cc: Dhinakaran Pandiyan 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 14 +++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c30cfcd90754..098a4cb71310 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7256,9 +7256,17 @@ enum {
>  #define  BDW_DPRS_MASK_VBLANK_SRD(1 << 0)
>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
> _CHICKEN_PIPESL_1_B)
>  
> -#define CHICKEN_TRANS_A 0x420c0
> -#define CHICKEN_TRANS_B 0x420c4
> -#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, 
> CHICKEN_TRANS_B)
> +#define _CHICKEN_TRANS_A 0x420c0
> +#define _CHICKEN_TRANS_B 0x420c4
> +#define _CHICKEN_TRANS_C 0x420c8
> +#define _CHICKEN_TRANS_D 0x420d8

note that enum transcoder has no TRANSCODER_D...

TRANSCODER_EDP = 3
so:
>>> hex(0x420c0+3*4)
'0x420cc'

> +#define _CHICKEN_TRANS_EDP   0x420cc
> +#define CHICKEN_TRANS(trans) _MMIO(_PICK(trans, \
> +_CHICKEN_TRANS_A, \
> +_CHICKEN_TRANS_B, \
> +_CHICKEN_TRANS_C, \
> +_CHICKEN_TRANS_D, \
> +_CHICKEN_TRANS_EDP))
>  #define  VSC_DATA_SEL_SOFTWARE_CONTROL   (1 << 25) /* GLK and CNL+ */
>  #define  DDI_TRAINING_OVERRIDE_ENABLE(1 << 19)
>  #define  DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
> -- 
> 2.18.0
> 
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/9] drm/i915: Drop posting reads to flush master interrupts

[Patchwork]

== Series Details ==

Series: series starting with [1/9] drm/i915: Drop posting reads to flush master 
interrupts
URL   : https://patchwork.freedesktop.org/series/45531/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4392_full -> Patchwork_9455_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9455_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9455_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9455_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-render:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9455_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-glk:  NOTRUN -> INCOMPLETE (fdo#103359, k.org#198133)

igt@drv_selftest@mock_scatterlist:
  shard-glk:  NOTRUN -> DMESG-WARN (fdo#103667)

igt@gem_ctx_isolation@rcs0-s3:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665) +1

igt@gem_exec_schedule@pi-ringfull-bsd:
  shard-glk:  NOTRUN -> FAIL (fdo#103158)

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@prime_vgem@coherency-gtt:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#100587)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  shard-apl:  DMESG-FAIL (fdo#106947, fdo#106560) -> PASS

igt@gem_exec_big:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-hsw:  FAIL (fdo#105363, fdo#102887) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS
  shard-hsw:  FAIL (fdo#99912) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4392 -> Patchwork_9455

  CI_DRM_4392: fa0510c4f4d6e85cba3068f08a83cb56b9fdf668 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9455: 191d5967cda2a65c0193982493b349395823dba4 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9455/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Reduce spinlock hold time during notify_ring() interrupt

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Reduce spinlock hold time during 
notify_ring() interrupt
URL   : https://patchwork.freedesktop.org/series/45527/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4391_full -> Patchwork_9454_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9454_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9454_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9454_full:

  === IGT changes ===

 Possible regressions 

igt@drv_selftest@mock_scatterlist:
  {shard-glk9}:   NOTRUN -> DMESG-WARN

igt@testdisplay:
  {shard-glk9}:   NOTRUN -> INCOMPLETE +1


 Warnings 

igt@gem_linear_blits@interruptible:
  shard-apl:  SKIP -> PASS

igt@gem_mocs_settings@mocs-rc6-blt:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9454_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_schedule@pi-ringfull-vebox:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#103158)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  NOTRUN -> FAIL (fdo#103822, fdo#104724)


 Possible fixes 

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS
  shard-kbl:  FAIL (fdo#99912) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4391 -> Patchwork_9454

  CI_DRM_4391: 9134bde2e681ec232f4d8bec56aa3700177630fe @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9454: 4788e34a2edeb12c5bb8d598a60ec225d6302413 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9454/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v8,1/2] drm/i915/psr: Lockless version of psr_wait_for_idle

[Patchwork]

== Series Details ==

Series: series starting with [v8,1/2] drm/i915/psr: Lockless version of 
psr_wait_for_idle
URL   : https://patchwork.freedesktop.org/series/45524/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4391_full -> Patchwork_9453_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9453_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9453_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9453_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  SKIP -> PASS

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9453_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_gtt:
  shard-glk:  PASS -> FAIL (fdo#105347)

igt@drv_suspend@shrink:
  shard-apl:  PASS -> FAIL (fdo#106886, fdo#107054)

igt@gem_exec_big:
  shard-hsw:  PASS -> INCOMPLETE (fdo#103540)

igt@gem_exec_schedule@pi-ringfull-bsd1:
  shard-kbl:  NOTRUN -> FAIL (fdo#103158)

igt@gem_exec_schedule@pi-ringfull-render:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#103158)

igt@gem_exec_schedule@preemptive-hang-render:
  shard-snb:  SKIP -> INCOMPLETE (fdo#105411)

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  NOTRUN -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-x-tiled:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#104724)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103822)

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#103167, fdo#104724)

igt@kms_setmode@basic:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#99912)


 Possible fixes 

igt@gem_ctx_isolation@rcs0-s3:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  FAIL (fdo#104724, fdo#103822) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4391 -> Patchwork_9453

  CI_DRM_4391: 9134bde2e681ec232f4d8bec56aa3700177630fe @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9453: 7a0d28ca8e878141795a1f3044fd373ad5593ac9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9453/shards.html
___
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[Intel-gfx] [PULL] drm-misc-next

[Gustavo Padovan]

Hi Dave,

One more for 4.19. We don't have any big change on this one,
it is mostly drivers updates here. Please pull.

Regards,

Gustavo

drm-misc-next-2018-06-27:
drm-misc-next for 4.19:

Cross-subsystem Changes:
devicetree documentation
dt-bindings defintions for sun8i (Jernej Skrabec)

Core Changes:
Consider drivers setting DRIVER_ATOMIC as atomic (Eric Anholt)
Improvements for in-kernel clients (Noralf Trønnes)
Export and rename drm_crtc_port_mask() (Jernej Skrabec)

Driver Changes:
v3d: Add looking for GPU scheduler jobs management (Eric Anholt)
Add Ilitek ILI9881c panel driver(Maxime Ripard)
rockchip: vop: fixup linebuffer mode calc error (Sandy Huang)
tinydrm: new driver for ILI9341 display panels (David Lechner)
sun4i: Add TCON TOP driver (Jernej Skrabec)
The following changes since commit c612ae0503af753c062594dcd14aecea121fa414:

  staging: android: ion: fix ion_dma_buf_attach signatur (2018-06-21 11:46:47 
+0200)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2018-06-27

for you to fetch changes up to 57e23de02f4878061818fd118129a6b0e1516b11:

  drm/sun4i: DW HDMI: Expand algorithm for possible crtcs (2018-06-27 21:44:05 
+0200)


drm-misc-next for 4.19:

Cross-subsystem Changes:
devicetree documentation
dt-bindings defintions for sun8i (Jernej Skrabec)

Core Changes:
Consider drivers setting DRIVER_ATOMIC as atomic (Eric Anholt)
Improvements for in-kernel clients (Noralf Trønnes)
Export and rename drm_crtc_port_mask() (Jernej Skrabec)

Driver Changes:
v3d: Add looking for GPU scheduler jobs management (Eric Anholt)
Add Ilitek ILI9881c panel driver(Maxime Ripard)
rockchip: vop: fixup linebuffer mode calc error (Sandy Huang)
tinydrm: new driver for ILI9341 display panels (David Lechner)
sun4i: Add TCON TOP driver (Jernej Skrabec)


Christian König (1):
  drm/omap: remove now unused functions

David Herrmann (1):
  drm: provide management functions for drm_file

David Lechner (4):
  MAINTAINERS: fix path to ilitek, ili9225 device tree bindings
  dt-bindings: Add vendor prefix for Adafruit
  dt-bindings: new binding for Ilitek ILI9341 display panels
  drm/tinydrm: new driver for ILI9341 display panels

Eric Anholt (4):
  drm/bridge: Move the struct drm_bridge member kerneldoc inline.
  drm/v3d: Take a lock across GPU scheduler job creation and queuing.
  drm/v3d: Remove the bad signaled() implementation.
  drm: Consider drivers setting DRIVER_ATOMIC as atomic.

Gustavo A. R. Silva (2):
  drm/gma500: Fix potential NULL pointer dereference
  drm/gma500: Fix compile warning

Jernej Skrabec (18):
  dt-bindings: display: sunxi-drm: Add TCON TOP description
  drm/sun4i: Add TCON TOP driver
  drm/sun4i: Fix releasing node when enumerating enpoints
  drm/sun4i: Split out code for enumerating endpoints in output port
  drm/sun4i: Add support for traversing graph with TCON TOP
  drm/sun4i: Don't skip TCONs if they don't have channel 0
  drm/sun4i: tcon: Generalize engine search algorithm
  drm/sun4i: Don't check for LVDS and RGB when TCON has only ch1
  drm/sun4i: Don't check for panel or bridge on TV TCONs
  drm/sun4i: Add support for R40 mixers
  dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY
  drm/sun4i: Enable DW HDMI PHY clock
  drm/sun4i: Don't change clock bits in DW HDMI PHY driver
  drm/sun4i: DW HDMI PHY: Add support for second PLL
  drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driver
  drm/sun4i: Add support for A64 HDMI PHY
  drm: of: Export and rename drm_crtc_port_mask()
  drm/sun4i: DW HDMI: Expand algorithm for possible crtcs

John Stultz (1):
  drm: kirin: Remove useless "Scale not support" error message

Maxime Ripard (2):
  dt-bindings: panel: Add the Ilitek ILI9881c panel documentation
  drm/panel: Add Ilitek ILI9881c panel driver

Noralf Trønnes (2):
  drm/file: Don't set master on in-kernel clients
  drm: Make ioctls available for in-kernel clients

Sandy Huang (1):
  drm/rockchip: vop: fixup linebuffer mode calc error

Souptick Joarder (1):
  gpu: drm: vc4: Adding new typedef vm_fault_t

Thomas Zimmermann (1):
  drm/gma500: Replace drm_gem_object_unreference_unlocked with put function

Ville Syrjälä (2):
  drm: Document mode_config.max_width/height as the max fb dimensions
  drm/rockchip: Use drm_crtc_mask()

 .../devicetree/bindings/display/ilitek,ili9341.txt |  27 ++
 .../bindings/display/panel/ilitek,ili9881c.txt |  20 +
 .../bindings/display/sunxi/sun4i-drm.txt   |  60 ++-
 .../devicetree/bindings/vendor-prefixes.txt|   1 +
 MAINTAINERS|   8 +-
 drivers/gpu/drm/drm_crtc_internal.h|  19 +-
 drivers/gpu/drm/drm_dumb_buffers.c

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix assert_plane() warning on bootup with external display (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix assert_plane() warning on bootup with external display 
(rev5)
URL   : https://patchwork.freedesktop.org/series/44909/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/intel_display.o
drivers/gpu/drm/i915/intel_display.c: In function ‘intel_modeset_init’:
drivers/gpu/drm/i915/intel_display.c:15285:5: error: ‘num_active_crtcs’ may be 
used uninitialized in this function [-Werror=maybe-uninitialized]
  if (num_active_crtcs > 1) {
 ^
cc1: all warnings being treated as errors
scripts/Makefile.build:317: recipe for target 
'drivers/gpu/drm/i915/intel_display.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1
scripts/Makefile.build:558: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:558: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:558: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1034: recipe for target 'drivers' failed
make: *** [drivers] Error 2

___
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[Intel-gfx] [PATCH v5] drm/i915: Fix assert_plane() warning on bootup with external display

[Azhar Shaikh]

On KBL, WHL RVPs, booting up with an external display connected, triggers
below warning, when the BiOS brings up the external display too.
This warning is not seen during hotplug.

[3.615226] [ cut here ]
[3.619829] plane 1A assertion failure (expected on, current off)
[3.632039] WARNING: CPU: 2 PID: 354 at 
drivers/gpu/drm/i915/intel_display.c:1294 assert_plane+0x71/0xbb
[3.633920] iwlwifi :00:14.3: loaded firmware version 38.c0e03d94.0 
op_mode iwlmvm
[3.647157] Modules linked in: iwlwifi cfg80211 btusb btrtl btbcm btintel 
bluetooth ecdh_generic
[3.647163] CPU: 2 PID: 354 Comm: frecon Not tainted 
4.17.0-rc7-50176-g655af12d39c2 #3
[3.647165] Hardware name: Intel Corporation CoffeeLake Client 
Platform/WhiskeyLake U DDR4 ERB, BIOS CNLSFWR1.R00.X140.B00.1804040304 
04/04/2018
[3.684509] RIP: 0010:assert_plane+0x71/0xbb
[3.764451] Call Trace:
[3.766888]  intel_atomic_commit_tail+0xa97/0xb77
[3.771569]  intel_atomic_commit+0x26a/0x279
[3.771572]  drm_atomic_helper_set_config+0x5c/0x76
[3.780670]  __drm_mode_set_config_internal+0x66/0x109
[3.780672]  drm_mode_setcrtc+0x4c9/0x5cc
[3.780674]  ? drm_mode_getcrtc+0x162/0x162
[3.789774]  ? drm_mode_getcrtc+0x162/0x162
[3.798108]  drm_ioctl_kernel+0x8d/0xe4
[3.801926]  drm_ioctl+0x27d/0x368
[3.805311]  ? drm_mode_getcrtc+0x162/0x162
[3.805314]  ? selinux_file_ioctl+0x14e/0x199
[3.805317]  vfs_ioctl+0x21/0x2f
[3.813812]  do_vfs_ioctl+0x491/0x4b4
[3.813813]  ? security_file_ioctl+0x37/0x4b
[3.813816]  ksys_ioctl+0x55/0x75
[3.820672]  __x64_sys_ioctl+0x1a/0x1e
[3.820674]  do_syscall_64+0x51/0x5f
[3.820678]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[3.828221] RIP: 0033:0x7b5e04953967
[3.835504] RSP: 002b:7fff2eafb6f8 EFLAGS: 0246 ORIG_RAX: 
0010
[3.835505] RAX: ffda RBX: 0002 RCX: 7b5e04953967
[3.835505] RDX: 7fff2eafb730 RSI: c06864a2 RDI: 000f
[3.835506] RBP: 7fff2eafb720 R08:  R09: 
[3.835507] R10: 0070 R11: 0246 R12: 000f
[3.879988] R13: 56bc9dd7d210 R14: 7fff2eafb730 R15: c06864a2
[3.887081] Code: 48 c7 c7 06 71 a5 be 84 c0 48 c7 c2 06 fd a3 be 48 89 f9 
48 0f 44 ca 84 db 48 0f 45 d7 48 c7 c7 df d3 a4 be 31 c0 e8 af a0 c0 ff <0f> 0b 
eb 2b 48 c7 c7 06 fd a3 be 84 c0 48 c7 c2 06 71 a5 be 48
[3.905845] WARNING: CPU: 2 PID: 354 at 
drivers/gpu/drm/i915/intel_display.c:1294 assert_plane+0x71/0xbb
[3.920964] ---[ end trace dac692f4ac46391a ]---

The warning is seen when mode_setcrtc() is called for pipeB
during bootup and before we get a mode_setcrtc() for pipeA,
while doing update_crtcs() in intel_atomic_commit_tail().
Now since, plane1A is still active after commit, update_crtcs()
is done for pipeA and eventually update_plane() for plane1A.

intel_plane_state->ctl for plane1A is not updated since set_modecrtc() is
called for pipeB. So intel_plane_state->ctl for plane 1A will be 0x0.
So doing an update_plane() for plane1A, will result in clearing
PLANE_CTL_ENABLE bit, and hence the warning.

To fix this warning, force all active planes to recompute their states
in probe.

Changes in v5:
- Drop drm_modeset_lock_all_ctx() since locks will be taken later.

Changes in v4:
- Handle locking in intel_initial_commit()
- Move the for loop inside intel_initial_commit() so that
  drm_atomic_commit() is called only once
- Call intel_initial_commit() only for more than one active crtc on boot.
- Save the return value of intel_initial_commit() and print a message in
  case of an error

Changes in v3:
- Add comments

Changes in v2:
- Force all planes to recompute their states.(Ville Syrjälä)
- Update the commit message

Signed-off-by: Azhar Shaikh 
Cc: Ville Syrjälä 
Cc: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/intel_display.c | 71 +++-
 1 file changed, 69 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3709fa1b6318..866ebbac30e9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15092,12 +15092,66 @@ static void intel_update_fdi_pll_freq(struct 
drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
 }
 
+static int intel_initial_commit(struct drm_device *dev)
+{
+   struct drm_atomic_state *state = NULL;
+   struct drm_modeset_acquire_ctx ctx;
+   struct drm_crtc_state *crtc_state;
+   struct intel_crtc *intel_crtc;
+   int ret = 0;
+
+   state = drm_atomic_state_alloc(dev);
+   if (!state)
+   return -ENOMEM;
+
+   drm_modeset_acquire_init(, 0);
+
+retry:
+   state->acquire_ctx = 
+
+   for_each_intel_crtc(dev, intel_crtc) {
+   struct drm_crtc *crtc = _crtc->base;
+
+  

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix CHICKEN_TRANS register offset

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CHICKEN_TRANS register offset
URL   : https://patchwork.freedesktop.org/series/45536/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4392 -> Patchwork_9456 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45536/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9456 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-dpms:
  fi-skl-6700hq:  PASS -> DMESG-WARN (fdo#105998, fdo#107054)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927, fdo#107054)

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: PASS -> FAIL (fdo#104008)


  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4392 -> Patchwork_9456

  CI_DRM_4392: fa0510c4f4d6e85cba3068f08a83cb56b9fdf668 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9456: dc2c463beb7c24876f33d086d2fb3c9427fe576e @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

dc2c463beb7c drm/i915: Fix CHICKEN_TRANS register offset

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9456/issues.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to 
gen8_pte_encode
URL   : https://patchwork.freedesktop.org/series/45519/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4390_full -> Patchwork_9451_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9451_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9451_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9451_full:

  === IGT changes ===

 Possible regressions 

igt@gem_userptr_blits@usage-restrictions:
  shard-kbl:  PASS -> FAIL
  shard-glk:  PASS -> FAIL
  shard-apl:  PASS -> FAIL


 Warnings 

igt@gem_exec_schedule@deep-blt:
  shard-kbl:  SKIP -> PASS

igt@kms_cursor_legacy@cursora-vs-flipa-legacy:
  shard-snb:  SKIP -> PASS +1


== Known issues ==

  Here are the changes found in Patchwork_9451_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_hangcheck:
  shard-apl:  PASS -> DMESG-FAIL (fdo#106560, fdo#106947)

igt@gem_exec_schedule@pi-ringfull-blt:
  shard-glk:  NOTRUN -> FAIL (fdo#103158)

igt@gem_exec_schedule@pi-ringfull-bsd:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#103158)

igt@gem_softpin@noreloc-s3:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#106509, fdo#105454)

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip@flip-vs-expired-vblank:
  shard-hsw:  PASS -> FAIL (fdo#105363, fdo#102887)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  NOTRUN -> FAIL (fdo#103822, fdo#104724)


 Possible fixes 

igt@gem_ctx_isolation@rcs0-s3:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@gem_ctx_switch@basic-all-light:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@kms_flip@dpms-vs-vblank-race:
  shard-glk:  FAIL (fdo#103060) -> PASS

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4390 -> Patchwork_9451

  CI_DRM_4390: fbe6c535c4179a7eb1e23a7cd20db612822eed2a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9451: 0a9bd1dfbdf1d543745267e086bbad6b13813687 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9451/shards.html
___
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[Intel-gfx] [PATCH] drm/i915: Fix CHICKEN_TRANS register offset

[José Roberto de Souza]

This registers offsets is not sequential for transcoder D and EDP so
for EDP transcoder it was writing to 0x420d0 that do not map to
any register in spec.

CHICKEN_TRANS is used in PSR2 and intel_enable_ddi_hdmi() to apply
WA #1143 but I'm not aware of any open issue cause by this offset
error.

Spec: 7524

Cc: Dhinakaran Pandiyan 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_reg.h | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c30cfcd90754..098a4cb71310 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7256,9 +7256,17 @@ enum {
 #define  BDW_DPRS_MASK_VBLANK_SRD  (1 << 0)
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
_CHICKEN_PIPESL_1_B)
 
-#define CHICKEN_TRANS_A 0x420c0
-#define CHICKEN_TRANS_B 0x420c4
-#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, 
CHICKEN_TRANS_B)
+#define _CHICKEN_TRANS_A 0x420c0
+#define _CHICKEN_TRANS_B 0x420c4
+#define _CHICKEN_TRANS_C 0x420c8
+#define _CHICKEN_TRANS_D 0x420d8
+#define _CHICKEN_TRANS_EDP   0x420cc
+#define CHICKEN_TRANS(trans) _MMIO(_PICK(trans, \
+  _CHICKEN_TRANS_A, \
+  _CHICKEN_TRANS_B, \
+  _CHICKEN_TRANS_C, \
+  _CHICKEN_TRANS_D, \
+  _CHICKEN_TRANS_EDP))
 #define  VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
 #define  DDI_TRAINING_OVERRIDE_ENABLE  (1 << 19)
 #define  DDI_TRAINING_OVERRIDE_VALUE   (1 << 18)
-- 
2.18.0

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Re: [Intel-gfx] [PATCH V2] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

[Clint Taylor]

On 06/25/2018 03:33 AM, Imre Deak wrote:

On Wed, Jun 13, 2018 at 02:48:49PM -0700, clinton.a.tay...@intel.com wrote:

From: Clint Taylor 

On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.

When measured on a scope the highspeed lines of the HDMI clock turn off
  for ~400uS during a normal resolution change. The HDMI retimer on the
  GLK NUC appears to require at least a full frame of quiet time before a
new faster clock can be correctly sync'd. The worst case scenario appears
to be 23.98Hz modes which requires a wait of 41.25ms. Add a quirk to the
driver for GLK NUC that waits 42ms.

V2: Add more devices to the quirk list

Cc: Imre Deak 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
Signed-off-by: Clint Taylor 
---
  drivers/gpu/drm/i915/i915_drv.h  |  1 +
  drivers/gpu/drm/i915/intel_ddi.c |  8 
  drivers/gpu/drm/i915/intel_display.c | 19 +++
  3 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be8c2f0..da196b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -656,6 +656,7 @@ enum intel_sbi_destination {
  #define QUIRK_BACKLIGHT_PRESENT (1<<3)
  #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
  #define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
  
  struct intel_fbdev;

  struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ca73387..bc3d012 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1791,6 +1791,9 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
  }
  
+/* Quirk time computed based on 24fps frame time of 41.25ms */

+#define DDI_DISABLED_QUIRK_TIME 42
+
  void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
   enum transcoder cpu_transcoder)
  {
@@ -1800,6 +1803,11 @@ void intel_ddi_disable_transcoder_func(struct 
drm_i915_private *dev_priv,
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
+
+   if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME) {
+   msleep(DDI_DISABLED_QUIRK_TIME);
+   DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");

No need for the define or the debug message here imo. msleep() can be
inaccurate (even sleeping less than expected), so I'd use a bigger
margin, sleeping say 100ms.


Easy to do and I can submit v3.



If the problem is with the HDMI retimer chip, we should limit the quirk
to HDMI outputs.
Output type is not available in intel_disable_ddi() and I would prefer 
not to change the interface only for the quirk. I could move the quirk 
execution up a level to haswell_crtc_disable() and detect the 
old_crtc_state->type before executing the quirk. However, the quirk is 
only being detected for certain boards that only have HDMI outputs. 
Unless more boards are added to the quirk_list[] we really don't need 
logic to detect HDMI outputs.


-Clint


+   }
  }
  
  int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8251e18..40e0306 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14749,6 +14749,17 @@ static void quirk_increase_t12_delay(struct drm_device 
*dev)
DRM_INFO("Applying T12 delay quirk\n");
  }
  
+/* GeminiLake NUC HDMI outputs require additional off time

+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = to_i915(dev);
+
+   dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+   DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
  struct intel_quirk {
int device;
int subsystem_vendor;
@@ -14835,6 +14846,14 @@ static int intel_dmi_reverse_brightness(const struct 
dmi_system_id *id)
  
  	/* Toshiba Satellite P50-C-18C */

{ 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+   /* GeminiLake NUC */
+   { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+   /* ASRock ITX*/
+   { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+   { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+

Extra w/s. A quirk list looks ok for now since we can't identify the
retimer chip in any other way.


  };
  
  static void intel_init_quirks(struct drm_device *dev)

--
1.9.1



___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Drop posting reads to flush master interrupts

[Patchwork]

== Series Details ==

Series: series starting with [1/9] drm/i915: Drop posting reads to flush master 
interrupts
URL   : https://patchwork.freedesktop.org/series/45531/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4392 -> Patchwork_9455 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45531/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9455 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@prime_vgem@basic-fence-flip:
  fi-byt-n2820:   PASS -> FAIL (fdo#104008)


  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4392 -> Patchwork_9455

  CI_DRM_4392: fa0510c4f4d6e85cba3068f08a83cb56b9fdf668 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9455: 191d5967cda2a65c0193982493b349395823dba4 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

191d5967cda2 drm/i915/execlists: Direct submission of new requests (avoid 
tasklet/ksoftirqd)
c0c2e4c7254a drm/i915/execlists: Trust the CSB
f9d017e3025c drm/i915/execlists: Stop storing the CSB read pointer in the mmio 
register
a395c426e0ef drm/i915/execlists: Reset CSB write pointer after reset
adcb871cf5c4 drm/i915/execlists: Unify CSB access pointers
bf1d86422d87 drm/i915/execlists: Process one CSB update at a time
03ce62d8f412 drm/i915/execlists: Pull CSB reset under the timeline.lock
79dff3d56d42 drm/i915/execlists: Pull submit after dequeue under timeline lock
e95bd2fda39a drm/i915: Drop posting reads to flush master interrupts

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9455/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Wait for engines to idle before retiring

[Patchwork]

== Series Details ==

Series: drm/i915: Wait for engines to idle before retiring
URL   : https://patchwork.freedesktop.org/series/45484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4389_full -> Patchwork_9450_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9450_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9450_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9450_full:

  === IGT changes ===

 Possible regressions 

igt@testdisplay:
  {shard-glk9}:   NOTRUN -> INCOMPLETE


 Warnings 

igt@gem_linear_blits@interruptible:
  shard-apl:  PASS -> SKIP

igt@perf_pmu@rc6:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9450_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_schedule@pi-ringfull-vebox:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#103158)

igt@gem_mmap_gtt@coherency:
  shard-glk:  NOTRUN -> FAIL (fdo#100587)

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  NOTRUN -> FAIL (fdo#105454, fdo#106509)

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103822)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-glk:  FAIL (fdo#105347) -> PASS

igt@gem_ctx_isolation@rcs0-s3:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@gem_exec_big:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#104724, fdo#103822) -> PASS

igt@kms_rotation_crc@sprite-rotation-90:
  shard-apl:  FAIL (fdo#104724, fdo#103925) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4389 -> Patchwork_9450

  CI_DRM_4389: 2a8b5fa69bd30a6068e4ca4aadf72867f3a2351f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9450: f2c5deeffc3a3ce60f92c35cb4e6049f099ec889 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9450/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/icp: Add Interrupt Support

[Paulo Zanoni]

Em Ter, 2018-06-26 às 13:52 -0700, Anusha Srivatsa escreveu:
> This patch addresses Interrupts from south display engine (SDE).
> 
> ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> Introduce these registers and their intended values.
> 
> Introduce icp_irq_handler().
> 
> The icp_irq_postinstall() takes care of
> enabling all PCH interrupt sources, to unmask
> them as needed with SDEIMR, as is done
> done by ibx_irq_pre_postinstall() for earlier platforms.
> We do not need to explicitly call the ibx_irq_pre_postinstall().
> 
> Also, while changing these,
> s/CPT/PPT/CPT-CNP comment.
> 
> v2:
> - remove redundant register defines.(Lucas)
> - Change register names to be more consistent with
> previous platforms (Lucas)
> 
> v3:
> -Reorder bit defines to a more appropriate location.
>  Change the comments. Confirm in the commit message that
>  icp_irq_postinstall() need not go to
>  ibx_irq_pre_postinstall() and ibx_irq_postinstall()
>  as in earlier platforms. (Paulo)
> 
> Cc: Lucas De Marchi 
> Cc: Paulo Zanoni 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjala 
> Signed-off-by: Anusha Srivatsa 
> [Paulo: coding style bikesheds and rebases].
> Signed-off-by: Paulo Zanoni 

Merged. Thanks everybody for the help.


> ---
>  drivers/gpu/drm/i915/i915_irq.c | 134
> +++-
>  drivers/gpu/drm/i915/i915_reg.h |  42 -
>  2 files changed, 173 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 46aaef5..7a7c4a2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -122,6 +122,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
>   [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
>  };
>  
> +static const u32 hpd_icp[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
> + [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
> + [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
> + [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
> + [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
> +};
> +
>  /* IIR can theoretically queue up two events. Be paranoid. */
>  #define GEN8_IRQ_RESET_NDX(type, which) do { \
>   I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum
> port port, u32 val)
>   }
>  }
>  
> +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> val)
> +{
> + switch (port) {
> + case PORT_A:
> + return val & ICP_DDIA_HPD_LONG_DETECT;
> + case PORT_B:
> + return val & ICP_DDIB_HPD_LONG_DETECT;
> + default:
> + return false;
> + }
> +}
> +
> +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_C:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> + case PORT_D:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> + case PORT_E:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> + case PORT_F:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> + default:
> + return false;
> + }
> +}
> +
>  static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
>  {
>   switch (port) {
> @@ -2385,6 +2422,43 @@ static void cpt_irq_handler(struct
> drm_i915_private *dev_priv, u32 pch_iir)
>   cpt_serr_int_handler(dev_priv);
>  }
>  
> +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> pch_iir)
> +{
> + u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> + u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> + u32 pin_mask = 0, long_mask = 0;
> +
> + if (ddi_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, _mask, _mask,
> +ddi_hotplug_trigger,
> +dig_hotplug_reg, hpd_icp,
> +icp_ddi_port_hotplug_long_detect)
> ;
> + }
> +
> + if (tc_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, _mask, _mask,
> +tc_hotplug_trigger,
> +dig_hotplug_reg, hpd_icp,
> +icp_tc_port_hotplug_long_detect);
> + }
> +
> + if (pin_mask)
> + intel_hpd_irq_handler(dev_priv, pin_mask,
> long_mask);
> +
> + if (pch_iir & SDE_GMBUS_ICP)
> + gmbus_irq_handler(dev_priv);
> +}
> +
>  static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> pch_iir)
>  {
>   u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> 

Re: [Intel-gfx] [PATCH] ALSA: hda - Handle pm failure during hotplug

[Takashi Iwai]

On Wed, 27 Jun 2018 08:30:37 +0200,
Takashi Iwai wrote:
> 
> On Wed, 27 Jun 2018 08:25:32 +0200,
> Chris Wilson wrote:
> > 
> > Obtaining the runtime pm wakeref can fail, especially in a hotplug
> > scenario where i915.ko has been unloaded. If we do not catch the
> > failure, we end up with an unbalanced pm.
> > 
> > References: 222bde03881c ("ALSA: hda - Fix mutex deadlock at HDMI/DP 
> > hotplug")
> > Signed-off-by: Chris Wilson 
> > Cc: Ville Syrjälä 
> > Cc: Takashi Iwai 
> > Cc: Vinod Koul 
> 
> Thanks, applied with Cc to stable.

After the disaster (not about football game but of my further fix
patch), I revisited this change, and found that it's also buggy.

When pm_runtime_get_sync() returns an error, it doesn't decrement the
refcount.  That is, you'd need to call pm_runtime_put_noidle() or
whatever after getting the error.

And, pm_runtime_get_sync() returns 1, not only a negative error.
So, non-zero check is anyway incorrect.

Due to these reasons, I nuked the commit again.

For the HDMI error without i915 binding, I'll resubmit the proper
patch to disable HDMI codec after i915 component bind failure, as an
alternative workaround.  The previous patch didn't work as expected.


thanks,

Takashi
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915: Drop posting reads to flush master interrupts

[Patchwork]

== Series Details ==

Series: series starting with [1/9] drm/i915: Drop posting reads to flush master 
interrupts
URL   : https://patchwork.freedesktop.org/series/45531/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e95bd2fda39a drm/i915: Drop posting reads to flush master interrupts
79dff3d56d42 drm/i915/execlists: Pull submit after dequeue under timeline lock
03ce62d8f412 drm/i915/execlists: Pull CSB reset under the timeline.lock
bf1d86422d87 drm/i915/execlists: Process one CSB update at a time
-:68: WARNING:MEMORY_BARRIER: memory barrier without comment
#68: FILE: drivers/gpu/drm/i915/intel_lrc.c:966:
+   smp_mb__after_atomic();

-:114: WARNING:LONG_LINE: line over 100 characters
#114: FILE: drivers/gpu/drm/i915/intel_lrc.c:990:
+ head, GEN8_CSB_READ_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",

-:115: WARNING:LONG_LINE: line over 100 characters
#115: FILE: drivers/gpu/drm/i915/intel_lrc.c:991:
+ tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");

-:183: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#183: FILE: drivers/gpu/drm/i915/intel_lrc.c:1022:
+ status, buf[2*head + 1],
   ^

-:211: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#211: FILE: drivers/gpu/drm/i915/intel_lrc.c:1040:
+   buf[2*head + 1] == execlists->preempt_complete_status) {
 ^

total: 0 errors, 3 warnings, 2 checks, 316 lines checked
adcb871cf5c4 drm/i915/execlists: Unify CSB access pointers
a395c426e0ef drm/i915/execlists: Reset CSB write pointer after reset
f9d017e3025c drm/i915/execlists: Stop storing the CSB read pointer in the mmio 
register
c0c2e4c7254a drm/i915/execlists: Trust the CSB
191d5967cda2 drm/i915/execlists: Direct submission of new requests (avoid 
tasklet/ksoftirqd)
-:104: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#104: 
References: 27af5eea54d1 ("drm/i915: Move execlists irq handler to a bottom 
half")

-:104: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit 
<12+ chars of sha1> ("")' - ie: 'commit 27af5eea54d1 ("drm/i915: 
Move execlists irq handler to a bottom half")'
#104: 
References: 27af5eea54d1 ("drm/i915: Move execlists irq handler to a bottom 
half")

total: 1 errors, 1 warnings, 0 checks, 178 lines checked

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[Intel-gfx] [PATCH i-g-t] igt/drv_module_reload: Revamp fault-injection

[Chris Wilson]

The current method of checking for a failed module load is flawed, as we
only report the error on probing it is not being reported back by
modprobe. So we have to dig inside the module_parameters while the
module is still loaded to discover the error.

v2: Expect i915.inject_load_failure to be zero on success

Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
Cc: Imre Deak 
Reviewed-by: Michał Winiarski 
---
 tests/drv_module_reload.c | 47 ++-
 1 file changed, 42 insertions(+), 5 deletions(-)

diff --git a/tests/drv_module_reload.c b/tests/drv_module_reload.c
index 3046d8227..57e5b50ec 100644
--- a/tests/drv_module_reload.c
+++ b/tests/drv_module_reload.c
@@ -234,6 +234,40 @@ reload(const char *opts_i915)
return err;
 }
 
+static int open_parameters(const char *module_name)
+{
+   char path[256];
+
+   snprintf(path, sizeof(path), "/sys/module/%s/parameters", module_name);
+   return open(path, O_RDONLY);
+}
+
+static int
+inject_fault(const char *module_name, const char *opt, int fault)
+{
+   char buf[1024];
+   int dir;
+
+   igt_assert(fault > 0);
+   snprintf(buf, sizeof(buf), "%s=%d", opt, fault);
+
+   if (igt_kmod_load(module_name, buf)) {
+   igt_warn("Failed to load module '%s' with options '%s'\n",
+module_name, buf);
+   return 1;
+   }
+
+   dir = open_parameters(module_name);
+   igt_sysfs_scanf(dir, opt, "%d", );
+   close(dir);
+
+   igt_debug("Loaded '%s %s', result=%d\n", module_name, buf, fault);
+
+   igt_kmod_unload(module_name, 0);
+
+   return fault;
+}
+
 static void
 gem_sanitycheck(void)
 {
@@ -320,12 +354,15 @@ igt_main
igt_assert_eq(reload("disable_display=1"), 0);
 
igt_subtest("basic-reload-inject") {
-   char buf[64];
int i = 0;
-   do {
-   snprintf(buf, sizeof(buf),
-"inject_load_failure=%d", ++i);
-   } while (reload(buf));
+
+   igt_i915_driver_unload();
+
+   while (inject_fault("i915", "inject_load_failure", ++i) == 0)
+   ;
+
+   /* We expect to hit at least one fault! */
+   igt_assert(i > 1);
}
 
igt_fixture {
-- 
2.18.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Reduce spinlock hold time during notify_ring() interrupt

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Reduce spinlock hold time during 
notify_ring() interrupt
URL   : https://patchwork.freedesktop.org/series/45527/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4391 -> Patchwork_9454 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45527/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9454 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


 Possible fixes 

igt@gem_ctx_create@basic-files:
  fi-glk-dsi: DMESG-WARN (fdo#106954) -> PASS


  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#106954 https://bugs.freedesktop.org/show_bug.cgi?id=106954


== Participating hosts (44 -> 40) ==

  Additional (1): fi-byt-j1900 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4391 -> Patchwork_9454

  CI_DRM_4391: 9134bde2e681ec232f4d8bec56aa3700177630fe @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9454: 4788e34a2edeb12c5bb8d598a60ec225d6302413 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4788e34a2ede drm/i915: Only signal from interrupt when requested
02f0fc1f0fcb drm/i915: Move the irq_counter inside the spinlock
e209cc72ebfc drm/i915: Only trigger missed-seqno checking next to boundary
1f5a0a938f95 drm/i915: Reduce spinlock hold time during notify_ring() interrupt

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9454/issues.html
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[Intel-gfx] [PATCH 8/9] drm/i915/execlists: Trust the CSB

[Chris Wilson]

Now that we use the CSB stored in the CPU friendly HWSP, we do not need
to track interrupts for when the mmio CSB registers are valid and can
just check where we read up to last from the cached HWSP. This means we
can forgo the atomic bit tracking from interrupt, and in the next patch
it means we can check the CSB at any time.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_irq.c | 11 ++-
 drivers/gpu/drm/i915/intel_engine_cs.c  |  8 ++
 drivers/gpu/drm/i915/intel_lrc.c| 38 ++---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 -
 4 files changed, 14 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3702992f9f75..44fb11ca3cab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1469,15 +1469,10 @@ static void snb_gt_irq_handler(struct drm_i915_private 
*dev_priv,
 static void
 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
 {
-   struct intel_engine_execlists * const execlists = >execlists;
bool tasklet = false;
 
-   if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
-   if (READ_ONCE(engine->execlists.active)) {
-   set_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
-   tasklet = true;
-   }
-   }
+   if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
+   tasklet = true;
 
if (iir & GT_RENDER_USER_INTERRUPT) {
notify_ring(engine);
@@ -1485,7 +1480,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 
iir)
}
 
if (tasklet)
-   tasklet_hi_schedule(>tasklet);
+   tasklet_hi_schedule(>execlists.tasklet);
 }
 
 static void gen8_gt_irq_ack(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7209c22798e6..ace93958689e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1353,12 +1353,10 @@ static void intel_engine_print_registers(const struct 
intel_engine_cs *engine,
ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
read = GEN8_CSB_READ_PTR(ptr);
write = GEN8_CSB_WRITE_PTR(ptr);
-   drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d 
from hws], interrupt posted? %s, tasklet queued? %s (%s)\n",
+   drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d 
from hws], tasklet queued? %s (%s)\n",
   read, execlists->csb_head,
   write,
   intel_read_status_page(engine, 
intel_hws_csb_write_index(engine->i915)),
-  yesno(test_bit(ENGINE_IRQ_EXECLIST,
- >irq_posted)),
   yesno(test_bit(TASKLET_STATE_SCHED,
  >execlists.tasklet.state)),
   
enableddisabled(!atomic_read(>execlists.tasklet.count)));
@@ -1570,11 +1568,9 @@ void intel_engine_dump(struct intel_engine_cs *engine,
spin_unlock(>rb_lock);
local_irq_restore(flags);
 
-   drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s) (execlists? %s)\n",
+   drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s)\n",
   engine->irq_posted,
   yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
- >irq_posted)),
-  yesno(test_bit(ENGINE_IRQ_EXECLIST,
  >irq_posted)));
 
drm_printf(m, "HWSP:\n");
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a6268103663f..87dd8ee117c8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -874,14 +874,6 @@ static void reset_irq(struct intel_engine_cs *engine)
smp_store_mb(engine->execlists.active, 0);
 
clear_gtiir(engine);
-
-   /*
-* The port is checked prior to scheduling a tasklet, but
-* just in case we have suspended the tasklet to do the
-* wedging make sure that when it wakes, it decides there
-* is no work to do by clearing the irq_posted bit.
-*/
-   clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
 }
 
 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
@@ -972,10 +964,6 @@ static void process_csb(struct intel_engine_cs *engine)
const u32 * const buf = execlists->csb_status;
u8 head, tail;
 
-   /* Clear before reading to catch new interrupts */
-   clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
-   smp_mb__after_atomic();
-
/* Note that csb_write, csb_status may be either in HWSP or mmio */
head = execlists->csb_head;
tail = READ_ONCE(*execlists->csb_write);
@@ -,11 +1099,10 @@ static void execlists_submission_tasklet(unsigned long 
data)
 {
struct intel_engine_cs * 

[Intel-gfx] [PATCH 9/9] drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)

[Chris Wilson]

Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on average! Deferring our work to a tasklet allowed us to do the
processing with irqs enabled, reducing the impact to an average of about
50us.

We have since eradicated the use of forcewaked mmio from inside the CSB
processing and ELSP submission, bringing the impact down to around 5us
(on Kabylake); an order of magnitude better than our measurements 2
years ago on Broadwell and only about 2x worse on average than the
gem_syslatency on an unladen system.

In this iteration of the tasklet-vs-direct submission debate, we seek a
compromise where by we submit new requests immediately to the HW but
defer processing the CS interrupt onto a tasklet. We gain the advantage
of low-latency and ksoftirqd avoidance when waking up the HW, while
avoiding the system-wide starvation of our CS irq-storms.

Comparing the impact on the maximum latency observed (that is the time
stolen from an RT process) over a 120s interval, repeated several times
(using gem_syslatency, similar to RT's cyclictest) while the system is
fully laden with i915 nops, we see that direct submission an actually
improve the worse case.

Maximum latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 2)
  x Always using tasklets (a couple of >1000us outliers removed)
  + Only using tasklets from CS irq, direct submission of requests
++
|  + |
|  + |
|  + |
|  +   + |
|  + + + |
|   +  + + +  x x x  |
|  +++ + + +  x  x  x  x  x  x   |
|  +++ + ++  + +  *x x  x  x  x  x   |
|  +++ + ++  + *  *x x  *  x  x  x   |
|+ +++ + ++  * * +*xxx  *  x  x  xx  |
|* +++ + * *x+**xx+ *  x  x  x   |
|   **x*++**+*x*xx+ * +x xx  x  x|
|x* **+***++*+***xx* xx*x xxx +x+|
| |__MA___|  |
|  |__M__A|  |
++
N   Min   MaxMedian   AvgStddev
x 11891   186   124 125.28814 16.279137
+ 12092   187   109 112.00833 13.458617
Difference at 95.0% confidence
-13.2798 +/- 3.79219
-10.5994% +/- 3.02677%
(Student's t, pooled s = 14.9237)

However the mean latency is adversely affected:

Mean latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 1)
  x Always using tasklets
  + Only using tasklets from CS irq, direct submission of requests
++
|   xx+   ++ |
|   xx+   ++ |
|   xx  + +++ ++ |
|   xxx + ++ |
|   xxx + ++ |
|   xxx + +++|
|   xxx   + ++   |
|    ++ ++   |
|    ++ ++   |
|  xx+++ |
| xxxx   +++ |
|x   x   x   ++ ++  +|
|   |__A__|  |
|  |A___||
++
N   Min   MaxMedian   AvgStddev
x 120 3.506 3.727 3.631 3.63214170.02773109
+ 120 3.834 4.149 4.039 4.0375167   0.041221676
Difference at 95.0% confidence
0.405375 +/- 0.00888913
11.1608% 

[Intel-gfx] [PATCH 4/9] drm/i915/execlists: Process one CSB update at a time

[Chris Wilson]

In the next patch, we will process the CSB events directly from the
submission path, rather than only after a CS interrupt. Hence, we will
no longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.

v2: Tvrtko pointed out it was safer to unconditionally kick the tasklet
after each irq, when assuming that the tasklet is called for each irq.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  |   7 +-
 drivers/gpu/drm/i915/intel_lrc.c | 278 +++
 2 files changed, 141 insertions(+), 144 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0bd8b4df1bff..3702992f9f75 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1473,9 +1473,10 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 
iir)
bool tasklet = false;
 
if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
-   if (READ_ONCE(engine->execlists.active))
-   tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
-   >irq_posted);
+   if (READ_ONCE(engine->execlists.active)) {
+   set_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
+   tasklet = true;
+   }
}
 
if (iir & GT_RENDER_USER_INTERRUPT) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b31e8f42aeb..91656eb2f2db 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -954,166 +954,162 @@ static void process_csb(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = >execlists;
struct execlist_port *port = execlists->port;
struct drm_i915_private *i915 = engine->i915;
+
+   /* The HWSP contains a (cacheable) mirror of the CSB */
+   const u32 *buf =
+   >status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+   unsigned int head, tail;
bool fw = false;
 
-   do {
-   /* The HWSP contains a (cacheable) mirror of the CSB */
-   const u32 *buf =
-   >status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
-   unsigned int head, tail;
-
-   /* Clear before reading to catch new interrupts */
-   clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
-   smp_mb__after_atomic();
-
-   if (unlikely(execlists->csb_use_mmio)) {
-   if (!fw) {
-   intel_uncore_forcewake_get(i915, 
execlists->fw_domains);
-   fw = true;
-   }
+   /* Clear before reading to catch new interrupts */
+   clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
+   smp_mb__after_atomic();
 
-   buf = (u32 * __force)
-   (i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+   if (unlikely(execlists->csb_use_mmio)) {
+   intel_uncore_forcewake_get(i915, execlists->fw_domains);
+   fw = true;
 
-   head = readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
-   tail = GEN8_CSB_WRITE_PTR(head);
-   head = GEN8_CSB_READ_PTR(head);
-   execlists->csb_head = head;
-   } else {
-   const int write_idx =
-   intel_hws_csb_write_index(i915) -
-   I915_HWS_CSB_BUF0_INDEX;
+   buf = (u32 * __force)
+   (i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
 
-   head = execlists->csb_head;
-   tail = READ_ONCE(buf[write_idx]);
-   rmb(); /* Hopefully paired with a wmb() in HW */
-   }
-   GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
+   head = readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+   tail = GEN8_CSB_WRITE_PTR(head);
+   head = GEN8_CSB_READ_PTR(head);
+   execlists->csb_head = head;
+   } else {
+   const int write_idx =
+   intel_hws_csb_write_index(i915) -
+   I915_HWS_CSB_BUF0_INDEX;
 
-   while (head != tail) {
-   struct i915_request *rq;
-   unsigned int status;
-   

[Intel-gfx] [PATCH 2/9] drm/i915/execlists: Pull submit after dequeue under timeline lock

[Chris Wilson]

In the next patch, we will begin processing the CSB from inside the
submission path (underneath an irqsoff section, and even from inside
interrupt handlers). This means that updating the execlists->port[] will
no longer be serialised by the tasklet but needs to be locked by the
engine->timeline.lock instead. Pull dequeue and submit under the same
lock for protection. (An alternate future plan is to keep the in/out
arrays separate for concurrent processing and reduced lock coverage.)

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 32 
 1 file changed, 12 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2b21a6596360..009db92b67d7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -567,7 +567,7 @@ static void complete_preempt_context(struct 
intel_engine_execlists *execlists)
execlists_clear_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
 }
 
-static bool __execlists_dequeue(struct intel_engine_cs *engine)
+static void __execlists_dequeue(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
struct execlist_port *port = execlists->port;
@@ -622,11 +622,11 @@ static bool __execlists_dequeue(struct intel_engine_cs 
*engine)
 * the HW to indicate that it has had a chance to respond.
 */
if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
-   return false;
+   return;
 
if (need_preempt(engine, last, execlists->queue_priority)) {
inject_preempt_context(engine);
-   return false;
+   return;
}
 
/*
@@ -651,7 +651,7 @@ static bool __execlists_dequeue(struct intel_engine_cs 
*engine)
 * priorities of the ports haven't been switch.
 */
if (port_count([1]))
-   return false;
+   return;
 
/*
 * WaIdleLiteRestore:bdw,skl
@@ -751,8 +751,10 @@ static bool __execlists_dequeue(struct intel_engine_cs 
*engine)
port != execlists->port ? rq_prio(last) : INT_MIN;
 
execlists->first = rb;
-   if (submit)
+   if (submit) {
port_assign(port, last);
+   execlists_submit_ports(engine);
+   }
 
/* We must always keep the beast fed if we have work piled up */
GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
@@ -761,24 +763,19 @@ static bool __execlists_dequeue(struct intel_engine_cs 
*engine)
if (last)
execlists_user_begin(execlists, execlists->port);
 
-   return submit;
+   /* If the engine is now idle, so should be the flag; and vice versa. */
+   GEM_BUG_ON(execlists_is_active(>execlists,
+  EXECLISTS_ACTIVE_USER) ==
+  !port_isset(engine->execlists.port));
 }
 
 static void execlists_dequeue(struct intel_engine_cs *engine)
 {
-   struct intel_engine_execlists * const execlists = >execlists;
unsigned long flags;
-   bool submit;
 
spin_lock_irqsave(>timeline.lock, flags);
-   submit = __execlists_dequeue(engine);
+   __execlists_dequeue(engine);
spin_unlock_irqrestore(>timeline.lock, flags);
-
-   if (submit)
-   execlists_submit_ports(engine);
-
-   GEM_BUG_ON(port_isset(execlists->port) &&
-  !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
 }
 
 void
@@ -1161,11 +1158,6 @@ static void execlists_submission_tasklet(unsigned long 
data)
 
if (!execlists_is_active(>execlists, EXECLISTS_ACTIVE_PREEMPT))
execlists_dequeue(engine);
-
-   /* If the engine is now idle, so should be the flag; and vice versa. */
-   GEM_BUG_ON(execlists_is_active(>execlists,
-  EXECLISTS_ACTIVE_USER) ==
-  !port_isset(engine->execlists.port));
 }
 
 static void queue_request(struct intel_engine_cs *engine,
-- 
2.18.0

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[Intel-gfx] [PATCH 6/9] drm/i915/execlists: Reset CSB write pointer after reset

[Chris Wilson]

On HW reset, the HW clears the write pointer (to 0). But since it also
writes its first CSB entry to slot 0, we need to reset the write pointer
back to the element before (so the first entry we read is 0).

This is required for the next patch, where we trust the CSB completely!

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 368a8c74d11d..8b111a268697 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -884,6 +884,21 @@ static void reset_irq(struct intel_engine_cs *engine)
clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
 }
 
+static void reset_csb_pointers(struct intel_engine_execlists *execlists)
+{
+   /*
+* After a reset, the HW starts writing into CSB entry [0]. We
+* therefore have to set our HEAD pointer back one entry so that
+* the *first* entry we check is entry 0. To complicate this further,
+* as we don't wait for the first interrupt after reset, we have to
+* fake the HW write to point back to the last entry so that our
+* inline comparison of our cached head position against the last HW
+* write works even before the first interrupt.
+*/
+   execlists->csb_head = GEN8_CSB_ENTRIES - 1;
+   WRITE_ONCE(*execlists->csb_write, (GEN8_CSB_ENTRIES - 1) | 0xff << 16);
+}
+
 static void execlists_cancel_requests(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
@@ -1953,7 +1968,7 @@ static void execlists_reset(struct intel_engine_cs 
*engine,
__unwind_incomplete_requests(engine);
 
/* Following the reset, we need to reload the CSB read/write pointers */
-   engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
+   reset_csb_pointers(>execlists);
 
spin_unlock_irqrestore(>timeline.lock, flags);
 
@@ -2452,7 +2467,6 @@ static int logical_ring_init(struct intel_engine_cs 
*engine)
upper_32_bits(ce->lrc_desc);
}
 
-   execlists->csb_head = GEN8_CSB_ENTRIES - 1;
execlists->csb_read =
i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
if (csb_force_mmio(i915)) {
@@ -2467,6 +2481,7 @@ static int logical_ring_init(struct intel_engine_cs 
*engine)
execlists->csb_write =

>status_page.page_addr[intel_hws_csb_write_index(i915)];
}
+   reset_csb_pointers(execlists);
 
return 0;
 
-- 
2.18.0

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[Intel-gfx] [PATCH 3/9] drm/i915/execlists: Pull CSB reset under the timeline.lock

[Chris Wilson]

In the following patch, we will process the CSB events under the
timeline.lock and not serialised by the tasklet. This also means that we
will need to protect access to common variables such as
execlists->csb_head with the timeline.lock during reset.

v2: Move sync_irq to avoid deadlocks between taking timeline.lock from
our interrupt handler.
v3: Kill off the synchronize_hardirq as it raises more questions than
answered; now we use the timeline.lock entirely for CSB serialisation
between the irq and elsewhere, we don't need to be so heavy handed with
flushing
v4: Treat request cancellation (wedging after failed reset) similarly

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 009db92b67d7..4b31e8f42aeb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -871,7 +871,6 @@ static void reset_irq(struct intel_engine_cs *engine)
 {
/* Mark all CS interrupts as complete */
smp_store_mb(engine->execlists.active, 0);
-   synchronize_hardirq(engine->i915->drm.irq);
 
clear_gtiir(engine);
 
@@ -908,14 +907,12 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
 * submission's irq state, we also wish to remind ourselves that
 * it is irq state.)
 */
-   local_irq_save(flags);
+   spin_lock_irqsave(>timeline.lock, flags);
 
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
reset_irq(engine);
 
-   spin_lock(>timeline.lock);
-
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, >timeline.requests, link) {
GEM_BUG_ON(!rq->global_seqno);
@@ -949,9 +946,7 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
execlists->first = NULL;
GEM_BUG_ON(port_isset(execlists->port));
 
-   spin_unlock(>timeline.lock);
-
-   local_irq_restore(flags);
+   spin_unlock_irqrestore(>timeline.lock, flags);
 }
 
 static void process_csb(struct intel_engine_cs *engine)
@@ -1969,8 +1964,7 @@ static void execlists_reset(struct intel_engine_cs 
*engine,
  engine->name, request ? request->global_seqno : 0,
  intel_engine_get_seqno(engine));
 
-   /* See execlists_cancel_requests() for the irq/spinlock split. */
-   local_irq_save(flags);
+   spin_lock_irqsave(>timeline.lock, flags);
 
/*
 * Catch up with any missed context-switch interrupts.
@@ -1985,14 +1979,12 @@ static void execlists_reset(struct intel_engine_cs 
*engine,
reset_irq(engine);
 
/* Push back any incomplete requests for replay after the reset. */
-   spin_lock(>timeline.lock);
__unwind_incomplete_requests(engine);
-   spin_unlock(>timeline.lock);
 
/* Following the reset, we need to reload the CSB read/write pointers */
engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
 
-   local_irq_restore(flags);
+   spin_unlock_irqrestore(>timeline.lock, flags);
 
/*
 * If the request was innocent, we leave the request in the ELSP
-- 
2.18.0

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[Intel-gfx] [PATCH 7/9] drm/i915/execlists: Stop storing the CSB read pointer in the mmio register

[Chris Wilson]

As we now never read back our current head position from the CSB
pointers register, and the HW itself doesn't use it to prevent
overwriting unread CSB entries, we do not need to keep updating the
register. As it turns out this register is not listed as being shadowed,
and so requires forcewake -- but we haven't been taking forcewake around
it so the writes has probably been regularly dropped. Fortuitously, we
only read the value after a reset where it did not matter, and zero was
the right answer (well, close enough).

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/intel_lrc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8b111a268697..a6268103663f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1100,8 +1100,6 @@ static void process_csb(struct intel_engine_cs *engine)
}
} while (head != tail);
 
-   writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
-  execlists->csb_read);
execlists->csb_head = head;
 }
 
-- 
2.18.0

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[Intel-gfx] [PATCH 5/9] drm/i915/execlists: Unify CSB access pointers

[Chris Wilson]

Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce the CSB access to a set of read/write/buffer pointers and
treat the various paths identically and not worry about forcewake.
(Forcewake is nightmare for worstcase latency, and we want to process
this all with irqsoff -- no latency allowed!)

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  12 ---
 drivers/gpu/drm/i915/intel_lrc.c| 116 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.h |  23 +++--
 3 files changed, 65 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d3264bd6e9dc..7209c22798e6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -25,7 +25,6 @@
 #include 
 
 #include "i915_drv.h"
-#include "i915_vgpu.h"
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
@@ -456,21 +455,10 @@ static void intel_engine_init_batch_pool(struct 
intel_engine_cs *engine)
i915_gem_batch_pool_init(>batch_pool, engine);
 }
 
-static bool csb_force_mmio(struct drm_i915_private *i915)
-{
-   /* Older GVT emulation depends upon intercepting CSB mmio */
-   if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
-   return true;
-
-   return false;
-}
-
 static void intel_engine_init_execlist(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
 
-   execlists->csb_use_mmio = csb_force_mmio(engine->i915);
-
execlists->port_mask = 1;
BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 91656eb2f2db..368a8c74d11d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -137,6 +137,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_gem_render_state.h"
+#include "i915_vgpu.h"
 #include "intel_lrc_reg.h"
 #include "intel_mocs.h"
 #include "intel_workarounds.h"
@@ -953,44 +954,23 @@ static void process_csb(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
struct execlist_port *port = execlists->port;
-   struct drm_i915_private *i915 = engine->i915;
-
-   /* The HWSP contains a (cacheable) mirror of the CSB */
-   const u32 *buf =
-   >status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
-   unsigned int head, tail;
-   bool fw = false;
+   const u32 * const buf = execlists->csb_status;
+   u8 head, tail;
 
/* Clear before reading to catch new interrupts */
clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
smp_mb__after_atomic();
 
-   if (unlikely(execlists->csb_use_mmio)) {
-   intel_uncore_forcewake_get(i915, execlists->fw_domains);
-   fw = true;
-
-   buf = (u32 * __force)
-   (i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+   /* Note that csb_write, csb_status may be either in HWSP or mmio */
+   head = execlists->csb_head;
+   tail = READ_ONCE(*execlists->csb_write);
+   GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
+   if (unlikely(head == tail))
+   return;
 
-   head = readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
-   tail = GEN8_CSB_WRITE_PTR(head);
-   head = GEN8_CSB_READ_PTR(head);
-   execlists->csb_head = head;
-   } else {
-   const int write_idx =
-   intel_hws_csb_write_index(i915) -
-   I915_HWS_CSB_BUF0_INDEX;
+   rmb(); /* Hopefully paired with a wmb() in HW */
 
-   head = execlists->csb_head;
-   tail = READ_ONCE(buf[write_idx]);
-   rmb(); /* Hopefully paired with a wmb() in HW */
-   }
-   GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
-
-   while (head != tail) {
+   do {
struct i915_request *rq;
unsigned int status;
unsigned int count;
@@ -1016,12 +996,12 @@ static void process_csb(struct intel_engine_cs *engine)
 * status notifier.
 */
 
-   status = READ_ONCE(buf[2 * 

[Intel-gfx] [PATCH 1/9] drm/i915: Drop posting reads to flush master interrupts

[Chris Wilson]

We do not need to do a posting read of our uncached mmio write to
re-enable the master interrupt lines after handling an interrupt, so
don't. This saves us a slow UC read before we can process the interrupt,
most noticeable in execlists where any stalls imposes extra latency on
GPU command execution.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_irq.c | 9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46aaef5c1851..0bd8b4df1bff 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2131,7 +2131,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void 
*arg)
 
I915_WRITE(VLV_IER, ier);
I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
-   POSTING_READ(VLV_MASTER_IER);
 
if (gt_iir)
snb_gt_irq_handler(dev_priv, gt_iir);
@@ -2216,7 +2215,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void 
*arg)
 
I915_WRITE(VLV_IER, ier);
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
-   POSTING_READ(GEN8_MASTER_IRQ);
 
gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
 
@@ -2548,7 +2546,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
/* disable master interrupt before clearing iir  */
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
-   POSTING_READ(DEIER);
 
/* Disable south interrupts. We'll only write to SDEIIR once, so further
 * interrupts will will be stored on its back queue, and then we'll be
@@ -2558,7 +2555,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
if (!HAS_PCH_NOP(dev_priv)) {
sde_ier = I915_READ(SDEIER);
I915_WRITE(SDEIER, 0);
-   POSTING_READ(SDEIER);
}
 
/* Find, clear, then process each source of interrupt */
@@ -2593,11 +2589,8 @@ static irqreturn_t ironlake_irq_handler(int irq, void 
*arg)
}
 
I915_WRITE(DEIER, de_ier);
-   POSTING_READ(DEIER);
-   if (!HAS_PCH_NOP(dev_priv)) {
+   if (!HAS_PCH_NOP(dev_priv))
I915_WRITE(SDEIER, sde_ier);
-   POSTING_READ(SDEIER);
-   }
 
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
enable_rpm_wakeref_asserts(dev_priv);
-- 
2.18.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,1/2] drm/i915/psr: Lockless version of psr_wait_for_idle

[Patchwork]

== Series Details ==

Series: series starting with [v8,1/2] drm/i915/psr: Lockless version of 
psr_wait_for_idle
URL   : https://patchwork.freedesktop.org/series/45524/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4391 -> Patchwork_9453 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45524/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9453 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@gem_ctx_create@basic-files:
  fi-glk-dsi: DMESG-WARN (fdo#106954) -> PASS


  fdo#106954 https://bugs.freedesktop.org/show_bug.cgi?id=106954


== Participating hosts (44 -> 40) ==

  Additional (1): fi-byt-j1900 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4391 -> Patchwork_9453

  CI_DRM_4391: 9134bde2e681ec232f4d8bec56aa3700177630fe @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9453: 7a0d28ca8e878141795a1f3044fd373ad5593ac9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7a0d28ca8e87 drm/i915: Wait for PSR exit before checking for vblank evasion
f6ed4df15922 drm/i915/psr: Lockless version of psr_wait_for_idle

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9453/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Wait for engines to idle before retiring

[Patchwork]

== Series Details ==

Series: drm/i915: Wait for engines to idle before retiring
URL   : https://patchwork.freedesktop.org/series/45484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9449_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9449_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9449_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9449_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  SKIP -> PASS

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  PASS -> SKIP

igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
  shard-hsw:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9449_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@mock_scatterlist:
  shard-kbl:  NOTRUN -> DMESG-WARN (fdo#103667)

igt@gem_ctx_isolation@rcs0-s3:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)

igt@gem_exec_schedule@pi-ringfull-blt:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#103158)

igt@gem_exec_schedule@pi-ringfull-vebox:
  shard-glk:  NOTRUN -> FAIL (fdo#103158)

igt@gem_mmap_gtt@coherency:
  shard-glk:  NOTRUN -> FAIL (fdo#100587)

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  NOTRUN -> FAIL (fdo#105454, fdo#106509)

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)

igt@prime_vgem@coherency-gtt:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#100587)

igt@testdisplay:
  shard-glk:  NOTRUN -> INCOMPLETE (fdo#103359, k.org#198133)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@drv_suspend@shrink:
  shard-snb:  FAIL (fdo#107054, fdo#106886) -> PASS

igt@gem_ctx_switch@basic-all-light:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@gem_softpin@noreloc-s3:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS


 Warnings 

igt@drv_selftest@live_gtt:
  shard-glk:  INCOMPLETE (fdo#103359, k.org#198133) -> FAIL 
(fdo#105347)


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9449

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9449: d4e1a15d8976c8d91bd97ad63ee667df3c08030a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9449/shards.html
___
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[Intel-gfx] [PATCH 1/4] drm/i915: Reduce spinlock hold time during notify_ring() interrupt

[Chris Wilson]

By taking advantage of the RCU protection of the task struct, we can find
the appropriate signaler under the spinlock and then release the spinlock
before waking the task and signaling the fence.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_irq.c | 32 +---
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46aaef5c1851..56a080bc4498 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1145,21 +1145,23 @@ static void ironlake_rps_change_irq_handler(struct 
drm_i915_private *dev_priv)
 
 static void notify_ring(struct intel_engine_cs *engine)
 {
+   const u32 seqno = intel_engine_get_seqno(engine);
struct i915_request *rq = NULL;
+   struct task_struct *tsk = NULL;
struct intel_wait *wait;
 
-   if (!engine->breadcrumbs.irq_armed)
+   if (unlikely(!engine->breadcrumbs.irq_armed))
return;
 
atomic_inc(>irq_count);
-   set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
+
+   rcu_read_lock();
 
spin_lock(>breadcrumbs.irq_lock);
wait = engine->breadcrumbs.irq_wait;
if (wait) {
-   bool wakeup = engine->irq_seqno_barrier;
-
-   /* We use a callback from the dma-fence to submit
+   /*
+* We use a callback from the dma-fence to submit
 * requests after waiting on our own requests. To
 * ensure minimum delay in queuing the next request to
 * hardware, signal the fence now rather than wait for
@@ -1170,19 +1172,22 @@ static void notify_ring(struct intel_engine_cs *engine)
 * and to handle coalescing of multiple seqno updates
 * and many waiters.
 */
-   if (i915_seqno_passed(intel_engine_get_seqno(engine),
- wait->seqno)) {
+   if (i915_seqno_passed(seqno, wait->seqno)) {
struct i915_request *waiter = wait->request;
 
-   wakeup = true;
if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
  >fence.flags) &&
intel_wait_check_request(wait, waiter))
rq = i915_request_get(waiter);
-   }
 
-   if (wakeup)
-   wake_up_process(wait->tsk);
+   tsk = wait->tsk;
+   } else {
+   if (engine->irq_seqno_barrier) {
+   set_bit(ENGINE_IRQ_BREADCRUMB,
+   >irq_posted);
+   tsk = wait->tsk;
+   }
+   }
} else {
if (engine->breadcrumbs.irq_armed)
__intel_engine_disarm_breadcrumbs(engine);
@@ -1195,6 +1200,11 @@ static void notify_ring(struct intel_engine_cs *engine)
i915_request_put(rq);
}
 
+   if (tsk && tsk->state & TASK_NORMAL)
+   wake_up_process(tsk);
+
+   rcu_read_unlock();
+
trace_intel_engine_notify(engine, wait);
 }
 
-- 
2.18.0

___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 3/4] drm/i915: Move the irq_counter inside the spinlock

[Chris Wilson]

Rather than have multiple locked instructions inside the notify_ring()
irq handler, move them inside the spinlock and reduce their intrinsic
locking.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_irq.c  |  4 ++--
 drivers/gpu/drm/i915/i915_request.c  |  4 ++--
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 11 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  2 +-
 4 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 55aba89adfb1..6adeaac48ea9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1153,8 +1153,6 @@ static void notify_ring(struct intel_engine_cs *engine)
if (unlikely(!engine->breadcrumbs.irq_armed))
return;
 
-   atomic_inc(>irq_count);
-
rcu_read_lock();
 
spin_lock(>breadcrumbs.irq_lock);
@@ -1189,6 +1187,8 @@ static void notify_ring(struct intel_engine_cs *engine)
tsk = wait->tsk;
}
}
+
+   engine->breadcrumbs.irq_count++;
} else {
if (engine->breadcrumbs.irq_armed)
__intel_engine_disarm_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index e1dbb544046f..39b296878ba2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1196,7 +1196,7 @@ static bool __i915_spin_request(const struct i915_request 
*rq,
 * takes to sleep on a request, on the order of a microsecond.
 */
 
-   irq = atomic_read(>irq_count);
+   irq = READ_ONCE(engine->breadcrumbs.irq_count);
timeout_us += local_clock_us();
do {
if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
@@ -1208,7 +1208,7 @@ static bool __i915_spin_request(const struct i915_request 
*rq,
 * assume we won't see one in the near future but require
 * the engine->seqno_barrier() to fixup coherency.
 */
-   if (atomic_read(>irq_count) != irq)
+   if (READ_ONCE(engine->breadcrumbs.irq_count) != irq)
break;
 
if (signal_pending_state(state, current))
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 86a987b8ac66..1db6ba7d926e 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -98,12 +98,14 @@ static void intel_breadcrumbs_hangcheck(struct timer_list 
*t)
struct intel_engine_cs *engine =
from_timer(engine, t, breadcrumbs.hangcheck);
struct intel_breadcrumbs *b = >breadcrumbs;
+   unsigned int irq_count;
 
if (!b->irq_armed)
return;
 
-   if (b->hangcheck_interrupts != atomic_read(>irq_count)) {
-   b->hangcheck_interrupts = atomic_read(>irq_count);
+   irq_count = READ_ONCE(b->irq_count);
+   if (b->hangcheck_interrupts != irq_count) {
+   b->hangcheck_interrupts = irq_count;
mod_timer(>hangcheck, wait_timeout());
return;
}
@@ -272,13 +274,14 @@ static bool use_fake_irq(const struct intel_breadcrumbs 
*b)
if (!test_bit(engine->id, >i915->gpu_error.missed_irq_rings))
return false;
 
-   /* Only start with the heavy weight fake irq timer if we have not
+   /*
+* Only start with the heavy weight fake irq timer if we have not
 * seen any interrupts since enabling it the first time. If the
 * interrupts are still arriving, it means we made a mistake in our
 * engine->seqno_barrier(), a timing error that should be transient
 * and unlikely to reoccur.
 */
-   return atomic_read(>irq_count) == b->hangcheck_interrupts;
+   return READ_ONCE(b->irq_count) == b->hangcheck_interrupts;
 }
 
 static void enable_fake_irq(struct intel_breadcrumbs *b)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index a0bc7a8222b4..44ac90ec540c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -345,7 +345,6 @@ struct intel_engine_cs {
struct drm_i915_gem_object *default_state;
void *pinned_default_state;
 
-   atomic_t irq_count;
unsigned long irq_posted;
 #define ENGINE_IRQ_BREADCRUMB 0
 #define ENGINE_IRQ_EXECLIST 1
@@ -380,6 +379,7 @@ struct intel_engine_cs {
 
unsigned int hangcheck_interrupts;
unsigned int irq_enabled;
+   unsigned int irq_count;
 
bool irq_armed : 1;
I915_SELFTEST_DECLARE(bool mock : 1);
-- 
2.18.0

___
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[Intel-gfx] [PATCH 2/4] drm/i915: Only trigger missed-seqno checking next to boundary

[Chris Wilson]

If we have more interrupts pending (because we know there are more
breadcrumb signals before the completion), then we do not need to
trigger an irq_seqno_barrier or even wakeup the task on this interrupt
as there will be another. To allow some margin of error (we are trying
to work around incoherent seqno after all), we wakeup the breadcrumb
before the target as well as on the target.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_irq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 56a080bc4498..55aba89adfb1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1182,7 +1182,8 @@ static void notify_ring(struct intel_engine_cs *engine)
 
tsk = wait->tsk;
} else {
-   if (engine->irq_seqno_barrier) {
+   if (engine->irq_seqno_barrier &&
+   i915_seqno_passed(seqno, wait->seqno - 1)) {
set_bit(ENGINE_IRQ_BREADCRUMB,
>irq_posted);
tsk = wait->tsk;
-- 
2.18.0

___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 4/4] drm/i915: Only signal from interrupt when requested

[Chris Wilson]

Avoid calling dma_fence_signal() from inside the interrupt if we haven't
enabled signaling on the request.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_irq.c | 8 ++--
 drivers/gpu/drm/i915/i915_request.c | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++---
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6adeaac48ea9..1eba2c3895fc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1173,7 +1173,8 @@ static void notify_ring(struct intel_engine_cs *engine)
if (i915_seqno_passed(seqno, wait->seqno)) {
struct i915_request *waiter = wait->request;
 
-   if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
+   if (waiter &&
+   !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
  >fence.flags) &&
intel_wait_check_request(wait, waiter))
rq = i915_request_get(waiter);
@@ -1196,8 +1197,11 @@ static void notify_ring(struct intel_engine_cs *engine)
spin_unlock(>breadcrumbs.irq_lock);
 
if (rq) {
-   dma_fence_signal(>fence);
+   spin_lock(>lock);
+   dma_fence_signal_locked(>fence);
GEM_BUG_ON(!i915_request_completed(rq));
+   spin_unlock(>lock);
+
i915_request_put(rq);
}
 
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 39b296878ba2..a2f7e9358450 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1285,7 +1285,7 @@ long i915_request_wait(struct i915_request *rq,
if (flags & I915_WAIT_LOCKED)
add_wait_queue(errq, );
 
-   intel_wait_init(, rq);
+   intel_wait_init();
 
 restart:
do {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 44ac90ec540c..78f01a35823a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -928,11 +928,10 @@ static inline u32 intel_hws_preempt_done_address(struct 
intel_engine_cs *engine)
 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
 
-static inline void intel_wait_init(struct intel_wait *wait,
-  struct i915_request *rq)
+static inline void intel_wait_init(struct intel_wait *wait)
 {
wait->tsk = current;
-   wait->request = rq;
+   wait->request = NULL;
 }
 
 static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 
seqno)
-- 
2.18.0

___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: encourage BIT() macro usage in register definitions

[Patchwork]

== Series Details ==

Series: drm/i915: encourage BIT() macro usage in register definitions
URL   : https://patchwork.freedesktop.org/series/45498/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9446_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9446_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9446_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9446_full:

  === IGT changes ===

 Warnings 

igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
  shard-hsw:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9446_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_await@wide-contexts:
  shard-glk:  PASS -> FAIL (fdo#105900)

igt@gem_exec_schedule@pi-ringfull-blt:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#103158)

igt@gem_exec_schedule@pi-ringfull-vebox:
  shard-glk:  NOTRUN -> FAIL (fdo#103158)

igt@gem_mmap_gtt@coherency:
  shard-glk:  NOTRUN -> FAIL (fdo#100587)

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  NOTRUN -> FAIL (fdo#106509, fdo#105454)

igt@kms_flip@2x-plain-flip-fb-recreate:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#100368)

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103822)

igt@kms_flip_tiling@flip-y-tiled:
  {shard-glk9}:   NOTRUN -> FAIL (fdo#104724)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)

igt@testdisplay:
  shard-glk:  NOTRUN -> INCOMPLETE (fdo#103359, k.org#198133)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-glk:  INCOMPLETE (fdo#103359, k.org#198133) -> PASS
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@drv_suspend@shrink:
  shard-snb:  FAIL (fdo#107054, fdo#106886) -> PASS

igt@gem_ctx_switch@basic-all-light:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@gem_softpin@noreloc-s3:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@kms_flip@dpms-vs-vblank-race:
  shard-kbl:  FAIL (fdo#103060) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#104724, fdo#103822) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9446

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9446: d22f87f4e6805dea2e32f6b9e0a78f1717cff8f4 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9446/shards.html
___
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[Intel-gfx] [PATCH v8 2/2] drm/i915: Wait for PSR exit before checking for vblank evasion

[Tarun Vyas]

The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
the pipe_update_start call schedules itself out to check back later.

On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
lags w.r.t core kernel code, hot plugging an external display triggers
tons of "potential atomic update errors" in the dmesg, on *pipe A*. A
closer analysis reveals that we try to read the scanline 3 times and
eventually timeout, b/c PSR hasn't exited fully leading to a PIPEDSL
stuck @ 1599. This issue is not seen on upstream kernels, b/c for *some*
reason we loop inside intel_pipe_update start for ~2+ msec which in this
case is more than enough to exit PSR fully, hence an *unstuck* PIPEDSL
counter, hence no error. On the other hand, the ChromeOS kernel spends
~1.1 msec looping inside intel_pipe_update_start and hence errors out
b/c the source is still in PSR.

Regardless, we should wait for PSR exit (if PSR is disabled, we incur
a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
fully exited PSR, then checking for vblank evasion isn't actually
applicable.

v4: Comment explaining psr_wait after enabling VBL interrupts (DK)

v5: CAN_PSR() to handle platforms that don't support PSR.

v6: Handle local_irq_disable on early return (Chris)

Signed-off-by: Tarun Vyas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 344c0e709b19..4990d6e84ddf 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -107,13 +107,21 @@ void intel_pipe_update_start(const struct 
intel_crtc_state *new_crtc_state)
  VBLANK_EVASION_TIME_US);
max = vblank_start - 1;
 
-   local_irq_disable();
-
if (min <= 0 || max <= 0)
-   return;
+   goto irq_disable;
 
if (WARN_ON(drm_crtc_vblank_get(>base)))
-   return;
+   goto irq_disable;
+
+   /*
+* Wait for psr to idle out after enabling the VBL interrupts
+* VBL interrupts will start the PSR exit and prevent a PSR
+* re-entry as well.
+*/
+   if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv))
+   DRM_ERROR("PSR idle timed out, atomic update may fail\n");
+
+   local_irq_disable();
 
crtc->debug.min_vbl = min;
crtc->debug.max_vbl = max;
@@ -171,6 +179,10 @@ void intel_pipe_update_start(const struct intel_crtc_state 
*new_crtc_state)
crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 
trace_i915_pipe_update_vblank_evaded(crtc);
+   return;
+
+irq_disable:
+   local_irq_disable();
 }
 
 /**
-- 
2.13.5

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[Intel-gfx] [PATCH v8 1/2] drm/i915/psr: Lockless version of psr_wait_for_idle

[Tarun Vyas]

This is a lockless version of the exisiting psr_wait_for_idle().
We want to wait for PSR to idle out inside intel_pipe_update_start.
At the time of a pipe update, we should never race with any psr
enable or disable code, which is a part of crtc enable/disable.
The follow up patch will use this lockless wait inside pipe_update_
start to wait for PSR to idle out before checking for vblank evasion.
We need to keep the wait in pipe_update_start to as less as it can be.
So,we can live and flourish w/o taking any psr locks at all.

Even if psr is never enabled, psr2_enabled will be false and this
function will wait for PSR1 to idle out, which should just return
immediately, so a very short (~1-2 usec) wait for cases where PSR
is disabled.

v2: Add comment to explain the 25msec timeout (DK)

v3: Rename psr_wait_for_idle to __psr_wait_for_idle_locked to avoid
naming conflicts and propagate err (if any) to the caller (Chris)

v5: Form a series with the next patch

v7: Better explain the need for lockless wait and increase the max
timeout to handle refresh rates < 60 Hz (Daniel Vetter)

v8: Rebase

Signed-off-by: Tarun Vyas 
---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 36 ++--
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a6ff2600a3a0..b9b70321c054 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1922,6 +1922,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
 void intel_psr_short_pulse(struct intel_dp *intel_dp);
+int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 45f1cb7d6c04..23acc9ac8d4d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -717,7 +717,39 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_work_sync(_priv->psr.work);
 }
 
-static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
+int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv)
+{
+   i915_reg_t reg;
+   u32 mask;
+
+   /*
+* The sole user right now is intel_pipe_update_start(),
+* which won't race with psr_enable/disable, which is
+* where psr2_enabled is written to. So, we don't need
+* to acquire the psr.lock. More importantly, we want the
+* latency inside intel_pipe_update_start() to be as low
+* as possible, so no need to acquire psr.lock when it is
+* not needed and will induce latencies in the atomic
+* update path.
+*/
+   if (dev_priv->psr.psr2_enabled) {
+   reg = EDP_PSR2_STATUS;
+   mask = EDP_PSR2_STATUS_STATE_MASK;
+   } else {
+   reg = EDP_PSR_STATUS;
+   mask = EDP_PSR_STATUS_STATE_MASK;
+   }
+
+   /*
+* Max time for PSR to idle = Inverse of the refresh rate +
+* 6 ms of exit training time + 1.5 ms of aux channel
+* handshake. 50 msec is defesive enough to cover everything.
+*/
+   return intel_wait_for_register(dev_priv, reg, mask,
+  EDP_PSR_STATUS_STATE_IDLE, 50);
+}
+
+static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
 {
struct intel_dp *intel_dp;
i915_reg_t reg;
@@ -763,7 +795,7 @@ static void intel_psr_work(struct work_struct *work)
 * PSR might take some time to get fully disabled
 * and be ready for re-enable.
 */
-   if (!psr_wait_for_idle(dev_priv))
+   if (!__psr_wait_for_idle_locked(dev_priv))
goto unlock;
 
/*
-- 
2.13.5

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v7,1/2] drm/i915/psr: Lockless version of psr_wait_for_idle

[Patchwork]

== Series Details ==

Series: series starting with [v7,1/2] drm/i915/psr: Lockless version of 
psr_wait_for_idle
URL   : https://patchwork.freedesktop.org/series/45521/
State : failure

== Summary ==

Applying: drm/i915/psr: Lockless version of psr_wait_for_idle
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_drv.h
M   drivers/gpu/drm/i915/intel_psr.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_psr.c
Auto-merging drivers/gpu/drm/i915/intel_drv.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_drv.h
error: Failed to merge in the changes.
Patch failed at 0001 drm/i915/psr: Lockless version of psr_wait_for_idle
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to 
gen8_pte_encode
URL   : https://patchwork.freedesktop.org/series/45519/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4390 -> Patchwork_9451 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45519/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9451 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713


== Participating hosts (44 -> 40) ==

  Additional (1): fi-byt-j1900 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4390 -> Patchwork_9451

  CI_DRM_4390: fbe6c535c4179a7eb1e23a7cd20db612822eed2a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9451: 0a9bd1dfbdf1d543745267e086bbad6b13813687 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0a9bd1dfbdf1 drm/i915/userptr: Enable read-only support on gen8+
75194c6128be drm/i915: Reject attempted pwrites into a read-only object
5526e0e6fc80 drm/i915: Prevent writing into a read-only object via a GGTT mmap
efda09477394 drm/i915/gtt: Read-only pages for insert_entries on bdw+
edc140b84d5c drm/i915/gtt: Add read only pages to gen8_pte_encode

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9451/issues.html
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[Intel-gfx] [PATCH i-g-t] igt/gem_userptr: Check read-only mappings

[Chris Wilson]

Setup a userptr object that only has a read-only mapping back to a file
store (memfd). Then attempt to write into that mapping using the GPU and
assert that those writes do not land (while also writing via a writable
userptr mapping into the same memfd to verify that the GPU is working!)

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
---
 configure.ac  |   1 +
 lib/ioctl_wrappers.c  |   4 +-
 lib/ioctl_wrappers.h  |   4 +-
 lib/meson.build   |   1 +
 meson.build   |   1 +
 tests/Makefile.am |   4 +-
 tests/gem_userptr_blits.c | 337 +-
 7 files changed, 342 insertions(+), 10 deletions(-)

diff --git a/configure.ac b/configure.ac
index 1ee4e90e9..195963d4f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -125,6 +125,7 @@ PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
 PKG_CHECK_MODULES(KMOD, [libkmod])
 PKG_CHECK_MODULES(PROCPS, [libprocps])
 PKG_CHECK_MODULES(LIBUNWIND, [libunwind])
+PKG_CHECK_MODULES(SSL, [openssl])
 PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], 
[have_valgrind=no])
 
 if test x$have_valgrind = xyes; then
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 79db44a8c..d5d2a4e4c 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -869,7 +869,7 @@ int gem_madvise(int fd, uint32_t handle, int state)
return madv.retained;
 }
 
-int __gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags, 
uint32_t *handle)
+int __gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t 
flags, uint32_t *handle)
 {
struct drm_i915_gem_userptr userptr;
 
@@ -898,7 +898,7 @@ int __gem_userptr(int fd, void *ptr, int size, int 
read_only, uint32_t flags, ui
  *
  * Returns userptr handle for the GEM object.
  */
-void gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags, 
uint32_t *handle)
+void gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t 
flags, uint32_t *handle)
 {
igt_assert_eq(__gem_userptr(fd, ptr, size, read_only, flags, handle), 
0);
 }
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index b966f72c9..8e2cd380b 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -133,8 +133,8 @@ struct local_i915_gem_userptr {
 #define LOCAL_I915_USERPTR_UNSYNCHRONIZED (1<<31)
uint32_t handle;
 };
-void gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags, 
uint32_t *handle);
-int __gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags, 
uint32_t *handle);
+void gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t 
flags, uint32_t *handle);
+int __gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t 
flags, uint32_t *handle);
 
 void gem_sw_finish(int fd, uint32_t handle);
 
diff --git a/lib/meson.build b/lib/meson.build
index 1a355414e..939167f91 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -62,6 +62,7 @@ lib_deps = [
pthreads,
math,
realtime,
+   ssl,
 ]
 
 if libdrm_intel.found()
diff --git a/meson.build b/meson.build
index 4d15d6238..638c01066 100644
--- a/meson.build
+++ b/meson.build
@@ -98,6 +98,7 @@ pciaccess = dependency('pciaccess', version : '>=0.10')
 libkmod = dependency('libkmod')
 libprocps = dependency('libprocps', required : true)
 libunwind = dependency('libunwind', required : true)
+ssl = dependency('openssl', required : true)
 
 valgrind = null_dep
 valgrindinfo = 'No'
diff --git a/tests/Makefile.am b/tests/Makefile.am
index f41ad5096..ba307b220 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -126,8 +126,8 @@ gem_tiled_swapping_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_tiled_swapping_LDADD = $(LDADD) -lpthread
 prime_self_import_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 prime_self_import_LDADD = $(LDADD) -lpthread
-gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
-gem_userptr_blits_LDADD = $(LDADD) -lpthread
+gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) $(SSL_CFLAGS)
+gem_userptr_blits_LDADD = $(LDADD) $(SSL_LIBS) -lpthread
 perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
 
 gem_eio_LDADD = $(LDADD) -lrt
diff --git a/tests/gem_userptr_blits.c b/tests/gem_userptr_blits.c
index 7e3b6ef38..30c6bc48c 100644
--- a/tests/gem_userptr_blits.c
+++ b/tests/gem_userptr_blits.c
@@ -43,13 +43,17 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
+#include 
+
 #include "drm.h"
 #include "i915_drm.h"
 
@@ -238,6 +242,57 @@ blit(int fd, uint32_t dst, uint32_t src, uint32_t *all_bo, 
int n_bo)
return ret;
 }
 
+static void store_dword(int fd, uint32_t target,
+   uint32_t offset, uint32_t value)
+{
+   const int gen = intel_gen(intel_get_drm_devid(fd));
+   struct drm_i915_gem_exec_object2 obj[2];
+   struct drm_i915_gem_relocation_entry reloc;
+   struct drm_i915_gem_execbuffer2 execbuf;
+ 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to 
gen8_pte_encode
URL   : https://patchwork.freedesktop.org/series/45519/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/gtt: Add read only pages to gen8_pte_encode
Okay!

Commit: drm/i915/gtt: Read-only pages for insert_entries on bdw+
+drivers/gpu/drm/i915/selftests/i915_gem_context.c:506:25: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/i915_gem_context.c:506:25: warning: expression 
using sizeof(void)

Commit: drm/i915: Prevent writing into a read-only object via a GGTT mmap
Okay!

Commit: drm/i915: Reject attempted pwrites into a read-only object
Okay!

Commit: drm/i915/userptr: Enable read-only support on gen8+
Okay!

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[Intel-gfx] [PATCH v7 1/2] drm/i915/psr: Lockless version of psr_wait_for_idle

[Tarun Vyas]

This is a lockless version of the exisiting psr_wait_for_idle().
We want to wait for PSR to idle out inside intel_pipe_update_start.
At the time of a pipe update, we should never race with any psr
enable or disable code, which is a part of crtc enable/disable.
The follow up patch will use this lockless wait inside pipe_update_
start to wait for PSR to idle out before checking for vblank evasion.
We need to keep the wait in pipe_update_start to as less as it can be.
So,we can live and flourish w/o taking any psr locks at all.

Even if psr is never enabled, psr2_enabled will be false and this
function will wait for PSR1 to idle out, which should just return
immediately, so a very short (~1-2 usec) wait for cases where PSR
is disabled.

v2: Add comment to explain the 25msec timeout (DK)

v3: Rename psr_wait_for_idle to __psr_wait_for_idle_locked to avoid
naming conflicts and propagate err (if any) to the caller (Chris)

v5: Form a series with the next patch

v7: Better explain the need for lockless wait and increase the max
timeout to handle refresh rates < 60 Hz (Daniel Vetter)

Signed-off-by: Tarun Vyas 
---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 36 ++--
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 578346b8d7e2..9cb2b8afdd3e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1920,6 +1920,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
  struct intel_crtc_state *crtc_state);
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
+int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index aea81ace854b..d11fd8a01d98 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -757,7 +757,39 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_work_sync(_priv->psr.work);
 }
 
-static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
+int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv)
+{
+   i915_reg_t reg;
+   u32 mask;
+
+   /*
+* The sole user right now is intel_pipe_update_start(),
+* which won't race with psr_enable/disable, which is
+* where psr2_enabled is written to. So, we don't need
+* to acquire the psr.lock. More importantly, we want the
+* latency inside intel_pipe_update_start() to be as low
+* as possible, so no need to acquire psr.lock when it is
+* not needed and will induce latencies in the atomic
+* update path.
+*/
+   if (dev_priv->psr.psr2_enabled) {
+   reg = EDP_PSR2_STATUS;
+   mask = EDP_PSR2_STATUS_STATE_MASK;
+   } else {
+   reg = EDP_PSR_STATUS;
+   mask = EDP_PSR_STATUS_STATE_MASK;
+   }
+
+   /*
+* Max time for PSR to idle = Inverse of the refresh rate +
+* 6 ms of exit training time + 1.5 ms of aux channel
+* handshake. 50 msec is defesive enough to cover everything.
+*/
+   return intel_wait_for_register(dev_priv, reg, mask,
+  EDP_PSR_STATUS_STATE_IDLE, 50);
+}
+
+static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
 {
struct intel_dp *intel_dp;
i915_reg_t reg;
@@ -803,7 +835,7 @@ static void intel_psr_work(struct work_struct *work)
 * PSR might take some time to get fully disabled
 * and be ready for re-enable.
 */
-   if (!psr_wait_for_idle(dev_priv))
+   if (!__psr_wait_for_idle_locked(dev_priv))
goto unlock;
 
/*
-- 
2.13.5

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[Intel-gfx] [PATCH v7 2/2] drm/i915: Wait for PSR exit before checking for vblank evasion

[Tarun Vyas]

The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
the pipe_update_start call schedules itself out to check back later.

On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
lags w.r.t core kernel code, hot plugging an external display triggers
tons of "potential atomic update errors" in the dmesg, on *pipe A*. A
closer analysis reveals that we try to read the scanline 3 times and
eventually timeout, b/c PSR hasn't exited fully leading to a PIPEDSL
stuck @ 1599. This issue is not seen on upstream kernels, b/c for *some*
reason we loop inside intel_pipe_update start for ~2+ msec which in this
case is more than enough to exit PSR fully, hence an *unstuck* PIPEDSL
counter, hence no error. On the other hand, the ChromeOS kernel spends
~1.1 msec looping inside intel_pipe_update_start and hence errors out
b/c the source is still in PSR.

Regardless, we should wait for PSR exit (if PSR is disabled, we incur
a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
fully exited PSR, then checking for vblank evasion isn't actually
applicable.

v4: Comment explaining psr_wait after enabling VBL interrupts (DK)

v5: CAN_PSR() to handle platforms that don't support PSR.

v6: Handle local_irq_disable on early return (Chris)

Signed-off-by: Tarun Vyas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 344c0e709b19..4990d6e84ddf 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -107,13 +107,21 @@ void intel_pipe_update_start(const struct 
intel_crtc_state *new_crtc_state)
  VBLANK_EVASION_TIME_US);
max = vblank_start - 1;
 
-   local_irq_disable();
-
if (min <= 0 || max <= 0)
-   return;
+   goto irq_disable;
 
if (WARN_ON(drm_crtc_vblank_get(>base)))
-   return;
+   goto irq_disable;
+
+   /*
+* Wait for psr to idle out after enabling the VBL interrupts
+* VBL interrupts will start the PSR exit and prevent a PSR
+* re-entry as well.
+*/
+   if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv))
+   DRM_ERROR("PSR idle timed out, atomic update may fail\n");
+
+   local_irq_disable();
 
crtc->debug.min_vbl = min;
crtc->debug.max_vbl = max;
@@ -171,6 +179,10 @@ void intel_pipe_update_start(const struct intel_crtc_state 
*new_crtc_state)
crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 
trace_i915_pipe_update_vblank_evaded(crtc);
+   return;
+
+irq_disable:
+   local_irq_disable();
 }
 
 /**
-- 
2.13.5

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to 
gen8_pte_encode
URL   : https://patchwork.freedesktop.org/series/45519/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
edc140b84d5c drm/i915/gtt: Add read only pages to gen8_pte_encode
efda09477394 drm/i915/gtt: Read-only pages for insert_entries on bdw+
-:192: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield.  Prefer bool 
bitfields as unsigned int or u<8|16|32>
#192: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:330:
+   bool pt_kmap_wc:1;

-:195: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield.  Prefer bool 
bitfields as unsigned int or u<8|16|32>
#195: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:333:
+   bool has_read_only:1;

-:271: WARNING:LINE_SPACING: Missing a blank line after declarations
#271: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:430:
+   struct drm_file *file;
+   I915_RND_STATE(prng);

-:342: ERROR:CODE_INDENT: code indent should use tabs where possible
#342: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:501:
+^I   ^Indwords, INTEL_INFO(i915)->num_rings);$

-:342: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#342: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:501:
+^I   ^Indwords, INTEL_INFO(i915)->num_rings);$

-:342: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#342: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:501:
+   pr_info("Submitted %lu dwords (across %u engines)\n",
+   ndwords, INTEL_INFO(i915)->num_rings);

total: 1 errors, 4 warnings, 1 checks, 323 lines checked
5526e0e6fc80 drm/i915: Prevent writing into a read-only object via a GGTT mmap
-:182: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield.  Prefer bool 
bitfields as unsigned int or u<8|16|32>
#182: FILE: include/drm/drm_vma_manager.h:44:
+   bool readonly:1;

total: 0 errors, 1 warnings, 0 checks, 118 lines checked
75194c6128be drm/i915: Reject attempted pwrites into a read-only object
0a9bd1dfbdf1 drm/i915/userptr: Enable read-only support on gen8+

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Add generic fbdev emulation

[Patchwork]

== Series Details ==

Series: drm: Add generic fbdev emulation
URL   : https://patchwork.freedesktop.org/series/45488/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9445_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9445_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9445_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9445_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  SKIP -> PASS

igt@gem_linear_blits@interruptible:
  shard-apl:  SKIP -> PASS

igt@kms_cursor_crc@cursor-128x128-sliding:
  shard-snb:  PASS -> SKIP +2

igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
  shard-hsw:  SKIP -> PASS

igt@perf_pmu@rc6:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9445_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_hangcheck:
  shard-apl:  NOTRUN -> DMESG-FAIL (fdo#106947, fdo#106560)

igt@gem_mmap_gtt@coherency:
  shard-glk:  NOTRUN -> FAIL (fdo#100587)

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  NOTRUN -> FAIL (fdo#106509, fdo#105454)

igt@kms_flip@dpms-vs-vblank-race:
  shard-glk:  PASS -> FAIL (fdo#103060)

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@drv_suspend@shrink:
  shard-snb:  FAIL (fdo#106886, fdo#107054) -> PASS

igt@gem_ctx_switch@basic-all-light:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@kms_flip@dpms-vs-vblank-race:
  shard-kbl:  FAIL (fdo#103060) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105189) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105363) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9445

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9445: c240e5f96c88d7a55f91b4faf366ab2680d4f459 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9445/shards.html
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[Intel-gfx] [CI 1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode

[Chris Wilson]

From: Jon Bloomfield 

We can set a bit inside the ppGTT PTE to indicate a page is read-only;
writes from the GPU will be discarded. We can use this to protect pages
and in particular support read-only userptr mappings (necessary for
importing PROT_READ vma).

Signed-off-by: Jon Bloomfield 
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 25 ++---
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c6aa761ca085..30914a765400 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -244,10 +244,13 @@ static void clear_pages(struct i915_vma *vma)
 }
 
 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
- enum i915_cache_level level)
+ enum i915_cache_level level,
+ u32 flags)
 {
-   gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW;
-   pte |= addr;
+   gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+
+   if (unlikely(flags & PTE_READ_ONLY))
+   pte &= ~_PAGE_RW;
 
switch (level) {
case I915_CACHE_NONE:
@@ -637,7 +640,7 @@ static void gen8_initialize_pt(struct i915_address_space 
*vm,
   struct i915_page_table *pt)
 {
fill_px(vm, pt,
-   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC));
+   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
 }
 
 static void gen6_initialize_pt(struct gen6_hw_ppgtt *ppgtt,
@@ -785,7 +788,7 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space 
*vm,
unsigned int pte = gen8_pte_index(start);
unsigned int pte_end = pte + num_entries;
const gen8_pte_t scratch_pte =
-   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
+   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
gen8_pte_t *vaddr;
 
GEM_BUG_ON(num_entries > pt->used_ptes);
@@ -960,7 +963,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
  enum i915_cache_level cache_level)
 {
struct i915_page_directory *pd;
-   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
+   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0);
gen8_pte_t *vaddr;
bool ret;
 
@@ -1028,7 +1031,7 @@ static void gen8_ppgtt_insert_huge_entries(struct 
i915_vma *vma,
   struct sgt_dma *iter,
   enum i915_cache_level cache_level)
 {
-   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
+   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0);
u64 start = vma->node.start;
dma_addr_t rem = iter->sg->length;
 
@@ -1494,7 +1497,7 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, 
struct seq_file *m)
 {
struct i915_address_space *vm = >vm;
const gen8_pte_t scratch_pte =
-   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
+   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
u64 start = 0, length = ppgtt->vm.total;
 
if (use_4lvl(vm)) {
@@ -2397,7 +2400,7 @@ static void gen8_ggtt_insert_page(struct 
i915_address_space *vm,
gen8_pte_t __iomem *pte =
(gen8_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT);
 
-   gen8_set_pte(pte, gen8_pte_encode(addr, level));
+   gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
 
ggtt->invalidate(vm->i915);
 }
@@ -2410,7 +2413,7 @@ static void gen8_ggtt_insert_entries(struct 
i915_address_space *vm,
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
struct sgt_iter sgt_iter;
gen8_pte_t __iomem *gtt_entries;
-   const gen8_pte_t pte_encode = gen8_pte_encode(0, level);
+   const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0);
dma_addr_t addr;
 
gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
@@ -2478,7 +2481,7 @@ static void gen8_ggtt_clear_range(struct 
i915_address_space *vm,
unsigned first_entry = start >> PAGE_SHIFT;
unsigned num_entries = length >> PAGE_SHIFT;
const gen8_pte_t scratch_pte =
-   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
+   gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
gen8_pte_t __iomem *gtt_base =
(gen8_pte_t __iomem *)ggtt->gsm + first_entry;
const int max_entries = ggtt_total_entries(ggtt) - first_entry;
-- 
2.18.0

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[Intel-gfx] [CI 4/5] drm/i915: Reject attempted pwrites into a read-only object

[Chris Wilson]

If the user created a read-only object, they should not be allowed to
circumvent the write protection using the pwrite ioctl.

Signed-off-by: Chris Wilson 
Cc: Jon Bloomfield 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
Reviewed-by: Jon Bloomfield 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_gem.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c17cc48d0476..0389074e5ec0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1623,6 +1623,12 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
goto err;
}
 
+   /* Writes not allowed into this read-only object */
+   if (i915_gem_object_is_readonly(obj)) {
+   ret = -EINVAL;
+   goto err;
+   }
+
trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 
ret = -ENODEV;
-- 
2.18.0

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[Intel-gfx] [CI 2/5] drm/i915/gtt: Read-only pages for insert_entries on bdw+

[Chris Wilson]

From: Jon Bloomfield 

Hook up the flags to allow read-only ppGTT mappings for gen8+

v2: Include a selftest to check that writes to a readonly PTE are
dropped
v3: Don't duplicate cpu_check() as we can just reuse it, and even worse
don't wholesale copy the theory-of-operation comment from igt_ctx_exec
without changing it to explain the intention behind the new test!
v4: Joonas really likes magic mystery values

Signed-off-by: Jon Bloomfield 
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c   |  45 ---
 drivers/gpu/drm/i915/i915_gem_gtt.h   |   7 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  11 +-
 .../gpu/drm/i915/selftests/i915_gem_context.c | 112 +-
 4 files changed, 153 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 30914a765400..3773e661dd9d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -204,7 +204,7 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
return err;
}
 
-   /* Currently applicable only to VLV */
+   /* Applicable to VLV, and gen8+ */
pte_flags = 0;
if (vma->obj->gt_ro)
pte_flags |= PTE_READ_ONLY;
@@ -960,10 +960,11 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
  struct i915_page_directory_pointer *pdp,
  struct sgt_dma *iter,
  struct gen8_insert_pte *idx,
- enum i915_cache_level cache_level)
+ enum i915_cache_level cache_level,
+ u32 flags)
 {
struct i915_page_directory *pd;
-   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0);
+   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
gen8_pte_t *vaddr;
bool ret;
 
@@ -1014,14 +1015,14 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt 
*ppgtt,
 static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
   struct i915_vma *vma,
   enum i915_cache_level cache_level,
-  u32 unused)
+  u32 flags)
 {
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct sgt_dma iter = sgt_dma(vma);
struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
 
gen8_ppgtt_insert_pte_entries(ppgtt, >pdp, , ,
- cache_level);
+ cache_level, flags);
 
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 }
@@ -1029,9 +1030,10 @@ static void gen8_ppgtt_insert_3lvl(struct 
i915_address_space *vm,
 static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
   struct i915_page_directory_pointer 
**pdps,
   struct sgt_dma *iter,
-  enum i915_cache_level cache_level)
+  enum i915_cache_level cache_level,
+  u32 flags)
 {
-   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0);
+   const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
u64 start = vma->node.start;
dma_addr_t rem = iter->sg->length;
 
@@ -1147,19 +1149,21 @@ static void gen8_ppgtt_insert_huge_entries(struct 
i915_vma *vma,
 static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
   struct i915_vma *vma,
   enum i915_cache_level cache_level,
-  u32 unused)
+  u32 flags)
 {
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct sgt_dma iter = sgt_dma(vma);
struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
 
if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
-   gen8_ppgtt_insert_huge_entries(vma, pdps, , cache_level);
+   gen8_ppgtt_insert_huge_entries(vma, pdps, , cache_level,
+  flags);
} else {
struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
 
while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
-, , cache_level))
+, , cache_level,
+flags))
GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
 
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
@@ -1572,6 +1576,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct 

[Intel-gfx] [CI 3/5] drm/i915: Prevent writing into a read-only object via a GGTT mmap

[Chris Wilson]

If the user has created a read-only object, they should not be allowed
to circumvent the write protection by using a GGTT mmapping. Deny it.

Also most machines do not support read-only GGTT PTEs, so again we have
to reject attempted writes. Fortunately, this is known a priori, so we
can at least reject in the call to create the mmap (with a sanity check
in the fault handler).

v2: Check the vma->vm_flags during mmap() to allow readonly access.
v3: Remove VM_MAYWRITE to curtail mprotect()

Testcase: igt/gem_userptr_blits/readonly_mmap*
Signed-off-by: Chris Wilson 
Cc: Jon Bloomfield 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
Cc: David Herrmann 
Reviewed-by: Matthew Auld  #v1
Reviewed-by: Jon Bloomfield 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/drm_gem.c |  9 +
 drivers/gpu/drm/i915/i915_gem.c   |  4 
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 12 +++-
 drivers/gpu/drm/i915/i915_gem_object.h| 13 -
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_context.c |  5 +++--
 include/drm/drm_vma_manager.h |  1 +
 7 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 4a16d7b26c89..bf90625df3c5 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -1036,6 +1036,15 @@ int drm_gem_mmap(struct file *filp, struct 
vm_area_struct *vma)
return -EACCES;
}
 
+   if (node->readonly) {
+   if (vma->vm_flags & VM_WRITE) {
+   drm_gem_object_put_unlocked(obj);
+   return -EINVAL;
+   }
+
+   vma->vm_flags &= ~VM_MAYWRITE;
+   }
+
ret = drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT,
   vma);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5a9cae604e2b..c17cc48d0476 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2009,6 +2009,10 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
unsigned int flags;
int ret;
 
+   /* Sanity check that we allow writing into this object */
+   if (i915_gem_object_is_readonly(obj) && write)
+   return VM_FAULT_SIGBUS;
+
/* We don't use vmf->pgoff since that has the fake offset */
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3773e661dd9d..f46d873a7530 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -206,7 +206,7 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
 
/* Applicable to VLV, and gen8+ */
pte_flags = 0;
-   if (vma->obj->gt_ro)
+   if (i915_gem_object_is_readonly(vma->obj))
pte_flags |= PTE_READ_ONLY;
 
vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
@@ -2423,8 +2423,10 @@ static void gen8_ggtt_insert_entries(struct 
i915_address_space *vm,
const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0);
dma_addr_t addr;
 
-   /* The GTT does not support read-only mappings */
-   GEM_BUG_ON(flags & PTE_READ_ONLY);
+   /*
+* Note that we ignore PTE_READ_ONLY here. The caller must be careful
+* not to allow the user to override access to a read only page.
+*/
 
gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
gtt_entries += vma->node.start >> PAGE_SHIFT;
@@ -2663,7 +2665,7 @@ static int ggtt_bind_vma(struct i915_vma *vma,
 
/* Applicable to VLV (gen8+ do not support RO in the GGTT) */
pte_flags = 0;
-   if (obj->gt_ro)
+   if (i915_gem_object_is_readonly(obj))
pte_flags |= PTE_READ_ONLY;
 
intel_runtime_pm_get(i915);
@@ -2701,7 +2703,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
 
/* Currently applicable only to VLV */
pte_flags = 0;
-   if (vma->obj->gt_ro)
+   if (i915_gem_object_is_readonly(vma->obj))
pte_flags |= PTE_READ_ONLY;
 
if (flags & I915_VMA_LOCAL_BIND) {
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h 
b/drivers/gpu/drm/i915/i915_gem_object.h
index 54f00b350779..fd703d768b70 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -141,7 +141,6 @@ struct drm_i915_gem_object {
 * Is the object to be mapped as read-only to the GPU
 * Only honoured if hardware has relevant pte bit
 */
-   unsigned long gt_ro:1;
unsigned int cache_level:3;
unsigned int cache_coherent:2;
 #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
@@ -367,6 +366,18 @@ static inline void i915_gem_object_unlock(struct 
drm_i915_gem_object *obj)
reservation_object_unlock(obj->resv);
 }
 
+static 

[Intel-gfx] [CI 5/5] drm/i915/userptr: Enable read-only support on gen8+

[Chris Wilson]

On gen8 and onwards, we can mark GPU accesses through the ppGTT as being
read-only, that is cause any GPU write onto that page to be discarded
(not triggering a fault). This is all that we need to finally support
the read-only flag for userptr!

Testcase: igt/gem_userptr_blits/readonly*
Signed-off-by: Chris Wilson 
Cc: Jon Bloomfield 
Cc: Joonas Lahtinen 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Matthew Auld 
Reviewed-by: Jon Bloomfield 
---
 drivers/gpu/drm/i915/i915_gem_object.h  |  1 -
 drivers/gpu/drm/i915/i915_gem_userptr.c | 15 +--
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_object.h 
b/drivers/gpu/drm/i915/i915_gem_object.h
index fd703d768b70..b2dc2ece3ca3 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -267,7 +267,6 @@ struct drm_i915_gem_object {
union {
struct i915_gem_userptr {
uintptr_t ptr;
-   unsigned read_only :1;
 
struct i915_mm_struct *mm;
struct i915_mmu_object *mmu_object;
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 854bd51b9478..045db5ef17ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -507,7 +507,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct 
*_work)
struct mm_struct *mm = obj->userptr.mm->mm;
unsigned int flags = 0;
 
-   if (!obj->userptr.read_only)
+   if (!i915_gem_object_is_readonly(obj))
flags |= FOLL_WRITE;
 
ret = -EFAULT;
@@ -643,7 +643,7 @@ static int i915_gem_userptr_get_pages(struct 
drm_i915_gem_object *obj)
if (pvec) /* defer to worker if malloc fails */
pinned = __get_user_pages_fast(obj->userptr.ptr,
   num_pages,
-  !obj->userptr.read_only,
+  
!i915_gem_object_is_readonly(obj),
   pvec);
}
 
@@ -789,10 +789,12 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
return -EFAULT;
 
if (args->flags & I915_USERPTR_READ_ONLY) {
-   /* On almost all of the current hw, we cannot tell the GPU that 
a
-* page is readonly, so this is just a placeholder in the uAPI.
+   /*
+* On almost all of the older hw, we cannot tell the GPU that
+* a page is readonly.
 */
-   return -ENODEV;
+   if (INTEL_GEN(dev_priv) < 8 || !USES_PPGTT(dev_priv))
+   return -ENODEV;
}
 
obj = i915_gem_object_alloc(dev_priv);
@@ -806,7 +808,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
 
obj->userptr.ptr = args->user_ptr;
-   obj->userptr.read_only = !!(args->flags & I915_USERPTR_READ_ONLY);
+   if (args->flags & I915_USERPTR_READ_ONLY)
+   i915_gem_object_set_readonly(obj);
 
/* And keep a pointer to the current->mm for resolving the user pages
 * at binding. This means that we need to hook into the mmu_notifier
-- 
2.18.0

___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915/execlists: Pull submit after dequeue under timeline lock

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/execlists: Pull submit after 
dequeue under timeline lock
URL   : https://patchwork.freedesktop.org/series/45482/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9444_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9444_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9444_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9444_full:

  === IGT changes ===

 Possible regressions 

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  {shard-glk9}:   PASS -> FAIL


 Warnings 

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  PASS -> SKIP

igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
  shard-hsw:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9444_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@mock_scatterlist:
  shard-kbl:  NOTRUN -> DMESG-WARN (fdo#103667)

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
  shard-snb:  PASS -> FAIL (fdo#103167, fdo#104724)


 Possible fixes 

igt@drv_selftest@live_gtt:
  shard-glk:  INCOMPLETE (k.org#198133, fdo#103359) -> PASS
  shard-apl:  INCOMPLETE (fdo#103927) -> PASS

igt@drv_suspend@shrink:
  shard-snb:  FAIL (fdo#107054, fdo#106886) -> PASS

igt@gem_ctx_switch@basic-all-light:
  shard-hsw:  INCOMPLETE (fdo#103540) -> PASS

igt@gem_softpin@noreloc-s3:
  shard-kbl:  INCOMPLETE (fdo#103665) -> PASS

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105189) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9444

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9444: 3c095bbd351f896736360b6787b7d3f7d0b946ab @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9444/shards.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Wait for engines to idle before retiring

[Patchwork]

== Series Details ==

Series: drm/i915: Wait for engines to idle before retiring
URL   : https://patchwork.freedesktop.org/series/45484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4389 -> Patchwork_9450 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45484/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9450 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   PASS -> DMESG-FAIL (fdo#106103, fdo#107054, 
fdo#102614)

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: PASS -> FAIL (fdo#104008)
  fi-glk-j4005:   PASS -> FAIL (fdo#104008)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: INCOMPLETE (fdo#103927, fdo#107054) -> PASS


  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4389 -> Patchwork_9450

  CI_DRM_4389: 2a8b5fa69bd30a6068e4ca4aadf72867f3a2351f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9450: f2c5deeffc3a3ce60f92c35cb4e6049f099ec889 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f2c5deeffc3a drm/i915: Wait for engines to idle before retiring

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9450/issues.html
___
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Re: [Intel-gfx] [REGRESSION] 4.18-rc2: X61s thinkpad display unusable after xlock & lid close

[Vito Caputo]

On Wed, Jun 27, 2018 at 05:18:39PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 26, 2018 at 05:05:48PM -0700, Vito Caputo wrote:
> > Hello,
> > 
> > Beginning with 4.18, when I lock my X server using the `xlock` command,
> > and close the lid, upon reopening the lid I am not presented with the
> > xlock UI.
> > 
> > The system is not hung.  If I blindly enter the password, I get an
> > intact and functional pointer but none of the desktop is displayed.  I
> > can move the pointer, and cycling window focus generates some random
> > noise occasionally, but it's all nonsensical.  No windows are
> > discernable, it's just blackness with ephemeral noise on window cycles,
> > and a movable pointer.
> > 
> > The system does not suspend on lid close, with "HandleLidSwitch=ignore"
> > in logind.conf.  So this is a bit odd, since I don't observe this when I
> > just run `xlock` but don't close/open the lid before unlocking.
> > 
> > This is on Debian 9.4 amd64, the hardware is a 1.8Ghz X61s ThinkPad,
> > kernel config attached.  I'm using the modesetting Xorg driver on i915
> > KMS.
> 
> Ah, a Thinkpad with lid notifier. Now were getting somewhere :)
> 
> Can you pls test the stuff I listed here
> https://bugs.freedesktop.org/show_bug.cgi?id=105902#c5 ?
> 

Cherry-picking 8860e829faad on top of v4.18-rc2 seems to have fixed the
problem here.

Unfortunately I'm short on time currently to perform a bisect in the
interests of identifying the lid notification-breaking commit between
4.17 and 4.18.

Thanks,
Vito Caputo
___
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Re: [Intel-gfx] [PATCH v4] drm/i915: Fix assert_plane() warning on bootup with external display

[Ville Syrjälä]

On Wed, Jun 27, 2018 at 10:39:56AM -0700, Radhakrishna Sripada wrote:
> On Tue, Jun 26, 2018 at 05:55:59PM -0700, Azhar Shaikh wrote:
> > On KBL, WHL RVPs, booting up with an external display connected, triggers
> > below warning, when the BiOS brings up the external display too.
> > This warning is not seen during hotplug.
> > 
> > [3.615226] [ cut here ]
> > [3.619829] plane 1A assertion failure (expected on, current off)
> > [3.632039] WARNING: CPU: 2 PID: 354 at 
> > drivers/gpu/drm/i915/intel_display.c:1294 assert_plane+0x71/0xbb
> > [3.633920] iwlwifi :00:14.3: loaded firmware version 38.c0e03d94.0 
> > op_mode iwlmvm
> > [3.647157] Modules linked in: iwlwifi cfg80211 btusb btrtl btbcm 
> > btintel bluetooth ecdh_generic
> > [3.647163] CPU: 2 PID: 354 Comm: frecon Not tainted 
> > 4.17.0-rc7-50176-g655af12d39c2 #3
> > [3.647165] Hardware name: Intel Corporation CoffeeLake Client 
> > Platform/WhiskeyLake U DDR4 ERB, BIOS CNLSFWR1.R00.X140.B00.1804040304 
> > 04/04/2018
> > [3.684509] RIP: 0010:assert_plane+0x71/0xbb
> > [3.764451] Call Trace:
> > [3.766888]  intel_atomic_commit_tail+0xa97/0xb77
> > [3.771569]  intel_atomic_commit+0x26a/0x279
> > [3.771572]  drm_atomic_helper_set_config+0x5c/0x76
> > [3.780670]  __drm_mode_set_config_internal+0x66/0x109
> > [3.780672]  drm_mode_setcrtc+0x4c9/0x5cc
> > [3.780674]  ? drm_mode_getcrtc+0x162/0x162
> > [3.789774]  ? drm_mode_getcrtc+0x162/0x162
> > [3.798108]  drm_ioctl_kernel+0x8d/0xe4
> > [3.801926]  drm_ioctl+0x27d/0x368
> > [3.805311]  ? drm_mode_getcrtc+0x162/0x162
> > [3.805314]  ? selinux_file_ioctl+0x14e/0x199
> > [3.805317]  vfs_ioctl+0x21/0x2f
> > [3.813812]  do_vfs_ioctl+0x491/0x4b4
> > [3.813813]  ? security_file_ioctl+0x37/0x4b
> > [3.813816]  ksys_ioctl+0x55/0x75
> > [3.820672]  __x64_sys_ioctl+0x1a/0x1e
> > [3.820674]  do_syscall_64+0x51/0x5f
> > [3.820678]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
> > [3.828221] RIP: 0033:0x7b5e04953967
> > [3.835504] RSP: 002b:7fff2eafb6f8 EFLAGS: 0246 ORIG_RAX: 
> > 0010
> > [3.835505] RAX: ffda RBX: 0002 RCX: 
> > 7b5e04953967
> > [3.835505] RDX: 7fff2eafb730 RSI: c06864a2 RDI: 
> > 000f
> > [3.835506] RBP: 7fff2eafb720 R08:  R09: 
> > 
> > [3.835507] R10: 0070 R11: 0246 R12: 
> > 000f
> > [3.879988] R13: 56bc9dd7d210 R14: 7fff2eafb730 R15: 
> > c06864a2
> > [3.887081] Code: 48 c7 c7 06 71 a5 be 84 c0 48 c7 c2 06 fd a3 be 48 89 
> > f9 48 0f 44 ca 84 db 48 0f 45 d7 48 c7 c7 df d3 a4 be 31 c0 e8 af a0 c0 ff 
> > <0f> 0b eb 2b 48 c7 c7 06 fd a3 be 84 c0 48 c7 c2 06 71 a5 be 48
> > [3.905845] WARNING: CPU: 2 PID: 354 at 
> > drivers/gpu/drm/i915/intel_display.c:1294 assert_plane+0x71/0xbb
> > [3.920964] ---[ end trace dac692f4ac46391a ]---
> > 
> > The warning is seen when mode_setcrtc() is called for pipeB
> > during bootup and before we get a mode_setcrtc() for pipeA,
> > while doing update_crtcs() in intel_atomic_commit_tail().
> > Now since, plane1A is still active after commit, update_crtcs()
> > is done for pipeA and eventually update_plane() for plane1A.
> > 
> > intel_plane_state->ctl for plane1A is not updated since set_modecrtc() is
> > called for pipeB. So intel_plane_state->ctl for plane 1A will be 0x0.
> > So doing an update_plane() for plane1A, will result in clearing
> > PLANE_CTL_ENABLE bit, and hence the warning.
> > 
> > To fix this warning, force all active planes to recompute their states
> > in probe.
> > 
> > Signed-off-by: Azhar Shaikh 
> > ---
> > Changes in v4:
> > - Handle locking in intel_initial_commit()
> > - Move the for loop inside intel_initial_commit() so that
> >   drm_atomic_commit() is called only once
> > - Call intel_initial_commit() only for more than one active crtc on boot.
> > - Save the return value of intel_initial_commit() and print a message in
> >   case of an error
> > 
> > Changes in v3:
> > - Add comments
> > 
> > Changes in v2:
> > - Force all planes to recompute their states.(Ville Syrjälä)
> > - Update the commit message
> 
> Include the changelog in the commit message above Signed-off-by
> > 
> >  drivers/gpu/drm/i915/intel_display.c | 81 
> > +++-
> >  1 file changed, 79 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 3709fa1b6318..40bdb28aa2a5 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15092,12 +15092,76 @@ static void intel_update_fdi_pll_freq(struct 
> > drm_i915_private *dev_priv)
> > DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
> >  }
> >  
> > +static int intel_initial_commit(struct drm_device *dev)
> > +{

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Wait for engines to idle before retiring

[Patchwork]

== Series Details ==

Series: drm/i915: Wait for engines to idle before retiring
URL   : https://patchwork.freedesktop.org/series/45484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9449 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45484/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9449 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@debugfs_test@read_all_entries:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


 Possible fixes 

igt@kms_chamelium@dp-edid-read:
  fi-kbl-7500u:   FAIL (fdo#103841) -> PASS


  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9449

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9449: d4e1a15d8976c8d91bd97ad63ee667df3c08030a @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d4e1a15d8976 drm/i915: Wait for engines to idle before retiring

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9449/issues.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Improve crc-core driver interface (rev3)

[Patchwork]

== Series Details ==

Series: Improve crc-core driver interface (rev3)
URL   : https://patchwork.freedesktop.org/series/45246/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9447 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9447 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9447, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45246/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9447:

  === IGT changes ===

 Possible regressions 

igt@kms_pipe_crc_basic@bad-source:
  fi-skl-6770hq:  PASS -> FAIL +6
  fi-bwr-2160:PASS -> FAIL +4
  fi-hsw-4770r:   PASS -> FAIL +6
  fi-glk-j4005:   PASS -> FAIL
  fi-cfl-8700k:   PASS -> FAIL +6
  fi-cnl-psr: PASS -> FAIL
  {fi-kbl-x1275}: PASS -> FAIL
  fi-kbl-guc: PASS -> FAIL
  fi-glk-dsi: PASS -> FAIL
  fi-bsw-n3050:   PASS -> FAIL

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
  fi-ivb-3520m:   PASS -> FAIL +6
  fi-cfl-s3:  PASS -> FAIL +6
  fi-skl-6700hq:  PASS -> FAIL +6
  fi-skl-guc: PASS -> FAIL +6
  fi-blb-e6850:   PASS -> FAIL +4
  fi-byt-j1900:   PASS -> FAIL +4

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
  fi-ilk-650: PASS -> FAIL +4
  fi-elk-e7500:   PASS -> FAIL +4
  fi-byt-n2820:   PASS -> FAIL +4
  fi-snb-2520m:   PASS -> FAIL +4

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
  fi-bdw-5557u:   PASS -> FAIL +6
  fi-pnv-d510:PASS -> FAIL +4
  fi-skl-6600u:   PASS -> FAIL +6
  fi-bxt-dsi: PASS -> FAIL +6
  fi-hsw-4770:PASS -> FAIL +6
  fi-cfl-guc: PASS -> FAIL +6
  fi-ivb-3770:PASS -> FAIL +6

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
  fi-hsw-peppy:   PASS -> FAIL +6
  fi-bdw-gvtdvm:  PASS -> FAIL +6
  fi-gdg-551: PASS -> FAIL +4
  fi-kbl-7500u:   PASS -> FAIL +6
  fi-snb-2600:PASS -> FAIL +4

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
  fi-kbl-7567u:   PASS -> FAIL +6
  fi-skl-6260u:   PASS -> FAIL +6
  fi-skl-6700k2:  PASS -> FAIL +6
  fi-skl-gvtdvm:  PASS -> FAIL +6
  fi-bxt-j4205:   PASS -> FAIL +6
  fi-kbl-7560u:   PASS -> FAIL +6
  fi-whl-u:   PASS -> FAIL +6
  fi-kbl-r:   PASS -> FAIL +6


== Known issues ==

  Here are the changes found in Patchwork_9447 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
  fi-cnl-psr: PASS -> FAIL (fdo#106211) +5

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
  fi-glk-j4005:   PASS -> FAIL (fdo#106211) +5
  fi-bsw-n3050:   PASS -> FAIL (fdo#106211) +1

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  fi-glk-dsi: PASS -> FAIL (fdo#106211) +5


 Possible fixes 

igt@gem_exec_gttfill@basic:
  fi-byt-n2820:   FAIL (fdo#106744) -> PASS

igt@kms_chamelium@dp-edid-read:
  fi-kbl-7500u:   FAIL (fdo#103841) -> PASS


  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#106211 https://bugs.freedesktop.org/show_bug.cgi?id=106211
  fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9447

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9447: 904f779ffebbf617c4dcfc9d88c376b859f287fe @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

904f779ffebb Revert "drm: crc: Wait for a frame before returning from open()"
96aafbd70ef6 drm/crc: Cleanup crtc_crc_open function
942dc4f19471 drm/i915/crc: implement get_crc_sources callback
2c0afe823995 drm/i915/crc: implement verify_crc_source callback
6a5efb0f1291 drm/rcar-du/crc: Implement verify_crc_source callback
c3ae842570e2 drm/amdgpu_dm/crc: Implement verify_crc_source callback
7a6a81775e48 drm/rockchip/crc: Implement verify_crc_source callback
ba79e3af7743 drm: crc: Introduce get_crc_sources callback

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP2.2 (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Implement HDCP2.2 (rev7)
URL   : https://patchwork.freedesktop.org/series/38254/
State : failure

== Summary ==

Applying: drm: hdcp2.2 authentication msg definitions
Applying: drm: HDMI and DP specific HDCP2.2 defines
Applying: mei: bus: whitelist hdcp client
Applying: linux/mei: Header for mei_hdcp driver interface
Applying: drm/i915: wrapping all hdcp var into intel_hdcp
Applying: drm/i915: Define HDCP2.2 related variables
Applying: drm/i915: Define Intel HDCP2.2 registers
Applying: drm/i915: Initialize HDCP2.2 and its MEI interface
Applying: drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable
Applying: drm/i915: Pullout the bksv read and validation
Applying: drm/i915: Enable superior HDCP ver that is capable
Applying: drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure
Applying: drm/i915: Implement HDCP2.2 Enable and Disable
Applying: drm/i915: Enable and Disable HDCP2.2 port encryption
Applying: drm/i915: Implement HDCP2.2 receiver authentication
Applying: drm/i915: Implement HDCP2.2 repeater authentication
Applying: drm/i915: Implement HDCP2.2 link integrity check
Applying: drm/i915: Handle HDCP2.2 downstream topology change
Applying: drm/i915: hdcp_check_link only on CP_IRQ
Applying: drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ
Applying: drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
Applying: drm/i915/gmbus: Enable burst read
Applying: drm/i915: Implement the HDCP2.2 support for DP
Applying: drm/i915: Implement the HDCP2.2 support for HDMI
Applying: drm/i915: Add HDCP2.2 support for DP connectors
Applying: drm/i915: Add HDCP2.2 support for HDMI connectors
Applying: misc/mei/hdcp: Client driver for HDCP application
Applying: misc/mei/hdcp: mei_hdcp_component_registered can be static
Using index info to reconstruct a base tree...
M   drivers/misc/mei/hdcp/mei_hdcp.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/misc/mei/hdcp/mei_hdcp.c
CONFLICT (content): Merge conflict in drivers/misc/mei/hdcp/mei_hdcp.c
error: Failed to merge in the changes.
Patch failed at 0028 misc/mei/hdcp: mei_hdcp_component_registered can be static
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
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Re: [Intel-gfx] [PATCH v4] drm/i915: Fix assert_plane() warning on bootup with external display

[Radhakrishna Sripada]

On Tue, Jun 26, 2018 at 05:55:59PM -0700, Azhar Shaikh wrote:
> On KBL, WHL RVPs, booting up with an external display connected, triggers
> below warning, when the BiOS brings up the external display too.
> This warning is not seen during hotplug.
> 
> [3.615226] [ cut here ]
> [3.619829] plane 1A assertion failure (expected on, current off)
> [3.632039] WARNING: CPU: 2 PID: 354 at 
> drivers/gpu/drm/i915/intel_display.c:1294 assert_plane+0x71/0xbb
> [3.633920] iwlwifi :00:14.3: loaded firmware version 38.c0e03d94.0 
> op_mode iwlmvm
> [3.647157] Modules linked in: iwlwifi cfg80211 btusb btrtl btbcm btintel 
> bluetooth ecdh_generic
> [3.647163] CPU: 2 PID: 354 Comm: frecon Not tainted 
> 4.17.0-rc7-50176-g655af12d39c2 #3
> [3.647165] Hardware name: Intel Corporation CoffeeLake Client 
> Platform/WhiskeyLake U DDR4 ERB, BIOS CNLSFWR1.R00.X140.B00.1804040304 
> 04/04/2018
> [3.684509] RIP: 0010:assert_plane+0x71/0xbb
> [3.764451] Call Trace:
> [3.766888]  intel_atomic_commit_tail+0xa97/0xb77
> [3.771569]  intel_atomic_commit+0x26a/0x279
> [3.771572]  drm_atomic_helper_set_config+0x5c/0x76
> [3.780670]  __drm_mode_set_config_internal+0x66/0x109
> [3.780672]  drm_mode_setcrtc+0x4c9/0x5cc
> [3.780674]  ? drm_mode_getcrtc+0x162/0x162
> [3.789774]  ? drm_mode_getcrtc+0x162/0x162
> [3.798108]  drm_ioctl_kernel+0x8d/0xe4
> [3.801926]  drm_ioctl+0x27d/0x368
> [3.805311]  ? drm_mode_getcrtc+0x162/0x162
> [3.805314]  ? selinux_file_ioctl+0x14e/0x199
> [3.805317]  vfs_ioctl+0x21/0x2f
> [3.813812]  do_vfs_ioctl+0x491/0x4b4
> [3.813813]  ? security_file_ioctl+0x37/0x4b
> [3.813816]  ksys_ioctl+0x55/0x75
> [3.820672]  __x64_sys_ioctl+0x1a/0x1e
> [3.820674]  do_syscall_64+0x51/0x5f
> [3.820678]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
> [3.828221] RIP: 0033:0x7b5e04953967
> [3.835504] RSP: 002b:7fff2eafb6f8 EFLAGS: 0246 ORIG_RAX: 
> 0010
> [3.835505] RAX: ffda RBX: 0002 RCX: 
> 7b5e04953967
> [3.835505] RDX: 7fff2eafb730 RSI: c06864a2 RDI: 
> 000f
> [3.835506] RBP: 7fff2eafb720 R08:  R09: 
> 
> [3.835507] R10: 0070 R11: 0246 R12: 
> 000f
> [3.879988] R13: 56bc9dd7d210 R14: 7fff2eafb730 R15: 
> c06864a2
> [3.887081] Code: 48 c7 c7 06 71 a5 be 84 c0 48 c7 c2 06 fd a3 be 48 89 f9 
> 48 0f 44 ca 84 db 48 0f 45 d7 48 c7 c7 df d3 a4 be 31 c0 e8 af a0 c0 ff <0f> 
> 0b eb 2b 48 c7 c7 06 fd a3 be 84 c0 48 c7 c2 06 71 a5 be 48
> [3.905845] WARNING: CPU: 2 PID: 354 at 
> drivers/gpu/drm/i915/intel_display.c:1294 assert_plane+0x71/0xbb
> [3.920964] ---[ end trace dac692f4ac46391a ]---
> 
> The warning is seen when mode_setcrtc() is called for pipeB
> during bootup and before we get a mode_setcrtc() for pipeA,
> while doing update_crtcs() in intel_atomic_commit_tail().
> Now since, plane1A is still active after commit, update_crtcs()
> is done for pipeA and eventually update_plane() for plane1A.
> 
> intel_plane_state->ctl for plane1A is not updated since set_modecrtc() is
> called for pipeB. So intel_plane_state->ctl for plane 1A will be 0x0.
> So doing an update_plane() for plane1A, will result in clearing
> PLANE_CTL_ENABLE bit, and hence the warning.
> 
> To fix this warning, force all active planes to recompute their states
> in probe.
> 
> Signed-off-by: Azhar Shaikh 
> ---
> Changes in v4:
> - Handle locking in intel_initial_commit()
> - Move the for loop inside intel_initial_commit() so that
>   drm_atomic_commit() is called only once
> - Call intel_initial_commit() only for more than one active crtc on boot.
> - Save the return value of intel_initial_commit() and print a message in
>   case of an error
> 
> Changes in v3:
> - Add comments
> 
> Changes in v2:
> - Force all planes to recompute their states.(Ville Syrjälä)
> - Update the commit message

Include the changelog in the commit message above Signed-off-by
> 
>  drivers/gpu/drm/i915/intel_display.c | 81 
> +++-
>  1 file changed, 79 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 3709fa1b6318..40bdb28aa2a5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15092,12 +15092,76 @@ static void intel_update_fdi_pll_freq(struct 
> drm_i915_private *dev_priv)
>   DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
>  }
>  
> +static int intel_initial_commit(struct drm_device *dev)
> +{
> + struct drm_atomic_state *state = NULL;
> + struct drm_modeset_acquire_ctx ctx;
> + struct drm_crtc_state *crtc_state;
> + struct intel_crtc *intel_crtc;
> + int ret = 0;
> +
> + drm_modeset_acquire_init(, 0);
> +
> +retry:
> + state = 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: encourage BIT() macro usage in register definitions

[Patchwork]

== Series Details ==

Series: drm/i915: encourage BIT() macro usage in register definitions
URL   : https://patchwork.freedesktop.org/series/45498/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9446 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45498/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9446 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@kms_chamelium@dp-edid-read:
  fi-kbl-7500u:   FAIL (fdo#103841) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: INCOMPLETE (fdo#107054, fdo#103927) -> PASS


  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9446

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9446: d22f87f4e6805dea2e32f6b9e0a78f1717cff8f4 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d22f87f4e680 drm/i915: encourage BIT() macro usage in register definitions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9446/issues.html
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Re: [Intel-gfx] [DIM DOCS PATCH 2/2] doc: clarify what type of changes are acceptable at commit time

[Daniel Vetter]

On Wed, Jun 27, 2018 at 5:13 PM, Jani Nikula  wrote:
> As a rule of thumb, don't change patches while committing.
>
> Cc: Imre Deak 
> Signed-off-by: Jani Nikula 
> ---
>  drm-intel.rst | 7 +++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drm-intel.rst b/drm-intel.rst
> index baf48f459dd9..ad8ff9739336 100644
> --- a/drm-intel.rst
> +++ b/drm-intel.rst
> @@ -196,6 +196,13 @@ An inexhaustive list of details to check:
>coordinate with maintainers to avoid unnecessary pain with conflicts. 
> Usually
>some explicit merges are needed to avoid git getting lost.
>
> +* As a general rule, do not modify the patches while applying, apart from the
> +  commit message. If the patch conflicts, or needs to be changed due to 
> review,
> +  have the author rebase, update and resend. Any change at this stage is a
> +  potential issue bypassing CI.
>
Should we also mention that merge conflicts need to be told to
maintainers, so that they can do a backmerge? Just because this blew
up recently for drm-misc ...
-Daniel

> +  At most, minor comment and whitespace tweaks are acceptable.
> +
>  On Confidence, Complexity, and Transparency
>  ---
>
> --
> 2.11.0
>
> ___
> dim-tools mailing list
> dim-to...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dim-tools



-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [DIM DOCS PATCH 1/2] doc: update CI and pre-merge details in committer guidelines

[Daniel Vetter]

On Wed, Jun 27, 2018 at 5:13 PM, Jani Nikula  wrote:
> Lots has happened in the CI front since the first version was added.
>
> Signed-off-by: Jani Nikula 
> ---
>  drm-intel.rst | 45 -
>  1 file changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a/drm-intel.rst b/drm-intel.rst
> index c68949a41c95..baf48f459dd9 100644
> --- a/drm-intel.rst
> +++ b/drm-intel.rst
> @@ -172,6 +172,8 @@ An inexhaustive list of details to check:
>`details on testing requirements
>`_.
>
> +* The patch series has passed CI pre-merge testing. See CI details below.
> +
>  * An open source userspace, reviewed and ready for merging by the upstream
>project, must be available for new kernel ABI. Please see `details on
>upstreaming requirements
> @@ -186,11 +188,6 @@ An inexhaustive list of details to check:
>(or the author) stand a chance to fairly quickly understand what goes 
> wrong if
>the commit is reported to cause a regression?
>
> -* `checkpatch.pl` does not complain. (Some of the more subjective warnings 
> may
> -  be ignored at the committer's discretion.)
> -
> -* The patch does not introduce new `sparse` warnings.
> -
>  * When pushing someone else's patch you must add your own signed-off per
>http://developercertificate.org/. dim apply-branch should do this
>automatically for you.
> @@ -244,8 +241,6 @@ On Confidence, Complexity, and Transparency
>you have involved enough people to feel comfortable if the justification 
> for
>the commit is questioned afterwards.
>
> -* Make sure pre-merge testing is completed successfully.
> -
>  On Rough Consensus
>  --
>
> @@ -290,18 +285,34 @@ discussions happen in public forums, and make sure 
> there's a searchable
>  permanent record of any discussions for later reference. This means that for
>  most things internal meetings are not the most suitable venue.
>
> -Pre-Merge Testing
> --
> +Continuous Integration and Pre-Merge Testing
> +
> +
> +The requirements for CI_ pre-merge testing are:
> +
> +* ``checkpatch.pl`` does not complain. (Some of the more subjective warnings 
> may
> +  be ignored at the committer's discretion.)
> +
> +* The patch does not introduce new ``sparse`` warnings.
> +
> +* Patch series must pass IGT Basic Acceptance Tests (BAT) on all the CI 
> machines
> +  without causing regressions.
> +
> +* Patch series must pass full IGT tests on CI shard machines without causing
> +  regressions.

* Patch series must pass gpu piglit tests on all CI machines without
causing regressions.

Very recent addition, and thus far hasn't really resulted in
breakage/regression reports, but it's there production.

Otherwise lgtm, ack.
-Daniel

> +
> +The CI bots will send results to the patch author and intel-gfx for any 
> patches
> +tracked by patchwork. The results are also available on patchwork_ and the 
> CI_
> +site.
> +
> +Check CI failures and make sure any sporadic failures are a) pre-existing,
> +and b) tracked in bugzilla. If there's anything dubious that you can't track
> +down to pre-existing and tracked issues please don't push, but instead figure
> +out what's going on.
>
> -Our CI infrastructure is being built up and currently requirements for 
> pre-merge
> -testing are fairly simple:
> +.. _CI: https://intel-gfx-ci.01.org/
>
> -* All patches must past IGT Basic Acceptance Tests (BAT) on all the CI 
> machines
> -  without causing regressions.  The CI bots will send results to intel-gfx 
> for
> -  any patches tracked by patchwork. Check CI failures and make sure any 
> sporadic
> -  failures are a) pre-existing b) tracked in bugzilla. If there's anything
> -  dubious that you can't track down to pre-existing issues please 
> don't
> -  push, but instead figure out what's going on.
> +.. _patchwork: https://patchwork.freedesktop.org/project/intel-gfx/series/
>
>  Tooling
>  ===
> --
> 2.11.0
>
> ___
> dim-tools mailing list
> dim-to...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dim-tools



-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Add generic fbdev emulation

[Patchwork]

== Series Details ==

Series: drm: Add generic fbdev emulation
URL   : https://patchwork.freedesktop.org/series/45488/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9445 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45488/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9445 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: PASS -> FAIL (fdo#104008)


 Possible fixes 

igt@gem_exec_gttfill@basic:
  fi-byt-n2820:   FAIL (fdo#106744) -> PASS

igt@kms_chamelium@dp-edid-read:
  fi-kbl-7500u:   FAIL (fdo#103841) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: INCOMPLETE (fdo#103927, fdo#107054) -> PASS


  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9445

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9445: c240e5f96c88d7a55f91b4faf366ab2680d4f459 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c240e5f96c88 drm/cma-helper: Remove drm_fb_cma_fbdev_init_with_funcs()
0cf48089f8dd drm/tinydrm: Use drm_fbdev_generic_setup()
06da1c06d25e drm/fb-helper: Finish the generic fbdev emulation
31ff61ad53c0 drm/debugfs: Add internal client debugfs file
4c842b91d792 drm/client: Add client callbacks
6e28794b79ab drm/cma-helper: Use the generic fbdev emulation
6b6b258ed3ef drm/pl111: Set .gem_prime_vmap and .gem_prime_mmap
b405648a927c drm/fb-helper: Add generic fbdev emulation .fb_probe function
b94e8e78c556 drm: Begin an API for in-kernel clients

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9445/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Add generic fbdev emulation

[Patchwork]

== Series Details ==

Series: drm: Add generic fbdev emulation
URL   : https://patchwork.freedesktop.org/series/45488/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm: Begin an API for in-kernel clients
Okay!

Commit: drm/fb-helper: Add generic fbdev emulation .fb_probe function
+drivers/gpu/drm/drm_fb_helper.c:1006:20: warning: expression using sizeof(void)
+drivers/gpu/drm/drm_fb_helper.c:1006:20: warning: expression using sizeof(void)
+drivers/gpu/drm/drm_fb_helper.c:1007:20: warning: expression using sizeof(void)
+drivers/gpu/drm/drm_fb_helper.c:1007:20: warning: expression using sizeof(void)
+drivers/gpu/drm/drm_fb_helper.c:1008:20: warning: expression using sizeof(void)
+drivers/gpu/drm/drm_fb_helper.c:1008:20: warning: expression using sizeof(void)
+drivers/gpu/drm/drm_fb_helper.c:1009:20: warning: expression using sizeof(void)
+drivers/gpu/drm/drm_fb_helper.c:1009:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1006:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1006:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1007:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1007:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1008:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1008:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1009:20: warning: expression using sizeof(void)
-drivers/gpu/drm/drm_fb_helper.c:1009:20: warning: expression using sizeof(void)

Commit: drm/pl111: Set .gem_prime_vmap and .gem_prime_mmap
Okay!

Commit: drm/cma-helper: Use the generic fbdev emulation
Okay!

Commit: drm/client: Add client callbacks
Okay!

Commit: drm/debugfs: Add internal client debugfs file
Okay!

Commit: drm/fb-helper: Finish the generic fbdev emulation
Okay!

Commit: drm/tinydrm: Use drm_fbdev_generic_setup()
Okay!

Commit: drm/cma-helper: Remove drm_fb_cma_fbdev_init_with_funcs()
Okay!

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Add generic fbdev emulation

[Patchwork]

== Series Details ==

Series: drm: Add generic fbdev emulation
URL   : https://patchwork.freedesktop.org/series/45488/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b94e8e78c556 drm: Begin an API for in-kernel clients
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#26: 
new file mode 100644

-:31: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier 
tag in line 1
#31: FILE: Documentation/gpu/drm-client.rst:1:
+=

total: 0 errors, 2 warnings, 0 checks, 412 lines checked
b405648a927c drm/fb-helper: Add generic fbdev emulation .fb_probe function
6b6b258ed3ef drm/pl111: Set .gem_prime_vmap and .gem_prime_mmap
6e28794b79ab drm/cma-helper: Use the generic fbdev emulation
-:359: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#359: FILE: drivers/gpu/drm/drm_fb_cma_helper.c:172:
+struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev,
+   unsigned int preferred_bpp, unsigned int max_conn_count)

total: 0 errors, 0 warnings, 1 checks, 426 lines checked
4c842b91d792 drm/client: Add client callbacks
31ff61ad53c0 drm/debugfs: Add internal client debugfs file
06da1c06d25e drm/fb-helper: Finish the generic fbdev emulation
0cf48089f8dd drm/tinydrm: Use drm_fbdev_generic_setup()
c240e5f96c88 drm/cma-helper: Remove drm_fb_cma_fbdev_init_with_funcs()

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/execlists: Pull submit after dequeue under timeline lock

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/execlists: Pull submit after 
dequeue under timeline lock
URL   : https://patchwork.freedesktop.org/series/45482/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9444 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/45482/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9444 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@gem_exec_gttfill@basic:
  fi-byt-n2820:   FAIL (fdo#106744) -> PASS

igt@kms_chamelium@dp-edid-read:
  fi-kbl-7500u:   FAIL (fdo#103841) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: INCOMPLETE (fdo#107054, fdo#103927) -> PASS


  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744
  fdo#107054 https://bugs.freedesktop.org/show_bug.cgi?id=107054


== Participating hosts (45 -> 40) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4388 -> Patchwork_9444

  CI_DRM_4388: b3654d40e9004f17bb612e71aee129347ea2c4aa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9444: 3c095bbd351f896736360b6787b7d3f7d0b946ab @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3c095bbd351f drm/i915/execlists: Direct submission of new requests (avoid 
tasklet/ksoftirqd)
3f6971a35173 drm/i915/execlists: Reset CSB write pointer after reset
a674da9caa38 drm/i915/execlists: Unify CSB access pointers
cc1911d5fd49 drm/i915/execlists: Process one CSB update at a time
46bb4948501f drm/i915/execlists: Pull CSB reset under the timeline.lock
19f59a7491b7 drm/i915/execlists: Pull submit after dequeue under timeline lock

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9444/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915: encourage BIT() macro usage in register definitions

[Chris Wilson]

Quoting Michal Wajdeczko (2018-06-27 16:51:42)
> On Wed, 27 Jun 2018 16:41:13 +0200, Jani Nikula   
> wrote:
> 
> > There's already some BIT() usage here and there, embrace it.
> >
> > Cc: Paulo Zanoni 
> > Signed-off-by: Jani Nikula 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 9 +
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h  
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 476118f46cf3..64b9c270045d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -65,9 +65,10 @@
> >   * but do note that the macros may be needed to read as well as write  
> > the
> >   * register contents.
> >   *
> > - * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change  
> > this in
> > - * the future, but this is the prevailing style. Do **not** add  
> > ``_BIT`` suffix
> > - * to the name.
> > + * Define bits using ``BIT(N)`` instead of ``(1 << N)``. Do **not** add  
> > ``_BIT``
> > + * suffix to the name. Exception to ``BIT()`` usage: Value 1 for a bit  
> > field
> > + * should be defined using ``(1 << N)`` to be in line with other values  
> > such as
> > + * ``(2 << N)`` for the same field.
> >   *
> >   * Group the register and its contents together without blank lines,  
> > separate
> >   * from other registers and their contents with one blank line.
> > @@ -105,7 +106,7 @@
> >   *  #define _FOO_A  0xf000
> >   *  #define _FOO_B  0xf001
> >   *  #define FOO(pipe)   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
> > - *  #define   FOO_ENABLE(1 << 31)
> > + *  #define   FOO_ENABLEBIT(31)
> 
> hmm, this breaks nice consistency between one- and multi-bit fields ..
> 
> >   *  #define   FOO_MODE_MASK (0xf << 16)
> 
> .. but if you want to use macro for single bit, then maybe you should
> also consider other existing macro for the mask definition:
> 
> #define   FOO_MODE_MASK GENMASK(19, 16)
> 
> >   *  #define   FOO_MODE_SHIFT16
> >   *  #define   FOO_MODE_BAR  (0 << 16)
> 
> .. but we still don't have any macro for defining multi-bit values
> so I'm not sure if this change will make code really easier to read

#include 

I'm not sure if I'm ready to embrace that yet, but it does seem to be
the direction we should be heading in. Primarily to check the invalid
range checking & usage.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: encourage BIT() macro usage in register definitions

[Michal Wajdeczko]

On Wed, 27 Jun 2018 16:41:13 +0200, Jani Nikula   
wrote:



There's already some BIT() usage here and there, embrace it.

Cc: Paulo Zanoni 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_reg.h | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h  
b/drivers/gpu/drm/i915/i915_reg.h

index 476118f46cf3..64b9c270045d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -65,9 +65,10 @@
  * but do note that the macros may be needed to read as well as write  
the

  * register contents.
  *
- * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change  
this in
- * the future, but this is the prevailing style. Do **not** add  
``_BIT`` suffix

- * to the name.
+ * Define bits using ``BIT(N)`` instead of ``(1 << N)``. Do **not** add  
``_BIT``
+ * suffix to the name. Exception to ``BIT()`` usage: Value 1 for a bit  
field
+ * should be defined using ``(1 << N)`` to be in line with other values  
such as

+ * ``(2 << N)`` for the same field.
  *
  * Group the register and its contents together without blank lines,  
separate

  * from other registers and their contents with one blank line.
@@ -105,7 +106,7 @@
  *  #define _FOO_A  0xf000
  *  #define _FOO_B  0xf001
  *  #define FOO(pipe)   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
- *  #define   FOO_ENABLE(1 << 31)
+ *  #define   FOO_ENABLEBIT(31)


hmm, this breaks nice consistency between one- and multi-bit fields ..


  *  #define   FOO_MODE_MASK (0xf << 16)


.. but if you want to use macro for single bit, then maybe you should
also consider other existing macro for the mask definition:

   #define   FOO_MODE_MASK GENMASK(19, 16)


  *  #define   FOO_MODE_SHIFT16
  *  #define   FOO_MODE_BAR  (0 << 16)


.. but we still don't have any macro for defining multi-bit values
so I'm not sure if this change will make code really easier to read

Michal
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Re: [Intel-gfx] [PATCH 07/31] drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-06-27 16:21:24)
> 
> On 27/06/2018 14:29, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-06-27 14:15:22)
> >>
> >> On 27/06/2018 11:58, Chris Wilson wrote:
> >>> That tasklets get kicked randomly, I think was the culprit.
> >>
> >> What do you mean? I hope we have busy-idle quite controlled and we know
> >> when we should and should expect a tasklet. If we synced them when
> >> transitioning to idle they cannot happen. Otherwise we better be active!
> >> GEM_BUG_ON(!engine->i915->gt.awake) instead? Does that trigger?!
> > 
> > tasklet_schedule() is called off the main path, without locking, so
> > unsynchronized to parking. Just because.
> 
> I need to understand this - which main path? Submission - we will be 
> mark_busy. After last request - we will idle the engines and sync the 
> tasklet.

There's a bonus kick in intel_engine_is_idle() (behind an unprotected
read of active, so still possible to race), and I've added an
unconditional kick to pmu_enable because we play games with
tasklet_disable there that may cause us to miss a direct submission.
-Chris
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Re: [Intel-gfx] [PATCH 02/10] drm: crc: Introduce pre_crc_read function

[Kumar, Mahesh]

Hi,


On 6/27/2018 8:48 PM, Maarten Lankhorst wrote:

Op 27-06-18 om 16:44 schreef Mahesh Kumar:

This patch implements a callback function "pre_crc_read" which will
be called before crc read. In this function driver can implement and
preparation work required for successfully reading CRC data.

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
  drivers/gpu/drm/drm_debugfs_crc.c |  8 
  include/drm/drm_crtc.h| 14 ++
  2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
b/drivers/gpu/drm/drm_debugfs_crc.c
index c6a725b79ac6..2b4a737c5aeb 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -278,6 +278,14 @@ static ssize_t crtc_crc_read(struct file *filep, char 
__user *user_buf,
return 0;
}
  
+	if (crtc->funcs->pre_crc_read) {

+   ret = crtc->funcs->pre_crc_read(crtc);
+   if (ret) {
+   spin_unlock_irq(>lock);
+   return ret;
+   }
+   }
+
/* Nothing to read? */
while (crtc_crc_data_count(crc) == 0) {
if (filep->f_flags & O_NONBLOCK) {
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 1a6dcbf91744..bae432469616 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -676,6 +676,20 @@ struct drm_crtc_funcs {
 */
int (*verify_crc_source)(struct drm_crtc *crtc, const char *source,
 size_t *values_cnt);
+   /**
+* @pre_crc_read:
+*
+* Driver callback for performing any preparation work required by
+* driver before reading CRC
+*
+* This callback is optional if the driver does not support CRC
+* generation or no prework is required before reading the crc
+*
+* RETURNS:
+*
+* 0 on success or a negative error code on failure.
+*/
+   int (*pre_crc_read)(struct drm_crtc *crtc);
  
  	/**

 * @atomic_print_state:

I think this patch might have to be dropped, or reordered after the revert in 
10/10, because else in theory open could block. :)

Or maybe just drop until we have upstream kernel users?

thanks,
Can reorder it after patch-10 and if others also vote to drop it will 
take decision accordingly, atleast it should not block other patches :)


-Mahesh


~Maarten



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Re: [Intel-gfx] [PATCH 10/10] Revert "drm: crc: Wait for a frame before returning from open()"

[Maarten Lankhorst]

Op 27-06-18 om 16:44 schreef Mahesh Kumar:
> This reverts commit e8fa5671183c80342d520ad81d14fa79a9d4a680.
>
> Don't wait for first CRC during crtc_crc_open. It avoids one frame wait
> during open. If application want to wait after read call, it can use
> poll/read blocking read() call.
>
> Suggested-by: Ville Syrjälä 
> Signed-off-by: Mahesh Kumar 
> Cc: dri-de...@lists.freedesktop.org
> Cc: Tomeu Vizoso 
> ---
>  drivers/gpu/drm/drm_debugfs_crc.c | 16 
>  1 file changed, 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
> b/drivers/gpu/drm/drm_debugfs_crc.c
> index 08dfe19b6286..7aeed89f934a 100644
> --- a/drivers/gpu/drm/drm_debugfs_crc.c
> +++ b/drivers/gpu/drm/drm_debugfs_crc.c
> @@ -226,24 +226,8 @@ static int crtc_crc_open(struct inode *inode, struct 
> file *filep)
>   if (ret)
>   goto err;
>  
> - spin_lock_irq(>lock);
> - /*
> -  * Only return once we got a first frame, so userspace doesn't have to
> -  * guess when this particular piece of HW will be ready to start
> -  * generating CRCs.
> -  */
> - ret = wait_event_interruptible_lock_irq(crc->wq,
> - crtc_crc_data_count(crc),
> - crc->lock);
> - spin_unlock_irq(>lock);
> -
> - if (ret)
> - goto err_disable;
> -
>   return 0;
>  
> -err_disable:
> - crtc->funcs->set_crc_source(crtc, NULL);
>  err:
>   spin_lock_irq(>lock);
>   crtc_crc_cleanup(crc);

For the whole series except 2/10:

Reviewed-by: Maarten Lankhorst 

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Re: [Intel-gfx] [PATCH 07/31] drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)

[Tvrtko Ursulin]

On 27/06/2018 14:29, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-06-27 14:15:22)


On 27/06/2018 11:58, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-06-27 11:40:32)


On 25/06/2018 10:48, Chris Wilson wrote:

Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on average! Deferring our work to a tasklet allowed us to do the
processing with irqs enabled, reducing the impact to an average of about
50us.

We have since eradicated the use of forcewaked mmio from inside the CSB
processing and ELSP submission, bringing the impact down to around 5us
(on Kabylake); an order of magnitude better than our measurements 2
years ago on Broadwell and only about 2x worse on average than the
gem_syslatency on an unladen system.

In this iteration of the tasklet-vs-direct submission debate, we seek a
compromise where by we submit new requests immediately to the HW but
defer processing the CS interrupt onto a tasklet. We gain the advantage
of low-latency and ksoftirqd avoidance when waking up the HW, while
avoiding the system-wide starvation of our CS irq-storms.

Comparing the impact on the maximum latency observed (that is the time
stolen from an RT process) over a 120s interval, repeated several times
(using gem_syslatency, similar to RT's cyclictest) while the system is
fully laden with i915 nops, we see that direct submission an actually
improve the worse case.

Maximum latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 2)
 x Always using tasklets (a couple of >1000us outliers removed)
 + Only using tasklets from CS irq, direct submission of requests
++
|  + |
|  + |
|  + |
|  +   + |
|  + + + |
|   +  + + +  x x x  |
|  +++ + + +  x  x  x  x  x  x   |
|  +++ + ++  + +  *x x  x  x  x  x   |
|  +++ + ++  + *  *x x  *  x  x  x   |
|+ +++ + ++  * * +*xxx  *  x  x  xx  |
|* +++ + * *x+**xx+ *  x  x  x   |
|   **x*++**+*x*xx+ * +x xx  x  x|
|x* **+***++*+***xx* xx*x xxx +x+|
| |__MA___|  |
|  |__M__A|  |
++
   N   Min   MaxMedian   AvgStddev
x 11891   186   124 125.28814 16.279137
+ 12092   187   109 112.00833 13.458617
Difference at 95.0% confidence
-13.2798 +/- 3.79219
-10.5994% +/- 3.02677%
(Student's t, pooled s = 14.9237)

However the mean latency is adversely affected:

Mean latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 1)
 x Always using tasklets
 + Only using tasklets from CS irq, direct submission of requests
++
|   xx+   ++ |
|   xx+   ++ |
|   xx  + +++ ++ |
|   xxx + ++ |
|   xxx + ++ |
|   xxx + +++|
|   xxx   + ++   |
|    ++ ++   |
|    ++ ++   |
|  xx+++ |
| xxxx   +++ |
|x   x   x   ++ ++  +|
|   |__A__|  |
|  |A___||
++
   N   Min   MaxMedian   Avg

Re: [Intel-gfx] [PATCH 02/10] drm: crc: Introduce pre_crc_read function

[Maarten Lankhorst]

Op 27-06-18 om 16:44 schreef Mahesh Kumar:
> This patch implements a callback function "pre_crc_read" which will
> be called before crc read. In this function driver can implement and
> preparation work required for successfully reading CRC data.
>
> Signed-off-by: Mahesh Kumar 
> Cc: dri-de...@lists.freedesktop.org
> ---
>  drivers/gpu/drm/drm_debugfs_crc.c |  8 
>  include/drm/drm_crtc.h| 14 ++
>  2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
> b/drivers/gpu/drm/drm_debugfs_crc.c
> index c6a725b79ac6..2b4a737c5aeb 100644
> --- a/drivers/gpu/drm/drm_debugfs_crc.c
> +++ b/drivers/gpu/drm/drm_debugfs_crc.c
> @@ -278,6 +278,14 @@ static ssize_t crtc_crc_read(struct file *filep, char 
> __user *user_buf,
>   return 0;
>   }
>  
> + if (crtc->funcs->pre_crc_read) {
> + ret = crtc->funcs->pre_crc_read(crtc);
> + if (ret) {
> + spin_unlock_irq(>lock);
> + return ret;
> + }
> + }
> +
>   /* Nothing to read? */
>   while (crtc_crc_data_count(crc) == 0) {
>   if (filep->f_flags & O_NONBLOCK) {
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 1a6dcbf91744..bae432469616 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -676,6 +676,20 @@ struct drm_crtc_funcs {
>*/
>   int (*verify_crc_source)(struct drm_crtc *crtc, const char *source,
>size_t *values_cnt);
> + /**
> +  * @pre_crc_read:
> +  *
> +  * Driver callback for performing any preparation work required by
> +  * driver before reading CRC
> +  *
> +  * This callback is optional if the driver does not support CRC
> +  * generation or no prework is required before reading the crc
> +  *
> +  * RETURNS:
> +  *
> +  * 0 on success or a negative error code on failure.
> +  */
> + int (*pre_crc_read)(struct drm_crtc *crtc);
>  
>   /**
>* @atomic_print_state:

I think this patch might have to be dropped, or reordered after the revert in 
10/10, because else in theory open could block. :)

Or maybe just drop until we have upstream kernel users?

~Maarten

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[Intel-gfx] [DIM DOCS PATCH 1/2] doc: update CI and pre-merge details in committer guidelines

[Jani Nikula]

Lots has happened in the CI front since the first version was added.

Signed-off-by: Jani Nikula 
---
 drm-intel.rst | 45 -
 1 file changed, 28 insertions(+), 17 deletions(-)

diff --git a/drm-intel.rst b/drm-intel.rst
index c68949a41c95..baf48f459dd9 100644
--- a/drm-intel.rst
+++ b/drm-intel.rst
@@ -172,6 +172,8 @@ An inexhaustive list of details to check:
   `details on testing requirements
   `_.
 
+* The patch series has passed CI pre-merge testing. See CI details below.
+
 * An open source userspace, reviewed and ready for merging by the upstream
   project, must be available for new kernel ABI. Please see `details on
   upstreaming requirements
@@ -186,11 +188,6 @@ An inexhaustive list of details to check:
   (or the author) stand a chance to fairly quickly understand what goes wrong 
if
   the commit is reported to cause a regression?
 
-* `checkpatch.pl` does not complain. (Some of the more subjective warnings may
-  be ignored at the committer's discretion.)
-
-* The patch does not introduce new `sparse` warnings.
-
 * When pushing someone else's patch you must add your own signed-off per
   http://developercertificate.org/. dim apply-branch should do this
   automatically for you.
@@ -244,8 +241,6 @@ On Confidence, Complexity, and Transparency
   you have involved enough people to feel comfortable if the justification for
   the commit is questioned afterwards.
 
-* Make sure pre-merge testing is completed successfully.
-
 On Rough Consensus
 --
 
@@ -290,18 +285,34 @@ discussions happen in public forums, and make sure 
there's a searchable
 permanent record of any discussions for later reference. This means that for
 most things internal meetings are not the most suitable venue.
 
-Pre-Merge Testing
--
+Continuous Integration and Pre-Merge Testing
+
+
+The requirements for CI_ pre-merge testing are:
+
+* ``checkpatch.pl`` does not complain. (Some of the more subjective warnings 
may
+  be ignored at the committer's discretion.)
+
+* The patch does not introduce new ``sparse`` warnings.
+
+* Patch series must pass IGT Basic Acceptance Tests (BAT) on all the CI 
machines
+  without causing regressions.
+
+* Patch series must pass full IGT tests on CI shard machines without causing
+  regressions.
+
+The CI bots will send results to the patch author and intel-gfx for any patches
+tracked by patchwork. The results are also available on patchwork_ and the CI_
+site.
+
+Check CI failures and make sure any sporadic failures are a) pre-existing,
+and b) tracked in bugzilla. If there's anything dubious that you can't track
+down to pre-existing and tracked issues please don't push, but instead figure
+out what's going on.
 
-Our CI infrastructure is being built up and currently requirements for 
pre-merge
-testing are fairly simple:
+.. _CI: https://intel-gfx-ci.01.org/
 
-* All patches must past IGT Basic Acceptance Tests (BAT) on all the CI machines
-  without causing regressions.  The CI bots will send results to intel-gfx for
-  any patches tracked by patchwork. Check CI failures and make sure any 
sporadic
-  failures are a) pre-existing b) tracked in bugzilla. If there's anything
-  dubious that you can't track down to pre-existing issues please don't
-  push, but instead figure out what's going on.
+.. _patchwork: https://patchwork.freedesktop.org/project/intel-gfx/series/
 
 Tooling
 ===
-- 
2.11.0

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[Intel-gfx] [DIM DOCS PATCH 2/2] doc: clarify what type of changes are acceptable at commit time

[Jani Nikula]

As a rule of thumb, don't change patches while committing.

Cc: Imre Deak 
Signed-off-by: Jani Nikula 
---
 drm-intel.rst | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drm-intel.rst b/drm-intel.rst
index baf48f459dd9..ad8ff9739336 100644
--- a/drm-intel.rst
+++ b/drm-intel.rst
@@ -196,6 +196,13 @@ An inexhaustive list of details to check:
   coordinate with maintainers to avoid unnecessary pain with conflicts. Usually
   some explicit merges are needed to avoid git getting lost.
 
+* As a general rule, do not modify the patches while applying, apart from the
+  commit message. If the patch conflicts, or needs to be changed due to review,
+  have the author rebase, update and resend. Any change at this stage is a
+  potential issue bypassing CI.
+
+  At most, minor comment and whitespace tweaks are acceptable.
+
 On Confidence, Complexity, and Transparency
 ---
 
-- 
2.11.0

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Re: [Intel-gfx] [PATCH 3/8] drm: Add drm_for_each_connector_encoder_ids()

[Ville Syrjälä]

On Wed, Jun 27, 2018 at 11:11:57AM +0200, Daniel Vetter wrote:
> On Wed, Jun 27, 2018 at 11:08:48AM +0200, Daniel Vetter wrote:
> > On Tue, Jun 26, 2018 at 08:47:09PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > > 
> > > Add a convenience macro for iterating connector->encoder_ids[].
> > > Isolates the users from the implementation details.
> > > 
> > > Also use ARRAY_SIZE() when populating the array to avoid spreading
> > > knowledge about the array size all over.
> > > 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/drm_connector.c| 22 ++
> > >  drivers/gpu/drm/drm_fb_helper.c|  6 +++---
> > >  drivers/gpu/drm/drm_probe_helper.c |  9 +
> > >  include/drm/drm_connector.h| 11 +++
> > >  4 files changed, 29 insertions(+), 19 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_connector.c 
> > > b/drivers/gpu/drm/drm_connector.c
> > > index 2f9ebddd178e..c43646cb8145 100644
> > > --- a/drivers/gpu/drm/drm_connector.c
> > > +++ b/drivers/gpu/drm/drm_connector.c
> > > @@ -321,7 +321,7 @@ int drm_mode_connector_attach_encoder(struct 
> > > drm_connector *connector,
> > >   if (WARN_ON(connector->encoder))
> > >   return -EINVAL;
> > >  
> > > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> > > + for (i = 0; i < ARRAY_SIZE(connector->encoder_ids); i++) {
> > >   if (connector->encoder_ids[i] == 0) {
> > >   connector->encoder_ids[i] = encoder->base.id;
> > >   return 0;
> > > @@ -1693,6 +1693,7 @@ int drm_mode_getconnector(struct drm_device *dev, 
> > > void *data,
> > >   int encoders_count = 0;
> > >   int ret = 0;
> > >   int copied = 0;
> > > + u32 encoder_id;
> > >   int i;
> > >   struct drm_mode_modeinfo u_mode;
> > >   struct drm_mode_modeinfo __user *mode_ptr;
> > > @@ -1708,22 +1709,19 @@ int drm_mode_getconnector(struct drm_device *dev, 
> > > void *data,
> > >   if (!connector)
> > >   return -ENOENT;
> > >  
> > > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++)
> > > - if (connector->encoder_ids[i] != 0)
> > > - encoders_count++;
> > > + drm_for_each_connector_encoder_ids(connector, encoder_id, i)
> > > + encoders_count++;
> > >  
> > >   if ((out_resp->count_encoders >= encoders_count) && encoders_count) {
> > >   copied = 0;
> > >   encoder_ptr = (uint32_t __user *)(unsigned 
> > > long)(out_resp->encoders_ptr);
> > > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> > > - if (connector->encoder_ids[i] != 0) {
> > > - if (put_user(connector->encoder_ids[i],
> > > -  encoder_ptr + copied)) {
> > > - ret = -EFAULT;
> > > - goto out;
> > > - }
> > > - copied++;
> > > +
> > > + drm_for_each_connector_encoder_ids(connector, encoder_id, i) {
> > > + if (put_user(encoder_id, encoder_ptr + copied)) {
> > > + ret = -EFAULT;
> > > + goto out;
> > >   }
> > > + copied++;
> > >   }
> > >   }
> > >   out_resp->count_encoders = encoders_count;
> > > diff --git a/drivers/gpu/drm/drm_fb_helper.c 
> > > b/drivers/gpu/drm/drm_fb_helper.c
> > > index 61c39cd75a27..e086b08748f4 100644
> > > --- a/drivers/gpu/drm/drm_fb_helper.c
> > > +++ b/drivers/gpu/drm/drm_fb_helper.c
> > > @@ -2326,12 +2326,12 @@ static bool drm_target_preferred(struct 
> > > drm_fb_helper *fb_helper,
> > >  static bool connector_crtc_ok(struct drm_connector *connector,
> > > struct drm_crtc *crtc)
> > >  {
> > > + u32 encoder_id;
> > >   int i;
> > >  
> > > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> > > + drm_for_each_connector_encoder_ids(connector, encoder_id, i) {
> > >   struct drm_encoder *encoder =
> > > - drm_encoder_find(connector->dev, NULL,
> > > -  connector->encoder_ids[i]);
> > > + drm_encoder_find(connector->dev, NULL, encoder_id);
> > >  
> > >   if (encoder->possible_crtcs & drm_crtc_mask(crtc))
> > >   return true;
> > > diff --git a/drivers/gpu/drm/drm_probe_helper.c 
> > > b/drivers/gpu/drm/drm_probe_helper.c
> > > index 527743394150..0239f76c52fb 100644
> > > --- a/drivers/gpu/drm/drm_probe_helper.c
> > > +++ b/drivers/gpu/drm/drm_probe_helper.c
> > > @@ -88,9 +88,9 @@ drm_mode_validate_pipeline(struct drm_display_mode 
> > > *mode,
> > >   struct drm_connector *connector)
> > >  {
> > >   struct drm_device *dev = connector->dev;
> > > - uint32_t *ids = connector->encoder_ids;
> > >   enum drm_mode_status ret = MODE_OK;
> > > - unsigned int i;
> > > + u32 encoder_id;
> > > + int i;
> > >  
> > >   /* Step 1: Validate against connector */
> > >   ret = 

Re: [Intel-gfx] [PATCH 14/31] drm/i915: Only signal from interrupt when requested

[Mika Kuoppala]

Chris Wilson  writes:

> Avoid calling dma_fence_signal() from inside the interrupt if we haven't
> enabled signaling on the request.
>
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 8 ++--
>  drivers/gpu/drm/i915/i915_request.c | 2 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++---
>  3 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6730c1a7f135..0f0e64c915a2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1173,7 +1173,8 @@ static void notify_ring(struct intel_engine_cs *engine)
>   if (i915_seqno_passed(seqno, wait->seqno)) {
>   struct i915_request *waiter = wait->request;
>  
> - if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
> + if (waiter &&
> + !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
> >fence.flags) &&
>   intel_wait_check_request(wait, waiter))
>   rq = i915_request_get(waiter);
> @@ -1196,8 +1197,11 @@ static void notify_ring(struct intel_engine_cs *engine)
>   spin_unlock(>breadcrumbs.irq_lock);
>  
>   if (rq) {
> - dma_fence_signal(>fence);
> + spin_lock(>lock);
> + dma_fence_signal_locked(>fence);
>   GEM_BUG_ON(!i915_request_completed(rq));
> + spin_unlock(>lock);
> +
>   i915_request_put(rq);
>   }
>  
> diff --git a/drivers/gpu/drm/i915/i915_request.c 
> b/drivers/gpu/drm/i915/i915_request.c
> index 696125663105..14bf0be6f994 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1250,7 +1250,7 @@ long i915_request_wait(struct i915_request *rq,
>   if (flags & I915_WAIT_LOCKED)
>   add_wait_queue(errq, );
>  
> - intel_wait_init(, rq);
> + intel_wait_init();
>  
>  restart:
>   do {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 33602eb1c77f..4fd7c7b80fdb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -940,11 +940,10 @@ static inline u32 intel_hws_preempt_done_address(struct 
> intel_engine_cs *engine)
>  /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
>  int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
>  
> -static inline void intel_wait_init(struct intel_wait *wait,
> -struct i915_request *rq)
> +static inline void intel_wait_init(struct intel_wait *wait)
>  {
>   wait->tsk = current;
> - wait->request = rq;
> + wait->request = NULL;

Enabling signaling will setup the correct request for
those who might be wondering. So reduced locking and using more
lightweight variant.

Reviewed-by: Mika Kuoppala 
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[Intel-gfx] [PATCH i-g-t 4/5] igt: Add gem_ctx_engines

[Chris Wilson]

To exercise the new I915_CONTEXT_PARAM_ENGINES and interactions with
gem_execbuf().

Signed-off-by: Chris Wilson 
---
 tests/Makefile.sources  |   1 +
 tests/gem_ctx_engines.c | 236 
 tests/meson.build   |   1 +
 3 files changed, 238 insertions(+)
 create mode 100644 tests/gem_ctx_engines.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bd0bd5439..a7d4a8699 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -57,6 +57,7 @@ TESTS_progs = \
gem_ctx_bad_destroy \
gem_ctx_bad_exec \
gem_ctx_create \
+   gem_ctx_engines \
gem_ctx_exec \
gem_ctx_isolation \
gem_ctx_param \
diff --git a/tests/gem_ctx_engines.c b/tests/gem_ctx_engines.c
new file mode 100644
index 0..5dcbc3c90
--- /dev/null
+++ b/tests/gem_ctx_engines.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "i915/gem_context.h"
+
+struct i915_user_extension {
+   uint64_t next_extension;
+   uint64_t name;
+};
+
+struct i915_context_param_engines {
+   uint64_t extensions;
+
+   struct {
+   uint32_t class;
+   uint32_t instance;
+   } class_instance[0];
+};
+#define I915_CONTEXT_PARAM_ENGINES 0x7
+
+static bool has_context_engines(int i915)
+{
+   struct drm_i915_gem_context_param param = {
+   .ctx_id = 0,
+   .param = I915_CONTEXT_PARAM_ENGINES,
+   };
+   return __gem_context_set_param(i915, ) == 0;
+}
+
+static void invalid_engines(int i915)
+{
+   struct i915_context_param_engines stack = {}, *engines;
+   struct drm_i915_gem_context_param param = {
+   .ctx_id = gem_context_create(i915),
+   .param = I915_CONTEXT_PARAM_ENGINES,
+   .value = to_user_pointer(),
+   };
+   void *ptr;
+
+   param.size = 0;
+   igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+   param.size = 1;
+   igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+   param.size = sizeof(stack) - 1;
+   igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+   param.size = sizeof(stack) + 1;
+   igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+   param.size = 0;
+   igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+   /* Create a single page surrounded by inaccessible nothingness */
+   ptr = mmap(NULL, 3 * 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+   igt_assert(ptr != MAP_FAILED);
+
+   munmap(ptr, 4096);
+   engines = ptr + 4096;
+   munmap(ptr + 2 *4096, 4096);
+
+   param.size = sizeof(*engines) + sizeof(*engines->class_instance);
+   param.value = to_user_pointer(engines);
+
+   engines->class_instance[0].class = -1;
+   igt_assert_eq(__gem_context_set_param(i915, ), -ENOENT);
+
+   mprotect(engines, 4096, PROT_READ);
+   igt_assert_eq(__gem_context_set_param(i915, ), -ENOENT);
+
+   mprotect(engines, 4096, PROT_WRITE);
+   engines->class_instance[0].class = 0;
+   if (__gem_context_set_param(i915, )) /* XXX needs RCS */
+   goto out;
+
+   engines->extensions = to_user_pointer(ptr);
+   igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+   engines->extensions = 0;
+   igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+   param.value = to_user_pointer(engines - 1);
+   igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+   param.value = to_user_pointer(engines) - 1;
+   igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+   param.value = to_user_pointer(engines) - param.size +  1;
+   

[Intel-gfx] [PATCH i-g-t 5/5] igt: Add gem_exec_balancer

[Chris Wilson]

Exercise the in-kernel load balancer checking that we can distribute
batches across the set of ctx->engines to avoid load.

Signed-off-by: Chris Wilson 
---
 tests/Makefile.am |   1 +
 tests/Makefile.sources|   1 +
 tests/gem_exec_balancer.c | 465 ++
 tests/meson.build |   1 +
 4 files changed, 468 insertions(+)
 create mode 100644 tests/gem_exec_balancer.c

diff --git a/tests/Makefile.am b/tests/Makefile.am
index f41ad5096..c6f5932f7 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -106,6 +106,7 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_close_race_LDADD = $(LDADD) -lpthread
 gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_ctx_thrash_LDADD = $(LDADD) -lpthread
+gem_exec_balancer_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
 gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_exec_parallel_LDADD = $(LDADD) -lpthread
 gem_fence_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index a7d4a8699..bce7bbdad 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -72,6 +72,7 @@ TESTS_progs = \
gem_exec_async \
gem_exec_await \
gem_exec_bad_domains \
+   gem_exec_balancer \
gem_exec_basic \
gem_exec_big \
gem_exec_blt \
diff --git a/tests/gem_exec_balancer.c b/tests/gem_exec_balancer.c
new file mode 100644
index 0..125d32304
--- /dev/null
+++ b/tests/gem_exec_balancer.c
@@ -0,0 +1,465 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+
+#include "igt.h"
+#include "igt_perf.h"
+#include "i915/gem_ring.h"
+#include "sw_sync.h"
+
+IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
+
+#define I915_CONTEXT_PARAM_ENGINES 0x7
+
+struct class_instance {
+   uint32_t class;
+   uint32_t instance;
+};
+
+static bool has_class_instance(int i915, uint32_t class, uint32_t instance)
+{
+   int fd;
+
+   fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+   if (fd != -1) {
+   close(fd);
+   return true;
+   }
+
+   return false;
+}
+
+static struct class_instance *
+list_engines(int i915, uint32_t class_mask, unsigned int *out)
+{
+   unsigned int count = 0, size = 64;
+   struct class_instance *engines;
+
+   engines = malloc(size * sizeof(*engines));
+   if (!engines) {
+   *out = 0;
+   return NULL;
+   }
+
+   for (enum drm_i915_gem_engine_class class = I915_ENGINE_CLASS_RENDER;
+class_mask;
+class++, class_mask >>= 1) {
+   if (!(class_mask & 1))
+   continue;
+
+   for (unsigned int instance = 0;
+has_class_instance(i915, class, instance);
+instance++) {
+   if (count == size) {
+   struct class_instance *e;
+
+   size *= 2;
+   e = realloc(engines, size*sizeof(*engines));
+   if (!e) {
+   *out = count;
+   return engines;
+   }
+
+   engines = e;
+   }
+
+   engines[count++] = (struct class_instance){
+   .class = class,
+   .instance = instance,
+   };
+   }
+   }
+
+   if (!count) {
+   free(engines);
+   engines = NULL;
+   }
+
+   *out = count;
+   return engines;
+}
+
+static int __set_load_balancer(int i915, uint32_t ctx,
+  const struct class_instance *ci,
+ 

Re: [Intel-gfx] [PATCH v3 4/9] drm/cma-helper: Use the generic fbdev emulation

[kbuild test robot]

Hi Noralf,

I love your patch! Perhaps something to improve:

[auto build test WARNING on next-20180627]
[cannot apply to drm/drm-next linus/master drm-exynos/exynos-drm/for-next 
v4.18-rc2 v4.18-rc1 v4.17 v4.18-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Noralf-Tr-nnes/drm-Add-generic-fbdev-emulation/20180627-222604
config: i386-randconfig-x018-201825 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings

All warnings (new ones prefixed by >>):

   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 include/linux/err.h:PTR_ERR
   Cyclomatic Complexity 1 include/linux/err.h:IS_ERR
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 28 include/linux/slab.h:kmalloc_index
   Cyclomatic Complexity 67 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 5 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 2 drivers/gpu/drm/drm_fb_cma_helper.c:to_fbdev_cma
   Cyclomatic Complexity 3 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fb_cma_get_gem_obj
   Cyclomatic Complexity 2 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fb_cma_get_gem_addr
   Cyclomatic Complexity 4 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fbdev_cma_init
   Cyclomatic Complexity 2 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fb_cma_fbdev_init
   Cyclomatic Complexity 1 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fb_cma_fbdev_init_with_funcs
   Cyclomatic Complexity 1 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fbdev_cma_fini
   Cyclomatic Complexity 2 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fb_cma_fbdev_fini
   Cyclomatic Complexity 2 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fbdev_cma_restore_mode
   Cyclomatic Complexity 2 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fbdev_cma_hotplug_event
   Cyclomatic Complexity 2 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fbdev_cma_set_suspend
   Cyclomatic Complexity 2 
drivers/gpu/drm/drm_fb_cma_helper.c:drm_fbdev_cma_set_suspend_unlocked
   drivers/gpu/drm/drm_fb_cma_helper.c: In function 'drm_fbdev_cma_init':
>> drivers/gpu/drm/drm_fb_cma_helper.c:197:2: warning: 'client' may be used 
>> uninitialized in this function [-Wmaybe-uninitialized]
 drm_client_release(client);
 ^~

vim +/client +197 drivers/gpu/drm/drm_fb_cma_helper.c

   162  
   163  /**
   164   * drm_fbdev_cma_init() - Allocate and initializes a drm_fbdev_cma 
struct
   165   * @dev: DRM device
   166   * @preferred_bpp: Preferred bits per pixel for the device
   167   * @max_conn_count: Maximum number of connectors
   168   *
   169   * Returns a newly allocated drm_fbdev_cma struct or a ERR_PTR.
   170   */
   171  struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev,
   172  unsigned int preferred_bpp, unsigned int max_conn_count)
   173  {
   174  struct drm_fbdev_cma *fbdev_cma;
   175  struct drm_fb_helper *fb_helper;
   176  struct drm_client_dev *client;
   177  int ret;
   178  
   179  fbdev_cma = kzalloc(sizeof(*fbdev_cma), GFP_KERNEL);
   180  if (!fbdev_cma)
   181  return ERR_PTR(-ENOMEM);
   182  
   183  fb_helper = _cma->fb_helper;
   184  
   185  ret = drm_client_new(dev, _helper->client, "fbdev");
   186  if (ret)
   187  goto err_free;
   188  
   189  ret = drm_fb_helper_fbdev_setup(dev, fb_helper, 
_fb_cma_helper_funcs,
   190  preferred_bpp, max_conn_count);
   191  if (ret)
   192  goto err_client_put;
   193  
   194  return fbdev_cma;
   195  
   196  err_client_put:
 > 197  drm_client_release(client);
   198  err_free:
   199  kfree(fbdev_cma);
   200  
   201  return ERR_PTR(ret);
   202  }
   203  EXPORT_SYMBOL_GPL(drm_fbdev_cma_init);
   204  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
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[Intel-gfx] [PATCH i-g-t 2/5] igt/gem_ctx_switch: Exercise queues

[Chris Wilson]

Queues are a form of contexts that share vm and enfore a single timeline
across all engines. Test switching between them, just like ordinary
contexts.

Signed-off-by: Chris Wilson 
---
 tests/gem_ctx_switch.c | 75 +++---
 1 file changed, 55 insertions(+), 20 deletions(-)

diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index 766ff9ae9..6770e001f 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -43,7 +43,8 @@
 #define LOCAL_I915_EXEC_NO_RELOC (1<<11)
 #define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
 
-#define INTERRUPTIBLE 1
+#define INTERRUPTIBLE 0x1
+#define QUEUE 0x2
 
 static double elapsed(const struct timespec *start, const struct timespec *end)
 {
@@ -97,8 +98,12 @@ static void single(int fd, uint32_t handle,
 
gem_require_ring(fd, e->exec_id | e->flags);
 
-   for (n = 0; n < 64; n++)
-   contexts[n] = gem_context_create(fd);
+   for (n = 0; n < 64; n++) {
+   if (flags & QUEUE)
+   contexts[n] = gem_queue_create(fd);
+   else
+   contexts[n] = gem_context_create(fd);
+   }
 
memset(, 0, sizeof(obj));
obj.handle = handle;
@@ -183,8 +188,12 @@ static void all(int fd, uint32_t handle, unsigned flags, 
int timeout)
}
igt_require(nengine);
 
-   for (n = 0; n < ARRAY_SIZE(contexts); n++)
-   contexts[n] = gem_context_create(fd);
+   for (n = 0; n < ARRAY_SIZE(contexts); n++) {
+   if (flags & QUEUE)
+   contexts[n] = gem_queue_create(fd);
+   else
+   contexts[n] = gem_context_create(fd);
+   }
 
memset(obj, 0, sizeof(obj));
obj[1].handle = handle;
@@ -248,6 +257,17 @@ igt_main
 {
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
const struct intel_execution_engine *e;
+   static const struct {
+   const char *name;
+   unsigned int flags;
+   bool (*require)(int fd);
+   } phases[] = {
+   { "", 0, NULL },
+   { "-interruptible", INTERRUPTIBLE, NULL },
+   { "-queue", QUEUE, gem_has_queues },
+   { "-queue-interruptible", QUEUE | INTERRUPTIBLE, gem_has_queues 
},
+   { }
+   };
uint32_t light = 0, heavy;
int fd = -1;
 
@@ -269,21 +289,26 @@ igt_main
}
 
for (e = intel_execution_engines; e->name; e++) {
-   igt_subtest_f("%s%s", e->exec_id == 0 ? "basic-" : "", e->name)
-   single(fd, light, e, 0, 1, 5);
-
-   igt_skip_on_simulation();
-
-   igt_subtest_f("%s%s-heavy", e->exec_id == 0 ? "basic-" : "", 
e->name)
-   single(fd, heavy, e, 0, 1, 5);
-   igt_subtest_f("%s-interruptible", e->name)
-   single(fd, light, e, INTERRUPTIBLE, 1, 150);
-   igt_subtest_f("forked-%s", e->name)
-   single(fd, light, e, 0, ncpus, 150);
-   igt_subtest_f("forked-%s-heavy", e->name)
-   single(fd, heavy, e, 0, ncpus, 150);
-   igt_subtest_f("forked-%s-interruptible", e->name)
-   single(fd, light, e, INTERRUPTIBLE, ncpus, 150);
+   for (typeof(*phases) *p = phases; p->name; p++) {
+   igt_subtest_group {
+   igt_fixture {
+   if (p->require)
+   igt_require(p->require);
+   }
+
+   igt_subtest_f("%s%s%s", e->exec_id == 0 ? 
"basic-" : "", e->name, p->name)
+   single(fd, light, e, p->flags, 1, 5);
+
+   igt_skip_on_simulation();
+
+   igt_subtest_f("%s%s-heavy%s", e->exec_id == 0 ? 
"basic-" : "", e->name, p->name)
+   single(fd, heavy, e, p->flags, 1, 5);
+   igt_subtest_f("forked-%s%s", e->name, p->name)
+   single(fd, light, e, p->flags, ncpus, 
150);
+   igt_subtest_f("forked-%s-heavy%s", e->name, 
p->name)
+   single(fd, heavy, e, p->flags, ncpus, 
150);
+   }
+   }
}
 
igt_subtest("basic-all-light")
@@ -291,6 +316,16 @@ igt_main
igt_subtest("basic-all-heavy")
all(fd, heavy, 0, 5);
 
+   igt_subtest_group {
+   igt_fixture {
+   igt_require(gem_has_queues(fd));
+   }
+   igt_subtest("basic-queue-light")
+   all(fd, light, QUEUE, 5);
+   igt_subtest("basic-queue-heavy")
+   all(fd, heavy, QUEUE, 5);
+   }
+
igt_fixture {

[Intel-gfx] [PATCH i-g-t 3/5] igt/gem_exec_whisper: Fork all-engine tests one-per-engine

[Chris Wilson]

Add a new mode for some more stress, submit the all-engines tests
simultaneously, a stream per engine.

Signed-off-by: Chris Wilson 
---
 tests/gem_exec_whisper.c | 27 ++-
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/tests/gem_exec_whisper.c b/tests/gem_exec_whisper.c
index a41614a7b..d35807e30 100644
--- a/tests/gem_exec_whisper.c
+++ b/tests/gem_exec_whisper.c
@@ -88,6 +88,7 @@ static void verify_reloc(int fd, uint32_t handle,
 #define SYNC 0x40
 #define PRIORITY 0x80
 #define QUEUES 0x100
+#define ALL 0x200
 
 struct hang {
struct drm_i915_gem_exec_object2 obj;
@@ -197,6 +198,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
unsigned int eb_migrations = 0;
uint64_t old_offset;
int debugfs;
+   int nchild;
 
if (flags & PRIORITY) {
igt_require(gem_scheduler_enabled(fd));
@@ -212,6 +214,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
engines[nengine++] = engine;
}
} else {
+   igt_assert(!(flags & ALL));
igt_require(gem_has_ring(fd, engine));
igt_require(gem_can_store_dword(fd, engine));
engines[nengine++] = engine;
@@ -230,8 +233,19 @@ static void whisper(int fd, unsigned engine, unsigned 
flags)
if (flags & HANG)
init_hang();
 
+   nchild = 1;
+   if (flags & FORKED)
+   nchild *= sysconf(_SC_NPROCESSORS_ONLN);
+   if (flags & ALL)
+   nchild *= nengine;
+
intel_detect_and_clear_missed_interrupts(fd);
-   igt_fork(child, flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1)  {
+   igt_fork(child, nchild) {
+   if (flags & ALL) {
+   engines[0] = engines[child % nengine];
+   nengine = 1;
+   }
+
memset(, 0, sizeof(scratch));
scratch.handle = gem_create(fd, 4096);
scratch.flags = EXEC_OBJECT_WRITE;
@@ -334,7 +348,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
for (pass = 0; pass < 1024; pass++) {
uint64_t offset;
 
-   if (!(flags & FORKED))
+   if (nchild == 1)
write_seqno(debugfs, pass);
 
if (flags & HANG)
@@ -375,8 +389,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 
gem_write(fd, batches[1023].handle, loc, , 
sizeof(pass));
for (n = 1024; --n >= 1; ) {
+   uint32_t handle[2] = {};
int this_fd = fd;
-   uint32_t handle[2];
 
execbuf.buffers_ptr = 
to_user_pointer([n-1]);
reloc_migrations += batches[n-1].offset 
!= inter[n].presumed_offset;
@@ -535,7 +549,7 @@ igt_main
{ "queues-sync", QUEUES | SYNC },
{ NULL }
};
-   int fd;
+   int fd = -1;
 
igt_fixture {
fd = drm_open_driver_master(DRIVER_INTEL);
@@ -546,9 +560,12 @@ igt_main
igt_fork_hang_detector(fd);
}
 
-   for (const struct mode *m = modes; m->name; m++)
+   for (const struct mode *m = modes; m->name; m++) {
igt_subtest_f("%s", m->name)
whisper(fd, ALL_ENGINES, m->flags);
+   igt_subtest_f("%s-all", m->name)
+   whisper(fd, ALL_ENGINES, m->flags | ALL);
+   }
 
for (const struct intel_execution_engine *e = intel_execution_engines;
 e->name; e++) {
-- 
2.18.0

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[Intel-gfx] [PATCH i-g-t 1/5] igt: Exercise creating context with shared GTT

[Chris Wilson]

v2: Test each shared context is its own timeline and allows request
reordering between shared contexts.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Michal Wajdeczko 
---
 lib/i915/gem_context.c   |  66 +++
 lib/i915/gem_context.h   |  13 +
 tests/Makefile.sources   |   1 +
 tests/gem_ctx_shared.c   | 896 +++
 tests/gem_exec_whisper.c |  32 +-
 5 files changed, 999 insertions(+), 9 deletions(-)
 create mode 100644 tests/gem_ctx_shared.c

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 669bd318c..02cf2ccf3 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -273,3 +273,69 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int 
prio)
 {
igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
 }
+
+struct local_i915_gem_context_create_v2 {
+   uint32_t ctx_id;
+   uint32_t flags;
+   uint32_t share_ctx;
+   uint32_t pad;
+};
+
+#define LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE   DRM_IOWR (DRM_COMMAND_BASE + 
DRM_I915_GEM_CONTEXT_CREATE, struct local_i915_gem_context_create_v2)
+
+int
+__gem_context_create_shared(int i915, uint32_t share, unsigned int flags,
+   uint32_t *out)
+{
+   struct local_i915_gem_context_create_v2 arg = {
+   .flags = flags,
+   .share_ctx = share,
+   };
+   int err = 0;
+
+   if (igt_ioctl(i915, LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE, ))
+   err = -errno;
+
+   *out = arg.ctx_id;
+
+   errno = 0;
+   return err;
+}
+
+static bool __gem_context_has(int i915, uint32_t flags)
+{
+   uint32_t ctx;
+
+   __gem_context_create_shared(i915, 0, flags, );
+   if (ctx)
+   gem_context_destroy(i915, ctx);
+
+   errno = 0;
+   return ctx;
+}
+
+bool gem_contexts_has_shared_gtt(int i915)
+{
+   return __gem_context_has(i915, I915_GEM_CONTEXT_SHARE_GTT);
+}
+
+bool gem_has_queues(int i915)
+{
+   return __gem_context_has(i915, I915_GEM_CONTEXT_SHARE_GTT);
+}
+
+uint32_t gem_context_create_shared(int i915, uint32_t share, unsigned int 
flags)
+{
+   uint32_t ctx;
+
+   igt_assert_eq(__gem_context_create_shared(i915, share, flags, ), 0);
+
+   return ctx;
+}
+
+uint32_t gem_queue_create(int i915)
+{
+   return gem_context_create_shared(i915, 0,
+I915_GEM_CONTEXT_SHARE_GTT |
+I915_GEM_CONTEXT_SINGLE_TIMELINE);
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6..5ed992a70 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -29,6 +29,19 @@ int __gem_context_create(int fd, uint32_t *ctx_id);
 void gem_context_destroy(int fd, uint32_t ctx_id);
 int __gem_context_destroy(int fd, uint32_t ctx_id);
 
+#define I915_GEM_CONTEXT_SHARE_GTT 0x1
+#define I915_GEM_CONTEXT_SINGLE_TIMELINE 0x2
+
+int __gem_context_create_shared(int i915,
+   uint32_t share, unsigned int flags,
+   uint32_t *out);
+uint32_t gem_context_create_shared(int i915,
+  uint32_t share, unsigned int flags);
+uint32_t gem_queue_create(int i915);
+
+bool gem_contexts_has_shared_gtt(int i915);
+bool gem_has_queues(int i915);
+
 bool gem_has_contexts(int fd);
 void gem_require_contexts(int fd);
 void gem_context_require_bannable(int fd);
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index ad62611fb..bd0bd5439 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -60,6 +60,7 @@ TESTS_progs = \
gem_ctx_exec \
gem_ctx_isolation \
gem_ctx_param \
+   gem_ctx_shared \
gem_ctx_switch \
gem_ctx_thrash \
gem_double_irq_loop \
diff --git a/tests/gem_ctx_shared.c b/tests/gem_ctx_shared.c
new file mode 100644
index 0..9d3239f69
--- /dev/null
+++ b/tests/gem_ctx_shared.c
@@ -0,0 +1,896 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * 

[Intel-gfx] [RFC PATCH] misc/mei/hdcp: mei_hdcp_component_registered can be static

[kbuild test robot]

Fixes: 0654edaa3690 ("misc/mei/hdcp: Component framework for I915 Interface")
Signed-off-by: kbuild test robot 
---
 mei_hdcp.c |8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index ba75502..146a4be 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -34,10 +34,10 @@
 #include 
 #include 
 
-bool mei_hdcp_component_registered;
+static bool mei_hdcp_component_registered;
 static struct mei_cl_device *mei_cldev;
 
-struct i915_hdcp_component_ops mei_hdcp_component_ops = {
+static struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner  = THIS_MODULE,
.initiate_hdcp2_session = NULL,
.verify_receiver_cert_prepare_km= NULL,
@@ -87,7 +87,7 @@ static const struct component_ops mei_hdcp_component_bind_ops 
= {
.unbind = mei_hdcp_component_unbind,
 };
 
-void mei_hdcp_component_init(struct device *dev)
+static void mei_hdcp_component_init(struct device *dev)
 {
int ret;
 
@@ -100,7 +100,7 @@ void mei_hdcp_component_init(struct device *dev)
mei_hdcp_component_registered = true;
 }
 
-void mei_hdcp_component_cleanup(struct device *dev)
+static void mei_hdcp_component_cleanup(struct device *dev)
 {
if (!mei_hdcp_component_registered)
return;
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Re: [Intel-gfx] [PATCH v5 28/40] misc/mei/hdcp: Component framework for I915 Interface

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20180627]
[cannot apply to v4.18-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180627-174219
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/misc/mei/hdcp/mei_hdcp.c:37:6: sparse: symbol 
>> 'mei_hdcp_component_registered' was not declared. Should it be static?
>> drivers/misc/mei/hdcp/mei_hdcp.c:40:32: sparse: symbol 
>> 'mei_hdcp_component_ops' was not declared. Should it be static?
>> drivers/misc/mei/hdcp/mei_hdcp.c:90:6: sparse: symbol 
>> 'mei_hdcp_component_init' was not declared. Should it be static?
>> drivers/misc/mei/hdcp/mei_hdcp.c:103:6: sparse: symbol 
>> 'mei_hdcp_component_cleanup' was not declared. Should it be static?

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation
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[Intel-gfx] [PATCH 10/10] Revert "drm: crc: Wait for a frame before returning from open()"

[Mahesh Kumar]

This reverts commit e8fa5671183c80342d520ad81d14fa79a9d4a680.

Don't wait for first CRC during crtc_crc_open. It avoids one frame wait
during open. If application want to wait after read call, it can use
poll/read blocking read() call.

Suggested-by: Ville Syrjälä 
Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
Cc: Tomeu Vizoso 
---
 drivers/gpu/drm/drm_debugfs_crc.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
b/drivers/gpu/drm/drm_debugfs_crc.c
index 08dfe19b6286..7aeed89f934a 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -226,24 +226,8 @@ static int crtc_crc_open(struct inode *inode, struct file 
*filep)
if (ret)
goto err;
 
-   spin_lock_irq(>lock);
-   /*
-* Only return once we got a first frame, so userspace doesn't have to
-* guess when this particular piece of HW will be ready to start
-* generating CRCs.
-*/
-   ret = wait_event_interruptible_lock_irq(crc->wq,
-   crtc_crc_data_count(crc),
-   crc->lock);
-   spin_unlock_irq(>lock);
-
-   if (ret)
-   goto err_disable;
-
return 0;
 
-err_disable:
-   crtc->funcs->set_crc_source(crtc, NULL);
 err:
spin_lock_irq(>lock);
crtc_crc_cleanup(crc);
-- 
2.16.2

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[Intel-gfx] [PATCH 03/10] drm: crc: Introduce get_crc_sources callback

[Mahesh Kumar]

This patch implements a callback function "get_crc_sources" which
will be called during read of control node. It is an optional
callback function and if driver implements this callback, driver
should print list of available CRC sources in seq_file privided
as an input to the callback.

Changes Since V1: (Daniel)
 - return const pointer to an array of crc sources list
 - do validation of sources in CRC-core

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_debugfs_crc.c | 20 +++-
 include/drm/drm_crtc.h| 16 
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
b/drivers/gpu/drm/drm_debugfs_crc.c
index 2b4a737c5aeb..a7b6d5de81de 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -67,9 +67,27 @@
 static int crc_control_show(struct seq_file *m, void *data)
 {
struct drm_crtc *crtc = m->private;
+   size_t count;
+
+   if (crtc->funcs->get_crc_sources) {
+   const char *const *sources = crtc->funcs->get_crc_sources(crtc,
+   );
+   size_t values_cnt;
+   int i;
+
+   if (count <= 0 || !sources)
+   goto out;
+
+   seq_puts(m, "[");
+   for (i = 0; i < count; i++)
+   if (!crtc->funcs->verify_crc_source(crtc, sources[i],
+   _cnt))
+   seq_printf(m, "%s ", sources[i]);
+   seq_puts(m, "] ");
+   }
 
+out:
seq_printf(m, "%s\n", crtc->crc.source);
-
return 0;
 }
 
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index bae432469616..594326664abe 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -690,6 +690,22 @@ struct drm_crtc_funcs {
 * 0 on success or a negative error code on failure.
 */
int (*pre_crc_read)(struct drm_crtc *crtc);
+   /**
+* @get_crc_sources:
+*
+* Driver callback for getting a list of all the available sources for
+* CRC generation.
+*
+* This callback is optional if the driver does not support exporting of
+* possible CRC sources list. CRC-core does the verification of sources.
+*
+* RETURNS:
+*
+* a constant character pointer to the list of all the available CRC
+* sources
+*/
+   const char *const *(*get_crc_sources)(struct drm_crtc *crtc,
+ size_t *count);
 
/**
 * @atomic_print_state:
-- 
2.16.2

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[Intel-gfx] [PATCH 06/10] drm/rcar-du/crc: Implement verify_crc_source callback

[Mahesh Kumar]

This patch implements "verify_crc_source" callback function for
rcar drm driver.

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 40 ++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c 
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 15dc9caa128b..24eeaa7e14d7 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -756,6 +756,45 @@ static void rcar_du_crtc_disable_vblank(struct drm_crtc 
*crtc)
rcrtc->vblank_enable = false;
 }
 
+static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
+ const char *source_name,
+ size_t *values_cnt)
+{
+   struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+   unsigned int index = 0;
+   unsigned int i;
+   int ret;
+
+   /*
+* Parse the source name. Supported values are "plane%u" to compute the
+* CRC on an input plane (%u is the plane ID), and "auto" to compute the
+* CRC on the composer (VSP) output.
+*/
+   if (!source_name || !strcmp(source_name, "auto")) {
+   goto out;
+   } else if (strstarts(source_name, "plane")) {
+   ret = kstrtouint(source_name + strlen("plane"), 10, );
+   if (ret < 0)
+   return ret;
+
+   for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
+   if (index == rcrtc->vsp->planes[i].plane.base.id) {
+   index = i;
+   break;
+   }
+   }
+
+   if (i >= rcrtc->vsp->num_planes)
+   return -EINVAL;
+   } else {
+   return -EINVAL;
+   }
+
+out:
+   *values_cnt = 1;
+   return 0;
+}
+
 static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
   const char *source_name,
   size_t *values_cnt)
@@ -861,6 +900,7 @@ static const struct drm_crtc_funcs crtc_funcs_gen3 = {
.enable_vblank = rcar_du_crtc_enable_vblank,
.disable_vblank = rcar_du_crtc_disable_vblank,
.set_crc_source = rcar_du_crtc_set_crc_source,
+   .verify_crc_source = rcar_du_crtc_verify_crc_source,
 };
 
 /* 
-
-- 
2.16.2

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[Intel-gfx] [PATCH 04/10] drm/rockchip/crc: Implement verify_crc_source callback

[Mahesh Kumar]

This patch implements "verify_crc_source" callback function for
rockchip drm driver.

Changes since V1:
 - simplify the verification (Jani N)

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index effecbed2d11..77e91b15ddb4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1138,12 +1138,31 @@ static int vop_crtc_set_crc_source(struct drm_crtc 
*crtc,
 
return ret;
 }
+
+static int
+vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
+  size_t *values_cnt)
+{
+   if (source_name && strcmp(source_name, "auto") != 0)
+   return -EINVAL;
+
+   *values_cnt = 3;
+   return 0;
+}
+
 #else
 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
   const char *source_name, size_t *values_cnt)
 {
return -ENODEV;
 }
+
+static int
+vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
+  size_t *values_cnt)
+{
+   return -ENODEV;
+}
 #endif
 
 static const struct drm_crtc_funcs vop_crtc_funcs = {
@@ -1156,6 +1175,7 @@ static const struct drm_crtc_funcs vop_crtc_funcs = {
.enable_vblank = vop_crtc_enable_vblank,
.disable_vblank = vop_crtc_disable_vblank,
.set_crc_source = vop_crtc_set_crc_source,
+   .verify_crc_source = vop_crtc_verify_crc_source,
 };
 
 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
-- 
2.16.2

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[Intel-gfx] [PATCH 09/10] drm/crc: Cleanup crtc_crc_open function

[Mahesh Kumar]

This patch make changes to allocate crc-entries buffer before
enabling CRC generation.
It moves all the failure check early in the function before setting
the source or memory allocation.
Now set_crc_source takes only two variable inputs, values_cnt we
already gets as part of verify_crc_source.

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |  3 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c  |  4 +-
 drivers/gpu/drm/drm_debugfs_crc.c  | 52 +-
 drivers/gpu/drm/i915/intel_drv.h   |  3 +-
 drivers/gpu/drm/i915/intel_pipe_crc.c  |  4 +-
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c |  5 +--
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|  6 +--
 include/drm/drm_crtc.h |  3 +-
 8 files changed, 30 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index e43ed064dc46..54056d180003 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -258,8 +258,7 @@ amdgpu_dm_remove_sink_from_freesync_module(struct 
drm_connector *connector);
 
 /* amdgpu_dm_crc.c */
 #ifdef CONFIG_DEBUG_FS
-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name,
- size_t *values_cnt);
+int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
 const char *src_name,
 size_t *values_cnt);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index dfcca594d52a..e7ad528f5853 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -62,8 +62,7 @@ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const 
char *src_name,
return 0;
 }
 
-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name,
-  size_t *values_cnt)
+int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
 {
struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
struct dc_stream_state *stream_state = crtc_state->stream;
@@ -99,7 +98,6 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, 
const char *src_name,
return -EINVAL;
}
 
-   *values_cnt = 3;
/* Reset crc_skipped on dm state */
crtc_state->crc_skip_count = 0;
return 0;
diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
b/drivers/gpu/drm/drm_debugfs_crc.c
index a7b6d5de81de..08dfe19b6286 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -124,11 +124,9 @@ static ssize_t crc_control_write(struct file *file, const 
char __user *ubuf,
if (source[len] == '\n')
source[len] = '\0';
 
-   if (crtc->funcs->verify_crc_source) {
-   ret = crtc->funcs->verify_crc_source(crtc, source, _cnt);
-   if (ret)
-   return ret;
-   }
+   ret = crtc->funcs->verify_crc_source(crtc, source, _cnt);
+   if (ret)
+   return ret;
 
spin_lock_irq(>lock);
 
@@ -193,12 +191,15 @@ static int crtc_crc_open(struct inode *inode, struct file 
*filep)
return ret;
}
 
-   if (crtc->funcs->verify_crc_source) {
-   ret = crtc->funcs->verify_crc_source(crtc, crc->source,
-_cnt);
-   if (ret)
-   return ret;
-   }
+   ret = crtc->funcs->verify_crc_source(crtc, crc->source, _cnt);
+   if (ret)
+   return ret;
+
+   if (WARN_ON(values_cnt > DRM_MAX_CRC_NR))
+   return -EINVAL;
+
+   if (WARN_ON(values_cnt == 0))
+   return -EINVAL;
 
spin_lock_irq(>lock);
if (!crc->opened)
@@ -210,30 +211,22 @@ static int crtc_crc_open(struct inode *inode, struct file 
*filep)
if (ret)
return ret;
 
-   ret = crtc->funcs->set_crc_source(crtc, crc->source, _cnt);
-   if (ret)
-   goto err;
-
-   if (WARN_ON(values_cnt > DRM_MAX_CRC_NR)) {
-   ret = -EINVAL;
-   goto err_disable;
-   }
-
-   if (WARN_ON(values_cnt == 0)) {
-   ret = -EINVAL;
-   goto err_disable;
-   }
-
entries = kcalloc(DRM_CRC_ENTRIES_NR, sizeof(*entries), GFP_KERNEL);
if (!entries) {
ret = -ENOMEM;
-   goto err_disable;
+   goto err;
}
 
spin_lock_irq(>lock);
crc->entries = entries;
crc->values_cnt = values_cnt;
+   

[Intel-gfx] [PATCH 08/10] drm/i915/crc: implement get_crc_sources callback

[Mahesh Kumar]

This patch implements get_crc_sources callback, which returns list of
all the valid crc sources supported by driver in current platform.

Changes since V1:
 - Return array of crc sources

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/i915/intel_display.c  | 1 +
 drivers/gpu/drm/i915/intel_drv.h  | 3 +++
 drivers/gpu/drm/i915/intel_pipe_crc.c | 7 +++
 3 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 821754fb49f1..b7951b3587e5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12894,6 +12894,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.atomic_destroy_state = intel_crtc_destroy_state,
.set_crc_source = intel_crtc_set_crc_source,
.verify_crc_source = intel_crtc_verify_crc_source,
+   .get_crc_sources = intel_crtc_get_crc_sources,
 };
 
 struct wait_rps_boost {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 764b53dfe7de..99e3b6477d39 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2158,11 +2158,14 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, 
const char *source_name,
  size_t *values_cnt);
 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
 const char *source_name, size_t *values_cnt);
+const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
+ size_t *count);
 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
 #else
 #define intel_crtc_set_crc_source NULL
 #define intel_crtc_verify_crc_source NULL
+#define intel_crtc_get_crc_sources NULL
 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
 {
 }
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c 
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index a37521380f94..1dffc346f1bc 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -1001,6 +1001,13 @@ intel_is_valid_crc_source(struct drm_i915_private 
*dev_priv,
return ivb_crc_source_valid(dev_priv, source);
 }
 
+const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
+ size_t *count)
+{
+   *count = ARRAY_SIZE(pipe_crc_sources);
+   return pipe_crc_sources;
+}
+
 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char 
*source_name,
 size_t *values_cnt)
 {
-- 
2.16.2

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[Intel-gfx] [PATCH 05/10] drm/amdgpu_dm/crc: Implement verify_crc_source callback

[Mahesh Kumar]

This patch implements "verify_crc_source" callback function for
AMD drm driver.

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  4 
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 16 
 3 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 655950102827..b2f357cb8f7f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2563,6 +2563,7 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = 
{
.atomic_duplicate_state = dm_crtc_duplicate_state,
.atomic_destroy_state = dm_crtc_destroy_state,
.set_crc_source = amdgpu_dm_crtc_set_crc_source,
+   .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
.enable_vblank = dm_enable_vblank,
.disable_vblank = dm_disable_vblank,
 };
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index a29dc35954c9..e43ed064dc46 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -260,9 +260,13 @@ amdgpu_dm_remove_sink_from_freesync_module(struct 
drm_connector *connector);
 #ifdef CONFIG_DEBUG_FS
 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name,
  size_t *values_cnt);
+int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
+const char *src_name,
+size_t *values_cnt);
 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
 #else
 #define amdgpu_dm_crtc_set_crc_source NULL
+#define amdgpu_dm_crtc_verify_crc_source NULL
 #define amdgpu_dm_crtc_handle_crc_irq(x)
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 52f2c01349e3..dfcca594d52a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -46,6 +46,22 @@ static enum amdgpu_dm_pipe_crc_source 
dm_parse_crc_source(const char *source)
return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
 }
 
+int
+amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
+size_t *values_cnt)
+{
+   enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
+
+   if (source < 0) {
+   DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
+src_name, crtc->index);
+   return -EINVAL;
+   }
+
+   *values_cnt = 3;
+   return 0;
+}
+
 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name,
   size_t *values_cnt)
 {
-- 
2.16.2

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[Intel-gfx] [PATCH 07/10] drm/i915/crc: implement verify_crc_source callback

[Mahesh Kumar]

This patch implements verify_crc_source callback function introduced
earlier in this series.

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/i915/intel_display.c  |   1 +
 drivers/gpu/drm/i915/intel_drv.h  |   3 +
 drivers/gpu/drm/i915/intel_pipe_crc.c | 108 ++
 3 files changed, 112 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index eaa0663963a5..821754fb49f1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12893,6 +12893,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.atomic_duplicate_state = intel_crtc_duplicate_state,
.atomic_destroy_state = intel_crtc_destroy_state,
.set_crc_source = intel_crtc_set_crc_source,
+   .verify_crc_source = intel_crtc_verify_crc_source,
 };
 
 struct wait_rps_boost {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a6ff2600a3a0..764b53dfe7de 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2156,10 +2156,13 @@ int intel_pipe_crc_create(struct drm_minor *minor);
 #ifdef CONFIG_DEBUG_FS
 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
  size_t *values_cnt);
+int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
+const char *source_name, size_t *values_cnt);
 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
 #else
 #define intel_crtc_set_crc_source NULL
+#define intel_crtc_verify_crc_source NULL
 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
 {
 }
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c 
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 39a4e4edda07..a37521380f94 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -913,6 +913,114 @@ int intel_pipe_crc_create(struct drm_minor *minor)
return 0;
 }
 
+static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
+const enum intel_pipe_crc_source source)
+{
+   switch (source) {
+   case INTEL_PIPE_CRC_SOURCE_PIPE:
+   case INTEL_PIPE_CRC_SOURCE_NONE:
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
+const enum intel_pipe_crc_source source)
+{
+   switch (source) {
+   case INTEL_PIPE_CRC_SOURCE_PIPE:
+   case INTEL_PIPE_CRC_SOURCE_TV:
+   case INTEL_PIPE_CRC_SOURCE_DP_B:
+   case INTEL_PIPE_CRC_SOURCE_DP_C:
+   case INTEL_PIPE_CRC_SOURCE_DP_D:
+   case INTEL_PIPE_CRC_SOURCE_NONE:
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
+   const enum intel_pipe_crc_source source)
+{
+   switch (source) {
+   case INTEL_PIPE_CRC_SOURCE_PIPE:
+   case INTEL_PIPE_CRC_SOURCE_DP_B:
+   case INTEL_PIPE_CRC_SOURCE_DP_C:
+   case INTEL_PIPE_CRC_SOURCE_DP_D:
+   case INTEL_PIPE_CRC_SOURCE_NONE:
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
+   const enum intel_pipe_crc_source source)
+{
+   switch (source) {
+   case INTEL_PIPE_CRC_SOURCE_PIPE:
+   case INTEL_PIPE_CRC_SOURCE_PLANE1:
+   case INTEL_PIPE_CRC_SOURCE_PLANE2:
+   case INTEL_PIPE_CRC_SOURCE_NONE:
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
+   const enum intel_pipe_crc_source source)
+{
+   switch (source) {
+   case INTEL_PIPE_CRC_SOURCE_PIPE:
+   case INTEL_PIPE_CRC_SOURCE_PLANE1:
+   case INTEL_PIPE_CRC_SOURCE_PLANE2:
+   case INTEL_PIPE_CRC_SOURCE_PF:
+   case INTEL_PIPE_CRC_SOURCE_NONE:
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+static int
+intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
+ const enum intel_pipe_crc_source source)
+{
+   if (IS_GEN2(dev_priv))
+   return i8xx_crc_source_valid(dev_priv, source);
+   else if (INTEL_GEN(dev_priv) < 5)
+   return i9xx_crc_source_valid(dev_priv, source);
+   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+   return vlv_crc_source_valid(dev_priv, source);
+   else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
+   return ilk_crc_source_valid(dev_priv, source);
+   else
+   return ivb_crc_source_valid(dev_priv, source);
+}
+
+int 

[Intel-gfx] [PATCH 00/10] Improve crc-core driver interface

[Mahesh Kumar]

This series improves crc-core <-> driver interface.
This series adds following functionality in the crc-core
 - Now control node will print all the available sources if
   implemented by driver along with current source.
 - Setting of sorce will fail if provided source is not supported
 - cleanup of crtc_crc_open function first allocate memory before
   enabling CRC generation
 - Don't block open() call instead wait in crc read call.

Following IGT will fail due to crc-core <-> driver interface change
igt@kms_pipe_crc_basic@bad-source 
ig@kms_pipe_crc_basic@nonblocking-crc-pipe-X 
ig@kms_pipe_crc_basic@nonblocking-crc-pipe-X-frame-sequence
In nonblocking crc tests we'll get lesser crc's due to skipping crc

AMD/Rockchip/rcar code path is not validated and need inputs

Changes:
 - Add dri-devel in Cc
Changes rev2:
 - now get_crc_sources returns a constant pointer to an array of
   source list and crc-core does the verification

Cc: dri-de...@lists.freedesktop.org

Mahesh Kumar (10):
  drm: crc: Introduce verify_crc_source callback
  drm: crc: Introduce pre_crc_read function
  drm: crc: Introduce get_crc_sources callback
  drm/rockchip/crc: Implement verify_crc_source callback
  drm/amdgpu_dm/crc: Implement verify_crc_source callback
  drm/rcar-du/crc: Implement verify_crc_source callback
  drm/i915/crc: implement verify_crc_source callback
  drm/i915/crc: implement get_crc_sources callback
  drm/crc: Cleanup crtc_crc_open function
  Revert "drm: crc: Wait for a frame before returning from open()"

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |   7 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c  |  20 +++-
 drivers/gpu/drm/drm_debugfs_crc.c  |  78 --
 drivers/gpu/drm/i915/intel_display.c   |   2 +
 drivers/gpu/drm/i915/intel_drv.h   |   8 +-
 drivers/gpu/drm/i915/intel_pipe_crc.c  | 118 -
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c |  45 +++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|  26 -
 include/drm/drm_crtc.h |  47 +++-
 10 files changed, 301 insertions(+), 51 deletions(-)

-- 
2.16.2

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[Intel-gfx] [PATCH 01/10] drm: crc: Introduce verify_crc_source callback

[Mahesh Kumar]

This patch adds a new callback function "verify_crc_source" which will
be used during setting the crc source in control node and while opening
data node for crc reading. This will help in avoiding setting of wrong
string for source.

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_debugfs_crc.c | 15 +++
 include/drm/drm_crtc.h| 15 +++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
b/drivers/gpu/drm/drm_debugfs_crc.c
index 9f8312137cad..c6a725b79ac6 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -87,6 +87,8 @@ static ssize_t crc_control_write(struct file *file, const 
char __user *ubuf,
struct drm_crtc *crtc = m->private;
struct drm_crtc_crc *crc = >crc;
char *source;
+   size_t values_cnt;
+   int ret = 0;
 
if (len == 0)
return 0;
@@ -104,6 +106,12 @@ static ssize_t crc_control_write(struct file *file, const 
char __user *ubuf,
if (source[len] == '\n')
source[len] = '\0';
 
+   if (crtc->funcs->verify_crc_source) {
+   ret = crtc->funcs->verify_crc_source(crtc, source, _cnt);
+   if (ret)
+   return ret;
+   }
+
spin_lock_irq(>lock);
 
if (crc->opened) {
@@ -167,6 +175,13 @@ static int crtc_crc_open(struct inode *inode, struct file 
*filep)
return ret;
}
 
+   if (crtc->funcs->verify_crc_source) {
+   ret = crtc->funcs->verify_crc_source(crtc, crc->source,
+_cnt);
+   if (ret)
+   return ret;
+   }
+
spin_lock_irq(>lock);
if (!crc->opened)
crc->opened = true;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 23eddbccab10..1a6dcbf91744 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -661,6 +661,21 @@ struct drm_crtc_funcs {
 */
int (*set_crc_source)(struct drm_crtc *crtc, const char *source,
  size_t *values_cnt);
+   /**
+* @verify_crc_source:
+*
+* verifies the source of CRC checksums of frames before setting the
+* source for CRC and during crc open.
+*
+* This callback is optional if the driver does not support any CRC
+* generation functionality.
+*
+* RETURNS:
+*
+* 0 on success or a negative error code on failure.
+*/
+   int (*verify_crc_source)(struct drm_crtc *crtc, const char *source,
+size_t *values_cnt);
 
/**
 * @atomic_print_state:
-- 
2.16.2

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[Intel-gfx] [PATCH 02/10] drm: crc: Introduce pre_crc_read function

[Mahesh Kumar]

This patch implements a callback function "pre_crc_read" which will
be called before crc read. In this function driver can implement and
preparation work required for successfully reading CRC data.

Signed-off-by: Mahesh Kumar 
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/drm_debugfs_crc.c |  8 
 include/drm/drm_crtc.h| 14 ++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/drm_debugfs_crc.c 
b/drivers/gpu/drm/drm_debugfs_crc.c
index c6a725b79ac6..2b4a737c5aeb 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -278,6 +278,14 @@ static ssize_t crtc_crc_read(struct file *filep, char 
__user *user_buf,
return 0;
}
 
+   if (crtc->funcs->pre_crc_read) {
+   ret = crtc->funcs->pre_crc_read(crtc);
+   if (ret) {
+   spin_unlock_irq(>lock);
+   return ret;
+   }
+   }
+
/* Nothing to read? */
while (crtc_crc_data_count(crc) == 0) {
if (filep->f_flags & O_NONBLOCK) {
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 1a6dcbf91744..bae432469616 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -676,6 +676,20 @@ struct drm_crtc_funcs {
 */
int (*verify_crc_source)(struct drm_crtc *crtc, const char *source,
 size_t *values_cnt);
+   /**
+* @pre_crc_read:
+*
+* Driver callback for performing any preparation work required by
+* driver before reading CRC
+*
+* This callback is optional if the driver does not support CRC
+* generation or no prework is required before reading the crc
+*
+* RETURNS:
+*
+* 0 on success or a negative error code on failure.
+*/
+   int (*pre_crc_read)(struct drm_crtc *crtc);
 
/**
 * @atomic_print_state:
-- 
2.16.2

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[Intel-gfx] [PATCH] drm/i915: encourage BIT() macro usage in register definitions

[Jani Nikula]

There's already some BIT() usage here and there, embrace it.

Cc: Paulo Zanoni 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_reg.h | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 476118f46cf3..64b9c270045d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -65,9 +65,10 @@
  * but do note that the macros may be needed to read as well as write the
  * register contents.
  *
- * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
- * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
- * to the name.
+ * Define bits using ``BIT(N)`` instead of ``(1 << N)``. Do **not** add 
``_BIT``
+ * suffix to the name. Exception to ``BIT()`` usage: Value 1 for a bit field
+ * should be defined using ``(1 << N)`` to be in line with other values such as
+ * ``(2 << N)`` for the same field.
  *
  * Group the register and its contents together without blank lines, separate
  * from other registers and their contents with one blank line.
@@ -105,7 +106,7 @@
  *  #define _FOO_A  0xf000
  *  #define _FOO_B  0xf001
  *  #define FOO(pipe)   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
- *  #define   FOO_ENABLE(1 << 31)
+ *  #define   FOO_ENABLEBIT(31)
  *  #define   FOO_MODE_MASK (0xf << 16)
  *  #define   FOO_MODE_SHIFT16
  *  #define   FOO_MODE_BAR  (0 << 16)
-- 
2.11.0

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Re: [Intel-gfx] [PATCH v5 16/40] drm/i915: Implement HDCP2.2 repeater authentication

[kbuild test robot]

Hi Ramalingam,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.18-rc2 next-20180627]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180627-174219
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

   drivers/gpu/drm/i915/i915_drv.h:3674:16: sparse: expression using 
sizeof(void)
>> drivers/gpu/drm/i915/intel_hdcp.c:1451:30: sparse: incorrect type in 
>> assignment (different base types) @@expected restricted __be16 
>> [assigned] [usertype] k @@got e] k @@
   drivers/gpu/drm/i915/intel_hdcp.c:1451:30:expected restricted __be16 
[assigned] [usertype] k
   drivers/gpu/drm/i915/intel_hdcp.c:1451:30:got int
   drivers/gpu/drm/i915/intel_hdcp.c:1890:6: sparse: symbol 
'is_hdcp2_supported' was not declared. Should it be static?

vim +1451 drivers/gpu/drm/i915/intel_hdcp.c

  1432  
  1433  static
  1434  int hdcp2_propagate_stream_management_info(struct intel_connector 
*connector)
  1435  {
  1436  struct intel_digital_port *intel_dig_port = 
conn_to_dig_port(connector);
  1437  struct intel_hdcp *hdcp = >hdcp;
  1438  union {
  1439  struct hdcp2_rep_stream_manage stream_manage;
  1440  struct hdcp2_rep_stream_ready stream_ready;
  1441  } msgs;
  1442  const struct intel_hdcp_shim *shim = hdcp->hdcp_shim;
  1443  int ret;
  1444  
  1445  /* Prepare RepeaterAuth_Stream_Manage msg */
  1446  msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
  1447  reverse_endianness(msgs.stream_manage.seq_num_m, 
HDCP_2_2_SEQ_NUM_LEN,
  1448 (u8 *)>seq_num_m);
  1449  
  1450  /* K no of streams is fixed as 1. Stored as big-endian. */
> 1451  msgs.stream_manage.k = __swab16(1);
  1452  
  1453  /* For HDMI this is forced to be 0x0. For DP SST also this is 
0x0. */
  1454  msgs.stream_manage.streams[0].stream_id = 0;
  1455  msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
  1456  
  1457  /* Send it to Repeater */
  1458  ret = shim->write_2_2_msg(intel_dig_port, _manage,
  1459sizeof(msgs.stream_manage));
  1460  if (ret < 0)
  1461  return ret;
  1462  
  1463  ret = shim->read_2_2_msg(intel_dig_port, 
HDCP_2_2_REP_STREAM_READY,
  1464   _ready, 
sizeof(msgs.stream_ready));
  1465  if (ret < 0)
  1466  return ret;
  1467  
  1468  hdcp->mei_data.seq_num_m = hdcp->seq_num_m;
  1469  hdcp->mei_data.streams[0].stream_type = hdcp->content_type;
  1470  
  1471  ret = hdcp2_verify_mprime(connector, _ready);
  1472  if (ret < 0)
  1473  return ret;
  1474  
  1475  hdcp->seq_num_m++;
  1476  
  1477  if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) {
  1478  DRM_DEBUG_KMS("seq_num_m roll over.\n");
  1479  return -1;
  1480  }
  1481  
  1482  return 0;
  1483  }
  1484  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation
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