[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
== Series Details == Series: drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register URL : https://patchwork.freedesktop.org/series/47520/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4600_full -> Patchwork_9828_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9828_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: shard-kbl: PASS -> DMESG-FAIL (fdo#106947, fdo#106560) igt@gem_ctx_isolation@vcs0-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105189) igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-glk: PASS -> FAIL (fdo#103375) Possible fixes igt@drv_suspend@shrink: shard-glk: FAIL (fdo#106886) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: shard-glk: FAIL (fdo#105312) -> PASS igt@kms_flip@wf_vblank-ts-check-interruptible: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@pm_rps@min-max-config-loaded: shard-apl: FAIL (fdo#102250) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105312 https://bugs.freedesktop.org/show_bug.cgi?id=105312 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4600 -> Patchwork_9828 CI_DRM_4600: 308427119c70d0aaa90433b05969a0317165b122 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9828: a28e77d4b74217285bd1e4f954063a59830e3a6c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9828/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
== Series Details ==
Series: drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
URL : https://patchwork.freedesktop.org/series/47520/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4600 -> Patchwork_9828 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47520/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9828 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107258, fdo#107175)
igt@drv_selftest@live_workarounds:
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-j4005: NOTRUN -> FAIL (fdo#100368)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-kbl-guc: DMESG-FAIL (fdo#106947) -> PASS
fi-skl-6260u: DMESG-FAIL (fdo#107174, fdo#106560) -> PASS
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-FAIL (fdo#106103, fdo#102614) -> PASS
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
fi-skl-6700k2: FAIL (fdo#103191) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (48 -> 45) ==
Additional (2): fi-skl-guc fi-glk-j4005
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-byt-clapper
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4600 -> Patchwork_9828
CI_DRM_4600: 308427119c70d0aaa90433b05969a0317165b122 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9828: a28e77d4b74217285bd1e4f954063a59830e3a6c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a28e77d4b742 drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9828/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
== Series Details ==
Series: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
URL : https://patchwork.freedesktop.org/series/47518/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4600_full -> Patchwork_9826_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9826_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9826_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_9826_full:
=== IGT changes ===
Warnings
igt@kms_atomic_transition@plane-all-transition-nonblocking:
shard-snb: PASS -> SKIP +2
== Known issues ==
Here are the changes found in Patchwork_9826_full that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_ctx_isolation@vcs0-s3:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
shard-kbl: PASS -> FAIL (fdo#103925)
igt@perf@polling:
shard-hsw: PASS -> FAIL (fdo#102252)
Possible fixes
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS
igt@kms_flip@basic-flip-vs-wf_vblank:
shard-glk: FAIL (fdo#105312) -> PASS
igt@kms_flip@dpms-vs-vblank-race:
shard-glk: FAIL (fdo#103060) -> PASS
igt@kms_flip@wf_vblank-ts-check-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
shard-kbl: FAIL (fdo#99912) -> PASS
Warnings
igt@drv_suspend@shrink:
shard-glk: FAIL (fdo#106886) -> INCOMPLETE (fdo#103359,
fdo#106886, k.org#198133)
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#105312 https://bugs.freedesktop.org/show_bug.cgi?id=105312
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4600 -> Patchwork_9826
CI_DRM_4600: 308427119c70d0aaa90433b05969a0317165b122 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9826: b12d368538105a81cc71815aeff6197064ae8a9c @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9826/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
== Series Details ==
Series: drm/i915/icl: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in
this hook
URL : https://patchwork.freedesktop.org/series/47519/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4600 -> Patchwork_9827 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9827 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9827, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47519/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9827:
=== IGT changes ===
Possible regressions
igt@gem_ringfill@basic-default-hang:
fi-elk-e7500: PASS -> DMESG-WARN
== Known issues ==
Here are the changes found in Patchwork_9827 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107175, fdo#107258)
igt@drv_selftest@live_hangcheck:
fi-bdw-5557u: PASS -> DMESG-FAIL (fdo#106560)
igt@drv_selftest@live_workarounds:
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-kbl-guc: DMESG-FAIL (fdo#106947) -> PASS
fi-skl-6260u: DMESG-FAIL (fdo#107174, fdo#106560) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-FAIL (fdo#106103, fdo#102614) -> PASS
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
fi-skl-6700k2: FAIL (fdo#103191) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (48 -> 45) ==
Additional (2): fi-skl-guc fi-glk-j4005
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-byt-clapper
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4600 -> Patchwork_9827
CI_DRM_4600: 308427119c70d0aaa90433b05969a0317165b122 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9827: e5529aa3662792da36e042b8676bcc5c227915f9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e5529aa36627 drm/i915/icl: Add pre_pll_enable hook for ICL and set DFLEXDPMLE
in this hook
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9827/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
We don't have proper watermark NV12 support on ICL due to differences
in how it should be implemented. In commit 234059da0f33
("drm/i915/icl: NV12 y-plane ddb is not in same plane") we avoided
writing the non-existent PLANE_NV12_BUF_CFG registers but we forgot to
also avoid them on the hardware state readout. While the code is still
not correct, at least now we can avoid unclaimed register error
messages when dealing with RGB formats, which makes CI happier.
Also add some FIXME comments in order to make it even more clear that
there's still work to do.
References: commit 234059da0f33 ("drm/i915/icl: NV12 y-plane ddb is
not in same plane")
Cc: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2531eb75bdce..04cef1369e8c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3909,7 +3909,12 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private
*dev_priv,
val & PLANE_CTL_ALPHA_MASK);
val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
- val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+ /*
+* FIXME: add proper NV12 support for ICL. Avoid reading unclaimed
+* registers for now.
+*/
+ if (INTEL_GEN(dev_priv) < 11)
+ val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
if (fourcc == DRM_FORMAT_NV12) {
skl_ddb_entry_init_from_hw(dev_priv,
@@ -4977,6 +4982,7 @@ static void skl_write_plane_wm(struct intel_crtc
*intel_crtc,
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
>plane[pipe][plane_id]);
+ /* FIXME: add proper NV12 support for ICL. */
if (INTEL_GEN(dev_priv) >= 11)
return skl_ddb_entry_write(dev_priv,
PLANE_BUF_CFG(pipe, plane_id),
--
2.14.4
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
In case of Legacy DP connector on TypeC port (C, D, E or F), the
flex IO DPMLE register is set to maximum number of lanes since
there is no muxing with other controllers in this case.
While in case of the TypeC connector, it is set to the lane count
obained from DFLEXDPSP register.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL and add this programming in that hook.
v3:
* Call intel_dp_max_common_lane_count that gets lane count
common between sink, source, fia
v2:
* Add pre pll enable hook and move dflexdpmle programming
to that hook (Animesh)
Cc: Jani Nikula
Cc: Animesh Manna
Cc: Anusha Srivatsa
Cc: Paulo Zanoni
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 18 ++
drivers/gpu/drm/i915/intel_dp.c | 20
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0adc043..eb00ac4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3193,6 +3193,22 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder
*encoder,
bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
}
+static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_connector_state *conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv,
+ intel_dig_port->base.port);
+
+ if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
+ return;
+
+ intel_dp_set_fia_lane_count(intel_dp);
+}
+
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -3709,6 +3725,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_encoder->enable = intel_enable_ddi;
if (IS_GEN9_LP(dev_priv))
intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
+ if (IS_ICELAKE(dev_priv))
+ intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
intel_encoder->pre_enable = intel_ddi_pre_enable;
intel_encoder->disable = intel_disable_ddi;
intel_encoder->post_disable = intel_ddi_post_disable;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 49a3149..6683cdc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2127,6 +2127,26 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
intel_dp->link_mst = link_mst;
}
+void intel_dp_set_fia_lane_count(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv,
+ intel_dig_port->base.port);
+ u8 lane_count = intel_dp_max_common_lane_count(intel_dp);
+ u32 val;
+
+ /* In case of legacy/static DP over Type-C port there is no muxing
+* with other controllers so this is set to max lane count.
+* In case of Type_C it is set to the DFLEXDPSP.DPX4TXLATC value.
+*/
+ val = I915_READ(PORT_TX_DFLEXDPMLE1);
+ val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
+ val |= DFLEXDPMLE1_DPMLETC(tc_port, lane_count);
+ I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
+}
+
static void intel_dp_prepare(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1ad7c11..d98cdb9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1676,6 +1676,7 @@ bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
void intel_dp_set_link_params(struct intel_dp *intel_dp,
int link_rate, uint8_t lane_count,
bool link_mst);
+void intel_dp_set_fia_lane_count(struct intel_dp *intel_dp);
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
int link_rate, uint8_t lane_count);
void intel_dp_start_link_train(struct intel_dp *intel_dp);
--
2.7.4
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
== Series Details ==
Series: drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
URL : https://patchwork.freedesktop.org/series/47518/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4600 -> Patchwork_9826 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47518/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9826 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107175, fdo#107258)
igt@drv_selftest@live_hangcheck:
fi-skl-6600u: PASS -> DMESG-FAIL (fdo#107174, fdo#106560)
igt@drv_selftest@live_workarounds:
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@gem_exec_suspend@basic-s3:
fi-snb-2600:PASS -> DMESG-WARN (fdo#102365)
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: PASS -> DMESG-WARN (fdo#105128, fdo#107139)
igt@kms_busy@basic-flip-b:
fi-kbl-r: PASS -> DMESG-WARN (fdo#105602)
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: PASS -> FAIL (fdo#104008)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-kbl-guc: DMESG-FAIL (fdo#106947) -> PASS
fi-skl-6260u: DMESG-FAIL (fdo#107174, fdo#106560) -> PASS
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-FAIL (fdo#106103, fdo#102614) -> PASS
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
fi-skl-6700k2: FAIL (fdo#103191) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (48 -> 45) ==
Additional (2): fi-skl-guc fi-glk-j4005
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-byt-clapper
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4600 -> Patchwork_9826
CI_DRM_4600: 308427119c70d0aaa90433b05969a0317165b122 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9826: b12d368538105a81cc71815aeff6197064ae8a9c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b12d36853810 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9826/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows
Unlike the other ports, TC ports are not available to use as soon as
we get a hotplug. The TC PHYs can be shared between multiple
controllers: display, USB, etc. As a result, handshaking through FIA
is required around connect and disconnect to cleanly transfer
ownership with the controller and set the type-C power state.
This patch implements the flow sequences described by our
specification. We opt to grab ownership of the ports as soon as we get
the hotplugs in order to simplify the interactions and avoid surprises
in the user space side. We may consider changing this in the future,
once we improve our testing capabilities on this area.
v2:
* This unifies the DP and HDMI patches so we can discuss everything
at once so people looking at random single patches can actually
understand the direction.
* I found out the spec was updated a while ago. There's a small
difference in the connect flow and the patch was updated for that.
* Our spec also now gives a good explanation on what is really
happening. As a result, comments were added.
* Add some more comments as requested by Rodrigo (Rodrigo).
BSpec: 21750, 4250.
Cc: Animesh Manna
Cc: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++
drivers/gpu/drm/i915/intel_dp.c | 110 +-
drivers/gpu/drm/i915/intel_hdmi.c | 11 ++--
3 files changed, 123 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 079c89da8831..bcf6ef75cffe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10753,4 +10753,10 @@ enum skl_power_gate {
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
+#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
+#define DP_PHY_MODE_STATUS_COMPLETED(tc_port)(1 << (tc_port))
+
+#define PORT_TX_DFLEXDPCSSS_MMIO(0x163894)
+#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fec21aa3db93..6a6ddc3a71e3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4818,6 +4818,104 @@ static void icl_update_tc_port_type(struct
drm_i915_private *dev_priv,
type_str);
}
+/*
+ * This function implements the first part of the Connect Flow described by our
+ * specification, Gen11 TypeC Programming chapter. The rest of the flow
(reading
+ * lanes, EDID, etc) is done as needed in the typical places.
+ *
+ * Unlike the other ports, type-C ports are not available to use as soon as we
+ * get a hotplug. The type-C PHYs can be shared between multiple controllers:
+ * display, USB, etc. As a result, handshaking through FIA is required around
+ * connect and disconnect to cleanly transfer ownership with the controller and
+ * set the type-C power state.
+ *
+ * We could opt to only do the connect flow when we actually try to use the AUX
+ * channels or do a modeset, then immediately run the disconnect flow after
+ * usage, but there are some implications on this for a dynamic environment:
+ * things may go away or change behind our backs. So for now our driver is
+ * always trying to acquire ownership of the controller as soon as it gets an
+ * interrupt (or polls state and sees a port is connected) and only gives it
+ * back when it sees a disconnect. Implementation of a more fine-grained model
+ * will require a lot of coordination with user space and thorough testing for
+ * the extra possible cases.
+ */
+static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *dig_port)
+{
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ u32 val;
+
+ if (dig_port->tc_type != TC_PORT_LEGACY &&
+ dig_port->tc_type != TC_PORT_TYPEC)
+ return true;
+
+ val = I915_READ(PORT_TX_DFLEXDPPMS);
+ if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
+ DRM_ERROR("DP PHY for TC port %d not ready\n", tc_port);
+ return false;
+ }
+
+ /*
+* This function may be called many times in a row without an HPD event
+* in between, so try to avoid the write when we can.
+*/
+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
+ val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
+ }
+
+ /*
+* Now we have to re-check the live state, in case the port recently
+* became disconnected. Not necessary for legacy mode.
+*/
+ if (dig_port->tc_type == TC_PORT_TYPEC &&
+ !(I915_READ(PORT_TX_DFLEXDPSP) &
Re: [Intel-gfx] [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Singh, Gaurav K
>; dri-de...@lists.freedesktop.org; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC
>parameters
>
>This patch adds inline functions and helpers for obtaining DP sink's supported
>DSC
>parameters like DSC sink support, eDP compressed BPP supported, maximum slice
>count supported by the sink devices, DSC line buffer bit depth supported on DP
>sink, DSC sink maximum color depth by parsing corresponding DPCD registers.
>
>v4:
>* Add helper to give line buf bit depth (Manasi)
>v3:
>* Use SLICE_CAP_2 for DP (Anusha)
>v2:
>* Add DSC sink support macro (Jani N)
>
>Cc: Gaurav K Singh
>Cc: dri-de...@lists.freedesktop.org
>Cc: Jani Nikula
>Cc: Ville Syrjala
>Cc: Anusha Srivatsa
>Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
>---
> drivers/gpu/drm/drm_dp_helper.c | 89
>+
> include/drm/drm_dp_helper.h | 30 ++
> 2 files changed, 119 insertions(+)
>
>diff --git a/drivers/gpu/drm/drm_dp_helper.c
>b/drivers/gpu/drm/drm_dp_helper.c index 0cccbcb..7dc61d1 100644
>--- a/drivers/gpu/drm/drm_dp_helper.c
>+++ b/drivers/gpu/drm/drm_dp_helper.c
>@@ -1336,3 +1336,92 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
>struct drm_dp_desc *desc,
> return 0;
> }
> EXPORT_SYMBOL(drm_dp_read_desc);
>+
>+/**
>+ * DRM DP Helpers for DSC
>+ */
>+u8 drm_dp_dsc_sink_max_slice_count(const u8
>dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>+ bool is_edp)
>+{
>+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
>+
>+ if (is_edp) {
>+ /* For eDP, register DSC_SLICE_CAPABILITIES_1
NIT : the actual register is DSC_SLICE_CAP_1
gives slice count
>*/
>+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
>+ return 4;
>+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
>+ return 2;
>+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
>+ return 1;
>+ } else {
>+ /* For DP, use values from DSC_SLICE_CAP_1 and
>DSC_SLICE_CAP2 */
^^^ DSC_SLICE_CAP_2
>+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 -
>DP_DSC_SUPPORT];
>+
>+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
>+ return 24;
>+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
>+ return 20;
>+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
>+ return 16;
>+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
>+ return 12;
>+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
>+ return 10;
>+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
>+ return 8;
>+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
>+ return 6;
>+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
>+ return 4;
>+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
>+ return 2;
>+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
>+ return 1;
>+ }
>+
>+ return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
>+
>+u8 drm_dp_dsc_sink_line_buf_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH -
>+DP_DSC_SUPPORT];
>+
>+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_9:
>+ return 9;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_10:
>+ return 10;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_11:
>+ return 11;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_12:
>+ return 12;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_13:
>+ return 13;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_14:
>+ return 14;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_15:
>+ return 15;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_16:
>+ return 16;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_8:
>+ return 8;
>+ }
>+
>+ return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
>+
>+u8 drm_dp_dsc_sink_max_color_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+ switch (dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP -
>DP_DSC_SUPPORT]) {
>+ case DP_DSC_12_BPC:
>+ return 12;
>+ case DP_DSC_10_BPC:
>+ return 10;
>+ case DP_DSC_8_BPC:
>+ return 8;
>+ }
>+ return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
>diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>eb0d86c..8c1dbca 100644
>--- a/include/drm/drm_dp_helper.h
>+++ b/include/drm/drm_dp_helper.h
>@@ -1064,6
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Drop stray clearing of rps->last_adj
== Series Details == Series: drm/i915: Drop stray clearing of rps->last_adj URL : https://patchwork.freedesktop.org/series/47513/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4599_full -> Patchwork_9822_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9822_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9822_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9822_full: === IGT changes === Warnings igt@kms_cursor_crc@cursor-128x128-onscreen: shard-snb: SKIP -> PASS +2 == Known issues == Here are the changes found in Patchwork_9822_full that come from known issues: === IGT changes === Issues hit igt@gem_ctx_isolation@vcs0-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105189) Possible fixes igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: shard-glk: FAIL (fdo#103928) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-kbl: FAIL (fdo#105363, fdo#102887) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-glk: FAIL (fdo#103375) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@pm_rps@min-max-config-loaded: shard-apl: FAIL (fdo#102250) -> PASS shard-glk: FAIL -> PASS fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4599 -> Patchwork_9822 CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9822: fe9a14be12bd52f5db858b6118dc191f4e98d5ca @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9822/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP
== Series Details == Series: Display Stream Compression enabling on eDP/DP URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Applying: drm/dp: Define payload size for DP SDP PPS packet Applying: drm/dsc: Define Display Stream Compression PPS infoframe Applying: drm/dsc: Define VESA Display Stream Compression Capabilities Applying: drm/dsc: Define Rate Control values that do not change over configurations Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Applying: drm/i915/dp: Compute DSC pipe config in atomic check Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Applying: drm/i915/dsc: Define & Compute VESA DSC params Applying: drm/i915/dsc: Compute Rate Control parameters for DSC Applying: drm/i915/dp: Enable/Disable DSC in DP Sink Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c). error: could not build fake ancestor Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Daniel
>Vetter ; Srivatsa, Anusha ;
>Singh, Gaurav K
>Subject: [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set
>on Hotplug/eDP Init
>
>DSC is supported on eDP starting GEN 10 display and on DP starting GEN 11.
>This patch implements the discovery phase of DSC. On hotplug, source reads the
>DSC DPCD register set (0x00060 - 0x006F) to read the decompression capabilities
>of the sink device.
A sentence telling that DSC on eDP is supported on Geminilake would be more
clear. In the code below, we check if it is gen10 or GLK. The commit message
speaks of DSC support only for Gen10+ for eDP and Gen 11+ for DP.
Implementation looks good.
>This entire block of registers is cached in intel_dp so that capability
>information
>can be used during DSC configuration phase during compute_config phase of the
>modeset.
>For eDP, this caching happens during the eDP initialization.
>This caching is done only for eDP and DP rev >= 1.4
>
>v5:
>* Fix the block comment (Gaurav)
>* Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha)
>v4:
>* Cache these only for Gen >= 11
>v3:
>* Remove the dsc_sink_support field in intel_dp (Jani N)
>v2:
>* Clear the cached registers on hotplug always (Jani N)
>* Combine the eDP and DP caching in same function (Jani N)
>
>Cc: Jani Nikula
>Cc: Ville Syrjala
>Cc: Daniel Vetter
>Cc: Anusha Srivatsa
>Cc: Gaurav K Singh
>Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
>---
> drivers/gpu/drm/i915/intel_dp.c | 32
>drivers/gpu/drm/i915/intel_drv.h | 1 +
> 2 files changed, 33 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 8e0e14b..afa4e2d 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -3877,6 +3877,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
> return intel_dp->dpcd[DP_DPCD_REV] != 0; }
>
>+static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) {
>+ /*
>+ *Clear the cached register set to avoid using stale values
>+ * for the sinks that do not support DSC.
>+ */
>+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
>+
>+ /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
>+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
>+ intel_dp->edp_dpcd[0] >= DP_EDP_14) {
>+ if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
>+ intel_dp->dsc_dpcd,
>+ sizeof(intel_dp->dsc_dpcd)) < 0)
>+ DRM_ERROR("Failed to read DPCD register 0x%x\n",
>+DP_DSC_SUPPORT);
>+
>+ DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
>+(int)sizeof(intel_dp->dsc_dpcd),
>+intel_dp->dsc_dpcd);
>+ }
>+}
>+
> static bool
> intel_edp_init_dpcd(struct intel_dp *intel_dp) { @@ -3953,6 +3976,10 @@
>intel_edp_init_dpcd(struct intel_dp *intel_dp)
>
> intel_dp_set_common_rates(intel_dp);
>
>+ /* Read the eDP DSC DPCD registers */
>+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>+ intel_dp_get_dsc_sink_cap(intel_dp);
>+
> return true;
> }
>
>@@ -4944,6 +4971,7 @@ intel_dp_long_pulse(struct intel_connector
>*connector)
>
> if (status == connector_status_disconnected) {
> memset(_dp->compliance, 0, sizeof(intel_dp-
>>compliance));
>+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
>
> if (intel_dp->is_mst) {
> DRM_DEBUG_KMS("MST device may have disappeared
>%d vs %d\n", @@ -4969,6 +4997,10 @@ intel_dp_long_pulse(struct
>intel_connector *connector)
>
> intel_dp_print_rates(intel_dp);
>
>+ /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
>+ if (INTEL_GEN(dev_priv) >= 11)
>+ intel_dp_get_dsc_sink_cap(intel_dp);
>+
> drm_dp_read_desc(_dp->aux, _dp->desc,
>drm_dp_is_branch(intel_dp->dpcd));
>
>diff --git a/drivers/gpu/drm/i915/intel_drv.h
>b/drivers/gpu/drm/i915/intel_drv.h
>index 99a5f5b..29abe7a 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -1070,6 +1070,7 @@ struct intel_dp {
> uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
>+ u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> /* source rates */
> int num_source_rates;
> const int *source_rates;
>--
>2.7.4
___
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Re: [Intel-gfx] [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
>-Original Message- >From: Navare, Manasi D >Sent: Tuesday, July 31, 2018 2:07 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D ; dri- >de...@lists.freedesktop.org; Jani Nikula ; Ville >Syrjala ; Srivatsa, Anusha >; Singh, Gaurav K >Subject: [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size >define and missing SHIFT > >This patch defines the DP DSC receiver capability size that gives total number >of >DP DSC DPCD registers. >This also adds a missing #defines for DP DSC support missed in the commit id >(ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") > >v3: >* MIN_SLICE_WIDTH = 2560 (Anusha) >* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 >v2: >* Add SHIFT define and DECOMPRESSION_EN define misse din prev patch ^^^ "missed in previous" >Cc: dri-de...@lists.freedesktop.org >Cc: Jani Nikula >Cc: Ville Syrjala >Cc: Anusha Srivatsa >Cc: Gaurav K Singh >Signed-off-by: Manasi Navare Other than the typo, the patch looks good. Checked with Spec. Reviewed-by: Anusha Srivatsa >--- > include/drm/drm_dp_helper.h | 6 ++ > 1 file changed, 6 insertions(+) > >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index >05cc31b..eb0d86c 100644 >--- a/include/drm/drm_dp_helper.h >+++ b/include/drm/drm_dp_helper.h >@@ -230,6 +230,8 @@ > #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ > > #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ >+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define >+DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 > > #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 > # define DP_DSC_RGB (1 << 0) >@@ -278,6 +280,8 @@ > # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) > > #define DP_DSC_MAX_SLICE_WIDTH 0x06C >+#define DP_DSC_MIN_SLICE_WIDTH_VALUE2560 >+#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 > > #define DP_DSC_SLICE_CAP_2 0x06D > # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) >@@ -476,6 +480,7 @@ > # define DP_AUX_FRAME_SYNC_VALID (1 << 0) > > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ >+# define DP_DECOMPRESSION_EN(1 << 0) > > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > # define DP_PSR_ENABLE(1 << 0) >@@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 >link_status[DP_LINK_STATUS_SI > > #define DP_BRANCH_OUI_HEADER_SIZE 0xc > #define DP_RECEIVER_CAP_SIZE 0xf >+#define DP_DSC_RECEIVER_CAP_SIZE0xf > #define EDP_PSR_RECEIVER_CAP_SIZE 2 > #define EDP_DISPLAY_CTL_CAP_SIZE 3 > >-- >2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
== Series Details == Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt URL : https://patchwork.freedesktop.org/series/47367/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4599_full -> Patchwork_9821_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9821_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9821_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9821_full: === IGT changes === Warnings igt@kms_cursor_crc@cursor-128x128-onscreen: shard-snb: SKIP -> PASS +2 igt@kms_plane_lowres@pipe-a-tiling-none: shard-snb: PASS -> SKIP +1 == Known issues == Here are the changes found in Patchwork_9821_full that come from known issues: === IGT changes === Issues hit igt@gem_ctx_isolation@vcs0-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_flip@plain-flip-ts-check: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@wf_vblank-ts-check-interruptible: shard-glk: PASS -> FAIL (fdo#103928) igt@perf@blocking: shard-hsw: PASS -> FAIL (fdo#102252) Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#103665, fdo#106023) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: shard-glk: FAIL (fdo#103928) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-kbl: FAIL (fdo#105363, fdo#102887) -> PASS igt@pm_rps@min-max-config-loaded: shard-apl: FAIL (fdo#102250) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4599 -> Patchwork_9821 CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9821: 3dfe5d390b1482b0326f6d9ee324206721c760e1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9821/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP
== Series Details == Series: Display Stream Compression enabling on eDP/DP URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Applying: drm/dp: Define payload size for DP SDP PPS packet Applying: drm/dsc: Define Display Stream Compression PPS infoframe Applying: drm/dsc: Define VESA Display Stream Compression Capabilities Applying: drm/dsc: Define Rate Control values that do not change over configurations Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Applying: drm/i915/dp: Compute DSC pipe config in atomic check Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Applying: drm/i915/dsc: Define & Compute VESA DSC params Applying: drm/i915/dsc: Compute Rate Control parameters for DSC Applying: drm/i915/dp: Enable/Disable DSC in DP Sink Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c). error: could not build fake ancestor Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Drop stray clearing of rps->last_adj
== Series Details ==
Series: drm/i915: Drop stray clearing of rps->last_adj
URL : https://patchwork.freedesktop.org/series/47513/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599 -> Patchwork_9822 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47513/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9822 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_requests:
{fi-bsw-kefka}: PASS -> INCOMPLETE (fdo#105876)
igt@drv_selftest@live_workarounds:
{fi-bsw-kefka}: PASS -> DMESG-FAIL (fdo#107292)
fi-kbl-x1275: PASS -> DMESG-FAIL (fdo#107292)
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: PASS -> FAIL (fdo#104008)
Possible fixes
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-WARN (fdo#107372) -> DMESG-FAIL (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105876 https://bugs.freedesktop.org/show_bug.cgi?id=105876
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (50 -> 45) ==
Additional (1): fi-gdg-551
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 fi-icl-u
fi-byt-clapper
== Build changes ==
* Linux: CI_DRM_4599 -> Patchwork_9822
CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9822: fe9a14be12bd52f5db858b6118dc191f4e98d5ca @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fe9a14be12bd drm/i915: Drop stray clearing of rps->last_adj
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9822/issues.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP
== Series Details == Series: Display Stream Compression enabling on eDP/DP URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Applying: drm/dp: Define payload size for DP SDP PPS packet Applying: drm/dsc: Define Display Stream Compression PPS infoframe Applying: drm/dsc: Define VESA Display Stream Compression Capabilities Applying: drm/dsc: Define Rate Control values that do not change over configurations Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Applying: drm/i915/dp: Compute DSC pipe config in atomic check Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Applying: drm/i915/dsc: Define & Compute VESA DSC params Applying: drm/i915/dsc: Compute Rate Control parameters for DSC Applying: drm/i915/dp: Enable/Disable DSC in DP Sink Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c). error: could not build fake ancestor Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Terminate the context image with BB_END
Quoting Lionel Landwerlin (2018-07-31 13:47:32) > On 30/07/18 17:43, Chris Wilson wrote: > > In the aub trace utility, the context images are terminated with a > > MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise. > > Do the same for our protocontext image for completeness, and in passing > > apply the magic bit for gen10 to mark the end of the context image. > > > > Reported-by: Lionel Landwerlin > > Signed-off-by: Chris Wilson > > Cc: Lionel Landwerlin > > Doesn't look like anything exploded. > Have you noticed any improvement maybe in the benchmarks? Haven't found anything that shows a difference. I expect that after the first save, the context image has grown the BB_END. I was going to dissect the default context image to see if that was true. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 1/2] drm/i915: ddb_size is of u16 type
Quoting Mahesh Kumar (2018-07-31 15:24:44) > ddb_size is u16 so use same return type for intel_get_ddb_size > wrapper. > > Signed-off-by: Mahesh Kumar Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/skl: distribute DDB based on panel resolution
Quoting Mahesh Kumar (2018-07-31 15:24:45)
> + for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> + const struct drm_display_mode *adjusted_mode;
> + int hdisplay, vdisplay;
> + enum pipe pipe;
> +
> + if (!crtc_state->enable)
> + continue;
> +
> + pipe = to_intel_crtc(crtc)->pipe;
> + adjusted_mode = _state->adjusted_mode;
> + drm_mode_get_hv_timing(adjusted_mode, , );
You should check with Ville whether the adjusted_mode is already
adjusted. But at any rate hdisplay is not affected by hv_timing.
> + total_width += hdisplay;
> +
> + if (pipe < for_pipe)
> + width_before_pipe += hdisplay;
> + else if (pipe == for_pipe)
> + pipe_width = hdisplay;
> + }
> +
> + ddb_size_before_pipe = (ddb_size * width_before_pipe) / total_width;
ddb_size_before_pipe can just be alloc->start.
(brackets here) are redundant, so have a discussion as to whether they
aide or hinder comprehension.
> + pipe_size = (ddb_size * pipe_width) / total_width;
> + alloc->start = ddb_size_before_pipe;
> alloc->end = alloc->start + pipe_size;
To avoid truncation fun (and prev_crtc->end != this_crtc->start), use
alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions private to gvt
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions
private to gvt
URL : https://patchwork.freedesktop.org/series/47367/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599 -> Patchwork_9821 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47367/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9821 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_workarounds:
{fi-bsw-kefka}: PASS -> DMESG-FAIL (fdo#107292)
fi-whl-u: PASS -> DMESG-FAIL (fdo#107292)
igt@drv_selftest@mock_hugepages:
fi-bwr-2160:PASS -> DMESG-FAIL (fdo#107254)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-skl-6260u: PASS -> INCOMPLETE (fdo#104108)
Possible fixes
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107254 https://bugs.freedesktop.org/show_bug.cgi?id=107254
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
== Participating hosts (50 -> 45) ==
Additional (1): fi-gdg-551
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks
fi-ctg-p8600 fi-byt-clapper
== Build changes ==
* Linux: CI_DRM_4599 -> Patchwork_9821
CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9821: 3dfe5d390b1482b0326f6d9ee324206721c760e1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3dfe5d390b14 drm/i915: remove confusing GPIO vs PCH_GPIO
25709fb172d6 drm/i915/gvt: use its own define for gpio
90b1a8ff8071 drm/i915: make PCH_GMBUS* definitions private to gvt
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9821/issues.html
___
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Re: [Intel-gfx] [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
Quoting Manasi Navare (2018-07-31 22:07:06) > + /* PPS 4 */ > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel & > + DSC_PPS_BPP_HIGH_MASK) >> > + DSC_PPS_MSB_SHIFT) | To avoid overhanging cliffs, insert the newline after the sequence point. Quite a few examples throughout the series that would benefit from more judicial placement of line breaks. > + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | > + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT | > + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | > + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; Furthermore, you only need the SPDX shorthand rather than full licence text. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
From: Gaurav K Singh
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v5 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v4: (From Manasi)
* Rebase on top of revised patches
v3 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
v2 (From Manasi):
* Fix tons of compilation errors like undefined
variables, incorrect use of macros and all dirty laundry
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 13
drivers/gpu/drm/i915/intel_vdsc.c| 38
3 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ffc9a7..cb6a80a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3427,6 +3427,8 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
extern void intel_dsc_enable(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6b1d151..2b0be6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5829,6 +5829,9 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ int i;
intel_encoders_disable(crtc, old_crtc_state, old_state);
@@ -5845,6 +5848,16 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+ struct intel_encoder *encoder =
+ to_intel_encoder(conn_state->best_encoder);
+
+ if (conn_state->crtc != crtc)
+ continue;
+
+ intel_dsc_disable(encoder, old_crtc_state);
+ }
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 32da285..96f6f94 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1048,3 +1048,41 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(struct intel_encoder *encoder,
+ struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+ /* Put the PG2 power well for VDSC on eDP */
+ /* FIXME: Use VDSC power domain when its added */
+ if (intel_dp_is_edp(intel_dp))
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+}
--
2.7.4
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[Intel-gfx] [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_psr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4bd5768..fdb028f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.7.4
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[Intel-gfx] [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
From: Gaurav K Singh
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 30adc15..4cfcd03 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -56,6 +56,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct dsc_rc_range_parameters {
--
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[Intel-gfx] [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
include/drm/drm_dsc.h | 2 +-
6 files changed, 472 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5794f10..deaf2d4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7132f52..dc0a3c2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp =
%d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b7c2652..33cc777 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index 000..ecd270c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *
[Intel-gfx] [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 221 ++
include/drm/drm_dsc.h | 22
4 files changed, 256 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index f9cfcdc..50bb717 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index a6771ce..961e511 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index 000..99a8794
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,221 @@
+/*
+ *Copyright © 2018 Intel Corp
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more
[Intel-gfx] [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index eda323d..ebd99d7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -33,6 +33,12 @@
#define DSC_MUX_WORD_SIZE_8_10_BPC 48
#define DSC_MUX_WORD_SIZE_12_BPC 64
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
2.7.4
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[Intel-gfx] [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 23 +--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7bdc214..b8e41db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4658,6 +4658,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8363fbd..a37fbf0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct drm_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -390,11 +406,14 @@ static void hsw_write_infoframe(struct drm_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ i915_reg_t data_reg;
+ int data_size = 0;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+ data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
2.7.4
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[Intel-gfx] [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v5:
* Get the max slice width from DPCD
* Check against Min_Slice_width of 2560 (Anusha)
v4:
* #defines for PPR in slice count helper (Gaurav)
v3:
* Simply logic for bpp (DK)
* Limit the valid slice count by max supported by Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Dhinakaran Pandiyan
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 104 +++
drivers/gpu/drm/i915/intel_drv.h | 4 ++
2 files changed, 108 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index afa4e2d..ec2af43 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -45,6 +45,17 @@
#define DP_DPRX_ESI_LEN 14
+/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
+#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+
+/* DP DSC throughput values used for slice count calculations KPixels/s */
+#define DP_DSC_PEAK_PIXEL_RATE 272
+#define DP_DSC_MAX_ENC_THROUGHPUT_034
+#define DP_DSC_MAX_ENC_THROUGHPUT_140
+
+/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
+#define DP_DSC_FEC_OVERHEAD_FACTOR 976
+
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
@@ -93,6 +104,14 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
};
+/* Constants for DP DSC configurations */
+static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
+
+/* With Single pipe configuration, HW is capable of supporting maximum
+ * of 4 slices per line.
+ */
+static const u8 valid_dsc_slicecount[] = {1, 2, 4};
+
/**
* intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
PCH)
* @intel_dp: DP struct
@@ -4087,6 +4106,91 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8
*sink_irq_vector)
DP_DPRX_ESI_LEN;
}
+uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
+int mode_clock, int mode_hdisplay)
+{
+ u16 bits_per_pixel, max_bpp_small_joiner_ram;
+ int i;
+
+ /*
+* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
+* (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
+* FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
+* for MST -> TimeSlotsPerMTP has to be calculated
+*/
+ bits_per_pixel = (link_clock * lane_count * 8 *
+ DP_DSC_FEC_OVERHEAD_FACTOR) /
+ (mode_clock * 1000);
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
+ mode_hdisplay;
+
+ /*
+* Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
+* check, output bpp from small joiner RAM check)
+*/
+ bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+
+ /* Error out if the max bpp is less than smallest allowed valid bpp */
+ if (bits_per_pixel < valid_dsc_bpp[0]) {
+ DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
+ return 0;
+ }
+
+ /* Find the nearest match in the array of known BPPs from VESA */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
+
+ /*
+* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
+* fractional part is 0
+*/
+ return bits_per_pixel << 4;
+}
+
+uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+int mode_clock,
+int mode_hdisplay)
+{
+ u8 min_slice_count, i;
+ int max_slice_width;
+
+ if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_0);
+ else
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_1);
+
+ max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
+ if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
+ DRM_DEBUG_KMS("Unsupported slice width
[Intel-gfx] [PATCH v2 21/23] drm/i915/icl: Add Display Stream Splitter control registers
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v2:
- Add define to conditionally check the buffer target depth (James Ausmus)
Suggested-by: Madhav Chauhan
Cc: Madhav Chauhan
Cc: Manasi Navare
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8e41db..0ae38b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7792,6 +7792,39 @@ enum {
#define RC_MAX_QP_SHIFT5
#define RC_MIN_QP_SHIFT0
+/* Display Stream Splitter Control */
+#define DSS_CTL1 _MMIO(0x67400)
+#define SPLITTER_ENABLE (1 << 31)
+#define JOINER_ENABLE (1 << 30)
+#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
+#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
+#define OVERLAP_PIXELS_MASK (0xf << 16)
+#define OVERLAP_PIXELS(pixels)((pixels) << 16)
+#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+#define MAX_DL_BUFFER_TARGET_DEPTH0x5A0
+
+#define DSS_CTL2 _MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_DL_BUF_TARGET_DEPTH_MASK(0xfff << 0)
+#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+
+#define _ICL_PIPE_DSS_CTL1_PB 0x78200
+#define _ICL_PIPE_DSS_CTL1_PC 0x78400
+#define ICL_PIPE_DSS_CTL1(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_PIPE_DSS_CTL1_PB, \
+
_ICL_PIPE_DSS_CTL1_PC)
+#define BIG_JOINER_ENABLE (1 << 29)
+#define MASTER_BIG_JOINER_ENABLE (1 << 28)
+#define VGA_CENTERING_ENABLE (1 << 27)
+
+#define _ICL_PIPE_DSS_CTL2_PB 0x78204
+#define _ICL_PIPE_DSS_CTL2_PC 0x78404
+#define ICL_PIPE_DSS_CTL2(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_PIPE_DSS_CTL2_PB, \
+
_ICL_PIPE_DSS_CTL2_PC)
+
#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
--
2.7.4
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[Intel-gfx] [PATCH v2 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_vdsc.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index bd5dc96..32da285 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1011,6 +1011,12 @@ void intel_dsc_enable(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1024,5 +1030,21 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
+ /* Configure DSS_CTL registers for DSC */
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.7.4
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[Intel-gfx] [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f49f99..334a5db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -52,6 +52,7 @@
#include
#include
#include
+#include
#include "i915_params.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 68b2401..b7c2652 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -895,6 +895,15 @@ struct intel_crtc_state {
/* output format is YCBCR 4:2:0 */
bool ycbcr420;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
2.7.4
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[Intel-gfx] [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_vdsc.c | 129 ++
1 file changed, 129 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index ecd270c..23ba083 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -335,6 +335,132 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* RC_MODEL_SIZE is a constant across all configurations */
+ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DP_DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel, 8);
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (8 * vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
+ DP_DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel) + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_ERROR("FinalOfs < RcModelSze for this InitialXmitDelay\n");
+ return -1;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size << 3) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_ERROR("NflBpgOffset is too large for this slice height\n");
+ return -1;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+ vdsc_cfg->initial_offset +
+ num_extra_mux_bits) << 11),
+
[Intel-gfx] [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
---
include/drm/drm_dsc.h | 365 ++
1 file changed, 365 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index 000..678e8e6
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16
[Intel-gfx] [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index e3db9dc..bd5dc96 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(>base, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -1003,5 +1022,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice ocunt and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_display.c | 20 +++--
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 141 +++
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
4 files changed, 142 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 577b30d..de895ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6460,7 +6460,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
- intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+ intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
link_bw, _config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6697,17 +6697,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool reduce_m_n)
{
m_n->tu = 64;
- compute_m_n(bits_per_pixel * pixel_clock,
- link_clock * nlanes * 8,
- _n->gmch_m, _n->gmch_n,
- reduce_m_n);
+ /* For DSC, Data M/N calculation uses compressed BPP */
+ if (compressed_bpp)
+ compute_m_n(compressed_bpp * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ reduce_m_n);
+ else
+ compute_m_n(bits_per_pixel * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ reduce_m_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 0a79a46..ba013e4 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -360,7 +360,8 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool reduce_m_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8459d74..7132f52 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1897,6 +1899,16 @@ static int intel_dp_compute_bpp(struct intel_dp
*intel_dp,
}
}
+ /* If DSC is supported, use the max value reported by panel */
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ bpc = min_t(u8,
+ drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd),
+ DP_DSC_MAX_SUPPORTED_BPC);
+ if (!bpc)
+ bpp = 3 * bpc;
+ }
+
return bpp;
}
@@ -1957,14 +1969,11 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
link_clock =
[Intel-gfx] [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding DPCD registers.
v4:
* Add helper to give line buf bit depth (Manasi)
v3:
* Use SLICE_CAP_2 for DP (Anusha)
v2:
* Add DSC sink support macro (Jani N)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/drm_dp_helper.c | 89 +
include/drm/drm_dp_helper.h | 30 ++
2 files changed, 119 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 0cccbcb..7dc61d1 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1336,3 +1336,92 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
return 0;
}
EXPORT_SYMBOL(drm_dp_read_desc);
+
+/**
+ * DRM DP Helpers for DSC
+ */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp)
+{
+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
+
+ if (is_edp) {
+ /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count
*/
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ } else {
+ /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
+
+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
+ return 24;
+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
+ return 20;
+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
+ return 16;
+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
+ return 12;
+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
+ return 10;
+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
+ return 8;
+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
+ return 6;
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
+
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH -
DP_DSC_SUPPORT];
+
+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
+ case DP_DSC_LINE_BUF_BIT_DEPTH_9:
+ return 9;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_10:
+ return 10;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_11:
+ return 11;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_12:
+ return 12;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_13:
+ return 13;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_14:
+ return 14;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_15:
+ return 15;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_16:
+ return 16;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_8:
+ return 8;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
+
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ switch (dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]) {
+ case DP_DSC_12_BPC:
+ return 12;
+ case DP_DSC_10_BPC:
+ return 10;
+ case DP_DSC_8_BPC:
+ return 8;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index eb0d86c..8c1dbca 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1064,6 +1064,36 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
}
+/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp);
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+
+static inline bool
+drm_dp_sink_supports_dsc(const u8
[Intel-gfx] [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 15 +++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0adc043..5e8c891 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2825,6 +2825,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ DP_DECOMPRESSION_EN);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3154,6 +3156,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ ~DP_DECOMPRESSION_EN);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dc0a3c2..1a8329c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2925,6 +2925,21 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ int state)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE, state);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ state == DP_DECOMPRESSION_EN ? "enable" :
"disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 33cc777..ced62e0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1691,6 +1691,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ int state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
DSC is supported on eDP starting GEN 10 display and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x006F) to
read the decompression capabilities of the sink device.
This entire block of registers is cached in intel_dp so that
capability information can be used during DSC configuration
phase during compute_config phase of the modeset.
For eDP, this caching happens during the eDP initialization.
This caching is done only for eDP and DP rev >= 1.4
v5:
* Fix the block comment (Gaurav)
* Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha)
v4:
* Cache these only for Gen >= 11
v3:
* Remove the dsc_sink_support field in intel_dp (Jani N)
v2:
* Clear the cached registers on hotplug always (Jani N)
* Combine the eDP and DP caching in same function (Jani N)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Daniel Vetter
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 32
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8e0e14b..afa4e2d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3877,6 +3877,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
return intel_dp->dpcd[DP_DPCD_REV] != 0;
}
+static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
+{
+ /*
+*Clear the cached register set to avoid using stale values
+* for the sinks that do not support DSC.
+*/
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+
+ /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
+ intel_dp->edp_dpcd[0] >= DP_EDP_14) {
+ if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
+intel_dp->dsc_dpcd,
+sizeof(intel_dp->dsc_dpcd)) < 0)
+ DRM_ERROR("Failed to read DPCD register 0x%x\n",
+ DP_DSC_SUPPORT);
+
+ DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
+ (int)sizeof(intel_dp->dsc_dpcd),
+ intel_dp->dsc_dpcd);
+ }
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp)
{
@@ -3953,6 +3976,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_common_rates(intel_dp);
+ /* Read the eDP DSC DPCD registers */
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
return true;
}
@@ -4944,6 +4971,7 @@ intel_dp_long_pulse(struct intel_connector *connector)
if (status == connector_status_disconnected) {
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
if (intel_dp->is_mst) {
DRM_DEBUG_KMS("MST device may have disappeared %d vs
%d\n",
@@ -4969,6 +4997,10 @@ intel_dp_long_pulse(struct intel_connector *connector)
intel_dp_print_rates(intel_dp);
+ /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
+ if (INTEL_GEN(dev_priv) >= 11)
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
drm_dp_read_desc(_dp->aux, _dp->desc,
drm_dp_is_branch(intel_dp->dpcd));
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 99a5f5b..29abe7a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1070,6 +1070,7 @@ struct intel_dp {
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
/* source rates */
int num_source_rates;
const int *source_rates;
--
2.7.4
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities
From: Gaurav K Singh
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
---
include/drm/drm_dsc.h | 110 ++
1 file changed, 110 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 678e8e6..eda323d 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -30,6 +30,116 @@
/* VESA Display Stream Compression DSC 1.2 constants */
#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+
+/* Configuration for a single Rate Control model range */
+struct dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie., disable stuffing bits) */
+ bool vbr_enable;
+ /* Mux word size (in bits) for SSM mode */
+ u8 mux_word_size;
+ /*
+* The (max) size in bytes of the "chunks" that are
+* used in slice multiplexing
+*/
+ u16 slice_chunk_size;
+ /* Rate Control buffer siz in bits */
+ u16 rc_bits;
+ /* DSC Minor Version */
+ u8 dsc_version_minor;
+ /* DSC Major version */
+ u8
[Intel-gfx] [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ec2af43..8459d74 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -612,9 +612,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk;
+ uint16_t dsc_max_output_bpp = 0;
+ uint8_t dsc_slice_count = 0;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
@@ -637,7 +640,29 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(target_clock, 18);
- if (mode_rate > max_rate || target_clock > max_dotclk)
+ /*
+* Output bpp is stored in 6.4 format so right shift by 4 to get the
+* integer value since we support only integer values of bpp.
+*/
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ if (intel_dp_is_edp(intel_dp)) {
+ dsc_max_output_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
+ dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
+ true);
+ } else {
+ dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
+
max_lanes,
+
target_clock,
+
mode->hdisplay) >> 4;
+ dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp,
+
target_clock,
+
mode->hdisplay);
+ }
+ }
+
+ if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count))
||
+ target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
if (mode->clock < 1)
--
2.7.4
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[Intel-gfx] [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 6 +
drivers/gpu/drm/i915/intel_vdsc.c| 423 +++
3 files changed, 431 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 334a5db..0ffc9a7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3425,6 +3425,8 @@ extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv);
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index de895ab..6b1d151 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5410,6 +5410,12 @@ static void intel_encoders_pre_enable(struct drm_crtc
*crtc,
if (encoder->pre_enable)
encoder->pre_enable(encoder, crtc_state, conn_state);
+
+ /*
+* Enable and Configure Display Stream Compression in the source
+* if enabled in intel_crtc_state.
+*/
+ intel_dsc_enable(encoder, crtc_state);
}
}
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 23ba083..e3db9dc 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -582,3 +582,426 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return 0;
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = 0;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ else
+ pps_val &= ~DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ else
+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ else
+ pps_val &= ~DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ else
+ pps_val &= ~DSC_VBR_ENABLE;
+
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+ /*
+* If 2 VDSC instances are needed, configure PPS for second
+* VDSC
+*/
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
+ } else {
+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+ pps_val);
+ }
+
+ /* Populate PICTURE_PARAMETER_SET_1 registers */
+ pps_val = 0;
+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+ DRM_INFO("PPS1 = 0x%08x\n", pps_val);
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
+ /*
+* If 2 VDSC instances are needed, configure PPS for second
+* VDSC
+*/
+ if (crtc_state->dsc_params.dsc_split)
+
[Intel-gfx] [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Reviewed-by: Harry Wentland
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8c1dbca..0cf2407 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -998,6 +998,7 @@ struct dp_sdp_header {
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
struct edp_vsc_psr {
struct dp_sdp_header sdp_header;
--
2.7.4
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[Intel-gfx] [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP
Cc: dri-de...@lists.freedesktop.org VESA has developed an industry standard Display Stream Compression(DSC) for interoperable, visually lossless compression over display links to address the needs for higher resolution displays. This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels. This implementation is based on VESA DP 1.4 and DSC specifications. These patches have been validated on 1080p eDP 1.4 panel with DSC support and FPGA based DP 1.4 sink device. This patch series fixes some CI warnings from prev series: https://patchwork.freedesktop.org/series/47461/ Gaurav K Singh (6): drm/dsc: Define VESA Display Stream Compression Capabilities drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare (15): drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init drm/dp: DRM DP helper/macros to get DP sink DSC parameters drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported drm/dp: Define payload size for DP SDP PPS packet drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Add helpers for DSC picture parameter set infoframes drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable Srivatsa, Anusha (2): drm/dsc: Define Rate Control values that do not change over configurations drm/i915/icl: Add Display Stream Splitter control registers Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile |2 +- drivers/gpu/drm/drm_dp_helper.c | 89 +++ drivers/gpu/drm/drm_dsc.c | 221 +++ drivers/gpu/drm/i915/Makefile |3 +- drivers/gpu/drm/i915/i915_drv.h |5 + drivers/gpu/drm/i915/i915_reg.h | 34 ++ drivers/gpu/drm/i915/intel_ddi.c |5 + drivers/gpu/drm/i915/intel_display.c | 39 +- drivers/gpu/drm/i915/intel_display.h |3 +- drivers/gpu/drm/i915/intel_dp.c | 326 +- drivers/gpu/drm/i915/intel_dp_mst.c |2 +- drivers/gpu/drm/i915/intel_drv.h | 21 + drivers/gpu/drm/i915/intel_hdmi.c | 23 +- drivers/gpu/drm/i915/intel_psr.c | 10 + drivers/gpu/drm/i915/intel_vdsc.c | 1088 + include/drm/drm_dp_helper.h | 40 ++ include/drm/drm_dsc.h | 506 +++ 18 files changed, 2400 insertions(+), 29 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
This patch defines the DP DSC receiver capability size that gives total number of DP DSC DPCD registers. This also adds a missing #defines for DP DSC support missed in the commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") v3: * MIN_SLICE_WIDTH = 2560 (Anusha) * Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 v2: * Add SHIFT define and DECOMPRESSION_EN define misse din prev patch Cc: dri-de...@lists.freedesktop.org Cc: Jani Nikula Cc: Ville Syrjala Cc: Anusha Srivatsa Cc: Gaurav K Singh Signed-off-by: Manasi Navare --- include/drm/drm_dp_helper.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 05cc31b..eb0d86c 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -230,6 +230,8 @@ #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -278,6 +280,8 @@ # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) #define DP_DSC_MAX_SLICE_WIDTH 0x06C +#define DP_DSC_MIN_SLICE_WIDTH_VALUE2560 +#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 #define DP_DSC_SLICE_CAP_2 0x06D # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) @@ -476,6 +480,7 @@ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ +# define DP_DECOMPRESSION_EN(1 << 0) #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) @@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Drop stray clearing of rps->last_adj
We used to reset last_adj to 0 on crossing a power domain boundary, to
slow down our rate of change. However, commit 60548c554be2 ("drm/i915:
Interactive RPS mode") accidentally caused it to be reset on every
frequency update, nerfing the fast response granted by the slow start
algorithm.
Fixes: 60548c554be2 ("drm/i915: Interactive RPS mode")
Testcase: igt/pm_rps/mix-max-config-loaded
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2531eb75bdce..f90a3c7f1c40 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6371,7 +6371,6 @@ static void gen6_set_rps_thresholds(struct
drm_i915_private *dev_priv, u8 val)
new_power = HIGH_POWER;
rps_set_power(dev_priv, new_power);
mutex_unlock(>power.mutex);
- rps->last_adj = 0;
}
void intel_rps_mark_interactive(struct drm_i915_private *i915, bool
interactive)
--
2.18.0
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Re: [Intel-gfx] [PATCH 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
>-Original Message- >From: Navare, Manasi D >Sent: Monday, July 30, 2018 7:13 PM >To: intel-gfx@lists.freedesktop.org >Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Srivatsa, >Anusha >; Singh, Gaurav K ; >Navare, Manasi D ; dri- >de...@lists.freedesktop.org >Subject: [PATCH 01/23] drm/dp: Add DP DSC DPCD receiver capability size define >and missing SHIFT > >This patch defines the DP DSC receiver capability size that gives total number >of >DP DSC DPCD registers. >This also adds a missing #defines for DP DSC support missed in the commit id >(ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") > >v3: >* MIN_SLICE_WIDTH = 2560 (Anusha) >* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 >v2: >* Add SHIFT define and DECOMPRESSION_EN define misse din prev patch missed in previous >Cc: dri-de...@lists.freedesktop.org >Cc: Jani Nikula >Cc: Ville Syrjala >Cc: Anusha Srivatsa >Cc: Gaurav K Singh >Signed-off-by: Manasi Navare But that apart, checked with spec. Changes look good. Reviewed-by: Anusha Srivatsa >--- > include/drm/drm_dp_helper.h | 6 ++ > 1 file changed, 6 insertions(+) > >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index >05cc31b..eb0d86c 100644 >--- a/include/drm/drm_dp_helper.h >+++ b/include/drm/drm_dp_helper.h >@@ -230,6 +230,8 @@ > #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ > > #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ >+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define >+DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 > > #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 > # define DP_DSC_RGB (1 << 0) >@@ -278,6 +280,8 @@ > # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) > > #define DP_DSC_MAX_SLICE_WIDTH 0x06C >+#define DP_DSC_MIN_SLICE_WIDTH_VALUE2560 >+#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 > > #define DP_DSC_SLICE_CAP_2 0x06D > # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) >@@ -476,6 +480,7 @@ > # define DP_AUX_FRAME_SYNC_VALID (1 << 0) > > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ >+# define DP_DECOMPRESSION_EN(1 << 0) > > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > # define DP_PSR_ENABLE(1 << 0) >@@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 >link_status[DP_LINK_STATUS_SI > > #define DP_BRANCH_OUI_HEADER_SIZE 0xc > #define DP_RECEIVER_CAP_SIZE 0xf >+#define DP_DSC_RECEIVER_CAP_SIZE0xf > #define EDP_PSR_RECEIVER_CAP_SIZE 2 > #define EDP_DISPLAY_CTL_CAP_SIZE 3 > >-- >2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 11/35] drm/i915: Enable and Disable of HDCP2.2
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>Subject: [PATCH v6 11/35] drm/i915: Enable and Disable of HDCP2.2
>
>Considering that HDCP2.2 is more secure than HDCP1.4, When a setup supports
>HDCP2.2 and HDCP1.4, HDCP2.2 will be enabled.
>
>When HDCP2.2 enabling fails and HDCP1.4 is supported, HDCP1.4 is enabled.
>
>This change implements a sequence of enabling and disabling of
>HDCP2.2 authentication and HDCP2.2 port encryption.
>
>v2:
> Included few optimization suggestions [Chris Wilson]
> Commit message is updated as per the rebased version.
> intel_wait_for_register is used instead of wait_for. [Chris Wilson]
>v3:
> No changes.
>v4:
> Extra comment added and Style issue fixed [Uma]
>v5:
> Rebased as part of patch reordering.
> HDCP2 encryption status is tracked.
> HW state check is moved into WARN_ON [Daniel]
>v6:
> Redefined the mei service functions as per comp redesign.
> Merged patches related to hdcp2.2 enabling and disabling [Sean Paul].
> Required shim functionality is defined [Sean Paul]
>
>Signed-off-by: Ramalingam C
>---
> drivers/gpu/drm/i915/intel_drv.h | 5 +
> drivers/gpu/drm/i915/intel_hdcp.c | 226
>--
> 2 files changed, 221 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_drv.h
>b/drivers/gpu/drm/i915/intel_drv.h
>index 38262792813a..21683702bcdc 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -380,6 +380,10 @@ struct intel_hdcp_shim {
>
> /* Detects the HDCP protocol(DP/HDMI) required on the port */
> enum hdcp_protocol (*hdcp_protocol)(void);
>+
>+ /* Detects whether Panel is HDCP2.2 capable */
>+ int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
>+ bool *capable);
> };
>
> struct intel_hdcp {
>@@ -393,6 +397,7 @@ struct intel_hdcp {
> /* HDCP2.2 related definitions */
> /* Flag indicates whether this connector supports HDCP2.2 or not. */
> bool hdcp2_supported;
>+ bool hdcp2_in_use;
>
> /*
>* Content Stream Type defined by content owner. TYPE0(0x0) content
>can diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
>b/drivers/gpu/drm/i915/intel_hdcp.c
>index 18509c3bae08..4ace64315baa 100644
>--- a/drivers/gpu/drm/i915/intel_hdcp.c
>+++ b/drivers/gpu/drm/i915/intel_hdcp.c
>@@ -17,10 +17,51 @@
> #include "i915_reg.h"
>
> #define KEY_LOAD_TRIES5
>+#define TIME_FOR_ENCRYPT_STATUS_CHANGE32
> #define GET_MEI_DDI_INDEX(port) (((port) == PORT_A) ? DDI_A : \
>(enum hdcp_physical_port)(port))
>
> static int intel_hdcp2_init(struct intel_connector *connector);
>+static int _intel_hdcp2_enable(struct intel_connector *connector);
>+static int _intel_hdcp2_disable(struct intel_connector *connector);
>+static int intel_hdcp_read_valid_bksv(struct intel_digital_port
>+*intel_dig_port,
>+ const struct intel_hdcp_shim *shim, u8 *bksv);
>static
>struct
>+intel_digital_port *conn_to_dig_port(struct intel_connector
>+*connector);
>+
>+/* Is HDCP1.4 capable on Platform and Panel */ static bool
Instead of Panel, call it as sink.
>+intel_hdcp_capable(struct intel_connector *connector) {
>+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
>+ struct intel_hdcp *hdcp = >hdcp;
>+ bool capable = false;
>+ u8 bksv[5];
>+
>+ if (hdcp->shim->hdcp_capable) {
>+ hdcp->shim->hdcp_capable(intel_dig_port, );
>+ } else {
>+ if (!intel_hdcp_read_valid_bksv(intel_dig_port,
>+ hdcp->shim, bksv))
>+ capable = true;
>+ }
>+
>+ return capable;
>+}
>+
>+/* Is HDCP2.2 capable on Platform and Panel */ static bool
Same as above.
>+intel_hdcp2_capable(struct intel_connector *connector) {
>+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
>+ struct intel_hdcp *hdcp = >hdcp;
>+ bool capable = false;
>+
>+ /* Check the panel's hdcp2.2 compliance if platform supports it. */
Here too.
>+ if (hdcp->hdcp2_supported)
>+ hdcp->shim->hdcp_2_2_capable(intel_dig_port, );
>+
>+ return capable;
>+}
>
> static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
> const struct intel_hdcp_shim *shim) @@ -
>791,22 +832,33 @@ int intel_hdcp_init(struct intel_connector *connector, int
>intel_hdcp_enable(struct intel_connector *connector) {
> struct intel_hdcp *hdcp = >hdcp;
>- int ret;
>+ int ret = -EINVAL;
>
> if (!hdcp->shim)
> return -ENOENT;
>
> mutex_lock(>mutex);
>
Re: [Intel-gfx] [RFC 1/3] drm: Add colorspace property
On Tue, 2018-07-24 at 21:15 +0530, Uma Shankar wrote:
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -209,6 +209,17 @@
> #define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
> #define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
>
> +enum extended_colorimetry {
> + EXTENDED_COLORIMETRY_XV_YCC_601 = 0,
> + EXTENDED_COLORIMETRY_XV_YCC_709,
> + EXTENDED_COLORIMETRY_S_YCC_601,
> + EXTENDED_COLORIMETRY_ADOBE_YCC_601,
> + EXTENDED_COLORIMETRY_ADOBE_RGB,
> + EXTENDED_COLORIMETRY_BT2020_RGB,
> + EXTENDED_COLORIMETRY_BT2020_YCC,
> + EXTENDED_COLORIMETRY_BT2020_CYCC,
> +};
This doesn't give any way to distinguish "not set" from BT.601, which
I'm not sure I like.
Is this enum simply built to match the values you're injecting into the
InfoFrame? Would we need a different enum for DisplayPort?
- ajax
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Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On Tue, Jul 31, 2018 at 7:41 PM, Eric Dumazet wrote: > On Tue, Jul 31, 2018 at 10:36 AM Christopher Lameter wrote: > >> >> If there is refcounting going on then why use SLAB_TYPESAFE_BY_RCU? > > To allow fast reuse of objects, without going through call_rcu() and > reducing cache efficiency. > > I believe this is mentioned in Documentation/RCU/rculist_nulls.txt Is it OK to overwrite ct->status? It seems that are some read and writes to it right after atomic_inc_not_zero. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On Tue, Jul 31, 2018 at 10:10 AM Florian Westphal wrote: > > Andrey Ryabinin wrote: > > Guys, it seems that we have a lot of code using SLAB_TYPESAFE_BY_RCU cache > > without constructor. > > I think it's nearly impossible to use that combination without having bugs. > > It's either you don't really need the SLAB_TYPESAFE_BY_RCU, or you need to > > have a constructor in kmem_cache. > > > > Could you guys, please, verify your code if it's really need SLAB_TYPSAFE > > or constructor? > > > > E.g. the netlink code look extremely suspicious: > > > > /* > >* Do not use kmem_cache_zalloc(), as this cache uses > >* SLAB_TYPESAFE_BY_RCU. > >*/ > > ct = kmem_cache_alloc(nf_conntrack_cachep, gfp); > > if (ct == NULL) > > goto out; > > > > spin_lock_init(>lock); > > > > If nf_conntrack_cachep objects really used in rcu typesafe manner, than > > 'ct' returned by kmem_cache_alloc might still be > > in use by another cpu. So we just reinitialize spin_lock used by someone > > else? > > That would be a bug, nf_conn objects are reference counted. > > spinlock can only be used after object had its refcount incremented. > > lookup operation on nf_conn object: > 1. compare keys > 2. attempt to obtain refcount (using _not_zero version) > 3. compare keys again after refcount was obtained > > if any of that fails, nf_conn candidate is skipped. Yes, the key here is the refcount, this is only what we need to clear after kmem_cache_alloc() By definition, if an object is being freed/reallocated, the refcount should be already 0, and clearing it again is a NOP. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On Tue, Jul 31, 2018 at 10:51 AM Dmitry Vyukov wrote: > > > Is it OK to overwrite ct->status? It seems that are some read and > writes to it right after atomic_inc_not_zero. If it is after a (successful) atomic_inc_not_zero(), the object is guaranteed to be alive (not freed or about to be freed). About readind/writing a specific field, all traditional locking rules apply. For TCP socket, we would generally grab the socket lock before reading/writing various fields. ct->status seems to be manipulated with set_bit() and clear_bit() which are SMP safe. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
Andrey Ryabinin wrote: > Guys, it seems that we have a lot of code using SLAB_TYPESAFE_BY_RCU cache > without constructor. > I think it's nearly impossible to use that combination without having bugs. > It's either you don't really need the SLAB_TYPESAFE_BY_RCU, or you need to > have a constructor in kmem_cache. > > Could you guys, please, verify your code if it's really need SLAB_TYPSAFE or > constructor? > > E.g. the netlink code look extremely suspicious: > > /* >* Do not use kmem_cache_zalloc(), as this cache uses >* SLAB_TYPESAFE_BY_RCU. >*/ > ct = kmem_cache_alloc(nf_conntrack_cachep, gfp); > if (ct == NULL) > goto out; > > spin_lock_init(>lock); > > If nf_conntrack_cachep objects really used in rcu typesafe manner, than 'ct' > returned by kmem_cache_alloc might still be > in use by another cpu. So we just reinitialize spin_lock used by someone else? That would be a bug, nf_conn objects are reference counted. spinlock can only be used after object had its refcount incremented. lookup operation on nf_conn object: 1. compare keys 2. attempt to obtain refcount (using _not_zero version) 3. compare keys again after refcount was obtained if any of that fails, nf_conn candidate is skipped. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On Tue, Jul 31, 2018 at 10:36 AM Christopher Lameter wrote: > > If there is refcounting going on then why use SLAB_TYPESAFE_BY_RCU? To allow fast reuse of objects, without going through call_rcu() and reducing cache efficiency. I believe this is mentioned in Documentation/RCU/rculist_nulls.txt ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Something is breaking the driver for me
Hi all, It turned out my cable was defectuous. Keep up the great work and support, sorry for the noise on the list ! Cheers ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Do not use iowait while waiting for the GPU
Mika Kuoppala writes:
> Chris Wilson writes:
>
>> A recent trend for cpufreq is to boost the CPU frequencies for
>> iowaiters, in particularly to benefit high frequency I/O. We do the same
>> and boost the GPU clocks to try and minimise time spent waiting for the
>> GPU. However, as the igfx and CPU share the same TDP, boosting the CPU
>> frequency will result in the GPU being throttled and its frequency being
>> reduced. Thus declaring iowait negatively impacts on GPU throughput.
>>
>> v2: Both sleeps!
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107410
>> References: 52ccc4314293 ("cpufreq: intel_pstate: HWP boost performance on
>> IO wakeup")
>
> The commit above has it's own heuristics on when to actual ramp up,
> inspecting the interval of io waits.
>
> Regardless of that, with shared tdp, the waiter should not stand in a
> way.
I've been running some tests with this series (and your previous ones).
I still see statistically significant regressions in latency-sensitive
benchmarks with this series applied:
qgears2/render-backend=XRender Extension/test-mode=Text: XXX ±0.26% x12 -> XXX
±0.36% x15 d=-0.97% ±0.32% p=0.00%
lightsmark: XXX ±0.51% x22 -> XXX
±0.49% x20 d=-1.58% ±0.50% p=0.00%
gputest/triangle:XXX ±0.67% x10 -> XXX
±1.76% x20 d=-1.73% ±1.47% p=0.52%
synmark/OglMultithread:ĝ XXX ±0.47% x10 -> XXX
±1.06% x20 d=-3.59% ±0.88% p=0.00%
Numbers above are from a partial benchmark run on BXT J3455 -- I'm still
waiting to get the results of a full run though.
Worse, in combination with my intel_pstate branch the effect of this
patch is strictly negative. There are no improvements because the
cpufreq governor is able to figure out by itself that boosting the
frequency of the CPU under GPU-bound conditions cannot possibly help
(The HWP boost logic could be fixed to do the same thing easily which
would allow us to obtain the best of both worlds on big core). The
reason for the regressions is that IOWAIT is a useful signal for the
cpufreq governor to provide reduced latency in applications that are
unable to parallelize enough work between CPU and the IO device -- The
upstream governor is just using it rather ineffectively.
> And that it fixes a regression:
>
This patch isn't necessary anymore to fix the regression, there is
another change going in that mitigates the problem [1]. Can we please
keep the IO schedule calls here? (and elsewhere in the atomic commit
code)
[1] https://lkml.org/lkml/2018/7/30/880
> Reviewed-by: Mika Kuoppala
>
> On other way around, the atomic commit code on updating
> planes, could potentially benefit of changing to the
> io_schedule_timeout. (and/or adopting c state limits)
>
> -Mika
>
>> Signed-off-by: Chris Wilson
>> Cc: Tvrtko Ursulin
>> Cc: Joonas Lahtinen
>> Cc: Eero Tamminen
>> Cc: Francisco Jerez
>> ---
>> drivers/gpu/drm/i915/i915_request.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_request.c
>> b/drivers/gpu/drm/i915/i915_request.c
>> index f3ff8dbe363d..3e48ea87b324 100644
>> --- a/drivers/gpu/drm/i915/i915_request.c
>> +++ b/drivers/gpu/drm/i915/i915_request.c
>> @@ -1376,7 +1376,7 @@ long i915_request_wait(struct i915_request *rq,
>> goto complete;
>> }
>>
>> -timeout = io_schedule_timeout(timeout);
>> +timeout = schedule_timeout(timeout);
>> } while (1);
>>
>> GEM_BUG_ON(!intel_wait_has_seqno());
>> @@ -1414,7 +1414,7 @@ long i915_request_wait(struct i915_request *rq,
>>wait.seqno - 1))
>> qos = wait_dma_qos_add();
>>
>> -timeout = io_schedule_timeout(timeout);
>> +timeout = schedule_timeout(timeout);
>>
>> if (intel_wait_complete() &&
>> intel_wait_check_request(, rq))
>> --
>> 2.18.0
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Re: [Intel-gfx] [PATCH v6 09/35] drm/i915: Initialize HDCP2.2 and its MEI interface
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>Subject: [PATCH v6 09/35] drm/i915: Initialize HDCP2.2 and its MEI interface
>
>Initialize HDCP2.2 support. This includes the mei interface initialization
>along with
>required component registration.
>
>v2:
> mei interface handle is protected with mutex. [Chris Wilson]
>v3:
> Notifiers are used for the mei interface state.
>v4:
> Poll for mei client device state
> Error msg for out of mem [Uma]
> Inline req for init function removed [Uma]
>v5:
> Rebase as Part of reordering.
> Component is used for the I915 and MEI_HDCP interface [Daniel]
>v6:
> HDCP2.2 uses the I915 component master to communicate with mei_hdcp
> - [Daniel]
> Required HDCP2.2 variables defined [Sean Paul]
>
>Signed-off-by: Ramalingam C
>---
> drivers/gpu/drm/i915/intel_dp.c | 3 +-
> drivers/gpu/drm/i915/intel_drv.h | 23 +++-
>drivers/gpu/drm/i915/intel_hdcp.c | 77
>++-
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> include/drm/i915_component.h | 60 ++
> 5 files changed, 161 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 5be07e1d816d..12eb5bd33b7e 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -6406,7 +6406,8 @@ intel_dp_init_connector(struct intel_digital_port
>*intel_dig_port,
> intel_dp_add_properties(intel_dp, connector);
>
> if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
>- int ret = intel_hdcp_init(intel_connector, _dp_hdcp_shim);
>+ int ret = intel_hdcp_init(intel_connector, _dp_hdcp_shim,
>+false);
> if (ret)
> DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> }
>diff --git a/drivers/gpu/drm/i915/intel_drv.h
>b/drivers/gpu/drm/i915/intel_drv.h
>index c32665136d5d..38262792813a 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -29,6 +29,7 @@
> #include
> #include
> #include
>+#include
> #include
> #include "i915_drv.h"
> #include
>@@ -376,6 +377,9 @@ struct intel_hdcp_shim {
> /* Detects panel's hdcp capability. This is optional for HDMI. */
> int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
> bool *hdcp_capable);
>+
>+ /* Detects the HDCP protocol(DP/HDMI) required on the port */
>+ enum hdcp_protocol (*hdcp_protocol)(void);
> };
>
> struct intel_hdcp {
>@@ -385,6 +389,20 @@ struct intel_hdcp {
> uint64_t value;
> struct delayed_work check_work;
> struct work_struct prop_work;
>+
>+ /* HDCP2.2 related definitions */
>+ /* Flag indicates whether this connector supports HDCP2.2 or not. */
>+ bool hdcp2_supported;
>+
>+ /*
>+ * Content Stream Type defined by content owner. TYPE0(0x0) content
>can
>+ * flow in the link protected by HDCP2.2 or HDCP1.4, where as
>TYPE1(0x1)
>+ * content can flow only through a link protected by HDCP2.2.
>+ */
>+ u8 content_type;
>+
>+ /* mei interface related information */
>+ struct mei_hdcp_data mei_data;
> };
>
> struct intel_connector {
>@@ -1903,11 +1921,14 @@ void intel_hdcp_atomic_check(struct
>drm_connector *connector,
>struct drm_connector_state *old_state,
>struct drm_connector_state *new_state); int
>intel_hdcp_init(struct intel_connector *connector,
>- const struct intel_hdcp_shim *hdcp_shim);
>+ const struct intel_hdcp_shim *hdcp_shim,
>+ bool hdcp2_supported);
> int intel_hdcp_enable(struct intel_connector *connector); int
>intel_hdcp_disable(struct intel_connector *connector); int
>intel_hdcp_check_link(struct intel_connector *connector); bool
>is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
>+int intel_hdcp_component_init(struct drm_i915_private *dev_priv); bool
>+is_hdcp2_supported(struct drm_i915_private *dev_priv);
>
> /* intel_psr.c */
> #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
>diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
>b/drivers/gpu/drm/i915/intel_hdcp.c
>index 55bc4d423187..cfe915c3f336 100644
>--- a/drivers/gpu/drm/i915/intel_hdcp.c
>+++ b/drivers/gpu/drm/i915/intel_hdcp.c
>@@ -8,13 +8,19 @@
>
> #include
> #include
>+#include
> #include
> #include
>+#include
>
> #include "intel_drv.h"
> #include "i915_reg.h"
>
> #define KEY_LOAD_TRIES5
>+#define GET_MEI_DDI_INDEX(port) (((port) == PORT_A) ? DDI_A : \
>+ (enum
[Intel-gfx] ✓ Fi.CI.IGT: success for Enable Display Stream Compression on eDP/DP (rev2)
== Series Details == Series: Enable Display Stream Compression on eDP/DP (rev2) URL : https://patchwork.freedesktop.org/series/47461/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4599_full -> Patchwork_9820_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9820_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9820_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9820_full: === IGT changes === Warnings igt@kms_cursor_crc@cursor-128x128-onscreen: shard-snb: SKIP -> PASS +2 == Known issues == Here are the changes found in Patchwork_9820_full that come from known issues: === IGT changes === Issues hit igt@gem_ctx_isolation@vcs0-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_flip@wf_vblank-ts-check-interruptible: shard-glk: PASS -> FAIL (fdo#100368) Possible fixes igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: shard-glk: FAIL (fdo#103928) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-kbl: FAIL (fdo#102887, fdo#105363) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4599 -> Patchwork_9820 CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9820: c518575b081fdc62af71f4a8dd8f51d6e74b0527 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9820/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On Tue, Jul 31, 2018 at 10:49 AM Linus Torvalds
wrote:
>
> So the re-use might initialize the fields lazily, not necessarily using a
> ctor.
In particular, the pattern that nf_conntrack uses looks like it is safe.
If you have a well-defined refcount, and use "atomic_inc_not_zero()"
to guard the speculative RCU access section, and use
"atomic_dec_and_test()" in the freeing section, then you should be
safe wrt new allocations.
If you have a completely new allocation that has "random stale
content", you know that it cannot be on the RCU list, so there is no
speculative access that can ever see that random content.
So the only case you need to worry about is a re-use allocation, and
you know that the refcount will start out as zero even if you don't
have a constructor.
So you can think of the refcount itself as always having a zero
constructor, *BUT* you need to be careful with ordering.
In particular, whoever does the allocation needs to then set the
refcount to a non-zero value *after* it has initialized all the other
fields. And in particular, it needs to make sure that it uses the
proper memory ordering to do so.
And in this case, we have
static struct nf_conn *
__nf_conntrack_alloc(struct net *net,
{
...
atomic_set(>ct_general.use, 0);
which is a no-op for the re-use case (whether racing or not, since any
"inc_not_zero" users won't touch it), but initializes it to zero for
the "completely new object" case.
And then, the thing that actually exposes it to the speculative walkers does:
int
nf_conntrack_hash_check_insert(struct nf_conn *ct)
{
...
smp_wmb();
/* The caller holds a reference to this object */
atomic_set(>ct_general.use, 2);
which means that it stays as zero until everything is actually set up,
and then the optimistic walker can use the other fields (including
spinlocks etc) to verify that it's actually the right thing. The
smp_wmb() means that the previous initialization really will be
visible before the object is visible.
Side note: on some architectures it might help to make that "smp_wmb
-> atomic_set()" sequence be am "smp_store_release()" instead. Doesn't
matter on x86, but might matter on arm64.
NOTE! One thing to be very worried about is that re-initializing
whatever RCU lists means that now the RCU walker may be walking on the
wrong list so the walker may do the right thing for this particular
entry, but it may miss walking *other* entries. So then you can get
spurious lookup failures, because the RCU walker never walked all the
way to the end of the right list. That ends up being a much more
subtle bug.
But the nf_conntrack case seems to get that right too, see the restart
in nf_conntrack_find().
So I don't see anything wrong in nf_conntrack.
But yes, using SLAB_TYPESAFE_BY_RCU is very very subtle. But most of
the subtleties have nothing to do with having a constructor, they are
about those "make sure memory ordering wrt refcount is right" and
"restart speculative RCU walk" issues that actually happen regardless
of having a constructor or not.
Linus
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Display Stream Compression on eDP/DP (rev2)
== Series Details ==
Series: Enable Display Stream Compression on eDP/DP (rev2)
URL : https://patchwork.freedesktop.org/series/47461/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4599 -> Patchwork_9820 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47461/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9820:
=== IGT changes ===
Possible regressions
igt@drv_selftest@live_coherency:
{fi-icl-u}: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_9820 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_module_reload@basic-reload-inject:
fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107425)
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: PASS -> DMESG-WARN (fdo#107139, fdo#105128)
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: PASS -> FAIL (fdo#104008)
Possible fixes
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-WARN (fdo#107372) -> DMESG-FAIL (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
== Participating hosts (50 -> 46) ==
Additional (1): fi-gdg-551
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-byt-clapper
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4599 -> Patchwork_9820
CI_DRM_4599: 64f0c5b2bf42d83cab790c4607d08d06a9e50e82 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9820: c518575b081fdc62af71f4a8dd8f51d6e74b0527 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c518575b081f drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
93dd5a51c49a drm/i915/dp: Configure Display stream splitter registers during
DSC enable
74c50a243b19 drm/i915/icl: Add Display Stream Splitter control registers
3e5086ab7ce0 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
2fb6aeab6aeb drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
363456f7ee95 drm/i915/dp: Configure i915 Picture parameter Set registers during
DSC enabling
aa794586ed2a drm/i915/dp: Enable/Disable DSC in DP Sink
019eec0259af drm/i915/dsc: Compute Rate Control parameters for DSC
e1de0bb838ae drm/i915/dsc: Define & Compute VESA DSC params
296fd9b47516 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
ea64a4506689 drm/i915/dp: Do not enable PSR2 if DSC is enabled
797cfde71a78 drm/i915/dp: Compute DSC pipe config in atomic check
aa96679ec57e drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
411f986ec2b2 drm/dsc: Add helpers for DSC picture parameter set infoframes
d93be48c680f drm/dsc: Define Rate Control values that do not change over
configurations
dfce08e3cd4a drm/dsc: Define VESA Display Stream Compression Capabilities
4e91c7ad5834 drm/dsc: Define Display Stream Compression PPS infoframe
518d81d5eff2 drm/dp: Define payload size for DP SDP PPS packet
aead51650cbe drm/i915/dp: Validate modes using max Output BPP and slice count
when DSC supported
08e091309edb drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
0081fe19d05d drm/dp: DRM DP helper/macros to get DP sink DSC parameters
5c8ad85804c4 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP
Init
27c39427ec85 drm/dp: Add DP DSC DPCD receiver capability size define and
missing SHIFT
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9820/issues.html
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Display Stream Compression on eDP/DP (rev2)
== Series Details == Series: Enable Display Stream Compression on eDP/DP (rev2) URL : https://patchwork.freedesktop.org/series/47461/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Okay! Commit: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Okay! Commit: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Okay! Commit: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC +drivers/gpu/drm/i915/intel_dp.c:4133:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4133:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4175:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4175:27: warning: expression using sizeof(void) Commit: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Okay! Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:197:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:197:61:got unsigned short [unsigned] [usertype] +drivers/gpu/drm/drm_dsc.c:197:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:203:63:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:203:63:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:203:63: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:203:63: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:203:63: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:203:63: warning: incorrect type in argument 1 (different base types) Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3653:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3654:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1905:23: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:369:39: warning: expression using sizeof(void) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3654:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3656:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/icl: Add Display Stream Splitter control registers Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits +drivers/gpu/drm/i915/intel_vdsc.c:1050:6: warning: symbol 'intel_dsc_disable' was not declared. Should it be static? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On Tue, 31 Jul 2018, Andrey Ryabinin wrote: > Guys, it seems that we have a lot of code using SLAB_TYPESAFE_BY_RCU cache > without constructor. > I think it's nearly impossible to use that combination without having bugs. > It's either you don't really need the SLAB_TYPESAFE_BY_RCU, or you need to > have a constructor in kmem_cache. > > Could you guys, please, verify your code if it's really need SLAB_TYPSAFE or > constructor? > > E.g. the netlink code look extremely suspicious: > > /* >* Do not use kmem_cache_zalloc(), as this cache uses >* SLAB_TYPESAFE_BY_RCU. >*/ > ct = kmem_cache_alloc(nf_conntrack_cachep, gfp); > if (ct == NULL) > goto out; > > spin_lock_init(>lock); > > If nf_conntrack_cachep objects really used in rcu typesafe manner, than 'ct' > returned by kmem_cache_alloc might still be > in use by another cpu. So we just reinitialize spin_lock used by someone else? ct may still be read by another cpu in a RCU section but the object was freed elsewhere so no other processor may modify the object. The lock must have been released before freeing the slab object and thus the initialization of the spinlock is unnecessary if it was initialized in ctor. If there is refcounting going on then why use SLAB_TYPESAFE_BY_RCU? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On Tue, Jul 31, 2018 at 10:36 AM Christopher Lameter wrote: > > If there is refcounting going on then why use SLAB_TYPESAFE_BY_RCU? .. because the object can be accessed (by RCU) after the refcount has gone down to zero, and the thing has been released. That's the whole and only point of SLAB_TYPESAFE_BY_RCU. That flag basically says: "I may end up accessing this object *after* it has been free'd, because there may be RCU lookups in flight" This has nothing to do with constructors. It's ok if the object gets reused as an object of the same type and does *not* get re-initialized, because we're perfectly fine seeing old stale data. What it guarantees is that the slab isn't shared with any other kind of object, _and_ that the underlying pages are free'd after an RCU quiescent period (so the pages aren't shared with another kind of object either during an RCU walk). And it doesn't necessarily have to have a constructor, because the thing that a RCU walk will care about is (a) guaranteed to be an object that *has* been on some RCU list (so it's not a "new" object) (b) the RCU walk needs to have logic to verify that it's still the *same* object and hasn't been re-used as something else. So the re-use might initialize the fields lazily, not necessarily using a ctor. And the point of using SLAB_TYPESAFE_BY_RCU is that using the more traditional RCU freeing - where you free each object one by one with an RCU delay - can be prohibitively slow and have a huge memory overhead (because of big chunks of memory that are queued for freeing). In contrast, a SLAB_TYPESAFE_BY_RCU memory gets free'd and re-used immediately, but because it gets reused as the same kind of object, the RCU walker can "know" what parts have meaning for re-use, in a way it couidn't if the re-use was random. That said, it *is* subtle, and people should be careful. Linus ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Display Stream Compression on eDP/DP (rev2)
== Series Details ==
Series: Enable Display Stream Compression on eDP/DP (rev2)
URL : https://patchwork.freedesktop.org/series/47461/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
27c39427ec85 drm/dp: Add DP DSC DPCD receiver capability size define and
missing SHIFT
5c8ad85804c4 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP
Init
-:62: CHECK:SPACING: No space is necessary after a cast
#62: FILE: drivers/gpu/drm/i915/intel_dp.c:3898:
+ (int) sizeof(intel_dp->dsc_dpcd),
total: 0 errors, 0 warnings, 1 checks, 63 lines checked
0081fe19d05d drm/dp: DRM DP helper/macros to get DP sink DSC parameters
08e091309edb drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#24:
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
-:115: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#115: FILE: drivers/gpu/drm/i915/intel_dp.c:4150:
+* fractional part is 0 */
total: 0 errors, 2 warnings, 0 checks, 131 lines checked
aead51650cbe drm/i915/dp: Validate modes using max Output BPP and slice count
when DSC supported
518d81d5eff2 drm/dp: Define payload size for DP SDP PPS packet
4e91c7ad5834 drm/dsc: Define Display Stream Compression PPS infoframe
-:21: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#21:
new file mode 100644
-:26: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#26: FILE: include/drm/drm_dsc.h:1:
+/*
total: 0 errors, 2 warnings, 0 checks, 365 lines checked
dfce08e3cd4a drm/dsc: Define VESA Display Stream Compression Capabilities
d93be48c680f drm/dsc: Define Rate Control values that do not change over
configurations
411f986ec2b2 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#19:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#69:
new file mode 100644
-:74: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#74: FILE: drivers/gpu/drm/drm_dsc.c:1:
+/*
-:210: WARNING:LONG_LINE: line over 100 characters
#210: FILE: drivers/gpu/drm/drm_dsc.c:137:
+ pps_sdp->pps_payload.scale_increment_interval =
cpu_to_be16(dsc_cfg->scale_increment_interval);
-:213: WARNING:LONG_LINE: line over 100 characters
#213: FILE: drivers/gpu/drm/drm_dsc.c:140:
+ pps_sdp->pps_payload.scale_decrement_interval_high =
(u8)((dsc_cfg->scale_decrement_interval &
-:214: WARNING:LONG_LINE: line over 100 characters
#214: FILE: drivers/gpu/drm/drm_dsc.c:141:
+
DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
-:276: WARNING:LONG_LINE: line over 100 characters
#276: FILE: drivers/gpu/drm/drm_dsc.c:203:
+ pps_sdp->pps_payload.rc_range_parameters[i] =
cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
total: 0 errors, 7 warnings, 0 checks, 285 lines checked
aa96679ec57e drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
797cfde71a78 drm/i915/dp: Compute DSC pipe config in atomic check
-:122: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#122: FILE: drivers/gpu/drm/i915/intel_dp.c:1909:
+ bpp = 3*bpc;
^
-:183: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#183: FILE: drivers/gpu/drm/i915/intel_dp.c:2016:
+ } else {
+
-:205: CHECK:BRACES: braces {} should be used on all arms of this statement
#205: FILE: drivers/gpu/drm/i915/intel_dp.c:2038:
+ if (pipe_config->dsc_params.slice_count > 1)
[...]
+ else {
[...]
-:207: CHECK:BRACES: Unbalanced braces around else statement
#207: FILE: drivers/gpu/drm/i915/intel_dp.c:2040:
+ else {
total: 0 errors, 0 warnings, 4 checks, 256 lines checked
ea64a4506689 drm/i915/dp: Do not enable PSR2 if DSC is enabled
296fd9b47516 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
e1de0bb838ae drm/i915/dsc: Define & Compute VESA DSC params
-:82: WARNING:MISSING_SPACE: break quoted strings at a space character
#82: FILE: drivers/gpu/drm/i915/intel_dp.c:2047:
+ DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp =
%d"
+ "Compressed BPP = %d\n",
-:100: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#100: FILE: drivers/gpu/drm/i915/intel_drv.h:1756:
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
-:106: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS
[Intel-gfx] [PATCH v2] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice ocunt and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_display.c | 20 +++--
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 141 +++
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
4 files changed, 142 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 577b30d..de895ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6460,7 +6460,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
- intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+ intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
link_bw, _config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6697,17 +6697,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool reduce_m_n)
{
m_n->tu = 64;
- compute_m_n(bits_per_pixel * pixel_clock,
- link_clock * nlanes * 8,
- _n->gmch_m, _n->gmch_n,
- reduce_m_n);
+ /* For DSC, Data M/N calculation uses compressed BPP */
+ if (compressed_bpp)
+ compute_m_n(compressed_bpp * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ reduce_m_n);
+ else
+ compute_m_n(bits_per_pixel * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ reduce_m_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 0a79a46..ba013e4 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -360,7 +360,8 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool reduce_m_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c86c8f4..fb179f1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1897,6 +1899,16 @@ static int intel_dp_compute_bpp(struct intel_dp
*intel_dp,
}
}
+ /* If DSC is supported, use the max value reported by panel */
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ bpc = min_t(u8,
+ drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd),
+ DP_DSC_MAX_SUPPORTED_BPC);
+ if (!bpc)
+ bpp = 3*bpc;
+ }
+
return bpp;
}
@@ -1957,14 +1969,11 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
link_clock =
[Intel-gfx] SLAB_TYPESAFE_BY_RCU without constructors (was Re: [PATCH v4 13/17] khwasan: add hooks implementation)
On 07/31/2018 07:04 PM, Andrey Ryabinin wrote: >> Somewhat offtopic, but I can't understand how SLAB_TYPESAFE_BY_RCU >> slabs can be useful without ctors or at least memset(0). Objects in >> such slabs need to be type-stable, but I can't understand how it's >> possible to establish type stability without a ctor... Are these bugs? > > Yeah, I puzzled by this too. However, I think it's hard but possible to make > it work, at least in theory. > There must be an initializer, which consists of two parts: > a) initilize objects fields > b) expose object to the world (add it to list or something like that) > > (a) part must somehow to be ok to race with another cpu which might already > use the object. > (b) part must must use e.g. barriers to make sure that racy users will see > previously inilized fields. > Racy users must have parring barrier of course. > > But it sound fishy, and very easy to fuck up. I won't be surprised if every > single one SLAB_TYPESAFE_BY_RCU user > without ->ctor is bogus. It certainly would be better to convert those to use > ->ctor. > > Such caches seems used by networking subsystem in proto_register(): > > prot->slab = kmem_cache_create_usercopy(prot->name, > prot->obj_size, 0, > SLAB_HWCACHE_ALIGN | SLAB_ACCOUNT | > prot->slab_flags, > prot->useroffset, prot->usersize, > NULL); > > And certain protocols specify SLAB_TYPESAFE_BY_RCU in ->slab_flags, such as: > llc_proto, smc_proto, smc_proto6, tcp_prot, tcpv6_prot, dccp_v6_prot, > dccp_v4_prot. > > > Also nf_conntrack_cachep, kernfs_node_cache, jbd2_journal_head_cache and > i915_request cache. > [+CC maintainer of the relevant code.] Guys, it seems that we have a lot of code using SLAB_TYPESAFE_BY_RCU cache without constructor. I think it's nearly impossible to use that combination without having bugs. It's either you don't really need the SLAB_TYPESAFE_BY_RCU, or you need to have a constructor in kmem_cache. Could you guys, please, verify your code if it's really need SLAB_TYPSAFE or constructor? E.g. the netlink code look extremely suspicious: /* * Do not use kmem_cache_zalloc(), as this cache uses * SLAB_TYPESAFE_BY_RCU. */ ct = kmem_cache_alloc(nf_conntrack_cachep, gfp); if (ct == NULL) goto out; spin_lock_init(>lock); If nf_conntrack_cachep objects really used in rcu typesafe manner, than 'ct' returned by kmem_cache_alloc might still be in use by another cpu. So we just reinitialize spin_lock used by someone else? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/skl: distribute DDB based on panel resolution (rev2)
== Series Details == Series: drm/i915/skl: distribute DDB based on panel resolution (rev2) URL : https://patchwork.freedesktop.org/series/47428/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4598_full -> Patchwork_9819_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9819_full that come from known issues: === IGT changes === Issues hit igt@gem_ctx_isolation@vcs0-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_universal_plane@cursor-fb-leak-pipe-b: shard-apl: PASS -> FAIL (fdo#107241) Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105189) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS +1 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#107241 https://bugs.freedesktop.org/show_bug.cgi?id=107241 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4598 -> Patchwork_9819 CI_DRM_4598: dc620be7ec801cea836a872f8a63469909562312 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9819: 74e1f9e3424ca18587c45314cfe562dc76db33b4 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9819/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/skl: distribute DDB based on panel resolution (rev2)
== Series Details ==
Series: drm/i915/skl: distribute DDB based on panel resolution (rev2)
URL : https://patchwork.freedesktop.org/series/47428/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4598 -> Patchwork_9819 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47428/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_9819 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_hangcheck:
fi-kbl-7567u: PASS -> DMESG-FAIL (fdo#106560, fdo#106947)
igt@drv_selftest@live_workarounds:
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
Possible fixes
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-skl-6260u: INCOMPLETE (fdo#104108) -> PASS
{igt@kms_psr@primary_mmap_gtt}:
fi-cnl-psr: DMESG-WARN (fdo#107372) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (51 -> 46) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-byt-clapper
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4598 -> Patchwork_9819
CI_DRM_4598: dc620be7ec801cea836a872f8a63469909562312 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9819: 74e1f9e3424ca18587c45314cfe562dc76db33b4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
74e1f9e3424c drm/i915/skl: distribute DDB based on panel resolution
2e027cb6e438 drm/i915: ddb_size is of u16 type
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9819/issues.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Interactive RPS mode (rev5)
== Series Details == Series: drm/i915: Interactive RPS mode (rev5) URL : https://patchwork.freedesktop.org/series/46334/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4597_full -> Patchwork_9818_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9818_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-snb: PASS -> FAIL (fdo#106886) igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: PASS -> FAIL (fdo#102887) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) shard-kbl: PASS -> FAIL (fdo#99912) igt@kms_universal_plane@cursor-fb-leak-pipe-b: shard-apl: PASS -> FAIL (fdo#107241) igt@pm_rps@min-max-config-loaded: shard-apl: PASS -> FAIL (fdo#102250) shard-glk: PASS -> FAIL (fdo#102250) Possible fixes igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: shard-glk: FAIL (fdo#103928) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-glk: FAIL (fdo#103375) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107241 https://bugs.freedesktop.org/show_bug.cgi?id=107241 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4597 -> Patchwork_9818 CI_DRM_4597: 25409b97e5c944ac473092da917513d0de862db5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9818: 93827b4e697a0069a4dca914b233b7c1878954b4 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9818/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/skl: distribute DDB based on panel resolution
We distribute DDB equally among all pipes irrespective of display
buffer requirement of each pipe. This leads to a situation where high
resolution y-tiled display can not be enabled with 2 low resolution
displays.
Main contributing factor for DDB requirement is width of the display.
This patch make changes to distribute ddb based on display width.
So display with higher width will get bigger chunk of DDB.
Changes Since V1:
- pipe_size/ddb_size will not overflow u16 so use appropriate
data-types during computation (Chris)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107113
Cc: raviraj.p.sita...@intel.com
Cc: Chris Wilson
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 54 +++--
1 file changed, 41 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 91120560a61b..3a0b5a60f73c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3814,8 +3814,13 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev,
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_crtc *for_crtc = cstate->base.crtc;
+ const struct drm_crtc_state *crtc_state;
+ const struct drm_crtc *crtc;
+ u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
+ enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 pipe_size, ddb_size;
- int nth_active_pipe;
+ u16 ddb_size_before_pipe;
+ u32 i;
if (WARN_ON(!state) || !cstate->base.active) {
alloc->start = 0;
@@ -3833,14 +3838,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev,
*num_active, ddb);
/*
-* If the state doesn't change the active CRTC's, then there's
-* no need to recalculate; the existing pipe allocation limits
-* should remain unchanged. Note that we're safe from racing
-* commits since any racing commit that changes the active CRTC
-* list would need to grab _all_ crtc locks, including the one
-* we currently hold.
+* If the state doesn't change the active CRTC's or there is no
+* modeset request, then there's no need to recalculate;
+* the existing pipe allocation limits should remain unchanged.
+* Note that we're safe from racing commits since any racing commit
+* that changes the active CRTC list or do modeset would need to
+* grab _all_ crtc locks, including the one we currently hold.
*/
- if (!intel_state->active_pipe_changes) {
+ if (!intel_state->active_pipe_changes && !intel_state->modeset) {
/*
* alloc may be cleared by clear_intel_crtc_state,
* copy from old state to be sure
@@ -3849,10 +3854,33 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev,
return;
}
- nth_active_pipe = hweight32(intel_state->active_crtcs &
- (drm_crtc_mask(for_crtc) - 1));
- pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
- alloc->start = nth_active_pipe * ddb_size / *num_active;
+ /*
+* Watermark/ddb requirement highly depends upon width of the
+* framebuffer, So instead of allocating DDB equally among pipes
+* distribute DDB based on resolution/width of the display.
+*/
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ const struct drm_display_mode *adjusted_mode;
+ int hdisplay, vdisplay;
+ enum pipe pipe;
+
+ if (!crtc_state->enable)
+ continue;
+
+ pipe = to_intel_crtc(crtc)->pipe;
+ adjusted_mode = _state->adjusted_mode;
+ drm_mode_get_hv_timing(adjusted_mode, , );
+ total_width += hdisplay;
+
+ if (pipe < for_pipe)
+ width_before_pipe += hdisplay;
+ else if (pipe == for_pipe)
+ pipe_width = hdisplay;
+ }
+
+ ddb_size_before_pipe = (ddb_size * width_before_pipe) / total_width;
+ pipe_size = (ddb_size * pipe_width) / total_width;
+ alloc->start = ddb_size_before_pipe;
alloc->end = alloc->start + pipe_size;
}
@@ -5259,7 +5287,7 @@ skl_ddb_add_affected_pipes(struct drm_atomic_state
*state, bool *changed)
* any other display updates race with this transaction, so we need
* to grab the lock on *all* CRTC's.
*/
- if (intel_state->active_pipe_changes) {
+ if (intel_state->active_pipe_changes || intel_state->modeset) {
realloc_pipes = ~0;
intel_state->wm_results.dirty_pipes = ~0;
}
--
2.16.2
___
Intel-gfx
[Intel-gfx] [PATCH v1 1/2] drm/i915: ddb_size is of u16 type
ddb_size is u16 so use same return type for intel_get_ddb_size
wrapper.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7312ecb73415..91120560a61b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3771,11 +3771,11 @@ bool intel_can_enable_sagv(struct drm_atomic_state
*state)
return true;
}
-static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *cstate,
- const unsigned int total_data_rate,
- const int num_active,
- struct skl_ddb_allocation *ddb)
+static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *cstate,
+ const unsigned int total_data_rate,
+ const int num_active,
+ struct skl_ddb_allocation *ddb)
{
const struct drm_display_mode *adjusted_mode;
u64 total_data_bw;
@@ -3814,7 +3814,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_crtc *for_crtc = cstate->base.crtc;
- unsigned int pipe_size, ddb_size;
+ u16 pipe_size, ddb_size;
int nth_active_pipe;
if (WARN_ON(!state) || !cstate->base.active) {
--
2.16.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/2] distribute DDB based on panel resolution
This series make changes to distribute DDB based on resolution of panel instead of dividing equally among pipes. Mahesh Kumar (2): drm/i915: ddb_size is of u16 type drm/i915/skl: distribute DDB based on panel resolution drivers/gpu/drm/i915/intel_pm.c | 66 + 1 file changed, 47 insertions(+), 19 deletions(-) -- 2.16.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0
Hi, On 7/28/2018 11:18 AM, Rodrigo Vivi wrote: On Fri, Jul 27, 2018 at 11:40:14AM +0530, Kumar, Mahesh wrote: Hi Matt, On 7/27/2018 9:21 AM, Matt Turner wrote: On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: Bspec: 4381 Do we know that these numbers are stable? yes these numbers are fixed in Bspec I don't know if this form is common in the kernel, but in Mesa we specify the name of the page which should always allow readers to find it. This is common practice in kernel to give Bspec Number reference instead of name of the page. Well, I believe Matt has a good point here. It is stable for now and for a while, but we had seen changes on the web interface in use. Also this number doesn't help devs who don't use the web interface. sure, will update this in next version. Will float updated series once receive review comments on other patches. -Mahesh -Mahesh ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Interactive RPS mode (rev5)
== Series Details ==
Series: drm/i915: Interactive RPS mode (rev5)
URL : https://patchwork.freedesktop.org/series/46334/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4597 -> Patchwork_9818 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/46334/revisions/5/mbox/
== Known issues ==
Here are the changes found in Patchwork_9818 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_coherency:
{fi-icl-u}: PASS -> DMESG-FAIL (fdo#107435)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-skl-6600u: DMESG-FAIL (fdo#106560, fdo#107174) -> PASS
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107435 https://bugs.freedesktop.org/show_bug.cgi?id=107435
== Participating hosts (53 -> 45) ==
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-kbl-8809g fi-byt-clapper
== Build changes ==
* Linux: CI_DRM_4597 -> Patchwork_9818
CI_DRM_4597: 25409b97e5c944ac473092da917513d0de862db5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9818: 93827b4e697a0069a4dca914b233b7c1878954b4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
93827b4e697a drm/i915: Interactive RPS mode
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9818/issues.html
___
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[Intel-gfx] [PATCH 2/2] drm/i915/psr: Add debugfs support to force toggling PSR1/2 mode.
This will make it easier to test PSR1 on PSR2 capable eDP machines.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_psr.c | 27 ---
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef04b6cd7863..07783b9e7960 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -617,6 +617,8 @@ struct i915_psr {
#define I915_PSR_DEBUG_DEFAULT (0 << 1)
#define I915_PSR_DEBUG_DISABLE (1 << 1)
#define I915_PSR_DEBUG_ENABLE (2 << 1)
+#define I915_PSR_DEBUG_FORCE_PSR1 (3 << 1)
+#define I915_PSR_DEBUG_FORCE_PSR2 (4 << 1)
u32 debug;
bool sink_support;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7848829094ca..4cf4ac7068d0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -813,19 +813,38 @@ static bool __psr_wait_for_idle_locked(struct
drm_i915_private *dev_priv)
return err == 0 && dev_priv->psr.enabled;
}
+static bool switching_psr(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *crtc_state,
+ u32 mode)
+{
+ /* Can't switch psr state anyway if PSR2 is not supported. */
+ if (!crtc_state || !crtc_state->has_psr2)
+ return false;
+
+ if (dev_priv->psr.psr2_enabled && mode == I915_PSR_DEBUG_FORCE_PSR1)
+ return true;
+
+ if (!dev_priv->psr.psr2_enabled && mode != I915_PSR_DEBUG_FORCE_PSR1)
+ return true;
+
+ return false;
+}
+
int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
struct drm_modeset_acquire_ctx *ctx,
u64 val)
{
struct drm_device *dev = _priv->drm;
struct drm_connector_state *conn_state;
+ struct intel_crtc_state *crtc_state = NULL;
struct drm_crtc *crtc;
struct intel_dp *dp;
int ret;
bool enable;
+ u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
- (val & I915_PSR_DEBUG_MODE_MASK) > I915_PSR_DEBUG_ENABLE) {
+ mode > I915_PSR_DEBUG_FORCE_PSR2) {
DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);
return -EINVAL;
}
@@ -843,7 +862,8 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private
*dev_priv,
if (ret)
return ret;
- ret =
wait_for_completion_interruptible(>state->commit->hw_done);
+ crtc_state = to_intel_crtc_state(crtc->state);
+ ret =
wait_for_completion_interruptible(_state->base.commit->hw_done);
} else
ret =
wait_for_completion_interruptible(_state->commit->hw_done);
@@ -856,10 +876,11 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private
*dev_priv,
enable = psr_global_enabled(val);
- if (!enable)
+ if (!enable || switching_psr(dev_priv, crtc_state, mode))
intel_psr_disable_locked(dev_priv->psr.dp);
dev_priv->psr.debug = val;
+ dev_priv->psr.psr2_enabled = mode != I915_PSR_DEBUG_FORCE_PSR1 &&
crtc_state->has_psr2;
intel_psr_irq_control(dev_priv, dev_priv->psr.debug &
I915_PSR_DEBUG_IRQ);
if (dev_priv->psr.prepared && enable)
--
2.18.0
___
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[Intel-gfx] [PATCH 1/2] drm/i915: Allow control of PSR at runtime through debugfs, v4.
Currently tests modify i915.enable_psr and then do a modeset cycle
to change PSR. We can write a value to i915_edp_psr_debug to force
a certain PSR mode without a modeset.
To retain compatibility with older userspace, we also still allow
the override through the module parameter, and add some tracking
to check whether a debugfs mode is specified.
Changes since v1:
- Rename dev_priv->psr.enabled to .dp, and .hw_configured to .enabled.
- Fix i915_psr_debugfs_mode to match the writes to debugfs.
- Rename __i915_edp_psr_write to intel_psr_set_debugfs_mode, simplify
it and move it to intel_psr.c. This keeps all internals in intel_psr.c
- Perform an interruptible wait for hw completion outside of the psr
lock, instead of being forced to trywait and return -EBUSY.
Changes since v2:
- Rebase on top of intel_psr changes.
Changes since v3:
- Assign psr.dp during init. (dhnkrn)
- Add prepared bool, which should be used instead of relying on psr.dp. (dhnkrn)
- Fix -EDEADLK handling in debugfs. (dhnkrn)
- Clean up waiting for idle in intel_psr_set_debugfs_mode.
- Print PSR mode when trying to enable PSR. (dhnkrn)
- Move changing psr debug setting to i915_edp_psr_debug_set. (dhnkrn)
Signed-off-by: Maarten Lankhorst
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 -
drivers/gpu/drm/i915/i915_drv.h | 12 ++-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h| 5 +-
drivers/gpu/drm/i915/intel_psr.c| 136 +++-
5 files changed, 144 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 59dc0610ea44..a7e927413e8e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2705,7 +2705,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
intel_runtime_pm_get(dev_priv);
mutex_lock(_priv->psr.lock);
- seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
+ seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
dev_priv->psr.busy_frontbuffer_bits);
@@ -2747,14 +2747,29 @@ static int
i915_edp_psr_debug_set(void *data, u64 val)
{
struct drm_i915_private *dev_priv = data;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret;
if (!CAN_PSR(dev_priv))
return -ENODEV;
- DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
+ DRM_DEBUG_KMS("Setting PSR debug to %llx\n", val);
intel_runtime_pm_get(dev_priv);
- intel_psr_irq_control(dev_priv, !!val);
+
+ drm_modeset_acquire_init(, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
+
+retry:
+ ret = intel_psr_set_debugfs_mode(dev_priv, , val);
+ if (ret == -EDEADLK) {
+ ret = drm_modeset_backoff();
+ if (!ret)
+ goto retry;
+ }
+
+ drm_modeset_drop_locks();
+ drm_modeset_acquire_fini();
+
intel_runtime_pm_put(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f49f9988dfa..ef04b6cd7863 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -611,8 +611,17 @@ struct i915_drrs {
struct i915_psr {
struct mutex lock;
+
+#define I915_PSR_DEBUG_IRQ BIT(0)
+#define I915_PSR_DEBUG_MODE_MASK (7 << 1)
+#define I915_PSR_DEBUG_DEFAULT (0 << 1)
+#define I915_PSR_DEBUG_DISABLE (1 << 1)
+#define I915_PSR_DEBUG_ENABLE (2 << 1)
+
+ u32 debug;
bool sink_support;
- struct intel_dp *enabled;
+ bool prepared, enabled;
+ struct intel_dp *dp;
bool active;
struct work_struct work;
unsigned busy_frontbuffer_bits;
@@ -622,7 +631,6 @@ struct i915_psr {
bool alpm;
bool psr2_enabled;
u8 sink_sync_latency;
- bool debug;
ktime_t last_entry_attempt;
ktime_t last_exit;
};
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5dadefca2ad2..defd696e71fc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4051,7 +4051,7 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
if (IS_HASWELL(dev_priv)) {
gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ intel_psr_irq_control(dev_priv, dev_priv->psr.debug &
I915_PSR_DEBUG_IRQ);
display_mask |= DE_EDP_PSR_INT_HSW;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 99a5f5be5b82..f4cfb7ed2262 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1930,6 +1930,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Interactive RPS mode (rev5)
== Series Details == Series: drm/i915: Interactive RPS mode (rev5) URL : https://patchwork.freedesktop.org/series/46334/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Interactive RPS mode -O:drivers/gpu/drm/i915/i915_irq.c:1265:22: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_irq.c:1265:22: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_irq.c:1265:22: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_irq.c:1265:22: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3645:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3653:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Interactive RPS mode (rev5)
== Series Details ==
Series: drm/i915: Interactive RPS mode (rev5)
URL : https://patchwork.freedesktop.org/series/46334/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
93827b4e697a drm/i915: Interactive RPS mode
-:27: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit e9af4ea2b9e7 ("drm/i915: Avoid
waitboosting on the active request")'
#27:
full throttle and upclock the GPU to max. But in commit e9af4ea2b9e7, we
-:124: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#124: FILE: drivers/gpu/drm/i915/i915_drv.h:785:
+ struct mutex mutex;
-:139: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#139: FILE: drivers/gpu/drm/i915/i915_drv.h:3431:
+extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
total: 1 errors, 0 warnings, 2 checks, 257 lines checked
___
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[Intel-gfx] [PATCH] drm/i915: Interactive RPS mode
RPS provides a feedback loop where we use the load during the previous
evaluation interval to decide whether to up or down clock the GPU
frequency. Our responsiveness is split into 3 regimes, a high and low
plateau with the intent to keep the gpu clocked high to cover occasional
stalls under high load, and low despite occasional glitches under steady
low load, and inbetween. However, we run into situations like kodi where
we want to stay at low power (video decoding is done efficiently
inside the fixed function HW and doesn't need high clocks even for high
bitrate streams), but just occasionally the pipeline is more complex
than a video decode and we need a smidgen of extra GPU power to present
on time. In the high power regime, we sample at sub frame intervals with
a bias to upclocking, and conversely at low power we sample over a few
frames worth to provide what we consider to be the right levels of
responsiveness respectively. At low power, we more or less expect to be
kicked out to high power at the start of a busy sequence by waitboosting.
Prior to commit e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active
request") whenever we missed the frame or stalled, we would immediate go
full throttle and upclock the GPU to max. But in commit e9af4ea2b9e7, we
relaxed the waitboosting to only apply if the pipeline was deep to avoid
over-committing resources for a near miss. Sadly though, a near miss is
still a miss, and perceptible as jitter in the frame delivery.
To try and prevent the near miss before having to resort to boosting
after the fact, we use the pageflip queue as an indication that we are
in an "interactive" regime and so should sample the load more frequently
to provide power before the frame misses it vblank. This will make us
more favorable to providing a small power increase (one or two bins) as
required rather than going all the way to maximum and then having to
work back down again. (We still keep the waitboosting mechanism around
just in case a dramatic change in system load requires urgent uplocking,
faster than we can provide in a few evaluation intervals.)
v2: Reduce rps_set_interactive to a boolean parameter to avoid the
confusion of what if they wanted a new power mode after pinning to a
different mode (which to choose?)
v3: Only reprogram RPS while the GT is awake, it will be set when we
wake the GT, and while off warns about being used outside of rpm.
v4: Fix deferred application of interactive mode
v5: s/state/interactive/
v6: Group the mutex with its principle in a substruct
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107111
Fixes: e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active request")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Radoslaw Szwichtenberg
Cc: Ville Syrjälä
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 ++--
drivers/gpu/drm/i915/i915_drv.h | 16 +++--
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/intel_display.c | 20 ++
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 101 ++-
6 files changed, 111 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 59dc0610ea44..f9ce35da4123 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1218,7 +1218,8 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
seq_printf(m, "RP PREV UP: %d (%dus)\n",
rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
- seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
+ seq_printf(m, "Up threshold: %d%%\n",
+ rps->power.up_threshold);
seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
@@ -1226,7 +1227,8 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv,
rpcurdown));
seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv,
rpprevdown));
- seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
+ seq_printf(m, "Down threshold: %d%%\n",
+ rps->power.down_threshold);
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
@@ -2218,6 +2220,7 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
seq_printf(m, "Boosts outstanding? %d\n",
atomic_read(>num_waiters));
+ seq_printf(m, "Interactive? %d\n",
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Do not use iowait while waiting for the GPU
Chris Wilson writes:
> A recent trend for cpufreq is to boost the CPU frequencies for
> iowaiters, in particularly to benefit high frequency I/O. We do the same
> and boost the GPU clocks to try and minimise time spent waiting for the
> GPU. However, as the igfx and CPU share the same TDP, boosting the CPU
> frequency will result in the GPU being throttled and its frequency being
> reduced. Thus declaring iowait negatively impacts on GPU throughput.
>
> v2: Both sleeps!
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107410
> References: 52ccc4314293 ("cpufreq: intel_pstate: HWP boost performance on IO
> wakeup")
The commit above has it's own heuristics on when to actual ramp up,
inspecting the interval of io waits.
Regardless of that, with shared tdp, the waiter should not stand in a
way. And that it fixes a regression:
Reviewed-by: Mika Kuoppala
On other way around, the atomic commit code on updating
planes, could potentially benefit of changing to the
io_schedule_timeout. (and/or adopting c state limits)
-Mika
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Eero Tamminen
> Cc: Francisco Jerez
> ---
> drivers/gpu/drm/i915/i915_request.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index f3ff8dbe363d..3e48ea87b324 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1376,7 +1376,7 @@ long i915_request_wait(struct i915_request *rq,
> goto complete;
> }
>
> - timeout = io_schedule_timeout(timeout);
> + timeout = schedule_timeout(timeout);
> } while (1);
>
> GEM_BUG_ON(!intel_wait_has_seqno());
> @@ -1414,7 +1414,7 @@ long i915_request_wait(struct i915_request *rq,
> wait.seqno - 1))
> qos = wait_dma_qos_add();
>
> - timeout = io_schedule_timeout(timeout);
> + timeout = schedule_timeout(timeout);
>
> if (intel_wait_complete() &&
> intel_wait_check_request(, rq))
> --
> 2.18.0
___
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Re: [Intel-gfx] [PATCH] drm/i915: Interactive RPS mode
Quoting Chris Wilson (2018-07-23 13:01:00)
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -784,6 +784,8 @@ struct intel_rps {
>
> int last_adj;
> enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
> + unsigned int interactive;
> + struct mutex power_lock;
Please describe the new mutex with a few words because it's not
immediately obvious which members fall under it.
This kind of a change could always use some Tested-by's.
Reviewed-by: Joonas Lahtinen
Regards, Joonas
___
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Re: [Intel-gfx] [PATCH] firmware/dmc/icl: load v1.07 on icelake.
On Mon, Jul 30, 2018 at 04:57:11PM -0700, Anusha Srivatsa wrote:
> Add Support to load DMC on Icelake.
>
> Cc: Rodrigo Vivi
> Cc: Paulo Zanoni
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_csr.c | 7 +++
> 1 file changed, 7 insertions(+)
the firmware also needs to be loaded during runtime/system resume, by adding
the following to icl_display_core_init(), similarly to other platforms:
if (resume && dev_priv->csr.dmc_payload)
intel_csr_load_program(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index cf9b600..393d419 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -34,6 +34,9 @@
> * low-power state and comes back to normal.
> */
>
> +#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
> +#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> +
> #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
> MODULE_FIRMWARE(I915_CSR_GLK);
> #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
> @@ -301,6 +304,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> *dev_priv,
> if (csr->fw_path == i915_modparams.dmc_firmware_path) {
> /* Bypass version check for firmware override. */
> required_version = csr->version;
> + } else if (IS_ICELAKE(dev_priv)) {
> + required_version = ICL_CSR_VERSION_REQUIRED;
> } else if (IS_CANNONLAKE(dev_priv)) {
> required_version = CNL_CSR_VERSION_REQUIRED;
> } else if (IS_GEMINILAKE(dev_priv)) {
> @@ -458,6 +463,8 @@ void intel_csr_ucode_init(struct drm_i915_private
> *dev_priv)
>
> if (i915_modparams.dmc_firmware_path)
> csr->fw_path = i915_modparams.dmc_firmware_path;
> + else if (IS_ICELAKE(dev_priv))
> + csr->fw_path = I915_CSR_ICL;
> else if (IS_CANNONLAKE(dev_priv))
> csr->fw_path = I915_CSR_CNL;
> else if (IS_GEMINILAKE(dev_priv))
> --
> 2.7.4
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/i915/execlists: Terminate the context image with BB_END
On 30/07/18 17:43, Chris Wilson wrote:
In the aub trace utility, the context images are terminated with a
MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise.
Do the same for our protocontext image for completeness, and in passing
apply the magic bit for gen10 to mark the end of the context image.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Doesn't look like anything exploded.
Have you noticed any improvement maybe in the benchmarks?
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_lrc.c | 4
drivers/gpu/drm/i915/intel_lrc_reg.h | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fad689efb67a..b0be180c6294 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2653,6 +2653,10 @@ static void execlists_init_reg_state(u32 *regs,
i915_oa_init_reg_state(engine, ctx, regs);
}
+
+ regs[CTX_END] = MI_BATCH_BUFFER_END;
+ if (INTEL_GEN(dev_priv) >= 10)
+ regs[CTX_END] |= BIT(0);
}
static int
diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h
b/drivers/gpu/drm/i915/intel_lrc_reg.h
index 169a2239d6c7..5ef932d810a7 100644
--- a/drivers/gpu/drm/i915/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/intel_lrc_reg.h
@@ -37,7 +37,7 @@
#define CTX_PDP0_LDW 0x32
#define CTX_LRI_HEADER_2 0x41
#define CTX_R_PWR_CLK_STATE 0x42
-#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
+#define CTX_END0x44
#define CTX_REG(reg_state, pos, reg, val) do { \
u32 *reg_state__ = (reg_state); \
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Re: [Intel-gfx] [PATCH v6 06/35] drm/i915: Define Intel HDCP2.2 registers
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>Subject: [PATCH v6 06/35] drm/i915: Define Intel HDCP2.2 registers
>
>Intel HDCP2.2 registers are defined with addr offsets and bit details.
>
>v2:
> Replaced the arith calc with _PICK [Sean Paul]
>v3:
> No changes.
>v4:
> %s/HDCP2_CTR_DDI/HDCP2_CTL_DDI [Uma]
>v5:
> Added parentheses for the parameters of macro.
>v6:
> No changes
>
Changes look ok to me.
Reviewed-by: Uma Shankar
>Signed-off-by: Ramalingam C
>Reviewed-by: Sean Paul
>---
> drivers/gpu/drm/i915/i915_reg.h | 32
> 1 file changed, 32 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 0424e45f88db..9f7be54cbd1c 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8856,6 +8856,38 @@ enum skl_power_gate {
> #define HDCP_STATUS_CIPHER BIT(16)
> #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
>
>+/* HDCP2.2 Registers */
>+#define _PORTA_HDCP2_BASE 0x66800
>+#define _PORTB_HDCP2_BASE 0x66500
>+#define _PORTC_HDCP2_BASE 0x66600
>+#define _PORTD_HDCP2_BASE 0x66700
>+#define _PORTE_HDCP2_BASE 0x66A00
>+#define _PORTF_HDCP2_BASE 0x66900
>+#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
>+_PORTA_HDCP2_BASE, \
>+_PORTB_HDCP2_BASE, \
>+_PORTC_HDCP2_BASE, \
>+_PORTD_HDCP2_BASE, \
>+_PORTE_HDCP2_BASE, \
>+_PORTF_HDCP2_BASE) + (x))
>+
>+#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port,
>0x98)
>+#define AUTH_LINK_AUTHENTICATED BIT(31)
>+#define AUTH_LINK_TYPE BIT(30)
>+#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
>+#define AUTH_CLR_KEYS BIT(18)
>+
>+#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
>+#define CTL_LINK_ENCRYPTION_REQ BIT(31)
>+
>+#define HDCP2_STATUS_DDI(port)_PORT_HDCP2_BASE(port,
>0xB4)
>+#define STREAM_ENCRYPTION_STATUS_A BIT(31)
>+#define STREAM_ENCRYPTION_STATUS_B BIT(30)
>+#define STREAM_ENCRYPTION_STATUS_C BIT(29)
>+#define LINK_TYPE_STATUSBIT(22)
>+#define LINK_AUTH_STATUSBIT(21)
>+#define LINK_ENCRYPTION_STATUS BIT(20)
>+
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> #define _TRANS_DDI_FUNC_CTL_B 0x61400
>--
>2.7.4
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Re: [Intel-gfx] [PATCH v6 05/35] drm/i915: wrapping all hdcp var into intel_hdcp
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>Subject: [PATCH v6 05/35] drm/i915: wrapping all hdcp var into intel_hdcp
>
>Considering significant number of HDCP specific variables, it will be clean to
>have
>separate struct for HDCP.
>
>New structure called intel_hdcp is added within intel_connector.
>
>v2:
> struct hdcp statically allocated. [Sean Paul]
> enable and disable function parameters are retained.[Sean Paul]
>v3:
> No Changes.
>v4:
> Commit msg is rephrased [Uma]
>v5:
> Comment for mutex definition.
>v6:
> hdcp_ prefix from all intel_hdcp members are removed [Sean Paul]
> inline function intel_hdcp_to_connector is defined [Sean Paul]
>
Changes look ok to me.
Reviewed-by: Uma Shankar
>Signed-off-by: Ramalingam C
>Reviewed-by: Sean Paul
>---
> drivers/gpu/drm/i915/intel_display.c | 6 +-
> drivers/gpu/drm/i915/intel_drv.h | 15 +++--
> drivers/gpu/drm/i915/intel_hdcp.c| 107 +++
> 3 files changed, 72 insertions(+), 56 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c
>b/drivers/gpu/drm/i915/intel_display.c
>index 8f3199b06d1f..b8106f0fd64b 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -15878,9 +15878,9 @@ static void intel_hpd_poll_fini(struct drm_device
>*dev)
> for_each_intel_connector_iter(connector, _iter) {
> if (connector->modeset_retry_work.func)
> cancel_work_sync(>modeset_retry_work);
>- if (connector->hdcp_shim) {
>- cancel_delayed_work_sync(
>>hdcp_check_work);
>- cancel_work_sync(>hdcp_prop_work);
>+ if (connector->hdcp.shim) {
>+ cancel_delayed_work_sync(
>>hdcp.check_work);
>+ cancel_work_sync(>hdcp.prop_work);
> }
> }
> drm_connector_list_iter_end(_iter);
>diff --git a/drivers/gpu/drm/i915/intel_drv.h
>b/drivers/gpu/drm/i915/intel_drv.h
>index 61e715ddd0d5..c32665136d5d 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -378,6 +378,15 @@ struct intel_hdcp_shim {
> bool *hdcp_capable);
> };
>
>+struct intel_hdcp {
>+ const struct intel_hdcp_shim *shim;
>+ /* Mutex for hdcp state of the connector */
>+ struct mutex mutex;
>+ uint64_t value;
>+ struct delayed_work check_work;
>+ struct work_struct prop_work;
>+};
>+
> struct intel_connector {
> struct drm_connector base;
> /*
>@@ -410,11 +419,7 @@ struct intel_connector {
> /* Work struct to schedule a uevent on link train failure */
> struct work_struct modeset_retry_work;
>
>- const struct intel_hdcp_shim *hdcp_shim;
>- struct mutex hdcp_mutex;
>- uint64_t hdcp_value; /* protected by hdcp_mutex */
>- struct delayed_work hdcp_check_work;
>- struct work_struct hdcp_prop_work;
>+ struct intel_hdcp hdcp;
> };
>
> struct intel_digital_connector_state {
>diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
>b/drivers/gpu/drm/i915/intel_hdcp.c
>index 0cc6a861bcf8..55bc4d423187 100644
>--- a/drivers/gpu/drm/i915/intel_hdcp.c
>+++ b/drivers/gpu/drm/i915/intel_hdcp.c
>@@ -626,6 +626,7 @@ struct intel_digital_port *conn_to_dig_port(struct
>intel_connector *connector)
>
> static int _intel_hdcp_disable(struct intel_connector *connector) {
>+ struct intel_hdcp *hdcp = >hdcp;
> struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
> struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> enum port port = intel_dig_port->base.port; @@ -641,7 +642,7 @@
>static int _intel_hdcp_disable(struct intel_connector *connector)
> return -ETIMEDOUT;
> }
>
>- ret = connector->hdcp_shim->toggle_signalling(intel_dig_port, false);
>+ ret = hdcp->shim->toggle_signalling(intel_dig_port, false);
> if (ret) {
> DRM_ERROR("Failed to disable HDCP signalling\n");
> return ret;
>@@ -653,6 +654,7 @@ static int _intel_hdcp_disable(struct intel_connector
>*connector)
>
> static int _intel_hdcp_enable(struct intel_connector *connector) {
>+ struct intel_hdcp *hdcp = >hdcp;
> struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
> int i, ret, tries = 3;
>
>@@ -677,8 +679,7 @@ static int _intel_hdcp_enable(struct intel_connector
>*connector)
>
> /* Incase of authentication failures, HDCP spec expects reauth. */
> for (i = 0; i < tries; i++) {
>- ret = intel_hdcp_auth(conn_to_dig_port(connector),
>-connector->hdcp_shim);
>+ ret =
Re: [Intel-gfx] [PATCH v6 04/35] linux/mei: Header for mei_hdcp driver interface
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>Subject: [PATCH v6 04/35] linux/mei: Header for mei_hdcp driver interface
>
>Data structures and Enum for the I915-MEI_HDCP interface are defined at
>
>
>v2:
> Rebased.
>v3:
> mei_cl_device is removed from mei_hdcp_data [Tomas]
>v4:
> Comment style and typo fixed [Uma]
>v5:
> Rebased.
>v6:
> No changes.
>
>Signed-off-by: Ramalingam C
>---
> include/linux/mei_hdcp.h | 100
>+++
> 1 file changed, 100 insertions(+)
> create mode 100644 include/linux/mei_hdcp.h
>
>diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h new file mode
>100644 index ..f993e389d7cf
>--- /dev/null
>+++ b/include/linux/mei_hdcp.h
>@@ -0,0 +1,100 @@
>+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
>+/*
>+ * Copyright © 2017-2018 Intel Corporation
>+ *
>+ * Permission to use, copy, modify, distribute, and sell this software
>+and its
>+ * documentation for any purpose is hereby granted without fee,
>+provided that
>+ * the above copyright notice appear in all copies and that both that
>+copyright
>+ * notice and this permission notice appear in supporting
>+documentation, and
>+ * that the name of the copyright holders not be used in advertising or
>+ * publicity pertaining to distribution of the software without
>+specific,
>+ * written prior permission. The copyright holders make no
>+representations
>+ * about the suitability of this software for any purpose. It is
>+provided "as
>+ * is" without express or implied warranty.
>+ *
>+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO
>THIS
>+SOFTWARE,
>+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
>IN
>+NO
>+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL,
>+INDIRECT OR
>+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING
>FROM LOSS
>+OF USE,
>+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
>+OTHER
>+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
>+PERFORMANCE
>+ * OF THIS SOFTWARE.
>+ *
>+ * Authors:
>+ *Ramalingam C
>+ */
>+
>+#ifndef _LINUX_MEI_HDCP_H
>+#define _LINUX_MEI_HDCP_H
>+
>+#include
>+
>+/*
>+ * Enumeration of the physical DDI available on the platform */ enum
No need of multi line comment style.
>+hdcp_physical_port {
>+ INVALID_PORT = 0x00,/* Not a valid port */
>+
>+ DDI_RANGE_BEGIN = 0x01, /* Beginning of the valid DDI port range
>*/
>+ DDI_B = 0x01, /* Port DDI B */
>+ DDI_C = 0x02, /* Port DDI C */
>+ DDI_D = 0x03, /* Port DDI D */
>+ DDI_E = 0x04, /* Port DDI E */
>+ DDI_F = 0x05, /* Port DDI F */
>+ DDI_A = 0x07, /* Port DDI A */
>+ DDI_RANGE_END = DDI_A,/* End of the valid DDI port range */
>+};
>+
>+/* The types of HDCP 2.2 ports supported */ enum
>+hdcp_integrated_port_type {
>+ HDCP_INVALID_TYPE = 0x00,
>+
>+ /* HDCP 2.x ports that are integrated into Intel HW */
>+ INTEGRATED = 0x01,
>+
>+ /* HDCP2.2 discrete wired Tx port with LSPCON (HDMI 2.0) solution */
>+ LSPCON = 0x02,
>+
>+ /* HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3) solution */
>+ CPDP= 0x03,
>+};
>+
>+/*
>+ * wired_protocol: Supported integrated wired HDCP protocol.
>+ * Based on this value, Minor difference needed between wired
>+specifications
>+ * are handled.
>+ */
>+enum hdcp_protocol {
>+ HDCP_PROTOCOL_INVALID,
>+ HDCP_PROTOCOL_HDMI,
>+ HDCP_PROTOCOL_DP
>+};
>+
>+/*
>+ * mei_hdcp_data: Input data to the mei_hdcp APIs.
>+ */
No need of multi line comment.
With above comments addressed.
Reviewed-by: Uma Shankar
>+struct mei_hdcp_data {
>+ enum hdcp_physical_port port;
>+ enum hdcp_integrated_port_type port_type;
>+ enum hdcp_protocol protocol;
>+
>+ /*
>+ * No of streams transmitted on a port.
>+ * In case of HDMI & DP SST, single stream will be
>+ * transmitted on a port.
>+ */
>+ uint16_t k;
>+
>+ /*
>+ * Count of RepeaterAuth_Stream_Manage msg propagated.
>+ * Initialized to 0 on AKE_INIT. Incremented after every successful
>+ * transmission of RepeaterAuth_Stream_Manage message. When it rolls
>+ * over re-Auth has to be triggered.
>+ */
>+ uint32_t seq_num_m;
>+
>+ /* k(No of Streams per port) x structure of wired_streamid_type */
>+ struct hdcp2_streamid_type *streams;
>+};
>+
>+#endif /* defined (_LINUX_MEI_HDCP_H) */
>--
>2.7.4
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Re: [Intel-gfx] [PATCH v6 02/35] drm: HDMI and DP specific HDCP2.2 defines
>-Original Message-
>From: C, Ramalingam
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Cc: Sharma, Shashank ; C, Ramalingam
>
>Subject: [PATCH v6 02/35] drm: HDMI and DP specific HDCP2.2 defines
>
>This patch adds HDCP register definitions for HDMI and DP HDCP adaptations.
>
>HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, where as
>HDCP2.2 register offsets in DPCD offsets are defined at drm_dp_helper.h.
>
>v2:
> bit_field definitions are replaced by macros. [Tomas and Jani]
>v3:
> No Changes.
>v4:
> Comments style and typos are fixed [Uma]
>v5:
> Fix for macros.
>v6:
> Adds _MS to the timeouts to represent units [Sean Paul]
>
>Signed-off-by: Ramalingam C
>Reviewed-by: Sean Paul
>---
> include/drm/drm_dp_helper.h | 51
>+
> include/drm/drm_hdcp.h | 30 ++
> 2 files changed, 81 insertions(+)
>
>diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>c01564991a9f..17e0889d6aaa 100644
>--- a/include/drm/drm_dp_helper.h
>+++ b/include/drm/drm_dp_helper.h
>@@ -904,6 +904,57 @@
> #define DP_AUX_HDCP_KSV_FIFO 0x6802C
> #define DP_AUX_HDCP_AINFO 0x6803B
>
>+/* DP HDCP2.2 parameter offsets in DPCD address space */
>+#define DP_HDCP_2_2_REG_RTX_OFFSET0x69000
>+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
>+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET0x6900B
>+#define DP_HDCP_2_2_REG_RRX_OFFSET0x69215
>+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET0x6921D
>+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
>+#define DP_HDCP_2_2_REG_EKH_KM_OFFSET 0x692A0
It would be good to append WRITE since we have a READ counterpart to be
explicit.
>+#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
>+#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
>+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
>+#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
>+#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
>+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
>+#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
>+#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
>+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
>+#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
>+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
>+#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
>+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
>+#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
>+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
>+#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
>+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
>+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET0x69494
>+#define DP_HDCP_2_2_REG_DBG_OFFSET0x69518
>+
>+/* DP HDCP message start offsets in DPCD address space */
>+#define DP_HDCP_2_2_AKE_INIT_OFFSET
> DP_HDCP_2_2_REG_RTX_OFFSET
>+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET
> DP_HDCP_2_2_REG_CERT_RX_OFFSET
>+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET
> DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
>+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET
> DP_HDCP_2_2_REG_EKH_KM_OFFSET
>+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET
> DP_HDCP_2_2_REG_HPRIME_OFFSET
>+#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
>+
> DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
>+#define DP_HDCP_2_2_LC_INIT_OFFSET
> DP_HDCP_2_2_REG_RN_OFFSET
>+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET
> DP_HDCP_2_2_REG_LPRIME_OFFSET
>+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
> DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
>+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
> DP_HDCP_2_2_REG_RXINFO_OFFSET
>+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET
> DP_HDCP_2_2_REG_V_OFFSET
>+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET
> DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
>+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET
> DP_HDCP_2_2_REG_MPRIME_OFFSET
>+
>+#define HDCP_2_2_DP_RXSTATUS_LEN 1
>+#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
>+#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
>+#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
>+#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x)((x) & BIT(3))
>+#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
>+
> /* DP 1.2 Sideband message defines */
> /* peer device type - DP 1.2a Table 2-92 */
> #define DP_PEER_DEVICE_NONE 0x0
>diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index
>a2a4a159fcde..2b4cfb0b7324 100644
>--- a/include/drm/drm_hdcp.h
>+++ b/include/drm/drm_hdcp.h
>@@ -222,4 +222,34 @@ struct hdcp2_dp_errata_stream_type {
> uint8_t stream_type;
> } __packed;
>
>+/* HDCP2.2 TIMEOUTs in mSec */
Re: [Intel-gfx] [PATCH v6 01/35] drm: hdcp2.2 authentication msg definitions
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>; Usyskin, Alexander ;
>Shankar, Uma
>Subject: [PATCH v6 01/35] drm: hdcp2.2 authentication msg definitions
>
>This patch defines the hdcp2.2 protocol messages for authentication.
>
>v2:
> bit_fields are removed. Instead bitmasking used. [Tomas and Jani]
> prefix HDCP_2_2_ is added to the macros. [Tomas]
>v3:
> No Changes.
>v4:
> Style and spellings are fixed [Uma]
>v5:
> Fix for macros.
>v6:
> comment for Type is improved [Sean Paul]
>
>Signed-off-by: Ramalingam C
>---
> include/drm/drm_hdcp.h | 184
>+
> 1 file changed, 184 insertions(+)
>
>diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index
>98e63d870139..a2a4a159fcde 100644
>--- a/include/drm/drm_hdcp.h
>+++ b/include/drm/drm_hdcp.h
>@@ -38,4 +38,188 @@
> #define DRM_HDCP_DDC_BSTATUS 0x41
> #define DRM_HDCP_DDC_KSV_FIFO 0x43
>
>+#define DRM_HDCP_1_4_SRM_ID 0x8
>+#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
>+#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
>+
>+/* Protocol message definition for HDCP2.2 specification */
>+/*
>+ * Protected content streams are classified into 2 types:
>+ * - Type0: Can be transmitted with HDCP 1.4+
>+ * - Type1: Can be transmitted with HDCP 2.2+ */
>+#define HDCP_STREAM_TYPE0 0x00
>+#define HDCP_STREAM_TYPE1 0x01
>+
>+/* HDCP2.2 Msg IDs */
>+#define HDCP_2_2_NULL_MSG 1
>+#define HDCP_2_2_AKE_INIT 2
>+#define HDCP_2_2_AKE_SEND_CERT3
>+#define HDCP_2_2_AKE_NO_STORED_KM 4
>+#define HDCP_2_2_AKE_STORED_KM5
>+#define HDCP_2_2_AKE_SEND_HPRIME 7
>+#define HDCP_2_2_AKE_SEND_PAIRING_INFO8
>+#define HDCP_2_2_LC_INIT 9
>+#define HDCP_2_2_LC_SEND_LPRIME 10
>+#define HDCP_2_2_SKE_SEND_EKS 11
>+#define HDCP_2_2_REP_SEND_RECVID_LIST 12
>+#define HDCP_2_2_REP_SEND_ACK 15
>+#define HDCP_2_2_REP_STREAM_MANAGE16
>+#define HDCP_2_2_REP_STREAM_READY 17
>+#define HDCP_2_2_ERRATA_DP_STREAM_TYPE50
>+
>+#define HDCP_2_2_RTX_LEN 8
>+#define HDCP_2_2_RRX_LEN 8
>+
>+#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128
>+#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3
>+#define HDCP_2_2_K_PUB_RX_LEN
> (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
>+
>HDCP_2_2_K_PUB_RX_EXP_E_LEN)
>+
>+#define HDCP_2_2_DCP_LLC_SIG_LEN 384
>+
>+#define HDCP_2_2_E_KPUB_KM_LEN128
>+#define HDCP_2_2_E_KH_KM_M_LEN(16 + 16)
>+#define HDCP_2_2_H_PRIME_LEN 32
>+#define HDCP_2_2_E_KH_KM_LEN 16
>+#define HDCP_2_2_RN_LEN 8
>+#define HDCP_2_2_L_PRIME_LEN 32
>+#define HDCP_2_2_E_DKEY_KS_LEN16
>+#define HDCP_2_2_RIV_LEN 8
>+#define HDCP_2_2_SEQ_NUM_LEN 3
>+#define HDCP_2_2_LPRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
>+#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
>+#define HDCP_2_2_MAX_DEVICE_COUNT 31
>+#define HDCP_2_2_RECEIVER_IDS_MAX_LEN
> (HDCP_2_2_RECEIVER_ID_LEN * \
>+
>HDCP_2_2_MAX_DEVICE_COUNT)
>+#define HDCP_2_2_MPRIME_LEN 32
>+
>+/* Following Macros take a byte at a time for bit(s) masking */
>+/*
>+ * TODO: This has to be changed for DP MST, as multiple stream on
>+ * same port is possible.
>+ * For HDCP2.2 on HDMI and DP SST this value is always 1.
>+ */
>+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
>+#define HDCP_2_2_TXCAP_MASK_LEN 2
>+#define HDCP_2_2_RXCAPS_LEN 3
>+#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
>+#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
>+#define HDCP_2_2_RXINFO_LEN 2
>+
>+/* HDCP1.x compliant device in downstream */
>+#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x)((x) & BIT(0))
>+
>+/* HDCP2.0 Compliant repeater in downstream */
>+#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x)((x) & BIT(1))
>+#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
>+#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
>+#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
>+#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
>+#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
>+
>+struct hdcp2_cert_rx {
>+ uint8_t receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
>+ uint8_t kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
>+
Re: [Intel-gfx] [PATCH] drm/i915/skl: distribute DDB based on panel resolution
Hi Chris,
Thanks for review.
On 7/30/2018 9:08 PM, Chris Wilson wrote:
Quoting Mahesh Kumar (2018-07-30 15:12:02)
We distribute DDB equally among all pipes irrespective of display
buffer requirement of each pipe. This leads to a situation where high
resolution y-tiled display can not be enabled with 2 low resolution
displays.
Main contributing factor for DDB requirement is width of the display.
This patch make changes to distribute ddb based on display width.
So display with higher width will get bigger chunk of DDB.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107113
Cc: raviraj.p.sita...@intel.com
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 55 +++--
1 file changed, 42 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7312ecb73415..e092f0deb93d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3814,8 +3814,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev,
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_crtc *for_crtc = cstate->base.crtc;
+ enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
+ const struct drm_crtc_state *crtc_state;
+ const struct drm_crtc *crtc;
+ u32 pipe_width[I915_MAX_PIPES] = {0};
+ u32 total_width = 0, width_before_pipe = 0;
unsigned int pipe_size, ddb_size;
- int nth_active_pipe;
+ u16 ddb_size_before_pipe;
+ u32 i;
if (WARN_ON(!state) || !cstate->base.active) {
alloc->start = 0;
@@ -3833,14 +3839,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev,
*num_active, ddb);
/*
-* If the state doesn't change the active CRTC's, then there's
-* no need to recalculate; the existing pipe allocation limits
-* should remain unchanged. Note that we're safe from racing
-* commits since any racing commit that changes the active CRTC
-* list would need to grab _all_ crtc locks, including the one
-* we currently hold.
+* If the state doesn't change the active CRTC's or there is no
+* modeset request, then there's no need to recalculate;
+* the existing pipe allocation limits should remain unchanged.
+* Note that we're safe from racing commits since any racing commit
+* that changes the active CRTC list or do modeset would need to
+* grab _all_ crtc locks, including the one we currently hold.
*/
- if (!intel_state->active_pipe_changes) {
+ if (!intel_state->active_pipe_changes && !intel_state->modeset) {
/*
* alloc may be cleared by clear_intel_crtc_state,
* copy from old state to be sure
@@ -3849,10 +3855,33 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev,
return;
}
- nth_active_pipe = hweight32(intel_state->active_crtcs &
- (drm_crtc_mask(for_crtc) - 1));
- pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
- alloc->start = nth_active_pipe * ddb_size / *num_active;
+ /*
+* Watermark/ddb requirement highly depends upon width of the
+* framebuffer, So instead of allocating DDB equally among pipes
+* distribute DDB based on resolution/width of the display.
+*/
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ const struct drm_display_mode *adjusted_mode;
+ int hdisplay, vdisplay;
+ enum pipe pipe;
+
+ if (!crtc_state->enable)
+ continue;
+
+ pipe = to_intel_crtc(crtc)->pipe;
+ adjusted_mode = _state->adjusted_mode;
+ drm_mode_get_hv_timing(adjusted_mode, , );
+ pipe_width[pipe] = hdisplay;
+ total_width += pipe_width[pipe];
+
+ if (pipe < for_pipe)
+ width_before_pipe += pipe_width[pipe];
+ }
+
+ ddb_size_before_pipe = div_u64(ddb_size * width_before_pipe,
+ total_width);
ddb_size is unsigned int (u32)
width_before_pipe is u32
ddb_size_before_pipe is u16
That mismash of types is itself perplexing, but u32*u16 is only u32, you
need to cast it to u64 to avoid the overflow: i.e.
div_u64(mul_u32_u32(ddb_size, width_before_pipe),
total_width);
But ddb_size_before_pipe obviously need to be the same type as ddb_size,
and if u16 is good enough, then you do not need a 64b divide!
hmm, ddb_size will not go beyond u16 as we have only 1024 blocks and in
future also I'm not expecting it to overflow u16.
I don't wanted to change already used data-types , anyway will clean
this
