Re: [Intel-gfx] [RFC 1/3] drm/i915/icl: Restructure ICL DPLL enable functionality
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, October 3, 2018 5:11 PM
> To: Ville Syrjälä ; Kulkarni, Vandita
>
> Cc: intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
>
> Subject: Re: [Intel-gfx] [RFC 1/3] drm/i915/icl: Restructure ICL DPLL enable
> functionality
>
> On Wed, 03 Oct 2018, Jani Nikula wrote:
> > On Wed, 03 Oct 2018, Jani Nikula wrote:
> >> On Fri, 14 Sep 2018, Ville Syrjälä wrote:
> >>> On Fri, Sep 14, 2018 at 12:24:12PM +0530, Vandita Kulkarni wrote:
> From: Madhav Chauhan
>
> In Gen11, DPLL 0 and 1 are shared between DDI and DSI.
> Most of the steps for enabling DPLL are common across DDI and DSI.
> This patch makes icl_dpll_enable() generic which will be used by
> all the encoders.
>
> Signed-off-by: Madhav Chauhan
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 12
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 19 ++-
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
> 3 files changed, 15 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index cd01a09..2942a24 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2810,6 +2810,18 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> mutex_lock(_priv->dpll_lock);
>
> if (IS_ICELAKE(dev_priv)) {
> +enum intel_dpll_id id = pll->info->id;
> +i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
> +
> +val = I915_READ(enable_reg);
> +val |= PLL_ENABLE;
> +I915_WRITE(enable_reg, val);
> +
> +/* TODO: wait times missing from the spec. */
> +if (intel_wait_for_register(dev_priv, enable_reg,
> PLL_LOCK,
> +PLL_LOCK, 5))
> +DRM_ERROR("PLL %d not locked\n", id);
> +
> >>>
> >>> I don't really see why this can't stay in the dpll mgr.
> >>
> >> Agreed, I think it should stay in DPLL manager.
> >>
> >> The thing is, DPLL enabling for DSI requires encoder specific steps
> >> in the middle of the sequence hidden in DPLL manager. It's not pretty
> >> to add that in DPLL manager.
> >>
> >> One approach might be to add encoder hooks to call from the right
> >> spot in the DPLL manager, "mid_pll_enable". It's annoying because it
> >> would have to happen in the middle of the platform specific DPLL
> >> manager
> >> pll->info->funcs->enable hook. We'd have to call the hooks from
> >> pll->info->funcs->platform
> >> specific code, or split those hooks in two. The former is ugly
> >> because it requires passing crtc to the pll enable hook. So I guess
> >> add a pll post enable hook.
> >>
> >> Below's some draft code to give an idea what I mean. You'd move the
> >> above hunk to the post hook instead.
> >>
> >> So then we'd add mid_pll_enable hooks and do the required magic in
> >> the DSI mid pll hook.
Thanks Jani, let me try this out.
Regards,
Vandita
> >
> > PS. And even with this I'm not yet sure if we can do the overall DPLL
> > enabling at the right spot wrt bspec DSI mode set sequence. *cringe*.
>
> Ville reminded me that we did have this idea of pushing pll enable calls down
> to
> encoders on DDI platforms. This would help, of course.
>
> BR,
> Jani.
>
>
> >
> > BR,
> > Jani.
> >
> >>
> >> Overall I'm starting to feel the appeal of driving modeset from
> >> encoders, with library style helpers provided from intel_display.c,
> >> instead of adding more and more encoder hooks to do stuff at specific
> >> places. But I digress.
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> index e6cac9225536..a4ca1b4a124c 100644
> >> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> @@ -191,6 +191,12 @@ void intel_enable_shared_dpll(struct intel_crtc
> >> *crtc)
> >>
> >>DRM_DEBUG_KMS("enabling %s\n", pll->info->name);
> >>pll->info->funcs->enable(dev_priv, pll);
> >> +
> >> + intel_encoders_mid_pll_enable(crtc); /* pipe_config, old_state? */
> >> +
> >> + if (pll->info->funcs->post_enable)
> >> + pll->info->funcs->post_enable(dev_priv, pll);
> >> +
> >>pll->on = true;
> >>
> >> out:
> >> @@ -3199,6 +3205,7 @@ static void icl_dump_hw_state(struct
> >> drm_i915_private *dev_priv,
> >>
> >> static const struct intel_shared_dpll_funcs icl_pll_funcs = {
> >>.enable = icl_pll_enable,
> >> + .post_enable = icl_pll_post_enable,
> >>.disable = icl_pll_disable,
> >>.get_hw_state = icl_pll_get_hw_state, }; diff --git
> >> a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> >>
Re: [Intel-gfx] [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles
On Wed, Oct 03, 2018 at 04:43:53PM -0700, Lucas De Marchi wrote:
> On Wed, Oct 03, 2018 at 04:30:36PM -0700, Rodrigo Vivi wrote:
> > On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote:
> > > Display WA #1178 is meant to fix Aux channel voltage swing too low with
> > > some type C dongles. Although it is for type C, of ICL it only applies
> > > to combo phy and not to eDP. This means we need to apply the WA only on
> > > Aux B.
> > >
> > > Cc: Rodrigo Vivi
> > > Cc: Paulo Zanoni
> > > Cc: Ville Syrjälä
> > > Cc: Imre Deak
> > > Signed-off-by: Lucas De Marchi
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 4
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++
> > > 2 files changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index e7e6ca7f9665..1e92112d23de 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8928,6 +8928,10 @@ enum skl_power_gate {
> > > #define CNL_AUX_ANAOVRD1_ENABLE(1 << 16)
> > > #define CNL_AUX_ANAOVRD1_LDO_BYPASS(1 << 23)
> > >
> > > +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398)
> > > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS(1 << 7)
> > > +#define ICL_AUX_ANAOVRD1_ENABLE(1 << 0)
> > > +
> > > /* HDCP Key Registers */
> > > #define HDCP_KEY_CONF_MMIO(0x66c00)
> > > #define HDCP_AKSV_SEND_TRIGGER BIT(31)
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 0fdabce647ab..a97d2f762b77 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct
> > > drm_i915_private *dev_priv,
> > > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> > >
> > > hsw_wait_for_power_well_enable(dev_priv, power_well);
> > > +
> > > + /* Display WA #1178: icl */
> > > + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) {
> >
> > Spec tells:
> > CNL: This programming does not apply to Aux A.
> > ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1
> > with extra note of This programming only applies for external ports on the
> > combo PHY,
> > not on type C PHY, and not for eDP.
> >
> > So I believe we need to add Aux A here and add a check for !is_edp
>
> ha! But spec 20584 for Icelake says Combo Port A can only be used for eDP or
> DSI.
> Or am I missing anything here?
Hmm... maybe some weird platforms could configuration could use
Aux A with Port B through VBT?!
I've seen in the past port E with aux B and Port E with aux C.
But I really thing it is unlikely indeed...
So, feel free to go with:
Reviewed-by: Rodrigo Vivi
>
> Lucas De Marchi
>
> >
> > > + val = I915_READ(ICL_AUX_ANAOVRD1_B);
> > > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> > > + I915_WRITE(ICL_AUX_ANAOVRD1_B, val);
> > > + }
> > > }
> > >
> > > static void
> > > --
> > > 2.17.1
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> ___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: apply Display WA #1178 to fix type C dongles
== Series Details == Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles URL : https://patchwork.freedesktop.org/series/50102/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4925 -> Patchwork_10352 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50102/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10352 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) Possible fixes igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (48 -> 42) == Additional (1): fi-kbl-7560u Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 == Build changes == * Linux: CI_DRM_4925 -> Patchwork_10352 CI_DRM_4925: b652f33e63e1aafb7fc1cb2a9648a14d66f0d35f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10352: 4531b0c35129f74192eb31d5fa4671274cc69bc8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4531b0c35129 drm/i915/icl: apply Display WA #1178 to fix type C dongles == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10352/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles
On Wed, Oct 03, 2018 at 04:30:36PM -0700, Rodrigo Vivi wrote:
> On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote:
> > Display WA #1178 is meant to fix Aux channel voltage swing too low with
> > some type C dongles. Although it is for type C, of ICL it only applies
> > to combo phy and not to eDP. This means we need to apply the WA only on
> > Aux B.
> >
> > Cc: Rodrigo Vivi
> > Cc: Paulo Zanoni
> > Cc: Ville Syrjälä
> > Cc: Imre Deak
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++
> > 2 files changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index e7e6ca7f9665..1e92112d23de 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8928,6 +8928,10 @@ enum skl_power_gate {
> > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
> > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
> >
> > +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398)
> > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
> > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
> > +
> > /* HDCP Key Registers */
> > #define HDCP_KEY_CONF _MMIO(0x66c00)
> > #define HDCP_AKSV_SEND_TRIGGERBIT(31)
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 0fdabce647ab..a97d2f762b77 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct
> > drm_i915_private *dev_priv,
> > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> >
> > hsw_wait_for_power_well_enable(dev_priv, power_well);
> > +
> > + /* Display WA #1178: icl */
> > + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) {
>
> Spec tells:
> CNL: This programming does not apply to Aux A.
> ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1
> with extra note of This programming only applies for external ports on the
> combo PHY,
> not on type C PHY, and not for eDP.
>
> So I believe we need to add Aux A here and add a check for !is_edp
ha! But spec 20584 for Icelake says Combo Port A can only be used for eDP or
DSI.
Or am I missing anything here?
Lucas De Marchi
>
> > + val = I915_READ(ICL_AUX_ANAOVRD1_B);
> > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> > + I915_WRITE(ICL_AUX_ANAOVRD1_B, val);
> > + }
> > }
> >
> > static void
> > --
> > 2.17.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> ___
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Re: [Intel-gfx] [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles
On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote:
> Display WA #1178 is meant to fix Aux channel voltage swing too low with
> some type C dongles. Although it is for type C, of ICL it only applies
> to combo phy and not to eDP. This means we need to apply the WA only on
> Aux B.
>
> Cc: Rodrigo Vivi
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4
> drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e7e6ca7f9665..1e92112d23de 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8928,6 +8928,10 @@ enum skl_power_gate {
> #define CNL_AUX_ANAOVRD1_ENABLE(1 << 16)
> #define CNL_AUX_ANAOVRD1_LDO_BYPASS(1 << 23)
>
> +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398)
> +#define ICL_AUX_ANAOVRD1_LDO_BYPASS(1 << 7)
> +#define ICL_AUX_ANAOVRD1_ENABLE(1 << 0)
> +
> /* HDCP Key Registers */
> #define HDCP_KEY_CONF_MMIO(0x66c00)
> #define HDCP_AKSV_SEND_TRIGGER BIT(31)
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0fdabce647ab..a97d2f762b77 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
> +
> + /* Display WA #1178: icl */
> + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) {
Spec tells:
CNL: This programming does not apply to Aux A.
ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1
with extra note of This programming only applies for external ports on the
combo PHY,
not on type C PHY, and not for eDP.
So I believe we need to add Aux A here and add a check for !is_edp
> + val = I915_READ(ICL_AUX_ANAOVRD1_B);
> + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> + I915_WRITE(ICL_AUX_ANAOVRD1_B, val);
> + }
> }
>
> static void
> --
> 2.17.1
>
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[Intel-gfx] ✓ Fi.CI.IGT: success for Refactor and Add helper function for combophy/tc ports
== Series Details ==
Series: Refactor and Add helper function for combophy/tc ports
URL : https://patchwork.freedesktop.org/series/50484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4919_full -> Patchwork_10341_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10341_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: PASS -> FAIL (fdo#103232) +5
igt@kms_cursor_crc@cursor-256x85-onscreen:
shard-glk: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: PASS -> FAIL (fdo#103232, fdo#103191)
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-snb: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-glk: PASS -> FAIL (fdo#103167) +2
{igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max}:
shard-skl: NOTRUN -> FAIL (fdo#108145)
{igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max}:
shard-glk: PASS -> FAIL (fdo#108145)
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-apl: PASS -> FAIL (fdo#103166) +1
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166)
Possible fixes
igt@kms_busy@extended-pageflip-hang-newfb-render-c:
shard-glk: DMESG-WARN (fdo#107956) -> PASS
igt@kms_cursor_crc@cursor-128x42-random:
shard-skl: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
shard-skl: FAIL (fdo#103184) -> PASS +1
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
shard-skl: FAIL (fdo#103167) -> PASS +5
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
shard-skl: FAIL (fdo#105682) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
shard-apl: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
shard-glk: FAIL (fdo#103167) -> PASS +3
{igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
shard-skl: FAIL (fdo#108145) -> PASS
{igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max}:
shard-apl: FAIL (fdo#108145) -> PASS
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
shard-glk: FAIL (fdo#103166) -> PASS +1
igt@kms_universal_plane@universal-plane-pipe-b-functional:
shard-apl: FAIL (fdo#103166) -> PASS +1
Warnings
{igt@kms_plane_alpha_blend@pipe-a-alpha-basic}:
shard-glk: FAIL (fdo#108145) -> INCOMPLETE (fdo#103359,
k.org#198133)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4919 -> Patchwork_10341
CI_DRM_4919: e489eb0296673790264b25266ef45aae7d1ab566 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10341: f57caa7775e7b812ebab31aba3d1608bea229222 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915/guc: init GuC descriptors after GuC load
On 03/10/18 08:24, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2018-10-03 01:12:57) On 02/10/18 15:39, Patchwork wrote: == Series Details == Series: series starting with [v2,1/3] drm/i915/guc: init GuC descriptors after GuC load URL : https://patchwork.freedesktop.org/series/50464/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4915 -> Patchwork_10331 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10331 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10331, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50464/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10331: === IGT changes === Possible regressions igt@drv_selftest@live_gem: fi-whl-u: PASS -> INCOMPLETE fi-skl-6600u: PASS -> INCOMPLETE fi-kbl-7560u: PASS -> INCOMPLETE fi-cfl-s3: PASS -> INCOMPLETE fi-skl-iommu: PASS -> INCOMPLETE fi-skl-6700k2: PASS -> INCOMPLETE fi-skl-6700hq: PASS -> INCOMPLETE fi-cfl-8109u: PASS -> INCOMPLETE fi-kbl-7500u: PASS -> INCOMPLETE fi-cfl-8700k: PASS -> INCOMPLETE fi-skl-6770hq: PASS -> INCOMPLETE fi-kbl-7567u: PASS -> INCOMPLETE fi-kbl-x1275: PASS -> INCOMPLETE fi-kbl-8809g: PASS -> INCOMPLETE fi-kbl-r: PASS -> INCOMPLETE Those failures are there even without my patches (see https://patchwork.freedesktop.org/series/40112/). Is there an existing bugzilla? In the meantime, I'll have a look to see if I can find what's causing this. inject_preempt_context() fails when talking to the guc, catastrophe ensues. As shown above it's quite reliable after a fake suspend/resume, but it also happens during normal preemption (the preemption smoketest was added to exercise this issue). -Chris Do you consider this a blocker to getting the patches merged? BTW, on my SKL even with the preemption smoketest I didn't see any issue on the tree I based the patches on (from Monday) and I only see issues after: b16c765122f987056e1dc9ef6c214571bb5bd694 is the first bad commit commit b16c765122f987056e1dc9ef6c214571bb5bd694 Author: Chris Wilson Date: Mon Oct 1 15:47:53 2018 +0100 drm/i915: Priority boost for new clients However I don't get any error logs out (the machine just dies) so not sure if it is the same issue or not. with that patch and the 2 following related ones reverted I've been running the live selftests in a loop without issues. Is this the bug you mentioned or are those possibly 2 different issues? Thanks, Daniele ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 1/2] drm: Add connector property to limit max bpc
On Mon, Oct 01, 2018 at 09:23:38AM +0200, Daniel Vetter wrote:
> On Mon, Sep 24, 2018 at 02:08:14PM -0700, Radhakrishna Sripada wrote:
> > At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> > level shifters etc. To workaround them we may need to drive the output
> > at a lower bpc. Currently the user space does not have a way to limit
> > the bpc. The default bpc to be programmed is decided by the driver and
> > is run against connector limitations.
> >
> > Creating a new connector property "max bpc" in order to limit the bpc.
> > xrandr can make use of this connector property to make sure that bpc does
> > not exceed the configured value. This property can be used by userspace to
> > set the bpc.
> >
> > V2: Initialize max_bpc to satisfy kms_properties
> > V3: Move the property to drm_connector
> > V4: Split drm and i915 components(Ville)
> > V5: Make the property per connector(Ville)
> > V6: Compare the requested bpc to connector bpc(Daniel)
> > Move the attach_property function to core(Ville)
> > V7: Fix checkpatch warnings
> > V8: Simplify the connector check code(Ville)
> > V9: Const display_info(Ville)
> > V10: Fix CI issues.
> >
> > Cc: Ville Syrjälä
> > Cc: Daniel Vetter
> > Cc: Kishore Kadiyala
> > Cc: Rodrigo Vivi
> > Cc: Manasi Navare
> > Cc: Stanislav Lisovskiy
> > Cc: Sunpeng Li
> > Signed-off-by: Radhakrishna Sripada
>
> Skimming this, I think it looks good now at a high-level.
>
> What's missing is now kernel-doc for these new prorties, needs to be added
> here:
>
> https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#standard-connector-properties
>
> With that I'm happy with the high-level design:
>
> Acked-by: Daniel Vetter
>
> No full review since I didn't look at the igt side for this. Userspace I
> think is ok, since it's just another connector prop.
kms_properties would test this newly added property as part of the connector
properties.
Do you suggest me to add a new subtest to try checking the different values for
the
newly added property?
--Radhakrishna Sripada
> -Daniel
>
> > ---
> > drivers/gpu/drm/drm_atomic.c| 5 +
> > drivers/gpu/drm/drm_atomic_helper.c | 4
> > drivers/gpu/drm/drm_atomic_uapi.c | 4
> > drivers/gpu/drm/drm_connector.c | 33 +
> > include/drm/drm_connector.h | 20
> > 5 files changed, 66 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > index 2870ae205237..f328bcca84a8 100644
> > --- a/drivers/gpu/drm/drm_atomic.c
> > +++ b/drivers/gpu/drm/drm_atomic.c
> > @@ -390,6 +390,7 @@ static int drm_atomic_connector_check(struct
> > drm_connector *connector,
> > {
> > struct drm_crtc_state *crtc_state;
> > struct drm_writeback_job *writeback_job = state->writeback_job;
> > + const struct drm_display_info *info = >display_info;
> >
> > if ((connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) ||
> > !writeback_job)
> > return 0;
> > @@ -417,6 +418,10 @@ static int drm_atomic_connector_check(struct
> > drm_connector *connector,
> > return -EINVAL;
> > }
> >
> > + state->max_bpc = info->bpc ? info->bpc : 8;
> > + if (connector->max_bpc_property)
> > + state->max_bpc = min(state->max_bpc, state->max_requested_bpc);
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c
> > index e49b22381048..75aeca35f6d9 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -639,6 +639,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
> > if (old_connector_state->link_status !=
> > new_connector_state->link_status)
> > new_crtc_state->connectors_changed = true;
> > +
> > + if (old_connector_state->max_requested_bpc !=
> > + new_connector_state->max_requested_bpc)
> > + new_crtc_state->connectors_changed = true;
> > }
> >
> > if (funcs->atomic_check)
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index d5b7f315098c..86ac33922b09 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -740,6 +740,8 @@ static int drm_atomic_connector_set_property(struct
> > drm_connector *connector,
> >
> > return set_out_fence_for_connector(state->state, connector,
> >fence_ptr);
> > + } else if (property == connector->max_bpc_property) {
> > + state->max_requested_bpc = val;
> > } else if (connector->funcs->atomic_set_property) {
> > return connector->funcs->atomic_set_property(connector,
> > state, property, val);
> > @@ -804,6 +806,8 @@
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Flush the CS events before unpinning
== Series Details ==
Series: drm/i915/execlists: Flush the CS events before unpinning
URL : https://patchwork.freedesktop.org/series/50494/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4919_full -> Patchwork_10340_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10340_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_contexts:
shard-snb: PASS -> INCOMPLETE (fdo#105411)
igt@drv_suspend@shrink:
shard-skl: PASS -> INCOMPLETE (fdo#106886)
igt@gem_userptr_blits@readonly-unsync:
shard-skl: PASS -> INCOMPLETE (fdo#108074)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108)
igt@kms_cursor_crc@cursor-128x42-onscreen:
shard-glk: PASS -> FAIL (fdo#103232) +5
igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
shard-skl: PASS -> FAIL (fdo#103184)
igt@kms_fbcon_fbt@psr-suspend:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-apl: PASS -> FAIL (fdo#103167) +4
shard-glk: PASS -> FAIL (fdo#103167) +2
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108)
{igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max}:
shard-skl: NOTRUN -> FAIL (fdo#108145) +1
{igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max}:
shard-glk: PASS -> FAIL (fdo#108145) +1
igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166) +2
igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +3
igt@kms_sysfs_edid_timing:
shard-skl: NOTRUN -> FAIL (fdo#100047)
Possible fixes
igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
shard-skl: FAIL (fdo#103184) -> PASS +1
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
shard-skl: FAIL (fdo#103167) -> PASS +3
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS +1
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-apl: FAIL (fdo#103166) -> PASS +3
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
shard-glk: FAIL (fdo#103166) -> PASS +1
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
shard-kbl: FAIL (fdo#99912) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4919 -> Patchwork_10340
CI_DRM_4919: e489eb0296673790264b25266ef45aae7d1ab566 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10340: f8924caa9adab083e6fd9d57c94b65c4651f453d @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
== Series Details == Series: series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask URL : https://patchwork.freedesktop.org/series/50526/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4925 -> Patchwork_10351 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50526/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10351 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_switch@basic-default-heavy: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) igt@kms_psr@cursor_plane_move: fi-kbl-r: PASS -> FAIL (fdo#107383) +3 fi-whl-u: PASS -> FAIL (fdo#107383) +3 igt@kms_psr@primary_mmap_gtt: fi-kbl-7560u: NOTRUN -> FAIL (fdo#107383) +3 fi-cnl-u: PASS -> FAIL (fdo#107383) +3 igt@kms_psr@primary_page_flip: fi-skl-6600u: PASS -> FAIL (fdo#107383) +3 Possible fixes igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107383 https://bugs.freedesktop.org/show_bug.cgi?id=107383 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (48 -> 38) == Additional (1): fi-kbl-7560u Missing(11): fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-skl-guc fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-cfl-s3 fi-icl-u fi-skl-6700hq == Build changes == * Linux: CI_DRM_4925 -> Patchwork_10351 CI_DRM_4925: b652f33e63e1aafb7fc1cb2a9648a14d66f0d35f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10351: 514e604a2b9a7a2422d760c87651585b6896a1c5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 514e604a2b9a drm/i915/psr: Remove alpm from i915_psr 665311b03a29 drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 1537843c8c69 drm/i915/psr: Remove main link standby mode from debugfs bfceeb76d06e drm/i915/psr: Use WA to force HW tracking to exit PSR2 5fa7ea20efba drm/i915/psr: Remove PSR2 TODO error handling 357c03ffd698 drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL f91c986fb9b7 drm/i915/psr: Share PSR and PSR2 exit mask == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10351/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
On Wednesday, October 3, 2018 1:50:30 PM PDT José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
> while PSR2 is active, so don't configure sink DPCD with a
> wrong value.
>
> v4: rebased on top of the patch removing link standby from debugfs
Reviewed-by: Dhinakaran Pandiyan
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index 423cdf84059c..26317a4e03d2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -346,12 +346,14 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp) drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE);
> dpcd_val |= DP_PSR_ENABLE_PSR2;
> + } else {
> + if (dev_priv->psr.link_standby)
> + dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> +
> + if (INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
> }
>
> - if (dev_priv->psr.link_standby)
> - dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> - dpcd_val |= DP_PSR_CRC_VERIFICATION;
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>
> drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 5/7] drm/i915/psr: Remove main link standby mode from debugfs
On Wednesday, October 3, 2018 1:50:29 PM PDT José Roberto de Souza wrote:
> Main link stand by is only valid for PSR1 as it is not possible to
> enable PSR2 and keep main link on but even for PSR1 it is not useful
> information and it can be removed without any drawbacks.
> But if someone still wants to check that this patch is providing the
> full PSR_CTL register value so user can check if bit 27 is set, this
> will also expose more information about how PSR1 and PSR2 was
> configured in source.
Yes, knowing the full configuration (idle frames, training pattern ) is very
useful for debug.
>
> Cc: Dhinakaran Pandiyan
> Suggested-by: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 25 -
> 1 file changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c index f42e93b71e67..48e65becd035
> 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2712,8 +2712,8 @@ psr_source_status(struct drm_i915_private *dev_priv,
> struct seq_file *m) static int i915_edp_psr_status(struct seq_file *m, void
> *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - u32 psrperf = 0;
> - bool enabled = false;
> + u32 val;
> + bool enabled;
> bool sink_support;
>
> if (!HAS_PSR(dev_priv))
> @@ -2733,24 +2733,23 @@ static int i915_edp_psr_status(struct seq_file *m,
> void *data) seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
> dev_priv->psr.busy_frontbuffer_bits);
>
> - if (dev_priv->psr.psr2_enabled)
> - enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
> - else
> - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> -
> - seq_printf(m, "Main link in standby mode: %s\n",
> -yesno(dev_priv->psr.link_standby));
> + if (dev_priv->psr.psr2_enabled) {
> + val = I915_READ(EDP_PSR2_CTL);
> + enabled = val & EDP_PSR2_ENABLE;
> + } else {
> + val = I915_READ(EDP_PSR_CTL);
> + enabled = val & EDP_PSR_ENABLE;
> + }
>
> - seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
> + seq_printf(m, "HW enabled: %s [0x%x]\n", yesno(enabled), val);
The status register is printed as []. Can we
please keep this interface consistent? Also, this change will need changes in
IGTs.
With the print format changed
Reviewed-by: Dhinakaran Pandiyan
>
> /*
>* SKL+ Perf counter is reset to 0 everytime DC state is entered
>*/
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - psrperf = I915_READ(EDP_PSR_PERF_CNT) &
> - EDP_PSR_PERF_CNT_MASK;
> + val = I915_READ(EDP_PSR_PERF_CNT) & EDP_PSR_PERF_CNT_MASK;
>
> - seq_printf(m, "Performance_Counter: %u\n", psrperf);
> + seq_printf(m, "Performance_Counter: %u\n", val);
> }
>
> psr_source_status(dev_priv, m);
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
== Series Details == Series: series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask URL : https://patchwork.freedesktop.org/series/50526/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/psr: Share PSR and PSR2 exit mask Okay! Commit: drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL Okay! Commit: drm/i915/psr: Remove PSR2 TODO error handling Okay! Commit: drm/i915/psr: Use WA to force HW tracking to exit PSR2 Okay! Commit: drm/i915/psr: Remove main link standby mode from debugfs Okay! Commit: drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 Okay! Commit: drm/i915/psr: Remove alpm from i915_psr -drivers/gpu/drm/i915/selftests/../i915_drv.h:3726:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3725:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Optionally disable automatic recovery after a GPU reset (rev2)
== Series Details ==
Series: drm/i915: Optionally disable automatic recovery after a GPU reset (rev2)
URL : https://patchwork.freedesktop.org/series/50458/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4919_full -> Patchwork_10339_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10339_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10339_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10339_full:
=== IGT changes ===
Possible regressions
igt@gem_ctx_param@invalid-param-get:
shard-skl: PASS -> FAIL +1
shard-apl: PASS -> FAIL +1
shard-glk: PASS -> FAIL +1
igt@gem_ctx_param@invalid-param-set:
shard-kbl: PASS -> FAIL +1
shard-hsw: PASS -> FAIL +1
shard-snb: PASS -> FAIL +1
== Known issues ==
Here are the changes found in Patchwork_10339_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@drv_suspend@debugfs-reader:
shard-skl: NOTRUN -> INCOMPLETE (fdo#104108, fdo#107773) +1
igt@gem_exec_big:
shard-hsw: PASS -> TIMEOUT (fdo#107937)
igt@gem_userptr_blits@readonly-unsync:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: PASS -> FAIL (fdo#103232) +4
igt@kms_cursor_crc@cursor-128x42-onscreen:
shard-glk: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: PASS -> FAIL (fdo#103232, fdo#103191)
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
shard-glk: PASS -> FAIL (fdo#103167) +3
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-apl: PASS -> FAIL (fdo#103167) +3
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763)
{igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max}:
shard-skl: NOTRUN -> FAIL (fdo#108145)
{igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max}:
shard-glk: PASS -> FAIL (fdo#108145) +2
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166) +4
igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108)
igt@kms_vblank@pipe-c-ts-continuation-suspend:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@pm_rpm@fences:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
Possible fixes
igt@kms_busy@extended-pageflip-hang-newfb-render-c:
shard-apl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-kbl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_cursor_crc@cursor-128x42-random:
shard-skl: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-256x256-sliding:
shard-glk: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
shard-skl: FAIL (fdo#103184) -> PASS +1
igt@kms_draw_crc@draw-method-xrgb-pwrite-ytiled:
shard-glk: FAIL -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
shard-skl: FAIL (fdo#103167) -> PASS +5
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
shard-skl: FAIL (fdo#105682) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
shard-apl: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-glk: FAIL (fdo#103167) -> PASS +3
igt@kms_plane@pixel-format-pipe-a-planes:
shard-glk: FAIL (fdo#103166) -> PASS
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-apl: FAIL (fdo#103166) -> PASS +3
{igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
shard-skl: FAIL (fdo#108145) -> PASS
{igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb}:
shard-glk: FAIL (fdo#108145) -> PASS
{name}: This element is
[Intel-gfx] [PATCH v4 5/7] drm/i915/psr: Remove main link standby mode from debugfs
Main link stand by is only valid for PSR1 as it is not possible to
enable PSR2 and keep main link on but even for PSR1 it is not useful
information and it can be removed without any drawbacks.
But if someone still wants to check that this patch is providing the
full PSR_CTL register value so user can check if bit 27 is set, this
will also expose more information about how PSR1 and PSR2 was
configured in source.
Cc: Dhinakaran Pandiyan
Suggested-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f42e93b71e67..48e65becd035 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2712,8 +2712,8 @@ psr_source_status(struct drm_i915_private *dev_priv,
struct seq_file *m)
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- u32 psrperf = 0;
- bool enabled = false;
+ u32 val;
+ bool enabled;
bool sink_support;
if (!HAS_PSR(dev_priv))
@@ -2733,24 +2733,23 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
dev_priv->psr.busy_frontbuffer_bits);
- if (dev_priv->psr.psr2_enabled)
- enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
- else
- enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
-
- seq_printf(m, "Main link in standby mode: %s\n",
- yesno(dev_priv->psr.link_standby));
+ if (dev_priv->psr.psr2_enabled) {
+ val = I915_READ(EDP_PSR2_CTL);
+ enabled = val & EDP_PSR2_ENABLE;
+ } else {
+ val = I915_READ(EDP_PSR_CTL);
+ enabled = val & EDP_PSR_ENABLE;
+ }
- seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
+ seq_printf(m, "HW enabled: %s [0x%x]\n", yesno(enabled), val);
/*
* SKL+ Perf counter is reset to 0 everytime DC state is entered
*/
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- psrperf = I915_READ(EDP_PSR_PERF_CNT) &
- EDP_PSR_PERF_CNT_MASK;
+ val = I915_READ(EDP_PSR_PERF_CNT) & EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, "Performance_Counter: %u\n", psrperf);
+ seq_printf(m, "Performance_Counter: %u\n", val);
}
psr_source_status(dev_priv, m);
--
2.19.0
___
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[Intel-gfx] [PATCH v4 1/7] drm/i915/psr: Share PSR and PSR2 exit mask
Now both PSR and PSR2 have the same exit mask, so let's share then
instead of have the same code 2 times.
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 34
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 83528647b40b..102da7aae9d8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -580,28 +580,20 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
else
chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
-
- I915_WRITE(EDP_PSR_DEBUG,
- EDP_PSR_DEBUG_MASK_MEMUP |
- EDP_PSR_DEBUG_MASK_HPD |
- EDP_PSR_DEBUG_MASK_LPSP |
- EDP_PSR_DEBUG_MASK_MAX_SLEEP |
- EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
- } else {
- /*
-* Per Spec: Avoid continuous PSR exit by masking MEMUP
-* and HPD. also mask LPSP to avoid dependency on other
-* drivers that might block runtime_pm besides
-* preventing other hw tracking issues now we can rely
-* on frontbuffer tracking.
-*/
- I915_WRITE(EDP_PSR_DEBUG,
- EDP_PSR_DEBUG_MASK_MEMUP |
- EDP_PSR_DEBUG_MASK_HPD |
- EDP_PSR_DEBUG_MASK_LPSP |
- EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
- EDP_PSR_DEBUG_MASK_MAX_SLEEP);
}
+
+ /*
+* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
+* mask LPSP to avoid dependency on other drivers that might block
+* runtime_pm besides preventing other hw tracking issues now we
+* can rely on frontbuffer tracking.
+*/
+ I915_WRITE(EDP_PSR_DEBUG,
+ EDP_PSR_DEBUG_MASK_MEMUP |
+ EDP_PSR_DEBUG_MASK_HPD |
+ EDP_PSR_DEBUG_MASK_LPSP |
+ EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
+ EDP_PSR_DEBUG_MASK_MAX_SLEEP);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
--
2.19.0
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[Intel-gfx] [PATCH v4 2/7] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
ICL spec states that this bit is now reserved.
Bspec: 7722
v2(Dhinakaran and Jani):
- instead of remove bit in gen11 now only setting if if gen < 11
- changed commit title
Cc: Jani Nikula
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_psr.c | 16 ++--
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507cfb9b..aff6f6754d79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4195,7 +4195,7 @@ enum {
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
-#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1 << 16)
+#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1 << 16) /* Reserved in ICL+ */
#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
#define EDP_PSR2_CTL _MMIO(0x6f900)
@@ -4232,7 +4232,7 @@ enum {
#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
-#define PSR_EVENT_REGISTER_UPDATE (1 << 5)
+#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
#define PSR_EVENT_HDCP_ENABLE (1 << 4)
#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
#define PSR_EVENT_VBI_ENABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 102da7aae9d8..5006b30b848d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -563,6 +563,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 mask;
/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
* use hardcoded values PSR AUX transactions
@@ -588,12 +589,15 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
* runtime_pm besides preventing other hw tracking issues now we
* can rely on frontbuffer tracking.
*/
- I915_WRITE(EDP_PSR_DEBUG,
- EDP_PSR_DEBUG_MASK_MEMUP |
- EDP_PSR_DEBUG_MASK_HPD |
- EDP_PSR_DEBUG_MASK_LPSP |
- EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
- EDP_PSR_DEBUG_MASK_MAX_SLEEP);
+ mask = EDP_PSR_DEBUG_MASK_MEMUP |
+ EDP_PSR_DEBUG_MASK_HPD |
+ EDP_PSR_DEBUG_MASK_LPSP |
+ EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
+
+ I915_WRITE(EDP_PSR_DEBUG, mask);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
--
2.19.0
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[Intel-gfx] [PATCH v4 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
wrong value.
v4: rebased on top of the patch removing link standby from debugfs
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 423cdf84059c..26317a4e03d2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -346,12 +346,14 @@ static void intel_psr_enable_sink(struct intel_dp
*intel_dp)
drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE);
dpcd_val |= DP_PSR_ENABLE_PSR2;
+ } else {
+ if (dev_priv->psr.link_standby)
+ dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+
+ if (INTEL_GEN(dev_priv) >= 8)
+ dpcd_val |= DP_PSR_CRC_VERIFICATION;
}
- if (dev_priv->psr.link_standby)
- dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
- if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
- dpcd_val |= DP_PSR_CRC_VERIFICATION;
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
--
2.19.0
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[Intel-gfx] [PATCH v4 4/7] drm/i915/psr: Use WA to force HW tracking to exit PSR2
This WA also works fine for PSR2, triggering a selective update when
possible.
Acked-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 1c4beaca1c0f..423cdf84059c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1027,20 +1027,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
/* By definition flush = invalidate + flush */
if (frontbuffer_bits) {
- if (dev_priv->psr.psr2_enabled) {
- intel_psr_exit(dev_priv);
- } else {
- /*
-* Display WA #0884: all
-* This documented WA for bxt can be safely applied
-* broadly so we can force HW tracking to exit PSR
-* instead of disabling and re-enabling.
-* Workaround tells us to write 0 to CUR_SURFLIVE_A,
-* but it makes more sense write to the current active
-* pipe.
-*/
- I915_WRITE(CURSURFLIVE(pipe), 0);
- }
+ /*
+* Display WA #0884: all
+* This documented WA for bxt can be safely applied
+* broadly so we can force HW tracking to exit PSR
+* instead of disabling and re-enabling.
+* Workaround tells us to write 0 to CUR_SURFLIVE_A,
+* but it makes more sense write to the current active
+* pipe.
+*/
+ I915_WRITE(CURSURFLIVE(pipe), 0);
}
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
--
2.19.0
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[Intel-gfx] [PATCH v4 7/7] drm/i915/psr: Remove alpm from i915_psr
ALPM is a requirement and we don't need to keep it's cached, what
were done in commit 97c9de66ca80
("drm/i915/psr: Fix ALPM cap check for PSR2") but the alpm was not
removed from i915_psr.
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2264b30ce51a..7ddbb7f460c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -634,7 +634,6 @@ struct i915_psr {
bool sink_psr2_support;
bool link_standby;
bool colorimetry_support;
- bool alpm;
bool psr2_enabled;
u8 sink_sync_latency;
ktime_t last_entry_attempt;
--
2.19.0
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[Intel-gfx] [PATCH v4 3/7] drm/i915/psr: Remove PSR2 TODO error handling
We are already handling all PSR2 errors, so we can drop this TODO. Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 5006b30b848d..1c4beaca1c0f 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -1128,8 +1128,6 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) intel_psr_disable_locked(intel_dp); /* clear status register */ drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS, val); - - /* TODO: handle PSR2 errors */ exit: mutex_unlock(>lock); } -- 2.19.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/18] drm/vc4: Use drm_atomic_helper_shutdown
Daniel Vetter writes: > drm_plane_helper_disable is a non-atomic drivers only function, and > will blow up (since no one passes the locking context it needs). > > Atomic drivers which want to quiescent their hw on unload should > use drm_atomic_helper_shutdown() instead. > > v2: Rebase. I've definitely never tested unload. Looks like we could drop vc4_plane_destroy() entirely? Regardless, acked-by. signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm/i915/dp: Remove i915.enable_dp_mst module parameter
On Wed, Oct 03, 2018 at 12:36:01PM -0700, Dhinakaran Pandiyan wrote:
> MST is enabled by default on all platforms that support it. I don't think
> we should be providing a switch to work around MST issues as the feature
> has been supported for a while now. Let's kill this module parameter
> that we also do not test in CI.
>
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_params.c | 3 ---
> drivers/gpu/drm/i915/i915_params.h | 1 -
> drivers/gpu/drm/i915/intel_dp.c| 6 --
> 3 files changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index bd6bd8879cab..ea5961ae6803 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -156,9 +156,6 @@ i915_param_named_unsafe(huc_firmware_path, charp, 0400,
> i915_param_named_unsafe(dmc_firmware_path, charp, 0400,
> "DMC firmware path to use instead of the default one");
>
> -i915_param_named_unsafe(enable_dp_mst, bool, 0600,
> - "Enable multi-stream transport (MST) for new DisplayPort sinks.
> (default: true)");
> -
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
> i915_param_named_unsafe(inject_load_failure, uint, 0400,
> "Force an error after a number of failure check points (0:disabled
> (default), N:force failure at the Nth failure check point)");
> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> index 7e56c516c815..5d995af2ef58 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -65,7 +65,6 @@ struct drm_printer;
> param(bool, disable_display, false) \
> param(bool, verbose_state_checks, true) \
> param(bool, nuclear_pageflip, false) \
> - param(bool, enable_dp_mst, true) \
> param(bool, enable_dpcd_backlight, false) \
> param(bool, enable_gvt, false)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 15a981ef5966..b0d8baae6d96 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4054,9 +4054,6 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
> {
> u8 mstm_cap;
>
> - if (!i915_modparams.enable_dp_mst)
> - return false;
> -
> if (!intel_dp->can_mst)
> return false;
>
> @@ -4072,9 +4069,6 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
> static void
> intel_dp_configure_mst(struct intel_dp *intel_dp)
> {
> - if (!i915_modparams.enable_dp_mst)
> - return;
> -
> if (!intel_dp->can_mst)
> return;
>
> --
> 2.17.1
>
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[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, Here goes drm-intel-fixes-2018-10-03: There's one fix for our zlib incomlete Z_FINISH on our error state handling, plus a compilation warning fix and a tiny code clean up. Thanks, Rodrigo. The following changes since commit 17b57b1883c1285f3d0dc2266e8f79286a7bef38: Linux 4.19-rc6 (2018-09-30 07:15:35 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-10-03 for you to fetch changes up to 4c9613ce556fdeb671e779668b627ea3a2b61728: drm/i915: Handle incomplete Z_FINISH for compressed error states (2018-10-03 08:02:42 -0700) There's one fix for our zlib incomlete Z_FINISH on our error state handling , plus a compilation warning fix and a tiny code clean up. Anusha Srivatsa (1): drm/i915: Do not redefine the has_csr parameter. Chris Wilson (2): drm/i915: Avoid compiler warning for maybe unused gu_misc_iir drm/i915: Handle incomplete Z_FINISH for compressed error states drivers/gpu/drm/i915/i915_gpu_error.c | 88 +-- drivers/gpu/drm/i915/i915_gpu_error.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 33 + drivers/gpu/drm/i915/i915_pci.c | 1 - 4 files changed, 76 insertions(+), 47 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Always try to reset the GPU on takeover (rev2)
== Series Details == Series: drm/i915: Always try to reset the GPU on takeover (rev2) URL : https://patchwork.freedesktop.org/series/50497/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4924 -> Patchwork_10350 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50497/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10350 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@cs-compute: fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094) igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@drv_module_reload@basic-no-display: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725) igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: PASS -> DMESG-WARN (fdo#107139, fdo#105128) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@pm_rpm@module-reload: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) Possible fixes igt@drv_selftest@live_hangcheck: fi-cfl-8109u: INCOMPLETE -> PASS igt@gem_exec_suspend@basic-s3: fi-cfl-8109u: DMESG-WARN (fdo#107345) -> PASS +3 igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094 == Participating hosts (48 -> 40) == Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_4924 -> Patchwork_10350 CI_DRM_4924: f75010b928b4b4cde8a1d2ce0c2bea516b3ba111 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10350: 1aafa2b64a2e0770558c45c6a2d17a9dea159324 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1aafa2b64a2e drm/i915: Always try to reset the GPU on takeover == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10350/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] pci: Add a few new IDs for Intel GPU "spurious interrupt" quirk
On Thu, Sep 27, 2018 at 10:10:07AM +0800, Bin Meng wrote:
> On Thu, Sep 27, 2018 at 12:57 AM Bjorn Helgaas wrote:
> > On Wed, Sep 26, 2018 at 08:14:01AM -0700, Bin Meng wrote:
> > > Add more PCI IDs to the Intel GPU "spurious interrupt" quirk table,
> > > which are known to break.
> >
> > Do you have a reference for this? Any public bug reports, bugzilla,
> > Intel spec reference or errata? "Which are known to break" is pretty
> > vague.
>
> Sorry I used wrong words and should have been clearer. These devices
> are validated to be broken. The test I used is very simple, just
> unplug the VGA cable and plug it again, and "spurious interrupt" will
> be seen on the interrupt line of the IGD device. I was not aware of
> any public bugs filed to Intel, nor seen any errata from Intel.
The original commit, f67fd55fa96f ("PCI: Add quirk for still enabled
interrupts on Intel Sandy Bridge GPUs"), says some systems "crash"
(not sure if that means an oops or an actual crash that requires a
reboot) and on other systems, Linux disables the shared interrupt
line. I assume disabling the interrupt line keeps devices using that
line from working, but does not directly cause a crash.
What specific symptom do you see here? I think it might be useful to
collect details, e.g., dmesg logs, /proc/interrupts contents, output
of "sudo lspci -vv", etc., for the systems you're quirking here. I'm
hoping we can eventually figure out a solution that doesn't require a
quirk for every new GPU, and maybe that info will help find it.
> > > See commit f67fd55fa96f ("PCI: Add quirk for still enabled interrupts
> > > on Intel Sandy Bridge GPUs"), and commit 7c82126a94e6 ("PCI: Add new
> > > ID for Intel GPU "spurious interrupt" quirk") for some history.
> > >
> > > Based on current findings, it is highly possible that all Intel
> > > 1st/2nd/3rd generation Core processors' IGD has such quirk.
> >
> > Can you include a reference to these "current findings"? I assume you
> > have bug reports that include the device IDs you're adding? If not,
> > how did you build this list of new IDs?
>
> By "current findings" I mean given the IDs we have here, plus previous
> one added by Thomas, it's highly possible this VGA BIOS bug exists in
> every 1st/2nd/3rd generation Core processors.
>
> > The function comment added by f67fd55fa96f ("PCI: Add quirk for still
> > enabled interrupts on Intel Sandy Bridge GPUs") suggests that this is
> > actually a BIOS issue, not a hardware erratum, i.e., I don't see
> > anything there that suggests a hardware defect.
> >
> > But there must be a hole somewhere -- the kernel can't be expected to
> > disable interrupts in device-specific ways when there's no driver
> > loaded. Maybe it's simply a BIOS defect or maybe there's some
> > interrupt or _PRT-related setup we're missing.
>
> It's a pure VGA BIOS bug, not the BIOS bug or _PRT etc. The VGA BIOS
> forgot to turn off the interrupt on these devices.
If this is a VGA BIOS defect, it's not very likely that it will
magically be fixed for all new Intel GPUs, so in effect it sounds like
we need to update this list of quirks in Linux every time a new Intel
GPU comes out. That prospect is a little daunting.
Do you happen to know if Windows has the same problem? I.e., if you
boot an old version of Windows with a new GPU, and unplug the VGA
cable, does Windows crash? If Windows can figure out how to handle
that situation gracefully, Linux should be able to do it, too.
> > > Signed-off-by: Bin Meng
> > > Cc: # v3.4+
> > > ---
> > >
> > > drivers/pci/quirks.c | 4
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > > index 6bc27b7..c0673a7 100644
> > > --- a/drivers/pci/quirks.c
> > > +++ b/drivers/pci/quirks.c
> > > @@ -3190,7 +3190,11 @@ static void disable_igfx_irq(struct pci_dev *dev)
> > >
> > > pci_iounmap(dev, regs);
> > > }
> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
> > > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
> > > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
> > > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
> > >
> > > --
>
> Regards,
> Bin
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Remove i915.enable_dp_mst module parameter
== Series Details == Series: drm/i915/dp: Remove i915.enable_dp_mst module parameter URL : https://patchwork.freedesktop.org/series/50520/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4924 -> Patchwork_10349 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50520/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10349 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@cs-compute: fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094) igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@pm_rpm@module-reload: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097, fdo#107726) Possible fixes igt@drv_selftest@live_hangcheck: fi-cfl-8109u: INCOMPLETE -> PASS igt@gem_exec_suspend@basic-s3: fi-cfl-8109u: DMESG-WARN (fdo#107345) -> PASS +3 igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094 == Participating hosts (48 -> 43) == Additional (1): fi-pnv-d510 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4924 -> Patchwork_10349 CI_DRM_4924: f75010b928b4b4cde8a1d2ce0c2bea516b3ba111 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10349: ef22f18114f650bad88045f81d4e659c45330ebb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ef22f18114f6 drm/i915/dp: Remove i915.enable_dp_mst module parameter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10349/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next-fixes for 4.20
Hi Dave, We've cut over to misc-next-fixes for 4.20, so just one patch this week. It's Neil's fix for mali binary driver. drm-misc-next-fixes-2018-10-03: - Add EXPERT config option to allow phys mem leak from fbdev for blob drivers (Neil) Cc: Neil Armstrong Cheers, Sean The following changes since commit 87c2ee740c07f1edae9eec8bc45cb9b32a68f323: Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next (2018-09-28 09:48:40 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2018-10-03 for you to fetch changes up to 4be9bd10e22dfc7fc101c5cf5969ef2d3a042d8a: drm/fb_helper: Allow leaking fbdev smem_start (2018-10-03 21:08:21 +0200) - Add EXPERT config option to allow phys mem leak from fbdev for blob drivers (Neil) Cc: Neil Armstrong Neil Armstrong (1): drm/fb_helper: Allow leaking fbdev smem_start drivers/gpu/drm/Kconfig | 20 drivers/gpu/drm/drm_fb_helper.c | 33 +++-- 2 files changed, 51 insertions(+), 2 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Always try to reset the GPU on takeover
When we first introduced the reset to sanitize the GPU on taking over
from the BIOS and before returning control to third parties (the BIOS!),
we restricted it to only systems utilizing HW contexts as we were
uncertain of how stable our reset mechanism truly was. We now have
reasonable coverage across all machines that expose a GPU reset method,
and so we should be safe to sanitize the GPU state everywhere.
v2: We _have_ to skip the reset if it would clobber the display.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 11 ++-
drivers/gpu/drm/i915/i915_pci.c | 5 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_engine_cs.c | 4
5 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7d45e71100bc..50a87272af12 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3441,8 +3441,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
i915_retire_requests(i915);
GEM_BUG_ON(i915->gt.active_requests);
- if (!intel_gpu_reset(i915, ALL_ENGINES))
- intel_engines_sanitize(i915);
+ intel_engines_sanitize(i915);
/*
* Undo nop_submit_request. We prevent all new i915 requests from
@@ -5034,8 +5033,6 @@ void __i915_gem_object_release_unless_active(struct
drm_i915_gem_object *obj)
void i915_gem_sanitize(struct drm_i915_private *i915)
{
- int err;
-
GEM_TRACE("\n");
mutex_lock(>drm.struct_mutex);
@@ -5060,11 +5057,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
* it may impact the display and we are uncertain about the stability
* of the reset, so this could be applied to even earlier gen.
*/
- err = -ENODEV;
- if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
- err = WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
- if (!err)
- intel_engines_sanitize(i915);
+ intel_engines_sanitize(i915);
intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
intel_runtime_pm_put(i915);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9ddd2db906ce..be0ae8a96fe9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -69,6 +69,7 @@
GEN(2), \
.num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
+ .gpu_reset_clobbers_display = true, \
.has_gmch_display = 1, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
@@ -109,6 +110,7 @@ static const struct intel_device_info intel_i865g_info = {
GEN(3), \
.num_pipes = 2, \
.has_gmch_display = 1, \
+ .gpu_reset_clobbers_display = true, \
.ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
@@ -179,6 +181,7 @@ static const struct intel_device_info intel_pineview_info =
{
.num_pipes = 2, \
.has_hotplug = 1, \
.has_gmch_display = 1, \
+ .gpu_reset_clobbers_display = true, \
.ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
@@ -208,6 +211,7 @@ static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
.ring_mask = RENDER_RING | BSD_RING,
+ .gpu_reset_clobbers_display = false,
};
static const struct intel_device_info intel_gm45_info = {
@@ -216,6 +220,7 @@ static const struct intel_device_info intel_gm45_info = {
.is_mobile = 1, .has_fbc = 1,
.supports_tv = 1,
.ring_mask = RENDER_RING | BSD_RING,
+ .gpu_reset_clobbers_display = false,
};
#define GEN5_FEATURES \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index af7002640cdf..a80a4627032e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -92,6 +92,7 @@ enum intel_ppgtt {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_fbc); \
func(has_fpga_dbg); \
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 36434c5359b1..9774a6b3a313 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3778,8 +3778,8 @@ __intel_display_resume(struct drm_device *dev,
static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
{
- return intel_has_gpu_reset(dev_priv) &&
- INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
+ return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
+ intel_has_gpu_reset(dev_priv));
}
void intel_prepare_reset(struct
[Intel-gfx] [RFC] drm/i915/dp: Remove i915.enable_dp_mst module parameter
MST is enabled by default on all platforms that support it. I don't think
we should be providing a switch to work around MST issues as the feature
has been supported for a while now. Let's kill this module parameter
that we also do not test in CI.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_params.c | 3 ---
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_dp.c| 6 --
3 files changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index bd6bd8879cab..ea5961ae6803 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -156,9 +156,6 @@ i915_param_named_unsafe(huc_firmware_path, charp, 0400,
i915_param_named_unsafe(dmc_firmware_path, charp, 0400,
"DMC firmware path to use instead of the default one");
-i915_param_named_unsafe(enable_dp_mst, bool, 0600,
- "Enable multi-stream transport (MST) for new DisplayPort sinks.
(default: true)");
-
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
i915_param_named_unsafe(inject_load_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c516c815..5d995af2ef58 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -65,7 +65,6 @@ struct drm_printer;
param(bool, disable_display, false) \
param(bool, verbose_state_checks, true) \
param(bool, nuclear_pageflip, false) \
- param(bool, enable_dp_mst, true) \
param(bool, enable_dpcd_backlight, false) \
param(bool, enable_gvt, false)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 15a981ef5966..b0d8baae6d96 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4054,9 +4054,6 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
{
u8 mstm_cap;
- if (!i915_modparams.enable_dp_mst)
- return false;
-
if (!intel_dp->can_mst)
return false;
@@ -4072,9 +4069,6 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
static void
intel_dp_configure_mst(struct intel_dp *intel_dp)
{
- if (!i915_modparams.enable_dp_mst)
- return;
-
if (!intel_dp->can_mst)
return;
--
2.17.1
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Re: [Intel-gfx] [PATCH] drm: Fix kernel doc for DRM_MODE_PROP_IMMUTABLE
On Tue, Oct 02, 2018 at 02:50:55PM -0700, Manasi Navare wrote:
> This patch explains the DRM_MODE_PROP_IMMUTABLE flag a bit better
> by telling which function to call if kernel wants to update
> drm object's immutable properties.
>
> Suggested-by: Daniel Vetter
> Cc: Daniel Vetter
> Signed-off-by: Manasi Navare
Reviewed-by: Daniel Vetter
> ---
> include/drm/drm_property.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h
> index 5b9efff35d6d..4a0a80d658c7 100644
> --- a/include/drm/drm_property.h
> +++ b/include/drm/drm_property.h
> @@ -153,7 +153,8 @@ struct drm_property {
>* userspace. The kernel is allowed to update the value of these
>* properties. This is generally used to expose probe state to
>* userspace, e.g. the EDID, or the connector path property on DP
> - * MST sinks.
> + * MST sinks. Kernel can update the value of an immutable property
> + * by calling drm_object_property_set_value().
>*/
> uint32_t flags;
>
> --
> 2.18.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Provide more clues as to why MST is/is not used
== Series Details == Series: drm/i915: Provide more clues as to why MST is/is not used URL : https://patchwork.freedesktop.org/series/50518/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4923 -> Patchwork_10348 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10348 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10348, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50518/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10348: === IGT changes === Warnings igt@pm_rpm@module-reload: fi-hsw-4770r: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10348 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-cfl-8109u: PASS -> INCOMPLETE (fdo#108126, fdo#107187) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 Possible fixes igt@drv_getparams_basic@basic-eu-total: fi-kbl-7560u: INCOMPLETE (fdo#103665) -> PASS igt@drv_module_reload@basic-reload: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: DMESG-WARN (fdo#107425, fdo#107924) -> PASS igt@gem_basic@bad-close: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS +1 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107187 https://bugs.freedesktop.org/show_bug.cgi?id=107187 fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126 == Participating hosts (49 -> 42) == Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-bdw-samus == Build changes == * Linux: CI_DRM_4923 -> Patchwork_10348 CI_DRM_4923: ebe8b202efb15420473f26d2386d1302bfc91429 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10348: 94e496dcb58633193bf44ec38387f250db43b48d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 94e496dcb586 drm/i915: Provide more clues as to why MST is/is not used == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10348/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Provide more clues as to why MST is/is not used
On Wednesday, October 3, 2018 11:42:10 AM PDT Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Always print out the information whether the port and sink can each
> do MST. And let's include the modparam in the debug output as well.
> Makes life a little less confusing when you don't have to wonder
> why MST isn't kicking in.
>
> This does cause a slight change in our behaviour towards the sink.
> Previously we only read the MSTM_CAP register after passing all
> the other checks. Now we will read that register regardless. Hopefully
> some crazy sink doesn't get confused by a simple register read.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp.c | 33 ++---
> 1 file changed, 18 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c index 15a981ef5966..1a510cf58fb5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4050,16 +4050,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> }
>
> static bool
> -intel_dp_can_mst(struct intel_dp *intel_dp)
> +intel_dp_sink_can_mst(struct intel_dp *intel_dp)
> {
> u8 mstm_cap;
>
> - if (!i915_modparams.enable_dp_mst)
> - return false;
> -
> - if (!intel_dp->can_mst)
> - return false;
> -
> if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
> return false;
>
> @@ -4069,21 +4063,30 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
> return mstm_cap & DP_MST_CAP;
> }
>
> +static bool
> +intel_dp_can_mst(struct intel_dp *intel_dp)
> +{
> + return i915_modparams.enable_dp_mst &&
> + intel_dp->can_mst &&
> + intel_dp_sink_can_mst(intel_dp);
> +}
> +
> static void
> intel_dp_configure_mst(struct intel_dp *intel_dp)
> {
> - if (!i915_modparams.enable_dp_mst)
> - return;
> + struct intel_encoder *encoder =
> + _to_dig_port(intel_dp)->base;
> + bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
> +
> + DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
> + port_name(encoder->port), yesno(intel_dp->can_mst),
> + yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
>
> if (!intel_dp->can_mst)
> return;
>
> - intel_dp->is_mst = intel_dp_can_mst(intel_dp);
> -
> - if (intel_dp->is_mst)
> - DRM_DEBUG_KMS("Sink is MST capable\n");
> - else
> - DRM_DEBUG_KMS("Sink is not MST capable\n");
> + intel_dp->is_mst = sink_can_mst &&
> + i915_modparams.enable_dp_mst;
Should we still keep this modparam around? I don't know if anyone actually
uses it to work around MST issues. Even if there are MST issues, we should be
fixing them.
I see the value in the debug message,
Reviewed-by: Dhinakaran Pandiyan
>
> drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
> intel_dp->is_mst);
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Re: [Intel-gfx] [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc
Alexandru-Cosmin Gheorghe kirjoitti 3.10.2018 klo 20.18:
On Wed, Oct 03, 2018 at 02:31:08PM +0300, Juha-Pekka Heikkila wrote:
Hi Alex,
For my patches there seems limited interest to get them merged before IGT
support these modes..I'm not holding my breath for this.
I'm interested if that counts.
I asked the same question on the DRM_FORMAT_XYUV thread, do we need to
wait for userspace to get new fourcc merged.
I'd say yes. Why would otherwise clutter headers which affect what other
guys are doing for different drivers?
If it makes any difference for you I made KMS video output plug-in for
VLC media player as part of my enablement of P01x formats. My plug-in
didn't make it to any VLC release yet but you can find it in VLC master
branch. Through my plug-in you can ask any fourcc for setting up KMS
planes, then you'll need to find which VLC fourcc matches your KMS plane
and tell VLC about it on commandline. If you have driver implementation
of P010 format which I saw earlier in your patch you can compile VLC
with P010 included in DRM headers and then you'll be able to watch
videos using your new format. For P01x formats recompile is needed as
their setup is different from other formats, packed formats should work
without anything special.
/Juha-Pekka
https://lists.freedesktop.org/archives/intel-gfx/2018-September/174877.html
/Juha-Pekka
On 02.10.2018 18:00, Alexandru-Cosmin Gheorghe wrote:
Hi,
How is this going on, anything holding it back from getting merged ?
I'm interested in adding/using P010, [1]
Thank you,
Alex Gheorghe
[1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186963.html
On Thu, Aug 30, 2018 at 03:41:11PM +0300, Juha-Pekka Heikkila wrote:
Add P010 definition, semi-planar yuv format where each component
is 16 bits 10 msb containing color value. First come Y plane [10:6]
followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
Add P012 definition, semi-planar yuv format where each component
is 16 bits 12 msb containing color value. First come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 10 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..32e07a2 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_P010,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P012,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P016,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9..daaabb1 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -178,6 +178,16 @@ extern "C" {
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /*
non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr
+ * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
+ * component xxx msb Y [xxx:16-xxx]
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian [xxx:16-xxx:xxx:16-xxx]
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2
subsampled Cr:Cb plane, 10 bit per channel */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2
subsampled Cr:Cb plane, 12 bit per channel */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2
subsampled Cr:Cb plane, 16 bit per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.7.4
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Re: [Intel-gfx] [PATCH v10 2/2] drm/i915: Allow "max bpc" property to limit pipe_bpp
On Wed, Oct 03, 2018 at 11:42:14AM -0700, Radhakrishna Sripada wrote:
> On Mon, Oct 01, 2018 at 04:48:01PM +0300, Ville Syrjälä wrote:
> > On Mon, Sep 24, 2018 at 02:08:15PM -0700, Radhakrishna Sripada wrote:
> > > Use the newly added "max bpc" connector property to limit pipe bpp.
> > >
> > > V3: Use drm_connector_state to access the "max bpc" property
> > > V4: Initialize the drm property, add suuport to DP(Ville)
> > > V5: Use the property in the connector and fix CI failure(Ville)
> > > V6: Use the core function to attach max_bpc property, remove the redundant
> > > clamping of pipe bpp based on connector info
> > > V7: Fix Checkpatch warnings
> > > V9: Cleanup connected_sink_max_bpp and fix initial value in DP(Ville)
> > >
> > > Cc: Ville Syrjälä
> > > Cc: Daniel Vetter
> > > Cc: Rodrigo Vivi
> > > Cc: Kishore Kadiyala
> > > Cc: Manasi Navare
> > > Cc: Stanislav Lisovskiy
> > > Signed-off-by: Radhakrishna Sripada
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 48
> > > +---
> > > drivers/gpu/drm/i915/intel_dp.c | 4 +++
> > > drivers/gpu/drm/i915/intel_hdmi.c| 5
> > > 3 files changed, 37 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 931898013506..057abfd77cc3 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -10839,30 +10839,38 @@ static void
> > > intel_modeset_update_connector_atomic_state(struct drm_device *dev)
> > > drm_connector_list_iter_end(_iter);
> > > }
> > >
> > > -static void
> > > -connected_sink_compute_bpp(struct intel_connector *connector,
> > > -struct intel_crtc_state *pipe_config)
> > > +static int
> > > +connected_sink_max_bpp(const struct drm_connector_state *conn_state,
> > > +struct intel_crtc_state *pipe_config)
> > > {
> > > - const struct drm_display_info *info = >base.display_info;
> > > - int bpp = pipe_config->pipe_bpp;
> > > + int bpp;
> > > + struct drm_display_info *info = _state->connector->display_info;
> > >
> > > - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
> > > - connector->base.base.id,
> > > - connector->base.name);
> > > + bpp = min(pipe_config->pipe_bpp, conn_state->max_bpc * 3);
> >
> > Needs a check to make sure the connector has the property.
> We do make a check for the connector property in the drm core. In the absence
> of the property, conn_state->max_bpc carries the limit imposed from
> connector->display_info.bpc and would be requiring the codepath below.
Ah yes. That part is perfectly good then.
>
> Thoughts?
>
> -- Radhakrishna Sripada
> >
> > >
> > > - /* Don't use an invalid EDID bpc value */
> > > - if (info->bpc != 0 && info->bpc * 3 < bpp) {
> > > - DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported
> > > max of %d\n",
> > > - bpp, info->bpc * 3);
> > > - pipe_config->pipe_bpp = info->bpc * 3;
> > > + switch (conn_state->max_bpc) {
> > > + case 6 ... 7:
> > > + pipe_config->pipe_bpp = 6 * 3;
> > > + case 8 ... 9:
> > > + pipe_config->pipe_bpp = 8 * 3;
> > > + break;
> > > + case 10 ... 11:
> > > + pipe_config->pipe_bpp = 10 * 3;
> > > + break;
> > > + case 12:
> > > + pipe_config->pipe_bpp = 12 * 3;
> > > + break;
> > > + default:
> > > + return -EINVAL;
> > > }
> > >
> > > - /* Clamp bpp to 8 on screens without EDID 1.4 */
> > > - if (info->bpc == 0 && bpp > 24) {
> > > - DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit
> > > of 24\n",
> > > - bpp);
> > > - pipe_config->pipe_bpp = 24;
> > > + if (bpp != pipe_config->pipe_bpp) {
> > > + DRM_DEBUG_KMS("Limiting display bpp to %d instead of requested "
> > > + "bpp %d, Edid bpp %d\n", bpp, 3 * info->bpc,
> > > + 3 * conn_state->max_requested_bpc);
> >
> > The format string doesn't seem to match the arguments.
> >
> > > + pipe_config->pipe_bpp = bpp;
> > > }
> > > + return 0;
> > > }
> > >
> > > static int
> > > @@ -10893,8 +10901,8 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> > > if (connector_state->crtc != >base)
> > > continue;
> > >
> > > - connected_sink_compute_bpp(to_intel_connector(connector),
> > > -pipe_config);
> > > + if (connected_sink_max_bpp(connector_state, pipe_config) < 0)
> > > + return -EINVAL;
> > > }
> > >
> > > return bpp;
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 6b4c19123f2a..d8e128e771a1 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -5719,6 +5719,10 @@
[Intel-gfx] [PATCH] drm/i915: Provide more clues as to why MST is/is not used
From: Ville Syrjälä
Always print out the information whether the port and sink can each
do MST. And let's include the modparam in the debug output as well.
Makes life a little less confusing when you don't have to wonder
why MST isn't kicking in.
This does cause a slight change in our behaviour towards the sink.
Previously we only read the MSTM_CAP register after passing all
the other checks. Now we will read that register regardless. Hopefully
some crazy sink doesn't get confused by a simple register read.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 15a981ef5966..1a510cf58fb5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4050,16 +4050,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
}
static bool
-intel_dp_can_mst(struct intel_dp *intel_dp)
+intel_dp_sink_can_mst(struct intel_dp *intel_dp)
{
u8 mstm_cap;
- if (!i915_modparams.enable_dp_mst)
- return false;
-
- if (!intel_dp->can_mst)
- return false;
-
if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
return false;
@@ -4069,21 +4063,30 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
return mstm_cap & DP_MST_CAP;
}
+static bool
+intel_dp_can_mst(struct intel_dp *intel_dp)
+{
+ return i915_modparams.enable_dp_mst &&
+ intel_dp->can_mst &&
+ intel_dp_sink_can_mst(intel_dp);
+}
+
static void
intel_dp_configure_mst(struct intel_dp *intel_dp)
{
- if (!i915_modparams.enable_dp_mst)
- return;
+ struct intel_encoder *encoder =
+ _to_dig_port(intel_dp)->base;
+ bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
+
+ DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
+ port_name(encoder->port), yesno(intel_dp->can_mst),
+ yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
if (!intel_dp->can_mst)
return;
- intel_dp->is_mst = intel_dp_can_mst(intel_dp);
-
- if (intel_dp->is_mst)
- DRM_DEBUG_KMS("Sink is MST capable\n");
- else
- DRM_DEBUG_KMS("Sink is not MST capable\n");
+ intel_dp->is_mst = sink_can_mst &&
+ i915_modparams.enable_dp_mst;
drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
intel_dp->is_mst);
--
2.16.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix the HDMI hot plug disconnection failure (rev2)
== Series Details == Series: drm/i915: Fix the HDMI hot plug disconnection failure (rev2) URL : https://patchwork.freedesktop.org/series/50477/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4923 -> Patchwork_10347 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10347 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10347, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50477/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10347: === IGT changes === Possible regressions igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN fi-elk-e7500: PASS -> DMESG-WARN Warnings igt@pm_rpm@module-reload: fi-hsw-4770r: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10347 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_sanitycheck: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) igt@gem_exec_suspend@basic-s3: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: PASS -> DMESG-WARN (fdo#107139, fdo#105128) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) Possible fixes igt@drv_getparams_basic@basic-eu-total: fi-kbl-7560u: INCOMPLETE (fdo#103665) -> PASS igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: DMESG-WARN (fdo#107425, fdo#107924) -> PASS igt@gem_basic@bad-close: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS +1 igt@pm_rpm@module-reload: fi-glk-j4005: DMESG-WARN (fdo#107726) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139 fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 == Participating hosts (49 -> 42) == Additional (1): fi-pnv-d510 Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bwr-2160 fi-bsw-cyan fi-ctg-p8600 fi-blb-e6850 == Build changes == * Linux: CI_DRM_4923 -> Patchwork_10347 CI_DRM_4923: ebe8b202efb15420473f26d2386d1302bfc91429 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10347: b2aa0791339bd4d8cbbb956c7dd423e8d0f419f5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b2aa0791339b drm/i915: Fix the HDMI hot plug disconnection failure (v2) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10347/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 2/2] drm/i915: Allow "max bpc" property to limit pipe_bpp
On Mon, Oct 01, 2018 at 04:48:01PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 24, 2018 at 02:08:15PM -0700, Radhakrishna Sripada wrote:
> > Use the newly added "max bpc" connector property to limit pipe bpp.
> >
> > V3: Use drm_connector_state to access the "max bpc" property
> > V4: Initialize the drm property, add suuport to DP(Ville)
> > V5: Use the property in the connector and fix CI failure(Ville)
> > V6: Use the core function to attach max_bpc property, remove the redundant
> > clamping of pipe bpp based on connector info
> > V7: Fix Checkpatch warnings
> > V9: Cleanup connected_sink_max_bpp and fix initial value in DP(Ville)
> >
> > Cc: Ville Syrjälä
> > Cc: Daniel Vetter
> > Cc: Rodrigo Vivi
> > Cc: Kishore Kadiyala
> > Cc: Manasi Navare
> > Cc: Stanislav Lisovskiy
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 48
> > +---
> > drivers/gpu/drm/i915/intel_dp.c | 4 +++
> > drivers/gpu/drm/i915/intel_hdmi.c| 5
> > 3 files changed, 37 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 931898013506..057abfd77cc3 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10839,30 +10839,38 @@ static void
> > intel_modeset_update_connector_atomic_state(struct drm_device *dev)
> > drm_connector_list_iter_end(_iter);
> > }
> >
> > -static void
> > -connected_sink_compute_bpp(struct intel_connector *connector,
> > - struct intel_crtc_state *pipe_config)
> > +static int
> > +connected_sink_max_bpp(const struct drm_connector_state *conn_state,
> > + struct intel_crtc_state *pipe_config)
> > {
> > - const struct drm_display_info *info = >base.display_info;
> > - int bpp = pipe_config->pipe_bpp;
> > + int bpp;
> > + struct drm_display_info *info = _state->connector->display_info;
> >
> > - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
> > - connector->base.base.id,
> > - connector->base.name);
> > + bpp = min(pipe_config->pipe_bpp, conn_state->max_bpc * 3);
>
> Needs a check to make sure the connector has the property.
We do make a check for the connector property in the drm core. In the absence
of the property, conn_state->max_bpc carries the limit imposed from
connector->display_info.bpc and would be requiring the codepath below.
Thoughts?
-- Radhakrishna Sripada
>
> >
> > - /* Don't use an invalid EDID bpc value */
> > - if (info->bpc != 0 && info->bpc * 3 < bpp) {
> > - DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported
> > max of %d\n",
> > - bpp, info->bpc * 3);
> > - pipe_config->pipe_bpp = info->bpc * 3;
> > + switch (conn_state->max_bpc) {
> > + case 6 ... 7:
> > + pipe_config->pipe_bpp = 6 * 3;
> > + case 8 ... 9:
> > + pipe_config->pipe_bpp = 8 * 3;
> > + break;
> > + case 10 ... 11:
> > + pipe_config->pipe_bpp = 10 * 3;
> > + break;
> > + case 12:
> > + pipe_config->pipe_bpp = 12 * 3;
> > + break;
> > + default:
> > + return -EINVAL;
> > }
> >
> > - /* Clamp bpp to 8 on screens without EDID 1.4 */
> > - if (info->bpc == 0 && bpp > 24) {
> > - DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit
> > of 24\n",
> > - bpp);
> > - pipe_config->pipe_bpp = 24;
> > + if (bpp != pipe_config->pipe_bpp) {
> > + DRM_DEBUG_KMS("Limiting display bpp to %d instead of requested "
> > + "bpp %d, Edid bpp %d\n", bpp, 3 * info->bpc,
> > + 3 * conn_state->max_requested_bpc);
>
> The format string doesn't seem to match the arguments.
>
> > + pipe_config->pipe_bpp = bpp;
> > }
> > + return 0;
> > }
> >
> > static int
> > @@ -10893,8 +10901,8 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> > if (connector_state->crtc != >base)
> > continue;
> >
> > - connected_sink_compute_bpp(to_intel_connector(connector),
> > - pipe_config);
> > + if (connected_sink_max_bpp(connector_state, pipe_config) < 0)
> > + return -EINVAL;
> > }
> >
> > return bpp;
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6b4c19123f2a..d8e128e771a1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -5719,6 +5719,10 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> > struct drm_connector *connect
> > intel_attach_force_audio_property(connector);
> >
> > intel_attach_broadcast_rgb_property(connector);
> > + if (HAS_GMCH_DISPLAY(dev_priv))
> > +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Cache the error string (rev5)
== Series Details ==
Series: drm/i915: Cache the error string (rev5)
URL : https://patchwork.freedesktop.org/series/46777/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4919_full -> Patchwork_10338_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10338_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_userptr_blits@readonly-unsync:
shard-skl: PASS -> INCOMPLETE (fdo#108074)
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: PASS -> FAIL (fdo#103232) +3
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: PASS -> FAIL (fdo#103191, fdo#103232)
igt@kms_fbcon_fbt@psr-suspend:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_flip@flip-vs-expired-vblank:
shard-skl: NOTRUN -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-apl: PASS -> FAIL (fdo#103167) +1
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
shard-glk: PASS -> FAIL (fdo#103167) +1
{igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max}:
shard-skl: NOTRUN -> FAIL (fdo#108145) +1
{igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max}:
shard-glk: PASS -> FAIL (fdo#108145) +1
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-apl: PASS -> FAIL (fdo#103166) +1
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166)
igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +2
igt@kms_sysfs_edid_timing:
shard-skl: NOTRUN -> FAIL (fdo#100047)
igt@pm_rpm@system-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107807)
Possible fixes
igt@kms_cursor_crc@cursor-128x42-random:
shard-skl: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-256x256-random:
shard-glk: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
shard-skl: FAIL (fdo#105682) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
shard-apl: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS +3
igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc:
shard-skl: FAIL (fdo#103167) -> PASS +1
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-apl: FAIL (fdo#103166) -> PASS +2
{igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
shard-skl: FAIL (fdo#108145) -> PASS
igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
shard-glk: FAIL (fdo#103166) -> PASS +1
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
Warnings
{igt@kms_plane_alpha_blend@pipe-a-alpha-basic}:
shard-glk: FAIL (fdo#108145) -> DMESG-WARN (fdo#106538,
fdo#105763)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
Re: [Intel-gfx] [PATCH 1/3] drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents
This seems really useful for the DSC PPS bitfields in i915_reg.h
since its a lot of bitfileds mapped from the spec to the macros for
for MASKS and SHIFTS for 128 bytes of PPS data.
This patch set only updates them in case of few registers.
All the other MASKS and SHIFTS clean up for all i915 registers
as a follow up right?
Manasi
On Wed, Oct 03, 2018 at 07:05:21PM +0300, Jani Nikula wrote:
> Introduce REG_BIT(n) to define register bits and REG_FIELD_MASK(h, l) to
> define register field masks.
>
> We define the above as wrappers to BIT() and GENMASK() respectively to
> force u32 type to go with our register size. Additionally, the specified
> type will be helpful with follow-up to define and use register field
> values through bitfield operations, and the macro wrapper naming is
> aligned as well.
>
> The intention is that these are easier to get right and review against
> the spec than hand rolled masks.
>
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Michal Wajdeczko
> Cc: Mika Kuoppala
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 68
> +++--
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 2 files changed, 40 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a71c507cfb9b..ac9258769435 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,6 +25,8 @@
> #ifndef _I915_REG_H_
> #define _I915_REG_H_
>
> +#include
> +
> /**
> * DOC: The i915 register macro definition style guide
> *
> @@ -59,15 +61,13 @@
> * significant to least significant bit. Indent the register content macros
> * using two extra spaces between ``#define`` and the macro name.
> *
> - * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit
> field
> - * contents so that they are already shifted in place, and can be directly
> - * OR'd. For convenience, function-like macros may be used to define bit
> fields,
> - * but do note that the macros may be needed to read as well as write the
> - * register contents.
> + * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Use
> + * ``REG_FIELD_MASK()`` to define _MASK. Define bit field contents so that
> they
> + * are already shifted in place, and can be directly OR'd. For convenience,
> + * function-like macros may be used to define bit fields, but do note that
> the
> + * macros may be needed to read as well as write the register contents.
> *
> - * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this
> in
> - * the future, but this is the prevailing style. Do **not** add ``_BIT``
> suffix
> - * to the name.
> + * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the
> name.
> *
> * Group the register and its contents together without blank lines, separate
> * from other registers and their contents with one blank line.
> @@ -105,8 +105,8 @@
> * #define _FOO_A 0xf000
> * #define _FOO_B 0xf001
> * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
> - * #define FOO_ENABLE(1 << 31)
> - * #define FOO_MODE_MASK (0xf << 16)
> + * #define FOO_ENABLEREG_BIT(31)
> + * #define FOO_MODE_MASK REG_FIELD_MASK(19, 16)
> * #define FOO_MODE_SHIFT16
> * #define FOO_MODE_BAR (0 << 16)
> * #define FOO_MODE_BAZ (1 << 16)
> @@ -116,6 +116,17 @@
> * #define GEN8_BAR_MMIO(0xb888)
> */
>
> +/*
> + * Macro for defining register bits. Local wrapper for BIT() to force u32.
> + */
> +#define REG_BIT(n) ((u32)BIT(n))
> +
> +/*
> + * Macro for defining register field masks. Local wrapper for GENMASK() to
> force
> + * u32.
> + */
> +#define REG_FIELD_MASK(h, l) ((u32)GENMASK(h, l))
> +
> typedef struct {
> uint32_t reg;
> } i915_reg_t;
> @@ -4612,7 +4623,7 @@ enum {
>
> #define _PP_STATUS 0x61200
> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
> -#define PP_ON (1 << 31)
> +#define PP_ON REG_BIT(31)
> /*
> * Indicates that all dependencies of the panel are on:
> *
> @@ -4620,14 +4631,14 @@ enum {
> * - pipe enabled
> * - LVDS/DVOB/DVOC on
> */
> -#define PP_READY (1 << 30)
> +#define PP_READY REG_BIT(30)
> +#define PP_SEQUENCE_MASK REG_FIELD_MASK(29, 28)
> #define PP_SEQUENCE_NONE (0 << 28)
> #define PP_SEQUENCE_POWER_UP (1 << 28)
> #define PP_SEQUENCE_POWER_DOWN (2 << 28)
> -#define PP_SEQUENCE_MASK (3 << 28)
> #define PP_SEQUENCE_SHIFT 28
> -#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
> -#define PP_SEQUENCE_STATE_MASK 0x000f
> +#define PP_CYCLE_DELAY_ACTIVE
[Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v2)
On some platforms, slowly unplugging (wiggling) the HDMI cable makes
the kernel to believe the HDMI display still connected. This is because
the HDMI DDC lines are disconnected sometimes later after the hot-plug
interrupt triggered. Use the hot plug live states to honor HDMI hot plug
status in addtion to access the DDC channels.
v2: Fix the formatting issue
Cc: Jani Nikula
Cc: Chris Chiu
Signed-off-by: Guang Bai
---
drivers/gpu/drm/i915/intel_hotplug.c | 32 +---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
b/drivers/gpu/drm/i915/intel_hotplug.c
index 648a13c..98ab1ab 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -246,17 +246,43 @@ static void intel_hpd_irq_storm_reenable_work(struct
work_struct *work)
intel_runtime_pm_put(dev_priv);
}
+#define MAX_SHORT_PULSE_MS 100
+#define PORT_CHECK_LOOP_COUNT 3
+
bool intel_encoder_hotplug(struct intel_encoder *encoder,
struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
- enum drm_connector_status old_status;
+ enum drm_connector_status old_status, new_status;
+ enum hpd_pin pin = encoder->hpd_pin;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 count = 0;
WARN_ON(!mutex_is_locked(>mode_config.mutex));
old_status = connector->base.status;
- connector->base.status =
- drm_helper_probe_detect(>base, NULL, false);
+ /*
+* Set HDMI connection status based on hot-plug live states and
+* display probe results.
+*/
+ if ((encoder->type == INTEL_OUTPUT_HDMI ||
+encoder->type == INTEL_OUTPUT_DDI) &&
+ dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
+ do {
+ new_status = connector_status_disconnected;
+ msleep(MAX_SHORT_PULSE_MS);
+
+ if (intel_digital_port_connected(encoder))
+ new_status =
drm_helper_probe_detect(>base,
+NULL,
false);
+ if (new_status == connector_status_connected)
+ break;
+ } while (++count <= PORT_CHECK_LOOP_COUNT);
+ connector->base.status = new_status;
+ } else {
+ connector->base.status =
+ drm_helper_probe_detect(>base, NULL, false);
+ }
if (old_status == connector->base.status)
return false;
--
2.7.4
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: create function to identify combophy port
On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
>
> Signed-off-by: Mahesh Kumar
> Cc: Madhav Chauhan
> Cc: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 15 ---
> drivers/gpu/drm/i915/intel_display.c | 11 +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> *dev_priv, enum port por
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port,
> INTEL_OUTPUT_HDMI, _entries);
> else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder
> *encoder,
> uint32_t pll_id;
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> - if (port == PORT_A || port == PORT_B) {
> + if (intel_port_is_combophy(dev_priv, port)) {
> if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
> link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder
> *encoder)
> int n_entries;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> _entries);
> else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> u32 level,
> enum intel_output_type type)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
>
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> else
> icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>
> - if (port == PORT_A || port == PORT_B) {
> + if (intel_port_is_combophy(dev_priv, port)) {
> val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder
> *encoder,
> mutex_lock(_priv->dpll_lock);
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port >= PORT_C)
> + if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port),
> icl_pll_to_ddi_pll_sel(encoder, pll));
> } else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder
> *encoder)
> enum port port = encoder->port;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port >= PORT_C)
> + if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> } else if (IS_CANNONLAKE(dev_priv)) {
> I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
> *dev_priv, enum port port)
> return port - PORT_C;
> }
>
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port
> port)
> +{
> + if (port == PORT_NONE)
> + return false;
> +
> + if (IS_ICELAKE(dev_priv))
> + return (port <= PORT_B);
please remove parenthesis
> +
> + return false;
> +}
> +
> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
> {
> switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> ---
Re: [Intel-gfx] [PATCH 2/8] drm/i915/icl: use combophy/TC helper functions during display detection
On Wed, Oct 03, 2018 at 12:51:57PM +0530, Mahesh Kumar wrote:
> Instead of directly comparing HPD pins use intel_port_is_combophy/tc
> helper functions to distinguish between combophy/TC ports.
>
> Signed-off-by: Mahesh Kumar
> Cc: Manasi Navare
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 15 +--
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 15a981ef5966..f6b9be81ea18 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4965,19 +4965,14 @@ static bool icl_digital_port_connected(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(>base);
>
> - switch (encoder->hpd_pin) {
> - case HPD_PORT_A:
> - case HPD_PORT_B:
> + if (intel_port_is_combophy(dev_priv, encoder->port))
> return icl_combo_port_connected(dev_priv, dig_port);
> - case HPD_PORT_C:
> - case HPD_PORT_D:
> - case HPD_PORT_E:
> - case HPD_PORT_F:
> + else if (intel_port_is_tc(dev_priv, encoder->port))
> return icl_tc_port_connected(dev_priv, dig_port);
> - default:
> + else
> MISSING_CASE(encoder->hpd_pin);
> - return false;
> - }
> +
> + return false;
> }
>
> /*
> --
> 2.16.2
>
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: create function to identify combophy port
On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
>
> Signed-off-by: Mahesh Kumar
> Cc: Madhav Chauhan
> Cc: Manasi Navare
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 15 ---
> drivers/gpu/drm/i915/intel_display.c | 11 +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> *dev_priv, enum port por
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port,
> INTEL_OUTPUT_HDMI, _entries);
> else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder
> *encoder,
> uint32_t pll_id;
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> - if (port == PORT_A || port == PORT_B) {
> + if (intel_port_is_combophy(dev_priv, port)) {
> if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
> link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder
> *encoder)
> int n_entries;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> _entries);
> else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> u32 level,
> enum intel_output_type type)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
>
> - if (port == PORT_A || port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port))
> icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> else
> icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>
> - if (port == PORT_A || port == PORT_B) {
> + if (intel_port_is_combophy(dev_priv, port)) {
> val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder
> *encoder,
> mutex_lock(_priv->dpll_lock);
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port >= PORT_C)
> + if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port),
> icl_pll_to_ddi_pll_sel(encoder, pll));
> } else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder
> *encoder)
> enum port port = encoder->port;
>
> if (IS_ICELAKE(dev_priv)) {
> - if (port >= PORT_C)
> + if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> } else if (IS_CANNONLAKE(dev_priv)) {
> I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
> *dev_priv, enum port port)
> return port - PORT_C;
> }
>
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port
> port)
> +{
> + if (port == PORT_NONE)
> + return false;
> +
> + if (IS_ICELAKE(dev_priv))
> + return (port <= PORT_B);
> +
> + return false;
> +}
> +
> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
> {
> switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> ---
Re: [Intel-gfx] [PATCH 4/8] drm/i915/icl: Use helper functions to classify the ports
On Wed, Oct 03, 2018 at 12:51:59PM +0530, Mahesh Kumar wrote:
> From: Vandita Kulkarni
>
> Use intel_port_is_tc and intel_port_is_combophy
> functions to replace the individual port checks
> from port C to F and port A to B respectively.
>
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: Mahesh Kumar
> Cc: Lucas De Marchi
> Cc: Madhav Chauhan
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_display.c | 15 ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 --
> 2 files changed, 8 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 16d9a20a420a..e31d71526afd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9296,24 +9296,17 @@ static void icelake_get_ddi_pll(struct
> drm_i915_private *dev_priv,
> u32 temp;
>
> /* TODO: TBT pll not implemented. */
> - switch (port) {
> - case PORT_A:
> - case PORT_B:
> + if (intel_port_is_combophy(dev_priv, port)) {
> temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
>
> if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
> return;
> - break;
> - case PORT_C:
> - case PORT_D:
> - case PORT_E:
> - case PORT_F:
> + } else if (intel_port_is_tc(dev_priv, port)) {
> id = icl_port_to_mg_pll_id(port);
> - break;
> - default:
> - MISSING_CASE(port);
> + } else {
> + WARN(1, "Invalid port %x\n", port);
> return;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 510ea90f6f5b..5b2ee49aee14 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2874,6 +2874,7 @@ static struct intel_shared_dpll *
> icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>struct intel_encoder *encoder)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *intel_dig_port =
> enc_to_dig_port(>base);
> struct intel_shared_dpll *pll;
> @@ -2883,18 +2884,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> int clock = crtc_state->port_clock;
> bool ret;
>
> - switch (port) {
> - case PORT_A:
> - case PORT_B:
> + if (intel_port_is_combophy(dev_priv, port)) {
> min = DPLL_ID_ICL_DPLL0;
> max = DPLL_ID_ICL_DPLL1;
> ret = icl_calc_dpll_state(crtc_state, encoder, clock,
> _state);
> - break;
> - case PORT_C:
> - case PORT_D:
> - case PORT_E:
> - case PORT_F:
> + } else if (intel_port_is_tc(dev_priv, port)) {
> if (intel_dig_port->tc_type == TC_PORT_TBT) {
> min = DPLL_ID_ICL_TBTPLL;
> max = min;
> @@ -2906,8 +2901,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
> _state);
> }
> - break;
> - default:
> + } else {
> MISSING_CASE(port);
> return NULL;
> }
> --
> 2.16.2
>
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Re: [Intel-gfx] [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc
On Wed, Oct 03, 2018 at 02:31:08PM +0300, Juha-Pekka Heikkila wrote:
> Hi Alex,
>
> For my patches there seems limited interest to get them merged before IGT
> support these modes..I'm not holding my breath for this.
I'm interested if that counts.
I asked the same question on the DRM_FORMAT_XYUV thread, do we need to
wait for userspace to get new fourcc merged.
>
> https://lists.freedesktop.org/archives/intel-gfx/2018-September/174877.html
>
> /Juha-Pekka
>
> On 02.10.2018 18:00, Alexandru-Cosmin Gheorghe wrote:
> >Hi,
> >
> >How is this going on, anything holding it back from getting merged ?
> >I'm interested in adding/using P010, [1]
> >
> >Thank you,
> >Alex Gheorghe
> >
> >[1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186963.html
> >
> >On Thu, Aug 30, 2018 at 03:41:11PM +0300, Juha-Pekka Heikkila wrote:
> >>Add P010 definition, semi-planar yuv format where each component
> >>is 16 bits 10 msb containing color value. First come Y plane [10:6]
> >>followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
> >>
> >>Add P012 definition, semi-planar yuv format where each component
> >>is 16 bits 12 msb containing color value. First come Y plane [12:4]
> >>followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
> >>
> >>Add P016 definition, semi-planar yuv format where each component
> >>is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
> >>plane [16:16]
> >>
> >>Signed-off-by: Juha-Pekka Heikkila
> >>---
> >> drivers/gpu/drm/drm_fourcc.c | 3 +++
> >> include/uapi/drm/drm_fourcc.h | 10 ++
> >> 2 files changed, 13 insertions(+)
> >>
> >>diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> >>index 35c1e27..32e07a2 100644
> >>--- a/drivers/gpu/drm/drm_fourcc.c
> >>+++ b/drivers/gpu/drm/drm_fourcc.c
> >>@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32
> >>format)
> >>{ .format = DRM_FORMAT_UYVY,.depth = 0,
> >> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_VYUY,.depth = 0,
> >> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_AYUV,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
> >> true, .is_yuv = true },
> >>+ { .format = DRM_FORMAT_P010,.depth = 0,
> >>.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true
> >>},
> >>+ { .format = DRM_FORMAT_P012,.depth = 0,
> >>.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true
> >>},
> >>+ { .format = DRM_FORMAT_P016,.depth = 0,
> >>.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true
> >>},
> >>};
> >>unsigned int i;
> >>diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> >>index 2ed46e9..daaabb1 100644
> >>--- a/include/uapi/drm/drm_fourcc.h
> >>+++ b/include/uapi/drm/drm_fourcc.h
> >>@@ -178,6 +178,16 @@ extern "C" {
> >> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /*
> >> non-subsampled Cb:Cr plane */
> >> /*
> >>+ * 2 plane YCbCr
> >>+ * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
> >>+ * component xxx msb Y [xxx:16-xxx]
> >>+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian
> >>[xxx:16-xxx:xxx:16-xxx]
> >>+ */
> >>+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2
> >>subsampled Cr:Cb plane, 10 bit per channel */
> >>+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2
> >>subsampled Cr:Cb plane, 12 bit per channel */
> >>+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2
> >>subsampled Cr:Cb plane, 16 bit per channel */
> >>+
> >>+/*
> >> * 3 plane YCbCr
> >> * index 0: Y plane, [7:0] Y
> >> * index 1: Cb plane, [7:0] Cb
> >>--
> >>2.7.4
> >>
> >>___
> >>dri-devel mailing list
> >>dri-de...@lists.freedesktop.org
> >>https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >
--
Cheers,
Alex G
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents
On Wed, Oct 03, 2018 at 07:05:21PM +0300, Jani Nikula wrote:
> Introduce REG_BIT(n) to define register bits and REG_FIELD_MASK(h, l) to
> define register field masks.
>
> We define the above as wrappers to BIT() and GENMASK() respectively to
> force u32 type to go with our register size. Additionally, the specified
> type will be helpful with follow-up to define and use register field
> values through bitfield operations, and the macro wrapper naming is
> aligned as well.
>
> The intention is that these are easier to get right and review against
> the spec than hand rolled masks.
My first impression was that reg rage as mask would get harder to code and
review, but it is just because I'm used to the current style
But when thinking the real case of looking to the spec and writing the code
and/or reviewing it, the range makes indeed clear.
>
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Michal Wajdeczko
> Cc: Mika Kuoppala
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 68
> +++--
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 2 files changed, 40 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a71c507cfb9b..ac9258769435 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,6 +25,8 @@
> #ifndef _I915_REG_H_
> #define _I915_REG_H_
>
> +#include
> +
> /**
> * DOC: The i915 register macro definition style guide
> *
> @@ -59,15 +61,13 @@
> * significant to least significant bit. Indent the register content macros
> * using two extra spaces between ``#define`` and the macro name.
> *
> - * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit
> field
> - * contents so that they are already shifted in place, and can be directly
> - * OR'd. For convenience, function-like macros may be used to define bit
> fields,
> - * but do note that the macros may be needed to read as well as write the
> - * register contents.
> + * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Use
> + * ``REG_FIELD_MASK()`` to define _MASK. Define bit field contents so that
> they
> + * are already shifted in place, and can be directly OR'd. For convenience,
> + * function-like macros may be used to define bit fields, but do note that
> the
> + * macros may be needed to read as well as write the register contents.
can we add a note that this is all inclusive bits on the range?
> *
> - * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this
> in
> - * the future, but this is the prevailing style. Do **not** add ``_BIT``
> suffix
> - * to the name.
> + * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the
> name.
> *
> * Group the register and its contents together without blank lines, separate
> * from other registers and their contents with one blank line.
> @@ -105,8 +105,8 @@
> * #define _FOO_A 0xf000
> * #define _FOO_B 0xf001
> * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
> - * #define FOO_ENABLE(1 << 31)
> - * #define FOO_MODE_MASK (0xf << 16)
> + * #define FOO_ENABLEREG_BIT(31)
> + * #define FOO_MODE_MASK REG_FIELD_MASK(19, 16)
> * #define FOO_MODE_SHIFT16
> * #define FOO_MODE_BAR (0 << 16)
> * #define FOO_MODE_BAZ (1 << 16)
> @@ -116,6 +116,17 @@
> * #define GEN8_BAR_MMIO(0xb888)
> */
>
> +/*
> + * Macro for defining register bits. Local wrapper for BIT() to force u32.
> + */
> +#define REG_BIT(n) ((u32)BIT(n))
> +
> +/*
> + * Macro for defining register field masks. Local wrapper for GENMASK() to
> force
> + * u32.
> + */
> +#define REG_FIELD_MASK(h, l) ((u32)GENMASK(h, l))
> +
> typedef struct {
> uint32_t reg;
> } i915_reg_t;
> @@ -4612,7 +4623,7 @@ enum {
>
> #define _PP_STATUS 0x61200
> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
> -#define PP_ON (1 << 31)
> +#define PP_ON REG_BIT(31)
> /*
> * Indicates that all dependencies of the panel are on:
> *
> @@ -4620,14 +4631,14 @@ enum {
> * - pipe enabled
> * - LVDS/DVOB/DVOC on
> */
> -#define PP_READY (1 << 30)
> +#define PP_READY REG_BIT(30)
> +#define PP_SEQUENCE_MASK REG_FIELD_MASK(29, 28)
> #define PP_SEQUENCE_NONE (0 << 28)
> #define PP_SEQUENCE_POWER_UP (1 << 28)
> #define PP_SEQUENCE_POWER_DOWN (2 << 28)
> -#define PP_SEQUENCE_MASK (3 << 28)
> #define PP_SEQUENCE_SHIFT 28
> -#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
> -#define PP_SEQUENCE_STATE_MASK 0x000f
> +#define PP_CYCLE_DELAY_ACTIVE
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: introduce macros to define register contents
== Series Details == Series: drm/i915: introduce macros to define register contents URL : https://patchwork.freedesktop.org/series/50513/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4922 -> Patchwork_10346 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50513/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10346 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107774, fdo#107859, fdo#107556) fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@gem_exec_suspend@basic-s4-devices: fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773) igt@gem_wait@basic-wait-all: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) Possible fixes igt@gem_exec_suspend@basic-s3: fi-bdw-samus: INCOMPLETE (fdo#107773) -> PASS igt@gem_tiled_fence_blits@basic: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 == Participating hosts (48 -> 44) == Additional (3): fi-kbl-soraka fi-skl-guc fi-snb-2520m Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_4922 -> Patchwork_10346 CI_DRM_4922: 97b376a5213463a70eb977282f5486ded096648f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10346: e48993ff28501495fe5483d19cbe53be5722a8a7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e48993ff2850 drm/i915: introduce REG_FIELD() to define register field values 9d10556d888e drm/i915: deprecate _SHIFT in favor of FIELD_GET() and _MASK fa2aca822675 drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10346/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Restore vblank interrupts earlier (rev4)
== Series Details == Series: series starting with [v2,1/3] drm/i915: Restore vblank interrupts earlier (rev4) URL : https://patchwork.freedesktop.org/series/50393/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4922 -> Patchwork_10345 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50393/revisions/4/mbox/ == Known issues == Here are the changes found in Patchwork_10345 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774, fdo#107859) igt@kms_addfb_basic@unused-pitches: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-cfl-8109u: PASS -> INCOMPLETE (fdo#108126, fdo#106070) igt@pm_rpm@module-reload: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) Possible fixes igt@gem_tiled_fence_blits@basic: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126 == Participating hosts (48 -> 43) == Additional (2): fi-kbl-soraka fi-snb-2520m Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u == Build changes == * Linux: CI_DRM_4922 -> Patchwork_10345 CI_DRM_4922: 97b376a5213463a70eb977282f5486ded096648f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10345: b1aa286906d2a13955c417342a2df5db4943a39a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b1aa286906d2 drm/i915: Clean up early plane debugs d5a5d74e82b0 drm/i915: Use the correct crtc when sanitizing plane mapping c6a938a3e0a7 drm/i915: Restore vblank interrupts earlier == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10345/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: introduce macros to define register contents
== Series Details == Series: drm/i915: introduce macros to define register contents URL : https://patchwork.freedesktop.org/series/50513/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents Okay! Commit: drm/i915: deprecate _SHIFT in favor of FIELD_GET() and _MASK Okay! Commit: drm/i915: introduce REG_FIELD() to define register field values +drivers/gpu/drm/i915/intel_display.c:1219:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/intel_display.c:1228:22: error: Expected constant expression in case statement ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: introduce macros to define register contents
== Series Details == Series: drm/i915: introduce macros to define register contents URL : https://patchwork.freedesktop.org/series/50513/ State : warning == Summary == $ dim checkpatch origin/drm-tip fa2aca822675 drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents 9d10556d888e drm/i915: deprecate _SHIFT in favor of FIELD_GET() and _MASK e48993ff2850 drm/i915: introduce REG_FIELD() to define register field values -:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_mask' - possible side-effects? #60: FILE: drivers/gpu/drm/i915/i915_reg.h:135: +#define REG_FIELD(_mask, _val) \ + (((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)) total: 0 errors, 0 warnings, 1 checks, 94 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: Clean up early plane debugs
On Wed, Oct 03, 2018 at 05:50:52PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Print the plane hw state readout results in the common format
> we already use for pipes and encoders. Also print some clearer
> debug messages when we disable planes during the early phases
> of state readout/sanitization.
>
> v2: Rebase
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 16 ++--
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index f0d004641b0d..24fe3b1fb2a9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2768,10 +2768,6 @@ intel_set_plane_visible(struct intel_crtc_state
> *crtc_state,
> crtc_state->base.plane_mask |= drm_plane_mask(>base);
> else
> crtc_state->base.plane_mask &= ~drm_plane_mask(>base);
> -
> - DRM_DEBUG_KMS("%s active planes 0x%x\n",
> - crtc_state->base.crtc->name,
> - crtc_state->active_planes);
> }
>
> static void fixup_active_planes(struct intel_crtc_state *crtc_state)
> @@ -2799,6 +2795,10 @@ static void intel_plane_disable_noatomic(struct
> intel_crtc *crtc,
> struct intel_plane_state *plane_state =
> to_intel_plane_state(plane->base.state);
>
> + DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
> + plane->base.base.id, plane->base.name,
> + crtc->base.base.id, crtc->base.name);
> +
> intel_set_plane_visible(crtc_state, plane_state, false);
> fixup_active_planes(crtc_state);
>
> @@ -15523,8 +15523,8 @@ intel_sanitize_plane_mapping(struct drm_i915_private
> *dev_priv)
> if (pipe == crtc->pipe)
> continue;
>
> - DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling
> plane\n",
> - plane->base.name);
> + DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe,
> disabling plane\n",
> + plane->base.base.id, plane->base.name);
>
> plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> intel_plane_disable_noatomic(plane_crtc, plane);
> @@ -15713,6 +15713,10 @@ static void readout_plane_state(struct
> drm_i915_private *dev_priv)
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> intel_set_plane_visible(crtc_state, plane_state, visible);
> +
> + DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
> + plane->base.base.id, plane->base.name,
> + enableddisabled(visible), pipe_name(pipe));
> }
>
> for_each_intel_crtc(_priv->drm, crtc) {
> --
> 2.16.4
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Use the correct crtc when sanitizing plane mapping
On Wed, Oct 03, 2018 at 05:50:17PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> When we decide that a plane is attached to the wrong pipe we try
> to turn off said plane. However we are passing around the crtc we
> think that the plane is supposed to be using rather than the crtc
> it is currently using. That doesn't work all that well because
> we may have to do vblank waits etc. and the other pipe might
> not even be enabled here. So let's pass the plane's current crtc to
> intel_plane_disable_noatomic() so that it can its job correctly.
>
> To do that semi-cleanly we also have to change the plane readout
> to record the plane's visibility into the bitmasks of the crtc
> where the plane is currently enabled rather than to the crtc
> we want to use for the plane.
>
> One caveat here is that our active_planes bitmask will get confused
> if both planes are enabled on the same pipe. Fortunately we can use
> plane_mask to reconstruct active_planes sufficiently since
> plane_mask still has the same meaning (is the plane visible?)
> during readout. We also have to do the same during the initial
> plane readout as the second plane could clear the active_planes
> bit the first plane had already set.
>
> v2: Rely on fixup_active_planes() to populate active_planes fully (Daniel)
> Add Daniel's proposed comment to better document why we do this
> Drop the redundant intel_set_plane_visible() call
>
> Cc: sta...@vger.kernel.org # fcba862e8428 drm/i915: Have
> plane->get_hw_state() return the current pipe
> Cc: sta...@vger.kernel.org
> Cc: Dennis
> Cc: Daniel Vetter
> Tested-by: Dennis
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105637
> Fixes: b1e01595a66d ("drm/i915: Redo plane sanitation during readout")
> Signed-off-by: Ville Syrjälä
I have the illusion of understanding this stuff now.
Reviewed-by: Daniel Vetter
But let's see whether testers and CI agree :-)
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 78
> +---
> 1 file changed, 46 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d2828159f6c8..f0d004641b0d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2764,20 +2764,33 @@ intel_set_plane_visible(struct intel_crtc_state
> *crtc_state,
>
> plane_state->base.visible = visible;
>
> - /* FIXME pre-g4x don't work like this */
> - if (visible) {
> + if (visible)
> crtc_state->base.plane_mask |= drm_plane_mask(>base);
> - crtc_state->active_planes |= BIT(plane->id);
> - } else {
> + else
> crtc_state->base.plane_mask &= ~drm_plane_mask(>base);
> - crtc_state->active_planes &= ~BIT(plane->id);
> - }
>
> DRM_DEBUG_KMS("%s active planes 0x%x\n",
> crtc_state->base.crtc->name,
> crtc_state->active_planes);
> }
>
> +static void fixup_active_planes(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_plane *plane;
> +
> + /*
> + * Active_planes aliases if multiple "primary" or cursor planes
> + * have been used on the same (or wrong) pipe. plane_mask uses
> + * unique ids, hence we can use that to reconstruct active_planes.
> + */
> + crtc_state->active_planes = 0;
> +
> + drm_for_each_plane_mask(plane, _priv->drm,
> + crtc_state->base.plane_mask)
> + crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
> +}
> +
> static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>struct intel_plane *plane)
> {
> @@ -2787,6 +2800,7 @@ static void intel_plane_disable_noatomic(struct
> intel_crtc *crtc,
> to_intel_plane_state(plane->base.state);
>
> intel_set_plane_visible(crtc_state, plane_state, false);
> + fixup_active_planes(crtc_state);
>
> if (plane->id == PLANE_PRIMARY)
> intel_pre_disable_primary_noatomic(>base);
> @@ -2805,7 +2819,6 @@ intel_find_initial_plane_obj(struct intel_crtc
> *intel_crtc,
> struct drm_i915_gem_object *obj;
> struct drm_plane *primary = intel_crtc->base.primary;
> struct drm_plane_state *plane_state = primary->state;
> - struct drm_crtc_state *crtc_state = intel_crtc->base.state;
> struct intel_plane *intel_plane = to_intel_plane(primary);
> struct intel_plane_state *intel_state =
> to_intel_plane_state(plane_state);
> @@ -2900,10 +2913,6 @@ intel_find_initial_plane_obj(struct intel_crtc
> *intel_crtc,
> plane_state->fb = fb;
> plane_state->crtc = _crtc->base;
>
> - intel_set_plane_visible(to_intel_crtc_state(crtc_state),
> - to_intel_plane_state(plane_state),
> -
[Intel-gfx] [PATCH 3/3] drm/i915: introduce REG_FIELD() to define register field values
Slightly verbose, but does away with hand rolled shifts. Ties the field
values with the mask defining the field.
Unfortunately we don't get the build-time checks of FIELD_PREP() due to
it not evaluating to a constant expression.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: Mika Kuoppala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 58 +++--
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dce4a6ac394c..4dfb0f6f9e60 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -63,10 +63,10 @@
* using two extra spaces between ``#define`` and the macro name.
*
* Define bit fields using ``REG_FIELD_MASK(h, l)``. Define bit field contents
- * so that they are already shifted in place, and can be directly OR'd. For
- * convenience, function-like macros may be used to define bit fields, but do
- * note that the macros may be needed to read as well as write the register
- * contents.
+ * using ``REG_FIELD(mask, value)``. This will define the values already
shifted
+ * in place, so they can be directly OR'd together. For convenience,
+ * function-like macros may be used to define bit fields, but do note that the
+ * macros may be needed to read as well as write the register contents.
*
* Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the
name.
*
@@ -108,9 +108,9 @@
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
* #define FOO_ENABLEREG_BIT(31)
* #define FOO_MODE_MASK REG_FIELD_MASK(19, 16)
- * #define FOO_MODE_BAR (0 << 16)
- * #define FOO_MODE_BAZ (1 << 16)
- * #define FOO_MODE_QUX_SNB (2 << 16)
+ * #define FOO_MODE_BAR REG_FIELD(FOO_MODE_MASK, 0)
+ * #define FOO_MODE_BAZ REG_FIELD(FOO_MODE_MASK, 1)
+ * #define FOO_MODE_QUX_SNB REG_FIELD(FOO_MODE_MASK, 2)
*
* #define BAR _MMIO(0xb000)
* #define GEN8_BAR_MMIO(0xb888)
@@ -127,6 +127,14 @@
*/
#define REG_FIELD_MASK(h, l) ((u32)GENMASK(h, l))
+/*
+ * Macro for defining register field values. Local version of FIELD_PREP() to
+ * evaluate to an integer constant expression to allow use in e.g. case
+ * labels. Unfortunately this loses build-time checks on mask and value.
+ */
+#define REG_FIELD(_mask, _val) \
+ (((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask))
+
typedef struct {
uint32_t reg;
} i915_reg_t;
@@ -4633,25 +4641,25 @@ enum {
*/
#define PP_READY REG_BIT(30)
#define PP_SEQUENCE_MASK REG_FIELD_MASK(29, 28)
-#define PP_SEQUENCE_NONE (0 << 28)
-#define PP_SEQUENCE_POWER_UP (1 << 28)
-#define PP_SEQUENCE_POWER_DOWN (2 << 28)
+#define PP_SEQUENCE_NONE REG_FIELD(PP_SEQUENCE_MASK, 0)
+#define PP_SEQUENCE_POWER_UP REG_FIELD(PP_SEQUENCE_MASK, 1)
+#define PP_SEQUENCE_POWER_DOWN REG_FIELD(PP_SEQUENCE_MASK, 2)
#define PP_CYCLE_DELAY_ACTIVEREG_BIT(27)
#define PP_SEQUENCE_STATE_MASK REG_FIELD_MASK(3, 0)
-#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
-#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
-#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
-#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
-#define PP_SEQUENCE_STATE_ON_IDLE(0x8 << 0)
-#define PP_SEQUENCE_STATE_ON_S1_0(0x9 << 0)
-#define PP_SEQUENCE_STATE_ON_S1_2(0xa << 0)
-#define PP_SEQUENCE_STATE_ON_S1_3(0xb << 0)
-#define PP_SEQUENCE_STATE_RESET (0xf << 0)
+#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD(PP_SEQUENCE_STATE_MASK, 0x0)
+#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD(PP_SEQUENCE_STATE_MASK, 0x1)
+#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD(PP_SEQUENCE_STATE_MASK, 0x2)
+#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD(PP_SEQUENCE_STATE_MASK, 0x3)
+#define PP_SEQUENCE_STATE_ON_IDLEREG_FIELD(PP_SEQUENCE_STATE_MASK, 0x8)
+#define PP_SEQUENCE_STATE_ON_S1_0REG_FIELD(PP_SEQUENCE_STATE_MASK, 0x9)
+#define PP_SEQUENCE_STATE_ON_S1_2REG_FIELD(PP_SEQUENCE_STATE_MASK, 0xa)
+#define PP_SEQUENCE_STATE_ON_S1_3REG_FIELD(PP_SEQUENCE_STATE_MASK, 0xb)
+#define PP_SEQUENCE_STATE_RESET REG_FIELD(PP_SEQUENCE_STATE_MASK, 0xf)
#define _PP_CONTROL0x61204
#define PP_CONTROL(pps_idx)_MMIO_PPS(pps_idx, _PP_CONTROL)
#define PANEL_UNLOCK_MASK REG_FIELD_MASK(31, 16)
-#define PANEL_UNLOCK_REGS (0xabcd << 16)
+#define PANEL_UNLOCK_REGS REG_FIELD(PANEL_UNLOCK_MASK, 0xabcd)
#define BXT_POWER_CYCLE_DELAY_MASKREG_FIELD_MASK(8, 4)
#define EDP_FORCE_VDD REG_BIT(3)
#define EDP_BLC_ENABLEREG_BIT(2)
@@ -4661,11 +4669,11 @@ enum {
[Intel-gfx] [PATCH 1/3] drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents
Introduce REG_BIT(n) to define register bits and REG_FIELD_MASK(h, l) to
define register field masks.
We define the above as wrappers to BIT() and GENMASK() respectively to
force u32 type to go with our register size. Additionally, the specified
type will be helpful with follow-up to define and use register field
values through bitfield operations, and the macro wrapper naming is
aligned as well.
The intention is that these are easier to get right and review against
the spec than hand rolled masks.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: Mika Kuoppala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 68 +++--
drivers/gpu/drm/i915/intel_dp.c | 2 +-
2 files changed, 40 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507cfb9b..ac9258769435 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,8 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
+#include
+
/**
* DOC: The i915 register macro definition style guide
*
@@ -59,15 +61,13 @@
* significant to least significant bit. Indent the register content macros
* using two extra spaces between ``#define`` and the macro name.
*
- * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
- * contents so that they are already shifted in place, and can be directly
- * OR'd. For convenience, function-like macros may be used to define bit
fields,
- * but do note that the macros may be needed to read as well as write the
- * register contents.
+ * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Use
+ * ``REG_FIELD_MASK()`` to define _MASK. Define bit field contents so that they
+ * are already shifted in place, and can be directly OR'd. For convenience,
+ * function-like macros may be used to define bit fields, but do note that the
+ * macros may be needed to read as well as write the register contents.
*
- * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
- * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
- * to the name.
+ * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the
name.
*
* Group the register and its contents together without blank lines, separate
* from other registers and their contents with one blank line.
@@ -105,8 +105,8 @@
* #define _FOO_A 0xf000
* #define _FOO_B 0xf001
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
- * #define FOO_ENABLE(1 << 31)
- * #define FOO_MODE_MASK (0xf << 16)
+ * #define FOO_ENABLEREG_BIT(31)
+ * #define FOO_MODE_MASK REG_FIELD_MASK(19, 16)
* #define FOO_MODE_SHIFT16
* #define FOO_MODE_BAR (0 << 16)
* #define FOO_MODE_BAZ (1 << 16)
@@ -116,6 +116,17 @@
* #define GEN8_BAR_MMIO(0xb888)
*/
+/*
+ * Macro for defining register bits. Local wrapper for BIT() to force u32.
+ */
+#define REG_BIT(n) ((u32)BIT(n))
+
+/*
+ * Macro for defining register field masks. Local wrapper for GENMASK() to
force
+ * u32.
+ */
+#define REG_FIELD_MASK(h, l) ((u32)GENMASK(h, l))
+
typedef struct {
uint32_t reg;
} i915_reg_t;
@@ -4612,7 +4623,7 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
-#define PP_ON(1 << 31)
+#define PP_ONREG_BIT(31)
/*
* Indicates that all dependencies of the panel are on:
*
@@ -4620,14 +4631,14 @@ enum {
* - pipe enabled
* - LVDS/DVOB/DVOC on
*/
-#define PP_READY (1 << 30)
+#define PP_READY REG_BIT(30)
+#define PP_SEQUENCE_MASK REG_FIELD_MASK(29, 28)
#define PP_SEQUENCE_NONE (0 << 28)
#define PP_SEQUENCE_POWER_UP (1 << 28)
#define PP_SEQUENCE_POWER_DOWN (2 << 28)
-#define PP_SEQUENCE_MASK (3 << 28)
#define PP_SEQUENCE_SHIFT28
-#define PP_CYCLE_DELAY_ACTIVE(1 << 27)
-#define PP_SEQUENCE_STATE_MASK 0x000f
+#define PP_CYCLE_DELAY_ACTIVEREG_BIT(27)
+#define PP_SEQUENCE_STATE_MASK REG_FIELD_MASK(3, 0)
#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
@@ -4640,42 +4651,41 @@ enum {
#define _PP_CONTROL0x61204
#define PP_CONTROL(pps_idx)_MMIO_PPS(pps_idx, _PP_CONTROL)
+#define PANEL_UNLOCK_MASK REG_FIELD_MASK(31, 16)
#define PANEL_UNLOCK_REGS (0xabcd << 16)
-#define PANEL_UNLOCK_MASK (0x << 16)
-#define BXT_POWER_CYCLE_DELAY_MASK0x1f0
+#define
[Intel-gfx] [PATCH 2/3] drm/i915: deprecate _SHIFT in favor of FIELD_GET() and _MASK
bitfield.h defines FIELD_GET() and FIELD_PREP() macros to access
bitfields using the mask alone, with no need for separate shift. Indeed,
the shift is redundant.
For the most part, FIELD_GET() is shorter than masking followed by
shift, and arguably has more clarity.
FIELD_PREP() can get more verbose than simply shifting in place, but it
does provide masking to ensure we don't overflow the mask, something we
usually don't bother with currently.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: Mika Kuoppala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 21 ++--
drivers/gpu/drm/i915/intel_dp.c | 40 ---
drivers/gpu/drm/i915/intel_lvds.c | 40 ++-
3 files changed, 40 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac9258769435..dce4a6ac394c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
+#include
#include
/**
@@ -61,11 +62,11 @@
* significant to least significant bit. Indent the register content macros
* using two extra spaces between ``#define`` and the macro name.
*
- * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Use
- * ``REG_FIELD_MASK()`` to define _MASK. Define bit field contents so that they
- * are already shifted in place, and can be directly OR'd. For convenience,
- * function-like macros may be used to define bit fields, but do note that the
- * macros may be needed to read as well as write the register contents.
+ * Define bit fields using ``REG_FIELD_MASK(h, l)``. Define bit field contents
+ * so that they are already shifted in place, and can be directly OR'd. For
+ * convenience, function-like macros may be used to define bit fields, but do
+ * note that the macros may be needed to read as well as write the register
+ * contents.
*
* Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the
name.
*
@@ -107,7 +108,6 @@
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
* #define FOO_ENABLEREG_BIT(31)
* #define FOO_MODE_MASK REG_FIELD_MASK(19, 16)
- * #define FOO_MODE_SHIFT16
* #define FOO_MODE_BAR (0 << 16)
* #define FOO_MODE_BAZ (1 << 16)
* #define FOO_MODE_QUX_SNB (2 << 16)
@@ -4636,7 +4636,6 @@ enum {
#define PP_SEQUENCE_NONE (0 << 28)
#define PP_SEQUENCE_POWER_UP (1 << 28)
#define PP_SEQUENCE_POWER_DOWN (2 << 28)
-#define PP_SEQUENCE_SHIFT28
#define PP_CYCLE_DELAY_ACTIVEREG_BIT(27)
#define PP_SEQUENCE_STATE_MASK REG_FIELD_MASK(3, 0)
#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
@@ -4654,7 +4653,6 @@ enum {
#define PANEL_UNLOCK_MASK REG_FIELD_MASK(31, 16)
#define PANEL_UNLOCK_REGS (0xabcd << 16)
#define BXT_POWER_CYCLE_DELAY_MASKREG_FIELD_MASK(8, 4)
-#define BXT_POWER_CYCLE_DELAY_SHIFT 4
#define EDP_FORCE_VDD REG_BIT(3)
#define EDP_BLC_ENABLEREG_BIT(2)
#define PANEL_POWER_RESET REG_BIT(1)
@@ -4662,7 +4660,6 @@ enum {
#define _PP_ON_DELAYS 0x61208
#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
-#define PANEL_PORT_SELECT_SHIFT 30
#define PANEL_PORT_SELECT_MASKREG_FIELD_MASK(31, 30)
#define PANEL_PORT_SELECT_LVDS(0 << 30)
#define PANEL_PORT_SELECT_DPA (1 << 30)
@@ -4670,23 +4667,17 @@ enum {
#define PANEL_PORT_SELECT_DPD (3 << 30)
#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
#define PANEL_POWER_UP_DELAY_MASK REG_FIELD_MASK(28, 16)
-#define PANEL_POWER_UP_DELAY_SHIFT16
#define PANEL_LIGHT_ON_DELAY_MASK REG_FIELD_MASK(12, 0)
-#define PANEL_LIGHT_ON_DELAY_SHIFT0
#define _PP_OFF_DELAYS 0x6120C
#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
#define PANEL_POWER_DOWN_DELAY_MASK REG_FIELD_MASK(28, 16)
-#define PANEL_POWER_DOWN_DELAY_SHIFT 16
#define PANEL_LIGHT_OFF_DELAY_MASKREG_FIELD_MASK(12, 0)
-#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
#define _PP_DIVISOR0x61210
#define PP_DIVISOR(pps_idx)_MMIO_PPS(pps_idx, _PP_DIVISOR)
#define PP_REFERENCE_DIVIDER_MASK REG_FIELD_MASK(31, 8)
-#define PP_REFERENCE_DIVIDER_SHIFT8
#define PANEL_POWER_CYCLE_DELAY_MASK REG_FIELD_MASK(4, 0)
-#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
/* Panel fitting */
#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 31eef9b0e33b..848ce42d7770 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5767,25
[Intel-gfx] [PATCH 0/3] drm/i915: introduce macros to define register contents
Actual serious v1 after the RFC [1]. The major change is to add local wrappers or versions of the BIT(), GENMASK(), and FIELD_PREP() macros for i915_reg.h to ensure u32 type and integer constant expressions. It's a bit of a meh but does provide an opportunity for unified local naming of the macros. After some back and forth, REG_BIT(), REG_FIELD_MASK() and REG_FIELD() are what I settled on, but I guess I expect some bikeshedding... The big loss is the build-time checking of the defined field values; FIELD_PREP() does it in a way that prohibits macro use in e.g. case labels. bloat-o-meter indicates slight increase, unsurprising due to the added masking to avoid the values overflowing their fields. The changed sample is too small to make any big conclusions though. add/remove: 0/0 grow/shrink: 3/0 up/down: 81/0 (81) Function old new delta intel_dp_init_panel_power_sequencer_registers 863 912 +49 intel_pre_enable_lvds618 646 +28 intel_pps_readout_hw_state 385 389 +4 Total: Before=1106128, After=1106209, chg +0.01% BR, Jani. [1] https://patchwork.freedesktop.org/series/50267/ Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michal Wajdeczko Cc: Mika Kuoppala Jani Nikula (3): drm/i915: introduce REG_BIT() and REG_FIELD_MASK() to define register contents drm/i915: deprecate _SHIFT in favor of FIELD_GET() and _MASK drm/i915: introduce REG_FIELD() to define register field values drivers/gpu/drm/i915/i915_reg.h | 129 -- drivers/gpu/drm/i915/intel_dp.c | 42 + drivers/gpu/drm/i915/intel_lvds.c | 40 ++-- 3 files changed, 104 insertions(+), 107 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915: Restore vblank interrupts earlier (rev4)
== Series Details == Series: series starting with [v2,1/3] drm/i915: Restore vblank interrupts earlier (rev4) URL : https://patchwork.freedesktop.org/series/50393/ State : warning == Summary == $ dim checkpatch origin/drm-tip c6a938a3e0a7 drm/i915: Restore vblank interrupts earlier d5a5d74e82b0 drm/i915: Use the correct crtc when sanitizing plane mapping -:34: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #34: Cc: sta...@vger.kernel.org # fcba862e8428 drm/i915: Have plane->get_hw_state() return the current pipe total: 0 errors, 1 warnings, 0 checks, 155 lines checked b1aa286906d2 drm/i915: Clean up early plane debugs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915/guc: init GuC descriptors after GuC load
Quoting Daniele Ceraolo Spurio (2018-10-03 01:12:57) > > > On 02/10/18 15:39, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [v2,1/3] drm/i915/guc: init GuC descriptors > > after GuC load > > URL : https://patchwork.freedesktop.org/series/50464/ > > State : failure > > > > == Summary == > > > > = CI Bug Log - changes from CI_DRM_4915 -> Patchwork_10331 = > > > > == Summary - FAILURE == > > > >Serious unknown changes coming with Patchwork_10331 absolutely need to be > >verified manually. > > > >If you think the reported changes have nothing to do with the changes > >introduced in Patchwork_10331, please notify your bug team to allow them > >to document this new failure mode, which will reduce false positives in > > CI. > > > >External URL: > > https://patchwork.freedesktop.org/api/1.0/series/50464/revisions/1/mbox/ > > > > == Possible new issues == > > > >Here are the unknown changes that may have been introduced in > > Patchwork_10331: > > > >=== IGT changes === > > > > Possible regressions > > > > igt@drv_selftest@live_gem: > >fi-whl-u: PASS -> INCOMPLETE > >fi-skl-6600u: PASS -> INCOMPLETE > >fi-kbl-7560u: PASS -> INCOMPLETE > >fi-cfl-s3: PASS -> INCOMPLETE > >fi-skl-iommu: PASS -> INCOMPLETE > >fi-skl-6700k2: PASS -> INCOMPLETE > >fi-skl-6700hq: PASS -> INCOMPLETE > >fi-cfl-8109u: PASS -> INCOMPLETE > >fi-kbl-7500u: PASS -> INCOMPLETE > >fi-cfl-8700k: PASS -> INCOMPLETE > >fi-skl-6770hq: PASS -> INCOMPLETE > >fi-kbl-7567u: PASS -> INCOMPLETE > >fi-kbl-x1275: PASS -> INCOMPLETE > >fi-kbl-8809g: PASS -> INCOMPLETE > >fi-kbl-r: PASS -> INCOMPLETE > > > > Those failures are there even without my patches (see > https://patchwork.freedesktop.org/series/40112/). Is there an existing > bugzilla? In the meantime, I'll have a look to see if I can find what's > causing this. inject_preempt_context() fails when talking to the guc, catastrophe ensues. As shown above it's quite reliable after a fake suspend/resume, but it also happens during normal preemption (the preemption smoketest was added to exercise this issue). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/guc: init GuC descriptors after GuC load
On Tue, 02 Oct 2018 23:54:28 +0200, Daniele Ceraolo Spurio wrote: GuC stores some data in there, which might be stale after a reset. We already reset the WQ head and tail, but more things are being moved to the descriptor with the interface updates. Instead of trying to track them one by one, always memset and init the descriptors from scratch after GuC is loaded. The code is also reorganized so that the above operations and the doorbell creation are grouped as "client enabling" v2: add proc_desc_fini for symmetry (Daniele), remove unneeded var init, add guc_is_alive() (Michal) Cc: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio --- Reviewed-by: Michal Wajdeczko Michal ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.
On Wed, Oct 03, 2018 at 07:51:24AM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 03, 2018 at 11:27:42AM +0530, Yadav, Jyoti R wrote:
> >
> >
> > On 10/3/2018 10:36 AM, Vivi, Rodrigo wrote:
> > >
> > > > On Oct 2, 2018, at 9:20 PM, Yadav, Jyoti R
> > > > wrote:
> > > >
> > > > DC5 and DC6 counter register tells about residency of DC5 and DC6.
> > > > These registers are same for SKL and ICL.
> > > >
> > > > v2 : Remove csr_version check.
> > > > Added generic check regarding DC counters for Gen9 onwards.
> > > > (Rodrigo)
> > > > v3 : Simplified gen checks. (Chris)
> > > >
> > > > Signed-off-by: Jyoti Yadav
> > > > ---
> > > > drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > 2 files changed, 3 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index a5265c2..af13077 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -2897,13 +2897,12 @@ static int i915_dmc_info(struct seq_file *m,
> > > > void *unused)
> > > > seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> > > >CSR_VERSION_MINOR(csr->version));
> > > >
> > > > -if (IS_KABYLAKE(dev_priv) ||
> > > > -(IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
> > > > +if ((!IS_BROXTON(dev_priv)) && IS_GEN(dev_priv, 9, 11)) {
> > > > seq_printf(m, "DC3 -> DC5 count: %d\n",
> > > >I915_READ(SKL_CSR_DC3_DC5_COUNT));
> > > > seq_printf(m, "DC5 -> DC6 count: %d\n",
> > > >I915_READ(SKL_CSR_DC5_DC6_COUNT));
> > > > -} else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1,
> > > > 4)) {
> > > > +} else if (IS_BROXTON(dev_priv)) {
> > > > seq_printf(m, "DC3 -> DC5 count: %d\n",
> > > >I915_READ(BXT_CSR_DC3_DC5_COUNT));
> > > > }
> > > Please do the other way around...
> > > If is broxton {
> > > } else if gen(9,11) {
> > > }
> > >
> > > So no need for repetition with nots...
> > I was thinking of doing the same earlier, but then thought we should
> > maintain Platform hierarchy. Same trend is followed in other files as well.
>
> Hmm... general guidance is to leave newer platforms at the top indeed.
> But I think we cannot enforce that as a hard rule when code cleanliness is
> compromised.
> Besides that we already have other exceptions around and this case is a range
> against only platform who is exception, not actually a platform order. BXT is
> inside the range(9, 11) and is the exception... SKL is older than BXT and in
> your proposed block it comes before bxt what breaks that rule anyways right?!
I think the "new first, old last" is a good general guideline. But I
agree with Rodrigo that sometimes that would make things too messy.
In which case I think we can extend the guideline to "helpful
exceptions first, then follow the new->old order". Eg. VLV/CHV
have a habit of needing such exceptions.
I think generally if you have to stop and really think what the
if-statement is saying you should do something to simplify it.
Sometimes just reordering the if ladder a bit is enough, other
times it can be helpful to just extract the entire condition
into a small helper function that has a descriptive name.
Eg.
if (IS_A || (gen >= x && !IS_B))
vs.
if (has_something())
The first one almost needs pen and paper to decypher. With the
second one you can just keep on reading without having to
waste further brain cells.
>
> > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 8534f88..573d5f3 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -6985,6 +6985,7 @@ enum {
> > > > /* MMIO address range for CSR program (0x8 - 0x82FFF) */
> > > > #define CSR_MMIO_START_RANGE0x8
> > > > #define CSR_MMIO_END_RANGE0x8
> > > > +/* DC3_DC5 count and DC5_DC6 count registers are same for SKL and ICL
> > > > */
> > > > #define SKL_CSR_DC3_DC5_COUNT_MMIO(0x80030)
> > > > #define SKL_CSR_DC5_DC6_COUNT_MMIO(0x8002C)
> > > > #define BXT_CSR_DC3_DC5_COUNT_MMIO(0x80038)
> > > > --
> > > > 1.9.1
> > > >
> >
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.
On Wed, Oct 03, 2018 at 11:27:42AM +0530, Yadav, Jyoti R wrote:
>
>
> On 10/3/2018 10:36 AM, Vivi, Rodrigo wrote:
> >
> > > On Oct 2, 2018, at 9:20 PM, Yadav, Jyoti R
> > > wrote:
> > >
> > > DC5 and DC6 counter register tells about residency of DC5 and DC6.
> > > These registers are same for SKL and ICL.
> > >
> > > v2 : Remove csr_version check.
> > > Added generic check regarding DC counters for Gen9 onwards.
> > > (Rodrigo)
> > > v3 : Simplified gen checks. (Chris)
> > >
> > > Signed-off-by: Jyoti Yadav
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 2 files changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index a5265c2..af13077 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2897,13 +2897,12 @@ static int i915_dmc_info(struct seq_file *m, void
> > > *unused)
> > > seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> > >CSR_VERSION_MINOR(csr->version));
> > >
> > > -if (IS_KABYLAKE(dev_priv) ||
> > > -(IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
> > > +if ((!IS_BROXTON(dev_priv)) && IS_GEN(dev_priv, 9, 11)) {
> > > seq_printf(m, "DC3 -> DC5 count: %d\n",
> > >I915_READ(SKL_CSR_DC3_DC5_COUNT));
> > > seq_printf(m, "DC5 -> DC6 count: %d\n",
> > >I915_READ(SKL_CSR_DC5_DC6_COUNT));
> > > -} else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1,
> > > 4)) {
> > > +} else if (IS_BROXTON(dev_priv)) {
> > > seq_printf(m, "DC3 -> DC5 count: %d\n",
> > >I915_READ(BXT_CSR_DC3_DC5_COUNT));
> > > }
> > Please do the other way around...
> > If is broxton {
> > } else if gen(9,11) {
> > }
> >
> > So no need for repetition with nots...
> I was thinking of doing the same earlier, but then thought we should
> maintain Platform hierarchy. Same trend is followed in other files as well.
Hmm... general guidance is to leave newer platforms at the top indeed.
But I think we cannot enforce that as a hard rule when code cleanliness is
compromised.
Besides that we already have other exceptions around and this case is a range
against only platform who is exception, not actually a platform order. BXT is
inside the range(9, 11) and is the exception... SKL is older than BXT and in
your proposed block it comes before bxt what breaks that rule anyways right?!
> >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 8534f88..573d5f3 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6985,6 +6985,7 @@ enum {
> > > /* MMIO address range for CSR program (0x8 - 0x82FFF) */
> > > #define CSR_MMIO_START_RANGE0x8
> > > #define CSR_MMIO_END_RANGE0x8
> > > +/* DC3_DC5 count and DC5_DC6 count registers are same for SKL and ICL */
> > > #define SKL_CSR_DC3_DC5_COUNT_MMIO(0x80030)
> > > #define SKL_CSR_DC5_DC6_COUNT_MMIO(0x8002C)
> > > #define BXT_CSR_DC3_DC5_COUNT_MMIO(0x80038)
> > > --
> > > 1.9.1
> > >
>
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[Intel-gfx] [PATCH v2 3/3] drm/i915: Clean up early plane debugs
From: Ville Syrjälä
Print the plane hw state readout results in the common format
we already use for pipes and encoders. Also print some clearer
debug messages when we disable planes during the early phases
of state readout/sanitization.
v2: Rebase
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f0d004641b0d..24fe3b1fb2a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2768,10 +2768,6 @@ intel_set_plane_visible(struct intel_crtc_state
*crtc_state,
crtc_state->base.plane_mask |= drm_plane_mask(>base);
else
crtc_state->base.plane_mask &= ~drm_plane_mask(>base);
-
- DRM_DEBUG_KMS("%s active planes 0x%x\n",
- crtc_state->base.crtc->name,
- crtc_state->active_planes);
}
static void fixup_active_planes(struct intel_crtc_state *crtc_state)
@@ -2799,6 +2795,10 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
+ DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
+ plane->base.base.id, plane->base.name,
+ crtc->base.base.id, crtc->base.name);
+
intel_set_plane_visible(crtc_state, plane_state, false);
fixup_active_planes(crtc_state);
@@ -15523,8 +15523,8 @@ intel_sanitize_plane_mapping(struct drm_i915_private
*dev_priv)
if (pipe == crtc->pipe)
continue;
- DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling
plane\n",
- plane->base.name);
+ DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe,
disabling plane\n",
+ plane->base.base.id, plane->base.name);
plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
intel_plane_disable_noatomic(plane_crtc, plane);
@@ -15713,6 +15713,10 @@ static void readout_plane_state(struct
drm_i915_private *dev_priv)
crtc_state = to_intel_crtc_state(crtc->base.state);
intel_set_plane_visible(crtc_state, plane_state, visible);
+
+ DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
+ plane->base.base.id, plane->base.name,
+ enableddisabled(visible), pipe_name(pipe));
}
for_each_intel_crtc(_priv->drm, crtc) {
--
2.16.4
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[Intel-gfx] [PATCH v2 2/3] drm/i915: Use the correct crtc when sanitizing plane mapping
From: Ville Syrjälä
When we decide that a plane is attached to the wrong pipe we try
to turn off said plane. However we are passing around the crtc we
think that the plane is supposed to be using rather than the crtc
it is currently using. That doesn't work all that well because
we may have to do vblank waits etc. and the other pipe might
not even be enabled here. So let's pass the plane's current crtc to
intel_plane_disable_noatomic() so that it can its job correctly.
To do that semi-cleanly we also have to change the plane readout
to record the plane's visibility into the bitmasks of the crtc
where the plane is currently enabled rather than to the crtc
we want to use for the plane.
One caveat here is that our active_planes bitmask will get confused
if both planes are enabled on the same pipe. Fortunately we can use
plane_mask to reconstruct active_planes sufficiently since
plane_mask still has the same meaning (is the plane visible?)
during readout. We also have to do the same during the initial
plane readout as the second plane could clear the active_planes
bit the first plane had already set.
v2: Rely on fixup_active_planes() to populate active_planes fully (Daniel)
Add Daniel's proposed comment to better document why we do this
Drop the redundant intel_set_plane_visible() call
Cc: sta...@vger.kernel.org # fcba862e8428 drm/i915: Have plane->get_hw_state()
return the current pipe
Cc: sta...@vger.kernel.org
Cc: Dennis
Cc: Daniel Vetter
Tested-by: Dennis
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105637
Fixes: b1e01595a66d ("drm/i915: Redo plane sanitation during readout")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 78 +---
1 file changed, 46 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d2828159f6c8..f0d004641b0d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2764,20 +2764,33 @@ intel_set_plane_visible(struct intel_crtc_state
*crtc_state,
plane_state->base.visible = visible;
- /* FIXME pre-g4x don't work like this */
- if (visible) {
+ if (visible)
crtc_state->base.plane_mask |= drm_plane_mask(>base);
- crtc_state->active_planes |= BIT(plane->id);
- } else {
+ else
crtc_state->base.plane_mask &= ~drm_plane_mask(>base);
- crtc_state->active_planes &= ~BIT(plane->id);
- }
DRM_DEBUG_KMS("%s active planes 0x%x\n",
crtc_state->base.crtc->name,
crtc_state->active_planes);
}
+static void fixup_active_planes(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_plane *plane;
+
+ /*
+* Active_planes aliases if multiple "primary" or cursor planes
+* have been used on the same (or wrong) pipe. plane_mask uses
+* unique ids, hence we can use that to reconstruct active_planes.
+*/
+ crtc_state->active_planes = 0;
+
+ drm_for_each_plane_mask(plane, _priv->drm,
+ crtc_state->base.plane_mask)
+ crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
+}
+
static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
struct intel_plane *plane)
{
@@ -2787,6 +2800,7 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
to_intel_plane_state(plane->base.state);
intel_set_plane_visible(crtc_state, plane_state, false);
+ fixup_active_planes(crtc_state);
if (plane->id == PLANE_PRIMARY)
intel_pre_disable_primary_noatomic(>base);
@@ -2805,7 +2819,6 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
struct drm_i915_gem_object *obj;
struct drm_plane *primary = intel_crtc->base.primary;
struct drm_plane_state *plane_state = primary->state;
- struct drm_crtc_state *crtc_state = intel_crtc->base.state;
struct intel_plane *intel_plane = to_intel_plane(primary);
struct intel_plane_state *intel_state =
to_intel_plane_state(plane_state);
@@ -2900,10 +2913,6 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
plane_state->fb = fb;
plane_state->crtc = _crtc->base;
- intel_set_plane_visible(to_intel_crtc_state(crtc_state),
- to_intel_plane_state(plane_state),
- true);
-
atomic_or(to_intel_plane(primary)->frontbuffer_bit,
>frontbuffer_bits);
}
@@ -15494,17 +15503,6 @@ void i830_disable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
POSTING_READ(DPLL(pipe));
}
-static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
-
[Intel-gfx] [PATCH v2 1/3] drm/i915: Restore vblank interrupts earlier
From: Ville Syrjälä
Plane sanitation needs vblank interrupts (on account of CxSR disable).
So let's restore vblank interrupts earlier.
v2: Make it actually build
v3: Add comment to explain why we need this (Daniel)
Cc: sta...@vger.kernel.org
Cc: Dennis
Tested-by: Dennis
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105637
Fixes: b1e01595a66d ("drm/i915: Redo plane sanitation during readout")
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 36434c5359b1..d2828159f6c8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15570,13 +15570,9 @@ static void intel_sanitize_crtc(struct intel_crtc
*crtc,
I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
}
- /* restore vblank interrupts to correct state */
- drm_crtc_vblank_reset(>base);
if (crtc->active) {
struct intel_plane *plane;
- drm_crtc_vblank_on(>base);
-
/* Disable everything but the primary plane */
for_each_intel_plane_on_crtc(dev, crtc, plane) {
const struct intel_plane_state *plane_state =
@@ -15918,7 +15914,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
int i;
@@ -15931,15 +15926,23 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
/* HW state is read out, now we need to sanitize this mess. */
get_encoder_power_domains(dev_priv);
- intel_sanitize_plane_mapping(dev_priv);
+ /*
+* intel_sanitize_plane_mapping() may need to do vblank
+* waits, so we need vblank interrupts restored beforehand.
+*/
+ for_each_intel_crtc(_priv->drm, crtc) {
+ drm_crtc_vblank_reset(>base);
- for_each_intel_encoder(dev, encoder) {
- intel_sanitize_encoder(encoder);
+ if (crtc->active)
+ drm_crtc_vblank_on(>base);
}
- for_each_pipe(dev_priv, pipe) {
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ intel_sanitize_plane_mapping(dev_priv);
+ for_each_intel_encoder(dev, encoder)
+ intel_sanitize_encoder(encoder);
+
+ for_each_intel_crtc(_priv->drm, crtc) {
intel_sanitize_crtc(crtc, ctx);
intel_dump_pipe_config(crtc, crtc->config,
"[setup_hw_state]");
--
2.16.4
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: First cleanup pass to get rid of more crtc->config users.
== Series Details ==
Series: drm/i915: First cleanup pass to get rid of more crtc->config users.
URL : https://patchwork.freedesktop.org/series/50506/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_display.o
In file included from ./include/linux/list.h:9:0,
from ./include/linux/dmi.h:5,
from drivers/gpu/drm/i915/intel_display.c:27:
drivers/gpu/drm/i915/intel_display.c: In function ‘i9xx_set_pll_dividers’:
./include/linux/kernel.h:995:41: error: initialization from incompatible
pointer type [-Werror=incompatible-pointer-types]
#define container_of(ptr, type, member) ({\
^
drivers/gpu/drm/i915/intel_drv.h:1003:26: note: in expansion of macro
‘container_of’
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
^~~~
drivers/gpu/drm/i915/intel_display.c:6110:34: note: in expansion of macro
‘to_intel_crtc’
struct intel_crtc_state *crtc = to_intel_crtc(crtc_state->base.crtc);
^
drivers/gpu/drm/i915/intel_display.c:6111:56: error: ‘struct drm_crtc_state’
has no member named ‘dev’
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
^
In file included from drivers/gpu/drm/i915/intel_drv.h:33:0,
from drivers/gpu/drm/i915/intel_display.c:36:
drivers/gpu/drm/i915/intel_display.c:6113:21: error: ‘struct intel_crtc_state’
has no member named ‘pipe’
I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
^
drivers/gpu/drm/i915/i915_drv.h:3617:76: note: in definition of macro
‘I915_WRITE’
#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv,
(reg), (val), true)
^~~
drivers/gpu/drm/i915/i915_reg.h:161:32: note: in expansion of macro ‘_MMIO’
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
^
drivers/gpu/drm/i915/i915_reg.h:160:27: note: in expansion of macro ‘_PICK_EVEN’
#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
^~
drivers/gpu/drm/i915/i915_reg.h:161:38: note: in expansion of macro ‘_PIPE’
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
^
drivers/gpu/drm/i915/i915_reg.h:3315:19: note: in expansion of macro
‘_MMIO_PIPE’
#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
^~
drivers/gpu/drm/i915/intel_display.c:6113:13: note: in expansion of macro ‘FP0’
I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
^~~
drivers/gpu/drm/i915/intel_display.c:6114:21: error: ‘struct intel_crtc_state’
has no member named ‘pipe’
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
^
drivers/gpu/drm/i915/i915_drv.h:3617:76: note: in definition of macro
‘I915_WRITE’
#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv,
(reg), (val), true)
^~~
drivers/gpu/drm/i915/i915_reg.h:161:32: note: in expansion of macro ‘_MMIO’
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
^
drivers/gpu/drm/i915/i915_reg.h:160:27: note: in expansion of macro ‘_PICK_EVEN’
#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
^~
drivers/gpu/drm/i915/i915_reg.h:161:38: note: in expansion of macro ‘_PIPE’
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
^
drivers/gpu/drm/i915/i915_reg.h:3316:19: note: in expansion of macro
‘_MMIO_PIPE’
#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
^~
drivers/gpu/drm/i915/intel_display.c:6114:13: note: in expansion of macro ‘FP1’
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
^~~
drivers/gpu/drm/i915/intel_display.c: In function ‘i9xx_crtc_enable’:
drivers/gpu/drm/i915/intel_display.c:6131:24: error: passing argument 1 of
‘i9xx_set_pll_dividers’ from incompatible pointer type
[-Werror=incompatible-pointer-types]
i9xx_set_pll_dividers(intel_crtc);
^~
drivers/gpu/drm/i915/intel_display.c:6108:13: note: expected ‘const struct
intel_crtc_state *’ but argument is of type ‘struct intel_crtc *’
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
^
cc1: all warnings being treated as errors
scripts/Makefile.build:305: recipe for target
'drivers/gpu/drm/i915/intel_display.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1
scripts/Makefile.build:546: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Always try to reset the GPU on takeover
== Series Details == Series: drm/i915: Always try to reset the GPU on takeover URL : https://patchwork.freedesktop.org/series/50497/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4920 -> Patchwork_10342 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10342 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10342, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50497/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10342: === IGT changes === Possible regressions igt@drv_module_reload@basic-reload-inject: fi-bwr-2160:PASS -> INCOMPLETE fi-pnv-d510:PASS -> DMESG-WARN fi-blb-e6850: PASS -> DMESG-WARN igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-gdg-551: NOTRUN -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10342 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-bsw-n3050: PASS -> DMESG-WARN (fdo#106207) igt@gem_exec_suspend@basic-s3: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) Possible fixes igt@drv_selftest@live_sanitycheck: fi-bsw-n3050: DMESG-WARN (fdo#106207) -> PASS +6 igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> SKIP igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106207 https://bugs.freedesktop.org/show_bug.cgi?id=106207 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 == Participating hosts (50 -> 45) == Additional (1): fi-gdg-551 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4920 -> Patchwork_10342 CI_DRM_4920: 9e927736cee239e957e2de92774b82fce5223587 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10342: 66aba631f7a4a3e7175e35aed8a8e954c5c1a668 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 66aba631f7a4 drm/i915: Always try to reset the GPU on takeover == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10342/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for 21st century intel_gpu_top
== Series Details == Series: 21st century intel_gpu_top URL : https://patchwork.freedesktop.org/series/50498/ State : failure == Summary == Applying: drm/i915/pmu: Fix enable count array size and bounds checking Applying: drm/i915: Keep a count of requests waiting for a slot on GPU Applying: drm/i915: Keep a count of requests submitted from userspace Applying: drm/i915/pmu: Add queued counter Applying: drm/i915/pmu: Add runnable counter Applying: drm/i915/pmu: Add running counter Applying: drm/i915: Store engine backpointer in the intel_context Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_gem_context.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_gem_context.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_context.h error: Failed to merge in the changes. Patch failed at 0007 drm/i915: Store engine backpointer in the intel_context Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use the correct crtc when sanitizing plane mapping
On Wed, Oct 03, 2018 at 10:53:11AM +0200, Daniel Vetter wrote:
> On Tue, Oct 02, 2018 at 05:21:36PM +0300, Ville Syrjälä wrote:
> > On Tue, Oct 02, 2018 at 02:11:34PM +0200, Daniel Vetter wrote:
> > > On Mon, Oct 01, 2018 at 05:31:20PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > When we decide that a plane is attached to the wrong pipe we try
> > > > to turn off said plane. However we are passing around the crtc we
> > > > think that the plane is supposed to be using rather than the crtc
> > > > it is currently using. That doesn't work all that well because
> > > > we may have to do vblank waits etc. and the other pipe might
> > > > not even be enabled here. So let's pass the plane's current crtc to
> > > > intel_plane_disable_noatomic() so that it can its job correctly.
> > > >
> > > > To do that semi-cleanly we also have to change the plane readout
> > > > to record the plane's visibility into the bitmasks of the crtc
> > > > where the plane is currently enabled rather than to the crtc
> > > > we want to use for the plane.
> > > >
> > > > One caveat here is that our active_planes bitmask will get confused
> > > > if both planes are enabled on the same pipe. Fortunately we can use
> > > > plane_mask to reconstruct active_planes sufficiently since
> > > > plane_mask still has the same meaning (is the plane visible?)
> > > > during readout. We also have to do the same during the initial
> > > > plane readout as the second plane could clear the active_planes
> > > > bit the first plane had already set.
> > >
> > > How often have we broken this :-/
> > >
> > > Unfortunately I still don't have a good idea how to best CI this, since we
> > > shut down everything on module unload. Maybe we should have a special mode
> > > for module unload to leave the hw on, so that we can start testing various
> > > fastboot scenarios ...
> >
> > Yeah, that might be nice. Though wouldn't directly help here since
> > we'd still have to move the plane to the other pipe. But we could
> > of course make the driver unload do that for us as well.
> >
> > Oh and to hit this bug we'd also need to make sure cxsr is enabled
> > when we unload as that's what leads to the vblank wait. That's actually
> > the reason I didn't catch this bug originally. None of my machines
> > have a VBIOS that enables cxsr.
>
> Well that should be easy, as long as i915.ko enables cxsr ...
>
> Just pondered this since with Hans' work fedora is now using fastbook, so
> constantly breaking this stuff is kinda no longer a good option. But
> definitely future work.
>
> > > Some questions below.
> > >
> > > > Cc: sta...@vger.kernel.org # fcba862e8428 drm/i915: Have
> > > > plane->get_hw_state() return the current pipe
> > > > Cc: sta...@vger.kernel.org
> > > > Cc: Dennis
> > > > Tested-by: Dennis
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105637
> > > > Fixes: b1e01595a66d ("drm/i915: Redo plane sanitation during readout")
> > > > Signed-off-by: Ville Syrjälä
> > > > ---
> > > > drivers/gpu/drm/i915/intel_display.c | 63
> > > > +++-
> > > > 1 file changed, 47 insertions(+), 16 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index e018b37bed39..c72be8cd1f54 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -15475,15 +15475,16 @@ void i830_disable_pipe(struct
> > > > drm_i915_private *dev_priv, enum pipe pipe)
> > > > POSTING_READ(DPLL(pipe));
> > > > }
> > > >
> > > > -static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
> > > > - struct intel_plane *plane)
> > > > +static void fixup_active_planes(struct intel_crtc *crtc)
> > > > {
> > > > - enum pipe pipe;
> > > > -
> > > > - if (!plane->get_hw_state(plane, ))
> > > > - return true;
> > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > + struct intel_crtc_state *crtc_state =
> > > > + to_intel_crtc_state(crtc->base.state);
> > > > + struct drm_plane *plane;
> > > >
> > > > - return pipe == crtc->pipe;
> > > > + drm_for_each_plane_mask(plane, _priv->drm,
> > > > + crtc_state->base.plane_mask)
> > > > + crtc_state->active_planes |=
> > > > BIT(to_intel_plane(plane)->id);
> > >
> > > I think we need to also update plane_mask here.
> >
> > plane_mask will be correct since each plane has a unique bit there.
> > And in fact we use plane_mask to reconstruct active_planes.
> >
> > What we could do is set active_planes=0 before the loop, as the loop
> > will populate it fully anyway.
>
> That + comment explaining why we don't need to reconstruct plane_mask
> would be good. Since I completely missed that. Something like:
>
> /* active_planes aliases if mutliple
Re: [Intel-gfx] [PATCH 13/13] drm/i915: Get rid of intel_crtc->config in crtc_enable/disable functions
On Wed, Oct 03, 2018 at 03:37:15PM +0200, Maarten Lankhorst wrote:
> These functions already have a pointer to the correct state,
> so use it instead of crtc->config.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 60 ++--
> 1 file changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 22f556b824f9..01ad6bd3b7de 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5594,15 +5594,15 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
> if (pipe_config->has_pch_encoder)
> intel_prepare_shared_dpll(pipe_config);
>
> - if (intel_crtc_has_dp_encoder(intel_crtc->config))
> + if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(pipe_config);
> intel_set_pipe_src_size(pipe_config);
>
> - if (intel_crtc->config->has_pch_encoder) {
> + if (pipe_config->has_pch_encoder) {
> intel_cpu_transcoder_set_m_n(intel_crtc,
> - _crtc->config->fdi_m_n, NULL);
> + _config->fdi_m_n, NULL);
> }
>
> ironlake_set_pipeconf(pipe_config);
> @@ -5611,7 +5611,7 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
>
> intel_encoders_pre_enable(crtc, pipe_config, old_state);
>
> - if (intel_crtc->config->has_pch_encoder) {
> + if (pipe_config->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
>* cpu pipes, hence this is separate from all the other fdi/pch
>* enabling. */
> @@ -5630,10 +5630,10 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
> intel_color_load_luts(_config->base);
>
> if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(old_intel_state,
> intel_crtc->config);
> + dev_priv->display.initial_watermarks(old_intel_state,
> pipe_config);
> intel_enable_pipe(pipe_config);
>
> - if (intel_crtc->config->has_pch_encoder)
> + if (pipe_config->has_pch_encoder)
> ironlake_pch_enable(old_intel_state, pipe_config);
>
> assert_vblank_disabled(crtc);
> @@ -5650,7 +5650,7 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
>* some interlaced HDMI modes. Let's do the double wait always
>* in case there are more corner cases we don't know about.
>*/
> - if (intel_crtc->config->has_pch_encoder) {
> + if (pipe_config->has_pch_encoder) {
> intel_wait_for_vblank(dev_priv, pipe);
> intel_wait_for_vblank(dev_priv, pipe);
> }
> @@ -5699,7 +5699,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
> *pipe_config,
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_crtc->pipe, hsw_workaround_pipe;
> - enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> struct intel_atomic_state *old_intel_state =
> to_intel_atomic_state(old_state);
> bool psl_clkgate_wa;
> @@ -5718,7 +5718,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
> *pipe_config,
>
> intel_encoders_pre_enable(crtc, pipe_config, old_state);
>
> - if (intel_crtc_has_dp_encoder(intel_crtc->config))
> + if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -5729,12 +5729,12 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
> if (cpu_transcoder != TRANSCODER_EDP &&
> !transcoder_is_dsi(cpu_transcoder)) {
> I915_WRITE(PIPE_MULT(cpu_transcoder),
> -intel_crtc->config->pixel_multiplier - 1);
> +pipe_config->pixel_multiplier - 1);
> }
>
> - if (intel_crtc->config->has_pch_encoder) {
> + if (pipe_config->has_pch_encoder) {
> intel_cpu_transcoder_set_m_n(intel_crtc,
> - _crtc->config->fdi_m_n, NULL);
> + _config->fdi_m_n, NULL);
> }
>
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -5748,7 +5748,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
> *pipe_config,
>
> /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> - intel_crtc->config->pch_pfit.enabled;
> + pipe_config->pch_pfit.enabled;
> if
Re: [Intel-gfx] [PATCH 12/13] drm/i915: Get rid of crtc->config in chv_data_lane_soft_reset
On Wed, Oct 03, 2018 at 03:37:14PM +0200, Maarten Lankhorst wrote:
> Fixing chv_set_phy_signal_level() still requires too many levels of
> indirection to pass crtc_state along.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_dpio_phy.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 00b3ab656b06..3c7f10d17658 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -748,7 +748,7 @@ void chv_data_lane_soft_reset(struct intel_encoder
> *encoder,
> val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
>
> - if (crtc->config->lane_count > 2) {
> + if (crtc_state->lane_count > 2) {
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> if (reset)
> val &= ~(DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET);
> @@ -765,7 +765,7 @@ void chv_data_lane_soft_reset(struct intel_encoder
> *encoder,
> val |= DPIO_PCS_CLK_SOFT_RESET;
> vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
>
> - if (crtc->config->lane_count > 2) {
> + if (crtc_state->lane_count > 2) {
Reviewed-by: Ville Syrjälä
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> val |= CHV_PCS_REQ_SOFTRESET_EN;
> if (reset)
> --
> 2.19.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/13] drm/i915: Get rid of crtc->config dereference in intel_dp_retrain_link
On Wed, Oct 03, 2018 at 03:37:13PM +0200, Maarten Lankhorst wrote: > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 15a981ef5966..d9cc52b2ba79 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -4417,7 +4417,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, > > /* Suppress underruns caused by re-training */ > intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); > - if (crtc->config->has_pch_encoder) > + if (crtc_state->has_pch_encoder) Oh yes, we have a state now. Which means all the remaining ->config usages in link training code should also be nukeable now? Mostly down to some plumbing work perhaps? Reviewed-by: Ville Syrjälä > intel_set_pch_fifo_underrun_reporting(dev_priv, > > intel_crtc_pch_transcoder(crtc), false); > > @@ -4428,7 +4428,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, > intel_wait_for_vblank(dev_priv, crtc->pipe); > > intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); > - if (crtc->config->has_pch_encoder) > + if (crtc_state->has_pch_encoder) > intel_set_pch_fifo_underrun_reporting(dev_priv, > > intel_crtc_pch_transcoder(crtc), true); > > -- > 2.19.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/13] drm/i915: Use crtc->state in intel_fbdev_init_bios
On Wed, Oct 03, 2018 at 03:37:12PM +0200, Maarten Lankhorst wrote:
> fbdev init shouldn't race with userspace since it's called from
> intel_modeset_init, so it's safe to dereference crtc->state and
> assume nothing changed yet.
>
> At least not more harmful than crtc->config.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_fbdev.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
> b/drivers/gpu/drm/i915/intel_fbdev.c
> index f99332972b7a..2480c7d6edee 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -593,7 +593,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
>* pipe. Note we need to use the selected fb's pitch and bpp
>* rather than the current pipe's, since they differ.
>*/
> - cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay;
> + cur_size = crtc->state->adjusted_mode.crtc_hdisplay;
Yeah, we're alreday looking at crtc->state->active above, so this should
equally safe.
Reviewed-by: Ville Syrjälä
> cur_size = cur_size * fb->base.format->cpp[0];
> if (fb->base.pitches[0] < cur_size) {
> DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs
> %d)\n",
> @@ -603,13 +603,13 @@ static bool intel_fbdev_init_bios(struct drm_device
> *dev,
> break;
> }
>
> - cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
> + cur_size = crtc->state->adjusted_mode.crtc_vdisplay;
> cur_size = intel_fb_align_height(>base, 0, cur_size);
> cur_size *= fb->base.pitches[0];
> DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
> pipe_name(intel_crtc->pipe),
> -
> intel_crtc->config->base.adjusted_mode.crtc_hdisplay,
> -
> intel_crtc->config->base.adjusted_mode.crtc_vdisplay,
> + crtc->state->adjusted_mode.crtc_hdisplay,
> + crtc->state->adjusted_mode.crtc_vdisplay,
> fb->base.format->cpp[0] * 8,
> cur_size);
>
> --
> 2.19.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 09/13] drm/i915: Get rid of crtc->config from icl_pll_to_ddi_pll_sel
On Wed, Oct 03, 2018 at 03:37:11PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
With a bit if commit msg added
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b6594948b617..9e82281b4fdf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1060,10 +1060,10 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct
> intel_shared_dpll *pll)
> }
>
> static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> -const struct intel_shared_dpll *pll)
> +const struct intel_crtc_state
> *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - int clock = crtc->config->port_clock;
> + const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + int clock = crtc_state->port_clock;
> const enum intel_dpll_id id = pll->info->id;
>
> switch (id) {
> @@ -2798,11 +2798,12 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
> }
>
> static void intel_ddi_clk_select(struct intel_encoder *encoder,
> - const struct intel_shared_dpll *pll)
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> uint32_t val;
> + const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> if (WARN_ON(!pll))
> return;
> @@ -2812,7 +2813,7 @@ static void intel_ddi_clk_select(struct intel_encoder
> *encoder,
> if (IS_ICELAKE(dev_priv)) {
> if (port >= PORT_C)
> I915_WRITE(DDI_CLK_SEL(port),
> -icl_pll_to_ddi_pll_sel(encoder, pll));
> +icl_pll_to_ddi_pll_sel(encoder, crtc_state));
> } else if (IS_CANNONLAKE(dev_priv)) {
> /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
> val = I915_READ(DPCLKA_CFGCR0);
> @@ -2886,7 +2887,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>
> intel_edp_panel_on(intel_dp);
>
> - intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
> + intel_ddi_clk_select(encoder, crtc_state);
>
> intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>
> @@ -2928,7 +2929,7 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
> struct intel_digital_port *dig_port = enc_to_dig_port(>base);
>
> intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> - intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
> + intel_ddi_clk_select(encoder, crtc_state);
>
> intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>
> --
> 2.19.0
>
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Re: [Intel-gfx] [PATCH 08/13] drm/i915: Make shared dpll functions take crtc_state
On Wed, Oct 03, 2018 at 03:37:10PM +0200, Maarten Lankhorst wrote:
> Do not rely on crtc->config any more. Remove the assertion from
> ibx_pch_dpll_disable, because we the dpll state tracking should
> already handle this case correctly.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 14 ++--
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 31 +++
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 6 +++---
> 3 files changed, 22 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 57c81e8e44be..22f556b824f9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4749,7 +4749,7 @@ static void ironlake_pch_enable(const struct
> intel_atomic_state *state,
>* Note that enable_shared_dpll tries to do the right thing, but
>* get_shared_dpll unconditionally resets the pll - we need that to have
>* the right LVDS enable sequence. */
> - intel_enable_shared_dpll(crtc);
> + intel_enable_shared_dpll(crtc_state);
>
> /* set transcoder timing, panel must allow it */
> assert_panel_unlocked(dev_priv, pipe);
> @@ -5591,8 +5591,8 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - if (intel_crtc->config->has_pch_encoder)
> - intel_prepare_shared_dpll(intel_crtc);
> + if (pipe_config->has_pch_encoder)
> + intel_prepare_shared_dpll(pipe_config);
>
> if (intel_crtc_has_dp_encoder(intel_crtc->config))
> intel_dp_set_m_n(intel_crtc, M1_N1);
> @@ -5710,8 +5710,8 @@ static void haswell_crtc_enable(struct intel_crtc_state
> *pipe_config,
>
> intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>
> - if (intel_crtc->config->shared_dpll)
> - intel_enable_shared_dpll(intel_crtc);
> + if (pipe_config->shared_dpll)
> + intel_enable_shared_dpll(pipe_config);
>
> if (INTEL_GEN(dev_priv) >= 11)
> icl_map_plls_to_ports(crtc, pipe_config, old_state);
> @@ -6286,7 +6286,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
> *crtc,
>
> intel_fbc_disable(intel_crtc);
> intel_update_watermarks(intel_crtc);
> - intel_disable_shared_dpll(intel_crtc);
> + intel_disable_shared_dpll(crtc_state);
>
> domains = intel_crtc->enabled_power_domains;
> for_each_power_domain(domain, domains)
> @@ -12735,7 +12735,7 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> dev_priv->display.crtc_disable(old_intel_crtc_state,
> state);
> intel_crtc->active = false;
> intel_fbc_disable(intel_crtc);
> - intel_disable_shared_dpll(intel_crtc);
> + intel_disable_shared_dpll(old_intel_crtc_state);
>
> /*
>* Underruns don't always raise
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index e6cac9225536..54662c974c0b 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -131,13 +131,13 @@ void assert_shared_dpll(struct drm_i915_private
> *dev_priv,
> * This calls the PLL's prepare hook if it has one and if the PLL is not
> * already enabled. The prepare hook is platform specific.
> */
> -void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> +void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_shared_dpll *pll = crtc->config->shared_dpll;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> - if (WARN_ON(pll == NULL))
> + if (!WARN_ON(!pll))
> return;
>
> mutex_lock(_priv->dpll_lock);
> @@ -158,11 +158,11 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> *
> * Enable the shared DPLL used by @crtc.
> */
> -void intel_enable_shared_dpll(struct intel_crtc *crtc)
> +void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_shared_dpll *pll = crtc->config->shared_dpll;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> unsigned int crtc_mask = drm_crtc_mask(>base);
Re: [Intel-gfx] [PATCH 07/13] drm/i915: Make ironlake_pch_transcoder_set_timings take crtc_state
On Wed, Oct 03, 2018 at 03:37:09PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
commit msg
Otherwise
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 36a8d5fb8881..57c81e8e44be 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4599,12 +4599,12 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
>desired_divisor << auxdiv);
> }
>
> -static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
> +static void ironlake_pch_transcoder_set_timings(const struct
> intel_crtc_state *crtc_state,
> enum pipe pch_transcoder)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
> I915_READ(HTOTAL(cpu_transcoder)));
> @@ -4753,7 +4753,7 @@ static void ironlake_pch_enable(const struct
> intel_atomic_state *state,
>
> /* set transcoder timing, panel must allow it */
> assert_panel_unlocked(dev_priv, pipe);
> - ironlake_pch_transcoder_set_timings(crtc, pipe);
> + ironlake_pch_transcoder_set_timings(crtc_state, pipe);
>
> intel_fdi_normal_train(crtc);
>
> @@ -4800,7 +4800,7 @@ static void lpt_pch_enable(const struct
> intel_atomic_state *state,
> lpt_program_iclkip(crtc);
>
> /* Set transcoder timing. */
> - ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
> + ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
>
> lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
> }
> --
> 2.19.0
>
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Re: [Intel-gfx] [PATCH 06/13] drm/i915: Make pll functions take crtc_state
On Wed, Oct 03, 2018 at 03:37:08PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 56784ae26369..36a8d5fb8881 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1565,14 +1565,15 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
> }
> }
>
> -static void i9xx_disable_pll(struct intel_crtc *crtc)
> +static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> /* Disable DVO 2x clock on both PLLs if necessary */
> if (IS_I830(dev_priv) &&
> - intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
> + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO) &&
> !intel_num_dvo_pipes(dev_priv)) {
> I915_WRITE(DPLL(PIPE_B),
> I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
> @@ -4323,10 +4324,10 @@ static void ivb_manual_fdi_link_train(struct
> intel_crtc *crtc,
> DRM_DEBUG_KMS("FDI train done.\n");
> }
Looks like you missed i9xx_set_pll_dividers() here. I think I saw it in
a later patch though, but maybe move it here?
commit msg...
Otherwise
Reviewed-by: Ville Syrjälä
>
> -static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
> +static void ironlake_fdi_pll_enable(const struct intel_crtc_state
> *crtc_state)
> {
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> int pipe = intel_crtc->pipe;
> i915_reg_t reg;
> u32 temp;
> @@ -4335,7 +4336,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc
> *intel_crtc)
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
> - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> + temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
> temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
> I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
>
> @@ -5614,7 +5615,7 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
> /* Note: FDI PLL enabling _must_ be done before we enable the
>* cpu pipes, hence this is separate from all the other fdi/pch
>* enabling. */
> - ironlake_fdi_pll_enable(intel_crtc);
> + ironlake_fdi_pll_enable(pipe_config);
> } else {
> assert_fdi_tx_disabled(dev_priv, pipe);
> assert_fdi_rx_disabled(dev_priv, pipe);
> @@ -6211,7 +6212,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state
> *old_crtc_state,
> else if (IS_VALLEYVIEW(dev_priv))
> vlv_disable_pll(dev_priv, pipe);
> else
> - i9xx_disable_pll(intel_crtc);
> + i9xx_disable_pll(old_crtc_state);
> }
>
> intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
> --
> 2.19.0
>
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Re: [Intel-gfx] [PATCH 05/13] drm/i915: Make skl_detach_scalers take crtc_state
On Wed, Oct 03, 2018 at 03:37:07PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 91574abafb65..56784ae26369 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3502,13 +3502,13 @@ static void skl_detach_scaler(struct intel_crtc
> *intel_crtc, int id)
> /*
> * This function detaches (aka. unbinds) unused scalers in hardware
> */
> -static void skl_detach_scalers(struct intel_crtc *intel_crtc)
> +static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc_scaler_state *scaler_state;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
s/intel_crtc/crtc/ looks easy enough to sneak in again.
Commit msg missing.
Otherwise
Reviewed-by: Ville Syrjälä
> + const struct intel_crtc_scaler_state *scaler_state =
> + _state->scaler_state;
> int i;
>
> - scaler_state = _crtc->config->scaler_state;
> -
> /* loop through and disable scalers that aren't in use */
> for (i = 0; i < intel_crtc->num_scalers; i++) {
> if (!scaler_state->scalers[i].in_use)
> @@ -3916,7 +3916,7 @@ static void intel_update_pipe_config(const struct
> intel_crtc_state *old_crtc_sta
>
> /* on skylake this is done by detaching scalers */
> if (INTEL_GEN(dev_priv) >= 9) {
> - skl_detach_scalers(crtc);
> + skl_detach_scalers(new_crtc_state);
>
> if (new_crtc_state->pch_pfit.enabled)
> skylake_pfit_enable(new_crtc_state);
> @@ -13335,7 +13335,7 @@ static void intel_begin_crtc_commit(struct drm_crtc
> *crtc,
> if (intel_cstate->update_pipe)
> intel_update_pipe_config(old_intel_cstate, intel_cstate);
> else if (INTEL_GEN(dev_priv) >= 9)
> - skl_detach_scalers(intel_crtc);
> + skl_detach_scalers(intel_cstate);
>
> out:
> if (dev_priv->display.atomic_update_watermarks)
> --
> 2.19.0
>
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Re: [Intel-gfx] [PATCH 04/13] drm/i915: Use crtc_state in ironlake_enable_pch_transcoder
On Wed, Oct 03, 2018 at 03:37:06PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ca5e4d72d476..91574abafb65 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1666,16 +1666,16 @@ void vlv_wait_port_ready(struct drm_i915_private
> *dev_priv,
>I915_READ(dpll_reg) & port_mask, expected_mask);
> }
>
> -static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> -enum pipe pipe)
> +static void ironlake_enable_pch_transcoder(const struct intel_crtc_state
> *crtc_state)
> {
> - struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
> - pipe);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
s/intel_crtc/crtc/ looks easy here as well, And commit msg is awol.
Otherwise
Reviewed-by: Ville Syrjälä
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> + enum pipe pipe = intel_crtc->pipe;
> i915_reg_t reg;
> uint32_t val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> - assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
> + assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
>
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(dev_priv, pipe);
> @@ -1701,7 +1701,7 @@ static void ironlake_enable_pch_transcoder(struct
> drm_i915_private *dev_priv,
>* here for both 8bpc and 12bpc.
>*/
> val &= ~PIPECONF_BPC_MASK;
> - if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> val |= PIPECONF_8BPC;
> else
> val |= pipeconf_val & PIPECONF_BPC_MASK;
> @@ -1710,7 +1710,7 @@ static void ironlake_enable_pch_transcoder(struct
> drm_i915_private *dev_priv,
> val &= ~TRANS_INTERLACE_MASK;
> if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
> if (HAS_PCH_IBX(dev_priv) &&
> - intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
> + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> val |= TRANS_LEGACY_INTERLACED_ILK;
> else
> val |= TRANS_INTERLACED;
> @@ -4784,7 +4784,7 @@ static void ironlake_pch_enable(const struct
> intel_atomic_state *state,
> I915_WRITE(reg, temp);
> }
>
> - ironlake_enable_pch_transcoder(dev_priv, pipe);
> + ironlake_enable_pch_transcoder(crtc_state);
> }
>
> static void lpt_pch_enable(const struct intel_atomic_state *state,
> --
> 2.19.0
>
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Re: [Intel-gfx] [PATCH 03/13] drm/i915: Make intel_set_pipe_timings/src_size take a pointer to crtc_state
On Wed, Oct 03, 2018 at 03:37:05PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 41 ++--
> 1 file changed, 20 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 701caab4e382..ca5e4d72d476 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -142,8 +142,8 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *ifb,
> struct drm_i915_gem_object *obj,
> struct drm_mode_fb_cmd2 *mode_cmd);
> static void i9xx_set_pipeconf(struct intel_crtc_state *crtc_state);
> -static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
> -static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
> +static void intel_set_pipe_timings(const struct intel_crtc_state
> *crtc_state);
> +static void intel_set_pipe_src_size(const struct intel_crtc_state
> *crtc_state);
> static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>struct intel_link_m_n *m_n,
>struct intel_link_m_n *m2_n2);
> @@ -5596,8 +5596,8 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
> if (intel_crtc_has_dp_encoder(intel_crtc->config))
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> - intel_set_pipe_timings(intel_crtc);
> - intel_set_pipe_src_size(intel_crtc);
> + intel_set_pipe_timings(pipe_config);
> + intel_set_pipe_src_size(pipe_config);
>
> if (intel_crtc->config->has_pch_encoder) {
> intel_cpu_transcoder_set_m_n(intel_crtc,
> @@ -5721,9 +5721,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
> *pipe_config,
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_set_pipe_timings(intel_crtc);
> + intel_set_pipe_timings(pipe_config);
>
> - intel_set_pipe_src_size(intel_crtc);
> + intel_set_pipe_src_size(pipe_config);
>
> if (cpu_transcoder != TRANSCODER_EDP &&
> !transcoder_is_dsi(cpu_transcoder)) {
> @@ -6062,12 +6062,10 @@ static void valleyview_crtc_enable(struct
> intel_crtc_state *pipe_config,
> if (intel_crtc_has_dp_encoder(intel_crtc->config))
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> - intel_set_pipe_timings(intel_crtc);
> - intel_set_pipe_src_size(intel_crtc);
> + intel_set_pipe_timings(pipe_config);
> + intel_set_pipe_src_size(pipe_config);
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> I915_WRITE(CHV_CANVAS(pipe), 0);
> }
> @@ -6134,8 +6132,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state
> *pipe_config,
> if (intel_crtc_has_dp_encoder(intel_crtc->config))
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> - intel_set_pipe_timings(intel_crtc);
> - intel_set_pipe_src_size(intel_crtc);
> + intel_set_pipe_timings(pipe_config);
> + intel_set_pipe_src_size(pipe_config);
>
> i9xx_set_pipeconf(pipe_config);
>
> @@ -7331,12 +7329,13 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
> crtc_state->dpll_hw_state.dpll = dpll;
> }
>
> -static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> +static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
More easy s/intel_crtc/crtc/ candidates in this patch.
And missing a commit message. Otherwise lgtm
Reviewed-by: Ville Syrjälä
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> enum pipe pipe = intel_crtc->pipe;
> - enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> - const struct drm_display_mode *adjusted_mode =
> _crtc->config->base.adjusted_mode;
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + const struct drm_display_mode *adjusted_mode =
> _state->base.adjusted_mode;
> uint32_t crtc_vtotal, crtc_vblank_end;
> int vsyncshift = 0;
>
> @@ -7350,7 +7349,7 @@ static void intel_set_pipe_timings(struct intel_crtc
> *intel_crtc)
> crtc_vtotal -= 1;
> crtc_vblank_end -= 1;
>
> - if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
> else
> vsyncshift = adjusted_mode->crtc_hsync_start -
> @@ -7392,18 +7391,18 @@ static void intel_set_pipe_timings(struct intel_crtc
> *intel_crtc)
>
> }
Re: [Intel-gfx] [PATCH 02/13] drm/i915: Make panel fitter functions take state
On Wed, Oct 03, 2018 at 03:37:04PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 91 ++--
> 1 file changed, 45 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 264feed76c08..701caab4e382 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -158,9 +158,9 @@ static void intel_begin_crtc_commit(struct drm_crtc *,
> struct drm_crtc_state *);
> static void intel_finish_crtc_commit(struct drm_crtc *, struct
> drm_crtc_state *);
> static void intel_crtc_init_scalers(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state);
> -static void skylake_pfit_enable(struct intel_crtc *crtc);
> -static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
> -static void ironlake_pfit_enable(struct intel_crtc *crtc);
> +static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
> +static void ironlake_pfit_disable(const struct intel_crtc_state
> *old_crtc_state);
> +static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
> static void intel_modeset_setup_hw_state(struct drm_device *dev,
>struct drm_modeset_acquire_ctx *ctx);
> static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
> @@ -3919,12 +3919,12 @@ static void intel_update_pipe_config(const struct
> intel_crtc_state *old_crtc_sta
> skl_detach_scalers(crtc);
>
> if (new_crtc_state->pch_pfit.enabled)
> - skylake_pfit_enable(crtc);
> + skylake_pfit_enable(new_crtc_state);
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> if (new_crtc_state->pch_pfit.enabled)
> - ironlake_pfit_enable(crtc);
> + ironlake_pfit_enable(new_crtc_state);
> else if (old_crtc_state->pch_pfit.enabled)
> - ironlake_pfit_disable(crtc, true);
> + ironlake_pfit_disable(old_crtc_state);
> }
> }
>
> @@ -5041,19 +5041,19 @@ static void skylake_scaler_disable(struct intel_crtc
> *crtc)
> skl_detach_scaler(crtc, i);
> }
>
> -static void skylake_pfit_enable(struct intel_crtc *crtc)
> +static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe = crtc->pipe;
> - struct intel_crtc_scaler_state *scaler_state =
> - >config->scaler_state;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + const struct intel_crtc_scaler_state *scaler_state =
> + _state->scaler_state;
>
> - if (crtc->config->pch_pfit.enabled) {
> + if (crtc_state->pch_pfit.enabled) {
> u16 uv_rgb_hphase, uv_rgb_vphase;
> int id;
>
> - if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
> + if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> return;
>
> uv_rgb_hphase = skl_scaler_calc_phase(1, false);
> @@ -5066,18 +5066,18 @@ static void skylake_pfit_enable(struct intel_crtc
> *crtc)
> PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
> I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
> PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> - I915_WRITE(SKL_PS_WIN_POS(pipe, id),
> crtc->config->pch_pfit.pos);
> - I915_WRITE(SKL_PS_WIN_SZ(pipe, id),
> crtc->config->pch_pfit.size);
> + I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
> + I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
> }
> }
>
> -static void ironlake_pfit_enable(struct intel_crtc *crtc)
> +static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int pipe = crtc->pipe;
>
> - if (crtc->config->pch_pfit.enabled) {
> + if (crtc_state->pch_pfit.enabled) {
> /* Force use of hard-coded filter coefficients
>* as some pre-programmed values are broken,
>* e.g. x201.
> @@ -5087,8 +5087,8 @@ static void ironlake_pfit_enable(struct intel_crtc
> *crtc)
>PF_PIPE_SEL_IVB(pipe));
> else
> I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
> -
Re: [Intel-gfx] [PATCH 01/13] drm/i915: Remove dereferences of crtc->config in set_pipeconf/misc functions.
On Wed, Oct 03, 2018 at 03:37:03PM +0200, Maarten Lankhorst wrote:
> One more user of crtc->config down. :)
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 72 ++--
> 1 file changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 36434c5359b1..264feed76c08 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -141,15 +141,15 @@ static void ironlake_pch_clock_get(struct intel_crtc
> *crtc,
> static int intel_framebuffer_init(struct intel_framebuffer *ifb,
> struct drm_i915_gem_object *obj,
> struct drm_mode_fb_cmd2 *mode_cmd);
> -static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
> +static void i9xx_set_pipeconf(struct intel_crtc_state *crtc_state);
Group this with the others?
I think the state can be const for all of these.
> static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
> static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
> static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>struct intel_link_m_n *m_n,
>struct intel_link_m_n *m2_n2);
> -static void ironlake_set_pipeconf(struct drm_crtc *crtc);
> -static void haswell_set_pipeconf(struct drm_crtc *crtc);
> -static void haswell_set_pipemisc(struct drm_crtc *crtc);
> +static void ironlake_set_pipeconf(struct intel_crtc_state *crtc_state);
> +static void haswell_set_pipeconf(struct intel_crtc_state *crtc_state);
> +static void haswell_set_pipemisc(struct intel_crtc_state *crtc_state);
> static void vlv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> static void chv_prepare_pll(struct intel_crtc *crtc,
> @@ -5604,7 +5604,7 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
>_crtc->config->fdi_m_n, NULL);
> }
>
> - ironlake_set_pipeconf(crtc);
> + ironlake_set_pipeconf(pipe_config);
>
> intel_crtc->active = true;
>
> @@ -5737,9 +5737,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
> *pipe_config,
> }
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - haswell_set_pipeconf(crtc);
> + haswell_set_pipeconf(pipe_config);
>
> - haswell_set_pipemisc(crtc);
> + haswell_set_pipemisc(pipe_config);
>
> intel_color_set_csc(_config->base);
>
> @@ -6073,7 +6073,7 @@ static void valleyview_crtc_enable(struct
> intel_crtc_state *pipe_config,
> I915_WRITE(CHV_CANVAS(pipe), 0);
> }
>
> - i9xx_set_pipeconf(intel_crtc);
> + i9xx_set_pipeconf(pipe_config);
>
> intel_color_set_csc(_config->base);
>
> @@ -6138,7 +6138,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state
> *pipe_config,
> intel_set_pipe_timings(intel_crtc);
> intel_set_pipe_src_size(intel_crtc);
>
> - i9xx_set_pipeconf(intel_crtc);
> + i9xx_set_pipeconf(pipe_config);
>
> intel_crtc->active = true;
>
> @@ -7480,8 +7480,9 @@ void intel_mode_from_pipe_config(struct
> drm_display_mode *mode,
> drm_mode_set_name(mode);
> }
>
> -static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> +static void i9xx_set_pipeconf(struct intel_crtc_state *crtc_state)
> {
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
s/intel_crtc/crtc/ while at it?
same in the other functions.
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> uint32_t pipeconf;
>
> @@ -7491,18 +7492,18 @@ static void i9xx_set_pipeconf(struct intel_crtc
> *intel_crtc)
> if (IS_I830(dev_priv))
> pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) &
> PIPECONF_ENABLE;
>
> - if (intel_crtc->config->double_wide)
> + if (crtc_state->double_wide)
> pipeconf |= PIPECONF_DOUBLE_WIDE;
>
> /* only g4x and later have fancy bpc/dither controls */
> if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> IS_CHERRYVIEW(dev_priv)) {
> /* Bspec claims that we can't use dithering for 30bpp pipes. */
> - if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp
> != 30)
> + if (crtc_state->dither && crtc_state->pipe_bpp != 30)
> pipeconf |= PIPECONF_DITHER_EN |
> PIPECONF_DITHER_TYPE_SP;
>
> - switch (intel_crtc->config->pipe_bpp) {
> + switch (crtc_state->pipe_bpp) {
> case 18:
> pipeconf |= PIPECONF_6BPC;
> break;
> @@ -7518,9 +7519,9 @@ static void i9xx_set_pipeconf(struct intel_crtc
> *intel_crtc)
> }
> }
>
> - if
[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor and Add helper function for combophy/tc ports
== Series Details == Series: Refactor and Add helper function for combophy/tc ports URL : https://patchwork.freedesktop.org/series/50484/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4919 -> Patchwork_10341 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10341 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10341, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50484/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10341: === IGT changes === Warnings igt@pm_rpm@module-reload: fi-hsw-4770r: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10341 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@cs-compute: fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094) igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@drv_module_reload@basic-reload: fi-glk-j4005: NOTRUN -> DMESG-WARN (fdo#106248, fdo#106725) igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107425, fdo#107924) igt@gem_exec_suspend@basic-s3: fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: NOTRUN -> DMESG-WARN (fdo#106000) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: NOTRUN -> FAIL (fdo#100368) igt@kms_flip@basic-plain-flip: fi-glk-j4005: NOTRUN -> DMESG-WARN (fdo#106097) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: NOTRUN -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: NOTRUN -> FAIL (fdo#103191, fdo#107362) igt@pm_rpm@module-reload: fi-glk-j4005: NOTRUN -> DMESG-WARN (fdo#107726) Possible fixes igt@gem_exec_suspend@basic-s3: fi-byt-clapper: INCOMPLETE (fdo#102657) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094 == Participating hosts (49 -> 45) == Additional (1): fi-glk-j4005 Missing(5): fi-ctg-p8600 fi-bsw-cyan fi-byt-squawks fi-icl-u2 fi-hsw-4200u == Build changes == * Linux: CI_DRM_4919 -> Patchwork_10341 CI_DRM_4919: e489eb0296673790264b25266ef45aae7d1ab566 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10341: f57caa7775e7b812ebab31aba3d1608bea229222 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f57caa7775e7 drm/i915/icl: Fix DDI/TC port clk_off bits 4eca1f772c36 drm/i915/icl: Introduce new macros to get combophy registers 7b2d6f208091 drm/i915/icl: Combine all port/combophy macros at one place c62ea17882cf drm/i915/icl: Refactor icl pll functions ae94362d7d98 drm/i915/icl: Use helper functions to classify the ports ff20ff437676 drm/i915/icl: Refactor get_ddi_pll using helper func 576a046de6ca drm/i915/icl: use combophy/TC helper functions during display detection a9fc7d4482e1 drm/i915/icl: create function to identify combophy port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10341/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH xf86-video-intel v1] sna: Added AYUV format support for textured and sprite video adapters.
On Wed, Oct 03, 2018 at 01:34:47PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-10-03 13:28:30)
> > On Wed, Oct 03, 2018 at 12:29:53PM +0100, Chris Wilson wrote:
> > > Quoting Stanislav Lisovskiy (2018-10-02 10:38:53)
> > > > diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h
> > > > index 6669af9d..ef88d1f9 100644
> > > > --- a/src/sna/sna_render.h
> > > > +++ b/src/sna/sna_render.h
> > > > @@ -139,20 +139,25 @@ struct sna_composite_op {
> > > >
> > > > struct {
> > > > uint32_t flags;
> > > > + uint8_t wm_kernel;
> > > > } gen6;
> > > >
> > > > struct {
> > > > uint32_t flags;
> > > > + uint8_t wm_kernel;
> > > > } gen7;
> > > >
> > > > struct {
> > > > uint32_t flags;
> > > > + uint8_t wm_kernel;
> > > > } gen8;
> > > >
> > > > struct {
> > > > uint32_t flags;
> > > > + uint8_t wm_kernel;
> > > > } gen9;
> > > > } u;
> > > > + unsigned long gen9_kernel;
> > >
> > > Do you want to try again without the surplus changes? Maybe ask Ville
> > > for his patches to base your work on?
> >
> > Unfortunaltely I still haven't managed to figure out why chrome
> > becomes a bit hangy on my ivb when I start to emit
> > 3DSTATE_CONSTANT_* in the ddx.
> >
> > The error state is somewhat peculiar BTW. It always hangs at the
> > start of a batch like so:
> >
> > ACTHD: 0x 00efa014
> >
> > batch (rcs0 (submitted by chrome [23031], ctx 2 [5], score 0)) at
> > 0x_00efa000
> > 0x00efa000: 0x7a03: PIPE_CONTROL
> > 0x00efa004: 0x00105021:qword write, cs stall, render target cache
> > flush, DC flush, depth cache flush,
> > 0x00efa008: 0x:destination address
> > 0x00efa00c: 0x:immediate dword low
> > 0x00efa010: 0x:immediate dword high
> > 0x00efa014: 0x61010008: STATE_BASE_ADDRESS
> > 0x00efa018: 0x0111:general state base address 0x0110
> > 0x00efa01c: 0x1001:surface state base address 0x1000
> > 0x00efa020: 0x1001:dynamic state base address 0x1000
> > 0x00efa024: 0x0001:indirect state base address 0x
> > 0x00efa028: 0x5001:instruction state base address 0x5000
> > 0x00efa02c: 0x0001:general state upper bound disabled
> > 0x00efa030: 0xf001:dynamic state upper bound 0xf000
> > 0x00efa034: 0x0001:indirect state upper bound disabled
> > 0x00efa038: 0x0001:instruction state upper bound disabled
> > 0x00efa03c: 0x7a03: PIPE_CONTROL
> > 0x00efa040: 0x0c04:no write, instruction cache invalidate,
> > texture cache invalidate, state cache invalida>
> > 0x00efa044: 0x:destination address
> > 0x00efa048: 0x:immediate dword low
> > 0x00efa04c: 0x:immediate dword high
> >
> > No idea why there's an end of pipe flush as the first thing in the batch,
> > and no idea how that could possibly hang due to stuff that was done in
> > another batch/context.
>
> Yeah, that is suspect. :|
>
> Waitasec qword write to 0? That seems fishy.
Yeah that one looked a bit odd to me as well, however looks like there
is something there:
Active (rcs0) [18]:
_0308500020480 3f 00 00 dirty LLC
_ 4096 3e 02 00 dirty LLC
Full error state attached, in case you're curious about other details.
--
Ville Syrjälä
Intel
GPU HANG: ecode 7:0:0x85fc, in chrome [23031], reason: hang on rcs0,
action: reset
Kernel: 4.18.0+
Time: 1538323109 s 571333 us
Boottime: 1207910 s 429320 us
Uptime: 7617 s 917098 us
Epoch: 4524289216 jiffies (300 HZ)
Capture: 4524291008 jiffies; 26767 ms ago, 5974 ms after epoch
Active process (on ring rcs0): chrome [23031], score 0
Reset count: 3
Suspend count: 27
Platform: IVYBRIDGE
PCI ID: 0x0166
PCI Revision: 0x09
PCI Subsystem: 17aa:21f9
IOMMU enabled?: -1
GT awake: yes
RPM wakelock: yes
PM suspended: no
EIR: 0x
IER: 0xfc000421
GTIER[0]: 0x00401021
PGTBL_ER: 0x
FORCEWAKE: 0x00010001
DERRMR: 0x
CCID: 0x7fff410d
Missed interrupts: 0x
fence[0] = 216c009020eb003
fence[1] =
fence[2] = 28f9009027f6003
fence[3] =
fence[4] =
fence[5] = 20ea00901fe7003
fence[6] = 1fe600901f65003
fence[7] =
fence[8] =
fence[9] = 1e6006f00f9d001
fence[10] =
fence[11] =
fence[12] =
fence[13] = 23f600902375003
fence[14] = 22700090216d003
fence[15] =
fence[16] =
fence[17] = 1f6400901e61003
fence[18] =
fence[19] = 22f200902271003
fence[20] =
fence[21] = f7f00900efe003
fence[22] =
[Intel-gfx] [PATCH 07/13] drm/i915: Make ironlake_pch_transcoder_set_timings take crtc_state
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 36a8d5fb8881..57c81e8e44be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4599,12 +4599,12 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
desired_divisor << auxdiv);
}
-static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
+static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state
*crtc_state,
enum pipe pch_transcoder)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
I915_READ(HTOTAL(cpu_transcoder)));
@@ -4753,7 +4753,7 @@ static void ironlake_pch_enable(const struct
intel_atomic_state *state,
/* set transcoder timing, panel must allow it */
assert_panel_unlocked(dev_priv, pipe);
- ironlake_pch_transcoder_set_timings(crtc, pipe);
+ ironlake_pch_transcoder_set_timings(crtc_state, pipe);
intel_fdi_normal_train(crtc);
@@ -4800,7 +4800,7 @@ static void lpt_pch_enable(const struct
intel_atomic_state *state,
lpt_program_iclkip(crtc);
/* Set transcoder timing. */
- ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
+ ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
--
2.19.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/13] drm/i915: Get rid of crtc->config in chv_data_lane_soft_reset
Fixing chv_set_phy_signal_level() still requires too many levels of
indirection to pass crtc_state along.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_dpio_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 00b3ab656b06..3c7f10d17658 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -748,7 +748,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
- if (crtc->config->lane_count > 2) {
+ if (crtc_state->lane_count > 2) {
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
if (reset)
val &= ~(DPIO_PCS_TX_LANE2_RESET |
DPIO_PCS_TX_LANE1_RESET);
@@ -765,7 +765,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
val |= DPIO_PCS_CLK_SOFT_RESET;
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
- if (crtc->config->lane_count > 2) {
+ if (crtc_state->lane_count > 2) {
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
if (reset)
--
2.19.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/13] drm/i915: Use crtc->state in intel_fbdev_init_bios
fbdev init shouldn't race with userspace since it's called from
intel_modeset_init, so it's safe to dereference crtc->state and
assume nothing changed yet.
At least not more harmful than crtc->config.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_fbdev.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index f99332972b7a..2480c7d6edee 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -593,7 +593,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
* pipe. Note we need to use the selected fb's pitch and bpp
* rather than the current pipe's, since they differ.
*/
- cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay;
+ cur_size = crtc->state->adjusted_mode.crtc_hdisplay;
cur_size = cur_size * fb->base.format->cpp[0];
if (fb->base.pitches[0] < cur_size) {
DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs
%d)\n",
@@ -603,13 +603,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
break;
}
- cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
+ cur_size = crtc->state->adjusted_mode.crtc_vdisplay;
cur_size = intel_fb_align_height(>base, 0, cur_size);
cur_size *= fb->base.pitches[0];
DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
pipe_name(intel_crtc->pipe),
-
intel_crtc->config->base.adjusted_mode.crtc_hdisplay,
-
intel_crtc->config->base.adjusted_mode.crtc_vdisplay,
+ crtc->state->adjusted_mode.crtc_hdisplay,
+ crtc->state->adjusted_mode.crtc_vdisplay,
fb->base.format->cpp[0] * 8,
cur_size);
--
2.19.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/13] drm/i915: Get rid of crtc->config dereference in intel_dp_retrain_link
Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 15a981ef5966..d9cc52b2ba79 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4417,7 +4417,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, /* Suppress underruns caused by re-training */ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); - if (crtc->config->has_pch_encoder) + if (crtc_state->has_pch_encoder) intel_set_pch_fifo_underrun_reporting(dev_priv, intel_crtc_pch_transcoder(crtc), false); @@ -4428,7 +4428,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_wait_for_vblank(dev_priv, crtc->pipe); intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); - if (crtc->config->has_pch_encoder) + if (crtc_state->has_pch_encoder) intel_set_pch_fifo_underrun_reporting(dev_priv, intel_crtc_pch_transcoder(crtc), true); -- 2.19.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/13] drm/i915: Make pll functions take crtc_state
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 56784ae26369..36a8d5fb8881 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1565,14 +1565,15 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
}
}
-static void i9xx_disable_pll(struct intel_crtc *crtc)
+static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
/* Disable DVO 2x clock on both PLLs if necessary */
if (IS_I830(dev_priv) &&
- intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO) &&
!intel_num_dvo_pipes(dev_priv)) {
I915_WRITE(DPLL(PIPE_B),
I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
@@ -4323,10 +4324,10 @@ static void ivb_manual_fdi_link_train(struct intel_crtc
*crtc,
DRM_DEBUG_KMS("FDI train done.\n");
}
-static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
+static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = intel_crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
int pipe = intel_crtc->pipe;
i915_reg_t reg;
u32 temp;
@@ -4335,7 +4336,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
- temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
+ temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
@@ -5614,7 +5615,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
- ironlake_fdi_pll_enable(intel_crtc);
+ ironlake_fdi_pll_enable(pipe_config);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
@@ -6211,7 +6212,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state,
else if (IS_VALLEYVIEW(dev_priv))
vlv_disable_pll(dev_priv, pipe);
else
- i9xx_disable_pll(intel_crtc);
+ i9xx_disable_pll(old_crtc_state);
}
intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
--
2.19.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/13] drm/i915: Get rid of intel_crtc->config in crtc_enable/disable functions
These functions already have a pointer to the correct state,
so use it instead of crtc->config.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 60 ++--
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 22f556b824f9..01ad6bd3b7de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5594,15 +5594,15 @@ static void ironlake_crtc_enable(struct
intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
intel_prepare_shared_dpll(pipe_config);
- if (intel_crtc_has_dp_encoder(intel_crtc->config))
+ if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(pipe_config);
intel_set_pipe_src_size(pipe_config);
- if (intel_crtc->config->has_pch_encoder) {
+ if (pipe_config->has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
-_crtc->config->fdi_m_n, NULL);
+_config->fdi_m_n, NULL);
}
ironlake_set_pipeconf(pipe_config);
@@ -5611,7 +5611,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_encoders_pre_enable(crtc, pipe_config, old_state);
- if (intel_crtc->config->has_pch_encoder) {
+ if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
@@ -5630,10 +5630,10 @@ static void ironlake_crtc_enable(struct
intel_crtc_state *pipe_config,
intel_color_load_luts(_config->base);
if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(old_intel_state,
intel_crtc->config);
+ dev_priv->display.initial_watermarks(old_intel_state,
pipe_config);
intel_enable_pipe(pipe_config);
- if (intel_crtc->config->has_pch_encoder)
+ if (pipe_config->has_pch_encoder)
ironlake_pch_enable(old_intel_state, pipe_config);
assert_vblank_disabled(crtc);
@@ -5650,7 +5650,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
* some interlaced HDMI modes. Let's do the double wait always
* in case there are more corner cases we don't know about.
*/
- if (intel_crtc->config->has_pch_encoder) {
+ if (pipe_config->has_pch_encoder) {
intel_wait_for_vblank(dev_priv, pipe);
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -5699,7 +5699,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe, hsw_workaround_pipe;
- enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
bool psl_clkgate_wa;
@@ -5718,7 +5718,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_encoders_pre_enable(crtc, pipe_config, old_state);
- if (intel_crtc_has_dp_encoder(intel_crtc->config))
+ if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(intel_crtc, M1_N1);
if (!transcoder_is_dsi(cpu_transcoder))
@@ -5729,12 +5729,12 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
if (cpu_transcoder != TRANSCODER_EDP &&
!transcoder_is_dsi(cpu_transcoder)) {
I915_WRITE(PIPE_MULT(cpu_transcoder),
- intel_crtc->config->pixel_multiplier - 1);
+ pipe_config->pixel_multiplier - 1);
}
- if (intel_crtc->config->has_pch_encoder) {
+ if (pipe_config->has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
-_crtc->config->fdi_m_n, NULL);
+_config->fdi_m_n, NULL);
}
if (!transcoder_is_dsi(cpu_transcoder))
@@ -5748,7 +5748,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
-intel_crtc->config->pch_pfit.enabled;
+pipe_config->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
@@ -5788,10 +5788,10 @@ static void haswell_crtc_enable(struct
[Intel-gfx] [PATCH 05/13] drm/i915: Make skl_detach_scalers take crtc_state
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 91574abafb65..56784ae26369 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3502,13 +3502,13 @@ static void skl_detach_scaler(struct intel_crtc
*intel_crtc, int id)
/*
* This function detaches (aka. unbinds) unused scalers in hardware
*/
-static void skl_detach_scalers(struct intel_crtc *intel_crtc)
+static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc_scaler_state *scaler_state;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ const struct intel_crtc_scaler_state *scaler_state =
+ _state->scaler_state;
int i;
- scaler_state = _crtc->config->scaler_state;
-
/* loop through and disable scalers that aren't in use */
for (i = 0; i < intel_crtc->num_scalers; i++) {
if (!scaler_state->scalers[i].in_use)
@@ -3916,7 +3916,7 @@ static void intel_update_pipe_config(const struct
intel_crtc_state *old_crtc_sta
/* on skylake this is done by detaching scalers */
if (INTEL_GEN(dev_priv) >= 9) {
- skl_detach_scalers(crtc);
+ skl_detach_scalers(new_crtc_state);
if (new_crtc_state->pch_pfit.enabled)
skylake_pfit_enable(new_crtc_state);
@@ -13335,7 +13335,7 @@ static void intel_begin_crtc_commit(struct drm_crtc
*crtc,
if (intel_cstate->update_pipe)
intel_update_pipe_config(old_intel_cstate, intel_cstate);
else if (INTEL_GEN(dev_priv) >= 9)
- skl_detach_scalers(intel_crtc);
+ skl_detach_scalers(intel_cstate);
out:
if (dev_priv->display.atomic_update_watermarks)
--
2.19.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/13] drm/i915: Make panel fitter functions take state
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 91 ++--
1 file changed, 45 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 264feed76c08..701caab4e382 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -158,9 +158,9 @@ static void intel_begin_crtc_commit(struct drm_crtc *,
struct drm_crtc_state *);
static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state
*);
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
-static void skylake_pfit_enable(struct intel_crtc *crtc);
-static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
-static void ironlake_pfit_enable(struct intel_crtc *crtc);
+static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
+static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state);
+static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
@@ -3919,12 +3919,12 @@ static void intel_update_pipe_config(const struct
intel_crtc_state *old_crtc_sta
skl_detach_scalers(crtc);
if (new_crtc_state->pch_pfit.enabled)
- skylake_pfit_enable(crtc);
+ skylake_pfit_enable(new_crtc_state);
} else if (HAS_PCH_SPLIT(dev_priv)) {
if (new_crtc_state->pch_pfit.enabled)
- ironlake_pfit_enable(crtc);
+ ironlake_pfit_enable(new_crtc_state);
else if (old_crtc_state->pch_pfit.enabled)
- ironlake_pfit_disable(crtc, true);
+ ironlake_pfit_disable(old_crtc_state);
}
}
@@ -5041,19 +5041,19 @@ static void skylake_scaler_disable(struct intel_crtc
*crtc)
skl_detach_scaler(crtc, i);
}
-static void skylake_pfit_enable(struct intel_crtc *crtc)
+static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe = crtc->pipe;
- struct intel_crtc_scaler_state *scaler_state =
- >config->scaler_state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ const struct intel_crtc_scaler_state *scaler_state =
+ _state->scaler_state;
- if (crtc->config->pch_pfit.enabled) {
+ if (crtc_state->pch_pfit.enabled) {
u16 uv_rgb_hphase, uv_rgb_vphase;
int id;
- if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
+ if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
return;
uv_rgb_hphase = skl_scaler_calc_phase(1, false);
@@ -5066,18 +5066,18 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
- I915_WRITE(SKL_PS_WIN_POS(pipe, id),
crtc->config->pch_pfit.pos);
- I915_WRITE(SKL_PS_WIN_SZ(pipe, id),
crtc->config->pch_pfit.size);
+ I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
+ I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
}
}
-static void ironlake_pfit_enable(struct intel_crtc *crtc)
+static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int pipe = crtc->pipe;
- if (crtc->config->pch_pfit.enabled) {
+ if (crtc_state->pch_pfit.enabled) {
/* Force use of hard-coded filter coefficients
* as some pre-programmed values are broken,
* e.g. x201.
@@ -5087,8 +5087,8 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
PF_PIPE_SEL_IVB(pipe));
else
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
- I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
+
[Intel-gfx] [PATCH 01/13] drm/i915: Remove dereferences of crtc->config in set_pipeconf/misc functions.
One more user of crtc->config down. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 72 ++--
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 36434c5359b1..264feed76c08 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -141,15 +141,15 @@ static void ironlake_pch_clock_get(struct intel_crtc
*crtc,
static int intel_framebuffer_init(struct intel_framebuffer *ifb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd);
-static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
+static void i9xx_set_pipeconf(struct intel_crtc_state *crtc_state);
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n,
struct intel_link_m_n *m2_n2);
-static void ironlake_set_pipeconf(struct drm_crtc *crtc);
-static void haswell_set_pipeconf(struct drm_crtc *crtc);
-static void haswell_set_pipemisc(struct drm_crtc *crtc);
+static void ironlake_set_pipeconf(struct intel_crtc_state *crtc_state);
+static void haswell_set_pipeconf(struct intel_crtc_state *crtc_state);
+static void haswell_set_pipemisc(struct intel_crtc_state *crtc_state);
static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
@@ -5604,7 +5604,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
_crtc->config->fdi_m_n, NULL);
}
- ironlake_set_pipeconf(crtc);
+ ironlake_set_pipeconf(pipe_config);
intel_crtc->active = true;
@@ -5737,9 +5737,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
}
if (!transcoder_is_dsi(cpu_transcoder))
- haswell_set_pipeconf(crtc);
+ haswell_set_pipeconf(pipe_config);
- haswell_set_pipemisc(crtc);
+ haswell_set_pipemisc(pipe_config);
intel_color_set_csc(_config->base);
@@ -6073,7 +6073,7 @@ static void valleyview_crtc_enable(struct
intel_crtc_state *pipe_config,
I915_WRITE(CHV_CANVAS(pipe), 0);
}
- i9xx_set_pipeconf(intel_crtc);
+ i9xx_set_pipeconf(pipe_config);
intel_color_set_csc(_config->base);
@@ -6138,7 +6138,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_set_pipe_timings(intel_crtc);
intel_set_pipe_src_size(intel_crtc);
- i9xx_set_pipeconf(intel_crtc);
+ i9xx_set_pipeconf(pipe_config);
intel_crtc->active = true;
@@ -7480,8 +7480,9 @@ void intel_mode_from_pipe_config(struct drm_display_mode
*mode,
drm_mode_set_name(mode);
}
-static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
+static void i9xx_set_pipeconf(struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
uint32_t pipeconf;
@@ -7491,18 +7492,18 @@ static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc)
if (IS_I830(dev_priv))
pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) &
PIPECONF_ENABLE;
- if (intel_crtc->config->double_wide)
+ if (crtc_state->double_wide)
pipeconf |= PIPECONF_DOUBLE_WIDE;
/* only g4x and later have fancy bpc/dither controls */
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) {
/* Bspec claims that we can't use dithering for 30bpp pipes. */
- if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp
!= 30)
+ if (crtc_state->dither && crtc_state->pipe_bpp != 30)
pipeconf |= PIPECONF_DITHER_EN |
PIPECONF_DITHER_TYPE_SP;
- switch (intel_crtc->config->pipe_bpp) {
+ switch (crtc_state->pipe_bpp) {
case 18:
pipeconf |= PIPECONF_6BPC;
break;
@@ -7518,9 +7519,9 @@ static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc)
}
}
- if (intel_crtc->config->base.adjusted_mode.flags &
DRM_MODE_FLAG_INTERLACE) {
+ if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
if (INTEL_GEN(dev_priv) < 4 ||
- intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
[Intel-gfx] [PATCH 09/13] drm/i915: Get rid of crtc->config from icl_pll_to_ddi_pll_sel
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_ddi.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b6594948b617..9e82281b4fdf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1060,10 +1060,10 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct
intel_shared_dpll *pll)
}
static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
- const struct intel_shared_dpll *pll)
+ const struct intel_crtc_state
*crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- int clock = crtc->config->port_clock;
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ int clock = crtc_state->port_clock;
const enum intel_dpll_id id = pll->info->id;
switch (id) {
@@ -2798,11 +2798,12 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
}
static void intel_ddi_clk_select(struct intel_encoder *encoder,
-const struct intel_shared_dpll *pll)
+const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
uint32_t val;
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
if (WARN_ON(!pll))
return;
@@ -2812,7 +2813,7 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
if (IS_ICELAKE(dev_priv)) {
if (port >= PORT_C)
I915_WRITE(DDI_CLK_SEL(port),
- icl_pll_to_ddi_pll_sel(encoder, pll));
+ icl_pll_to_ddi_pll_sel(encoder, crtc_state));
} else if (IS_CANNONLAKE(dev_priv)) {
/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
val = I915_READ(DPCLKA_CFGCR0);
@@ -2886,7 +2887,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_edp_panel_on(intel_dp);
- intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
+ intel_ddi_clk_select(encoder, crtc_state);
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
@@ -2928,7 +2929,7 @@ static void intel_ddi_pre_enable_hdmi(struct
intel_encoder *encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(>base);
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
- intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
+ intel_ddi_clk_select(encoder, crtc_state);
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
--
2.19.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/13] drm/i915: Use crtc_state in ironlake_enable_pch_transcoder
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ca5e4d72d476..91574abafb65 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1666,16 +1666,16 @@ void vlv_wait_port_ready(struct drm_i915_private
*dev_priv,
I915_READ(dpll_reg) & port_mask, expected_mask);
}
-static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe)
+static void ironlake_enable_pch_transcoder(const struct intel_crtc_state
*crtc_state)
{
- struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
- pipe);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+ enum pipe pipe = intel_crtc->pipe;
i915_reg_t reg;
uint32_t val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
+ assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, pipe);
@@ -1701,7 +1701,7 @@ static void ironlake_enable_pch_transcoder(struct
drm_i915_private *dev_priv,
* here for both 8bpc and 12bpc.
*/
val &= ~PIPECONF_BPC_MASK;
- if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
val |= PIPECONF_8BPC;
else
val |= pipeconf_val & PIPECONF_BPC_MASK;
@@ -1710,7 +1710,7 @@ static void ironlake_enable_pch_transcoder(struct
drm_i915_private *dev_priv,
val &= ~TRANS_INTERLACE_MASK;
if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
if (HAS_PCH_IBX(dev_priv) &&
- intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
val |= TRANS_LEGACY_INTERLACED_ILK;
else
val |= TRANS_INTERLACED;
@@ -4784,7 +4784,7 @@ static void ironlake_pch_enable(const struct
intel_atomic_state *state,
I915_WRITE(reg, temp);
}
- ironlake_enable_pch_transcoder(dev_priv, pipe);
+ ironlake_enable_pch_transcoder(crtc_state);
}
static void lpt_pch_enable(const struct intel_atomic_state *state,
--
2.19.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/13] drm/i915: Make intel_set_pipe_timings/src_size take a pointer to crtc_state
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 41 ++--
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 701caab4e382..ca5e4d72d476 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -142,8 +142,8 @@ static int intel_framebuffer_init(struct intel_framebuffer
*ifb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd);
static void i9xx_set_pipeconf(struct intel_crtc_state *crtc_state);
-static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
-static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
+static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
+static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n,
struct intel_link_m_n *m2_n2);
@@ -5596,8 +5596,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
if (intel_crtc_has_dp_encoder(intel_crtc->config))
intel_dp_set_m_n(intel_crtc, M1_N1);
- intel_set_pipe_timings(intel_crtc);
- intel_set_pipe_src_size(intel_crtc);
+ intel_set_pipe_timings(pipe_config);
+ intel_set_pipe_src_size(pipe_config);
if (intel_crtc->config->has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
@@ -5721,9 +5721,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_dp_set_m_n(intel_crtc, M1_N1);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_pipe_timings(intel_crtc);
+ intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(intel_crtc);
+ intel_set_pipe_src_size(pipe_config);
if (cpu_transcoder != TRANSCODER_EDP &&
!transcoder_is_dsi(cpu_transcoder)) {
@@ -6062,12 +6062,10 @@ static void valleyview_crtc_enable(struct
intel_crtc_state *pipe_config,
if (intel_crtc_has_dp_encoder(intel_crtc->config))
intel_dp_set_m_n(intel_crtc, M1_N1);
- intel_set_pipe_timings(intel_crtc);
- intel_set_pipe_src_size(intel_crtc);
+ intel_set_pipe_timings(pipe_config);
+ intel_set_pipe_src_size(pipe_config);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
- struct drm_i915_private *dev_priv = to_i915(dev);
-
I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
I915_WRITE(CHV_CANVAS(pipe), 0);
}
@@ -6134,8 +6132,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config,
if (intel_crtc_has_dp_encoder(intel_crtc->config))
intel_dp_set_m_n(intel_crtc, M1_N1);
- intel_set_pipe_timings(intel_crtc);
- intel_set_pipe_src_size(intel_crtc);
+ intel_set_pipe_timings(pipe_config);
+ intel_set_pipe_src_size(pipe_config);
i9xx_set_pipeconf(pipe_config);
@@ -7331,12 +7329,13 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
crtc_state->dpll_hw_state.dpll = dpll;
}
-static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
+static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
enum pipe pipe = intel_crtc->pipe;
- enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
- const struct drm_display_mode *adjusted_mode =
_crtc->config->base.adjusted_mode;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ const struct drm_display_mode *adjusted_mode =
_state->base.adjusted_mode;
uint32_t crtc_vtotal, crtc_vblank_end;
int vsyncshift = 0;
@@ -7350,7 +7349,7 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc)
crtc_vtotal -= 1;
crtc_vblank_end -= 1;
- if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
else
vsyncshift = adjusted_mode->crtc_hsync_start -
@@ -7392,18 +7391,18 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc)
}
-static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
+static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = intel_crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *intel_crtc =
[Intel-gfx] [PATCH 08/13] drm/i915: Make shared dpll functions take crtc_state
Do not rely on crtc->config any more. Remove the assertion from
ibx_pch_dpll_disable, because we the dpll state tracking should
already handle this case correctly.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 14 ++--
drivers/gpu/drm/i915/intel_dpll_mgr.c | 31 +++
drivers/gpu/drm/i915/intel_dpll_mgr.h | 6 +++---
3 files changed, 22 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 57c81e8e44be..22f556b824f9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4749,7 +4749,7 @@ static void ironlake_pch_enable(const struct
intel_atomic_state *state,
* Note that enable_shared_dpll tries to do the right thing, but
* get_shared_dpll unconditionally resets the pll - we need that to have
* the right LVDS enable sequence. */
- intel_enable_shared_dpll(crtc);
+ intel_enable_shared_dpll(crtc_state);
/* set transcoder timing, panel must allow it */
assert_panel_unlocked(dev_priv, pipe);
@@ -5591,8 +5591,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- if (intel_crtc->config->has_pch_encoder)
- intel_prepare_shared_dpll(intel_crtc);
+ if (pipe_config->has_pch_encoder)
+ intel_prepare_shared_dpll(pipe_config);
if (intel_crtc_has_dp_encoder(intel_crtc->config))
intel_dp_set_m_n(intel_crtc, M1_N1);
@@ -5710,8 +5710,8 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
- if (intel_crtc->config->shared_dpll)
- intel_enable_shared_dpll(intel_crtc);
+ if (pipe_config->shared_dpll)
+ intel_enable_shared_dpll(pipe_config);
if (INTEL_GEN(dev_priv) >= 11)
icl_map_plls_to_ports(crtc, pipe_config, old_state);
@@ -6286,7 +6286,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc,
intel_fbc_disable(intel_crtc);
intel_update_watermarks(intel_crtc);
- intel_disable_shared_dpll(intel_crtc);
+ intel_disable_shared_dpll(crtc_state);
domains = intel_crtc->enabled_power_domains;
for_each_power_domain(domain, domains)
@@ -12735,7 +12735,7 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
dev_priv->display.crtc_disable(old_intel_crtc_state,
state);
intel_crtc->active = false;
intel_fbc_disable(intel_crtc);
- intel_disable_shared_dpll(intel_crtc);
+ intel_disable_shared_dpll(old_intel_crtc_state);
/*
* Underruns don't always raise
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e6cac9225536..54662c974c0b 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -131,13 +131,13 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
* This calls the PLL's prepare hook if it has one and if the PLL is not
* already enabled. The prepare hook is platform specific.
*/
-void intel_prepare_shared_dpll(struct intel_crtc *crtc)
+void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_shared_dpll *pll = crtc->config->shared_dpll;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- if (WARN_ON(pll == NULL))
+ if (!WARN_ON(!pll))
return;
mutex_lock(_priv->dpll_lock);
@@ -158,11 +158,11 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
*
* Enable the shared DPLL used by @crtc.
*/
-void intel_enable_shared_dpll(struct intel_crtc *crtc)
+void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_shared_dpll *pll = crtc->config->shared_dpll;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int crtc_mask = drm_crtc_mask(>base);
unsigned int old_mask;
@@ -203,10 +203,11 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
*
* Disable the shared DPLL used by @crtc.
*/
-void
[Intel-gfx] [PATCH 00/13] drm/i915: First cleanup pass to get rid of more crtc->config users.
There are a lot of places where we use crtc->config, but shouldn't and easy ways around it are available. In many cases, either the function itself, or the calling function has a pointer to the correct state, so use it when available. This is not a full cleanup yet, want to send it in parts. :) Maarten Lankhorst (13): drm/i915: Remove dereferences of crtc->config in set_pipeconf/misc functions. drm/i915: Make panel fitter functions take state drm/i915: Make intel_set_pipe_timings/src_size take a pointer to crtc_state drm/i915: Use crtc_state in ironlake_enable_pch_transcoder drm/i915: Make skl_detach_scalers take crtc_state drm/i915: Make pll functions take crtc_state drm/i915: Make ironlake_pch_transcoder_set_timings take crtc_state drm/i915: Make shared dpll functions take crtc_state drm/i915: Get rid of crtc->config from icl_pll_to_ddi_pll_sel drm/i915: Use crtc->state in intel_fbdev_init_bios drm/i915: Get rid of crtc->config dereference in intel_dp_retrain_link drm/i915: Get rid of crtc->config in chv_data_lane_soft_reset drm/i915: Get rid of intel_crtc->config in crtc_enable/disable functions drivers/gpu/drm/i915/intel_ddi.c | 15 +- drivers/gpu/drm/i915/intel_display.c | 335 +- drivers/gpu/drm/i915/intel_dp.c | 4 +- drivers/gpu/drm/i915/intel_dpio_phy.c | 4 +- drivers/gpu/drm/i915/intel_dpll_mgr.c | 31 +-- drivers/gpu/drm/i915/intel_dpll_mgr.h | 6 +- drivers/gpu/drm/i915/intel_fbdev.c| 8 +- 7 files changed, 198 insertions(+), 205 deletions(-) -- 2.19.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Flush the CS events before unpinning
== Series Details == Series: drm/i915/execlists: Flush the CS events before unpinning URL : https://patchwork.freedesktop.org/series/50494/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4919 -> Patchwork_10340 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50494/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10340 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@cs-compute: fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094) igt@amdgpu/amd_cs_nop@fork-gfx0: fi-kbl-8809g: NOTRUN -> DMESG-WARN (fdo#107762) +1 igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@drv_module_reload@basic-reload: fi-glk-j4005: NOTRUN -> DMESG-WARN (fdo#106725, fdo#106248) igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: NOTRUN -> FAIL (fdo#100368) fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773) igt@pm_rpm@module-reload: fi-glk-j4005: NOTRUN -> DMESG-WARN (fdo#107726) Possible fixes igt@gem_exec_suspend@basic-s3: fi-byt-clapper: INCOMPLETE (fdo#102657) -> PASS igt@gem_exec_suspend@basic-s4-devices: fi-bdw-samus: INCOMPLETE (fdo#107773) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 fdo#107762 https://bugs.freedesktop.org/show_bug.cgi?id=107762 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094 == Participating hosts (49 -> 44) == Additional (1): fi-glk-j4005 Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_4919 -> Patchwork_10340 CI_DRM_4919: e489eb0296673790264b25266ef45aae7d1ab566 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10340: f8924caa9adab083e6fd9d57c94b65c4651f453d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f8924caa9ada drm/i915/execlists: Flush the CS events before unpinning == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10340/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH xf86-video-intel v1] sna: Added AYUV format support for textured and sprite video adapters.
On Wed, 2018-10-03 at 12:29 +0100, Chris Wilson wrote:
> Quoting Stanislav Lisovskiy (2018-10-02 10:38:53)
> > diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h
> > index 6669af9d..ef88d1f9 100644
> > --- a/src/sna/sna_render.h
> > +++ b/src/sna/sna_render.h
> > @@ -139,20 +139,25 @@ struct sna_composite_op {
> >
> > struct {
> > uint32_t flags;
> > + uint8_t wm_kernel;
> > } gen6;
> >
> > struct {
> > uint32_t flags;
> > + uint8_t wm_kernel;
> > } gen7;
> >
> > struct {
> > uint32_t flags;
> > + uint8_t wm_kernel;
> > } gen8;
> >
> > struct {
> > uint32_t flags;
> > + uint8_t wm_kernel;
> > } gen9;
> > } u;
> > + unsigned long gen9_kernel;
>
> Do you want to try again without the surplus changes? Maybe ask Ville
> for his patches to base your work on?
> -Chris
Yep, I took part of Ville's patch for the flags issue, required for
gen9+.
--
Best Regards,
Lisovskiy Stanislav
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