[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fia: FIA registers offset implementation.
== Series Details == Series: drm/i915/fia: FIA registers offset implementation. URL : https://patchwork.freedesktop.org/series/51566/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10596 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51566/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10596 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@pm_rpm@module-reload: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 == Participating hosts (46 -> 42) == Additional (1): fi-icl-u Missing(5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-u2 == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10596 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10596: 83ce394575f3bee8490b496aff48f6f469608860 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 83ce394575f3 drm/i915/fia: FIA registers offset implementation. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10596/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset implementation.
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573348b3..e2f5c3a95ad4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,15 @@ enum i915_power_well_id {
#define BXT_PORT_CL2CM_DW6(phy)_BXT_PHY((phy),
_PORT_CL2CM_DW6_BC)
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
+/* FIA Offsets */
+#define FIA_0 0x163000
+#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
+#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
+#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
+#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
+
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1_MMIO(0x1638C0)
+#define PORT_TX_DFLEXDPMLE1_MMIO(FIA_0 +
PORT_TX_DFLEXDPMLE1_OFFSET)
#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
#define DFLEXDPMLE1_DPMLETC(n, x)((x) << (4 * (n)))
@@ -10957,17 +10964,17 @@ enum skl_power_gate {
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
+#define PORT_TX_DFLEXDPSP _MMIO(FIA_0 +
PORT_TX_DFLEXDPSP_OFFSET)
#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
#define TC_LIVE_STATE_TC(tc_port)(1 << ((tc_port) * 8 + 5))
#define DP_LANE_ASSIGNMENT_SHIFT(tc_port)((tc_port) * 8)
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
-#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
+#define PORT_TX_DFLEXDPPMS _MMIO(FIA_0 +
PORT_TX_DFLEXDPPMS_OFFSET)
#define DP_PHY_MODE_STATUS_COMPLETED(tc_port)(1 << (tc_port))
-#define PORT_TX_DFLEXDPCSSS_MMIO(0x163894)
+#define PORT_TX_DFLEXDPCSSS_MMIO(FIA_0 +
PORT_TX_DFLEXDPCSSS_OFFSET)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
#endif /* _I915_REG_H_ */
--
2.17.1
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Forward Error Correction (rev3)
== Series Details == Series: Forward Error Correction (rev3) URL : https://patchwork.freedesktop.org/series/47848/ State : failure == Summary == Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_dp.c). error: could not build fake ancestor Patch failed at 0001 i915/dp/fec: Cache the FEC_CAPABLE DPCD register Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 2/7] drm/dp/fec: DRM helper for Forward Error Correction
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style changes (Gaurav)
- Use drm_dp_dpcd_readb instead of drm_dp_dpcd_read. (Jani)
v4:
- Avoid aux reads everytime, instead read cached
values of dpcd register (jani)
- Move helper to drm_dp_helper.h like other dsc
helpers.(Anusha)
v5: rebased. Change the helper parameter suitably.
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
include/drm/drm_dp_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 2649529d0d8f..b08f50b852f5 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1101,6 +1101,13 @@ drm_dp_dsc_sink_max_slice_width(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
DP_DSC_SLICE_WIDTH_MULTIPLIER;
}
+/* Forward Error Correction Support on DP 1.4 */
+static inline bool
+drm_dp_sink_supports_fec(const u8 fec_capable)
+{
+ return fec_capable & DP_FEC_CAPABLE;
+}
+
/*
* DisplayPort AUX channel
*/
--
2.17.1
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[Intel-gfx] [v3 5/7] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 14 ++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1de0a3917d7f..efbada95dc4e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2932,6 +2932,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
DP_DECOMPRESSION_EN);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4776ce6f2174..c446821c58b2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3057,6 +3057,20 @@ void intel_dp_sink_set_decompression_state(struct
intel_dp *intel_dp,
state == DP_DECOMPRESSION_EN ? "enable" :
"disable");
}
+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state,
+int state)
+{
+ int ret;
+
+ if (!crtc_state->can_fec)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION, state);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9dac242ead12..a15ecdb4a706 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1796,6 +1796,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int
mode);
void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state,
int state);
+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+const struct intel_crtc_state *crtc_state,
+int state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.17.1
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[Intel-gfx] [v3 6/7] i915/dp/fec: Configure the Forward Error Correction bits.
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 27 +++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e85f53cb9cdd..8b1753939299 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9134,6 +9134,7 @@ enum skl_power_gate {
#define _DP_TP_CTL_B 0x64140
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
#define DP_TP_CTL_ENABLE (1 << 31)
+#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
@@ -9152,6 +9153,7 @@ enum skl_power_gate {
#define _DP_TP_STATUS_A0x64044
#define _DP_TP_STATUS_B0x64144
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE(1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index efbada95dc4e..5badeaefb539 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2889,6 +2889,29 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
}
}
+void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ enum port port = intel_dig_port->base.port;
+ u32 val;
+
+ /* FEC support exists for DP 1.4 only */
+ if (!crtc_state->can_fec)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val |= DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ 1))
+ DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -2934,9 +2957,13 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
DP_DECOMPRESSION_EN);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY);
intel_dp_start_link_train(intel_dp);
+
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
+ /* Set FEC state after link training */
+ intel_dp_enable_fec_state(intel_dp, crtc_state);
+
icl_enable_phy_clock_gating(dig_port);
if (!is_mst)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a15ecdb4a706..405a44b3b3a8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1799,6 +1799,8 @@ void intel_dp_sink_set_decompression_state(struct
intel_dp *intel_dp,
void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
int state);
+void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.17.1
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[Intel-gfx] [v3 7/7] drm/i915/fec: Disable FEC state.
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 32
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5badeaefb539..1e16c9aa0e65 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2912,6 +2912,31 @@ void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
+void intel_dp_disable_fec_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ enum port port = intel_dig_port->base.port;
+ u32 val;
+ u8 dsc_en_state;
+
+ if (!crtc_state->can_fec)
+ return;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ drm_dp_dpcd_readb(_dp->aux, DP_DSC_ENABLE, _en_state);
+
+ if (!dsc_en_state) {
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+ }
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3052,7 +3077,11 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
static void intel_disable_ddi_buf(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(>base);
+ struct intel_dp *intel_dp = _port->dp;
+ struct intel_crtc_state *crtc_state;
enum port port = encoder->port;
+
bool wait = false;
u32 val;
@@ -3068,6 +3097,9 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder)
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
I915_WRITE(DP_TP_CTL(port), val);
+ /* Disable FEC in DP Sink */
+ intel_dp_disable_fec_state(intel_dp, crtc_state);
+
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 405a44b3b3a8..a2f4562dabe2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1801,6 +1801,8 @@ void intel_dp_sink_set_fec_ready(struct intel_dp
*intel_dp,
int state);
void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+void intel_dp_disable_fec_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.17.1
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[Intel-gfx] [v3 0/7] Forward Error Correction
With Display Compression, the bit error in the pixel stream can turn into a significant corruption on the screen. The DP1.4 adds FEC - Forward Error Correction scheme which uses Reed-Solomon parity/correction check generated by the source and used by the sink to detect and correct small numbers of bit errors in the compressed stream. v2: Avoid doing aux channel read eberytime we check for FEC support. Instead cache the value of the DPCD registers, similar to the DSC implementaion (Jani) v3: Add fec as a state to crtc. Move around the code. (Ville) This is rebased on top of Manasi's End-to-end DSC Implementation: https://patchwork.freedesktop.org/series/47514/ Anusha Srivatsa (7): i915/dp/fec: Cache the FEC_CAPABLE DPCD register drm/dp/fec: DRM helper for Forward Error Correction i915/dp/fec: Check for FEC Support i915/dp/fec: Add can_fec to the crtc state. drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION i915/dp/fec: Configure the Forward Error Correction bits. drm/i915/fec: Disable FEC state. drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ddi.c | 60 drivers/gpu/drm/i915/intel_dp.c | 58 -- drivers/gpu/drm/i915/intel_drv.h | 11 ++ include/drm/drm_dp_helper.h | 7 5 files changed, 136 insertions(+), 2 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 4/7] i915/dp/fec: Add can_fec to the crtc state.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 22 ++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cfcef9e4b5d9..4776ce6f2174 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2045,6 +2045,23 @@ intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp,
return false;
}
+static bool intel_dp_can_fec(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ if (INTEL_GEN(dev_priv) < 11 || intel_dp_is_edp(intel_dp))
+ return false;
+
+ /* On Gen 11, FEC is Supported Only for DP SST modes.
+* Let us start by enabling FEC for Compressed streams.
+*/
+ if (pipe_config->dsc_params.compression_enable)
+ return true;
+ else
+ return false;
+
+}
static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits)
@@ -2129,6 +2146,11 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_config->dsc_params.compressed_bpp,
pipe_config->dsc_params.slice_count);
+ /* For DP 1.4, Enable DSC if FEC can be configured */
+ pipe_config->can_fec = intel_dp_can_fec(intel_dp, pipe_config);
+ if (!pipe_config->can_fec)
+ return false;
+
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9a94c6544bf5..9dac242ead12 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -940,6 +940,9 @@ struct intel_crtc_state {
u8 slice_count;
} dsc_params;
struct drm_dsc_config dp_dsc_cfg;
+
+ /* Forward Error correction State */
+ bool can_fec;
};
struct intel_crtc {
--
2.17.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 3/7] i915/dp/fec: Check for FEC Support
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Check if the sink supports FEC using the helper.
v2: Mention External DP where ever FEC is mentioned
in the code.Check return status of dpcd reads. (Gaurav)
- Do regular mode check even if FEC is not supported. (manasi)
v3: Do not perform any dpcd writes in the atomic
check phase. (DK, Manasi)
v4: Use debug level logging for scenario where sink does
not support a feature. (DK)
v5: Correct commit message. rebase.
v6: pass single field instead of an array for helper
function. (manasi)
Cc: Gaurav K Singh
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Cc: Dhinakaran Pandiyan
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 16d1db7c9398..cfcef9e4b5d9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -680,7 +680,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
- } else {
+ } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
@@ -690,7 +690,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
mode->hdisplay);
- }
+ } else
+ DRM_DEBUG_KMS("Sink device does not Support FEC\n");
}
if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count))
||
@@ -2063,6 +2064,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp))
return false;
+ /* DSC not supported if external DP sink does not support FEC */
+ if (!intel_dp_is_edp(intel_dp) &&
+ !drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
+ DRM_DEBUG_KMS("Sink does not support Forward Error Correction,
disabling Display Compression\n");
+ return false;
+ }
+
/* DSC not supported for DSC sink BPC < 8 */
if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
--
2.17.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 1/7] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
Suggested-by: Jani Nikula
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 10 ++
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5a638503e36a..16d1db7c9398 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4198,9 +4198,13 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
*intel_dp)
/*
*Clear the cached register set to avoid using stale values
* for the sinks that do not support DSC.
+* Similarly, clear the cached FEC register.
*/
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+ /* Clear fec_capable to avoid using stale values */
+ intel_dp->fec_capable = 0;
+
/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@@ -4214,6 +4218,12 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
*intel_dp)
(int)sizeof(intel_dp->dsc_dpcd),
intel_dp->dsc_dpcd);
}
+ /* FEC is supported only on DP 1.4 */
+ if (!intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] >= 0x14) {
+ if (drm_dp_dpcd_readb(_dp->aux, DP_FEC_CAPABILITY,
+ _dp->fec_capable) < 0)
+ DRM_ERROR("Failed to read FEC DPCD register\n");
+ }
}
static bool
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 16bbc3768e02..9a94c6544bf5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1119,6 +1119,7 @@ struct intel_dp {
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+ u8 fec_capable;
/* source rates */
int num_source_rates;
const int *source_rates;
--
2.17.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG
== Series Details == Series: drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG URL : https://patchwork.freedesktop.org/series/51538/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10594 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51538/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10594 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload-inject: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725, fdo#106248, fdo#106000) igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_frontbuffer_tracking@basic: fi-glk-j4005: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@pm_rpm@module-reload: fi-skl-6600u: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 == Participating hosts (46 -> 42) == Additional (1): fi-icl-u Missing(5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-skl-6700hq == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10594 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10594: 12c12dd87b67ab5dd9e2d651372fc7a404c64bc9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 12c12dd87b67 drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10594/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH] RFC: Make igts for cross-driver stuff mandatory?
Make igt for cross-driver, I think you should rename it first, not an intel specific. NO company wants their employee working on other company stuff. You can rename it to DGT(drm graphics test), and published following libdrm, or directly merge to libdrm, then everyone can use it and develop it in same page, which is only my personal opinion. Regards, David > -Original Message- > From: dri-devel On Behalf Of Eric > Anholt > Sent: Friday, October 26, 2018 12:36 AM > To: Sean Paul ; Daniel Vetter > Cc: IGT development ; Intel Graphics > Development ; DRI Development de...@lists.freedesktop.org>; amd-...@lists.freedesktop.org > Subject: Re: [igt-dev] [PATCH] RFC: Make igts for cross-driver stuff > mandatory? > > Sean Paul writes: > > > On Fri, Oct 19, 2018 at 10:50:49AM +0200, Daniel Vetter wrote: > >> Hi all, > >> > >> This is just to collect feedback on this idea, and see whether the > >> overall dri-devel community stands on all this. I think the past few > >> cross-vendor uapi extensions all came with igts attached, and > >> personally I think there's lots of value in having them: A > >> cross-vendor interface isn't useful if every driver implements it > >> slightly differently. > >> > >> I think there's 2 questions here: > >> > >> - Do we want to make such testcases mandatory? > >> > > > > Yes, more testing == better code. > > > > > >> - If yes, are we there yet, or is there something crucially missing > >> still? > > > > In my experience, no. Last week while trying to replicate an intel-gfx > > CI failure, I tried compiling igt for one of my (intel) chromebooks. > > It seems like cross-compilation (or, in my case, just specifying > > prefix/ld_library_path/sbin_path) is broken on igt. If we want to > > impose restrictions across the entire subsystem, we need to make sure > > that everyone can build and deploy igt easily. > > > > I managed to hack around everything and get it working, but I still > > haven't tried switching out the toolchain. Once we have some GitLab CI > > to validate cross-compilation, then we can consider making IGT mandatory. > > > > It's possible that I'm just a meson n00b and didn't use the right > > incantation, so maybe it already works, but then we need better > documentation. > > > > I've pasted my horrible hacks below, I also didn't have libunwind, so > > removed its usage. > > I've also had to cut out libunwind for cross-compiling on many occasions. > Worst library. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.20
On 2018.10.25 11:28:28 -0700, Rodrigo Vivi wrote: > On Thu, Oct 25, 2018 at 04:07:14PM +0300, Joonas Lahtinen wrote: > > Quoting Zhenyu Wang (2018-10-23 06:46:59) > > > > > > Hi, > > > > > > Here's gvt-next-fixes for 4.20 with three changes. Mostly > > > to fix possible arbitrary update on guest GGTT entry and > > > with proper invalidate of old entry. Another one for one > > > chicken reg mask fix. > > > > > > thanks > > > > Hi, > > > > DIM seems to be (rightfully) complaining about one commit: > > > > 3e740f0ec37acecaa364c19d2d2826df83c8bf20 is lacking committer of sign-off > > This is something I'm asking gvt for a while already: > Please make review mandatory on your side. > yes, we are appling review process more strictly on gvt side, that one should be reviewed by Zhi when I was offline, but he seems forget to add r-b and I forgot to sign-off...Sorry for that, will regenerate. -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
== Series Details == Series: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o URL : https://patchwork.freedesktop.org/series/51542/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10585_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10585_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10585_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10585_full: === IGT changes === Possible regressions igt@gem_busy@close-race: shard-glk: PASS -> DMESG-FAIL == Known issues == Here are the changes found in Patchwork_10585_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#106886, fdo#103359) igt@gem_exec_schedule@pi-ringfull-blt: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctx0: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) +1 igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-hsw: PASS -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-128x128-suspend: shard-glk: PASS -> FAIL (fdo#103232) +1 igt@kms_cursor_crc@cursor-256x256-random: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-64x21-random: shard-apl: PASS -> FAIL (fdo#103232) +4 igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) +4 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-glk: PASS -> FAIL (fdo#103167, fdo#105682) igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: shard-skl: NOTRUN -> FAIL (fdo#103167) +3 igt@kms_plane@plane-position-covered-pipe-a-planes: shard-glk: PASS -> FAIL (fdo#103166) +2 igt@kms_plane@plane-position-covered-pipe-c-planes: shard-apl: PASS -> DMESG-WARN (fdo#108549) +26 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#108146) igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103166) igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) +3 igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) shard-skl: NOTRUN -> FAIL (fdo#99912) igt@kms_vblank@pipe-b-ts-continuation-modeset-rpm: shard-apl: PASS -> DMESG-FAIL (fdo#108549) +1 Possible fixes igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-apl: DMESG-FAIL (fdo#108549) -> PASS +3 igt@kms_atomic_transition@plane-all-modeset-transition: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: FAIL (fdo#106641) -> PASS igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-kbl: DMESG-WARN (fdo#107956) -> PASS igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: FAIL (fdo#108145) -> PASS +1 igt@kms_color@pipe-b-ctm-blue-to-red: shard-apl: DMESG-WARN (fdo#108549) -> PASS +21 igt@kms_color@pipe-c-degamma: shard-apl: FAIL (fdo#104782) -> PASS igt@kms_cursor_crc@cursor-128x42-onscreen: shard-apl: FAIL (fdo#103232) -> PASS +3 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS +5 igt@kms_frontbuffer_tracking@fbc-badstride: shard-skl: FAIL (fdo#105682) -> PASS igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt: shard-skl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-skl: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-x: shard-apl: FAIL
Re: [Intel-gfx] [FW: [PATCH 3/6] drm/i915/gtt: Disable read-only support under GVT]
> -Original Message- > From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On > Behalf Of Chris Wilson > Sent: Thursday, October 25, 2018 8:51 PM > To: Yuan, Hang > Cc: intel-gfx@lists.freedesktop.org; joonas.lahti...@linux.intel.com; > matthew.william.a...@gmail.com; Zhenyu Wang > ; Bloomfield, Jon ; > intel-gvt-...@lists.freedesktop.org > Subject: RE: [FW: [PATCH 3/6] drm/i915/gtt: Disable read-only support under > GVT] > > Quoting Yuan, Hang (2018-10-25 11:07:48) > > Hi Chris, > > > > I checked GVT shadow PPGTT handling codes and think GVT does > propagate guest PTE flags to shadow PPGTT entry. Then I run i915 self-test > case "igt_ctx_readonly" in KVMGT's guest. The case doesn't report any errors. > Can I know if there are any other reasons that you think GVT breaks read- > only support? > > I thought it was from a ci result, but going back through the logs we have > never run the selftests at that time under CI. So call it a lack of testing > and a > misread of the code. > > igt_ctx_readonly should be sufficient to prove the test, except it needs a bit > of refinement to be stricter over hang detection. > https://patchwork.freedesktop.org/patch/256433/ > -Chris [Yuan, Hang] Thanks. I will apply the patch and test again. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/plane: Export drm_plane_check_pixel_format()
== Series Details == Series: series starting with [1/2] drm/plane: Export drm_plane_check_pixel_format() URL : https://patchwork.freedesktop.org/series/51563/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10593 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51563/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10593 that come from known issues: === IGT changes === Issues hit igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#107713) igt@pm_rpm@basic-rte: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 == Participating hosts (46 -> 43) == Additional (1): fi-icl-u Missing(4): fi-bsw-cyan fi-ilk-m540 fi-byt-squawks fi-gdg-551 == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10593 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10593: bce3a00f737ca126daa6940159d15ffc43931ac3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bce3a00f737c drm/i915: Reuse plane format modifier checks to verify addfb() arguments 442fd2d0bbaf drm/plane: Export drm_plane_check_pixel_format() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10593/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2)
== Series Details == Series: drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2) URL : https://patchwork.freedesktop.org/series/50649/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10584_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10584_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-blt: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@gem_userptr_blits@readonly-unsync: shard-skl: PASS -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-c-legacy-gamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-256x256-dpms: shard-glk: PASS -> FAIL (fdo#103232) +4 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: PASS -> FAIL (fdo#103167) +4 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#108146) igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: shard-glk: PASS -> FAIL (fdo#108145) +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) +2 igt@kms_setmode@basic: shard-skl: NOTRUN -> FAIL (fdo#99912) igt@kms_vblank@pipe-b-ts-continuation-modeset-rpm: shard-apl: PASS -> DMESG-FAIL (fdo#108549) +1 igt@kms_vblank@pipe-c-wait-busy-hang: shard-apl: PASS -> DMESG-WARN (fdo#108549) +24 igt@pm_rpm@system-suspend-devices: shard-skl: NOTRUN -> INCOMPLETE (fdo#107807) Possible fixes igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-apl: DMESG-FAIL (fdo#108549) -> PASS +3 igt@kms_atomic_transition@plane-all-modeset-transition: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: FAIL (fdo#106641) -> PASS igt@kms_color@pipe-b-ctm-blue-to-red: shard-apl: DMESG-WARN (fdo#108549) -> PASS +21 igt@kms_color@pipe-c-degamma: shard-apl: FAIL (fdo#104782) -> PASS igt@kms_cursor_crc@cursor-128x42-onscreen: shard-apl: FAIL (fdo#103232) -> PASS +3 igt@kms_cursor_crc@cursor-256x256-random: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x256-suspend: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS +4 igt@kms_frontbuffer_tracking@fbc-badstride: shard-skl: FAIL (fdo#105682) -> PASS igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt: shard-skl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-skl: FAIL (fdo#103166) -> PASS igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039 fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074 fdo#108145
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/plane: Export drm_plane_check_pixel_format()
== Series Details ==
Series: series starting with [1/2] drm/plane: Export
drm_plane_check_pixel_format()
URL : https://patchwork.freedesktop.org/series/51563/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
442fd2d0bbaf drm/plane: Export drm_plane_check_pixel_format()
bce3a00f737c drm/i915: Reuse plane format modifier checks to verify addfb()
arguments
-:28: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#28: FILE: drivers/gpu/drm/i915/intel_display.c:14366:
+static bool any_plane_supports_format(struct drm_i915_private *dev_priv,
+uint64_t fb_modifier,
-:84: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#84: FILE: drivers/gpu/drm/i915/intel_display.c:14418:
+ DRM_DEBUG_KMS("Unsupported pixel format %s or modifier
0x%llx\n",
+ drm_get_format_name(mode_cmd->pixel_format,
total: 0 errors, 0 warnings, 2 checks, 134 lines checked
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source()
== Series Details == Series: series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() URL : https://patchwork.freedesktop.org/series/51562/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10592 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10592 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10592, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51562/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10592: === IGT changes === Possible regressions igt@kms_busy@basic-flip-a: fi-whl-u: PASS -> DMESG-WARN +2 fi-icl-u: NOTRUN -> DMESG-WARN igt@pm_rpm@basic-pci-d3-state: fi-skl-6600u: PASS -> DMESG-WARN +1 fi-kbl-7560u: PASS -> DMESG-WARN +1 fi-kbl-r: PASS -> DMESG-WARN +1 igt@pm_rpm@module-reload: fi-cfl-s3: PASS -> DMESG-WARN +1 fi-skl-6700hq: PASS -> DMESG-WARN +2 fi-cnl-u: PASS -> DMESG-WARN +2 fi-icl-u2: PASS -> DMESG-WARN +2 == Known issues == Here are the changes found in Patchwork_10592 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#107713) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (46 -> 44) == Additional (1): fi-icl-u Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10592 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10592: 4970b1f8ea5864ccf8177a81d69875d5cba0cfac @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4970b1f8ea58 drm/i915: Do not enable PSR in the next modeset after a error 06f2c7c4845b drm/i915: Keep PSR disabled after a driver reload after a PSR error 8722041afd17 drm/i915: Disable PSR when a PSR aux error happen 16514d3f1562 drm/i915/icl: Reset PSR interruptions 57fe8ec72fc8 drm/i915: Unmask PSR interruptions before assert IIR 804e6b686a8c drm/i915: Check PSR errors instead of retrain while PSR is enabled bcacc1b8ef43 drm/i915: Avoid a full port detection in the first eDP short pulse 811e7883ff20 drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked() 2692c0e3b41e drm/i915/psr: Always wait for idle state when disabling PSR 3ed40d086a0b drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10592/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Reuse plane format modifier checks to verify addfb() arguments
Currently there is some duplication of pixel format and modifier
validation code between the fb creation and plane check paths. We can
unify them by checking if any plane supports a pixel format and modifier
combination during framebuffer creation.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_display.c | 116 ++-
1 file changed, 19 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe045abb6472..1b5d936a93d0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14362,6 +14362,19 @@ u32 intel_fb_pitch_limit(struct drm_i915_private
*dev_priv,
DRM_MODE_ROTATE_0);
}
+static bool any_plane_supports_format(struct drm_i915_private *dev_priv,
+uint64_t fb_modifier,
+uint32_t pixel_format)
+{
+ struct drm_plane *plane;
+
+ drm_for_each_plane(plane, _priv->drm)
+ if (!drm_plane_check_pixel_format(plane, pixel_format,
+ fb_modifier))
+ return true;
+ return false;
+}
+
static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd)
@@ -14399,40 +14412,12 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
}
}
- /* Passed in modifier sanity checking. */
- switch (mode_cmd->modifier[0]) {
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- switch (mode_cmd->pixel_format) {
- case DRM_FORMAT_XBGR:
- case DRM_FORMAT_ABGR:
- case DRM_FORMAT_XRGB:
- case DRM_FORMAT_ARGB:
- break;
- default:
- DRM_DEBUG_KMS("RC supported only with RGB
formats\n");
- goto err;
- }
- /* fall through */
- case I915_FORMAT_MOD_Yf_TILED:
- if (mode_cmd->pixel_format == DRM_FORMAT_C8) {
- DRM_DEBUG_KMS("Indexed format does not support Yf
tiling\n");
- goto err;
- }
- /* fall through */
- case I915_FORMAT_MOD_Y_TILED:
- if (INTEL_GEN(dev_priv) < 9) {
- DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
- mode_cmd->modifier[0]);
- goto err;
- }
- break;
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
- DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
- mode_cmd->modifier[0]);
+ if (!any_plane_supports_format(dev_priv, mode_cmd->modifier[0],
+ mode_cmd->pixel_format)) {
+ DRM_DEBUG_KMS("Unsupported pixel format %s or modifier
0x%llx\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ _name),
+ mode_cmd->modifier[0]);
goto err;
}
@@ -14466,69 +14451,6 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
goto err;
}
- /* Reject formats not supported by any plane early. */
- switch (mode_cmd->pixel_format) {
- case DRM_FORMAT_C8:
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB:
- case DRM_FORMAT_ARGB:
- break;
- case DRM_FORMAT_XRGB1555:
- if (INTEL_GEN(dev_priv) > 3) {
- DRM_DEBUG_KMS("unsupported pixel format: %s\n",
-
drm_get_format_name(mode_cmd->pixel_format, _name));
- goto err;
- }
- break;
- case DRM_FORMAT_ABGR:
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- INTEL_GEN(dev_priv) < 9) {
- DRM_DEBUG_KMS("unsupported pixel format: %s\n",
-
drm_get_format_name(mode_cmd->pixel_format, _name));
- goto err;
- }
- break;
- case DRM_FORMAT_XBGR:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
- if (INTEL_GEN(dev_priv) < 4) {
- DRM_DEBUG_KMS("unsupported pixel format: %s\n",
-
drm_get_format_name(mode_cmd->pixel_format, _name));
- goto err;
-
[Intel-gfx] [PATCH 1/2] drm/plane: Export drm_plane_check_pixel_format()
i915 will make use of this to fail early during framebuffer creation. Suggested-by: Ville Syrjälä Cc: dri-de...@lists.freedesktop.org Cc: Ville Syrjälä Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/drm_plane.c | 1 + include/drm/drm_plane.h | 11 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 1fa98bd12003..e834788619d1 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -589,6 +589,7 @@ int drm_plane_check_pixel_format(struct drm_plane *plane, return 0; } +EXPORT_SYMBOL(drm_plane_check_pixel_format); static int __setplane_check(struct drm_plane *plane, struct drm_crtc *crtc, diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 0a0834bef8bd..8637b5239eb3 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -763,6 +763,17 @@ static inline struct drm_plane *drm_plane_find(struct drm_device *dev, return mo ? obj_to_plane(mo) : NULL; } +/** + * drm_plane_check_pixel_format - check format and modifier support. + * @plane: plane to check support against. + * @format: pixel format to check support for. + * @modifier: format modifier to check support for. + * + * Returns 0 on success or negative error code on failure. + */ +int drm_plane_check_pixel_format(struct drm_plane *plane, +u32 format, u64 modifier); + /** * drm_for_each_plane_mask - iterate over planes specified by bitmask * @plane: the loop cursor -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source()
== Series Details == Series: series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() URL : https://patchwork.freedesktop.org/series/51562/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() Okay! Commit: drm/i915/psr: Always wait for idle state when disabling PSR Okay! Commit: drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked() Okay! Commit: drm/i915: Avoid a full port detection in the first eDP short pulse Okay! Commit: drm/i915: Check PSR errors instead of retrain while PSR is enabled Okay! Commit: drm/i915: Unmask PSR interruptions before assert IIR Okay! Commit: drm/i915/icl: Reset PSR interruptions Okay! Commit: drm/i915: Disable PSR when a PSR aux error happen -drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) Commit: drm/i915: Keep PSR disabled after a driver reload after a PSR error Okay! Commit: drm/i915: Do not enable PSR in the next modeset after a error -drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3709:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source()
== Series Details == Series: series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() URL : https://patchwork.freedesktop.org/series/51562/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3ed40d086a0b drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() 2692c0e3b41e drm/i915/psr: Always wait for idle state when disabling PSR 811e7883ff20 drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked() bcacc1b8ef43 drm/i915: Avoid a full port detection in the first eDP short pulse 804e6b686a8c drm/i915: Check PSR errors instead of retrain while PSR is enabled 57fe8ec72fc8 drm/i915: Unmask PSR interruptions before assert IIR 16514d3f1562 drm/i915/icl: Reset PSR interruptions 8722041afd17 drm/i915: Disable PSR when a PSR aux error happen 06f2c7c4845b drm/i915: Keep PSR disabled after a driver reload after a PSR error 4970b1f8ea58 drm/i915: Do not enable PSR in the next modeset after a error -:25: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 #25: FILE: drivers/gpu/drm/i915/i915_drv.h:642: + bool sink_not_reliable; total: 0 errors, 0 warnings, 1 checks, 43 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/glk: Remove 99% limitation.
== Series Details == Series: drm/i915/glk: Remove 99% limitation. URL : https://patchwork.freedesktop.org/series/51561/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10591 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51561/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10591 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#107713) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719, fdo#106000) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) fi-hsw-4770r: PASS -> DMESG-WARN (fdo#105602) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 == Participating hosts (46 -> 44) == Additional (1): fi-icl-u Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10591 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10591: b3b8532f9e695e6dad96fe2d5da583cceeb51fe6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b3b8532f9e69 drm/i915/glk: Remove 99% limitation. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10591/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 10/10] drm/i915: Do not enable PSR in the next modeset after a error
When we detect a error and disable PSR, it is kept disable until the
next modeset but as the sink already show signs that it do not
properly work with PSR lets disabled it for good to avoid any
additional flickering.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 11 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2a2574f34b4a..89479d0ee6b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -639,6 +639,7 @@ struct i915_psr {
ktime_t last_entry_attempt;
ktime_t last_exit;
u32 irq_aux_error;
+ bool sink_not_reliable;
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 718270da1061..47b334b6af16 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -542,6 +542,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
+ if (dev_priv->psr.sink_not_reliable) {
+ DRM_DEBUG_KMS("Sink not reliable set\n");
+ return;
+ }
+
if (IS_HASWELL(dev_priv) &&
I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
S3D_ENABLE) {
@@ -942,6 +947,7 @@ static void intel_psr_handle_irq(struct drm_i915_private
*dev_priv)
mutex_lock(>lock);
intel_psr_disable_locked(psr->dp);
+ psr->sink_not_reliable = true;
/* let's make sure that sink is awaken */
drm_dp_dpcd_writeb(>dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
@@ -1141,6 +1147,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
intel_psr_disable_locked(intel_dp);
+ psr->sink_not_reliable = true;
}
if (drm_dp_dpcd_readb(_dp->aux, DP_PSR_ERROR_STATUS, ) != 1) {
@@ -1158,8 +1165,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
if (val & ~errors)
DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
val & ~errors);
- if (val & errors)
+ if (val & errors) {
intel_psr_disable_locked(intel_dp);
+ psr->sink_not_reliable = true;
+ }
/* clear status register */
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS, val);
exit:
--
2.19.1
___
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[Intel-gfx] [PATCH v3 06/10] drm/i915: Unmask PSR interruptions before assert IIR
The IIR register is a result of a AND operation between the mask
register and the actual interruption state so checking IIR before
unmask interruptions will never get any errors even if they exits.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d1f53723388..21756e9a7523 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4086,8 +4086,8 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
}
if (IS_HASWELL(dev_priv)) {
- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -4232,8 +4232,8 @@ static void gen8_de_irq_postinstall(struct
drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
for_each_pipe(dev_priv, pipe) {
dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
--
2.19.1
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[Intel-gfx] [PATCH v3 03/10] drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked()
In the past we had hooks to configure HW for VLV/CHV too, in the drop
of VLV/CHV support the intel_psr_disable_source() code was not moved
to the caller, so doing it here.
Suggested-by: Dhinakaran Pandiyan
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 25 +
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4c226b78c3fc..2d692ad41bf9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -680,13 +680,20 @@ static void intel_psr_exit(struct drm_i915_private
*dev_priv)
dev_priv->psr.active = false;
}
-static void
-intel_psr_disable_source(struct intel_dp *intel_dp)
+static void intel_psr_disable_locked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;
+ lockdep_assert_held(_priv->psr.lock);
+
+ if (!dev_priv->psr.enabled)
+ return;
+
+ DRM_DEBUG_KMS("Disabling PSR%s\n",
+ dev_priv->psr.psr2_enabled ? "2" : "1");
+
intel_psr_exit(dev_priv);
if (dev_priv->psr.psr2_enabled) {
@@ -701,20 +708,6 @@ intel_psr_disable_source(struct intel_dp *intel_dp)
if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
2000))
DRM_ERROR("Timed out waiting PSR idle state\n");
-}
-
-static void intel_psr_disable_locked(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- lockdep_assert_held(_priv->psr.lock);
-
- if (!dev_priv->psr.enabled)
- return;
-
- DRM_DEBUG_KMS("Disabling PSR%s\n",
- dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_disable_source(intel_dp);
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
--
2.19.1
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[Intel-gfx] [PATCH v3 09/10] drm/i915: Keep PSR disabled after a driver reload after a PSR error
If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
will still keep the error set even after the reset done in the
irq_preinstall and irq_uninstall hooks.
And enabling in this situation cause the screen to freeze in the
first time that PSR HW tries to activate so lets keep PSR disabled
to avoid any rendering problems.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 68201cc24d25..718270da1061 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -529,6 +529,19 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
+ /*
+* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
+* will still keep the error set even after the reset done in the
+* irq_preinstall and irq_uninstall hooks.
+* And enabling in this situation cause the screen to freeze in the
+* first time that PSR HW tries to activate so lets keep PSR disabled
+* to avoid any rendering problems.
+*/
+ if (I915_READ(EDP_PSR_IIR) & EDP_PSR_ERROR(TRANSCODER_EDP)) {
+ DRM_DEBUG_KMS("PSR interruption error set\n");
+ return;
+ }
+
if (IS_HASWELL(dev_priv) &&
I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
S3D_ENABLE) {
--
2.19.1
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[Intel-gfx] [PATCH v3 08/10] drm/i915: Disable PSR when a PSR aux error happen
While PSR is active hardware will do aux transactions by it self to
wakeup sink to receive a new frame when necessary. If that
transaction is not acked by sink, hardware will trigger this
interruption.
So let's disable PSR as it is a hint that there is problem with this
sink.
The removed FIXME was asking to manually train the link but we don't
need to do that as by spec sink should do a short pulse when it is
out of sync with source, we just need to make sure it is awaken and
the SDP header with PSR disable will trigger this condition.
v3: added workarround to fix scheduled work starvation cause by
to frequent PSR error interruption
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 53 +---
2 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d7761b8ac07..2a2574f34b4a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -638,6 +638,7 @@ struct i915_psr {
u8 sink_sync_latency;
ktime_t last_entry_attempt;
ktime_t last_exit;
+ u32 irq_aux_error;
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 08b5351e4efb..68201cc24d25 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -152,6 +152,7 @@ void intel_psr_irq_handler(struct drm_i915_private
*dev_priv, u32 psr_iir)
u32 transcoders = BIT(TRANSCODER_EDP);
enum transcoder cpu_transcoder;
ktime_t time_ns = ktime_get();
+ u32 mask = 0;
if (INTEL_GEN(dev_priv) >= 8)
transcoders |= BIT(TRANSCODER_A) |
@@ -159,10 +160,23 @@ void intel_psr_irq_handler(struct drm_i915_private
*dev_priv, u32 psr_iir)
BIT(TRANSCODER_C);
for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- /* FIXME: Exit PSR and link train manually when this happens. */
- if (psr_iir & EDP_PSR_ERROR(cpu_transcoder))
- DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",
- transcoder_name(cpu_transcoder));
+ if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ DRM_WARN("[transcoder %s] PSR aux error\n",
+transcoder_name(cpu_transcoder));
+
+ spin_lock(_priv->irq_lock);
+ dev_priv->psr.irq_aux_error |= BIT(cpu_transcoder);
+ spin_unlock(_priv->irq_lock);
+
+ /*
+* If this interruption is not masked it will keep
+* interrupting so fast that it prevents the scheduled
+* work to run.
+* Also after a PSR error, we don't want to arm PSR
+* again so we don't care about unmask the interruption.
+*/
+ mask |= EDP_PSR_ERROR(cpu_transcoder);
+ }
if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
dev_priv->psr.last_entry_attempt = time_ns;
@@ -184,6 +198,13 @@ void intel_psr_irq_handler(struct drm_i915_private
*dev_priv, u32 psr_iir)
}
}
}
+
+ if (mask) {
+ mask |= I915_READ(EDP_PSR_IMR);
+ I915_WRITE(EDP_PSR_IMR, mask);
+
+ schedule_work(_priv->psr.work);
+ }
}
static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
@@ -893,11 +914,35 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private
*dev_priv,
return ret;
}
+static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
+{
+ struct i915_psr *psr = _priv->psr;
+ u32 irq_aux_error;
+
+ spin_lock_irq(_priv->irq_lock);
+ irq_aux_error = psr->irq_aux_error;
+ psr->irq_aux_error = 0;
+ spin_unlock_irq(_priv->irq_lock);
+
+ WARN_ON(irq_aux_error & ~BIT(TRANSCODER_EDP));
+
+ mutex_lock(>lock);
+
+ intel_psr_disable_locked(psr->dp);
+ /* let's make sure that sink is awaken */
+ drm_dp_dpcd_writeb(>dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+
+ mutex_unlock(_priv->psr.lock);
+}
+
static void intel_psr_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv), psr.work);
+ if (READ_ONCE(dev_priv->psr.irq_aux_error))
+ intel_psr_handle_irq(dev_priv);
+
mutex_lock(_priv->psr.lock);
if (!dev_priv->psr.enabled)
--
2.19.1
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[Intel-gfx] [PATCH v3 05/10] drm/i915: Check PSR errors instead of retrain while PSR is enabled
When a PSR error happens sink sets the PSR errors register and also
set the link to a error status.
So in the short pulse handling it was returning earlier and doing a
full detection and attempting to retrain but it fails as PSR HW is
in change of the main-link.
Just call intel_psr_short_pulse() before
intel_dp_needs_link_retrain() is not the right fix as
intel_dp_needs_link_retrain() would return true and trigger a full
detection while PSR HW is still in change of main-link.
Check for PSR active is also not safe as it could be inactive due a
frontbuffer invalidate and still doing the PSR exit sequence.
v3: added comment in intel_dp_needs_link_retrain()
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 15 +++
3 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fce67094c2a0..9bf3a128adb3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4401,6 +4401,17 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
if (!intel_dp->link_trained)
return false;
+ /*
+* While PSR source HW is enabled, it will control main-link sending
+* frames, enabling and disabling it so trying to do a retrain will fail
+* as the link would or not be on or it could mix training patterns
+* and frame data at the same time causing retrain to fail.
+* Also when exiting PSR, HW will retrain the link anyways fixing
+* any link status error.
+*/
+ if (intel_psr_enabled(intel_dp))
+ return false;
+
if (!intel_dp_get_link_status(intel_dp, link_status))
return false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308729b4..ce89c92eaf0a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2031,6 +2031,7 @@ void intel_psr_irq_handler(struct drm_i915_private
*dev_priv, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
+bool intel_psr_enabled(struct intel_dp *intel_dp);
/* intel_quirks.c */
void intel_init_quirks(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d692ad41bf9..08b5351e4efb 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1107,3 +1107,18 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
exit:
mutex_unlock(>lock);
}
+
+bool intel_psr_enabled(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ bool ret;
+
+ if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
+ return false;
+
+ mutex_lock(_priv->psr.lock);
+ ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
+ mutex_unlock(_priv->psr.lock);
+
+ return ret;
+}
--
2.19.1
___
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[Intel-gfx] [PATCH v3 07/10] drm/i915/icl: Reset PSR interruptions
All other interruptions gen11 interruptions are reset in gen11_irq_reset() also it is done for other gens that supports PSR. Cc: Dhinakaran Pandiyan Cc: Paulo Zanoni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 21756e9a7523..09f7723dbd5c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3679,6 +3679,9 @@ static void gen11_irq_reset(struct drm_device *dev) I915_WRITE(GEN11_DISPLAY_INT_CTL, 0); + I915_WRITE(EDP_PSR_IMR, 0x); + I915_WRITE(EDP_PSR_IIR, 0x); + for_each_pipe(dev_priv, pipe) if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 02/10] drm/i915/psr: Always wait for idle state when disabling PSR
It should always wait for idle state when disabling PSR because PSR
could be inactive due a call to intel_psr_exit() and while PSR is
still being disabled asynchronously userspace could change the
modeset causing a call to psr_disable() that will not wait for PSR
idle and then PSR will be enabled again while PSR is still not idle.
v2: rebased on top of the patch reusing psr_exit()
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 41 ++--
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index f698b3f45c6d..4c226b78c3fc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -661,8 +661,12 @@ static void intel_psr_exit(struct drm_i915_private
*dev_priv)
{
u32 val;
- if (!dev_priv->psr.active)
+ if (!dev_priv->psr.active) {
+ if (INTEL_GEN(dev_priv) >= 9)
+ WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
+ WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
return;
+ }
if (dev_priv->psr.psr2_enabled) {
val = I915_READ(EDP_PSR2_CTL);
@@ -680,32 +684,23 @@ static void
intel_psr_disable_source(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ i915_reg_t psr_status;
+ u32 psr_status_mask;
- if (dev_priv->psr.active) {
- i915_reg_t psr_status;
- u32 psr_status_mask;
-
- intel_psr_exit(dev_priv);
+ intel_psr_exit(dev_priv);
- if (dev_priv->psr.psr2_enabled) {
- psr_status = EDP_PSR2_STATUS;
- psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
- } else {
- psr_status = EDP_PSR_STATUS;
- psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
- }
-
- /* Wait till PSR is idle */
- if (intel_wait_for_register(dev_priv,
- psr_status, psr_status_mask, 0,
- 2000))
- DRM_ERROR("Timed out waiting for PSR Idle State\n");
+ if (dev_priv->psr.psr2_enabled) {
+ psr_status = EDP_PSR2_STATUS;
+ psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
- if (dev_priv->psr.psr2_enabled)
- WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
- else
- WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+ psr_status = EDP_PSR_STATUS;
+ psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
}
+
+ /* Wait till PSR is idle */
+ if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
+ 2000))
+ DRM_ERROR("Timed out waiting PSR idle state\n");
}
static void intel_psr_disable_locked(struct intel_dp *intel_dp)
--
2.19.1
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[Intel-gfx] [PATCH v3 04/10] drm/i915: Avoid a full port detection in the first eDP short pulse
Some eDP panels do not set a valid sink count value and even for the
ones that sets is should always be one for eDP, that is why it is not
cached in intel_edp_init_dpcd().
But intel_dp_short_pulse() compares the old count with the read one
if there is a mistmatch a full port detection will be executed, what
was happening in the first short pulse interruption of eDP panels
that sets sink count.
Instead of just skip the compasison for eDP panels, lets not read
the sink count at all for eDP.
v2: the previous version of this patch was caching the sink count
in intel_edp_init_dpcd() but I was pointed out by Ville a patch that
handled a case of a eDP panel that do not set sink count
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 44 +++--
1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8e64f149ab09..fce67094c2a0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4039,8 +4039,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
{
- u8 sink_count;
-
if (!intel_dp_read_dpcd(intel_dp))
return false;
@@ -4050,25 +4048,35 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
intel_dp_set_common_rates(intel_dp);
}
- if (drm_dp_dpcd_readb(_dp->aux, DP_SINK_COUNT, _count) <= 0)
- return false;
-
/*
-* Sink count can change between short pulse hpd hence
-* a member variable in intel_dp will track any changes
-* between short pulse interrupts.
+* Some eDP panels do not set a valid value for sink count, that is why
+* it don't care about read it here and in intel_edp_init_dpcd().
*/
- intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
+ if (!intel_dp_is_edp(intel_dp)) {
+ u8 count;
+ ssize_t r;
- /*
-* SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
-* a dongle is present but no display. Unless we require to know
-* if a dongle is present or not, we don't need to update
-* downstream port information. So, an early return here saves
-* time from performing other operations which are not required.
-*/
- if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
- return false;
+ r = drm_dp_dpcd_readb(_dp->aux, DP_SINK_COUNT, );
+ if (r < 1)
+ return false;
+
+ /*
+* Sink count can change between short pulse hpd hence
+* a member variable in intel_dp will track any changes
+* between short pulse interrupts.
+*/
+ intel_dp->sink_count = DP_GET_SINK_COUNT(count);
+
+ /*
+* SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
+* a dongle is present but no display. Unless we require to know
+* if a dongle is present or not, we don't need to update
+* downstream port information. So, an early return here saves
+* time from performing other operations which are not required.
+*/
+ if (!intel_dp->sink_count)
+ return false;
+ }
if (!drm_dp_is_branch(intel_dp->dpcd))
return true; /* native DP sink */
--
2.19.1
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[Intel-gfx] [PATCH v3 01/10] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source()
Both functions have the same code to disable PSR, so let's reuse that
code instead of duplicate.
Suggested-by: Dhinakaran Pandiyan
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 50 ++--
1 file changed, 21 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 423cdf84059c..f698b3f45c6d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -657,6 +657,25 @@ void intel_psr_enable(struct intel_dp *intel_dp,
mutex_unlock(_priv->psr.lock);
}
+static void intel_psr_exit(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ if (!dev_priv->psr.active)
+ return;
+
+ if (dev_priv->psr.psr2_enabled) {
+ val = I915_READ(EDP_PSR2_CTL);
+ WARN_ON(!(val & EDP_PSR2_ENABLE));
+ I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
+ } else {
+ val = I915_READ(EDP_PSR_CTL);
+ WARN_ON(!(val & EDP_PSR_ENABLE));
+ I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
+ }
+ dev_priv->psr.active = false;
+}
+
static void
intel_psr_disable_source(struct intel_dp *intel_dp)
{
@@ -666,20 +685,14 @@ intel_psr_disable_source(struct intel_dp *intel_dp)
i915_reg_t psr_status;
u32 psr_status_mask;
+ intel_psr_exit(dev_priv);
+
if (dev_priv->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
-
- I915_WRITE(EDP_PSR2_CTL,
- I915_READ(EDP_PSR2_CTL) &
- ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
-
} else {
psr_status = EDP_PSR_STATUS;
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
-
- I915_WRITE(EDP_PSR_CTL,
- I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
}
/* Wait till PSR is idle */
@@ -687,8 +700,6 @@ intel_psr_disable_source(struct intel_dp *intel_dp)
psr_status, psr_status_mask, 0,
2000))
DRM_ERROR("Timed out waiting for PSR Idle State\n");
-
- dev_priv->psr.active = false;
} else {
if (dev_priv->psr.psr2_enabled)
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
@@ -926,25 +937,6 @@ static void intel_psr_work(struct work_struct *work)
mutex_unlock(_priv->psr.lock);
}
-static void intel_psr_exit(struct drm_i915_private *dev_priv)
-{
- u32 val;
-
- if (!dev_priv->psr.active)
- return;
-
- if (dev_priv->psr.psr2_enabled) {
- val = I915_READ(EDP_PSR2_CTL);
- WARN_ON(!(val & EDP_PSR2_ENABLE));
- I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
- } else {
- val = I915_READ(EDP_PSR_CTL);
- WARN_ON(!(val & EDP_PSR_ENABLE));
- I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
- }
- dev_priv->psr.active = false;
-}
-
/**
* intel_psr_invalidate - Invalidade PSR
* @dev_priv: i915 device
--
2.19.1
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[Intel-gfx] [PATCH] drm/i915/glk: Remove 99% limitation.
While checking the opportunity to add a display_gen
check to allow glk and cnl to be on same bucket I noticed
these FIXME cases here.
So I got the confirmation from HW architect that we actually
never needed this workaround.
"GLK supports 2 pixel per clock, so pixel clock can be up to 2 * cdclk."
So, this reverts commit 97f55ca5b662 ("drm/i915/glk: limit pixel
clock to 99% of cdclk workaround")
Fixes: 97f55ca5b662 ("drm/i915/glk: limit pixel clock to 99% of cdclk
workaround")
Cc: Ville Syrjälä
Cc: Madhav Chauhan
Cc: Jani Nikula
Cc: Clinton Taylor
Cc: Arthur J Runyan
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cdclk.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 29075c763428..8d74276029e6 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2138,16 +2138,8 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
int pixel_rate)
{
- if (INTEL_GEN(dev_priv) >= 10)
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return DIV_ROUND_UP(pixel_rate, 2);
- else if (IS_GEMINILAKE(dev_priv))
- /*
-* FIXME: Avoid using a pixel clock that is more than 99% of
the cdclk
-* as a temporary workaround. Use a higher cdclk instead. (Note
that
-* intel_compute_max_dotclk() limits the max pixel clock to 99%
of max
-* cdclk.)
-*/
- return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
else if (IS_GEN9(dev_priv) ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
@@ -2543,14 +2535,8 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
{
int max_cdclk_freq = dev_priv->max_cdclk_freq;
- if (INTEL_GEN(dev_priv) >= 10)
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return 2 * max_cdclk_freq;
- else if (IS_GEMINILAKE(dev_priv))
- /*
-* FIXME: Limiting to 99% as a temporary workaround. See
-* intel_min_cdclk() for details.
-*/
- return 2 * max_cdclk_freq * 99 / 100;
else if (IS_GEN9(dev_priv) ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return max_cdclk_freq;
--
2.19.1
___
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Re: [Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+
On Tue, Oct 23, 2018 at 10:30:18AM +0300, Jani Nikula wrote:
> On Mon, 22 Oct 2018, Rodrigo Vivi wrote:
> > On Mon, Oct 22, 2018 at 05:12:18PM -0700, Paulo Zanoni wrote:
> >> Em Seg, 2018-10-22 às 16:55 -0700, Rodrigo Vivi escreveu:
> >> > On Mon, Oct 22, 2018 at 04:32:00PM -0700, Paulo Zanoni wrote:
> >> > > Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu:
> >> > > > On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote:
> >> > > > > BSpec does not show these WAs as applicable to GLK, and for CNL
> >> > > > > it
> >> > > > > only shows them applicable for a super early pre-production
> >> > > > > stepping
> >> > > > > we shouldn't be caring about anymore. Remove these so we can
> >> > > > > avoid
> >> > > > > them on ICL too.
> >> > > > >
> >> > > > > Cc: Matt Roper
> >> > > > > Signed-off-by: Paulo Zanoni
> >> > > > > ---
> >> > > > > drivers/gpu/drm/i915/intel_pm.c | 43 ++---
> >> > > > >
> >> > > > >
> >> > > > > 1 file changed, 23 insertions(+), 20 deletions(-)
> >> > > > >
> >> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >> > > > > b/drivers/gpu/drm/i915/intel_pm.c
> >> > > > > index 67a4d0735291..18157c6ee126 100644
> >> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > > > > @@ -4696,28 +4696,31 @@ static int skl_compute_plane_wm(const
> >> > > > > struct drm_i915_private *dev_priv,
> >> > > > >res_lines = div_round_up_fixed16(selected_result,
> >> > > > > wp-
> >> > > > > > plane_blocks_per_line);
> >> > > > >
> >> > > > > - /* Display WA #1125: skl,bxt,kbl,glk */
> >> > > > > - if (level == 0 && wp->rc_surface)
> >> > > > > - res_blocks += fixed16_to_u32_round_up(wp-
> >> > > > > > y_tile_minimum);
> >> > > > >
> >> > > > > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
> >> > > >
> >> > > > IS_GEN9_BC || IS_BXT
> >> > > >
> >> > > > would be a little easier to parse, me thinks.
> >> > >
> >> > > I can do that, but what I really want is "DISPLAY_GEN(dev_priv) ==
> >> > > 9".
> >> >
> >> > work in progress...
> >> >
> >> > btw...
> >> >
> >> > DISPLAY_GEN(dev_priv) == 9 or simply DISPLAY(dev_priv, 9) ?
> >>
> >> It should mimic the model we already use: INTEL_GEN(dev_priv) >= 9.
> >
> > there's a macro defined on gen we end up never using
> > IS_GEN(9, GEN_FOREVER) with the same effect of INTEL_GEN(dev_priv) >= 9
> >
> > Should we just kill that or try to use more that instead of direct
> > comparison?
> >
> > The advantage seems to be the use of bitmasks...
> >
> >>
> >> I would expect a macro called DISPLAY() to return *the* Display or to
> >> simply display somewhere the thing I pass as an argument. Now
> >> DISPLAY_GEN() sounds more like it returns the GEN of the DISPLAY (or
> >> generates a Display).
> >
> > what about IS_DISPLAY(dev_priv, 9) ?
> > and IS_DISPLAY_RANGE(dev_priv, 5, 9)
>
> Perhaps IS_DISPLAY_GEN(dev_priv, start, end).
>
> *However* the naming and composition of the macro is *much* less
> important than what the code ends up looking.
I fully agree. For this reason I started with the already existent GEN checks.
> Does the display gen
> adequately cover the differences between platforms ultimately?
This thought got me starting many different attempts and then
using git reset --hard HEAD
so many times this week.
No, this is not enough to cover all the needs. Geminilake right
now is the only exception case. We could have another case on internal
right now where we could use same approach to make it better.
But still the ugliest part can be the intersaction and gray areas with
GEM part.
>
> For example, a clear counter indication is that you'll be hard pressed
> to express the current HAS_GMCH_DISPLAY() in terms of display gen in a
> way that doesn't have to check for VLV/CHV.
Yeap, I don't think this display_gen solve this case. Although maybe
the range can help a bit to reduce the gmch_display checks.
> I don't think you can avoid
> IS_GEMINILAKE() either, you'll end up using display gen 10 in some
> places but Geminilake in others, ultimately making the end result worse
> than the starting point.
Well... I decided to give a try starting for the glk case to see
how it gets.
https://github.com/vivijim/drm-intel/tree/display_gen
Could you please take a look and let me know what do you think?
This version is taking display_gen to extreme, but we could
have a reduced one with glk checks inside bxt and dsi functions.
well, either way one fact is that we already have a code that is mixed with
IS_GEN and platform codename checks. Even if we still have some cases
where platform codename checks is unavoidable maybe it is better if we
prefer gen or display gen over platform codename when possible.
At least it reduces the mixed cases and gets easier to add
new platforms.
Thanks,
Rodrigo.
>
> BR,
> Jani.
>
>
> >
> >>
> >>
> >> >
> >> > I'm play around here with:
> >> >
>
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: Add function to check for linear surfaces (rev2)
== Series Details == Series: series starting with [v2,1/2] drm/i915: Add function to check for linear surfaces (rev2) URL : https://patchwork.freedesktop.org/series/51550/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10590 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51550/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10590 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: fi-kbl-7560u: PASS -> INCOMPLETE (fdo#108044) igt@gem_exec_suspend@basic-s3: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#107713) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) igt@pm_rpm@module-reload: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044 == Participating hosts (46 -> 44) == Additional (1): fi-icl-u Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10590 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10590: 4959d3f659f5c6f328e09c7778b6b3001628591e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4959d3f659f5 drm/i915: Do not program aux plane offsets on gen11+ 873d35bb5c58 drm/i915: Add function to check for linear surfaces == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10590/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/syncobj: Avoid kmalloc(GFP_KERNEL) under spinlock
== Series Details == Series: drm/syncobj: Avoid kmalloc(GFP_KERNEL) under spinlock URL : https://patchwork.freedesktop.org/series/51525/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10581_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10581_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> INCOMPLETE (fdo#106886, k.org#198133, fdo#103359) igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@gem_userptr_blits@readonly-unsync: shard-skl: PASS -> INCOMPLETE (fdo#108074) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-apl: PASS -> DMESG-FAIL (fdo#108549) igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-hsw: PASS -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-a-ctm-max: shard-apl: PASS -> FAIL (fdo#108147) igt@kms_concurrent@pipe-a: shard-apl: PASS -> DMESG-WARN (fdo#108549) +10 igt@kms_cursor_crc@cursor-128x128-random: shard-apl: PASS -> FAIL (fdo#103232) +2 shard-glk: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-128x128-suspend: shard-skl: PASS -> INCOMPLETE (fdo#104108) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) +6 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-glk: PASS -> FAIL (fdo#105682, fdo#103167) igt@kms_plane@plane-position-covered-pipe-a-planes: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_plane@plane-position-covered-pipe-c-planes: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#108146) igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: shard-glk: PASS -> FAIL (fdo#108145) +1 igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) shard-skl: NOTRUN -> FAIL (fdo#99912) igt@kms_vblank@pipe-a-wait-idle-hang: shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133) Possible fixes igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: FAIL (fdo#106641) -> PASS igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_color@pipe-b-ctm-blue-to-red: shard-apl: DMESG-WARN (fdo#108549) -> PASS +10 igt@kms_color@pipe-c-degamma: shard-apl: FAIL (fdo#104782) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +5 igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc: shard-skl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS +4 igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: shard-skl: FAIL (fdo#108145, fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-c-tiling-x: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_setmode@basic: shard-hsw: FAIL (fdo#99912) -> PASS igt@kms_vblank@pipe-b-ts-continuation-modeset: shard-apl: DMESG-FAIL (fdo#108549) -> PASS +1 Warnings igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb: shard-apl: FAIL (fdo#108145) -> DMESG-FAIL (fdo#108145, fdo#108549) fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51558/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10589 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10589 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10589, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51558/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10589: === IGT changes === Possible regressions igt@drv_selftest@live_hangcheck: fi-skl-guc: PASS -> DMESG-FAIL == Known issues == Here are the changes found in Patchwork_10589 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@drv_module_reload@basic-reload-inject: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106248, fdo#106725) igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (46 -> 43) == Additional (1): fi-icl-u Missing(4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10589 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10589: 1219baa05119d8730e59bcb8a582aa9fdb5a31d6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1219baa05119 drm/dp: Define payload size for DP SDP PPS packet 210cec132d70 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 040fe1b1e366 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC 76ea47879c90 drm/dp: DRM DP helper/macros to get DP sink DSC parameters 9c1f7154a9d3 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init fa18e8c8969f drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 48f9de182d37 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10589/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51558/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Okay! Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Okay! Commit: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Okay! Commit: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Okay! Commit: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC +drivers/gpu/drm/i915/intel_dp.c:4208:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4208:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4251:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4251:27: warning: expression using sizeof(void) Commit: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Okay! Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51558/ State : warning == Summary == $ dim checkpatch origin/drm-tip 48f9de182d37 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming fa18e8c8969f drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 9c1f7154a9d3 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 76ea47879c90 drm/dp: DRM DP helper/macros to get DP sink DSC parameters 040fe1b1e366 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC -:27: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #27: * rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha) total: 0 errors, 1 warnings, 0 checks, 132 lines checked 210cec132d70 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 1219baa05119 drm/dp: Define payload size for DP SDP PPS packet ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: HPD IRQ storm detection fixes
== Series Details == Series: drm/i915: HPD IRQ storm detection fixes URL : https://patchwork.freedesktop.org/series/51556/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10588 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51556/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10588 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_execlists: fi-apl-guc: PASS -> INCOMPLETE (fdo#106693) igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_frontbuffer_tracking@basic: fi-icl-u2: PASS -> FAIL (fdo#103167) igt@pm_rpm@module-reload: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 == Participating hosts (46 -> 44) == Additional (1): fi-icl-u Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10588 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10588: 1784501ab2ab85a6144e2759380b541219c2c714 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1784501ab2ab drm/i915: Add short HPD IRQ storm detection for non-MST systems 94a9e3d60a0b drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10588/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/syncobj: Avoid kmalloc(GFP_KERNEL) under spinlock
== Series Details == Series: drm/syncobj: Avoid kmalloc(GFP_KERNEL) under spinlock URL : https://patchwork.freedesktop.org/series/51525/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10580_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10580_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-blt: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctx0: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) +1 igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-apl: PASS -> DMESG-FAIL (fdo#108549) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-hsw: PASS -> DMESG-WARN (fdo#107956) igt@kms_concurrent@pipe-a: shard-apl: PASS -> DMESG-WARN (fdo#108549) +13 igt@kms_cursor_crc@cursor-128x128-random: shard-apl: PASS -> FAIL (fdo#103232) +3 igt@kms_cursor_crc@cursor-128x128-suspend: shard-glk: PASS -> FAIL (fdo#103232) +3 igt@kms_cursor_crc@cursor-256x256-random: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-suspend: shard-apl: PASS -> FAIL (fdo#103232, fdo#103191) igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled: shard-skl: NOTRUN -> FAIL (fdo#103184) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) +4 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-apl: PASS -> FAIL (fdo#103167) +4 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: PASS -> FAIL (fdo#105682, fdo#103167) igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: shard-skl: NOTRUN -> FAIL (fdo#103167) +2 igt@kms_plane@pixel-format-pipe-c-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885) igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#108146) igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-skl: NOTRUN -> FAIL (fdo#103166, fdo#107815) igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) shard-skl: NOTRUN -> FAIL (fdo#99912) igt@pm_backlight@fade_with_suspend: shard-skl: NOTRUN -> FAIL (fdo#107847) igt@pm_rpm@gem-evict-pwrite: shard-skl: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_busy@close-race: shard-apl: DMESG-FAIL -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-apl: DMESG-FAIL (fdo#108549) -> PASS +3 igt@kms_atomic_transition@plane-all-modeset-transition: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_busy@extended-pageflip-hang-newfb-render-b: shard-glk: DMESG-WARN (fdo#107956) -> PASS igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_color@pipe-b-ctm-blue-to-red: shard-apl: DMESG-WARN (fdo#108549) -> PASS +21 igt@kms_cursor_crc@cursor-256x256-suspend: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +3 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS +6 igt@kms_frontbuffer_tracking@fbc-badstride: shard-skl: FAIL (fdo#105682) -> PASS igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt: shard-skl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-skl: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1
[Intel-gfx] [PATCH v2 1/2] drm/i915: Add function to check for linear surfaces
A framebuffer can comprise surfaces with distinct tiling formats,
making checks against modifier alone insufficient. Make use of a
function to identify a linear surface based on both modifier and color
plane.
v2: Typo fix
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_display.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe045abb6472..25e5402efd52 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2205,6 +2205,11 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
return new_offset;
}
+static inline bool is_surface_linear(uint64_t modifier, int color_plane)
+{
+ return modifier == DRM_FORMAT_MOD_LINEAR;
+}
+
static u32 intel_adjust_aligned_offset(int *x, int *y,
const struct drm_framebuffer *fb,
int color_plane,
@@ -2217,7 +,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
WARN_ON(new_offset > old_offset);
- if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
+ if (!is_surface_linear(fb->modifier, color_plane)) {
unsigned int tile_size, tile_width, tile_height;
unsigned int pitch_tiles;
@@ -2281,14 +2286,13 @@ static u32 intel_compute_aligned_offset(struct
drm_i915_private *dev_priv,
unsigned int rotation,
u32 alignment)
{
- uint64_t fb_modifier = fb->modifier;
unsigned int cpp = fb->format->cpp[color_plane];
u32 offset, offset_aligned;
if (alignment)
alignment--;
- if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
+ if (!is_surface_linear(fb->modifier, color_plane)) {
unsigned int tile_size, tile_width, tile_height;
unsigned int tile_rows, tiles, pitch_tiles;
@@ -2525,7 +2529,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
tile_size);
offset /= tile_size;
- if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
+ if (!is_surface_linear(fb->modifier, i)) {
unsigned int tile_width, tile_height;
unsigned int pitch_tiles;
struct drm_rect r;
--
2.14.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: HPD IRQ storm detection fixes
== Series Details == Series: drm/i915: HPD IRQ storm detection fixes URL : https://patchwork.freedesktop.org/series/51556/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST Okay! Commit: drm/i915: Add short HPD IRQ storm detection for non-MST systems -drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3714:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Plane Input CSC for ICL (rev3)
== Series Details == Series: Enable Plane Input CSC for ICL (rev3) URL : https://patchwork.freedesktop.org/series/51463/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10587 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51463/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_10587 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-skl-6700k2: PASS -> INCOMPLETE (fdo#104108, k.org#199541, fdo#105524) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-icl-u: NOTRUN -> FAIL (fdo#103375) +1 Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541 == Participating hosts (46 -> 44) == Additional (1): fi-icl-u Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5038 -> Patchwork_10587 CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10587: ca48ad67d283f6b861e6acfbe8ba7b6cfba5ebae @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ca48ad67d283 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion 99febf0a6212 drm/i915/icl: Define Plane Input CSC Coefficient Registers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10587/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for attempts at catching mmu_notifer deadlocks
== Series Details == Series: attempts at catching mmu_notifer deadlocks URL : https://patchwork.freedesktop.org/series/51522/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10579_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10579_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10579_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10579_full: === IGT changes === Possible regressions igt@gem_userptr_blits@dmabuf-sync: shard-kbl: PASS -> DMESG-WARN +9 igt@gem_userptr_blits@map-fixed-invalidate-busy: shard-glk: PASS -> DMESG-WARN +6 igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: shard-apl: PASS -> DMESG-WARN +6 shard-skl: PASS -> DMESG-WARN +5 igt@gem_userptr_blits@sync-unmap-after-close: shard-hsw: PASS -> DMESG-WARN +6 igt@gem_userptr_blits@sync-unmap-cycles: shard-snb: PASS -> DMESG-WARN +9 shard-skl: NOTRUN -> DMESG-WARN +1 igt@kms_flip_tiling@flip-to-yf-tiled: shard-skl: NOTRUN -> FAIL == Known issues == Here are the changes found in Patchwork_10579_full that come from known issues: === IGT changes === Issues hit igt@gem_userptr_blits@readonly-unsync: shard-skl: PASS -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-hsw: PASS -> DMESG-WARN (fdo#107956) igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge: shard-apl: PASS -> DMESG-WARN (fdo#108549) +19 igt@kms_color@pipe-a-degamma: shard-apl: PASS -> FAIL (fdo#108145, fdo#104782) igt@kms_color@pipe-b-degamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-128x128-random: shard-apl: PASS -> FAIL (fdo#103232) +6 igt@kms_cursor_crc@cursor-128x128-suspend: shard-apl: PASS -> FAIL (fdo#103232, fdo#103191) igt@kms_cursor_crc@cursor-256x256-random: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-sliding: shard-glk: PASS -> FAIL (fdo#103232) +5 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled: shard-skl: NOTRUN -> FAIL (fdo#103184) igt@kms_flip_tiling@flip-changes-tiling-yf: shard-skl: PASS -> FAIL (fdo#108303, fdo#108228) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) +7 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: PASS -> FAIL (fdo#103167) +3 igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +2 igt@kms_plane@pixel-format-pipe-c-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166) igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108) igt@kms_plane@plane-position-covered-pipe-a-planes: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_plane@plane-position-covered-pipe-c-planes: shard-apl: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +2 igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103166) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@kms_universal_plane@universal-plane-pipe-c-functional: shard-snb: SKIP -> INCOMPLETE (fdo#105411) igt@pm_backlight@fade_with_suspend: shard-skl: NOTRUN -> FAIL (fdo#107847) igt@pm_rpm@dpms-mode-unset-lpsp: shard-skl: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-apl:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Plane Input CSC for ICL (rev3)
== Series Details == Series: Enable Plane Input CSC for ICL (rev3) URL : https://patchwork.freedesktop.org/series/51463/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers Okay! Commit: drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev3)
== Series Details == Series: Enable Plane Input CSC for ICL (rev3) URL : https://patchwork.freedesktop.org/series/51463/ State : warning == Summary == $ dim checkpatch origin/drm-tip 99febf0a6212 drm/i915/icl: Define Plane Input CSC Coefficient Registers -:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #54: FILE: drivers/gpu/drm/i915/i915_reg.h:6603: +#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #54: FILE: drivers/gpu/drm/i915/i915_reg.h:6603: +#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:70: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #70: FILE: drivers/gpu/drm/i915/i915_reg.h:6619: +#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:70: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #70: FILE: drivers/gpu/drm/i915/i915_reg.h:6619: +#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:86: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #86: FILE: drivers/gpu/drm/i915/i915_reg.h:6635: +#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) -:86: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #86: FILE: drivers/gpu/drm/i915/i915_reg.h:6635: +#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) total: 0 errors, 0 warnings, 6 checks, 62 lines checked ca48ad67d283 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Add function to check for linear surfaces
== Series Details == Series: series starting with [1/2] drm/i915: Add function to check for linear surfaces URL : https://patchwork.freedesktop.org/series/51550/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10586 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10586 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10586, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51550/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10586: === IGT changes === Possible regressions igt@debugfs_test@read_all_entries: fi-icl-u: NOTRUN -> FAIL fi-blb-e6850: PASS -> FAIL fi-kbl-soraka: PASS -> FAIL igt@gem_exec_suspend@basic-s3: fi-ilk-650: PASS -> DMESG-WARN igt@kms_addfb_basic@bo-too-small-due-to-tiling: fi-kbl-x1275: PASS -> FAIL +3 fi-kbl-guc: PASS -> FAIL +3 igt@kms_addfb_basic@size-max: fi-apl-guc: PASS -> FAIL +38 fi-kbl-8809g: PASS -> FAIL +3 igt@kms_addfb_basic@small-bo: fi-kbl-7560u: PASS -> FAIL +40 fi-bwr-2160:PASS -> FAIL +25 igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: PASS -> FAIL +40 igt@kms_chamelium@hdmi-crc-fast: fi-skl-6700k2: PASS -> FAIL +40 igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: fi-hsw-4770r: PASS -> FAIL +37 fi-cfl-8700k: PASS -> FAIL +38 igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: fi-skl-guc: PASS -> FAIL +39 fi-whl-u: PASS -> FAIL +40 igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: fi-bsw-n3050: PASS -> FAIL +25 fi-hsw-4770:PASS -> FAIL +38 igt@kms_flip@basic-flip-vs-dpms: fi-ilk-650: PASS -> FAIL +30 fi-skl-6770hq: PASS -> FAIL +38 igt@kms_flip@basic-flip-vs-modeset: fi-cnl-u: PASS -> FAIL +40 igt@kms_flip@basic-flip-vs-wf_vblank: fi-hsw-peppy: PASS -> FAIL +37 fi-skl-6260u: PASS -> FAIL +38 igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-icl-u2: PASS -> FAIL +39 igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: fi-bxt-j4205: PASS -> FAIL +38 fi-skl-6700hq: PASS -> FAIL +40 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-ivb-3520m: PASS -> FAIL +36 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-elk-e7500: PASS -> FAIL +25 fi-byt-n2820: PASS -> FAIL +31 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-bsw-kefka: PASS -> FAIL +32 fi-bdw-5557u: PASS -> FAIL +37 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-bdw-gvtdvm: PASS -> FAIL +34 fi-gdg-551: PASS -> FAIL +25 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c: fi-kbl-7567u: PASS -> FAIL +38 fi-skl-gvtdvm: PASS -> FAIL +35 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence: fi-glk-dsi: PASS -> FAIL +39 igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-cfl-guc: PASS -> FAIL +38 igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL +30 fi-cfl-s3: PASS -> FAIL +40 igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-bxt-dsi: PASS -> FAIL +39 igt@kms_psr@cursor_plane_move: fi-kbl-r: PASS -> FAIL +40 igt@pm_rpm@basic-pci-d3-state: fi-skl-6600u: PASS -> FAIL +40 fi-byt-j1900: PASS -> FAIL +32 fi-gdg-551: SKIP -> FAIL +2 igt@pm_rpm@basic-rte: fi-skl-iommu: PASS -> FAIL +38 fi-glk-j4005: PASS -> FAIL +36 fi-skl-gvtdvm: SKIP -> FAIL +2 fi-elk-e7500: SKIP -> FAIL +3 fi-ilk-650: SKIP -> FAIL +2 fi-bdw-gvtdvm: SKIP -> FAIL +2 fi-bwr-2160:SKIP -> FAIL +2 igt@pm_rpm@module-reload: fi-ivb-3520m: SKIP -> FAIL +2 Warnings igt@debugfs_test@read_all_entries: fi-icl-u2: DMESG-WARN (fdo#108070) -> FAIL igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> FAIL igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000) -> FAIL igt@prime_vgem@basic-fence-flip: fi-hsw-4770r: PASS -> SKIP fi-kbl-7500u: PASS -> SKIP fi-cfl-8700k: PASS -> SKIP fi-skl-guc: PASS -> SKIP fi-cfl-guc: PASS
[Intel-gfx] [CI 6/7] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8380044affed..6f66a38ba0b2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -635,9 +635,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk;
+ u16 dsc_max_output_bpp = 0;
+ u8 dsc_slice_count = 0;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
@@ -660,7 +663,33 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(target_clock, 18);
- if (mode_rate > max_rate || target_clock > max_dotclk)
+ /*
+* Output bpp is stored in 6.4 format so right shift by 4 to get the
+* integer value since we support only integer values of bpp.
+*/
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ if (intel_dp_is_edp(intel_dp)) {
+ dsc_max_output_bpp =
+ drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd)
>> 4;
+ dsc_slice_count =
+
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
+ true);
+ } else {
+ dsc_max_output_bpp =
+ intel_dp_dsc_get_output_bpp(max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay) >>
4;
+ dsc_slice_count =
+ intel_dp_dsc_get_slice_count(intel_dp,
+target_clock,
+mode->hdisplay);
+ }
+ }
+
+ if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count))
||
+ target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
if (mode->clock < 1)
--
2.18.0
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[Intel-gfx] [CI 4/7] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding DPCD registers.
v4:
* Add helper to give line buf bit depth (Manasi)
* Correct the bit masking in color depth helper (manasi)
v3:
* Use SLICE_CAP_2 for DP (Anusha)
v2:
* Add DSC sink support macro (Jani N)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/drm_dp_helper.c | 90 +
include/drm/drm_dp_helper.h | 30 +++
2 files changed, 120 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 37c01b6076ec..6d483487f2b4 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1352,3 +1352,93 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
return 0;
}
EXPORT_SYMBOL(drm_dp_read_desc);
+
+/**
+ * DRM DP Helpers for DSC
+ */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp)
+{
+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
+
+ if (is_edp) {
+ /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count
*/
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ } else {
+ /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
+
+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
+ return 24;
+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
+ return 20;
+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
+ return 16;
+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
+ return 12;
+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
+ return 10;
+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
+ return 8;
+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
+ return 6;
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
+
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH -
DP_DSC_SUPPORT];
+
+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
+ case DP_DSC_LINE_BUF_BIT_DEPTH_9:
+ return 9;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_10:
+ return 10;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_11:
+ return 11;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_12:
+ return 12;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_13:
+ return 13;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_14:
+ return 14;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_15:
+ return 15;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_16:
+ return 16;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_8:
+ return 8;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
+
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
+
+ if (color_depth & DP_DSC_12_BPC)
+ return 12;
+ if (color_depth & DP_DSC_10_BPC)
+ return 10;
+ if (color_depth & DP_DSC_8_BPC)
+ return 8;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index dd33d59739f8..7f7f5b965466 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1067,6 +1067,36 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
}
+/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp);
+u8 drm_dp_dsc_sink_line_buf_depth(const u8
[Intel-gfx] [CI 3/7] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is cached in intel_dp so that
capability information can be used during DSC configuration
phase during compute_config phase of the modeset.
For eDP, this caching happens during the eDP initialization.
This caching is done only for eDP and DP rev >= 1.4
v5:
* Fix the block comment (Gaurav)
* Fix the commit message DSC DPCD addresses (Gaurav)
* Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha)
v4:
* Cache these only for Gen >= 11
v3:
* Remove the dsc_sink_support field in intel_dp (Jani N)
v2:
* Clear the cached registers on hotplug always (Jani N)
* Combine the eDP and DP caching in same function (Jani N)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Daniel Vetter
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 32
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8e64f149ab09..55e070b85c02 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3956,6 +3956,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
return intel_dp->dpcd[DP_DPCD_REV] != 0;
}
+static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
+{
+ /*
+*Clear the cached register set to avoid using stale values
+* for the sinks that do not support DSC.
+*/
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+
+ /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
+ intel_dp->edp_dpcd[0] >= DP_EDP_14) {
+ if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
+intel_dp->dsc_dpcd,
+sizeof(intel_dp->dsc_dpcd)) < 0)
+ DRM_ERROR("Failed to read DPCD register 0x%x\n",
+ DP_DSC_SUPPORT);
+
+ DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
+ (int)sizeof(intel_dp->dsc_dpcd),
+ intel_dp->dsc_dpcd);
+ }
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp)
{
@@ -4032,6 +4055,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_common_rates(intel_dp);
+ /* Read the eDP DSC DPCD registers */
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
return true;
}
@@ -5126,6 +5153,7 @@ intel_dp_detect(struct drm_connector *connector,
if (status == connector_status_disconnected) {
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
if (intel_dp->is_mst) {
DRM_DEBUG_KMS("MST device may have disappeared %d vs
%d\n",
@@ -5151,6 +5179,10 @@ intel_dp_detect(struct drm_connector *connector,
intel_dp_print_rates(intel_dp);
+ /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
+ if (INTEL_GEN(dev_priv) >= 11)
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
drm_dp_read_desc(_dp->aux, _dp->desc,
drm_dp_is_branch(intel_dp->dpcd));
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308729b4..4cacf0e3fa17 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1109,6 +1109,7 @@ struct intel_dp {
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
/* source rates */
int num_source_rates;
const int *source_rates;
--
2.18.0
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[Intel-gfx] [CI 2/7] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
This patch defines the DP DSC receiver capability size that gives total number of DP DSC DPCD registers. This also adds a missing #defines for DP DSC support missed in the commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") v3: * MIN_SLICE_WIDTH = 2560 (Anusha) * Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 v2: * Add SHIFT define and DECOMPRESSION_EN define missed in prev patch Cc: dri-de...@lists.freedesktop.org Cc: Jani Nikula Cc: Ville Syrjala Cc: Anusha Srivatsa Cc: Gaurav K Singh Signed-off-by: Manasi Navare Reviewed-by: Anusha Srivatsa --- include/drm/drm_dp_helper.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 9ad98e8d9ede..dd33d59739f8 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -231,6 +231,8 @@ #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -279,6 +281,8 @@ # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) #define DP_DSC_MAX_SLICE_WIDTH 0x06C +#define DP_DSC_MIN_SLICE_WIDTH_VALUE2560 +#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 #define DP_DSC_SLICE_CAP_2 0x06D # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) @@ -477,6 +481,7 @@ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ +# define DP_DECOMPRESSION_EN(1 << 0) #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) @@ -965,6 +970,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573348b3..64cca0a83cf7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10903,6 +10903,7 @@ enum skl_power_gate {
#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame)
<< 20)
#define DSC_SLICE_PER_LINE(slice_per_line)((slice_per_line) << 16)
#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
((slice_chunk_size) << 0)
--
2.18.0
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[Intel-gfx] [CI 5/7] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as input arguments
so that this can be called in intel_dp_mode_valid (Manasi)
v5:
* Get the max slice width from DPCD
* Check against Min_Slice_width of 2560 (Anusha)
v4:
* #defines for PPR in slice count helper (Gaurav)
v3:
* Simply logic for bpp (DK)
* Limit the valid slice count by max supported by Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Dhinakaran Pandiyan
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 104 +++
drivers/gpu/drm/i915/intel_drv.h | 4 ++
2 files changed, 108 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 55e070b85c02..8380044affed 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -45,6 +45,17 @@
#define DP_DPRX_ESI_LEN 14
+/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
+#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+
+/* DP DSC throughput values used for slice count calculations KPixels/s */
+#define DP_DSC_PEAK_PIXEL_RATE 272
+#define DP_DSC_MAX_ENC_THROUGHPUT_034
+#define DP_DSC_MAX_ENC_THROUGHPUT_140
+
+/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
+#define DP_DSC_FEC_OVERHEAD_FACTOR 976
+
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
@@ -93,6 +104,14 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
};
+/* Constants for DP DSC configurations */
+static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
+
+/* With Single pipe configuration, HW is capable of supporting maximum
+ * of 4 slices per line.
+ */
+static const u8 valid_dsc_slicecount[] = {1, 2, 4};
+
/**
* intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
PCH)
* @intel_dp: DP struct
@@ -4162,6 +4181,91 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8
*sink_irq_vector)
DP_DPRX_ESI_LEN;
}
+u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
+ int mode_clock, int mode_hdisplay)
+{
+ u16 bits_per_pixel, max_bpp_small_joiner_ram;
+ int i;
+
+ /*
+* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
+* (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
+* FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
+* for MST -> TimeSlotsPerMTP has to be calculated
+*/
+ bits_per_pixel = (link_clock * lane_count * 8 *
+ DP_DSC_FEC_OVERHEAD_FACTOR) /
+ mode_clock;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
+ mode_hdisplay;
+
+ /*
+* Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
+* check, output bpp from small joiner RAM check)
+*/
+ bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+
+ /* Error out if the max bpp is less than smallest allowed valid bpp */
+ if (bits_per_pixel < valid_dsc_bpp[0]) {
+ DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
+ return 0;
+ }
+
+ /* Find the nearest match in the array of known BPPs from VESA */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
+
+ /*
+* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
+* fractional part is 0
+*/
+ return bits_per_pixel << 4;
+}
+
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock,
+ int mode_hdisplay)
+{
+ u8 min_slice_count, i;
+ int max_slice_width;
+
+ if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_0);
+ else
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_1);
+
+ max_slice_width =
[Intel-gfx] [CI 7/7] drm/dp: Define payload size for DP SDP PPS packet
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Reviewed-by: Harry Wentland
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 7f7f5b965466..730243dd41e2 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1001,6 +1001,7 @@ struct dp_sdp_header {
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
struct edp_vsc_psr {
struct dp_sdp_header sdp_header;
--
2.18.0
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[Intel-gfx] [PATCH 2/2] drm/i915: Add short HPD IRQ storm detection for non-MST systems
Unfortunately, it seems that the HPD IRQ storm problem from the early
days of Intel GPUs was never entirely solved, only mostly. Within the
last couple of days, I got a bug report from one of our customers who
had been having issues with their machine suddenly booting up very
slowly after having updated. The amount of time it took to boot went
from around 30 seconds, to over 6 minutes consistently.
After some investigation, I discovered that i915 was reporting massive
amounts of short HPD IRQ spam on this system from the DisplayPort port,
despite there not being anything actually connected. The symptoms would
start with one "long" HPD IRQ being detected at boot:
[1.891398] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0044, dig 0x0044, pins 0x00a0
[1.891436] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long
[1.891472] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN
5 - cnt: 0
[1.891508] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - long
[1.891544] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN
7 - cnt: 0
[1.891592] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long
[1.891628] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port D - long
…
followed by constant short IRQs afterwards:
[1.895091] [drm:intel_encoder_hotplug [i915]] [CONNECTOR:66:DP-1] status
updated from unknown to disconnected
[1.895129] [drm:i915_hotplug_work_func [i915]] Connector DP-3 (pin 7)
received hotplug event.
[1.895165] [drm:intel_dp_detect [i915]] [CONNECTOR:72:DP-3]
[1.895275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.895312] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.895762] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.895799] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.896239] [drm:intel_dp_aux_xfer [i915]] dp_aux_ch timeout status
0x71450085
[1.896293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.896330] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.896781] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.896817] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.897275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
The customer's system in question has a GM45 GPU, which is apparently
well known for hotplugging storms.
So, workaround this impressively broken hardware by detecting short IRQ
storms using a separate threshold and count, one that is much higher
then the threshold for long IRQs. We default to a threshold of 50 short
pulses within the timespan of a second, which should amount to about
100ms of constant pulsing. This should be a good middle ground between
avoiding detecting false IRQ storms, while still catching short IRQ
storms quickly enough to minimize the amount of time we'll stutter every
time hotplugging gets re-enabled and immediately disabled by another
short IRQ storm.
And just to be extra safe: we don't enable this by default on systems
with MST support. There's too high of a chance of MST support triggering
storm detection, and systems that are new enough to support MST are a
lot less likely to have issues with IRQ storms anyway.
As a note: this patch was tested using a ThinkPad T450s and a Chamelium
to simulate the short IRQ storms.
Signed-off-by: Lyude Paul
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 89 +++-
drivers/gpu/drm/i915/i915_drv.h | 15 +++--
drivers/gpu/drm/i915/i915_irq.c | 14 -
drivers/gpu/drm/i915/intel_hotplug.c | 84 --
4 files changed, 150 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b4744a68cd88..84e89fbd55fb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4566,21 +4566,24 @@ static const struct file_operations i915_forcewake_fops
= {
.release = i915_forcewake_release,
};
-static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
+static int i915_hpd_storm_show(struct seq_file *m, bool long_hpd)
{
struct drm_i915_private *dev_priv = m->private;
struct i915_hotplug *hotplug = _priv->hotplug;
+ const unsigned int threshold = long_hpd ?
+ hotplug->long_hpd_storm_threshold :
+ hotplug->short_hpd_storm_threshold;
- seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
+ seq_printf(m, "Threshold: %d\n", threshold);
seq_printf(m, "Detected: %s\n",
yesno(delayed_work_pending(>reenable_work)));
[Intel-gfx] [PATCH 0/2] drm/i915: HPD IRQ storm detection fixes
IMPORTANT - As a note: I have not had the customer who this second patch is for test this yet, I'm sending this ahead of time to make sure this is something that isn't too crazy for upstream to accept. I'm not planning on pushing this after review until I've verified this actually fixes their problems. This series contains a fix for a problem which is very difficult to reproduce under normal circumstances without specialized testing hardware, along with a fix that seems to be required for some especially rebellious GM45 laptops. Lyude Paul (2): drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST drm/i915: Add short HPD IRQ storm detection for non-MST systems drivers/gpu/drm/i915/i915_debugfs.c | 89 +++- drivers/gpu/drm/i915/i915_drv.h | 15 +++-- drivers/gpu/drm/i915/i915_irq.c | 14 - drivers/gpu/drm/i915/intel_hotplug.c | 87 --- 4 files changed, 152 insertions(+), 53 deletions(-) -- 2.17.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST
Turns out that if you trigger an HPD storm on a system that has an MST
topology connected to it, you'll end up causing the kernel to eventually
hit a NULL deref:
[ 332.339041] BUG: unable to handle kernel NULL pointer dereference at
00ec
[ 332.340906] PGD 0 P4D 0
[ 332.342750] Oops: [#1] SMP PTI
[ 332.344579] CPU: 2 PID: 25 Comm: kworker/2:0 Kdump: loaded Tainted: G
O 4.18.0-rc3short-hpd-storm+ #2
[ 332.346453] Hardware name: LENOVO 20BWS1KY00/20BWS1KY00, BIOS JBET71WW (1.35
) 09/14/2018
[ 332.348361] Workqueue: events intel_hpd_irq_storm_reenable_work [i915]
[ 332.350301] RIP: 0010:intel_hpd_irq_storm_reenable_work.cold.3+0x2f/0x86
[i915]
[ 332.352213] Code: 00 00 ba e8 00 00 00 48 c7 c6 c0 aa 5f a0 48 c7 c7 d0 73
62 a0 4c 89 c1 4c 89 04 24 e8 7f f5 af e0 4c 8b 04 24 44 89 f8 29 e8 <41> 39 80
ec 00 00 00 0f 85 43 13 fc ff 41 0f b6 86 b8 04 00 00 41
[ 332.354286] RSP: 0018:c9147e48 EFLAGS: 00010006
[ 332.356344] RAX: 0005 RBX: 8802c226c9d4 RCX: 0006
[ 332.358404] RDX: RSI: 0082 RDI: 88032dc95570
[ 332.360466] RBP: 0005 R08: R09: 88031b3dc840
[ 332.362528] R10: R11: 00031a069602 R12: 8802c226ca20
[ 332.364575] R13: 8802c2268000 R14: 880310661000 R15: 000a
[ 332.366615] FS: () GS:88032dc8()
knlGS:
[ 332.368658] CS: 0010 DS: ES: CR0: 80050033
[ 332.370690] CR2: 00ec CR3: 0200a003 CR4: 003606e0
[ 332.372724] DR0: DR1: DR2:
[ 332.374773] DR3: DR6: fffe0ff0 DR7: 0400
[ 332.376798] Call Trace:
[ 332.378809] process_one_work+0x1a1/0x350
[ 332.380806] worker_thread+0x30/0x380
[ 332.382777] ? wq_update_unbound_numa+0x10/0x10
[ 332.384772] kthread+0x112/0x130
[ 332.386740] ? kthread_create_worker_on_cpu+0x70/0x70
[ 332.388706] ret_from_fork+0x35/0x40
[ 332.390651] Modules linked in: i915(O) vfat fat joydev btusb btrtl btbcm
btintel bluetooth ecdh_generic iTCO_wdt wmi_bmof i2c_algo_bit drm_kms_helper
intel_rapl syscopyarea sysfillrect x86_pkg_temp_thermal sysimgblt coretemp
fb_sys_fops crc32_pclmul drm psmouse pcspkr mei_me mei i2c_i801 lpc_ich
mfd_core i2c_core tpm_tis tpm_tis_core thinkpad_acpi wmi tpm rfkill video
crc32c_intel serio_raw ehci_pci xhci_pci ehci_hcd xhci_hcd [last unloaded: i915]
[ 332.394963] CR2: 00ec
This appears to be due to the fact that with an MST topology, not all
intel_connector structs will have ->encoder set. So, fix this by
skipping connectors without encoders in
intel_hpd_irq_storm_reenable_work().
For those wondering, this bug was found on accident while simulating HPD
storms using a Chamelium connected to a ThinkPad T450s (Broadwell).
Signed-off-by: Lyude Paul
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_hotplug.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
b/drivers/gpu/drm/i915/intel_hotplug.c
index 648a13c6043c..7d21aac10d16 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -228,7 +228,8 @@ static void intel_hpd_irq_storm_reenable_work(struct
work_struct *work)
drm_for_each_connector_iter(connector, _iter) {
struct intel_connector *intel_connector =
to_intel_connector(connector);
- if (intel_connector->encoder->hpd_pin == pin) {
+ if (intel_connector->encoder &&
+ intel_connector->encoder->hpd_pin == pin) {
if (connector->polled !=
intel_connector->polled)
DRM_DEBUG_DRIVER("Reenabling HPD on
connector %s\n",
connector->name);
--
2.17.2
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Re: [Intel-gfx] [PATCH] drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
On Thu, Oct 25, 2018 at 12:36 PM Nathan Chancellor
wrote:
>
> This warning is disabled by default in scripts/Makefile.extrawarn when
> W= is not provided but this Makefile adds -Wall after this warning is
> disabled so it shows up in the build when it shouldn't:
>
> In file included from drivers/gpu/drm/i915/intel_breadcrumbs.c:895:
> drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c:350:34: error:
> variable 'wq' is uninitialized when used within its own initialization
> [-Werror,-Wuninitialized]
> DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
> ^~
> ./include/linux/wait.h:74:63: note: expanded from macro
> 'DECLARE_WAIT_QUEUE_HEAD_ONSTACK'
> struct wait_queue_head name = __WAIT_QUEUE_HEAD_INIT_ONSTACK(name)
> ^~~~
> ./include/linux/wait.h:72:33: note: expanded from macro
> '__WAIT_QUEUE_HEAD_INIT_ONSTACK'
> ({ init_waitqueue_head(); name; })
>^~~~
> 1 error generated.
>
> This warning looks to be a false positive given that init_waitqueue_head
> initializes name before it is used. Rather than disable the warning for
> the full folder like commit 46e2068081e9 ("drm/i915: Disable some extra
cc author/reviewer of 46e2068081e9.
I'm fine with the patch as is, unless others prefer to disable it for
the whole subdir? We could be playing whack-a-mole in the future
disabling this warning for other translation units.
> clang warnings"), just disable it for the one problematic file because
> it could be a useful warning for other cases.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/220
> Signed-off-by: Nathan Chancellor
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 1c2857f13ad4..f36c420afb99 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -26,6 +26,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
>
> # Fine grained warnings disable
> CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
> +CFLAGS_intel_breadcrumbs.o = $(call cc-disable-warning, uninitialized)
> CFLAGS_intel_fbdev.o = $(call cc-disable-warning, override-init)
>
> subdir-ccflags-y += \
> --
> 2.19.1
>
--
Thanks,
~Nick Desaulniers
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Re: [Intel-gfx] [v4 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers
On Fri, Oct 26, 2018 at 03:33:37AM +0530, Uma Shankar wrote:
> Defined the plane input csc coefficient registers and macros.
> 6 registers are used to program a total of 9 coefficients,
> added macros to define each of them for all the planes
> supporting the feature on pipes. On ICL, bottom 3 planes
> have this capability.
>
> v2: Segregated the register macro definition as separate patch
> as per Maarten's suggestion.
>
> v3: Removed a redundant 3rd Pipe register definition and
> simplified the equally spaced register definition by adding an
> offset as per Matt's comment.
>
> v4: No Change
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h | 50
> +
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 69eb573..d806e6b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6569,6 +6569,7 @@ enum {
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
> #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> +#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> #define PLANE_COLOR_PIPE_CSC_ENABLE(1 << 23) /* Pre-ICL */
> #define PLANE_COLOR_CSC_MODE_BYPASS(0 << 17)
> #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
> @@ -6585,6 +6586,55 @@ enum {
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> +/* Input CSC Register Definitions */
> +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
> + _PLANE_INPUT_CSC_RY_GY_1_B)
> +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> + _PLANE_INPUT_CSC_RY_GY_2_B)
> +
> +#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)\
The _REG suffix on these names could probably be dropped to make them a
bit shorter. But otherwise, these match all the offsets I see in the
bspec, so
Reviewed-by: Matt Roper
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
> + _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
> + _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
>
> #define _PLANE_CTL_1_B 0x71180
> #define _PLANE_CTL_2_B 0x71280
> --
> 1.9.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
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--
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Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [v4 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
On Fri, Oct 26, 2018 at 03:33:38AM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> Note: This is currently untested and floated to get an early feedback
> on the design and implementation for this feature. In parallel,
> I will test this on actual ICL hardware and confirm with planar
> formats.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_color.c | 79
>
> drivers/gpu/drm/i915/intel_display.c | 23 ---
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 98 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..3a52d92 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e08
>
> +#define ROFF(x) (((x) & 0x) << 16)
> +#define GOFF(x) (((x) & 0x) << 0)
> +#define BOFF(x) (((x) & 0x) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x800
> +#define PREOFF_YUV_TO_RGB_ME 0xF00
> +#define PREOFF_YUV_TO_RGB_LO 0x800
Doesn't bit #12 need to be set for each of these values (0x1800, 0x1F00,
0x1800)? At least that's what I came up with based on the assumption
that input CSC is programmed the same way as pipe CSC, but I might be
overlooking or miscalculating something.
The pipe CSC page gives an example of converting YUV to RGB with a table
that matches your csc matrix below, and a note "Program the CSC
Pre-Offsets to -1/2, -1/16, and -1/2."
The bspec indicates the register values here are 13-bits (12:0 in the
register dword) and are 2's complement fractions allowing values between
-1 and 1 (exclusive). So I take that to mean:
1/2 = 0 1000
-1/2 (one's complement) = 1 0111
-1/2 (two's complement) = 1 1000 = 0x1800
and
1/16 = 0 0001
-1/16 (one's complement) = 1 1110
-1/16 (two's complement) = 1 = 0x1F00
Anyway, it would probably be good to give a comment indicating what the
human-readable values you're using are supposed to be and an indication
of how the register is programmed to represent those values.
Matt
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
> + /* BT.601 full range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 7800, 0x0,
> + 0x8B28, 7800, 0x9AC0,
> + 0x0, 7800, 0x7DD8,
> + },
> + /* BT.709 full range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 7800, 0x0,
> + 0x9EF8, 7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /* BT.601 Limted range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 7950, 0x0,
> + 0x8CB8, 7918, 0x9C40,
> + 0x0, 7918, 0x7FC8,
> + },
> + /* BT.709 Limited range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT709] = {
> +
[Intel-gfx] [v4 0/2] Enable Plane Input CSC for ICL
This patch series enables plane input csc feature for ICL. This is needed for YUV to RGB conversion on bottom 3 planes on ICL, other planes are handled in the legacy way using fixed function hardware. This series enables color conversion for Full Range YUV data, limited range handling will be done as a separate patch. v2: Separated the patch into 2 parts as per Maarten's comments. Addressed Ville and Maarten's review comment. v3: Redesigned the register macro definition as per Matt's comment. Addressed Maarten's review comment. v4: Added support for Limited Range Color Handling. Note: This is currently untested and floated to get feedback on the design and implementation for this feature. In parallel, I will test this on actual ICL hardware and confirm with planar formats. Uma Shankar (2): drm/i915/icl: Define Plane Input CSC Coefficient Registers drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion drivers/gpu/drm/i915/i915_reg.h | 50 +++ drivers/gpu/drm/i915/intel_color.c | 79 drivers/gpu/drm/i915/intel_display.c | 23 --- drivers/gpu/drm/i915/intel_drv.h | 2 + 4 files changed, 148 insertions(+), 6 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v4 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It programs the coefficients and enables
the plane input csc unit in hardware.
Note: This is currently untested and floated to get an early feedback
on the design and implementation for this feature. In parallel,
I will test this on actual ICL hardware and confirm with planar
formats.
v2: Addressed Maarten's and Ville's review comments and added the
coefficients in a 2D array instead of independent Macros.
v3: Added individual coefficient matrix (9 values) instead of 6
register values as per Maarten's comment. Also addresed a shift
issue with B channel coefficient.
v4: Added support for Limited Range Color Handling
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 79
drivers/gpu/drm/i915/intel_display.c | 23 ---
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 98 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 5127da2..3a52d92 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -57,6 +57,15 @@
#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
#define CSC_RGB_TO_YUV_BV 0x1e08
+#define ROFF(x) (((x) & 0x) << 16)
+#define GOFF(x) (((x) & 0x) << 0)
+#define BOFF(x) (((x) & 0x) << 16)
+
+/* Preoffset values for YUV to RGB Conversion */
+#define PREOFF_YUV_TO_RGB_HI 0x800
+#define PREOFF_YUV_TO_RGB_ME 0xF00
+#define PREOFF_YUV_TO_RGB_LO 0x800
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
return -EINVAL;
}
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ enum pipe pipe = crtc->pipe;
+ struct intel_plane *intel_plane =
+ to_intel_plane(plane_state->base.plane);
+ enum plane_id plane = intel_plane->id;
+
+ static const u16 input_csc_matrix[][9] = {
+ /* BT.601 full range YCbCr -> full range RGB */
+ [DRM_COLOR_YCBCR_BT601] = {
+ 0x7AF8, 7800, 0x0,
+ 0x8B28, 7800, 0x9AC0,
+ 0x0, 7800, 0x7DD8,
+ },
+ /* BT.709 full range YCbCr -> full range RGB */
+ [DRM_COLOR_YCBCR_BT709] = {
+ 0x7C98, 7800, 0x0,
+ 0x9EF8, 7800, 0xABF8,
+ 0x0, 0x7800, 0x7ED8,
+ },
+ };
+
+ /* Matrix for Limited Range to Full Range Conversion */
+ static const u16 input_csc_matrix_lr[][9] = {
+ /* BT.601 Limted range YCbCr -> full range RGB */
+ [DRM_COLOR_YCBCR_BT601] = {
+ 0x7CC8, 7950, 0x0,
+ 0x8CB8, 7918, 0x9C40,
+ 0x0, 7918, 0x7FC8,
+ },
+ /* BT.709 Limited range YCbCr -> full range RGB */
+ [DRM_COLOR_YCBCR_BT709] = {
+ 0x7EA8, 7950, 0x0,
+ 0x, 7918, 0xADA8,
+ 0x0, 0x7918, 0x6870,
+ },
+ };
+ const u16 *csc;
+
+ if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ csc = input_csc_matrix[plane_state->base.color_encoding];
+ else
+ csc = input_csc_matrix_lr[plane_state->base.color_encoding];
+
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 0), ROFF(csc[0]) |
+ GOFF(csc[1]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 1), BOFF(csc[2]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 2), ROFF(csc[3]) |
+ GOFF(csc[4]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 3), BOFF(csc[5]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 4), ROFF(csc[6]) |
+ GOFF(csc[7]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 5), BOFF(csc[8]));
+
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 0),
+ PREOFF_YUV_TO_RGB_HI);
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 1),
+ PREOFF_YUV_TO_RGB_ME);
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 2),
+ PREOFF_YUV_TO_RGB_LO);
+
+
[Intel-gfx] [v4 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.
v4: No Change
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 50 +
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573..d806e6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,6 +6569,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709(1 << 17)
@@ -6585,6 +6586,55 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A0x70278
#define _PLANE_NV12_BUF_CFG_2_A0x70378
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+_PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+_PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+_PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+_PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)\
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+_PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)\
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+_PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)\
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
--
1.9.1
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[Intel-gfx] [PATCH 1/2] drm/i915: Add function to check for linear surfaces
A framebuffer can comprise surfaces with distinct tiling formats,
making checks against modifier alone insufficient. Make use of a
function to identify a linear surface based on both modifier and color
plane.
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_display.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe045abb6472..5cf1dd0b741d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2205,6 +2205,11 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
return new_offset;
}
+static inline bool is_surface_linear(uint64_t modifier, int color_plane)
+{
+ return modifier == DRM_FORMAT_MOD_LINEAR;
+}
+
static u32 intel_adjust_aligned_offset(int *x, int *y,
const struct drm_framebuffer *fb,
int color_plane,
@@ -2217,7 +,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
WARN_ON(new_offset > old_offset);
- if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
+ if (!is_surface_linear(fb->modifier, color_plane)) {
unsigned int tile_size, tile_width, tile_height;
unsigned int pitch_tiles;
@@ -2281,14 +2286,13 @@ static u32 intel_compute_aligned_offset(struct
drm_i915_private *dev_priv,
unsigned int rotation,
u32 alignment)
{
- uint64_t fb_modifier = fb->modifier;
unsigned int cpp = fb->format->cpp[color_plane];
u32 offset, offset_aligned;
if (alignment)
alignment--;
- if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
+ if (!is_surface_linear(fb->modifier, color_plane)) {
unsigned int tile_size, tile_width, tile_height;
unsigned int tile_rows, tiles, pitch_tiles;
@@ -2525,7 +2529,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
tile_size);
offset /= tile_size;
- if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
+ if (is_surface_linear(fb->modifier, i)) {
unsigned int tile_width, tile_height;
unsigned int pitch_tiles;
struct drm_rect r;
--
2.14.1
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[Intel-gfx] [PATCH 2/2] drm/i915: Do not program aux plane offsets on gen11+
The PLANE_AUX_OFFSET mmio does not exist on ICL, do not program it. We'll
still calculate the aux offset as it is required for adjusing x-y offsets.
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_sprite.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cfaddc05fea6..a27d6f67c7c5 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -414,9 +414,11 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
(plane_state->color_plane[1].offset - surf_addr) |
aux_stride);
- I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->color_plane[1].y << 16) |
- plane_state->color_plane[1].x);
+
+ if (INTEL_GEN(dev_priv) < 11)
+ I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
+ (plane_state->color_plane[1].y << 16) |
+ plane_state->color_plane[1].x);
if (icl_is_hdr_plane(plane)) {
u32 cus_ctl = 0;
--
2.14.1
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Re: [Intel-gfx] [PATCH] drm/i915/userptr: Avoid struct_mutex recursion for mmu_invalidate_range_start
Chris Wilson writes:
> Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> notifiers") we have been able to report failure from
> mmu_invalidate_range_start which allows us to use a trylock on the
> struct_mutex to avoid potential recursion and report -EBUSY instead.
> Furthermore, this allows us to pull the work into the main callback and
> avoid the sleight-of-hand in using a workqueue to avoid lockdep.
>
> However, not all paths to mmu_invalidate_range_start are prepared to
> handle failure, so instead of reporting the recursion, deal with it.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108375
Does this address https://bugs.freedesktop.org/show_bug.cgi?id=108456 ?
> References: 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> notifiers")
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gem.c | 12 +-
> drivers/gpu/drm/i915/i915_gem_userptr.c | 219
> 3 files changed, 115 insertions(+), 120 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2d7761b8ac07..c3b94c3f930f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3076,8 +3076,8 @@ enum i915_mm_subclass { /* lockdep subclass for
> obj->mm.lock */
> I915_MM_SHRINKER
> };
>
> -void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> - enum i915_mm_subclass subclass);
> +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> + enum i915_mm_subclass subclass);
> void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
>
> enum i915_map_type {
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 93d09282710d..de7ccb3eb7b8 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2454,17 +2454,18 @@ __i915_gem_object_unset_pages(struct
> drm_i915_gem_object *obj)
> return pages;
> }
>
> -void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> - enum i915_mm_subclass subclass)
> +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> + enum i915_mm_subclass subclass)
> {
> struct sg_table *pages;
> + int ret = -EBUSY;
>
> if (i915_gem_object_has_pinned_pages(obj))
> - return;
> + return -EBUSY;
>
> GEM_BUG_ON(obj->bind_count);
> if (!i915_gem_object_has_pages(obj))
> - return;
> + return 0;
>
> /* May be called by shrinker from within get_pages() (on another bo) */
> mutex_lock_nested(>mm.lock, subclass);
> @@ -2480,8 +2481,11 @@ void __i915_gem_object_put_pages(struct
> drm_i915_gem_object *obj,
> if (!IS_ERR(pages))
> obj->ops->put_pages(obj, pages);
>
> + ret = 0;
> unlock:
> mutex_unlock(>mm.lock);
> +
> + return ret;
> }
>
> bool i915_sg_trim(struct sg_table *orig_st)
> diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/i915_gem_userptr.c
> index 2c9b284036d1..a8f3c304db55 100644
> --- a/drivers/gpu/drm/i915/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
> @@ -50,79 +50,84 @@ struct i915_mmu_notifier {
> struct hlist_node node;
> struct mmu_notifier mn;
> struct rb_root_cached objects;
> - struct workqueue_struct *wq;
> + struct i915_mm_struct *mm;
> };
>
> struct i915_mmu_object {
> struct i915_mmu_notifier *mn;
> struct drm_i915_gem_object *obj;
> struct interval_tree_node it;
> - struct list_head link;
> - struct work_struct work;
> - bool attached;
> };
>
> -static void cancel_userptr(struct work_struct *work)
> -{
> - struct i915_mmu_object *mo = container_of(work, typeof(*mo), work);
> - struct drm_i915_gem_object *obj = mo->obj;
> - struct work_struct *active;
> -
> - /* Cancel any active worker and force us to re-evaluate gup */
> - mutex_lock(>mm.lock);
> - active = fetch_and_zero(>userptr.work);
> - mutex_unlock(>mm.lock);
> - if (active)
> - goto out;
> -
> - i915_gem_object_wait(obj, I915_WAIT_ALL, MAX_SCHEDULE_TIMEOUT, NULL);
> -
> - mutex_lock(>base.dev->struct_mutex);
> -
> - /* We are inside a kthread context and can't be interrupted */
> - if (i915_gem_object_unbind(obj) == 0)
> - __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> - WARN_ONCE(i915_gem_object_has_pages(obj),
> - "Failed to release pages: bind_count=%d, pages_pin_count=%d,
> pin_global=%d\n",
> - obj->bind_count,
> - atomic_read(>mm.pages_pin_count),
> - obj->pin_global);
> -
> - mutex_unlock(>base.dev->struct_mutex);
> -
> -out:
> - i915_gem_object_put(obj);
> -}
> -
> static
Re: [Intel-gfx] [RFC v2] GuC firmware versioning change
On Mon, Oct 22, 2018 at 03:54:45PM -0700, Jeff McGee wrote: > See https://lists.freedesktop.org/archives/intel-gfx/2018-October/178452.html > for RFC v1 and the helpful feedback incorporated into this v2. thanks! I liked the new one. Acked-by: Rodrigo Vivi > > The GuC firmware team is proposing a change to the firmware versioning scheme. > The goal is to more accurately track the firmware interface to help users > manage dependencies on that interface. The proposed scheme is based on > semver.org. > > The proposed version number would consist of these 3 mandatory fields in order > of significance: MAJOR.MINOR.PATCH. Contrast this with the 2 fields in the > current version number: MAJOR.MINOR. The version block in the firmware header > will be refactored to contain these 3 fields so that i915 can continue to > verify the version before loading. The firmware file would adopt a change of > naming format to match: > > Current: _guc_ver_.bin (skl_guc_ver9_33.bin) > Proposed: _guc_ver__.bin (skl_guc_ver5_4_7.bin) > > The MAJOR number conforms to the major in semver.org. It increments on a > backwards incompatible change of the interface. The MAJOR number basically > works the same between the current and proposed versioning schemes. > > The MINOR number conforms to the minor in semver.org. It increments on a > backwards compatible change of the interface (new interfaces that are optional > to use). It will also increment on substantial new internal functionality that > doesn't affect the interface but should be called out to the user. It resets > to > 0 on a change of MAJOR. The MINOR number in the current versioning scheme > increments on any backwards compatible change. The proposed versioning scheme > breaks this into the MINOR number just described and the PATCH number below. > > The PATCH number conforms to the patch in semver.org. It increments on a > backwards compatible internal change, usually a bug fix. It resets to 0 on a > change of MINOR. > > The MAJOR.MINOR collectively define the interface version. Because the MINOR > may also increment on a substantial internal change, it doesn't always mark an > interface change, e.g. 4.5 and 4.6 may have identical interfaces. But the > determination of interface compatibility is unchanged, e.g. 4.6 is always > backwards compatible with 4.5. > > Each MAJOR.MINOR may continue to receive internal fixes along a branch even > after the main branch has moved on to another MAJOR.MINOR. Releases from these > fix-only branches increment only the PATCH number on that MAJOR.MINOR, and > therefore remain semantically consistent with the main branch. Consider an > example: > > v1.0.0 v1.0.1 v1.0.2 v1.1.0 v1.1.1 > O--O--O--O--O<-- main adopts v1.1.x >\ > \ > \ > O--O <-- fixes for interface v1.0.x >v1.0.3 v1.0.4 > > The key here is that the branching happened from the last fix (v1.0.2) on the > main branch prior to the change of interface (v1.1.0). As long as only fixes > are applied to v1.0.x, there is no risk of version number clash. All of these > release versions remain semantically connected with one small caveat. If this > set of release versions came sequentially along a single branch, one could > infer > that the exact fixes in v1.0.4 were inherited by v1.1.0. With this "hidden" > branching, this may not be true as this example shows. One should always > review > the release notes to confirm release ancestry and content. > > The above scenario of continued fixes on a given interface version represents > the most common form of release branching expected, and can be handled quite > smoothly within the proposed scheme as shown. But it may also be necessary to > branch from an arbitrary point and with an arbitrary scope of changes. Such a > scenario could not be handled with the basic 3 fields without violating > semver.org semantics. One or more additional version fields will need to be > defined. The GuC firmware team intends to avoid this scenario as long as > possible, though some day a customer or other situation might force it upon > us. > > For now we will just defer the design for handling the aforementioned > scenario, > though I am summarizing some options below to be considered if and when. None > of these are being put into effect immediately as part of the proposed change. > > At minimum we will need a 4th field to contain a branch ID. This will be a > numeric ID in the firmware image header, but can be mapped to a descriptive > branch string via a table that is part of the official firmware interface > documentation. If and when the branch ID field is added, it will start with a > value of 1 for that first branch, the mainline being implicitly branch ID 0. > There seems to be two logical choices for how to
Re: [Intel-gfx] [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
On Wed, Oct 24, 2018 at 06:28:02PM -0400, Lyude Paul wrote:
> On Wed, 2018-10-24 at 15:28 -0700, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same node can be used from userspace to force DSC enable.
> >
> > v2:
> > * Use kstrtobool_from_user to avoid explicit error checking (Lyude)
> > * Rebase on drm-tip (Manasi)
> >
> > Cc: Rodrigo Vivi
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Lyude Paul
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Lyude Paul
>
> (just making a note to anyone passing by this: my R-B here is still valid!)
> (also thanks for the patch :)
Thanks Lyude for thsi note and the initial review feedback! Appreciate your
time and inputs.
Manasi
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 71 -
> > drivers/gpu/drm/i915/intel_dp.c | 1 +
> > drivers/gpu/drm/i915/intel_drv.h| 3 ++
> > 3 files changed, 74 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 5cadfcd03ea9..6e631f08dd4b 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4999,6 +4999,72 @@ static int i915_hdcp_sink_capability_show(struct
> > seq_file *m, void *data)
> > }
> > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> >
> > +static int i915_dsc_support_show(struct seq_file *m, void *data)
> > +{
> > + struct drm_connector *connector = m->private;
> > + struct intel_encoder *encoder = intel_attached_encoder(connector);
> > + struct intel_dp *intel_dp =
> > + enc_to_intel_dp(>base);
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *crtc_state;
> > +
> > + crtc = to_intel_crtc(encoder->base.crtc);
> > + crtc_state = to_intel_crtc_state(crtc->base.state);
> > + drm_modeset_lock(>base.mutex, NULL);
> > + seq_printf(m, "Enabled: %s\n",
> > + yesno(crtc_state->dsc_params.compression_enable));
> > + seq_printf(m, "Supported: %s\n",
> > + yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> > + drm_modeset_unlock(>base.mutex);
> > +
> > + return 0;
> > +}
> > +
> > +static ssize_t i915_dsc_support_write(struct file *file,
> > + const char __user *ubuf,
> > + size_t len, loff_t *offp)
> > +{
> > + bool dsc_enable = false;
> > + int ret;
> > + struct drm_connector *connector =
> > + ((struct seq_file *)file->private_data)->private;
> > + struct intel_encoder *encoder = intel_attached_encoder(connector);
> > + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> > +
> > + if (len == 0)
> > + return 0;
> > +
> > + DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
> > +(unsigned int)len);
> > +
> > + ret = kstrtobool_from_user(ubuf, len, _enable);
> > + if (ret < 0)
> > + return ret;
> > +
> > + DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
> > +(dsc_enable) ? "true" : "false");
> > + intel_dp->force_dsc_en = dsc_enable;
> > +
> > + *offp += len;
> > + return len;
> > +}
> > +
> > +static int i915_dsc_support_open(struct inode *inode,
> > +struct file *file)
> > +{
> > + return single_open(file, i915_dsc_support_show,
> > + inode->i_private);
> > +}
> > +
> > +static const struct file_operations i915_dsc_support_fops = {
> > + .owner = THIS_MODULE,
> > + .open = i915_dsc_support_open,
> > + .read = seq_read,
> > + .llseek = seq_lseek,
> > + .release = single_release,
> > + .write = i915_dsc_support_write
> > +};
> > +
> > /**
> > * i915_debugfs_connector_add - add i915 specific connector debugfs files
> > * @connector: pointer to a registered drm_connector
> > @@ -5017,9 +5083,12 @@ int i915_debugfs_connector_add(struct drm_connector
> > *connector)
> > return -ENODEV;
> >
> > if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > - connector->connector_type == DRM_MODE_CONNECTOR_eDP)
> > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > debugfs_create_file("i915_dpcd", S_IRUGO, root,
> > connector, _dpcd_fops);
> > + debugfs_create_file("i915_dsc_support", S_IRUGO, root,
> > + connector, _dsc_support_fops);
> > + }
> >
> > if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > debugfs_create_file("i915_panel_timings", S_IRUGO, root,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 72e6605f0ed7..0b5939992c2b 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2287,6 +2287,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >
Re: [Intel-gfx] [PATCH v6 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink
On Thu, Oct 25, 2018 at 05:03:06PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:30PM -0700, Manasi Navare wrote:
> > From: Gaurav K Singh
> >
> > This patch enables decompression support in sink device
> > before link training and disables the same during the
> > DDI disabling.
> >
> > v2:(From Manasi)
> > * Change the enable/disable function to take crtc_state
> > instead of intel_dp as an argument (Manasi)
> > * Use the compression_enable flag as part of crtc_state (Manasi)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 5 +
> > drivers/gpu/drm/i915/intel_dp.c | 15 +++
> > drivers/gpu/drm/i915/intel_drv.h | 3 +++
> > 3 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index e40a8c97d34b..1de0a3917d7f 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2930,6 +2930,8 @@ static void intel_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> > intel_ddi_init_dp_buf_reg(encoder);
> > if (!is_mst)
> > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > + intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> > + DP_DECOMPRESSION_EN);
> > intel_dp_start_link_train(intel_dp);
> > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> > intel_dp_stop_link_train(intel_dp);
> > @@ -3272,6 +3274,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
> > *encoder,
> > intel_edp_drrs_disable(intel_dp, old_crtc_state);
> > intel_psr_disable(intel_dp, old_crtc_state);
> > intel_edp_backlight_off(old_conn_state);
> > + /* Disable the decompression in DP Sink */
> > + intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
> > + ~DP_DECOMPRESSION_EN);
>
> That looks suspicious.
>
> I can't figure out what value you're actually passing here since I
> can't find the definiiton of DP_DECOMPRESSION_EN anywhere.
This is defined in /include/drm/drm_dp_helper.h
Manasi
>
> > }
> >
> > static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 35162c3bc811..72e6605f0ed7 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3005,6 +3005,21 @@ static bool downstream_hpd_needs_d0(struct intel_dp
> > *intel_dp)
> > intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
> > }
> >
> > +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + int state)
> > +{
> > + int ret;
> > +
> > + if (!crtc_state->dsc_params.compression_enable)
> > + return;
> > +
> > + ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE, state);
> > + if (ret < 0)
> > + DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
> > + state == DP_DECOMPRESSION_EN ? "enable" :
> > "disable");
> > +}
> > +
> > /* If the sink supports it, try to set the power state appropriately */
> > void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
> > {
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index c4be4ba7adac..4f5d17bcd54e 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1786,6 +1786,9 @@ void intel_dp_stop_link_train(struct intel_dp
> > *intel_dp);
> > int intel_dp_retrain_link(struct intel_encoder *encoder,
> > struct drm_modeset_acquire_ctx *ctx);
> > void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
> > +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + int state);
> > void intel_dp_encoder_reset(struct drm_encoder *encoder);
> > void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
> > void intel_dp_encoder_destroy(struct drm_encoder *encoder);
> > --
> > 2.18.0
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
== Series Details == Series: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o URL : https://patchwork.freedesktop.org/series/51542/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10585 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51542/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10585 that come from known issues: === IGT changes === Issues hit igt@drv_getparams_basic@basic-eu-total: fi-skl-6770hq: PASS -> DMESG-WARN (fdo#105541) igt@drv_selftest@live_sanitycheck: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@prime_vgem@basic-fence-flip: fi-cfl-8700k: PASS -> FAIL (fdo#104008) Possible fixes igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_frontbuffer_tracking@basic: fi-glk-j4005: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105541 https://bugs.freedesktop.org/show_bug.cgi?id=105541 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 == Participating hosts (46 -> 44) == Additional (1): fi-icl-u Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5037 -> Patchwork_10585 CI_DRM_5037: e11750586cb6054bd319ad217cecd045febaacc5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4694: ff8d1156723f235e82cb4fcfd2cd6e5a5bb211fa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10585: af9ae53ac686bf661bdc630f0aee4364a7a2f1c1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == af9ae53ac686 drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10585/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
On Thu, Oct 25, 2018 at 05:09:42PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:34PM -0700, Manasi Navare wrote:
> > DSC PPS secondary data packet infoframes are filled with
> > DSC picure parameter set metadata according to the DSC standard.
> > These infoframes are sent to the sink device and used during DSC
> > decoding.
> >
> > v2:
> > * Rebase ond drm-tip
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/intel_vdsc.c | 21 +
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> > b/drivers/gpu/drm/i915/intel_vdsc.c
> > index b0fc716bbbfd..4b4b812d68f3 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
> > intel_encoder *encoder,
> > }
> > }
> >
> > +static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
>
> const crtc_state
Yes wil make this a const
>
> s/send/write/ ?
Hmm in terms of VDSC, the SDP packet is the one that gets sent to the sink from
source
after we write the infoframe.
So I named it as _send_dsc_pps_sdp, but I am okay changing that to
write_dsc_pps_sdp
since all we are doing is writing an infoframe that gets sent out.
Manasi
>
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > + struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
> > + struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
> > +
> > + /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
> > + drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
> > +
> > + /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
> > + drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
> > +
> > + intel_dig_port->write_infoframe(encoder, crtc_state,
> > + DP_SDP_PPS, _dsc_pps_sdp,
> > + sizeof(dp_dsc_pps_sdp));
> > +}
> > +
> > void intel_dsc_enable(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -997,5 +1016,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> >
> > intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> >
> > + intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
> > +
> > return;
> > }
> > --
> > 2.18.0
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v6 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable
On Thu, Oct 25, 2018 at 05:15:34PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:36PM -0700, Manasi Navare wrote:
> > Display Stream Splitter registers need to be programmed to enable
> > the joiner if two DSC engines are used and also to enable
> > the left and the right DSC engines. This happens as part of
> > the DSC enabling routine in the source in atomic commit.
> >
> > v3:
> > * Use cpu_transcoder instead of encoder->type (Ville)
> > v2:
> > * Rebase (Manasi)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/intel_vdsc.c | 22 ++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> > b/drivers/gpu/drm/i915/intel_vdsc.c
> > index 4b4b812d68f3..8b46619aae15 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -1010,6 +1010,12 @@ static void intel_dp_send_dsc_pps_sdp(struct
> > intel_encoder *encoder,
> > void intel_dsc_enable(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + enum pipe pipe = crtc->pipe;
> > + i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> > + u32 dss_ctl1_val = 0;
> > + u32 dss_ctl2_val = 0;
> >
> > if (!crtc_state->dsc_params.compression_enable)
> > return;
> > @@ -1018,5 +1024,21 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> >
> > intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
> >
> > + /* Configure DSS_CTL registers for DSC */
>
> This comment seems redundant.
Yes, might have added this during the early development cycles. Will remove it
now
that it follows the functions that actually do it.
Thanks for pointing it out.
>
> > + if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
> > + dss_ctl1_reg = DSS_CTL1;
> > + dss_ctl2_reg = DSS_CTL2;
> > + } else {
> > + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> > + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
>
> Shouldn't these be cpu_transcoder too? Yeah, it's the same thing
> essentially, but I think it's better to use the thing that
> actually matches the hardware.
But if you look at the spec def of PIPE_DSS_CTL1 and 2, it actually
has a set of registers for Pipe B and different for Pipe C.
So in case of external DP VDSC engines are tied to per pipe
on ICL as well.
Only for eDP, it is tied to transcoder EDP and hence I look at the
transcoder eDP and use DSS_CTL1 or 2 else use PIPE_DSS_CTL1/2.
>
> I wonder if it would even make sense to do the trans==EDP check
> in the macro as well. Would avoid cluttering the code with
> details like this. The macro wouldn't be the prettiest thing
> ever, but that more or less holds for all reg macros.
>
So add a macro something like this:
#define IS_TRANSCODER_EDP(crtc-state) crtc_state->cpu_transcoder ==
TRANSCODER_EDP;
Is this what you are suggesting?
MAnasi
> > + }
> > + dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
> > + if (crtc_state->dsc_params.dsc_split) {
> > + dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
> > + dss_ctl1_val |= JOINER_ENABLE;
> > + }
> > + I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
> > + I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
> > +
> > return;
> > }
> > --
> > 2.18.0
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v6 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
On Thu, Oct 25, 2018 at 05:16:58PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:37PM -0700, Manasi Navare wrote:
> > 1. Disable Left/right VDSC branch in DSS Ctrl reg
> > depending on the number of VDSC engines being used
> > 2. Disable joiner in DSS Ctrl reg
> >
> > v3 (From Manasi):
> > * Add Disable PG2 for VDSC on eDP
> > v2 (From Manasi):
> > * Use old_crtc_state to find dsc params
> > * Add a condition to disable only if
> > dsc state compression is enabled
> > * Use correct DSS CTL regs
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Signed-off-by: Manasi Navare
> > Signed-off-by: Gaurav K Singh
> > Reviewed-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/intel_display.c | 13 +++
> > drivers/gpu/drm/i915/intel_vdsc.c| 33
> > 3 files changed, 48 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 16e6bb98eb1b..e31f19a688bc 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3489,6 +3489,8 @@ extern bool intel_set_memory_cxsr(struct
> > drm_i915_private *dev_priv,
> > bool enable);
> > extern void intel_dsc_enable(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state);
> > +extern void intel_dsc_disable(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state);
> >
> > int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> > struct drm_file *file);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 023a9baef101..3d9d70d3314e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5853,6 +5853,9 @@ static void haswell_crtc_disable(struct
> > intel_crtc_state *old_crtc_state,
> > struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> > + struct drm_connector_state *conn_state;
> > + struct drm_connector *conn;
> > + int i;
> >
> > intel_encoders_disable(crtc, old_crtc_state, old_state);
> >
> > @@ -5869,6 +5872,16 @@ static void haswell_crtc_disable(struct
> > intel_crtc_state *old_crtc_state,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_ddi_disable_transcoder_func(old_crtc_state);
> >
> > + for_each_new_connector_in_state(old_state, conn, conn_state, i) {
> > + struct intel_encoder *encoder =
> > + to_intel_encoder(conn_state->best_encoder);
> > +
> > + if (conn_state->crtc != crtc)
> > + continue;
> > +
> > + intel_dsc_disable(encoder, old_crtc_state);
> > + }
>
> Can't we do this from the encodr hooks? /me didn't check the modeset
> sequence docs...
Hmm yes it could be made part of intel_encoders_post_disable(). The spec is not
clear in terms of where in the sequence shd this be disabled.
Do you think intel_encoders_post_disable() is the right place?
Manasi
>
> > +
> > if (INTEL_GEN(dev_priv) >= 9)
> > skylake_scaler_disable(intel_crtc);
> > else
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> > b/drivers/gpu/drm/i915/intel_vdsc.c
> > index 8b46619aae15..5e76b4a44d90 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -1042,3 +1042,36 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> >
> > return;
> > }
> > +
> > +void intel_dsc_disable(struct intel_encoder *encoder,
> > + struct intel_crtc_state *old_crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + enum pipe pipe = crtc->pipe;
> > + i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> > + u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
> > +
> > + if (!old_crtc_state->dsc_params.compression_enable)
> > + return;
> > +
> > + if (encoder->type == INTEL_OUTPUT_EDP) {
> > + dss_ctl1_reg = DSS_CTL1;
> > + dss_ctl2_reg = DSS_CTL2;
> > + } else {
> > + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> > + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> > + }
> > + dss_ctl1_val = I915_READ(dss_ctl1_reg);
> > + if (dss_ctl1_val & JOINER_ENABLE)
> > + dss_ctl1_val &= ~JOINER_ENABLE;
> > + I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
> > +
> > + dss_ctl2_val = I915_READ(dss_ctl2_reg);
> > + if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
> > + dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
> > + dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
> > + RIGHT_BRANCH_VDSC_ENABLE);
> > +
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2)
== Series Details == Series: drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2) URL : https://patchwork.freedesktop.org/series/50649/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10584 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50649/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10584 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_sanitycheck: fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726) Possible fixes igt@kms_busy@basic-flip-c: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_frontbuffer_tracking@basic: fi-glk-j4005: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@pm_rpm@module-reload: fi-glk-j4005: DMESG-WARN (fdo#107726) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 == Participating hosts (46 -> 44) == Additional (1): fi-icl-u Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5037 -> Patchwork_10584 CI_DRM_5037: e11750586cb6054bd319ad217cecd045febaacc5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4694: ff8d1156723f235e82cb4fcfd2cd6e5a5bb211fa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10584: bd7c3e303cdaf8ecf19136ef1135f517e3b9c7c4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bd7c3e303cda drm/i915/hdmi: Reorder structure to match specification e2ad180a5f8f drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10584/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
== Series Details == Series: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o URL : https://patchwork.freedesktop.org/series/51542/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o - +./include/linux/mm.h:592:13: error: not a function +./include/linux/mm.h:592:13: error: not a function +./include/linux/mm.h:592:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/mm.h:592:13: warning: call with no type! +./include/linux/slab.h:631:13: error: not a function +./include/linux/slab.h:631:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:631:13: warning: call with no type! +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix ilk+ watermarks when disabling pipes
== Series Details == Series: drm/i915: Fix ilk+ watermarks when disabling pipes URL : https://patchwork.freedesktop.org/series/51518/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5035_full -> Patchwork_10578_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10578_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10578_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10578_full: === IGT changes === Possible regressions igt@gem_busy@close-race: shard-skl: PASS -> DMESG-FAIL igt@gem_exec_whisper@normal: shard-skl: PASS -> TIMEOUT == Known issues == Here are the changes found in Patchwork_10578_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106886) igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-apl: PASS -> DMESG-FAIL (fdo#108549) +1 igt@kms_atomic_transition@plane-all-modeset-transition: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_available_modes_crc@available_mode_test_crc: shard-snb: PASS -> FAIL (fdo#106641) igt@kms_color@pipe-a-degamma: shard-apl: PASS -> FAIL (fdo#108145, fdo#104782) igt@kms_cursor_crc@cursor-256x256-suspend: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359) +1 igt@kms_cursor_crc@cursor-64x21-random: shard-apl: PASS -> FAIL (fdo#103232) +3 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled: shard-skl: PASS -> FAIL (fdo#103184) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: shard-glk: PASS -> FAIL (fdo#103167) +4 igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) shard-glk: PASS -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_rotation_crc@primary-rotation-180: shard-snb: PASS -> FAIL (fdo#103925) igt@kms_vblank@pipe-c-wait-busy-hang: shard-apl: PASS -> DMESG-WARN (fdo#108549) +19 igt@perf@polling: shard-hsw: PASS -> FAIL (fdo#102252) igt@pm_rpm@gem-execbuf-stress-pc8: shard-skl: SKIP -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_busy@close-race: shard-apl: DMESG-FAIL -> PASS igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-hsw: DMESG-WARN (fdo#107956) -> PASS igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge: shard-apl: DMESG-WARN (fdo#108549) -> PASS +23 igt@kms_cursor_crc@cursor-128x128-onscreen: shard-glk: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_crc@cursor-128x128-random: shard-kbl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +7 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: FAIL (fdo#105682, fdo#103167) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-kbl: DMESG-FAIL (fdo#103166, fdo#105602, fdo#103558) -> PASS igt@kms_plane@plane-position-covered-pipe-c-planes: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_vblank@pipe-b-ts-continuation-suspend: shard-apl: DMESG-FAIL (fdo#108549) -> PASS Warnings igt@gem_ppgtt@blt-vs-render-ctx0: shard-skl: INCOMPLETE (fdo#106887) -> TIMEOUT (fdo#108039) igt@kms_cursor_crc@cursor-64x64-random: shard-apl: DMESG-WARN (fdo#108549) -> FAIL (fdo#103232) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-kbl: DMESG-FAIL (fdo#108145,
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Avoid struct_mutex recursion for mmu_invalidate_range_start
Quoting Daniel Vetter (2018-10-25 20:16:50)
> On Thu, Oct 25, 2018 at 01:45:42PM +0100, Chris Wilson wrote:
> > Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> > notifiers") we have been able to report failure from
> > mmu_invalidate_range_start which allows us to use a trylock on the
> > struct_mutex to avoid potential recursion and report -EBUSY instead.
> > Furthermore, this allows us to pull the work into the main callback and
> > avoid the sleight-of-hand in using a workqueue to avoid lockdep.
> >
> > However, not all paths to mmu_invalidate_range_start are prepared to
> > handle failure, so instead of reporting the recursion, deal with it.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108375
> > References: 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> > notifiers")
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 4 +-
> > drivers/gpu/drm/i915/i915_gem.c | 12 +-
> > drivers/gpu/drm/i915/i915_gem_userptr.c | 219
> > 3 files changed, 115 insertions(+), 120 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 2d7761b8ac07..c3b94c3f930f 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3076,8 +3076,8 @@ enum i915_mm_subclass { /* lockdep subclass for
> > obj->mm.lock */
> > I915_MM_SHRINKER
> > };
> >
> > -void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> > - enum i915_mm_subclass subclass);
> > +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> > + enum i915_mm_subclass subclass);
> > void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
> >
> > enum i915_map_type {
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 93d09282710d..de7ccb3eb7b8 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -2454,17 +2454,18 @@ __i915_gem_object_unset_pages(struct
> > drm_i915_gem_object *obj)
> > return pages;
> > }
> >
> > -void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> > - enum i915_mm_subclass subclass)
> > +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> > + enum i915_mm_subclass subclass)
> > {
> > struct sg_table *pages;
> > + int ret = -EBUSY;
> >
> > if (i915_gem_object_has_pinned_pages(obj))
> > - return;
> > + return -EBUSY;
> >
> > GEM_BUG_ON(obj->bind_count);
> > if (!i915_gem_object_has_pages(obj))
> > - return;
> > + return 0;
> >
> > /* May be called by shrinker from within get_pages() (on another bo)
> > */
> > mutex_lock_nested(>mm.lock, subclass);
> > @@ -2480,8 +2481,11 @@ void __i915_gem_object_put_pages(struct
> > drm_i915_gem_object *obj,
> > if (!IS_ERR(pages))
> > obj->ops->put_pages(obj, pages);
> >
> > + ret = 0;
> > unlock:
> > mutex_unlock(>mm.lock);
> > +
> > + return ret;
> > }
> >
> > bool i915_sg_trim(struct sg_table *orig_st)
> > diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
> > b/drivers/gpu/drm/i915/i915_gem_userptr.c
> > index 2c9b284036d1..a8f3c304db55 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_userptr.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
> > @@ -50,79 +50,84 @@ struct i915_mmu_notifier {
> > struct hlist_node node;
> > struct mmu_notifier mn;
> > struct rb_root_cached objects;
> > - struct workqueue_struct *wq;
> > + struct i915_mm_struct *mm;
> > };
> >
> > struct i915_mmu_object {
> > struct i915_mmu_notifier *mn;
> > struct drm_i915_gem_object *obj;
> > struct interval_tree_node it;
> > - struct list_head link;
> > - struct work_struct work;
> > - bool attached;
> > };
> >
> > -static void cancel_userptr(struct work_struct *work)
> > -{
> > - struct i915_mmu_object *mo = container_of(work, typeof(*mo), work);
> > - struct drm_i915_gem_object *obj = mo->obj;
> > - struct work_struct *active;
> > -
> > - /* Cancel any active worker and force us to re-evaluate gup */
> > - mutex_lock(>mm.lock);
> > - active = fetch_and_zero(>userptr.work);
> > - mutex_unlock(>mm.lock);
> > - if (active)
> > - goto out;
> > -
> > - i915_gem_object_wait(obj, I915_WAIT_ALL, MAX_SCHEDULE_TIMEOUT, NULL);
> > -
> > - mutex_lock(>base.dev->struct_mutex);
> > -
> > - /* We are inside a kthread context and can't be interrupted */
> > - if (i915_gem_object_unbind(obj) == 0)
> > - __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> > - WARN_ONCE(i915_gem_object_has_pages(obj),
> > - "Failed to release pages: bind_count=%d,
> >
Re: [Intel-gfx] [PATCH v6 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
On Thu, Oct 25, 2018 at 05:22:18PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:38PM -0700, Manasi Navare wrote:
> > A separate power well 2 (PG2) is required for VDSC on eDP transcoder
> > whereas all other transcoders use the power wells associated with the
> > transcoders for VDSC.
> > This patch adds a helper to obtain correct power domain depending on
> > transcoder being used and enables/disables the power wells during
> > VDSC enabling/disabling.
> >
> > v2:
> > * Fix tabs, const crtc_state, fix comments (Ville)
> >
> > Suggested-by: Ville Syrjala
> > Cc: Ville Syrjala
> > Cc: Imre Deak
> > Cc: Rodrigo Vivi
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_vdsc.c | 26 ++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> > b/drivers/gpu/drm/i915/intel_vdsc.c
> > index 5e76b4a44d90..0fed36e2491a 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -581,6 +581,24 @@ int intel_dp_compute_dsc_params(struct intel_dp
> > *intel_dp,
> > return 0;
> > }
> >
> > +static enum intel_display_power_domain
> > +intel_dsc_get_power_domains(const struct intel_crtc_state *crtc_state)
>
> intel_dsc_power_domain() or something like that to match
> the naming convention introduced by intel_ddi_main_link_aux_domain()?
Ok i can rename to use intel_dsc_power_domain() but it should still live
in intel_vdsc.c right?
>
> Oh, and we'll need to update intel_ddi_get_power_domains() as well.
We would need to add this power domain here so that its obtained during
the intel_modeset_setup_hw_state()..?
Manasi
>
> > +{
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > + /*
> > +* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
> > +* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> > +* For any other transcoder, VDSC/joining uses the power well associated
> > +* with the pipe/transcoder in use. Hence another reference on the
> > +* transcoder power domain will suffice.
> > +*/
> > + if (cpu_transcoder == TRANSCODER_EDP)
> > + return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > + else
> > + return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> > +}
> > +
> > static void intel_configure_pps_for_dsc_encoder(struct intel_encoder
> > *encoder,
> > struct intel_crtc_state
> > *crtc_state)
> > {
> > @@ -1020,6 +1038,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> > if (!crtc_state->dsc_params.compression_enable)
> > return;
> >
> > + /* Enable Power wells for VDSC/joining */
> > + intel_display_power_get(dev_priv,
> > + intel_dsc_get_power_domains(crtc_state));
> > +
> > intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> >
> > intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
> > @@ -1074,4 +1096,8 @@ void intel_dsc_disable(struct intel_encoder *encoder,
> > RIGHT_BRANCH_VDSC_ENABLE);
> > I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
> >
> > + /* Disable Power wells for VDSC/joining */
> > + intel_display_power_put(dev_priv,
> > + intel_dsc_get_power_domains(old_crtc_state));
> > +
>
> Bogus newline here.
>
> > }
> > --
> > 2.18.0
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH] drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
This warning is disabled by default in scripts/Makefile.extrawarn when
W= is not provided but this Makefile adds -Wall after this warning is
disabled so it shows up in the build when it shouldn't:
In file included from drivers/gpu/drm/i915/intel_breadcrumbs.c:895:
drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c:350:34: error:
variable 'wq' is uninitialized when used within its own initialization
[-Werror,-Wuninitialized]
DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
^~
./include/linux/wait.h:74:63: note: expanded from macro
'DECLARE_WAIT_QUEUE_HEAD_ONSTACK'
struct wait_queue_head name = __WAIT_QUEUE_HEAD_INIT_ONSTACK(name)
^~~~
./include/linux/wait.h:72:33: note: expanded from macro
'__WAIT_QUEUE_HEAD_INIT_ONSTACK'
({ init_waitqueue_head(); name; })
^~~~
1 error generated.
This warning looks to be a false positive given that init_waitqueue_head
initializes name before it is used. Rather than disable the warning for
the full folder like commit 46e2068081e9 ("drm/i915: Disable some extra
clang warnings"), just disable it for the one problematic file because
it could be a useful warning for other cases.
Link: https://github.com/ClangBuiltLinux/linux/issues/220
Signed-off-by: Nathan Chancellor
---
drivers/gpu/drm/i915/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c2857f13ad4..f36c420afb99 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -26,6 +26,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
# Fine grained warnings disable
CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
+CFLAGS_intel_breadcrumbs.o = $(call cc-disable-warning, uninitialized)
CFLAGS_intel_fbdev.o = $(call cc-disable-warning, override-init)
subdir-ccflags-y += \
--
2.19.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2)
== Series Details == Series: drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2) URL : https://patchwork.freedesktop.org/series/50649/ State : warning == Summary == $ dim checkpatch origin/drm-tip e2ad180a5f8f drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value total: 0 errors, 1 warnings, 0 checks, 29 lines checked bd7c3e303cda drm/i915/hdmi: Reorder structure to match specification ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Avoid struct_mutex recursion for mmu_invalidate_range_start
On Thu, Oct 25, 2018 at 01:45:42PM +0100, Chris Wilson wrote:
> Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> notifiers") we have been able to report failure from
> mmu_invalidate_range_start which allows us to use a trylock on the
> struct_mutex to avoid potential recursion and report -EBUSY instead.
> Furthermore, this allows us to pull the work into the main callback and
> avoid the sleight-of-hand in using a workqueue to avoid lockdep.
>
> However, not all paths to mmu_invalidate_range_start are prepared to
> handle failure, so instead of reporting the recursion, deal with it.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108375
> References: 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> notifiers")
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gem.c | 12 +-
> drivers/gpu/drm/i915/i915_gem_userptr.c | 219
> 3 files changed, 115 insertions(+), 120 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2d7761b8ac07..c3b94c3f930f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3076,8 +3076,8 @@ enum i915_mm_subclass { /* lockdep subclass for
> obj->mm.lock */
> I915_MM_SHRINKER
> };
>
> -void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> - enum i915_mm_subclass subclass);
> +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> + enum i915_mm_subclass subclass);
> void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
>
> enum i915_map_type {
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 93d09282710d..de7ccb3eb7b8 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2454,17 +2454,18 @@ __i915_gem_object_unset_pages(struct
> drm_i915_gem_object *obj)
> return pages;
> }
>
> -void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> - enum i915_mm_subclass subclass)
> +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> + enum i915_mm_subclass subclass)
> {
> struct sg_table *pages;
> + int ret = -EBUSY;
>
> if (i915_gem_object_has_pinned_pages(obj))
> - return;
> + return -EBUSY;
>
> GEM_BUG_ON(obj->bind_count);
> if (!i915_gem_object_has_pages(obj))
> - return;
> + return 0;
>
> /* May be called by shrinker from within get_pages() (on another bo) */
> mutex_lock_nested(>mm.lock, subclass);
> @@ -2480,8 +2481,11 @@ void __i915_gem_object_put_pages(struct
> drm_i915_gem_object *obj,
> if (!IS_ERR(pages))
> obj->ops->put_pages(obj, pages);
>
> + ret = 0;
> unlock:
> mutex_unlock(>mm.lock);
> +
> + return ret;
> }
>
> bool i915_sg_trim(struct sg_table *orig_st)
> diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/i915_gem_userptr.c
> index 2c9b284036d1..a8f3c304db55 100644
> --- a/drivers/gpu/drm/i915/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
> @@ -50,79 +50,84 @@ struct i915_mmu_notifier {
> struct hlist_node node;
> struct mmu_notifier mn;
> struct rb_root_cached objects;
> - struct workqueue_struct *wq;
> + struct i915_mm_struct *mm;
> };
>
> struct i915_mmu_object {
> struct i915_mmu_notifier *mn;
> struct drm_i915_gem_object *obj;
> struct interval_tree_node it;
> - struct list_head link;
> - struct work_struct work;
> - bool attached;
> };
>
> -static void cancel_userptr(struct work_struct *work)
> -{
> - struct i915_mmu_object *mo = container_of(work, typeof(*mo), work);
> - struct drm_i915_gem_object *obj = mo->obj;
> - struct work_struct *active;
> -
> - /* Cancel any active worker and force us to re-evaluate gup */
> - mutex_lock(>mm.lock);
> - active = fetch_and_zero(>userptr.work);
> - mutex_unlock(>mm.lock);
> - if (active)
> - goto out;
> -
> - i915_gem_object_wait(obj, I915_WAIT_ALL, MAX_SCHEDULE_TIMEOUT, NULL);
> -
> - mutex_lock(>base.dev->struct_mutex);
> -
> - /* We are inside a kthread context and can't be interrupted */
> - if (i915_gem_object_unbind(obj) == 0)
> - __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> - WARN_ONCE(i915_gem_object_has_pages(obj),
> - "Failed to release pages: bind_count=%d, pages_pin_count=%d,
> pin_global=%d\n",
> - obj->bind_count,
> - atomic_read(>mm.pages_pin_count),
> - obj->pin_global);
> -
> - mutex_unlock(>base.dev->struct_mutex);
> -
> -out:
> - i915_gem_object_put(obj);
> -}
> -
> static void add_object(struct
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG
== Series Details == Series: drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG URL : https://patchwork.freedesktop.org/series/51538/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10583 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10583 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10583, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51538/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10583: === IGT changes === Possible regressions igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-icl-u2: PASS -> DMESG-WARN == Known issues == Here are the changes found in Patchwork_10583 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: PASS -> DMESG-WARN (fdo#105128, fdo#107139) Possible fixes igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_frontbuffer_tracking@basic: fi-glk-j4005: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@pm_rpm@module-reload: fi-glk-j4005: DMESG-WARN (fdo#107726) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726 == Participating hosts (46 -> 43) == Additional (1): fi-icl-u Missing(4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5037 -> Patchwork_10583 CI_DRM_5037: e11750586cb6054bd319ad217cecd045febaacc5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4694: ff8d1156723f235e82cb4fcfd2cd6e5a5bb211fa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10583: a762edd5c7c822847f5487ad2c2b935b627f90bf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a762edd5c7c8 drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10583/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/userptr: Avoid struct_mutex recursion for mmu_invalidate_range_start (rev2)
== Series Details == Series: drm/i915/userptr: Avoid struct_mutex recursion for mmu_invalidate_range_start (rev2) URL : https://patchwork.freedesktop.org/series/51362/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5035_full -> Patchwork_10577_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10577_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10577_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10577_full: === IGT changes === Possible regressions igt@gem_busy@close-race: shard-glk: PASS -> DMESG-FAIL == Known issues == Here are the changes found in Patchwork_10577_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106886) igt@gem_eio@in-flight-suspend: shard-apl: PASS -> DMESG-WARN (fdo#107957) igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-apl: PASS -> DMESG-FAIL (fdo#108549) +2 igt@kms_atomic_transition@plane-all-modeset-transition: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_color@pipe-a-degamma: shard-apl: PASS -> FAIL (fdo#104782, fdo#108145) igt@kms_concurrent@pipe-a: shard-apl: PASS -> DMESG-WARN (fdo#108549) +21 igt@kms_cursor_crc@cursor-size-change: shard-glk: PASS -> FAIL (fdo#103232) +2 igt@kms_flip_tiling@flip-changes-tiling-yf: shard-skl: PASS -> FAIL (fdo#108303, fdo#108228) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) +3 igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) shard-glk: PASS -> FAIL (fdo#108145) igt@kms_universal_plane@universal-plane-pipe-a-functional: shard-apl: PASS -> FAIL (fdo#103166) Possible fixes igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-skl: DMESG-WARN (fdo#107956) -> PASS igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge: shard-apl: DMESG-WARN (fdo#108549) -> PASS +23 igt@kms_cursor_crc@cursor-128x128-random: shard-apl: FAIL (fdo#103232) -> PASS +1 shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +7 igt@kms_cursor_crc@cursor-256x256-random: shard-glk: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_crc@cursor-256x256-suspend: shard-kbl: INCOMPLETE (fdo#103665) -> PASS shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc: shard-skl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: FAIL (fdo#105682, fdo#103167) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-kbl: DMESG-FAIL (fdo#103166, fdo#103558, fdo#105602) -> PASS igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: shard-skl: FAIL (fdo#108145, fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_vblank@pipe-b-ts-continuation-suspend: shard-apl: DMESG-FAIL (fdo#108549) -> PASS Warnings igt@gem_ppgtt@blt-vs-render-ctx0: shard-skl: INCOMPLETE (fdo#106887) -> TIMEOUT (fdo#108039) igt@kms_cursor_crc@cursor-64x64-random: shard-apl: DMESG-WARN (fdo#108549) -> FAIL (fdo#103232) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-kbl: DMESG-FAIL (fdo#108145, fdo#103558, fdo#105602) -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb: shard-apl: FAIL (fdo#108145) -> DMESG-FAIL (fdo#108145, fdo#108549) igt@kms_setmode@basic: shard-apl: DMESG-WARN (fdo#108549) -> FAIL (fdo#99912) fdo#103158
Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values
On 10/15/2018 04:31 AM, Jani Nikula wrote:
On Mon, 15 Oct 2018, Jani Nikula wrote:
On Fri, 05 Oct 2018, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N
value mode instead of HDMI specification values.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 769f3f5..4b8f6f6 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -144,6 +144,8 @@ struct dp_aud_n_m {
/* HDMI N/CTS table */
#define TMDS_297M 297000
#define TMDS_296M 296703
+#define TMDS_594M 594000
+#define TMDS_593M 593407
static const struct {
int sample_rate;
int clock;
@@ -164,6 +166,20 @@ struct dp_aud_n_m {
{ 176400, TMDS_297M, 18816, 247500 },
{ 192000, TMDS_296M, 23296, 281250 },
{ 192000, TMDS_297M, 20480, 247500 },
+ { 44100, TMDS_593M, 8918, 937500 },
+ { 44100, TMDS_594M, 9408, 99 },
+ { 48000, TMDS_593M, 5824, 562500 },
+ { 48000, TMDS_594M, 6144, 594000 },
+ { 32000, TMDS_593M, 5824, 843750 },
+ { 32000, TMDS_594M, 3072, 445500 },
+ { 88200, TMDS_593M, 17836, 937500 },
+ { 88200, TMDS_594M, 9408, 99 },
The N here should be 18816. The rest looks good.
Good catch. I'll make the change in v2.
PS. This should probably have Cc: stable.
Done
Could I persuade you to write a cleanup patch on top to re-arrange the
array in groups:
/* multiples of 32 kHz */
/* multiples of 44.1 kHz */
/* multiples of 48 kHz */
with each group in increasing audio sample frequency, I'll review it in
same go. Otherwise, I'll write the patch myself. The current ordering is
a PITA to review against the spec...
patch 2/2 send with structure reorganized by Sample Frequency.
TODO: add N/CTS values for 30 and 36 bit 297Mhz modes.
-Clint
BR,
Jani.
BR,
Jani.
+ { 96000, TMDS_593M, 11648, 562500 },
+ { 96000, TMDS_594M, 12288, 594000 },
+ { 176400, TMDS_593M, 35672, 937500 },
+ { 176400, TMDS_594M, 37632, 99 },
+ { 192000, TMDS_593M, 23296, 562500 },
+ { 192000, TMDS_594M, 24576, 594000 },
};
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
___
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[Intel-gfx] [PATCH v2 2/2] drm/i915/hdmi: Reorder structure to match specification
From: Clint Taylor
reorder structure of 297, 594 N values to group Audio Sample Frequencies
together to make updating from HDMI specification easier.
V2: Match patch 1/2 version
Cc: Jani Nikula
Cc: sta...@vger.kernel.org
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index ee3ca2d..47caecb 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -153,32 +153,32 @@ struct dp_aud_n_m {
int n;
int cts;
} hdmi_aud_ncts[] = {
- { 44100, TMDS_296M, 4459, 234375 },
- { 44100, TMDS_297M, 4704, 247500 },
- { 48000, TMDS_296M, 5824, 281250 },
- { 48000, TMDS_297M, 5120, 247500 },
{ 32000, TMDS_296M, 5824, 421875 },
{ 32000, TMDS_297M, 3072, 222750 },
+ { 44100, TMDS_296M, 4459, 234375 },
+ { 44100, TMDS_297M, 4704, 247500 },
{ 88200, TMDS_296M, 8918, 234375 },
{ 88200, TMDS_297M, 9408, 247500 },
- { 96000, TMDS_296M, 11648, 281250 },
- { 96000, TMDS_297M, 10240, 247500 },
{ 176400, TMDS_296M, 17836, 234375 },
{ 176400, TMDS_297M, 18816, 247500 },
+ { 48000, TMDS_296M, 5824, 281250 },
+ { 48000, TMDS_297M, 5120, 247500 },
+ { 96000, TMDS_296M, 11648, 281250 },
+ { 96000, TMDS_297M, 10240, 247500 },
{ 192000, TMDS_296M, 23296, 281250 },
{ 192000, TMDS_297M, 20480, 247500 },
- { 44100, TMDS_593M, 8918, 937500 },
- { 44100, TMDS_594M, 9408, 99 },
- { 48000, TMDS_593M, 5824, 562500 },
- { 48000, TMDS_594M, 6144, 594000 },
{ 32000, TMDS_593M, 5824, 843750 },
{ 32000, TMDS_594M, 3072, 445500 },
+ { 44100, TMDS_593M, 8918, 937500 },
+ { 44100, TMDS_594M, 9408, 99 },
{ 88200, TMDS_593M, 17836, 937500 },
{ 88200, TMDS_594M, 18816, 99 },
- { 96000, TMDS_593M, 11648, 562500 },
- { 96000, TMDS_594M, 12288, 594000 },
{ 176400, TMDS_593M, 35672, 937500 },
{ 176400, TMDS_594M, 37632, 99 },
+ { 48000, TMDS_593M, 5824, 562500 },
+ { 48000, TMDS_594M, 6144, 594000 },
+ { 96000, TMDS_593M, 11648, 562500 },
+ { 96000, TMDS_594M, 12288, 594000 },
{ 192000, TMDS_593M, 23296, 562500 },
{ 192000, TMDS_594M, 24576, 594000 },
};
--
1.9.1
___
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[Intel-gfx] [PATCH 0/2] HDMI 2.0 clock recovery values
From: Clint Taylor Added HDMI 2.0 N and CTS values for 594 Pixel clock modes. Reorganized structure to group by Audio Sample Frequency Clint Taylor (2): drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values drm/i915/hdmi: Reorder structure to match specification drivers/gpu/drm/i915/intel_audio.c | 29 +++-- 1 file changed, 23 insertions(+), 6 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value
mode instead of HDMI specification values.
V2: Fix 88.2 Hz N value
Cc: Jani Nikula
Cc: sta...@vger.kernel.org
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 769f3f5..ee3ca2d 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -144,6 +144,9 @@ struct dp_aud_n_m {
/* HDMI N/CTS table */
#define TMDS_297M 297000
#define TMDS_296M 296703
+#define TMDS_594M 594000
+#define TMDS_593M 593407
+
static const struct {
int sample_rate;
int clock;
@@ -164,6 +167,20 @@ struct dp_aud_n_m {
{ 176400, TMDS_297M, 18816, 247500 },
{ 192000, TMDS_296M, 23296, 281250 },
{ 192000, TMDS_297M, 20480, 247500 },
+ { 44100, TMDS_593M, 8918, 937500 },
+ { 44100, TMDS_594M, 9408, 99 },
+ { 48000, TMDS_593M, 5824, 562500 },
+ { 48000, TMDS_594M, 6144, 594000 },
+ { 32000, TMDS_593M, 5824, 843750 },
+ { 32000, TMDS_594M, 3072, 445500 },
+ { 88200, TMDS_593M, 17836, 937500 },
+ { 88200, TMDS_594M, 18816, 99 },
+ { 96000, TMDS_593M, 11648, 562500 },
+ { 96000, TMDS_594M, 12288, 594000 },
+ { 176400, TMDS_593M, 35672, 937500 },
+ { 176400, TMDS_594M, 37632, 99 },
+ { 192000, TMDS_593M, 23296, 562500 },
+ { 192000, TMDS_594M, 24576, 594000 },
};
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
--
1.9.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Plane Input CSC for ICL (rev2)
== Series Details == Series: Enable Plane Input CSC for ICL (rev2) URL : https://patchwork.freedesktop.org/series/51463/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10582 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51463/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10582 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-plain-flip: fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@pm_rpm@basic-pci-d3-state: fi-glk-dsi: PASS -> INCOMPLETE (k.org#198133, fdo#103359) Possible fixes igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (46 -> 42) == Additional (1): fi-icl-u Missing(5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-glk-j4005 == Build changes == * Linux: CI_DRM_5037 -> Patchwork_10582 CI_DRM_5037: e11750586cb6054bd319ad217cecd045febaacc5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4694: ff8d1156723f235e82cb4fcfd2cd6e5a5bb211fa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10582: f8ddd10579f0945f49761c4af0e7eb23a5a1c7f8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f8ddd10579f0 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion 300ba10fc48e drm/i915/icl: Define Plane Input CSC Coefficient Registers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10582/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.20
On Thu, Oct 25, 2018 at 04:07:14PM +0300, Joonas Lahtinen wrote: > Quoting Zhenyu Wang (2018-10-23 06:46:59) > > > > Hi, > > > > Here's gvt-next-fixes for 4.20 with three changes. Mostly > > to fix possible arbitrary update on guest GGTT entry and > > with proper invalidate of old entry. Another one for one > > chicken reg mask fix. > > > > thanks > > Hi, > > DIM seems to be (rightfully) complaining about one commit: > > 3e740f0ec37acecaa364c19d2d2826df83c8bf20 is lacking committer of sign-off This is something I'm asking gvt for a while already: Please make review mandatory on your side. > > Probably better if you re-submit the PR for -fixes (rebased for > v4.20-rc1). > > Regards, Joonas > > > -- > > The following changes since commit 835fe6d75d14c1513910ed7f5665127fee12acc8: > > > > firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake. (2018-10-18 > > 10:36:10 +0300) > > > > are available in the Git repository at: > > > > https://github.com/intel/gvt-linux.git tags/gvt-next-fixes-2018-10-23 > > > > for you to fetch changes up to 3e740f0ec37acecaa364c19d2d2826df83c8bf20: > > > > drm/i915/gvt: correct mask setting for CSFE_CHICKEN1 (2018-10-19 11:32:41 > > +0800) > > > > > > gvt-next-fixes-2018-10-23 > > > > - Fix invalidate of old ggtt entry (Hang) > > - Fix partial ggtt entry update in any order (Hang) > > - Fix one mask setting for chicken reg (Xinyun) > > > > > > Hang Yuan (2): > > drm/i915/gvt: invalidate old ggtt page when update ggtt entry > > drm/i915/gvt: support inconsecutive partial gtt entry write > > > > Xinyun Liu (1): > > drm/i915/gvt: correct mask setting for CSFE_CHICKEN1 > > > > drivers/gpu/drm/i915/gvt/gtt.c | 115 > > > > drivers/gpu/drm/i915/gvt/gtt.h | 9 ++- > > drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- > > 3 files changed, 66 insertions(+), 60 deletions(-) > > > > > > -- > > Open Source Technology Center, Intel ltd. > > > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Plane Input CSC for ICL (rev2)
== Series Details == Series: Enable Plane Input CSC for ICL (rev2) URL : https://patchwork.freedesktop.org/series/51463/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers Okay! Commit: drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev2)
== Series Details == Series: Enable Plane Input CSC for ICL (rev2) URL : https://patchwork.freedesktop.org/series/51463/ State : warning == Summary == $ dim checkpatch origin/drm-tip 300ba10fc48e drm/i915/icl: Define Plane Input CSC Coefficient Registers -:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #51: FILE: drivers/gpu/drm/i915/i915_reg.h:6603: +#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #51: FILE: drivers/gpu/drm/i915/i915_reg.h:6603: +#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #67: FILE: drivers/gpu/drm/i915/i915_reg.h:6619: +#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #67: FILE: drivers/gpu/drm/i915/i915_reg.h:6619: +#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:83: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #83: FILE: drivers/gpu/drm/i915/i915_reg.h:6635: +#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) -:83: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #83: FILE: drivers/gpu/drm/i915/i915_reg.h:6635: +#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) total: 0 errors, 0 warnings, 6 checks, 62 lines checked f8ddd10579f0 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG
Conceptually user should be knowing the feature status through uAPI.
So HDCP authentication failure information need not DRM_ERRORS.
They are needed only for ENG debugging.
And also in HDCP we tolerate the retries for HDCP authentication.
Hence if we print the failure info initial attempts as ERRORs CI will
fail the IGT.
So we present the information of the failures in form of DRM_DEBUG
msgs for debugging purpose.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 46 +++
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 5b423a78518d..d92b04c3ed4e 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -166,8 +166,8 @@ static int intel_hdcp_load_keys(struct drm_i915_private
*dev_priv)
SKL_PCODE_LOAD_HDCP_KEYS, 1);
mutex_unlock(_priv->pcu_lock);
if (ret) {
- DRM_ERROR("Failed to initiate HDCP key load (%d)\n",
- ret);
+ DRM_DEBUG_KMS("Failed to initiate HDCP key load (%d)\n",
+ ret);
return ret;
}
} else {
@@ -195,7 +195,7 @@ static int intel_write_sha_text(struct drm_i915_private
*dev_priv, u32 sha_text)
I915_WRITE(HDCP_SHA_TEXT, sha_text);
if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
- DRM_ERROR("Timed out waiting for SHA1 ready\n");
+ DRM_DEBUG_KMS("Timed out waiting for SHA1 ready\n");
return -ETIMEDOUT;
}
return 0;
@@ -219,7 +219,7 @@ u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port
*intel_dig_port)
default:
break;
}
- DRM_ERROR("Unknown port %d\n", port);
+ DRM_DEBUG_KMS("Unknown port %d\n", port);
return -EINVAL;
}
@@ -448,7 +448,7 @@ int intel_hdcp_auth_downstream(struct intel_digital_port
*intel_dig_port,
ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
if (ret) {
- DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
+ DRM_DEBUG_KMS("KSV list failed to become ready (%d)\n", ret);
return ret;
}
@@ -458,7 +458,7 @@ int intel_hdcp_auth_downstream(struct intel_digital_port
*intel_dig_port,
if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
- DRM_ERROR("Max Topology Limit Exceeded\n");
+ DRM_DEBUG_KMS("Max Topology Limit Exceeded\n");
return -EPERM;
}
@@ -494,7 +494,7 @@ int intel_hdcp_auth_downstream(struct intel_digital_port
*intel_dig_port,
}
if (i == tries) {
- DRM_ERROR("V Prime validation failed.(%d)\n", ret);
+ DRM_DEBUG_KMS("V Prime validation failed.(%d)\n", ret);
goto err;
}
@@ -543,7 +543,7 @@ static int intel_hdcp_auth(struct intel_digital_port
*intel_dig_port,
if (ret)
return ret;
if (!hdcp_capable) {
- DRM_ERROR("Panel is not HDCP capable\n");
+ DRM_DEBUG_KMS("Panel is not HDCP capable\n");
return -EINVAL;
}
}
@@ -557,7 +557,7 @@ static int intel_hdcp_auth(struct intel_digital_port
*intel_dig_port,
if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
HDCP_STATUS_AN_READY,
HDCP_STATUS_AN_READY, 1)) {
- DRM_ERROR("Timed out waiting for An\n");
+ DRM_DEBUG_KMS("Timed out waiting for An\n");
return -ETIMEDOUT;
}
@@ -594,7 +594,7 @@ static int intel_hdcp_auth(struct intel_digital_port
*intel_dig_port,
/* Wait for R0 ready */
if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
(HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
- DRM_ERROR("Timed out waiting for R0 ready\n");
+ DRM_DEBUG_KMS("Timed out waiting for R0 ready\n");
return -ETIMEDOUT;
}
@@ -629,15 +629,15 @@ static int intel_hdcp_auth(struct intel_digital_port
*intel_dig_port,
}
if (i == tries) {
- DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
- I915_READ(PORT_HDCP_STATUS(port)));
+ DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n",
+ I915_READ(PORT_HDCP_STATUS(port)));
return -ETIMEDOUT;
}
/* Wait for encryption confirmation */
if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
[Intel-gfx] [v3 0/2] Enable Plane Input CSC for ICL
This patch series enables plane input csc feature for ICL. This is needed for YUV to RGB conversion on bottom 3 planes on ICL, other planes are handled in the legacy way using fixed function hardware. This series enables color conversion for Full Range YUV data, limited range handling will be done as a separate patch. v2: Separated the patch into 2 parts as per Maarten's comments. Addressed Ville and Maarten's review comment. v3: Redesigned the register macro definition as per Matt's comment. Addressed Maarten's review comment. Note: This is currently untested and floated to get feedback on the design and implementation for this feature. In parallel, I will test this on actual ICL hardware and confirm with planar formats. Uma Shankar (2): drm/i915/icl: Define Plane Input CSC Coefficient Registers drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion drivers/gpu/drm/i915/i915_reg.h | 50 +++ drivers/gpu/drm/i915/intel_color.c | 58 drivers/gpu/drm/i915/intel_display.c | 24 +++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ 4 files changed, 128 insertions(+), 6 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It programs the coefficients and enables
the plane input csc unit in hardware.
v2: Addressed Maarten's and Ville's review comments and added the
coefficients in a 2D array instead of independent Macros.
v3: Added individual coefficient matrix (9 values) instead of 6
register values as per Maarten's comment. Also addresed a shift
issue with B channel coefficient.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 58
drivers/gpu/drm/i915/intel_display.c | 24 +++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 78 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 5127da2..2f77c8b 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -57,6 +57,15 @@
#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
#define CSC_RGB_TO_YUV_BV 0x1e08
+#define ROFF(x) (((x) & 0x) << 16)
+#define GOFF(x) (((x) & 0x) << 0)
+#define BOFF(x) (((x) & 0x) << 16)
+
+/* Preoffset values for YUV to RGB Conversion */
+#define PREOFF_YUV_TO_RGB_HI 0x800
+#define PREOFF_YUV_TO_RGB_ME 0xF00
+#define PREOFF_YUV_TO_RGB_LO 0x800
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -643,6 +652,55 @@ int intel_color_check(struct drm_crtc *crtc,
return -EINVAL;
}
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ enum pipe pipe = crtc->pipe;
+ struct intel_plane *intel_plane =
+ to_intel_plane(plane_state->base.plane);
+ enum plane_id plane = intel_plane->id;
+
+ static const u16 input_csc_matrix[][9] = {
+ /* BT.601 full range YCbCr -> full range RGB */
+ [DRM_COLOR_YCBCR_BT601] = {
+ 0x7AF8, 7800, 0x0,
+ 0x8B28, 7800, 0x9AC0,
+ 0x0, 7800, 0x7DD8,
+ },
+ /* BT.709 full range YCbCr -> full range RGB */
+ [DRM_COLOR_YCBCR_BT709] = {
+ 0x7C98, 7800, 0x0,
+ 0x9EF8, 7800, 0xABF8,
+ 0x0, 0x7800, 0x7ED8,
+ },
+ };
+ const u16 *csc = input_csc_matrix[plane_state->base.color_encoding];
+
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 0), ROFF(csc[0]) |
+ GOFF(csc[1]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 1), BOFF(csc[2]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 2), ROFF(csc[3]) |
+ GOFF(csc[4]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 3), BOFF(csc[5]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 4), ROFF(csc[6]) |
+ GOFF(csc[7]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 5), BOFF(csc[8]));
+
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 0),
+ PREOFF_YUV_TO_RGB_HI);
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 1),
+ PREOFF_YUV_TO_RGB_ME);
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 2),
+ PREOFF_YUV_TO_RGB_LO);
+
+ I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 0), 0x0);
+ I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 1), 0x0);
+ I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 2), 0x0);
+}
+
void intel_color_init(struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe045ab..be65419 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3666,6 +3666,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state,
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+
u32 plane_color_ctl = 0;
if (INTEL_GEN(dev_priv) < 11) {
@@ -3676,13 +3678,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state,
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if
[Intel-gfx] [v3 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd register definition and simplified
the equally spaced register definition by adding an offset as
per Matt's comment.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 50 +
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573..d806e6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,6 +6569,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709(1 << 17)
@@ -6585,6 +6586,55 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A0x70278
#define _PLANE_NV12_BUF_CFG_2_A0x70378
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+_PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+_PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+_PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+_PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)\
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+_PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)\
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+_PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)\
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
--
1.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: fix call_kern.cocci warnings v3
Op 25-10-18 om 14:01 schreef Chunming Zhou:
>
> 在 2018/10/25 18:36, Maarten Lankhorst 写道:
>> Op 25-10-18 om 12:21 schreef Chunming Zhou:
>>> drivers/gpu/drm/drm_syncobj.c:202:4-14: ERROR: function
>>> drm_syncobj_find_signal_pt_for_point called on line 390 inside lock on line
>>> 389 but uses GFP_KERNEL
>>>
>>>Find functions that refer to GFP_KERNEL but are called with locks held.
>>>
>>> Generated by: scripts/coccinelle/locks/call_kern.cocci
>>>
>>> v2:
>>> syncobj->timeline still needs protect.
>>>
>>> v3:
>>> use a global signaled fence instead of re-allocation.
>>>
>>> Signed-off-by: Chunming Zhou
>>> Cc: Maarten Lankhorst
>>> Cc: intel-gfx@lists.freedesktop.org
>>> Cc: Christian König
>>> ---
>>> drivers/gpu/drm/drm_drv.c | 2 ++
>>> drivers/gpu/drm/drm_syncobj.c | 52 +--
>>> include/drm/drm_syncobj.h | 1 +
>>> 3 files changed, 34 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
>>> index 36e8e9cbec52..0a6f1023d6c3 100644
>>> --- a/drivers/gpu/drm/drm_drv.c
>>> +++ b/drivers/gpu/drm/drm_drv.c
>>> @@ -37,6 +37,7 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>>
>>> #include "drm_crtc_internal.h"
>>> #include "drm_legacy.h"
>>> @@ -1003,6 +1004,7 @@ static int __init drm_core_init(void)
>>> if (ret < 0)
>>> goto error;
>>>
>>> + drm_syncobj_stub_fence_init();
>>> drm_core_init_complete = true;
>>>
>>> DRM_DEBUG("Initialized\n");
>>> diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
>>> index b7eaa603f368..6b3f5a06e4d3 100644
>>> --- a/drivers/gpu/drm/drm_syncobj.c
>>> +++ b/drivers/gpu/drm/drm_syncobj.c
>>> @@ -80,6 +80,27 @@ struct drm_syncobj_signal_pt {
>>> struct list_head list;
>>> };
>>>
>>> +static struct drm_syncobj_stub_fence stub_signaled_fence;
>>> +static void global_stub_fence_release(struct dma_fence *fence)
>>> +{
>>> + /* it is impossible to come here */
>>> + BUG();
>>> +}
>> WARN_ON_ONCE(1)? No need to halt the machine.
>>
>>> +static const struct dma_fence_ops global_stub_fence_ops = {
>>> + .get_driver_name = drm_syncobj_stub_fence_get_name,
>>> + .get_timeline_name = drm_syncobj_stub_fence_get_name,
>>> + .release = global_stub_fence_release,
>>> +};
>>> +
>>> +void drm_syncobj_stub_fence_init(void)
>>> +{
>>> + spin_lock_init(_signaled_fence.lock);
>>> + dma_fence_init(_signaled_fence.base,
>>> + _stub_fence_ops,
>>> + _signaled_fence.lock,
>>> + 0, 0);
>>> + dma_fence_signal(_signaled_fence.base);
>>> +}
>>> /**
>>>* drm_syncobj_find - lookup and reference a sync object.
>>>* @file_private: drm file private pointer
>>> @@ -111,24 +132,14 @@ static struct dma_fence
>>> uint64_t point)
>>> {
>>> struct drm_syncobj_signal_pt *signal_pt;
>>> + struct dma_fence *f = NULL;
>>>
>>> + spin_lock(>pt_lock);
>>> if ((syncobj->type == DRM_SYNCOBJ_TYPE_TIMELINE) &&
>>> (point <= syncobj->timeline)) {
>>> - struct drm_syncobj_stub_fence *fence =
>>> - kzalloc(sizeof(struct drm_syncobj_stub_fence),
>>> - GFP_KERNEL);
>>> -
>>> - if (!fence)
>>> - return NULL;
>>> - spin_lock_init(>lock);
>>> - dma_fence_init(>base,
>>> - _syncobj_stub_fence_ops,
>>> - >lock,
>>> - syncobj->timeline_context,
>>> - point);
>>> -
>>> - dma_fence_signal(>base);
>>> - return >base;
>>> + dma_fence_get(_signaled_fence.base);
>>> + spin_unlock(>pt_lock);
>>> + return _signaled_fence.base;
>>> }
>>>
>>> list_for_each_entry(signal_pt, >signal_pt_list, list) {
>>> @@ -137,9 +148,12 @@ static struct dma_fence
>>> if ((syncobj->type == DRM_SYNCOBJ_TYPE_BINARY) &&
>>> (point != signal_pt->value))
>>> continue;
>>> - return dma_fence_get(_pt->fence_array->base);
>>> + f = dma_fence_get(_pt->fence_array->base);
>>> + break;
>>> }
>>> - return NULL;
>>> + spin_unlock(>pt_lock);
>>> +
>>> + return f;
>>> }
>>>
>>> static void drm_syncobj_add_callback_locked(struct drm_syncobj *syncobj,
>>> @@ -166,9 +180,7 @@ static void
>>> drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,
>>> }
>>>
>>> mutex_lock(>cb_mutex);
>>> - spin_lock(>pt_lock);
>>> *fence = drm_syncobj_find_signal_pt_for_point(syncobj, pt_value);
>>> - spin_unlock(>pt_lock);
>>> if (!*fence)
>>> drm_syncobj_add_callback_locked(syncobj, cb, func);
>>> mutex_unlock(>cb_mutex);
>>> @@ -379,11 +391,9 @@ drm_syncobj_point_get(struct drm_syncobj *syncobj, u64
>>> point, u64 flags,
>>> if (ret < 0)
>>>
