Re: [Intel-gfx] [v2 1/2] drm: Add colorspace property
Regards
Shashank
On 10/31/2018 5:35 PM, Uma Shankar wrote:
This patch adds a colorspace property enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the colorspace enum to incorporate both HDMI and DP supported
colorspaces. Also, added a default option for colorspace.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_uapi.c | 4
drivers/gpu/drm/drm_connector.c | 44 +++
include/drm/drm_connector.h | 7 +++
include/drm/drm_mode_config.h | 6 ++
include/uapi/drm/drm_mode.h | 24 +
5 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index d5b7f31..9e1d46b 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -721,6 +721,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
state->picture_aspect_ratio = val;
} else if (property == config->content_type_property) {
state->content_type = val;
+ } else if (property == config->colorspace_property) {
+ state->colorspace = val;
} else if (property == connector->scaling_mode_property) {
state->scaling_mode = val;
} else if (property == connector->content_protection_property) {
@@ -795,6 +797,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*val = state->picture_aspect_ratio;
} else if (property == config->content_type_property) {
*val = state->content_type;
+ } else if (property == config->colorspace_property) {
+ *val = state->colorspace;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
} else if (property == connector->content_protection_property) {
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index aa18b1d..5ad52a0 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -826,6 +826,38 @@ int drm_display_info_set_bus_formats(struct
drm_display_info *info,
};
DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list)
+static const struct drm_prop_enum_list colorspace[] = {
+ /* Standard Definition Colorimetry based on CEA 861 */
+ { COLORIMETRY_ITU_601, "601" },
+ { COLORIMETRY_ITU_709, "709" },
+ /* Standard Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_601, "601" },
+ /* High Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_709, "709" },
+ /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
+ { COLORIMETRY_S_YCC_601, "s601" },
+ /* Colorimetry based on IEC 61966-2-5 [33] */
+ { COLORIMETRY_ADOBE_YCC_601, "adobe601" },
+ /* Colorimetry based on IEC 61966-2-5 */
+ { COLORIMETRY_ADOBE_RGB, "adobe_rgb" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_RGB, "BT2020_rgb" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_YCC, "BT2020_ycc" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_CYCC, "BT2020_cycc" },
+ /* DP MSA Colorimetry */
+ { COLORIMETRY_Y_CBCR_ITU_601, "YCBCR_ITU_601" },
+ { COLORIMETRY_Y_CBCR_ITU_709, "YCBCR_ITU_709" },
+ { COLORIMETRY_SRGB, "SRGB" },
+ { COLORIMETRY_RGB_WIDE_GAMUT, "RGB Wide Gamut" },
+ { COLORIMETRY_SCRGB, "SCRGB" },
+ { COLORIMETRY_DCI_P3, "DCIP3" },
+ { COLORIMETRY_CUSTOM_COLOR_PROFILE, "Custom Proflie" },
+ /* FOR HD 720p+, Default Colorimetry is based on ITU-R BT.709 */
+ { COLORIMETRY_DEFAULT, "Default: ITU_709" },
+};
+
/**
* DOC: standard connector properties
*
@@ -972,6 +1004,12 @@ int drm_display_info_set_bus_formats(struct
drm_display_info *info,
*can also expose this property to external outputs, in which case they
*must support "None", which should be the default (since external screens
*have a built-in scaler).
+ *
+ * colorspace:
+ * This property helps select a suitable colorspace based on the sink
+ * capability. Modern sink devices support wider gamut like BT2020.
+ * This helps switch to BT2020 mode if the BT2020 encoded video stream
+ * is being played by the user, same for any other colorspace.
As commented on the previous patch, we might have to consider the HW
capability while doing this.
*/
int drm_connector_create_standard_properties(struct drm_device *dev)
@@ -1020,6 +1058,12 @@ int drm_connector_create_standard_properties(struct
drm_device *dev)
return -ENOMEM;
dev->mode_config.non_desktop_property = prop;
+ prop = drm_property_create_enum(dev,
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe
== Series Details == Series: series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe URL : https://patchwork.freedesktop.org/series/51997/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5083_full -> Patchwork_10721_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10721_full that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries_display_off: shard-skl: PASS -> INCOMPLETE (fdo#104108) igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@gem_render_copy@x-tiled: shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538) +1 igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-kbl: PASS -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-glk: PASS -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-256x85-random: shard-glk: PASS -> FAIL (fdo#103232) +2 igt@kms_cursor_crc@cursor-64x64-dpms: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_cursor_crc@cursor-64x64-offscreen: shard-skl: PASS -> FAIL (fdo#103232) +1 igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled: shard-glk: PASS -> FAIL (fdo#103184) igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled: shard-skl: PASS -> FAIL (fdo#103184) igt@kms_draw_crc@draw-method-xrgb-pwrite-untiled: shard-skl: PASS -> FAIL (fdo#108472) igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu: shard-skl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc: shard-skl: PASS -> FAIL (fdo#105682, fdo#103167) igt@kms_plane@pixel-format-pipe-c-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166) igt@kms_plane@plane-position-covered-pipe-a-planes: shard-apl: PASS -> FAIL (fdo#103166) +3 igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: shard-skl: PASS -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: shard-kbl: PASS -> DMESG-FAIL (fdo#105602, fdo#103558) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_vblank@pipe-b-wait-forked-busy: shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +2 igt@pm_backlight@fade_with_suspend: shard-skl: NOTRUN -> FAIL (fdo#107847) igt@pm_rpm@system-suspend-devices: shard-skl: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_exec_reloc@basic-wc-cpu-noreloc: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: FAIL (fdo#106641) -> PASS igt@kms_cursor_crc@cursor-128x128-random: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_crc@cursor-256x256-dpms: shard-glk: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_crc@cursor-64x64-suspend: shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: shard-apl: FAIL (fdo#103167) -> PASS +3 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: shard-glk: FAIL (fdo#103167) -> PASS +4 igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +3 shard-apl: FAIL (fdo#103166) -> PASS +1 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763
Re: [Intel-gfx] [v2 0/2] Add Colorspace connector property interface
Hello Uma, My comments inline. On 10/31/2018 5:35 PM, Uma Shankar wrote: This patch series creates a new connector property to program colorspace to sink devices. Modern sink devices support more than 1 type of colorspace like 601, 709, BT2020 etc. This helps to switch based on content type which is to be displayed. The decision lies with compositors as to in which scenarios, a particular colorspace will be picked. This will be helpful mostly to switch to higher gamut colorspaces like BT2020 when the media content is encoded as BT2020. Thereby giving a good visual experience to users. The expectation from userspace is that it should parse the EDID and get supported colorspaces. Use this property and switch to the one supported. Kernel will not give the supported colorspaces since this is panel dependent and our curremt property infrastructure is not supporting it. I am not very sure about this part, consider a situation where, I have connected a HDMI 2.0 monitor which supports BT2020 gamut, to a GEN9 device, running an user-space which can also support BT2020 playback / HDR playback. Now, both monitor and user-space supports BT2020 playback, but the HW doesn't, and this will create a problem during playback. So I gess we need to expose a kernel Cap or property to showcase if the HW can support BT2020/DCI-P3 gamut space or not. - Shashank Have tested this using xrandr by using below command: xrandr --output HDMI2 --set "Colorspace" "BT2020_rgb" v2: Addressed Ville and Maarten's review comments. Merged the 2nd and 3rd patch into one common logical patch. Uma Shankar (2): drm: Add colorspace property drm/i915: Attach colorspace property and enable modeset drivers/gpu/drm/drm_atomic_uapi.c | 4 drivers/gpu/drm/drm_connector.c | 44 + drivers/gpu/drm/i915/intel_atomic.c | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 5 + include/drm/drm_connector.h | 7 ++ include/drm/drm_mode_config.h | 6 + include/uapi/drm/drm_mode.h | 24 7 files changed, 91 insertions(+) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe
== Series Details == Series: series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe URL : https://patchwork.freedesktop.org/series/51997/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5083 -> Patchwork_10721 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51997/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10721 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS Warnings igt@drv_selftest@live_contexts: fi-icl-u2: INCOMPLETE (fdo#108315) -> DMESG-FAIL (fdo#108569) fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (50 -> 45) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5083 -> Patchwork_10721 CI_DRM_5083: a4e9f377a9b50521b5a07c544c97f67e3338f2c3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4706: 5421c73a7db3cfaa85ab24325fe6e898cbb27fb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10721: 64bb1ef628e8d7a30c1114e92be96158053bdd8d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 64bb1ef628e8 drm/i915/dsc: Add Per connector debugfs node for DSC support/enable 9e778cbe005f drm/i915/dsc: Enable and disable appropriate power wells for VDSC 2a5b79ad1d98 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits a92c77c255c1 drm/i915/dp: Configure Display stream splitter registers during DSC enable 60aae01038ed drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 093a1a6e72a0 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 55228524d5aa drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 3ff059cd1079 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 6d3d7696244f drm/i915/dp: Enable/Disable DSC in DP Sink d30d485fbaa5 drm/i915/dsc: Compute Rate Control parameters for DSC a11590e2c032 drm/i915/dsc: Define & Compute VESA DSC params 7f3efca7e47a drm/i915/dp: Do not enable PSR2 if DSC is enabled 476f87616dbe drm/i915/dp: Compute DSC pipe config in atomic check d16ba85051ec drm/i915/dp: Add DSC params and DSC config to intel_crtc_state 16ed1feab6af drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants 2fdfc3121810 drm/dsc: Add helpers for DSC picture parameter set infoframes 9e8cbea7c63a drm/dsc: Define Rate Control values that do not change over configurations c5a2fc29ad7f drm/dsc: Define VESA Display Stream Compression Capabilities e904fd188f2c drm/dsc: Define Display Stream Compression PPS infoframe == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10721/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: HPD IRQ storm detection fixes (rev3)
== Series Details == Series: drm/i915: HPD IRQ storm detection fixes (rev3) URL : https://patchwork.freedesktop.org/series/51556/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5082_full -> Patchwork_10720_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10720_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10720_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10720_full: === IGT changes === Warnings igt@kms_plane@plane-panning-bottom-right-pipe-b-planes: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10720_full that come from known issues: === IGT changes === Issues hit igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_cursor_crc@cursor-128x42-random: shard-glk: PASS -> FAIL (fdo#103232) +3 igt@kms_cursor_crc@cursor-64x64-dpms: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) +1 Possible fixes igt@drv_suspend@debugfs-reader: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: FAIL (fdo#106641) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: shard-kbl: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-128x42-onscreen: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_crc@cursor-64x64-dpms: shard-glk: FAIL (fdo#103232) -> PASS +1 igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled: shard-skl: FAIL (fdo#103184) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: FAIL (fdo#103167, fdo#105682) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: shard-glk: FAIL (fdo#103167) -> PASS +3 igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: shard-skl: FAIL (fdo#103167) -> PASS +3 igt@kms_pipe_crc_basic@read-crc-pipe-a: shard-skl: FAIL (fdo#107362) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS igt@perf@blocking: shard-hsw: FAIL (fdo#102252) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_5082 -> Patchwork_10720 CI_DRM_5082: 71cc71176de66cc725595a436f761f183a8b9ca7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4706: 5421c73a7db3cfaa85ab24325fe6e898cbb27fb3
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe
== Series Details == Series: series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe URL : https://patchwork.freedesktop.org/series/51997/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:200:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:200:61:got int +drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:207:25:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:207:25:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types) Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1896:23: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3709:16: warning: expression using sizeof(void) Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC Okay! Commit: drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe
== Series Details ==
Series: series starting with [CI,01/19] drm/dsc: Define Display Stream
Compression PPS infoframe
URL : https://patchwork.freedesktop.org/series/51997/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e904fd188f2c drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 342 lines checked
c5a2fc29ad7f drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Gaurav K Singh
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
9e8cbea7c63a drm/dsc: Define Rate Control values that do not change over
configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Srivatsa, Anusha '
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
2fdfc3121810 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 285 lines checked
16ed1feab6af drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
d16ba85051ec drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:942:
+ bool compression_enable;
-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
476f87616dbe drm/i915/dp: Compute DSC pipe config in atomic check
-:273: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#273: FILE: drivers/gpu/drm/i915/intel_dp.c:2112:
+ limits.max_bpp >= DP_DSC_MIN_SUPPORTED_BPC*3)
^
total: 0 errors, 0 warnings, 1 checks, 292 lines checked
7f3efca7e47a drm/i915/dp: Do not enable PSR2 if DSC is enabled
a11590e2c032 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68:
Co-developed-by: Manasi Navare
-:95: WARNING:MISSING_SPACE: break quoted strings at a space character
#95: FILE: drivers/gpu/drm/i915/intel_dp.c:2080:
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#119:
new file mode 100644
-:405: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#405: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3 warnings, 1 checks, 496 lines checked
d30d485fbaa5 drm/i915/dsc: Compute Rate Control parameters for DSC
-:141: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#141: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+ vdsc_cfg->slice_bpg_offset)*
^
-:173: CHECK:LINE_SPACING: Please don't use multiple blank lines
#173: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+
total: 0 errors, 0 warnings, 2 checks, 138 lines checked
6d3d7696244f drm/i915/dp: Enable/Disable DSC in DP Sink
3ff059cd1079 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
55228524d5aa drm/i915/dp: Configure
[Intel-gfx] [CI 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v4:
* Add missed connector_status check (Manasi)
* Create i915_dsc_support node only for Gen >=10 (manasi)
* Access intel_dp->dsc_dpcd only if its not NULL (Manasi)
v3:
* Combine Force_dsc_en with this patch (Ville)
v2:
* Use kstrtobool_from_user to avoid explicit error checking (Lyude)
* Rebase on drm-tip (Manasi)
Cc: Rodrigo Vivi
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Lyude Paul
Signed-off-by: Manasi Navare
Reviewed-by: Lyude Paul
---
drivers/gpu/drm/i915/i915_debugfs.c | 77 +
drivers/gpu/drm/i915/intel_dp.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h| 3 ++
3 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a4d9d996fda..195591ff578a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5000,6 +5000,76 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_dsc_support_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_encoder *encoder = intel_attached_encoder(connector);
+ struct intel_dp *intel_dp =
+ enc_to_intel_dp(>base);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ crtc = to_intel_crtc(encoder->base.crtc);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+ drm_modeset_lock(>base.mutex, NULL);
+ seq_printf(m, "Enabled: %s\n",
+ yesno(crtc_state->dsc_params.compression_enable));
+ if (intel_dp->dsc_dpcd)
+ seq_printf(m, "Supported: %s\n",
+ yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+ drm_modeset_unlock(>base.mutex);
+
+ return 0;
+}
+
+static ssize_t i915_dsc_support_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ bool dsc_enable = false;
+ int ret;
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder = intel_attached_encoder(connector);
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+
+ if (len == 0)
+ return 0;
+
+ DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
+(unsigned int)len);
+
+ ret = kstrtobool_from_user(ubuf, len, _enable);
+ if (ret < 0)
+ return ret;
+
+ DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
+(dsc_enable) ? "true" : "false");
+ intel_dp->force_dsc_en = dsc_enable;
+
+ *offp += len;
+ return len;
+}
+
+static int i915_dsc_support_open(struct inode *inode,
+struct file *file)
+{
+ return single_open(file, i915_dsc_support_show,
+ inode->i_private);
+}
+
+static const struct file_operations i915_dsc_support_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_support_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_support_write
+};
+
/**
* i915_debugfs_connector_add - add i915 specific connector debugfs files
* @connector: pointer to a registered drm_connector
@@ -5012,6 +5082,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
int i915_debugfs_connector_add(struct drm_connector *connector)
{
struct dentry *root = connector->debugfs_entry;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
/* The connector must have been registered beforehands. */
if (!root)
@@ -5036,5 +5107,11 @@ int i915_debugfs_connector_add(struct drm_connector
*connector)
connector, _hdcp_sink_capability_fops);
}
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+connector->connector_type == DRM_MODE_CONNECTOR_eDP))
+ debugfs_create_file("i915_dsc_support", S_IRUGO, root,
+ connector, _dsc_support_fops);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4464f18d99c1..ebe679de3f41 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2161,7 +2161,7 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
[Intel-gfx] [CI 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 6 +
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_vdsc.c| 419 +++
4 files changed, 428 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 994f9bfcd483..d0e5440d14ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3485,6 +3485,8 @@ extern void intel_rps_mark_interactive(struct
drm_i915_private *i915,
bool interactive);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index af12c15ed94f..bba08322afb7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2962,6 +2962,12 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
+
+ /*
+* Enable and Configure Display Stream Compression in the source
+* if enabled in intel_crtc_state.
+*/
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6cc64c132c8c..00ef825dcbf4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5417,6 +5417,7 @@ static void intel_encoders_pre_enable(struct drm_crtc
*crtc,
if (encoder->pre_enable)
encoder->pre_enable(encoder, crtc_state, conn_state);
+
}
}
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index a76f78b9c0ee..0eaa69778160 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -580,3 +580,422 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return 0;
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ else
+ pps_val &= ~DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ else
+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ else
+ pps_val &= ~DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ else
+ pps_val &= ~DSC_VBR_ENABLE;
+
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+ /*
+* If 2
[Intel-gfx] [CI 14/19] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 21 +++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 672fcdab4d23..1a84e8f98e66 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4567,6 +4567,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index bc5b945f9a71..ae751679047c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ int data_size;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
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[Intel-gfx] [CI 03/19] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 3292dfed9d0a..b88e31bd9da7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
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[Intel-gfx] [CI 09/19] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
5 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 28c7d7884e88..a51a9ae0f496 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -156,7 +156,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9a1af25f3316..df5a0cbc744d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2075,6 +2075,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1a51d7852be0..ab6c4a1efc51 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1854,6 +1854,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..0a1918f2f643
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh
+ * Manasi Navare
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+
[Intel-gfx] [CI 12/19] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index b0b23e1e9392..4e6b824ccc8c 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -226,6 +226,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c453366cd24..acbe52adbf16 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2006,9 +2008,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
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[Intel-gfx] [CI 01/19] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
v4:
* Remove redundant blankline in doc (Ville)
* use drm_dsc namespace for all structs (Ville)
* Use packed struct (Ville)
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
---
include/drm/drm_dsc.h | 342 ++
1 file changed, 342 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index ..78db4f61d01c
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct drm_dsc_picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16 pic_width;
+ /**
+* @slice_height:
+* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+*/
+ __be16 slice_height;
+ /**
+* @slice_width:
+* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+*/
+ __be16 slice_width;
+ /**
+* @chunk_size:
+* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+* that are used for slice multiplexing.
+*/
+ __be16 chunk_size;
+ /**
+* @initial_xmit_delay_high:
+* PPS16[1:0] - Most Significant two bits of initial transmission delay.
+* It specifies the number of pixel times that the encoder waits before
+* transmitting data from its rate buffer.
+* PPS16[7:2] - Reserved
+*/
+
[Intel-gfx] [CI 05/19] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
--
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[Intel-gfx] [CI 08/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bc2d88313ed0..08967657b742 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
if (i915_modparams.enable_psr == -1)
return false;
+ /* Cannot enable DSC and PSR2 simultaneously */
+ WARN_ON(crtc_state->dsc_params.compression_enable &&
+ crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -463,6 +467,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.18.0
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[Intel-gfx] [CI 17/19] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c| 32
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d0e5440d14ca..83d0ada15821 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3487,6 +3487,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
extern void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 00ef825dcbf4..d66ae04a66c5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5848,6 +5848,8 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index fae5193551d8..02102cd275fd 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1041,3 +1041,35 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+}
--
2.18.0
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[Intel-gfx] [CI 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 127 ++
1 file changed, 127 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0a1918f2f643..a76f78b9c0ee 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_DEBUG_KMS("FinalOfs < RcModelSze for this
InitialXmitDelay\n");
+ return -EINVAL;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size * 8) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_DEBUG_KMS("NflBpgOffset is too large for this slice
height\n");
+ return -EINVAL;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+
[Intel-gfx] [CI 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed-by: Gaurav K Singh
Acked-by: Harry Wentland
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 78db4f61d01c..3292dfed9d0a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
#include
/* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES 15
+#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+#define DSC_RC_PIXELS_PER_GROUP3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
+#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+
+/* Configuration for a single Rate Control model range */
+struct drm_dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie.,
[Intel-gfx] [CI 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0eaa69778160..85af5f784aad 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(encoder, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -997,5 +1016,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
2.18.0
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[Intel-gfx] [CI 16/19] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 85af5f784aad..fae5193551d8 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1010,6 +1010,12 @@ static void intel_dp_write_dsc_pps_sdp(struct
intel_encoder *encoder,
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1018,5 +1024,20 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.18.0
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[Intel-gfx] [CI 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 20 +++-
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 170 ---
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
4 files changed, 169 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 31fbf67cb661..6cc64c132c8c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
- intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+ intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
link_bw, _config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n)
{
m_n->tu = 64;
- compute_m_n(bits_per_pixel * pixel_clock,
- link_clock * nlanes * 8,
- _n->gmch_m, _n->gmch_n,
- constant_n);
+ /* For DSC, Data M/N calculation uses compressed BPP */
+ if (compressed_bpp)
+ compute_m_n(compressed_bpp * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
+ else
+ compute_m_n(bits_per_pixel * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..b0b23e1e9392 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -407,7 +407,8 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d6ee11525dd9..9a1af25f3316 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1840,6 +1842,29 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+
[Intel-gfx] [CI 06/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
v2:
* Rebase on drm-tip (Manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2a88a7eb871b..994f9bfcd483 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include "i915_params.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3bebc1c31157..1a51d7852be0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -936,6 +936,15 @@ struct intel_crtc_state {
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
2.18.0
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[Intel-gfx] [CI 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 16
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3eea987e909b..af12c15ed94f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2952,6 +2952,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3291,6 +3293,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ false);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index df5a0cbc744d..4464f18d99c1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2975,6 +2975,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE,
+enable ? DP_DECOMPRESSION_EN : 0);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ enable ? "enable" : "disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ab6c4a1efc51..ff20efbe78b4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1796,6 +1796,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.18.0
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[Intel-gfx] [CI 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v7:
* Use BUILD_BUG_ON() to protect changing struct size (Ville)
* Remove typecaseting (Ville)
* Include byteorder.h in drm_dsc.c (Ville)
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in
Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 228 ++
include/drm/drm_dsc.h | 21 +++
4 files changed, 262 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index 4b4dc236ef6f..b422eb8edf16 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 576ba985e138..3a3e6fb6d476 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index ..3a4942c1ae3b
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ const struct drm_dsc_config *dsc_cfg)
+{
+ int i;
+
+ /*Protect against someone accidently changing struct size */
+ BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+
+ memset(_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version =
+ dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+ /* PPS 3 */
+
[Intel-gfx] [CI 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c | 25 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index bba08322afb7..82d78f2727d8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2126,6 +2126,12 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+ /*
+* VDSC power is needed when DSC is enabled
+*/
+ if (crtc_state->dsc_params.compression_enable)
+ domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ff20efbe78b4..4d7339305dd1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1860,6 +1860,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp, int mode_clock,
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 02102cd275fd..a25b71ae9b1c 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -581,6 +581,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return 0;
}
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ /*
+* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* For any other transcoder, VDSC/joining uses the power well associated
+* with the pipe/transcoder in use. Hence another reference on the
+* transcoder power domain will suffice.
+*/
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else
+ return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
@@ -1020,6 +1038,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
+ /* Enable Power wells for VDSC/joining */
+ intel_display_power_get(dev_priv,
+ intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1072,4 +1094,7 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+ /* Disable Power wells for VDSC/joining */
+ intel_display_power_put(dev_priv,
+ intel_dsc_power_domain(old_crtc_state));
}
--
2.18.0
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Re: [Intel-gfx] [v4 7/7] drm/i915/fec: Disable FEC state.
On Tue, Oct 30, 2018 at 05:45:17PM -0700, Anusha Srivatsa wrote:
> Set the suitable bits in DP_TP_CTL to stop
> bit correction when DSC is disabled.
>
> v2:
> - rebased.
> - Add additional check for compression state. (Gaurav)
>
> v3: rebased.
>
> v4:
> - Move the code to the proper spot according to spec (Ville)
> - Use proper checks (manasi)
>
> Cc: Gaurav K Singh
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Manasi Navare
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 32
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 2 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f03f44f332c7..d28280c3b299 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2915,6 +2915,31 @@ void intel_dp_enable_fec_state(struct intel_dp
> *intel_dp,
> DRM_ERROR("Timed out waiting for FEC Enable Status\n");
> }
>
> +void intel_dp_disable_fec_state(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + enum port port = intel_dig_port->base.port;
> + u32 val;
> + u8 dsc_en_state;
> +
> + if (!crtc_state->fec_enable)
> + return;
> +
> + if (!crtc_state->dsc_params.compression_enable)
> + return;
> +
> + drm_dp_dpcd_readb(_dp->aux, DP_DSC_ENABLE, _en_state);
> +
> + if (!dsc_en_state) {
> + val = I915_READ(DP_TP_CTL(port));
> + val &= ~DP_TP_CTL_FEC_ENABLE;
> + I915_WRITE(DP_TP_CTL(port), val);
> + POSTING_READ(DP_TP_CTL(port));
> + }
> +}
> +
> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state
> *conn_state)
> @@ -3055,7 +3080,11 @@ static void intel_ddi_pre_enable(struct intel_encoder
> *encoder,
> static void intel_disable_ddi_buf(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(>base);
> + struct intel_dp *intel_dp = _port->dp;
> + struct intel_crtc_state *crtc_state;
> enum port port = encoder->port;
> +
> bool wait = false;
> u32 val;
>
> @@ -3071,6 +3100,9 @@ static void intel_disable_ddi_buf(struct intel_encoder
> *encoder)
> val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> I915_WRITE(DP_TP_CTL(port), val);
>
> + /* Disable FEC in DP Sink */
> + intel_dp_disable_fec_state(intel_dp, crtc_state);
crtc_state is uninitialized here. You need to pass crtc_state to
intel_disable_ddi_buf()
or just call intel_dp_disable_fec_state() from the caller of
intel_disable_ddi_buf() right
after it.
Manasi
> +
> if (wait)
> intel_wait_ddi_buf_idle(dev_priv, port);
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 1cdfa9c5da43..4ed04fad83b7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1801,6 +1801,8 @@ void intel_dp_sink_set_fec_ready(struct intel_dp
> *intel_dp,
>int state);
> void intel_dp_enable_fec_state(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> +void intel_dp_disable_fec_state(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> void intel_dp_encoder_reset(struct drm_encoder *encoder);
> void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
> void intel_dp_encoder_destroy(struct drm_encoder *encoder);
> --
> 2.17.1
>
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Re: [Intel-gfx] [PATCH v8 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
On Fri, Nov 02, 2018 at 02:31:38PM -0700, Manasi Navare wrote:
> DSC can be supported per DP connector. This patch adds a per connector
> debugfs node to expose DSC support capability by the kernel.
> The same node can be used from userspace to force DSC enable.
>
> force_dsc_en written through this debugfs node is used to force
> DSC even for lower resolutions.
>
> v3:
> * Combine Force_dsc_en with this patch (Ville)
> v2:
> * Use kstrtobool_from_user to avoid explicit error checking (Lyude)
> * Rebase on drm-tip (Manasi)
>
> Cc: Rodrigo Vivi
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Lyude Paul
> Signed-off-by: Manasi Navare
> Reviewed-by: Lyude Paul
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 71 -
> drivers/gpu/drm/i915/intel_dp.c | 3 +-
> drivers/gpu/drm/i915/intel_drv.h| 3 ++
> 3 files changed, 75 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1a4d9d996fda..fe619b54b64d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -5000,6 +5000,72 @@ static int i915_hdcp_sink_capability_show(struct
> seq_file *m, void *data)
> }
> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>
> +static int i915_dsc_support_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct intel_encoder *encoder = intel_attached_encoder(connector);
> + struct intel_dp *intel_dp =
> + enc_to_intel_dp(>base);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
Missed this check in the rebase or respin:
if (connector->status != connector_status_connected)
resulting into a lot of CI errors. will fix this in the next rev
> +
> + crtc = to_intel_crtc(encoder->base.crtc);
> + crtc_state = to_intel_crtc_state(crtc->base.state);
> + drm_modeset_lock(>base.mutex, NULL);
> + seq_printf(m, "Enabled: %s\n",
> +yesno(crtc_state->dsc_params.compression_enable));
> + seq_printf(m, "Supported: %s\n",
> +yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> + drm_modeset_unlock(>base.mutex);
> +
> + return 0;
> +}
> +
> +static ssize_t i915_dsc_support_write(struct file *file,
> + const char __user *ubuf,
> + size_t len, loff_t *offp)
> +{
> + bool dsc_enable = false;
> + int ret;
> + struct drm_connector *connector =
> + ((struct seq_file *)file->private_data)->private;
> + struct intel_encoder *encoder = intel_attached_encoder(connector);
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> +
> + if (len == 0)
> + return 0;
> +
> + DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
> + (unsigned int)len);
> +
> + ret = kstrtobool_from_user(ubuf, len, _enable);
> + if (ret < 0)
> + return ret;
> +
> + DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
> + (dsc_enable) ? "true" : "false");
> + intel_dp->force_dsc_en = dsc_enable;
> +
> + *offp += len;
> + return len;
> +}
> +
> +static int i915_dsc_support_open(struct inode *inode,
> + struct file *file)
> +{
> + return single_open(file, i915_dsc_support_show,
> +inode->i_private);
> +}
> +
> +static const struct file_operations i915_dsc_support_fops = {
> + .owner = THIS_MODULE,
> + .open = i915_dsc_support_open,
> + .read = seq_read,
> + .llseek = seq_lseek,
> + .release = single_release,
> + .write = i915_dsc_support_write
> +};
> +
> /**
> * i915_debugfs_connector_add - add i915 specific connector debugfs files
> * @connector: pointer to a registered drm_connector
> @@ -5018,9 +5084,12 @@ int i915_debugfs_connector_add(struct drm_connector
> *connector)
> return -ENODEV;
>
> if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> - connector->connector_type == DRM_MODE_CONNECTOR_eDP)
> + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> debugfs_create_file("i915_dpcd", S_IRUGO, root,
> connector, _dpcd_fops);
> + debugfs_create_file("i915_dsc_support", S_IRUGO, root,
> + connector, _dsc_support_fops);
also since DSC only supported on GEN >= 10, should we create this node only for
higher GENs?
Manasi
> + }
>
> if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> debugfs_create_file("i915_panel_timings", S_IRUGO, root,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f8bf942c8f71..4d866d49d870 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2158,7 +2158,7 @@
Re: [Intel-gfx] [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic check phase.
> These values are then later used to populate the remaining DSC
> and RC parameters before enbaling DSC in atomic commit.
>
> v11:
> * Const crtc_state, reject DSC on DP without FEC (Ville)
> * Dont set dsc_split to false (Ville)
> v10:
> * Add a helper for dp_dsc support (Ville)
> * Set pipe_config to max bpp, link params for DSC for now (Ville)
> * Compute bpp - use dp dsc support helper (Ville)
> v9:
> * Rebase on top of drm-tip that now uses fast_narrow config
> for edp (Manasi)
> v8:
> * Check for DSC bpc not 0 (manasi)
>
> v7:
> * Fix indentation in compute_m_n (Manasi)
>
> v6 (From Gaurav):
> * Remove function call of intel_dp_compute_dsc_params() and
> invoke intel_dp_compute_dsc_params() in the patch where
> it is defined to fix compilation warning (Gaurav)
>
> v5:
> Add drm_dsc_cfg in intel_crtc_state (Manasi)
>
> v4:
> * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> * Add a comment why we need to check PSR while enabling DSC (Gaurav)
>
> v3:
> * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
>
> v2:
> * Add if-else for eDP/DP (Gaurav)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Manasi Navare
> Reviewed-by: Anusha Srivatsa
> Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 +++-
> drivers/gpu/drm/i915/intel_display.h | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 167 ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> 4 files changed, 166 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b219d5858160..477e53c37353 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct
> intel_crtc *intel_crtc,
>
> pipe_config->fdi_lanes = lane;
>
> - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> link_bw, _config->fdi_m_n, false);
>
> ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> @@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned int
> n,
> }
>
> void
> -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> +int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n)
> {
> m_n->tu = 64;
>
> - compute_m_n(bits_per_pixel * pixel_clock,
> - link_clock * nlanes * 8,
> - _n->gmch_m, _n->gmch_n,
> - constant_n);
> + /* For DSC, Data M/N calculation uses compressed BPP */
> + if (compressed_bpp)
> + compute_m_n(compressed_bpp * pixel_clock,
> + link_clock * nlanes * 8,
> + _n->gmch_m, _n->gmch_n,
> + constant_n);
> + else
> + compute_m_n(bits_per_pixel * pixel_clock,
> + link_clock * nlanes * 8,
> + _n->gmch_m, _n->gmch_n,
> + constant_n);
>
> compute_m_n(pixel_clock, link_clock,
> _n->link_m, _n->link_n,
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..b0b23e1e9392 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -407,7 +407,8 @@ struct intel_link_m_n {
>(__i)++) \
> for_each_if(plane)
>
> -void intel_link_compute_m_n(int bpp, int nlanes,
> +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> + int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b39b4bda8e40..58326fc9d935 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -47,6 +47,8 @@
>
> /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> +#define DP_DSC_MIN_SUPPORTED_BPC 8
> +#define DP_DSC_MAX_SUPPORTED_BPC 10
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: HPD IRQ storm detection fixes (rev3)
== Series Details == Series: drm/i915: HPD IRQ storm detection fixes (rev3) URL : https://patchwork.freedesktop.org/series/51556/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5082 -> Patchwork_10720 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10720 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10720, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51556/revisions/3/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10720: === IGT changes === Warnings igt@pm_rpm@module-reload: fi-hsw-4770r: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10720 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107425, fdo#107924) igt@drv_selftest@live_execlists: fi-apl-guc: PASS -> INCOMPLETE (fdo#103927, fdo#106693) igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107774, fdo#107556, fdo#107859) igt@prime_vgem@basic-fence-flip: fi-cfl-8700k: PASS -> FAIL (fdo#104008) Possible fixes igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cfl-8109u: INCOMPLETE (fdo#106070, fdo#108126) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693 fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126 == Participating hosts (50 -> 44) == Additional (1): fi-kbl-soraka Missing(7): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 == Build changes == * Linux: CI_DRM_5082 -> Patchwork_10720 CI_DRM_5082: 71cc71176de66cc725595a436f761f183a8b9ca7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4706: 5421c73a7db3cfaa85ab24325fe6e898cbb27fb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10720: c09ca9624feda6f8d963e5a085056fbc6fb92202 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c09ca9624fed drm/i915: Add short HPD IRQ storm detection for non-MST systems 0d11bfe6ec1c drm/i915: Clarify flow for disabling IRQs on storms c3d529fb232c drm/i915: Fix threshold check in intel_hpd_irq_storm_detect() d44d4e697a61 drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST a7f26c0167e3 drm/i915: Fix possible race in intel_dp_add_mst_connector() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10720/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Fix suspend/resume for TypeC HDMI
== Series Details == Series: drm/i915/icl: Fix suspend/resume for TypeC HDMI URL : https://patchwork.freedesktop.org/series/51976/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10716_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10716_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10716_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10716_full: === IGT changes === Possible regressions igt@kms_cursor_crc@cursor-64x21-offscreen: shard-skl: PASS -> INCOMPLETE Warnings igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy: shard-snb: SKIP -> PASS +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt: shard-snb: PASS -> SKIP +1 igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10716_full that come from known issues: === IGT changes === Issues hit igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-glk: PASS -> DMESG-WARN (fdo#107956) igt@kms_chv_cursor_fail@pipe-b-128x128-bottom-edge: shard-skl: PASS -> FAIL (fdo#104671) igt@kms_chv_cursor_fail@pipe-b-64x64-bottom-edge: shard-kbl: PASS -> DMESG-WARN (fdo#105345) igt@kms_color@pipe-c-legacy-gamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#106509, fdo#105454) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-skl: NOTRUN -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: shard-skl: PASS -> FAIL (fdo#107362, fdo#103191) igt@kms_plane@plane-position-covered-pipe-c-planes: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108) Possible fixes igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-skl: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-128x128-suspend: shard-skl: INCOMPLETE (fdo#104108) -> PASS igt@kms_cursor_crc@cursor-128x42-random: shard-skl: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x256-sliding: shard-glk: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_crc@cursor-256x85-random: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_flip@flip-vs-expired-vblank: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane@plane-position-covered-pipe-b-planes: shard-glk: FAIL (fdo#103166) -> PASS +2 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@pm_rpm@legacy-planes-dpms: shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: HPD IRQ storm detection fixes (rev3)
== Series Details == Series: drm/i915: HPD IRQ storm detection fixes (rev3) URL : https://patchwork.freedesktop.org/series/51556/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix possible race in intel_dp_add_mst_connector() Okay! Commit: drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST Okay! Commit: drm/i915: Fix threshold check in intel_hpd_irq_storm_detect() Okay! Commit: drm/i915: Clarify flow for disabling IRQs on storms Okay! Commit: drm/i915: Add short HPD IRQ storm detection for non-MST systems -drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/5] drm/i915: Fix threshold check in intel_hpd_irq_storm_detect()
Currently in intel_hpd_irq_storm_detect() when we detect that the last
recorded hotplug wasn't within the period defined by
HPD_STORM_DETECT_DELAY, we make the mistake of resetting the HPD count
to 0 without incrementing it. This results in us only enabling storm
detection when we go +2 above the threshold, e.g. an HPD threshold of 5
would not trigger a storm until we reach a total of 7 hotplugs.
So: rework the code a bit so we reset the HPD count when
HPD_STORM_DETECT_DELAY has passed, then increment the count afterwards.
Also, clean things up a bit to make it easier to undertand.
Cc: Ville Syrjälä
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/i915/intel_hotplug.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
b/drivers/gpu/drm/i915/intel_hotplug.c
index 8326900a311e..c11d73de16f2 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -135,24 +135,27 @@ enum hpd_pin intel_hpd_pin_default(struct
drm_i915_private *dev_priv,
static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
enum hpd_pin pin)
{
- unsigned long start = dev_priv->hotplug.stats[pin].last_jiffies;
+ struct i915_hotplug *hpd = _priv->hotplug;
+ unsigned long start = hpd->stats[pin].last_jiffies;
unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
- const int threshold = dev_priv->hotplug.hpd_storm_threshold;
+ const int threshold = hpd->hpd_storm_threshold;
bool storm = false;
+ if (!threshold)
+ return false;
+
if (!time_in_range(jiffies, start, end)) {
- dev_priv->hotplug.stats[pin].last_jiffies = jiffies;
- dev_priv->hotplug.stats[pin].count = 0;
- DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n",
pin);
- } else if (dev_priv->hotplug.stats[pin].count > threshold &&
- threshold) {
- dev_priv->hotplug.stats[pin].state = HPD_MARK_DISABLED;
+ hpd->stats[pin].last_jiffies = jiffies;
+ hpd->stats[pin].count = 0;
+ }
+
+ if (++hpd->stats[pin].count > threshold) {
+ hpd->stats[pin].state = HPD_MARK_DISABLED;
DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", pin);
storm = true;
} else {
- dev_priv->hotplug.stats[pin].count++;
DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n",
pin,
- dev_priv->hotplug.stats[pin].count);
+ hpd->stats[pin].count);
}
return storm;
--
2.19.1
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[Intel-gfx] [PATCH v3 2/5] drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST
Turns out that if you trigger an HPD storm on a system that has an MST
topology connected to it, you'll end up causing the kernel to eventually
hit a NULL deref:
[ 332.339041] BUG: unable to handle kernel NULL pointer dereference at
00ec
[ 332.340906] PGD 0 P4D 0
[ 332.342750] Oops: [#1] SMP PTI
[ 332.344579] CPU: 2 PID: 25 Comm: kworker/2:0 Kdump: loaded Tainted: G
O 4.18.0-rc3short-hpd-storm+ #2
[ 332.346453] Hardware name: LENOVO 20BWS1KY00/20BWS1KY00, BIOS JBET71WW (1.35
) 09/14/2018
[ 332.348361] Workqueue: events intel_hpd_irq_storm_reenable_work [i915]
[ 332.350301] RIP: 0010:intel_hpd_irq_storm_reenable_work.cold.3+0x2f/0x86
[i915]
[ 332.352213] Code: 00 00 ba e8 00 00 00 48 c7 c6 c0 aa 5f a0 48 c7 c7 d0 73
62 a0 4c 89 c1 4c 89 04 24 e8 7f f5 af e0 4c 8b 04 24 44 89 f8 29 e8 <41> 39 80
ec 00 00 00 0f 85 43 13 fc ff 41 0f b6 86 b8 04 00 00 41
[ 332.354286] RSP: 0018:c9147e48 EFLAGS: 00010006
[ 332.356344] RAX: 0005 RBX: 8802c226c9d4 RCX: 0006
[ 332.358404] RDX: RSI: 0082 RDI: 88032dc95570
[ 332.360466] RBP: 0005 R08: R09: 88031b3dc840
[ 332.362528] R10: R11: 00031a069602 R12: 8802c226ca20
[ 332.364575] R13: 8802c2268000 R14: 880310661000 R15: 000a
[ 332.366615] FS: () GS:88032dc8()
knlGS:
[ 332.368658] CS: 0010 DS: ES: CR0: 80050033
[ 332.370690] CR2: 00ec CR3: 0200a003 CR4: 003606e0
[ 332.372724] DR0: DR1: DR2:
[ 332.374773] DR3: DR6: fffe0ff0 DR7: 0400
[ 332.376798] Call Trace:
[ 332.378809] process_one_work+0x1a1/0x350
[ 332.380806] worker_thread+0x30/0x380
[ 332.382777] ? wq_update_unbound_numa+0x10/0x10
[ 332.384772] kthread+0x112/0x130
[ 332.386740] ? kthread_create_worker_on_cpu+0x70/0x70
[ 332.388706] ret_from_fork+0x35/0x40
[ 332.390651] Modules linked in: i915(O) vfat fat joydev btusb btrtl btbcm
btintel bluetooth ecdh_generic iTCO_wdt wmi_bmof i2c_algo_bit drm_kms_helper
intel_rapl syscopyarea sysfillrect x86_pkg_temp_thermal sysimgblt coretemp
fb_sys_fops crc32_pclmul drm psmouse pcspkr mei_me mei i2c_i801 lpc_ich
mfd_core i2c_core tpm_tis tpm_tis_core thinkpad_acpi wmi tpm rfkill video
crc32c_intel serio_raw ehci_pci xhci_pci ehci_hcd xhci_hcd [last unloaded: i915]
[ 332.394963] CR2: 00ec
This appears to be due to the fact that with an MST topology, not all
intel_connector structs will have ->encoder set. So, fix this by
skipping connectors without encoders in
intel_hpd_irq_storm_reenable_work().
For those wondering, this bug was found on accident while simulating HPD
storms using a Chamelium connected to a ThinkPad T450s (Broadwell).
Changes since v1:
- Check intel_connector->mst_port instead of intel_connector->encoder
Signed-off-by: Lyude Paul
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_hotplug.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
b/drivers/gpu/drm/i915/intel_hotplug.c
index 648a13c6043c..8326900a311e 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -228,7 +228,9 @@ static void intel_hpd_irq_storm_reenable_work(struct
work_struct *work)
drm_for_each_connector_iter(connector, _iter) {
struct intel_connector *intel_connector =
to_intel_connector(connector);
- if (intel_connector->encoder->hpd_pin == pin) {
+ /* Don't check MST ports, they don't have pins */
+ if (!intel_connector->mst_port &&
+ intel_connector->encoder->hpd_pin == pin) {
if (connector->polled !=
intel_connector->polled)
DRM_DEBUG_DRIVER("Reenabling HPD on
connector %s\n",
connector->name);
--
2.19.1
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[Intel-gfx] [PATCH v3 1/5] drm/i915: Fix possible race in intel_dp_add_mst_connector()
This hasn't caused any issues yet that I'm aware of, but as Ville
Syrjälä pointed out - we need to make sure that
intel_connector->mst_port is set before initializing MST connectors,
since in theory we could potentially check intel_connector->mst_port in
i915_hpd_poll_init_work() after registering the connector but before
having written it's value.
Signed-off-by: Lyude Paul
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp_mst.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 8b71d64ebd9d..8cb4093f8bcc 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -441,6 +441,10 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (!intel_connector)
return NULL;
+ intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
+ intel_connector->mst_port = intel_dp;
+ intel_connector->port = port;
+
connector = _connector->base;
ret = drm_connector_init(dev, connector, _dp_mst_connector_funcs,
DRM_MODE_CONNECTOR_DisplayPort);
@@ -451,10 +455,6 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
drm_connector_helper_add(connector,
_dp_mst_connector_helper_funcs);
- intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
- intel_connector->mst_port = intel_dp;
- intel_connector->port = port;
-
for_each_pipe(dev_priv, pipe) {
struct drm_encoder *enc =
_dp->mst_encoders[pipe]->base.base;
--
2.19.1
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[Intel-gfx] [PATCH v3 0/5] drm/i915: HPD IRQ storm detection fixes
This series contains a fix for a problem which is very difficult to reproduce under normal circumstances without specialized testing hardware, along with a fix that seems to be required for some especially rebellious GM45 laptops. Lyude Paul (5): drm/i915: Fix possible race in intel_dp_add_mst_connector() drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST drm/i915: Fix threshold check in intel_hpd_irq_storm_detect() drm/i915: Clarify flow for disabling IRQs on storms drm/i915: Add short HPD IRQ storm detection for non-MST systems drivers/gpu/drm/i915/i915_debugfs.c | 74 ++ drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_irq.c | 7 +++ drivers/gpu/drm/i915/intel_dp_mst.c | 8 +-- drivers/gpu/drm/i915/intel_hotplug.c | 78 +--- 5 files changed, 137 insertions(+), 35 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 5/5] drm/i915: Add short HPD IRQ storm detection for non-MST systems
Unfortunately, it seems that the HPD IRQ storm problem from the early
days of Intel GPUs was never entirely solved, only mostly. Within the
last couple of days, I got a bug report from one of our customers who
had been having issues with their machine suddenly booting up very
slowly after having updated. The amount of time it took to boot went
from around 30 seconds, to over 6 minutes consistently.
After some investigation, I discovered that i915 was reporting massive
amounts of short HPD IRQ spam on this system from the DisplayPort port,
despite there not being anything actually connected. The symptoms would
start with one "long" HPD IRQ being detected at boot:
[1.891398] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0044, dig 0x0044, pins 0x00a0
[1.891436] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long
[1.891472] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN
5 - cnt: 0
[1.891508] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - long
[1.891544] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN
7 - cnt: 0
[1.891592] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long
[1.891628] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port D - long
…
followed by constant short IRQs afterwards:
[1.895091] [drm:intel_encoder_hotplug [i915]] [CONNECTOR:66:DP-1] status
updated from unknown to disconnected
[1.895129] [drm:i915_hotplug_work_func [i915]] Connector DP-3 (pin 7)
received hotplug event.
[1.895165] [drm:intel_dp_detect [i915]] [CONNECTOR:72:DP-3]
[1.895275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.895312] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.895762] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.895799] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.896239] [drm:intel_dp_aux_xfer [i915]] dp_aux_ch timeout status
0x71450085
[1.896293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.896330] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.896781] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
[1.896817] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[1.897275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat
0x0020, dig 0x0020, pins 0x0080
The customer's system in question has a GM45 GPU, which is apparently
well known for hotplugging storms.
So, workaround this impressively broken hardware by changing the default
HPD storm threshold from 5 to 50. Then, make long IRQs count for 10, and
short IRQs count for 1. This makes it so that 5 long IRQs will trigger
an HPD storm, and on systems with short HPD storm detection 50 short
IRQs will trigger an HPD storm. 50 short IRQs amounts to 100ms of
constant pulsing, which seems like a good middleground between being too
sensitive and not being sensitive enough (which would cause visible
stutters in userspace every time a storm occurs).
And just to be extra safe: we don't enable this by default on systems
with MST support. There's too high of a chance of MST support triggering
storm detection, and systems that are new enough to support MST are a
lot less likely to have issues with IRQ storms anyway.
As a note: this patch was tested using a ThinkPad T450s and a Chamelium
to simulate the short IRQ storms.
Changes since v1:
- Don't use two separate thresholds, just make long IRQs count for 10
each and short IRQs count for 1. This simplifies the code a bit
- Ville Syrjälä
Changes since v2:
- Document @long_hpd in intel_hpd_irq_storm_detect, no functional
changes
Signed-off-by: Lyude Paul
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 74
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_irq.c | 7 +++
drivers/gpu/drm/i915/intel_hotplug.c | 49 ++
4 files changed, 114 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a4d9d996fda..b9d6e1be6052 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4658,6 +4658,79 @@ static const struct file_operations
i915_hpd_storm_ctl_fops = {
.write = i915_hpd_storm_ctl_write
};
+static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = m->private;
+
+ seq_printf(m, "Enabled: %s\n",
+ yesno(dev_priv->hotplug.hpd_short_storm_enabled));
+
+ return 0;
+}
+
+static int
+i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, i915_hpd_short_storm_ctl_show,
+
[Intel-gfx] [PATCH v3 4/5] drm/i915: Clarify flow for disabling IRQs on storms
This is rather confusing to look at as-is: dev_priv->display.hpd_irq_setup(dev_priv); in intel_hpd_irq_handler() handles disabling the actual HPD IRQ, while intel_hpd_irq_storm_disable() handles moving the HPD pin state over from MARK_DISABLED to DISABLED along with enabling polling for it. Cc: Ville Syrjälä Signed-off-by: Lyude Paul --- drivers/gpu/drm/i915/intel_hotplug.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index c11d73de16f2..e5e3eeb7e482 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -351,7 +351,7 @@ static void i915_hotplug_work_func(struct work_struct *work) hpd_event_bits = dev_priv->hotplug.event_bits; dev_priv->hotplug.event_bits = 0; - /* Disable hotplug on connectors that hit an irq storm. */ + /* Enable polling for connectors which had HPD IRQ storms */ intel_hpd_irq_storm_disable(dev_priv); spin_unlock_irq(_priv->irq_lock); @@ -458,6 +458,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, } } + /* +* Disable any IRQs that storms were detected on. Polling enablement +* happens later in our hotplug work. +*/ if (storm_detected && dev_priv->display_irqs_enabled) dev_priv->display.hpd_irq_setup(dev_priv); spin_unlock(_priv->irq_lock); -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
== Series Details == Series: drm/i915/icl: Fix power well 2 wrt. DC-off toggling order URL : https://patchwork.freedesktop.org/series/51971/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10715_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10715_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10715_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10715_full: === IGT changes === Warnings igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy: shard-snb: SKIP -> PASS +3 igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10715_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@preempt-contexts-render: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +1 igt@gem_exec_whisper@normal: shard-skl: PASS -> TIMEOUT (fdo#108592) igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#106887, fdo#103665, fdo#106023) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-glk: PASS -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-b-ctm-0-75: shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +6 igt@kms_color@pipe-c-ctm-negative: shard-skl: PASS -> FAIL (fdo#107361) igt@kms_cursor_crc@cursor-64x64-onscreen: shard-glk: PASS -> FAIL (fdo#103232) +1 igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#105454) igt@kms_flip@basic-flip-vs-dpms: shard-kbl: PASS -> DMESG-WARN (fdo#103313, fdo#105345) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@modeset-vs-vblank-race: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc: shard-glk: PASS -> DMESG-FAIL (fdo#106538) igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@kms_vblank@pipe-a-wait-idle-hang: shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133) Possible fixes igt@kms_cursor_crc@cursor-128x128-suspend: shard-skl: INCOMPLETE (fdo#104108) -> PASS igt@kms_cursor_crc@cursor-256x256-sliding: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x85-random: shard-apl: FAIL (fdo#103232) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-glk: FAIL (fdo#103166) -> PASS igt@pm_rpm@legacy-planes-dpms: shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959 fdo#106023
Re: [Intel-gfx] [PATCH 3/4] drm/i915/icl: Only grab TC ports when using it
On Sat, 2018-11-03 at 01:06 +0200, Imre Deak wrote:
> On Fri, Nov 02, 2018 at 01:39:23PM -0700, José Roberto de Souza
> wrote:
> > When suspending or unloading the driver, it needs to release the
> > TC ports so HW can change it state without wait for driver
> > handshake.
> > Spec also state that if the port is not used by driver it should
> > release TC access, so here only grabbing control of the TC ports
> > and
> > marking as unsafe when aux power is needed as have aux power well
> > is
> > a requirement to have DDI enabled in TC ports, the pre_pll_enable
> > and
> > post_pll_disable hooks takes care of getting and releasing it.
> >
> > BSpec: 21750
> >
> > Cc: Imre Deak
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
>
> Agreed that we should force a manual disconnect before entering
> low-power states and driver unloading, but I don't think this should
> be
> done from the power well code. We could perform multiple AUX
> transfers
> after a connect event around each of which we would enable/disable
> the
> AUX power well. We would then likely continue doing a modeset. During
> this whole sequence I don't think we should do forced
> connects/disconnects due to the AUX power well getting
> enabled/disabled.
>
> I think normally we should change the connection status (that is the
> safe/unsafe mode you're setting here) in response to HPD events, also
> considering that we may have to delay changing the state as discussed
> earlier with Ville (due to an ongoing AUX transfer or active mode in
> the
What do you think about use power_well->count to delay when type-
c/legacy is disconnected?
Then when the last reference is taken
icl_tc_phy_aux_power_well_disable() check if the TC live status is
disconnected and mark as unsafe.
> opposite TypeC mode). Then only during system/runtime suspend and
> unload
> should we do a forced disconnect, which would be safe since at those
> points we don't have any pending AUX transfers or active outputs.
>
> --Imre
>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 28 -
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 55
> > -
> > 2 files changed, 54 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 52a54ef746af..d978127e7208 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -5013,16 +5013,6 @@ static bool icl_tc_phy_connect(struct
> > drm_i915_private *dev_priv,
> > return false;
> > }
> >
> > - /*
> > -* This function may be called many times in a row without an
> > HPD event
> > -* in between, so try to avoid the write when we can.
> > -*/
> > - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> > - if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
> > - val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> > - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> > - }
> > -
> > /*
> > * Now we have to re-check the live state, in case the port
> > recently
> > * became disconnected. Not necessary for legacy mode.
> > @@ -5044,24 +5034,6 @@ static bool icl_tc_phy_connect(struct
> > drm_i915_private *dev_priv,
> > static void icl_tc_phy_disconnect(struct drm_i915_private
> > *dev_priv,
> > struct intel_digital_port *dig_port)
> > {
> > - enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port-
> > >base.port);
> > -
> > - if (dig_port->tc_type == TC_PORT_UNKNOWN)
> > - return;
> > -
> > - /*
> > -* TBT disconnection flow is read the live status, what was
> > done in
> > -* caller.
> > -*/
> > - if (dig_port->tc_type == TC_PORT_TYPEC ||
> > - dig_port->tc_type == TC_PORT_LEGACY) {
> > - u32 val;
> > -
> > - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> > - val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> > - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> > - }
> > -
> > dig_port->tc_type = TC_PORT_UNKNOWN;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 6c453366cd24..dab5f90646c4 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -465,6 +465,48 @@ icl_combo_phy_aux_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > hsw_wait_for_power_well_disable(dev_priv, power_well);
> > }
> >
> > +static void icl_tc_grab_control(struct drm_i915_private *dev_priv,
> > + enum aux_ch aux_ch, bool grab)
> > +{
> > + struct drm_device *dev = _priv->drm;
> > + struct drm_connector_list_iter conn_iter;
> > + struct drm_connector *connector;
> > +
> > + drm_connector_list_iter_begin(dev, _iter);
> > + drm_for_each_connector_iter(connector, _iter) {
> > + struct intel_connector *intel_connector;
> > + struct intel_encoder *intel_encoder;
> > +
Re: [Intel-gfx] [PATCH 3/4] drm/i915/icl: Only grab TC ports when using it
On Fri, Nov 02, 2018 at 01:39:23PM -0700, José Roberto de Souza wrote:
> When suspending or unloading the driver, it needs to release the
> TC ports so HW can change it state without wait for driver handshake.
> Spec also state that if the port is not used by driver it should
> release TC access, so here only grabbing control of the TC ports and
> marking as unsafe when aux power is needed as have aux power well is
> a requirement to have DDI enabled in TC ports, the pre_pll_enable and
> post_pll_disable hooks takes care of getting and releasing it.
>
> BSpec: 21750
>
> Cc: Imre Deak
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
Agreed that we should force a manual disconnect before entering
low-power states and driver unloading, but I don't think this should be
done from the power well code. We could perform multiple AUX transfers
after a connect event around each of which we would enable/disable the
AUX power well. We would then likely continue doing a modeset. During
this whole sequence I don't think we should do forced
connects/disconnects due to the AUX power well getting enabled/disabled.
I think normally we should change the connection status (that is the
safe/unsafe mode you're setting here) in response to HPD events, also
considering that we may have to delay changing the state as discussed
earlier with Ville (due to an ongoing AUX transfer or active mode in the
opposite TypeC mode). Then only during system/runtime suspend and unload
should we do a forced disconnect, which would be safe since at those
points we don't have any pending AUX transfers or active outputs.
--Imre
> ---
> drivers/gpu/drm/i915/intel_dp.c | 28 -
> drivers/gpu/drm/i915/intel_runtime_pm.c | 55 -
> 2 files changed, 54 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 52a54ef746af..d978127e7208 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5013,16 +5013,6 @@ static bool icl_tc_phy_connect(struct drm_i915_private
> *dev_priv,
> return false;
> }
>
> - /*
> - * This function may be called many times in a row without an HPD event
> - * in between, so try to avoid the write when we can.
> - */
> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> - if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
> - val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> - }
> -
> /*
>* Now we have to re-check the live state, in case the port recently
>* became disconnected. Not necessary for legacy mode.
> @@ -5044,24 +5034,6 @@ static bool icl_tc_phy_connect(struct drm_i915_private
> *dev_priv,
> static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
> struct intel_digital_port *dig_port)
> {
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> -
> - if (dig_port->tc_type == TC_PORT_UNKNOWN)
> - return;
> -
> - /*
> - * TBT disconnection flow is read the live status, what was done in
> - * caller.
> - */
> - if (dig_port->tc_type == TC_PORT_TYPEC ||
> - dig_port->tc_type == TC_PORT_LEGACY) {
> - u32 val;
> -
> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> - val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> - }
> -
> dig_port->tc_type = TC_PORT_UNKNOWN;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6c453366cd24..dab5f90646c4 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -465,6 +465,48 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> +static void icl_tc_grab_control(struct drm_i915_private *dev_priv,
> + enum aux_ch aux_ch, bool grab)
> +{
> + struct drm_device *dev = _priv->drm;
> + struct drm_connector_list_iter conn_iter;
> + struct drm_connector *connector;
> +
> + drm_connector_list_iter_begin(dev, _iter);
> + drm_for_each_connector_iter(connector, _iter) {
> + struct intel_connector *intel_connector;
> + struct intel_encoder *intel_encoder;
> + struct intel_digital_port *dig_port;
> + enum tc_port tc_port;
> +
> + intel_connector = to_intel_connector(connector);
> + if (!intel_connector->encoder)
> + continue;
> + intel_encoder = intel_connector->encoder;
> + dig_port = enc_to_dig_port(_encoder->base);
> +
> + if (!dig_port || dig_port->aux_ch != aux_ch)
> + continue;
> +
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Fix combo PHY HW context loss
== Series Details == Series: drm/i915/icl: Fix combo PHY HW context loss URL : https://patchwork.freedesktop.org/series/51970/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10714_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10714_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10714_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10714_full: === IGT changes === Warnings igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy: shard-snb: SKIP -> PASS +3 igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP igt@pm_rpm@universal-planes: shard-skl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10714_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-apl: PASS -> INCOMPLETE (fdo#106886, fdo#103927) igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665, fdo#106887) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-glk: PASS -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_chv_cursor_fail@pipe-b-128x128-bottom-edge: shard-skl: PASS -> FAIL (fdo#104671) igt@kms_color@pipe-b-ctm-negative: shard-skl: PASS -> FAIL (fdo#107361) igt@kms_cursor_crc@cursor-128x42-offscreen: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-64x64-onscreen: shard-glk: PASS -> FAIL (fdo#103232) +1 igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#105454, fdo#106509) igt@kms_cursor_legacy@pipe-b-torture-move: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_draw_crc@draw-method-xrgb-mmap-wc-ytiled: shard-skl: NOTRUN -> FAIL (fdo#103184) igt@kms_flip@flip-vs-dpms-interruptible: shard-kbl: PASS -> DMESG-WARN (fdo#103313, fdo#105345) igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt: shard-skl: NOTRUN -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-skl: NOTRUN -> FAIL (fdo#105682) +1 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: shard-skl: PASS -> FAIL (fdo#107362, fdo#103191) igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +1 igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_vblank@pipe-b-ts-continuation-suspend: shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108) +1 Possible fixes igt@kms_cursor_crc@cursor-128x42-random: shard-skl: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x256-sliding: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@pm_rpm@legacy-planes-dpms: shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105682
Re: [Intel-gfx] [PATCH 3/5] drm/i915: merge gen checks to use range
On Fri, Nov 02, 2018 at 03:28:00PM -0700, Lucas De Marchi wrote:
> On Fri, Nov 02, 2018 at 03:12:18PM -0700, Rodrigo Vivi wrote:
> > On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote:
> > > On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> > > > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote:
> > > > > On Thu, Nov 01, 2018 at 11:31:25AM +, Tvrtko Ursulin wrote:
> > > > > >
> > > > > > On 01/11/2018 08:35, Lucas De Marchi wrote:
> > > > > > > Instead of using several IS_GEN(), it's possible to pass the
> > > > > > > range as argument. By code inspection these were the ranges deemed
> > > > > > > necessary for spatch:
> > > > > > >
> > > > > > > @@
> > > > > > > expression e;
> > > > > > > @@
> > > > > > > (
> > > > > > > - IS_GEN(e, 3) || IS_GEN(e, 4)
> > > > > > > + IS_GEN(e, 3, 4)
> > > > > > > |
> > > > > > > - IS_GEN(e, 5) || IS_GEN(e, 6)
> > > > > > > + IS_GEN(e, 5, 6)
> > > > > > > |
> > > > > > > - IS_GEN(e, 6) || IS_GEN(e, 7)
> > > > > > > + IS_GEN(e, 6, 7)
> > > > > > > |
> > > > > > > - IS_GEN(e, 7) || IS_GEN(e, 8)
> > > > > > > + IS_GEN(e, 7, 8)
> > > > > > > |
> > > > > > > - IS_GEN(e, 8) || IS_GEN(e, 9)
> > > > > > > + IS_GEN(e, 8, 9)
> > > > > > > |
> > > > > > > - IS_GEN(e, 10) || IS_GEN(e, 9)
> > > > > > > + IS_GEN(e, 9, 10)
> > > > > > > |
> > > > > > > - IS_GEN(e, 9) || IS_GEN(e, 10)
> > > > > > > + IS_GEN(e, 9, 10)
> > > > > > > )
> > > > > > >
> > > > > > > Signed-off-by: Lucas De Marchi
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/i915_debugfs.c| 6 +++---
> > > > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/i915_perf.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/intel_crt.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++--
> > > > > > > drivers/gpu/drm/i915/intel_uncore.c| 6 +++---
> > > > > > > 10 files changed, 15 insertions(+), 15 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > > index 28d95f9d0b0e..f2fbc016bd7f 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct
> > > > > > > seq_file *m, void *data)
> > > > > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> > > > > > >
> > > > > > > swizzle_string(dev_priv->mm.bit_6_swizzle_y));
> > > > > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
> > > > > > > + if (IS_GEN(dev_priv, 3, 4)) {
> > > > > >
> > > > > > I can see value in it but think it would read better with
> > > > > > IS_GEN_RANGE.
> > > > >
> > > > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an
> > > > > then
> > > > > bring the patches that make sense here. There was a recent patch from
> > > > > Rodrigo
> > > > > doing that. I'll include it in next version.
> > > >
> > > > I liked the double args idea but after reading I believe
> > > > it gets clear IS_GEN_RANGE.
> > > >
> > > > >
> > > > > >
> > > > > > Are there any cases of or-ed IS_GEN checks with something
> > > > > > sandwiched in
> > > > > > between then, which the above spatch would miss?
> > > > >
> > > > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" --
> > > > > drivers/gpu/drm/i915/``
> > > > > I didn't find any. The only thing I found was a missed case for gen3
> > > > > || gen2
> > > > > that was not covered by the spatch.
> > > > >
> > > > > >
> > > > > > How many non-consecutive IS_GEN gen checks are there? To give us
> > > > > > some ideas
> > > > > > if the usual pattern is range, or perhaps checks against a list of
> > > > > > gens also
> > > > > > exists? (Gut feeling says no.)
> > > > >
> > > > > only cases of <=, <, >=, >.
> > > >
> > > > For these cases on patches 4 and 5::
> > > >
> > > > What about converting all < n to <= n-1 and all > n to >= n + 1
> > > > get FORVER back and introduce IS_GEN_UNTIL ?
> > > >
> > > > IS_GEN_UNTIL(dev_priv, e)
> > > > IS_GEN_RANGE(dev_priv, s, FOREVER)
> > > >
> > > > so we can also kill INTEL_GEN.
> > > >
> > > > Another different idea on top of that.
> > > >
> > > > What about removing all "IS_"?
> > > >
> > > > so end result could be something like that:
> > > >
> > > > INTEL_GEN(dev_priv, n)
> > > > DISPLAY_GEN(dev_priv, n)
> > > > INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> > > > DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> > > > INTEL_GEN_UNTIL(dev_priv, e)
> > > > DISPLAY_GEN_UNTIL(dev_priv, e)
> > > >
> > > > (maybe s/INTEL/GT)
> > >
> > > I like it.
Re: [Intel-gfx] [PATCH 0/2] drm/i915/icl: Fix suspend/resume for TypeC HDMI
On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote: > This patch adds missing programming for static/fixed/legacy TypeC > HDMI > outputs. The lack of this resulted in blank screen when booting > without > an HDMI display being connected, or after system suspend/resume, > since > in these cases BIOS doesn't do the programming either. This case is working now. Tested-by: José Roberto de Souza > > Cc: Vandita Kulkarni > Cc: Paulo Zanoni > Cc: Maarten Lankhorst > Cc: Manasi Navare > > Imre Deak (2): > drm/i915/icl: Configure MG PHY gating for HDMI ports too > drm/i915/icl: Configure MG DP mode for HDMI ports too > > drivers/gpu/drm/i915/intel_ddi.c | 138 > ++- > drivers/gpu/drm/i915/intel_dp.c | 132 --- > -- > drivers/gpu/drm/i915/intel_drv.h | 3 - > 3 files changed, 137 insertions(+), 136 deletions(-) > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/lease: debug output for lease creation (rev2)
== Series Details == Series: series starting with [1/3] drm/lease: debug output for lease creation (rev2) URL : https://patchwork.freedesktop.org/series/51944/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC drivers/gpu/drm/drm_lease.o drivers/gpu/drm/drm_lease.c: In function ‘fill_object_idr’: drivers/gpu/drm/drm_lease.c:426:28: warning: passing argument 2 of ‘validate_lease’ makes integer from pointer without a cast [-Wint-conversion] ret = validate_lease(dev, lessor_priv, object_count, objects, ^~~ drivers/gpu/drm/drm_lease.c:355:12: note: expected ‘int’ but argument is of type ‘struct drm_file *’ static int validate_lease(struct drm_device *dev, ^~ drivers/gpu/drm/drm_lease.c:426:41: warning: passing argument 3 of ‘validate_lease’ makes pointer from integer without a cast [-Wint-conversion] ret = validate_lease(dev, lessor_priv, object_count, objects, ^~~~ drivers/gpu/drm/drm_lease.c:355:12: note: expected ‘struct drm_mode_object **’ but argument is of type ‘int’ static int validate_lease(struct drm_device *dev, ^~ drivers/gpu/drm/drm_lease.c:426:8: error: too many arguments to function ‘validate_lease’ ret = validate_lease(dev, lessor_priv, object_count, objects, ^~ drivers/gpu/drm/drm_lease.c:355:12: note: declared here static int validate_lease(struct drm_device *dev, ^~ scripts/Makefile.build:305: recipe for target 'drivers/gpu/drm/drm_lease.o' failed make[3]: *** [drivers/gpu/drm/drm_lease.o] Error 1 scripts/Makefile.build:546: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:546: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1052: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for DSC enabling remaining patches respin
== Series Details == Series: DSC enabling remaining patches respin URL : https://patchwork.freedesktop.org/series/51986/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5082 -> Patchwork_10718 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10718 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10718, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51986/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10718: === IGT changes === Possible regressions igt@debugfs_test@read_all_entries: fi-skl-iommu: PASS -> INCOMPLETE +1 fi-ivb-3770:PASS -> INCOMPLETE +1 fi-cfl-s3: PASS -> INCOMPLETE +1 fi-icl-u: PASS -> INCOMPLETE fi-skl-6700hq: PASS -> INCOMPLETE +1 fi-skl-6770hq: PASS -> INCOMPLETE +1 fi-skl-6260u: PASS -> INCOMPLETE +1 fi-snb-2600:PASS -> INCOMPLETE +1 fi-skl-6600u: PASS -> INCOMPLETE igt@drv_module_reload@basic-reload: fi-cnl-u: PASS -> INCOMPLETE +1 fi-kbl-x1275: PASS -> INCOMPLETE +1 fi-kbl-r: PASS -> INCOMPLETE +1 fi-cfl-8700k: PASS -> INCOMPLETE +1 fi-icl-u2: PASS -> INCOMPLETE fi-ivb-3520m: PASS -> INCOMPLETE +1 fi-hsw-4770:PASS -> INCOMPLETE +1 fi-bsw-n3050: PASS -> INCOMPLETE +1 fi-bsw-kefka: PASS -> INCOMPLETE +1 fi-kbl-7567u: PASS -> INCOMPLETE +1 fi-whl-u: PASS -> INCOMPLETE +1 fi-skl-6700k2: PASS -> INCOMPLETE +1 Warnings igt@debugfs_test@read_all_entries: fi-icl-u2: DMESG-WARN (fdo#108070) -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10718 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-glk-dsi: PASS -> INCOMPLETE (fdo#103359, k.org#198133) +1 fi-bxt-j4205: PASS -> INCOMPLETE (fdo#103927) +1 fi-elk-e7500: PASS -> INCOMPLETE (fdo#103989) +1 fi-skl-gvtdvm: PASS -> INCOMPLETE (fdo#105600) +1 igt@drv_module_reload@basic-reload: fi-skl-guc: PASS -> INCOMPLETE (fdo#106693) +1 fi-bdw-gvtdvm: PASS -> INCOMPLETE (fdo#105600) +1 fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) +1 fi-cfl-guc: PASS -> INCOMPLETE (fdo#106693) +1 fi-kbl-guc: PASS -> INCOMPLETE (fdo#106693) +1 fi-byt-clapper: PASS -> INCOMPLETE (fdo#102657) +1 fi-byt-j1900: PASS -> INCOMPLETE (fdo#102657) +1 fi-apl-guc: PASS -> INCOMPLETE (fdo#103927, fdo#106693) +1 fi-skl-6600u: PASS -> INCOMPLETE (fdo#104108) fi-kbl-7560u: PASS -> INCOMPLETE (fdo#103665) +1 igt@gem_ctx_switch@basic-default: fi-icl-u: PASS -> INCOMPLETE (fdo#108535, fdo#108315) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#106612) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cfl-8109u: INCOMPLETE (fdo#108126, fdo#106070) -> PASS fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612 fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070 fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 fdo#108535 https://bugs.freedesktop.org/show_bug.cgi?id=108535 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (50 -> 45) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
Re: [Intel-gfx] [PATCH 3/5] drm/i915: merge gen checks to use range
On Fri, Nov 02, 2018 at 03:12:18PM -0700, Rodrigo Vivi wrote:
> On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote:
> > On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> > > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote:
> > > > On Thu, Nov 01, 2018 at 11:31:25AM +, Tvrtko Ursulin wrote:
> > > > >
> > > > > On 01/11/2018 08:35, Lucas De Marchi wrote:
> > > > > > Instead of using several IS_GEN(), it's possible to pass the
> > > > > > range as argument. By code inspection these were the ranges deemed
> > > > > > necessary for spatch:
> > > > > >
> > > > > > @@
> > > > > > expression e;
> > > > > > @@
> > > > > > (
> > > > > > - IS_GEN(e, 3) || IS_GEN(e, 4)
> > > > > > + IS_GEN(e, 3, 4)
> > > > > > |
> > > > > > - IS_GEN(e, 5) || IS_GEN(e, 6)
> > > > > > + IS_GEN(e, 5, 6)
> > > > > > |
> > > > > > - IS_GEN(e, 6) || IS_GEN(e, 7)
> > > > > > + IS_GEN(e, 6, 7)
> > > > > > |
> > > > > > - IS_GEN(e, 7) || IS_GEN(e, 8)
> > > > > > + IS_GEN(e, 7, 8)
> > > > > > |
> > > > > > - IS_GEN(e, 8) || IS_GEN(e, 9)
> > > > > > + IS_GEN(e, 8, 9)
> > > > > > |
> > > > > > - IS_GEN(e, 10) || IS_GEN(e, 9)
> > > > > > + IS_GEN(e, 9, 10)
> > > > > > |
> > > > > > - IS_GEN(e, 9) || IS_GEN(e, 10)
> > > > > > + IS_GEN(e, 9, 10)
> > > > > > )
> > > > > >
> > > > > > Signed-off-by: Lucas De Marchi
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_debugfs.c| 6 +++---
> > > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> > > > > > drivers/gpu/drm/i915/i915_perf.c | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_crt.c | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++--
> > > > > > drivers/gpu/drm/i915/intel_uncore.c| 6 +++---
> > > > > > 10 files changed, 15 insertions(+), 15 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > index 28d95f9d0b0e..f2fbc016bd7f 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file
> > > > > > *m, void *data)
> > > > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> > > > > >swizzle_string(dev_priv->mm.bit_6_swizzle_y));
> > > > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
> > > > > > + if (IS_GEN(dev_priv, 3, 4)) {
> > > > >
> > > > > I can see value in it but think it would read better with
> > > > > IS_GEN_RANGE.
> > > >
> > > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then
> > > > bring the patches that make sense here. There was a recent patch from
> > > > Rodrigo
> > > > doing that. I'll include it in next version.
> > >
> > > I liked the double args idea but after reading I believe
> > > it gets clear IS_GEN_RANGE.
> > >
> > > >
> > > > >
> > > > > Are there any cases of or-ed IS_GEN checks with something sandwiched
> > > > > in
> > > > > between then, which the above spatch would miss?
> > > >
> > > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" --
> > > > drivers/gpu/drm/i915/``
> > > > I didn't find any. The only thing I found was a missed case for gen3 ||
> > > > gen2
> > > > that was not covered by the spatch.
> > > >
> > > > >
> > > > > How many non-consecutive IS_GEN gen checks are there? To give us some
> > > > > ideas
> > > > > if the usual pattern is range, or perhaps checks against a list of
> > > > > gens also
> > > > > exists? (Gut feeling says no.)
> > > >
> > > > only cases of <=, <, >=, >.
> > >
> > > For these cases on patches 4 and 5::
> > >
> > > What about converting all < n to <= n-1 and all > n to >= n + 1
> > > get FORVER back and introduce IS_GEN_UNTIL ?
> > >
> > > IS_GEN_UNTIL(dev_priv, e)
> > > IS_GEN_RANGE(dev_priv, s, FOREVER)
> > >
> > > so we can also kill INTEL_GEN.
> > >
> > > Another different idea on top of that.
> > >
> > > What about removing all "IS_"?
> > >
> > > so end result could be something like that:
> > >
> > > INTEL_GEN(dev_priv, n)
> > > DISPLAY_GEN(dev_priv, n)
> > > INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> > > DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> > > INTEL_GEN_UNTIL(dev_priv, e)
> > > DISPLAY_GEN_UNTIL(dev_priv, e)
> > >
> > > (maybe s/INTEL/GT)
> >
> > I like it. I'm just not sure about UNTIL, because I will always have doubts
> > if
> > it's inclusive or not. But I guess we have the same today with RANGE and we
> > just get used to it. By making all of them inclusive, it will be easier.
> >
> > Anyway, my preference is:
> >
> > GT_GEN(dev_priv, n)
> > GT_GEN_RANGE(dev_priv, s, e)
> > and e
Re: [Intel-gfx] [PATCH 3/5] drm/i915: merge gen checks to use range
On Fri, Nov 02, 2018 at 12:47:28PM -0700, Lucas De Marchi wrote:
> On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> > On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote:
> > > On Thu, Nov 01, 2018 at 11:31:25AM +, Tvrtko Ursulin wrote:
> > > >
> > > > On 01/11/2018 08:35, Lucas De Marchi wrote:
> > > > > Instead of using several IS_GEN(), it's possible to pass the
> > > > > range as argument. By code inspection these were the ranges deemed
> > > > > necessary for spatch:
> > > > >
> > > > > @@
> > > > > expression e;
> > > > > @@
> > > > > (
> > > > > - IS_GEN(e, 3) || IS_GEN(e, 4)
> > > > > + IS_GEN(e, 3, 4)
> > > > > |
> > > > > - IS_GEN(e, 5) || IS_GEN(e, 6)
> > > > > + IS_GEN(e, 5, 6)
> > > > > |
> > > > > - IS_GEN(e, 6) || IS_GEN(e, 7)
> > > > > + IS_GEN(e, 6, 7)
> > > > > |
> > > > > - IS_GEN(e, 7) || IS_GEN(e, 8)
> > > > > + IS_GEN(e, 7, 8)
> > > > > |
> > > > > - IS_GEN(e, 8) || IS_GEN(e, 9)
> > > > > + IS_GEN(e, 8, 9)
> > > > > |
> > > > > - IS_GEN(e, 10) || IS_GEN(e, 9)
> > > > > + IS_GEN(e, 9, 10)
> > > > > |
> > > > > - IS_GEN(e, 9) || IS_GEN(e, 10)
> > > > > + IS_GEN(e, 9, 10)
> > > > > )
> > > > >
> > > > > Signed-off-by: Lucas De Marchi
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_debugfs.c| 6 +++---
> > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> > > > > drivers/gpu/drm/i915/i915_perf.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_crt.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++--
> > > > > drivers/gpu/drm/i915/intel_uncore.c| 6 +++---
> > > > > 10 files changed, 15 insertions(+), 15 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > index 28d95f9d0b0e..f2fbc016bd7f 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file
> > > > > *m, void *data)
> > > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> > > > > swizzle_string(dev_priv->mm.bit_6_swizzle_y));
> > > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
> > > > > + if (IS_GEN(dev_priv, 3, 4)) {
> > > >
> > > > I can see value in it but think it would read better with IS_GEN_RANGE.
> > >
> > > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then
> > > bring the patches that make sense here. There was a recent patch from
> > > Rodrigo
> > > doing that. I'll include it in next version.
> >
> > I liked the double args idea but after reading I believe
> > it gets clear IS_GEN_RANGE.
> >
> > >
> > > >
> > > > Are there any cases of or-ed IS_GEN checks with something sandwiched in
> > > > between then, which the above spatch would miss?
> > >
> > > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" --
> > > drivers/gpu/drm/i915/``
> > > I didn't find any. The only thing I found was a missed case for gen3 ||
> > > gen2
> > > that was not covered by the spatch.
> > >
> > > >
> > > > How many non-consecutive IS_GEN gen checks are there? To give us some
> > > > ideas
> > > > if the usual pattern is range, or perhaps checks against a list of gens
> > > > also
> > > > exists? (Gut feeling says no.)
> > >
> > > only cases of <=, <, >=, >.
> >
> > For these cases on patches 4 and 5::
> >
> > What about converting all < n to <= n-1 and all > n to >= n + 1
> > get FORVER back and introduce IS_GEN_UNTIL ?
> >
> > IS_GEN_UNTIL(dev_priv, e)
> > IS_GEN_RANGE(dev_priv, s, FOREVER)
> >
> > so we can also kill INTEL_GEN.
> >
> > Another different idea on top of that.
> >
> > What about removing all "IS_"?
> >
> > so end result could be something like that:
> >
> > INTEL_GEN(dev_priv, n)
> > DISPLAY_GEN(dev_priv, n)
> > INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> > DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> > INTEL_GEN_UNTIL(dev_priv, e)
> > DISPLAY_GEN_UNTIL(dev_priv, e)
> >
> > (maybe s/INTEL/GT)
>
> I like it. I'm just not sure about UNTIL, because I will always have doubts if
> it's inclusive or not. But I guess we have the same today with RANGE and we
> just get used to it. By making all of them inclusive, it will be easier.
>
> Anyway, my preference is:
>
> GT_GEN(dev_priv, n)
> GT_GEN_RANGE(dev_priv, s, e)
> and e can be GEN_FOREVER, aka -1. The macro has enough knowledge to work
> out
one niptik
I prefer FOREVER alone than GEN_FOREVER because macro already has "GEN"
> the mask, e.g. s == 10, e == FOREVER => mask == ~(BIT(s) | (BIT(s) - 1))
>
> And the DISPLAY_GEN* counterparts.
>
> IMO there's no need to have _UNTIL because it can
Re: [Intel-gfx] [PATCH 2/5] drm/i915/cnl+: Move the combo PHY init/uninit code to a new file
On Fri, Nov 02, 2018 at 11:06:43PM +0200, Souza, Jose wrote:
> On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> > Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code
> > in a
> > separate file.
> >
> > No functional change.
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Paulo Zanoni
> > Cc: Ville Syrjälä
> > Cc: José Roberto de Souza
> > Cc: Rodrigo Vivi
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 6 ++
> > drivers/gpu/drm/i915/intel_combo_phy.c | 159
> >
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 127 ++--
> > -
> > 4 files changed, 174 insertions(+), 119 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/intel_combo_phy.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile
> > index 28c7d7884e88..1e7e9513bb10 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -113,6 +113,7 @@ i915-y += intel_audio.o \
> > intel_bios.o \
> > intel_cdclk.o \
> > intel_color.o \
> > + intel_combo_phy.o \
> > intel_connector.o \
> > intel_display.o \
> > intel_dpio_phy.o \
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 6157f8128cc5..62882e1ddbee 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3571,6 +3571,12 @@ void vlv_phy_pre_encoder_enable(struct
> > intel_encoder *encoder,
> > void vlv_phy_reset_lanes(struct intel_encoder *encoder,
> > const struct intel_crtc_state
> > *old_crtc_state);
> >
> > +/* intel_combo_phy.c */
> > +void icl_combo_phys_init(struct drm_i915_private *dev_priv);
> > +void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> > +void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
> > +void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> > +
> > int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> > int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> > u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> > b/drivers/gpu/drm/i915/intel_combo_phy.c
> > new file mode 100644
> > index ..13184ae5a217
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> > @@ -0,0 +1,159 @@
> > +/*
> > + * Copyright © 2018 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> > OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#include "intel_drv.h"
> > +
> > +enum {
> > + PROCMON_0_85V_DOT_0,
> > + PROCMON_0_95V_DOT_0,
> > + PROCMON_0_95V_DOT_1,
> > + PROCMON_1_05V_DOT_0,
> > + PROCMON_1_05V_DOT_1,
> > +};
> > +
> > +static const struct cnl_procmon {
> > + u32 dw1, dw9, dw10;
> > +} cnl_procmon_values[] = {
> > + [PROCMON_0_85V_DOT_0] =
> > + { .dw1 = 0x, .dw9 = 0x62AB67BB, .dw10 =
> > 0x51914F96, },
> > + [PROCMON_0_95V_DOT_0] =
> > + { .dw1 = 0x, .dw9 = 0x86E172C7, .dw10 =
> > 0x77CA5EAB, },
> > + [PROCMON_0_95V_DOT_1] =
> > + { .dw1 = 0x, .dw9 = 0x93F87FE1, .dw10 =
> > 0x8AE871C5, },
> > + [PROCMON_1_05V_DOT_0] =
> > + { .dw1 = 0x, .dw9 = 0x98FA82DD, .dw10 =
> > 0x89E46DC1, },
> > + [PROCMON_1_05V_DOT_1] =
> > + { .dw1 = 0x0044, .dw9 = 0x9A00AB25, .dw10 =
> > 0x8AE38FF1, },
> > +};
> > +
> > +/*
> > + * CNL has just one set of registers, while ICL has two sets: one
> > for port A and
> > + * the other for port B. The CNL registers are equivalent to the ICL
> > port A
> > + * registers, that's why we call the ICL macros even though the
> > function has CNL
> > + * on its
Re: [Intel-gfx] [PATCH 1/5] drm/i915/icl: Fix combo PHY uninit
On Fri, Nov 02, 2018 at 10:57:19PM +0200, Souza, Jose wrote: > On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote: > > BSpec says to clear the comp init HW flag too during combo PHY > > uninit, > > so do that. The lack of this could badly interact with the PHY reinit > > after a DC6/9 transition at least, where (after a follow-up patch > > fixing > > the init code) we'd skip the initialization incorrectly due to this > > flag > > being set. > > > > BSpec: 21257 > > Cc: Paulo Zanoni > > Cc: Ville Syrjälä > > Cc: José Roberto de Souza > > Cc: Rodrigo Vivi > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > > b/drivers/gpu/drm/i915/intel_runtime_pm.c > > index 6c453366cd24..a7eea8423580 100644 > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -3668,6 +3668,10 @@ void icl_display_core_uninit(struct > > drm_i915_private *dev_priv) > > val = I915_READ(ICL_PHY_MISC(port)); > > val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > > I915_WRITE(ICL_PHY_MISC(port), val); > > + > > + val = I915_READ(ICL_PORT_COMP_DW0(port)); > > + val &= ~COMP_INIT; > > + I915_WRITE(ICL_PORT_COMP_DW0(port), val); > > As DDIA PHY is the master maybe would be more safe clear it by last? AFAIK that only means that the slave copies some calibration data from the master during initialization and the spec doesn't require any order here either. Perhaps it would still be better to keep the reverse order in any case, but that should be a separate change as we already disabled them in this order so far. > > Other than that: > Reviewed-by: José Roberto de Souza > > > > } > > } > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915/cnl+: Verify combo PHY HW state during PHY uninit
On Fri, Nov 02, 2018 at 11:25:58PM +0200, Souza, Jose wrote:
> On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> > Verify on CNL, ICL that the combo PHY HW state stayed intact after
> > PHY
> > initialization.
> >
> > Cc: Paulo Zanoni
> > Cc: Ville Syrjälä
> > Cc: José Roberto de Souza
> > Cc: Rodrigo Vivi
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_combo_phy.c | 103
> > -
> > 1 file changed, 101 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> > b/drivers/gpu/drm/i915/intel_combo_phy.c
> > index 13184ae5a217..1522e2a25390 100644
> > --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> > @@ -52,8 +52,8 @@ static const struct cnl_procmon {
> > * registers, that's why we call the ICL macros even though the
> > function has CNL
> > * on its name.
> > */
> > -static void cnl_set_procmon_ref_values(struct drm_i915_private
> > *dev_priv,
> > - enum port port)
> > +static const struct cnl_procmon *
> > +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> > port port)
> > {
> > const struct cnl_procmon *procmon;
> > u32 val;
> > @@ -80,6 +80,17 @@ static void cnl_set_procmon_ref_values(struct
> > drm_i915_private *dev_priv,
> > break;
> > }
> >
> > + return procmon;
> > +}
> > +
> > +static void cnl_set_procmon_ref_values(struct drm_i915_private
> > *dev_priv,
> > + enum port port)
> > +{
> > + const struct cnl_procmon *procmon;
> > + u32 val;
> > +
> > + procmon = cnl_get_procmon_ref_values(dev_priv, port);
> > +
> > val = I915_READ(ICL_PORT_COMP_DW1(port));
> > val &= ~((0xff << 16) | 0xff);
> > val |= procmon->dw1;
> > @@ -89,6 +100,63 @@ static void cnl_set_procmon_ref_values(struct
> > drm_i915_private *dev_priv,
> > I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> > }
> >
> > +static bool check_phy_reg(struct drm_i915_private *dev_priv,
> > + enum port port, i915_reg_t reg, u32 mask,
> > + u32 expected_val)
> > +{
> > + u32 val = I915_READ(reg);
> > +
> > + if ((val & mask) != expected_val) {
> > + DRM_DEBUG_DRIVER("Port-%c combo PHY reg %08x state
> > mismatch: "
> > +"current %08x mask %08x expected
> > %08x\n",
> > +port_name(port),
> > +reg.reg, val, mask, expected_val);
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static bool cnl_verify_procmon_ref_values(struct drm_i915_private
> > *dev_priv,
> > + enum port port)
> > +{
> > + const struct cnl_procmon *procmon;
> > + bool ret;
> > +
> > + procmon = cnl_get_procmon_ref_values(dev_priv, port);
> > +
> > + ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
> > + (0xff << 16) | 0xff, procmon->dw1);
> > + ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
> > +-1U, procmon->dw9);
> > + ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
> > +-1U, procmon->dw10);
> > +
> > + return ret;
> > +}
> > +
> > +static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
> > +{
> > + return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
> > + (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
>
>
> Minor but would be better add parenthesis in the first part:
>
> return (!(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN)) &&
> (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
That's overdoing it imo. Consider that you wouldn't do the same for
!a && b
>
> > +}
> > +
> > +static bool cnl_combo_phy_verify_state(struct drm_i915_private
> > *dev_priv)
> > +{
> > + enum port port = PORT_A;
> > + bool ret;
> > +
> > + if (!cnl_combo_phy_enabled(dev_priv))
> > + return false;
> > +
> > + ret = cnl_verify_procmon_ref_values(dev_priv, port);
> > +
> > + ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
> > +CL_POWER_DOWN_ENABLE,
> > CL_POWER_DOWN_ENABLE);
> > +
> > + return ret;
> > +}
> > +
> > void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
> > {
> > u32 val;
> > @@ -113,11 +181,38 @@ void cnl_combo_phys_uninit(struct
> > drm_i915_private *dev_priv)
> > {
> > u32 val;
> >
> > + if (!cnl_combo_phy_verify_state(dev_priv))
> > + DRM_WARN("Combo PHY HW state changed unexpectedly.\n");
> > +
> > val = I915_READ(CHICKEN_MISC_2);
> > val |= CNL_COMP_PWR_DOWN;
> > I915_WRITE(CHICKEN_MISC_2, val);
> > }
> >
> > +static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> > + enum port port)
> > +{
> > + return !(I915_READ(ICL_PHY_MISC(port)) &
> > +ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSC enabling remaining patches respin
== Series Details == Series: DSC enabling remaining patches respin URL : https://patchwork.freedesktop.org/series/51986/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:200:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:200:61:got int +drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:207:25:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:207:25:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types) Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1893:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1897:31: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1897:31: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3709:16: warning: expression using sizeof(void) Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC Okay! Commit: drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Configure MG DP mode for HDMI ports too
On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote:
> The MG DP mode needs to be configured for Type C static/fixed/legacy
> HDMI ports too, the same way as it's configured for Type C
> static/fixed/legacy, fix this.
Reviewed-by: José Roberto de Souza
>
> Bspec: 4232, 21735
> Cc: Vandita Kulkarni
> Cc: Paulo Zanoni
> Cc: Maarten Lankhorst
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 68
> +++-
> drivers/gpu/drm/i915/intel_dp.c | 66 --
>
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 3 files changed, 67 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index cb06058179fd..ab9a36c4ba3b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2980,6 +2980,71 @@ static void
> icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> I915_WRITE(MG_MISC_SUS0(tc_port), val);
> }
>
> +static void icl_program_mg_dp_mode(struct intel_digital_port
> *intel_dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(intel_dig_port-
> >base.base.dev);
> + enum port port = intel_dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + u32 ln0, ln1, lane_info;
> +
> + if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type ==
> TC_PORT_TBT)
> + return;
> +
> + ln0 = I915_READ(MG_DP_MODE(port, 0));
> + ln1 = I915_READ(MG_DP_MODE(port, 1));
> +
> + switch (intel_dig_port->tc_type) {
> + case TC_PORT_TYPEC:
> + ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE);
> + ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE);
> +
> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> + DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> + DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> +
> + switch (lane_info) {
> + case 0x1:
> + case 0x4:
> + break;
> + case 0x2:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> + break;
> + case 0x3:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> +MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + case 0x8:
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> + break;
> + case 0xC:
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> +MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + case 0xF:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> +MG_DP_MODE_CFG_DP_X2_MODE;
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> +MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + default:
> + MISSING_CASE(lane_info);
> + }
> + break;
> +
> + case TC_PORT_LEGACY:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE;
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> +
> + default:
> + MISSING_CASE(intel_dig_port->tc_type);
> + return;
> + }
> +
> + I915_WRITE(MG_DP_MODE(port, 0), ln0);
> + I915_WRITE(MG_DP_MODE(port, 1), ln1);
> +}
> +
> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state)
> @@ -3002,7 +3067,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> - icl_program_mg_dp_mode(intel_dp);
> + icl_program_mg_dp_mode(dig_port);
> icl_disable_phy_clock_gating(dig_port);
>
> if (IS_ICELAKE(dev_priv))
> @@ -3044,6 +3109,7 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> + icl_program_mg_dp_mode(dig_port);
> icl_disable_phy_clock_gating(dig_port);
>
> if (IS_ICELAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 127fc82902c6..b667fa85f609 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -241,72 +241,6 @@ intel_dp_link_required(int pixel_clock, int bpp)
> return DIV_ROUND_UP(pixel_clock * bpp, 8);
> }
>
> -void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
> -{
> - struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - enum port port =
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Release DDI power well references in MST ports
On Fri, Nov 02, 2018 at 01:39:22PM -0700, José Roberto de Souza wrote:
> MST ports did not had the post_pll_disable() hook causing the
> references get in pre_pll_enable() never being released causing
> DDI and AUX CH being enabled all the times.
>
> Cc: Imre Deak
> Cc: Manasi Navare
> Signed-off-by: José Roberto de Souza
Err, thanks for catching it. We really need more testing on MST.. You
could also add the Fixes: line.
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 8b71d64ebd9d..8e3d0b04580b 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -215,6 +215,20 @@ static void intel_mst_pre_pll_enable_dp(struct
> intel_encoder *encoder,
> pipe_config, NULL);
> }
>
> +static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state
> *pipe_config,
> + const struct drm_connector_state
> *conn_state)
> +{
Nit: these are better called old_crtc_state, old_conn_state.
> + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
> + struct intel_digital_port *intel_dig_port = intel_mst->primary;
> + struct intel_dp *intel_dp = _dig_port->dp;
> +
> + if (intel_dp->active_mst_links == 0 &&
> + intel_dig_port->base.post_pll_disable)
Since by now all DDI platforms (which are the only platforms supporting
MST) define the .pre_pll_enable() .post_pll_disable() hooks you could
remove the NULL check for them (in a follow-up patch).
Either with or without changing the above nit:
Reviewed-by: Imre Deak
> + intel_dig_port->base.post_pll_disable(_dig_port->base,
> + pipe_config, NULL);
> +}
> +
> static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state
> *conn_state)
> @@ -549,6 +563,7 @@ intel_dp_create_fake_mst_encoder(struct
> intel_digital_port *intel_dig_port, enum
> intel_encoder->disable = intel_mst_disable_dp;
> intel_encoder->post_disable = intel_mst_post_disable_dp;
> intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
> + intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
> intel_encoder->pre_enable = intel_mst_pre_enable_dp;
> intel_encoder->enable = intel_mst_enable_dp;
> intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> --
> 2.19.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DSC enabling remaining patches respin
== Series Details ==
Series: DSC enabling remaining patches respin
URL : https://patchwork.freedesktop.org/series/51986/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9b21924528e8 drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 342 lines checked
16a55a785bf0 drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Gaurav K Singh
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
ce9a9d5aa5fb drm/dsc: Define Rate Control values that do not change over
configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Srivatsa, Anusha '
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
6af5ac50eb08 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 285 lines checked
c08bada2b32b drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
25415c4aaac3 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:942:
+ bool compression_enable;
-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
a0605ab24857 drm/i915/dp: Compute DSC pipe config in atomic check
-:166: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#166: FILE: drivers/gpu/drm/i915/intel_dp.c:1897:
+ bpp = min(bpp, 3*bpc);
^
-:268: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#268: FILE: drivers/gpu/drm/i915/intel_dp.c:2109:
+ limits.max_bpp >= DP_DSC_MIN_SUPPORTED_BPC*3)
^
total: 0 errors, 0 warnings, 2 checks, 289 lines checked
a333f52a4ca6 drm/i915/dp: Do not enable PSR2 if DSC is enabled
841953754a45 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68:
Co-developed-by: Manasi Navare
-:95: WARNING:MISSING_SPACE: break quoted strings at a space character
#95: FILE: drivers/gpu/drm/i915/intel_dp.c:2077:
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#119:
new file mode 100644
-:405: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#405: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3 warnings, 1 checks, 496 lines checked
1f8a2181315a drm/i915/dsc: Compute Rate Control parameters for DSC
-:141: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#141: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+ vdsc_cfg->slice_bpg_offset)*
^
-:173: CHECK:LINE_SPACING: Please don't use multiple blank lines
#173: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+
total: 0 errors, 0 warnings, 2 checks, 138 lines checked
Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Configure MG PHY gating for HDMI ports too
On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote:
> The MG PHY clock gating needs to be configured for Type C
> static/fixed/legacy HDMI ports the same way it's configured for Type
> C
> static/fixed/legacy and aternate mode DP ports, fix this.
>
Reviewed-by: José Roberto de Souza
> Bspec: 4232, 21735
> Cc: Vandita Kulkarni
> Cc: Paulo Zanoni
> Cc: Maarten Lankhorst
> Cc: Manasi Navare
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 70
>
> drivers/gpu/drm/i915/intel_dp.c | 66 --
> ---
> drivers/gpu/drm/i915/intel_drv.h | 2 --
> 3 files changed, 70 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 3eea987e909b..cb06058179fd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2914,6 +2914,72 @@ static void intel_ddi_clk_disable(struct
> intel_encoder *encoder)
> }
> }
>
> +static void icl_enable_phy_clock_gating(struct intel_digital_port
> *dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> + enum port port = dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> 1) };
> + u32 val;
> + int i;
> +
> + if (tc_port == PORT_TC_NONE)
> + return;
> +
> + for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> + val = I915_READ(mg_regs[i]);
> + val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> +MG_DP_MODE_CFG_TRPWR_GATING |
> +MG_DP_MODE_CFG_CLNPWR_GATING |
> +MG_DP_MODE_CFG_DIGPWR_GATING |
> +MG_DP_MODE_CFG_GAONPWR_GATING;
> + I915_WRITE(mg_regs[i], val);
> + }
> +
> + val = I915_READ(MG_MISC_SUS0(tc_port));
> + val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
> +MG_MISC_SUS0_CFG_TR2PWR_GATING |
> +MG_MISC_SUS0_CFG_CL2PWR_GATING |
> +MG_MISC_SUS0_CFG_GAONPWR_GATING |
> +MG_MISC_SUS0_CFG_TRPWR_GATING |
> +MG_MISC_SUS0_CFG_CL1PWR_GATING |
> +MG_MISC_SUS0_CFG_DGPWR_GATING;
> + I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +}
> +
> +static void icl_disable_phy_clock_gating(struct intel_digital_port
> *dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> + enum port port = dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> 1) };
> + u32 val;
> + int i;
> +
> + if (tc_port == PORT_TC_NONE)
> + return;
> +
> + for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> + val = I915_READ(mg_regs[i]);
> + val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> + MG_DP_MODE_CFG_TRPWR_GATING |
> + MG_DP_MODE_CFG_CLNPWR_GATING |
> + MG_DP_MODE_CFG_DIGPWR_GATING |
> + MG_DP_MODE_CFG_GAONPWR_GATING);
> + I915_WRITE(mg_regs[i], val);
> + }
> +
> + val = I915_READ(MG_MISC_SUS0(tc_port));
> + val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
> + MG_MISC_SUS0_CFG_TR2PWR_GATING |
> + MG_MISC_SUS0_CFG_CL2PWR_GATING |
> + MG_MISC_SUS0_CFG_GAONPWR_GATING |
> + MG_MISC_SUS0_CFG_TRPWR_GATING |
> + MG_MISC_SUS0_CFG_CL1PWR_GATING |
> + MG_MISC_SUS0_CFG_DGPWR_GATING);
> + I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +}
> +
> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state)
> @@ -2978,6 +3044,8 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> + icl_disable_phy_clock_gating(dig_port);
> +
> if (IS_ICELAKE(dev_priv))
> icl_ddi_vswing_sequence(encoder, crtc_state-
> >port_clock,
> level, INTEL_OUTPUT_HDMI);
> @@ -2988,6 +3056,8 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
> else
> intel_prepare_hdmi_ddi_buffers(encoder, level);
>
> + icl_enable_phy_clock_gating(dig_port);
> +
> if (IS_GEN9_BC(dev_priv))
> skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index b39b4bda8e40..127fc82902c6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -307,72 +307,6 @@ void icl_program_mg_dp_mode(struct intel_dp
> *intel_dp)
>
[Intel-gfx] [PATCH] drm/lease: look at ->universal_planes only once
It's lockless, and userspace might chance it underneath us. That's not
really a problem, all userspace gets is a slightly dysfunctional
lease with the current code. But this might change, and gcc might
decide to reload a few too many times, and then boom. So better safe
than sorry.
v2: Remove the now unused lessor_priv argument from validate_lease()
(Keith).
Cc: Keith Packard
Cc: Dave Airlie
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_lease.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c
index 3b0342a45ae9..739d3830173f 100644
--- a/drivers/gpu/drm/drm_lease.c
+++ b/drivers/gpu/drm/drm_lease.c
@@ -353,9 +353,9 @@ void drm_lease_revoke(struct drm_master *top)
}
static int validate_lease(struct drm_device *dev,
- struct drm_file *lessor_priv,
int object_count,
- struct drm_mode_object **objects)
+ struct drm_mode_object **objects,
+ bool universal_planes)
{
int o;
int has_crtc = -1;
@@ -372,14 +372,14 @@ static int validate_lease(struct drm_device *dev,
if (objects[o]->type == DRM_MODE_OBJECT_CONNECTOR &&
has_connector == -1)
has_connector = o;
- if (lessor_priv->universal_planes) {
+ if (universal_planes) {
if (objects[o]->type == DRM_MODE_OBJECT_PLANE &&
has_plane == -1)
has_plane = o;
}
}
if (has_crtc == -1 || has_connector == -1)
return -EINVAL;
- if (lessor_priv->universal_planes && has_plane == -1)
+ if (universal_planes && has_plane == -1)
return -EINVAL;
return 0;
}
@@ -393,6 +393,8 @@ static int fill_object_idr(struct drm_device *dev,
struct drm_mode_object **objects;
u32 o;
int ret;
+ bool universal_planes = READ_ONCE(lessor_priv->universal_planes);
+
objects = kcalloc(object_count, sizeof(struct drm_mode_object *),
GFP_KERNEL);
if (!objects)
@@ -421,7 +423,8 @@ static int fill_object_idr(struct drm_device *dev,
}
}
- ret = validate_lease(dev, lessor_priv, object_count, objects);
+ ret = validate_lease(dev, lessor_priv, object_count, objects,
+universal_planes);
if (ret) {
DRM_DEBUG_LEASE("lease validation failed\n");
goto out_free_objects;
@@ -448,7 +451,7 @@ static int fill_object_idr(struct drm_device *dev,
object_id, ret);
goto out_free_objects;
}
- if (obj->type == DRM_MODE_OBJECT_CRTC &&
!lessor_priv->universal_planes) {
+ if (obj->type == DRM_MODE_OBJECT_CRTC && !universal_planes) {
struct drm_crtc *crtc = obj_to_crtc(obj);
ret = idr_alloc(leases, _lease_idr_object,
crtc->primary->base.id, crtc->primary->base.id + 1, GFP_KERNEL);
if (ret < 0) {
--
2.14.4
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/icl: Fix port B combo PHY context loss after DC transitions
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote: > On ICL DMC/PCODE retains the HW context only for port A across DC > transitions, for the other port B combo PHY, it doesn't. So we need > to > do this manually after exiting from DC6. Do the reinit even after > exiting from DC5, it won't hurt since we only reinit the PHY in case > it's needed (in case it was disabled to begin with). > > As can be guessed from the bugzilla report leaving the PHY uninited > will > lead to a later timeout during the port B specific AUX and DDI_IO > power > well enabling. > > Bspec: 21257 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108070 > Cc: Paulo Zanoni > Cc: Ville Syrjälä > Cc: José Roberto de Souza > Cc: Rodrigo Vivi > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 8 > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index f8da471e81aa..763912c0245c 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -843,6 +843,14 @@ static void gen9_dc_off_power_well_enable(struct > drm_i915_private *dev_priv, > > if (IS_GEN9_LP(dev_priv)) > bxt_verify_ddi_phy_power_wells(dev_priv); > + Minor: else if (INTEL_GEN(dev_priv) >= 11) Maybe? Other than that: Reviewed-by: José Roberto de Souza > + if (IS_ICELAKE(dev_priv)) > + /* > + * DMC retains HW context only for port A, the other > combo > + * PHY's HW context for port B is lost after DC > transitions, > + * so we need to restore it manually. > + */ > + icl_combo_phys_init(dev_priv); > } > > static void gen9_dc_off_power_well_disable(struct drm_i915_private > *dev_priv, ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915/cnl+: Verify combo PHY HW state during PHY uninit
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Verify on CNL, ICL that the combo PHY HW state stayed intact after
> PHY
> initialization.
>
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_combo_phy.c | 103
> -
> 1 file changed, 101 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> b/drivers/gpu/drm/i915/intel_combo_phy.c
> index 13184ae5a217..1522e2a25390 100644
> --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> @@ -52,8 +52,8 @@ static const struct cnl_procmon {
> * registers, that's why we call the ICL macros even though the
> function has CNL
> * on its name.
> */
> -static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> -enum port port)
> +static const struct cnl_procmon *
> +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> port port)
> {
> const struct cnl_procmon *procmon;
> u32 val;
> @@ -80,6 +80,17 @@ static void cnl_set_procmon_ref_values(struct
> drm_i915_private *dev_priv,
> break;
> }
>
> + return procmon;
> +}
> +
> +static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> +enum port port)
> +{
> + const struct cnl_procmon *procmon;
> + u32 val;
> +
> + procmon = cnl_get_procmon_ref_values(dev_priv, port);
> +
> val = I915_READ(ICL_PORT_COMP_DW1(port));
> val &= ~((0xff << 16) | 0xff);
> val |= procmon->dw1;
> @@ -89,6 +100,63 @@ static void cnl_set_procmon_ref_values(struct
> drm_i915_private *dev_priv,
> I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> }
>
> +static bool check_phy_reg(struct drm_i915_private *dev_priv,
> + enum port port, i915_reg_t reg, u32 mask,
> + u32 expected_val)
> +{
> + u32 val = I915_READ(reg);
> +
> + if ((val & mask) != expected_val) {
> + DRM_DEBUG_DRIVER("Port-%c combo PHY reg %08x state
> mismatch: "
> + "current %08x mask %08x expected
> %08x\n",
> + port_name(port),
> + reg.reg, val, mask, expected_val);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool cnl_verify_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> + enum port port)
> +{
> + const struct cnl_procmon *procmon;
> + bool ret;
> +
> + procmon = cnl_get_procmon_ref_values(dev_priv, port);
> +
> + ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
> + (0xff << 16) | 0xff, procmon->dw1);
> + ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
> + -1U, procmon->dw9);
> + ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
> + -1U, procmon->dw10);
> +
> + return ret;
> +}
> +
> +static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
> +{
> + return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
> + (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
> +}
> +
> +static bool cnl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv)
> +{
> + enum port port = PORT_A;
> + bool ret;
> +
> + if (!cnl_combo_phy_enabled(dev_priv))
> + return false;
> +
> + ret = cnl_verify_procmon_ref_values(dev_priv, port);
> +
> + ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
> + CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
> +
> + return ret;
> +}
> +
> void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
> {
> u32 val;
> @@ -113,11 +181,38 @@ void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
> {
> u32 val;
>
> + if (!cnl_combo_phy_verify_state(dev_priv))
> + DRM_WARN("Combo PHY HW state changed unexpectedly.\n");
> +
> val = I915_READ(CHICKEN_MISC_2);
> val |= CNL_COMP_PWR_DOWN;
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> +static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> + enum port port)
> +{
> + return !(I915_READ(ICL_PHY_MISC(port)) &
> + ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> + (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
> +}
> +
> +static bool icl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv,
> +enum port port)
> +{
> + bool ret;
> +
> + if (!icl_combo_phy_enabled(dev_priv, port))
> + return false;
> +
> + ret = cnl_verify_procmon_ref_values(dev_priv, port);
> +
> + ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
> +
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Reuse the aux_domain cached
On Fri, Nov 02, 2018 at 01:39:21PM -0700, José Roberto de Souza wrote:
> intel_dp_detect() caches the aux_domain in the beginning of the
> function as it is used twice, so lets also use it as the aux_domain
> don't change in runtime.
>
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_dp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e7233dfa1794..52a54ef746af 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5289,8 +5289,7 @@ intel_dp_detect(struct drm_connector *connector,
>
> ret = intel_dp_retrain_link(encoder, ctx);
> if (ret) {
> - intel_display_power_put(dev_priv,
> -
> intel_aux_power_domain(dig_port));
> + intel_display_power_put(dev_priv, aux_domain);
Thanks for catching it.
status = ret;
goto out_put_power;
and adding the label at the end would be cleaner. Either way:
Reviewed-by: Imre Deak
> return ret;
> }
> }
> --
> 2.19.1
>
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/icl: Skip init for an already enabled combo PHY
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Bspec says we should skip the initialization of combo PHYs that are
> already initialized. We'll need to reinit the PHYs more frequently
> when exiting from DC6 (after the next patch), so let's make sure the
> uninit sequence complies with the spec. For safety skip the init only
> if
> all the PHY register fields have their expected values.
>
> Bspec: 21257
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_combo_phy.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> b/drivers/gpu/drm/i915/intel_combo_phy.c
> index 1522e2a25390..7b911702f834 100644
> --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> @@ -220,6 +220,12 @@ void icl_combo_phys_init(struct drm_i915_private
> *dev_priv)
> for (port = PORT_A; port <= PORT_B; port++) {
> u32 val;
>
> + if (icl_combo_phy_verify_state(dev_priv, port)) {
> + DRM_DEBUG_DRIVER("Port-%c combo PHY already
> enabled, won't reprogram it.\n",
> + port_name(port));
> + continue;
> + }
> +
> val = I915_READ(ICL_PHY_MISC(port));
> val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> I915_WRITE(ICL_PHY_MISC(port), val);
___
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[Intel-gfx] [PATCH v8 16/19] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 85af5f784aad..fae5193551d8 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1010,6 +1010,12 @@ static void intel_dp_write_dsc_pps_sdp(struct
intel_encoder *encoder,
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1018,5 +1024,20 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.18.0
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[Intel-gfx] [PATCH v8 12/19] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index b0b23e1e9392..4e6b824ccc8c 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -226,6 +226,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c453366cd24..acbe52adbf16 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2006,9 +2008,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
2.18.0
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[Intel-gfx] [PATCH v8 08/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bc2d88313ed0..08967657b742 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
if (i915_modparams.enable_psr == -1)
return false;
+ /* Cannot enable DSC and PSR2 simultaneously */
+ WARN_ON(crtc_state->dsc_params.compression_enable &&
+ crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -463,6 +467,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.18.0
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[Intel-gfx] [PATCH v8 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 127 ++
1 file changed, 127 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0a1918f2f643..a76f78b9c0ee 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_DEBUG_KMS("FinalOfs < RcModelSze for this
InitialXmitDelay\n");
+ return -EINVAL;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size * 8) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_DEBUG_KMS("NflBpgOffset is too large for this slice
height\n");
+ return -EINVAL;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+
[Intel-gfx] [PATCH v8 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0eaa69778160..85af5f784aad 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(encoder, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -997,5 +1016,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
2.18.0
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[Intel-gfx] [PATCH v8 05/19] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
--
2.18.0
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[Intel-gfx] [PATCH v8 14/19] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 21 +++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0e6e14fe9fa..49c3c24965eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4550,6 +4550,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 0c587e4503e3..61867a6733a8 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ int data_size;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
2.18.0
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[Intel-gfx] [PATCH v8 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 6 +
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_vdsc.c| 419 +++
4 files changed, 428 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7797a41c648..f347d0d7b9eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3485,6 +3485,8 @@ extern void intel_rps_mark_interactive(struct
drm_i915_private *i915,
bool interactive);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index af12c15ed94f..bba08322afb7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2962,6 +2962,12 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
+
+ /*
+* Enable and Configure Display Stream Compression in the source
+* if enabled in intel_crtc_state.
+*/
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 477e53c37353..d3aa77f4d606 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5417,6 +5417,7 @@ static void intel_encoders_pre_enable(struct drm_crtc
*crtc,
if (encoder->pre_enable)
encoder->pre_enable(encoder, crtc_state, conn_state);
+
}
}
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index a76f78b9c0ee..0eaa69778160 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -580,3 +580,422 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return 0;
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ else
+ pps_val &= ~DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ else
+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ else
+ pps_val &= ~DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ else
+ pps_val &= ~DSC_VBR_ENABLE;
+
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+ /*
+* If 2
[Intel-gfx] [PATCH v8 09/19] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
5 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 28c7d7884e88..a51a9ae0f496 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -156,7 +156,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 58326fc9d935..3d401a4e93b8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2072,6 +2072,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 491872353cf0..3b57146766bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1853,6 +1853,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..0a1918f2f643
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh
+ * Manasi Navare
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+
[Intel-gfx] [PATCH v8 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 16
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3eea987e909b..af12c15ed94f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2952,6 +2952,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3291,6 +3293,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ false);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3d401a4e93b8..f8bf942c8f71 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2972,6 +2972,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE,
+enable ? DP_DECOMPRESSION_EN : 0);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ enable ? "enable" : "disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3b57146766bb..e537561b3d40 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1795,6 +1795,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.18.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c | 25 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index bba08322afb7..82d78f2727d8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2126,6 +2126,12 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+ /*
+* VDSC power is needed when DSC is enabled
+*/
+ if (crtc_state->dsc_params.compression_enable)
+ domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e537561b3d40..2d41dff6eed1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1859,6 +1859,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp, int mode_clock,
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 02102cd275fd..a25b71ae9b1c 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -581,6 +581,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return 0;
}
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ /*
+* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* For any other transcoder, VDSC/joining uses the power well associated
+* with the pipe/transcoder in use. Hence another reference on the
+* transcoder power domain will suffice.
+*/
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else
+ return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
@@ -1020,6 +1038,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
+ /* Enable Power wells for VDSC/joining */
+ intel_display_power_get(dev_priv,
+ intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1072,4 +1094,7 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+ /* Disable Power wells for VDSC/joining */
+ intel_display_power_put(dev_priv,
+ intel_dsc_power_domain(old_crtc_state));
}
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 00/19] DSC enabling remaining patches respin
This patch series addresses following comments from the previous series: https://patchwork.freedesktop.org/series/51916/ - no FEC so should reject DSC on external DP -> Added this to intel_dp_source_supports_dsc - get_power_domains() thing wasn't right -> Fixed the logic -The potentially user triggerable DRM_ERROR()s have to be removed or explained why they can't happen (in which case a WARN() would probably be a more clear hint to the reader). -> Changed DRM_ERROR to DRM_DEBUG_KMS The intel_dsc_enable() call I definitely would like see moved into the encoder->per_enable(). No one will think to look for it in the current location. -> Moved this to intel_ddi_pre_enable_dp The i915_modparams.enable_psr change seemed unrelated, but no idea if it's intentional or not. -> Removed unintentional changes And finally there were various style nits that are optional. But I would recomment doing them since it's trivial stuff and avoids further churn in the code later. -> Fixed the nits Gaurav K Singh (3): drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare (15): drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Define VESA Display Stream Compression Capabilities drm/dsc: Add helpers for DSC picture parameter set infoframes drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable drm/i915/dp: Disable DSC in source by disabling DSS CTL bits drm/i915/dsc: Enable and disable appropriate power wells for VDSC drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Srivatsa, Anusha (1): drm/dsc: Define Rate Control values that do not change over configurations Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile|2 +- drivers/gpu/drm/drm_dsc.c | 228 + drivers/gpu/drm/i915/Makefile |3 +- drivers/gpu/drm/i915/i915_debugfs.c | 71 +- drivers/gpu/drm/i915/i915_drv.h |4 + drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_ddi.c| 17 + drivers/gpu/drm/i915/intel_display.c| 23 +- drivers/gpu/drm/i915/intel_display.h|4 +- drivers/gpu/drm/i915/intel_dp.c | 191 +++- drivers/gpu/drm/i915/intel_dp_mst.c |2 +- drivers/gpu/drm/i915/intel_drv.h| 21 + drivers/gpu/drm/i915/intel_hdmi.c | 21 +- drivers/gpu/drm/i915/intel_psr.c| 14 + drivers/gpu/drm/i915/intel_runtime_pm.c |4 +- drivers/gpu/drm/i915/intel_vdsc.c | 1100 +++ include/drm/drm_dp_helper.h |3 + include/drm/drm_dsc.h | 485 ++ 19 files changed, 2174 insertions(+), 32 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v3:
* Combine Force_dsc_en with this patch (Ville)
v2:
* Use kstrtobool_from_user to avoid explicit error checking (Lyude)
* Rebase on drm-tip (Manasi)
Cc: Rodrigo Vivi
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Lyude Paul
Signed-off-by: Manasi Navare
Reviewed-by: Lyude Paul
---
drivers/gpu/drm/i915/i915_debugfs.c | 71 -
drivers/gpu/drm/i915/intel_dp.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h| 3 ++
3 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a4d9d996fda..fe619b54b64d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5000,6 +5000,72 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_dsc_support_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_encoder *encoder = intel_attached_encoder(connector);
+ struct intel_dp *intel_dp =
+ enc_to_intel_dp(>base);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+
+ crtc = to_intel_crtc(encoder->base.crtc);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+ drm_modeset_lock(>base.mutex, NULL);
+ seq_printf(m, "Enabled: %s\n",
+ yesno(crtc_state->dsc_params.compression_enable));
+ seq_printf(m, "Supported: %s\n",
+ yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+ drm_modeset_unlock(>base.mutex);
+
+ return 0;
+}
+
+static ssize_t i915_dsc_support_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ bool dsc_enable = false;
+ int ret;
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder = intel_attached_encoder(connector);
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+
+ if (len == 0)
+ return 0;
+
+ DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
+(unsigned int)len);
+
+ ret = kstrtobool_from_user(ubuf, len, _enable);
+ if (ret < 0)
+ return ret;
+
+ DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
+(dsc_enable) ? "true" : "false");
+ intel_dp->force_dsc_en = dsc_enable;
+
+ *offp += len;
+ return len;
+}
+
+static int i915_dsc_support_open(struct inode *inode,
+struct file *file)
+{
+ return single_open(file, i915_dsc_support_show,
+ inode->i_private);
+}
+
+static const struct file_operations i915_dsc_support_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_support_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_support_write
+};
+
/**
* i915_debugfs_connector_add - add i915 specific connector debugfs files
* @connector: pointer to a registered drm_connector
@@ -5018,9 +5084,12 @@ int i915_debugfs_connector_add(struct drm_connector
*connector)
return -ENODEV;
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
- connector->connector_type == DRM_MODE_CONNECTOR_eDP)
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
debugfs_create_file("i915_dpcd", S_IRUGO, root,
connector, _dpcd_fops);
+ debugfs_create_file("i915_dsc_support", S_IRUGO, root,
+ connector, _dsc_support_fops);
+ }
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
debugfs_create_file("i915_panel_timings", S_IRUGO, root,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f8bf942c8f71..4d866d49d870 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2158,7 +2158,7 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
);
/* enable compression if the mode doesn't fit available BW */
- if (!ret) {
+ if (!ret || intel_dp->force_dsc_en) {
if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
))
return false;
@@ -2251,6 +2251,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
[Intel-gfx] [PATCH v8 17/19] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c| 32
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f347d0d7b9eb..c80c9a1af3d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3487,6 +3487,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
extern void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d3aa77f4d606..cbeea906c531 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5848,6 +5848,8 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index fae5193551d8..02102cd275fd 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1041,3 +1041,35 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+}
--
2.18.0
___
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[Intel-gfx] [PATCH v8 03/19] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 3292dfed9d0a..b88e31bd9da7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
2.18.0
___
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[Intel-gfx] [PATCH v8 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v7:
* Use BUILD_BUG_ON() to protect changing struct size (Ville)
* Remove typecaseting (Ville)
* Include byteorder.h in drm_dsc.c (Ville)
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in
Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 228 ++
include/drm/drm_dsc.h | 21 +++
4 files changed, 262 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index 4b4dc236ef6f..b422eb8edf16 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 576ba985e138..3a3e6fb6d476 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index ..3a4942c1ae3b
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ const struct drm_dsc_config *dsc_cfg)
+{
+ int i;
+
+ /*Protect against someone accidently changing struct size */
+ BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+
+ memset(_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version =
+ dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+ /* PPS 3 */
+
[Intel-gfx] [PATCH v8 06/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
v2:
* Rebase on drm-tip (Manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6157f8128cc5..d7797a41c648 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include "i915_params.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 191c26e17f2d..491872353cf0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -936,6 +936,15 @@ struct intel_crtc_state {
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
2.18.0
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[Intel-gfx] [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 20 +++-
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 167 ---
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
4 files changed, 166 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b219d5858160..477e53c37353 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
- intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+ intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
link_bw, _config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n)
{
m_n->tu = 64;
- compute_m_n(bits_per_pixel * pixel_clock,
- link_clock * nlanes * 8,
- _n->gmch_m, _n->gmch_n,
- constant_n);
+ /* For DSC, Data M/N calculation uses compressed BPP */
+ if (compressed_bpp)
+ compute_m_n(compressed_bpp * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
+ else
+ compute_m_n(bits_per_pixel * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..b0b23e1e9392 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -407,7 +407,8 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b39b4bda8e40..58326fc9d935 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1840,6 +1842,29 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
[Intel-gfx] [PATCH v8 01/19] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
v4:
* Remove redundant blankline in doc (Ville)
* use drm_dsc namespace for all structs (Ville)
* Use packed struct (Ville)
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
---
include/drm/drm_dsc.h | 342 ++
1 file changed, 342 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index ..78db4f61d01c
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct drm_dsc_picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16 pic_width;
+ /**
+* @slice_height:
+* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+*/
+ __be16 slice_height;
+ /**
+* @slice_width:
+* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+*/
+ __be16 slice_width;
+ /**
+* @chunk_size:
+* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+* that are used for slice multiplexing.
+*/
+ __be16 chunk_size;
+ /**
+* @initial_xmit_delay_high:
+* PPS16[1:0] - Most Significant two bits of initial transmission delay.
+* It specifies the number of pixel times that the encoder waits before
+* transmitting data from its rate buffer.
+* PPS16[7:2] - Reserved
+*/
+
[Intel-gfx] [PATCH v8 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed-by: Gaurav K Singh
Acked-by: Harry Wentland
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 78db4f61d01c..3292dfed9d0a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
#include
/* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES 15
+#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+#define DSC_RC_PIXELS_PER_GROUP3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
+#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+
+/* Configuration for a single Rate Control model range */
+struct drm_dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie.,
Re: [Intel-gfx] [PATCH 3/5] drm/i915/cnl+: Verify combo PHY HW state during PHY uninit
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Verify on CNL, ICL that the combo PHY HW state stayed intact after
> PHY
> initialization.
>
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_combo_phy.c | 103
> -
> 1 file changed, 101 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> b/drivers/gpu/drm/i915/intel_combo_phy.c
> index 13184ae5a217..1522e2a25390 100644
> --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> @@ -52,8 +52,8 @@ static const struct cnl_procmon {
> * registers, that's why we call the ICL macros even though the
> function has CNL
> * on its name.
> */
> -static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> -enum port port)
> +static const struct cnl_procmon *
> +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> port port)
> {
> const struct cnl_procmon *procmon;
> u32 val;
> @@ -80,6 +80,17 @@ static void cnl_set_procmon_ref_values(struct
> drm_i915_private *dev_priv,
> break;
> }
>
> + return procmon;
> +}
> +
> +static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> +enum port port)
> +{
> + const struct cnl_procmon *procmon;
> + u32 val;
> +
> + procmon = cnl_get_procmon_ref_values(dev_priv, port);
> +
> val = I915_READ(ICL_PORT_COMP_DW1(port));
> val &= ~((0xff << 16) | 0xff);
> val |= procmon->dw1;
> @@ -89,6 +100,63 @@ static void cnl_set_procmon_ref_values(struct
> drm_i915_private *dev_priv,
> I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> }
>
> +static bool check_phy_reg(struct drm_i915_private *dev_priv,
> + enum port port, i915_reg_t reg, u32 mask,
> + u32 expected_val)
> +{
> + u32 val = I915_READ(reg);
> +
> + if ((val & mask) != expected_val) {
> + DRM_DEBUG_DRIVER("Port-%c combo PHY reg %08x state
> mismatch: "
> + "current %08x mask %08x expected
> %08x\n",
> + port_name(port),
> + reg.reg, val, mask, expected_val);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool cnl_verify_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> + enum port port)
> +{
> + const struct cnl_procmon *procmon;
> + bool ret;
> +
> + procmon = cnl_get_procmon_ref_values(dev_priv, port);
> +
> + ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
> + (0xff << 16) | 0xff, procmon->dw1);
> + ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
> + -1U, procmon->dw9);
> + ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
> + -1U, procmon->dw10);
> +
> + return ret;
> +}
> +
> +static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
> +{
> + return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
> + (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
Minor but would be better add parenthesis in the first part:
return (!(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN)) &&
(I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
> +}
> +
> +static bool cnl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv)
> +{
> + enum port port = PORT_A;
> + bool ret;
> +
> + if (!cnl_combo_phy_enabled(dev_priv))
> + return false;
> +
> + ret = cnl_verify_procmon_ref_values(dev_priv, port);
> +
> + ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
> + CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
> +
> + return ret;
> +}
> +
> void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
> {
> u32 val;
> @@ -113,11 +181,38 @@ void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
> {
> u32 val;
>
> + if (!cnl_combo_phy_verify_state(dev_priv))
> + DRM_WARN("Combo PHY HW state changed unexpectedly.\n");
> +
> val = I915_READ(CHICKEN_MISC_2);
> val |= CNL_COMP_PWR_DOWN;
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> +static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> + enum port port)
> +{
> + return !(I915_READ(ICL_PHY_MISC(port)) &
> + ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> + (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
Same in here:
return (!(I915_READ(ICL_PHY_MISC(port)) &
ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN)) &&
(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
Other than that:
Reviewed-by: José Roberto de Souza
> +}
> +
> +static bool icl_combo_phy_verify_state(struct
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/25] RFT drm/i915/execlists: Flush memory before signaling ELSQ
== Series Details == Series: series starting with [01/25] RFT drm/i915/execlists: Flush memory before signaling ELSQ URL : https://patchwork.freedesktop.org/series/51967/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5081_full -> Patchwork_10713_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10713_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10713_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10713_full: === IGT changes === Possible regressions igt@drv_selftest@live_hangcheck: shard-hsw: PASS -> DMESG-WARN igt@drv_selftest@live_workarounds: shard-apl: PASS -> DMESG-WARN shard-glk: PASS -> DMESG-WARN Warnings igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy: shard-snb: SKIP -> PASS +3 igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10713_full that come from known issues: === IGT changes === Issues hit igt@gem_eio@reset-stress: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@gem_render_copy_redux@normal: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106650) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-glk: PASS -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-c-legacy-gamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-256x85-sliding: shard-skl: PASS -> FAIL (fdo#103232) igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#106509, fdo#105454) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@plain-flip-ts-check-interruptible: shard-kbl: PASS -> FAIL (fdo#100368) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-skl: NOTRUN -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: PASS -> FAIL (fdo#107815) igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) shard-apl: PASS -> FAIL (fdo#103166) +1 Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: TIMEOUT (fdo#108039) -> PASS igt@kms_busy@extended-pageflip-hang-newfb-render-b: shard-glk: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-128x42-random: shard-skl: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x85-random: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_flip@flip-vs-expired-vblank: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-apl: FAIL (fdo#108145) -> PASS igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-glk: FAIL (fdo#103166) -> PASS +2 igt@pm_rpm@legacy-planes-dpms: shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
Re: [Intel-gfx] [PATCH 2/5] drm/i915/cnl+: Move the combo PHY init/uninit code to a new file
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote:
> Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code
> in a
> separate file.
>
> No functional change.
>
> Suggested-by: Ville Syrjälä
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> drivers/gpu/drm/i915/intel_combo_phy.c | 159
>
> drivers/gpu/drm/i915/intel_runtime_pm.c | 127 ++--
> -
> 4 files changed, 174 insertions(+), 119 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_combo_phy.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 28c7d7884e88..1e7e9513bb10 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -113,6 +113,7 @@ i915-y += intel_audio.o \
> intel_bios.o \
> intel_cdclk.o \
> intel_color.o \
> + intel_combo_phy.o \
> intel_connector.o \
> intel_display.o \
> intel_dpio_phy.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 6157f8128cc5..62882e1ddbee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3571,6 +3571,12 @@ void vlv_phy_pre_encoder_enable(struct
> intel_encoder *encoder,
> void vlv_phy_reset_lanes(struct intel_encoder *encoder,
>const struct intel_crtc_state
> *old_crtc_state);
>
> +/* intel_combo_phy.c */
> +void icl_combo_phys_init(struct drm_i915_private *dev_priv);
> +void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> +void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
> +void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> +
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> b/drivers/gpu/drm/i915/intel_combo_phy.c
> new file mode 100644
> index ..13184ae5a217
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> @@ -0,0 +1,159 @@
> +/*
> + * Copyright © 2018 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice (including
> the next
> + * paragraph) shall be included in all copies or substantial
> portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "intel_drv.h"
> +
> +enum {
> + PROCMON_0_85V_DOT_0,
> + PROCMON_0_95V_DOT_0,
> + PROCMON_0_95V_DOT_1,
> + PROCMON_1_05V_DOT_0,
> + PROCMON_1_05V_DOT_1,
> +};
> +
> +static const struct cnl_procmon {
> + u32 dw1, dw9, dw10;
> +} cnl_procmon_values[] = {
> + [PROCMON_0_85V_DOT_0] =
> + { .dw1 = 0x, .dw9 = 0x62AB67BB, .dw10 =
> 0x51914F96, },
> + [PROCMON_0_95V_DOT_0] =
> + { .dw1 = 0x, .dw9 = 0x86E172C7, .dw10 =
> 0x77CA5EAB, },
> + [PROCMON_0_95V_DOT_1] =
> + { .dw1 = 0x, .dw9 = 0x93F87FE1, .dw10 =
> 0x8AE871C5, },
> + [PROCMON_1_05V_DOT_0] =
> + { .dw1 = 0x, .dw9 = 0x98FA82DD, .dw10 =
> 0x89E46DC1, },
> + [PROCMON_1_05V_DOT_1] =
> + { .dw1 = 0x0044, .dw9 = 0x9A00AB25, .dw10 =
> 0x8AE38FF1, },
> +};
> +
> +/*
> + * CNL has just one set of registers, while ICL has two sets: one
> for port A and
> + * the other for port B. The CNL registers are equivalent to the ICL
> port A
> + * registers, that's why we call the ICL macros even though the
> function has CNL
> + * on its name.
> + */
> +static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> +enum port port)
> +{
> + const struct cnl_procmon *procmon;
> + u32 val;
> +
> + val = I915_READ(ICL_PORT_COMP_DW3(port));
> + switch (val &
Re: [Intel-gfx] [PATCH v7 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
On Fri, Nov 02, 2018 at 07:52:53PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:53PM -0700, Manasi Navare wrote:
> > After encoder->pre_enable() hook, after link training sequence is
> > completed, PPS registers for DSC encoder are configured using the
> > DSC state parameters in intel_crtc_state as part of DSC enabling
> > routine in the source. DSC enabling routine is called after
> > encoder->pre_enable() before enbaling the pipe and after
> > compression is enabled on the sink.
> >
> > v5:
> > * make crtc_state const (Ville)
> > v4:
> > * Use cpu_transcoder instead of encoder->type for using EDP transcoder
> > DSC registers(Ville)
> > * Keep all PSS regs together (Anusha)
> >
> > v3:
> > * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
> > are used (Manasi)
> > * Add DSC slice_row_per_frame in PPS16 (Manasi)
> >
> > v2:
> > * Enable PG2 power well for VDSC on eDP
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 +
> > drivers/gpu/drm/i915/intel_display.c | 6 +
> > drivers/gpu/drm/i915/intel_vdsc.c| 419 +++
> > 3 files changed, 427 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index d7797a41c648..f347d0d7b9eb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3485,6 +3485,8 @@ extern void intel_rps_mark_interactive(struct
> > drm_i915_private *i915,
> >bool interactive);
> > extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
> > bool enable);
> > +extern void intel_dsc_enable(struct intel_encoder *encoder,
> > +const struct intel_crtc_state *crtc_state);
> >
> > int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> > struct drm_file *file);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 477e53c37353..2e96e2004831 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5417,6 +5417,12 @@ static void intel_encoders_pre_enable(struct
> > drm_crtc *crtc,
> >
> > if (encoder->pre_enable)
> > encoder->pre_enable(encoder, crtc_state, conn_state);
> > +
> > + /*
> > +* Enable and Configure Display Stream Compression in the source
> > +* if enabled in intel_crtc_state.
> > +*/
> > + intel_dsc_enable(encoder, crtc_state);
>
> Didn't I ask for this to be moved into the pre_enable hook?
> We definitely don't want it here as it would be a very suprising place
> for stuff like this.
I will move it to intel_ddi_pre_enable_dp() at the end of the function.
Manasi
>
> > }
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
> > b/drivers/gpu/drm/i915/intel_vdsc.c
> > index b93cb32026fa..9f80a86f95df 100644
> > --- a/drivers/gpu/drm/i915/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> > @@ -580,3 +580,422 @@ int intel_dp_compute_dsc_params(struct intel_dp
> > *intel_dp,
> >
> > return 0;
> > }
> > +
> > +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder
> > *encoder,
> > + const struct intel_crtc_state
> > *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
> > + enum pipe pipe = crtc->pipe;
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + u32 pps_val = 0;
> > + u32 rc_buf_thresh_dword[4];
> > + u32 rc_range_params_dword[8];
> > + u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
> > + int i = 0;
> > +
> > + /* Populate PICTURE_PARAMETER_SET_0 registers */
> > + pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> > + DSC_VER_MIN_SHIFT |
> > + vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> > + vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> > + if (vdsc_cfg->block_pred_enable)
> > + pps_val |= DSC_BLOCK_PREDICTION;
> > + else
> > + pps_val &= ~DSC_BLOCK_PREDICTION;
> > + if (vdsc_cfg->convert_rgb)
> > + pps_val |= DSC_COLOR_SPACE_CONVERSION;
> > + else
> > + pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
> > + if (vdsc_cfg->enable422)
> > + pps_val |= DSC_422_ENABLE;
> > + else
> > + pps_val &= ~DSC_422_ENABLE;
> > + if (vdsc_cfg->vbr_enable)
> > + pps_val |= DSC_VBR_ENABLE;
> > + else
> > + pps_val &= ~DSC_VBR_ENABLE;
> > +
> > + DRM_INFO("PPS0 = 0x%08x\n", pps_val);
> > +if
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Reuse the aux_domain cached
== Series Details == Series: series starting with [1/4] drm/i915: Reuse the aux_domain cached URL : https://patchwork.freedesktop.org/series/51983/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5081 -> Patchwork_10717 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10717 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10717, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51983/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10717: === IGT changes === Possible regressions igt@drv_module_reload@basic-no-display: fi-icl-u2: PASS -> DMESG-WARN +2 igt@drv_module_reload@basic-reload: fi-icl-u: PASS -> DMESG-WARN +2 == Known issues == Here are the changes found in Patchwork_10717 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107859, fdo#107774, fdo#107556) igt@prime_vgem@basic-fence-flip: fi-apl-guc: PASS -> FAIL (fdo#104008) Possible fixes igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 == Participating hosts (50 -> 45) == Additional (1): fi-kbl-soraka Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u == Build changes == * Linux: CI_DRM_5081 -> Patchwork_10717 CI_DRM_5081: f5e16acf6c85d38756c3efdb77ec6aede55df0ba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4705: 7983e19ed62ec8db1884f55e07e458a62cc51e37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10717: 722af784c0a60ffb61cd71fd9fcbdba7bfcd1b48 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 722af784c0a6 drm/i915/icl: Delay hotplug processing for tc ports 9c011275643e drm/i915/icl: Only grab TC ports when using it 61201ac1c365 drm/i915: Release DDI power well references in MST ports d81abcdc9b49 drm/i915: Reuse the aux_domain cached == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10717/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/icl: Fix combo PHY uninit
On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote: > BSpec says to clear the comp init HW flag too during combo PHY > uninit, > so do that. The lack of this could badly interact with the PHY reinit > after a DC6/9 transition at least, where (after a follow-up patch > fixing > the init code) we'd skip the initialization incorrectly due to this > flag > being set. > > BSpec: 21257 > Cc: Paulo Zanoni > Cc: Ville Syrjälä > Cc: José Roberto de Souza > Cc: Rodrigo Vivi Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 6c453366cd24..a7eea8423580 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -3668,6 +3668,10 @@ void icl_display_core_uninit(struct > drm_i915_private *dev_priv) > val = I915_READ(ICL_PHY_MISC(port)); > val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > I915_WRITE(ICL_PHY_MISC(port), val); > + > + val = I915_READ(ICL_PORT_COMP_DW0(port)); > + val &= ~COMP_INIT; > + I915_WRITE(ICL_PORT_COMP_DW0(port), val); As DDIA PHY is the master maybe would be more safe clear it by last? Other than that: Reviewed-by: José Roberto de Souza > } > } > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Release DDI power well references in MST ports
On Fri, Nov 02, 2018 at 01:39:22PM -0700, José Roberto de Souza wrote:
> MST ports did not had the post_pll_disable() hook causing the
> references get in pre_pll_enable() never being released causing
> DDI and AUX CH being enabled all the times.
>
> Cc: Imre Deak
> Cc: Manasi Navare
> Signed-off-by: José Roberto de Souza
Patches 1 and 2 are
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 8b71d64ebd9d..8e3d0b04580b 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -215,6 +215,20 @@ static void intel_mst_pre_pll_enable_dp(struct
> intel_encoder *encoder,
> pipe_config, NULL);
> }
>
> +static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state
> *pipe_config,
> + const struct drm_connector_state
> *conn_state)
> +{
> + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
> + struct intel_digital_port *intel_dig_port = intel_mst->primary;
> + struct intel_dp *intel_dp = _dig_port->dp;
> +
> + if (intel_dp->active_mst_links == 0 &&
> + intel_dig_port->base.post_pll_disable)
> + intel_dig_port->base.post_pll_disable(_dig_port->base,
> + pipe_config, NULL);
> +}
> +
> static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state
> *conn_state)
> @@ -549,6 +563,7 @@ intel_dp_create_fake_mst_encoder(struct
> intel_digital_port *intel_dig_port, enum
> intel_encoder->disable = intel_mst_disable_dp;
> intel_encoder->post_disable = intel_mst_post_disable_dp;
> intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
> + intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
> intel_encoder->pre_enable = intel_mst_pre_enable_dp;
> intel_encoder->enable = intel_mst_enable_dp;
> intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> --
> 2.19.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: Reuse the aux_domain cached
== Series Details == Series: series starting with [1/4] drm/i915: Reuse the aux_domain cached URL : https://patchwork.freedesktop.org/series/51983/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Reuse the aux_domain cached Okay! Commit: drm/i915: Release DDI power well references in MST ports Okay! Commit: drm/i915/icl: Only grab TC ports when using it Okay! Commit: drm/i915/icl: Delay hotplug processing for tc ports -drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST
On Fri, Oct 26, 2018 at 06:49:08PM -0400, Lyude Paul wrote:
> Turns out that if you trigger an HPD storm on a system that has an MST
> topology connected to it, you'll end up causing the kernel to eventually
> hit a NULL deref:
>
> [ 332.339041] BUG: unable to handle kernel NULL pointer dereference at
> 00ec
> [ 332.340906] PGD 0 P4D 0
> [ 332.342750] Oops: [#1] SMP PTI
> [ 332.344579] CPU: 2 PID: 25 Comm: kworker/2:0 Kdump: loaded Tainted: G
> O 4.18.0-rc3short-hpd-storm+ #2
> [ 332.346453] Hardware name: LENOVO 20BWS1KY00/20BWS1KY00, BIOS JBET71WW
> (1.35 ) 09/14/2018
> [ 332.348361] Workqueue: events intel_hpd_irq_storm_reenable_work [i915]
> [ 332.350301] RIP: 0010:intel_hpd_irq_storm_reenable_work.cold.3+0x2f/0x86
> [i915]
> [ 332.352213] Code: 00 00 ba e8 00 00 00 48 c7 c6 c0 aa 5f a0 48 c7 c7 d0 73
> 62 a0 4c 89 c1 4c 89 04 24 e8 7f f5 af e0 4c 8b 04 24 44 89 f8 29 e8 <41> 39
> 80 ec 00 00 00 0f 85 43 13 fc ff 41 0f b6 86 b8 04 00 00 41
> [ 332.354286] RSP: 0018:c9147e48 EFLAGS: 00010006
> [ 332.356344] RAX: 0005 RBX: 8802c226c9d4 RCX:
> 0006
> [ 332.358404] RDX: RSI: 0082 RDI:
> 88032dc95570
> [ 332.360466] RBP: 0005 R08: R09:
> 88031b3dc840
> [ 332.362528] R10: R11: 00031a069602 R12:
> 8802c226ca20
> [ 332.364575] R13: 8802c2268000 R14: 880310661000 R15:
> 000a
> [ 332.366615] FS: () GS:88032dc8()
> knlGS:
> [ 332.368658] CS: 0010 DS: ES: CR0: 80050033
> [ 332.370690] CR2: 00ec CR3: 0200a003 CR4:
> 003606e0
> [ 332.372724] DR0: DR1: DR2:
>
> [ 332.374773] DR3: DR6: fffe0ff0 DR7:
> 0400
> [ 332.376798] Call Trace:
> [ 332.378809] process_one_work+0x1a1/0x350
> [ 332.380806] worker_thread+0x30/0x380
> [ 332.382777] ? wq_update_unbound_numa+0x10/0x10
> [ 332.384772] kthread+0x112/0x130
> [ 332.386740] ? kthread_create_worker_on_cpu+0x70/0x70
> [ 332.388706] ret_from_fork+0x35/0x40
> [ 332.390651] Modules linked in: i915(O) vfat fat joydev btusb btrtl btbcm
> btintel bluetooth ecdh_generic iTCO_wdt wmi_bmof i2c_algo_bit drm_kms_helper
> intel_rapl syscopyarea sysfillrect x86_pkg_temp_thermal sysimgblt coretemp
> fb_sys_fops crc32_pclmul drm psmouse pcspkr mei_me mei i2c_i801 lpc_ich
> mfd_core i2c_core tpm_tis tpm_tis_core thinkpad_acpi wmi tpm rfkill video
> crc32c_intel serio_raw ehci_pci xhci_pci ehci_hcd xhci_hcd [last unloaded:
> i915]
> [ 332.394963] CR2: 00ec
>
> This appears to be due to the fact that with an MST topology, not all
> intel_connector structs will have ->encoder set. So, fix this by
> skipping connectors without encoders in
> intel_hpd_irq_storm_reenable_work().
>
> For those wondering, this bug was found on accident while simulating HPD
> storms using a Chamelium connected to a ThinkPad T450s (Broadwell).
>
> Changes since v1:
> - Check intel_connector->mst_port instead of intel_connector->encoder
>
> Signed-off-by: Lyude Paul
> Cc: Ville Syrjälä
1 and 2 are
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_hotplug.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
> b/drivers/gpu/drm/i915/intel_hotplug.c
> index 648a13c6043c..8326900a311e 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -228,7 +228,9 @@ static void intel_hpd_irq_storm_reenable_work(struct
> work_struct *work)
> drm_for_each_connector_iter(connector, _iter) {
> struct intel_connector *intel_connector =
> to_intel_connector(connector);
>
> - if (intel_connector->encoder->hpd_pin == pin) {
> + /* Don't check MST ports, they don't have pins */
> + if (!intel_connector->mst_port &&
> + intel_connector->encoder->hpd_pin == pin) {
> if (connector->polled !=
> intel_connector->polled)
> DRM_DEBUG_DRIVER("Reenabling HPD on
> connector %s\n",
>connector->name);
> --
> 2.17.2
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH 4/4] drm/i915/icl: Delay hotplug processing for tc ports
Some USB type-C dongles requires some time to power on before being
able to process aux channel transactions.
It was not a problem for older gens because there was a bridge
between DP port and USB-C controller adding some delay but ICL
handles type-C native.
So here trying to do a aux channel transaction at each 150ms for up 5
times, before giving up.
Cc: Paulo Zanoni
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 7 +++
drivers/gpu/drm/i915/intel_drv.h | 6 ++-
drivers/gpu/drm/i915/intel_hotplug.c | 76
4 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2a88a7eb871b..b81f8b55750e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2789,6 +2789,7 @@ enum hpd_pin intel_hpd_pin_default(struct
drm_i915_private *dev_priv,
enum port port);
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
+void intel_hotplug_tc_wa_work(struct work_struct *__work);
/* i915_irq.c */
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d978127e7208..2042711887f1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5379,6 +5379,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
{
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
struct intel_dp *intel_dp = _dig_port->dp;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_dp_mst_encoder_cleanup(intel_dig_port);
if (intel_dp_is_edp(intel_dp)) {
@@ -5395,6 +5396,8 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
unregister_reboot_notifier(_dp->edp_notifier);
intel_dp->edp_notifier.notifier_call = NULL;
}
+ } else if (IS_ICELAKE(dev_priv)) {
+ cancel_delayed_work_sync(_dp->tc_wa_work);
}
intel_dp_aux_fini(intel_dp);
@@ -6758,6 +6761,10 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}
+ if (IS_ICELAKE(dev_priv) && !intel_dp_is_edp(intel_dp))
+ INIT_DELAYED_WORK(_dp->tc_wa_work,
+ intel_hotplug_tc_wa_work);
+
return true;
fail:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 191c26e17f2d..06d282e4ecb7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1137,7 +1137,11 @@ struct intel_dp {
int panel_power_cycle_delay;
int backlight_on_delay;
int backlight_off_delay;
- struct delayed_work panel_vdd_work;
+ union {
+ struct delayed_work panel_vdd_work;
+ struct delayed_work tc_wa_work;
+ };
+ u8 tc_wa_count;
bool want_panel_vdd;
unsigned long last_power_on;
unsigned long last_backlight_off;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
b/drivers/gpu/drm/i915/intel_hotplug.c
index 648a13c6043c..d4094db1a3c3 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -323,6 +323,64 @@ static void i915_digport_work_func(struct work_struct
*work)
}
}
+#define TC_WA_DELAY_MSEC 150
+#define TC_WA_TRIES 5
+
+/*
+ * Test if TC dongle is responsive return true if so otherwise schedule a
+ * work to try again and return false
+ */
+static bool intel_hotplug_tc_wa_test(struct intel_dp *intel_dp)
+{
+ u8 buff;
+
+ intel_dp->tc_wa_count++;
+
+ if (drm_dp_dpcd_read(_dp->aux, DP_DPCD_REV, , 1) != 1)
+ goto not_responsive;
+
+ if (!drm_probe_ddc(_dp->aux.ddc))
+ goto not_responsive;
+
+ return true;
+
+not_responsive:
+ if (intel_dp->tc_wa_count < TC_WA_TRIES) {
+ unsigned long delay;
+
+ delay = msecs_to_jiffies(TC_WA_DELAY_MSEC);
+ schedule_delayed_work(_dp->tc_wa_work, delay);
+ } else {
+ DRM_DEBUG_KMS("TC not responsive, giving up\n");
+ }
+
+ return false;
+}
+
+void intel_hotplug_tc_wa_work(struct work_struct *__work)
+{
+ struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
+struct intel_dp, tc_wa_work);
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *intel_encoder = _dig_port->base;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
[Intel-gfx] [PATCH 3/4] drm/i915/icl: Only grab TC ports when using it
When suspending or unloading the driver, it needs to release the
TC ports so HW can change it state without wait for driver handshake.
Spec also state that if the port is not used by driver it should
release TC access, so here only grabbing control of the TC ports and
marking as unsafe when aux power is needed as have aux power well is
a requirement to have DDI enabled in TC ports, the pre_pll_enable and
post_pll_disable hooks takes care of getting and releasing it.
BSpec: 21750
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 28 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 55 -
2 files changed, 54 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52a54ef746af..d978127e7208 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5013,16 +5013,6 @@ static bool icl_tc_phy_connect(struct drm_i915_private
*dev_priv,
return false;
}
- /*
-* This function may be called many times in a row without an HPD event
-* in between, so try to avoid the write when we can.
-*/
- val = I915_READ(PORT_TX_DFLEXDPCSSS);
- if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
- val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
- I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
- }
-
/*
* Now we have to re-check the live state, in case the port recently
* became disconnected. Not necessary for legacy mode.
@@ -5044,24 +5034,6 @@ static bool icl_tc_phy_connect(struct drm_i915_private
*dev_priv,
static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
struct intel_digital_port *dig_port)
{
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
-
- if (dig_port->tc_type == TC_PORT_UNKNOWN)
- return;
-
- /*
-* TBT disconnection flow is read the live status, what was done in
-* caller.
-*/
- if (dig_port->tc_type == TC_PORT_TYPEC ||
- dig_port->tc_type == TC_PORT_LEGACY) {
- u32 val;
-
- val = I915_READ(PORT_TX_DFLEXDPCSSS);
- val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
- I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
- }
-
dig_port->tc_type = TC_PORT_UNKNOWN;
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c453366cd24..dab5f90646c4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -465,6 +465,48 @@ icl_combo_phy_aux_power_well_disable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
+static void icl_tc_grab_control(struct drm_i915_private *dev_priv,
+ enum aux_ch aux_ch, bool grab)
+{
+ struct drm_device *dev = _priv->drm;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_connector *connector;
+
+ drm_connector_list_iter_begin(dev, _iter);
+ drm_for_each_connector_iter(connector, _iter) {
+ struct intel_connector *intel_connector;
+ struct intel_encoder *intel_encoder;
+ struct intel_digital_port *dig_port;
+ enum tc_port tc_port;
+
+ intel_connector = to_intel_connector(connector);
+ if (!intel_connector->encoder)
+ continue;
+ intel_encoder = intel_connector->encoder;
+ dig_port = enc_to_dig_port(_encoder->base);
+
+ if (!dig_port || dig_port->aux_ch != aux_ch)
+ continue;
+
+ tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+
+ if (dig_port->tc_type == TC_PORT_TYPEC ||
+ dig_port->tc_type == TC_PORT_LEGACY) {
+ u32 val;
+
+ val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ if (grab)
+ val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
+ else
+ val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
+ I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
+ }
+
+ break;
+ }
+ drm_connector_list_iter_end(_iter);
+}
+
#define ICL_AUX_PW_TO_CH(pw_idx) \
((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
@@ -475,6 +517,8 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(power_well->desc->hsw.idx);
u32 val;
+ icl_tc_grab_control(dev_priv, aux_ch, true);
+
val = I915_READ(DP_AUX_CH_CTL(aux_ch));
val &= ~DP_AUX_CH_CTL_TBT_IO;
if (power_well->desc->hsw.is_tc_tbt)
@@ -484,6 +528,15 @@
[Intel-gfx] [PATCH 1/4] drm/i915: Reuse the aux_domain cached
intel_dp_detect() caches the aux_domain in the beginning of the
function as it is used twice, so lets also use it as the aux_domain
don't change in runtime.
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e7233dfa1794..52a54ef746af 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5289,8 +5289,7 @@ intel_dp_detect(struct drm_connector *connector,
ret = intel_dp_retrain_link(encoder, ctx);
if (ret) {
- intel_display_power_put(dev_priv,
-
intel_aux_power_domain(dig_port));
+ intel_display_power_put(dev_priv, aux_domain);
return ret;
}
}
--
2.19.1
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[Intel-gfx] [PATCH 2/4] drm/i915: Release DDI power well references in MST ports
MST ports did not had the post_pll_disable() hook causing the
references get in pre_pll_enable() never being released causing
DDI and AUX CH being enabled all the times.
Cc: Imre Deak
Cc: Manasi Navare
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp_mst.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 8b71d64ebd9d..8e3d0b04580b 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -215,6 +215,20 @@ static void intel_mst_pre_pll_enable_dp(struct
intel_encoder *encoder,
pipe_config, NULL);
}
+static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*pipe_config,
+ const struct drm_connector_state
*conn_state)
+{
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
+ struct intel_digital_port *intel_dig_port = intel_mst->primary;
+ struct intel_dp *intel_dp = _dig_port->dp;
+
+ if (intel_dp->active_mst_links == 0 &&
+ intel_dig_port->base.post_pll_disable)
+ intel_dig_port->base.post_pll_disable(_dig_port->base,
+ pipe_config, NULL);
+}
+
static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state
*conn_state)
@@ -549,6 +563,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port
*intel_dig_port, enum
intel_encoder->disable = intel_mst_disable_dp;
intel_encoder->post_disable = intel_mst_post_disable_dp;
intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
+ intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
intel_encoder->pre_enable = intel_mst_pre_enable_dp;
intel_encoder->enable = intel_mst_enable_dp;
intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
--
2.19.1
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Re: [Intel-gfx] [PATCH v7 07/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled
On Fri, Nov 02, 2018 at 07:51:18PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:46:47PM -0700, Manasi Navare wrote:
> > If a eDP panel supports both PSR2 and VDSC, our HW cannot
> > support both at a time. Give priority to PSR2 if a requested
> > resolution can be supported without compression else enable
> > VDSC and keep PSR2 disabled.
> >
> > v3:
> > * Rebase
> > v2:
> > * Add warning for DSC and PSR2 enabled together (DK)
> >
> > Cc: Rodrigo Vivi
> > Cc: Jani Nikula
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 16 +---
> > 1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index bc2d88313ed0..8f063e1e2fb2 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -71,9 +71,9 @@ static bool psr_global_enabled(u32 debug)
> > static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> >const struct intel_crtc_state *crtc_state)
> > {
> > - /* Disable PSR2 by default for all platforms */
> > - if (i915_modparams.enable_psr == -1)
> > - return false;
>
> That seems unrelated to DSC?
Thats a good catch, i think thsi got removed due to a rebase by mistake.
I will add it back there.
Manasi
>
> > + /* Cannot enable DSC and PSR2 simultaneously */
> > + WARN_ON(crtc_state->dsc_params.compression_enable &&
> > + crtc_state->has_psr2);
> >
> > switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > case I915_PSR_DEBUG_FORCE_PSR1:
> > @@ -463,6 +463,16 @@ static bool intel_psr2_config_valid(struct intel_dp
> > *intel_dp,
> > if (!dev_priv->psr.sink_psr2_support)
> > return false;
> >
> > + /*
> > +* DSC and PSR2 cannot be enabled simultaneously. If a requested
> > +* resolution requires DSC to be enabled, priority is given to DSC
> > +* over PSR2.
> > +*/
> > + if (crtc_state->dsc_params.compression_enable) {
> > + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
> > + return false;
> > + }
> > +
> > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> > psr_max_h = 4096;
> > psr_max_v = 2304;
> > --
> > 2.18.0
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix suspend/resume for TypeC HDMI
== Series Details == Series: drm/i915/icl: Fix suspend/resume for TypeC HDMI URL : https://patchwork.freedesktop.org/series/51976/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5081 -> Patchwork_10716 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51976/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10716 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_cpu_reloc@basic: fi-kbl-7560u: INCOMPLETE (fdo#103665) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (50 -> 44) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5081 -> Patchwork_10716 CI_DRM_5081: f5e16acf6c85d38756c3efdb77ec6aede55df0ba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4705: 7983e19ed62ec8db1884f55e07e458a62cc51e37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10716: 5862e7326db031964c0da64846806ee65b6e672d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5862e7326db0 drm/i915/icl: Configure MG DP mode for HDMI ports too 5587a135f248 drm/i915/icl: Configure MG PHY gating for HDMI ports too == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10716/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/icl: Fix suspend/resume for TypeC HDMI
== Series Details == Series: drm/i915/icl: Fix suspend/resume for TypeC HDMI URL : https://patchwork.freedesktop.org/series/51976/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/icl: Configure MG PHY gating for HDMI ports too Okay! Commit: drm/i915/icl: Configure MG DP mode for HDMI ports too +drivers/gpu/drm/i915/intel_dp.c:365:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:365:28: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_dp.c:365:28: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_dp.c:365:28: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 00/19] DSC enabling remaining patches
Thanks Ville for this detailed review. I will spin this now with the required fixes and send it over. Manasi On Fri, Nov 02, 2018 at 08:06:04PM +0200, Ville Syrjälä wrote: > On Thu, Nov 01, 2018 at 11:46:40PM -0700, Manasi Navare wrote: > > This patch series addresses review comments on previous DSC series: > > > > https://patchwork.freedesktop.org/series/47514/ > > > > Gaurav K Singh (3): > > drm/i915/dsc: Define & Compute VESA DSC params > > drm/i915/dsc: Compute Rate Control parameters for DSC > > drm/i915/dp: Enable/Disable DSC in DP Sink > > > > Manasi Navare (15): > > drm/dsc: Define Display Stream Compression PPS infoframe > > drm/dsc: Define VESA Display Stream Compression Capabilities > > drm/dsc: Add helpers for DSC picture parameter set infoframes > > drm/i915/dp: Add DSC params and DSC config to intel_crtc_state > > drm/i915/dp: Compute DSC pipe config in atomic check > > drm/i915/dp: Do not enable PSR2 if DSC is enabled > > drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants > > drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI > > drm/i915/dp: Configure i915 Picture parameter Set registers during DSC > > enabling > > drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs > > drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes > > drm/i915/dp: Configure Display stream splitter registers during DSC > > enable > > drm/i915/dp: Disable DSC in source by disabling DSS CTL bits > > drm/i915/dsc: Enable and disable appropriate power wells for VDSC > > drm/i915/dsc: Add Per connector debugfs node for DSC support/enable > > > > Srivatsa, Anusha (1): > > drm/dsc: Define Rate Control values that do not change over > > configurations > > I think we have these real functional issues left: > - no FEC so should reject DSC on external DP > - get_power_domains() thing wasn't right > > The potentially user triggerable DRM_ERROR()s have to be > removed or explained why they can't happen (in which case > a WARN() would probably be a more clear hint to the reader). > > The intel_dsc_enable() call I definitely would like see > moved into the encoder->per_enable(). No one will think to > look for it in the current location. > > The i915_modparams.enable_psr change seemed unrelated, but > no idea if it's intentional or not. > > And finally there were various style nits that are optional. > But I would recomment doing them since it's trivial stuff and > avoids further churn in the code later. > > I think that's about it really. > > > > > Documentation/gpu/drm-kms-helpers.rst | 12 + > > drivers/gpu/drm/Makefile|2 +- > > drivers/gpu/drm/drm_dsc.c | 228 + > > drivers/gpu/drm/i915/Makefile |3 +- > > drivers/gpu/drm/i915/i915_debugfs.c | 71 +- > > drivers/gpu/drm/i915/i915_drv.h |4 + > > drivers/gpu/drm/i915/i915_reg.h |1 + > > drivers/gpu/drm/i915/intel_ddi.c|8 +- > > drivers/gpu/drm/i915/intel_display.c| 28 +- > > drivers/gpu/drm/i915/intel_display.h|4 +- > > drivers/gpu/drm/i915/intel_dp.c | 196 +++- > > drivers/gpu/drm/i915/intel_dp_mst.c |2 +- > > drivers/gpu/drm/i915/intel_drv.h| 21 + > > drivers/gpu/drm/i915/intel_hdmi.c | 21 +- > > drivers/gpu/drm/i915/intel_psr.c| 16 +- > > drivers/gpu/drm/i915/intel_runtime_pm.c |4 +- > > drivers/gpu/drm/i915/intel_vdsc.c | 1100 +++ > > include/drm/drm_dp_helper.h |3 + > > include/drm/drm_dsc.h | 485 ++ > > 19 files changed, 2169 insertions(+), 40 deletions(-) > > create mode 100644 drivers/gpu/drm/drm_dsc.c > > create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c > > create mode 100644 include/drm/drm_dsc.h > > > > -- > > 2.18.0 > > > > ___ > > dri-devel mailing list > > dri-de...@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- > Ville Syrjälä > Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: merge gen checks to use range
On Fri, Nov 02, 2018 at 12:19:13PM -0700, Rodrigo Vivi wrote:
> On Fri, Nov 02, 2018 at 11:10:10AM -0700, Lucas De Marchi wrote:
> > On Thu, Nov 01, 2018 at 11:31:25AM +, Tvrtko Ursulin wrote:
> > >
> > > On 01/11/2018 08:35, Lucas De Marchi wrote:
> > > > Instead of using several IS_GEN(), it's possible to pass the
> > > > range as argument. By code inspection these were the ranges deemed
> > > > necessary for spatch:
> > > >
> > > > @@
> > > > expression e;
> > > > @@
> > > > (
> > > > - IS_GEN(e, 3) || IS_GEN(e, 4)
> > > > + IS_GEN(e, 3, 4)
> > > > |
> > > > - IS_GEN(e, 5) || IS_GEN(e, 6)
> > > > + IS_GEN(e, 5, 6)
> > > > |
> > > > - IS_GEN(e, 6) || IS_GEN(e, 7)
> > > > + IS_GEN(e, 6, 7)
> > > > |
> > > > - IS_GEN(e, 7) || IS_GEN(e, 8)
> > > > + IS_GEN(e, 7, 8)
> > > > |
> > > > - IS_GEN(e, 8) || IS_GEN(e, 9)
> > > > + IS_GEN(e, 8, 9)
> > > > |
> > > > - IS_GEN(e, 10) || IS_GEN(e, 9)
> > > > + IS_GEN(e, 9, 10)
> > > > |
> > > > - IS_GEN(e, 9) || IS_GEN(e, 10)
> > > > + IS_GEN(e, 9, 10)
> > > > )
> > > >
> > > > Signed-off-by: Lucas De Marchi
> > > > ---
> > > > drivers/gpu/drm/i915/i915_debugfs.c| 6 +++---
> > > > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> > > > drivers/gpu/drm/i915/i915_perf.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_crt.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++--
> > > > drivers/gpu/drm/i915/intel_uncore.c| 6 +++---
> > > > 10 files changed, 15 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index 28d95f9d0b0e..f2fbc016bd7f 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m,
> > > > void *data)
> > > > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> > > >swizzle_string(dev_priv->mm.bit_6_swizzle_y));
> > > > - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
> > > > + if (IS_GEN(dev_priv, 3, 4)) {
> > >
> > > I can see value in it but think it would read better with IS_GEN_RANGE.
> >
> > Ok, it seems there's a rough consensus of s/IS_GEN/IS_GEN_RANGE/ an then
> > bring the patches that make sense here. There was a recent patch from
> > Rodrigo
> > doing that. I'll include it in next version.
>
> I liked the double args idea but after reading I believe
> it gets clear IS_GEN_RANGE.
>
> >
> > >
> > > Are there any cases of or-ed IS_GEN checks with something sandwiched in
> > > between then, which the above spatch would miss?
> >
> > By manually inspecting the result of ``git grep -ne "IS_GEN(.*" --
> > drivers/gpu/drm/i915/``
> > I didn't find any. The only thing I found was a missed case for gen3 || gen2
> > that was not covered by the spatch.
> >
> > >
> > > How many non-consecutive IS_GEN gen checks are there? To give us some
> > > ideas
> > > if the usual pattern is range, or perhaps checks against a list of gens
> > > also
> > > exists? (Gut feeling says no.)
> >
> > only cases of <=, <, >=, >.
>
> For these cases on patches 4 and 5::
>
> What about converting all < n to <= n-1 and all > n to >= n + 1
> get FORVER back and introduce IS_GEN_UNTIL ?
>
> IS_GEN_UNTIL(dev_priv, e)
> IS_GEN_RANGE(dev_priv, s, FOREVER)
>
> so we can also kill INTEL_GEN.
>
> Another different idea on top of that.
>
> What about removing all "IS_"?
>
> so end result could be something like that:
>
> INTEL_GEN(dev_priv, n)
> DISPLAY_GEN(dev_priv, n)
> INTEL_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> DISPLAY_GEN_RANGE(dev_priv, s, e) #or e = FOREVER
> INTEL_GEN_UNTIL(dev_priv, e)
> DISPLAY_GEN_UNTIL(dev_priv, e)
>
> (maybe s/INTEL/GT)
I like it. I'm just not sure about UNTIL, because I will always have doubts if
it's inclusive or not. But I guess we have the same today with RANGE and we
just get used to it. By making all of them inclusive, it will be easier.
Anyway, my preference is:
GT_GEN(dev_priv, n)
GT_GEN_RANGE(dev_priv, s, e)
and e can be GEN_FOREVER, aka -1. The macro has enough knowledge to work out
the mask, e.g. s == 10, e == FOREVER => mask == ~(BIT(s) | (BIT(s) - 1))
And the DISPLAY_GEN* counterparts.
IMO there's no need to have _UNTIL because it can also be expressed as
GT_GEN_RANGE(dev_priv, GEN_FOREVER, 10).
This way we can also kill the comparisons INTEL_GEN(dev_priv) == x, so we always
work with the gen_mask field. Which means the compiler can do a single
comparison
(/me hoping it actually generates good code)
There are corner cases though:
What should we do with e.g. IS_GEN9_LP() and friends?
Any conversion like these will create a lot of
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
== Series Details == Series: drm/i915/icl: Fix power well 2 wrt. DC-off toggling order URL : https://patchwork.freedesktop.org/series/51971/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5081 -> Patchwork_10715 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51971/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10715 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107859, fdo#107556, fdo#107774) fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) Possible fixes igt@gem_cpu_reloc@basic: fi-kbl-7560u: INCOMPLETE (fdo#103665) -> PASS fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 == Participating hosts (50 -> 46) == Additional (1): fi-kbl-soraka Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5081 -> Patchwork_10715 CI_DRM_5081: f5e16acf6c85d38756c3efdb77ec6aede55df0ba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4705: 7983e19ed62ec8db1884f55e07e458a62cc51e37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10715: ece6e91bbcf0dc689304f528f4cba383c6d9daf9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ece6e91bbcf0 drm/i915/icl: Fix power well 2 wrt. DC-off toggling order == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10715/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
