[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Get pipe id following atomic guidelines
== Series Details == Series: drm/i915/psr: Get pipe id following atomic guidelines URL : https://patchwork.freedesktop.org/series/53132/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Get pipe id following atomic guidelines -drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/psr: Get pipe id following atomic guidelines
As stated in struct drm_encoder, crtc field should only be used
by non-atomic drivers.
So here caching the pipe id in intel_psr_enable() what is way more
simple and efficient than at every call to
intel_psr_flush()/invalidate() get the
drm.mode_config.connection_mutex lock to safely be able to get the
pipe id by reading drm_connector_state.crtc.
This should fix the null pointer dereference crash below as the
previous way to get the pipe id was prone to race conditions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105959
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 19 ---
2 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f763b30f98d9..9ea39b82836f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -494,6 +494,7 @@ struct i915_psr {
bool sink_support;
bool prepared, enabled;
struct intel_dp *dp;
+ enum pipe pipe;
bool active;
struct work_struct work;
unsigned busy_frontbuffer_bits;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 572e626eadff..11a520074f06 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -705,6 +705,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.prepared = true;
+ dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
if (psr_global_enabled(dev_priv->psr.debug))
intel_psr_enable_locked(dev_priv, crtc_state);
@@ -1012,9 +1013,6 @@ static void intel_psr_work(struct work_struct *work)
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits, enum fb_op_origin origin)
{
- struct drm_crtc *crtc;
- enum pipe pipe;
-
if (!CAN_PSR(dev_priv))
return;
@@ -1027,10 +1025,7 @@ void intel_psr_invalidate(struct drm_i915_private
*dev_priv,
return;
}
- crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
- pipe = to_intel_crtc(crtc)->pipe;
-
- frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
+ frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
if (frontbuffer_bits)
@@ -1055,9 +1050,6 @@ void intel_psr_invalidate(struct drm_i915_private
*dev_priv,
void intel_psr_flush(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits, enum fb_op_origin origin)
{
- struct drm_crtc *crtc;
- enum pipe pipe;
-
if (!CAN_PSR(dev_priv))
return;
@@ -1070,10 +1062,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
return;
}
- crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
- pipe = to_intel_crtc(crtc)->pipe;
-
- frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
+ frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
/* By definition flush = invalidate + flush */
@@ -1087,7 +1076,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
* but it makes more sense write to the current active
* pipe.
*/
- I915_WRITE(CURSURFLIVE(pipe), 0);
+ I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
}
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 12/35] drm/i915: Implement the HDCP2.2 support for DP
On 11/28/2018 10:56 AM, Stéphane Marchesin wrote:
Hi,
Just a drive-by comment, but did you check that this fails gracefully
on platforms which don't enable the ME? For example Chrome OS :)
That is taken care :) HDCP2.2 is attempted only if platform enables the
ME and its required kernel drivers.
--Ram
Stéphane
On Tue, Nov 27, 2018 at 2:48 AM Ramalingam C wrote:
Implements the DP adaptation specific HDCP2.2 functions.
These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.
v2:
wait for cp_irq is merged with this patch. Rebased.
v3:
wait_queue is used for wait for cp_irq [Chris Wilson]
v4:
Style fixed.
%s/PARING/PAIRING
Few style fixes [Uma]
v5:
Lookup table for DP HDCP2.2 msg details [Daniel].
Extra lines are removed.
v6:
Rebased.
v7:
Fixed some regression introduced at v5. [Ankit]
Macro HDCP_2_2_RX_CAPS_VERSION_VAL is reused [Uma]
Converted a function to inline [Uma]
%s/uintxx_t/uxx
v8:
Error due to the sinks are reported as DEBUG logs.
Adjust to the new mei interface.
Signed-off-by: Ramalingam C
Signed-off-by: Ankit K Nautiyal
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dp.c | 338 ++
drivers/gpu/drm/i915/intel_drv.h | 7 +
drivers/gpu/drm/i915/intel_hdcp.c | 6 +
3 files changed, 351 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ecc4706db7dc..1cc82e490999 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -5347,6 +5348,27 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
pps_unlock(intel_dp);
}
+static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
+int timeout)
+{
+ long ret;
+
+ /* Reinit */
+ atomic_set(>cp_irq_recved, 0);
+
+#define C (atomic_read(>cp_irq_recved) > 0)
+ ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
+ msecs_to_jiffies(timeout));
+
+ if (ret > 0) {
+ atomic_set(>cp_irq_recved, 0);
+ return 0;
+ } else if (!ret) {
+ return -ETIMEDOUT;
+ }
+ return (int)ret;
+}
+
static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
u8 *an)
@@ -5570,6 +5592,316 @@ int intel_dp_hdcp_capable(struct intel_digital_port
*intel_dig_port,
return 0;
}
+static struct hdcp2_dp_msg_data {
+ u8 msg_id;
+ u32 offset;
+ bool msg_detectable;
+ u32 timeout;
+ u32 timeout2; /* Added for non_paired situation */
+ } hdcp2_msg_data[] = {
+ {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0},
+ {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
+ false, HDCP_2_2_CERT_TIMEOUT_MS, 0},
+ {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
+ false, 0, 0},
+ {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
+ false, 0, 0},
+ {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
+ true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
+ HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
+ {HDCP_2_2_AKE_SEND_PAIRING_INFO,
+ DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
+ HDCP_2_2_PAIRING_TIMEOUT_MS, 0},
+ {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0},
+ {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
+ false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0},
+ {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
+ 0, 0},
+ {HDCP_2_2_REP_SEND_RECVID_LIST,
+ DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
+ HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
+ {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
+ 0, 0},
+ {HDCP_2_2_REP_STREAM_MANAGE,
+ DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
+ 0, 0},
+ {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
+ false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0},
+ {HDCP_2_2_ERRATA_DP_STREAM_TYPE,
+ DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
+ 0, 0},
+ };
+
+static inline
+int intel_dp_hdcp2_read_rx_status(struct
Re: [Intel-gfx] [PATCH] drm/fbdev: Make skip_vt_switch the default
Op 27-11-18 om 18:34 schreef Daniel Vetter: > KMS drivers really should all be able to restore their display state > on resume without fbcon helping out. So make this the default. > > Since I'm not entirely foolish, make it only a default, which drivers > can still override. That way when the inevitable regression report > happens I can fix things up with a one-liner plus FIXME comment that > someone should fix up the suspend/resume code in that driver. > > But at least all new drivers won't be broken by accident as soon as > you turn off fbcon because "suspend/resume worked when I tested it". > > v2: Keep this for radeon because of > > commit 18c437caa5b18a235dd65cec224eab54bebcee65 > Author: Alex Deucher > Date: Tue Nov 14 17:19:29 2017 -0500 > > Revert "drm/radeon: dont switch vt on suspend" > > Thanks to Michel Dänzer for pointing this one out. Maybe just reload the gamma lut on resume for radeon, instead of relying on fbcon? Otherwise patch looks sane, would be nice if radeon was fixed instead of worked around. Reviewed-by: Maarten Lankhorst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix TV encoder support (rev5)
== Series Details ==
Series: drm/i915: Fix TV encoder support (rev5)
URL : https://patchwork.freedesktop.org/series/52378/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10920_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10920_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10920_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10920_full:
=== IGT changes ===
Warnings
igt@kms_chv_cursor_fail@pipe-b-64x64-top-edge:
shard-snb: SKIP -> PASS +1
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10920_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@debugfs_test@read_all_entries_display_off:
shard-skl: PASS -> INCOMPLETE ([fdo#104108])
igt@gem_exec_schedule@pi-ringfull-blt:
shard-skl: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_schedule@pi-ringfull-vebox:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_suspend@basic-s3:
shard-kbl: PASS -> INCOMPLETE ([fdo#103665])
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: PASS -> TIMEOUT ([fdo#108039])
igt@i915_suspend@shrink:
shard-skl: NOTRUN -> INCOMPLETE ([fdo#106886])
igt@kms_atomic_transition@1x-modeset-transitions-fencing:
shard-kbl: PASS -> DMESG-WARN ([fdo#103313], [fdo#105345])
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: PASS -> FAIL ([fdo#106641])
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
shard-skl: NOTRUN -> DMESG-WARN ([fdo#107956])
igt@kms_chv_cursor_fail@pipe-c-128x128-right-edge:
shard-skl: NOTRUN -> FAIL ([fdo#104671])
igt@kms_cursor_crc@cursor-256x85-onscreen:
shard-apl: PASS -> FAIL ([fdo#103232]) +3
igt@kms_cursor_crc@cursor-64x21-random:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103232])
igt@kms_flip@dpms-vs-vblank-race:
shard-apl: PASS -> FAIL ([fdo#103060])
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-apl: PASS -> FAIL ([fdo#103167]) +3
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
shard-glk: PASS -> FAIL ([fdo#103167])
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
{shard-iclb}: PASS -> FAIL ([fdo#103167])
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
shard-skl: NOTRUN -> FAIL ([fdo#103167]) +2
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL ([fdo#108145]) +1
igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
shard-skl: NOTRUN -> FAIL ([fdo#107815])
igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
shard-glk: PASS -> FAIL ([fdo#103166])
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-apl: PASS -> FAIL ([fdo#103166]) +3
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
{shard-iclb}: PASS -> FAIL ([fdo#103166])
igt@pm_rpm@reg-read-ioctl:
{shard-iclb}: PASS -> DMESG-WARN ([fdo#108654]) +1
igt@pm_rpm@sysfs-read:
{shard-iclb}: PASS -> INCOMPLETE ([fdo#107713], [fdo#108840])
Possible fixes
igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
shard-skl: FAIL ([fdo#104671]) -> PASS
igt@kms_color@pipe-a-legacy-gamma:
shard-skl: FAIL ([fdo#104782], [fdo#108145]) -> PASS
igt@kms_cursor_crc@cursor-64x64-dpms:
shard-apl: FAIL ([fdo#103232]) -> PASS +1
igt@kms_cursor_crc@cursor-64x64-offscreen:
shard-skl: FAIL ([fdo#103232]) -> PASS +1
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN ([fdo#105763], [fdo#106538]) -> PASS
igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
shard-glk: FAIL ([fdo#103184]) -> PASS
igt@kms_flip@flip-vs-expired-vblank:
shard-skl: FAIL ([fdo#105363]) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-apl: FAIL ([fdo#102887], [fdo#105363]) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
{shard-iclb}: FAIL ([fdo#103167]) -> PASS +7
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
shard-skl: FAIL ([fdo#105682]) -> PASS
igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt:
shard-skl:
Re: [Intel-gfx] [PATCH v8 12/35] drm/i915: Implement the HDCP2.2 support for DP
Hi,
Just a drive-by comment, but did you check that this fails gracefully
on platforms which don't enable the ME? For example Chrome OS :)
Stéphane
On Tue, Nov 27, 2018 at 2:48 AM Ramalingam C wrote:
>
> Implements the DP adaptation specific HDCP2.2 functions.
>
> These functions perform the DPCD read and write for communicating the
> HDCP2.2 auth message back and forth.
>
> v2:
> wait for cp_irq is merged with this patch. Rebased.
> v3:
> wait_queue is used for wait for cp_irq [Chris Wilson]
> v4:
> Style fixed.
> %s/PARING/PAIRING
> Few style fixes [Uma]
> v5:
> Lookup table for DP HDCP2.2 msg details [Daniel].
> Extra lines are removed.
> v6:
> Rebased.
> v7:
> Fixed some regression introduced at v5. [Ankit]
> Macro HDCP_2_2_RX_CAPS_VERSION_VAL is reused [Uma]
> Converted a function to inline [Uma]
> %s/uintxx_t/uxx
> v8:
> Error due to the sinks are reported as DEBUG logs.
> Adjust to the new mei interface.
>
> Signed-off-by: Ramalingam C
> Signed-off-by: Ankit K Nautiyal
> Reviewed-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_dp.c | 338
> ++
> drivers/gpu/drm/i915/intel_drv.h | 7 +
> drivers/gpu/drm/i915/intel_hdcp.c | 6 +
> 3 files changed, 351 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ecc4706db7dc..1cc82e490999 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -31,6 +31,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -5347,6 +5348,27 @@ void intel_dp_encoder_suspend(struct intel_encoder
> *intel_encoder)
> pps_unlock(intel_dp);
> }
>
> +static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
> +int timeout)
> +{
> + long ret;
> +
> + /* Reinit */
> + atomic_set(>cp_irq_recved, 0);
> +
> +#define C (atomic_read(>cp_irq_recved) > 0)
> + ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
> + msecs_to_jiffies(timeout));
> +
> + if (ret > 0) {
> + atomic_set(>cp_irq_recved, 0);
> + return 0;
> + } else if (!ret) {
> + return -ETIMEDOUT;
> + }
> + return (int)ret;
> +}
> +
> static
> int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
> u8 *an)
> @@ -5570,6 +5592,316 @@ int intel_dp_hdcp_capable(struct intel_digital_port
> *intel_dig_port,
> return 0;
> }
>
> +static struct hdcp2_dp_msg_data {
> + u8 msg_id;
> + u32 offset;
> + bool msg_detectable;
> + u32 timeout;
> + u32 timeout2; /* Added for non_paired situation */
> + } hdcp2_msg_data[] = {
> + {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0},
> + {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
> + false, HDCP_2_2_CERT_TIMEOUT_MS, 0},
> + {HDCP_2_2_AKE_NO_STORED_KM,
> DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
> + false, 0, 0},
> + {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
> + false, 0, 0},
> + {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
> + true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
> + HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
> + {HDCP_2_2_AKE_SEND_PAIRING_INFO,
> + DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET,
> true,
> + HDCP_2_2_PAIRING_TIMEOUT_MS, 0},
> + {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0},
> + {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
> + false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0},
> + {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET,
> false,
> + 0, 0},
> + {HDCP_2_2_REP_SEND_RECVID_LIST,
> + DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
> + HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
> + {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET,
> false,
> + 0, 0},
> + {HDCP_2_2_REP_STREAM_MANAGE,
> + DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
> + 0, 0},
> + {HDCP_2_2_REP_STREAM_READY,
> DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
> + false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0},
> + {HDCP_2_2_ERRATA_DP_STREAM_TYPE,
> + DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
> + 0, 0},
> + };
> +
> +static inline
>
Re: [Intel-gfx] [PATCH v8 12/35] drm/i915: Implement the HDCP2.2 support for DP
On 11/27/2018 11:07 PM, Daniel Vetter wrote:
On Tue, Nov 27, 2018 at 04:54:15PM +, Bloomfield, Jon wrote:
I'm not formally reviewing this series, but while glancing at it, I noticed
-Original Message-
From: Intel-gfx On Behalf Of
Ramalingam C
Sent: Tuesday, November 27, 2018 2:43 AM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
daniel.vet...@ffwll.ch; Winkler, Tomas
Subject: [Intel-gfx] [PATCH v8 12/35] drm/i915: Implement the HDCP2.2
support for DP
Implements the DP adaptation specific HDCP2.2 functions.
These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.
v2:
wait for cp_irq is merged with this patch. Rebased.
v3:
wait_queue is used for wait for cp_irq [Chris Wilson]
v4:
Style fixed.
%s/PARING/PAIRING
Few style fixes [Uma]
v5:
Lookup table for DP HDCP2.2 msg details [Daniel].
Extra lines are removed.
v6:
Rebased.
v7:
Fixed some regression introduced at v5. [Ankit]
Macro HDCP_2_2_RX_CAPS_VERSION_VAL is reused [Uma]
Converted a function to inline [Uma]
%s/uintxx_t/uxx
v8:
Error due to the sinks are reported as DEBUG logs.
Adjust to the new mei interface.
Signed-off-by: Ramalingam C
Signed-off-by: Ankit K Nautiyal
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dp.c | 338
++
drivers/gpu/drm/i915/intel_drv.h | 7 +
drivers/gpu/drm/i915/intel_hdcp.c | 6 +
3 files changed, 351 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index ecc4706db7dc..1cc82e490999 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -5347,6 +5348,27 @@ void intel_dp_encoder_suspend(struct
intel_encoder *intel_encoder)
pps_unlock(intel_dp);
}
+
+static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
+{
+ int i;
+
+ for (i = 0; i < sizeof(hdcp2_msg_data); i++)
Should be
sizeof(hdcp2_msg_data) / sizeof(*hdcp2_msg_data)
or equivalent.
ARRAY_SIZE is probably what you want here.
yes. missed it as authentication flow always provides the valid msg_id.
Will fix it.
--Ram
-Daniel
Has the failure return been tested?
+ if (hdcp2_msg_data[i].msg_id == msg_id)
+ return _msg_data[i];
+
+ return NULL;
+}
+
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
== Series Details ==
Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53097/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10918_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10918_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10918_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10918_full:
=== IGT changes ===
Possible regressions
igt@gem_userptr_blits@readonly-unsync:
shard-kbl: PASS -> TIMEOUT
{igt@runner@aborted}:
{shard-iclb}: NOTRUN -> FAIL
Warnings
igt@kms_chv_cursor_fail@pipe-b-64x64-top-edge:
shard-snb: SKIP -> PASS +1
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10918_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@drm_import_export@import-close-race-flink:
shard-skl: PASS -> TIMEOUT ([fdo#108667])
igt@gem_exec_schedule@pi-ringfull-blt:
shard-skl: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_schedule@pi-ringfull-vebox:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_suspend@basic-s3:
shard-kbl: PASS -> INCOMPLETE ([fdo#103665])
igt@gem_mmap_gtt@big-copy-xy:
shard-glk: PASS -> INCOMPLETE ([fdo#103359], [k.org#198133])
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: PASS -> TIMEOUT ([fdo#108039])
igt@gem_workarounds@suspend-resume-fd:
shard-skl: PASS -> INCOMPLETE ([fdo#104108], [fdo#107773])
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
shard-skl: NOTRUN -> DMESG-WARN ([fdo#107956])
igt@kms_color@pipe-a-ctm-max:
shard-apl: PASS -> FAIL ([fdo#108147])
igt@kms_color@pipe-c-legacy-gamma:
shard-kbl: PASS -> DMESG-WARN ([fdo#103313], [fdo#103558],
[fdo#105602]) +2
igt@kms_cursor_crc@cursor-128x42-sliding:
shard-apl: PASS -> FAIL ([fdo#103232]) +2
shard-glk: PASS -> FAIL ([fdo#103232]) +3
igt@kms_cursor_crc@cursor-64x21-random:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103232])
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: PASS -> FAIL ([fdo#103191], [fdo#103232])
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-hsw: PASS -> FAIL ([fdo#102887])
igt@kms_flip_tiling@flip-yf-tiled:
shard-skl: PASS -> FAIL ([fdo#108145])
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
shard-glk: PASS -> FAIL ([fdo#103167]) +4
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
shard-apl: PASS -> FAIL ([fdo#103167]) +3
igt@kms_frontbuffer_tracking@fbc-1p-rte:
shard-kbl: PASS -> DMESG-WARN ([fdo#103313], [fdo#103558])
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
shard-skl: NOTRUN -> FAIL ([fdo#103167]) +2
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
{shard-iclb}: PASS -> FAIL ([fdo#103167]) +1
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL ([fdo#108145])
igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
shard-kbl: NOTRUN -> FAIL ([fdo#108145])
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL ([fdo#103166]) +3
shard-apl: PASS -> FAIL ([fdo#103166]) +1
igt@kms_rmfb@rmfb-ioctl:
shard-kbl: PASS -> DMESG-WARN ([fdo#103558], [fdo#105602]) +19
igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
shard-kbl: PASS -> DMESG-WARN ([fdo#103558], [fdo#103841],
[fdo#105079], [fdo#105602])
igt@pm_rpm@gem-mmap-cpu:
{shard-iclb}: PASS -> INCOMPLETE ([fdo#108840])
igt@pm_rpm@i2c:
{shard-iclb}: PASS -> DMESG-WARN ([fdo#107724])
igt@pm_rpm@legacy-planes-dpms:
{shard-iclb}: PASS -> DMESG-WARN ([fdo#108654])
igt@pm_rpm@modeset-pc8-residency-stress:
{shard-iclb}: SKIP -> INCOMPLETE ([fdo#108840])
{igt@runner@aborted}:
shard-kbl: NOTRUN -> FAIL ([fdo#103841])
Possible fixes
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: INCOMPLETE ([fdo#103665], [fdo#106023], [fdo#106887])
-> PASS
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
Re: [Intel-gfx] [PATCH v6 3/6] drm/dp_mst: Start tracking per-port VCPI allocations
On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote: > On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote: > > On Mon, 2018-11-26 at 22:22 +0100, Daniel Vetter wrote: > > > On Mon, Nov 26, 2018 at 10:04:21PM +0100, Daniel Vetter wrote: > > > > On Thu, Nov 15, 2018 at 07:50:05PM -0500, Lyude Paul wrote: > > > > > There has been a TODO waiting for quite a long time in > > > > > drm_dp_mst_topology.c: > > > > > > > > > > /* We cannot rely on port->vcpi.num_slots to update > > > > >* topology_state->avail_slots as the port may not exist if > > > > > the parent > > > > >* branch device was unplugged. This should be fixed by > > > > > tracking > > > > >* per-port slot allocation in drm_dp_mst_topology_state > > > > > instead of > > > > >* depending on the caller to tell us how many slots to > > > > > release. > > > > >*/ > > > > > > > > > > That's not the only reason we should fix this: forcing the driver to > > > > > track the VCPI allocations throughout a state's atomic check is > > > > > error prone, because it means that extra care has to be taken with > > > > > the > > > > > order that drm_dp_atomic_find_vcpi_slots() and > > > > > drm_dp_atomic_release_vcpi_slots() are called in in order to ensure > > > > > idempotency. Currently the only driver actually using these helpers, > > > > > i915, doesn't even do this correctly: multiple ->best_encoder() > > > > > checks > > > > > with i915's current implementation would not be idempotent and would > > > > > over-allocate VCPI slots, something I learned trying to implement > > > > > fallback retraining in MST. > > > > > > > > > > So: simplify this whole mess, and teach > > > > > drm_dp_atomic_find_vcpi_slots() > > > > > and drm_dp_atomic_release_vcpi_slots() to track the VCPI allocations > > > > > for > > > > > each port. This allows us to ensure idempotency without having to > > > > > rely > > > > > on the driver as much. Additionally: the driver doesn't need to do > > > > > any > > > > > kind of VCPI slot tracking anymore if it doesn't need it for it's > > > > > own > > > > > internal state. > > > > > > > > > > Additionally; this adds a new drm_dp_mst_atomic_check() helper which > > > > > must be used by atomic drivers to perform validity checks for the > > > > > new > > > > > VCPI allocations incurred by a state. > > > > > > > > > > Also: update the documentation and make it more obvious that these > > > > > /must/ be called by /all/ atomic drivers supporting MST. > > > > > > > > > > Changes since v6: > > > > > - Keep a kref to all of the ports we have allocations on. This > > > > > required > > > > >a good bit of changing to when we call drm_dp_find_vcpi_slots(), > > > > >mainly that we need to ensure that we only redo VCPI allocations > > > > > on > > > > >actual mode or CRTC changes, not crtc_state->active changes. > > > > >Additionally, we no longer take the registration of the DRM > > > > > connector > > > > >for each port into account because so long as we have a kref to > > > > > the > > > > >port in the new or previous atomic state, the connector will stay > > > > >registered. > > > > > > > > I write an entire pile of small nitpits (still included most of them > > > > below), until I realized this here wont work. Delaying the call to > > > > destroy > > > > the connector (well, unregister it really) wreaks the design we've > > > > come up > > > > with thus far, resulting in most of my comments here. > > > > > > > > Instead, all we need to do is delay the kfree(port) at the bottom of > > > > drm_dp_destroy_port(). The vcpi allocation structure _only_ needs the > > > > pointer value to stay valid, as a lookup key. It doesn't care at all > > > > about > > > > anything actually stored in there. So the only thing we need to delay > > > > is > > > > the kfree. I think the simplest way to achieve this is to add a 2nd > > > > kref > > > > (port->kfree_ref or something like that), with on reference held by > > > > the > > > > port itself (released in drm_dp_destroy_port), and the other one held > > > > as-needed by the vcpi allocation lists. > > > > > > > > I think if we go with this design instead of retrofitting a semantic > > > > change of the port lifetime itself, all the complications I complain > > > > about > > > > below should disappear. > > > > > > In the above I meant drm_dp_destroy_port or > > > drm_dp_destroy_connector_work. > > > > > > Aside: I think creating a kref for the final kfree would also solve a > > > bunch of other issues in a much neater way: In > > > > > > commit f038c5b99fc1332f558b495d136d4f433ee65caa > > > Author: Lyude Paul > > > Date: Tue Nov 13 17:46:14 2018 -0500 > > > > > > drm/dp_mst: Skip validating ports during destruction, just ref > > > > > > we could use that kfree reference to make sure the port pointer is > > > alive. > > > This of course means that drm_dp_update_payload_part1() would also need > > > to > > > use the kfree
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size
== Series Details ==
Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO
size
URL : https://patchwork.freedesktop.org/series/53096/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10917_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10917_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10917_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10917_full:
=== IGT changes ===
Warnings
igt@kms_chv_cursor_fail@pipe-b-64x64-top-edge:
shard-snb: SKIP -> PASS
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10917_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_exec_schedule@pi-ringfull-blt:
shard-skl: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_schedule@pi-ringfull-vebox:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103158])
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: PASS -> TIMEOUT ([fdo#108039])
igt@kms_atomic_transition@1x-modeset-transitions-fencing:
shard-skl: NOTRUN -> FAIL ([fdo#108470])
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: PASS -> FAIL ([fdo#106641])
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
shard-skl: NOTRUN -> DMESG-WARN ([fdo#107956])
igt@kms_color@pipe-a-ctm-max:
shard-apl: PASS -> FAIL ([fdo#108147])
igt@kms_cursor_crc@cursor-256x256-dpms:
shard-glk: PASS -> FAIL ([fdo#103232]) +2
igt@kms_cursor_crc@cursor-256x85-onscreen:
shard-apl: PASS -> FAIL ([fdo#103232]) +2
igt@kms_cursor_crc@cursor-64x21-random:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103232])
igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
shard-skl: PASS -> FAIL ([fdo#103184], [fdo#103232])
igt@kms_fbcon_fbt@fbc-suspend:
shard-skl: PASS -> INCOMPLETE ([fdo#104108], [fdo#107773])
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: PASS -> FAIL ([fdo#102887], [fdo#105363])
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: PASS -> FAIL ([fdo#105363])
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-apl: PASS -> FAIL ([fdo#103167]) +1
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
shard-skl: NOTRUN -> FAIL ([fdo#103167])
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
{shard-iclb}: PASS -> FAIL ([fdo#103167]) +2
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
shard-skl: NOTRUN -> FAIL ([fdo#105682]) +1
igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
shard-skl: NOTRUN -> FAIL ([fdo#103191], [fdo#107362])
igt@kms_plane@plane-position-covered-pipe-c-planes:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103166])
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL ([fdo#108145])
igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
shard-glk: PASS -> FAIL ([fdo#103166]) +3
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
shard-apl: PASS -> FAIL ([fdo#103166]) +1
{shard-iclb}: PASS -> FAIL ([fdo#103166])
igt@kms_rotation_crc@primary-rotation-90:
shard-skl: NOTRUN -> FAIL ([fdo#103925], [fdo#107815])
igt@pm_rpm@dpms-mode-unset-non-lpsp:
{shard-iclb}: SKIP -> INCOMPLETE ([fdo#108840])
igt@pm_rpm@gem-idle:
{shard-iclb}: PASS -> INCOMPLETE ([fdo#107713], [fdo#108840]) +1
igt@pm_rpm@gem-mmap-cpu:
{shard-iclb}: PASS -> INCOMPLETE ([fdo#108840])
Possible fixes
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-snb: DMESG-WARN ([fdo#107956]) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
shard-kbl: DMESG-WARN ([fdo#107956]) -> PASS +1
igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
shard-skl: FAIL ([fdo#104671]) -> PASS
igt@kms_color@pipe-a-legacy-gamma:
shard-skl: FAIL ([fdo#104782], [fdo#108145]) -> PASS
igt@kms_cursor_crc@cursor-64x64-dpms:
shard-apl: FAIL ([fdo#103232]) -> PASS +1
igt@kms_cursor_crc@cursor-64x64-offscreen:
shard-skl: FAIL ([fdo#103232]) -> PASS +1
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk:
Re: [Intel-gfx] [v4 1/3] drm: Add HDMI colorspace property
Hi Uma,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.20-rc4 next-20181127]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Uma-Shankar/Add-Colorspace-connector-property-interface/20181128-083317
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x017-201847 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings
All warnings (new ones prefixed by >>):
drivers/gpu/drm/drm_connector.c: In function
'drm_mode_create_colorspace_property':
>> drivers/gpu/drm/drm_connector.c:1459:33: warning: 'prop' may be used
>> uninitialized in this function [-Wmaybe-uninitialized]
connector->colorspace_property = prop;
~~~^~
vim +/prop +1459 drivers/gpu/drm/drm_connector.c
1427
1428 /**
1429 * drm_mode_create_colorspace_property - create colorspace property
1430 * Colorspace:
1431 * This property helps select a suitable colorspace based on the
sink
1432 * capability. Modern sink devices support wider gamut like BT2020.
1433 * This helps switch to BT2020 mode if the BT2020 encoded video
stream
1434 * is being played by the user, same for any other colorspace.
1435 * @connector: connector to set property on.
1436 *
1437 * Called by a driver the first time it's needed, must be attached to
desired
1438 * connectors.
1439 *
1440 * Returns:
1441 * Zero on success, negative errno on failure.
1442 */
1443 int drm_mode_create_colorspace_property(struct drm_connector *connector)
1444 {
1445 struct drm_device *dev = connector->dev;
1446 struct drm_property *prop;
1447
1448 if (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
1449 connector->connector_type ==
DRM_MODE_CONNECTOR_HDMIB) {
1450
1451 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
1452 "Colorspace",
1453 hdmi_colorspace,
1454
ARRAY_SIZE(hdmi_colorspace));
1455 if (!prop)
1456 return -ENOMEM;
1457 }
1458
> 1459 connector->colorspace_property = prop;
1460
1461 return 0;
1462 }
1463 EXPORT_SYMBOL(drm_mode_create_colorspace_property);
1464
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 0/7] Make GEN macros more similar
On Tue, Nov 27, 2018 at 11:35:54AM +, Tvrtko Ursulin wrote: > > On 27/11/2018 09:36, Lucas De Marchi wrote: > > On Tue, Nov 27, 2018 at 10:37:21AM +0200, Jani Nikula wrote: > > > On Mon, 26 Nov 2018, Rodrigo Vivi wrote: > > > > On Thu, Nov 22, 2018 at 08:54:30AM +, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > > On 21/11/2018 22:19, Rodrigo Vivi wrote: > > > > > > On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: > > > > > > > On Thu, Nov 08, 2018 at 11:23:46AM +, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > > > On 08/11/2018 00:57, Lucas De Marchi wrote: > > > > > > > > > On Wed, Nov 07, 2018 at 10:05:19AM +, Tvrtko Ursulin > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > On 06/11/2018 21:51, Lucas De Marchi wrote: > > > > > > > > > > > This is the second version of the series trying to make > > > > > > > > > > > GEN checks > > > > > > > > > > > more similar. These or roughly the changes from v1: > > > > > > > > > > > > > > > > > > > > > > - We don't have a single macro receiving 2 or 3 > > > > > > > > > > > parameters. Now there > > > > > > > > > > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the > > > > > > > > > > > conversion from > > > > > > > > > > > IS_GEN() while the second is the conversion from > > > > > > > > > > > IS_GEN() > > > > > > > > > > > - Bring GEN_FOREVER back to be used with above macros > > > > > > > > > > > - Patch converting <, <=, ==, >, >= checks using > > > > > > > > > > > INTEL_GEN() to > > > > > > > > > > > use the macros above was added > > > > > > > > > > > - INTEL_GEN() is removed to avoid it being used when we > > > > > > > > > > > should prefer > > > > > > > > > > > the new macros > > > > > > > > > > > > > > > > > > > > > > The idea of the names is to pave the way for checks of > > > > > > > > > > > the display version, > > > > > > > > > > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > > > > > > > > > > > > > > > > > > > > > > In the commit messages we have the scripts to regenerate > > > > > > > > > > > the patch to make > > > > > > > > > > > it easier to apply after the discussions and also to be > > > > > > > > > > > able to convert > > > > > > > > > > > inflight patches. > > > > > > > > > > > > > > > > > > > > > > Sorry in advance for the noise this causes in the > > > > > > > > > > > codebase, but hopefully > > > > > > > > > > > it is for the greater good. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Lucas De Marchi (6): > > > > > > > > > > > Revert "drm/i915: Kill GEN_FOREVER" > > > > > > > > > > > drm/i915: replace IS_GEN with GT_GEN(..., N) > > > > > > > > > > > drm/i915: rename IS_GEN9_* to GT_GEN9_* > > > > > > > > > > > drm/i915: replace gen checks using operators by > > > > > > > > > > > GT_GEN/GT_GEN_RANGE > > > > > > > > > > > > > > > > > > > > I have reservations about this patch, where I think forcing > > > > > > > > > > only one flavour > > > > > > > > > > maybe is not the best thing. Because for plain if-ladder > > > > > > > > > > cases it feels more > > > > > > > > > > readable to stick with the current scheme of arithmetic > > > > > > > > > > comparisons. And it > > > > > > > > > > is more efficient in code as well. > > > > > > > > > > > > > > > > > > > > Range checks are on the other hand useful either when > > > > > > > > > > combined in the same > > > > > > > > > > conditional as some other bitmask based test, or when both > > > > > > > > > > ends of the > > > > > > > > > > comparison edge are bound. > > > > > > > > > > > > > > > > > > So are you against changing the == to use the macros, > > > > > > > > > changing the >=, >, <, <=, > > > > > > > > > or all of them? > > > > > > > > > > > > > > > > Definitely not all of them. Just plain if ladders I think are > > > > > > > > definitely > > > > > > > > more readable in source and result in better code in the normal > > > > > > > > fashion of: > > > > > > > > > > > > > > > > if (gen >= 11) > > > > > > > > else if (gen >= 9) > > > > > > > > else if (gen >= 7) > > > > > > > > ... etc ... > > > > > > > > > > > > > > > > Where I think it makes sense is when either both edges are > > > > > > > > bound, like: > > > > > > > > > > > > > > > > if (gen < 11 || gen >= 8) > > > > > > > > if (gen >= 10 || gen == 8) > > > > > > > > > > > > > > ok, I will take a look before respinning this. > > > > > > > > > > > > > > > > > > > > > > > But not sure how many of those there are. > > > > > > > > > > > > > > > > What definitely exists in large-ish numbers are: > > > > > > > > > > > > specially on display side... > > > > > > > > > > > > > > > > > > > > > > if (gen >= 11 || IS_PLATFORM) > > > > > > > > > > > > My goal is exactly to organize the gen numbers in a way that > > > > > > we minimize this mix as much as possible. > > > > > > > > > > > > > > > > > > > > > > At some point I had a prototype
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL : https://patchwork.freedesktop.org/series/51878/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10915_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10915_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10915_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10915_full:
=== IGT changes ===
Warnings
igt@kms_chv_cursor_fail@pipe-b-64x64-top-edge:
shard-snb: SKIP -> PASS
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10915_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@debugfs_test@read_all_entries_display_off:
shard-skl: PASS -> INCOMPLETE ([fdo#104108])
igt@gem_exec_suspend@basic-s3:
shard-kbl: PASS -> INCOMPLETE ([fdo#103665])
igt@gem_softpin@noreloc-s3:
shard-skl: PASS -> INCOMPLETE ([fdo#104108], [fdo#107773])
igt@i915_suspend@shrink:
shard-skl: NOTRUN -> INCOMPLETE ([fdo#106886])
igt@kms_chv_cursor_fail@pipe-c-128x128-right-edge:
shard-skl: NOTRUN -> FAIL ([fdo#104671])
igt@kms_color@pipe-a-ctm-0-25:
shard-skl: PASS -> FAIL ([fdo#108682])
igt@kms_color@pipe-a-ctm-max:
shard-apl: PASS -> FAIL ([fdo#108147])
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: PASS -> FAIL ([fdo#103232]) +3
igt@kms_cursor_crc@cursor-64x21-onscreen:
shard-glk: PASS -> FAIL ([fdo#103232]) +2
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: PASS -> FAIL ([fdo#103191], [fdo#103232])
igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
shard-skl: PASS -> FAIL ([fdo#103184], [fdo#103232])
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
shard-apl: PASS -> FAIL ([fdo#103167]) +2
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
shard-glk: PASS -> FAIL ([fdo#103167]) +6
igt@kms_frontbuffer_tracking@fbc-suspend:
shard-skl: PASS -> INCOMPLETE ([fdo#104108], [fdo#105959])
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
shard-skl: NOTRUN -> FAIL ([fdo#103167]) +1
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
{shard-iclb}: PASS -> FAIL ([fdo#103167]) +3
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL ([fdo#108145]) +1
igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
shard-skl: NOTRUN -> FAIL ([fdo#107815])
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
{shard-iclb}: PASS -> FAIL ([fdo#103166])
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL ([fdo#103166])
shard-apl: PASS -> FAIL ([fdo#103166]) +1
igt@kms_psr@no_drrs:
{shard-iclb}: PASS -> FAIL ([fdo#108341])
igt@pm_rpm@sysfs-read:
{shard-iclb}: PASS -> INCOMPLETE ([fdo#107713], [fdo#108840])
Possible fixes
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
{shard-iclb}: DMESG-WARN ([fdo#107956]) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-apl: DMESG-WARN ([fdo#107956]) -> PASS
igt@kms_color@pipe-a-legacy-gamma:
shard-skl: FAIL ([fdo#104782], [fdo#108145]) -> PASS
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN ([fdo#105763], [fdo#106538]) -> PASS
igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
shard-glk: FAIL ([fdo#103184]) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-apl: FAIL ([fdo#102887], [fdo#105363]) -> PASS
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
{shard-iclb}: FAIL ([fdo#103167]) -> PASS +3
igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
{shard-iclb}: FAIL ([fdo#103166]) -> PASS +1
igt@pm_rpm@pm-caching:
shard-skl: INCOMPLETE ([fdo#107807]) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167
Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: replace IS_GEN with GT_GEN(..., N)
On Tue, Nov 27, 2018 at 10:31:49AM +0200, Jani Nikula wrote: > On Mon, 26 Nov 2018, Rodrigo Vivi wrote: > > On Fri, Nov 23, 2018 at 02:42:59PM +0200, Jani Nikula wrote: > >> On Wed, 21 Nov 2018, Rodrigo Vivi wrote: > >> > On Tue, Nov 06, 2018 at 01:51:19PM -0800, Lucas De Marchi wrote: > >> >> Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of > >> >> IS_GEN to pss the gen as parameter. This prepares for the addition > >> >> of display gen checks by renaming the IS_GENx() and using common code > >> >> for all the n gens. > >> >> > >> >> The following spatch was used to convert the users of these macros: > >> >> > >> >> @@ > >> >> expression e; > >> >> @@ > >> >> ( > >> >> - IS_GEN2(e) > >> >> + GT_GEN(e, 2) > >> >> | > >> >> - IS_GEN3(e) > >> >> + GT_GEN(e, 3) > >> >> | > >> >> - IS_GEN4(e) > >> >> + GT_GEN(e, 4) > >> >> | > >> >> - IS_GEN5(e) > >> >> + GT_GEN(e, 5) > >> >> | > >> >> - IS_GEN6(e) > >> >> + GT_GEN(e, 6) > >> >> | > >> >> - IS_GEN7(e) > >> >> + GT_GEN(e, 7) > >> >> | > >> >> - IS_GEN8(e) > >> >> + GT_GEN(e, 8) > >> >> | > >> >> - IS_GEN9(e) > >> >> + GT_GEN(e, 9) > >> >> | > >> >> - IS_GEN10(e) > >> >> + GT_GEN(e, 10) > >> >> | > >> >> - IS_GEN11(e) > >> >> + GT_GEN(e, 11) > >> >> ) > >> >> > >> >> Signed-off-by: Lucas De Marchi > >> > > >> > Reviewed-by: Rodrigo Vivi > >> > >> I think this is a contentious patch. I am not sure I agree with the > >> change. Please hold off on merging until further discussion. > > > > Yeap. I just reviewed the ones that no body raised any issue yet. > > So it would pop up on their inbox again for a double change to complain. > > > > I didn't add reviewed on the patches we are still discussing exactly > > to avoid merging it without finishing the discussions. > > I don't think we've reached consensus on IS_GEN -> GT_GEN. yeap... I just noticed this on the other branch of this thread :( > > BR, > Jani. > > > > > > Thanks, > > Rodrigo. > > > >> > >> > >> Thanks, > >> Jani. > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI v12 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Manasi Navare
>Sent: Tuesday, November 27, 2018 1:41 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [CI v12 05/23] drm/dsc: Add helpers for DSC picture
>parameter set infoframes
>
>According to Display Stream compression spec 1.2, the picture parameter set
>metadata is sent from source to sink device using the DP Secondary data packet.
>An infoframe is formed for the PPS SDP header and PPS SDP payload bytes.
>This patch adds helpers to fill the PPS SDP header and PPS SDP payload
>according
>to the DSC 1.2 specification.
>
>v7:
>* Use BUILD_BUG_ON() to protect changing struct size (Ville)
>* Remove typecaseting (Ville)
>* Include byteorder.h in drm_dsc.c (Ville)
>* Correct kernel doc spacing (Anusha)
>v6:
>* Use proper sequence points for breaking down the assignments (Chris Wilson)
>* Use SPDX identifier
>v5:
>Do not use bitfields for DRM structs (Jani N)
>v4:
>* Use DSC constants for params that dont change across configurations
>v3:
>* Add reference to added kernel-docs in
>Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter)
>
>v2:
>* Add EXPORT_SYMBOL for the drm functions (Manasi)
>
>Cc: dri-de...@lists.freedesktop.org
>Cc: Jani Nikula
>Cc: Ville Syrjala
>Cc: Anusha Srivatsa
>Cc: Harry Wentland
>Signed-off-by: Manasi Navare
>Acked-by: Harry Wentland
Looks good :)
Reviewed-by: Anusha Srivatsa
>---
> Documentation/gpu/drm-kms-helpers.rst | 12 ++
> drivers/gpu/drm/Makefile | 2 +-
> drivers/gpu/drm/drm_dsc.c | 228 ++
> include/drm/drm_dsc.h | 21 +++
> 4 files changed, 262 insertions(+), 1 deletion(-) create mode 100644
>drivers/gpu/drm/drm_dsc.c
>
>diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-
>kms-helpers.rst
>index 4b4dc236ef6f..b422eb8edf16 100644
>--- a/Documentation/gpu/drm-kms-helpers.rst
>+++ b/Documentation/gpu/drm-kms-helpers.rst
>@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference .. kernel-doc::
>drivers/gpu/drm/drm_mipi_dsi.c
>:export:
>
>+Display Stream Compression Helper Functions Reference
>+=
>+
>+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
>+ :doc: dsc helpers
>+
>+.. kernel-doc:: include/drm/drm_dsc.h
>+ :internal:
>+
>+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
>+ :export:
>+
> Output Probing Helper Functions Reference
>=
>
>diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index
>1fafc2f8e8f9..e490fe2687db 100644
>--- a/drivers/gpu/drm/Makefile
>+++ b/drivers/gpu/drm/Makefile
>@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
> drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
> drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
>
>-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
>+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
>+drm_probe_helper.o \
> drm_plane_helper.o drm_dp_mst_topology.o
>drm_atomic_helper.o \
> drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
> drm_simple_kms_helper.o drm_modeset_helper.o \ diff --git
>a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c new file mode
>100644 index ..bc2b23adb072
>--- /dev/null
>+++ b/drivers/gpu/drm/drm_dsc.c
>@@ -0,0 +1,228 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2018 Intel Corp
>+ *
>+ * Author:
>+ * Manasi Navare */
>+
>+#include
>+#include
>+#include
>+#include
>+#include
>+#include
>+#include
>+
>+/**
>+ * DOC: dsc helpers
>+ *
>+ * These functions contain some common logic and helpers to deal with
>+VESA
>+ * Display Stream Compression standard required for DSC on Display
>+Port/eDP or
>+ * MIPI display interfaces.
>+ */
>+
>+/**
>+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
>+ * for DisplayPort as per the DP 1.4 spec.
>+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set */
>+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
>+{
>+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
>+
>+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
>+ pps_sdp->pps_header.HB2 =
>DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
>+}
>+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
>+
>+/**
>+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
>+ * using the DSC configuration parameters in the order expected
>+ * by the DSC Display Sink device. For the DSC, the sink device
>+ * expects the PPS payload in the big endian format for the fields
>+ * that span more than 1 byte.
>+ *
>+ * @pps_sdp:
>+ * Secondary data packet for DSC Picture Parameter Set
>+ * @dsc_cfg:
>+ * DSC Configuration data filled by driver */ void
>+drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>+ const struct drm_dsc_config *dsc_cfg) {
>+ int i;
>+
>+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
== Series Details ==
Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53113/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7a0e6f477712 drm/dsc: Modify DRM helper to return complete DSC color depth
capabilities
ea7d0af71145 drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 342 lines checked
5a10579136d2 drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Gaurav K Singh
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
997353e778c6 drm/dsc: Define Rate Control values that do not change over
configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Srivatsa, Anusha '
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
9d11c6b79b15 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#79:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 285 lines checked
86063cff9200 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
e84e030e63eb drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+ bool compression_enable;
-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:944:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
515ca97957b0 drm/i915/dp: Compute DSC pipe config in atomic check
8eaadf4ee2f3 drm/i915/dp: Do not enable PSR2 if DSC is enabled
5da78eb1b699 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68:
Co-developed-by: Manasi Navare
-:95: WARNING:MISSING_SPACE: break quoted strings at a space character
#95: FILE: drivers/gpu/drm/i915/intel_dp.c:1958:
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#119:
new file mode 100644
-:405: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#405: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3 warnings, 1 checks, 496 lines checked
5a4aa749bcea drm/i915/dsc: Compute Rate Control parameters for DSC
-:141: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#141: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+ vdsc_cfg->slice_bpg_offset)*
^
-:173: CHECK:LINE_SPACING: Please don't use multiple blank lines
#173: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+
total: 0 errors, 0 warnings, 2 checks, 136 lines checked
c3e3d9cb6b67 drm/i915/dp: Enable/Disable DSC in DP Sink
45b31fa193ee drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
f8773070bae7 drm/i915/dp: Configure i915 Picture parameter Set registers during
DSC enabling
-:347: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#347: FILE: drivers/gpu/drm/i915/intel_vdsc.c:853:
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
== Series Details == Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities URL : https://patchwork.freedesktop.org/series/53113/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:200:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:200:61:got int +drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:207:25:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:207:25:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types) Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1896:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1938:58: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3573:16: warning: expression using sizeof(void) Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC Okay! Commit: i915/dp/fec: Add fec_enable to the crtc state. Okay! Commit: drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Okay! Commit: i915/dp/fec: Configure the Forward Error Correction bits. Okay! Commit: drm/i915/fec: Disable FEC state. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
== Series Details ==
Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53113/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212 -> Patchwork_10923 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53113/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10923 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_mmap@basic-small-bo:
fi-glk-dsi: PASS -> INCOMPLETE ([fdo#103359], [k.org#198133])
igt@i915_selftest@live_hangcheck:
fi-kbl-7560u: PASS -> INCOMPLETE ([fdo#108044])
igt@kms_frontbuffer_tracking@basic:
{fi-icl-u3}:PASS -> FAIL ([fdo#103167])
{igt@runner@aborted}:
{fi-icl-u3}:NOTRUN -> FAIL ([fdo#108315])
Possible fixes
igt@gem_ctx_create@basic-files:
fi-bsw-n3050: DMESG-FAIL ([fdo#108656]) -> PASS
Warnings
igt@i915_selftest@live_contexts:
{fi-icl-u3}:DMESG-FAIL ([fdo#108569]) -> INCOMPLETE ([fdo#108315])
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044
fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (51 -> 45) ==
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5212 -> Patchwork_10923
CI_DRM_5212: db8d567e7cf70aeca866e85972078cd5c9b59cfb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4734: 0a961239c27bfbd60c045e6255b2970d4bf84411 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10923: a79d7adf1fd16e1e4384f46afc61d05e1e2b8cde @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a79d7adf1fd1 drm/i915/fec: Disable FEC state.
fbd778a69e5b i915/dp/fec: Configure the Forward Error Correction bits.
c76984aa6e6e drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
5d9589b73cf3 i915/dp/fec: Add fec_enable to the crtc state.
146fc028c63b drm/i915/dsc: Enable and disable appropriate power wells for VDSC
22be2d18f427 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
6bbec3a991c6 drm/i915/dp: Configure Display stream splitter registers during
DSC enable
e95a9ab97cb9 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
1f07378353b9 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
f8773070bae7 drm/i915/dp: Configure i915 Picture parameter Set registers during
DSC enabling
45b31fa193ee drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
c3e3d9cb6b67 drm/i915/dp: Enable/Disable DSC in DP Sink
5a4aa749bcea drm/i915/dsc: Compute Rate Control parameters for DSC
5da78eb1b699 drm/i915/dsc: Define & Compute VESA DSC params
8eaadf4ee2f3 drm/i915/dp: Do not enable PSR2 if DSC is enabled
515ca97957b0 drm/i915/dp: Compute DSC pipe config in atomic check
e84e030e63eb drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
86063cff9200 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
9d11c6b79b15 drm/dsc: Add helpers for DSC picture parameter set infoframes
997353e778c6 drm/dsc: Define Rate Control values that do not change over
configurations
5a10579136d2 drm/dsc: Define VESA Display Stream Compression Capabilities
ea7d0af71145 drm/dsc: Define Display Stream Compression PPS infoframe
7a0e6f477712 drm/dsc: Modify DRM helper to return complete DSC color depth
capabilities
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10923/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ringbuffer: Clear semaphore sync registers on ring init
== Series Details ==
Series: drm/i915/ringbuffer: Clear semaphore sync registers on ring init
URL : https://patchwork.freedesktop.org/series/53112/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212 -> Patchwork_10922 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53112/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10922 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_exec_suspend@basic-s4-devices:
fi-ivb-3520m: PASS -> FAIL ([fdo#108880])
igt@i915_selftest@live_coherency:
fi-gdg-551: PASS -> DMESG-FAIL ([fdo#107164])
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: PASS -> DMESG-WARN ([fdo#105998])
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: PASS -> FAIL ([fdo#103167])
igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
fi-byt-clapper: PASS -> FAIL ([fdo#103191], [fdo#107362])
Possible fixes
igt@gem_ctx_create@basic-files:
fi-bsw-n3050: DMESG-FAIL ([fdo#108656]) -> PASS
igt@kms_chamelium@hdmi-hpd-fast:
{fi-kbl-7500u}: FAIL -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
fdo#108880 https://bugs.freedesktop.org/show_bug.cgi?id=108880
== Participating hosts (51 -> 45) ==
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5212 -> Patchwork_10922
CI_DRM_5212: db8d567e7cf70aeca866e85972078cd5c9b59cfb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4734: 0a961239c27bfbd60c045e6255b2970d4bf84411 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10922: 280b224f42bc6c4b744c3317065a5cc0635e28b6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
280b224f42bc drm/i915/ringbuffer: Clear semaphore sync registers on ring init
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10922/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
On Tue, Nov 27, 2018 at 4:46 AM Joonas Lahtinen wrote: > I think a more abstract property "% of GPU (processing power)" might > be a more universal approach. One can then implement that through > subdividing the resources or timeslicing them, depending on the GPU > topology. > > Leasing 1/8th, 1/4th or 1/2 of the GPU would probably be the most > applicable to cloud provider usecases, too. At least that's what I > see done for the CPUs today. I think there are opportunities to slice the gpu in more than one way (similar to the way it is done for cpu.) We can potentially frame resources as continuous or discrete. Percentage definitely fits well for continuous measurements such as time/time slices but I think there are places for discrete units such as core counts as well. Regards, Kenny > That combined with the "GPU memory usable" property should be a good > starting point to start subdividing the GPU resources for multiple > users. > > Regards, Joonas > > > > > Your feedback is highly appreciated. > > > > Best Regards, > > Harish > > > > > > > > From: amd-gfx on behalf of Tejun > > Heo > > Sent: Tuesday, November 20, 2018 5:30 PM > > To: Ho, Kenny > > Cc: cgro...@vger.kernel.org; intel-gfx@lists.freedesktop.org; > > y2ke...@gmail.com; amd-...@lists.freedesktop.org; > > dri-de...@lists.freedesktop.org > > Subject: Re: [PATCH RFC 2/5] cgroup: Add mechanism to register vendor > > specific DRM devices > > > > > > Hello, > > > > On Tue, Nov 20, 2018 at 10:21:14PM +, Ho, Kenny wrote: > > > By this reply, are you suggesting that vendor specific resources > > > will never be acceptable to be managed under cgroup? Let say a user > > > > I wouldn't say never but whatever which gets included as a cgroup > > controller should have clearly defined resource abstractions and the > > control schemes around them including support for delegation. AFAICS, > > gpu side still seems to have a long way to go (and it's not clear > > whether that's somewhere it will or needs to end up). > > > > > want to have similar functionality as what cgroup is offering but to > > > manage vendor specific resources, what would you suggest as a > > > solution? When you say keeping vendor specific resource regulation > > > inside drm or specific drivers, do you mean we should replicate the > > > cgroup infrastructure there or do you mean either drm or specific > > > driver should query existing hierarchy (such as device or perhaps > > > cpu) for the process organization information? > > > > > > To put the questions in more concrete terms, let say a user wants to > > > expose certain part of a gpu to a particular cgroup similar to the > > > way selective cpu cores are exposed to a cgroup via cpuset, how > > > should we go about enabling such functionality? > > > > Do what the intel driver or bpf is doing? It's not difficult to hook > > into cgroup for identification purposes. > > > > Thanks. > > > > -- > > tejun > > ___ > > amd-gfx mailing list > > amd-...@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > > > > > amd-gfx Info Page - freedesktop.org > > lists.freedesktop.org > > To see the collection of prior postings to the list, visit the amd-gfx > > Archives.. Using amd-gfx: To post a message to all the list members, send > > email to amd-...@lists.freedesktop.org. You can subscribe to the list, or > > change your existing subscription, in the sections below. > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/6] Remove all bad dp_mst_port uses and hide struct def
For the series: Acked-by: Ben Skeggs On Sat, 17 Nov 2018 at 10:21, Lyude Paul wrote: > > So we don't ever have to worry about drivers touching drm_dp_mst_port > structs without verifying them and crashing again. > > Lyude Paul (6): > drm/dp_mst: Add drm_dp_get_payload_info() > drm/nouveau: Use drm_dp_get_payload_info() for getting payload/vcpi > drm/nouveau: Stop reading port->mgr in nv50_mstc_get_modes() > drm/nouveau: Stop reading port->mgr in nv50_mstc_detect() > drm/dp_mst: Hide drm_dp_mst_port contents from drivers > drm/i915: Start using struct drm_dp_mst_port again > > drivers/gpu/drm/drm_dp_mst_topology.c | 115 > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > drivers/gpu/drm/i915/intel_drv.h| 2 +- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 60 + > include/drm/drm_dp_mst_helper.h | 65 ++ > 5 files changed, 146 insertions(+), 98 deletions(-) > > -- > 2.19.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev2)
== Series Details == Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev2) URL : https://patchwork.freedesktop.org/series/49669/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5212 -> Patchwork_10921 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49669/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10921 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-kefka: PASS -> FAIL ([fdo#108656]) igt@gem_exec_suspend@basic-s4-devices: fi-ivb-3520m: PASS -> FAIL ([fdo#108880]) fi-blb-e6850: PASS -> INCOMPLETE ([fdo#107718]) igt@i915_selftest@live_hangcheck: fi-bwr-2160:PASS -> DMESG-FAIL ([fdo#108735]) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN ([fdo#105998]) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN ([fdo#102614]) Possible fixes igt@gem_ctx_create@basic-files: fi-bsw-n3050: DMESG-FAIL ([fdo#108656]) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 fdo#108880 https://bugs.freedesktop.org/show_bug.cgi?id=108880 == Participating hosts (51 -> 43) == Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-icl-u3 == Build changes == * Linux: CI_DRM_5212 -> Patchwork_10921 CI_DRM_5212: db8d567e7cf70aeca866e85972078cd5c9b59cfb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4734: 0a961239c27bfbd60c045e6255b2970d4bf84411 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10921: d147afa0255b8eb26dfb36632bb788ef4a118f92 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d147afa0255b drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10921/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Sanitize DDI port clock gating for DSI ports
== Series Details ==
Series: drm/i915/icl: Sanitize DDI port clock gating for DSI ports
URL : https://patchwork.freedesktop.org/series/53093/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10914_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10914_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10914_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10914_full:
=== IGT changes ===
Warnings
igt@kms_chv_cursor_fail@pipe-b-64x64-top-edge:
shard-snb: SKIP -> PASS
igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
shard-snb: PASS -> SKIP +2
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10914_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_ctx_isolation@vcs0-clean:
shard-apl: PASS -> INCOMPLETE ([fdo#103927])
igt@gem_exec_schedule@pi-ringfull-blt:
shard-skl: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_schedule@pi-ringfull-vebox:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_suspend@basic-s3:
shard-kbl: PASS -> INCOMPLETE ([fdo#103665])
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: PASS -> TIMEOUT ([fdo#108039])
igt@gem_pwrite@stolen-uncached:
shard-snb: SKIP -> INCOMPLETE ([fdo#105411])
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
shard-skl: NOTRUN -> DMESG-WARN ([fdo#107956])
igt@kms_color@pipe-a-degamma:
shard-skl: PASS -> FAIL ([fdo#104782], [fdo#108145])
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: PASS -> FAIL ([fdo#103232])
igt@kms_cursor_crc@cursor-128x42-sliding:
shard-glk: PASS -> FAIL ([fdo#103232])
igt@kms_cursor_crc@cursor-64x21-random:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103232])
igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
shard-skl: PASS -> FAIL ([fdo#103184])
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-hsw: PASS -> FAIL ([fdo#102887])
igt@kms_flip_tiling@flip-yf-tiled:
shard-skl: PASS -> FAIL ([fdo#108145])
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
shard-skl: NOTRUN -> FAIL ([fdo#103167]) +2
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
{shard-iclb}: PASS -> FAIL ([fdo#103167]) +4
igt@kms_plane@pixel-format-pipe-b-planes:
shard-apl: PASS -> FAIL ([fdo#103166]) +1
igt@kms_plane@plane-position-covered-pipe-c-planes:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103166])
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL ([fdo#108145])
igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
shard-skl: PASS -> FAIL ([fdo#107815])
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
{shard-iclb}: PASS -> FAIL ([fdo#103166]) +3
igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
shard-glk: PASS -> FAIL ([fdo#103166]) +1
igt@kms_rmfb@rmfb-ioctl:
shard-kbl: PASS -> DMESG-WARN ([fdo#103558], [fdo#105602]) +20
igt@pm_rpm@gem-execbuf:
shard-skl: PASS -> INCOMPLETE ([fdo#107803], [fdo#107807])
igt@pm_rpm@gem-mmap-cpu:
shard-skl: PASS -> INCOMPLETE ([fdo#107807])
igt@pm_rpm@system-suspend-modeset:
shard-skl: PASS -> INCOMPLETE ([fdo#104108], [fdo#107807])
Possible fixes
igt@kms_busy@extended-pageflip-hang-newfb-render-b:
shard-apl: DMESG-WARN ([fdo#107956]) -> PASS
igt@kms_color@pipe-a-legacy-gamma:
shard-skl: FAIL ([fdo#104782], [fdo#108145]) -> PASS
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN ([fdo#105763], [fdo#106538]) -> PASS
igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
shard-glk: FAIL ([fdo#103184]) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-apl: FAIL ([fdo#102887], [fdo#105363]) -> PASS
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
{shard-iclb}: FAIL ([fdo#103167]) -> PASS +5
igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
{shard-iclb}: FAIL ([fdo#103166]) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL ([fdo#99912]) -> PASS
igt@pm_rpm@fences-dpms:
shard-skl: INCOMPLETE ([fdo#107807]) -> PASS +2
Re: [Intel-gfx] [PATCH 1/9] drm/i915: Disable PSR in Apple panels
On Tue, 2018-11-27 at 15:38 +0200, Ville Syrjälä wrote:
> On Mon, Nov 26, 2018 at 04:37:02PM -0800, José Roberto de Souza
> wrote:
> > i915 yet don't support PSR in Apple panels, so lets keep it
> > disabled
> > while we work on that.
> >
> > Fixes: 598c6cfe0690 (drm/i915/psr: Enable PSR1 on gen-9+ HW)
> > Cc: Rodrigo Vivi
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 2 ++
> > drivers/gpu/drm/i915/intel_psr.c | 6 ++
> > include/drm/drm_dp_helper.h | 1 +
> > 3 files changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > b/drivers/gpu/drm/drm_dp_helper.c
> > index 6d483487f2b4..6b5a19d3e347 100644
> > --- a/drivers/gpu/drm/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > @@ -1273,6 +1273,8 @@ static const struct dpcd_quirk
> > dpcd_quirk_list[] = {
> > { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
> > BIT(DP_DPCD_QUIRK_CONSTANT_N) },
> > /* LG LP140WF6-SPM1 eDP panel */
> > { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r',
> > 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
> > + /* Apple panels needs some additional handling to support PSR
> > */
> > + { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false,
> > BIT(DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED) }
> > };
> >
> > #undef OUI
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 572e626eadff..f5d27a02eb28 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -274,6 +274,12 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> > DRM_DEBUG_KMS("Panel lacks power state control, PSR
> > cannot be enabled\n");
> > return;
> > }
> > +
> > + if (drm_dp_has_quirk(_dp->desc,
> > DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED)) {
> > + DRM_DEBUG_KMS("PSR support not currently available for
> > this panel\n");
> > + return;
> > + }
> > +
> > dev_priv->psr.sink_support = true;
> > dev_priv->psr.sink_sync_latency =
> > intel_dp_get_sink_sync_latency(intel_dp);
> > diff --git a/include/drm/drm_dp_helper.h
> > b/include/drm/drm_dp_helper.h
> > index 3314e91f6eb3..db516c48cda3 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1364,6 +1364,7 @@ enum drm_dp_quirk {
> > * to 16 bits. So will give a constant value (0x8000) for
> > compatability.
> > */
> > DP_DPCD_QUIRK_CONSTANT_N,
> > + DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED,
>
> Why such a convoluted name? DP_DPCD_QUIRK_NO_PSR?
Okay changing to DP_DPCD_QUIRK_NO_PSR.
>
> > };
> >
> > /**
> > --
> > 2.19.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev2)
== Series Details == Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev2) URL : https://patchwork.freedesktop.org/series/49669/ State : warning == Summary == $ dim checkpatch origin/drm-tip d147afa0255b drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT -:89: CHECK:LINE_SPACING: Please don't use multiple blank lines #89: FILE: drivers/gpu/drm/i915/intel_dp.c:3843: + + total: 0 errors, 0 warnings, 1 checks, 53 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v12 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v7:
* Remove unnecessary comments, leftovers (Ville)
* No need for explicit val &= ~ (Ville)
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 2 +
drivers/gpu/drm/i915/intel_vdsc.c | 410 ++
3 files changed, 414 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 183aae996305..9dc8731907af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3343,6 +3343,8 @@ extern void intel_rps_mark_interactive(struct
drm_i915_private *i915,
bool interactive);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+void intel_dsc_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fa5ad62cd0db..339be10986d7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3144,6 +3144,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
+
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index b644f69f1c93..0e72520abdfc 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -577,3 +577,413 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+ /*
+* If 2 VDSC instances are needed, configure PPS for second
+* VDSC
+*/
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
+ } else {
+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+ pps_val);
+ }
+
+ /* Populate PICTURE_PARAMETER_SET_1 registers */
+ pps_val = 0;
+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+ DRM_INFO("PPS1 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+
[Intel-gfx] [CI v12 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed-by: Gaurav K Singh
Acked-by: Harry Wentland
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 78db4f61d01c..3292dfed9d0a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
#include
/* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES 15
+#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+#define DSC_RC_PIXELS_PER_GROUP3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
+#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+
+/* Configuration for a single Rate Control model range */
+struct drm_dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie.,
[Intel-gfx] [CI v12 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 572e626eadff..2084784f320d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
if (i915_modparams.enable_psr == -1)
return false;
+ /* Cannot enable DSC and PSR2 simultaneously */
+ WARN_ON(crtc_state->dsc_params.compression_enable &&
+ crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -502,6 +506,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.19.1
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[Intel-gfx] [CI v12 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 2cc933b57d94..c2534142167f 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -998,6 +998,12 @@ static void intel_dp_write_dsc_pps_sdp(struct
intel_encoder *encoder,
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1006,5 +1012,20 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.19.1
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[Intel-gfx] [CI v12 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 16
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad11540ac436..fa5ad62cd0db 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3134,6 +3134,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3491,6 +3493,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ false);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a48d93160c04..b7b2484696a4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2857,6 +2857,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE,
+enable ? DP_DECOMPRESSION_EN : 0);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ enable ? "enable" : "disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 316ec1e107bf..fa452fbb16c6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1797,6 +1797,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.19.1
___
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[Intel-gfx] [CI v12 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v7:
* Use BUILD_BUG_ON() to protect changing struct size (Ville)
* Remove typecaseting (Ville)
* Include byteorder.h in drm_dsc.c (Ville)
* Correct kernel doc spacing (Anusha)
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in
Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 228 ++
include/drm/drm_dsc.h | 21 +++
4 files changed, 262 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index 4b4dc236ef6f..b422eb8edf16 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 1fafc2f8e8f9..e490fe2687db 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index ..bc2b23adb072
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ const struct drm_dsc_config *dsc_cfg)
+{
+ int i;
+
+ /* Protect against someone accidently changing struct size */
+ BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+
+ memset(_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version =
+ dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+
[Intel-gfx] [CI v12 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0e72520abdfc..2cc933b57d94 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -976,6 +976,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(encoder, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -985,5 +1004,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
2.19.1
___
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[Intel-gfx] [CI v12 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5e253f741d29..b41b06dc8347 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -242,6 +242,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1c2de9b69a19..4350a5270423 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2028,9 +2030,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
2.19.1
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[Intel-gfx] [CI v12 08/23] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v14:
Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
v13:
* Compute DSC bpc only when DSC is req to be enabled (Ville)
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Ville Syrjala
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_display.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 192 ---
3 files changed, 172 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22b2a4e..69bb0b75a806 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6724,7 +6724,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5f2955b944da..5e253f741d29 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -423,7 +423,7 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 70ae3d57316b..a2780733768a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1708,6 +1710,26 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ /* FIXME: FEC needed for external DP until then reject DSC on DP */
+ if (!intel_dp_is_edp(intel_dp))
+ return false;
+
+ return INTEL_GEN(dev_priv) >= 10 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A;
+}
+
+static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
+}
+
static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config)
{
@@ -1842,14 +1864,115 @@ intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp,
return false;
}
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+{
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc;
[Intel-gfx] [CI v12 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c| 31
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9dc8731907af..5fe5d8f2d061 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3345,6 +3345,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 69bb0b75a806..7a221fb9ca66 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5889,6 +5889,8 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index c2534142167f..2acbfb69f5f2 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1029,3 +1029,34 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+}
--
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[Intel-gfx] [CI v12 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)
v5: Move to intel_ddi.c
- Make the function static (Anusha)
v6: Dont pass state as a separate argument (Ville)
v7: (From Manasi)
* Correct the debug print (Ville)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6533624226a7..4c74bbe1cf73 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct
intel_digital_port *intel_dig_port)
I915_WRITE(MG_DP_MODE(port, 1), ln1);
}
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
+{
+ if (!crtc_state->fec_enable)
+ return;
+
+ if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION,
DP_FEC_READY) <= 0)
+ DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
--
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[Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
5 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0ff878c994e2..8370b9de6e4f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -157,7 +157,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a2780733768a..a48d93160c04 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1953,6 +1953,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 270212fa43a0..316ec1e107bf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1852,6 +1852,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..0a1918f2f643
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh
+ * Manasi Navare
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+
[Intel-gfx] [CI v12 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
v2:
* Rebase on drm-tip (Manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f763b30f98d9..183aae996305 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include "i915_fixed.h"
#include "i915_params.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a62d77b76291..270212fa43a0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -937,6 +937,15 @@ struct intel_crtc_state {
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
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[Intel-gfx] [CI v12 04/23] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 3292dfed9d0a..b88e31bd9da7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
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[Intel-gfx] [CI v12 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 21 +++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe8f71..eadd880b0ef6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4570,6 +4570,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index e2c6a2b3e8f2..07e803a604bd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ int data_size;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
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[Intel-gfx] [CI v12 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 126 +-
1 file changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0a1918f2f643..b644f69f1c93 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_DEBUG_KMS("FinalOfs < RcModelSze for this
InitialXmitDelay\n");
+ return -ERANGE;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size * 8) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_DEBUG_KMS("NflBpgOffset is too large for this slice
height\n");
+ return -ERANGE;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+
[Intel-gfx] [CI v12 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
--
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[Intel-gfx] [CI v12 20/23] i915/dp/fec: Add fec_enable to the crtc state.
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)
- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)
v3: Check for FEC support along with setting crtc state.
v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)
v5: Move fec check to intel_dp_supports_dsc(Ville)
v6: Remove warning. rebase.
v7: change crtc state to include DP sink and fec capability
of source.(Manasi)
v8: Set fec_enable in crtc in intel_dp_compute_config().
v9 (From Manasi):
* Combine the !edp and !fec_support check
* Derive dev_priv from intel_dp directly
v10 (From Manasi):
* Rebase
Suggested-by: Ville Syrjala
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b7b2484696a4..afee9c76a341 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
- } else {
+ } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
@@ -1710,14 +1710,25 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
-static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
const struct intel_crtc_state
*pipe_config)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- /* FIXME: FEC needed for external DP until then reject DSC on DP */
- if (!intel_dp_is_edp(intel_dp))
- return false;
+ return INTEL_GEN(dev_priv) >= 11 && pipe_config->cpu_transcoder !=
TRANSCODER_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
+ drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
+
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
return INTEL_GEN(dev_priv) >= 10 &&
pipe_config->cpu_transcoder != TRANSCODER_A;
@@ -1726,6 +1737,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp
*intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
+ if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
+ return false;
+
return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
@@ -2129,6 +2143,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
+ pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config);
+
if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
return false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b5693cac26d7..8c582d53c00a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -946,6 +946,9 @@ struct intel_crtc_state {
u8 slice_count;
} dsc_params;
struct drm_dsc_config dp_dsc_cfg;
+
+ /* Forward Error correction State */
+ bool fec_enable;
};
struct intel_crtc {
--
2.19.1
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[Intel-gfx] [CI v12 23/23] drm/i915/fec: Disable FEC state.
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
v6: Resolve warnings. Add crtc_state as an argument to
intel_disable_ddi_buf(). (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 12acdb08a750..61d7145f93bf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3133,6 +3133,22 @@ static void intel_ddi_enable_fec(struct intel_encoder
*encoder,
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3272,7 +3288,8 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
}
}
-static void intel_disable_ddi_buf(struct intel_encoder *encoder)
+static void intel_disable_ddi_buf(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
@@ -3291,6 +3308,9 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder)
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
I915_WRITE(DP_TP_CTL(port), val);
+ /* Disable FEC in DP Sink */
+ intel_ddi_disable_fec_state(encoder, crtc_state);
+
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
}
@@ -3314,7 +3334,7 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
}
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_edp_panel_vdd_on(intel_dp);
intel_edp_panel_off(intel_dp);
@@ -3337,7 +3357,7 @@ static void intel_ddi_post_disable_hdmi(struct
intel_encoder *encoder,
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
@@ -3388,7 +3408,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder
*encoder,
val &= ~FDI_RX_ENABLE;
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_ddi_clk_disable(encoder);
val = I915_READ(FDI_RX_MISC(PIPE_A));
--
2.19.1
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[Intel-gfx] [CI v12 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c | 26 ++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 339be10986d7..6533624226a7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2154,6 +2154,12 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+ /*
+* VDSC power is needed when DSC is enabled
+*/
+ if (crtc_state->dsc_params.compression_enable)
+ domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fa452fbb16c6..b5693cac26d7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1858,6 +1858,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp, int mode_clock,
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 2acbfb69f5f2..17ef78652f71 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -578,6 +578,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ /*
+* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* For any other transcoder, VDSC/joining uses the power well associated
+* with the pipe/transcoder in use. Hence another reference on the
+* transcoder power domain will suffice.
+*/
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else
+ return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
@@ -1008,6 +1026,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
+ /* Enable Power wells for VDSC/joining */
+ intel_display_power_get(dev_priv,
+ intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1059,4 +1081,8 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+ /* Disable Power wells for VDSC/joining */
+ intel_display_power_put(dev_priv,
+ intel_dsc_power_domain(old_crtc_state));
}
--
2.19.1
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[Intel-gfx] [CI v12 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.
v2:
* Simplify the logic (Ville)
Signed-off-by: Manasi Navare
Cc: Ville Syrjala
Reviewed-by: Ville Syrjala
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/drm_dp_helper.c | 14 --
include/drm/drm_dp_helper.h | 3 ++-
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 6d483487f2b4..2d6c491a0542 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1428,17 +1428,19 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
}
EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+u8 dsc_bpc[3])
{
+ int num_bpc = 0;
u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
if (color_depth & DP_DSC_12_BPC)
- return 12;
+ dsc_bpc[num_bpc++] = 12;
if (color_depth & DP_DSC_10_BPC)
- return 10;
+ dsc_bpc[num_bpc++] = 10;
if (color_depth & DP_DSC_8_BPC)
- return 8;
+ dsc_bpc[num_bpc++] = 8;
- return 0;
+ return num_bpc;
}
-EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
+EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3314e91f6eb3..5736c942c85b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1123,7 +1123,8 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
+u8 dsc_bpc[3]);
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
--
2.19.1
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[Intel-gfx] [CI v12 22/23] i915/dp/fec: Configure the Forward Error Correction bits.
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.
v6: Pass intel_encoder, instead of intel_dp. (Ville)
v7: Remove unwanted comments (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eadd880b0ef6..d3ef97915455 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9198,6 +9198,7 @@ enum skl_power_gate {
#define _DP_TP_CTL_B 0x64140
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
#define DP_TP_CTL_ENABLE (1 << 31)
+#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
@@ -9216,6 +9217,7 @@ enum skl_power_gate {
#define _DP_TP_STATUS_A0x64044
#define _DP_TP_STATUS_B0x64144
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE(1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4c74bbe1cf73..12acdb08a750 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3112,6 +3112,27 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp
*intel_dp,
DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
}
+static void intel_ddi_enable_fec(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val |= DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ 1))
+ DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3157,6 +3178,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
+ intel_ddi_enable_fec(encoder, crtc_state);
+
icl_enable_phy_clock_gating(dig_port);
if (!is_mst)
--
2.19.1
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[Intel-gfx] [CI v12 02/23] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
v4:
* Remove redundant blankline in doc (Ville)
* use drm_dsc namespace for all structs (Ville)
* Use packed struct (Ville)
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
---
include/drm/drm_dsc.h | 342 ++
1 file changed, 342 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index ..78db4f61d01c
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct drm_dsc_picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16 pic_width;
+ /**
+* @slice_height:
+* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+*/
+ __be16 slice_height;
+ /**
+* @slice_width:
+* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+*/
+ __be16 slice_width;
+ /**
+* @chunk_size:
+* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+* that are used for slice multiplexing.
+*/
+ __be16 chunk_size;
+ /**
+* @initial_xmit_delay_high:
+* PPS16[1:0] - Most Significant two bits of initial transmission delay.
+* It specifies the number of pixel times that the encoder waits before
+* transmitting data from its rate buffer.
+* PPS16[7:2] - Reserved
+*/
+
Re: [Intel-gfx] [Nouveau] [PATCH 1/6] drm/dp_mst: Add drm_dp_get_payload_info()
On Tue, 2018-11-27 at 22:23 +0100, Daniel Vetter wrote:
> On Fri, Nov 16, 2018 at 07:21:15PM -0500, Lyude Paul wrote:
> > Some hardware (nvidia hardware in particular) needs to be notified of
> > the exact VCPI and payload settings that the topology manager decided on
> > for each mstb port. Since there isn't currently any way to get this
> > information without going through port (which drivers are very much not
> > supposed to do by themselves, ever), let's add one.
> >
> > Signed-off-by: Lyude Paul
> > ---
> > drivers/gpu/drm/drm_dp_mst_topology.c | 56 +++
> > include/drm/drm_dp_mst_helper.h | 5 ++-
> > 2 files changed, 60 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > index 529414556962..4336d17ce904 100644
> > --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> > @@ -1982,6 +1982,62 @@ int drm_dp_update_payload_part2(struct
> > drm_dp_mst_topology_mgr *mgr)
> > }
> > EXPORT_SYMBOL(drm_dp_update_payload_part2);
> >
> > +/**
> > + * drm_dp_get_payload_info() - Retrieve payload/vcpi information for the
> > given
> > + * @port
> > + * @mgr: manager to use
> > + * @port: the port to get the relevant payload information for
> > + * @vcpi_out: where to copy the port's VCPI information to
> > + * @payload_out: where to copy the port's payload information to
> > + *
> > + * Searches the current payloads for @mgr and finds the relevant payload
> > and
> > + * VCPI information that was programmed by the topology mgr, then copies
> > it
> > + * into @vcpi_out and @payload_out. Drivers which need to know this
> > + * information must use this helper as opposed to checking @port
> > themselves,
> > + * as this helper will ensure the port reference is still valid and grab
> > the
> > + * appropriate locks in @mgr.
> > + *
> > + * Returns:
> > + * 0 on success, negative error code if the port is no longer valid or a
> > + * programmed payload could not be found for @port.
> > + */
> > +int drm_dp_get_payload_info(struct drm_dp_mst_topology_mgr *mgr,
> > + struct drm_dp_mst_port *port,
> > + struct drm_dp_vcpi *vcpi_out,
> > + struct drm_dp_payload *payload_out)
> > +{
> > + struct drm_dp_payload *payload = NULL;
> > + int i;
> > + int ret = 0;
> > +
> > + port = drm_dp_get_validated_port_ref(mgr, port);
> > + if (!port)
> > + return -EINVAL;
>
> This is the part that I mean in our other/irc discussions. The
> dp_get_validated_port here could fail when it's going to surprise the
> driver. With the dp_port_malloc_get stuff we could instead just grab a
> port_malloc_kref when storing the port in mgr->payload, which would
> guarantee that the port based lookup below still works.
Yeah, that makes more sense now that there's context :P, sgtm.
>
> > +
> > + mutex_lock(>payload_lock);
> > + /* Figure out which of the payloads belongs to this port */
> > + for (i = 0; i < mgr->max_payloads; i++) {
> > + if (mgr->payloads[i].vcpi == port->vcpi.vcpi) {
>
> Or maybe even rework the lookup here to use the port pointer (as an
> abstract key) instead of port->vcpi.vcpi. With port_malloc_kref we could
> guarantee that it keeps working, even after the port has been destroyed.
>
> And (without checking) I think that's needed anyway to clean up the
> payload update hacks in the connector destroy work ...
> -Daniel
>
> > + payload = >payloads[i];
> > + break;
> > + }
> > + }
> > +
> > + if (!payload) {
> > + DRM_DEBUG_KMS("Failed to find payload for port %p\n", port);
> > + ret = -EINVAL;
> > + goto out;
> > + }
> > +
> > + *payload_out = *payload;
> > + *vcpi_out = port->vcpi;
> > +out:
> > + mutex_unlock(>payload_lock);
> > + drm_dp_put_port(port);
> > + return ret;
> > +}
> > +EXPORT_SYMBOL(drm_dp_get_payload_info);
> > +
> > #if 0 /* unused as of yet */
> > static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr,
> > struct drm_dp_mst_port *port,
> > diff --git a/include/drm/drm_dp_mst_helper.h
> > b/include/drm/drm_dp_mst_helper.h
> > index 59f005b419cf..9cc93ea60e7e 100644
> > --- a/include/drm/drm_dp_mst_helper.h
> > +++ b/include/drm/drm_dp_mst_helper.h
> > @@ -592,7 +592,10 @@ bool drm_dp_mst_allocate_vcpi(struct
> > drm_dp_mst_topology_mgr *mgr,
> > struct drm_dp_mst_port *port, int pbn, int
> > slots);
> >
> > int drm_dp_mst_get_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct
> > drm_dp_mst_port *port);
> > -
> > +int drm_dp_get_payload_info(struct drm_dp_mst_topology_mgr *mgr,
> > + struct drm_dp_mst_port *port,
> > + struct drm_dp_vcpi *vcpi_out,
> > + struct drm_dp_payload
Re: [Intel-gfx] [Nouveau] [PATCH 1/6] drm/dp_mst: Add drm_dp_get_payload_info()
On Fri, Nov 16, 2018 at 07:21:15PM -0500, Lyude Paul wrote:
> Some hardware (nvidia hardware in particular) needs to be notified of
> the exact VCPI and payload settings that the topology manager decided on
> for each mstb port. Since there isn't currently any way to get this
> information without going through port (which drivers are very much not
> supposed to do by themselves, ever), let's add one.
>
> Signed-off-by: Lyude Paul
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 56 +++
> include/drm/drm_dp_mst_helper.h | 5 ++-
> 2 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 529414556962..4336d17ce904 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -1982,6 +1982,62 @@ int drm_dp_update_payload_part2(struct
> drm_dp_mst_topology_mgr *mgr)
> }
> EXPORT_SYMBOL(drm_dp_update_payload_part2);
>
> +/**
> + * drm_dp_get_payload_info() - Retrieve payload/vcpi information for the
> given
> + * @port
> + * @mgr: manager to use
> + * @port: the port to get the relevant payload information for
> + * @vcpi_out: where to copy the port's VCPI information to
> + * @payload_out: where to copy the port's payload information to
> + *
> + * Searches the current payloads for @mgr and finds the relevant payload and
> + * VCPI information that was programmed by the topology mgr, then copies it
> + * into @vcpi_out and @payload_out. Drivers which need to know this
> + * information must use this helper as opposed to checking @port themselves,
> + * as this helper will ensure the port reference is still valid and grab the
> + * appropriate locks in @mgr.
> + *
> + * Returns:
> + * 0 on success, negative error code if the port is no longer valid or a
> + * programmed payload could not be found for @port.
> + */
> +int drm_dp_get_payload_info(struct drm_dp_mst_topology_mgr *mgr,
> + struct drm_dp_mst_port *port,
> + struct drm_dp_vcpi *vcpi_out,
> + struct drm_dp_payload *payload_out)
> +{
> + struct drm_dp_payload *payload = NULL;
> + int i;
> + int ret = 0;
> +
> + port = drm_dp_get_validated_port_ref(mgr, port);
> + if (!port)
> + return -EINVAL;
This is the part that I mean in our other/irc discussions. The
dp_get_validated_port here could fail when it's going to surprise the
driver. With the dp_port_malloc_get stuff we could instead just grab a
port_malloc_kref when storing the port in mgr->payload, which would
guarantee that the port based lookup below still works.
> +
> + mutex_lock(>payload_lock);
> + /* Figure out which of the payloads belongs to this port */
> + for (i = 0; i < mgr->max_payloads; i++) {
> + if (mgr->payloads[i].vcpi == port->vcpi.vcpi) {
Or maybe even rework the lookup here to use the port pointer (as an
abstract key) instead of port->vcpi.vcpi. With port_malloc_kref we could
guarantee that it keeps working, even after the port has been destroyed.
And (without checking) I think that's needed anyway to clean up the
payload update hacks in the connector destroy work ...
-Daniel
> + payload = >payloads[i];
> + break;
> + }
> + }
> +
> + if (!payload) {
> + DRM_DEBUG_KMS("Failed to find payload for port %p\n", port);
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + *payload_out = *payload;
> + *vcpi_out = port->vcpi;
> +out:
> + mutex_unlock(>payload_lock);
> + drm_dp_put_port(port);
> + return ret;
> +}
> +EXPORT_SYMBOL(drm_dp_get_payload_info);
> +
> #if 0 /* unused as of yet */
> static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr,
>struct drm_dp_mst_port *port,
> diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
> index 59f005b419cf..9cc93ea60e7e 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -592,7 +592,10 @@ bool drm_dp_mst_allocate_vcpi(struct
> drm_dp_mst_topology_mgr *mgr,
> struct drm_dp_mst_port *port, int pbn, int slots);
>
> int drm_dp_mst_get_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct
> drm_dp_mst_port *port);
> -
> +int drm_dp_get_payload_info(struct drm_dp_mst_topology_mgr *mgr,
> + struct drm_dp_mst_port *port,
> + struct drm_dp_vcpi *vcpi_out,
> + struct drm_dp_payload *payload_out);
>
> void drm_dp_mst_reset_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct
> drm_dp_mst_port *port);
>
> --
> 2.19.1
>
> ___
> Nouveau mailing list
> nouv...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/nouveau
--
[Intel-gfx] [PATCH] drm/i915/ringbuffer: Clear semaphore sync registers on ring init
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e18a64d41843..82c844488755 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -529,6 +529,13 @@ static int init_ring_common(struct intel_engine_cs *engine)
intel_engine_reset_breadcrumbs(engine);
+ if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
+ I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
+ I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
+ if (HAS_VEBOX(dev_priv))
+ I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
+ }
+
/* Enforce ordering by reading HEAD register back */
I915_READ_HEAD(engine);
--
2.20.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/icl: Enable Y210, Y212, Y216 format for primary and sprite planes
Swati Sharma kirjoitti 22.10.2018 klo 8.31:
From: Vidya Srinivas
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
v3: since support for planar formats on ICL was getting totally
skipped, added support for the same in intel_display.c and
intel_sprite.c. (juha)
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 58
drivers/gpu/drm/i915/intel_sprite.c | 42 --
2 files changed, 92 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 98f2939..f83fbb4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -105,6 +105,42 @@
DRM_FORMAT_NV12,
};
+static const uint32_t icl_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
+static const uint32_t icl_pri_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13788,16 +13824,26 @@ bool skl_plane_has_planar(struct drm_i915_private
*dev_priv,
fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
}
+
^^ stray newline?
The next if(){}else{} I would write separating gen11 from gen9 because
you need both tables, primary_formats as well as pri_planar_formats, for
gen11.
So, instead of having
if(>=gen9) {
if(>=gen11) {
..
} else {
..
}
}
I'd write it like
if(>=gen11) {
..
} else if(>=gen9) {
..
} els...
I think it will be much easier to read. Same below in intel_sprite.c
/Juha-Pekka
if (INTEL_GEN(dev_priv) >= 9) {
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
-PLANE_PRIMARY);
-
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ PLANE_PRIMARY);
+
+ if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_PRIMARY)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ intel_primary_formats = icl_primary_formats;
+ num_formats = ARRAY_SIZE(icl_primary_formats);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
+ } else if (INTEL_GEN(dev_priv) >= 11) {
+ intel_primary_formats = icl_pri_planar_formats;
+ num_formats = ARRAY_SIZE(icl_pri_planar_formats);
+ } else {
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
- } else {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
}
if (primary->has_ccs)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c831360..7d9b3e4 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1564,6 +1564,36 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_NV12,
};
+static uint32_t icl_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
+static uint32_t icl_planar_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for Add Colorspace connector property interface (rev4)
== Series Details ==
Series: Add Colorspace connector property interface (rev4)
URL : https://patchwork.freedesktop.org/series/47132/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5211_full -> Patchwork_10913_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10913_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10913_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10913_full:
=== IGT changes ===
Possible regressions
igt@kms_sequence@queue-busy:
shard-skl: NOTRUN -> FAIL
Warnings
igt@kms_chv_cursor_fail@pipe-b-64x64-top-edge:
shard-snb: SKIP -> PASS
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10913_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@drm_import_export@import-close-race-flink:
shard-skl: PASS -> TIMEOUT ([fdo#108667])
igt@gem_exec_reuse@contexts:
shard-apl: PASS -> INCOMPLETE ([fdo#103927])
igt@gem_exec_schedule@pi-ringfull-blt:
shard-skl: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_schedule@pi-ringfull-vebox:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103158])
igt@gem_exec_suspend@basic-s3:
shard-kbl: PASS -> INCOMPLETE ([fdo#103665])
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: PASS -> TIMEOUT ([fdo#108039])
igt@kms_atomic_transition@1x-modeset-transitions-fencing:
shard-skl: NOTRUN -> FAIL ([fdo#108470])
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
shard-skl: NOTRUN -> DMESG-WARN ([fdo#107956])
igt@kms_chv_cursor_fail@pipe-c-128x128-right-edge:
shard-skl: NOTRUN -> FAIL ([fdo#104671])
igt@kms_color@pipe-a-ctm-0-25:
shard-skl: PASS -> FAIL ([fdo#108682])
igt@kms_color@pipe-c-legacy-gamma:
shard-skl: PASS -> FAIL ([fdo#104782])
igt@kms_cursor_crc@cursor-256x256-onscreen:
shard-glk: PASS -> FAIL ([fdo#103232]) +1
igt@kms_cursor_crc@cursor-64x21-random:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103232])
igt@kms_cursor_crc@cursor-64x64-sliding:
shard-apl: PASS -> FAIL ([fdo#103232]) +3
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: PASS -> FAIL ([fdo#103191], [fdo#103232])
igt@kms_draw_crc@draw-method-xrgb-render-untiled:
shard-skl: NOTRUN -> FAIL ([fdo#103184])
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL ([fdo#105363])
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
shard-skl: NOTRUN -> FAIL ([fdo#105682])
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
shard-apl: PASS -> FAIL ([fdo#103167]) +4
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
{shard-iclb}: PASS -> FAIL ([fdo#103167])
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
shard-skl: NOTRUN -> FAIL ([fdo#103167]) +2
igt@kms_frontbuffer_tracking@fbcpsr-suspend:
shard-skl: PASS -> INCOMPLETE ([fdo#104108], [fdo#106978])
igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
shard-skl: NOTRUN -> FAIL ([fdo#103191], [fdo#107362])
igt@kms_plane@plane-position-covered-pipe-c-planes:
{shard-iclb}: NOTRUN -> FAIL ([fdo#103166])
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL ([fdo#108145]) +1
igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
shard-skl: NOTRUN -> FAIL ([fdo#107815])
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
{shard-iclb}: PASS -> FAIL ([fdo#103166])
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
shard-apl: PASS -> FAIL ([fdo#103166]) +3
igt@kms_psr@no_drrs:
{shard-iclb}: PASS -> FAIL ([fdo#108341])
igt@kms_rotation_crc@primary-rotation-90:
shard-skl: NOTRUN -> FAIL ([fdo#103925], [fdo#107815])
igt@pm_rpm@gem-pread:
shard-skl: PASS -> INCOMPLETE ([fdo#107807])
igt@pm_rpm@sysfs-read:
{shard-iclb}: PASS -> INCOMPLETE ([fdo#107713], [fdo#108840])
Possible fixes
igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
shard-skl: FAIL ([fdo#104671]) -> PASS
igt@kms_color@pipe-a-legacy-gamma:
shard-skl: FAIL ([fdo#104782], [fdo#108145]) -> PASS
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/icl: Add Y210, Y212, Y216 plane control definitions
I did earlier give R-b for this patch. The patch anyway hasn't changed
as those defines have not changed.
/Juha-Pekka
Swati Sharma kirjoitti 22.10.2018 klo 8.31:
From: Vidya Srinivas
Added needed plane control flag definitions for Y210, Y212 and
Y216 formats.
v3: no change
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507..cbb2917 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6506,6 +6506,9 @@ enum {
#define PLANE_CTL_FORMAT_RGB_565(14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
+#define PLANE_CTL_FORMAT_Y210(1 << 23)
+#define PLANE_CTL_FORMAT_Y212(3 << 23)
+#define PLANE_CTL_FORMAT_Y216(5 << 23)
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21)
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix TV encoder support (rev5)
== Series Details ==
Series: drm/i915: Fix TV encoder support (rev5)
URL : https://patchwork.freedesktop.org/series/52378/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10920 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/52378/revisions/5/mbox/
== Known issues ==
Here are the changes found in Patchwork_10920 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_exec_suspend@basic-s4-devices:
fi-ivb-3520m: PASS -> FAIL ([fdo#108880])
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: PASS -> DMESG-WARN ([fdo#105998])
igt@kms_frontbuffer_tracking@basic:
{fi-icl-u3}:PASS -> FAIL ([fdo#103167])
Possible fixes
igt@i915_module_load@reload:
fi-blb-e6850: INCOMPLETE ([fdo#107718]) -> PASS
igt@i915_selftest@live_hangcheck:
fi-cfl-8109u: INCOMPLETE ([fdo#106070]) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-WARN ([fdo#102614]) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: FAIL ([fdo#107362]) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-byt-clapper: FAIL ([fdo#103191], [fdo#107362]) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-cfl-8109u: DMESG-WARN ([fdo#106107]) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108880 https://bugs.freedesktop.org/show_bug.cgi?id=108880
== Participating hosts (51 -> 45) ==
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-snb-2600
== Build changes ==
* Linux: CI_DRM_5211 -> Patchwork_10920
CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10920: c07c3bae1ed1cb76147b294d469eb6a59e241a87 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c07c3bae1ed1 drm/i915/tv: Filter out >1024 wide modes that would need vertical
scaling on gen3
58f23f67a2d0 drm/i915/tv: Fix >1024 modes on gen3
9f80e4bca57d drm/i915/tv: Generate better pipe timings for TV encoder
090d9895cab2 drm/i915/tv: Add 1080p30/50/60 TV modes
3938af790529 drm/i915/tv: Nuke reported_modes[]
3843e6fbfd73 drm/i915/tv: Make TV mode autoselection actually useable
554460968989 drm/i915/tv: Use drm_mode_set_name() to name TV modes
9a0d12af09b2 drm/i915/tv: Deobfuscate preferred mode selection
dbcb06f0dbb5 drm/i915/tv: Nuke silly 0 initialzation of xpos/ypos
4198959702ba drm/i915/tv: Use bools where appropriate
57d0c552757f drm/i915/tv: Store the TV oversampling factor in the TV mode
0e2acc87b153 drm/i915/tv: Fix tv mode clocks
c2ee18a09a71 drm/i915/tv: Fix interlaced ysize calculation
18faa03a3c3e drm/i915: Don't try to use the hardware frame counter with i965gm
TV output
af05bf07d808 drm/vblank: Allow dynamic per-crtc max_vblank_count
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10920/
___
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[Intel-gfx] [PATCH v7] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
From: Matt Atwood
According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 0h through Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.
There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 0h through Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.
This patch helps with backward compatibility for devices pre DP1.3.
v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.
v3: white space fixes
v4: make path dependent on DPCD revision > 1.2
v5: split into function, removed DPCD rev check
v6: add debugging prints for early exit conditions
v7 (From Manasi):
* Memcpy, memcmp and debig logging based on sizeof(dpcd_ext) (Jani N)
* Exit early (Jani N)
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Matt Atwood
Tested-by: Manasi Navare
Acked-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 41 +
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 70ae3d57316b..a9eb14a4ab27 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3802,6 +3802,45 @@ intel_dp_link_down(struct intel_encoder *encoder,
}
}
+static void
+intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
+{
+ u8 dpcd_ext[6];
+
+ /*
+* Prior to DP1.3 the bit represented by
+* DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
+* if it is set DP_DPCD_REV at h could be at a value less than
+* the true capability of the panel. The only way to check is to
+* then compare h and 2200h.
+*/
+ if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
+ return;
+
+ DRM_DEBUG_KMS("DPCD: Reading extended receiver capabilities\n");
+
+ if (drm_dp_dpcd_read(_dp->aux, DP_DP13_DPCD_REV,
+_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
+ DRM_ERROR("DPCD failed read at extended capabilities\n");
+ return;
+ }
+ if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
+ DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD
rev\n");
+ return;
+ }
+ if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext))) {
+ DRM_DEBUG_KMS("Extended Receiver Cap DPCD match the base
DPCD\n");
+ return;
+ }
+
+ DRM_DEBUG_KMS("Base DPCD: %*ph\n", (int)sizeof(dpcd_ext),
intel_dp->dpcd);
+ DRM_DEBUG_KMS("Extended Receiver Cap DPCD: %*ph\n",
+ (int)sizeof(dpcd_ext), dpcd_ext);
+ memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
+}
+
+
bool
intel_dp_read_dpcd(struct intel_dp *intel_dp)
{
@@ -3809,6 +3848,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
sizeof(intel_dp->dpcd)) < 0)
return false; /* aux transfer failed */
+ intel_dp_extended_receiver_capabilities(intel_dp);
+
DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd),
intel_dp->dpcd);
return intel_dp->dpcd[DP_DPCD_REV] != 0;
--
2.19.1
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Re: [Intel-gfx] [PATCH i-g-t 4/4] igt/v3d_*: Add new tests for the V3D UABI.
Petri Latvala writes: > On Mon, Nov 26, 2018 at 12:46:46PM -0800, Eric Anholt wrote: >> Petri Latvala writes: >> >> > On Wed, Nov 14, 2018 at 02:28:32PM -0800, Eric Anholt wrote: >> >> These are basic non-rendering tests of the UABI. >> >> >> >> Signed-off-by: Eric Anholt >> >> --- >> >> lib/igt_v3d.c | 4 -- >> >> tests/Makefile.am | 2 + >> >> tests/Makefile.sources| 6 +++ >> >> tests/meson.build | 3 ++ >> >> tests/v3d_ci/README | 26 + >> >> tests/v3d_ci/v3d.testlist | 6 +++ >> >> tests/v3d_get_bo_offset.c | 78 ++ >> >> tests/v3d_get_param.c | 80 +++ >> >> tests/v3d_mmap.c | 55 +++ >> > >> > >> > Do you need a separate directory for v3d or can you use the vc4 >> > directory for v3d as well? Renamed to 'broadcom-ci' maybe? >> >> Do we really need to introduce the vendor name separate from the driver >> name? I guess intel_ci makes some sense if it's used by Intel's CI, but >> these are just the test lists for anyone that happens to use igt for >> this driver. > > Fair enough, I was assuming there's an active CI somewhere that used > both at the same time. > > > > Acked-by: Petri Latvala Thanks for taking a look at these and acking them! signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 4/5] drm: Add library for shmem backed GEM objects
Daniel Vetter writes:
> On Mon, Nov 26, 2018 at 04:36:21PM -0800, Eric Anholt wrote:
>> Noralf Trønnes writes:
>> > +static void drm_gem_shmem_vm_close(struct vm_area_struct *vma)
>> > +{
>> > + struct drm_gem_object *obj = vma->vm_private_data;
>> > + struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
>> > +
>> > + drm_gem_shmem_put_pages(shmem);
>> > + drm_gem_vm_close(vma);
>> > +}
>> > +
>> > +const struct vm_operations_struct drm_gem_shmem_vm_ops = {
>> > + .fault = drm_gem_shmem_fault,
>> > + .open = drm_gem_vm_open,
>> > + .close = drm_gem_shmem_vm_close,
>> > +};
>> > +EXPORT_SYMBOL_GPL(drm_gem_shmem_vm_ops);
>>
>> I just saw a warning from drm_gem_shmem_put_pages() for
>> !shmem->pages_use_count -- I think drm_gem_vm_open() needs to
>> drm_gem_shmem_get_pages().
>
> Yeah we need a drm_gem_shmem_vm_open here.
Adding one of those fixed my refcounting issues, so I've sent out a v6
with it.
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix TV encoder support (rev5)
== Series Details == Series: drm/i915: Fix TV encoder support (rev5) URL : https://patchwork.freedesktop.org/series/52378/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/vblank: Allow dynamic per-crtc max_vblank_count Okay! Commit: drm/i915: Don't try to use the hardware frame counter with i965gm TV output Okay! Commit: drm/i915/tv: Fix interlaced ysize calculation Okay! Commit: drm/i915/tv: Fix tv mode clocks Okay! Commit: drm/i915/tv: Store the TV oversampling factor in the TV mode Okay! Commit: drm/i915/tv: Use bools where appropriate Okay! Commit: drm/i915/tv: Nuke silly 0 initialzation of xpos/ypos Okay! Commit: drm/i915/tv: Deobfuscate preferred mode selection Okay! Commit: drm/i915/tv: Use drm_mode_set_name() to name TV modes Okay! Commit: drm/i915/tv: Make TV mode autoselection actually useable Okay! Commit: drm/i915/tv: Nuke reported_modes[] Okay! Commit: drm/i915/tv: Add 1080p30/50/60 TV modes Okay! Commit: drm/i915/tv: Generate better pipe timings for TV encoder Okay! Commit: drm/i915/tv: Fix >1024 modes on gen3 +drivers/gpu/drm/i915/intel_tv.c:889:28: warning: symbol 'intel_tv_connector_duplicate_state' was not declared. Should it be static? Commit: drm/i915/tv: Filter out >1024 wide modes that would need vertical scaling on gen3 Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 02/15] drm/i915: Don't try to use the hardware frame counter with i965gm TV output
From: Ville Syrjälä
On i965gm the hardware frame counter does not work when
the TV encoder is active. So let's not try to consult
the hardware frame counter in that case. Instead we'll
fall back to the timestamp based guesstimation method
used on gen2.
Note that the pipe timings generated by the TV encoder
are also rather peculiar. Apparently the pipe wants to
run at a much higher speed (related to the oversample
clock somehow it seems) but during the vertical active
period the TV encoder stalls the pipe every few lines
to keep its speed in check. But once the vertical
blanking period is reached the pipe gets to run at full
speed. This means our vblank timestamp estimates are
suspect. Fixing all that would require quite a bit
more work. This simple fix at least avoids the nasty
vblank timeouts that are happening currently.
Curiously the frame counter works just fine on i945gm
and gm45. I don't really understand what kind of mishap
occurred with the hardware design on i965gm. Sadly
I wasn't able to find any chicken bits etc. that would
fix the frame counter :(
v2: Move the zero vs. non-zero hw counter value handling
into i915_get_vblank_counter() (Daniel)
Use the per-crtc maximum exclusively, leaving the
per-device maximum at zero
v3: max_vblank_count not populated yet in intel_enable_pipe()
use intel_crtc_max_vblank_count() instead
Cc: sta...@vger.kernel.org
Cc: Daniel Vetter
Fixes: 51e31d49c890 ("drm/i915: Use generic vblank wait")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93782
Signed-off-by: Ville Syrjälä
fix#_slub_broken.S
---
drivers/gpu/drm/i915/i915_irq.c | 27 ++--
drivers/gpu/drm/i915/intel_display.c | 48 +++-
2 files changed, 58 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d447d7d508f4..ab2d4eefef18 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -822,11 +822,26 @@ static void i915_enable_asle_pipestat(struct
drm_i915_private *dev_priv)
static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_vblank_crtc *vblank = >vblank[pipe];
+ const struct drm_display_mode *mode = >hwmode;
i915_reg_t high_frame, low_frame;
u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
- const struct drm_display_mode *mode = >vblank[pipe].hwmode;
unsigned long irqflags;
+ /*
+* On i965gm TV output the frame counter only works up to
+* the point when we enable the TV encoder. After that the
+* frame counter ceases to work and reads zero. We need a
+* vblank wait before enabling the TV encoder and so we
+* have to enable vblank interrupts while the frame counter
+* is still in a working state. However the core vblank code
+* does not like us returning non-zero frame counter values
+* when we've told it that we don't have a working frame
+* counter. Thus we must stop non-zero values leaking out.
+*/
+ if (!vblank->max_vblank_count)
+ return 0;
+
htotal = mode->crtc_htotal;
hsync_start = mode->crtc_hsync_start;
vbl_start = mode->crtc_vblank_start;
@@ -4836,16 +4851,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 8)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
- if (IS_GEN2(dev_priv)) {
- /* Gen2 doesn't have a hardware frame counter */
- dev->max_vblank_count = 0;
- } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
- dev->max_vblank_count = 0x; /* full 32 bit counter */
+ if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
dev->driver->get_vblank_counter = g4x_get_vblank_counter;
- } else {
+ else if (INTEL_GEN(dev_priv) >= 3)
dev->driver->get_vblank_counter = i915_get_vblank_counter;
- dev->max_vblank_count = 0xff; /* only 24 bits of frame
count */
- }
/*
* Opt out of the vblank disable timer on everything except gen2.
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22b2a4e..cb13eff78ad9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1754,6 +1754,35 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc
*crtc)
return crtc->pipe;
}
+static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+ /*
+* On i965gm the hardware frame counter reads
+* zero when the TV encoder is enabled :(
+*/
+ if (IS_I965GM(dev_priv) &&
+ (crtc_state->output_types
Re: [Intel-gfx] [PATCH v6 3/6] drm/dp_mst: Start tracking per-port VCPI allocations
On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote: > On Mon, 2018-11-26 at 22:22 +0100, Daniel Vetter wrote: > > On Mon, Nov 26, 2018 at 10:04:21PM +0100, Daniel Vetter wrote: > > > On Thu, Nov 15, 2018 at 07:50:05PM -0500, Lyude Paul wrote: > > > > There has been a TODO waiting for quite a long time in > > > > drm_dp_mst_topology.c: > > > > > > > > /* We cannot rely on port->vcpi.num_slots to update > > > > * topology_state->avail_slots as the port may not exist if the > > > > parent > > > > * branch device was unplugged. This should be fixed by tracking > > > > * per-port slot allocation in drm_dp_mst_topology_state > > > > instead of > > > > * depending on the caller to tell us how many slots to release. > > > > */ > > > > > > > > That's not the only reason we should fix this: forcing the driver to > > > > track the VCPI allocations throughout a state's atomic check is > > > > error prone, because it means that extra care has to be taken with the > > > > order that drm_dp_atomic_find_vcpi_slots() and > > > > drm_dp_atomic_release_vcpi_slots() are called in in order to ensure > > > > idempotency. Currently the only driver actually using these helpers, > > > > i915, doesn't even do this correctly: multiple ->best_encoder() checks > > > > with i915's current implementation would not be idempotent and would > > > > over-allocate VCPI slots, something I learned trying to implement > > > > fallback retraining in MST. > > > > > > > > So: simplify this whole mess, and teach drm_dp_atomic_find_vcpi_slots() > > > > and drm_dp_atomic_release_vcpi_slots() to track the VCPI allocations for > > > > each port. This allows us to ensure idempotency without having to rely > > > > on the driver as much. Additionally: the driver doesn't need to do any > > > > kind of VCPI slot tracking anymore if it doesn't need it for it's own > > > > internal state. > > > > > > > > Additionally; this adds a new drm_dp_mst_atomic_check() helper which > > > > must be used by atomic drivers to perform validity checks for the new > > > > VCPI allocations incurred by a state. > > > > > > > > Also: update the documentation and make it more obvious that these > > > > /must/ be called by /all/ atomic drivers supporting MST. > > > > > > > > Changes since v6: > > > > - Keep a kref to all of the ports we have allocations on. This required > > > >a good bit of changing to when we call drm_dp_find_vcpi_slots(), > > > >mainly that we need to ensure that we only redo VCPI allocations on > > > >actual mode or CRTC changes, not crtc_state->active changes. > > > >Additionally, we no longer take the registration of the DRM connector > > > >for each port into account because so long as we have a kref to the > > > >port in the new or previous atomic state, the connector will stay > > > >registered. > > > > > > I write an entire pile of small nitpits (still included most of them > > > below), until I realized this here wont work. Delaying the call to destroy > > > the connector (well, unregister it really) wreaks the design we've come up > > > with thus far, resulting in most of my comments here. > > > > > > Instead, all we need to do is delay the kfree(port) at the bottom of > > > drm_dp_destroy_port(). The vcpi allocation structure _only_ needs the > > > pointer value to stay valid, as a lookup key. It doesn't care at all about > > > anything actually stored in there. So the only thing we need to delay is > > > the kfree. I think the simplest way to achieve this is to add a 2nd kref > > > (port->kfree_ref or something like that), with on reference held by the > > > port itself (released in drm_dp_destroy_port), and the other one held > > > as-needed by the vcpi allocation lists. > > > > > > I think if we go with this design instead of retrofitting a semantic > > > change of the port lifetime itself, all the complications I complain about > > > below should disappear. > > > > In the above I meant drm_dp_destroy_port or drm_dp_destroy_connector_work. > > > > Aside: I think creating a kref for the final kfree would also solve a > > bunch of other issues in a much neater way: In > > > > commit f038c5b99fc1332f558b495d136d4f433ee65caa > > Author: Lyude Paul > > Date: Tue Nov 13 17:46:14 2018 -0500 > > > > drm/dp_mst: Skip validating ports during destruction, just ref > > > > we could use that kfree reference to make sure the port pointer is alive. > > This of course means that drm_dp_update_payload_part1() would also need to > > use the kfree reference for the vcpi allocations. And probably everywhere > > else (e.g. in your nouveau series for payload information). > > > > That would give us a very clear separation overall between "port can still > > be used because it's not yet unplugged" vs. "port only hangs around > > because a bunch of vcpi allocations and other payload things upstream of > > the port might still need the port lookup key to free
Re: [Intel-gfx] [PATCH v2 01/15] drm/vblank: Allow dynamic per-crtc max_vblank_count
On Tue, Nov 27, 2018 at 08:20:04PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On i965gm we need to adjust max_vblank_count dynamically
> depending on whether the TV encoder is used or not. To
> that end add a per-crtc max_vblank_count that takes
> precedence over its device wide counterpart. The driver
> can now call drm_crtc_set_max_vblank_count() to configure
> the per-crtc value before calling drm_vblank_on().
>
> Also looks like there was some discussion about exynos needing
> similar treatment.
>
> v2: Drop the extra max_vblank_count!=0 check for the
> WARN(last!=current), will take care of it in i915 code (Daniel)
> WARN_ON(!inmodeset) (Daniel)
> WARN_ON(dev->max_vblank_count)
> Pimp up the docs (Daniel)
Yeah I'm happy with the pile of WARN_ON here. And docs look great too.
Reviewed-by: Daniel Vetter
>
> Cc: sta...@vger.kernel.org
> Cc: Inki Dae
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_vblank.c | 45 +---
> include/drm/drm_device.h | 8 ++-
> include/drm/drm_vblank.h | 22 ++
> 3 files changed, 71 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
> index 98e091175921..cde71ee95a8f 100644
> --- a/drivers/gpu/drm/drm_vblank.c
> +++ b/drivers/gpu/drm/drm_vblank.c
> @@ -105,13 +105,20 @@ static void store_vblank(struct drm_device *dev,
> unsigned int pipe,
> write_sequnlock(>seqlock);
> }
>
> +static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe)
> +{
> + struct drm_vblank_crtc *vblank = >vblank[pipe];
> +
> + return vblank->max_vblank_count ?: dev->max_vblank_count;
> +}
> +
> /*
> * "No hw counter" fallback implementation of .get_vblank_counter() hook,
> * if there is no useable hardware frame counter available.
> */
> static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int
> pipe)
> {
> - WARN_ON_ONCE(dev->max_vblank_count != 0);
> + WARN_ON_ONCE(drm_max_vblank_count(dev, pipe) != 0);
> return 0;
> }
>
> @@ -198,6 +205,7 @@ static void drm_update_vblank_count(struct drm_device
> *dev, unsigned int pipe,
> ktime_t t_vblank;
> int count = DRM_TIMESTAMP_MAXRETRIES;
> int framedur_ns = vblank->framedur_ns;
> + u32 max_vblank_count = drm_max_vblank_count(dev, pipe);
>
> /*
>* Interrupts were disabled prior to this call, so deal with counter
> @@ -216,9 +224,9 @@ static void drm_update_vblank_count(struct drm_device
> *dev, unsigned int pipe,
> rc = drm_get_last_vbltimestamp(dev, pipe, _vblank,
> in_vblank_irq);
> } while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);
>
> - if (dev->max_vblank_count != 0) {
> + if (max_vblank_count) {
> /* trust the hw counter when it's around */
> - diff = (cur_vblank - vblank->last) & dev->max_vblank_count;
> + diff = (cur_vblank - vblank->last) & max_vblank_count;
> } else if (rc && framedur_ns) {
> u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
>
> @@ -1204,6 +1212,37 @@ void drm_crtc_vblank_reset(struct drm_crtc *crtc)
> }
> EXPORT_SYMBOL(drm_crtc_vblank_reset);
>
> +/**
> + * drm_crtc_set_max_vblank_count - configure the hw max vblank counter value
> + * @crtc: CRTC in question
> + * @max_vblank_count: max hardware vblank counter value
> + *
> + * Update the maximum hardware vblank counter value for @crtc
> + * at runtime. Useful for hardware where the operation of the
> + * hardware vblank counter depends on the currently active
> + * display configuration.
> + *
> + * For example, if the hardware vblank counter does not work
> + * when a specific connector is active the maximum can be set
> + * to zero. And when that specific connector isn't active the
> + * maximum can again be set to the appropriate non-zero value.
> + *
> + * If used, must be called before drm_vblank_on().
> + */
> +void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc,
> +u32 max_vblank_count)
> +{
> + struct drm_device *dev = crtc->dev;
> + unsigned int pipe = drm_crtc_index(crtc);
> + struct drm_vblank_crtc *vblank = >vblank[pipe];
> +
> + WARN_ON(dev->max_vblank_count);
> + WARN_ON(!READ_ONCE(vblank->inmodeset));
> +
> + vblank->max_vblank_count = max_vblank_count;
> +}
> +EXPORT_SYMBOL(drm_crtc_set_max_vblank_count);
> +
> /**
> * drm_crtc_vblank_on - enable vblank events on a CRTC
> * @crtc: CRTC in question
> diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h
> index 42411b3ea0c8..45e43ce9652f 100644
> --- a/include/drm/drm_device.h
> +++ b/include/drm/drm_device.h
> @@ -184,7 +184,13 @@ struct drm_device {
>* races and imprecision over longer time periods, hence exposing a
>* hardware vblank counter is always recommended.
>*
> - * If non-zeor,
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
On 26/11/2018 06:51, Michal Wajdeczko wrote:
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
wrote:
/snip/
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 8382d591c784..1a853cc627e3 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -687,6 +687,13 @@ enum intel_guc_report_status {
INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
};
+enum intel_guc_sleep_state_status {
+ INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
+ INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
+ INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+};
btw, it used to be 0,1,2 but from some time fw defines above as:
INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3,
Michal
Yeah, I think I had already mentioned in some reply that the newer
firmware does suspend/resume differently, but I haven't looked at the
details. I'm not even sure if polling the register will still be required.
Daniele
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix TV encoder support (rev4)
== Series Details == Series: drm/i915: Fix TV encoder support (rev4) URL : https://patchwork.freedesktop.org/series/52378/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10919 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10919 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10919, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/52378/revisions/4/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10919: === IGT changes === Possible regressions igt@i915_module_load@reload: fi-glk-j4005: PASS -> DMESG-WARN +4 fi-skl-iommu: PASS -> DMESG-WARN +4 fi-bdw-gvtdvm: PASS -> DMESG-WARN +3 fi-snb-2520m: PASS -> DMESG-WARN +2 igt@i915_module_load@reload-with-fault-injection: fi-skl-gvtdvm: PASS -> DMESG-WARN +3 fi-cfl-guc: PASS -> DMESG-WARN +4 fi-skl-guc: PASS -> DMESG-WARN +3 fi-cfl-8700k: PASS -> DMESG-WARN +4 fi-skl-6700k2: PASS -> DMESG-WARN +2 fi-skl-6260u: PASS -> DMESG-WARN +4 fi-ivb-3520m: PASS -> DMESG-WARN +3 fi-ilk-650: PASS -> DMESG-WARN +1 igt@kms_busy@basic-flip-b: fi-bdw-5557u: PASS -> DMESG-WARN +4 igt@kms_busy@basic-flip-c: fi-hsw-peppy: PASS -> DMESG-WARN +3 fi-ivb-3770:PASS -> DMESG-WARN +3 fi-icl-u2: PASS -> DMESG-WARN == Known issues == Here are the changes found in Patchwork_10919 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-n3050: PASS -> FAIL ([fdo#108656]) igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE ([fdo#107718]) igt@i915_module_load@reload-with-fault-injection: fi-hsw-4770:PASS -> DMESG-WARN ([fdo#107924]) fi-hsw-peppy: PASS -> DMESG-WARN ([fdo#107924]) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL ([fdo#103191], [fdo#107362]) +1 Possible fixes igt@i915_selftest@live_hangcheck: fi-cfl-8109u: INCOMPLETE ([fdo#106070]) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN ([fdo#102614]) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: FAIL ([fdo#107362]) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL ([fdo#103191], [fdo#107362]) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: DMESG-WARN ([fdo#106107]) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 == Participating hosts (51 -> 44) == Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-snb-2600 == Build changes == * Linux: CI_DRM_5211 -> Patchwork_10919 CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10919: 39640710adab3f7f9c448d94542d9410222b4065 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 39640710adab drm/i915/tv: Filter out >1024 wide modes that would need vertical scaling on gen3 07ccbfdd05af drm/i915/tv: Fix >1024 modes on gen3 7fdc0da96974 drm/i915/tv: Generate better pipe timings for TV encoder 53ac682f877e drm/i915/tv: Add 1080p30/50/60 TV modes b59b4cdc04f9 drm/i915/tv: Nuke reported_modes[] 4f2cb6238ad3 drm/i915/tv: Make TV mode autoselection actually useable 0eb9da57f9dc drm/i915/tv: Use drm_mode_set_name() to name TV modes 287f7ac24759 drm/i915/tv: Deobfuscate preferred mode selection c0f6c577fc7e drm/i915/tv: Nuke silly 0 initialzation of xpos/ypos 46e2ca9d9c6d drm/i915/tv: Use bools where appropriate a1484e8e981a drm/i915/tv: Store the TV oversampling factor in the TV mode 80917f6b2693 drm/i915/tv: Fix tv mode clocks 055e572d3e07 drm/i915/tv: Fix interlaced ysize calculation cb0be7c79c97 drm/i915: Don't try to use the hardware frame counter with i965gm TV output d9864f1ce3a3 drm/vblank: Allow dynamic
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
== Series Details == Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities URL : https://patchwork.freedesktop.org/series/53097/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10918 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53097/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10918 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-n3050: PASS -> INCOMPLETE ([fdo#108714]) igt@gem_exec_suspend@basic-s4-devices: fi-ivb-3520m: PASS -> FAIL ([fdo#108880]) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: PASS -> INCOMPLETE ([fdo#107718]) igt@kms_psr@primary_mmap_gtt: fi-glk-dsi: SKIP -> INCOMPLETE ([fdo#103359], [k.org#198133]) Possible fixes igt@i915_selftest@live_hangcheck: fi-cfl-8109u: INCOMPLETE ([fdo#106070]) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN ([fdo#102614]) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: FAIL ([fdo#107362]) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL ([fdo#103191], [fdo#107362]) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: DMESG-WARN ([fdo#106107]) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108714 https://bugs.freedesktop.org/show_bug.cgi?id=108714 fdo#108880 https://bugs.freedesktop.org/show_bug.cgi?id=108880 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (51 -> 45) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-snb-2600 == Build changes == * Linux: CI_DRM_5211 -> Patchwork_10918 CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10918: 0c1f2afef9c526762b0f797c1db79ecc26b0fa62 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0c1f2afef9c5 drm/i915/fec: Disable FEC state. d9355283d266 i915/dp/fec: Configure the Forward Error Correction bits. 43c49d130d57 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION 96008331f00c i915/dp/fec: Add fec_enable to the crtc state. 8c2f974809b9 drm/i915/dsc: Enable and disable appropriate power wells for VDSC 0b918115e1f4 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits b480353d8479 drm/i915/dp: Configure Display stream splitter registers during DSC enable 76ff0de57bbb drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes cd379836e433 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs 4489512d99cc drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 738d3e39b498 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 3fe1eaeafcc1 drm/i915/dp: Enable/Disable DSC in DP Sink 7ac193d4beba drm/i915/dsc: Compute Rate Control parameters for DSC b250f4133544 drm/i915/dsc: Define & Compute VESA DSC params 410642768023 drm/i915/dp: Do not enable PSR2 if DSC is enabled 8f8c03228817 drm/i915/dp: Compute DSC pipe config in atomic check dd433139c981 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state 259e70ec73c9 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants 71de78c19cd0 drm/dsc: Add helpers for DSC picture parameter set infoframes c270fd909ad4 drm/dsc: Define Rate Control values that do not change over configurations 2c62da01daa8 drm/dsc: Define VESA Display Stream Compression Capabilities 66a26c5082ff drm/dsc: Define Display Stream Compression PPS infoframe b564f4b939ca drm/dsc: Modify DRM helper to return complete DSC color depth capabilities == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10918/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix TV encoder support (rev4)
== Series Details == Series: drm/i915: Fix TV encoder support (rev4) URL : https://patchwork.freedesktop.org/series/52378/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/vblank: Allow dynamic per-crtc max_vblank_count Okay! Commit: drm/i915: Don't try to use the hardware frame counter with i965gm TV output Okay! Commit: drm/i915/tv: Fix interlaced ysize calculation Okay! Commit: drm/i915/tv: Fix tv mode clocks Okay! Commit: drm/i915/tv: Store the TV oversampling factor in the TV mode Okay! Commit: drm/i915/tv: Use bools where appropriate Okay! Commit: drm/i915/tv: Nuke silly 0 initialzation of xpos/ypos Okay! Commit: drm/i915/tv: Deobfuscate preferred mode selection Okay! Commit: drm/i915/tv: Use drm_mode_set_name() to name TV modes Okay! Commit: drm/i915/tv: Make TV mode autoselection actually useable Okay! Commit: drm/i915/tv: Nuke reported_modes[] Okay! Commit: drm/i915/tv: Add 1080p30/50/60 TV modes Okay! Commit: drm/i915/tv: Generate better pipe timings for TV encoder Okay! Commit: drm/i915/tv: Fix >1024 modes on gen3 +drivers/gpu/drm/i915/intel_tv.c:889:28: warning: symbol 'intel_tv_connector_duplicate_state' was not declared. Should it be static? Commit: drm/i915/tv: Filter out >1024 wide modes that would need vertical scaling on gen3 Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size
On 27/11/2018 09:38, Mika Kuoppala wrote:
Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.
Note that not all registers in the 12-deep CSB fifo are in a contiguous
range, the new ones (6-11) start at mmio_base + 0x3C0 (Bspec: 11724). If
we read contiguously we'll access the registers that are in between the
2 CSB ranges (e.g. RING_CONTEXT_STATUS_PTR). Not a real issue for us
since we always read from HWSP where the CSBs are contiguous, but we
need to at least update intel_engine_print_registers(). Also not sure if
GVT still needs the MMIO mode, if not we could maybe just rip it out
instead of adapting it.
Daniele
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_engine_cs.c | 16 +---
drivers/gpu/drm/i915/intel_lrc.c| 24 +---
drivers/gpu/drm/i915/intel_lrc.h| 9 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 15 +--
4 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 759c0fd58f8c..218ef817da1d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1347,27 +1347,29 @@ static void intel_engine_print_registers(const struct
intel_engine_cs *engine,
unsigned int idx;
u8 read, write;
- drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+ drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
I915_READ(RING_EXECLIST_STATUS_LO(engine)),
- I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+ I915_READ(RING_EXECLIST_STATUS_HI(engine)),
+ execlists->csb_entries);
read = execlists->csb_head;
write = READ_ONCE(*execlists->csb_write);
drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
read, write,
-
GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+ I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
+ GEN11_CSB_WRITE_PTR_MASK,
yesno(test_bit(TASKLET_STATE_SCHED,
>execlists.tasklet.state)),
enableddisabled(!atomic_read(>execlists.tasklet.count)));
- if (read >= GEN8_CSB_ENTRIES)
+ if (read >= execlists->csb_entries)
read = 0;
- if (write >= GEN8_CSB_ENTRIES)
+ if (write >= execlists->csb_entries)
write = 0;
if (read > write)
- write += GEN8_CSB_ENTRIES;
+ write += execlists->csb_entries;
while (read < write) {
- idx = ++read % GEN8_CSB_ENTRIES;
+ idx = ++read % execlists->csb_entries;
drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x],
context: %d [mmio:%d]\n",
idx,
hws[idx * 2],
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 08fd9b12e4d7..5487fe496bb6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -767,6 +767,7 @@ execlists_cancel_port_requests(struct
intel_engine_execlists * const execlists)
static void reset_csb_pointers(struct intel_engine_execlists *execlists)
{
+ u32 reset_val;
/*
* After a reset, the HW starts writing into CSB entry [0]. We
* therefore have to set our HEAD pointer back one entry so that
@@ -776,8 +777,19 @@ static void reset_csb_pointers(struct
intel_engine_execlists *execlists)
* inline comparison of our cached head position against the last HW
* write works even before the first interrupt.
*/
- execlists->csb_head = execlists->csb_write_reset;
- WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
+ execlists->csb_head = execlists->csb_entries - 1;
+
+ if (execlists_mmio_mode(execlists)) {
+ const u32 mask = execlists->csb_entries == GEN8_CSB_ENTRIES ?
+ GEN8_CSB_WRITE_PTR_MASK :
+ GEN11_CSB_WRITE_PTR_MASK;
+
+ reset_val = _MASKED_FIELD(mask, execlists->csb_head);
+ } else {
+ reset_val = execlists->csb_head;
+ }
+
+ WRITE_ONCE(*execlists->csb_write, reset_val);
}
static void nop_submission_tasklet(unsigned long data)
@@ -895,7 +907,7 @@ static void process_csb(struct intel_engine_cs *engine)
unsigned int status;
unsigned int count;
- if (++head == GEN8_CSB_ENTRIES)
+ if (++head
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
== Series Details == Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities URL : https://patchwork.freedesktop.org/series/53097/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:200:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:200:61:got int +drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:207:25:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:207:25:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types) Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1896:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1916:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1937:58: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1937:58: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3573:16: warning: expression using sizeof(void) Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC Okay! Commit: i915/dp/fec: Add fec_enable to the crtc state. Okay! Commit: drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Okay! Commit: i915/dp/fec: Configure the Forward Error Correction bits. Okay! Commit: drm/i915/fec: Disable FEC state. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
== Series Details ==
Series: series starting with [CI,v11,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53097/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b564f4b939ca drm/dsc: Modify DRM helper to return complete DSC color depth
capabilities
66a26c5082ff drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 342 lines checked
2c62da01daa8 drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Gaurav K Singh
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
c270fd909ad4 drm/dsc: Define Rate Control values that do not change over
configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Srivatsa, Anusha '
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
71de78c19cd0 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#79:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 285 lines checked
259e70ec73c9 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
dd433139c981 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+ bool compression_enable;
-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:944:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
8f8c03228817 drm/i915/dp: Compute DSC pipe config in atomic check
-:189: WARNING:LINE_SPACING: Missing a blank line after declarations
#189: FILE: drivers/gpu/drm/i915/intel_dp.c:1924:
+ u8 dsc_dp_slice_count;
+ dsc_max_output_bpp =
-:263: WARNING:TABSTOP: Statements should start on a tabstop
#263: FILE: drivers/gpu/drm/i915/intel_dp.c:2025:
+else
total: 0 errors, 2 warnings, 0 checks, 262 lines checked
410642768023 drm/i915/dp: Do not enable PSR2 if DSC is enabled
b250f4133544 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68:
Co-developed-by: Manasi Navare
-:95: WARNING:MISSING_SPACE: break quoted strings at a space character
#95: FILE: drivers/gpu/drm/i915/intel_dp.c:1957:
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#119:
new file mode 100644
-:405: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#405: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3 warnings, 1 checks, 496 lines checked
7ac193d4beba drm/i915/dsc: Compute Rate Control parameters for DSC
-:141: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#141: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+ vdsc_cfg->slice_bpg_offset)*
^
-:173: CHECK:LINE_SPACING: Please don't use multiple blank lines
#173: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+
total: 0 errors, 0
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size
== Series Details == Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size URL : https://patchwork.freedesktop.org/series/53096/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10917 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53096/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10917 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-ivb-3520m: PASS -> FAIL ([fdo#108880]) igt@i915_selftest@live_coherency: fi-gdg-551: PASS -> DMESG-FAIL ([fdo#107164]) Possible fixes igt@i915_module_load@reload: fi-blb-e6850: INCOMPLETE ([fdo#107718]) -> PASS igt@i915_selftest@live_hangcheck: fi-cfl-8109u: INCOMPLETE ([fdo#106070]) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN ([fdo#102614]) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: FAIL ([fdo#107362]) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL ([fdo#103191], [fdo#107362]) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: DMESG-WARN ([fdo#106107]) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108880 https://bugs.freedesktop.org/show_bug.cgi?id=108880 == Participating hosts (51 -> 45) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-snb-2600 == Build changes == * Linux: CI_DRM_5211 -> Patchwork_10917 CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10917: 237214ef4edbf9418187688d4e9fd5994ce2662d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 237214ef4edb drm/i915: Assert the csb tail is within bounds fc7285048942 drm/i915/icl: Switch to using 12 deep CSB status FIFO 72334c0aa634 drm/i915: Prepare for larger CSB status FIFO size == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10917/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/nouveau: Stop reading port->mgr in nv50_mstc_detect()
On Sat, 2018-11-17 at 12:24 +, Sasha Levin wrote:
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a -stable tag.
> The stable tag indicates that it's relevant for the following trees: all
>
> The bot has tested the following trees: v4.19.2, v4.18.19, v4.14.81,
> v4.9.137, v4.4.163, v3.18.125,
>
> v4.19.2: Build OK!
> v4.18.19: Build OK!
> v4.14.81: Failed to apply! Possible dependencies:
> e46368cf77f2 ("drm/nouveau/drm/nouveau: Grab runtime PM ref in
> nv50_mstc_detect()")
>
> v4.9.137: Failed to apply! Possible dependencies:
> e46368cf77f2 ("drm/nouveau/drm/nouveau: Grab runtime PM ref in
> nv50_mstc_detect()")
>
> v4.4.163: Failed to apply! Possible dependencies:
> e46368cf77f2 ("drm/nouveau/drm/nouveau: Grab runtime PM ref in
> nv50_mstc_detect()")
>
> v3.18.125: Failed to apply! Possible dependencies:
> e46368cf77f2 ("drm/nouveau/drm/nouveau: Grab runtime PM ref in
> nv50_mstc_detect()")
>
>
> How should we proceed with this patch?
e46368cf77f2 ("drm/nouveau/drm/nouveau: Grab runtime PM ref in
nv50_mstc_detect()")
Should also be backported for v4.9+, and then this patch should be applied on
top of that.
>
> --
> Thanks,
> Sasha
--
Cheers,
Lyude Paul
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/fbdev: Make skip_vt_switch the default (rev2)
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev2)
URL : https://patchwork.freedesktop.org/series/53094/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10916 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10916 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10916, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53094/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10916:
=== IGT changes ===
Possible regressions
igt@i915_selftest@live_sanitycheck:
fi-bxt-dsi: PASS -> DMESG-WARN
{igt@runner@aborted}:
fi-bxt-dsi: NOTRUN -> FAIL
== Known issues ==
Here are the changes found in Patchwork_10916 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_ctx_create@basic-files:
fi-bsw-n3050: PASS -> INCOMPLETE ([fdo#108714])
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: PASS -> FAIL ([fdo#103167])
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
fi-byt-clapper: PASS -> FAIL ([fdo#103191], [fdo#107362])
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-blb-e6850: PASS -> INCOMPLETE ([fdo#107718])
{igt@runner@aborted}:
{fi-icl-u3}:NOTRUN -> FAIL ([fdo#108866 ])
Possible fixes
igt@i915_selftest@live_hangcheck:
fi-cfl-8109u: INCOMPLETE ([fdo#106070]) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-WARN ([fdo#102614]) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: FAIL ([fdo#107362]) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-byt-clapper: FAIL ([fdo#103191], [fdo#107362]) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-cfl-8109u: DMESG-WARN ([fdo#106107]) -> PASS
Warnings
igt@i915_selftest@live_contexts:
{fi-icl-u3}:DMESG-FAIL ([fdo#108569]) -> INCOMPLETE ([fdo#108315])
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
fdo#108714 https://bugs.freedesktop.org/show_bug.cgi?id=108714
fdo#108866 https://bugs.freedesktop.org/show_bug.cgi?id=108866
== Participating hosts (51 -> 46) ==
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5211 -> Patchwork_10916
CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10916: d2c59bd255a1cff3428493e4a80bd16681754294 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d2c59bd255a1 drm/fbdev: Make skip_vt_switch the default
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10916/
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 02/15] drm/i915: Don't try to use the hardware frame counter with i965gm TV output
From: Ville Syrjälä
On i965gm the hardware frame counter does not work when
the TV encoder is active. So let's not try to consult
the hardware frame counter in that case. Instead we'll
fall back to the timestamp based guesstimation method
used on gen2.
Note that the pipe timings generated by the TV encoder
are also rather peculiar. Apparently the pipe wants to
run at a much higher speed (related to the oversample
clock somehow it seems) but during the vertical active
period the TV encoder stalls the pipe every few lines
to keep its speed in check. But once the vertical
blanking period is reached the pipe gets to run at full
speed. This means our vblank timestamp estimates are
suspect. Fixing all that would require quite a bit
more work. This simple fix at least avoids the nasty
vblank timeouts that are happening currently.
Curiously the frame counter works just fine on i945gm
and gm45. I don't really understand what kind of mishap
occurred with the hardware design on i965gm. Sadly
I wasn't able to find any chicken bits etc. that would
fix the frame counter :(
v2: Move the zero vs. non-zero hw counter value handling
into i915_get_vblank_counter() (Daniel)
Use the per-crtc maximum exclusively, leaving the
per-device maximum at zero
Cc: sta...@vger.kernel.org
Cc: Daniel Vetter
Fixes: 51e31d49c890 ("drm/i915: Use generic vblank wait")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93782
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 27 ++-
drivers/gpu/drm/i915/intel_display.c | 49 +++-
2 files changed, 59 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d447d7d508f4..ab2d4eefef18 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -822,11 +822,26 @@ static void i915_enable_asle_pipestat(struct
drm_i915_private *dev_priv)
static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_vblank_crtc *vblank = >vblank[pipe];
+ const struct drm_display_mode *mode = >hwmode;
i915_reg_t high_frame, low_frame;
u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
- const struct drm_display_mode *mode = >vblank[pipe].hwmode;
unsigned long irqflags;
+ /*
+* On i965gm TV output the frame counter only works up to
+* the point when we enable the TV encoder. After that the
+* frame counter ceases to work and reads zero. We need a
+* vblank wait before enabling the TV encoder and so we
+* have to enable vblank interrupts while the frame counter
+* is still in a working state. However the core vblank code
+* does not like us returning non-zero frame counter values
+* when we've told it that we don't have a working frame
+* counter. Thus we must stop non-zero values leaking out.
+*/
+ if (!vblank->max_vblank_count)
+ return 0;
+
htotal = mode->crtc_htotal;
hsync_start = mode->crtc_hsync_start;
vbl_start = mode->crtc_vblank_start;
@@ -4836,16 +4851,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 8)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
- if (IS_GEN2(dev_priv)) {
- /* Gen2 doesn't have a hardware frame counter */
- dev->max_vblank_count = 0;
- } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
- dev->max_vblank_count = 0x; /* full 32 bit counter */
+ if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
dev->driver->get_vblank_counter = g4x_get_vblank_counter;
- } else {
+ else if (INTEL_GEN(dev_priv) >= 3)
dev->driver->get_vblank_counter = i915_get_vblank_counter;
- dev->max_vblank_count = 0xff; /* only 24 bits of frame
count */
- }
/*
* Opt out of the vblank disable timer on everything except gen2.
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22b2a4e..3eafea4e598f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1758,6 +1758,7 @@ static void intel_enable_pipe(const struct
intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_vblank_crtc *vblank =
_priv->drm.vblank[drm_crtc_index(>base)];
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
i915_reg_t reg;
@@ -1806,7 +1807,7 @@ static void intel_enable_pipe(const struct
intel_crtc_state *new_crtc_state)
* when it's derived from the timestamps. So let's
[Intel-gfx] [PATCH v2 01/15] drm/vblank: Allow dynamic per-crtc max_vblank_count
From: Ville Syrjälä
On i965gm we need to adjust max_vblank_count dynamically
depending on whether the TV encoder is used or not. To
that end add a per-crtc max_vblank_count that takes
precedence over its device wide counterpart. The driver
can now call drm_crtc_set_max_vblank_count() to configure
the per-crtc value before calling drm_vblank_on().
Also looks like there was some discussion about exynos needing
similar treatment.
v2: Drop the extra max_vblank_count!=0 check for the
WARN(last!=current), will take care of it in i915 code (Daniel)
WARN_ON(!inmodeset) (Daniel)
WARN_ON(dev->max_vblank_count)
Pimp up the docs (Daniel)
Cc: sta...@vger.kernel.org
Cc: Inki Dae
Cc: Daniel Vetter
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_vblank.c | 45 +---
include/drm/drm_device.h | 8 ++-
include/drm/drm_vblank.h | 22 ++
3 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 98e091175921..cde71ee95a8f 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -105,13 +105,20 @@ static void store_vblank(struct drm_device *dev, unsigned
int pipe,
write_sequnlock(>seqlock);
}
+static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe)
+{
+ struct drm_vblank_crtc *vblank = >vblank[pipe];
+
+ return vblank->max_vblank_count ?: dev->max_vblank_count;
+}
+
/*
* "No hw counter" fallback implementation of .get_vblank_counter() hook,
* if there is no useable hardware frame counter available.
*/
static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe)
{
- WARN_ON_ONCE(dev->max_vblank_count != 0);
+ WARN_ON_ONCE(drm_max_vblank_count(dev, pipe) != 0);
return 0;
}
@@ -198,6 +205,7 @@ static void drm_update_vblank_count(struct drm_device *dev,
unsigned int pipe,
ktime_t t_vblank;
int count = DRM_TIMESTAMP_MAXRETRIES;
int framedur_ns = vblank->framedur_ns;
+ u32 max_vblank_count = drm_max_vblank_count(dev, pipe);
/*
* Interrupts were disabled prior to this call, so deal with counter
@@ -216,9 +224,9 @@ static void drm_update_vblank_count(struct drm_device *dev,
unsigned int pipe,
rc = drm_get_last_vbltimestamp(dev, pipe, _vblank,
in_vblank_irq);
} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);
- if (dev->max_vblank_count != 0) {
+ if (max_vblank_count) {
/* trust the hw counter when it's around */
- diff = (cur_vblank - vblank->last) & dev->max_vblank_count;
+ diff = (cur_vblank - vblank->last) & max_vblank_count;
} else if (rc && framedur_ns) {
u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
@@ -1204,6 +1212,37 @@ void drm_crtc_vblank_reset(struct drm_crtc *crtc)
}
EXPORT_SYMBOL(drm_crtc_vblank_reset);
+/**
+ * drm_crtc_set_max_vblank_count - configure the hw max vblank counter value
+ * @crtc: CRTC in question
+ * @max_vblank_count: max hardware vblank counter value
+ *
+ * Update the maximum hardware vblank counter value for @crtc
+ * at runtime. Useful for hardware where the operation of the
+ * hardware vblank counter depends on the currently active
+ * display configuration.
+ *
+ * For example, if the hardware vblank counter does not work
+ * when a specific connector is active the maximum can be set
+ * to zero. And when that specific connector isn't active the
+ * maximum can again be set to the appropriate non-zero value.
+ *
+ * If used, must be called before drm_vblank_on().
+ */
+void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc,
+ u32 max_vblank_count)
+{
+ struct drm_device *dev = crtc->dev;
+ unsigned int pipe = drm_crtc_index(crtc);
+ struct drm_vblank_crtc *vblank = >vblank[pipe];
+
+ WARN_ON(dev->max_vblank_count);
+ WARN_ON(!READ_ONCE(vblank->inmodeset));
+
+ vblank->max_vblank_count = max_vblank_count;
+}
+EXPORT_SYMBOL(drm_crtc_set_max_vblank_count);
+
/**
* drm_crtc_vblank_on - enable vblank events on a CRTC
* @crtc: CRTC in question
diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h
index 42411b3ea0c8..45e43ce9652f 100644
--- a/include/drm/drm_device.h
+++ b/include/drm/drm_device.h
@@ -184,7 +184,13 @@ struct drm_device {
* races and imprecision over longer time periods, hence exposing a
* hardware vblank counter is always recommended.
*
-* If non-zeor, _crtc_funcs.get_vblank_counter must be set.
+* This is the statically configured device wide maximum. The driver
+* can instead choose to use a runtime configurable per-crtc value
+* _vblank_crtc.max_vblank_count, in which case @max_vblank_count
+* must be left at zero. See drm_crtc_set_max_vblank_count() on how
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/fbdev: Make skip_vt_switch the default (rev2)
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev2)
URL : https://patchwork.freedesktop.org/series/53094/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d2c59bd255a1 drm/fbdev: Make skip_vt_switch the default
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 18c437caa5b1 ("Revert
"drm/radeon: dont switch vt on suspend"")'
#22:
commit 18c437caa5b18a235dd65cec224eab54bebcee65
-:133: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 1 errors, 1 warnings, 0 checks, 47 lines checked
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev11)
URL : https://patchwork.freedesktop.org/series/51878/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5211 -> Patchwork_10915 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/51878/revisions/11/mbox/
== Known issues ==
Here are the changes found in Patchwork_10915 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_ctx_create@basic-files:
fi-bsw-n3050: PASS -> FAIL ([fdo#108656])
fi-bsw-kefka: PASS -> DMESG-FAIL ([fdo#108656])
{igt@runner@aborted}:
{fi-icl-u3}:NOTRUN -> FAIL ([fdo#108866 ])
fi-bsw-kefka: NOTRUN -> FAIL ([fdo#108656])
Possible fixes
igt@i915_module_load@reload:
fi-blb-e6850: INCOMPLETE ([fdo#107718]) -> PASS
igt@i915_selftest@live_hangcheck:
fi-cfl-8109u: INCOMPLETE ([fdo#106070]) -> PASS
igt@kms_chamelium@hdmi-hpd-fast:
{fi-kbl-7500u}: FAIL -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: FAIL ([fdo#107362]) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-byt-clapper: FAIL ([fdo#103191], [fdo#107362]) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-cfl-8109u: DMESG-WARN ([fdo#106107]) -> PASS
Warnings
igt@i915_selftest@live_contexts:
{fi-icl-u3}:DMESG-FAIL ([fdo#108569]) -> INCOMPLETE ([fdo#108315])
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
fdo#108866 https://bugs.freedesktop.org/show_bug.cgi?id=108866
== Participating hosts (51 -> 46) ==
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5211 -> Patchwork_10915
CI_DRM_5211: b6ba4ad91b7c6c4341c40a05b0326470e0c293cb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4732: eae5c3587e56abc581af9b59060cd316df2caa08 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10915: f626b07e7e192b298698c64e5fda851e03e79495 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f626b07e7e19 drm/i915: Pass the plane to icl_program_input_csc_coeff()
972e01e50301 drm/i915: Rename the confusing 'plane_id' to 'color_plane'
6581d1c88787 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
378d0718daa0 drm/i915: Move ddb/wm programming into plane update/disable hooks
on skl+
4611696fec9f drm/i915: Don't pass dev_priv around so much
900570f29731 drm/i915: Clean up skl+ vs. icl+ watermark computation
c59c49fe42d5 drm/i915: Pass the entire skl_plane_wm to
skl_compute_transition_wm()
ef730820a9b9 drm/i915: Remove some useless zeroing on skl+ wm calculations
edbc517f0a76 drm/i915: Fix latency==0 handling for level 0 watermark on skl+
7107a3d9c003 drm/i915: Pass the new crtc_state to ->disable_plane()
0384431cd12f drm/i915: Introduce crtc_state->update_planes bitmask
ef3ad7085ebf drm/i915: Move single buffered plane register writes to the end
094cd6f80a68 drm/i915: Reorganize plane register writes to make them more atomic
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10915/
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[Intel-gfx] [CI v11 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0e72520abdfc..2cc933b57d94 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -976,6 +976,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(encoder, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -985,5 +1004,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
2.19.1
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[Intel-gfx] [CI v11 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)
v5: Move to intel_ddi.c
- Make the function static (Anusha)
v6: Dont pass state as a separate argument (Ville)
v7: (From Manasi)
* Correct the debug print (Ville)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6533624226a7..4c74bbe1cf73 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct
intel_digital_port *intel_dig_port)
I915_WRITE(MG_DP_MODE(port, 1), ln1);
}
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
+{
+ if (!crtc_state->fec_enable)
+ return;
+
+ if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION,
DP_FEC_READY) <= 0)
+ DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
--
2.19.1
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[Intel-gfx] [CI v11 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5e253f741d29..b41b06dc8347 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -242,6 +242,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1c2de9b69a19..4350a5270423 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2028,9 +2030,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
2.19.1
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[Intel-gfx] [CI v11 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c | 25 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 339be10986d7..6533624226a7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2154,6 +2154,12 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+ /*
+* VDSC power is needed when DSC is enabled
+*/
+ if (crtc_state->dsc_params.compression_enable)
+ domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fa452fbb16c6..b5693cac26d7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1858,6 +1858,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp, int mode_clock,
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index a13b776dc8fa..17ef78652f71 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -578,6 +578,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ /*
+* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* For any other transcoder, VDSC/joining uses the power well associated
+* with the pipe/transcoder in use. Hence another reference on the
+* transcoder power domain will suffice.
+*/
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else
+ return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
@@ -1008,6 +1026,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
+ /* Enable Power wells for VDSC/joining */
+ intel_display_power_get(dev_priv,
+ intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1060,4 +1082,7 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+ /* Disable Power wells for VDSC/joining */
+ intel_display_power_put(dev_priv,
+ intel_dsc_power_domain(old_crtc_state));
}
--
2.19.1
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[Intel-gfx] [CI v11 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 126 +-
1 file changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0a1918f2f643..b644f69f1c93 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_DEBUG_KMS("FinalOfs < RcModelSze for this
InitialXmitDelay\n");
+ return -ERANGE;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size * 8) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_DEBUG_KMS("NflBpgOffset is too large for this slice
height\n");
+ return -ERANGE;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+
[Intel-gfx] [CI v11 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
--
2.19.1
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[Intel-gfx] [CI v11 08/23] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v14:
Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
v13:
* Compute DSC bpc only when DSC is req to be enabled (Ville)
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Ville Syrjala
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_display.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 191 ---
3 files changed, 171 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e9f4e22b2a4e..69bb0b75a806 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6724,7 +6724,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5f2955b944da..5e253f741d29 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -423,7 +423,7 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 70ae3d57316b..6fe89dbd8129 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1708,6 +1710,26 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ /* FIXME: FEC needed for external DP until then reject DSC on DP */
+ if (!intel_dp_is_edp(intel_dp))
+ return false;
+
+ return INTEL_GEN(dev_priv) >= 10 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A;
+}
+
+static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
+}
+
static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config)
{
@@ -1842,14 +1864,114 @@ intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp,
return false;
}
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+{
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc;
[Intel-gfx] [CI v11 04/23] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 3292dfed9d0a..b88e31bd9da7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
2.19.1
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[Intel-gfx] [CI v11 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.
v2:
* Simplify the logic (Ville)
Signed-off-by: Manasi Navare
Cc: Ville Syrjala
Reviewed-by: Ville Syrjala
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/drm_dp_helper.c | 14 --
include/drm/drm_dp_helper.h | 3 ++-
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 6d483487f2b4..2d6c491a0542 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1428,17 +1428,19 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
}
EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+u8 dsc_bpc[3])
{
+ int num_bpc = 0;
u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
if (color_depth & DP_DSC_12_BPC)
- return 12;
+ dsc_bpc[num_bpc++] = 12;
if (color_depth & DP_DSC_10_BPC)
- return 10;
+ dsc_bpc[num_bpc++] = 10;
if (color_depth & DP_DSC_8_BPC)
- return 8;
+ dsc_bpc[num_bpc++] = 8;
- return 0;
+ return num_bpc;
}
-EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
+EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3314e91f6eb3..5736c942c85b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1123,7 +1123,8 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
+u8 dsc_bpc[3]);
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
--
2.19.1
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[Intel-gfx] [CI v11 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c| 32
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 335f7667739b..19a8b21b8f14 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3345,6 +3345,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
extern void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 69bb0b75a806..7a221fb9ca66 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5889,6 +5889,8 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index c2534142167f..a13b776dc8fa 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1029,3 +1029,35 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+}
--
2.19.1
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[Intel-gfx] [CI v11 23/23] drm/i915/fec: Disable FEC state.
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
v6: Resolve warnings. Add crtc_state as an argument to
intel_disable_ddi_buf(). (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 12acdb08a750..61d7145f93bf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3133,6 +3133,22 @@ static void intel_ddi_enable_fec(struct intel_encoder
*encoder,
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3272,7 +3288,8 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
}
}
-static void intel_disable_ddi_buf(struct intel_encoder *encoder)
+static void intel_disable_ddi_buf(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
@@ -3291,6 +3308,9 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder)
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
I915_WRITE(DP_TP_CTL(port), val);
+ /* Disable FEC in DP Sink */
+ intel_ddi_disable_fec_state(encoder, crtc_state);
+
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
}
@@ -3314,7 +3334,7 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
}
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_edp_panel_vdd_on(intel_dp);
intel_edp_panel_off(intel_dp);
@@ -3337,7 +3357,7 @@ static void intel_ddi_post_disable_hdmi(struct
intel_encoder *encoder,
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
@@ -3388,7 +3408,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder
*encoder,
val &= ~FDI_RX_ENABLE;
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_ddi_clk_disable(encoder);
val = I915_READ(FDI_RX_MISC(PIPE_A));
--
2.19.1
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[Intel-gfx] [CI v11 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed-by: Gaurav K Singh
Acked-by: Harry Wentland
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 78db4f61d01c..3292dfed9d0a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
#include
/* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES 15
+#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+#define DSC_RC_PIXELS_PER_GROUP3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
+#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+
+/* Configuration for a single Rate Control model range */
+struct drm_dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie.,
[Intel-gfx] [CI v11 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 2cc933b57d94..c2534142167f 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -998,6 +998,12 @@ static void intel_dp_write_dsc_pps_sdp(struct
intel_encoder *encoder,
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1006,5 +1012,20 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.19.1
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[Intel-gfx] [CI v11 22/23] i915/dp/fec: Configure the Forward Error Correction bits.
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.
v6: Pass intel_encoder, instead of intel_dp. (Ville)
v7: Remove unwanted comments (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eadd880b0ef6..d3ef97915455 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9198,6 +9198,7 @@ enum skl_power_gate {
#define _DP_TP_CTL_B 0x64140
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
#define DP_TP_CTL_ENABLE (1 << 31)
+#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
@@ -9216,6 +9217,7 @@ enum skl_power_gate {
#define _DP_TP_STATUS_A0x64044
#define _DP_TP_STATUS_B0x64144
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE(1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4c74bbe1cf73..12acdb08a750 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3112,6 +3112,27 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp
*intel_dp,
DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
}
+static void intel_ddi_enable_fec(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val |= DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ 1))
+ DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3157,6 +3178,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
+ intel_ddi_enable_fec(encoder, crtc_state);
+
icl_enable_phy_clock_gating(dig_port);
if (!is_mst)
--
2.19.1
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[Intel-gfx] [CI v11 20/23] i915/dp/fec: Add fec_enable to the crtc state.
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)
- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)
v3: Check for FEC support along with setting crtc state.
v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)
v5: Move fec check to intel_dp_supports_dsc(Ville)
v6: Remove warning. rebase.
v7: change crtc state to include DP sink and fec capability
of source.(Manasi)
v8: Set fec_enable in crtc in intel_dp_compute_config().
v9 (From Manasi):
* Combine the !edp and !fec_support check
* Derive dev_priv from intel_dp directly
v10 (From Manasi):
* Rebase
Suggested-by: Ville Syrjala
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6523edabe8db..0ed5aa03de92 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
- } else {
+ } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
@@ -1710,14 +1710,25 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
-static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
const struct intel_crtc_state
*pipe_config)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- /* FIXME: FEC needed for external DP until then reject DSC on DP */
- if (!intel_dp_is_edp(intel_dp))
- return false;
+ return INTEL_GEN(dev_priv) >= 11 && pipe_config->cpu_transcoder !=
TRANSCODER_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
+ drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
+
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
return INTEL_GEN(dev_priv) >= 10 &&
pipe_config->cpu_transcoder != TRANSCODER_A;
@@ -1726,6 +1737,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp
*intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
+ if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
+ return false;
+
return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
@@ -2128,6 +2142,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
+ pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config);
+
if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
return false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b5693cac26d7..8c582d53c00a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -946,6 +946,9 @@ struct intel_crtc_state {
u8 slice_count;
} dsc_params;
struct drm_dsc_config dp_dsc_cfg;
+
+ /* Forward Error correction State */
+ bool fec_enable;
};
struct intel_crtc {
--
2.19.1
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[Intel-gfx] [CI v11 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v7:
* Remove unnecessary comments, leftovers (Ville)
* No need for explicit val &= ~ (Ville)
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 2 +
drivers/gpu/drm/i915/intel_vdsc.c | 410 ++
3 files changed, 414 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 183aae996305..335f7667739b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3343,6 +3343,8 @@ extern void intel_rps_mark_interactive(struct
drm_i915_private *i915,
bool interactive);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fa5ad62cd0db..339be10986d7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3144,6 +3144,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
+
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index b644f69f1c93..0e72520abdfc 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -577,3 +577,413 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+ /*
+* If 2 VDSC instances are needed, configure PPS for second
+* VDSC
+*/
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
+ } else {
+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+ pps_val);
+ }
+
+ /* Populate PICTURE_PARAMETER_SET_1 registers */
+ pps_val = 0;
+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+ DRM_INFO("PPS1 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+
[Intel-gfx] [CI v11 10/23] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
5 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0ff878c994e2..8370b9de6e4f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -157,7 +157,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6fe89dbd8129..35dac1517dc4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1952,6 +1952,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 270212fa43a0..316ec1e107bf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1852,6 +1852,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..0a1918f2f643
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh
+ * Manasi Navare
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+
[Intel-gfx] [CI v11 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v7:
* Use BUILD_BUG_ON() to protect changing struct size (Ville)
* Remove typecaseting (Ville)
* Include byteorder.h in drm_dsc.c (Ville)
* Correct kernel doc spacing (Anusha)
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in
Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 228 ++
include/drm/drm_dsc.h | 21 +++
4 files changed, 262 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index 4b4dc236ef6f..b422eb8edf16 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 1fafc2f8e8f9..e490fe2687db 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index ..bc2b23adb072
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ const struct drm_dsc_config *dsc_cfg)
+{
+ int i;
+
+ /* Protect against someone accidently changing struct size */
+ BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+
+ memset(_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version =
+ dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+
[Intel-gfx] [CI v11 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 572e626eadff..2084784f320d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
if (i915_modparams.enable_psr == -1)
return false;
+ /* Cannot enable DSC and PSR2 simultaneously */
+ WARN_ON(crtc_state->dsc_params.compression_enable &&
+ crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -502,6 +506,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.19.1
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[Intel-gfx] [CI v11 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 21 +++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe8f71..eadd880b0ef6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4570,6 +4570,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index e2c6a2b3e8f2..07e803a604bd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ int data_size;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
2.19.1
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[Intel-gfx] [CI v11 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
v2:
* Rebase on drm-tip (Manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f763b30f98d9..183aae996305 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include "i915_fixed.h"
#include "i915_params.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a62d77b76291..270212fa43a0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -937,6 +937,15 @@ struct intel_crtc_state {
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
2.19.1
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[Intel-gfx] [CI v11 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 16
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad11540ac436..fa5ad62cd0db 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3134,6 +3134,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3491,6 +3493,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ false);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 35dac1517dc4..6523edabe8db 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2856,6 +2856,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE,
+enable ? DP_DECOMPRESSION_EN : 0);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ enable ? "enable" : "disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 316ec1e107bf..fa452fbb16c6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1797,6 +1797,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.19.1
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[Intel-gfx] [CI v11 02/23] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
v4:
* Remove redundant blankline in doc (Ville)
* use drm_dsc namespace for all structs (Ville)
* Use packed struct (Ville)
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
---
include/drm/drm_dsc.h | 342 ++
1 file changed, 342 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index ..78db4f61d01c
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct drm_dsc_picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16 pic_width;
+ /**
+* @slice_height:
+* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+*/
+ __be16 slice_height;
+ /**
+* @slice_width:
+* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+*/
+ __be16 slice_width;
+ /**
+* @chunk_size:
+* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+* that are used for slice multiplexing.
+*/
+ __be16 chunk_size;
+ /**
+* @initial_xmit_delay_high:
+* PPS16[1:0] - Most Significant two bits of initial transmission delay.
+* It specifies the number of pixel times that the encoder waits before
+* transmitting data from its rate buffer.
+* PPS16[7:2] - Reserved
+*/
+
[Intel-gfx] ✓ Fi.CI.IGT: success for HDCP1.4 fixes (rev8)
== Series Details ==
Series: HDCP1.4 fixes (rev8)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5209_full -> Patchwork_10912_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10912_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_exec_schedule@pi-ringfull-vebox:
shard-skl: NOTRUN -> FAIL ([fdo#103158])
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-skl: NOTRUN -> TIMEOUT ([fdo#108039])
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: PASS -> INCOMPLETE ([fdo#103665], [fdo#106023],
[fdo#106887])
igt@gem_userptr_blits@readonly-unsync:
shard-skl: NOTRUN -> INCOMPLETE ([fdo#108074])
igt@i915_suspend@shrink:
shard-snb: NOTRUN -> DMESG-WARN ([fdo#108784])
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-skl: PASS -> INCOMPLETE ([fdo#104108])
igt@kms_cursor_crc@cursor-128x42-random:
shard-glk: PASS -> FAIL ([fdo#103232]) +1
shard-apl: PASS -> FAIL ([fdo#103232]) +1
igt@kms_fbcon_fbt@fbc-suspend:
shard-skl: PASS -> INCOMPLETE ([fdo#104108], [fdo#107773]) +1
igt@kms_fbcon_fbt@psr:
shard-skl: NOTRUN -> FAIL ([fdo#107882])
igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
shard-glk: PASS -> FAIL ([fdo#103060])
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: PASS -> FAIL ([fdo#105363])
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-skl: NOTRUN -> FAIL ([fdo#103167])
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
shard-apl: PASS -> FAIL ([fdo#103167])
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
{shard-iclb}: PASS -> FAIL ([fdo#103167]) +1
igt@kms_plane@pixel-format-pipe-c-planes:
shard-apl: PASS -> FAIL ([fdo#103166])
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
shard-skl: PASS -> FAIL ([fdo#103166])
igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
shard-skl: NOTRUN -> FAIL ([fdo#108145])
igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
shard-skl: NOTRUN -> FAIL ([fdo#103166], [fdo#107815])
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL ([fdo#103166]) +1
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
{shard-iclb}: PASS -> FAIL ([fdo#103166])
igt@pm_rpm@legacy-planes:
{shard-iclb}: PASS -> INCOMPLETE ([fdo#108840])
Possible fixes
igt@drm_import_export@import-close-race-flink:
shard-skl: TIMEOUT ([fdo#108667]) -> PASS
igt@gem_ctx_isolation@vcs0-s3:
shard-skl: INCOMPLETE ([fdo#104108], [fdo#107773]) -> PASS
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: FAIL ([fdo#108145]) -> PASS
igt@kms_cursor_crc@cursor-64x21-onscreen:
shard-apl: FAIL ([fdo#103232]) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-apl: FAIL ([fdo#103167]) -> PASS +2
igt@kms_frontbuffer_tracking@fbc-1p-rte:
shard-apl: FAIL ([fdo#103167], [fdo#105682]) -> PASS
igt@kms_frontbuffer_tracking@fbc-suspend:
shard-skl: INCOMPLETE ([fdo#104108], [fdo#105959], [fdo#107773])
-> PASS
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
{shard-iclb}: FAIL ([fdo#103167]) -> PASS +3
igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
shard-skl: FAIL ([fdo#103166]) -> PASS
igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
shard-apl: FAIL ([fdo#108145]) -> PASS
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
{shard-iclb}: FAIL ([fdo#103166]) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
shard-glk: FAIL ([fdo#103166]) -> PASS
igt@kms_setmode@basic:
shard-kbl: FAIL ([fdo#99912]) -> PASS
igt@perf_pmu@rc6-runtime-pm-long:
shard-skl: FAIL ([fdo#105010]) -> PASS
Warnings
igt@kms_content_protection@legacy:
shard-apl: FAIL ([fdo#108597]) -> INCOMPLETE ([fdo#103927])
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103665
