[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug (rev3)
== Series Details ==
Series: drm/i915/psr: Execute the default PSR code path when setting
i915_edp_psr_debug (rev3)
URL : https://patchwork.freedesktop.org/series/56013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5522_full -> Patchwork_12115_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12115_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540] / [fdo#109482]
* igt@kms_color@pipe-c-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +2
- shard-apl: PASS -> FAIL [fdo#103166] +1
Possible fixes
* igt@gem_exec_blt@cold:
- shard-glk: DMESG-WARN [fdo#105763] / [fdo#106538] -> PASS
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-hsw: FAIL [fdo#99912] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109482]: https://bugs.freedesktop.org/show_bug.cgi?id=109482
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 4)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5522 -> Patchwork_12115
CI_DRM_5522: 3f287cb6d4ae4689eb7c53e4c25f0fba3df16438 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12115: 918de5c71b79aba838256f798383ca2a506b4d82 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12115/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow normal clients to always preempt idle priority clients
== Series Details ==
Series: drm/i915: Allow normal clients to always preempt idle priority clients
URL : https://patchwork.freedesktop.org/series/56072/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5522_full -> Patchwork_12114_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12114_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@noreloc-s3:
- shard-snb: PASS -> DMESG-WARN [fdo#102365]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-glk: PASS -> FAIL [fdo#103166] +2
Possible fixes
* igt@gem_exec_blt@cold:
- shard-glk: DMESG-WARN [fdo#105763] / [fdo#106538] -> PASS
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-glk: FAIL [fdo#103166] -> PASS +1
Warnings
* igt@i915_suspend@shrink:
- shard-snb: DMESG-WARN [fdo#109244] -> INCOMPLETE [fdo#105411] /
[fdo#106886]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (6 -> 4)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5522 -> Patchwork_12114
CI_DRM_5522: 3f287cb6d4ae4689eb7c53e4c25f0fba3df16438 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12114: 0f047db616837cfdcac1e08e596030251cee34ef @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12114/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cfl: Adding another PCI Device ID.
== Series Details ==
Series: drm/i915/cfl: Adding another PCI Device ID.
URL : https://patchwork.freedesktop.org/series/56075/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5522 -> Patchwork_12116
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56075/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12116 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@gem_ctx_create@basic-files:
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#103665]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@i915_selftest@live_hangcheck:
- fi-glk-j4005: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- fi-kbl-7567u: {SKIP} [fdo#109271] -> PASS +1
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: {SKIP} [fdo#109271] -> PASS +33
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (49 -> 44)
--
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan fi-icl-u2 fi-ctg-p8600
Build changes
-
* Linux: CI_DRM_5522 -> Patchwork_12116
CI_DRM_5522: 3f287cb6d4ae4689eb7c53e4c25f0fba3df16438 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12116: ab594f4fdd62f7e043b94092a218ba1b52af293d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ab594f4fdd62 drm/i915/cfl: Adding another PCI Device ID.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12116/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] gvt-next
Hi, This should be last gvt-next pull for this round, which adds VFIO edid region support in GVT, VM manager can use this to specify custom EDID for VM, which can be used for e.g UI resize, etc. p.s, Next week will be chinese new year, so team will be offline then. Thanks. -- The following changes since commit 2e679d48f38c378650db403b4ba2248adf0691b2: drm/i915/gvt: switch to kernel types (2019-01-23 13:56:14 +0800) are available in the Git repository at: https://github.com/intel/gvt-linux.git tags/gvt-next-2019-02-01 for you to fetch changes up to 39c68e87bc50a71bcfe93582d9b0673ef30db418: drm/i915/gvt: add VFIO EDID region (2019-01-31 11:41:25 +0800) gvt-next-2019-02-01 - new VFIO EDID region support (Henry) Hang Yuan (3): drm/i915/gvt: add functions to get default resolution drm/i915/gvt: add hotplug emulation drm/i915/gvt: add VFIO EDID region drivers/gpu/drm/i915/gvt/display.c | 31 drivers/gpu/drm/i915/gvt/display.h | 37 +++-- drivers/gpu/drm/i915/gvt/gvt.c | 1 + drivers/gpu/drm/i915/gvt/gvt.h | 3 + drivers/gpu/drm/i915/gvt/hypercall.h | 1 + drivers/gpu/drm/i915/gvt/kvmgt.c | 143 +++ drivers/gpu/drm/i915/gvt/mpt.h | 17 + drivers/gpu/drm/i915/gvt/vgpu.c | 6 ++ 8 files changed, 233 insertions(+), 6 deletions(-) -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/cfl: Adding another PCI Device ID.
== Series Details == Series: drm/i915/cfl: Adding another PCI Device ID. URL : https://patchwork.freedesktop.org/series/56075/ State : warning == Summary == $ dim checkpatch origin/drm-tip ab594f4fdd62 drm/i915/cfl: Adding another PCI Device ID. -:13: WARNING:BAD_SIGN_OFF: email address 'Dmitry Rogozhkin' might be better as 'Dmitry Rogozhkin ' #13: Reported-by: Dmitry Rogozhkin -:14: WARNING:BAD_SIGN_OFF: email address 'Dmitry Rogozhkin' might be better as 'Dmitry Rogozhkin ' #14: Cc: Dmitry Rogozhkin total: 0 errors, 2 warnings, 0 checks, 16 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cfl: Adding another PCI Device ID.
While cross checking PCI IDs from Intel Media SDK and kernel Dmitry noticed this gap. So we checked the spec and this new ID had been recently added. Reported-by: Dmitry Rogozhkin Cc: Dmitry Rogozhkin Cc: José Roberto de Souza Signed-off-by: Rodrigo Vivi --- include/drm/i915_pciids.h | 4 1 file changed, 4 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index df72be7e8b88..d2fad7b0fcf6 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -394,6 +394,9 @@ INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ /* CFL H */ +#define INTEL_CFL_H_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x3E9C, info) + #define INTEL_CFL_H_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ @@ -426,6 +429,7 @@ #define INTEL_CFL_IDS(info) \ INTEL_CFL_S_GT1_IDS(info), \ INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT1_IDS(info), \ INTEL_CFL_H_GT2_IDS(info), \ INTEL_CFL_U_GT2_IDS(info), \ INTEL_CFL_U_GT3_IDS(info), \ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-tip:drm-tip 891/897] drivers/gpu/drm/amd/amdgpu/../display/modules/power/power_helpers.c:160:9: warning: #pragma pack (pop) encountered without matching #pragma pack (push)
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: 3f287cb6d4ae4689eb7c53e4c25f0fba3df16438
commit: 0a2fe4901d16d28bb8ad5f7032e9579f85e7e594 [891/897] Merge
remote-tracking branch 'drm/drm-next' into drm-tip
config: riscv-allmodconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 8.2.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 0a2fe4901d16d28bb8ad5f7032e9579f85e7e594
# save the attached .config to linux build tree
GCC_VERSION=8.2.0 make.cross ARCH=riscv
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/modules/power/power_helpers.c:160:9:
>> warning: #pragma pack (pop) encountered without matching #pragma pack (push)
>> [-Wpragmas]
#pragma pack(pop)
^~~~
vim +160 drivers/gpu/drm/amd/amdgpu/../display/modules/power/power_helpers.c
bf75572a Josip Pavic 2019-01-08 117
bf75572a Josip Pavic 2019-01-08 118 struct iram_table_v_2_2 {
bf75572a Josip Pavic 2019-01-08 119 /* flags */
bf75572a Josip Pavic 2019-01-08 120 uint16_t flags;
/* 0x00 U16 */
bf75572a Josip Pavic 2019-01-08 121
bf75572a Josip Pavic 2019-01-08 122 /* parameters for ABM2.2
algorithm */
bf75572a Josip Pavic 2019-01-08 123 uint8_t
min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */
bf75572a Josip Pavic 2019-01-08 124 uint8_t
max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
bf75572a Josip Pavic 2019-01-08 125 uint8_t
bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];/* 0x2a U2.6 */
bf75572a Josip Pavic 2019-01-08 126 uint8_t
dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
bf75572a Josip Pavic 2019-01-08 127 uint8_t
hybridFactor[NUM_AGGR_LEVEL]; /* 0x52
U0.8 */
bf75572a Josip Pavic 2019-01-08 128 uint8_t
contrastFactor[NUM_AGGR_LEVEL]; /* 0x56
U0.8 */
bf75572a Josip Pavic 2019-01-08 129 uint8_t
deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a
U0.8 */
bf75572a Josip Pavic 2019-01-08 130 uint8_t
iir_curve[NUM_AMBI_LEVEL];
/* 0x5e U0.8 */
bf75572a Josip Pavic 2019-01-08 131 uint8_t pad[29];
/* 0x63
U0.8 */
bf75572a Josip Pavic 2019-01-08 132
bf75572a Josip Pavic 2019-01-08 133 /* parameters for crgb
conversion */
bf75572a Josip Pavic 2019-01-08 134 uint16_t
crgb_thresh[NUM_POWER_FN_SEGS];/* 0x80
U3.13 */
bf75572a Josip Pavic 2019-01-08 135 uint16_t
crgb_offset[NUM_POWER_FN_SEGS];/* 0x90
U1.15 */
bf75572a Josip Pavic 2019-01-08 136 uint16_t
crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0
U4.12 */
bf75572a Josip Pavic 2019-01-08 137
bf75572a Josip Pavic 2019-01-08 138 /* parameters for custom curve
*/
bf75572a Josip Pavic 2019-01-08 139 /* thresholds for brightness
--> backlight */
bf75572a Josip Pavic 2019-01-08 140 uint16_t
backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */
bf75572a Josip Pavic 2019-01-08 141 /* offsets for brightness -->
backlight */
bf75572a Josip Pavic 2019-01-08 142 uint16_t
backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */
bf75572a Josip Pavic 2019-01-08 143
bf75572a Josip Pavic 2019-01-08 144 /* For reading PSR State
directly from IRAM */
bf75572a Josip Pavic 2019-01-08 145 uint8_t psr_state;
/* 0xf0
*/
bf75572a Josip Pavic 2019-01-08 146 uint8_t
dmcu_mcp_interface_version;
/* 0xf1 */
bf75572a Josip Pavic 2019-01-08 147 uint8_t
dmcu_abm_feature_version;
/* 0xf2 */
bf75572a Josip Pavic 2019-01-08 148 uint8_t
dmcu_psr_feature_version;
/* 0xf3 */
bf75572a Josip Pavic 2019-01-08 149 uint16_t dmcu_version;
/* 0xf4 */
bbf854dc David Francis 2018-11-26 150 uint8_t dmcu_state;
/* 0xf6
*/
bbf854dc David Francis 2018-11-26 151
bbf854
[Intel-gfx] ✓ Fi.CI.IGT: success for restore WaEnableFloatBlendOptimization
== Series Details ==
Series: restore WaEnableFloatBlendOptimization
URL : https://patchwork.freedesktop.org/series/56071/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5521_full -> Patchwork_12113_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12113_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@runner@aborted}:
- shard-snb: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12113_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#106509] / [fdo#107409]
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
Possible fixes
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-apl: FAIL [fdo#103166] -> PASS +1
Warnings
* igt@gem_exec_params@rel-constants-invalid-rel-gen5:
- shard-snb: INCOMPLETE [fdo#105411] / [fdo#107469] -> DMESG-WARN
[fdo#107469]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
[fdo#107469]: https://bugs.freedesktop.org/show_bug.cgi?id=107469
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 4)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5521 -> Patchwork_12113
CI_DRM_5521: dbd2e19079beb3b7f4077706179fba66d321e49f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12113: b3ca9b19919023e1bda80d7e66a3f8f3009dbc83 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12113/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for CRTC background color (rev6)
== Series Details ==
Series: CRTC background color (rev6)
URL : https://patchwork.freedesktop.org/series/50834/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5521_full -> Patchwork_12112_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12112_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind:
- shard-hsw: PASS -> DMESG-WARN [fdo#102614] +1
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#105454] / [fdo#106509]
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
Possible fixes
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS +2
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 4)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5521 -> Patchwork_12112
CI_DRM_5521: dbd2e19079beb3b7f4077706179fba66d321e49f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12112: 7d3a7c26e2ef212cb7e71c1ec19308d6f27b6506 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12112/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug (rev3)
== Series Details ==
Series: drm/i915/psr: Execute the default PSR code path when setting
i915_edp_psr_debug (rev3)
URL : https://patchwork.freedesktop.org/series/56013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5522 -> Patchwork_12115
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56013/revisions/3/mbox/
Known issues
Here are the changes found in Patchwork_12115 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- fi-kbl-7567u: {SKIP} [fdo#109271] -> PASS +1
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: {SKIP} [fdo#109271] -> PASS +33
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (49 -> 45)
--
Missing(4): fi-kbl-soraka fi-ctg-p8600 fi-bsw-cyan fi-ilk-m540
Build changes
-
* Linux: CI_DRM_5522 -> Patchwork_12115
CI_DRM_5522: 3f287cb6d4ae4689eb7c53e4c25f0fba3df16438 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12115: 918de5c71b79aba838256f798383ca2a506b4d82 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
918de5c71b79 drm/i915/psr: Execute the default PSR code path when setting
i915_edp_psr_debug
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12115/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow normal clients to always preempt idle priority clients
== Series Details ==
Series: drm/i915: Allow normal clients to always preempt idle priority clients
URL : https://patchwork.freedesktop.org/series/56072/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5522 -> Patchwork_12114
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56072/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12114:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_hangcheck:
- {fi-icl-y}: PASS -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12114 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182] +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- fi-kbl-7567u: {SKIP} [fdo#109271] -> PASS +1
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: {SKIP} [fdo#109271] -> PASS +33
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (49 -> 45)
--
Missing(4): fi-kbl-soraka fi-ctg-p8600 fi-bsw-cyan fi-ilk-m540
Build changes
-
* Linux: CI_DRM_5522 -> Patchwork_12114
CI_DRM_5522: 3f287cb6d4ae4689eb7c53e4c25f0fba3df16438 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12114: 0f047db616837cfdcac1e08e596030251cee34ef @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0f047db61683 drm/i915: Allow normal clients to always preempt idle priority
clients
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12114/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
== Series Details ==
Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
URL : https://patchwork.freedesktop.org/series/56059/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5520_full -> Patchwork_12111_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12111_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic-modeset-a:
- shard-glk: NOTRUN -> FAIL [fdo#109490]
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-apl: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: NOTRUN -> FAIL [fdo#105454] / [fdo#106509]
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@gem_mmap_gtt@hang:
- shard-glk: FAIL [fdo#109469] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-snb: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-pageflip-hang-newfb-render-a:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109469]: https://bugs.freedesktop.org/show_bug.cgi?id=109469
[fdo#109490]: https://bugs.freedesktop.org/show_bug.cgi?id=109490
Participating hosts (6 -> 4)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5520 -> Patchwork_12111
CI_DRM_5520: 91343140b5792a21430708ad761feaf17b8ae1a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12111: 49b8aff26fa20cf63e93cb18f5a8d473e6a31cc6 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12111/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow normal clients to always preempt idle priority clients
== Series Details == Series: drm/i915: Allow normal clients to always preempt idle priority clients URL : https://patchwork.freedesktop.org/series/56072/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Allow normal clients to always preempt idle priority clients -O:drivers/gpu/drm/i915/intel_ringbuffer.h:595:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_ringbuffer.h:595:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_ringbuffer.h:608:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_ringbuffer.h:608:23: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Allow normal clients to always preempt idle priority clients
== Series Details ==
Series: drm/i915: Allow normal clients to always preempt idle priority clients
URL : https://patchwork.freedesktop.org/series/56072/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0f047db61683 drm/i915: Allow normal clients to always preempt idle priority
clients
-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#24:
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between
submission ports")
-:24: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit f6322eddaff7
("drm/i915/preemption: Allow preemption between submission ports")'
#24:
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between
submission ports")
-:25: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit b16c765122f9 ("drm/i915:
Priority boost for new clients")'
#25:
References: b16c765122f9 ("drm/i915: Priority boost for new clients")
-:49: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#49: FILE: drivers/gpu/drm/i915/intel_ringbuffer.h:603:
+^I * ^Iprio >= max(0, last);$
total: 2 errors, 2 warnings, 0 checks, 21 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug
On Thu, 2019-01-31 at 10:34 +0100, Maarten Lankhorst wrote: > Op 31-01-2019 om 01:58 schreef José Roberto de Souza: > > Changing the i915_edp_psr_debug was enabling, disabling or > > switching > > PSR version by directly calling intel_psr_disable_locked() and > > intel_psr_enable_locked(), what is not the default PSR path that > > will > > be executed by real users. > > > > So lets force a fastset in the PSR CRTC to trigger a pipe update > > and > > stress the default code path. > > > > Recently a bug was found when switching from PSR2 to PSR1 while > > enable_psr kernel parameter was set to the default parameter, this > > changes fix it and also fixes the bug linked bellow were DRRS was > > left enabled together with PSR when enabling PSR from debugfs. > > > > v2: Handling missing case: disabled to PSR1 > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341 > > Cc: Maarten Lankhorst > > Cc: Dhinakaran Pandiyan > > Cc: Rodrigo Vivi > > Signed-off-by: José Roberto de Souza > > --- > > > > Should I add IGT tests to test every state switch combination? > > Should probably be done for DRRS as well. We should be able to stop > having to set has_drrs and has_psr unconditionally then. :) > Could be a separate followup patch. I have DRRS/PSR bugs assigned to me, I will definitely fix that in the future. > > The complete duplication of the whole atomic state is overkill and > should be avoided, just use > if (!intel_crtc_has_type(to_intel_crtc_state(crtc->state), > INTEL_OUTPUT_EDP) > continue; > > crtc_state = drm_atomic_get_old_crtc_state(...) > > > And then do a normal commit. We will add all planes and connectors as > needed. Thanks for the suggestion, just sent the new version with this. > > With that fixed: > Reviewed-by: Maarten Lankhorst > signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug
Changing the i915_edp_psr_debug was enabling, disabling or switching
PSR version by directly calling intel_psr_disable_locked() and
intel_psr_enable_locked(), what is not the default PSR path that will
be executed by real users.
So lets force a fastset in the PSR CRTC to trigger a pipe update and
stress the default code path.
Recently a bug was found when switching from PSR2 to PSR1 while
enable_psr kernel parameter was set to the default parameter, this
changes fix it and also fixes the bug linked bellow were DRRS was
left enabled together with PSR when enabling PSR from debugfs.
v2: Handling missing case: disabled to PSR1
v3: Not duplicating the whole atomic state(Maarten)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c| 2 +-
drivers/gpu/drm/i915/intel_drv.h| 6 +-
drivers/gpu/drm/i915/intel_psr.c| 188 +---
5 files changed, 119 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fa2c226fc779..766a5b4ad3d6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2607,7 +2607,6 @@ static int
i915_edp_psr_debug_set(void *data, u64 val)
{
struct drm_i915_private *dev_priv = data;
- struct drm_modeset_acquire_ctx ctx;
intel_wakeref_t wakeref;
int ret;
@@ -2618,18 +2617,7 @@ i915_edp_psr_debug_set(void *data, u64 val)
wakeref = intel_runtime_pm_get(dev_priv);
- drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
-
-retry:
- ret = intel_psr_set_debugfs_mode(dev_priv, &ctx, val);
- if (ret == -EDEADLK) {
- ret = drm_modeset_backoff(&ctx);
- if (!ret)
- goto retry;
- }
-
- drm_modeset_drop_locks(&ctx);
- drm_modeset_acquire_fini(&ctx);
+ ret = intel_psr_set_debugfs_mode(dev_priv, val);
intel_runtime_pm_put(dev_priv, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f11c66d172d3..baee581a0d5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -496,7 +496,7 @@ struct i915_psr {
u32 debug;
bool sink_support;
- bool prepared, enabled;
+ bool enabled;
struct intel_dp *dp;
enum pipe pipe;
bool active;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ca705546a0ab..9211e4579489 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3556,7 +3556,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
intel_panel_update_backlight(encoder, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 90ba5436370e..4c01decc30d3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2067,9 +2067,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
void intel_psr_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state);
-int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
- struct drm_modeset_acquire_ctx *ctx,
- u64 value);
+void intel_psr_update(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
+int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, u64 value);
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 84a0fb981561..e970ffd7dd0d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -51,6 +51,8 @@
* must be correctly synchronized/cancelled when shutting down the pipe."
*/
+#include
+#include
#include "intel_drv.h"
#include "i915_drv.h"
@@ -718,8 +720,11 @@ static void intel_psr_enable_locked(struct
drm_i915_private *dev_priv,
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
- if (dev_priv->psr.enabled)
- return;
+ WARN_ON(dev_priv->psr.enabled);
+
+ dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
+ dev_priv->psr.busy_frontbuffer_bits = 0;
+ dev_priv->psr.pipe = to_int
[Intel-gfx] ✓ Fi.CI.BAT: success for restore WaEnableFloatBlendOptimization
== Series Details ==
Series: restore WaEnableFloatBlendOptimization
URL : https://patchwork.freedesktop.org/series/56071/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5521 -> Patchwork_12113
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56071/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12113 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-ilk-650: PASS -> DMESG-WARN [fdo#106387]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS
- {fi-icl-y}: INCOMPLETE -> PASS
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
Participating hosts (49 -> 44)
--
Missing(5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5521 -> Patchwork_12113
CI_DRM_5521: dbd2e19079beb3b7f4077706179fba66d321e49f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12113: b3ca9b19919023e1bda80d7e66a3f8f3009dbc83 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b3ca9b199190 drm/i915/icl: restore WaEnableFloatBlendOptimization
3724f3bfa9a7 drm/i915: Save some lines of source code in workarounds
5ff28df401d6 drm/i915: Move workaround infrastructure code up
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12113/
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[Intel-gfx] [PATCH] drm/i915: Allow normal clients to always preempt idle priority clients
When first enabling preemption, we hesitated from making it a free-for-all
where every higher priority client would force a preempt-to-idle cycle
and take over from all lower priority clients. We hesitated because we
were uncertain just how well preemption would work in practice, whether
the preemption latency itself would detract from the latency gains for
higher priority tasks and whether it would work at all. Since
introducing preemption, we have been enabling it for more common tasks,
even giving normal clients a small preemptive boost when they first
start (to aide fairness and improve interactivity). Now lets take one
step further and give permission for all normal (priority:0) clients to
preempt any idle (priority:<0) task so that users running long compute
jobs do not overly impact other jobs (i.e. their desktop) and the system
remains responsive under such idle loads.
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between
submission ports")
References: b16c765122f9 ("drm/i915: Priority boost for new clients")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Cc: "Bloomfield, Jon"
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 34d0a148e664..983ad1e7914d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -592,7 +592,20 @@ intel_engine_has_preemption(const struct intel_engine_cs
*engine)
static inline bool __execlists_need_preempt(int prio, int last)
{
- return prio > max(0, last);
+ /*
+* Allow preemption of low -> normal -> high, but we do
+* not allow low priority tasks to preempt other low priority
+* tasks under the impression that latency for low priority
+* tasks does not matter (as much as background throughput),
+* so kiss.
+*
+* More naturally we would write
+* prio >= max(0, last);
+* except that we wish to prevent triggering preemption at the same
+* priority level: the task that is running should remain running
+* to preserve FIFO ordering of dependencies.
+*/
+ return prio > max(I915_PRIORITY_NORMAL - 1, last);
}
static inline void
--
2.20.1
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/icl: restore WaEnableFloatBlendOptimization
Quoting Talha Nassar (2019-02-01 01:08:44)
> Enables blend optimization for floating point RTs
>
> This restores the workaround that was reverted in c358514ba8da
> ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"").
>
> The revert was due to the register write seemingly not sticking,
> but the HW team has confirmed that this is because the
> register is WO and that the workaround is indeed required.
>
> Here the wa is added with a mask of 0 since the register is WO.
>
> References: https://hsdes.intel.com/resource/1408134172
> References: https://bugs.freedesktop.org/show_bug.cgi?id=107338
> Cc: Chris Wilson
> Cc: Mika Kuoppala
>
> Signed-off-by: Talha Nassar
Vouching for the code, not the hw,
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Move workaround infrastructure code up
Quoting Talha Nassar (2019-02-01 01:08:42) > From: Tvrtko Ursulin > > Top comment in intel_workarounds.c says common code should come first so > lets respect that. Also, by moving the common code together opportunities > to reduce duplication will become more obvious. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for restore WaEnableFloatBlendOptimization
== Series Details ==
Series: restore WaEnableFloatBlendOptimization
URL : https://patchwork.freedesktop.org/series/56071/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5ff28df401d6 drm/i915: Move workaround infrastructure code up
3724f3bfa9a7 drm/i915: Save some lines of source code in workarounds
b3ca9b199190 drm/i915/icl: restore WaEnableFloatBlendOptimization
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit c358514ba8da ("Revert
"drm/i915/icl: WaEnableFloatBlendOptimization"")'
#8:
This restores the workaround that was reverted in c358514ba8da
total: 1 errors, 0 warnings, 0 checks, 21 lines checked
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[Intel-gfx] [PATCH v2 0/4] drm/dp_mst: Fix regressions from new atomic VCPI helpers
This fixes the extra issues I discovered upstream after the introduction of my rework of the atomic VCPI helpers that occur during suspend/resume. This time around, we use a slightly different but much less complicated approach for fixing said issues. Cc: Daniel Vetter Lyude Paul (4): drm/dp_mst: Fix unbalanced malloc ref in drm_dp_mst_deallocate_vcpi() drm/dp_mst: Remove port validation in drm_dp_atomic_find_vcpi_slots() drm/atomic: Add drm_atomic_state->duplicated drm/nouveau: Move PBN and VCPI allocation into nv50_head_atom drivers/gpu/drm/drm_atomic_helper.c | 10 - drivers/gpu/drm/drm_dp_mst_topology.c | 51 + drivers/gpu/drm/i915/intel_dp_mst.c | 17 +++-- drivers/gpu/drm/nouveau/dispnv50/atom.h | 6 +++ drivers/gpu/drm/nouveau/dispnv50/disp.c | 31 --- drivers/gpu/drm/nouveau/dispnv50/head.c | 1 + include/drm/drm_atomic.h| 9 + 7 files changed, 85 insertions(+), 40 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/3] drm/i915: Save some lines of source code in workarounds
From: Tvrtko Ursulin
No functional or code size change - just notice we can compact the source
by re-using a single helper for adding workarounds.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_workarounds.c | 32 ++--
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 584c4a5..5c01055 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -142,7 +142,8 @@ static void _wa_add(struct i915_wa_list *wal, const struct
i915_wa *wa)
}
static void
-__wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+ u32 val)
{
struct i915_wa wa = {
.reg = reg,
@@ -156,26 +157,7 @@ __wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32
mask, u32 val)
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- struct i915_wa wa = {
- .reg = reg,
- .mask = val,
- .val = _MASKED_BIT_ENABLE(val)
- };
-
- _wa_add(wal, &wa);
-}
-
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
- u32 val)
-{
- struct i915_wa wa = {
- .reg = reg,
- .mask = mask,
- .val = val
- };
-
- _wa_add(wal, &wa);
+ wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
}
static void
@@ -190,16 +172,14 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32
val)
wa_write_masked_or(wal, reg, val, val);
}
-#define WA_REG(addr, mask, val) __wa_add(wal, (addr), (mask), (val))
-
#define WA_SET_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
#define WA_CLR_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
#define WA_SET_FIELD_MASKED(addr, mask, value) \
- WA_REG(addr, (mask), _MASKED_FIELD(mask, value))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine)
{
--
2.7.4
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[Intel-gfx] [PATCH v2 0/3] restore WaEnableFloatBlendOptimization
This is the v2 of my patch after taking the feed from Chris. I have also included the HSDES per Mika's suggestion. I am attaching the two-patch series from Tvrtko as there is a dependency. Also to note that git couldn't apply Tvrtko's first patch due to a patch by Daniele that touched the same file and was merged. I had to manually apply the patch and no code changes were necessary. v1: enabled the wa and added the register as wo in igt test. v2: also modified the wa mask Cc: Tvrtko Ursulin Cc: Chris Wilson Talha Nassar (1): drm/i915/icl: restore WaEnableFloatBlendOptimization Tvrtko Ursulin (2): drm/i915: Move workaround infrastructure code up drm/i915: Save some lines of source code in workarounds drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_workarounds.c | 70 +--- 2 files changed, 31 insertions(+), 42 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/3] drm/i915/icl: restore WaEnableFloatBlendOptimization
Enables blend optimization for floating point RTs
This restores the workaround that was reverted in c358514ba8da
("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"").
The revert was due to the register write seemingly not sticking,
but the HW team has confirmed that this is because the
register is WO and that the workaround is indeed required.
Here the wa is added with a mask of 0 since the register is WO.
References: https://hsdes.intel.com/resource/1408134172
References: https://bugs.freedesktop.org/show_bug.cgi?id=107338
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Talha Nassar
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03adcf3..6b96477 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2801,6 +2801,9 @@ enum i915_power_well_id {
#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
+#define GEN10_CACHE_MODE_SS_MMIO(0xe420)
+#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+
/* Fuse readout registers for GT */
#define HSW_PAVP_FUSE1 _MMIO(0x911C)
#define HSW_F1_EU_DIS_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5c01055..15f4a6d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -549,6 +549,12 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine)
if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
+ /* WaEnableFloatBlendOptimization:icl */
+ wa_write_masked_or(wal,
+ GEN10_CACHE_MODE_SS,
+ 0, /* write-only, so skip validation */
+ _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
}
void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
--
2.7.4
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[Intel-gfx] [PATCH v2 1/3] drm/i915: Move workaround infrastructure code up
From: Tvrtko Ursulin
Top comment in intel_workarounds.c says common code should come first so
lets respect that. Also, by moving the common code together opportunities
to reduce duplication will become more obvious.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 74
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3210ad4..584c4a5 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -153,6 +153,43 @@ __wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32
mask, u32 val)
_wa_add(wal, &wa);
}
+static void
+wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .mask = val,
+ .val = _MASKED_BIT_ENABLE(val)
+ };
+
+ _wa_add(wal, &wa);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+ u32 val)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .mask = mask,
+ .val = val
+ };
+
+ _wa_add(wal, &wa);
+}
+
+static void
+wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_write_masked_or(wal, reg, ~0, val);
+}
+
+static void
+wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_write_masked_or(wal, reg, val, val);
+}
+
#define WA_REG(addr, mask, val) __wa_add(wal, (addr), (mask), (val))
#define WA_SET_BIT_MASKED(addr, mask) \
@@ -603,43 +640,6 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
}
static void
-wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
-{
- struct i915_wa wa = {
- .reg = reg,
- .mask = val,
- .val = _MASKED_BIT_ENABLE(val)
- };
-
- _wa_add(wal, &wa);
-}
-
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
- u32 val)
-{
- struct i915_wa wa = {
- .reg = reg,
- .mask = mask,
- .val = val
- };
-
- _wa_add(wal, &wa);
-}
-
-static void
-wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
-{
- wa_write_masked_or(wal, reg, ~0, val);
-}
-
-static void
-wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
-{
- wa_write_masked_or(wal, reg, val, val);
-}
-
-static void
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
/* WaDisableKillLogic:bxt,skl,kbl */
--
2.7.4
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[Intel-gfx] [PATCH v2 2/4] drm/dp_mst: Remove port validation in drm_dp_atomic_find_vcpi_slots()
Since we now have an easy way of refcounting drm_dp_mst_port structs and
safely accessing their contents, there isn't any good reason to keep
validating ports here. It doesn't prevent us from performing modesets on
branch devices that have been removed either, and we already disallow
enabling new displays on unregistered connectors in
update_connector_routing() in drm_atomic_check_modeset(). All it does is
cause us to have to make weird special exceptions in our atomic
modesetting code. So, get rid of it entirely.
Signed-off-by: Lyude Paul
Fixes: eceae1472467 ("drm/dp_mst: Start tracking per-port VCPI allocations")
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_dp_mst_topology.c | 12 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 17 ++---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
3 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index abb0ea8ba9d9..4325e1518286 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3117,10 +3117,6 @@ int drm_dp_atomic_find_vcpi_slots(struct
drm_atomic_state *state,
if (IS_ERR(topology_state))
return PTR_ERR(topology_state);
- port = drm_dp_mst_topology_get_port_validated(mgr, port);
- if (port == NULL)
- return -EINVAL;
-
/* Find the current allocation for this port, if any */
list_for_each_entry(pos, &topology_state->vcpis, next) {
if (pos->port == port) {
@@ -3153,10 +3149,8 @@ int drm_dp_atomic_find_vcpi_slots(struct
drm_atomic_state *state,
/* Add the new allocation to the state */
if (!vcpi) {
vcpi = kzalloc(sizeof(*vcpi), GFP_KERNEL);
- if (!vcpi) {
- ret = -ENOMEM;
- goto out;
- }
+ if (!vcpi)
+ return -ENOMEM;
drm_dp_mst_get_port_malloc(port);
vcpi->port = port;
@@ -3165,8 +3159,6 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state
*state,
vcpi->vcpi = req_slots;
ret = req_slots;
-out:
- drm_dp_mst_topology_put_port(port);
return ret;
}
EXPORT_SYMBOL(drm_dp_atomic_find_vcpi_slots);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index cdb83d294cdd..fb67cd931117 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -80,17 +80,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
pipe_config->pbn = mst_pbn;
- /* Zombie connectors can't have VCPI slots */
- if (!drm_connector_is_unregistered(connector)) {
- slots = drm_dp_atomic_find_vcpi_slots(state,
- &intel_dp->mst_mgr,
- port,
- mst_pbn);
- if (slots < 0) {
- DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
- slots);
- return slots;
- }
+ slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, port,
+ mst_pbn);
+ if (slots < 0) {
+ DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
+ slots);
+ return slots;
}
intel_link_compute_m_n(bpp, lane_count,
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 2e8a5fd9b262..60d858c2f2ce 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -771,8 +771,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock,
bpp);
- if (drm_atomic_crtc_needs_modeset(crtc_state) &&
- !drm_connector_is_unregistered(connector)) {
+ if (drm_atomic_crtc_needs_modeset(crtc_state)) {
slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
mstc->port, mstc->pbn);
if (slots < 0)
--
2.20.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for CRTC background color (rev6)
== Series Details ==
Series: CRTC background color (rev6)
URL : https://patchwork.freedesktop.org/series/50834/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5521 -> Patchwork_12112
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/50834/revisions/6/mbox/
Known issues
Here are the changes found in Patchwork_12112 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- {fi-icl-y}: INCOMPLETE -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (49 -> 45)
--
Additional (1): fi-hsw-4770r
Missing(5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5521 -> Patchwork_12112
CI_DRM_5521: dbd2e19079beb3b7f4077706179fba66d321e49f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12112: 7d3a7c26e2ef212cb7e71c1ec19308d6f27b6506 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7d3a7c26e2ef drm/i915: Add background color hardware readout and state check
e8c3b924963a drm/i915/gen9+: Add support for pipe background color (v5)
8c549af67706 drm: Add CRTC background color property (v5)
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12112/
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for CRTC background color (rev6)
== Series Details == Series: CRTC background color (rev6) URL : https://patchwork.freedesktop.org/series/50834/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm: Add CRTC background color property (v5) Okay! Commit: drm/i915/gen9+: Add support for pipe background color (v5) Okay! Commit: drm/i915: Add background color hardware readout and state check +drivers/gpu/drm/i915/intel_display.c:12067:17: warning: constant 0xFFC0FFC0FFC0 is so big it is long +drivers/gpu/drm/i915/intel_display.c:12067:17: warning: constant 0xFFC0FFC0FFC0 is so big it is long +drivers/gpu/drm/i915/intel_display.c:12067:17: warning: constant 0xFFC0FFC0FFC0 is so big it is long +drivers/gpu/drm/i915/intel_display.c:12067:17: warning: constant 0xFFC0FFC0FFC0 is so big it is long ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CRTC background color (rev6)
== Series Details ==
Series: CRTC background color (rev6)
URL : https://patchwork.freedesktop.org/series/50834/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c549af67706 drm: Add CRTC background color property (v5)
-:239: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'shift' - possible
side-effects?
#239: FILE: include/uapi/drm/drm_mode.h:931:
+#define DRM_ARGB_COMP(c, shift, numbits) \
+ (__u16)(((c) & 0xull << (shift)) >> ((shift) + 16 - (numbits)))
total: 0 errors, 0 warnings, 1 checks, 146 lines checked
e8c3b924963a drm/i915/gen9+: Add support for pipe background color (v5)
7d3a7c26e2ef drm/i915: Add background color hardware readout and state check
-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#65: FILE: drivers/gpu/drm/i915/intel_display.c:11801:
+#define PIPE_CONF_CHECK_LLX_MASKED(name, mask) do { \
+ if ((current_config->name & mask) != (pipe_config->name & mask)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "(expected 0x%016llx, found 0x%016llx)\n", \
+ current_config->name & mask, \
+ pipe_config->name & mask); \
+ ret = false; \
+ } \
+} while (0)
-:65: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as
'(name)' to avoid precedence issues
#65: FILE: drivers/gpu/drm/i915/intel_display.c:11801:
+#define PIPE_CONF_CHECK_LLX_MASKED(name, mask) do { \
+ if ((current_config->name & mask) != (pipe_config->name & mask)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "(expected 0x%016llx, found 0x%016llx)\n", \
+ current_config->name & mask, \
+ pipe_config->name & mask); \
+ ret = false; \
+ } \
+} while (0)
-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible
side-effects?
#65: FILE: drivers/gpu/drm/i915/intel_display.c:11801:
+#define PIPE_CONF_CHECK_LLX_MASKED(name, mask) do { \
+ if ((current_config->name & mask) != (pipe_config->name & mask)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "(expected 0x%016llx, found 0x%016llx)\n", \
+ current_config->name & mask, \
+ pipe_config->name & mask); \
+ ret = false; \
+ } \
+} while (0)
-:65: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'mask' may be better as
'(mask)' to avoid precedence issues
#65: FILE: drivers/gpu/drm/i915/intel_display.c:11801:
+#define PIPE_CONF_CHECK_LLX_MASKED(name, mask) do { \
+ if ((current_config->name & mask) != (pipe_config->name & mask)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "(expected 0x%016llx, found 0x%016llx)\n", \
+ current_config->name & mask, \
+ pipe_config->name & mask); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 4 checks, 62 lines checked
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 2/3] drm/i915/gen9+: Add support for pipe background color (v5)
Gen9+ platforms allow CRTC's to be programmed with a background/canvas
color below the programmable planes. Let's expose this for use by
compositors.
v2:
- Split out bgcolor sanitization and programming of csc/gamma bits to a
separate patch that we can land before the ABI changes are ready to
go in. (Ville)
- Change a temporary variable name to be more consistent with
other similar functions. (Ville)
- Change register name to SKL_CANVAS for consistency with the
CHV_CANVAS register.
v3:
- Switch register name back to SKL_BOTTOM_COLOR. (Ville)
- Use non-_FW register write. (Ville)
- Minor parameter rename for consistency. (Ville)
v4:
- Removed use of bgcolor_changed flag.
v5:
- s/uint64_t/u64/
Cc: dri-de...@lists.freedesktop.org
Cc: wei.c...@intel.com
Cc: harish.krupo@intel.com
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 +++
drivers/gpu/drm/i915/intel_display.c | 46 +++-
2 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fa2c226fc779..e96fef9fa97c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3092,6 +3092,15 @@ static int i915_display_info(struct seq_file *m, void
*unused)
intel_plane_info(m, crtc);
}
+ if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) {
+ u64 background = pipe_config->base.bgcolor;
+
+ seq_printf(m, "\tbackground color (10bpc): r=%x g=%x
b=%x\n",
+ DRM_ARGB_RED(background, 10),
+ DRM_ARGB_GREEN(background, 10),
+ DRM_ARGB_BLUE(background, 10));
+ }
+
seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
yesno(!crtc->cpu_fifo_underrun_disabled),
yesno(!crtc->pch_fifo_underrun_disabled));
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a6d8985fe2e0..469480fe01a4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3896,6 +3896,28 @@ void intel_finish_reset(struct drm_i915_private
*dev_priv)
clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
}
+static void
+skl_update_background_color(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u64 propval = crtc_state->base.bgcolor;
+ u32 tmp;
+
+ /* Hardware is programmed with 10 bits of precision */
+ tmp = DRM_ARGB_RED(propval, 10) << 20
+ | DRM_ARGB_GREEN(propval, 10) << 10
+ | DRM_ARGB_BLUE(propval, 10);
+
+ /*
+* Set CSC and gamma for bottom color to ensure background pixels
+* receive the same color transformations as plane content.
+*/
+ tmp |= SKL_BOTTOM_COLOR_CSC_ENABLE | SKL_BOTTOM_COLOR_GAMMA_ENABLE;
+
+ I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe), tmp);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
@@ -3931,15 +3953,8 @@ static void intel_update_pipe_config(const struct
intel_crtc_state *old_crtc_sta
ironlake_pfit_disable(old_crtc_state);
}
- /*
-* We don't (yet) allow userspace to control the pipe background color,
-* so force it to black, but apply pipe gamma and CSC so that its
-* handling will match how we program our planes.
-*/
if (INTEL_GEN(dev_priv) >= 9)
- I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
- SKL_BOTTOM_COLOR_GAMMA_ENABLE |
- SKL_BOTTOM_COLOR_CSC_ENABLE);
+ skl_update_background_color(new_crtc_state);
}
static void intel_fdi_normal_train(struct intel_crtc *crtc)
@@ -11042,6 +11057,8 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc_state);
+ struct drm_crtc_state *old_crtc_state =
+ drm_atomic_get_old_crtc_state(crtc_state->state, crtc);
int ret;
bool mode_changed = needs_modeset(crtc_state);
@@ -11069,6 +11086,9 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
crtc_state->planes_changed = true;
}
+ if (crtc_state->bgcolor != old_crtc_state->bgcolor)
+ pipe_config->update_pipe = true;
+
ret = 0;
if (dev_priv->display.compute_pipe_wm) {
ret = dev_p
[Intel-gfx] [PATCH v5 3/3] drm/i915: Add background color hardware readout and state check
We should support readout and verification of crtc background color as
we do with other pipe state. Note that our hardware holds less bits of
precision than the CRTC state allows, so we need to take care to only
verify the most significant bits of the color after performing readout.
At boot time the pipe color is already sanitized to full black as
required by ABI, so the new readout here won't break that requirement.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_display.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 469480fe01a4..ecbfc8ce7b54 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9740,6 +9740,7 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain power_domain;
u64 power_domain_mask;
+ u32 bgcolor;
bool active;
intel_crtc_init_scalers(crtc, pipe_config);
@@ -9806,6 +9807,15 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
pipe_config->pixel_multiplier = 1;
}
+ if (INTEL_GEN(dev_priv) >= 9) {
+ bgcolor = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
+ pipe_config->base.bgcolor =
+ drm_argb(10, 0x,
+bgcolor >> 20 & 0x3FF,
+bgcolor >> 10 & 0x3FF,
+bgcolor & 0x3FF);
+ }
+
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put_unchecked(dev_priv, power_domain);
@@ -11422,6 +11432,10 @@ static void intel_dump_pipe_config(struct intel_crtc
*crtc,
drm_rect_width(&state->base.dst),
drm_rect_height(&state->base.dst));
}
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ DRM_DEBUG_KMS("background color: %llx\n",
+ pipe_config->base.bgcolor);
}
static bool check_digital_port_conflicts(struct drm_atomic_state *state)
@@ -11784,6 +11798,16 @@ intel_pipe_config_compare(struct drm_i915_private
*dev_priv,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLX_MASKED(name, mask) do { \
+ if ((current_config->name & mask) != (pipe_config->name & mask)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "(expected 0x%016llx, found 0x%016llx)\n", \
+ current_config->name & mask, \
+ pipe_config->name & mask); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_I(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_err(adjust, __stringify(name), \
@@ -12035,6 +12059,14 @@ intel_pipe_config_compare(struct drm_i915_private
*dev_priv,
PIPE_CONF_CHECK_I(min_voltage_level);
+ /*
+* Hardware only holds top 10 bits of each color component; ignore
+* bottom six bits (and all of alpha) when comparing against readout.
+*/
+ if (INTEL_GEN(dev_priv) >= 9)
+ PIPE_CONF_CHECK_LLX_MASKED(base.bgcolor, 0xFFC0FFC0FFC0);
+
+#undef PIPE_CONF_CHECK_LLX_MASKED
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_BOOL
--
2.14.5
___
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[Intel-gfx] [PATCH v5 1/3] drm: Add CRTC background color property (v5)
Some display controllers can be programmed to present non-black colors
for pixels not covered by any plane (or pixels covered by the
transparent regions of higher planes). Compositors that want a UI with
a solid color background can potentially save memory bandwidth by
setting the CRTC background property and using smaller planes to display
the rest of the content.
To avoid confusion between different ways of encoding RGB data, we
define a standard 64-bit format that should be used for this property's
value. Helper functions and macros are provided to generate and dissect
values in this standard format with varying component precision values.
v2:
- Swap internal representation's blue and red bits to make it easier
to read if printed out. (Ville)
- Document bgcolor property in drm_blend.c. (Sean Paul)
- s/background_color/bgcolor/ for consistency between property name and
value storage field. (Sean Paul)
- Add a convenience function to attach property to a given crtc.
v3:
- Restructure ARGB component extraction macros to be easier to
understand and enclose the parameters in () to avoid calculations
if expressions are passed. (Sean Paul)
- s/rgba/argb/ in helper function/macro names. Even though the idea is
to not worry about the internal representation of the u64, it can
still be confusing to look at code that uses 'rgba' terminology, but
stores values with argb ordering. (Ville)
v4:
- Drop the bgcolor_changed flag. (Ville, Brian Starkey)
- Clarify in kerneldoc that background color is expected to undergo the
same pipe-level degamma/csc/gamma transformations that planes do.
(Brian Starkey)
- Update kerneldoc to indicate non-opaque colors are allowed, but are
generally only useful in special cases such as when writeback
connectors are used (Brian Starkey / Eric Anholt)
v5:
- Set crtc->state->bgcolor to solid black inside
drm_crtc_add_bgcolor_property() in case drivers don't do this
themselves. (Ville)
- Add kerneldoc to drm_crtc_add_bgcolor_property() function.
Cc: dri-de...@lists.freedesktop.org
Cc: wei.c...@intel.com
Cc: harish.krupo@intel.com
Cc: Ville Syrjälä
Cc: Sean Paul
Cc: Brian Starkey
Cc: Eric Anholt
Cc: Stéphane Marchesin
Cc: Daniel Vetter
Signed-off-by: Matt Roper
Reviewed-by(v2): Sean Paul
Reviewed-by: Brian Starkey
---
drivers/gpu/drm/drm_atomic_uapi.c | 4
drivers/gpu/drm/drm_blend.c | 41 ---
drivers/gpu/drm/drm_mode_config.c | 6 ++
include/drm/drm_blend.h | 1 +
include/drm/drm_crtc.h| 12
include/drm/drm_mode_config.h | 5 +
include/uapi/drm/drm_mode.h | 28 ++
7 files changed, 94 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 9a1f41adfc67..d569e20e34e3 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -469,6 +469,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc
*crtc,
return -EFAULT;
set_out_fence_for_crtc(state->state, crtc, fence_ptr);
+ } else if (property == config->bgcolor_property) {
+ state->bgcolor = val;
} else if (crtc->funcs->atomic_set_property) {
return crtc->funcs->atomic_set_property(crtc, state, property,
val);
} else {
@@ -503,6 +505,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
else if (property == config->prop_out_fence_ptr)
*val = 0;
+ else if (property == config->bgcolor_property)
+ *val = state->bgcolor;
else if (crtc->funcs->atomic_get_property)
return crtc->funcs->atomic_get_property(crtc, state, property,
val);
else
diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
index 0c78ca386cbe..2ff69fae385c 100644
--- a/drivers/gpu/drm/drm_blend.c
+++ b/drivers/gpu/drm/drm_blend.c
@@ -175,9 +175,22 @@
* plane does not expose the "alpha" property, then this is
* assumed to be 1.0
*
- * Note that all the property extensions described here apply either to the
- * plane or the CRTC (e.g. for the background color, which currently is not
- * exposed and assumed to be black).
+ * The property extensions described above all apply to the plane. Drivers
+ * may also expose the following crtc property extension:
+ *
+ * BACKGROUND_COLOR:
+ * Background color is setup with drm_crtc_add_bgcolor_property(). It
+ * controls the ARGB color of a full-screen layer that exists below all
+ * planes. This color will be used for pixels not covered by any plane
+ * and may also be blended with plane contents as allowed by a plane's
+ * alpha values. The background color defaults to black, and is assumed
+ * to be black for drivers that
[Intel-gfx] [PATCH v5 0/3] CRTC background color
Previous patch series/discussion was here: https://lists.freedesktop.org/archives/dri-devel/2019-January/205504.html Reviewed userspace (chromeos) is here: https://chromium-review.googlesource.com/c/chromium/src/+/1278858 https://chromium-review.googlesource.com/c/chromiumos/platform/drm-tests/+/1241436 i-g-t test is here: https://lists.freedesktop.org/archives/igt-dev/2019-January/008751.html Just minor changes in this revision: - Patch 1: * drm_crtc_add_bgcolor_property() also explicitly sets the crtc state field to solid black in case the driver doesn't already do this. * Added kerneldoc for drm_crtc_add_bgcolor_property() - Patch 2: * s/uint64_t/u64/ - Patch 3: * New i915 patch to add bgcolor to hardware readout & state verification as suggested by Ville I think patches #1 and 2 have the necessary reviews and ABI prereqs to merge at this point. Dave/Daniel, any worries if we merge this through the intel tree rather than drm-misc? I think merging through the Intel tree may help avoid some minor conflicts with an upcoming series from Ville. Matt Roper (3): drm: Add CRTC background color property (v5) drm/i915/gen9+: Add support for pipe background color (v5) drm/i915: Add background color hardware readout and state check drivers/gpu/drm/drm_atomic_uapi.c| 4 ++ drivers/gpu/drm/drm_blend.c | 41 +-- drivers/gpu/drm/drm_mode_config.c| 6 +++ drivers/gpu/drm/i915/i915_debugfs.c | 9 + drivers/gpu/drm/i915/intel_display.c | 78 +++- include/drm/drm_blend.h | 1 + include/drm/drm_crtc.h | 12 ++ include/drm/drm_mode_config.h| 5 +++ include/uapi/drm/drm_mode.h | 28 + 9 files changed, 170 insertions(+), 14 deletions(-) -- 2.14.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: do not return invalid pointers as a *dentry
== Series Details ==
Series: drm/i915: do not return invalid pointers as a *dentry
URL : https://patchwork.freedesktop.org/series/56044/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5518_full -> Patchwork_12110_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12110_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-render:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-glk: PASS -> FAIL [fdo#103232] +1
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-apl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
Possible fixes
* igt@gem_eio@reset-stress:
- shard-hsw: INCOMPLETE [fdo#103540] / [fdo#109482] -> PASS
* igt@kms_color@pipe-b-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-hsw: INCOMPLETE [fdo#103540] -> PASS
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +3
* igt@kms_flip@flip-vs-panning-interruptible:
- shard-hsw: DMESG-WARN [fdo#102614] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@sw_sync@sync_busy_fork:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS +1
Warnings
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> DMESG-WARN
[fdo#107956]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109482]: https://bugs.freedesktop.org/show_bug.cgi?id=109482
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5518 -> Patchwork_12110
CI_DRM_5518: 2369fd28d3a46b865f6d4f1d309a4c6b7b4e6d93 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12110: 36920a9b0dc28118dd85e0595b13fda607b39e7e @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12110/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug
On Wed, 2019-01-30 at 16:58 -0800, José Roberto de Souza wrote:
> Changing the i915_edp_psr_debug was enabling, disabling or switching
> PSR version by directly calling intel_psr_disable_locked() and
> intel_psr_enable_locked(), what is not the default PSR path that will
> be executed by real users.
>
> So lets force a fastset in the PSR CRTC to trigger a pipe update and
> stress the default code path.
>
> Recently a bug was found when switching from PSR2 to PSR1 while
> enable_psr kernel parameter was set to the default parameter, this
> changes fix it and also fixes the bug linked bellow were DRRS was
> left enabled together with PSR when enabling PSR from debugfs.
>
> v2: Handling missing case: disabled to PSR1
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341
> Cc: Maarten Lankhorst
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
>
> Should I add IGT tests to test every state switch combination?
Yes, please. At the minimum we need, PSR1->PSR2->PSR1 to make sure the
driver warnings aren't triggered.
>
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c| 2 +-
> drivers/gpu/drm/i915/intel_drv.h| 6 +-
> drivers/gpu/drm/i915/intel_psr.c| 187 +-
> --
> 5 files changed, 118 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index fa2c226fc779..766a5b4ad3d6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2607,7 +2607,6 @@ static int
> i915_edp_psr_debug_set(void *data, u64 val)
> {
> struct drm_i915_private *dev_priv = data;
> - struct drm_modeset_acquire_ctx ctx;
> intel_wakeref_t wakeref;
> int ret;
>
> @@ -2618,18 +2617,7 @@ i915_edp_psr_debug_set(void *data, u64 val)
>
> wakeref = intel_runtime_pm_get(dev_priv);
>
> - drm_modeset_acquire_init(&ctx,
> DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> -
> -retry:
> - ret = intel_psr_set_debugfs_mode(dev_priv, &ctx, val);
> - if (ret == -EDEADLK) {
> - ret = drm_modeset_backoff(&ctx);
> - if (!ret)
> - goto retry;
> - }
> -
> - drm_modeset_drop_locks(&ctx);
> - drm_modeset_acquire_fini(&ctx);
> + ret = intel_psr_set_debugfs_mode(dev_priv, val);
>
> intel_runtime_pm_put(dev_priv, wakeref);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 22da9df1f0a7..f75b4ce4df5f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -496,7 +496,7 @@ struct i915_psr {
>
> u32 debug;
> bool sink_support;
> - bool prepared, enabled;
> + bool enabled;
> struct intel_dp *dp;
> enum pipe pipe;
> bool active;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index ca705546a0ab..9211e4579489 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3556,7 +3556,7 @@ static void intel_ddi_update_pipe_dp(struct
> intel_encoder *encoder,
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>
> - intel_psr_enable(intel_dp, crtc_state);
> + intel_psr_update(intel_dp, crtc_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> intel_panel_update_backlight(encoder, crtc_state, conn_state);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 90ba5436370e..4c01decc30d3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2067,9 +2067,9 @@ void intel_psr_enable(struct intel_dp
> *intel_dp,
> const struct intel_crtc_state *crtc_state);
> void intel_psr_disable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *old_crtc_state);
> -int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
> -struct drm_modeset_acquire_ctx *ctx,
> -u64 value);
> +void intel_psr_update(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> +int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
> u64 value);
> void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits,
> enum fb_op_origin origin);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 84a0fb981561..90fe05a33b71 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -51,6 +51,8 @@
> * must be correctly synchronized/cancelled when shutting down the
> pipe."
> */
>
> +#include
> +#include
>
> #include "intel_drv.h"
> #include "i915_drv.h"
> @@ -718,8 +720,11 @@ static void intel_psr
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev4)
Quoting Patchwork (2019-01-31 22:33:09) > Possible regressions > > * igt@gem_eio@unwedge-stress: > - shard-snb: PASS -> FAIL Old, random 2s delay. > Possible fixes > > * igt@gem_eio@reset-stress: > - shard-hsw: INCOMPLETE [fdo#103540] / [fdo#109482] -> PASS > > * igt@gem_mmap_gtt@hang: > - shard-kbl: FAIL [fdo#109469] -> PASS > - shard-hsw: FAIL [fdo#109469] -> PASS > - shard-snb: FAIL [fdo#109469] -> PASS > - shard-glk: FAIL [fdo#109469] -> PASS > - shard-apl: FAIL [fdo#109469] -> PASS I declare thee done! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev4)
== Series Details ==
Series: series starting with drm/i915: Revoke mmaps and prevent access to fence
registers across reset (rev4)
URL : https://patchwork.freedesktop.org/series/56042/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5518_full -> Patchwork_12109_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12109_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12109_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12109_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@unwedge-stress:
- shard-snb: PASS -> FAIL
Known issues
Here are the changes found in Patchwork_12109_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-render:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145] +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-apl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@gem_eio@reset-stress:
- shard-hsw: INCOMPLETE [fdo#103540] / [fdo#109482] -> PASS
* igt@gem_mmap_gtt@hang:
- shard-kbl: FAIL [fdo#109469] -> PASS
- shard-hsw: FAIL [fdo#109469] -> PASS
- shard-snb: FAIL [fdo#109469] -> PASS
- shard-glk: FAIL [fdo#109469] -> PASS
- shard-apl: FAIL [fdo#109469] -> PASS
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-hsw: INCOMPLETE [fdo#103540] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: {SKIP} [fdo#109271] -> PASS
* igt@sw_sync@sync_busy_fork:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS +1
Warnings
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-snb: DMESG-WARN [fdo#107956] -> INCOMPLETE [fdo#105411]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> INCOMPLETE
[fdo#105411]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-hsw: DMESG-WARN [fdo#107956] -> INCOMPLETE [fdo#103540] +2
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109469]: https://bugs.freedesktop.org/show_bug.cgi?id=109469
[fdo#109482]: https://bugs.freedesktop.org/show_bug.cgi?id=109482
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5518 -> Patchwork_12109
CI_DRM_5518: 2369fd28d3a46b865f6d4f1d309a4c6b7b4e6d93 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12109: b14cb740ba0da05e4c0bc3d7c4384487aa938dd8 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab841
[Intel-gfx] ✓ Fi.CI.IGT: success for Per context dynamic (sub)slice power-gating (rev29)
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev29)
URL : https://patchwork.freedesktop.org/series/48194/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5518_full -> Patchwork_12106_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12106_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-render:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-hsw: PASS -> FAIL [fdo#106641]
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_color@pipe-c-legacy-gamma:
- shard-kbl: PASS -> FAIL [fdo#104782]
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: NOTRUN -> FAIL [fdo#103232]
- shard-kbl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +5
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb-blt-ytiled:
- shard-glk: PASS -> FAIL [fdo#107589]
* igt@kms_flip@2x-flip-vs-modeset-interruptible:
- shard-hsw: PASS -> DMESG-WARN [fdo#102614]
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: PASS -> FAIL [fdo#108948]
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-kbl: PASS -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109381]
- shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538]
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-glk: PASS -> FAIL [fdo#103166] +4
* igt@prime_busy@hang-bsd:
- shard-apl: PASS -> FAIL [fdo#108807]
Possible fixes
* igt@gem_eio@reset-stress:
- shard-hsw: INCOMPLETE [fdo#103540] / [fdo#109482] -> PASS
* igt@gem_mmap_gtt@hang:
- shard-kbl: FAIL [fdo#109469] -> PASS
- shard-hsw: FAIL [fdo#109469] -> PASS
- shard-glk: FAIL [fdo#109469] -> PASS
* igt@gem_workarounds@suspend-resume:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_busy@basic-modeset-a:
- shard-apl: FAIL [fdo#109490] -> PASS +3
- shard-glk: FAIL [fdo#109490] -> PASS +3
- shard-snb: FAIL [fdo#109490] -> PASS +2
* igt@kms_busy@basic-modeset-b:
- shard-kbl: FAIL [fdo#109490] -> PASS +3
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-snb: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-hsw: INCOMPLETE [fdo#103540] -> PASS
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS
- shard-kbl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-snb: DMESG-WARN [fdo#107469] -> PASS
* igt@kms_flip@flip-vs-panning-interruptible:
- shard-hsw: DMESG-WARN [fdo#102614] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-snb: {SKIP} [fdo#109271] -> PASS +67
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
- shard-glk: {SKIP} [fdo#109271] -> PASS +140
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
- shard-hsw: {SKIP} [fdo#109271] -> PASS +141
* igt@kms_frontbuffer_tracking@fbc-farfromfence:
- shard-kbl: {SKIP} [fdo#109271] -> PASS +68
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render:
- shard-apl: {SKIP} [fdo#109271] -> PASS +66
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +4
- shard-kbl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
- shard-hsw: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@crtc-id:
- shard-hsw: FAIL [fdo#109490] -> PASS +3
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
== Series Details ==
Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
URL : https://patchwork.freedesktop.org/series/56059/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5520 -> Patchwork_12111
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56059/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12111 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (51 -> 45)
--
Additional (1): fi-glk-j4005
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5520 -> Patchwork_12111
CI_DRM_5520: 91343140b5792a21430708ad761feaf17b8ae1a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12111: 49b8aff26fa20cf63e93cb18f5a8d473e6a31cc6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel
Encoding/Colorimetry Format
bfebbc7e2acb drm: Add a VSC structure for handling Pixel Encoding/Colorimetry
Formats
485e788bfeee drm/i915/dp: Add a config function for YCBCR420 outputs
646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12111/
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
== Series Details == Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs URL : https://patchwork.freedesktop.org/series/56059/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 Okay! Commit: drm/i915/dp: Add a config function for YCBCR420 outputs Okay! Commit: drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats Okay! Commit: drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format Okay! Commit: drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA Okay! Commit: drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs -O:drivers/gpu/drm/i915/intel_dp.c:1769:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dp.c:1769:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1770:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1770:23: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
== Series Details == Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs URL : https://patchwork.freedesktop.org/series/56059/ State : warning == Summary == $ dim checkpatch origin/drm-tip 646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 -:20: WARNING:TABSTOP: Statements should start on a tabstop #20: FILE: drivers/gpu/drm/i915/intel_dp.c:6926: +if (INTEL_GEN(dev_priv) >= 11) total: 0 errors, 1 warnings, 0 checks, 9 lines checked 485e788bfeee drm/i915/dp: Add a config function for YCBCR420 outputs bfebbc7e2acb drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats 2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format -:44: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line #44: FILE: drivers/gpu/drm/i915/intel_dp.c:4412: + if (!intel_dp->attached_connector->base.ycbcr_420_allowed) return; total: 1 errors, 0 warnings, 0 checks, 93 lines checked 317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA -:41: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line #41: FILE: drivers/gpu/drm/i915/intel_ddi.c:1740: +* indicate VSC SDP for the Pixel Encoding/Colorimetry Format. + */ total: 0 errors, 1 warnings, 0 checks, 21 lines checked 49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs -:54: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770: + bpp = min(bpp, 3*bpc/bpp_divider); ^ -:54: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770: + bpp = min(bpp, 3*bpc/bpp_divider); ^ total: 0 errors, 0 warnings, 2 checks, 119 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 5/6] drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
When YCBCR 4:2:0 outputs is used for DP, we should program YCBCR 4:2:0 to
MSA and VSC SDP.
As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of Color
Encoding Format and Content Color Gamut] while sending YCBCR 420 signals
we should program MSA MISC1 fields which indicate VSC SDP for the Pixel
Encoding/Colorimetry Format.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 8
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a64deeb4e517..1045ca41b188 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9425,6 +9425,7 @@ enum skl_power_gate {
#define TRANS_MSA_12_BPC (3 << 5)
#define TRANS_MSA_16_BPC (4 << 5)
#define TRANS_MSA_CEA_RANGE (1 << 3)
+#define TRANS_MSA_USE_VSC_SDP (1 << 13)
/* LCPLL Control */
#define LCPLL_CTL _MMIO(0x130040)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8969f03393b8..c6aed2b06a59 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1732,6 +1732,14 @@ void intel_ddi_set_pipe_settings(const struct
intel_crtc_state *crtc_state)
*/
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
+ /*
+* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
+* of Color Encoding Format and Content Color Gamut] while sending
+* YCBCR 420 signals we should program MSA MISC1 fields which
+* indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+ */
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ temp |= TRANS_MSA_USE_VSC_SDP;
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
--
2.20.1
___
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[Intel-gfx] [RFC 2/6] drm/i915/dp: Add a config function for YCBCR420 outputs
This patch checks a support of YCBCR420 outputs on an encoder level.
If the input mode is YCBCR420-only mode then it prepares DP as an YCBCR420
output, else it continues with RGB output mode.
It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to using
a pipe scaler as RGB to YCbCr 4:4:4.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/intel_dp.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ad7382d3be86..a61aff23c8b2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2098,6 +2098,31 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
return 0;
}
+static bool
+intel_dp_ycbcr420_config(struct drm_connector *connector,
+struct intel_crtc_state *config)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
+
+ if (!connector->ycbcr_420_allowed) {
+ DRM_ERROR("Platform doesn't support YCBCR420 output\n");
+ return false;
+ }
+
+ config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+
+ /* YCBCR 420 output conversion needs a scaler */
+ if (skl_update_scaler_crtc(config)) {
+ DRM_DEBUG_KMS("Scaler allocation for output failed\n");
+ return false;
+ }
+
+ intel_pch_panel_fitting(intel_crtc, config,
+ DRM_MODE_SCALE_FULLSCREEN);
+
+ return true;
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2115,6 +2140,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
int ret;
+ struct drm_connector *connector = conn_state->connector;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -2123,6 +2149,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (lspcon->active)
lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
+ if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
+ if (!intel_dp_ycbcr420_config(connector, pipe_config)) {
+ DRM_ERROR("Can't support YCBCR420 output\n");
+ return false;
+ }
+ }
+
pipe_config->has_drrs = false;
if (IS_G4X(dev_priv) || port == PORT_A)
pipe_config->has_audio = false;
--
2.20.1
___
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[Intel-gfx] [RFC 4/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
Function intel_pixel_encoding_setup_vsc handles vsc header and data block
setup for pixel encoding / colorimetry format.
Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
for pixel encoding / colorimetry format as per dp 1.4a spec,
section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
table 2-120:VSC SDP Payload for DB16 through DB18.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 72
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ca705546a0ab..8969f03393b8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3400,6 +3400,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
+ intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a61aff23c8b2..3a9a5a3c33a9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4402,6 +4402,78 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp,
return 0;
}
+static void
+intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct dp_vsc_sdp vsc_sdp;
+
+ if (!intel_dp->attached_connector->base.ycbcr_420_allowed) return;
+
+ /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
+ memset(&vsc_sdp, 0, sizeof(vsc_sdp));
+ vsc_sdp.sdp_header.HB0 = 0;
+ vsc_sdp.sdp_header.HB1 = 0x7;
+
+ /* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication. A DP Source device is allowed
+* to indicate the pixel encoding/colorimetry format to the DP Sink
+* device with VSC SDP only when the DP Sink device supports it
+* (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
register
+* DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3) is set to
1)
+*/
+ vsc_sdp.sdp_header.HB2 = 0x5;
+
+ /* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
+* Colorimetry Format indication (HB2 = 05h).
+*/
+ vsc_sdp.sdp_header.HB3 = 0x13;
+ /* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
+* DB16[3:0] DP 1.4a spec, Table 2-120
+*/
+
+ /* https://patchwork.freedesktop.org/patch/166830/ i915 implementations
+* uses BT.709 color space
+*/
+ vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
+ vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
+
+ /* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
+* the following Component Bit Depth values are defined:
+* 001b = 8bpc.
+* 010b = 10bpc.
+* 011b = 12bpc.
+* 100b = 16bpc.
+*/
+ vsc_sdp.DB17 = 0x1;
+
+ /*
+* Content Type (Bits 2:0)
+* 000b = Not defined.
+* 001b = Graphics.
+* 010b = Photo.
+* 011b = Video.
+* 100b = Game
+* All other values are RESERVED.
+* Note: See CTA-861-G for the definition and expected
+* processing by a stream sink for the above contect types.
+*/
+ vsc_sdp.DB18 = 0;
+
+ intel_dig_port->write_infoframe(&intel_dig_port->base,
+ crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
+}
+
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+ return;
+
+ intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
+}
+
static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
int status = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 90ba5436370e..bc01a69e8a2a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1868,6 +1868,8 @@ u16 intel_dp_dsc_get_output_bpp(int link_clock, u8
lane_count,
int mode_clock, int mode_hdisplay);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
--
2.20.1
__
[Intel-gfx] [RFC 0/6] drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
On Gen 11 platform, to enable resolutions like 5K@120 (or higher) we need to use DSC (DP 1.4) or YCbCr4:2:0 (DP 1.3 or 1.4) on DP. In order to support YCbCr4:2:0 on DP we need to program YCBCR 4:2:0 to MSA and VSC SDP. This patches are RFC patches that add a VSC structure for handling Pixel Encoding/Colorimetry Formats and program YCBCR 4:2:0 to MSA and VSC SDP. This is currently not tested, but I wanted to get some inputs on this approach. The idea of a scaling (RGB -> YCbCr4:4:4 -> YCbCr 4:2:0) is to follow the same approach used in YCbCr 4:2:0 on HDMI. Gwan-gyeong Mun (6): drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 drm/i915/dp: Add a config function for YCBCR420 outputs drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 16 +++- drivers/gpu/drm/i915/intel_dp.c | 147 +-- drivers/gpu/drm/i915/intel_drv.h | 2 + include/drm/drm_dp_helper.h | 17 5 files changed, 176 insertions(+), 7 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 1/6] drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
Bspec describes that GEN10 only supports capability of YUV 4:2:0 output to HDMI port and GEN11 supports capability of YUV 4:2:0 output to both DP and HDMI ports. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 681e88405ada..ad7382d3be86 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -6923,6 +6923,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, connector->interlace_allowed = true; connector->doublescan_allowed = 0; +if (INTEL_GEN(dev_priv) >= 11) + connector->ycbcr_420_allowed = true; + intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); intel_dp_aux_init(intel_dp); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 6/6] drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
pipe_bpp value was assumed RGB therefore it was multiplied with 3.
But YCbCr 4:2:0 requires multiplier value to 1.5 therefore it divides
pipe_bpp to 2.
- RGB bpp = bpc x 3
- YCbCr 4:2:0 bpp = bpc x 1.5
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/intel_ddi.c | 7 +-
drivers/gpu/drm/i915/intel_dp.c | 41 ++--
2 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c6aed2b06a59..7f56aa7842c1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1696,6 +1696,7 @@ void intel_ddi_set_pipe_settings(const struct
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 temp;
+ int bpp;
if (!intel_crtc_has_dp_encoder(crtc_state))
return;
@@ -1707,7 +1708,11 @@ void intel_ddi_set_pipe_settings(const struct
intel_crtc_state *crtc_state)
if (crtc_state->limited_color_range)
temp |= TRANS_MSA_CEA_RANGE;
- switch (crtc_state->pipe_bpp) {
+ bpp = crtc_state->pipe_bpp;
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bpp *= 2;
+
+ switch (bpp) {
case 18:
temp |= TRANS_MSA_6_BPC;
break;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3a9a5a3c33a9..734c5743e03f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1761,12 +1761,13 @@ static int intel_dp_compute_bpp(struct intel_dp
*intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_connector *intel_connector = intel_dp->attached_connector;
int bpp, bpc;
+ int bpp_divider = pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
bpp = pipe_config->pipe_bpp;
bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd,
intel_dp->downstream_ports);
if (bpc > 0)
- bpp = min(bpp, 3*bpc);
+ bpp = min(bpp, 3*bpc/bpp_divider);
if (intel_dp_is_edp(intel_dp)) {
/* Get bpp from vbt only for panels that dont have bpp in edid
*/
@@ -1787,12 +1788,14 @@ intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits)
{
+ int bpp_divider = pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+
/* For DP Compliance we override the computed bpp for the pipe */
if (intel_dp->compliance.test_data.bpc != 0) {
- int bpp = 3 * intel_dp->compliance.test_data.bpc;
+ int bpp = 3 * intel_dp->compliance.test_data.bpc / bpp_divider;
limits->min_bpp = limits->max_bpp = bpp;
- pipe_config->dither_force_disable = bpp == 6 * 3;
+ pipe_config->dither_force_disable = bpp == 6 * 3 / bpp_divider;
DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
}
@@ -1826,8 +1829,9 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
struct drm_display_mode *adjusted_mode =
&pipe_config->base.adjusted_mode;
int bpp, clock, lane_count;
int mode_rate, link_clock, link_avail;
+ int bpp_divider = pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+ for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 /
bpp_divider) {
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
bpp);
@@ -1862,8 +1866,9 @@ intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp,
struct drm_display_mode *adjusted_mode =
&pipe_config->base.adjusted_mode;
int bpp, clock, lane_count;
int mode_rate, link_clock, link_avail;
+ int bpp_divider = pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+ for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 /
bpp_divider) {
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
bpp);
@@ -2009,6 +2014,7 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
struct link_config_limits limits;
int common_len;
int ret;
+ int bpp_divider = pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
common_len = intel_dp_common_len_rate_limit(intel_dp,
intel_dp->max_link_rate);
@@ -2022,7 +2028,7 @@ intel_dp_compute_link_config(struct intel_encoder
[Intel-gfx] [RFC 3/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
SDP VSC Header and Data Block follow DP 1.4a spec, section 2.2.5.7.5,
chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".
Signed-off-by: Gwan-gyeong Mun
---
include/drm/drm_dp_helper.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5db7fb8c8b50..6091d29757af 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1076,6 +1076,23 @@ struct edp_vsc_psr {
u8 DB8_31[24]; /* Reserved */
} __packed;
+struct dp_vsc_sdp {
+ struct dp_sdp_header sdp_header;
+ u8 DB0; /* Stereo Interface */
+ u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
+ u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
+ u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
+ u8 DB4; /* CRC value bits 7:0 of the G or Y component */
+ u8 DB5; /* CRC value bits 15:8 of the G or Y component */
+ u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
+ u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
+ u8 DB8_15[8]; /* Reserved */
+ u8 DB16; /* Pixel Encoding and Colorimetry Formats */
+ u8 DB17; /* Dynamic Range and Component Bit Depth */
+ u8 DB18; /* Content Type */
+ u8 DB19_31[13]; /* Reserved */
+} __packed;
+
#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915: Enable transition watermarks for glk
== Series Details ==
Series: series starting with [1/4] drm/i915: Enable transition watermarks for
glk
URL : https://patchwork.freedesktop.org/series/56025/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5518_full -> Patchwork_12103_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12103_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12103_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12103_full:
### IGT changes ###
Possible regressions
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-glk: PASS -> FAIL +2
Known issues
Here are the changes found in Patchwork_12103_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-render:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-glk: PASS -> DMESG-WARN [fdo#105763] / [fdo#106538]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-apl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166]
- shard-glk: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@gem_eio@reset-stress:
- shard-hsw: INCOMPLETE [fdo#103540] / [fdo#109482] -> PASS
* igt@gem_workarounds@suspend-resume:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-b-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-hsw: INCOMPLETE [fdo#103540] -> PASS
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-snb: DMESG-WARN [fdo#107469] -> PASS
* igt@kms_flip@flip-vs-panning-interruptible:
- shard-hsw: DMESG-WARN [fdo#102614] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: {SKIP} [fdo#109271] -> PASS
* igt@sw_sync@sync_busy_fork:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS +1
Warnings
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> DMESG-WARN
[fdo#107956]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#107469]: https://bugs.freedesktop.org/show_bug.cgi?id=107469
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109482]: https://bugs.freedesktop.org/show_bug.cgi?id=109482
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5518 -> Patchwork_12103
CI_DRM_5518: 2369fd28d3a46b865f6d4f1d309a4c6b7b4e6d93 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12103: 70785cf59b0d35fc4508bdb6b2e98c71435fedaf @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Implement HDCP2.2 (rev13)
== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev13)
URL : https://patchwork.freedesktop.org/series/38254/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5517_full -> Patchwork_12101_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12101_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145]
Possible fixes
* igt@gem_eio@reset-stress:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-glk: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_color@pipe-b-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS +1
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-glk: FAIL [fdo#108948] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: {SKIP} [fdo#109271] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5517 -> Patchwork_12101
CI_DRM_5517: b2e346ffed409cd4a9b5f010d996b72ec9e7080f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12101: cd6cc61ebb7f4dea4ef6e8221bf168a7f51bf113 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12101/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: do not return invalid pointers as a *dentry
On Thu, Jan 31, 2019 at 09:59:26AM -0800, Rodrigo Vivi wrote: > On Thu, Jan 31, 2019 at 02:15:07PM +0100, Greg Kroah-Hartman wrote: > > When calling debugfs functions, they can now return error values if > > something went wrong. If that happens, return a NULL as a *dentry to > > the relay core instead of passing it an illegal pointer. > > > > The relay core should be able to handle an illegal pointer, but add this > > check to be safe. > > > > Cc: Jani Nikula > > Cc: Joonas Lahtinen > > Cc: Rodrigo Vivi > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: intel-gfx@lists.freedesktop.org > > Cc: dri-de...@lists.freedesktop.org > > Signed-off-by: Greg Kroah-Hartman > > --- > > drivers/gpu/drm/i915/intel_guc_log.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_guc_log.c > > b/drivers/gpu/drm/i915/intel_guc_log.c > > index d3ebdbc0182e..8bf03497dcd8 100644 > > --- a/drivers/gpu/drm/i915/intel_guc_log.c > > +++ b/drivers/gpu/drm/i915/intel_guc_log.c > > @@ -140,6 +140,9 @@ static struct dentry *create_buf_file_callback(const > > char *filename, > > > > buf_file = debugfs_create_file(filename, mode, > >parent, buf, &relay_file_operations); > > + if (IS_ERR(buf_file)) > > + return NULL; > > I still see a return NULL inside debugfs_create_file on master, > but probably you are ahead with some change that I didn't see yet right? Yes, this patch is in linux-next now and should go to Linus for 5.0-final: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/commit/?h=driver-core-linus&id=ff9fb72bc07705c00795ca48631f7fffe24d2c6b > I'm just wondering if it wouldn't be better for now to go with > > if (IS_ERR_OR_NULL(buf_file)) Not really, because the next line is: > > return buf_file; So it's the same thing :) > apparently we also need it on i915_debugfs.c i915_debugfs_register() I have a bunch of patches I'm working on to go through and fix up all of this (you shouldn't be checking the return value at all, unless you really want to use it as a "real" dentry and not just something that debugfs uses internally. But for now, you should be fine, that call will only fail if you are out of memory, or did something really wrong. thanks, greg k-h ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Drop WaIncreaseLatencyIPCEnabled/1140 for cnl
On Thu, Jan 31, 2019 at 09:42:16AM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Drop WaIncreaseLatencyIPCEnabled/Display w/a #1140 for > early cnl steppings. Also switch the kbl/cfl case to check > for IS_GEN9_BC() for brevity. It ends up being the same thing > because IPC is disabled on SKL due to w/a #0477. I think this deserves a commend in the code, otherwise someone in the future might not notice that and send a patch to replace 9_BC per KBL || CFL... anyway: Reviewed-by: Rodrigo Vivi > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_pm.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 306e41ccc50e..55491e2d5134 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4701,9 +4701,7 @@ static void skl_compute_plane_wm(const struct > intel_crtc_state *cstate, >* WaIncreaseLatencyIPCEnabled: kbl,cfl >* Display WA #1141: kbl,cfl >*/ > - if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || > - IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) && > - dev_priv->ipc_enabled) > + if (IS_GEN9_BC(dev_priv) && dev_priv->ipc_enabled) > latency += 4; > > if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled) > -- > 2.19.2 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Document that we implement WaIncreaseLatencyIPCEnabled
On Thu, Jan 31, 2019 at 09:42:15AM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Display w/a #1141 is also known as WaIncreaseLatencyIPCEnabled. > Add that to the comment. > > Signed-off-by: Ville Syrjälä Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_pm.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d91aec396a4c..306e41ccc50e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4697,7 +4697,10 @@ static void skl_compute_plane_wm(const struct > intel_crtc_state *cstate, > if (latency == 0) > return; > > - /* Display WA #1141: kbl,cfl */ > + /* > + * WaIncreaseLatencyIPCEnabled: kbl,cfl > + * Display WA #1141: kbl,cfl > + */ > if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || > IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) && > dev_priv->ipc_enabled) > -- > 2.19.2 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Implement display w/a 1140 for glk/cnl
On Thu, Jan 31, 2019 at 09:42:14AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Display w/a #1140 tells us we have to program the transition
> watermark to the minimum value on glk/cnl. Let's do that.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5ce60faef28c..d91aec396a4c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4844,8 +4844,7 @@ static void skl_compute_transition_wm(const struct
> intel_crtc_state *cstate,
> {
> struct drm_device *dev = cstate->base.crtc->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> - u16 trans_min, trans_y_tile_min;
> - const u16 trans_amount = 10; /* This is configurable amount */
> + u16 trans_min, trans_y_tile_min, trans_amount;
> u16 wm0_sel_res_b, trans_offset_b, res_blocks;
>
> /*
> @@ -4859,9 +4858,16 @@ static void skl_compute_transition_wm(const struct
> intel_crtc_state *cstate,
> if (!dev_priv->ipc_enabled)
> return;
>
> - trans_min = 14;
> if (INTEL_GEN(dev_priv) >= 11)
> trans_min = 4;
> + else
> + trans_min = 14;
> +
> + /* Display WA #1140: glk,cnl */
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + trans_amount = 0;
> + else
> + trans_amount = 10; /* This is configurable amount */
>
> trans_offset_b = trans_min + trans_amount;
>
> --
> 2.19.2
>
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Enable transition watermarks for glk
On Thu, Jan 31, 2019 at 09:42:13AM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > We are mistakenly skipping transition watermarks on glk. Fix > up the condition for glk, and toss in the w/a name from > the database. > > Signed-off-by: Ville Syrjälä Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ed9786241307..5ce60faef28c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4848,8 +4848,11 @@ static void skl_compute_transition_wm(const struct > intel_crtc_state *cstate, > const u16 trans_amount = 10; /* This is configurable amount */ > u16 wm0_sel_res_b, trans_offset_b, res_blocks; > > - /* Transition WM are not recommended by HW team for GEN9 */ > - if (INTEL_GEN(dev_priv) <= 9) > + /* > + * WaDisableTWM:skl,kbl,cfl,bxt > + * Transition WM are not recommended by HW team for GEN9 > + */ > + if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) > return; > > /* Transition WM don't make any sense if ipc is disabled */ > -- > 2.19.2 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-next
On Thu, Jan 24, 2019 at 01:40:48PM +0800, Zhenyu Wang wrote: > > Hi, > > Here is gvt-next stuff. This includes Coffeelake support for GVT, > making kvmgt as self load module to have better dependence with > vfio/mdev, with some const treatment and kernel type change. ops, I also failed to let you know I had pulled this. I also already sent in previous pull request to Dave and Daniel. Sorry, Rodrigo. > > Thanks. > -- > The following changes since commit d1810909d841314ba94b14dc3de9e9fbc13b046a: > > drm/i915/gvt: fix spelling mistake "Interupts" -> "Interrupts" (2018-12-07 > 12:01:09 +0800) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux.git tags/gvt-next-2019-01-24 > > for you to fetch changes up to 2e679d48f38c378650db403b4ba2248adf0691b2: > > drm/i915/gvt: switch to kernel types (2019-01-23 13:56:14 +0800) > > > gvt-next-2019-01-24 > > - split kvmgt as seperate module (Zhenyu) > - Coffeelake GVT support (Fred) > - const treatment and change for kernel type (Jani) > > > Jani Nikula (4): > drm/i915/gvt: remove drmP.h include > drm/i915/gvt: give the cmd parser decode_info a const treatment > drm/i915/gvt: give the cmd parser cmd_info a const treatment > drm/i915/gvt: switch to kernel types > > Zhenyu Wang (3): > drm/i915/gvt: mandatory require hypervisor's host_init > drm/i915/gvt: remove unused parameter for hypervisor's host_exit call > drm/i915/gvt: Change KVMGT as self load module > > fred gao (6): > drm/i915/gvt: Add coffeelake platform definition > drm/i915/gvt: Add mmio handler for CFL > drm/i915/gvt: Enable gfx virtualiztion for CFL > drm/i915/gvt: Reuse the gmbus pin macro > drm/i915/gvt: Refine port select logic for CFL platform > drm/i915: Enable gfx virtualization for Coffeelake platform > > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gvt/Makefile | 1 - > drivers/gpu/drm/i915/gvt/cmd_parser.c | 83 > drivers/gpu/drm/i915/gvt/display.c | 12 ++-- > drivers/gpu/drm/i915/gvt/dmabuf.c | 5 +- > drivers/gpu/drm/i915/gvt/edid.c | 32 +++--- > drivers/gpu/drm/i915/gvt/fb_decoder.c | 12 +--- > drivers/gpu/drm/i915/gvt/gvt.c | 108 > +--- > drivers/gpu/drm/i915/gvt/gvt.h | 6 +- > drivers/gpu/drm/i915/gvt/handlers.c | 29 - > drivers/gpu/drm/i915/gvt/hypercall.h| 9 ++- > drivers/gpu/drm/i915/gvt/interrupt.c| 4 +- > drivers/gpu/drm/i915/gvt/kvmgt.c| 42 - > drivers/gpu/drm/i915/gvt/mmio.c | 6 +- > drivers/gpu/drm/i915/gvt/mmio.h | 11 ++-- > drivers/gpu/drm/i915/gvt/mmio_context.c | 18 +++--- > drivers/gpu/drm/i915/gvt/mpt.h | 13 ++-- > drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +- > drivers/gpu/drm/i915/gvt/scheduler.c| 7 +-- > drivers/gpu/drm/i915/gvt/scheduler.h| 2 +- > drivers/gpu/drm/i915/gvt/trace.h| 2 +- > drivers/gpu/drm/i915/intel_gvt.c| 12 +--- > 22 files changed, 204 insertions(+), 213 deletions(-) > > > -- > Open Source Technology Center, Intel ltd. > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: do not return invalid pointers as a *dentry
On Thu, Jan 31, 2019 at 02:15:07PM +0100, Greg Kroah-Hartman wrote: > When calling debugfs functions, they can now return error values if > something went wrong. If that happens, return a NULL as a *dentry to > the relay core instead of passing it an illegal pointer. > > The relay core should be able to handle an illegal pointer, but add this > check to be safe. > > Cc: Jani Nikula > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: David Airlie > Cc: Daniel Vetter > Cc: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Greg Kroah-Hartman > --- > drivers/gpu/drm/i915/intel_guc_log.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_guc_log.c > b/drivers/gpu/drm/i915/intel_guc_log.c > index d3ebdbc0182e..8bf03497dcd8 100644 > --- a/drivers/gpu/drm/i915/intel_guc_log.c > +++ b/drivers/gpu/drm/i915/intel_guc_log.c > @@ -140,6 +140,9 @@ static struct dentry *create_buf_file_callback(const char > *filename, > > buf_file = debugfs_create_file(filename, mode, > parent, buf, &relay_file_operations); > + if (IS_ERR(buf_file)) > + return NULL; I still see a return NULL inside debugfs_create_file on master, but probably you are ahead with some change that I didn't see yet right? I'm just wondering if it wouldn't be better for now to go with if (IS_ERR_OR_NULL(buf_file)) apparently we also need it on i915_debugfs.c i915_debugfs_register() Thanks, Rodrigo. > + > return buf_file; > } > > -- > 2.20.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/11] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Quoting Tvrtko Ursulin (2019-01-31 13:19:31)
>
> On 30/01/2019 02:19, Chris Wilson wrote:
> > Having introduced per-context seqno, we now have a means to identity
> > progress across the system without feel of rollback as befell the
> > global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
> > advance of submission safe in the knowledge that our target seqno and
> > address is stable.
> >
> > However, since we are telling the GPU to busy-spin on the target address
> > until it matches the signaling seqno, we only want to do so when we are
> > sure that busy-spin will be completed quickly. To achieve this we only
> > submit the request to HW once the signaler is itself executing (modulo
> > preemption causing us to wait longer), and we only do so for default and
> > above priority requests (so that idle priority tasks never themselves
> > hog the GPU waiting for others).
>
> It could be milliseconds though. I think apart from media-bench saying
> this is faster, we would need to look at performance per Watt as well.
>
> RING_SEMA_WAIT_POLL is a potential tunable as well. Not that I have an
> idea how to tune it.
>
> Eventually, do we dare adding this without a runtime switch? (There, I
> mentioned the taboo.)
Yes, we could make it a context setparam. I used priority here as
arguing that idle workloads don't want the extra power draw makes sense.
Downside of making it opt-in, nobody benefits. Still it's pretty limited
to media workloads at the moment (who else uses multiple rings atm), but
even there reducing latency for desktop video is justifiable imo.
(Now having said that, I should go out and find a video player to
benchmark... Maybe we can demonstrate reduced frame drop for Kodi. If I
say "Kodi, Kodi, Kodi" I summon a Kodi dev right?)
Downside of making it opt-out: everybody gets to experience our bugs,
and the onus is on us in making the right choice.
> > @@ -605,6 +606,17 @@ static bool can_merge_rq(const struct i915_request
> > *prev,
> > {
> > GEM_BUG_ON(!assert_priority_queue(prev, next));
> >
> > + /*
> > + * To avoid AB-BA deadlocks, we simply restrict ourselves to only
> > + * submitting one semaphore (think HW spinlock) to HW at a time. This
> > + * prevents the execution callback on a later sempahore from being
> > + * queued on another engine, so no cycle can be formed. Preemption
> > + * rules should mean that if this semaphore is preempted, its
> > + * dependency chain is preserved and suitably promoted via PI.
> > + */
> > + if (prev->sched.semaphore && !i915_request_started(prev))
> > + return false;
The other way I was thinking we could solve this is to move the
execute_cb from i915_request_submit until we actually insert the request
in ELSP[0] (or do the promotion from ELSP[1]).
I don't like either much. I don't really want to walk the list of
requests for port0 checking for execute_cb, but I don't also like
arbitrary splitting contexts (however, there seems to be reasons to do
that anyway).
It all depends on how fast we can service CS interrupts, and that needs
to always be fast. :|
-Chris
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Re: [Intel-gfx] [PATCH 10/11] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Quoting Chris Wilson (2019-01-31 13:39:50) > Quoting Tvrtko Ursulin (2019-01-31 13:19:31) > > > > On 30/01/2019 02:19, Chris Wilson wrote: > > > Having introduced per-context seqno, we now have a means to identity > > > progress across the system without feel of rollback as befell the > > > global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in > > > advance of submission safe in the knowledge that our target seqno and > > > address is stable. > > > > > > However, since we are telling the GPU to busy-spin on the target address > > > until it matches the signaling seqno, we only want to do so when we are > > > sure that busy-spin will be completed quickly. To achieve this we only > > > submit the request to HW once the signaler is itself executing (modulo > > > preemption causing us to wait longer), and we only do so for default and > > > above priority requests (so that idle priority tasks never themselves > > > hog the GPU waiting for others). > > > > It could be milliseconds though. I think apart from media-bench saying > > this is faster, we would need to look at performance per Watt as well. > > All throughput measurements are substantially faster, as you would > expect, and inter-engine latency decreased. I would hope it would > powergate/rc6 the EU while the CS was spinning, but I don't know :) Fwiw, it's about the power cost of simply spinning with the CS without any additional cost of utilizing the engine. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/3] lib/i915: Pretty print HW semaphores
Include whether the scheduler is using HW semaphore assistance in our
pretty debug strings, and make the caps known for requires.
Signed-off-by: Chris Wilson
---
lib/i915/gem_scheduler.c | 22 +++---
lib/i915/gem_scheduler.h | 2 ++
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/lib/i915/gem_scheduler.c b/lib/i915/gem_scheduler.c
index ad156306f..f9e052278 100644
--- a/lib/i915/gem_scheduler.c
+++ b/lib/i915/gem_scheduler.c
@@ -67,7 +67,7 @@ unsigned gem_scheduler_capability(int fd)
}
/**
- * gem_has_scheduler:
+ * gem_scheduler_enabled:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver has scheduling capability.
@@ -79,7 +79,7 @@ bool gem_scheduler_enabled(int fd)
}
/**
- * gem_has_ctx_priority:
+ * gem_scheduler_has_ctx_priority:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver supports assigning custom
@@ -92,7 +92,7 @@ bool gem_scheduler_has_ctx_priority(int fd)
}
/**
- * gem_has_preemption:
+ * gem_scheduler_has_preemption:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver supports preempting active
@@ -104,6 +104,20 @@ bool gem_scheduler_has_preemption(int fd)
LOCAL_I915_SCHEDULER_CAP_PREEMPTION;
}
+/**
+ * gem_scheduler_has_semaphores:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether the driver supports using HW semaphores
+ * to schedule dependencies in parallel (using the HW to delay execution until
+ * ready to reduce latency).
+ */
+bool gem_scheduler_has_semaphores(int fd)
+{
+ return gem_scheduler_capability(fd) &
+ LOCAL_I915_SCHEDULER_CAP_SEMAPHORES;
+}
+
/**
* gem_scheduler_print_capability:
* @fd: open i915 drm file descriptor
@@ -122,4 +136,6 @@ void gem_scheduler_print_capability(int fd)
igt_info(" - With priority sorting\n");
if (caps & LOCAL_I915_SCHEDULER_CAP_PREEMPTION)
igt_info(" - With preemption enabled\n");
+ if (caps & LOCAL_I915_SCHEDULER_CAP_SEMAPHORES)
+ igt_info(" - With HW semaphores enabled\n");
}
diff --git a/lib/i915/gem_scheduler.h b/lib/i915/gem_scheduler.h
index 9fcb02665..ead3eacb5 100644
--- a/lib/i915/gem_scheduler.h
+++ b/lib/i915/gem_scheduler.h
@@ -27,11 +27,13 @@
#define LOCAL_I915_SCHEDULER_CAP_ENABLED (1 << 0)
#define LOCAL_I915_SCHEDULER_CAP_PRIORITY (1 << 1)
#define LOCAL_I915_SCHEDULER_CAP_PREEMPTION(1 << 2)
+#define LOCAL_I915_SCHEDULER_CAP_SEMAPHORES(1 << 3)
unsigned gem_scheduler_capability(int fd);
bool gem_scheduler_enabled(int fd);
bool gem_scheduler_has_ctx_priority(int fd);
bool gem_scheduler_has_preemption(int fd);
+bool gem_scheduler_has_semaphores(int fd);
void gem_scheduler_print_capability(int fd);
#endif /* GEM_SCHEDULER_H */
--
2.20.1
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[Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_schedule: Measure semaphore power consumption
How much energy does spinning on a semaphore consume relative to plain
old spinning?
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_schedule.c | 72 +-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 0462ce84f..184ceb7d6 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -29,9 +29,10 @@
#include
#include "igt.h"
-#include "igt_vgem.h"
+#include "igt_gpu_power.h"
#include "igt_rand.h"
#include "igt_sysfs.h"
+#include "igt_vgem.h"
#include "i915/gem_ring.h"
#define LO 0
@@ -1191,6 +1192,65 @@ static void test_pi_ringfull(int fd, unsigned int engine)
munmap(result, 4096);
}
+static void measure_semaphore_power(int i915)
+{
+ struct gpu_power power;
+ unsigned int engine, signaler;
+
+ igt_require(gpu_power_open(&power) == 0);
+
+ for_each_physical_engine(i915, signaler) {
+ struct gpu_power_sample s_spin[2];
+ struct gpu_power_sample s_sema[2];
+ double baseline, total;
+ int64_t jiffie = 1;
+ igt_spin_t *spin;
+
+ spin = __igt_spin_batch_new(i915,
+ .engine = signaler,
+ .flags = IGT_SPIN_POLL_RUN);
+ gem_wait(i915, spin->handle, &jiffie); /* waitboost */
+ igt_assert(spin->running);
+ igt_spin_busywait_until_running(spin);
+
+ gpu_power_read(&power, &s_spin[0]);
+ usleep(100*1000);
+ gpu_power_read(&power, &s_spin[1]);
+
+ /* Add a waiter to each engine */
+ for_each_physical_engine(i915, engine) {
+ igt_spin_t *sema;
+
+ if (engine == signaler)
+ continue;
+
+ sema = __igt_spin_batch_new(i915,
+ .engine = engine,
+ .dependency = spin->handle);
+
+ igt_spin_batch_free(i915, sema);
+ }
+ usleep(10); /* just give the tasklets a chance to run */
+
+ gpu_power_read(&power, &s_sema[0]);
+ usleep(100*1000);
+ gpu_power_read(&power, &s_sema[1]);
+
+ igt_spin_batch_free(i915, spin);
+
+ baseline = gpu_power_W(&power, &s_spin[0], &s_spin[1]);
+ total = gpu_power_W(&power, &s_sema[0], &s_sema[1]);
+
+ igt_info("%s: %.1fmW + %.1fmW (total %1.fmW)\n",
+e__->name,
+1e3 * baseline,
+1e3 * (total - baseline),
+1e3 * total);
+ }
+
+ gpu_power_close(&power);
+}
+
igt_main
{
const struct intel_execution_engine *e;
@@ -1351,6 +1411,16 @@ igt_main
}
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(gem_scheduler_enabled(fd));
+ igt_require(gem_scheduler_has_semaphores(fd));
+ }
+
+ igt_subtest("semaphore-power")
+ measure_semaphore_power(fd);
+ }
+
igt_fixture {
igt_stop_hang_detector();
close(fd);
--
2.20.1
___
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[Intel-gfx] [PATCH i-g-t 2/3] lib: Add GPU power measurement
Read the RAPL power metrics courtesy of perf. Or your local HW
equivalent?
Signed-off-by: Chris Wilson
---
lib/Makefile.sources | 2 +
lib/igt_gpu_power.c | 106 +++
lib/igt_gpu_power.h | 51 +
lib/meson.build | 2 +
4 files changed, 161 insertions(+)
create mode 100644 lib/igt_gpu_power.c
create mode 100644 lib/igt_gpu_power.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 808b9617e..54d9e3e7b 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -24,6 +24,8 @@ lib_source_list = \
igt_color_encoding.c\
igt_color_encoding.h\
igt_edid_template.h \
+ igt_gpu_power.c \
+ igt_gpu_power.h \
igt_gt.c\
igt_gt.h\
igt_gvt.c \
diff --git a/lib/igt_gpu_power.c b/lib/igt_gpu_power.c
new file mode 100644
index 0..bf362b2f0
--- /dev/null
+++ b/lib/igt_gpu_power.c
@@ -0,0 +1,106 @@
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt_gpu_power.h"
+#include "igt_perf.h"
+
+static int filename_to_buf(const char *filename, char *buf, unsigned int sz)
+{
+ int fd;
+ ssize_t ret;
+
+ fd = open(filename, O_RDONLY);
+ if (fd < 0)
+ return -1;
+
+ ret = read(fd, buf, sz - 1);
+ close(fd);
+ if (ret < 1)
+ return -1;
+
+ buf[ret] = '\0';
+
+ return 0;
+}
+
+static uint64_t filename_to_u64(const char *filename, int base)
+{
+ char buf[64], *b;
+
+ if (filename_to_buf(filename, buf, sizeof(buf)))
+ return 0;
+
+ /*
+* Handle both single integer and key=value formats by skipping
+* leading non-digits.
+*/
+ b = buf;
+ while (*b && !isdigit(*b))
+ b++;
+
+ return strtoull(b, NULL, base);
+}
+
+static double filename_to_double(const char *filename)
+{
+ char *oldlocale;
+ char buf[80];
+ double v;
+
+ if (filename_to_buf(filename, buf, sizeof(buf)))
+ return 0;
+
+ oldlocale = setlocale(LC_ALL, "C");
+ v = strtod(buf, NULL);
+ setlocale(LC_ALL, oldlocale);
+
+ return v;
+}
+
+static uint64_t rapl_type_id(void)
+{
+ return filename_to_u64("/sys/devices/power/type", 10);
+}
+
+static uint64_t rapl_gpu_power(void)
+{
+ return filename_to_u64("/sys/devices/power/events/energy-gpu", 0);
+}
+
+static double rapl_gpu_power_scale(void)
+{
+ return filename_to_double("/sys/devices/power/events/energy-gpu.scale");
+}
+
+int gpu_power_open(struct gpu_power *power)
+{
+ power->fd = igt_perf_open(rapl_type_id(), rapl_gpu_power());
+ if (power->fd < 0)
+ return -errno;
+
+ power->scale = rapl_gpu_power_scale();
+ if (isnan(power->scale) || !power->scale) {
+ close(power->fd);
+ return -ERANGE;
+ }
+ power->scale *= 1e9;
+
+ return 0;
+}
+
+int gpu_power_read(struct gpu_power *power, struct gpu_power_sample *s)
+{
+ if (read(power->fd, s, sizeof(*s)) != sizeof(*s))
+ return -EINVAL;
+
+ return 0;
+}
+
+void gpu_power_close(struct gpu_power *power)
+{
+ close(power->fd);
+}
diff --git a/lib/igt_gpu_power.h b/lib/igt_gpu_power.h
new file mode 100644
index 0..f6e3cbb4d
--- /dev/null
+++ b/lib/igt_gpu_power.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef IGT_GPU_POWER_H
+#define IGT_GPU_POWER_H
+
+#include
+
+struct gpu_power {
+ int fd;
+ double scale;
+};
+
+struct gpu_power_sample {
+ uint64_t energy;
+ uint64_t time;
+};
+
+int gpu_power_open(struct gpu_power *power);
+int gpu_power_read(struct gpu_power *power, struct gpu_power_sample
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: prefix header search paths with $(srctree)/
== Series Details ==
Series: drm: prefix header search paths with $(srctree)/
URL : https://patchwork.freedesktop.org/series/56020/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5516_full -> Patchwork_12100_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12100_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_color@pipe-b-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-snb: PASS -> DMESG-WARN [fdo#107469]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@gem_workarounds@suspend-resume:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-hsw: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
- shard-hsw: FAIL [fdo#99912] -> PASS
Warnings
* igt@i915_suspend@shrink:
- shard-glk: DMESG-WARN [fdo#109244] -> INCOMPLETE [fdo#103359] /
[fdo#106886] / [k.org#198133]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107469]: https://bugs.freedesktop.org/show_bug.cgi?id=107469
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5516 -> Patchwork_12100
CI_DRM_5516: d537431fd6dca11e170254956857ed38ebe1bdab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12100: 8f3c4460101cc8125fdd592471c0c282412e30c0 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12100/
___
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Add TypeC ports only if VBT is present (rev2)
On Mon, Jan 28, 2019 at 08:29:51PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/icl: Add TypeC ports only if VBT is present (rev2)
> URL : https://patchwork.freedesktop.org/series/55733/
> State : success
Pushed to -dinq, thanks for the review.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5494_full -> Patchwork_12058_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_12058_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - shard-apl: NOTRUN -> DMESG-WARN [fdo#109467]
>
> * igt@gem_eio@wait-immediate:
> - shard-kbl: PASS -> FAIL [fdo#105957]
>
> * igt@kms_available_modes_crc@available_mode_test_crc:
> - shard-apl: PASS -> FAIL [fdo#106641]
>
> * igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
> - shard-glk: PASS -> FAIL [fdo#108145]
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
> - shard-hsw: PASS -> DMESG-WARN [fdo#102614]
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
> - shard-glk: PASS -> FAIL [fdo#103166] +2
>
> * igt@prime_vgem@basic-fence-flip:
> - shard-kbl: PASS -> FAIL [fdo#104008]
>
>
> Possible fixes
>
> * igt@kms_cursor_crc@cursor-64x21-sliding:
> - shard-apl: FAIL [fdo#103232] -> PASS
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-apl: INCOMPLETE [fdo#103927] -> PASS
>
> * igt@kms_plane@plane-position-covered-pipe-a-planes:
> - shard-glk: FAIL [fdo#103166] -> PASS
>
> * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
> - shard-glk: FAIL [fdo#108145] -> PASS
>
> * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
> - shard-apl: FAIL [fdo#103166] -> PASS +2
>
> * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
> - shard-kbl: FAIL [fdo#109016] -> PASS
>
> * igt@kms_vblank@pipe-b-ts-continuation-modeset-hang:
> - shard-snb: {SKIP} [fdo#109271] -> PASS
>
> * igt@prime_busy@hang-bsd:
> - shard-hsw: FAIL [fdo#108807] -> PASS
>
>
> Warnings
>
> * igt@gem_eio@in-flight-immediate:
> - shard-kbl: DMESG-FAIL [fdo#109467] -> DMESG-WARN [fdo#109467]
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
> [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
> [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
> [fdo#105957]: https://bugs.freedesktop.org/show_bug.cgi?id=105957
> [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#108807]: https://bugs.freedesktop.org/show_bug.cgi?id=108807
> [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109467]: https://bugs.freedesktop.org/show_bug.cgi?id=109467
>
>
> Participating hosts (6 -> 5)
> --
>
> Missing(1): shard-skl
>
>
> Build changes
> -
>
> * Linux: CI_DRM_5494 -> Patchwork_12058
>
> CI_DRM_5494: 543c074ff6a401b2bca5333234a9c13c4b0a5152 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4795: 031715e369cf01aecbe293910211e80e51995ffb @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_12058: cfbebb24056d36048d2eef0c934c85ef4a4695c0 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12058/
___
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ddi: Move DDI port detection to the corresponding helper (rev2)
On Fri, Dec 21, 2018 at 04:02:07PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/3] drm/i915/ddi: Move DDI port detection to > the corresponding helper (rev2) > URL : https://patchwork.freedesktop.org/series/54341/ > State : success Pushed patch 3 too from the series, thanks for the review. > > == Summary == > > CI Bug Log - changes from CI_DRM_5336_full -> Patchwork_11141_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_11141_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_schedule@pi-ringfull-blt: > - shard-skl: NOTRUN -> FAIL [fdo#103158] > > * igt@gem_ppgtt@blt-vs-render-ctxn: > - shard-skl: PASS -> TIMEOUT [fdo#108039] > > * igt@i915_selftest@live_workarounds: > - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] > > * igt@i915_suspend@shrink: > - shard-skl: NOTRUN -> DMESG-WARN [fdo#108784] > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: > - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 > > * igt@kms_busy@extended-pageflip-hang-newfb-render-c: > - shard-glk: PASS -> DMESG-WARN [fdo#107956] > > * igt@kms_color@pipe-c-ctm-max: > - shard-apl: PASS -> FAIL [fdo#108147] > > * igt@kms_cursor_crc@cursor-128x128-onscreen: > - shard-skl: NOTRUN -> FAIL [fdo#103232] +1 > > * igt@kms_cursor_crc@cursor-128x128-suspend: > - shard-iclb: NOTRUN -> FAIL [fdo#103232] > > * igt@kms_cursor_crc@cursor-256x256-onscreen: > - shard-skl: PASS -> FAIL [fdo#103232] +1 > > * igt@kms_cursor_crc@cursor-256x85-sliding: > - shard-apl: PASS -> FAIL [fdo#103232] > > * igt@kms_flip@basic-flip-vs-wf_vblank: > - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +9 > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: > - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +4 > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: > - shard-apl: PASS -> FAIL [fdo#103167] +1 > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: > - shard-skl: PASS -> FAIL [fdo#103167] +3 > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: > - shard-glk: PASS -> FAIL [fdo#103167] +4 > > * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: > - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +5 > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt: > - shard-iclb: PASS -> FAIL [fdo#103167] +2 > > * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: > - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1 > > * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: > - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] > > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: PASS -> FAIL [fdo#107815] / [fdo#108145] > > * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: > - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 > > * igt@kms_plane_multiple@atomic-pipe-b-tiling-y: > - shard-glk: PASS -> FAIL [fdo#103166] +4 > > * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: > - shard-apl: PASS -> FAIL [fdo#103166] +1 > > * igt@kms_plane_multiple@atomic-pipe-c-tiling-y: > - shard-iclb: PASS -> FAIL [fdo#103166] > > * igt@kms_setmode@basic: > - shard-kbl: PASS -> FAIL [fdo#99912] > > * igt@kms_sysfs_edid_timing: > - shard-iclb: PASS -> FAIL [fdo#100047] > > * igt@pm_rpm@fences: > - shard-iclb: NOTRUN -> INCOMPLETE [fdo#108840] > > * igt@pm_rpm@i2c: > - shard-iclb: PASS -> FAIL [fdo#104097] > > * igt@pm_rpm@universal-planes: > - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108654] / > [fdo#108756] > > * igt@sw_sync@sync_busy_fork: > - shard-iclb: PASS -> INCOMPLETE [fdo#108889] > > > Possible fixes > > * igt@gem_eio@unwedge-stress: > - shard-glk: FAIL [fdo#105957] -> PASS > > * igt@gem_userptr_blits@readonly-unsync: > - shard-skl: TIMEOUT [fdo#108887] -> PASS > > * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels: > - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +10 > > * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: > - shard-glk: FAIL [fdo#108145] -> PASS > > * igt@kms_chv_cursor_fail@pipe-b-128x128-bottom-edge: > - shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +11 > > * igt@kms_cursor_crc@cursor-128x128-dpms: > - shard-apl: FAIL [fdo#103232] -> PASS +1 > > * i
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: do not return invalid pointers as a *dentry
== Series Details ==
Series: drm/i915: do not return invalid pointers as a *dentry
URL : https://patchwork.freedesktop.org/series/56044/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5518 -> Patchwork_12110
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56044/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12110 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: NOTRUN -> DMESG-WARN [fdo#107709]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- fi-apl-guc: PASS -> DMESG-WARN [fdo#108566]
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#109485] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: DMESG-FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108915]: https://bugs.freedesktop.org/show_bug.cgi?id=108915
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
Participating hosts (43 -> 45)
--
Additional (6): fi-bxt-dsi fi-ivb-3770 fi-icl-y fi-bsw-kefka fi-skl-6600u
fi-snb-2600
Missing(4): fi-bsw-cyan fi-ilk-m540 fi-byt-squawks fi-icl-u2
Build changes
-
* Linux: CI_DRM_5518 -> Patchwork_12110
CI_DRM_5518: 2369fd28d3a46b865f6d4f1d309a4c6b7b4e6d93 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12110: 36920a9b0dc28118dd85e0595b13fda607b39e7e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
36920a9b0dc2 drm/i915: do not return invalid pointers as a *dentry
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12110/
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev4)
== Series Details ==
Series: series starting with drm/i915: Revoke mmaps and prevent access to fence
registers across reset (rev4)
URL : https://patchwork.freedesktop.org/series/56042/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5518 -> Patchwork_12109
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56042/revisions/4/mbox/
Known issues
Here are the changes found in Patchwork_12109 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: DMESG-FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108915]: https://bugs.freedesktop.org/show_bug.cgi?id=108915
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
Participating hosts (43 -> 46)
--
Additional (6): fi-bxt-dsi fi-ivb-3770 fi-icl-y fi-bsw-kefka fi-skl-6600u
fi-snb-2600
Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-
* Linux: CI_DRM_5518 -> Patchwork_12109
CI_DRM_5518: 2369fd28d3a46b865f6d4f1d309a4c6b7b4e6d93 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12109: b14cb740ba0da05e4c0bc3d7c4384487aa938dd8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b14cb740ba0d drm/i915: Serialise resets with wedging
4e2a0fb09b7a drm/i915: Wait for old resets before applying debugfs/i915_wedged
6c7dbf50ca32 drm/i915: Uninterruptibly drain the timelines on unwedging
2b82a38d5c70 drm/i915: Force the GPU reset upon wedging
2d631da15f0d drm/i915: Revoke mmaps and prevent access to fence registers
across reset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12109/
___
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Re: [Intel-gfx] [PATCH v10 07/40] drm/i915: hdcp1.4 CP_IRQ handling and SW encryption tracking
On 1/31/2019 1:26 PM, Daniel Vetter wrote:
On Thu, Jan 31, 2019 at 12:29:23PM +0530, Ramalingam C wrote:
"hdcp_encrypted" flag is defined to denote the HDCP1.4 encryption status.
This SW tracking is used to determine the need for real hdcp1.4 disable
and hdcp_check_link upon CP_IRQ.
On CP_IRQ we filter the CP_IRQ related to the states like Link failure
and reauthentication req etc and handle them in hdcp_check_link.
CP_IRQ corresponding to the authentication msg availability are ignored.
WARN_ON is added for the abrupt stop of HDCP encryption of a port.
v2:
bool is used in struct for the cleaner coding. [Daniel]
check_link work_fn is scheduled for cp_irq handling [Daniel]
Just doing a delta-review, v2 addresses my comment about synchronization
with the worker, so
Reviewed-by: Daniel Vetter
Thank you.
--Ram
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 5 ++-
drivers/gpu/drm/i915/intel_hdcp.c | 73 ---
3 files changed, 58 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 815ee68efa2f..9ce05819fc11 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4776,7 +4776,7 @@ static void intel_dp_check_service_irq(struct intel_dp
*intel_dp)
intel_dp_handle_test_request(intel_dp);
if (val & DP_CP_IRQ)
- intel_hdcp_check_link(intel_dp->attached_connector);
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
if (val & DP_SINK_SPECIFIC_IRQ)
DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 63e009286d5f..13a41e8cf4ff 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -399,6 +399,9 @@ struct intel_hdcp {
struct delayed_work check_work;
struct work_struct prop_work;
+ /* HDCP1.4 Encryption status */
+ bool hdcp_encrypted;
+
/* HDCP2.2 related definitions */
/* Flag indicates whether this connector supports HDCP2.2 or not. */
bool hdcp2_supported;
@@ -2073,10 +2076,10 @@ int intel_hdcp_init(struct intel_connector *connector,
bool hdcp2_supported);
int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
-int intel_hdcp_check_link(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
bool intel_hdcp_capable(struct intel_connector *connector);
bool is_hdcp2_supported(struct drm_i915_private *dev_priv);
+void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
/* intel_psr.c */
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index e0bb5f32ba90..c1b057f1501b 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -74,6 +74,16 @@ bool intel_hdcp_capable(struct intel_connector *connector)
return capable;
}
+static inline bool intel_hdcp_in_use(struct intel_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ enum port port = connector->encoder->port;
+ u32 reg;
+
+ reg = I915_READ(PORT_HDCP_STATUS(port));
+ return reg & HDCP_STATUS_ENC;
+}
+
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
{
@@ -668,6 +678,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ hdcp->hdcp_encrypted = false;
I915_WRITE(PORT_HDCP_CONF(port), 0);
if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
@@ -713,8 +724,10 @@ static int _intel_hdcp_enable(struct intel_connector
*connector)
/* Incase of authentication failures, HDCP spec expects reauth. */
for (i = 0; i < tries; i++) {
ret = intel_hdcp_auth(conn_to_dig_port(connector), hdcp->shim);
- if (!ret)
+ if (!ret) {
+ hdcp->hdcp_encrypted = true;
return 0;
+ }
DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret);
@@ -741,16 +754,17 @@ int intel_hdcp_check_link(struct intel_connector *connector)
enum port port = intel_dig_port->base.port;
int ret = 0;
- if (!hdcp->shim)
- return -ENOENT;
-
mutex_lock(&hdcp->mutex);
- if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+ /* Check_link valid only wh
Re: [Intel-gfx] [PATCH v10 06/40] drm/i915: MEI interface definition
On 1/31/2019 1:47 PM, Daniel Vetter wrote:
On Thu, Jan 31, 2019 at 12:29:22PM +0530, Ramalingam C wrote:
Defining the mei-i915 interface functions and initialization of
the interface.
v2:
Adjust to the new interface changes. [Tomas]
Added further debug logs for the failures at MEI i/f.
port in hdcp_port data is equipped to handle -ve values.
v3:
mei comp is matched for global i915 comp master. [Daniel]
In hdcp_shim hdcp_protocol() is replaced with const variable. [Daniel]
mei wrappers are adjusted as per the i/f change [Daniel]
v4:
port initialization is done only at hdcp2_init only [Danvet]
v5:
I915 registers a subcomponent to be matched with mei_hdcp [Daniel]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
When you make substantial changes to a patch (like here) and decide to
keep the r-b, then please indicate that it was for an earlier version. I
most definitely didn't review this one that re-adds all the locking :-)
sure :)
What's missing here is the component_del. Not exactly sure why this
doesn't blow up.
That is weird. But yes note the absence of _del. I will introduce the
the call to hdcp_exit at unload and handle the component_del.
Luckily we don't need a component_del_typed because
component_del already takes the (dev, ops) pair, and that's unique.
yes true.
-Ram
-Daniel
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/intel_drv.h | 5 +
drivers/gpu/drm/i915/intel_hdcp.c | 378 +-
include/drm/i915_component.h | 3 +
5 files changed, 393 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a7aaa1ac4c99..75aff907ba69 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -904,6 +904,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
mutex_init(&dev_priv->av_mutex);
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
+ mutex_init(&dev_priv->hdcp_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22da9df1f0a7..d9a0771af4d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,6 +55,7 @@
#include
#include
#include
+#include
#include "i915_fixed.h"
#include "i915_params.h"
@@ -2043,6 +2044,12 @@ struct drm_i915_private {
struct i915_pmu pmu;
+ struct i915_hdcp_comp_master *hdcp_master;
+ bool hdcp_comp_added;
+
+ /* Mutex to protect the above hdcp component related values. */
+ struct mutex hdcp_comp_mutex;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0ac870feb5e9..63e009286d5f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -41,6 +41,7 @@
#include
#include
#include
+#include
#include
struct drm_printer;
@@ -385,6 +386,9 @@ struct intel_hdcp_shim {
/* Detects panel's hdcp capability. This is optional for HDMI. */
int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
bool *hdcp_capable);
+
+ /* HDCP adaptation(DP/HDMI) required on the port */
+ enum hdcp_wired_protocol protocol;
};
struct intel_hdcp {
@@ -405,6 +409,7 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
+ struct hdcp_port_data port_data;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 1a85dc46692d..e0bb5f32ba90 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -7,8 +7,10 @@
*/
#include
+#include
#include
#include
+#include
#include "intel_drv.h"
#include "i915_reg.h"
@@ -832,6 +834,348 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv,
enum port port)
return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
}
+static __attribute__((unused)) int
+hdcp2_prepare_ake_init(struct intel_connector *connector,
+ struct hdcp2_ake_init *ake_data)
+{
+ struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_hdcp_comp_master *comp;
+ int ret;
+
+ mutex_lock(&dev_priv->hdcp_comp_mutex);
+ comp = dev_priv->hdcp_master;
+
+ if (!comp || !comp->ops) {
+ mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ return -EINVAL;
+ }
+
+ ret = comp->ops->initiate_hdcp2_session(comp->me
Re: [Intel-gfx] [PATCH 10/11] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Quoting Tvrtko Ursulin (2019-01-31 13:19:31)
>
> On 30/01/2019 02:19, Chris Wilson wrote:
> > Having introduced per-context seqno, we now have a means to identity
> > progress across the system without feel of rollback as befell the
> > global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
> > advance of submission safe in the knowledge that our target seqno and
> > address is stable.
> >
> > However, since we are telling the GPU to busy-spin on the target address
> > until it matches the signaling seqno, we only want to do so when we are
> > sure that busy-spin will be completed quickly. To achieve this we only
> > submit the request to HW once the signaler is itself executing (modulo
> > preemption causing us to wait longer), and we only do so for default and
> > above priority requests (so that idle priority tasks never themselves
> > hog the GPU waiting for others).
>
> It could be milliseconds though. I think apart from media-bench saying
> this is faster, we would need to look at performance per Watt as well.
All throughput measurements are substantially faster, as you would
expect, and inter-engine latency decreased. I would hope it would
powergate/rc6 the EU while the CS was spinning, but I don't know :)
> RING_SEMA_WAIT_POLL is a potential tunable as well. Not that I have an
> idea how to tune it.
>
> Eventually, do we dare adding this without a runtime switch? (There, I
> mentioned the taboo.)
Yes :p
> What about signal mode and handling this via context switches?
That's 99% of the timeslicing scheduler right there -- the handling of
deferred work with the complication of it impacting other engines.
> > +static int
> > +emit_semaphore_wait(struct i915_request *to,
> > + struct i915_request *from,
> > + gfp_t gfp)
> > +{
> > + u32 *cs;
> > + int err;
> > +
> > + GEM_BUG_ON(!from->timeline->has_initial_breadcrumb);
> > +
> > + err = i915_timeline_read_lock(from->timeline, to);
> > + if (err)
> > + return err;
> > +
> > + /*
> > + * If we know our signaling request has started, we know that it
> > + * must, at least, have passed its initial breadcrumb and that its
> > + * seqno can only increase, therefore any change in its breadcrumb
> > + * must indicate completion. By using a "not equal to start" compare
> > + * we avoid the murky issue of how to handle seqno wraparound in an
> > + * async environment (short answer, we must stop the world whenever
> > + * any context wraps!) as the likelihood of missing one request then
> > + * seeing the same start value for a new request is 1 in 2^31, and
> > + * even then we know that the new request has started and is in
> > + * progress, so we are sure it will complete soon enough (not to
> > + * worry about).
> > + */
> > + if (i915_request_started(from)) {
> > + cs = intel_ring_begin(to, 4);
> > + if (IS_ERR(cs))
> > + return PTR_ERR(cs);
> > +
> > + *cs++ = MI_SEMAPHORE_WAIT |
> > + MI_SEMAPHORE_GLOBAL_GTT |
> > + MI_SEMAPHORE_POLL |
> > + MI_SEMAPHORE_SAD_NEQ_SDD;
> > + *cs++ = from->fence.seqno - 1;
> > + *cs++ = from->timeline->hwsp_offset;
> > + *cs++ = 0;
> > +
> > + intel_ring_advance(to, cs);
> > + } else {
> > + int err;
> > +
> > + err = i915_request_await_execution(to, from, gfp);
> > + if (err)
> > + return err;
> > +
> > + cs = intel_ring_begin(to, 4);
> > + if (IS_ERR(cs))
> > + return PTR_ERR(cs);
> > +
> > + /*
> > + * Using greater-than-or-equal here means we have to worry
> > + * about seqno wraparound. To side step that issue, we swap
> > + * the timeline HWSP upon wrapping, so that everyone listening
> > + * for the old (pre-wrap) values do not see the much smaller
> > + * (post-wrap) values than they were expecting (and so wait
> > + * forever).
> > + */
> > + *cs++ = MI_SEMAPHORE_WAIT |
> > + MI_SEMAPHORE_GLOBAL_GTT |
> > + MI_SEMAPHORE_POLL |
> > + MI_SEMAPHORE_SAD_GTE_SDD;
> > + *cs++ = from->fence.seqno;
> > + *cs++ = from->timeline->hwsp_offset;
> > + *cs++ = 0;
> > +
> > + intel_ring_advance(to, cs);
> > + }
>
> Would it not work to have a single path which emits the wait on NEQ
> from->fence.seqno - 1, just i915_request_await_execution conditional on
> i915_request_started?
>
> In the !started case, having added the await, we would know the
> semaphore wait would not run until after the dependency has started, and
> NEQ would be true when it completes. The same as the above sta
Re: [Intel-gfx] [PATCH] drm/i915: Enable fastboot by default on VLV and CHV
Op 29-01-2019 om 15:22 schreef Hans de Goede: > We really want to have fastboot enabled by default to avoid an ugly > modeset during boot. > > Currently we are enabling fastboot by default on gen9+ (Skylake and newer). > The intention is to enable it on older generations after it has seen more > testing on gen9+. > > VLV and CHV devices are still being sold in stores today, as such it is > desirable to also enable fastboot by default on these now. > > I've extensively tested fastboot=1 support on over 50 different > Bay- and Cherry-Trail devices. Testing DSI and eDP panels as well as > HDMI output (and even DP over Type-C on one device). > > All 50 devices work fine with fastboot=1. On 2 devices their DSI panel > turns black as soon as the i915 driver loads when fastboot=0, so having > fastboot enabled is required for these 2 to work properly (for lack of > a better fix). > > Signed-off-by: Hans de Goede > --- > drivers/gpu/drm/i915/intel_display.c | 10 +- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index d756d7358292..0ff42a38023c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -11672,7 +11672,15 @@ static bool fastboot_enabled(struct drm_i915_private > *dev_priv) > return i915_modparams.fastboot; > > /* Enable fastboot by default on Skylake and newer */ > - return INTEL_GEN(dev_priv) >= 9; > + if (INTEL_GEN(dev_priv) >= 9) > + return true; > + > + /* Enable fastboot by default on VLV and CHV */ > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + return true; > + > + /* Disabled by default on all others */ > + return false; > } > > static bool Reviewed-by: Maarten Lankhorst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev4)
== Series Details == Series: series starting with drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev4) URL : https://patchwork.freedesktop.org/series/56042/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Revoke mmaps and prevent access to fence registers across reset -drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_reset.c:1304:5: warning: context imbalance in 'i915_reset_trylock' - different lock contexts for basic block -drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3543:16: warning: expression using sizeof(void) Commit: drm/i915: Force the GPU reset upon wedging Okay! Commit: drm/i915: Uninterruptibly drain the timelines on unwedging Okay! Commit: drm/i915: Wait for old resets before applying debugfs/i915_wedged Okay! Commit: drm/i915: Serialise resets with wedging Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/11] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
On 30/01/2019 02:19, Chris Wilson wrote:
Having introduced per-context seqno, we now have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
It could be milliseconds though. I think apart from media-bench saying
this is faster, we would need to look at performance per Watt as well.
RING_SEMA_WAIT_POLL is a potential tunable as well. Not that I have an
idea how to tune it.
Eventually, do we dare adding this without a runtime switch? (There, I
mentioned the taboo.)
What about signal mode and handling this via context switches?
But what AB-BA deadlocks? If you remove B, there can be no deadlock...
The issue is that with a deep ELSP queue, we can queue up a pair of
AB-BA on different engines, thus forming a classic mutual exclusion
deadlock. We side-step that issue by restricting the queue depth to
avoid having multiple semaphores in flight and so we only ever take one
set of locks at a time.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 153 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_scheduler.c | 1 +
drivers/gpu/drm/i915/i915_scheduler.h | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 5 +
drivers/gpu/drm/i915/intel_lrc.c | 14 +-
8 files changed, 178 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 07e4c3c68ecd..6d825cd28ae6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -326,6 +327,76 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kfree(cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(&rq->lock);
+
+ if (list_empty(&rq->execute_cb))
+ return;
+
+ list_for_each_entry(cb, &rq->execute_cb, link)
+ irq_work_queue(&cb->work);
+
+ /*
+* XXX Rollback on __i915_request_unsubmit()
+*
+* In the future, perhaps when we have an active time-slicing scheduler,
+* it will be interesting to unsubmit parallel execution and remove
+* busywaits from the GPU until their master is restarted. This is
+* quite hairy, we have to carefully rollback the fence and do a
+* preempt-to-idle cycle on the target engine, all the while the
+* master execute_cb may refire.
+*/
+ INIT_LIST_HEAD(&rq->execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+ unsigned long flags;
+
+ if (test_bit(I915_FENCE_FLAG_ACTIVE, &signal->fence.flags))
+ return 0;
+
+ cb = kmalloc(sizeof(*cb), gfp);
+ if (!cb)
+ return -ENOMEM;
+
+ cb->fence = &rq->submit;
+ i915_sw_fence_await(cb->fence);
+ init_irq_work(&cb->work, irq_execute_cb);
+
+ spin_lock_irqsave(&signal->lock, flags);
+ if (test_bit(I915_FENCE_FLAG_ACTIVE, &signal->fence.flags)) {
+ i915_sw_fence_complete(cb->fence);
+ kfree(cb);
+ } else {
+ list_add_tail(&cb->link, &signal->execute_cb);
+ }
+ spin_unlock_irqrestore(&signal->lock, flags);
+
+ return 0;
+}
+
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -373,6 +444,7 @@ void __i915_request_submit(struct i915_request *request)
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
!i915_request_enable_breadcrumb(request))
intel_engine_queue_brea
[Intel-gfx] [PATCH] drm/i915: do not return invalid pointers as a *dentry
When calling debugfs functions, they can now return error values if something went wrong. If that happens, return a NULL as a *dentry to the relay core instead of passing it an illegal pointer. The relay core should be able to handle an illegal pointer, but add this check to be safe. Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: David Airlie Cc: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/i915/intel_guc_log.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c index d3ebdbc0182e..8bf03497dcd8 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.c +++ b/drivers/gpu/drm/i915/intel_guc_log.c @@ -140,6 +140,9 @@ static struct dentry *create_buf_file_callback(const char *filename, buf_file = debugfs_create_file(filename, mode, parent, buf, &relay_file_operations); + if (IS_ERR(buf_file)) + return NULL; + return buf_file; } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Revoke mmaps and prevent access to fence registers across reset
Previously, we were able to rely on the recursive properties of
struct_mutex to allow us to serialise revoking mmaps and reacquiring the
FENCE registers with them being clobbered over a global device reset.
I then proceeded to throw out the baby with the bath water in order to
pursue a struct_mutex-less reset.
Perusing LWN for alternative strategies, the dilemma on how to serialise
access to a global resource on one side was answered by
https://lwn.net/Articles/202847/ -- Sleepable RCU:
1 int readside(void) {
2 int idx;
3 rcu_read_lock();
4 if (nomoresrcu) {
5 rcu_read_unlock();
6 return -EINVAL;
7 }
8 idx = srcu_read_lock(&ss);
9 rcu_read_unlock();
10 /* SRCU read-side critical section. */
11 srcu_read_unlock(&ss, idx);
12 return 0;
13 }
14
15 void cleanup(void)
16 {
17 nomoresrcu = 1;
18 synchronize_rcu();
19 synchronize_srcu(&ss);
20 cleanup_srcu_struct(&ss);
21 }
No more worrying about stop_machine, just an uber-complex mutex,
optimised for reads, with the overhead pushed to the rare reset path.
However, we do run the risk of a deadlock as we allocate underneath the
SRCU read lock, and the allocation may require a GPU reset, causing a
dependency cycle via the in-flight requests. We resolve that by declaring
the driver wedged and cancelling all in-flight rendering.
v2: Use expedited rcu barriers to match our earlier timing
characteristics.
v3: Try to annotate locking contexts for sparse
v4: Reduce selftest lock duration to avoid a reset deadlock with fences
Testcase: igt/gem_mmap_gtt/hang
Fixes: eb8d0f5af4ec ("drm/i915: Remove GPU reset dependence on struct_mutex")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 18 +--
drivers/gpu/drm/i915/i915_gem.c | 56 +++--
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 31 +
drivers/gpu/drm/i915/i915_gpu_error.h | 12 +-
drivers/gpu/drm/i915/i915_reset.c | 107 +++---
drivers/gpu/drm/i915/i915_reset.h | 4 +
.../gpu/drm/i915/selftests/intel_hangcheck.c | 5 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
9 files changed, 109 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fa2c226fc779..2cea263b4d79 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1281,14 +1281,11 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
intel_wakeref_t wakeref;
enum intel_engine_id id;
+ seq_printf(m, "Reset flags: %lx\n", dev_priv->gpu_error.flags);
if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
- seq_puts(m, "Wedged\n");
+ seq_puts(m, "\tWedged\n");
if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
- seq_puts(m, "Reset in progress: struct_mutex backoff\n");
- if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
- seq_puts(m, "Waiter holding struct mutex\n");
- if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
- seq_puts(m, "struct_mutex blocked for reset\n");
+ seq_puts(m, "\tDevice (global) reset in progress\n");
if (!i915_modparams.enable_hangcheck) {
seq_puts(m, "Hangcheck disabled\n");
@@ -3885,9 +3882,6 @@ i915_wedged_set(void *data, u64 val)
* while it is writing to 'i915_wedged'
*/
- if (i915_reset_backoff(&i915->gpu_error))
- return -EAGAIN;
-
i915_handle_error(i915, val, I915_ERROR_CAPTURE,
"Manually set wedged engine mask = %llx", val);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22da9df1f0a7..f7a0e5185874 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2987,7 +2987,12 @@ i915_gem_obj_finish_shmem_access(struct
drm_i915_gem_object *obj)
i915_gem_object_unpin_pages(obj);
}
-int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
+static inline int __must_check
+i915_mutex_lock_interruptible(struct drm_device *dev)
+{
+ return mutex_lock_interruptible(&dev->struct_mutex);
+}
+
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
@@ -3004,21 +3009,11 @@ int __must_check i915_gem_set_global_seqno(struct
drm_device *dev, u32 seqno);
struct i915_request *
i915_gem_find_active_request(struct intel_engine_cs *engine);
-static inline bool i915_reset_backoff(struct i915_gpu_error *error)
-{
- return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
-}
-
static inline bool i91
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev3)
== Series Details ==
Series: series starting with [1/5] drm/i915: Revoke mmaps and prevent access to
fence registers across reset (rev3)
URL : https://patchwork.freedesktop.org/series/56042/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5518 -> Patchwork_12108
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12108 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12108, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56042/revisions/3/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12108:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_hangcheck:
- fi-bdw-gvtdvm: PASS -> TIMEOUT
- fi-bdw-5557u: PASS -> TIMEOUT
- fi-bwr-2160:PASS -> INCOMPLETE
- fi-kbl-7567u: PASS -> TIMEOUT
- fi-glk-j4005: PASS -> TIMEOUT
- fi-cfl-8109u: PASS -> TIMEOUT
- fi-snb-2520m: PASS -> TIMEOUT
- fi-pnv-d510:PASS -> TIMEOUT
- fi-cfl-8700k: PASS -> INCOMPLETE
- fi-whl-u: PASS -> TIMEOUT
- fi-ilk-650: PASS -> TIMEOUT
- fi-ivb-3520m: PASS -> INCOMPLETE
- fi-kbl-x1275: PASS -> TIMEOUT
- fi-bsw-kefka: NOTRUN -> TIMEOUT
- fi-byt-clapper: PASS -> TIMEOUT
- fi-bsw-n3050: PASS -> TIMEOUT
- fi-hsw-4770:PASS -> INCOMPLETE
- fi-skl-6770hq: PASS -> TIMEOUT
- fi-ivb-3770:NOTRUN -> INCOMPLETE
- fi-skl-6260u: PASS -> TIMEOUT
- fi-snb-2600:NOTRUN -> TIMEOUT
- fi-hsw-4770r: PASS -> INCOMPLETE
- fi-hsw-peppy: PASS -> TIMEOUT
Known issues
Here are the changes found in Patchwork_12108 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_hangcheck:
- fi-kbl-r: PASS -> INCOMPLETE [fdo#108744]
- fi-elk-e7500: PASS -> INCOMPLETE [fdo#103989]
- fi-skl-gvtdvm: PASS -> INCOMPLETE [fdo#105600] / [fdo#108744]
- fi-bxt-j4205: PASS -> INCOMPLETE [fdo#103927]
- fi-skl-6700hq: PASS -> INCOMPLETE [fdo#108744]
- fi-kbl-7500u: PASS -> INCOMPLETE [fdo#108744]
- fi-byt-j1900: PASS -> INCOMPLETE [fdo#102657]
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#108044] / [fdo#108744]
- fi-byt-n2820: PASS -> INCOMPLETE [fdo#102657]
- fi-skl-6700k2: PASS -> INCOMPLETE [fdo#108744]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#109485] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: DMESG-FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#105600]: https://bugs.freedesktop.org/show_bug.cgi?id=105600
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bug
Re: [Intel-gfx] [PATCH v10 18/40] drm/i915: CP_IRQ handling for DP HDCP2.2 msgs
On Thu, Jan 31, 2019 at 09:08:04AM +0100, Daniel Vetter wrote:
> On Thu, Jan 31, 2019 at 12:29:34PM +0530, Ramalingam C wrote:
> > Implements the
> > Waitqueue is created to wait for CP_IRQ
> > Signaling the CP_IRQ arrival through atomic variable.
> > For applicable DP HDCP2.2 msgs read wait for CP_IRQ.
> >
> > As per HDCP2.2 spec "HDCP Transmitters must process CP_IRQ interrupts
> > when they are received from HDCP Receivers"
> >
> > Without CP_IRQ processing, DP HDCP2.2 H_Prime msg was getting corrupted
> > while reading it based on corresponding status bit. This creates the
> > random failures in reading the DP HDCP2.2 msgs.
> >
> > Signed-off-by: Ramalingam C
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 33 +
> > drivers/gpu/drm/i915/intel_drv.h | 7 +++
> > drivers/gpu/drm/i915/intel_hdcp.c | 6 ++
> > 3 files changed, 38 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index b13c41220ce0..4e36df266ab3 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -5619,6 +5619,24 @@ void intel_dp_encoder_suspend(struct intel_encoder
> > *intel_encoder)
> > edp_panel_vdd_off_sync(intel_dp);
> > }
> >
> > +static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
> > + int timeout)
> > +{
> > + long ret;
> > +
> > + /* Reinit */
> > + atomic_set(&hdcp->cp_irq_recved, 0);
>
> This is still fundamentally racy. The way it's usually done is through a
> counter, i.e. the wait function samples the atomic counter, and the wait
> condition is then that the counter has increased.
>
> The interrupt handler on the other hand just does an atomic_inc. That way
> you never have the problem that the interrupt handler has set 1 before we
> clear it to 0 here.
>
> That still leaves the race that it has incremented _before_ we sampled in
> this function here. There the counter sampling needs to be moved out
> (probably before we send out the message to the sink), and passed into
> this function as a parameter.
>
> Finally there's the wrapping problem, so best to just have a condition
> like sampled_counter != current_counter.
>
> I assume this won't matter for correctness if we miss the interrupt, we
> just time out and at that point the next message should be available. But
> it's less confusing to have more correct code.
Another option would be to shrug the races off (add a comment explaining
why that's ok) and use struct completion instead of wait_queue. That one
is explicitly for one-shot stuff where the wake-up itself is all we need,
and there's no further condition to check.
-Daniel
>
> Cheers, Daniel
>
> > +
> > +#define C (atomic_read(&hdcp->cp_irq_recved) > 0)
> > + ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
> > + msecs_to_jiffies(timeout));
> > +
> > + if (ret > 0)
> > + atomic_set(&hdcp->cp_irq_recved, 0);
> > + else if (!ret)
> > + DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
> > +}
> > +
> > static
> > int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
> > u8 *an)
> > @@ -5963,14 +5981,13 @@ intel_dp_hdcp2_wait_for_msg(struct
> > intel_digital_port *intel_dig_port,
> > mdelay(timeout);
> > ret = 0;
> > } else {
> > - /* TODO: In case if you need to wait on CP_IRQ, do it here */
> > - ret = __wait_for(ret =
> > -hdcp2_detect_msg_availability(intel_dig_port,
> > - msg_id,
> > - &msg_ready),
> > -!ret && msg_ready, timeout * 1000,
> > -1000, 5 * 1000);
> > -
> > + /*
> > +* Ignoring the return of the intel_dp_hdcp_wait_for_cp_irq,
> > +* Just to detect the msg availability before failing it.
> > +*/
> > + intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
> > + ret = hdcp2_detect_msg_availability(intel_dig_port,
> > + msg_id, &msg_ready);
> > if (!msg_ready)
> > ret = -ETIMEDOUT;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 747fe7361287..1901d12bacc4 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -464,6 +464,13 @@ struct intel_hdcp {
> > * over re-Auth has to be triggered.
> > */
> > u32 seq_num_m;
> > +
> > + /*
> > +* Work queue to signal the CP_IRQ. Used for the waiters to read the
> > +* available information from HDCP DP sink.
> > +*/
> > + wait_queue_head_t cp_irq_queue;
> > + atomic_t cp
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug (rev2)
== Series Details ==
Series: drm/i915/psr: Execute the default PSR code path when setting
i915_edp_psr_debug (rev2)
URL : https://patchwork.freedesktop.org/series/56013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5515_full -> Patchwork_12099_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12099_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_pwrite_pread@snooped-copy-performance:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-b-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
Possible fixes
* igt@gem_workarounds@suspend-resume:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: FAIL [fdo#106510] / [fdo#108145] -> PASS
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: DMESG-WARN [fdo#103313] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@perf@blocking:
- shard-hsw: FAIL [fdo#102252] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102252]: https://bugs.freedesktop.org/show_bug.cgi?id=102252
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5515 -> Patchwork_12099
CI_DRM_5515: d90f6e750bfce2161e5460364651c65cbfe1a1da @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12099: 3751c63cdcb9e048d053a5c122ae66ce2dee1170 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12099/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev3)
== Series Details == Series: series starting with [1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset (rev3) URL : https://patchwork.freedesktop.org/series/56042/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Revoke mmaps and prevent access to fence registers across reset -drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_reset.c:1304:5: warning: context imbalance in 'i915_reset_lock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_reset.c:1325:6: warning: context imbalance in 'i915_reset_unlock' - unexpected unlock -drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3543:16: warning: expression using sizeof(void) Commit: drm/i915: Force the GPU reset upon wedging Okay! Commit: drm/i915: Uninterruptibly drain the timelines on unwedging Okay! Commit: drm/i915: Wait for old resets before applying debugfs/i915_wedged Okay! Commit: drm/i915: Serialise resets with wedging Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset
== Series Details ==
Series: series starting with [1/5] drm/i915: Revoke mmaps and prevent access to
fence registers across reset
URL : https://patchwork.freedesktop.org/series/56042/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5518 -> Patchwork_12107
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12107 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12107, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56042/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12107:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_hangcheck:
- fi-bdw-gvtdvm: PASS -> TIMEOUT
- fi-bdw-5557u: PASS -> TIMEOUT
- fi-bwr-2160:PASS -> INCOMPLETE
- fi-kbl-7567u: PASS -> TIMEOUT
- fi-glk-j4005: PASS -> TIMEOUT
- fi-cfl-8109u: PASS -> TIMEOUT
- fi-snb-2520m: PASS -> TIMEOUT
- fi-cfl-8700k: PASS -> INCOMPLETE
- fi-whl-u: PASS -> TIMEOUT
- fi-ilk-650: PASS -> TIMEOUT
- fi-ivb-3520m: PASS -> TIMEOUT
- fi-kbl-x1275: PASS -> TIMEOUT
- fi-kbl-8809g: PASS -> TIMEOUT
- fi-bsw-kefka: NOTRUN -> TIMEOUT
- fi-blb-e6850: PASS -> TIMEOUT
- fi-byt-clapper: PASS -> TIMEOUT
- fi-skl-6600u: NOTRUN -> TIMEOUT
- fi-bsw-n3050: PASS -> INCOMPLETE
- fi-byt-j1900: PASS -> TIMEOUT
- fi-hsw-4770:PASS -> INCOMPLETE
- fi-skl-6770hq: PASS -> TIMEOUT
- fi-byt-n2820: PASS -> TIMEOUT
- fi-ivb-3770:NOTRUN -> INCOMPLETE
- fi-skl-6700k2: PASS -> TIMEOUT
- fi-snb-2600:NOTRUN -> TIMEOUT
- fi-hsw-4770r: PASS -> TIMEOUT
- fi-hsw-peppy: PASS -> TIMEOUT
Known issues
Here are the changes found in Patchwork_12107 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-kbl-r: PASS -> INCOMPLETE [fdo#108744]
- fi-elk-e7500: PASS -> INCOMPLETE [fdo#103989]
- fi-skl-gvtdvm: PASS -> INCOMPLETE [fdo#105600] / [fdo#108744]
- fi-bxt-j4205: PASS -> INCOMPLETE [fdo#103927]
- fi-skl-6700hq: PASS -> INCOMPLETE [fdo#108744]
- fi-kbl-7500u: PASS -> INCOMPLETE [fdo#108744]
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#108044] / [fdo#108744]
- fi-skl-6260u: PASS -> INCOMPLETE [fdo#108744]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
Possible fixes
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#109485] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: DMESG-FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#105600]: https://bugs.freedesktop.org/show_bug.cgi?id=105600
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108915]: https://bugs.freedesktop.org/show_bug.cgi?id=108915
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
Participating hosts (43 -> 45)
--
Additional (6): fi-bxt-dsi fi-ivb-3770 fi-icl-y fi-bsw-kefka fi-skl-6600u
fi-snb-2600
Missing(4): fi-ilk-m540 fi-byt-squawks fi
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset
== Series Details == Series: series starting with [1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset URL : https://patchwork.freedesktop.org/series/56042/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Revoke mmaps and prevent access to fence registers across reset -drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem.c:986:39: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_reset.c:1304:5: warning: context imbalance in 'i915_reset_lock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_reset.c:1325:6: warning: context imbalance in 'i915_reset_unlock' - unexpected unlock -drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3543:16: warning: expression using sizeof(void) Commit: drm/i915: Force the GPU reset upon wedging Okay! Commit: drm/i915: Uninterruptibly drain the timelines on unwedging Okay! Commit: drm/i915: Wait for old resets before applying debugfs/i915_wedged Okay! Commit: drm/i915: Serialise resets with wedging Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Serialise resets with wedging
Prevent concurrent set-wedge with ongoing resets (and vice versa) by
taking the same wedge_mutex around both operations.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 68 ++-
1 file changed, 40 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index bbe3141c5c72..5e21bf781c0b 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -793,17 +793,14 @@ static void nop_submit_request(struct i915_request
*request)
intel_engine_queue_breadcrumbs(engine);
}
-void i915_gem_set_wedged(struct drm_i915_private *i915)
+static void __i915_gem_set_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- mutex_lock(&error->wedge_mutex);
- if (test_bit(I915_WEDGED, &error->flags)) {
- mutex_unlock(&error->wedge_mutex);
+ if (test_bit(I915_WEDGED, &error->flags))
return;
- }
if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(i915)) {
struct drm_printer p = drm_debug_printer(__func__);
@@ -852,12 +849,18 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
set_bit(I915_WEDGED, &error->flags);
GEM_TRACE("end\n");
- mutex_unlock(&error->wedge_mutex);
+}
- wake_up_all(&error->reset_queue);
+void i915_gem_set_wedged(struct drm_i915_private *i915)
+{
+ struct i915_gpu_error *error = &i915->gpu_error;
+
+ mutex_lock(&error->wedge_mutex);
+ __i915_gem_set_wedged(i915);
+ mutex_unlock(&error->wedge_mutex);
}
-bool i915_gem_unset_wedged(struct drm_i915_private *i915)
+static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
struct i915_timeline *tl;
@@ -868,8 +871,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
if (!i915->gt.scratch) /* Never full initialised, recovery impossible */
return false;
- mutex_lock(&error->wedge_mutex);
-
GEM_TRACE("start\n");
/*
@@ -920,11 +921,21 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
clear_bit(I915_WEDGED, &i915->gpu_error.flags);
- mutex_unlock(&i915->gpu_error.wedge_mutex);
-
return true;
}
+bool i915_gem_unset_wedged(struct drm_i915_private *i915)
+{
+ struct i915_gpu_error *error = &i915->gpu_error;
+ bool result;
+
+ mutex_lock(&error->wedge_mutex);
+ result = __i915_gem_unset_wedged(i915);
+ mutex_unlock(&error->wedge_mutex);
+
+ return result;
+}
+
static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
{
int err, i;
@@ -976,7 +987,7 @@ void i915_reset(struct drm_i915_private *i915,
GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
/* Clear any previous failed attempts at recovery. Time to try again. */
- if (!i915_gem_unset_wedged(i915))
+ if (!__i915_gem_unset_wedged(i915))
return;
if (reason)
@@ -1038,7 +1049,7 @@ void i915_reset(struct drm_i915_private *i915,
*/
add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
error:
- i915_gem_set_wedged(i915);
+ __i915_gem_set_wedged(i915);
goto finish;
}
@@ -1198,6 +1209,7 @@ void i915_handle_error(struct drm_i915_private *i915,
unsigned long flags,
const char *fmt, ...)
{
+ struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
intel_wakeref_t wakeref;
unsigned int tmp;
@@ -1234,20 +1246,19 @@ void i915_handle_error(struct drm_i915_private *i915,
* Try engine reset when available. We fall back to full reset if
* single reset fails.
*/
- if (intel_has_reset_engine(i915) &&
- !i915_terminally_wedged(&i915->gpu_error)) {
+ if (intel_has_reset_engine(i915) && !i915_terminally_wedged(error)) {
for_each_engine_masked(engine, i915, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
-&i915->gpu_error.flags))
+&error->flags))
continue;
if (i915_reset_engine(engine, msg) == 0)
engine_mask &= ~intel_engine_flag(engine);
clear_bit(I915_RESET_ENGINE + engine->id,
- &i915->gpu_error.flags);
- wake_up_bit(&i915->gpu_error.flags,
+ &error->flags);
+
[Intel-gfx] [PATCH] drm/i915: Serialise resets with wedging
Prevent concurrent set-wedge with ongoing resets (and vice versa) by
taking the same wedge_mutex around both operations.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 70 ++-
1 file changed, 40 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index bbe3141c5c72..ce266865b594 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -793,18 +793,12 @@ static void nop_submit_request(struct i915_request
*request)
intel_engine_queue_breadcrumbs(engine);
}
-void i915_gem_set_wedged(struct drm_i915_private *i915)
+static void __i915_gem_set_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- mutex_lock(&error->wedge_mutex);
- if (test_bit(I915_WEDGED, &error->flags)) {
- mutex_unlock(&error->wedge_mutex);
- return;
- }
-
if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(i915)) {
struct drm_printer p = drm_debug_printer(__func__);
@@ -852,12 +846,19 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
set_bit(I915_WEDGED, &error->flags);
GEM_TRACE("end\n");
- mutex_unlock(&error->wedge_mutex);
+}
- wake_up_all(&error->reset_queue);
+void i915_gem_set_wedged(struct drm_i915_private *i915)
+{
+ struct i915_gpu_error *error = &i915->gpu_error;
+
+ mutex_lock(&error->wedge_mutex);
+ if (!test_bit(I915_WEDGED, &error->flags))
+ __i915_gem_set_wedged(i915);
+ mutex_unlock(&error->wedge_mutex);
}
-bool i915_gem_unset_wedged(struct drm_i915_private *i915)
+static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
struct i915_timeline *tl;
@@ -868,8 +869,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
if (!i915->gt.scratch) /* Never full initialised, recovery impossible */
return false;
- mutex_lock(&error->wedge_mutex);
-
GEM_TRACE("start\n");
/*
@@ -920,11 +919,21 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
clear_bit(I915_WEDGED, &i915->gpu_error.flags);
- mutex_unlock(&i915->gpu_error.wedge_mutex);
-
return true;
}
+bool i915_gem_unset_wedged(struct drm_i915_private *i915)
+{
+ struct i915_gpu_error *error = &i915->gpu_error;
+ bool result;
+
+ mutex_lock(&error->wedge_mutex);
+ result = __i915_gem_unset_wedged(i915);
+ mutex_unlock(&error->wedge_mutex);
+
+ return result;
+}
+
static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
{
int err, i;
@@ -976,7 +985,7 @@ void i915_reset(struct drm_i915_private *i915,
GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
/* Clear any previous failed attempts at recovery. Time to try again. */
- if (!i915_gem_unset_wedged(i915))
+ if (!__i915_gem_unset_wedged(i915))
return;
if (reason)
@@ -1038,7 +1047,7 @@ void i915_reset(struct drm_i915_private *i915,
*/
add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
error:
- i915_gem_set_wedged(i915);
+ __i915_gem_set_wedged(i915);
goto finish;
}
@@ -1198,6 +1207,7 @@ void i915_handle_error(struct drm_i915_private *i915,
unsigned long flags,
const char *fmt, ...)
{
+ struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
intel_wakeref_t wakeref;
unsigned int tmp;
@@ -1234,20 +1244,19 @@ void i915_handle_error(struct drm_i915_private *i915,
* Try engine reset when available. We fall back to full reset if
* single reset fails.
*/
- if (intel_has_reset_engine(i915) &&
- !i915_terminally_wedged(&i915->gpu_error)) {
+ if (intel_has_reset_engine(i915) && !i915_terminally_wedged(error)) {
for_each_engine_masked(engine, i915, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
-&i915->gpu_error.flags))
+&error->flags))
continue;
if (i915_reset_engine(engine, msg) == 0)
engine_mask &= ~intel_engine_flag(engine);
clear_bit(I915_RESET_ENGINE + engine->id,
- &i915->gpu_error.flags);
- wake_up_bit(&i915->gpu_error.flags,
+ &error->f
Re: [Intel-gfx] [PATCH v4.1 2/3] drm: Add CRTC background color property (v4)
On Wed, Jan 30, 2019 at 06:11:16PM -0800, Matt Roper wrote:
> On Wed, Jan 30, 2019 at 11:01:25PM +0200, Ville Syrjälä wrote:
> > On Wed, Jan 30, 2019 at 10:51:21AM -0800, Matt Roper wrote:
> > > Some display controllers can be programmed to present non-black colors
> > > for pixels not covered by any plane (or pixels covered by the
> > > transparent regions of higher planes). Compositors that want a UI with
> > > a solid color background can potentially save memory bandwidth by
> > > setting the CRTC background property and using smaller planes to display
> > > the rest of the content.
> > >
> > > To avoid confusion between different ways of encoding RGB data, we
> > > define a standard 64-bit format that should be used for this property's
> > > value. Helper functions and macros are provided to generate and dissect
> > > values in this standard format with varying component precision values.
> > >
> > > v2:
> > > - Swap internal representation's blue and red bits to make it easier
> > >to read if printed out. (Ville)
> > > - Document bgcolor property in drm_blend.c. (Sean Paul)
> > > - s/background_color/bgcolor/ for consistency between property name and
> > >value storage field. (Sean Paul)
> > > - Add a convenience function to attach property to a given crtc.
> > >
> > > v3:
> > > - Restructure ARGB component extraction macros to be easier to
> > >understand and enclose the parameters in () to avoid calculations
> > >if expressions are passed. (Sean Paul)
> > > - s/rgba/argb/ in helper function/macro names. Even though the idea is
> > >to not worry about the internal representation of the u64, it can
> > >still be confusing to look at code that uses 'rgba' terminology, but
> > >stores values with argb ordering. (Ville)
> > >
> > > v4:
> > > - Drop the bgcolor_changed flag. (Ville, Brian Starkey)
> > > - Clarify in kerneldoc that background color is expected to undergo the
> > >same pipe-level degamma/csc/gamma transformations that planes do.
> > >(Brian Starkey)
> > > - Update kerneldoc to indicate non-opaque colors are allowed, but are
> > >generally only useful in special cases such as when writeback
> > >connectors are used (Brian Starkey / Eric Anholt)
> > >
> > > Cc: dri-de...@lists.freedesktop.org
> > > Cc: wei.c...@intel.com
> > > Cc: harish.krupo@intel.com
> > > Cc: Ville Syrjälä
> > > Cc: Sean Paul
> > > Cc: Brian Starkey
> > > Cc: Eric Anholt
> > > Cc: Stéphane Marchesin
> > > Cc: Daniel Vetter
> > > Signed-off-by: Matt Roper
> > > Reviewed-by(v2): Sean Paul
> > > Reviewed-by: Brian Starkey
> > > ---
> > > drivers/gpu/drm/drm_atomic_uapi.c | 4
> > > drivers/gpu/drm/drm_blend.c | 27 ---
> > > drivers/gpu/drm/drm_mode_config.c | 6 ++
> > > include/drm/drm_blend.h | 1 +
> > > include/drm/drm_crtc.h| 12
> > > include/drm/drm_mode_config.h | 5 +
> > > include/uapi/drm/drm_mode.h | 28
> > > 7 files changed, 80 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > index 9a1f41adfc67..d569e20e34e3 100644
> > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > @@ -469,6 +469,8 @@ static int drm_atomic_crtc_set_property(struct
> > > drm_crtc *crtc,
> > > return -EFAULT;
> > >
> > > set_out_fence_for_crtc(state->state, crtc, fence_ptr);
> > > + } else if (property == config->bgcolor_property) {
> > > + state->bgcolor = val;
> > > } else if (crtc->funcs->atomic_set_property) {
> > > return crtc->funcs->atomic_set_property(crtc, state, property,
> > > val);
> > > } else {
> > > @@ -503,6 +505,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
> > > *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
> > > else if (property == config->prop_out_fence_ptr)
> > > *val = 0;
> > > + else if (property == config->bgcolor_property)
> > > + *val = state->bgcolor;
> > > else if (crtc->funcs->atomic_get_property)
> > > return crtc->funcs->atomic_get_property(crtc, state, property,
> > > val);
> > > else
> > > diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
> > > index 0c78ca386cbe..d451ac9e1d6d 100644
> > > --- a/drivers/gpu/drm/drm_blend.c
> > > +++ b/drivers/gpu/drm/drm_blend.c
> > > @@ -175,9 +175,22 @@
> > > *plane does not expose the "alpha" property, then this
> > > is
> > > *assumed to be 1.0
> > > *
> > > - * Note that all the property extensions described here apply either to
> > > the
> > > - * plane or the CRTC (e.g. for the background color, which currently is
> > > not
> > > - * exposed and assumed to be black).
> > > + * The property extensions described above all apply to the plane.
> > > Drivers
>
[Intel-gfx] [PATCH 1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset
Previously, we were able to rely on the recursive properties of
struct_mutex to allow us to serialise revoking mmaps and reacquiring the
FENCE registers with them being clobbered over a global device reset.
I then proceeded to throw out the baby with the bath water in order to
pursue a struct_mutex-less reset.
Perusing LWN for alternative strategies, the dilemma on how to serialise
access to a global resource on one side was answered by
https://lwn.net/Articles/202847/ -- Sleepable RCU:
1 int readside(void) {
2 int idx;
3 rcu_read_lock();
4 if (nomoresrcu) {
5 rcu_read_unlock();
6 return -EINVAL;
7 }
8 idx = srcu_read_lock(&ss);
9 rcu_read_unlock();
10 /* SRCU read-side critical section. */
11 srcu_read_unlock(&ss, idx);
12 return 0;
13 }
14
15 void cleanup(void)
16 {
17 nomoresrcu = 1;
18 synchronize_rcu();
19 synchronize_srcu(&ss);
20 cleanup_srcu_struct(&ss);
21 }
No more worrying about stop_machine, just an uber-complex mutex,
optimised for reads, with the overhead pushed to the rare reset path.
However, we do run the risk of a deadlock as we allocate underneath the
SRCU read lock, and the allocation may require a GPU reset, causing a
dependency cycle via the in-flight requests. We resolve that by declaring
the driver wedged and cancelling all in-flight rendering.
v2: Use expedited rcu barriers to match our earlier timing
characteristics.
Testcase: igt/gem_mmap_gtt/hang
Fixes: eb8d0f5af4ec ("drm/i915: Remove GPU reset dependence on struct_mutex")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 18 +--
drivers/gpu/drm/i915/i915_gem.c | 56 +++---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 31 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 12 +-
drivers/gpu/drm/i915/i915_reset.c | 103 +++---
drivers/gpu/drm/i915/i915_reset.h | 4 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
8 files changed, 103 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fa2c226fc779..2cea263b4d79 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1281,14 +1281,11 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
intel_wakeref_t wakeref;
enum intel_engine_id id;
+ seq_printf(m, "Reset flags: %lx\n", dev_priv->gpu_error.flags);
if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
- seq_puts(m, "Wedged\n");
+ seq_puts(m, "\tWedged\n");
if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
- seq_puts(m, "Reset in progress: struct_mutex backoff\n");
- if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
- seq_puts(m, "Waiter holding struct mutex\n");
- if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
- seq_puts(m, "struct_mutex blocked for reset\n");
+ seq_puts(m, "\tDevice (global) reset in progress\n");
if (!i915_modparams.enable_hangcheck) {
seq_puts(m, "Hangcheck disabled\n");
@@ -3885,9 +3882,6 @@ i915_wedged_set(void *data, u64 val)
* while it is writing to 'i915_wedged'
*/
- if (i915_reset_backoff(&i915->gpu_error))
- return -EAGAIN;
-
i915_handle_error(i915, val, I915_ERROR_CAPTURE,
"Manually set wedged engine mask = %llx", val);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22da9df1f0a7..f7a0e5185874 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2987,7 +2987,12 @@ i915_gem_obj_finish_shmem_access(struct
drm_i915_gem_object *obj)
i915_gem_object_unpin_pages(obj);
}
-int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
+static inline int __must_check
+i915_mutex_lock_interruptible(struct drm_device *dev)
+{
+ return mutex_lock_interruptible(&dev->struct_mutex);
+}
+
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
@@ -3004,21 +3009,11 @@ int __must_check i915_gem_set_global_seqno(struct
drm_device *dev, u32 seqno);
struct i915_request *
i915_gem_find_active_request(struct intel_engine_cs *engine);
-static inline bool i915_reset_backoff(struct i915_gpu_error *error)
-{
- return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
-}
-
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
return unlikely(test_bit(I915_WEDGED, &error->flags));
}
-static inline bool i915_reset_backoff_or_wedged(stru
[Intel-gfx] [PATCH 2/5] drm/i915: Force the GPU reset upon wedging
When declaring the GPU wedged, we do need to hit the GPU with the reset
hammer so that its state matches our presumed state during cleanup. If
the reset fails, it fails, and we may be unhappy but wedged. However, if
we are testing our wedge/unwedged handling, the desync carries over into
the next test and promptly explodes.
References: https://bugs.freedesktop.org/show_bug.cgi?id=106702
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reset.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 0a6784cec4fd..db37fe819504 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -532,9 +532,6 @@ typedef int (*reset_func)(struct drm_i915_private *,
static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
{
- if (!i915_modparams.reset)
- return NULL;
-
if (INTEL_GEN(i915) >= 8)
return gen8_reset_engines;
else if (INTEL_GEN(i915) >= 6)
@@ -599,6 +596,9 @@ bool intel_has_gpu_reset(struct drm_i915_private *i915)
if (USES_GUC(i915))
return false;
+ if (!i915_modparams.reset)
+ return NULL;
+
return intel_get_gpu_reset(i915);
}
@@ -823,7 +823,7 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
reset_prepare_engine(engine);
/* Even if the GPU reset fails, it should still stop the engines */
- if (INTEL_GEN(i915) >= 5)
+ if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
intel_gpu_reset(i915, ALL_ENGINES);
for_each_engine(engine, i915, id) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Serialise resets with wedging
Prevent concurrent set-wedge with ongoing resets (and vice versa) by
taking the same wedge_mutex around both operations.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 71 ++-
1 file changed, 41 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index bbe3141c5c72..3a14109435d4 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -793,18 +793,12 @@ static void nop_submit_request(struct i915_request
*request)
intel_engine_queue_breadcrumbs(engine);
}
-void i915_gem_set_wedged(struct drm_i915_private *i915)
+static void __i915_gem_set_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- mutex_lock(&error->wedge_mutex);
- if (test_bit(I915_WEDGED, &error->flags)) {
- mutex_unlock(&error->wedge_mutex);
- return;
- }
-
if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(i915)) {
struct drm_printer p = drm_debug_printer(__func__);
@@ -852,12 +846,20 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
set_bit(I915_WEDGED, &error->flags);
GEM_TRACE("end\n");
- mutex_unlock(&error->wedge_mutex);
+}
- wake_up_all(&error->reset_queue);
+void i915_gem_set_wedged(struct drm_i915_private *i915)
+{
+ struct i915_gpu_error *error = &i915->gpu_error;
+
+ mutex_lock(&error->wedge_mutex);
+ if (!test_bit(I915_WEDGED, &error->flags)) {
+ __i915_gem_set_wedged(i915);
+ mutex_unlock(&error->wedge_mutex);
+ }
}
-bool i915_gem_unset_wedged(struct drm_i915_private *i915)
+static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
struct i915_timeline *tl;
@@ -868,8 +870,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
if (!i915->gt.scratch) /* Never full initialised, recovery impossible */
return false;
- mutex_lock(&error->wedge_mutex);
-
GEM_TRACE("start\n");
/*
@@ -920,11 +920,21 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
clear_bit(I915_WEDGED, &i915->gpu_error.flags);
- mutex_unlock(&i915->gpu_error.wedge_mutex);
-
return true;
}
+bool i915_gem_unset_wedged(struct drm_i915_private *i915)
+{
+ struct i915_gpu_error *error = &i915->gpu_error;
+ bool result;
+
+ mutex_lock(&error->wedge_mutex);
+ result = __i915_gem_unset_wedged(i915);
+ mutex_unlock(&error->wedge_mutex);
+
+ return result;
+}
+
static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
{
int err, i;
@@ -976,7 +986,7 @@ void i915_reset(struct drm_i915_private *i915,
GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
/* Clear any previous failed attempts at recovery. Time to try again. */
- if (!i915_gem_unset_wedged(i915))
+ if (!__i915_gem_unset_wedged(i915))
return;
if (reason)
@@ -1038,7 +1048,7 @@ void i915_reset(struct drm_i915_private *i915,
*/
add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
error:
- i915_gem_set_wedged(i915);
+ __i915_gem_set_wedged(i915);
goto finish;
}
@@ -1198,6 +1208,7 @@ void i915_handle_error(struct drm_i915_private *i915,
unsigned long flags,
const char *fmt, ...)
{
+ struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
intel_wakeref_t wakeref;
unsigned int tmp;
@@ -1234,20 +1245,19 @@ void i915_handle_error(struct drm_i915_private *i915,
* Try engine reset when available. We fall back to full reset if
* single reset fails.
*/
- if (intel_has_reset_engine(i915) &&
- !i915_terminally_wedged(&i915->gpu_error)) {
+ if (intel_has_reset_engine(i915) && !i915_terminally_wedged(error)) {
for_each_engine_masked(engine, i915, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
-&i915->gpu_error.flags))
+&error->flags))
continue;
if (i915_reset_engine(engine, msg) == 0)
engine_mask &= ~intel_engine_flag(engine);
clear_bit(I915_RESET_ENGINE + engine->id,
- &i915->gpu_error.flags);
- wake_up_bit(&i915->gpu_error.flags,
+
[Intel-gfx] [PATCH 3/5] drm/i915: Uninterruptibly drain the timelines on unwedging
On wedging, we mark all executing requests as complete and all pending
requests completed as soon as they are ready. Before unwedging though we
wish to flush those pending requests prior to restoring default
execution, and so we must wait. Do so interruptibly as we do not provide
the EINTR gracefully back to userspace in this case but persistent in
the permanently wedged start without restarting the syscall.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 28
1 file changed, 8 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index db37fe819504..bbe3141c5c72 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -861,7 +861,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
struct i915_timeline *tl;
- bool ret = false;
if (!test_bit(I915_WEDGED, &error->flags))
return true;
@@ -886,30 +885,20 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
mutex_lock(&i915->gt.timelines.mutex);
list_for_each_entry(tl, &i915->gt.timelines.active_list, link) {
struct i915_request *rq;
- long timeout;
rq = i915_gem_active_get_unlocked(&tl->last_request);
if (!rq)
continue;
/*
-* We can't use our normal waiter as we want to
-* avoid recursively trying to handle the current
-* reset. The basic dma_fence_default_wait() installs
-* a callback for dma_fence_signal(), which is
-* triggered by our nop handler (indirectly, the
-* callback enables the signaler thread which is
-* woken by the nop_submit_request() advancing the seqno
-* and when the seqno passes the fence, the signaler
-* then signals the fence waking us up).
+* All internal dependencies (i915_requests) will have
+* been flushed by the set-wedge, but we may be stuck waiting
+* for external fences. These should all be capped to 10s
+* (I915_FENCE_TIMEOUT) so this wait should not be unbounded
+* in the worst case.
*/
- timeout = dma_fence_default_wait(&rq->fence, true,
-MAX_SCHEDULE_TIMEOUT);
+ dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);
i915_request_put(rq);
- if (timeout < 0) {
- mutex_unlock(&i915->gt.timelines.mutex);
- goto unlock;
- }
}
mutex_unlock(&i915->gt.timelines.mutex);
@@ -930,11 +919,10 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
clear_bit(I915_WEDGED, &i915->gpu_error.flags);
- ret = true;
-unlock:
+
mutex_unlock(&i915->gpu_error.wedge_mutex);
- return ret;
+ return true;
}
static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
--
2.20.1
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[Intel-gfx] [PATCH 4/5] drm/i915: Wait for old resets before applying debugfs/i915_wedged
Since we use the debugfs to recover the device after modifying the
i915.reset parameter, we need to be sure that we apply the reset and not
piggy-back onto a concurrent one in order for the parameter to take
effect.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2cea263b4d79..54e426883529 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3874,13 +3874,9 @@ i915_wedged_set(void *data, u64 val)
{
struct drm_i915_private *i915 = data;
- /*
-* There is no safeguard against this debugfs entry colliding
-* with the hangcheck calling same i915_handle_error() in
-* parallel, causing an explosion. For now we assume that the
-* test harness is responsible enough not to inject gpu hangs
-* while it is writing to 'i915_wedged'
-*/
+ /* Flush any previous reset before applying for a new one */
+ wait_event(i915->gpu_error.reset_queue,
+ !test_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags));
i915_handle_error(i915, val, I915_ERROR_CAPTURE,
"Manually set wedged engine mask = %llx", val);
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/opregion: rvda is relative from opregion base, not absolute
On Tue, 29 Jan 2019, Jani Nikula wrote: > This is obviously a backward/forward incompatible change. I've been > told there are no systems out there using the field. There are systems like that, in our CI too. Back to the drawing board. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v31 4/5] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
Quoting Tvrtko Ursulin (2019-01-31 12:47:51)
> From: Tvrtko Ursulin
>
> We want to allow userspace to reconfigure the subslice configuration on a
> per context basis.
>
> This is required for the functional requirement of shutting down non-VME
> enabled sub-slices on Gen11 parts.
>
> To do so, we expose a context parameter to allow adjustment of the RPCS
> register stored within the context image (and currently not accessible via
> LRI).
>
> If the context is adjusted before first use or whilst idle, the adjustment
> is for "free"; otherwise if the context is active we queue a request to do
> so (using the kernel context), following all other activity by that
> context, which is also marked as barrier for all following submission
> against the same context.
>
> Since the overhead of device re-configuration during context switching can
> be significant, especially in multi-context workloads, we limit this new
> uAPI to only support the Gen11 VME use case. In this use case either the
> device is fully enabled, and exactly one slice and half of the subslices
> are enabled.
>
> Example usage:
>
> struct drm_i915_gem_context_param_sseu sseu = { };
> struct drm_i915_gem_context_param arg = {
> .param = I915_CONTEXT_PARAM_SSEU,
> .ctx_id = gem_context_create(fd),
> .size = sizeof(sseu),
> .value = to_user_pointer(&sseu)
> };
>
> /* Query device defaults. */
> gem_context_get_param(fd, &arg);
>
> /* Set VME configuration on a 1x6x8 part. */
> sseu.slice_mask = 0x1;
> sseu.subslice_mask = 0xe0;
> gem_context_set_param(fd, &arg);
>
> v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu()
> (Lionel)
>
> v3: Add ability to program this per engine (Chris)
>
> v4: Move most get_sseu() into i915_gem_context.c (Lionel)
>
> v5: Validate sseu configuration against the device's capabilities (Lionel)
>
> v6: Change context powergating settings through MI_SDM on kernel context
> (Chris)
>
> v7: Synchronize the requests following a powergating setting change using
> a global dependency (Chris)
> Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
> Disable RPCS configuration setting for non capable users
> (Lionel/Tvrtko)
>
> v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
> s/dev_priv/i915/ (Tvrtko)
> Change uapi class/instance fields to u16 (Tvrtko)
> Bump mask fields to 64bits (Lionel)
> Don't return EPERM when dynamic sseu is disabled (Tvrtko)
>
> v9: Import context image into kernel context's ppgtt only when
> reconfiguring powergated slice/subslices (Chris)
> Use aliasing ppgtt when needed (Michel)
>
> Tvrtko Ursulin:
>
> v10:
> * Update for upstream changes.
> * Request submit needs a RPM reference.
> * Reject on !FULL_PPGTT for simplicity.
> * Pull out get/set param to helpers for readability and less indent.
> * Use i915_request_await_dma_fence in add_global_barrier to skip waits
>on the same timeline and avoid GEM_BUG_ON.
> * No need to explicitly assign a NULL pointer to engine in legacy mode.
> * No need to move gen8_make_rpcs up.
> * Factored out global barrier as prep patch.
> * Allow to only CAP_SYS_ADMIN if !Gen11.
>
> v11:
> * Remove engine vfunc in favour of local helper. (Chris Wilson)
> * Stop retiring requests before updates since it is not needed
>(Chris Wilson)
> * Implement direct CPU update path for idle contexts. (Chris Wilson)
> * Left side dependency needs only be on the same context timeline.
>(Chris Wilson)
> * It is sufficient to order the timeline. (Chris Wilson)
> * Reject !RCS configuration attempts with -ENODEV for now.
>
> v12:
> * Rebase for make_rpcs.
>
> v13:
> * Centralize SSEU normalization to make_rpcs.
> * Type width checking (uAPI <-> implementation).
> * Gen11 restrictions uAPI checks.
> * Gen11 subslice count differences handling.
> Chris Wilson:
> * args->size handling fixes.
> * Update context image from GGTT.
> * Postpone context image update to pinning.
> * Use i915_gem_active_raw instead of last_request_on_engine.
>
> v14:
> * Add activity tracker on intel_context to fix the lifetime issues
>and simplify the code. (Chris Wilson)
>
> v15:
> * Fix context pin leak if no space in ring by simplifying the
>context pinning sequence.
>
> v16:
> * Rebase for context get/set param locking changes.
> * Just -ENODEV on !Gen11. (Joonas)
>
> v17:
> * Fix one Gen11 subslice enablement rule.
> * Handle error from i915_sw_fence_await_sw_fence_gfp. (Chris Wilson)
>
> v18:
> * Update commit message. (Joonas)
> * Restrict uAPI to VME use case. (Joonas)
>
> v19:
> * Rebase.
>
> v20:
> * Rebase for ce->active_tracker.
>
> v21:
> * Rebase for IS_GEN changes.
>
> v22:
> * Reserve uAPI for flags straight away. (Chris Wilson)
>
> v23:
> * Rebase for RUNTIME_INFO.
>
> v24:
> * Added some headline docs for t
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Allocate active tracking nodes from a slabcache
Quoting Tvrtko Ursulin (2019-01-31 11:39:46)
>
>
> On 30/01/2019 20:50, Chris Wilson wrote:
> > Wrap the active tracking for a GPU references in a slabcache for faster
> > allocations, and hopefully better fragmentation reduction.
> >
>
> v2 where art thou? :)
You killed v2!
> > v3: Nothing device specific left, it's just a slabcache that we can
> > make global.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > diff --git a/drivers/gpu/drm/i915/i915_active.h
> > b/drivers/gpu/drm/i915/i915_active.h
> > index 6130c6770d10..48fdb1497883 100644
> > --- a/drivers/gpu/drm/i915/i915_active.h
> > +++ b/drivers/gpu/drm/i915/i915_active.h
> > @@ -63,4 +63,7 @@ void i915_active_fini(struct i915_active *ref);
> > static inline void i915_active_fini(struct i915_active *ref) { }
> > #endif
> >
> > +int i915_global_active_init(void);
> > +void i915_global_active_exit(void);
> > +
> > #endif /* _I915_ACTIVE_H_ */
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index 44c23ac60347..751a787c83d1 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
>
> Add explicit #include "i915_active.h"?
Indeed.
-Chris
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Allocate active tracking nodes from a slabcache
On 30/01/2019 20:50, Chris Wilson wrote:
Wrap the active tracking for a GPU references in a slabcache for faster
allocations, and hopefully better fragmentation reduction.
v2 where art thou? :)
v3: Nothing device specific left, it's just a slabcache that we can
make global.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 31 +++---
drivers/gpu/drm/i915/i915_active.h | 3 +++
drivers/gpu/drm/i915/i915_pci.c| 3 +++
3 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index b1fefe98f9a6..5818ddf88462 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -9,6 +9,17 @@
#define BKL(ref) (&(ref)->i915->drm.struct_mutex)
+/*
+ * Active refs memory management
+ *
+ * To be more economical with memory, we reap all the i915_active trees as
+ * they idle (when we know the active requests are inactive) and allocate the
+ * nodes from a local slab cache to hopefully reduce the fragmentation.
+ */
+static struct i915_global_active {
+ struct kmem_cache *slab_cache;
+} global;
+
struct active_node {
struct i915_gem_active base;
struct i915_active *ref;
@@ -23,7 +34,7 @@ __active_park(struct i915_active *ref)
rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
GEM_BUG_ON(i915_gem_active_isset(&it->base));
- kfree(it);
+ kmem_cache_free(global.slab_cache, it);
}
ref->tree = RB_ROOT;
}
@@ -96,11 +107,11 @@ active_instance(struct i915_active *ref, u64 idx)
p = &parent->rb_left;
}
- node = kmalloc(sizeof(*node), GFP_KERNEL);
+ node = kmem_cache_alloc(global.slab_cache, GFP_KERNEL);
/* kmalloc may retire the ref->last (thanks shrinker)! */
if (unlikely(!i915_gem_active_raw(&ref->last, BKL(ref {
- kfree(node);
+ kmem_cache_free(global.slab_cache, node);
goto out;
}
@@ -234,6 +245,20 @@ void i915_active_fini(struct i915_active *ref)
GEM_BUG_ON(!RB_EMPTY_ROOT(&ref->tree));
GEM_BUG_ON(ref->count);
}
+
+int __init i915_global_active_init(void)
+{
+ global.slab_cache = KMEM_CACHE(active_node, SLAB_HWCACHE_ALIGN);
+ if (!global.slab_cache)
+ return -ENOMEM;
+
+ return 0;
+}
+
+void __exit i915_global_active_exit(void)
+{
+ kmem_cache_destroy(global.slab_cache);
+}
#endif
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 6130c6770d10..48fdb1497883 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -63,4 +63,7 @@ void i915_active_fini(struct i915_active *ref);
static inline void i915_active_fini(struct i915_active *ref) { }
#endif
+int i915_global_active_init(void);
+void i915_global_active_exit(void);
+
#endif /* _I915_ACTIVE_H_ */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44c23ac60347..751a787c83d1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
Add explicit #include "i915_active.h"?
@@ -793,6 +793,8 @@ static int __init i915_init(void)
bool use_kms = true;
int err;
+ i915_global_active_init();
+
err = i915_mock_selftests();
if (err)
return err > 0 ? 0 : err;
@@ -824,6 +826,7 @@ static void __exit i915_exit(void)
return;
pci_unregister_driver(&i915_pci_driver);
+ i915_global_active_exit();
}
module_init(i915_init);
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Generalise GPU activity tracking
On 31/01/2019 11:32, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-01-31 11:25:10) On 30/01/2019 20:50, Chris Wilson wrote: We currently track GPU memory usage inside VMA, such that we never release memory used by the GPU until after it has finished accessing it. However, we may want to track other resources aside from VMA, or we may want to split a VMA into multiple independent regions and track each separately. For this purpose, generalise our request tracking (akin to struct reservation_object) so that we can embed it into other objects. Changelog where art thou? The changes are patches 2 & 3! This patch is just about moving code, we haven't come up with a new name so nothing to change here yet. But I wanted to discuss to the idea of immediately parking and using global slabs. There's a new GEM_BUG_ON! ;) Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Release the active tracker tree upon idling
On 30/01/2019 20:50, Chris Wilson wrote:
As soon as we detect that the active tracker is idle and we prepare to
call the retire callback, release the storage for our tree of
per-timeline nodes. We expect these to be infrequently usage and quick
s/usage/used/
to allocate, so there is little benefit in keeping the tree cached and
we would prefer to return the pages back to the system in a timely
fashion.
This also means that when we finalize the struct as a whole, we know as
the activity tracker must be idle, the tree has already been released.
Indeed we can reduce i915_active_fini() just the assertions that there
is nothing to do.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_active.c | 33 +-
drivers/gpu/drm/i915/i915_active.h | 4
2 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 91950d778cab..b1fefe98f9a6 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -16,12 +16,29 @@ struct active_node {
u64 timeline;
};
+static void
+__active_park(struct i915_active *ref)
+{
+ struct active_node *it, *n;
+
+ rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
+ GEM_BUG_ON(i915_gem_active_isset(&it->base));
+ kfree(it);
+ }
+ ref->tree = RB_ROOT;
+}
+
static void
__active_retire(struct i915_active *ref)
{
GEM_BUG_ON(!ref->count);
- if (!--ref->count)
- ref->retire(ref);
+ if (--ref->count)
+ return;
+
+ /* return the unused nodes to our slabcache */
+ __active_park(ref);
+
+ ref->retire(ref);
}
static void
@@ -210,18 +227,14 @@ int i915_request_await_active(struct i915_request *rq,
struct i915_active *ref)
return 0;
}
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
void i915_active_fini(struct i915_active *ref)
{
- struct active_node *it, *n;
-
GEM_BUG_ON(i915_gem_active_isset(&ref->last));
-
- rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
- GEM_BUG_ON(i915_gem_active_isset(&it->base));
- kfree(it);
- }
- ref->tree = RB_ROOT;
+ GEM_BUG_ON(!RB_EMPTY_ROOT(&ref->tree));
+ GEM_BUG_ON(ref->count);
}
+#endif
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/i915_active.c"
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 8bd7cf757d1a..6130c6770d10 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -57,6 +57,10 @@ i915_active_is_idle(const struct i915_active *ref)
return !ref->count;
}
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
void i915_active_fini(struct i915_active *ref);
+#else
+static inline void i915_active_fini(struct i915_active *ref) { }
+#endif
#endif /* _I915_ACTIVE_H_ */
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev29)
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev29)
URL : https://patchwork.freedesktop.org/series/48194/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5518 -> Patchwork_12106
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48194/revisions/29/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12106:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@cursor_plane_move:
- {fi-icl-u2}:PASS -> {SKIP} +3
- {fi-icl-u3}:PASS -> {SKIP} +3
Known issues
Here are the changes found in Patchwork_12106 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: NOTRUN -> DMESG-WARN [fdo#107709]
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bwr-2160:PASS -> FAIL [fdo#100368]
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: NOTRUN -> FAIL [fdo#108800]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: {SKIP} [fdo#109271] / [fdo#109278] -> PASS +2
- fi-apl-guc: {SKIP} [fdo#109271] -> PASS +5
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_busy@basic-flip-b:
- fi-cfl-guc: {SKIP} [fdo#109271] -> PASS +5
- fi-skl-guc: {SKIP} [fdo#109271] -> PASS +5
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#109485] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@prime_vgem@basic-wait-default:
- fi-kbl-guc: {SKIP} [fdo#109271] -> PASS +13
Warnings
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: DMESG-FAIL [fdo#103182] -> FAIL [fdo#103182]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108915]: https://bugs.freedesktop.org/show_bug.cgi?id=108915
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
Participating hosts (43 -> 46)
--
Additional (6): fi-bxt-dsi fi-ivb-3770 fi-icl-y fi-bsw-kefka fi-skl-6600u
fi-snb-2600
Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-
* IGT: IGT_4801 -> IGTPW_2250
* Linux: CI_DRM_5518 -> Patchwork_12106
CI_DRM_5518: 2369fd28d3a46b865f6d4f1d309a4c6b7b4e6d93 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2250: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2250/
IGT_4801: 6f6bacf12759fb319ade3ba37861ae711f8a5cd9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12106: 90e180c46c8b859a1216d9497e6b4a476e3e2ea1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
90e180c46c8b drm/i915/selftests: Context SSEU reconfiguration tests
c39a50cfc9cb drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11
only)
27b8398a7623 drm/i915: Add timeline barrier support
0c2b9f0bab2f drm/i915/perf: lock powergating configuration to default when
active
65d9322d71e7 drm/i915: Record the sseu configuration per-context & engine
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12106/
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Generalise GPU activity tracking
Quoting Tvrtko Ursulin (2019-01-31 11:25:10) > > On 30/01/2019 20:50, Chris Wilson wrote: > > We currently track GPU memory usage inside VMA, such that we never > > release memory used by the GPU until after it has finished accessing it. > > However, we may want to track other resources aside from VMA, or we may > > want to split a VMA into multiple independent regions and track each > > separately. For this purpose, generalise our request tracking (akin to > > struct reservation_object) so that we can embed it into other objects. > > > > Changelog where art thou? The changes are patches 2 & 3! This patch is just about moving code, we haven't come up with a new name so nothing to change here yet. But I wanted to discuss to the idea of immediately parking and using global slabs. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Generalise GPU activity tracking
On 30/01/2019 20:50, Chris Wilson wrote:
We currently track GPU memory usage inside VMA, such that we never
release memory used by the GPU until after it has finished accessing it.
However, we may want to track other resources aside from VMA, or we may
want to split a VMA into multiple independent regions and track each
separately. For this purpose, generalise our request tracking (akin to
struct reservation_object) so that we can embed it into other objects.
Changelog where art thou?
Signed-off-by: Chris Wilson
---
Ideas for names?
i915_activity_tracker
i915_active_object
i915_active_reference // tempting
gpu_read_lock (i915_read_lock was the first name I tried)
Fwiw, by the end there will be nothing i915 specific to this so perhaps
dma_read_lock isn't so bad?
i915_active_request -> dma_read_fence
Possibilities there.
i915_active_reference sounds good.
i915_active_reference_ref though? :) i915_active_reference_
-Chris
---
drivers/gpu/drm/i915/Makefile | 4 +-
drivers/gpu/drm/i915/i915_active.c| 228 ++
drivers/gpu/drm/i915/i915_active.h| 62 +
drivers/gpu/drm/i915/i915_active_types.h | 26 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_vma.c | 173 +++--
drivers/gpu/drm/i915/i915_vma.h | 9 +-
drivers/gpu/drm/i915/selftests/i915_active.c | 158
.../drm/i915/selftests/i915_live_selftests.h | 3 +-
9 files changed, 512 insertions(+), 154 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_active.c
create mode 100644 drivers/gpu/drm/i915/i915_active.h
create mode 100644 drivers/gpu/drm/i915/i915_active_types.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_active.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 210d0e8777b6..1787e1299b1b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,7 +57,9 @@ i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# GEM code
-i915-y += i915_cmd_parser.o \
+i915-y += \
+ i915_active.o \
+ i915_cmd_parser.o \
i915_gem_batch_pool.o \
i915_gem_clflush.o \
i915_gem_context.o \
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
new file mode 100644
index ..91950d778cab
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -0,0 +1,228 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_active.h"
+
+#define BKL(ref) (&(ref)->i915->drm.struct_mutex)
+
+struct active_node {
+ struct i915_gem_active base;
+ struct i915_active *ref;
+ struct rb_node node;
+ u64 timeline;
+};
+
+static void
+__active_retire(struct i915_active *ref)
+{
+ GEM_BUG_ON(!ref->count);
+ if (!--ref->count)
+ ref->retire(ref);
+}
+
+static void
+node_retire(struct i915_gem_active *base, struct i915_request *rq)
+{
+ __active_retire(container_of(base, struct active_node, base)->ref);
+}
+
+static void
+last_retire(struct i915_gem_active *base, struct i915_request *rq)
+{
+ __active_retire(container_of(base, struct i915_active, last));
+}
+
+static struct i915_gem_active *
+active_instance(struct i915_active *ref, u64 idx)
+{
+ struct active_node *node;
+ struct rb_node **p, *parent;
+ struct i915_request *old;
+
+ /*
+* We track the most recently used timeline to skip a rbtree search
+* for the common case, under typical loads we never need the rbtree
+* at all. We can reuse the last slot if it is empty, that is
+* after the previous activity has been retired, or if it matches the
+* current timeline.
+*
+* Note that we allow the timeline to be active simultaneously in
+* the rbtree and the last cache. We do this to avoid having
+* to search and replace the rbtree element for a new timeline, with
+* the cost being that we must be aware that the ref may be retired
+* twice for the same timeline (as the older rbtree element will be
+* retired before the new request added to last).
+*/
+ old = i915_gem_active_raw(&ref->last, BKL(ref));
+ if (!old || old->fence.context == idx)
+ goto out;
+
+ /* Move the currently active fence into the rbtree */
+ idx = old->fence.context;
+
+ parent = NULL;
+ p = &ref->tree.rb_node;
+ while (*p) {
+ parent = *p;
+
+ node = rb_entry(parent, struct active_node, node);
+ if (node->timeline == idx)
+ goto replace;
+
+ if (node->timeline < idx)
+ p = &parent->rb_right;
+ else
+ p = &parent->rb_left;
+ }
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per context dynamic (sub)slice power-gating (rev29)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev29) URL : https://patchwork.freedesktop.org/series/48194/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Record the sseu configuration per-context & engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3563:16: warning: expression using sizeof(void) Commit: drm/i915/perf: lock powergating configuration to default when active Okay! Commit: drm/i915: Add timeline barrier support Okay! Commit: drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) +drivers/gpu/drm/i915/intel_lrc.c:2503:25: warning: expression using sizeof(void) Commit: drm/i915/selftests: Context SSEU reconfiguration tests +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1134:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1134:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1134:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1134:25: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
