[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/9] drm/i915/psr: Remove PSR2 FIXME
== Series Details == Series: series starting with [v4,1/9] drm/i915/psr: Remove PSR2 FIXME URL : https://patchwork.freedesktop.org/series/57455/ State : success == Summary == CI Bug Log - changes from CI_DRM_5683 -> Patchwork_12353 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57455/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12353 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - fi-apl-guc: PASS -> DMESG-WARN [fdo#108566] * igt@kms_psr@cursor_plane_move: - fi-whl-u: PASS -> FAIL [fdo#107383] +3 Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: FAIL [fdo#103167] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 Participating hosts (45 -> 38) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_5683 -> Patchwork_12353 CI_DRM_5683: 40251405bb454b06259738bcebf4529c888f7fe0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12353: ff4c7ff7b3f047ed9bd682d56a5050eb9a2b64e4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ff4c7ff7b3f0 drm/i915: Enable PSR2 by default adab6c2064da drm/i915/psr: Set idle frames to maximum while getting pipe CRC 9e7167e444cf drm/i915: Drop redundant checks to update PSR state 0aef9406df81 drm/i915: Disable PSR2 while getting pipe CRC dd9ba679c107 drm/i915/crc: Make IPS workaround generic 376f040f9469 drm/i915/psr: Drop test for EDP in CRTC when forcing commit 6dcd509f0c19 drm/i915: Compute and commit color features in fastsets d41c4a7f5c1d drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset b965245818e9 drm/i915/psr: Remove PSR2 FIXME == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12353/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register
== Series Details == Series: series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register URL : https://patchwork.freedesktop.org/series/57454/ State : success == Summary == CI Bug Log - changes from CI_DRM_5683 -> Patchwork_12352 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57454/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12352 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_busy@basic-flip-a: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] / [fdo#109799] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@kms_busy@basic-flip-b: - fi-gdg-551: FAIL [fdo#103182] -> PASS [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#109799]: https://bugs.freedesktop.org/show_bug.cgi?id=109799 Participating hosts (45 -> 38) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-n2820 fi-bdw-samus Build changes - * Linux: CI_DRM_5683 -> Patchwork_12352 CI_DRM_5683: 40251405bb454b06259738bcebf4529c888f7fe0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12352: 2299a0a818e982fff3b5252b109a915c3a2f9a3f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2299a0a818e9 drm/i915: fix placement of ICP_PP_CONTROL dee9ff2ced87 drm/i915: Fix bit name in PP_STATUS register == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12352/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/vlv: Move czclk to intel_pm
== Series Details == Series: series starting with [1/5] drm/i915/vlv: Move czclk to intel_pm URL : https://patchwork.freedesktop.org/series/57453/ State : success == Summary == CI Bug Log - changes from CI_DRM_5683 -> Patchwork_12351 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57453/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12351 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +20 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] / [fdo#109799] Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@kms_busy@basic-flip-b: - fi-gdg-551: FAIL [fdo#103182] -> PASS [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#109799]: https://bugs.freedesktop.org/show_bug.cgi?id=109799 Participating hosts (45 -> 39) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_5683 -> Patchwork_12351 CI_DRM_5683: 40251405bb454b06259738bcebf4529c888f7fe0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12351: 06211158028af0eb8e8ce1ef8b71889253e139ba @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 06211158028a drm/i915: Extract gem_init() from modeset_load() ada5cd59f87a drm/i915: Move rawclck, power_domain and irq un/initialization from modeset functions fd3e84069434 drm/i915: Add a cleanup function for i915_modeset_load() 1a0f043cb3e3 drm/i915: Rename i915_load_modeset_init() to i915_modeset_load() 7fd936317d66 drm/i915/vlv: Move czclk to intel_pm == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12351/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/9] drm/i915/psr: Remove PSR2 FIXME
== Series Details == Series: series starting with [v4,1/9] drm/i915/psr: Remove PSR2 FIXME URL : https://patchwork.freedesktop.org/series/57455/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Remove PSR2 FIXME Okay! Commit: drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset Okay! Commit: drm/i915: Compute and commit color features in fastsets Okay! Commit: drm/i915/psr: Drop test for EDP in CRTC when forcing commit Okay! Commit: drm/i915/crc: Make IPS workaround generic Okay! Commit: drm/i915: Disable PSR2 while getting pipe CRC Okay! Commit: drm/i915: Drop redundant checks to update PSR state Okay! Commit: drm/i915/psr: Set idle frames to maximum while getting pipe CRC -O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) Commit: drm/i915: Enable PSR2 by default Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 2/5] drm/i915: Watchdog timeout: IRQ handler for gen8+
On Fri, 2019-03-01 at 09:36 +, Chris Wilson wrote:
> Quoting Carlos Santa (2019-02-21 02:58:16)
> > +#define GEN8_WATCHDOG_1000US(dev_priv)
> > watchdog_to_clock_counts(dev_priv, 1000)
> > +static void gen8_watchdog_irq_handler(unsigned long data)
> > +{
> > + struct intel_engine_cs *engine = (struct intel_engine_cs
> > *)data;
> > + struct drm_i915_private *dev_priv = engine->i915;
> > + unsigned int hung = 0;
> > + u32 current_seqno=0;
> > + char msg[80];
> > + unsigned int tmp;
> > + int len;
> > +
> > + /* Stop the counter to prevent further timeout interrupts
> > */
> > + I915_WRITE_FW(RING_CNTR(engine->mmio_base),
> > get_watchdog_disable(engine));
> > +
> > + /* Read the heartbeat seqno once again to check if we are
> > stuck? */
> > + current_seqno = intel_engine_get_hangcheck_seqno(engine);
>
> I have said this before, but this doesn't exist either, it's just a
> temporary glitch in the matrix.
That was my only way to check for the "quilty" seqno right before
resetting during smoke testing... Will reach out again before sending a
new rev to cross check on the new approach you mentioned today.
>
> > +if (current_seqno == engine->current_seqno) {
> > + hung |= engine->mask;
> > +
> > + len = scnprintf(msg, sizeof(msg), "%s on ",
> > "watchdog timeout");
> > + for_each_engine_masked(engine, dev_priv, hung, tmp)
> > + len += scnprintf(msg + len, sizeof(msg) -
> > len,
> > +"%s, ", engine->name);
> > + msg[len-2] = '\0';
> > +
> > + i915_handle_error(dev_priv, hung, 0, "%s", msg);
> > +
> > + /* Reset timer in case GPU hangs without another
> > request being added */
> > + i915_queue_hangcheck(dev_priv);
>
> You still haven't explained why we are not just resetting the engine
> immediately. Have you looked at the preempt-timeout patches that need
> to
> do the same thing from timer-irq context?
>
> Resending the same old stuff over and over again is just
> exasperating.
> -Chris
Oops, I had the wrong assumption, as I honestly thought removing the
workqueue from v3 would allow for an immediate reset. Thanks for the
feedback on the preempt-timeout series... will rework this.
Carlos
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register
== Series Details == Series: series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register URL : https://patchwork.freedesktop.org/series/57454/ State : warning == Summary == $ dim checkpatch origin/drm-tip dee9ff2ced87 drm/i915: Fix bit name in PP_STATUS register 2299a0a818e9 drm/i915: fix placement of ICP_PP_CONTROL -:7: WARNING:TYPO_SPELLING: 'aligment' may be misspelled - perhaps 'alignment'? #7: it down together with PP_CONTROL and fix the aligment of the bit total: 0 errors, 1 warnings, 0 checks, 34 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 7/9] drm/i915: Drop redundant checks to update PSR state
All of this checks are redudant and can be removed as the if bellow
already takes care when there is no changes in the state.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 73453d89a841..d3e3996551c6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -878,15 +878,11 @@ void intel_psr_update(struct intel_dp *intel_dp,
if (enable == psr->enabled && psr2_enable == psr->psr2_enabled)
goto unlock;
- if (psr->enabled) {
- if (!enable || psr2_enable != psr->psr2_enabled)
- intel_psr_disable_locked(intel_dp);
- }
+ if (psr->enabled)
+ intel_psr_disable_locked(intel_dp);
- if (enable) {
- if (!psr->enabled || psr2_enable != psr->psr2_enabled)
- intel_psr_enable_locked(dev_priv, crtc_state);
- }
+ if (enable)
+ intel_psr_enable_locked(dev_priv, crtc_state);
unlock:
mutex_unlock(_priv->psr.lock);
--
2.21.0
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[Intel-gfx] [PATCH v4 2/9] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset
Forcing a specific CRTC to the eDP connector was causing the
intel_psr_fastset_force() to mark mode_chaged in the wrong and
disabled CRTC causing no update in the PSR state.
Looks like our internal state track do not clear output_types and
has_psr in the disabled CRTCs, not sure if this is the expected
behavior or not but in the mean time this fix the issue.
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 8bed73914876..6175b1d2e0c8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -981,7 +981,8 @@ static int intel_psr_fastset_force(struct drm_i915_private
*dev_priv)
intel_crtc_state = to_intel_crtc_state(crtc_state);
- if (intel_crtc_has_type(intel_crtc_state, INTEL_OUTPUT_EDP) &&
+ if (crtc_state->active &&
+ intel_crtc_has_type(intel_crtc_state, INTEL_OUTPUT_EDP) &&
intel_crtc_state->has_psr) {
/* Mark mode as changed to trigger a pipe->update() */
crtc_state->mode_changed = true;
--
2.21.0
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[Intel-gfx] [PATCH v4 8/9] drm/i915/psr: Set idle frames to maximum while getting pipe CRC
Increase the idle frames to activate PSR1 to avoid CRC timeouts, as
soon as pipe CRC is enabled it will avoid PSR1 to activate but if
PSR1 is activate before that, hardware goes to lower power states
that inhibits CRC calculations causing CRC timeout errors in IGT
tests.
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 453af7438e67..e336f758e481 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -521,6 +521,7 @@ struct i915_psr {
bool sink_not_reliable;
bool irq_aux_error;
u16 su_x_granularity;
+ bool crc_enabled;
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d3e3996551c6..b237d96db277 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -452,6 +452,16 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
* frames, we'll go with 9 frames for now
*/
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+
+ /*
+* Increase the idle frames to active PSR1 to avoid CRC timeouts, as
+* soon as pipe CRC is enabled it will avoid PSR1 to activate but if
+* PSR1 is activate before that, hardware goes to lower power states
+* that inhibits CRC calculations.
+*/
+ if (dev_priv->psr.crc_enabled)
+ idle_frames = 0xf;
+
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
@@ -723,6 +733,7 @@ static void intel_psr_enable_locked(struct drm_i915_private
*dev_priv,
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ dev_priv->psr.crc_enabled = crtc_state->crc_enabled;
DRM_DEBUG_KMS("Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
@@ -865,7 +876,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct i915_psr *psr = _priv->psr;
- bool enable, psr2_enable;
+ bool enable, psr2_enable, pipe_crc_changed;
if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
return;
@@ -874,8 +885,10 @@ void intel_psr_update(struct intel_dp *intel_dp,
enable = crtc_state->has_psr && psr_global_enabled(psr->debug);
psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
+ pipe_crc_changed = crtc_state->crc_enabled != psr->crc_enabled;
- if (enable == psr->enabled && psr2_enable == psr->psr2_enabled)
+ if (enable == psr->enabled && psr2_enable == psr->psr2_enabled &&
+ !pipe_crc_changed)
goto unlock;
if (psr->enabled)
--
2.21.0
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[Intel-gfx] [PATCH v4 4/9] drm/i915/psr: Drop test for EDP in CRTC when forcing commit
If has_psr is set it means that CRTC has a EDP panel attached so it
can be dropped, also has_psr is better than check for EDP output
alone as it will avoid set mode_changed when PSR is not supported in
panel or with current modeset.
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6175b1d2e0c8..2d9f64c362e2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -981,9 +981,7 @@ static int intel_psr_fastset_force(struct drm_i915_private
*dev_priv)
intel_crtc_state = to_intel_crtc_state(crtc_state);
- if (crtc_state->active &&
- intel_crtc_has_type(intel_crtc_state, INTEL_OUTPUT_EDP) &&
- intel_crtc_state->has_psr) {
+ if (crtc_state->active && intel_crtc_state->has_psr) {
/* Mark mode as changed to trigger a pipe->update() */
crtc_state->mode_changed = true;
break;
--
2.21.0
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[Intel-gfx] [PATCH v4 6/9] drm/i915: Disable PSR2 while getting pipe CRC
When PSR2 is active aka after the number of frames programmed in
PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
interruptions causing IGT tests to fail due timeout.
This same behavior don't happen with PSR1, as soon as pipe CRC is
enabled it blocks PSR1 activation so CRC calculation continues to
happens normaly.
This patch also set mode_changed as true when PSR is available to
force atomic check functions to compute new PSR state, otherwise PSR2
would not be disabled.
v4: Only setting mode_changed if has_psr is set(Dhinakaran)
v3: Reusing intel_crtc_crc_prepare() and crc_enabled, only setting
mode_changed if it can do PSR.
v2: Changed commit description to describe that PSR2 inhibit CRC
calculations.
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
drivers/gpu/drm/i915/intel_psr.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index af64597c5c6e..c17f02b88453 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -307,6 +307,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc,
bool enable)
goto put_state;
}
+ pipe_config->base.mode_changed = pipe_config->has_psr;
pipe_config->crc_enabled = enable;
if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A) {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d9f64c362e2..73453d89a841 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
+ if (crtc_state->crc_enabled)
+ return false;
+
return true;
}
--
2.21.0
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[Intel-gfx] [PATCH v4 9/9] drm/i915: Enable PSR2 by default
The support for PSR2 was polished, IGT tests for PSR2 was added and it was tested performing regular user workloads like browsing, editing documents and compiling Linux, so it is time to enable it by default and enjoy even more power-savings. Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index b237d96db277..116c8b50ee78 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -80,9 +80,6 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, case I915_PSR_DEBUG_DISABLE: case I915_PSR_DEBUG_FORCE_PSR1: return false; - case I915_PSR_DEBUG_DEFAULT: - if (i915_modparams.enable_psr <= 0) - return false; default: return crtc_state->has_psr2; } -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/9] drm/i915/psr: Remove PSR2 FIXME
Now we are checking sink capabilities when probing PSR DPCD register and then dynamically checking in if new state is compatible with PSR in, so this FIXME can be dropped. Reviewed-by: Dhinakaran Pandiyan Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 75c1a5deebf5..8bed73914876 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -532,11 +532,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; int psr_max_h = 0, psr_max_v = 0; - /* -* FIXME psr2_support is messed up. It's both computed -* dynamically during PSR enable, and extracted from sink -* caps during eDP detection. -*/ if (!dev_priv->psr.sink_psr2_support) return false; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/9] drm/i915: Compute and commit color features in fastsets
In any commit, intel_modeset_pipe_config() will initialilly clear
and then recalculate most of the pipe states but it leave intel
specific color features states in reset state.
If after intel_pipe_config_compare() is detected that a fastset is
possible it will mark update_pipe as true and unsed mode_changed,
causing the color features state to be kept in reset state and then
latter being committed to hardware disabling the color features.
This issue can be reproduced by any code patch that duplicates the
actual(with color features already enabled) state and only mark
mode_changed as true.
Reviewed-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7c5e84ef5171..816e8f124b3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11232,7 +11232,8 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
return ret;
}
- if (mode_changed || crtc_state->color_mgmt_changed) {
+ if (mode_changed || pipe_config->update_pipe ||
+ crtc_state->color_mgmt_changed) {
ret = intel_color_check(pipe_config);
if (ret)
return ret;
--
2.21.0
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[Intel-gfx] [PATCH v4 5/9] drm/i915/crc: Make IPS workaround generic
Other features like PSR2 also needs to be disabled while getting CRC
so lets rename ips_force_disable to crc_enabled, drop all this checks
for pipe A and HSW and BDW and make it generic and
hsw_compute_ips_config() will take care of all the checks removed
from here.
v2: Renaming and parameter changes to the functions that prepares the
commit (Ville)
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 10 --
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_pipe_crc.c | 47 +++
3 files changed, 29 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 816e8f124b3b..328967c642b3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6751,7 +6751,13 @@ static bool hsw_compute_ips_config(struct
intel_crtc_state *crtc_state)
if (!hsw_crtc_state_ips_capable(crtc_state))
return false;
- if (crtc_state->ips_force_disable)
+ /*
+* When IPS gets enabled, the pipe CRC changes. Since IPS gets
+* enabled and disabled dynamically based on package C states,
+* user space can't make reliable use of the CRCs, so let's just
+* completely disable it.
+*/
+ if (crtc_state->crc_enabled)
return false;
/* IPS should be fine as long as at least one plane is enabled. */
@@ -11684,7 +11690,7 @@ clear_intel_crtc_state(struct intel_crtc_state
*crtc_state)
saved_state->shared_dpll = crtc_state->shared_dpll;
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
saved_state->pch_pfit.force_thru = crtc_state->pch_pfit.force_thru;
- saved_state->ips_force_disable = crtc_state->ips_force_disable;
+ saved_state->crc_enabled = crtc_state->crc_enabled;
if (IS_G4X(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
saved_state->wm = crtc_state->wm;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5412373e2f98..2be64529e4a2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -999,7 +999,8 @@ struct intel_crtc_state {
struct intel_link_m_n fdi_m_n;
bool ips_enabled;
- bool ips_force_disable;
+
+ bool crc_enabled;
bool enable_fbc;
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 53d4ec68d3c4..af64597c5c6e 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -280,15 +280,15 @@ static int ilk_pipe_crc_ctl_reg(enum
intel_pipe_crc_source *source,
return 0;
}
-static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
- bool enable)
+static void
+intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_device *dev = _priv->drm;
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
struct drm_modeset_acquire_ctx ctx;
- int ret = 0;
+ int ret;
drm_modeset_acquire_init(, 0);
@@ -307,17 +307,9 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private
*dev_priv,
goto put_state;
}
- if (HAS_IPS(dev_priv)) {
- /*
-* When IPS gets enabled, the pipe CRC changes. Since IPS gets
-* enabled and disabled dynamically based on package C states,
-* user space can't make reliable use of the CRCs, so let's just
-* completely disable it.
-*/
- pipe_config->ips_force_disable = enable;
- }
+ pipe_config->crc_enabled = enable;
- if (IS_HASWELL(dev_priv)) {
+ if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A) {
pipe_config->pch_pfit.force_thru = enable;
if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
pipe_config->pch_pfit.enabled != enable)
@@ -343,8 +335,7 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private
*dev_priv,
static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source,
- u32 *val,
- bool set_wa)
+ u32 *val)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
@@ -357,10 +348,6 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv,
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
break;
case
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fix atomic state leak when resetting HDMI link
== Series Details == Series: series starting with [1/3] drm/i915: Fix atomic state leak when resetting HDMI link URL : https://patchwork.freedesktop.org/series/57452/ State : success == Summary == CI Bug Log - changes from CI_DRM_5682 -> Patchwork_12350 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57452/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12350 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@memory-alloc: - fi-ivb-3520m: NOTRUN -> SKIP [fdo#109271] +48 Possible fixes * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: FAIL [fdo#103167] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (42 -> 38) -- Additional (1): fi-ivb-3520m Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-gdg-551 Build changes - * Linux: CI_DRM_5682 -> Patchwork_12350 CI_DRM_5682: e6481defd076c8507c8d5a503b2edd9c7a382ef7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12350: 43b6419ddc23e2be6a1ac5f5b6e73d24194cd449 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 43b6419ddc23 drm/i915: Forcing a modeset when resetting HDMI link cc51bea3db6e drm/i915: Don't manually add connectors and planes state 154d2c0bce1b drm/i915: Fix atomic state leak when resetting HDMI link == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12350/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Fix bit name in PP_STATUS register
According to the spec PP_SEQUENCE_STATE_ON_S1_1 is the correct name, so
just rename it.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9b482bc6433..c9b868347481 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4723,7 +4723,7 @@ enum {
#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
#define PP_SEQUENCE_STATE_ON_IDLE(0x8 << 0)
-#define PP_SEQUENCE_STATE_ON_S1_0(0x9 << 0)
+#define PP_SEQUENCE_STATE_ON_S1_1(0x9 << 0)
#define PP_SEQUENCE_STATE_ON_S1_2(0xa << 0)
#define PP_SEQUENCE_STATE_ON_S1_3(0xb << 0)
#define PP_SEQUENCE_STATE_RESET (0xf << 0)
--
2.20.1
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[Intel-gfx] [PATCH 2/2] drm/i915: fix placement of ICP_PP_CONTROL
This register was placed in the middle of the PP_STATUS definition. Move
it down together with PP_CONTROL and fix the aligment of the bit
definition (as per documentation it should be 2 spaces instead of 1).
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9b868347481..bbbc0649a180 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4692,17 +4692,6 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON(1 << 31)
-
-#define _PP_CONTROL_1 0xc7204
-#define _PP_CONTROL_2 0xc7304
-#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
- _PP_CONTROL_2)
-#define POWER_CYCLE_DELAY_MASK(0x1f << 4)
-#define POWER_CYCLE_DELAY_SHIFT 4
-#define VDD_OVERRIDE_FORCE(1 << 3)
-#define BACKLIGHT_ENABLE (1 << 2)
-#define PWR_DOWN_ON_RESET (1 << 1)
-#define PWR_STATE_TARGET (1 << 0)
/*
* Indicates that all dependencies of the panel are on:
*
@@ -4728,6 +4717,17 @@ enum {
#define PP_SEQUENCE_STATE_ON_S1_3(0xb << 0)
#define PP_SEQUENCE_STATE_RESET (0xf << 0)
+#define _PP_CONTROL_1 0xc7204
+#define _PP_CONTROL_2 0xc7304
+#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+ _PP_CONTROL_2)
+#define POWER_CYCLE_DELAY_MASK (0x1f << 4)
+#define POWER_CYCLE_DELAY_SHIFT 4
+#define VDD_OVERRIDE_FORCE (1 << 3)
+#define BACKLIGHT_ENABLE (1 << 2)
+#define PWR_DOWN_ON_RESET(1 << 1)
+#define PWR_STATE_TARGET (1 << 0)
+
#define _PP_CONTROL0x61204
#define PP_CONTROL(pps_idx)_MMIO_PPS(pps_idx, _PP_CONTROL)
#define PANEL_UNLOCK_REGS (0xabcd << 16)
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Yet another if/else sort of newer to older platforms. (rev3)
== Series Details == Series: drm/i915: Yet another if/else sort of newer to older platforms. (rev3) URL : https://patchwork.freedesktop.org/series/57112/ State : success == Summary == CI Bug Log - changes from CI_DRM_5679_full -> Patchwork_12348_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12348_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-semaphore-render: - shard-iclb: NOTRUN -> SKIP [fdo#109275] * igt@gem_ctx_isolation@rcs0-dirty-create: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +3 * igt@gem_ctx_param@invalid-param-set: - shard-skl: NOTRUN -> FAIL [fdo#109674] * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_schedule@preempt-other-chain-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +8 * igt@gem_mocs_settings@mocs-rc6-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] * igt@gem_mocs_settings@mocs-settings-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109287] +2 * igt@gem_pwrite@big-cpu-fbr: - shard-skl: NOTRUN -> SKIP [fdo#109271] +177 * igt@gem_pwrite@huge-gtt-forwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@gem_stolen@stolen-pread: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +2 * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] / [fdo#108840] * igt@i915_pm_rpm@legacy-planes: - shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] +1 * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3 * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@5x-modeset-transitions: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15 * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +3 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-apl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +2 * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: - shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145] * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +3 * igt@kms_color@pipe-b-legacy-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_color@pipe-c-ctm-max: - shard-skl: PASS -> FAIL [fdo#108147] * igt@kms_cursor_crc@cursor-256x256-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-512x512-dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled: - shard-skl: PASS -> FAIL [fdo#108472] * igt@kms_flip@2x-nonexisting-fb: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +8 * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-badstride: - shard-skl: PASS -> FAIL [fdo#105682] +2 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +16 * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-skl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: PASS -> FAIL [fdo#103167] +2 * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - shard-skl: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-apl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +4 * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-c-tiling-y: - shard-apl:
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
Reviewed-By: Dale B Stimson
On Fri, Mar 01, 2019 at 08:19:19AM +, Chris Wilson wrote:
> Verify that our list of nonpriv registers exist and are writable.
>
> v2: TD_CTL has a write_mask of 0x instead of being a masked
> register.
>
> Signed-off-by: Chris Wilson
> Cc: Dale B Stimson
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> ---
> tests/i915/gem_ctx_isolation.c | 167 +++--
> 1 file changed, 138 insertions(+), 29 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 839d49ade..e50cc9a72 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -59,16 +59,23 @@ enum {
>
> static const struct named_register {
> const char *name;
> - unsigned int gen_mask;
> - unsigned int engine_mask;
> - uint32_t offset;
> + unsigned int gen_mask; /* on which gen the register exists */
> + unsigned int engine_mask; /* preferred engine / powerwell */
> + uint32_t offset; /* address of register, from bottom of mmio bar */
> uint32_t count;
> uint32_t ignore_bits;
> + uint32_t write_mask; /* some registers bits do not exist */
> bool masked;
> } nonpriv_registers[] = {
> { "NOPID", NOCTX, RCS0, 0x2094 },
> { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> + {
> + "INSTPM",
> + GEN6, RCS0, 0x20c0,
> + .ignore_bits = BIT(8) /* ro counter */,
> + .write_mask = BIT(8) /* rsvd varies between gen */,
> + .masked = true,
> + },
> { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> @@ -78,7 +85,7 @@ static const struct named_register {
> { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
> { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
> { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
> @@ -86,7 +93,7 @@ static const struct named_register {
> { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
> { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
> { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
> - { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
> + { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
> { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
> { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
> { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
> @@ -94,45 +101,45 @@ static const struct named_register {
> { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
> { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
> { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> - { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> + { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
> { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> { "OACTXID", GEN8, RCS0, 0x2364 },
> - { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
> + { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
> { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> - { "GT_MODE", GEN8, RCS0, 0x7008 },
> - { "L3_Config", GEN7, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400 },
> + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> + { "L3_Config", GEN8, RCS0, 0x7034 },
> + { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> { "TD_CTL2", GEN8, RCS0, 0xe404 },
> - { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
> - { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
> - { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
> - { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
> + { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> + { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> + { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> + { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
> { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
> { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
> { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
>
[Intel-gfx] [PATCH 4/5] drm/i915: Move rawclck, power_domain and irq un/initialization from modeset functions
The initialization of those componentes is required by the GEM/GT not only display so lets move then to a more the appropriate place. Cc: Lucas De Marchi Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 39 drivers/gpu/drm/i915/intel_display.c | 7 - 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index cc07259ec946..2b5ce764e694 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -691,24 +691,15 @@ static int i915_modeset_load(struct drm_device *dev) if (ret) goto cleanup_vga_client; - /* must happen before intel_power_domains_init_hw() on VLV/CHV */ - intel_update_rawclk(dev_priv); - - intel_power_domains_init_hw(dev_priv, false); - intel_csr_ucode_init(dev_priv); - ret = intel_irq_install(dev_priv); - if (ret) - goto cleanup_csr; - intel_setup_gmbus(dev_priv); /* Important: The output setup functions called by modeset_init need * working irqs for e.g. gmbus and dp aux transfers. */ ret = intel_modeset_init(dev); if (ret) - goto cleanup_irq; + goto cleanup_gmbus; ret = i915_gem_init(dev_priv); if (ret) @@ -736,12 +727,9 @@ static int i915_modeset_load(struct drm_device *dev) i915_gem_fini(dev_priv); cleanup_modeset: intel_modeset_cleanup(dev); -cleanup_irq: - drm_irq_uninstall(dev); +cleanup_gmbus: intel_teardown_gmbus(dev_priv); -cleanup_csr: intel_csr_ucode_fini(dev_priv); - intel_power_domains_fini_hw(dev_priv); vga_switcheroo_unregister_client(pdev); cleanup_vga_client: vga_client_register(pdev, NULL, NULL, NULL); @@ -1765,9 +1753,18 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) if (ret < 0) goto out_cleanup_mmio; + /* must happen before intel_power_domains_init_hw() on VLV/CHV */ + intel_update_rawclk(dev_priv); + + intel_power_domains_init_hw(dev_priv, false); + + ret = intel_irq_install(dev_priv); + if (ret) + goto out_cleanup_power; + ret = i915_modeset_load(_priv->drm); if (ret < 0) - goto out_cleanup_hw; + goto out_cleanup_irq; i915_driver_register(dev_priv); @@ -1777,7 +1774,10 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) return 0; -out_cleanup_hw: +out_cleanup_irq: + drm_irq_uninstall(_priv->drm); +out_cleanup_power: + intel_power_domains_fini_hw(dev_priv); i915_driver_cleanup_hw(dev_priv); out_cleanup_mmio: i915_driver_cleanup_mmio(dev_priv); @@ -1810,6 +1810,13 @@ void i915_driver_unload(struct drm_device *dev) intel_gvt_cleanup(dev_priv); + /* +* Interrupts and polling as the first thing to avoid creating havoc. +* Too much stuff here (turning of connectors, ...) would +* experience fancy races otherwise. +*/ + intel_irq_uninstall(dev_priv); + i915_modeset_unload(dev); /* Free error state after interrupts are fully disabled. */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7963348f1c64..5158e8ecb9ed 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -16364,13 +16364,6 @@ void intel_modeset_cleanup(struct drm_device *dev) flush_work(_priv->atomic_helper.free_work); WARN_ON(!llist_empty(_priv->atomic_helper.free_list)); - /* -* Interrupts and polling as the first thing to avoid creating havoc. -* Too much stuff here (turning of connectors, ...) would -* experience fancy races otherwise. -*/ - intel_irq_uninstall(dev_priv); - /* * Due to the hpd irq storm handling the hotplug work can re-arm the * poll handlers. Hence disable polling after hpd handling is shut down. -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Add a cleanup function for i915_modeset_load()
Lets make i915_driver_unload() easier to read by starting to move
components initialized by i915_modeset_load() to
i915_modeset_unload().
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 27 ++-
drivers/gpu/drm/i915/intel_display.c | 2 --
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90c77fab3d70..cc07259ec946 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -639,6 +639,23 @@ static const struct vga_switcheroo_client_ops
i915_switcheroo_ops = {
.can_switch = i915_switcheroo_can_switch,
};
+static void i915_modeset_unload(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct pci_dev *pdev = dev_priv->drm.pdev;
+
+ intel_modeset_cleanup(dev);
+
+ intel_teardown_gmbus(dev_priv);
+
+ intel_bios_cleanup(dev_priv);
+
+ vga_switcheroo_unregister_client(pdev);
+ vga_client_register(pdev, NULL, NULL, NULL);
+
+ intel_csr_ucode_fini(dev_priv);
+}
+
static int i915_modeset_load(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1778,7 +1795,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
void i915_driver_unload(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct pci_dev *pdev = dev_priv->drm.pdev;
disable_rpm_wakeref_asserts(dev_priv);
@@ -1794,14 +1810,7 @@ void i915_driver_unload(struct drm_device *dev)
intel_gvt_cleanup(dev_priv);
- intel_modeset_cleanup(dev);
-
- intel_bios_cleanup(dev_priv);
-
- vga_switcheroo_unregister_client(pdev);
- vga_client_register(pdev, NULL, NULL, NULL);
-
- intel_csr_ucode_fini(dev_priv);
+ i915_modeset_unload(dev);
/* Free error state after interrupts are fully disabled. */
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 91a8ee611b12..7963348f1c64 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16393,8 +16393,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
intel_overlay_cleanup(dev_priv);
- intel_teardown_gmbus(dev_priv);
-
destroy_workqueue(dev_priv->modeset_wq);
intel_fbc_cleanup_cfb(dev_priv);
--
2.21.0
___
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[Intel-gfx] [PATCH 1/5] drm/i915/vlv: Move czclk to intel_pm
Moving VLV/CHV/BYT czclk to intel_pm as it is a core clock used as
base by several other GPU blocks including GT.
BSpec: 14370
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 12
drivers/gpu/drm/i915/intel_pm.c | 10 ++
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7c5e84ef5171..91a8ee611b12 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -180,17 +180,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv,
dev_priv->hpll_freq);
}
-static void intel_update_czclk(struct drm_i915_private *dev_priv)
-{
- if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
- return;
-
- dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
- CCK_CZ_CLOCK_CONTROL);
-
- DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
-}
-
static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *pipe_config)
@@ -15533,7 +15522,6 @@ int intel_modeset_init(struct drm_device *dev)
intel_shared_dpll_init(dev);
intel_update_fdi_pll_freq(dev_priv);
- intel_update_czclk(dev_priv);
intel_modeset_init_hw(dev);
intel_hdcp_component_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9c97a95c1816..cd363fa47cbc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7622,6 +7622,14 @@ static void vlv_init_gpll_ref_freq(struct
drm_i915_private *dev_priv)
dev_priv->gt_pm.rps.gpll_ref_freq);
}
+static void vlv_update_czclk(struct drm_i915_private *dev_priv)
+{
+ dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
+ CCK_CZ_CLOCK_CONTROL);
+
+ DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
+}
+
static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = _priv->gt_pm.rps;
@@ -7629,6 +7637,7 @@ static void valleyview_init_gt_powersave(struct
drm_i915_private *dev_priv)
valleyview_setup_pctx(dev_priv);
+ vlv_update_czclk(dev_priv);
vlv_init_gpll_ref_freq(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
@@ -7675,6 +7684,7 @@ static void cherryview_init_gt_powersave(struct
drm_i915_private *dev_priv)
cherryview_setup_pctx(dev_priv);
+ vlv_update_czclk(dev_priv);
vlv_init_gpll_ref_freq(dev_priv);
mutex_lock(_priv->sb_lock);
--
2.21.0
___
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[Intel-gfx] [PATCH 2/5] drm/i915: Rename i915_load_modeset_init() to i915_modeset_load()
i915_load_modeset_init() sounds horrible also lets rename it so
the future cleanup function of it can be easially recognized.
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c08abdef5eb6..90c77fab3d70 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -639,7 +639,7 @@ static const struct vga_switcheroo_client_ops
i915_switcheroo_ops = {
.can_switch = i915_switcheroo_can_switch,
};
-static int i915_load_modeset_init(struct drm_device *dev)
+static int i915_modeset_load(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -1748,7 +1748,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret < 0)
goto out_cleanup_mmio;
- ret = i915_load_modeset_init(_priv->drm);
+ ret = i915_modeset_load(_priv->drm);
if (ret < 0)
goto out_cleanup_hw;
--
2.21.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Fix atomic state leak when resetting HDMI link
== Series Details == Series: series starting with [1/3] drm/i915: Fix atomic state leak when resetting HDMI link URL : https://patchwork.freedesktop.org/series/57452/ State : warning == Summary == $ dim checkpatch origin/drm-tip 154d2c0bce1b drm/i915: Fix atomic state leak when resetting HDMI link cc51bea3db6e drm/i915: Don't manually add connectors and planes state -:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #19: drm_atomic_add_affected_connectors() total: 0 errors, 1 warnings, 0 checks, 14 lines checked 43b6419ddc23 drm/i915: Forcing a modeset when resetting HDMI link ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Extract gem_init() from modeset_load()
modeset_load() is definally not the right place to initialize gem but
it is there because it should only be called after intel_mode_init()
as one of the tasks of this function is check if BIOS have already
allocated a framebuffer and if so reuse it to accomplish a smooth
boot transition.
So here it is spliting the loading into two functions and
initializing gem between those functions.
Also renaming i915_modeset_unload() to i915_modeset_begin_unload()
as so far it is only doing this job and this way it can be used in
the errors paths of i915_driver_load().
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 58 -
1 file changed, 35 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2b5ce764e694..f4163a8bb244 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -639,7 +639,7 @@ static const struct vga_switcheroo_client_ops
i915_switcheroo_ops = {
.can_switch = i915_switcheroo_can_switch,
};
-static void i915_modeset_unload(struct drm_device *dev)
+static void i915_modeset_begin_unload(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -656,7 +656,7 @@ static void i915_modeset_unload(struct drm_device *dev)
intel_csr_ucode_fini(dev_priv);
}
-static int i915_modeset_load(struct drm_device *dev)
+static int i915_modeset_begin_load(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -701,9 +701,22 @@ static int i915_modeset_load(struct drm_device *dev)
if (ret)
goto cleanup_gmbus;
- ret = i915_gem_init(dev_priv);
- if (ret)
- goto cleanup_modeset;
+ return 0;
+
+cleanup_gmbus:
+ intel_teardown_gmbus(dev_priv);
+ intel_csr_ucode_fini(dev_priv);
+ vga_switcheroo_unregister_client(pdev);
+cleanup_vga_client:
+ vga_client_register(pdev, NULL, NULL, NULL);
+out:
+ return ret;
+}
+
+static int i915_modeset_finish_load(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
intel_overlay_setup(dev_priv);
@@ -712,7 +725,7 @@ static int i915_modeset_load(struct drm_device *dev)
ret = intel_fbdev_init(dev);
if (ret)
- goto cleanup_gem;
+ return ret;
/* Only enable hotplug handling once the fbdev is fully set up. */
intel_hpd_init(dev_priv);
@@ -720,21 +733,6 @@ static int i915_modeset_load(struct drm_device *dev)
intel_init_ipc(dev_priv);
return 0;
-
-cleanup_gem:
- if (i915_gem_suspend(dev_priv))
- DRM_ERROR("failed to idle hardware; continuing to unload!\n");
- i915_gem_fini(dev_priv);
-cleanup_modeset:
- intel_modeset_cleanup(dev);
-cleanup_gmbus:
- intel_teardown_gmbus(dev_priv);
- intel_csr_ucode_fini(dev_priv);
- vga_switcheroo_unregister_client(pdev);
-cleanup_vga_client:
- vga_client_register(pdev, NULL, NULL, NULL);
-out:
- return ret;
}
static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
@@ -1762,10 +1760,18 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_power;
- ret = i915_modeset_load(_priv->drm);
+ ret = i915_modeset_begin_load(_priv->drm);
if (ret < 0)
goto out_cleanup_irq;
+ ret = i915_gem_init(dev_priv);
+ if (ret)
+ goto out_cleanup_modeset_begin_load;
+
+ ret = i915_modeset_finish_load(_priv->drm);
+ if (ret < 0)
+ goto out_cleanup_gem;
+
i915_driver_register(dev_priv);
enable_rpm_wakeref_asserts(dev_priv);
@@ -1774,6 +1780,12 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
return 0;
+out_cleanup_gem:
+ if (i915_gem_suspend(dev_priv))
+ DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+ i915_gem_fini(dev_priv);
+out_cleanup_modeset_begin_load:
+ i915_modeset_begin_unload(_priv->drm);
out_cleanup_irq:
drm_irq_uninstall(_priv->drm);
out_cleanup_power:
@@ -1817,7 +1829,7 @@ void i915_driver_unload(struct drm_device *dev)
*/
intel_irq_uninstall(dev_priv);
- i915_modeset_unload(dev);
+ i915_modeset_begin_unload(dev);
/* Free error state after interrupts are fully disabled. */
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
--
2.21.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix atomic state leak when resetting HDMI link (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix atomic state leak when
resetting HDMI link (rev2)
URL : https://patchwork.freedesktop.org/series/57318/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5682 -> Patchwork_12349
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57318/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_12349 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-ivb-3520m: NOTRUN -> SKIP [fdo#109271] +48
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: PASS -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: PASS -> SKIP [fdo#109271] +33
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (42 -> 40)
--
Additional (2): fi-icl-y fi-ivb-3520m
Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_5682 -> Patchwork_12349
CI_DRM_5682: e6481defd076c8507c8d5a503b2edd9c7a382ef7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12349: f6a63f57880dcfa00396a42b62b2f465ea56f2a3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f6a63f57880d drm/i915: Don't manually add connectors and planes state
cfc630b1ed47 drm/i915: Fix atomic state leak when resetting HDMI link
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12349/
___
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[Intel-gfx] [PATCH 1/3] drm/i915: Fix atomic state leak when resetting HDMI link
Atomic state needs to be put even if the commit was successful.
Fixes: dba14b27dd3c ("drm/i915: Reinitialize sink scrambling/TMDS clock ratio
on HPD")
Reviewed-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Lyude Paul
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_ddi.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d918be927fc2..34dd5823398a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3984,12 +3984,7 @@ static int modeset_pipe(struct drm_crtc *crtc,
goto out;
ret = drm_atomic_commit(state);
- if (ret)
- goto out;
-
- return 0;
-
- out:
+out:
drm_atomic_state_put(state);
return ret;
--
2.21.0
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[Intel-gfx] [PATCH 3/3] drm/i915: Forcing a modeset when resetting HDMI link
With fastboot enabled in gen9+ it broke the HDMI reset as just setting mode_changed to true causes a fastset and here we want a full modeset that will disable and then enable the encoder of this HDMI link actually, so setting connectors_changed instead that will cause modeset as desired. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c22ddde2dfc1..d329f0c206ec 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3973,7 +3973,7 @@ static int modeset_pipe(struct drm_crtc *crtc, goto out; } - crtc_state->mode_changed = true; + crtc_state->connectors_changed = true; ret = drm_atomic_commit(state); out: -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Don't manually add connectors and planes state
drm_atomic_commit() call chain already takes care of adding connectors and planes, so lets no add then manually if not changing their states. drm_atomic_commit() drm_atomic_check_only() config->funcs->atomic_check()/intel_atomic_check() drm_atomic_helper_check() drm_atomic_helper_check_modeset() for_each_oldnew_crtc_in_state() drm_atomic_add_affected_connectors() drm_atomic_add_affected_planes() Reviewed-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Lyude Paul Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 8 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 34dd5823398a..c22ddde2dfc1 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3975,14 +3975,6 @@ static int modeset_pipe(struct drm_crtc *crtc, crtc_state->mode_changed = true; - ret = drm_atomic_add_affected_connectors(state, crtc); - if (ret) - goto out; - - ret = drm_atomic_add_affected_planes(state, crtc); - if (ret) - goto out; - ret = drm_atomic_commit(state); out: drm_atomic_state_put(state); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/13] drm/i915: Don't pass crtc to intel_find_shared_dpll()
On Thu, Feb 7, 2019 at 9:32 AM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Passing both crtc and its state is redundant. Pass just the state.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
for the series.
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 0a42d11c4c33..1d1a2c456257 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -241,11 +241,11 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> }
>
> static struct intel_shared_dpll *
> -intel_find_shared_dpll(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> +intel_find_shared_dpll(struct intel_crtc_state *crtc_state,
>enum intel_dpll_id range_min,
>enum intel_dpll_id range_max)
> {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll, *unused_pll = NULL;
> struct intel_shared_dpll_state *shared_dpll;
> @@ -436,7 +436,7 @@ ibx_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> crtc->base.base.id, crtc->base.name,
> pll->info->name);
> } else {
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> + pll = intel_find_shared_dpll(crtc_state,
> DPLL_ID_PCH_PLL_A,
> DPLL_ID_PCH_PLL_B);
> }
> @@ -780,7 +780,7 @@ static struct intel_shared_dpll
> *hsw_ddi_hdmi_get_dpll(int clock,
>
> crtc_state->dpll_hw_state.wrpll = val;
>
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> + pll = intel_find_shared_dpll(crtc_state,
> DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
>
> if (!pll)
> @@ -840,7 +840,7 @@ hsw_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> crtc_state->dpll_hw_state.spll =
> SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
> SPLL_PLL_SSC;
>
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> + pll = intel_find_shared_dpll(crtc_state,
> DPLL_ID_SPLL, DPLL_ID_SPLL);
> } else {
> return NULL;
> @@ -1411,11 +1411,11 @@ skl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> }
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> + pll = intel_find_shared_dpll(crtc_state,
> DPLL_ID_SKL_DPLL0,
> DPLL_ID_SKL_DPLL0);
> else
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> + pll = intel_find_shared_dpll(crtc_state,
> DPLL_ID_SKL_DPLL1,
> DPLL_ID_SKL_DPLL3);
> if (!pll)
> @@ -2390,7 +2390,7 @@ cnl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> return NULL;
> }
>
> - pll = intel_find_shared_dpll(crtc, crtc_state,
> + pll = intel_find_shared_dpll(crtc_state,
> DPLL_ID_SKL_DPLL0,
> DPLL_ID_SKL_DPLL2);
> if (!pll) {
> @@ -2945,7 +2945,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
>
> crtc_state->dpll_hw_state = pll_state;
>
> - pll = intel_find_shared_dpll(crtc, crtc_state, min, max);
> + pll = intel_find_shared_dpll(crtc_state, min, max);
> if (!pll) {
> DRM_DEBUG_KMS("No PLL selected\n");
> return NULL;
> --
> 2.19.2
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't manually add connectors and planes state
On Fri, 2019-03-01 at 15:43 +0200, Ville Syrjälä wrote: > On Thu, Feb 28, 2019 at 09:27:48PM +, Souza, Jose wrote: > > On Thu, 2019-02-28 at 13:37 +0200, Ville Syrjälä wrote: > > > On Wed, Feb 27, 2019 at 03:04:08PM -0800, José Roberto de Souza > > > wrote: > > > > drm_atomic_commit() call chain already takes care of adding > > > > connectors and planes, so lets no add then manually if not > > > > changing > > > > their states. > > > > > > The specific callgraph would make review easier. > > > > Appending this to the commit message is enough? > > > > drm_atomic_commit() > > drm_atomic_check_only() > > config->funcs->atomic_check()/intel_atomic_check() > > drm_atomic_helper_check() > > drm_atomic_helper_check_modeset() > > for_each_oldnew_crtc_in_state() > > drm_atomic_add_affected > > _connectors() > > drm_atomic_add_affected > > _planes() > > Yes, that helps. Thanks. > > Reviewed-by: Ville Syrjälä > > Hmm. I wonder if fastboot has actually broken this code. Maybe we > need > to set connectors_changed instead of mode_changed to guarantee the > full > modeset... Just tested and you are right, sending a separated patch to fix this. > > > > > Cc: Ville Syrjälä > > > > Cc: Lyude Paul > > > > Signed-off-by: José Roberto de Souza > > > > --- > > > > drivers/gpu/drm/i915/intel_ddi.c | 8 > > > > 1 file changed, 8 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > > index 34dd5823398a..c22ddde2dfc1 100644 > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > > @@ -3975,14 +3975,6 @@ static int modeset_pipe(struct drm_crtc > > > > *crtc, > > > > > > > > crtc_state->mode_changed = true; > > > > > > > > - ret = drm_atomic_add_affected_connectors(state, crtc); > > > > - if (ret) > > > > - goto out; > > > > - > > > > - ret = drm_atomic_add_affected_planes(state, crtc); > > > > - if (ret) > > > > - goto out; > > > > - > > > > ret = drm_atomic_commit(state); > > > > out: > > > > drm_atomic_state_put(state); > > > > -- > > > > 2.21.0 > > signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [CI,1/4] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57434/ State : success == Summary == CI Bug Log - changes from CI_DRM_5679_full -> Patchwork_12347_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12347_full that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries_display_off: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@gem_ctx_isolation@rcs0-dirty-create: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +3 * igt@gem_ctx_param@invalid-param-set: - shard-skl: NOTRUN -> FAIL [fdo#109674] * igt@gem_exec_parallel@bsd1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +194 * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_schedule@preempt-other-chain-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +8 * igt@gem_mocs_settings@mocs-rc6-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] * igt@gem_mocs_settings@mocs-settings-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109287] +2 * igt@gem_pwrite@huge-gtt-forwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@gem_stolen@stolen-pread: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +2 * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_rpm@basic-pci-d3-state: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@gem-execbuf-stress: - shard-iclb: PASS -> INCOMPLETE [fdo#108840] * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108654] * igt@i915_pm_rpm@system-suspend-modeset: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +2 * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +3 * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16 - shard-iclb: NOTRUN -> SKIP [fdo#109278] +2 * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +3 * igt@kms_color@pipe-b-legacy-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-128x42-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-512x512-dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232] * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_flip@2x-nonexisting-fb: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +8 * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +16 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-apl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +4 * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-b-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] +2 * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: - shard-glk: PASS -> FAIL [fdo#103166] * igt@kms_plane_multiple@atomic-pipe-c-tiling-none: - shard-iclb: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-apl: NOTRUN -> FAIL [fdo#103166] * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724] +1 * igt@kms_psr@primary_mmap_cpu: - shard-apl: NOTRUN -> SKIP [fdo#109271] +9 * igt@kms_psr@psr2_dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109441] *
Re: [Intel-gfx] [PATCH 2/2] drm/i915: allow platforms without eDP transcoder
On Mon, Feb 25, 2019 at 06:17:13AM -0800, Mika Kahola wrote:
Looks allright.
On Fri, 2019-02-22 at 15:02 -0800, Lucas De Marchi wrote:
Define a HAS_TRANSCODER_EDP() macro that checks if we have defined an
offset for this transcoder. This allows platforms to be defined
without
eDP transcoder.
Cc: Mika Kahola
Cc: Imre Deak
Cc: Rodrigo Vivi
Reviewed-by: Mika Kahola
humn.. this depends on the first patch. Is this r-b for both?
Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
drivers/gpu/drm/i915/intel_display.c | 5 -
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index cc09caf3870e..a8e9f0cf20f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2519,6 +2519,7 @@ static inline unsigned int
i915_sg_segment_size(void)
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)-
>display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)-
>has_fpga_dbg)
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)-
>display.has_psr)
+#define HAS_TRANSCODER_EDP(dev_priv)(INTEL_INFO(dev_priv)-
>trans_offsets[TRANSCODER_EDP] != 0)
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)-
>has_rc6)
#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)-
>has_rc6p)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c
index ea83071a22c4..8eeffa027b74 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1911,7 +1911,7 @@ bool intel_ddi_connector_get_hw_state(struct
intel_connector *intel_connector)
goto out;
}
- if (port == PORT_A)
+ if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
cpu_transcoder = TRANSCODER_EDP;
else
cpu_transcoder = (enum transcoder) pipe;
@@ -1973,7 +1973,7 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
if (!(tmp & DDI_BUF_CTL_ENABLE))
goto out;
- if (port == PORT_A) {
+ if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
@@ -3856,7 +3856,7 @@ static int intel_ddi_compute_config(struct
intel_encoder *encoder,
enum port port = encoder->port;
int ret;
- if (port == PORT_A)
+ if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
pipe_config->cpu_transcoder = TRANSCODER_EDP;
if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9dfb99195144..8bf4bdf2006a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9688,7 +9688,7 @@ static bool hsw_get_transcoder_state(struct
intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum intel_display_power_domain power_domain;
- unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
+ unsigned long panel_transcoder_mask = 0;
unsigned long enabled_panel_transcoders = 0;
enum transcoder panel_transcoder;
u32 tmp;
@@ -9697,6 +9697,9 @@ static bool hsw_get_transcoder_state(struct
intel_crtc *crtc,
panel_transcoder_mask |=
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
+ if (HAS_TRANSCODER_EDP(dev_priv))
+ panel_transcoder_mask |= BIT(TRANSCODER_EDP);
+
/*
* The pipe->transcoder mapping is fixed with the exception of
the eDP
* and DSI transcoders handled below.
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [1/4] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57432/ State : success == Summary == CI Bug Log - changes from CI_DRM_5679_full -> Patchwork_12346_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12346_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-dirty-create: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +3 * igt@gem_ctx_param@invalid-param-set: - shard-skl: NOTRUN -> FAIL [fdo#109674] * igt@gem_exec_parallel@bsd1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +171 * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_schedule@preempt-other-chain-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +8 * igt@gem_mocs_settings@mocs-rc6-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] * igt@gem_mocs_settings@mocs-settings-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109287] +2 * igt@gem_pwrite@huge-gtt-forwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@gem_stolen@stolen-pread: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +2 * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_rpm@gem-execbuf-stress: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +5 * igt@i915_pm_rpm@i2c: - shard-iclb: PASS -> INCOMPLETE [fdo#108840] - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@kms_atomic_interruptible@universal-setplane-primary: - shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +3 * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +3 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-apl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15 - shard-iclb: NOTRUN -> SKIP [fdo#109278] +2 * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +3 * igt@kms_color@pipe-b-legacy-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_color@pipe-c-ctm-max: - shard-skl: PASS -> FAIL [fdo#108147] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_cursor_crc@cursor-512x512-dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-64x64-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] +3 * igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled: - shard-skl: PASS -> FAIL [fdo#108472] * igt@kms_flip@2x-nonexisting-fb: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +8 * igt@kms_flip@plain-flip-ts-check: - shard-skl: NOTRUN -> FAIL [fdo#100368] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: - shard-glk: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-skl: PASS -> FAIL [fdo#105682] +1 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +16 * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-skl: PASS -> FAIL [fdo#103167] +2 * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - shard-skl: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-apl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +4 * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: - shard-iclb: PASS -> FAIL [fdo#103166] +3 * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-glk: PASS -> FAIL [fdo#103166] *
Re: [Intel-gfx] [PATCH 15/17] drm/vc4: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Maarten Lankhorst writes:
> Convert vc4 to using __drm_atomic_helper_crtc_reset(), instead of
> writing its own version. Instead of open coding destroy_state(),
> call it directly for freeing the old state.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Eric Anholt
> ---
> drivers/gpu/drm/vc4/vc4_crtc.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
> index e7c04a9eb219..fdf21594b050 100644
> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
> @@ -1041,12 +1041,13 @@ static void vc4_crtc_destroy_state(struct drm_crtc
> *crtc,
> static void
> vc4_crtc_reset(struct drm_crtc *crtc)
> {
> - if (crtc->state)
> - vc4_crtc_destroy_state(crtc->state);
> + struct vc4_crtc_state *crtc_state =
> + kzalloc(sizeof(*crtc_state), GFP_KERNEL);
>
> - crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
> if (crtc->state)
> - crtc->state->crtc = crtc;
> + vc4_crtc_destroy_state(crtc, crtc->state);
> +
> + __drm_atomic_helper_crtc_reset(crtc, _state->base);
Wouldn't it be much easier if __drm_atomic_helper_crtc_reset took in a
new state and destroyed the old state for you? It seems like hardly a
helper as is.
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Re: [Intel-gfx] [PATCH 01/17] drm/vc4: Fix memory leak during gpu reset.
Maarten Lankhorst writes: > __drm_atomic_helper_crtc_destroy_state does not free memory, it only > cleans it up. Fix this by calling the functions own destroy function. Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC
On Fri, 2019-03-01 at 22:45 +0200, Ville Syrjälä wrote:
> On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza
> wrote:
> > When PSR2 is active aka after the number of frames programmed in
> > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
> > interruptions causing IGT tests to fail due timeout.
>
> I'm more concerned about the all ones (or was it all zeroes?) crc we
> get when coming back from PSR. But I don't remmber right now if that
> was limited PSR2 or if it happens with PSR1 as well. Have you looked
> at that issue as well?
Just wrote a test that gets 500 CRCs and the real difference between
PSR1 and PSR2 is that PSR1 activation is blocked after the pipe CRC is
enabled while on PSR2 that don't happen.
After exit PSR2 I got more 4 CRC interruptions, 1 invalid value and 3
valid ones.
Got the results above in a WHL and ICL.
>
> > Oddly that don't happen when PSR1 active, so here it switches from
> > PSR2 to PSR1 while user is requesting pipe CRC.
> >
> > Force setting mode_changed as true is necessary to atomic checks
> > functions compute new PSR state, that is why it was added to
> > intel_crtc_crc_prepare().
> >
> > v3: Reusing intel_crtc_crc_prepare() and crc_enabled
> >
> > v2: Changed commit description to describe that PSR2 inhibit CRC
> > calculations.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
> > drivers/gpu/drm/i915/intel_psr.c | 3 +++
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > index f6d0b2aaffe2..e7ac24c33650 100644
> > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private
> > *dev_priv, struct drm_crtc *crtc,
> > goto put_state;
> > }
> >
> > + pipe_config->base.mode_changed = pipe_config->crc_enabled !=
> > enable;
> > pipe_config->crc_enabled = enable;
> >
> > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) {
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 6175b1d2e0c8..f7730b8b2ec0 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > return false;
> > }
> >
> > + if (crtc_state->crc_enabled)
> > + return false;
> > +
> > return true;
> > }
> >
> > --
> > 2.21.0
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Re: [Intel-gfx] [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC
On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza wrote:
> When PSR2 is active aka after the number of frames programmed in
> PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
> interruptions causing IGT tests to fail due timeout.
I'm more concerned about the all ones (or was it all zeroes?) crc we
get when coming back from PSR. But I don't remmber right now if that
was limited PSR2 or if it happens with PSR1 as well. Have you looked
at that issue as well?
>
> Oddly that don't happen when PSR1 active, so here it switches from
> PSR2 to PSR1 while user is requesting pipe CRC.
>
> Force setting mode_changed as true is necessary to atomic checks
> functions compute new PSR state, that is why it was added to
> intel_crtc_crc_prepare().
>
> v3: Reusing intel_crtc_crc_prepare() and crc_enabled
>
> v2: Changed commit description to describe that PSR2 inhibit CRC
> calculations.
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index f6d0b2aaffe2..e7ac24c33650 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private *dev_priv,
> struct drm_crtc *crtc,
> goto put_state;
> }
>
> + pipe_config->base.mode_changed = pipe_config->crc_enabled != enable;
> pipe_config->crc_enabled = enable;
>
> if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 6175b1d2e0c8..f7730b8b2ec0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> + if (crtc_state->crc_enabled)
> + return false;
> +
> return true;
> }
>
> --
> 2.21.0
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC
On Fri, 2019-03-01 at 12:12 -0800, Dhinakaran Pandiyan wrote:
> On Wed, 2019-02-27 at 17:32 -0800, José Roberto de Souza wrote:
> > When PSR2 is active aka after the number of frames programmed in
> > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
> > interruptions causing IGT tests to fail due timeout.
>
> Just to make sure we are documenting the issue correctly in the
> commit
> message - is it the SU state when CRC generation stops or deep sleep?
'Frames Before SU Entry' is the number of frames to activate PSR2, so
it stops as soons as PSR2 is active.
>
> -DK
> > Oddly that don't happen when PSR1 active, so here it switches from
> > PSR2 to PSR1 while user is requesting pipe CRC.
> >
> > Force setting mode_changed as true is necessary to atomic checks
> > functions compute new PSR state, that is why it was added to
> > intel_crtc_crc_prepare().
> >
> > v3: Reusing intel_crtc_crc_prepare() and crc_enabled
> >
> > v2: Changed commit description to describe that PSR2 inhibit CRC
> > calculations.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
> > drivers/gpu/drm/i915/intel_psr.c | 3 +++
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > index f6d0b2aaffe2..e7ac24c33650 100644
> > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private
> > *dev_priv, struct drm_crtc *crtc,
> > goto put_state;
> > }
> >
> > + pipe_config->base.mode_changed = pipe_config->crc_enabled !=
> > enable;
> > pipe_config->crc_enabled = enable;
> >
> > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) {
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 6175b1d2e0c8..f7730b8b2ec0 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > return false;
> > }
> >
> > + if (crtc_state->crc_enabled)
> > + return false;
> > +
> > return true;
> > }
> >
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Re: [Intel-gfx] [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC
On Wed, 2019-02-27 at 17:32 -0800, José Roberto de Souza wrote:
> When PSR2 is active aka after the number of frames programmed in
> PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
> interruptions causing IGT tests to fail due timeout.
Just to make sure we are documenting the issue correctly in the commit
message - is it the SU state when CRC generation stops or deep sleep?
-DK
>
> Oddly that don't happen when PSR1 active, so here it switches from
> PSR2 to PSR1 while user is requesting pipe CRC.
>
> Force setting mode_changed as true is necessary to atomic checks
> functions compute new PSR state, that is why it was added to
> intel_crtc_crc_prepare().
>
> v3: Reusing intel_crtc_crc_prepare() and crc_enabled
>
> v2: Changed commit description to describe that PSR2 inhibit CRC
> calculations.
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index f6d0b2aaffe2..e7ac24c33650 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private
> *dev_priv, struct drm_crtc *crtc,
> goto put_state;
> }
>
> + pipe_config->base.mode_changed = pipe_config->crc_enabled !=
> enable;
> pipe_config->crc_enabled = enable;
>
> if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 6175b1d2e0c8..f7730b8b2ec0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> + if (crtc_state->crc_enabled)
> + return false;
> +
> return true;
> }
>
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Check that whitelisted registers are accessible (rev7)
== Series Details == Series: drm/i915/selftests: Check that whitelisted registers are accessible (rev7) URL : https://patchwork.freedesktop.org/series/57342/ State : success == Summary == CI Bug Log - changes from CI_DRM_5677_full -> Patchwork_12345_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12345_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_cs_tlb@bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +3 * igt@gem_pread@stolen-uncached: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +37 * igt@gem_pwrite@huge-gtt-forwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@gem_stolen@stolen-pread: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@gen3_render_mixed_blits: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@i915_pm_rpm@cursor-dpms: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3 * igt@i915_pm_rpm@gem-evict-pwrite: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@sysfs-read: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724] +1 * igt@kms_atomic_transition@4x-modeset-transitions-nonblocking: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-newfb-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-snb: NOTRUN -> DMESG-WARN [fdo#107956] - shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_color@pipe-a-ctm-max: - shard-apl: PASS -> FAIL [fdo#108147] * igt@kms_color@pipe-c-ctm-max: - shard-skl: PASS -> FAIL [fdo#108147] * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: PASS -> FAIL [fdo#105767] * igt@kms_fbcon_fbt@fbc-suspend: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-flip-vs-wf_vblank: - shard-iclb: NOTRUN -> SKIP [fdo#109274] * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: PASS -> FAIL [fdo#103060] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: - shard-glk: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-snb: NOTRUN -> SKIP [fdo#109271] +74 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +5 * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt: - shard-skl: NOTRUN -> FAIL [fdo#105682] * igt@kms_plane@pixel-format-pipe-b-planes: - shard-apl: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7 - shard-skl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-iclb: PASS -> FAIL [fdo#103166] * igt@kms_psr@psr2_dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109441] * igt@kms_setmode@basic: - shard-kbl: PASS -> FAIL [fdo#99912] * igt@kms_vrr@flip-suspend: - shard-skl: NOTRUN -> SKIP [fdo#109271] +52 * igt@prime_nv_api@i915_nv_import_vs_close: - shard-apl: NOTRUN -> SKIP [fdo#109271] +20 * igt@prime_vgem@fence-write-hang: - shard-iclb: NOTRUN -> SKIP [fdo#109295] * igt@sw_sync@sync_busy_fork: - shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133] Possible fixes * igt@i915_pm_rpm@debugfs-read: - shard-iclb: INCOMPLETE [fdo#108840] -> PASS * igt@i915_pm_rpm@dpms-lpsp: - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +2 * igt@i915_selftest@live_workarounds: - shard-iclb: DMESG-FAIL [fdo#108954] -> PASS * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-iclb: DMESG-WARN [fdo#107956] -> PASS * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: - shard-glk: FAIL [fdo#108145] -> PASS * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: FAIL [fdo#103232] -> PASS +4 *
Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/crc: Make IPS workaround generic
On Thu, 2019-02-28 at 17:14 -0800, Souza, Jose wrote:
> On Thu, 2019-02-28 at 17:06 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2019-02-28 at 15:26 -0800, Souza, Jose wrote:
> > > On Thu, 2019-02-28 at 18:56 +0200, Ville Syrjälä wrote:
> > > > On Wed, Feb 27, 2019 at 05:32:57PM -0800, José Roberto de Souza
> > > > wrote:
> > > > > Other features like PSR2 also needs to be disabled while
> > > > > getting
> > > > > CRC
> > > > > so lets rename ips_force_disable to crc_enabled, drop all
> > > > > this
> > > > > checks
> > > > > for pipe A and HSW and BDW and make it generic and
> > > > > hsw_compute_ips_config() will take care of all the checks
> > > > > removed
> > > > > from here.
> > > > >
> > > > > Cc: Dhinakaran Pandiyan
> > > > > Cc: Ville Syrjälä
> > > > > Signed-off-by: José Roberto de Souza
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_display.c | 10 +--
> > > > > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 42 +
> > > > >
> > > > > --
> > > > > 3 files changed, 24 insertions(+), 31 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > > index 816e8f124b3b..328967c642b3 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > > @@ -6751,7 +6751,13 @@ static bool
> > > > > hsw_compute_ips_config(struct
> > > > > intel_crtc_state *crtc_state)
> > > > > if (!hsw_crtc_state_ips_capable(crtc_state))
> > > > > return false;
> > > > >
> > > > > - if (crtc_state->ips_force_disable)
> > > > > + /*
> > > > > + * When IPS gets enabled, the pipe CRC changes. Since
> > > > > IPS gets
> > > > > + * enabled and disabled dynamically based on package C
> > > > > states,
> > > > > + * user space can't make reliable use of the CRCs, so
> > > > > let's
> > > > > just
> > > > > + * completely disable it.
> > > > > + */
> > > > > + if (crtc_state->crc_enabled)
> > > > > return false;
> > > >
> > > > Hmm. I was wondering how we even manage to pass the state
> > > > checker
> > > > with
> > > > the current code. But apparently we don't have state checking
> > > > for
> > > > IPS.
> > > > I would suggest moving this into hsw_compute_ips_config() and
> > > > then
> > > > adding the state checker (for HSW only though since BDW can't
> > > > do
> > > > the
> > > > readout).
> > > >
> > > > >
> > > > > /* IPS should be fine as long as at least one plane is
> > > > > enabled.
> > > > > */
> > > > > @@ -11684,7 +11690,7 @@ clear_intel_crtc_state(struct
> > > > > intel_crtc_state *crtc_state)
> > > > > saved_state->shared_dpll = crtc_state->shared_dpll;
> > > > > saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> > > > > saved_state->pch_pfit.force_thru = crtc_state-
> > > > > > pch_pfit.force_thru;
> > > > >
> > > > > - saved_state->ips_force_disable = crtc_state-
> > > > > > ips_force_disable;
> > > > >
> > > > > + saved_state->crc_enabled = crtc_state->crc_enabled;
> > > > > if (IS_G4X(dev_priv) ||
> > > > > IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > > > saved_state->wm = crtc_state->wm;
> > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > > index 5412373e2f98..2be64529e4a2 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > > @@ -999,7 +999,8 @@ struct intel_crtc_state {
> > > > > struct intel_link_m_n fdi_m_n;
> > > > >
> > > > > bool ips_enabled;
> > > > > - bool ips_force_disable;
> > > > > +
> > > > > + bool crc_enabled;
> > > > >
> > > > > bool enable_fbc;
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > > index 53d4ec68d3c4..f6d0b2aaffe2 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > > @@ -280,11 +280,12 @@ static int ilk_pipe_crc_ctl_reg(enum
> > > > > intel_pipe_crc_source *source,
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -static void hsw_pipe_A_crc_wa(struct drm_i915_private
> > > > > *dev_priv,
> > > > > - bool enable)
> > > > > +static void
> > > > > +intel_crtc_crc_prepare(struct drm_i915_private *dev_priv,
> > > > > struct
> > > > > drm_crtc *crtc,
> > > >
> > > > Just pass in the intel_crtc
> > >
> > > Okay
> > >
> > > > > +bool enable)
> > > > > {
> > > > > struct drm_device *dev = _priv->drm;
> > > > > - struct intel_crtc *crtc =
> > > > > intel_get_crtc_for_pipe(dev_priv,
> > > > > PIPE_A);
> > > > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > >
> > > > and then we don't have to have an ugly name for this.
>
Re: [Intel-gfx] [PATCH 23/38] drm/i915: Re-arrange execbuf so context is known before engine
Quoting Tvrtko Ursulin (2019-03-01 15:33:50) > > On 01/03/2019 14:03, Chris Wilson wrote: > > From: Tvrtko Ursulin > > > > Needed for a following patch. > > > > Signed-off-by: Tvrtko Ursulin > > I'll do yours, you do mine. Criss-cross. Now that's an oldend but golden > reference. :) Reviewed-by: Chris Wilson Must remember to s-o-b, or at least check that dim checks it this time. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/38] drm/i915: Extend CONTEXT_CREATE to set parameters upon construction
Quoting Tvrtko Ursulin (2019-03-01 16:36:45)
>
> On 01/03/2019 14:03, Chris Wilson wrote:
> > It can be useful to have a single ioctl to create a context with all
> > the initial parameters instead of a series of create + setparam + setparam
> > ioctls. This extension to create context allows any of the parameters
> > to be passed in as a linked list to be applied to the newly constructed
> > context.
> >
> > v2: Make a local copy of user setparam (Tvrtko)
> > v3: Use flags to detect availability of extension interface
>
> Looks good to me.
>
> Why have you changed to use flags and not just check the extension field
> being non-null?
Hmm. I was thinking about how new userspace would use it on an old kernel.
As the extension is in a new bit of the extension struct that won't be
passed to the old ioctl, and so it would create a context and not report
any error despite not processing the extensions (userspace would be none
the wiser that the context was invalid). So a simple answer was to use
the flags field to indicate that we want the extension processed; the
old kernel would reject the ioctl due to pad!=0, a new kernel will be
happy. New userspace on old kernel can then fallback gracefully.
+uint32_t
+brw_clone_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id)
+{
+ struct drm_i915_gem_context_create_ext_clone ext_clone = {
+ .base = { I915_CONTEXT_CREATE_EXT_CLONE },
+ .clone = ctx_id,
+ .flags = ~I915_CONTEXT_CLONE_UNKNOWN,
+ };
+ struct drm_i915_gem_context_create_ext arg = {
+ .flags = I915_CONTEXT_CREATE_USE_EXTENSIONS,
+ .extensions = (uintptr_t)_clone
+ };
+ if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, ) == 0)
+ return arg.ctx_id;
+
+ return __brw_clone_hw_context(bufmgr, ctx_id);
+}
-Chris
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Re: [Intel-gfx] [PATCH 16/38] drm/i915: Introduce a context barrier callback
Quoting Tvrtko Ursulin (2019-03-01 16:12:33)
>
> On 01/03/2019 14:03, Chris Wilson wrote:
> > + counter = 0;
> > + err = context_barrier_task(ctx, 0, mock_barrier_task, );
> > + if (err) {
> > + pr_err("Failed at line %d, err=%d\n", __LINE__, err);
> > + goto out;
> > + }
> > + if (counter == 0) {
> > + pr_err("Did not retire immediately with 0 engines\n");
> > + err = -EINVAL;
> > + goto out;
> > + }
> > +
> > + counter = 0;
> > + err = context_barrier_task(ctx, -1, mock_barrier_task, );
> > + if (err) {
> > + pr_err("Failed at line %d, err=%d\n", __LINE__, err);
> > + goto out;
> > + }
> > + if (counter == 0) {
> > + pr_err("Did not retire immediately for all inactive
> > engines\n");
>
> Why would this one retire immediately? It will send requests down the
> pipe, no? So don't you actually need to wait for the tracker to be
> signalled and that counter == num_engines?
Nothing has used the context at this point, so we don't emit a request
on any engine, and the barrier can be immediately executed.
> > + err = -EINVAL;
> > + goto out;
> > + }
> > +
> > + rq = ERR_PTR(-ENODEV);
> > + with_intel_runtime_pm(i915, wakeref)
> > + rq = i915_request_alloc(i915->engine[RCS], ctx);
> > + if (IS_ERR(rq)) {
> > + pr_err("Request allocation failed!\n");
> > + goto out;
> > + }
> > + i915_request_add(rq);
>
> Doesn't this need to go under the wakeref as well?
No, we only need the wakeref to start (that's only to avoid blocking
inside request_alloc --- yeah, that's not exactly how it works, we'll be
back later to fix that!). The request then carries the GT wakeref with it.
> > + GEM_BUG_ON(list_empty(>active_engines));
> > +
> > + counter = 0;
> > + context_barrier_inject_fault = BIT(RCS);
> > + err = context_barrier_task(ctx, -1, mock_barrier_task, );
> > + context_barrier_inject_fault = 0;
> > + if (err == -ENXIO)
> > + err = 0;
> > + else
> > + pr_err("Did not hit fault injection!\n");
> > + if (counter != 0) {
> > + pr_err("Invoked callback on error!\n");
> > + err = -EIO;
> > + }
> > + if (err)
> > + goto out;
> > +
> > + counter = 0;
> > + err = context_barrier_task(ctx, -1, mock_barrier_task, );
> > + if (err) {
> > + pr_err("Failed at line %d, err=%d\n", __LINE__, err);
> > + goto out;
> > + }
> > + mock_device_flush(i915);
> > + if (counter == 0) {
> > + pr_err("Did not retire on each active engines\n");
> > + err = -EINVAL;
> > + goto out;
> > + }
>
> This one is inline with my understanding, and the context_barrier_task
> arguments are the same as the one above.. hm.. I am confused.
This time it is active, so we actually have to wait as the barrier waits
for the GPU before firing.
-Chris
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Re: [Intel-gfx] [PATCH 14/38] drm/i915: Introduce the i915_user_extension_method
Quoting Tvrtko Ursulin (2019-03-01 15:39:13)
>
> On 01/03/2019 14:03, Chris Wilson wrote:
> > +int i915_user_extensions(struct i915_user_extension __user *ext,
> > + const i915_user_extension_fn *tbl,
> > + unsigned long count,
> > + void *data)
> > +{
> > + unsigned int stackdepth = 512;
> > +
> > + while (ext) {
> > + int err;
> > + u64 x;
> > +
> > + if (!stackdepth--) /* recursion vs useful flexibility */
> > + return -EINVAL;
>
> I don't get this. What stack? Did you mean "static unsigned int
> stackdepth" in case someone puts i915_user_extension into the extension
> table? Or just a limit on number of chained extensions? But you are not
> processing the recursively here.
It's iterative recursion :)
I still think of this loop in terms of its simple tail recursion.
And if we need to individual levels for unwind, that is a manual stack.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Yet another if/else sort of newer to older platforms. (rev3)
== Series Details == Series: drm/i915: Yet another if/else sort of newer to older platforms. (rev3) URL : https://patchwork.freedesktop.org/series/57112/ State : success == Summary == CI Bug Log - changes from CI_DRM_5679 -> Patchwork_12348 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57112/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_12348 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-kbl-7560u: PASS -> INCOMPLETE [fdo#103665] * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@kms_busy@basic-flip-c: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] Possible fixes * igt@i915_pm_rpm@basic-pci-d3-state: - fi-hsw-4770:SKIP [fdo#109271] -> PASS +4 * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: SKIP [fdo#109271] / [fdo#109278] -> PASS +2 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (42 -> 39) -- Additional (1): fi-pnv-d510 Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u Build changes - * Linux: CI_DRM_5679 -> Patchwork_12348 CI_DRM_5679: e533152feeb49f1dc4e689a37c415a997e5d094b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12348: 63d3527df83a02100affd17e78cb1690c21b71aa @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 63d3527df83a drm/i915: Yet another if/else sort of newer to older platforms. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12348/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/crc: Make IPS workaround generic
On Fri, 2019-03-01 at 15:35 +0200, Ville Syrjälä wrote:
> On Thu, Feb 28, 2019 at 11:26:57PM +, Souza, Jose wrote:
> > On Thu, 2019-02-28 at 18:56 +0200, Ville Syrjälä wrote:
> > > On Wed, Feb 27, 2019 at 05:32:57PM -0800, José Roberto de Souza
> > > wrote:
> > > > Other features like PSR2 also needs to be disabled while
> > > > getting
> > > > CRC
> > > > so lets rename ips_force_disable to crc_enabled, drop all this
> > > > checks
> > > > for pipe A and HSW and BDW and make it generic and
> > > > hsw_compute_ips_config() will take care of all the checks
> > > > removed
> > > > from here.
> > > >
> > > > Cc: Dhinakaran Pandiyan
> > > > Cc: Ville Syrjälä
> > > > Signed-off-by: José Roberto de Souza
> > > > ---
> > > > drivers/gpu/drm/i915/intel_display.c | 10 +--
> > > > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 42 +
> > > >
> > > > --
> > > > 3 files changed, 24 insertions(+), 31 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index 816e8f124b3b..328967c642b3 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -6751,7 +6751,13 @@ static bool
> > > > hsw_compute_ips_config(struct
> > > > intel_crtc_state *crtc_state)
> > > > if (!hsw_crtc_state_ips_capable(crtc_state))
> > > > return false;
> > > >
> > > > - if (crtc_state->ips_force_disable)
> > > > + /*
> > > > +* When IPS gets enabled, the pipe CRC changes. Since
> > > > IPS gets
> > > > +* enabled and disabled dynamically based on package C
> > > > states,
> > > > +* user space can't make reliable use of the CRCs, so
> > > > let's
> > > > just
> > > > +* completely disable it.
> > > > +*/
> > > > + if (crtc_state->crc_enabled)
> > > > return false;
> > >
> > > Hmm. I was wondering how we even manage to pass the state checker
> > > with
> > > the current code. But apparently we don't have state checking for
> > > IPS.
> > > I would suggest moving this into hsw_compute_ips_config() and
> > > then
> > > adding the state checker (for HSW only though since BDW can't do
> > > the
> > > readout).
> > >
> > > >
> > > > /* IPS should be fine as long as at least one plane is
> > > > enabled.
> > > > */
> > > > @@ -11684,7 +11690,7 @@ clear_intel_crtc_state(struct
> > > > intel_crtc_state *crtc_state)
> > > > saved_state->shared_dpll = crtc_state->shared_dpll;
> > > > saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> > > > saved_state->pch_pfit.force_thru = crtc_state-
> > > > > pch_pfit.force_thru;
> > > > - saved_state->ips_force_disable = crtc_state-
> > > > >ips_force_disable;
> > > > + saved_state->crc_enabled = crtc_state->crc_enabled;
> > > > if (IS_G4X(dev_priv) ||
> > > > IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > > saved_state->wm = crtc_state->wm;
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index 5412373e2f98..2be64529e4a2 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -999,7 +999,8 @@ struct intel_crtc_state {
> > > > struct intel_link_m_n fdi_m_n;
> > > >
> > > > bool ips_enabled;
> > > > - bool ips_force_disable;
> > > > +
> > > > + bool crc_enabled;
> > > >
> > > > bool enable_fbc;
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > index 53d4ec68d3c4..f6d0b2aaffe2 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > > @@ -280,11 +280,12 @@ static int ilk_pipe_crc_ctl_reg(enum
> > > > intel_pipe_crc_source *source,
> > > > return 0;
> > > > }
> > > >
> > > > -static void hsw_pipe_A_crc_wa(struct drm_i915_private
> > > > *dev_priv,
> > > > - bool enable)
> > > > +static void
> > > > +intel_crtc_crc_prepare(struct drm_i915_private *dev_priv,
> > > > struct
> > > > drm_crtc *crtc,
> > >
> > > Just pass in the intel_crtc
> >
> > Okay
> >
> > > > + bool enable)
> > > > {
> > > > struct drm_device *dev = _priv->drm;
> > > > - struct intel_crtc *crtc =
> > > > intel_get_crtc_for_pipe(dev_priv,
> > > > PIPE_A);
> > > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > >
> > > and then we don't have to have an ugly name for this.
> > >
> > > Also pasing in dev_priv is redundant when you're already passing
> > > in
> > > the
> > > crtc.
> > >
> >
> > okay
> >
> > > The function name isn't super descriptive. It makes me think
> > > we're
> > > preparing for CRC capture, when in fact it just adds/removes the
> > >
Re: [Intel-gfx] [PATCH xf86-video-intel] sna: Switch back to hwcursor on the next cursor update
Quoting Ville Syrjälä (2018-10-19 21:41:05) > On Fri, Oct 19, 2018 at 09:08:15PM +0100, Chris Wilson wrote: > > Quoting Ville Syrjala (2018-10-19 17:55:02) > > > From: Ville Syrjälä > > > > > > Once we've switched to using the swcursor (possibly > > > due to the cursor ioctl failing) we currently keep > > > using the swcursor until the modeset. > > > > > > That's not particularly great as the swcursor has several > > > issues. Apart from the (presumably expected) flicker, > > > the cursor also tends to leave horrible trails behind > > > around dri2/3 windows (happens with tearfree at least). > > > > > > To avoid some of that let's try to switch back to the hwcursor > > > a bit sooner. We can do that neatly via the convenient swcursor > > > block handler. > > > > Ok, so that forces the sw cursor to be switched off on the very next > > xf86CursorSetCursor() after being enabled. If the HWCursor fails, the > > cursor should be invisible until the next block handler. Won't that > > cause the cursor to flicker even more? Hmm, except that the swcursor > > should be restored within a frame. So more or less simply doubling the > > work of using swcursor? (Probably not actually, since swcursor is > > effectively an undo and paint every time and now we just make those two > > distinct steps) Certainly achieves the goal of forcing HW cursor back on > > at the earliest opportunity. > > > > I think I have just argued that this doesn't actually impact on swcursor > > rendering, just extends the loop. > > Hmm. I didn't fully consider what happens when we try to switch back. > So first the old swscursor gets cleared out, then we try to turn on > the hwcursor, and if that still fails we eventually render the new > swcursor? Right, so I guess this just adds a bit of a delay between > the two steps. > > My intial thought was to use a timer, but then I realized that I > can just stick it into the block handler while still avoiding any > recursion horrors. Yup, works nicely and even better with your - enable_fb_access(scrn, FALSE); - enable_fb_access(scrn, TRUE); + xf86CursorResetCursor(scrn->pScreen); improvement! > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=106935 > > > Signed-off-by: Ville Syrjälä > > > > Tentative > > Reviewed-by: Chris Wilson > > I think I would like to review the impact on swcursor a bit more, > > FAIL_CURSOR_IOCTL be my friend. > > Sure. Maybe you can even figure out why we get those dirt trails ;) Mumble, mumble, mumble (faking copy area around DRI2CopyRegion). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [CI,1/4] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57434/ State : success == Summary == CI Bug Log - changes from CI_DRM_5679 -> Patchwork_12347 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57434/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12347 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@kms_busy@basic-flip-b: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_busy@basic-flip-c: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] Possible fixes * igt@i915_pm_rpm@basic-pci-d3-state: - fi-hsw-4770:SKIP [fdo#109271] -> PASS +4 * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: SKIP [fdo#109271] / [fdo#109278] -> PASS +2 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (42 -> 39) -- Additional (1): fi-pnv-d510 Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u Build changes - * Linux: CI_DRM_5679 -> Patchwork_12347 CI_DRM_5679: e533152feeb49f1dc4e689a37c415a997e5d094b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12347: 293b3c3d08c2529728aa7aeea139af325d6f945a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 293b3c3d08c2 drm/i915: Prioritise non-busywait semaphore workloads 44a508029dd9 drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ 0ee004ae9f8d drm/i915: Keep timeline HWSP allocated until idle across the system 81a0b2f4e32f drm/i915/execlists: Suppress redundant preemption == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12347/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/execlists: Suppress redundant preemption
== Series Details ==
Series: series starting with [1/4] drm/i915/execlists: Suppress redundant
preemption
URL : https://patchwork.freedesktop.org/series/57432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5679 -> Patchwork_12346
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57432/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12346 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#107139]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] /
[fdo#109799]
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770:SKIP [fdo#109271] -> PASS +4
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: SKIP [fdo#109271] / [fdo#109278] -> PASS +2
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#109799]: https://bugs.freedesktop.org/show_bug.cgi?id=109799
Participating hosts (42 -> 39)
--
Additional (2): fi-icl-y fi-pnv-d510
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan
Build changes
-
* Linux: CI_DRM_5679 -> Patchwork_12346
CI_DRM_5679: e533152feeb49f1dc4e689a37c415a997e5d094b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12346: 21928151c3fa7bfafedc62e719a91b7665d9f82c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
21928151c3fa drm/i915: Prioritise non-busywait semaphore workloads
104ad573f689 drm/i915: Use HW semaphores for inter-engine synchronisation on
gen8+
a4845dc1e901 drm/i915: Keep timeline HWSP allocated until idle across the system
4fadbc8c11d3 drm/i915/execlists: Suppress redundant preemption
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12346/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [CI,1/4] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57434/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Suppress redundant preemption Okay! Commit: drm/i915: Keep timeline HWSP allocated until idle across the system Okay! Commit: drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ -O:drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) Commit: drm/i915: Prioritise non-busywait semaphore workloads Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/38] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [01/38] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57427/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5676_full -> Patchwork_12343_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12343_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12343_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12343_full: ### IGT changes ### Possible regressions * igt@gem_busy@extended-blt: - shard-glk: PASS -> FAIL +7 - shard-snb: PASS -> FAIL +3 * igt@gem_busy@extended-parallel-bsd: - shard-iclb: PASS -> FAIL +7 - shard-skl: NOTRUN -> FAIL * igt@gem_busy@extended-parallel-bsd2: - shard-kbl: PASS -> FAIL +9 * igt@gem_busy@extended-parallel-vebox: - shard-apl: PASS -> FAIL +7 - shard-skl: PASS -> FAIL +2 - shard-hsw: NOTRUN -> FAIL * igt@gem_busy@extended-render: - shard-hsw: PASS -> FAIL +6 * igt@gem_busy@extended-semaphore-render: - shard-iclb: NOTRUN -> FAIL Warnings * igt@gem_busy@extended-semaphore-blt: - shard-iclb: SKIP [fdo#109275] -> FAIL +2 - shard-kbl: SKIP [fdo#109271] -> FAIL +5 - shard-glk: SKIP [fdo#109271] -> FAIL +3 * igt@gem_busy@extended-semaphore-vebox: - shard-apl: SKIP [fdo#109271] -> FAIL +3 - shard-skl: SKIP [fdo#109271] -> FAIL +3 Known issues Here are the changes found in Patchwork_12343_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-parallel-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +4 * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_store@pages-bsd1: - shard-apl: NOTRUN -> SKIP [fdo#109271] +17 * igt@gem_mocs_settings@mocs-reset-ctx-dirty-render: - shard-iclb: NOTRUN -> SKIP [fdo#109287] * igt@gem_pread@stolen-display: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] * igt@i915_pm_rpm@system-suspend-devices: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@kms_atomic_transition@4x-modeset-transitions: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-snb: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-iclb: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10 * igt@kms_busy@extended-pageflip-hang-oldfb-render-f: - shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-hsw: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_color@pipe-b-legacy-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-iclb: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-64x64-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] +3 * igt@kms_cursor_crc@cursor-64x64-sliding: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +3 * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: PASS -> FAIL [fdo#105767] * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@basic-flip-vs-dpms: - shard-hsw: PASS -> DMESG-WARN [fdo#102614] * igt@kms_flip@flip-vs-expired-vblank: - shard-skl:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [1/4] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57432/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Suppress redundant preemption Okay! Commit: drm/i915: Keep timeline HWSP allocated until idle across the system Okay! Commit: drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ -O:drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) Commit: drm/i915: Prioritise non-busywait semaphore workloads Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Yet another if/else sort of newer to older platforms.
No functional change. Just a reorg to match the preferred
behavior.
When rebasing internal branch on top of latest sort I noticed
few more cases that needs to get reordered.
Let's do in a bundle this time and hoping there's no other
missing places.
v2: Check for HSW/BDW ULT before generic IS_HASWELL or
IS_BROADWELL or it doesn't work as pointed by Ville.
But also ULT came afterwards anyway.
v3: Accepting suggestions from Lucas:
Sort CNL/CFL, KBL/SKL, and use <= 8 removing chv and bdw.
Cc: Ville Syrjälä
Cc: Chris Wilson
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.c | 20
drivers/gpu/drm/i915/i915_perf.c | 50 +-
drivers/gpu/drm/i915/intel_cdclk.c | 38 +++---
drivers/gpu/drm/i915/intel_workarounds.c | 64 +++-
4 files changed, 82 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c6354f6cdbdb..946212c9c5f9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -219,20 +219,20 @@ intel_virt_detect_pch(const struct drm_i915_private
*dev_priv)
* make an educated guess as to which PCH is really there.
*/
- if (IS_GEN(dev_priv, 5))
- id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
- else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
- id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
+ if (IS_ICELAKE(dev_priv))
+ id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
+ else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
+ id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
+ else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
+ id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
- else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
- id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
- else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
- id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
- else if (IS_ICELAKE(dev_priv))
- id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
+ else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
+ id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
+ else if (IS_GEN(dev_priv, 5))
+ id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
if (id)
DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9ebf99f3d8d3..72a9a35b40e2 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2881,12 +2881,24 @@ void i915_perf_register(struct drm_i915_private
*dev_priv)
sysfs_attr_init(_priv->perf.oa.test_config.sysfs_metric_id.attr);
- if (IS_HASWELL(dev_priv)) {
- i915_perf_load_test_config_hsw(dev_priv);
- } else if (IS_BROADWELL(dev_priv)) {
- i915_perf_load_test_config_bdw(dev_priv);
- } else if (IS_CHERRYVIEW(dev_priv)) {
- i915_perf_load_test_config_chv(dev_priv);
+ if (IS_ICELAKE(dev_priv)) {
+ i915_perf_load_test_config_icl(dev_priv);
+ } else if (IS_CANNONLAKE(dev_priv)) {
+ i915_perf_load_test_config_cnl(dev_priv);
+ } else if (IS_COFFEELAKE(dev_priv)) {
+ if (IS_CFL_GT2(dev_priv))
+ i915_perf_load_test_config_cflgt2(dev_priv);
+ if (IS_CFL_GT3(dev_priv))
+ i915_perf_load_test_config_cflgt3(dev_priv);
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ i915_perf_load_test_config_glk(dev_priv);
+ } else if (IS_KABYLAKE(dev_priv)) {
+ if (IS_KBL_GT2(dev_priv))
+ i915_perf_load_test_config_kblgt2(dev_priv);
+ else if (IS_KBL_GT3(dev_priv))
+ i915_perf_load_test_config_kblgt3(dev_priv);
+ } else if (IS_BROXTON(dev_priv)) {
+ i915_perf_load_test_config_bxt(dev_priv);
} else if (IS_SKYLAKE(dev_priv)) {
if (IS_SKL_GT2(dev_priv))
i915_perf_load_test_config_sklgt2(dev_priv);
@@ -2894,25 +2906,13 @@ void i915_perf_register(struct drm_i915_private
*dev_priv)
i915_perf_load_test_config_sklgt3(dev_priv);
else if (IS_SKL_GT4(dev_priv))
i915_perf_load_test_config_sklgt4(dev_priv);
- } else if (IS_BROXTON(dev_priv)) {
- i915_perf_load_test_config_bxt(dev_priv);
- } else if (IS_KABYLAKE(dev_priv)) {
- if (IS_KBL_GT2(dev_priv))
- i915_perf_load_test_config_kblgt2(dev_priv);
- else if (IS_KBL_GT3(dev_priv))
-
Re: [Intel-gfx] [PATCH] drm/i915: Yet another if/else sort of newer to older platforms.
On Thu, Feb 28, 2019 at 03:19:39PM -0800, Lucas De Marchi wrote:
> On Mon, Feb 25, 2019 at 11:11:30AM -0800, Rodrigo Vivi wrote:
> > No functional change. Just a reorg to match the preferred
> > behavior.
> >
> > When rebasing internal branch on top of latest sort I noticed
> > few more cases that needs to get reordered.
> >
> > Let's do in a bundle this time and hoping there's no other
> > missing places.
> >
> > v2: Check for HSW/BDW ULT before generic IS_HASWELL or
> >IS_BROADWELL or it doesn't work as pointed by Ville.
> >But also ULT came afterwards anyway.
> >
> > Cc: Ville Syrjälä
> > Cc: Chris Wilson
> > Cc: Lucas De Marchi
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 20
> > drivers/gpu/drm/i915/i915_perf.c | 50 +-
> > drivers/gpu/drm/i915/intel_cdclk.c | 38 +++---
> > drivers/gpu/drm/i915/intel_workarounds.c | 64
> > 4 files changed, 86 insertions(+), 86 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index c6354f6cdbdb..ed48aac1487d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -219,20 +219,20 @@ intel_virt_detect_pch(const struct drm_i915_private
> > *dev_priv)
> > * make an educated guess as to which PCH is really there.
> > */
> >
> > - if (IS_GEN(dev_priv, 5))
> > - id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
> > - else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> > - id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
> > + if (IS_ICELAKE(dev_priv))
> > + id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
> > + else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
>
> if you want to be strict about the order, then this should be:
accepted. It seems the most used one and makes sense
to keep CFL near the gen9 ones although cfl came after cnl
chronologically
>
> else if (IS_CANNONLAKE(dev_priv) || IS_COFFELAKE(dev_priv))
>
> > + id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
> > + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>
> ditto
accepted.
>
> > + id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
> > else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> > id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
> > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
> > - else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > - id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
> > - else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> > - id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
> > - else if (IS_ICELAKE(dev_priv))
> > - id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
> > + else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> > + id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
> > + else if (IS_GEN(dev_priv, 5))
> > + id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
> >
> > if (id)
> > DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index 9ebf99f3d8d3..72a9a35b40e2 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -2881,12 +2881,24 @@ void i915_perf_register(struct drm_i915_private
> > *dev_priv)
> >
> > sysfs_attr_init(_priv->perf.oa.test_config.sysfs_metric_id.attr);
> >
> > - if (IS_HASWELL(dev_priv)) {
> > - i915_perf_load_test_config_hsw(dev_priv);
> > - } else if (IS_BROADWELL(dev_priv)) {
> > - i915_perf_load_test_config_bdw(dev_priv);
> > - } else if (IS_CHERRYVIEW(dev_priv)) {
> > - i915_perf_load_test_config_chv(dev_priv);
> > + if (IS_ICELAKE(dev_priv)) {
> > + i915_perf_load_test_config_icl(dev_priv);
> > + } else if (IS_CANNONLAKE(dev_priv)) {
> > + i915_perf_load_test_config_cnl(dev_priv);
> > + } else if (IS_COFFEELAKE(dev_priv)) {
> > + if (IS_CFL_GT2(dev_priv))
> > + i915_perf_load_test_config_cflgt2(dev_priv);
> > + if (IS_CFL_GT3(dev_priv))
> > + i915_perf_load_test_config_cflgt3(dev_priv);
> > + } else if (IS_GEMINILAKE(dev_priv)) {
> > + i915_perf_load_test_config_glk(dev_priv);
> > + } else if (IS_KABYLAKE(dev_priv)) {
> > + if (IS_KBL_GT2(dev_priv))
> > + i915_perf_load_test_config_kblgt2(dev_priv);
> > + else if (IS_KBL_GT3(dev_priv))
> > + i915_perf_load_test_config_kblgt3(dev_priv);
> > + } else if (IS_BROXTON(dev_priv)) {
> > + i915_perf_load_test_config_bxt(dev_priv);
> > } else if (IS_SKYLAKE(dev_priv)) {
> > if (IS_SKL_GT2(dev_priv))
> > i915_perf_load_test_config_sklgt2(dev_priv);
> > @@ -2894,25 +2906,13 @@ void i915_perf_register(struct drm_i915_private
> > *dev_priv)
> >
[Intel-gfx] [CI 3/4] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Having introduced per-context seqno, we now have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
As might be reasonably expected, HW semaphores excel in inter-engine
synchronisation microbenchmarks (where the 3x reduced latency / increased
throughput more than offset the power cost of spinning on a second ring)
and have significant improvement (can be up to ~10%, most see no change)
for single clients that utilize multiple engines (typically media players
and transcoders), without regressing multiple clients that can saturate
the system or changing the power envelope dramatically.
v3: Drop the older NEQ branch, now we pin the signaler's HWSP anyway.
v4: Tell the world and include it as part of scheduler caps.
Testcase: igt/gem_exec_whisper
Testcase: igt/benchmarks/gem_wsim
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 138 +-
drivers/gpu/drm/i915/i915_request.h | 26 +++-
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 9 +-
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ++
include/uapi/drm/i915_drm.h | 1 +
10 files changed, 181 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c6354f6cdbdb..c08abdef5eb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -351,7 +351,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = 0;
+ value = !!(dev_priv->caps.scheduler &
I915_SCHEDULER_CAP_SEMAPHORES);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index d354967d6ae8..59e30b8c4ee9 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -32,9 +33,16 @@
#include "i915_active.h"
#include "i915_reset.h"
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
static struct i915_global_request {
struct kmem_cache *slab_requests;
struct kmem_cache *slab_dependencies;
+ struct kmem_cache *slab_execute_cbs;
} global;
static const char *i915_fence_get_driver_name(struct dma_fence *fence)
@@ -325,6 +333,69 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kmem_cache_free(global.slab_execute_cbs, cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(>lock);
+
+ if (list_empty(>execute_cb))
+ return;
+
+ list_for_each_entry(cb, >execute_cb, link)
+ irq_work_queue(>work);
+
+ /*
+* XXX Rollback on __i915_request_unsubmit()
+*
+* In the future, perhaps when we have an active time-slicing scheduler,
+* it will be interesting to unsubmit parallel execution and remove
+* busywaits from the GPU until their master is restarted. This is
+* quite hairy, we have to carefully rollback the fence and do a
+* preempt-to-idle cycle on the target engine, all the while the
+* master execute_cb may refire.
+*/
+ INIT_LIST_HEAD(>execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+
+ if (i915_request_is_active(signal))
+ return 0;
+
+
[Intel-gfx] [CI 1/4] drm/i915/execlists: Suppress redundant preemption
On unwinding the active request we give it a small (limited to internal
priority levels) boost to prevent it from being gazumped a second time.
However, this means that it can be promoted to above the request that
triggered the preemption request, causing a preempt-to-idle cycle for no
change. We can avoid this if we take the boost into account when
checking if the preemption request is valid.
v2: After preemption the active request will be after the preemptee if
they end up with equal priority.
v3: Tvrtko pointed out that this, the existing logic, makes
I915_PRIORITY_WAIT non-preemptible. Document this interesting quirk!
v4: Prove Tvrtko was right about WAIT being non-preemptible and test it.
v5: Except not all priorities were made equal, and the WAIT not preempting
is only if we start off as !NEWCLIENT.
v6: More commentary after coming to an understanding about what I had
forgotten to say.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 44 +---
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4f2187aa44e4..3fd0c45a2920 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,6 +164,8 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct intel_context *ce);
@@ -190,8 +192,30 @@ static inline int rq_prio(const struct i915_request *rq)
static int effective_prio(const struct i915_request *rq)
{
+ int prio = rq_prio(rq);
+
+ /*
+* On unwinding the active request, we give it a priority bump
+* equivalent to a freshly submitted request. This protects it from
+* being gazumped again, but it would be preferable if we didn't
+* let it be gazumped in the first place!
+*
+* See __unwind_incomplete_requests()
+*/
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
+ /*
+* After preemption, we insert the active request at the
+* end of the new priority level. This means that we will be
+* _lower_ priority than the preemptee all things equal (and
+* so the preemption is valid), so adjust our comparison
+* accordingly.
+*/
+ prio |= ACTIVE_PRIORITY;
+ prio--;
+ }
+
/* Restrict mere WAIT boosts from triggering preemption */
- return rq_prio(rq) | __NO_PREEMPTION;
+ return prio | __NO_PREEMPTION;
}
static int queue_prio(const struct intel_engine_execlists *execlists)
@@ -359,7 +383,7 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
{
struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
+ int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
lockdep_assert_held(>timeline.lock);
@@ -390,9 +414,21 @@ __unwind_incomplete_requests(struct intel_engine_cs
*engine)
* The active request is now effectively the start of a new client
* stream, so give it the equivalent small priority bump to prevent
* it being gazumped a second time by another peer.
+*
+* Note we have to be careful not to apply a priority boost to a request
+* still spinning on its semaphores. If the request hasn't started, that
+* means it is still waiting for its dependencies to be signaled, and
+* if we apply a priority boost to this request, we will boost it past
+* its signalers and so break PI.
+*
+* One consequence of this preemption boost is that we may jump
+* over lesser priorities (such as I915_PRIORITY_WAIT), effectively
+* making those priorities non-preemptible. They will be moved forward
+* in the priority queue, but they will not gain immediate access to
+* the GPU.
*/
- if (!(prio & I915_PRIORITY_NEWCLIENT)) {
- prio |= I915_PRIORITY_NEWCLIENT;
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
+ prio |= ACTIVE_PRIORITY;
active->sched.attr.priority = prio;
list_move_tail(>sched.link,
i915_sched_lookup_priolist(engine, prio));
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/4] drm/i915: Prioritise non-busywait semaphore workloads
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately. We then also have to be careful that we don't give earlier
semaphores an accidental boost because later work doesn't wait on other
rings, hence we keep a history of semaphore usage of the dependency chain.
v2: Stop rolling the bits into a chain and just use a flag in case this
request or any of our dependencies use a semaphore. The rolling around
was contagious as Tvrtko was heard to fall off his chair.
Testcase: igt/gem_exec_schedule/semaphore
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 16
drivers/gpu/drm/i915/i915_scheduler.c | 6 ++
drivers/gpu/drm/i915/i915_scheduler.h | 9 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 59e30b8c4ee9..bcf3c1a155e2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -813,6 +813,7 @@ emit_semaphore_wait(struct i915_request *to,
*cs++ = 0;
intel_ring_advance(to, cs);
+ to->sched.flags |= I915_SCHED_HAS_SEMAPHORE;
return 0;
}
@@ -1083,6 +1084,21 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ /*
+* Boost actual workloads past semaphores!
+*
+* With semaphores we spin on one engine waiting for another,
+* simply to reduce the latency of starting our work when
+* the signaler completes. However, if there is any other
+* work that we could be doing on this engine instead, that
+* is better utilisation and will reduce the overall duration
+* of the current work. To avoid PI boosting a semaphore
+* far in the distance past over useful work, we keep a history
+* of any semaphore use along our dependency chain.
+*/
+ if (!(request->sched.flags & I915_SCHED_HAS_SEMAPHORE))
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 50018ad30233..8a64748a7912 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -39,6 +39,7 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(>waiters_list);
INIT_LIST_HEAD(>link);
node->attr.priority = I915_PRIORITY_INVALID;
+ node->flags = 0;
}
static struct i915_dependency *
@@ -69,6 +70,11 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node
*node,
dep->signaler = signal;
dep->flags = flags;
+ /* Keep track of whether anyone on this chain has a semaphore */
+ if (signal->flags & I915_SCHED_HAS_SEMAPHORE &&
+ !node_started(signal))
+ node->flags |= I915_SCHED_HAS_SEMAPHORE;
+
ret = true;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 7d4a49750d92..6ce450cf63fa 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
@@ -74,6 +75,8 @@ struct i915_sched_node {
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
struct i915_sched_attr attr;
+ unsigned int flags;
+#define I915_SCHED_HAS_SEMAPHORE BIT(0)
};
struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6c9479acb433..578c8c98c718 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
[Intel-gfx] [CI 2/4] drm/i915: Keep timeline HWSP allocated until idle across the system
In preparation for enabling HW semaphores, we need to keep in flight
timeline HWSP alive until its use across entire system has completed,
as any other timeline active on the GPU may still refer back to the
already retired timeline. We both have to delay recycling available
cachelines and unpinning old HWSP until the next idle point.
An easy option would be to simply keep all used HWSP until the system as
a whole was idle, i.e. we could release them all at once on parking.
However, on a busy system, we may never see a global idle point,
essentially meaning the resource will be leaked until we are forced to
do a GC pass. We already employ a fine-grained idle detection mechanism
for vma, which we can reuse here so that each cacheline can be freed
immediately after the last request using it is retired.
v3: Keep track of the activity of each cacheline.
v4: cacheline_free() on canceling the seqno tracking
v5: Finally with a testcase to exercise wraparound
v6: Pack cacheline into empty bits of page-aligned vaddr
v7: Use i915_utils to hide the pointer casting around bit manipulation
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 31 +-
drivers/gpu/drm/i915/i915_request.h | 11 +
drivers/gpu/drm/i915/i915_timeline.c | 293 --
drivers/gpu/drm/i915/i915_timeline.h | 11 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 113 +++
5 files changed, 420 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 719d1a5ab082..d354967d6ae8 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -325,11 +325,6 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
-static u32 timeline_get_seqno(struct i915_timeline *tl)
-{
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
-}
-
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -532,8 +527,10 @@ struct i915_request *
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context
*ctx)
{
struct drm_i915_private *i915 = engine->i915;
- struct i915_request *rq;
struct intel_context *ce;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ u32 seqno;
int ret;
lockdep_assert_held(>drm.struct_mutex);
@@ -610,24 +607,27 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
}
- rq->rcustate = get_state_synchronize_rcu();
-
INIT_LIST_HEAD(>active_list);
+
+ tl = ce->ring->timeline;
+ ret = i915_timeline_get_seqno(tl, rq, );
+ if (ret)
+ goto err_free;
+
rq->i915 = i915;
rq->engine = engine;
rq->gem_context = ctx;
rq->hw_context = ce;
rq->ring = ce->ring;
- rq->timeline = ce->ring->timeline;
+ rq->timeline = tl;
GEM_BUG_ON(rq->timeline == >timeline);
- rq->hwsp_seqno = rq->timeline->hwsp_seqno;
+ rq->hwsp_seqno = tl->hwsp_seqno;
+ rq->hwsp_cacheline = tl->hwsp_cacheline;
+ rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
spin_lock_init(>lock);
- dma_fence_init(>fence,
- _fence_ops,
- >lock,
- rq->timeline->fence_context,
- timeline_get_seqno(rq->timeline));
+ dma_fence_init(>fence, _fence_ops, >lock,
+ tl->fence_context, seqno);
/* We bump the ref for the fence chain */
i915_sw_fence_init(_request_get(rq)->submit, submit_notify);
@@ -687,6 +687,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(>sched.signalers_list));
GEM_BUG_ON(!list_empty(>sched.waiters_list));
+err_free:
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
mutex_unlock(>ring->timeline->mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index be3ded6bcf56..09eaad06d2c6 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -38,6 +38,7 @@ struct drm_file;
struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+struct i915_timeline_cacheline;
struct i915_capture_list {
struct i915_capture_list *next;
@@ -148,6 +149,16 @@ struct i915_request {
*/
const u32 *hwsp_seqno;
+ /*
+* If we need to access the timeline's seqno for this request in
+* another request, we need to keep a read reference to this associated
+* cacheline, so that we do not free and recycle it before the foreign
+* observers have completed. Hence, we keep a pointer to the cacheline
+* inside the timeline's HWSP vma,
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Start subclassing crtc_state.
== Series Details == Series: drm: Start subclassing crtc_state. URL : https://patchwork.freedesktop.org/series/57425/ State : success == Summary == CI Bug Log - changes from CI_DRM_5676_full -> Patchwork_12342_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12342_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-parallel-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +4 * igt@gem_busy@extended-semaphore-render: - shard-iclb: NOTRUN -> SKIP [fdo#109275] * igt@gem_eio@in-flight-suspend: - shard-snb: PASS -> DMESG-WARN [fdo#102365] * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-snb: NOTRUN -> SKIP [fdo#109271] +50 * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_store@pages-bsd1: - shard-apl: NOTRUN -> SKIP [fdo#109271] +17 * igt@gem_mocs_settings@mocs-reset-ctx-dirty-render: - shard-iclb: NOTRUN -> SKIP [fdo#109287] * igt@gem_pread@stolen-display: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] / [fdo#108840] * igt@i915_pm_rpm@gem-execbuf-stress-extra-wait: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3 * igt@i915_pm_rpm@legacy-planes: - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 * igt@kms_atomic_transition@4x-modeset-transitions: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-iclb: PASS -> DMESG-WARN [fdo#107956] - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 * igt@kms_busy@extended-pageflip-hang-oldfb-render-f: - shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-hsw: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_chv_cursor_fail@pipe-b-64x64-bottom-edge: - shard-snb: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_color@pipe-b-legacy-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-256x256-random: - shard-apl: PASS -> FAIL [fdo#103232] +2 * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-iclb: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +3 * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: PASS -> FAIL [fdo#100368] * igt@kms_flip_tiling@flip-changes-tiling: - shard-skl: PASS -> FAIL [fdo#108303] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +7 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt: - shard-hsw: NOTRUN -> SKIP [fdo#109271] +19 * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - shard-skl: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-apl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-snb: PASS
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Check that whitelisted registers are accessible (rev7)
== Series Details ==
Series: drm/i915/selftests: Check that whitelisted registers are accessible
(rev7)
URL : https://patchwork.freedesktop.org/series/57342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5677 -> Patchwork_12345
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57342/revisions/7/mbox/
Known issues
Here are the changes found in Patchwork_12345 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-c:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] /
[fdo#109799]
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770:SKIP [fdo#109271] -> PASS +4
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#109799]: https://bugs.freedesktop.org/show_bug.cgi?id=109799
Participating hosts (42 -> 38)
--
Additional (2): fi-icl-y fi-pnv-d510
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-icl-u3
Build changes
-
* Linux: CI_DRM_5677 -> Patchwork_12345
CI_DRM_5677: ee86833a661594b0094ac2b840ebb0f5fef89517 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12345: fc318ca3dbecc340aeb4146978a8d51f3264df25 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fc318ca3dbec drm/i915/selftests: Check that whitelisted registers are accessible
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12345/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/38] drm/i915: Extend CONTEXT_CREATE to set parameters upon construction
On 01/03/2019 14:03, Chris Wilson wrote:
It can be useful to have a single ioctl to create a context with all
the initial parameters instead of a series of create + setparam + setparam
ioctls. This extension to create context allows any of the parameters
to be passed in as a linked list to be applied to the newly constructed
context.
v2: Make a local copy of user setparam (Tvrtko)
v3: Use flags to detect availability of extension interface
Looks good to me.
Why have you changed to use flags and not just check the extension field
being non-null?
Regards,
Tvrtko
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 447 +---
include/uapi/drm/i915_drm.h | 166 +
3 files changed, 339 insertions(+), 276 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6b75d1b7b8bd..de8effed4381 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2997,7 +2997,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY,
intel_sprite_set_colorkey_ioctl, DRM_MASTER),
DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
- DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE,
i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT,
i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY,
i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS,
i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 8c35b6019f0d..f883d99653a3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -89,6 +89,7 @@
#include
#include "i915_drv.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
#include "intel_lrc_reg.h"
#include "intel_workarounds.h"
@@ -1066,196 +1067,6 @@ static int set_ppgtt(struct i915_gem_context *ctx,
return err;
}
-static bool client_is_banned(struct drm_i915_file_private *file_priv)
-{
- return atomic_read(_priv->ban_score) >= I915_CLIENT_SCORE_BANNED;
-}
-
-int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file)
-{
- struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_context_create *args = data;
- struct drm_i915_file_private *file_priv = file->driver_priv;
- struct i915_gem_context *ctx;
- int ret;
-
- if (!DRIVER_CAPS(i915)->has_logical_contexts)
- return -ENODEV;
-
- if (args->pad != 0)
- return -EINVAL;
-
- ret = i915_terminally_wedged(i915);
- if (ret)
- return ret;
-
- if (client_is_banned(file_priv)) {
- DRM_DEBUG("client %s[%d] banned from creating ctx\n",
- current->comm,
- pid_nr(get_task_pid(current, PIDTYPE_PID)));
-
- return -EIO;
- }
-
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- return ret;
-
- ctx = i915_gem_create_context(i915, file_priv);
- mutex_unlock(>struct_mutex);
- if (IS_ERR(ctx))
- return PTR_ERR(ctx);
-
- GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
-
- args->ctx_id = ctx->user_handle;
- DRM_DEBUG("HW context %d created\n", args->ctx_id);
-
- return 0;
-}
-
-int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file)
-{
- struct drm_i915_gem_context_destroy *args = data;
- struct drm_i915_file_private *file_priv = file->driver_priv;
- struct i915_gem_context *ctx;
- int ret;
-
- if (args->pad != 0)
- return -EINVAL;
-
- if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
- return -ENOENT;
-
- ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
- if (!ctx)
- return -ENOENT;
-
- ret = mutex_lock_interruptible(>struct_mutex);
- if (ret)
- goto out;
-
- __destroy_hw_context(ctx, file_priv);
- mutex_unlock(>struct_mutex);
-
-out:
- i915_gem_context_put(ctx);
- return 0;
-}
-
-static int get_sseu(struct i915_gem_context *ctx,
- struct drm_i915_gem_context_param *args)
-{
- struct drm_i915_gem_context_param_sseu user_sseu;
- struct intel_engine_cs *engine;
- struct intel_context *ce;
- int ret;
-
- if (args->size == 0)
-
[Intel-gfx] [PATCH 2/4] drm/i915: Keep timeline HWSP allocated until idle across the system
In preparation for enabling HW semaphores, we need to keep in flight
timeline HWSP alive until its use across entire system has completed,
as any other timeline active on the GPU may still refer back to the
already retired timeline. We both have to delay recycling available
cachelines and unpinning old HWSP until the next idle point.
An easy option would be to simply keep all used HWSP until the system as
a whole was idle, i.e. we could release them all at once on parking.
However, on a busy system, we may never see a global idle point,
essentially meaning the resource will be leaked until we are forced to
do a GC pass. We already employ a fine-grained idle detection mechanism
for vma, which we can reuse here so that each cacheline can be freed
immediately after the last request using it is retired.
v3: Keep track of the activity of each cacheline.
v4: cacheline_free() on canceling the seqno tracking
v5: Finally with a testcase to exercise wraparound
v6: Pack cacheline into empty bits of page-aligned vaddr
v7: Use i915_utils to hide the pointer casting around bit manipulation
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 31 +-
drivers/gpu/drm/i915/i915_request.h | 11 +
drivers/gpu/drm/i915/i915_timeline.c | 293 --
drivers/gpu/drm/i915/i915_timeline.h | 11 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 113 +++
5 files changed, 420 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 719d1a5ab082..d354967d6ae8 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -325,11 +325,6 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
-static u32 timeline_get_seqno(struct i915_timeline *tl)
-{
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
-}
-
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -532,8 +527,10 @@ struct i915_request *
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context
*ctx)
{
struct drm_i915_private *i915 = engine->i915;
- struct i915_request *rq;
struct intel_context *ce;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ u32 seqno;
int ret;
lockdep_assert_held(>drm.struct_mutex);
@@ -610,24 +607,27 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
}
- rq->rcustate = get_state_synchronize_rcu();
-
INIT_LIST_HEAD(>active_list);
+
+ tl = ce->ring->timeline;
+ ret = i915_timeline_get_seqno(tl, rq, );
+ if (ret)
+ goto err_free;
+
rq->i915 = i915;
rq->engine = engine;
rq->gem_context = ctx;
rq->hw_context = ce;
rq->ring = ce->ring;
- rq->timeline = ce->ring->timeline;
+ rq->timeline = tl;
GEM_BUG_ON(rq->timeline == >timeline);
- rq->hwsp_seqno = rq->timeline->hwsp_seqno;
+ rq->hwsp_seqno = tl->hwsp_seqno;
+ rq->hwsp_cacheline = tl->hwsp_cacheline;
+ rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
spin_lock_init(>lock);
- dma_fence_init(>fence,
- _fence_ops,
- >lock,
- rq->timeline->fence_context,
- timeline_get_seqno(rq->timeline));
+ dma_fence_init(>fence, _fence_ops, >lock,
+ tl->fence_context, seqno);
/* We bump the ref for the fence chain */
i915_sw_fence_init(_request_get(rq)->submit, submit_notify);
@@ -687,6 +687,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(>sched.signalers_list));
GEM_BUG_ON(!list_empty(>sched.waiters_list));
+err_free:
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
mutex_unlock(>ring->timeline->mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index be3ded6bcf56..ea1e6f0ade53 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -38,6 +38,7 @@ struct drm_file;
struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+struct i915_timeline_cacheline;
struct i915_capture_list {
struct i915_capture_list *next;
@@ -148,6 +149,16 @@ struct i915_request {
*/
const u32 *hwsp_seqno;
+ /*
+* If we need to access the timeline's seqno for this request in
+* another request, we need to keep a read reference to this associated
+* cacheline, so that we do not free and recycle it before the foriegn
+* observers have completed. Hence, we keep a pointer to the cacheline
+* inside the timeline's HWSP vma,
[Intel-gfx] [PATCH 4/4] drm/i915: Prioritise non-busywait semaphore workloads
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately. We then also have to be careful that we don't give earlier
semaphores an accidental boost because later work doesn't wait on other
rings, hence we keep a history of semaphore usage of the dependency chain.
v2: Stop rolling the bits into a chain and just use a flag in case this
request or any of our dependencies use a semaphore. The rolling around
was contagious as Tvrtko was heard to fall off his chair.
Testcase: igt/gem_exec_schedule/semaphore
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 16
drivers/gpu/drm/i915/i915_scheduler.c | 6 ++
drivers/gpu/drm/i915/i915_scheduler.h | 9 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 59e30b8c4ee9..bcf3c1a155e2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -813,6 +813,7 @@ emit_semaphore_wait(struct i915_request *to,
*cs++ = 0;
intel_ring_advance(to, cs);
+ to->sched.flags |= I915_SCHED_HAS_SEMAPHORE;
return 0;
}
@@ -1083,6 +1084,21 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ /*
+* Boost actual workloads past semaphores!
+*
+* With semaphores we spin on one engine waiting for another,
+* simply to reduce the latency of starting our work when
+* the signaler completes. However, if there is any other
+* work that we could be doing on this engine instead, that
+* is better utilisation and will reduce the overall duration
+* of the current work. To avoid PI boosting a semaphore
+* far in the distance past over useful work, we keep a history
+* of any semaphore use along our dependency chain.
+*/
+ if (!(request->sched.flags & I915_SCHED_HAS_SEMAPHORE))
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 50018ad30233..8a64748a7912 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -39,6 +39,7 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(>waiters_list);
INIT_LIST_HEAD(>link);
node->attr.priority = I915_PRIORITY_INVALID;
+ node->flags = 0;
}
static struct i915_dependency *
@@ -69,6 +70,11 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node
*node,
dep->signaler = signal;
dep->flags = flags;
+ /* Keep track of whether anyone on this chain has a semaphore */
+ if (signal->flags & I915_SCHED_HAS_SEMAPHORE &&
+ !node_started(signal))
+ node->flags |= I915_SCHED_HAS_SEMAPHORE;
+
ret = true;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 7d4a49750d92..6ce450cf63fa 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
@@ -74,6 +75,8 @@ struct i915_sched_node {
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
struct i915_sched_attr attr;
+ unsigned int flags;
+#define I915_SCHED_HAS_SEMAPHORE BIT(0)
};
struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6c9479acb433..578c8c98c718 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
[Intel-gfx] [PATCH 3/4] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Having introduced per-context seqno, we now have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
As might be reasonably expected, HW semaphores excel in inter-engine
synchronisation microbenchmarks (where the 3x reduced latency / increased
throughput more than offset the power cost of spinning on a second ring)
and have significant improvement (can be up to ~10%, most see no change)
for single clients that utilize multiple engines (typically media players
and transcoders), without regressing multiple clients that can saturate
the system or changing the power envelope dramatically.
v3: Drop the older NEQ branch, now we pin the signaler's HWSP anyway.
v4: Tell the world and include it as part of scheduler caps.
Testcase: igt/gem_exec_whisper
Testcase: igt/benchmarks/gem_wsim
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 138 +-
drivers/gpu/drm/i915/i915_request.h | 15 ++-
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 9 +-
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ++
include/uapi/drm/i915_drm.h | 1 +
10 files changed, 171 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c6354f6cdbdb..c08abdef5eb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -351,7 +351,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = 0;
+ value = !!(dev_priv->caps.scheduler &
I915_SCHEDULER_CAP_SEMAPHORES);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index d354967d6ae8..59e30b8c4ee9 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -32,9 +33,16 @@
#include "i915_active.h"
#include "i915_reset.h"
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
static struct i915_global_request {
struct kmem_cache *slab_requests;
struct kmem_cache *slab_dependencies;
+ struct kmem_cache *slab_execute_cbs;
} global;
static const char *i915_fence_get_driver_name(struct dma_fence *fence)
@@ -325,6 +333,69 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kmem_cache_free(global.slab_execute_cbs, cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(>lock);
+
+ if (list_empty(>execute_cb))
+ return;
+
+ list_for_each_entry(cb, >execute_cb, link)
+ irq_work_queue(>work);
+
+ /*
+* XXX Rollback on __i915_request_unsubmit()
+*
+* In the future, perhaps when we have an active time-slicing scheduler,
+* it will be interesting to unsubmit parallel execution and remove
+* busywaits from the GPU until their master is restarted. This is
+* quite hairy, we have to carefully rollback the fence and do a
+* preempt-to-idle cycle on the target engine, all the while the
+* master execute_cb may refire.
+*/
+ INIT_LIST_HEAD(>execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+
+ if (i915_request_is_active(signal))
+ return 0;
+
+
[Intel-gfx] [PATCH 1/4] drm/i915/execlists: Suppress redundant preemption
On unwinding the active request we give it a small (limited to internal
priority levels) boost to prevent it from being gazumped a second time.
However, this means that it can be promoted to above the request that
triggered the preemption request, causing a preempt-to-idle cycle for no
change. We can avoid this if we take the boost into account when
checking if the preemption request is valid.
v2: After preemption the active request will be after the preemptee if
they end up with equal priority.
v3: Tvrtko pointed out that this, the existing logic, makes
I915_PRIORITY_WAIT non-preemptible. Document this interesting quirk!
v4: Prove Tvrtko was right about WAIT being non-preemptible and test it.
v5: Except not all priorities were made equal, and the WAIT not preempting
is only if we start off as !NEWCLIENT.
v6: More commentary after coming to an understand about what I had
forgotten to say.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 44 +---
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4f2187aa44e4..3fd0c45a2920 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,6 +164,8 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct intel_context *ce);
@@ -190,8 +192,30 @@ static inline int rq_prio(const struct i915_request *rq)
static int effective_prio(const struct i915_request *rq)
{
+ int prio = rq_prio(rq);
+
+ /*
+* On unwinding the active request, we give it a priority bump
+* equivalent to a freshly submitted request. This protects it from
+* being gazumped again, but it would be preferable if we didn't
+* let it be gazumped in the first place!
+*
+* See __unwind_incomplete_requests()
+*/
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
+ /*
+* After preemption, we insert the active request at the
+* end of the new priority level. This means that we will be
+* _lower_ priority than the preemptee all things equal (and
+* so the preemption is valid), so adjust our comparison
+* accordingly.
+*/
+ prio |= ACTIVE_PRIORITY;
+ prio--;
+ }
+
/* Restrict mere WAIT boosts from triggering preemption */
- return rq_prio(rq) | __NO_PREEMPTION;
+ return prio | __NO_PREEMPTION;
}
static int queue_prio(const struct intel_engine_execlists *execlists)
@@ -359,7 +383,7 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
{
struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
+ int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
lockdep_assert_held(>timeline.lock);
@@ -390,9 +414,21 @@ __unwind_incomplete_requests(struct intel_engine_cs
*engine)
* The active request is now effectively the start of a new client
* stream, so give it the equivalent small priority bump to prevent
* it being gazumped a second time by another peer.
+*
+* Note we have to be careful not to apply a priority boost to a request
+* still spinning on its semaphores. If the request hasn't started, that
+* means it is still waiting for its dependencies to be signaled, and
+* if we apply a priority boost to this request, we will boost it past
+* its signalers and so break PI.
+*
+* One consequence of this preemption boost is that we may jump
+* over lesser priorities (such as I915_PRIORITY_WAIT), effectively
+* making those priorities non-preemptible. They will be moved forward
+* in the priority queue, but they will not gain immediate access to
+* the GPU.
*/
- if (!(prio & I915_PRIORITY_NEWCLIENT)) {
- prio |= I915_PRIORITY_NEWCLIENT;
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
+ prio |= ACTIVE_PRIORITY;
active->sched.attr.priority = prio;
list_move_tail(>sched.link,
i915_sched_lookup_priolist(engine, prio));
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 16/38] drm/i915: Introduce a context barrier callback
On 01/03/2019 14:03, Chris Wilson wrote:
In the next patch, we will want to update live state within a context.
As this state may be in use by the GPU and we haven't been explicitly
tracking its activity, we instead attach it to a request we send down
the context setup with its new state and on retiring that request
cleanup the old state as we then know that it is no longer live.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 74 +
.../gpu/drm/i915/selftests/i915_gem_context.c | 103 ++
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 3b5145b30d85..91926a407548 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -707,6 +707,80 @@ last_request_on_engine(struct i915_timeline *timeline,
return NULL;
}
+struct context_barrier_task {
+ struct i915_active base;
+ void (*task)(void *data);
+ void *data;
+};
+
+static void cb_retire(struct i915_active *base)
+{
+ struct context_barrier_task *cb = container_of(base, typeof(*cb), base);
+
+ if (cb->task)
+ cb->task(cb->data);
+
+ i915_active_fini(>base);
+ kfree(cb);
+}
+
+I915_SELFTEST_DECLARE(static unsigned long context_barrier_inject_fault);
+static int context_barrier_task(struct i915_gem_context *ctx,
+ unsigned long engines,
I'm in two minds about usefulness of intel_engine_mask_t.
+ void (*task)(void *data),
+ void *data)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct context_barrier_task *cb;
+ struct intel_context *ce;
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ lockdep_assert_held(>drm.struct_mutex);
+ GEM_BUG_ON(!task);
+
+ cb = kmalloc(sizeof(*cb), GFP_KERNEL);
+ if (!cb)
+ return -ENOMEM;
+
+ i915_active_init(i915, >base, cb_retire);
+ i915_active_acquire(>base);
+
+ wakeref = intel_runtime_pm_get(i915);
+ list_for_each_entry(ce, >active_engines, active_link) {
+ struct intel_engine_cs *engine = ce->engine;
+ struct i915_request *rq;
+
+ if (!(ce->engine->mask & engines))
+ continue;
+
+ if (I915_SELFTEST_ONLY(context_barrier_inject_fault &
+ engine->mask)) {
+ err = -ENXIO;
+ break;
+ }
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = i915_active_ref(>base, rq->fence.context, rq);
+ i915_request_add(rq);
+ if (err)
+ break;
+ }
+ intel_runtime_pm_put(i915, wakeref);
+
+ cb->task = err ? NULL : task; /* caller needs to unwind instead */
+ cb->data = data;
+
+ i915_active_release(>base);
+
+ return err;
+}
+
int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915,
unsigned long mask)
{
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 7ae5033457b6..4f7c04247354 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -1594,10 +1594,113 @@ static int igt_switch_to_kernel_context(void *arg)
return err;
}
+static void mock_barrier_task(void *data)
+{
+ unsigned int *counter = data;
+
+ ++*counter;
+}
+
+static int mock_context_barrier(void *arg)
+{
+#undef pr_fmt
+#define pr_fmt(x) "context_barrier_task():" # x
+ struct drm_i915_private *i915 = arg;
+ struct i915_gem_context *ctx;
+ struct i915_request *rq;
+ intel_wakeref_t wakeref;
+ unsigned int counter;
+ int err;
+
+ /*
+* The context barrier provides us with a callback after it emits
+* a request; useful for retiring old state after loading new.
+*/
+
+ mutex_lock(>drm.struct_mutex);
+
+ ctx = mock_context(i915, "mock");
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto unlock;
+ }
+
+ counter = 0;
+ err = context_barrier_task(ctx, 0, mock_barrier_task, );
+ if (err) {
+ pr_err("Failed at line %d, err=%d\n", __LINE__, err);
+ goto out;
+ }
+ if (counter == 0) {
+ pr_err("Did not retire immediately with 0 engines\n");
+ err = -EINVAL;
+ goto out;
+ }
+
+ counter = 0;
+ err = context_barrier_task(ctx, -1, mock_barrier_task, );
+ if (err) {
+ pr_err("Failed at
[Intel-gfx] [CI] drm/i915/selftests: Check that whitelisted registers are accessible
There is no point in whitelisting a register that the user then cannot
write to, so check the register exists before merging such patches.
v2: Mark SLICE_COMMON_ECO_CHICKEN1 [731c] as write-only
v3: Use different variables for different meanings!
Signed-off-by: Chris Wilson
Cc: Dale B Stimson
Cc: Michał Winiarski
Reviewed-by: Michał Winiarski
Link:
https://patchwork.freedesktop.org/patch/msgid/20190301140404.26690-6-ch...@chris-wilson.co.uk
---
.../drm/i915/selftests/intel_workarounds.c| 378 +-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index e6ffc8ac22dc..9f12a0ec804b 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -12,6 +12,14 @@
#include "igt_spinner.h"
#include "igt_wedge_me.h"
#include "mock_context.h"
+#include "mock_drm.h"
+
+static const struct wo_register {
+ enum intel_platform platform;
+ u32 reg;
+} wo_registers[] = {
+ { INTEL_GEMINILAKE, 0x731c }
+};
#define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
struct wa_lists {
@@ -74,7 +82,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct
intel_engine_cs *engine)
if (IS_ERR(result))
return result;
- i915_gem_object_set_cache_level(result, I915_CACHE_LLC);
+ i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC);
cs = i915_gem_object_pin_map(result, I915_MAP_WB);
if (IS_ERR(cs)) {
@@ -331,6 +339,373 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
return err;
}
+static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void *ptr;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
+
+ ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(ptr)) {
+ err = PTR_ERR(ptr);
+ goto err_obj;
+ }
+ memset(ptr, 0xc5, PAGE_SIZE);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_cpu_domain(obj, false);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static struct i915_vma *create_batch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, 16 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static u32 reg_write(u32 old, u32 new, u32 rsvd)
+{
+ if (rsvd == 0x) {
+ old &= ~(new >> 16);
+ old |= new & (new >> 16);
+ } else {
+ old &= ~rsvd;
+ old |= new & rsvd;
+ }
+
+ return old;
+}
+
+static bool wo_register(struct intel_engine_cs *engine, u32 reg)
+{
+ enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
+ if (wo_registers[i].platform == platform &&
+ wo_registers[i].reg == reg)
+ return true;
+ }
+
+ return false;
+}
+
+static int check_dirty_whitelist(struct i915_gem_context *ctx,
+struct intel_engine_cs *engine)
+{
+ const u32 values[] = {
+ 0x,
+ 0x01010101,
+ 0x10100101,
+ 0x03030303,
+ 0x30300303,
+ 0x05050505,
+ 0x50500505,
+ 0x0f0f0f0f,
+ 0xf00ff00f,
+ 0x10101010,
+ 0xf0f01010,
+ 0x30303030,
+ 0xa0a03030,
+ 0x50505050,
+ 0xc0c05050,
+ 0xf0f0f0f0,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x00ff00ff,
+
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/execlists: Suppress redundant preemption (rev2)
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Suppress redundant preemption (rev2) URL : https://patchwork.freedesktop.org/series/57400/ State : success == Summary == CI Bug Log - changes from CI_DRM_5676_full -> Patchwork_12341_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12341_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-parallel-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +4 * igt@gem_eio@reset-stress: - shard-snb: PASS -> FAIL [fdo#109661] * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_store@pages-bsd1: - shard-apl: NOTRUN -> SKIP [fdo#109271] +17 * igt@gem_mocs_settings@mocs-reset-ctx-dirty-render: - shard-iclb: NOTRUN -> SKIP [fdo#109287] * igt@gem_pread@stolen-display: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_rpm@legacy-planes-dpms: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +1 * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@system-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] / [fdo#107807] * igt@i915_suspend@sysfs-reader: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] * igt@kms_atomic_transition@4x-modeset-transitions: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-iclb: PASS -> DMESG-WARN [fdo#107956] - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10 * igt@kms_busy@extended-pageflip-hang-oldfb-render-f: - shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-hsw: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_chv_cursor_fail@pipe-c-64x64-left-edge: - shard-skl: NOTRUN -> FAIL [fdo#104671] * igt@kms_color@pipe-b-degamma: - shard-snb: NOTRUN -> SKIP [fdo#109271] +10 * igt@kms_color@pipe-b-legacy-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-256x256-random: - shard-apl: PASS -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-iclb: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-64x64-sliding: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +3 * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip_tiling@flip-changes-tiling: - shard-skl: PASS -> FAIL [fdo#108303] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +6 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +61 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +7 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt: - shard-hsw: NOTRUN -> SKIP [fdo#109271] +19 * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - shard-skl: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-apl: PASS -> FAIL [fdo#108948] - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-apl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-b-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] +2
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Check that whitelisted registers are accessible (rev6)
== Series Details == Series: drm/i915/selftests: Check that whitelisted registers are accessible (rev6) URL : https://patchwork.freedesktop.org/series/57342/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/intel_workarounds.o In file included from drivers/gpu/drm/i915/intel_workarounds.c:1263:0: drivers/gpu/drm/i915/selftests/intel_workarounds.c: In function ‘create_scratch’: drivers/gpu/drm/i915/selftests/intel_workarounds.c:353:38: error: ‘result’ undeclared (first use in this function); did you mean ‘mf_result’? i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC); ^~ mf_result drivers/gpu/drm/i915/selftests/intel_workarounds.c:353:38: note: each undeclared identifier is reported only once for each function it appears in scripts/Makefile.build:276: recipe for target 'drivers/gpu/drm/i915/intel_workarounds.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_workarounds.o] Error 1 scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:492: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1043: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 15/38] drm/i915: Track active engines within a context
On 01/03/2019 14:03, Chris Wilson wrote:
For use in the next patch, if we track which engines have been used by
the HW, we can reduce the work required to flush our state off the HW to
those engines.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 +--
drivers/gpu/drm/i915/i915_gem_context.c | 5 +
drivers/gpu/drm/i915/i915_gem_context.h | 5 +
drivers/gpu/drm/i915/intel_lrc.c | 22 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++-
drivers/gpu/drm/i915/selftests/mock_context.c | 2 ++
drivers/gpu/drm/i915/selftests/mock_engine.c | 6 +
7 files changed, 43 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 298371aad445..36c63b087ffd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -388,12 +388,9 @@ static void print_context_stats(struct seq_file *m,
struct i915_gem_context *ctx;
list_for_each_entry(ctx, >contexts.list, link) {
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- for_each_engine(engine, i915, id) {
- struct intel_context *ce = to_intel_context(ctx,
engine);
+ struct intel_context *ce;
+ list_for_each_entry(ce, >active_engines, active_link) {
if (ce->state)
per_file_stats(0, ce->state->obj, );
if (ce->ring)
@@ -1880,9 +1877,7 @@ static int i915_context_status(struct seq_file *m, void
*unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_device *dev = _priv->drm;
- struct intel_engine_cs *engine;
struct i915_gem_context *ctx;
- enum intel_engine_id id;
int ret;
ret = mutex_lock_interruptible(>struct_mutex);
@@ -1890,6 +1885,8 @@ static int i915_context_status(struct seq_file *m, void
*unused)
return ret;
list_for_each_entry(ctx, _priv->contexts.list, link) {
+ struct intel_context *ce;
+
seq_puts(m, "HW context ");
if (!list_empty(>hw_id_link))
seq_printf(m, "%x [pin %u]", ctx->hw_id,
@@ -1912,11 +1909,8 @@ static int i915_context_status(struct seq_file *m, void
*unused)
seq_putc(m, ctx->remap_slice ? 'R' : 'r');
seq_putc(m, '\n');
- for_each_engine(engine, dev_priv, id) {
- struct intel_context *ce =
- to_intel_context(ctx, engine);
-
- seq_printf(m, "%s: ", engine->name);
+ list_for_each_entry(ce, >active_engines, active_link) {
+ seq_printf(m, "%s: ", ce->engine->name);
if (ce->state)
describe_obj(m, ce->state->obj);
if (ce->ring)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 004ffcfb305d..3b5145b30d85 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -224,6 +224,7 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
lockdep_assert_held(>i915->drm.struct_mutex);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
+ GEM_BUG_ON(!list_empty(>active_engines));
release_hw_id(ctx);
i915_ppgtt_put(ctx->ppgtt);
@@ -239,6 +240,7 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
put_pid(ctx->pid);
list_del(>link);
+ mutex_destroy(>mutex);
kfree_rcu(ctx, rcu);
}
@@ -351,6 +353,7 @@ intel_context_init(struct intel_context *ce,
struct intel_engine_cs *engine)
{
ce->gem_context = ctx;
+ ce->engine = engine;
INIT_LIST_HEAD(>signal_link);
INIT_LIST_HEAD(>signals);
@@ -379,6 +382,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
list_add_tail(>link, _priv->contexts.list);
ctx->i915 = dev_priv;
ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
+ INIT_LIST_HEAD(>active_engines);
+ mutex_init(>mutex);
for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++)
intel_context_init(>__engine[n], ctx, dev_priv->engine[n]);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index c39dbb32a5c6..df48013b581e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -163,6 +163,9 @@ struct i915_gem_context {
atomic_t hw_id_pin_count;
struct list_head hw_id_link;
+ struct list_head active_engines;
+ struct mutex mutex;
+
/**
* @user_handle: userspace identifier
*
@@ -176,7 +179,9 @@ struct i915_gem_context {
/**
[Intel-gfx] [CI] drm/i915/selftests: Check that whitelisted registers are accessible
There is no point in whitelisting a register that the user then cannot
write to, so check the register exists before merging such patches.
v2: Mark SLICE_COMMON_ECO_CHICKEN1 [731c] as write-only
v3: Use different variables for different meanings!
Signed-off-by: Chris Wilson
Cc: Dale B Stimson
Cc: Michał Winiarski
Reviewed-by: Michał Winiarski
Link:
https://patchwork.freedesktop.org/patch/msgid/20190301140404.26690-6-ch...@chris-wilson.co.uk
---
.../drm/i915/selftests/intel_workarounds.c| 378 +-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index e6ffc8ac22dc..37a6062dafdd 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -12,6 +12,14 @@
#include "igt_spinner.h"
#include "igt_wedge_me.h"
#include "mock_context.h"
+#include "mock_drm.h"
+
+static const struct wo_register {
+ enum intel_platform platform;
+ u32 reg;
+} wo_registers[] = {
+ { INTEL_GEMINILAKE, 0x731c }
+};
#define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
struct wa_lists {
@@ -74,7 +82,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct
intel_engine_cs *engine)
if (IS_ERR(result))
return result;
- i915_gem_object_set_cache_level(result, I915_CACHE_LLC);
+ i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC);
cs = i915_gem_object_pin_map(result, I915_MAP_WB);
if (IS_ERR(cs)) {
@@ -331,6 +339,373 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
return err;
}
+static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void *ptr;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC);
+
+ ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(ptr)) {
+ err = PTR_ERR(ptr);
+ goto err_obj;
+ }
+ memset(ptr, 0xc5, PAGE_SIZE);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_cpu_domain(obj, false);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static struct i915_vma *create_batch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, 16 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static u32 reg_write(u32 old, u32 new, u32 rsvd)
+{
+ if (rsvd == 0x) {
+ old &= ~(new >> 16);
+ old |= new & (new >> 16);
+ } else {
+ old &= ~rsvd;
+ old |= new & rsvd;
+ }
+
+ return old;
+}
+
+static bool wo_register(struct intel_engine_cs *engine, u32 reg)
+{
+ enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
+ if (wo_registers[i].platform == platform &&
+ wo_registers[i].reg == reg)
+ return true;
+ }
+
+ return false;
+}
+
+static int check_dirty_whitelist(struct i915_gem_context *ctx,
+struct intel_engine_cs *engine)
+{
+ const u32 values[] = {
+ 0x,
+ 0x01010101,
+ 0x10100101,
+ 0x03030303,
+ 0x30300303,
+ 0x05050505,
+ 0x50500505,
+ 0x0f0f0f0f,
+ 0xf00ff00f,
+ 0x10101010,
+ 0xf0f01010,
+ 0x30303030,
+ 0xa0a03030,
+ 0x50505050,
+ 0xc0c05050,
+ 0xf0f0f0f0,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+
[Intel-gfx] [CI] drm/i915/selftests: Check that whitelisted registers are accessible
There is no point in whitelisting a register that the user then cannot
write to, so check the register exists before merging such patches.
v2: Mark SLICE_COMMON_ECO_CHICKEN1 [731c] as write-only
v3: Use different variables for different meanings!
Signed-off-by: Chris Wilson
Cc: Dale B Stimson
Cc: Michał Winiarski
Reviewed-by: Michał Winiarski
Link:
https://patchwork.freedesktop.org/patch/msgid/20190301140404.26690-6-ch...@chris-wilson.co.uk
---
.../drm/i915/selftests/intel_workarounds.c| 378 +-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index e6ffc8ac22dc..e60fc61f2ba5 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -12,6 +12,14 @@
#include "igt_spinner.h"
#include "igt_wedge_me.h"
#include "mock_context.h"
+#include "mock_drm.h"
+
+static const struct wo_register {
+ enum intel_platform platform;
+ u32 reg;
+} wo_registers[] = {
+ { INTEL_GEMINILAKE, 0x731c }
+};
#define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
struct wa_lists {
@@ -74,7 +82,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct
intel_engine_cs *engine)
if (IS_ERR(result))
return result;
- i915_gem_object_set_cache_level(result, I915_CACHE_LLC);
+ i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC);
cs = i915_gem_object_pin_map(result, I915_MAP_WB);
if (IS_ERR(cs)) {
@@ -331,6 +339,373 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
return err;
}
+static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void *ptr;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+
+ ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(ptr)) {
+ err = PTR_ERR(ptr);
+ goto err_obj;
+ }
+ memset(ptr, 0xc5, PAGE_SIZE);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_cpu_domain(obj, false);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static struct i915_vma *create_batch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, 16 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static u32 reg_write(u32 old, u32 new, u32 rsvd)
+{
+ if (rsvd == 0x) {
+ old &= ~(new >> 16);
+ old |= new & (new >> 16);
+ } else {
+ old &= ~rsvd;
+ old |= new & rsvd;
+ }
+
+ return old;
+}
+
+static bool wo_register(struct intel_engine_cs *engine, u32 reg)
+{
+ enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
+ if (wo_registers[i].platform == platform &&
+ wo_registers[i].reg == reg)
+ return true;
+ }
+
+ return false;
+}
+
+static int check_dirty_whitelist(struct i915_gem_context *ctx,
+struct intel_engine_cs *engine)
+{
+ const u32 values[] = {
+ 0x,
+ 0x01010101,
+ 0x10100101,
+ 0x03030303,
+ 0x30300303,
+ 0x05050505,
+ 0x50500505,
+ 0x0f0f0f0f,
+ 0xf00ff00f,
+ 0x10101010,
+ 0xf0f01010,
+ 0x30303030,
+ 0xa0a03030,
+ 0x50505050,
+ 0xc0c05050,
+ 0xf0f0f0f0,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x00ff00ff,
+
Re: [Intel-gfx] [PATCH 14/38] drm/i915: Introduce the i915_user_extension_method
On 01/03/2019 14:03, Chris Wilson wrote:
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we define a new extension
struct that can be linked into the ioctl data only when required by the
user. The key advantage being able to ignore large control structs for
optional interfaces/extensions, while being able to process them in a
consistent manner.
In comparison to other extensible ioctls, the key difference is the
use of a linked chain of extension structs vs an array of tagged
pointers. For example,
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
__u32 length_dw;
__u64 chunk_data;
};
struct drm_amdgpu_cs_in {
__u32 ctx_id;
__u32 bo_list_handle;
__u32 num_chunks;
__u32 _pad;
__u64 chunks;
};
allows userspace to pass in array of pointers to extension structs, but
must therefore keep constructing that array along side the command stream.
In dynamic situations like that, a linked list is preferred and does not
similar from extra cache line misses as the extension structs themselves
must still be loaded separate to the chunks array.
v2: Apply the tail call optimisation directly to nip the worry of stack
overflow in the bud.
v3: Defend against recursion.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_user_extensions.c | 43 +
drivers/gpu/drm/i915/i915_user_extensions.h | 20 ++
drivers/gpu/drm/i915/i915_utils.h | 7
include/uapi/drm/i915_drm.h | 20 ++
5 files changed, 91 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.c
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a1d834068765..89105b1aaf12 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -46,6 +46,7 @@ i915-y := i915_drv.o \
i915_sw_fence.o \
i915_syncmap.o \
i915_sysfs.o \
+ i915_user_extensions.o \
intel_csr.o \
intel_device_info.o \
intel_pm.o \
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.c
b/drivers/gpu/drm/i915/i915_user_extensions.c
new file mode 100644
index ..879b4094b2d7
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.c
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#include "i915_user_extensions.h"
+
+int i915_user_extensions(struct i915_user_extension __user *ext,
+const i915_user_extension_fn *tbl,
+unsigned long count,
+void *data)
+{
+ unsigned int stackdepth = 512;
+
+ while (ext) {
+ int err;
+ u64 x;
+
+ if (!stackdepth--) /* recursion vs useful flexibility */
+ return -EINVAL;
I don't get this. What stack? Did you mean "static unsigned int
stackdepth" in case someone puts i915_user_extension into the extension
table? Or just a limit on number of chained extensions? But you are not
processing the recursively here.
Regards,
Tvrtko
+
+ if (get_user(x, >name))
+ return -EFAULT;
+
+ err = -EINVAL;
+ if (x < count && tbl[x])
+ err = tbl[x](ext, data);
+ if (err)
+ return err;
+
+ if (get_user(x, >next_extension))
+ return -EFAULT;
+
+ ext = u64_to_user_ptr(x);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.h
b/drivers/gpu/drm/i915/i915_user_extensions.h
new file mode 100644
index ..313a510b068a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef I915_USER_EXTENSIONS_H
+#define I915_USER_EXTENSIONS_H
+
+struct i915_user_extension;
+
+typedef int (*i915_user_extension_fn)(struct i915_user_extension __user *ext,
+ void *data);
+
+int i915_user_extensions(struct i915_user_extension __user *ext,
+const i915_user_extension_fn *tbl,
+unsigned long count,
+void *data);
+
+#endif /* I915_USER_EXTENSIONS_H */
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index 9726df37c4c4..fcc751aa1ea8 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@
Re: [Intel-gfx] [PATCH 23/38] drm/i915: Re-arrange execbuf so context is known before engine
On 01/03/2019 14:03, Chris Wilson wrote:
From: Tvrtko Ursulin
Needed for a following patch.
Signed-off-by: Tvrtko Ursulin
I'll do yours, you do mine. Criss-cross. Now that's an oldend but golden
reference. :)
Regards,
Tvrtko
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 07c0af316f86..53d0d70c97fa 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2312,10 +2312,6 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
- eb.engine = eb_select_engine(eb.i915, file, args);
- if (!eb.engine)
- return -EINVAL;
-
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
if (!in_fence)
@@ -2340,6 +2336,12 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_destroy;
+ eb.engine = eb_select_engine(eb.i915, file, args);
+ if (!eb.engine) {
+ err = -EINVAL;
+ goto err_engine;
+ }
+
/*
* Take a local wakeref for preparing to dispatch the execbuf as
* we expect to access the hardware fairly frequently in the
@@ -2505,6 +2507,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
mutex_unlock(>struct_mutex);
err_rpm:
intel_runtime_pm_put(eb.i915, wakeref);
+err_engine:
i915_gem_context_put(eb.ctx);
err_destroy:
eb_destroy();
___
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Re: [Intel-gfx] [PATCH 21/38] drm/i915: Fix I915_EXEC_RING_MASK
On 01/03/2019 14:03, Chris Wilson wrote:
This was supposed to be a mask of all known rings, but it is being used
by execbuffer to filter out invalid rings, and so is instead mapping high
unused values onto valid rings. Instead of a mask of all known rings,
we need it to be the mask of all possible rings.
Fixes: 549f7365820a ("drm/i915: Enable SandyBridge blitter ring")
Fixes: de1add360522 ("drm/i915: Decouple execbuf uAPI from internal
implementation")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: # v4.6+
---
include/uapi/drm/i915_drm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 60cbb2e4f140..4e59cc87527b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1004,7 +1004,7 @@ struct drm_i915_gem_execbuffer2 {
* struct drm_i915_gem_exec_fence *fences.
*/
__u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK (7<<0)
+#define I915_EXEC_RING_MASK (0x3f)
#define I915_EXEC_DEFAULT(0<<0)
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD(2<<0)
Easy pickings first.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 06/38] drm/i915/selftests: Check that whitelisted registers are accessible
Quoting Michał Winiarski (2019-03-01 15:18:58)
> On Fri, Mar 01, 2019 at 02:03:32PM +, Chris Wilson wrote:
> > +static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
> > +{
> > + struct drm_i915_gem_object *obj;
> > + struct i915_vma *vma;
> > + void *ptr;
> > + int err;
> > +
> > + obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
> > + if (IS_ERR(obj))
> > + return ERR_CAST(obj);
> > +
> > + i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
>
> Check return value.
Can't fail, but transform it into set_coherency which is void so you
can't complain :-p
> > + ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
> > + if (IS_ERR(ptr)) {
> > + err = PTR_ERR(ptr);
> > + goto err_obj;
> > + }
> > + memset(ptr, 0xc5, PAGE_SIZE);
> > + i915_gem_object_unpin_map(obj);
> > +
> > + vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
> > + if (IS_ERR(vma)) {
> > + err = PTR_ERR(vma);
> > + goto err_obj;
> > + }
> > +
> > + err = i915_vma_pin(vma, 0, 0, PIN_USER);
> > + if (err)
> > + goto err_obj;
> > +
> > + err = i915_gem_object_set_to_cpu_domain(obj, false);
> > + if (err)
> > + goto err_obj;
> > +
> > + return vma;
> > +
> > +err_obj:
> > + i915_gem_object_put(obj);
> > + return ERR_PTR(err);
> > +}
> > +
[more snip]
> > + if (wo_register(engine, reg))
> > + continue;
> > +
> > + srm = MI_STORE_REGISTER_MEM;
> > + lrm = MI_LOAD_REGISTER_MEM;
> > + if (INTEL_GEN(ctx->i915) >= 8)
> > + lrm++, srm++;
> > +
> > + pr_debug("%s: Writing garbage to %x {srm=0x%08x,
> > lrm=0x%08x}\n",
> > + engine->name, reg, srm, lrm);
>
> Why are we printing opcodes (srm/lrm)?
In a debug, can you guess? Because despite making a lrm variable I used
MI_LRM later on and spent a few runs wondering why the GPU kept hanging
with the wrong opcode. Consider it gone.
> > + cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
> > + if (IS_ERR(cs)) {
> > + err = PTR_ERR(cs);
> > + goto out_batch;
> > + }
>
> We're already using cs for batch! Extra pointer pls.
Will someone think of the poor electrons! Or is more, jobs for all!
> > +
> > + GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0x);
> > + rsvd = cs[ARRAY_SIZE(values)]; /* detect write masking */
>
> So we're writing 0x to get the mask. And there's a comment. And it
> will
> explode if someone changes the last value.
>
> Reviewed-by: Michał Winiarski
It'll do for now, there's a bit more I think we can improve on, but
incremental steps.
-Chris
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Re: [Intel-gfx] [PATCH 10/38] drm/i915: Store the BIT(engine->id) as the engine's mask
On 01/03/2019 14:03, Chris Wilson wrote:
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 39 +++
drivers/gpu/drm/i915/i915_reset.c | 8 ++--
drivers/gpu/drm/i915/intel_device_info.c | 6 +--
drivers/gpu/drm/i915/intel_device_info.h | 6 +--
drivers/gpu/drm/i915/intel_engine_cs.c| 15 ---
drivers/gpu/drm/i915/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 8 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 11 ++
.../gpu/drm/i915/selftests/i915_gem_context.c | 6 +--
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_guc.c| 4 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 4 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c| 4 +-
.../drm/i915/selftests/intel_workarounds.c| 2 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
19 files changed, 75 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf325a00d143..0dd680cdb9ce 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2099,7 +2099,7 @@ static inline struct drm_i915_private *huc_to_i915(struct
intel_huc *huc)
/* Iterator over subset of engines selected by mask */
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
- for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
+ for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
(tmp__) ? \
((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
0;)
@@ -2432,7 +2432,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define ALL_ENGINES (~0)
#define HAS_ENGINE(dev_priv, id) \
- (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
+ (!!(INTEL_INFO(dev_priv)->engine_mask & ENGINE_MASK(id)))
#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)HAS_ENGINE(dev_priv, VCS2)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7e79691664e5..99022738cc89 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -798,7 +798,7 @@ static void gen8_initialize_pml4(struct i915_address_space
*vm,
*/
static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
{
- ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->ring_mask;
+ ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->engine_mask;
Could rename pd_dirty_rings as well.
}
/* Removes entries from a single page table, releasing it if it's empty.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a9211c370cd1..524f55771f23 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -94,7 +94,7 @@
.gpu_reset_clobbers_display = true, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .ring_mask = RENDER_RING, \
+ .engine_mask = RENDER_RING, \
What RENDER_*RING* & co, while we are churning?
Could we use the not-much-remaining-used ENGINE_MASK in here? Like:
.engine_mask = ENGINE(RCS) | .. ;
.has_snoop = true, \
.has_coherent_ggtt = false, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -133,7 +133,7 @@ static const struct intel_device_info intel_i865g_info = {
.num_pipes = 2, \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
- .ring_mask = RENDER_RING, \
+ .engine_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -210,7 +210,7 @@ static const struct intel_device_info intel_pineview_info =
{
.display.has_hotplug = 1, \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
- .ring_mask = RENDER_RING, \
+ .engine_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -239,7 +239,7 @@ static const struct intel_device_info intel_i965gm_info = {
static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
- .ring_mask = RENDER_RING | BSD_RING,
+ .engine_mask = RENDER_RING | BSD_RING,
.gpu_reset_clobbers_display =
Re: [Intel-gfx] [PATCH 06/38] drm/i915/selftests: Check that whitelisted registers are accessible
On Fri, Mar 01, 2019 at 02:03:32PM +, Chris Wilson wrote:
> There is no point in whitelisting a register that the user then cannot
> write to, so check the register exists before merging such patches.
>
> v2: Mark SLICE_COMMON_ECO_CHICKEN1 [731c] as write-only
>
> Signed-off-by: Chris Wilson
> Cc: Dale B Stimson
> Cc: Michał Winiarski
> ---
> .../drm/i915/selftests/intel_workarounds.c| 376 ++
> 1 file changed, 376 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> index e6ffc8ac22dc..33b3ced83fde 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> @@ -12,6 +12,14 @@
> #include "igt_spinner.h"
> #include "igt_wedge_me.h"
> #include "mock_context.h"
> +#include "mock_drm.h"
> +
> +static const struct wo_register {
> + enum intel_platform platform;
> + u32 reg;
> +} wo_registers[] = {
> + { INTEL_GEMINILAKE, 0x731c }
> +};
>
> #define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
> struct wa_lists {
> @@ -331,6 +339,373 @@ static int check_whitelist_across_reset(struct
> intel_engine_cs *engine,
> return err;
> }
>
> +static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
> +{
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + void *ptr;
> + int err;
> +
> + obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
> + i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
Check return value.
> +
> + ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + if (IS_ERR(ptr)) {
> + err = PTR_ERR(ptr);
> + goto err_obj;
> + }
> + memset(ptr, 0xc5, PAGE_SIZE);
> + i915_gem_object_unpin_map(obj);
> +
> + vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
> + if (IS_ERR(vma)) {
> + err = PTR_ERR(vma);
> + goto err_obj;
> + }
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_USER);
> + if (err)
> + goto err_obj;
> +
> + err = i915_gem_object_set_to_cpu_domain(obj, false);
> + if (err)
> + goto err_obj;
> +
> + return vma;
> +
> +err_obj:
> + i915_gem_object_put(obj);
> + return ERR_PTR(err);
> +}
> +
[SNIP]
> +static int check_dirty_whitelist(struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine)
> +{
> + const u32 values[] = {
> + 0x,
> + 0x01010101,
> + 0x10100101,
> + 0x03030303,
> + 0x30300303,
> + 0x05050505,
> + 0x50500505,
> + 0x0f0f0f0f,
> + 0xf00ff00f,
> + 0x10101010,
> + 0xf0f01010,
> + 0x30303030,
> + 0xa0a03030,
> + 0x50505050,
> + 0xc0c05050,
> + 0xf0f0f0f0,
> + 0x,
> + 0x,
> + 0x,
> + 0x,
> + 0x00ff00ff,
> + 0xffff,
> + 0x00ff,
> + 0x,
> + };
> + struct i915_vma *scratch;
> + struct i915_vma *batch;
> + int err = 0, i, v;
> + u32 *cs;
> +
> + scratch = create_scratch(ctx);
> + if (IS_ERR(scratch))
> + return PTR_ERR(scratch);
> +
> + batch = create_batch(ctx);
> + if (IS_ERR(batch)) {
> + err = PTR_ERR(batch);
> + goto out_scratch;
> + }
> +
> + for (i = 0; i < engine->whitelist.count; i++) {
> + u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
> + u64 addr = scratch->node.start;
> + struct i915_request *rq;
> + u32 srm, lrm, rsvd;
> + u32 expect;
> + int idx;
> +
> + if (wo_register(engine, reg))
> + continue;
> +
> + srm = MI_STORE_REGISTER_MEM;
> + lrm = MI_LOAD_REGISTER_MEM;
> + if (INTEL_GEN(ctx->i915) >= 8)
> + lrm++, srm++;
> +
> + pr_debug("%s: Writing garbage to %x {srm=0x%08x, lrm=0x%08x}\n",
> + engine->name, reg, srm, lrm);
Why are we printing opcodes (srm/lrm)?
> +
> + cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
> + if (IS_ERR(cs)) {
> + err = PTR_ERR(cs);
> + goto out_batch;
> + }
> +
> + /* SRM original */
> + *cs++ = srm;
> + *cs++ = reg;
> + *cs++ = lower_32_bits(addr);
> + *cs++ = upper_32_bits(addr);
> +
> + idx = 1;
> + for (v = 0; v < ARRAY_SIZE(values); v++) {
> + /* LRI garbage */
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ =
Re: [Intel-gfx] [PATCH 03/11] drm/i915/execlists: Suppress redundant preemption
Quoting Tvrtko Ursulin (2019-03-01 15:07:58)
>
> On 01/03/2019 11:36, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-03-01 11:31:26)
> >>
> >> ping on below
> >>
> >> On 28/02/2019 13:11, Tvrtko Ursulin wrote:
> >>>
> >>> On 26/02/2019 10:23, Chris Wilson wrote:
> On unwinding the active request we give it a small (limited to internal
> priority levels) boost to prevent it from being gazumped a second time.
> However, this means that it can be promoted to above the request that
> triggered the preemption request, causing a preempt-to-idle cycle for no
> change. We can avoid this if we take the boost into account when
> checking if the preemption request is valid.
>
> v2: After preemption the active request will be after the preemptee if
> they end up with equal priority.
>
> v3: Tvrtko pointed out that this, the existing logic, makes
> I915_PRIORITY_WAIT non-preemptible. Document this interesting quirk!
>
> v4: Prove Tvrtko was right about WAIT being non-preemptible and test it.
> v5: Except not all priorities were made equal, and the WAIT not
> preempting
> is only if we start off as !NEWCLIENT.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 38
> 1 file changed, 34 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 0e20f3bc8210..dba19baf6808 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -164,6 +164,8 @@
> #define WA_TAIL_DWORDS 2
> #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
> +#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
> +
> static int execlists_context_deferred_alloc(struct i915_gem_context
> *ctx,
> struct intel_engine_cs *engine,
> struct intel_context *ce);
> @@ -190,8 +192,30 @@ static inline int rq_prio(const struct
> i915_request *rq)
> static int effective_prio(const struct i915_request *rq)
> {
> + int prio = rq_prio(rq);
> +
> + /*
> + * On unwinding the active request, we give it a priority bump
> + * equivalent to a freshly submitted request. This protects it from
> + * being gazumped again, but it would be preferable if we didn't
> + * let it be gazumped in the first place!
> + *
> + * See __unwind_incomplete_requests()
> + */
> + if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
> + /*
> + * After preemption, we insert the active request at the
> + * end of the new priority level. This means that we will be
> + * _lower_ priority than the preemptee all things equal (and
> + * so the preemption is valid), so adjust our comparison
> + * accordingly.
> + */
> + prio |= ACTIVE_PRIORITY;
> + prio--;
> + }
> +
> /* Restrict mere WAIT boosts from triggering preemption */
> - return rq_prio(rq) | __NO_PREEMPTION;
> + return prio | __NO_PREEMPTION;
> }
> static int queue_prio(const struct intel_engine_execlists *execlists)
> @@ -359,7 +383,7 @@ __unwind_incomplete_requests(struct
> intel_engine_cs *engine)
> {
> struct i915_request *rq, *rn, *active = NULL;
> struct list_head *uninitialized_var(pl);
> - int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
> + int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
> lockdep_assert_held(>timeline.lock);
> @@ -390,9 +414,15 @@ __unwind_incomplete_requests(struct
> intel_engine_cs *engine)
> * The active request is now effectively the start of a new client
> * stream, so give it the equivalent small priority bump to
> prevent
> * it being gazumped a second time by another peer.
> + *
> + * One consequence of this preemption boost is that we may jump
> + * over lesser priorities (such as I915_PRIORITY_WAIT), effectively
> + * making those priorities non-preemptible. They will be moved
> forward
> >>>
> >>> After the previous patch wait priority is non-preemptible by definition
> >>> making this suggestion preemption boost is making it so not accurate.
> >>>
> + * in the priority queue, but they will not gain immediate access to
> + * the GPU.
> */
> - if (!(prio & I915_PRIORITY_NEWCLIENT)) {
> - prio |= I915_PRIORITY_NEWCLIENT;
> + if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
> >>>
> >>> What is the importance of the has_started
Re: [Intel-gfx] [PATCH 05/38] drm/i915: Prioritise non-busywait semaphore workloads
On 01/03/2019 14:03, Chris Wilson wrote:
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately. We then also have to be careful that we don't give earlier
semaphores an accidental boost because later work doesn't wait on other
rings, hence we keep a history of semaphore usage of the dependency chain.
v2: Stop rolling the bits into a chain and just use a flag in case this
request or any of our dependencies use a semaphore. The rolling around
was contagious as Tvrtko was heard to fall off his chair.
Testcase: igt/gem_exec_schedule/semaphore
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 16
drivers/gpu/drm/i915/i915_scheduler.c | 6 ++
drivers/gpu/drm/i915/i915_scheduler.h | 9 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 59e30b8c4ee9..bcf3c1a155e2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -813,6 +813,7 @@ emit_semaphore_wait(struct i915_request *to,
*cs++ = 0;
intel_ring_advance(to, cs);
+ to->sched.flags |= I915_SCHED_HAS_SEMAPHORE;
return 0;
}
@@ -1083,6 +1084,21 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ /*
+* Boost actual workloads past semaphores!
+*
+* With semaphores we spin on one engine waiting for another,
+* simply to reduce the latency of starting our work when
+* the signaler completes. However, if there is any other
+* work that we could be doing on this engine instead, that
+* is better utilisation and will reduce the overall duration
+* of the current work. To avoid PI boosting a semaphore
+* far in the distance past over useful work, we keep a history
+* of any semaphore use along our dependency chain.
+*/
+ if (!(request->sched.flags & I915_SCHED_HAS_SEMAPHORE))
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 50018ad30233..8a64748a7912 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -39,6 +39,7 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(>waiters_list);
INIT_LIST_HEAD(>link);
node->attr.priority = I915_PRIORITY_INVALID;
+ node->flags = 0;
}
static struct i915_dependency *
@@ -69,6 +70,11 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node
*node,
dep->signaler = signal;
dep->flags = flags;
+ /* Keep track of whether anyone on this chain has a semaphore */
+ if (signal->flags & I915_SCHED_HAS_SEMAPHORE &&
+ !node_started(signal))
+ node->flags |= I915_SCHED_HAS_SEMAPHORE;
+
ret = true;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 7d4a49750d92..6ce450cf63fa 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
@@ -74,6 +75,8 @@ struct i915_sched_node {
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
struct i915_sched_attr attr;
+ unsigned int flags;
+#define I915_SCHED_HAS_SEMAPHORE BIT(0)
};
struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 53d6f7fdb50e..2268860cca44 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) *
Re: [Intel-gfx] [PATCH 04/38] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
On 01/03/2019 14:03, Chris Wilson wrote:
Having introduced per-context seqno, we now have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
As might be reasonably expected, HW semaphores excel in inter-engine
synchronisation microbenchmarks (where the 3x reduced latency / increased
throughput more than offset the power cost of spinning on a second ring)
and have significant improvement (can be up to ~10%, most see no change)
for single clients that utilize multiple engines (typically media players
and transcoders), without regressing multiple clients that can saturate
the system or changing the power envelope dramatically.
v3: Drop the older NEQ branch, now we pin the signaler's HWSP anyway.
v4: Tell the world and include it as part of scheduler caps.
Testcase: igt/gem_exec_whisper
Testcase: igt/benchmarks/gem_wsim
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 138 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 9 +-
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ++
include/uapi/drm/i915_drm.h | 1 +
10 files changed, 160 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c6354f6cdbdb..c08abdef5eb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -351,7 +351,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = 0;
+ value = !!(dev_priv->caps.scheduler &
I915_SCHEDULER_CAP_SEMAPHORES);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index d354967d6ae8..59e30b8c4ee9 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -32,9 +33,16 @@
#include "i915_active.h"
#include "i915_reset.h"
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
static struct i915_global_request {
struct kmem_cache *slab_requests;
struct kmem_cache *slab_dependencies;
+ struct kmem_cache *slab_execute_cbs;
} global;
static const char *i915_fence_get_driver_name(struct dma_fence *fence)
@@ -325,6 +333,69 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kmem_cache_free(global.slab_execute_cbs, cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(>lock);
+
+ if (list_empty(>execute_cb))
+ return;
+
+ list_for_each_entry(cb, >execute_cb, link)
+ irq_work_queue(>work);
+
+ /*
+* XXX Rollback on __i915_request_unsubmit()
+*
+* In the future, perhaps when we have an active time-slicing scheduler,
+* it will be interesting to unsubmit parallel execution and remove
+* busywaits from the GPU until their master is restarted. This is
+* quite hairy, we have to carefully rollback the fence and do a
+* preempt-to-idle cycle on the target engine, all the while the
+* master execute_cb may refire.
+*/
+ INIT_LIST_HEAD(>execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+
+ if
Re: [Intel-gfx] [PATCH 02/38] drm/i915: Introduce i915_timeline.mutex
On 01/03/2019 14:03, Chris Wilson wrote:
A simple mutex used for guarding the flow of requests in and out of the
timeline. In the short-term, it will be used only to guard the addition
of requests into the timeline, taken on alloc and released on commit so
that only one caller can construct a request into the timeline
(important as the seqno and ring pointers must be serialised). This will
be used by observers to ensure that the seqno/hwsp is stable. Later,
when we have reduced retiring to only operate on a single timeline at a
time, we can then use the mutex as the sole guard required for retiring.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c| 6 +-
drivers/gpu/drm/i915/i915_timeline.c | 1 +
drivers/gpu/drm/i915/i915_timeline.h | 2 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 4 +---
drivers/gpu/drm/i915/selftests/mock_timeline.c | 1 +
5 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index c65f6c990fdd..719d1a5ab082 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -563,6 +563,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
return ERR_CAST(ce);
reserve_gt(i915);
+ mutex_lock(>ring->timeline->mutex);
/* Move our oldest request to the slab-cache (if not in use!) */
rq = list_first_entry(>ring->request_list, typeof(*rq), ring_link);
@@ -688,6 +689,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
+ mutex_unlock(>ring->timeline->mutex);
unreserve_gt(i915);
intel_context_unpin(ce);
return ERR_PTR(ret);
@@ -880,7 +882,7 @@ void i915_request_add(struct i915_request *request)
GEM_TRACE("%s fence %llx:%lld\n",
engine->name, request->fence.context, request->fence.seqno);
- lockdep_assert_held(>i915->drm.struct_mutex);
+ lockdep_assert_held(>timeline->mutex);
trace_i915_request_add(request);
/*
@@ -991,6 +993,8 @@ void i915_request_add(struct i915_request *request)
*/
if (prev && i915_request_completed(prev))
i915_request_retire_upto(prev);
+
+ mutex_unlock(>timeline->mutex);
}
static unsigned long local_clock_us(unsigned int *cpu)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index b2202d2e58a2..87a80558da28 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -162,6 +162,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
timeline->fence_context = dma_fence_context_alloc(1);
spin_lock_init(>lock);
+ mutex_init(>mutex);
INIT_ACTIVE_REQUEST(>barrier);
INIT_ACTIVE_REQUEST(>last_request);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index 7bec7d2e45bf..36c3849f7108 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -44,6 +44,8 @@ struct i915_timeline {
#define TIMELINE_CLIENT 0 /* default subclass */
#define TIMELINE_ENGINE 1
+ struct mutex mutex; /* protects the flow of requests */
+
unsigned int pin_count;
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 7da52e3d67af..7e1b65b8eb19 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -141,14 +141,12 @@ static int igt_fence_wait(void *arg)
err = -ENOMEM;
goto out_locked;
}
- mutex_unlock(>drm.struct_mutex); /* safe as we are single user */
if (dma_fence_wait_timeout(>fence, false, T) != -ETIME) {
pr_err("fence wait success before submit (expected
timeout)!\n");
- goto out_device;
+ goto out_locked;
}
- mutex_lock(>drm.struct_mutex);
i915_request_add(request);
mutex_unlock(>drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index d2de9ece2118..416d85233263 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -14,6 +14,7 @@ void mock_timeline_init(struct i915_timeline *timeline, u64
context)
timeline->fence_context = context;
spin_lock_init(>lock);
+ mutex_init(>mutex);
INIT_ACTIVE_REQUEST(>barrier);
INIT_ACTIVE_REQUEST(>last_request);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 03/11] drm/i915/execlists: Suppress redundant preemption
On 01/03/2019 11:36, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-03-01 11:31:26)
ping on below
On 28/02/2019 13:11, Tvrtko Ursulin wrote:
On 26/02/2019 10:23, Chris Wilson wrote:
On unwinding the active request we give it a small (limited to internal
priority levels) boost to prevent it from being gazumped a second time.
However, this means that it can be promoted to above the request that
triggered the preemption request, causing a preempt-to-idle cycle for no
change. We can avoid this if we take the boost into account when
checking if the preemption request is valid.
v2: After preemption the active request will be after the preemptee if
they end up with equal priority.
v3: Tvrtko pointed out that this, the existing logic, makes
I915_PRIORITY_WAIT non-preemptible. Document this interesting quirk!
v4: Prove Tvrtko was right about WAIT being non-preemptible and test it.
v5: Except not all priorities were made equal, and the WAIT not
preempting
is only if we start off as !NEWCLIENT.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 38
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
b/drivers/gpu/drm/i915/intel_lrc.c
index 0e20f3bc8210..dba19baf6808 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,6 +164,8 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+
static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx,
struct intel_engine_cs *engine,
struct intel_context *ce);
@@ -190,8 +192,30 @@ static inline int rq_prio(const struct
i915_request *rq)
static int effective_prio(const struct i915_request *rq)
{
+ int prio = rq_prio(rq);
+
+ /*
+ * On unwinding the active request, we give it a priority bump
+ * equivalent to a freshly submitted request. This protects it from
+ * being gazumped again, but it would be preferable if we didn't
+ * let it be gazumped in the first place!
+ *
+ * See __unwind_incomplete_requests()
+ */
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
+ /*
+ * After preemption, we insert the active request at the
+ * end of the new priority level. This means that we will be
+ * _lower_ priority than the preemptee all things equal (and
+ * so the preemption is valid), so adjust our comparison
+ * accordingly.
+ */
+ prio |= ACTIVE_PRIORITY;
+ prio--;
+ }
+
/* Restrict mere WAIT boosts from triggering preemption */
- return rq_prio(rq) | __NO_PREEMPTION;
+ return prio | __NO_PREEMPTION;
}
static int queue_prio(const struct intel_engine_execlists *execlists)
@@ -359,7 +383,7 @@ __unwind_incomplete_requests(struct
intel_engine_cs *engine)
{
struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
+ int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
lockdep_assert_held(>timeline.lock);
@@ -390,9 +414,15 @@ __unwind_incomplete_requests(struct
intel_engine_cs *engine)
* The active request is now effectively the start of a new client
* stream, so give it the equivalent small priority bump to prevent
* it being gazumped a second time by another peer.
+ *
+ * One consequence of this preemption boost is that we may jump
+ * over lesser priorities (such as I915_PRIORITY_WAIT), effectively
+ * making those priorities non-preemptible. They will be moved
forward
After the previous patch wait priority is non-preemptible by definition
making this suggestion preemption boost is making it so not accurate.
+ * in the priority queue, but they will not gain immediate access to
+ * the GPU.
*/
- if (!(prio & I915_PRIORITY_NEWCLIENT)) {
- prio |= I915_PRIORITY_NEWCLIENT;
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
What is the importance of the has_started check? Hasn't the active
request been running by definition?
No. Semaphores. This is all about defending against incorrect promotion
while a request is still spinning on its dependencies (or else we get
promoted above them and PI is broken).
Is init_breadcrumb after the semaphore, ie. __i915_request_has_started
will be false while spinning on the semaphore. That possibly makes
sense.. But you know what I'll say next. It is extremely subtle and
sprinkled over the code so here we definitely need a comment explaining it.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 12/17] drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Hi Marteen,
On Fri, Mar 01, 2019 at 03:47:02PM +0100, Maarten Lankhorst wrote:
> Op 01-03-2019 om 15:36 schreef Laurent Pinchart:
> > On Fri, Mar 01, 2019 at 03:08:20PM +0100, Maarten Lankhorst wrote:
> >> Op 01-03-2019 om 14:13 schreef Laurent Pinchart:
> >>> On Fri, Mar 01, 2019 at 01:56:22PM +0100, Maarten Lankhorst wrote:
> Convert rcar-du to using __drm_atomic_helper_crtc_reset(), instead of
> writing its own version. Instead of open coding destroy_state(), call
> it directly for freeing the old state.
> >>> I don't think the second sentence applies to this patch.
> >>>
> Signed-off-by: Maarten Lankhorst
> Cc: Laurent Pinchart
> Cc: Kieran Bingham
> Cc: linux-renesas-...@vger.kernel.org
> ---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 +++
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 4cdea14d552f..7766551e67fc 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -891,22 +891,17 @@ static void rcar_du_crtc_cleanup(struct drm_crtc
> *crtc)
>
> static void rcar_du_crtc_reset(struct drm_crtc *crtc)
> {
> -struct rcar_du_crtc_state *state;
> +struct rcar_du_crtc_state *state = kzalloc(sizeof(*state),
> GFP_KERNEL);
>
> -if (crtc->state) {
> +if (crtc->state)
> rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
> -crtc->state = NULL;
> -}
>
> -state = kzalloc(sizeof(*state), GFP_KERNEL);
> +__drm_atomic_helper_crtc_reset(crtc, >state);
> >>> state may be NULL here if the above kzalloc() failed. Let's keep the
> >>> original order of the function, and simply call
> >>> __drm_atomic_helper_crtc_reset() after the NULL check below.
> >> There were 10 different ways crtc was implemented, I felt it was good to
> >> settle on one.
> >>
> >> We don't handle during reset at all, would need to start propagating this
> >> first before we should handle errors, imho.
> > That's not the point. As state can be NULL, you could end up
> > dereferencing a NULL pointer. The fact that the base state is the first
> > field in the rcar_du_crtc_state structure is just luck, and shouldn't be
> > relied on.
>
> Would it be ok if I changed it to state ? >state : NULL and let
> the compiler deal with it?
What's wrong with a proper implementation ?
static void rcar_du_crtc_reset(struct drm_crtc *crtc)
{
struct rcar_du_crtc_state *state;
if (crtc->state) {
rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
crtc->state = NULL;
}
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (state == NULL)
return;
__drm_atomic_helper_crtc_reset(crtc, >state);
state->crc.source = VSP1_DU_CRC_NONE;
state->crc.index = 0;
}
> Will probably fix up all other patches as well before committing.
You won't commit this one before I ack it, right ? :-)
> >> Looking more closely, it's the same way that errors in
> >> rcar_du_plane_reset() are handled. :)
> > It's not, the return value of kzalloc() is checked explicitly in
> > rcar_du_plane_reset() before calling __drm_atomic_helper_plane_reset().
> > Please copy the code flow of rcar_du_plane_reset() to implement
> > rcar_du_crtc_reset().
--
Regards,
Laurent Pinchart
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Re: [Intel-gfx] [PATCH 12/17] drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Op 01-03-2019 om 15:36 schreef Laurent Pinchart:
> Hi Marteen,
>
> On Fri, Mar 01, 2019 at 03:08:20PM +0100, Maarten Lankhorst wrote:
>> Op 01-03-2019 om 14:13 schreef Laurent Pinchart:
>>> On Fri, Mar 01, 2019 at 01:56:22PM +0100, Maarten Lankhorst wrote:
Convert rcar-du to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding destroy_state(), call
it directly for freeing the old state.
>>> I don't think the second sentence applies to this patch.
>>>
Signed-off-by: Maarten Lankhorst
Cc: Laurent Pinchart
Cc: Kieran Bingham
Cc: linux-renesas-...@vger.kernel.org
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 4cdea14d552f..7766551e67fc 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -891,22 +891,17 @@ static void rcar_du_crtc_cleanup(struct drm_crtc
*crtc)
static void rcar_du_crtc_reset(struct drm_crtc *crtc)
{
- struct rcar_du_crtc_state *state;
+ struct rcar_du_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (crtc->state) {
+ if (crtc->state)
rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
- crtc->state = NULL;
- }
- state = kzalloc(sizeof(*state), GFP_KERNEL);
+ __drm_atomic_helper_crtc_reset(crtc, >state);
>>> state may be NULL here if the above kzalloc() failed. Let's keep the
>>> original order of the function, and simply call
>>> __drm_atomic_helper_crtc_reset() after the NULL check below.
>> There were 10 different ways crtc was implemented, I felt it was good to
>> settle on one.
>>
>> We don't handle during reset at all, would need to start propagating this
>> first before we should handle errors, imho.
> That's not the point. As state can be NULL, you could end up
> dereferencing a NULL pointer. The fact that the base state is the first
> field in the rcar_du_crtc_state structure is just luck, and shouldn't be
> relied on.
Would it be ok if I changed it to state ? >state : NULL and let the
compiler deal with it?
Will probably fix up all other patches as well before committing.
>> Looking more closely, it's the same way that errors in
>> rcar_du_plane_reset() are handled. :)
> It's not, the return value of kzalloc() is checked explicitly in
> rcar_du_plane_reset() before calling __drm_atomic_helper_plane_reset().
> Please copy the code flow of rcar_du_plane_reset() to implement
> rcar_du_crtc_reset().
>
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Re: [Intel-gfx] [PATCH 12/17] drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Hi Marteen,
On Fri, Mar 01, 2019 at 03:08:20PM +0100, Maarten Lankhorst wrote:
> Op 01-03-2019 om 14:13 schreef Laurent Pinchart:
> > On Fri, Mar 01, 2019 at 01:56:22PM +0100, Maarten Lankhorst wrote:
> >> Convert rcar-du to using __drm_atomic_helper_crtc_reset(), instead of
> >> writing its own version. Instead of open coding destroy_state(), call
> >> it directly for freeing the old state.
> > I don't think the second sentence applies to this patch.
> >
> >> Signed-off-by: Maarten Lankhorst
> >> Cc: Laurent Pinchart
> >> Cc: Kieran Bingham
> >> Cc: linux-renesas-...@vger.kernel.org
> >> ---
> >> drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 +++
> >> 1 file changed, 3 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> >> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> >> index 4cdea14d552f..7766551e67fc 100644
> >> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> >> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> >> @@ -891,22 +891,17 @@ static void rcar_du_crtc_cleanup(struct drm_crtc
> >> *crtc)
> >>
> >> static void rcar_du_crtc_reset(struct drm_crtc *crtc)
> >> {
> >> - struct rcar_du_crtc_state *state;
> >> + struct rcar_du_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
> >>
> >> - if (crtc->state) {
> >> + if (crtc->state)
> >>rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
> >> - crtc->state = NULL;
> >> - }
> >>
> >> - state = kzalloc(sizeof(*state), GFP_KERNEL);
> >> + __drm_atomic_helper_crtc_reset(crtc, >state);
> >
> > state may be NULL here if the above kzalloc() failed. Let's keep the
> > original order of the function, and simply call
> > __drm_atomic_helper_crtc_reset() after the NULL check below.
>
> There were 10 different ways crtc was implemented, I felt it was good to
> settle on one.
>
> We don't handle during reset at all, would need to start propagating this
> first before we should handle errors, imho.
That's not the point. As state can be NULL, you could end up
dereferencing a NULL pointer. The fact that the base state is the first
field in the rcar_du_crtc_state structure is just luck, and shouldn't be
relied on.
> Looking more closely, it's the same way that errors in
> rcar_du_plane_reset() are handled. :)
It's not, the return value of kzalloc() is checked explicitly in
rcar_du_plane_reset() before calling __drm_atomic_helper_plane_reset().
Please copy the code flow of rcar_du_plane_reset() to implement
rcar_du_crtc_reset().
--
Regards,
Laurent Pinchart
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/38] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [01/38] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57427/ State : success == Summary == CI Bug Log - changes from CI_DRM_5676 -> Patchwork_12343 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57427/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12343 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_contexts: - fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: SKIP [fdo#109271] -> PASS * igt@i915_pm_rpm@basic-rte: - fi-bsw-kefka: FAIL [fdo#108800] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 Participating hosts (44 -> 38) -- Additional (2): fi-icl-u2 fi-pnv-d510 Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_5676 -> Patchwork_12343 CI_DRM_5676: 3911a5d7d3de6d8e491868bb0cd506346131d71b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12343: 800b0544e5143742e54cbcab646cdbd525895733 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 800b0544e514 drm/i915/execlists: Skip direct submission if only lite-restore 3b2bef0b3c17 drm/i915/selftests: Check preemption support on each engine 7988f06b0790 drm/i915: Allow specification of parallel execbuf 43190fadc3e7 drm/i915/execlists: Virtual engine bonding eb7f9c7d8fed drm/i915: Extend execution fence to support a callback 9a20e5c80942 drm/i915: Load balancing across a virtual engine 6ccc7beebb9c drm/i915: Introduce intel_context.pin_mutex for pin management b8e8c0a9719d drm/i915: Track the pinned kernel contexts on each engine 631bd21a494b drm/i915: Make context pinning part of intel_context_ops b2525b1af2fa drm/i915: Move over to intel_context_lookup() c34e28878e18 drm/i915: Store the intel_context_ops in the intel_engine_cs 53195d9716e1 drm/i915: Split struct intel_context definition to its own header ae2d6298740e drm/i915: Pass around the intel_context 40e466b00076 drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[] 481ec94ce3cc drm/i915: Allow a context to define its set of engines fa712cd9fcd4 drm/i915: Re-arrange execbuf so context is known before engine e7c03aa42717 drm/i915: Remove last traces of exec-id (GEM_BUSY) 5aae2005f1de drm/i915: Fix I915_EXEC_RING_MASK 4b3dbd308a4d drm/i915: Allow userspace to clone contexts on creation 2e12e535df62 drm/i915: Allow contexts to share a single timeline across all engines efcf633f1dbb drm/i915: Extend CONTEXT_CREATE to set parameters upon construction f8ec2c8c0830
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/38] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [01/38] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57427/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Suppress redundant preemption Okay! Commit: drm/i915: Introduce i915_timeline.mutex Okay! Commit: drm/i915: Keep timeline HWSP allocated until idle across the system Okay! Commit: drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ -O:drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) Commit: drm/i915: Prioritise non-busywait semaphore workloads Okay! Commit: drm/i915/selftests: Check that whitelisted registers are accessible Okay! Commit: drm/i915: Force GPU idle on suspend Okay! Commit: drm/i915/selftests: Improve switch-to-kernel-context checking Okay! Commit: drm/i915: Do a synchronous switch-to-kernel-context on idling Okay! Commit: drm/i915: Store the BIT(engine->id) as the engine's mask Okay! Commit: drm/i915: Refactor common code to load initial power context Okay! Commit: drm/i915: Reduce presumption of request ordering for barriers -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) Commit: drm/i915: Remove has-kernel-context Okay! Commit: drm/i915: Introduce the i915_user_extension_method Okay! Commit: drm/i915: Track active engines within a context Okay! Commit: drm/i915: Introduce a context barrier callback Okay! Commit: drm/i915: Create/destroy VM (ppGTT) for use with contexts -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:1134:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:1134:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1264:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1264:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:564:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:564:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:568:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:568:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:689:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:689:33: warning: expression using sizeof(void) Commit: drm/i915: Extend CONTEXT_CREATE to set parameters upon construction Okay! Commit: drm/i915: Allow contexts to share a single timeline across all engines Okay! Commit: drm/i915: Allow userspace to clone contexts on creation Okay! Commit: drm/i915: Fix I915_EXEC_RING_MASK Okay! Commit: drm/i915: Remove last traces of exec-id (GEM_BUSY) Okay! Commit: drm/i915: Re-arrange execbuf so context is known before engine Okay! Commit: drm/i915: Allow a context to define its set of engines +./include/linux/slab.h:664:13: error: not a function Commit: drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[] Okay! Commit: drm/i915: Pass around the intel_context Okay! Commit: drm/i915: Split struct intel_context definition to its own header Okay! Commit: drm/i915: Store the intel_context_ops in the intel_engine_cs Okay! Commit: drm/i915: Move over to intel_context_lookup() +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915: Make context pinning part of intel_context_ops Okay! Commit: drm/i915: Track the pinned kernel contexts on each engine Okay! Commit: drm/i915: Introduce intel_context.pin_mutex for pin management +drivers/gpu/drm/i915/intel_context.c:113:22: warning: context imbalance in 'intel_context_pin_lock' - wrong count at exit Commit: drm/i915: Load balancing across a virtual engine +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:285:13: warning: call with no type! +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: undefined identifier '__builtin_add_overflow' +./include/linux/overflow.h:287:13:got void +./include/linux/overflow.h:287:13: warning: call with no type! Commit: drm/i915: Extend execution fence to support a
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/38] drm/i915/execlists: Suppress redundant preemption
== Series Details ==
Series: series starting with [01/38] drm/i915/execlists: Suppress redundant
preemption
URL : https://patchwork.freedesktop.org/series/57427/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5e23d902d35d drm/i915/execlists: Suppress redundant preemption
2bf4e3894cc3 drm/i915: Introduce i915_timeline.mutex
bf3a70770514 drm/i915: Keep timeline HWSP allocated until idle across the system
183c1d46d005 drm/i915: Use HW semaphores for inter-engine synchronisation on
gen8+
f1ab995ada5f drm/i915: Prioritise non-busywait semaphore workloads
7da75240f892 drm/i915/selftests: Check that whitelisted registers are accessible
fb6dd69a3faf drm/i915: Force GPU idle on suspend
bd82e2da337c drm/i915/selftests: Improve switch-to-kernel-context checking
c3674ddd02ad drm/i915: Do a synchronous switch-to-kernel-context on idling
e210c30d893c drm/i915: Store the BIT(engine->id) as the engine's mask
-:262: CHECK:SPACING: No space is necessary after a cast
#262: FILE: drivers/gpu/drm/i915/intel_device_info.c:741:
+ BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
total: 0 errors, 0 warnings, 1 checks, 520 lines checked
40c040d7f36a drm/i915: Refactor common code to load initial power context
3344a6270d75 drm/i915: Reduce presumption of request ordering for barriers
0fbe8b734da4 drm/i915: Remove has-kernel-context
14c910b68d83 drm/i915: Introduce the i915_user_extension_method
-:58: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#58:
new file mode 100644
-:63: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#63: FILE: drivers/gpu/drm/i915/i915_user_extensions.c:1:
+/*
-:112: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#112: FILE: drivers/gpu/drm/i915/i915_user_extensions.h:1:
+/*
-:140: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ptr' - possible
side-effects?
#140: FILE: drivers/gpu/drm/i915/i915_utils.h:108:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:140: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible
side-effects?
#140: FILE: drivers/gpu/drm/i915/i915_utils.h:108:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:140: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'member' may be better as
'(member)' to avoid precedence issues
#140: FILE: drivers/gpu/drm/i915/i915_utils.h:108:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
total: 0 errors, 3 warnings, 3 checks, 109 lines checked
0b25c64b182f drm/i915: Track active engines within a context
-:110: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#110: FILE: drivers/gpu/drm/i915/i915_gem_context.h:167:
+ struct mutex mutex;
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
0baaabfdc6c8 drm/i915: Introduce a context barrier callback
f8ec2c8c0830 drm/i915: Create/destroy VM (ppGTT) for use with contexts
-:37: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#37: FILE: drivers/gpu/drm/i915/i915_drv.h:221:
+ struct mutex vm_lock;
-:551: WARNING:LINE_SPACING: Missing a blank line after declarations
#551: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:503:
+ struct drm_file *file;
+ IGT_TIMEOUT(end_time);
-:627: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#627: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:565:
+ ncontexts = dw = 0;
-:678: WARNING:LINE_SPACING: Missing a blank line after declarations
#678: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:610:
+ struct drm_file *file;
+ IGT_TIMEOUT(end_time);
-:758: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#758: FILE:
Re: [Intel-gfx] [PATCH 12/17] drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Op 01-03-2019 om 14:13 schreef Laurent Pinchart:
> Hi Maarten,
>
> Thank you for the patch.
>
> On Fri, Mar 01, 2019 at 01:56:22PM +0100, Maarten Lankhorst wrote:
>> Convert rcar-du to using __drm_atomic_helper_crtc_reset(), instead of
>> writing its own version. Instead of open coding destroy_state(), call
>> it directly for freeing the old state.
> I don't think the second sentence applies to this patch.
>
>> Signed-off-by: Maarten Lankhorst
>> Cc: Laurent Pinchart
>> Cc: Kieran Bingham
>> Cc: linux-renesas-...@vger.kernel.org
>> ---
>> drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 +++
>> 1 file changed, 3 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
>> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
>> index 4cdea14d552f..7766551e67fc 100644
>> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
>> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
>> @@ -891,22 +891,17 @@ static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
>>
>> static void rcar_du_crtc_reset(struct drm_crtc *crtc)
>> {
>> -struct rcar_du_crtc_state *state;
>> +struct rcar_du_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
>>
>> -if (crtc->state) {
>> +if (crtc->state)
>> rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
>> -crtc->state = NULL;
>> -}
>>
>> -state = kzalloc(sizeof(*state), GFP_KERNEL);
>> +__drm_atomic_helper_crtc_reset(crtc, >state);
> state may be NULL here if the above kzalloc() failed. Let's keep the
> original order of the function, and simply call
> __drm_atomic_helper_crtc_reset() after the NULL check below.
There were 10 different ways crtc was implemented, I felt it was good to settle
on one.
We don't handle during reset at all, would need to start propagating this first
before we should handle errors, imho.
Looking more closely, it's the same way that errors in rcar_du_plane_reset()
are handled. :)
Cheers,
~Maarten
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 33/38] drm/i915: Load balancing across a virtual engine
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load. The virtual engine has a single timeline across all
engines (it operates as a single queue), so it is not able to concurrently
run batches across multiple engines by itself; that is left up to the user
to submit multiple concurrent batches to multiple queues. Multiple users
will be load balanced across the system.
The mechanism used for load balancing in this patch is a late greedy
balancer. When a request is ready for execution, it is added to each
engine's queue, and when an engine is ready for its next request it
claims it from the virtual engine. The first engine to do so, wins, i.e.
the request is executed at the earliest opportunity (idle moment) in the
system.
As not all HW is created equal, the user is still able to skip the
virtual engine and execute the batch on a specific engine, all within the
same queue. It will then be executed in order on the correct engine,
with execution on other virtual engines being moved away due to the load
detection.
A couple of areas for potential improvement left!
- The virtual engine always take priority over equal-priority tasks.
Mostly broken up by applying FQ_CODEL rules for prioritising new clients,
and hopefully the virtual and real engines are not then congested (i.e.
all work is via virtual engines, or all work is to the real engine).
- We require the breadcrumb irq around every virtual engine request. For
normal engines, we eliminate the need for the slow round trip via
interrupt by using the submit fence and queueing in order. For virtual
engines, we have to allow any job to transfer to a new ring, and cannot
coalesce the submissions, so require the completion fence instead,
forcing the persistent use of interrupts.
- We only drip feed single requests through each virtual engine and onto
the physical engines, even if there was enough work to fill all ELSP,
leaving small stalls with an idle CS event at the end of every request.
Could we be greedy and fill both slots? Being lazy is virtuous for load
distribution on less-than-full workloads though.
Other areas of improvement are more general, such as reducing lock
contention, reducing dispatch overhead, looking at direct submission
rather than bouncing around tasklets etc.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.h| 5 +
drivers/gpu/drm/i915/i915_gem_context.c| 152 +-
drivers/gpu/drm/i915/i915_scheduler.c | 17 +-
drivers/gpu/drm/i915/i915_timeline_types.h | 1 +
drivers/gpu/drm/i915/intel_engine_types.h | 8 +
drivers/gpu/drm/i915/intel_lrc.c | 518 -
drivers/gpu/drm/i915/intel_lrc.h | 9 +
drivers/gpu/drm/i915/selftests/intel_lrc.c | 165 +++
include/uapi/drm/i915_drm.h| 30 ++
9 files changed, 889 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index b0e4b976880c..9905fcdd33c8 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -89,4 +89,9 @@ static inline bool __tasklet_is_enabled(const struct
tasklet_struct *t)
return !atomic_read(>count);
}
+static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
+{
+ return test_bit(TASKLET_STATE_SCHED, >state);
+}
+
#endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 321b26e302e5..57c85e990e80 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -91,6 +91,7 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
#include "intel_lrc_reg.h"
+#include "intel_lrc.h"
#include "intel_workarounds.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
@@ -236,6 +237,20 @@ static void release_hw_id(struct i915_gem_context *ctx)
mutex_unlock(>contexts.mutex);
}
+static void free_engines(struct intel_engine_cs **engines, int count)
+{
+ int i;
+
+ if (!engines)
+ return;
+
+ /* We own the veng we created; regular engines are ignored */
+ for (i = 0; i < count; i++)
+ intel_virtual_engine_destroy(engines[i]);
+
+ kfree(engines);
+}
+
static void i915_gem_context_free(struct i915_gem_context *ctx)
{
struct intel_context *it, *n;
@@ -246,8 +261,7 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
release_hw_id(ctx);
i915_ppgtt_put(ctx->ppgtt);
-
- kfree(ctx->engines);
+ free_engines(ctx->engines, ctx->nengine);
rbtree_postorder_for_each_entry_safe(it, n, >hw_contexts, node)
it->ops->destroy(it);
@@ -1338,13 +1352,115 @@
[Intel-gfx] [PATCH 07/38] drm/i915: Force GPU idle on suspend
To facilitate the next patch to allow preemptible kernels not to incur
the wrath of hangcheck, we need to ensure that we can still suspend and
shutdown. That is we will not be able to rely on hangcheck to terminate
a blocking kernel and instead must manually do so ourselves. The
advantage is that we can apply more pressure!
As we now perform a GPU reset to clean up any residual kernels, we leave
the GPU in an unknown state and in particular can not talk to the GuC
before we reinitialise it following resume. For example, we no longer
need to tell the GuC to suspend itself, as it is already reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a1ad5e137a97..f59af9567ec9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3167,13 +3167,6 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915,
lockdep_assert_held(>drm.struct_mutex);
- if (GEM_SHOW_DEBUG() && !timeout) {
- /* Presume that timeout was non-zero to begin with! */
- dev_warn(>drm.pdev->dev,
-"Missed idle-completion interrupt!\n");
- GEM_TRACE_DUMP();
- }
-
err = wait_for_engines(i915);
if (err)
return err;
@@ -4421,11 +4414,12 @@ int i915_gem_suspend(struct drm_i915_private *i915)
I915_WAIT_INTERRUPTIBLE |
I915_WAIT_LOCKED |
I915_WAIT_FOR_IDLE_BOOST,
-MAX_SCHEDULE_TIMEOUT);
- if (ret && ret != -EIO)
+HZ / 5);
+ if (ret == -EINTR)
goto err_unlock;
- assert_kernel_context_is_current(i915);
+ /* Forcibly cancel outstanding work and leave the gpu quiet. */
+ i915_gem_set_wedged(i915);
}
i915_retire_requests(i915); /* ensure we flush after wedging */
@@ -4440,15 +4434,11 @@ int i915_gem_suspend(struct drm_i915_private *i915)
*/
drain_delayed_work(>gt.idle_work);
- intel_uc_suspend(i915);
-
/*
* Assert that we successfully flushed all the work and
* reset the GPU back to its idle, low power state.
*/
- WARN_ON(i915->gt.awake);
- if (WARN_ON(!intel_engines_are_idle(i915)))
- i915_gem_set_wedged(i915); /* no hope, discard everything */
+ GEM_BUG_ON(i915->gt.awake);
intel_runtime_pm_put(i915, wakeref);
return 0;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/38] drm/i915: Prioritise non-busywait semaphore workloads
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately. We then also have to be careful that we don't give earlier
semaphores an accidental boost because later work doesn't wait on other
rings, hence we keep a history of semaphore usage of the dependency chain.
v2: Stop rolling the bits into a chain and just use a flag in case this
request or any of our dependencies use a semaphore. The rolling around
was contagious as Tvrtko was heard to fall off his chair.
Testcase: igt/gem_exec_schedule/semaphore
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 16
drivers/gpu/drm/i915/i915_scheduler.c | 6 ++
drivers/gpu/drm/i915/i915_scheduler.h | 9 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 59e30b8c4ee9..bcf3c1a155e2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -813,6 +813,7 @@ emit_semaphore_wait(struct i915_request *to,
*cs++ = 0;
intel_ring_advance(to, cs);
+ to->sched.flags |= I915_SCHED_HAS_SEMAPHORE;
return 0;
}
@@ -1083,6 +1084,21 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ /*
+* Boost actual workloads past semaphores!
+*
+* With semaphores we spin on one engine waiting for another,
+* simply to reduce the latency of starting our work when
+* the signaler completes. However, if there is any other
+* work that we could be doing on this engine instead, that
+* is better utilisation and will reduce the overall duration
+* of the current work. To avoid PI boosting a semaphore
+* far in the distance past over useful work, we keep a history
+* of any semaphore use along our dependency chain.
+*/
+ if (!(request->sched.flags & I915_SCHED_HAS_SEMAPHORE))
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 50018ad30233..8a64748a7912 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -39,6 +39,7 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(>waiters_list);
INIT_LIST_HEAD(>link);
node->attr.priority = I915_PRIORITY_INVALID;
+ node->flags = 0;
}
static struct i915_dependency *
@@ -69,6 +70,11 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node
*node,
dep->signaler = signal;
dep->flags = flags;
+ /* Keep track of whether anyone on this chain has a semaphore */
+ if (signal->flags & I915_SCHED_HAS_SEMAPHORE &&
+ !node_started(signal))
+ node->flags |= I915_SCHED_HAS_SEMAPHORE;
+
ret = true;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 7d4a49750d92..6ce450cf63fa 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
@@ -74,6 +75,8 @@ struct i915_sched_node {
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
struct i915_sched_attr attr;
+ unsigned int flags;
+#define I915_SCHED_HAS_SEMAPHORE BIT(0)
};
struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 53d6f7fdb50e..2268860cca44 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
-#define ACTIVE_PRIORITY
[Intel-gfx] [PATCH 28/38] drm/i915: Store the intel_context_ops in the intel_engine_cs
If we place a pointer to the engine specific intel_context_ops in the
engine itself, we can assign the ops pointer on initialising the
context, and then rely on it being set. This simplifies the code in
later patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/intel_engine_types.h| 1 +
drivers/gpu/drm/i915/intel_lrc.c | 13 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +---
drivers/gpu/drm/i915/selftests/mock_engine.c | 13 ++--
5 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index d04fa649bc0e..04c24caf30d2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -377,6 +377,7 @@ intel_context_init(struct intel_context *ce,
{
ce->gem_context = ctx;
ce->engine = engine;
+ ce->ops = engine->context;
INIT_LIST_HEAD(>signal_link);
INIT_LIST_HEAD(>signals);
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
b/drivers/gpu/drm/i915/intel_engine_types.h
index 5ec6e72d0ffb..546b790871ad 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -351,6 +351,7 @@ struct intel_engine_cs {
void(*set_default_submission)(struct intel_engine_cs
*engine);
+ const struct intel_context_ops *context;
struct intel_context *(*context_pin)(struct intel_engine_cs *engine,
struct i915_gem_context *ctx);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a2210f79dc67..4f6f09137662 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1381,11 +1381,6 @@ __execlists_context_pin(struct intel_engine_cs *engine,
return ERR_PTR(ret);
}
-static const struct intel_context_ops execlists_context_ops = {
- .unpin = execlists_context_unpin,
- .destroy = execlists_context_destroy,
-};
-
static struct intel_context *
execlists_context_pin(struct intel_engine_cs *engine,
struct i915_gem_context *ctx)
@@ -1399,11 +1394,14 @@ execlists_context_pin(struct intel_engine_cs *engine,
return ce;
GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
- ce->ops = _context_ops;
-
return __execlists_context_pin(engine, ctx, ce);
}
+static const struct intel_context_ops execlists_context_ops = {
+ .unpin = execlists_context_unpin,
+ .destroy = execlists_context_destroy,
+};
+
static int gen8_emit_init_breadcrumb(struct i915_request *rq)
{
u32 *cs;
@@ -2347,6 +2345,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->reset.reset = execlists_reset;
engine->reset.finish = execlists_reset_finish;
+ engine->context = _context_ops;
engine->context_pin = execlists_context_pin;
engine->request_alloc = execlists_request_alloc;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 764dcc5d5856..848b68e090d5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1348,7 +1348,7 @@ intel_ring_free(struct intel_ring *ring)
kfree(ring);
}
-static void intel_ring_context_destroy(struct intel_context *ce)
+static void ring_context_destroy(struct intel_context *ce)
{
GEM_BUG_ON(ce->pin_count);
@@ -1425,7 +1425,7 @@ static void __context_unpin(struct intel_context *ce)
i915_vma_unpin(vma);
}
-static void intel_ring_context_unpin(struct intel_context *ce)
+static void ring_context_unpin(struct intel_context *ce)
{
__context_unpin_ppgtt(ce->gem_context);
__context_unpin(ce);
@@ -1548,14 +1548,8 @@ __ring_context_pin(struct intel_engine_cs *engine,
return ERR_PTR(err);
}
-static const struct intel_context_ops ring_context_ops = {
- .unpin = intel_ring_context_unpin,
- .destroy = intel_ring_context_destroy,
-};
-
static struct intel_context *
-intel_ring_context_pin(struct intel_engine_cs *engine,
- struct i915_gem_context *ctx)
+ring_context_pin(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
{
struct intel_context *ce = to_intel_context(ctx, engine);
@@ -1565,11 +1559,14 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
return ce;
GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
- ce->ops = _context_ops;
-
return __ring_context_pin(engine, ctx, ce);
}
+static const struct intel_context_ops ring_context_ops = {
+ .unpin = ring_context_unpin,
+ .destroy = ring_context_destroy,
+};
+
static int intel_init_ring_buffer(struct intel_engine_cs *engine)
{
struct i915_timeline *timeline;
@@ -2275,7 +2272,8 @@ static
[Intel-gfx] [PATCH 27/38] drm/i915: Split struct intel_context definition to its own header
This complex struct pulling in half the driver deserves its own
isolation in preparation for intel_context becoming an outright
complicated class of its own.
In order to split this beast into its own header also requests splitting
several of its dependent types and their dependencies into their own
headers as well.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.h | 245 +---
drivers/gpu/drm/i915/i915_gem_context_types.h | 188 +++
drivers/gpu/drm/i915/i915_timeline.h | 70 +--
drivers/gpu/drm/i915/i915_timeline_types.h| 80 +++
drivers/gpu/drm/i915/intel_context.h | 47 ++
drivers/gpu/drm/i915/intel_context_types.h| 60 ++
drivers/gpu/drm/i915/intel_engine_types.h | 521 ++
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 502 +
drivers/gpu/drm/i915/intel_workarounds.h | 13 +-
.../gpu/drm/i915/intel_workarounds_types.h| 25 +
11 files changed, 928 insertions(+), 824 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gem_context_types.h
create mode 100644 drivers/gpu/drm/i915/i915_timeline_types.h
create mode 100644 drivers/gpu/drm/i915/intel_context.h
create mode 100644 drivers/gpu/drm/i915/intel_context_types.h
create mode 100644 drivers/gpu/drm/i915/intel_engine_types.h
create mode 100644 drivers/gpu/drm/i915/intel_workarounds_types.h
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index f09b5badbe73..110d5881c9de 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -25,225 +25,17 @@
#ifndef __I915_GEM_CONTEXT_H__
#define __I915_GEM_CONTEXT_H__
-#include
-#include
-#include
+#include "i915_gem_context_types.h"
#include "i915_gem.h"
#include "i915_scheduler.h"
+#include "intel_context.h"
#include "intel_device_info.h"
#include "intel_ringbuffer.h"
-struct pid;
-
struct drm_device;
struct drm_file;
-struct drm_i915_private;
-struct drm_i915_file_private;
-struct i915_hw_ppgtt;
-struct i915_request;
-struct i915_timeline;
-struct i915_vma;
-struct intel_ring;
-
-#define DEFAULT_CONTEXT_HANDLE 0
-
-struct intel_context;
-
-struct intel_context_ops {
- void (*unpin)(struct intel_context *ce);
- void (*destroy)(struct intel_context *ce);
-};
-
-/*
- * Powergating configuration for a particular (context,engine).
- */
-struct intel_sseu {
- u8 slice_mask;
- u8 subslice_mask;
- u8 min_eus_per_subslice;
- u8 max_eus_per_subslice;
-};
-
-/**
- * struct i915_gem_context - client state
- *
- * The struct i915_gem_context represents the combined view of the driver and
- * logical hardware state for a particular client.
- */
-struct i915_gem_context {
- /** i915: i915 device backpointer */
- struct drm_i915_private *i915;
-
- /** file_priv: owning file descriptor */
- struct drm_i915_file_private *file_priv;
-
- struct intel_engine_cs **engines;
-
- struct i915_timeline *timeline;
-
- /**
-* @ppgtt: unique address space (GTT)
-*
-* In full-ppgtt mode, each context has its own address space ensuring
-* complete seperation of one client from all others.
-*
-* In other modes, this is a NULL pointer with the expectation that
-* the caller uses the shared global GTT.
-*/
- struct i915_hw_ppgtt *ppgtt;
-
- /**
-* @pid: process id of creator
-*
-* Note that who created the context may not be the principle user,
-* as the context may be shared across a local socket. However,
-* that should only affect the default context, all contexts created
-* explicitly by the client are expected to be isolated.
-*/
- struct pid *pid;
-
- /**
-* @name: arbitrary name
-*
-* A name is constructed for the context from the creator's process
-* name, pid and user handle in order to uniquely identify the
-* context in messages.
-*/
- const char *name;
-
- /** link: place with _i915_private.context_list */
- struct list_head link;
- struct llist_node free_link;
-
- /**
-* @ref: reference count
-*
-* A reference to a context is held by both the client who created it
-* and on each request submitted to the hardware using the request
-* (to ensure the hardware has access to the state until it has
-* finished all pending writes). See i915_gem_context_get() and
-* i915_gem_context_put() for access.
-*/
- struct kref ref;
-
- /**
-* @rcu: rcu_head for deferred freeing.
-*/
- struct rcu_head rcu;
-
- /**
-* @user_flags: small set of booleans controlled by the user
-*/
- unsigned long user_flags;
-#define UCONTEXT_NO_ZEROMAP0
[Intel-gfx] [PATCH 17/38] drm/i915: Create/destroy VM (ppGTT) for use with contexts
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
local context barrier (Tvrtko)
v3: serialise with struct_mutex; it's lazy but required dammit
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_context.c | 254 +-
drivers/gpu/drm/i915/i915_gem_context.h | 5 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 1 -
.../gpu/drm/i915/selftests/i915_gem_context.c | 239
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 8 +-
include/uapi/drm/i915_drm.h | 36 +++
11 files changed, 511 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 224bb96b7877..6b75d1b7b8bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3008,6 +3008,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG,
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
};
static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 195e71bb4a4f..cbc2b59722ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -218,6 +218,9 @@ struct drm_i915_file_private {
} mm;
struct idr context_idr;
+ struct mutex vm_lock;
+ struct idr vm_idr;
+
unsigned int bsd_engine;
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 91926a407548..8c35b6019f0d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -124,6 +124,8 @@ static void lut_close(struct i915_gem_context *ctx)
struct i915_vma *vma = rcu_dereference_raw(*slot);
radix_tree_iter_delete(>handles_vma, , slot);
+
+ vma->open_count--;
__i915_gem_object_release_unless_active(vma->obj);
}
rcu_read_unlock();
@@ -308,7 +310,7 @@ static void context_close(struct i915_gem_context *ctx)
*/
lut_close(ctx);
if (ctx->ppgtt)
- i915_ppgtt_close(>ppgtt->vm);
+ i915_ppgtt_close(ctx->ppgtt);
ctx->file_priv = ERR_PTR(-EBADF);
i915_gem_context_put(ctx);
@@ -447,6 +449,32 @@ static void __destroy_hw_context(struct i915_gem_context
*ctx,
context_close(ctx);
}
+static struct i915_hw_ppgtt *
+__set_ppgtt(struct i915_gem_context *ctx, struct i915_hw_ppgtt *ppgtt)
+{
+ struct i915_hw_ppgtt *old = ctx->ppgtt;
+
+ i915_ppgtt_open(ppgtt);
+ ctx->ppgtt = i915_ppgtt_get(ppgtt);
+
+ ctx->desc_template = default_desc_template(ctx->i915, ppgtt);
+
+ return old;
+}
+
+static void __assign_ppgtt(struct i915_gem_context *ctx,
+ struct i915_hw_ppgtt *ppgtt)
+{
+ if (ppgtt == ctx->ppgtt)
+ return;
+
+ ppgtt = __set_ppgtt(ctx, ppgtt);
+ if (ppgtt) {
+ i915_ppgtt_close(ppgtt);
+ i915_ppgtt_put(ppgtt);
+ }
+}
+
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *file_priv)
@@ -473,8 +501,8 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
return ERR_CAST(ppgtt);
}
- ctx->ppgtt = ppgtt;
- ctx->desc_template = default_desc_template(dev_priv, ppgtt);
+ __assign_ppgtt(ctx, ppgtt);
+ i915_ppgtt_put(ppgtt);
}
trace_i915_context_create(ctx);
@@ -655,19 +683,29 @@ static int context_idr_cleanup(int id, void *p, void
*data)
return 0;
}
+static int vm_idr_cleanup(int id, void *p, void *data)
+{
+ i915_ppgtt_put(p);
+ return 0;
+}
+
int i915_gem_context_open(struct drm_i915_private *i915,
struct drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
struct i915_gem_context *ctx;
+ mutex_init(_priv->vm_lock);
+
[Intel-gfx] [PATCH 09/38] drm/i915: Do a synchronous switch-to-kernel-context on idling
When the system idles, we switch to the kernel context as a defensive
measure (no users are harmed if the kernel context is lost). Currently,
we issue a switch to kernel context and then come back later to see if
the kernel context is still current and the system is idle. However,
if we are no longer privy to the runqueue ordering, then we have to
relax our assumptions about the logical state of the GPU and the only
way to ensure that the kernel context is currently loaded is by issuing
a request to run after all others, and wait for it to complete all while
preventing anyone else from issuing their own requests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 14 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 139 --
drivers/gpu/drm/i915/i915_gem_context.c | 4 +
drivers/gpu/drm/i915/selftests/i915_gem.c | 9 +-
5 files changed, 63 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c08abdef5eb6..224bb96b7877 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -714,8 +714,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
cleanup_gem:
- if (i915_gem_suspend(dev_priv))
- DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+ i915_gem_suspend(dev_priv);
i915_gem_fini(dev_priv);
cleanup_modeset:
intel_modeset_cleanup(dev);
@@ -1787,8 +1786,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any external code that still may be under the RCU lock */
synchronize_rcu();
- if (i915_gem_suspend(dev_priv))
- DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+ i915_gem_suspend(dev_priv);
drm_atomic_helper_shutdown(dev);
@@ -1896,7 +1894,6 @@ static bool suspend_to_idle(struct drm_i915_private
*dev_priv)
static int i915_drm_prepare(struct drm_device *dev)
{
struct drm_i915_private *i915 = to_i915(dev);
- int err;
/*
* NB intel_display_suspend() may issue new requests after we've
@@ -1904,12 +1901,9 @@ static int i915_drm_prepare(struct drm_device *dev)
* split out that work and pull it forward so that after point,
* the GPU is not woken again.
*/
- err = i915_gem_suspend(i915);
- if (err)
- dev_err(>drm.pdev->dev,
- "GEM idle failed, suspend/resume might fail\n");
+ i915_gem_suspend(i915);
- return err;
+ return 0;
}
static int i915_drm_suspend(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 453af7438e67..cf325a00d143 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3046,7 +3046,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
unsigned int flags, long timeout);
-int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+void i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
vm_fault_t i915_gem_fault(struct vm_fault *vmf);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f59af9567ec9..503b02525c99 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2872,13 +2872,6 @@ i915_gem_retire_work_handler(struct work_struct *work)
round_jiffies_up_relative(HZ));
}
-static inline bool
-new_requests_since_last_retire(const struct drm_i915_private *i915)
-{
- return (READ_ONCE(i915->gt.active_requests) ||
- work_pending(>gt.idle_work.work));
-}
-
static void assert_kernel_context_is_current(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
@@ -2887,7 +2880,8 @@ static void assert_kernel_context_is_current(struct
drm_i915_private *i915)
if (i915_reset_failed(i915))
return;
- GEM_BUG_ON(i915->gt.active_requests);
+ i915_retire_requests(i915);
+
for_each_engine(engine, i915, id) {
GEM_BUG_ON(__i915_active_request_peek(>timeline.last_request));
GEM_BUG_ON(engine->last_retired_context !=
@@ -2895,77 +2889,75 @@ static void assert_kernel_context_is_current(struct
drm_i915_private *i915)
}
}
+static bool switch_to_kernel_context_sync(struct drm_i915_private *i915)
+{
+ if (i915_gem_switch_to_kernel_context(i915))
+ return false;
+
+ if (i915_gem_wait_for_idle(i915,
+ I915_WAIT_LOCKED |
+
