[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2) URL : https://patchwork.freedesktop.org/series/59180/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017_full -> Patchwork_12909_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12909_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12909_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12909_full: ### IGT changes ### Possible regressions * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-skl3/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@syncobj_wait@wait-for-submit-snapshot: - shard-skl: NOTRUN -> [INCOMPLETE][3] +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-skl2/igt@syncobj_w...@wait-for-submit-snapshot.html Known issues Here are the changes found in Patchwork_12909_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-rte: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([fdo#107807]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl2/igt@i915_pm_...@basic-rte.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-skl3/igt@i915_pm_...@basic-rte.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled: - shard-skl: [PASS][6] -> [FAIL][7] ([fdo#103184] / [fdo#103232]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl9/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-skl9/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#104108] / [fdo#107773]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl5/igt@kms_fbcon_...@psr-suspend.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-skl4/igt@kms_fbcon_...@psr-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#108040]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl9/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-skl9/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][12] -> [FAIL][13] ([fdo#103167]) +5 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-iclb1/igt@kms_frontbuffer_track...@fbc-stridechange.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-iclb5/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-iclb: [PASS][14] -> [INCOMPLETE][15] ([fdo#107713] / [fdo#110036 ]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-iclb1/igt@kms_pl...@pixel-format-pipe-c-planes-source-clamping.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-iclb1/igt@kms_pl...@pixel-format-pipe-c-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([fdo#108566]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108145]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109441]) +1 similar issue [20]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for dma-buf: add struct dma_buf_attach_info v2
== Series Details == Series: dma-buf: add struct dma_buf_attach_info v2 URL : https://patchwork.freedesktop.org/series/60107/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017_full -> Patchwork_12908_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12908_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12908_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12908_full: ### IGT changes ### Possible regressions * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-skl2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@gem_pwrite@small-cpu-random: - shard-skl: NOTRUN -> [INCOMPLETE][3] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-skl3/igt@gem_pwr...@small-cpu-random.html * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled: - shard-skl: NOTRUN -> [DMESG-WARN][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-skl4/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-xtiled.html Known issues Here are the changes found in Patchwork_12908_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][5] -> [DMESG-WARN][6] ([fdo#109982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-iclb7/igt@i915_pm_...@i2c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-iclb2/igt@i915_pm_...@i2c.html * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107773]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl10/igt@kms_cursor_...@cursor-128x128-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-skl7/igt@kms_cursor_...@cursor-128x128-suspend.html * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl2/igt@kms_cursor_...@cursor-64x64-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-skl8/igt@kms_cursor_...@cursor-64x64-suspend.html * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy: - shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#105767]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-hsw1/igt@kms_cursor_leg...@2x-cursor-vs-flip-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-hsw6/igt@kms_cursor_leg...@2x-cursor-vs-flip-legacy.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#103184] / [fdo#103232]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl9/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-skl5/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html * igt@kms_flip@flip-vs-suspend: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-apl2/igt@kms_f...@flip-vs-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-apl3/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip_tiling@flip-changes-tiling: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-iclb7/igt@kms_flip_til...@flip-changes-tiling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-iclb8/igt@kms_flip_til...@flip-changes-tiling.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103167]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/shard-skl9/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/shard-skl5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +1 similar issue [21]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor to expand subslice mask (rev6)
== Series Details == Series: Refactor to expand subslice mask (rev6) URL : https://patchwork.freedesktop.org/series/59742/ State : failure == Summary == Applying: drm/i915: Use local variable for SSEU info in GETPARAM ioctl Applying: drm/i915: Add macro for SSEU stride calculation Applying: drm/i915: Move calculation of subslices per slice to new function Applying: drm/i915: Move sseu helper functions to intel_sseu.h Applying: drm/i915: Remove inline from sseu helper functions Applying: drm/i915: Expand subslice mask error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_debugfs.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0006 drm/i915: Expand subslice mask When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
v2: add const to sseu_dev_info variable
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 21dac5a09fbe..c376244c19c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -324,6 +324,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
int value;
@@ -377,12 +378,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ value = sseu->eu_total;
if (!value)
return -ENODEV;
break;
@@ -399,7 +400,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(_priv->huc);
@@ -449,12 +450,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = sseu->subslice_mask[0];
if (!value)
return -ENODEV;
break;
--
2.21.0.5.gaeb582a983
___
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
On Tue, 2019-04-30 at 11:58 +0300, Jani Nikula wrote:
> On Mon, 29 Apr 2019, Stuart Summers wrote:
> > In the GETPARAM ioctl handler, use a local variable to consolidate
> > usage of SSEU runtime info.
> >
> > Cc: Daniele Ceraolo Spurio
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 11 ++-
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index aacc8dd6ecfd..b6ce7580d414 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -321,6 +321,7 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > {
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct pci_dev *pdev = dev_priv->drm.pdev;
> > + struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
>
> const?
Somehow I had missed this email, sorry for the late response. I'll make
this change and post a quick update.
Thanks,
Stuart
>
> > drm_i915_getparam_t *param = data;
> > int value;
> >
> > @@ -374,12 +375,12 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > value = i915_cmd_parser_get_version(dev_priv);
> > break;
> > case I915_PARAM_SUBSLICE_TOTAL:
> > - value = sseu_subslice_total(_INFO(dev_priv)-
> > >sseu);
> > + value = sseu_subslice_total(sseu);
> > if (!value)
> > return -ENODEV;
> > break;
> > case I915_PARAM_EU_TOTAL:
> > - value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
> > + value = sseu->eu_total;
> > if (!value)
> > return -ENODEV;
> > break;
> > @@ -396,7 +397,7 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > value = HAS_POOLED_EU(dev_priv);
> > break;
> > case I915_PARAM_MIN_EU_IN_POOL:
> > - value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
> > + value = sseu->min_eu_in_pool;
> > break;
> > case I915_PARAM_HUC_STATUS:
> > value = intel_huc_check_status(_priv->huc);
> > @@ -446,12 +447,12 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > value = intel_engines_has_context_isolation(dev_priv);
> > break;
> > case I915_PARAM_SLICE_MASK:
> > - value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
> > + value = sseu->slice_mask;
> > if (!value)
> > return -ENODEV;
> > break;
> > case I915_PARAM_SUBSLICE_MASK:
> > - value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
> > + value = sseu->subslice_mask[0];
> > if (!value)
> > return -ENODEV;
> > break;
>
>
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___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev5)
== Series Details == Series: Refactor to expand subslice mask (rev5) URL : https://patchwork.freedesktop.org/series/59742/ State : success == Summary == CI Bug Log - changes from CI_DRM_6020 -> Patchwork_12917 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59742/revisions/5/mbox/ Known issues Here are the changes found in Patchwork_12917 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live_hangcheck: - fi-bsw-kefka: [INCOMPLETE][1] -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12917/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [INCOMPLETE][3] ([fdo#107807]) -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12917/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (53 -> 45) -- Additional (1): fi-pnv-d510 Missing(9): fi-kbl-soraka fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6020 -> Patchwork_12917 CI_DRM_6020: 087f11254b9a7a79156a88509afc4c1e2d640a7f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12917: 9b09ab1e44a390105863ff2ce8831bc537f6d9c9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9b09ab1e44a3 drm/i915: Expand subslice mask 2b9349156f64 drm/i915: Remove inline from sseu helper functions f03d45e541ca drm/i915: Move sseu helper functions to intel_sseu.h 1aa1a9b832aa drm/i915: Move calculation of subslices per slice to new function 5c73378a02c2 drm/i915: Add macro for SSEU stride calculation 2699899bf520 drm/i915: Use local variable for SSEU info in GETPARAM ioctl == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12917/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask (rev5)
== Series Details == Series: Refactor to expand subslice mask (rev5) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl Okay! Commit: drm/i915: Add macro for SSEU stride calculation Okay! Commit: drm/i915: Move calculation of subslices per slice to new function Okay! Commit: drm/i915: Move sseu helper functions to intel_sseu.h Okay! Commit: drm/i915: Remove inline from sseu helper functions Okay! Commit: drm/i915: Expand subslice mask +drivers/gpu/drm/i915/i915_drv.c:460:24: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev5)
== Series Details == Series: Refactor to expand subslice mask (rev5) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2699899bf520 drm/i915: Use local variable for SSEU info in GETPARAM ioctl 5c73378a02c2 drm/i915: Add macro for SSEU stride calculation 1aa1a9b832aa drm/i915: Move calculation of subslices per slice to new function f03d45e541ca drm/i915: Move sseu helper functions to intel_sseu.h 2b9349156f64 drm/i915: Remove inline from sseu helper functions 9b09ab1e44a3 drm/i915: Expand subslice mask -:84: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu__' - possible side-effects? #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:84: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slice__' may be better as '(slice__)' to avoid precedence issues #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:84: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects? #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:84: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'subslice__' may be better as '(subslice__)' to avoid precedence issues #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ total: 0 errors, 0 warnings, 8 checks, 692 lines checked ___
[Intel-gfx] [PATCH 6/6] drm/i915: Expand subslice mask
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: fix spacing in set_sseu_info args
use set_sseu_info to initialize sseu data when building
device status in debugfs
rename variables in intel_engine_types.h to avoid checkpatch
warnings
v3: update headers in intel_sseu.h
v4: add const to some sseu_dev_info variables
use sseu->eu_stride for EU stride calculations
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 49 +--
drivers/gpu/drm/i915/gt/intel_sseu.h | 16 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c| 5 +-
drivers/gpu/drm/i915/i915_query.c| 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 142 +++
11 files changed, 198 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f7308479d511..e438d366874f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -908,7 +908,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private
*dev_priv)
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+ u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -984,6 +984,7 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1001,7 +1002,8 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d972c339309c..fa70528963a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
-(slice__) < I915_MAX_SLICES; \
-(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
(subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) &&
\
- (BIT(subslice__) &
instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? \
+ 1 : (sseu___)->slice_mask) & \
+ BIT(slice___)) \
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+BIT(subslice__ % BITS_PER_BYTE)) \
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_)
+ 1 : 0,
[Intel-gfx] [PATCH 3/6] drm/i915: Move calculation of subslices per slice to new function
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index c0b16b248d4c..f5ff6b7a756a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ffbf5d920429..0ecf006d26b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool
is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu,
struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct
sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aacc8dd6ecfd..b6ce7580d414 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,6 +321,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
int value;
@@ -374,12 +375,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ value = sseu->eu_total;
if (!value)
return -ENODEV;
break;
@@ -396,7 +397,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(_priv->huc);
@@ -446,12 +447,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = sseu->subslice_mask[0];
if (!value)
return -ENODEV;
break;
--
2.21.0.5.gaeb582a983
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2
Hi "Christian,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.1-rc7 next-20190430]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Christian-K-nig/dma-buf-add-struct-dma_buf_attach_info-v2/20190430-221017
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
sparse warnings: (new ones prefixed by >>)
>> drivers/xen/gntdev-dmabuf.c:634:33: sparse: sparse: incorrect type in
>> argument 1 (different base types) @@expected struct dma_buf_attach_info
>> const *info @@got dma_buf_attach_info const *info @@
>> drivers/xen/gntdev-dmabuf.c:634:33: sparse:expected struct
>> dma_buf_attach_info const *info
>> drivers/xen/gntdev-dmabuf.c:634:33: sparse:got struct dma_buf
>> *[assigned] dma_buf
>> drivers/xen/gntdev-dmabuf.c:634:32: sparse: sparse: too many arguments for
>> function dma_buf_attach
vim +634 drivers/xen/gntdev-dmabuf.c
bf8dc55b Oleksandr Andrushchenko 2018-07-20 605
932d6562 Oleksandr Andrushchenko 2018-07-20 606 static struct gntdev_dmabuf *
932d6562 Oleksandr Andrushchenko 2018-07-20 607 dmabuf_imp_to_refs(struct
gntdev_dmabuf_priv *priv, struct device *dev,
932d6562 Oleksandr Andrushchenko 2018-07-20 608 int fd, int
count, int domid)
932d6562 Oleksandr Andrushchenko 2018-07-20 609 {
bf8dc55b Oleksandr Andrushchenko 2018-07-20 610struct gntdev_dmabuf
*gntdev_dmabuf, *ret;
e648feab Christian König 2019-04-30 611struct
dma_buf_attach_info attach_info;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 612struct dma_buf *dma_buf;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 613struct
dma_buf_attachment *attach;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 614struct sg_table *sgt;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 615struct sg_page_iter
sg_iter;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 616int i;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 617
bf8dc55b Oleksandr Andrushchenko 2018-07-20 618dma_buf =
dma_buf_get(fd);
bf8dc55b Oleksandr Andrushchenko 2018-07-20 619if (IS_ERR(dma_buf))
bf8dc55b Oleksandr Andrushchenko 2018-07-20 620return
ERR_CAST(dma_buf);
bf8dc55b Oleksandr Andrushchenko 2018-07-20 621
bf8dc55b Oleksandr Andrushchenko 2018-07-20 622gntdev_dmabuf =
dmabuf_imp_alloc_storage(count);
bf8dc55b Oleksandr Andrushchenko 2018-07-20 623if
(IS_ERR(gntdev_dmabuf)) {
bf8dc55b Oleksandr Andrushchenko 2018-07-20 624ret =
gntdev_dmabuf;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 625goto fail_put;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 626}
bf8dc55b Oleksandr Andrushchenko 2018-07-20 627
bf8dc55b Oleksandr Andrushchenko 2018-07-20 628gntdev_dmabuf->priv =
priv;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 629gntdev_dmabuf->fd = fd;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 630
e648feab Christian König 2019-04-30 631memset(_info, 0,
sizeof(attach_info));
e648feab Christian König 2019-04-30 632attach_info.dev = dev;
e648feab Christian König 2019-04-30 633attach_info.dmabuf =
dma_buf;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 @634attach =
dma_buf_attach(dma_buf, dev);
bf8dc55b Oleksandr Andrushchenko 2018-07-20 635if (IS_ERR(attach)) {
bf8dc55b Oleksandr Andrushchenko 2018-07-20 636ret =
ERR_CAST(attach);
bf8dc55b Oleksandr Andrushchenko 2018-07-20 637goto
fail_free_obj;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 638}
bf8dc55b Oleksandr Andrushchenko 2018-07-20 639
bf8dc55b Oleksandr Andrushchenko 2018-07-20 640
gntdev_dmabuf->u.imp.attach = attach;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 641
bf8dc55b Oleksandr Andrushchenko 2018-07-20 642sgt =
dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
bf8dc55b Oleksandr Andrushchenko 2018-07-20 643if (IS_ERR(sgt)) {
bf8dc55b Oleksandr Andrushchenko 2018-07-20 644ret =
ERR_CAST(sgt);
bf8dc55b Oleksandr Andrushchenko 2018-07-20 645goto
fail_detach;
bf8dc55b Oleksandr Andrushchenko 2018-07-20 646}
bf8dc55b Oleksandr Andrushchenko 2018-07-20 647
bf8dc55b Oleksandr Andrushchenko 2018-07-20 648/* Check number of
pages that imported buffer has. */
bf8dc55b Oleksandr Andrushchenko 2018-07-20 649if
(attach->dmabuf->size != gntdev_dmabuf->nr_pages << PAGE_SHIFT) {
bf8dc55b Oleksandr Andrushchenko 2018-07-20 650ret =
ERR_PTR(-EINVAL);
bf8d
[Intel-gfx] [PATCH 0/6] Refactor to expand subslice mask
This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly v4: rebase v5: fix header test v6: address review comments from Jari address minor checkpatch warning in existing code use eu_stride for EU div-by-8 Stuart Summers (6): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Move sseu helper functions to intel_sseu.h drm/i915: Remove inline from sseu helper functions drm/i915: Expand subslice mask drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +-- drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 85 drivers/gpu/drm/i915/gt/intel_sseu.h | 30 ++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 50 +++-- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_gpu_error.c| 5 +- drivers/gpu/drm/i915/i915_query.c| 15 +- drivers/gpu/drm/i915/intel_device_info.c | 209 +++ drivers/gpu/drm/i915/intel_device_info.h | 47 - 12 files changed, 302 insertions(+), 197 deletions(-) -- 2.21.0.5.gaeb582a983 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915: Remove inline from sseu helper functions
Additionally, ensure these are all prefixed with intel_sseu_*
to match the convention of other functions in i915.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +++
drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 69
5 files changed, 102 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7f448f3bea0b..4a0b82fc108c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,60 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+unsigned int
+intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
+unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
+static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
+int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
+ u16 eu_mask)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 029e71d8f140..56e3721ae83f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,58 +63,17 @@ intel_sseu_from_device_info(const struct sseu_dev_info
*sseu)
return value;
}
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
+unsigned int
+intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
- return total;
-}
+unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-static inline unsigned int
-sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
-{
- return hweight8(sseu->subslice_mask[slice]);
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
+u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
+ int subslice);
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
- int slice, int subslice, u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
+void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
+
[Intel-gfx] [PATCH 2/6] drm/i915: Add macro for SSEU stride calculation
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
v2: update headers in intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
drivers/gpu/drm/i915/i915_query.c| 17 -
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 73bc824094e8..c0b16b248d4c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -8,11 +8,13 @@
#define __INTEL_SSEU_H__
#include
+#include
struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
+#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
struct sseu_dev_info {
u8 slice_mask;
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 782183b78f49..7c1708c22811 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices *
- DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
- eu_length = sseu->max_slices * sseu->max_subslices *
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
-
- total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
+ subslice_length = sseu->max_slices * subslice_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ total_length = sizeof(topo) + slice_length + subslice_length +
+ eu_length;
ret = copy_query_item(, sizeof(topo), total_length,
query_item);
@@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
+ topo.subslice_stride = subslice_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride =
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+ topo.eu_stride = eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
, sizeof(topo)))
--
2.21.0.5.gaeb582a983
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm/i915: Move sseu helper functions to intel_sseu.h
v2: fix spacing from checkpatch warning
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 47
drivers/gpu/drm/i915/intel_device_info.h | 47
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index f5ff6b7a756a..029e71d8f140 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info
*sseu)
return value;
}
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
static inline unsigned int
sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
return hweight8(sseu->subslice_mask[slice]);
}
+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+static inline void sseu_set_eus(struct sseu_dev_info *sseu,
+ int slice, int subslice, u16 eu_mask)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..6412a9c72898 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -218,53 +218,6 @@ struct intel_driver_caps {
bool has_logical_contexts:1;
};
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
-
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
- int slice, int subslice, u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
-
const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
--
2.21.0.5.gaeb582a983
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[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: disable framebuffer compression on GeminiLake
== Series Details == Series: i915: disable framebuffer compression on GeminiLake URL : https://patchwork.freedesktop.org/series/60090/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6014_full -> Patchwork_12904_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12904_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12904_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12904_full: ### IGT changes ### Possible regressions * igt@gem_exec_parallel@contexts: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-skl5/igt@gem_exec_paral...@contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-skl6/igt@gem_exec_paral...@contexts.html * igt@kms_psr@primary_render: - shard-skl: NOTRUN -> [INCOMPLETE][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-skl3/igt@kms_psr@primary_render.html Known issues Here are the changes found in Patchwork_12904_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_sync@basic-each: - shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-iclb1/igt@gem_s...@basic-each.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-iclb1/igt@gem_s...@basic-each.html * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][6] -> [DMESG-WARN][7] ([fdo#109982]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-iclb5/igt@i915_pm_...@i2c.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-iclb2/igt@i915_pm_...@i2c.html * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-apl2/igt@kms_cursor_...@cursor-64x64-suspend.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-apl8/igt@kms_cursor_...@cursor-64x64-suspend.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([fdo#104108]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-skl4/igt@kms_fbcon_...@fbc-suspend.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-skl1/igt@kms_fbcon_...@fbc-suspend.html * igt@kms_flip@2x-flip-vs-dpms-interruptible: - shard-glk: [PASS][12] -> [INCOMPLETE][13] ([fdo#103359] / [k.org#198133]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-glk1/igt@kms_f...@2x-flip-vs-dpms-interruptible.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-glk8/igt@kms_f...@2x-flip-vs-dpms-interruptible.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][14] -> [FAIL][15] ([fdo#105363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-glk4/igt@kms_f...@flip-vs-expired-vblank.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-iclb: [PASS][16] -> [FAIL][17] ([fdo#103167]) +6 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt: - shard-skl: [PASS][18] -> [INCOMPLETE][19] ([fdo#106978]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-skl1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-msflip-blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-skl10/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-msflip-blt.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-glk: [PASS][22] -> [SKIP][23]
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix setting 10 bit deep color mode
On Tue, Apr 30, 2019 at 06:05:18PM +0300, Ville Syrjälä wrote: > On Mon, Apr 29, 2019 at 05:00:28PM -0700, Aditya Swarup wrote: > > From: Ville Syrjälä > > > > There is a bug in hdmi_deep_color_possible() - we compare pipe_bpp > > <= 8*3 which returns true every time for hdmi_deep_color_possible 12 bit > > deep color mode test in intel_hdmi_compute_config().(Even when the > > requested color mode is 10 bit through max bpc property) > > > > Comparing pipe_bpp with bpc * 3 takes care of this condition where > > requested max bpc is 10 bit, so hdmi_deep_color_possible with 12 bit > > returns false when requested max bpc is 10. > > > > Signed-off-by: Ville Syrjälä > > How did my sob appear on this? Pretty sure I didn't actually put it > here. I added it, since you are the author of this patch and came up with the change. Imre and I have tested your patch and it is required. > > > Signed-off-by: Aditya Swarup > > Cc: Jani Nikula > > Cc: Manasi Navare > > Cc: Clinton Taylor > > --- > > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > > b/drivers/gpu/drm/i915/intel_hdmi.c > > index 991eb362ef4f..74f2dcb8b1ad 100644 > > --- a/drivers/gpu/drm/i915/intel_hdmi.c > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > > @@ -2159,7 +2159,7 @@ static bool hdmi_deep_color_possible(const struct > > intel_crtc_state *crtc_state, > > if (bpc == 10 && INTEL_GEN(dev_priv) < 11) > > return false; > > > > - if (crtc_state->pipe_bpp <= 8*3) > > + if (crtc_state->pipe_bpp < bpc * 3) > > return false; > > > > if (!crtc_state->has_hdmi_sink) > > -- > > 2.17.1 > > -- > Ville Syrjälä > Intel Regards, Aditya Swarup ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2)
== Series Details == Series: drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2) URL : https://patchwork.freedesktop.org/series/60062/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6014_full -> Patchwork_12903_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12903_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12903_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12903_full: ### IGT changes ### Possible regressions * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-skl: NOTRUN -> [INCOMPLETE][1] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-skl2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html Known issues Here are the changes found in Patchwork_12903_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-iclb: [PASS][2] -> [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-iclb2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-iclb6/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@i915_pm_rpm@debugfs-read: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([fdo#107807]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-skl6/igt@i915_pm_...@debugfs-read.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-skl5/igt@i915_pm_...@debugfs-read.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-apl2/igt@i915_susp...@debugfs-reader.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-apl3/igt@i915_susp...@debugfs-reader.html * igt@kms_color@pipe-c-ctm-0-25: - shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([fdo#107713]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-iclb1/igt@kms_co...@pipe-c-ctm-0-25.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-iclb3/igt@kms_co...@pipe-c-ctm-0-25.html * igt@kms_flip@2x-flip-vs-dpms-interruptible: - shard-glk: [PASS][10] -> [INCOMPLETE][11] ([fdo#103359] / [k.org#198133]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-glk1/igt@kms_f...@2x-flip-vs-dpms-interruptible.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-glk3/igt@kms_f...@2x-flip-vs-dpms-interruptible.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-hsw: [PASS][12] -> [FAIL][13] ([fdo#102887]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-hsw1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-hsw1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html - shard-glk: [PASS][14] -> [FAIL][15] ([fdo#105363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-glk6/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-glk6/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@2x-nonexisting-fb: - shard-hsw: [PASS][16] -> [INCOMPLETE][17] ([fdo#103540]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-hsw6/igt@kms_f...@2x-nonexisting-fb.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-hsw4/igt@kms_f...@2x-nonexisting-fb.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: [PASS][18] -> [FAIL][19] ([fdo#103167]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-skl: [PASS][20] -> [INCOMPLETE][21] ([fdo#106978]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/shard-skl10/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [21]:
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used
On Tue, Apr 30, 2019 at 07:13:36PM +0530, Sharma, Shashank wrote:
>
> On 4/30/2019 4:09 PM, Ville Syrjälä wrote:
> > On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote:
> >> On 4/26/2019 8:07 PM, Ville Syrjälä wrote:
> >>> On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
> On 4/13/2019 12:00 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The pipe has a special HDR mode with higher precision when only
> > HDR planes are active. Let's use it.
> >
> > Curiously this fixes the kms_color gamma/degamma tests when
> > using a HDR plane, which is always the case unless one hacks
> > the test to use an SDR plane. If one does hack the test to use
> > an SDR plane it does pass already.
> >
> > I have no actual explanation how the output after the gamma
> > LUT can be different between the two modes. The way the tests
> > are written should mean that the output should be identical
> > between the solid color vs. the gradient. But clearly that
> > somehow doesn't hold true for the HDR planes in non-HDR pipe
> > mode. Anyways, as long as we stick to one type of plane the
> > test should produce sensible results now.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 7 +++
> > drivers/gpu/drm/i915/intel_sprite.h | 12
> > 3 files changed, 16 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 8ad2f0a03f28..90d60ecd3317 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5767,6 +5767,7 @@ enum {
> > #define _PIPE_MISC_B0x71030
> > #define PIPEMISC_YUV420_ENABLE(1 << 27)
> > #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
> > +#define PIPEMISC_HDR_MODE(1 << 23) /* icl+ */
> > #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
> > #define PIPEMISC_DITHER_BPC_MASK (7 << 5)
> > #define PIPEMISC_DITHER_8_BPC (0 << 5)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 490bd49ff42a..d0dbdbd5db3f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4055,6 +4055,9 @@ static void intel_update_pipe_config(const struct
> > intel_crtc_state *old_crtc_sta
> > ironlake_pfit_disable(old_crtc_state);
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > + bdw_set_pipemisc(new_crtc_state);
> > +
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_set_pipe_chicken(crtc);
> > }
> > @@ -8869,6 +8872,10 @@ static void bdw_set_pipemisc(const struct
> > intel_crtc_state *crtc_state)
> > val |= PIPEMISC_YUV420_ENABLE |
> > PIPEMISC_YUV420_MODE_FULL_BLEND;
> >
> > + if (INTEL_GEN(dev_priv) >= 11 &&
> > + (crtc_state->active_planes & ~icl_hdr_plane_mask()) == 0)
> > + val |= PIPEMISC_HDR_MODE;
> > +
> Shouldn't we check if the content being played on plane is HDR before
> enabling this bit (even though I am not sure if there is any harm in
> doing that)? Or maybe check the connector->output_hdr_metadata ? Most of
> the times we would be sending SDR buffers on this plane. What happens
> exactly when we set this bit ? The bspec says:
>
> "This field enables the HDR mode, allowing for higher precision output
> from the HDR supporting planes and bypassing the SDR planes in blending.
> "
> >>> I think the bit is just misnamed (like most things with "HDR" in their
> >>> name). It's just a "gimme moar precision" bit.
> >> Lets make this a bit more clear, may be rename the bit to
> >> PIPEMISC_HDR_PRECISION_MODE instead?
> > Then it won't match the spec.
>
> Well we are keeping HDR_MODE aren't we ? may be
> PIPEMISC_HDR_MODE_PRECISION if that makes us closer to spec ?
Not super convinved that really helps the reader in any significant way,
but I changed it anyway.
Series pushed to dinq. Thanks for the reviews.
>
> - Shashank
>
> >> With that change, this patch is
> >>
> >> Reviewed-by: Shashank Sharma
> >>
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)
== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2) URL : https://patchwork.freedesktop.org/series/59956/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12916 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59956/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12916 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#110235]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-glk-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-glk-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/fi-glk-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html Possible fixes * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602] / [fdo#108744]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (51 -> 45) -- Additional (2): fi-icl-y fi-bdw-5557u Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes - * Linux: CI_DRM_6018 -> Patchwork_12916 CI_DRM_6018: 03fe208c324d490589fef877aed0005bc8946451 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12916: 53aadb3c2bf507a8505f12b09fbb1a3f79f272bc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 53aadb3c2bf5 drm/i915: Fix 90/270 degree rotated RGB565 src coord checks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)
== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2) URL : https://patchwork.freedesktop.org/series/59956/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks -O:drivers/gpu/drm/i915/intel_sprite.c:305:31: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_sprite.c:305:31: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_sprite.c:309:31: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_sprite.c:309:31: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)
== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2) URL : https://patchwork.freedesktop.org/series/59956/ State : warning == Summary == $ dim checkpatch origin/drm-tip 53aadb3c2bf5 drm/i915: Fix 90/270 degree rotated RGB565 src coord checks -:47: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #47: FILE: drivers/gpu/drm/i915/intel_sprite.c:309: + hsub = vsub = max(hsub, vsub); total: 0 errors, 0 warnings, 1 checks, 43 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2
On Tue, Apr 30, 2019 at 01:10:02PM +0200, Christian König wrote:
> Add a structure for the parameters of dma_buf_attach, this makes it much
> easier
> to add new parameters later on.
I don't understand this reasoning. What are the "new parameters" that
are being proposed, and why do we need to put them into memory to pass
them across this interface?
If the intention is to make it easier to change the interface, passing
parameters in this manner mean that it's easy for the interface to
change and drivers not to notice the changes, since the compiler will
not warn (unless some member of the structure that the driver is using
gets removed, in which case it will error.)
Additions to the structure will go unnoticed by drivers - what if the
caller is expecting some different kind of behaviour, and the driver
ignores that new addition?
This doesn't seem to me like a good idea.
>
> v2: rebase cleanup and fix all new implementations as well
>
> Signed-off-by: Christian König
> ---
> drivers/dma-buf/dma-buf.c | 13 +++--
> drivers/gpu/drm/armada/armada_gem.c | 6 +-
> drivers/gpu/drm/drm_prime.c | 6 +-
> drivers/gpu/drm/i915/i915_gem_dmabuf.c | 6 +-
> drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 6 +-
> drivers/gpu/drm/tegra/gem.c | 6 +-
> drivers/gpu/drm/udl/udl_dmabuf.c| 6 +-
> .../common/videobuf2/videobuf2-dma-contig.c | 6 +-
> .../media/common/videobuf2/videobuf2-dma-sg.c | 6 +-
> drivers/misc/fastrpc.c | 6 +-
> drivers/staging/media/tegra-vde/tegra-vde.c | 6 +-
> drivers/xen/gntdev-dmabuf.c | 4
> include/linux/dma-buf.h | 17 +++--
> 13 files changed, 76 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index 3ae6c0c2cc02..e295e76a8c57 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -535,8 +535,9 @@ EXPORT_SYMBOL_GPL(dma_buf_put);
> /**
> * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
> * calls attach() of dma_buf_ops to allow device-specific attach
> functionality
> - * @dmabuf: [in]buffer to attach device to.
> - * @dev: [in]device to be attached.
> + * @info:[in]holds all the attach related information provided
> + * by the importer. see dma_buf_attach_info
> + * for further details.
> *
> * Returns struct dma_buf_attachment pointer for this attachment. Attachments
> * must be cleaned up by calling dma_buf_detach().
> @@ -550,20 +551,20 @@ EXPORT_SYMBOL_GPL(dma_buf_put);
> * accessible to @dev, and cannot be moved to a more suitable place. This is
> * indicated with the error code -EBUSY.
> */
> -struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
> - struct device *dev)
> +struct dma_buf_attachment *dma_buf_attach(const struct dma_buf_attach_info
> *info)
> {
> + struct dma_buf *dmabuf = info->dmabuf;
> struct dma_buf_attachment *attach;
> int ret;
>
> - if (WARN_ON(!dmabuf || !dev))
> + if (WARN_ON(!dmabuf || !info->dev))
> return ERR_PTR(-EINVAL);
>
> attach = kzalloc(sizeof(*attach), GFP_KERNEL);
> if (!attach)
> return ERR_PTR(-ENOMEM);
>
> - attach->dev = dev;
> + attach->dev = info->dev;
> attach->dmabuf = dmabuf;
>
> mutex_lock(>lock);
> diff --git a/drivers/gpu/drm/armada/armada_gem.c
> b/drivers/gpu/drm/armada/armada_gem.c
> index 642d0e70d0f8..19c47821032f 100644
> --- a/drivers/gpu/drm/armada/armada_gem.c
> +++ b/drivers/gpu/drm/armada/armada_gem.c
> @@ -501,6 +501,10 @@ armada_gem_prime_export(struct drm_device *dev, struct
> drm_gem_object *obj,
> struct drm_gem_object *
> armada_gem_prime_import(struct drm_device *dev, struct dma_buf *buf)
> {
> + struct dma_buf_attach_info attach_info = {
> + .dev = dev->dev,
> + .dmabuf = buf
> + };
> struct dma_buf_attachment *attach;
> struct armada_gem_object *dobj;
>
> @@ -516,7 +520,7 @@ armada_gem_prime_import(struct drm_device *dev, struct
> dma_buf *buf)
> }
> }
>
> - attach = dma_buf_attach(buf, dev->dev);
> + attach = dma_buf_attach(_info);
> if (IS_ERR(attach))
> return ERR_CAST(attach);
>
> diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
> index dc079efb3b0f..1dd70fc095ee 100644
> --- a/drivers/gpu/drm/drm_prime.c
> +++ b/drivers/gpu/drm/drm_prime.c
> @@ -710,6 +710,10 @@ struct drm_gem_object *drm_gem_prime_import_dev(struct
> drm_device *dev,
> struct dma_buf *dma_buf,
> struct device *attach_dev)
> {
> + struct
[Intel-gfx] [PATCH v2] drm/i915: Fix 90/270 degree rotated RGB565 src coord checks
From: Ville Syrjälä
Supposedly both src coordinates have to even when doing 90/270
degree rotation with RGB565. This is definitely true for the
X coordinate (we just get a black screen when it is odd). My
experiments didn't show any misbehaviour with an odd
Y coordinate, but let's trust the spec and reject that one
as well.
v2: Ignore ccs hsub/vsub
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sprite.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 2913e89280d7..b133f254e26d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -294,26 +294,32 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
src->y1 = src_y << 16;
src->y2 = (src_y + src_h) << 16;
- if (!fb->format->is_yuv)
- return 0;
-
- /* YUV specific checks */
- if (!rotated) {
+ if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
+ hsub = 2;
+ vsub = 2;
+ } else if (is_ccs_modifier(fb->modifier)) {
+ hsub = 1;
+ vsub = 1;
+ } else {
hsub = fb->format->hsub;
vsub = fb->format->vsub;
- } else {
- hsub = vsub = max(fb->format->hsub, fb->format->vsub);
}
+ if (rotated)
+ hsub = vsub = max(hsub, vsub);
+
+ if (hsub == 1 && vsub == 1)
+ return 0;
+
if (src_x % hsub || src_w % hsub) {
- DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for
%sYUV planes\n",
- src_x, src_w, hsub, rotated ? "rotated " : "");
+ DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u
(rotated: %s)\n",
+ src_x, src_w, hsub, yesno(rotated));
return -EINVAL;
}
if (src_y % vsub || src_h % vsub) {
- DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for
%sYUV planes\n",
- src_y, src_h, vsub, rotated ? "rotated " : "");
+ DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u
(rotated: %s)\n",
+ src_y, src_h, vsub, yesno(rotated));
return -EINVAL;
}
--
2.21.0
___
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Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats
On Thu, Apr 11, 2019 at 08:33:08PM +, Sripada, Radhakrishna wrote:
> On Thu, 2019-04-11 at 21:27 +0300, Ville Syrjälä wrote:
> > On Tue, Apr 09, 2019 at 02:04:01PM -0700, Dhinakaran Pandiyan wrote:
> > > On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote:
> > > > On Tue, Apr 09, 2019 at 01:28:18PM -0700, Dhinakaran Pandiyan
> > > > wrote:
> > > > > On Tue, 2019-03-26 at 16:25 +0200, Ville Syrjala wrote:
> > > > > > From: Ville Syrjälä
> > > > > >
> > > > > > 6bpc is only legal for RGB and RAW pixel encodings. For the
> > > > > > rest
> > > > > > the minimum is 8bpc. Set our lower limit accordingly.
> > > > >
> > > > > Patch doesn't apply anymore, got a conflict in intel_drv.h.
> > > > >
> > > > >
> > > > > > Signed-off-by: Ville Syrjälä
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/intel_dp.c | 10 +-
> > > > > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_drv.h| 1 +
> > > > > > 3 files changed, 11 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > > index 2aee526ed632..149fdfbcb343 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > > @@ -2002,6 +2002,14 @@ static int
> > > > > > intel_dp_dsc_compute_config(struct
> > > > > > intel_dp
> > > > > > *intel_dp,
> > > > > > return 0;
> > > > > > }
> > > > > >
> > > > > > +int intel_dp_min_bpp(const struct intel_crtc_state
> > > > > > *crtc_state)
> > > > > > +{
> > > > > > + if (crtc_state->output_format ==
> > > > > > INTEL_OUTPUT_FORMAT_RGB)
> > > > > > + return 6 * 3;
> > > > > > + else
> > > > > > + return 8 * 3;
> > > > >
> > > > > Code matches spec, however I think there is a possibility of
> > > > > min_bpp
> > > > > becoming
> > > > > greater than max_bpp. The max_bpc property allows user space to
> > > > > set a value
> > > > > of 6
> > > > > and limits.min_bpp can become 24 because of the code above. Add
> > > > > a check for
> > > > > that
> > > > > in compute_link_config()? Probably would mess up the
> > > > > compute_config() loop
> > > > > too.
> > > >
> > > > The code looks correct. Ie. should just end up with -EINVAL.
> > >
> > > Yup, it does now as I read it carefully again :)
> > > Reviewed-by: Dhinakaran Pandiyan
> >
> > Ta. Pushed.
> Late on jumping the train but dont we have to limit the range exposed
> while attaching the "max bpc" as well in this case?
Late answering too. No we can't limit the range because we don't know
ahead of time whether RGB or YCbCr is going to be used. Well, we could
reject 6bpc entirely but that seems a bit silly too. The atomic check
will simply fail if you try a combo that doesn't work.
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Multi-segmented-gamma for ICL
== Series Details == Series: Enable Multi-segmented-gamma for ICL URL : https://patchwork.freedesktop.org/series/60126/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12915 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60126/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12915 that come from known issues: ### IGT changes ### Possible fixes * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [INCOMPLETE][1] ([fdo#107718]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Warnings * igt@runner@aborted: - fi-skl-iommu: [FAIL][3] ([fdo#104108]) -> [FAIL][4] ([fdo#104108] / [fdo#108602]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-skl-iommu/igt@run...@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/fi-skl-iommu/igt@run...@aborted.html [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 Participating hosts (51 -> 45) -- Additional (2): fi-icl-y fi-bdw-5557u Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes - * Linux: CI_DRM_6018 -> Patchwork_12915 CI_DRM_6018: 03fe208c324d490589fef877aed0005bc8946451 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12915: 2a7a87a80902a2561002f64e9b448dfe66b3d84e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2a7a87a80902 drm/i915/icl: Add Multi-segmented gamma support 7bc8c7b747f3 drm/i915: Rename ivb_load_lut_10_max 8811262cd9fa drm/i915/icl: Add register definitions for Multi Segmented gamma dc4b88abc4e0 drm/i915: Change gamma/degamma_lut_size data type to u32 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/execlists: Flush the tasklet on parking
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Flush the tasklet on parking URL : https://patchwork.freedesktop.org/series/60125/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12914 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60125/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12914 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html Possible fixes * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [INCOMPLETE][3] ([fdo#108602] / [fdo#108744]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 Participating hosts (51 -> 45) -- Additional (2): fi-icl-y fi-bdw-5557u Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-icl-dsi Build changes - * Linux: CI_DRM_6018 -> Patchwork_12914 CI_DRM_6018: 03fe208c324d490589fef877aed0005bc8946451 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12914: a275ed900b95b45edfed4e0ba51fb3ad82e91803 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a275ed900b95 drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) bec98fa23875 drm/i915: Cancel retire_worker on parking a6e0369f7ee8 drm/i915: Remove delay for idle_work ceb2c36b05a7 drm/i915: Leave engine parking to the engines a172f241e431 drm/i915/execlists: Flush the tasklet on parking == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Drop the _INCOMPLETE for has_infoframe
== Series Details == Series: drm/i915: Drop the _INCOMPLETE for has_infoframe URL : https://patchwork.freedesktop.org/series/60120/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12913 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60120/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12913 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live_evict: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([fdo#107709]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-bsw-kefka/igt@i915_selftest@live_evict.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/fi-bsw-kefka/igt@i915_selftest@live_evict.html Possible fixes * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [INCOMPLETE][5] ([fdo#108602] / [fdo#108744]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 Participating hosts (51 -> 45) -- Additional (1): fi-bdw-5557u Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes - * Linux: CI_DRM_6018 -> Patchwork_12913 CI_DRM_6018: 03fe208c324d490589fef877aed0005bc8946451 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12913: ab2a73634670e81e55f995342ec203a2531e835c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ab2a73634670 drm/i915: Drop the _INCOMPLETE for has_infoframe == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Multi-segmented-gamma for ICL
== Series Details == Series: Enable Multi-segmented-gamma for ICL URL : https://patchwork.freedesktop.org/series/60126/ State : warning == Summary == $ dim checkpatch origin/drm-tip dc4b88abc4e0 drm/i915: Change gamma/degamma_lut_size data type to u32 8811262cd9fa drm/i915/icl: Add register definitions for Multi Segmented gamma 7bc8c7b747f3 drm/i915: Rename ivb_load_lut_10_max 2a7a87a80902 drm/i915/icl: Add Multi-segmented gamma support -:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #89: FILE: drivers/gpu/drm/i915/intel_color.c:789: +icl_load_gcmax(const struct intel_crtc_state *crtc_state, + const struct drm_color_lut *entry) total: 0 errors, 0 warnings, 1 checks, 159 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add N & CTS values for 10/12 bit deep color
On 4/30/19 2:25 AM, Jani Nikula wrote:
On Thu, 04 Apr 2019, Aditya Swarup wrote:
On Tue, Apr 02, 2019 at 05:14:40AM -0700, Aditya Swarup wrote:
Adding N & CTS values for 10/12 bit deep color from Appendix C
table in HDMI 2.0 spec. The correct values for N is not chosen
automatically by hardware for deep color modes.
v2: Remove redundant code and make it generic.(Jani)
Signed-off-by: Aditya Swarup
Cc: Clint Taylor
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Manasi Navare
---
drivers/gpu/drm/i915/intel_audio.c | 82 +-
1 file changed, 69 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 502b57ce72ab..ad53b04fa5a2 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -70,6 +70,13 @@ struct dp_aud_n_m {
u16 n;
};
+struct hdmi_aud_ncts_table {
+ int sample_rate;
+ int clock;
+ int n;
+ int cts;
+};
+
/* Values according to DP 1.4 Table 2-104 */
static const struct dp_aud_n_m dp_aud_n_m[] = {
{ 32000, LC_162M, 1024, 10125 },
@@ -146,12 +153,7 @@ static const struct {
#define TMDS_594M 594000
#define TMDS_593M 593407
-static const struct {
- int sample_rate;
- int clock;
- int n;
- int cts;
-} hdmi_aud_ncts[] = {
+static const struct hdmi_aud_ncts_table hdmi_aud_ncts_24bpp[] = {
{ 32000, TMDS_296M, 5824, 421875 },
{ 32000, TMDS_297M, 3072, 222750 },
{ 32000, TMDS_593M, 5824, 843750 },
@@ -182,6 +184,49 @@ static const struct {
{ 192000, TMDS_594M, 24576, 594000 },
};
+/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
+/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
+#define TMDS_371M 371250
+#define TMDS_370M 370878
+
+static const struct hdmi_aud_ncts_table hdmi_aud_ncts_30bpp[] = {
+ { 32000, TMDS_370M, 5824, 527344 },
+ { 32000, TMDS_371M, 6144, 556875 },
+ { 44100, TMDS_370M, 8918, 585938 },
+ { 44100, TMDS_371M, 4704, 309375 },
+ { 88200, TMDS_370M, 17836, 585938 },
+ { 88200, TMDS_371M, 9408, 309375 },
+ { 176400, TMDS_370M, 35672, 585938 },
+ { 176400, TMDS_371M, 18816, 309375 },
+ { 48000, TMDS_370M, 11648, 703125 },
+ { 48000, TMDS_371M, 5120, 309375 },
+ { 96000, TMDS_370M, 23296, 703125 },
+ { 96000, TMDS_371M, 10240, 309375 },
+ { 192000, TMDS_370M, 46592, 703125 },
+ { 192000, TMDS_371M, 20480, 309375 },
+};
+
+/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
+#define TMDS_445_5M 445500
+#define TMDS_445M 445054
+
+static const struct hdmi_aud_ncts_table hdmi_aud_ncts_36bpp[] = {
+ { 32000, TMDS_445M, 5824, 632813 },
+ { 32000, TMDS_445_5M, 4096, 445500 },
+ { 44100, TMDS_445M, 8918, 703125 },
+ { 44100, TMDS_445_5M, 4704, 371250 },
+ { 88200, TMDS_445M, 17836, 703125 },
+ { 88200, TMDS_445_5M, 9408, 371250 },
+ { 176400, TMDS_445M, 35672, 703125 },
+ { 176400, TMDS_445_5M, 18816, 371250 },
+ { 48000, TMDS_445M, 5824, 421875 },
+ { 48000, TMDS_445_5M, 5120, 371250 },
+ { 96000, TMDS_445M, 11648, 421875 },
+ { 96000, TMDS_445_5M, 10240, 371250 },
+ { 192000, TMDS_445M, 23296, 421875 },
+ { 192000, TMDS_445_5M, 20480, 371250 },
+};
+
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state
*crtc_state)
{
@@ -210,16 +255,27 @@ static u32 audio_config_hdmi_pixel_clock(const struct
intel_crtc_state *crtc_sta
static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
int rate)
{
- const struct drm_display_mode *adjusted_mode =
- _state->base.adjusted_mode;
- int i;
+ const struct hdmi_aud_ncts_table *hdmi_ncts_table;
+ int i, size = 0;
+
+ if (crtc_state->pipe_bpp == 36) {
+ hdmi_ncts_table = hdmi_aud_ncts_36bpp;
+ size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
+ } else if (crtc_state->pipe_bpp == 30) {
+ hdmi_ncts_table = hdmi_aud_ncts_30bpp;
+ size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
+ } else {
+ hdmi_ncts_table = hdmi_aud_ncts_24bpp;
+ size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
+ }
- for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
- if (rate == hdmi_aud_ncts[i].sample_rate &&
- adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
- return hdmi_aud_ncts[i].n;
+ for (i = 0; i < size; i++) {
+ if (rate == hdmi_ncts_table[i].sample_rate &&
+ crtc_state->port_clock == hdmi_ncts_table[i].clock) {
+ return hdmi_ncts_table[i].n;
}
}
+
return 0;
}
--
2.17.1
Jani
Do you want me to change anything in this patch?
Hey, please don't drop
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is
bogus
URL : https://patchwork.freedesktop.org/series/60119/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12912
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/60119/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12912:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_backlight@basic-brightness:
- {fi-cml-u2}:NOTRUN -> [SKIP][1] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/fi-cml-u2/igt@i915_pm_backli...@basic-brightness.html
Known issues
Here are the changes found in Patchwork_12912 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-icl-y: [PASS][2] -> [INCOMPLETE][3] ([fdo#107713] /
[fdo#108569])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-icl-y/igt@i915_selftest@live_contexts.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/fi-icl-y/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: [PASS][4] -> [INCOMPLETE][5] ([fdo#108602] /
[fdo#108744])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][6] -> [FAIL][7] ([fdo#109485])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [DMESG-FAIL][8] ([fdo#110235]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
- fi-skl-gvtdvm: [DMESG-FAIL][10] ([fdo#110235]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@dp-crc-fast:
- {fi-cml-u2}:[DMESG-WARN][12] ([fdo#103841]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (53 -> 46)
--
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-
* Linux: CI_DRM_6017 -> Patchwork_12912
CI_DRM_6017: 69c3a37af9430650d1fc2ad4d0786898694d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12912: b8472fe8ca94a9efbe9689f0c9ad6a6d875c809a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b8472fe8ca94 drm/i915: hsw+ audio regs are per-transocder
e685e5944a53 drm/i915: Don't skip audio enable if ELD is bogus
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12912/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2
Hi "Christian,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.1-rc7 next-20190429]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Christian-K-nig/dma-buf-add-struct-dma_buf_attach_info-v2/20190430-221017
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 8.1.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=8.1.0 make.cross ARCH=xtensa
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/staging/media/tegra-vde/tegra-vde.c: In function
'tegra_vde_attach_dmabuf':
>> drivers/staging/media/tegra-vde/tegra-vde.c:573:13: error: 'dmabuf'
>> undeclared (first use in this function); did you mean 'dma_buf'?
.dmabuf = dmabuf
^~
dma_buf
drivers/staging/media/tegra-vde/tegra-vde.c:573:13: note: each undeclared
identifier is reported only once for each function it appears in
vim +573 drivers/staging/media/tegra-vde/tegra-vde.c
559
560 static int tegra_vde_attach_dmabuf(struct device *dev,
561 int fd,
562 unsigned long offset,
563 size_t min_size,
564 size_t align_size,
565 struct dma_buf_attachment **a,
566 dma_addr_t *addr,
567 struct sg_table **s,
568 size_t *size,
569 enum dma_data_direction dma_dir)
570 {
571 struct dma_buf_attach_info attach_info = {
572 .dev = dev,
> 573 .dmabuf = dmabuf
574 };
575 struct dma_buf_attachment *attachment;
576 struct dma_buf *dmabuf;
577 struct sg_table *sgt;
578 int err;
579
580 dmabuf = dma_buf_get(fd);
581 if (IS_ERR(dmabuf)) {
582 dev_err(dev, "Invalid dmabuf FD\n");
583 return PTR_ERR(dmabuf);
584 }
585
586 if (dmabuf->size & (align_size - 1)) {
587 dev_err(dev, "Unaligned dmabuf 0x%zX, should be aligned
to 0x%zX\n",
588 dmabuf->size, align_size);
589 return -EINVAL;
590 }
591
592 if ((u64)offset + min_size > dmabuf->size) {
593 dev_err(dev, "Too small dmabuf size %zu @0x%lX, should
be at least %zu\n",
594 dmabuf->size, offset, min_size);
595 return -EINVAL;
596 }
597
598 attachment = dma_buf_attach(_info);
599 if (IS_ERR(attachment)) {
600 dev_err(dev, "Failed to attach dmabuf\n");
601 err = PTR_ERR(attachment);
602 goto err_put;
603 }
604
605 sgt = dma_buf_map_attachment(attachment, dma_dir);
606 if (IS_ERR(sgt)) {
607 dev_err(dev, "Failed to get dmabufs sg_table\n");
608 err = PTR_ERR(sgt);
609 goto err_detach;
610 }
611
612 if (sgt->nents != 1) {
613 dev_err(dev, "Sparse DMA region is unsupported\n");
614 err = -EINVAL;
615 goto err_unmap;
616 }
617
618 *addr = sg_dma_address(sgt->sgl) + offset;
619 *a = attachment;
620 *s = sgt;
621
622 if (size)
623 *size = dmabuf->size - offset;
624
625 return 0;
626
627 err_unmap:
628 dma_buf_unmap_attachment(attachment, sgt, dma_dir);
629 err_detach:
630 dma_buf_detach(dmabuf, attachment);
631 err_put:
632 dma_buf_put(dmabuf);
633
634 return err;
635 }
636
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/4] drm/i915/icl: Add Multi-segmented gamma support
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from value range between 0.0 to 1.0,
ICL's multi-segment has 3 different sections:
- superfine segment: 9 values, ranges between 0 - 1/(128 * 256)
- fine segment: 257 values, ranges between 0 - 1/(128)
- corase segment: 257 values, ranges between 0 - 1
This patch:
- Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 * 256),
so that userspace can program with highest precision supported.
- Changes default gamma mode (non-legacy) to multi-segmented-gamma mode.
- Adds functions to program/detect multi-segment gamma.
V2: Addressed review comments from Ville
- separate function for superfine and fine segments.
- remove enum for segments.
- reuse last entry of the LUT as gc_max value.
- replace if() cond with switch...case in icl_load_luts.
- add an entry variable, instead of 'word'
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Suggested-by: Ville Syrjälä
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c| 3 +-
drivers/gpu/drm/i915/intel_color.c | 125 -
2 files changed, 123 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ffa2ee70a03d..83698951760b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -749,7 +749,8 @@ static const struct intel_device_info intel_cannonlake_info
= {
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1, \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
+ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262144 }
+
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 6c341bea514c..49831e8d02fb 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -41,6 +41,9 @@
#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
#define LEGACY_LUT_LENGTH 256
+#define ICL_GAMMA_MULTISEG_LUT_LENGTH (256 * 128 * 8)
+#define ICL_GAMMA_SUPERFINE_SEG_LENGTH 9
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -767,6 +770,113 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
}
}
+/* ilk+ "12.4" interpolated format (high 10 bits) */
+static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
+{
+ return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
+ (color->blue >> 6);
+}
+
+/* ilk+ "12.4" interpolated format (low 6 bits) */
+static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
+{
+ return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
+ (color->blue & 0x3f);
+}
+
+static void
+icl_load_gcmax(const struct intel_crtc_state *crtc_state,
+ const struct drm_color_lut *entry)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ /* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), entry->red);
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), entry->green);
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), entry->blue);
+}
+
+static void
+icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
+ const struct drm_color_lut *lut = blob->data;
+ enum pipe pipe = crtc->pipe;
+ u32 i;
+
+ if (!lut || drm_color_lut_size(blob) < ICL_GAMMA_SUPERFINE_SEG_LENGTH)
+ return;
+
+ /*
+* Every entry in the multi-segment LUT is corresponding to a superfine
+* segment step which is 1/(8 * 128 * 256).
+*
+* Superfine segment has 9 entries, corresponding to values
+* 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) 8/(8 * 128 * 256).
+*/
+ I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < 9; i++) {
+ const struct drm_color_lut *entry = [i];
+
+ I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
+ ilk_lut_12p4_udw(entry));
+ I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
+
[Intel-gfx] [PATCH v2 3/4] drm/i915: Rename ivb_load_lut_10_max
This patch renames function ivb_load_lut_10_max to
ivb_load_lut_ext_max.
Cc: Uma Shankar
Suggested-by: Ville Syrjala
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_color.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 962db1236970..6c341bea514c 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -607,7 +607,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
-static void ivb_load_lut_10_max(struct intel_crtc *crtc)
+static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -640,7 +640,7 @@ static void ivb_load_luts(const struct intel_crtc_state
*crtc_state)
} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(512));
} else {
@@ -648,7 +648,7 @@ static void ivb_load_luts(const struct intel_crtc_state
*crtc_state)
ivb_load_lut_10(crtc, blob,
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
@@ -663,7 +663,7 @@ static void bdw_load_luts(const struct intel_crtc_state
*crtc_state)
} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(512));
} else {
@@ -671,7 +671,7 @@ static void bdw_load_luts(const struct intel_crtc_state
*crtc_state)
bdw_load_lut_10(crtc, blob,
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
@@ -763,7 +763,7 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
i9xx_load_luts(crtc_state);
} else {
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
@@ -780,7 +780,7 @@ static void icl_load_luts(const struct intel_crtc_state
*crtc_state)
i9xx_load_luts(crtc_state);
} else {
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
--
2.17.1
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[Intel-gfx] [PATCH v2 2/4] drm/i915/icl: Add register definitions for Multi Segmented gamma
From: Uma Shankar
Add macros to define multi segmented gamma registers
V2: Addressed Ville's comments:
Add gen-lable before bit definition
Addressed Jani's comment
- Use REG_GENMASK() and REG_BIT()
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Maarten Lankhorst
Signed-off-by: Uma Shankar
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/i915_reg.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f0a0866c802..7d10b8d00d64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7198,7 +7198,10 @@ enum {
#define GAMMA_MODE_MODE_8BIT (0 << 0)
#define GAMMA_MODE_MODE_10BIT (1 << 0)
#define GAMMA_MODE_MODE_12BIT (2 << 0)
+/* ivb-bdw */
#define GAMMA_MODE_MODE_SPLIT (3 << 0)
+/* icl + */
+#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0)
/* DMC/CSR */
#define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
@@ -10145,6 +10148,22 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Add registers for Gen11 Multi Segmented Gamma Mode */
+#define _PAL_PREC_MULTI_SEG_INDEX_A0x4A408
+#define _PAL_PREC_MULTI_SEG_INDEX_B0x4AC08
+#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
+#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
+
+#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
+#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+
+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_INDEX_A, \
+ _PAL_PREC_MULTI_SEG_INDEX_B)
+#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_DATA_A, \
+ _PAL_PREC_MULTI_SEG_DATA_B)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
2.17.1
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[Intel-gfx] [PATCH v2 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32
Currently, data type of gamma_lut_size & degamma_lut_size elements
in intel_device_info is u16, which means it can accommodate maximum
64k values. In case of ICL multisegmented gamma, the size of gamma
LUT is 256K.
This patch changes the data type of both of these elements to u32.
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Uma Shankar
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_device_info.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..67677c356716 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -179,8 +179,8 @@ struct intel_device_info {
int cursor_offsets[I915_MAX_PIPES];
struct color_luts {
- u16 degamma_lut_size;
- u16 gamma_lut_size;
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
u32 degamma_lut_tests;
u32 gamma_lut_tests;
} color;
--
2.17.1
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[Intel-gfx] [PATCH v2 0/4] Enable Multi-segmented-gamma for ICL
This patch series enables programming of Multi-segmented-gamma palette for ICL. Shashank Sharma (3): drm/i915: Change gamma/degamma_lut_size data type to u32 drm/i915: Rename ivb_load_lut_10_max drm/i915/icl: Add Multi-segmented gamma support Uma Shankar (1): drm/i915/icl: Add register definitions for Multi Segmented gamma drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 19 drivers/gpu/drm/i915/intel_color.c | 139 +-- drivers/gpu/drm/i915/intel_device_info.h | 4 +- 4 files changed, 151 insertions(+), 14 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915/execlists: Flush the tasklet on parking
Tidy up the cleanup sequence by always ensure that the tasklet is
flushed on parking (before we cleanup). The parking provides a
convenient point to ensure that the backend is truly idle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++--
drivers/gpu/drm/i915/intel_guc_submission.c | 1 +
2 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 01f58a152a9e..ea7794d368d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2331,27 +2331,18 @@ static int gen8_init_rcs_context(struct i915_request
*rq)
return i915_gem_render_state_emit(rq);
}
+static void execlists_park(struct intel_engine_cs *engine)
+{
+ tasklet_kill(>execlists.tasklet);
+}
+
/**
* intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
* @engine: Engine Command Streamer.
*/
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv;
-
- /*
-* Tasklet cannot be active at this point due intel_mark_active/idle
-* so this is just for documentation.
-*/
- if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
->execlists.tasklet.state)))
- tasklet_kill(>execlists.tasklet);
-
- dev_priv = engine->i915;
-
- if (engine->buffer) {
- WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
- }
+ struct drm_i915_private *i915 = engine->i915;
if (engine->cleanup)
engine->cleanup(engine);
@@ -2361,7 +2352,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs
*engine)
lrc_destroy_wa_ctx(engine);
engine->i915 = NULL;
- dev_priv->engine[engine->id] = NULL;
+ i915->engine[engine->id] = NULL;
kfree(engine);
}
@@ -2376,7 +2367,7 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->reset.reset = execlists_reset;
engine->reset.finish = execlists_reset_finish;
- engine->park = NULL;
+ engine->park = execlists_park;
engine->unpark = NULL;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 4c814344809c..ed94001028f2 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1363,6 +1363,7 @@ static void guc_interrupts_release(struct
drm_i915_private *dev_priv)
static void guc_submission_park(struct intel_engine_cs *engine)
{
+ tasklet_kill(>execlists.tasklet);
intel_engine_unpin_breadcrumbs_irq(engine);
engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
--
2.20.1
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[Intel-gfx] [PATCH 2/5] drm/i915: Leave engine parking to the engines
Drop the check in GEM parking that the engines were already parked. The
intention here was that before we dropped the GT wakeref, we were sure
that no more interrupts could be raised -- however, we have already
dropped the wakeref by this point and the warning is no longer valid.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_pm.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 3b6e8d5be8e1..49b0ce594f20 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -17,24 +17,8 @@ static void i915_gem_park(struct drm_i915_private *i915)
lockdep_assert_held(>drm.struct_mutex);
- for_each_engine(engine, i915, id) {
- /*
-* We are committed now to parking the engines, make sure there
-* will be no more interrupts arriving later and the engines
-* are truly idle.
-*/
- if (wait_for(intel_engine_is_idle(engine), 10)) {
- struct drm_printer p = drm_debug_printer(__func__);
-
- dev_err(i915->drm.dev,
- "%s is not idle before parking\n",
- engine->name);
- intel_engine_dump(engine, , NULL);
- }
- tasklet_kill(>execlists.tasklet);
-
+ for_each_engine(engine, i915, id)
i915_gem_batch_pool_fini(>batch_pool);
- }
i915_timelines_park(i915);
i915_vma_parked(i915);
--
2.20.1
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[Intel-gfx] [PATCH 3/5] drm/i915: Remove delay for idle_work
The original intent for the delay before running the idle_work was to
provide a hysteresis to avoid ping-ponging the device runtime-pm. Since
then we have also pulled in some memory management and general device
management for parking. But with the inversion of the wakeref handling,
GEM is no longer responsible for the wakeref and by the time we call the
idle_work, the device is asleep. It seems appropriate now to drop the
delay and just run the worker immediately to flush the cached GEM state
before sleeping.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_pm.c| 21 +++
.../gpu/drm/i915/selftests/i915_gem_object.c | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 ++--
5 files changed, 12 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0e4dffcd4da4..7e8898d0b78b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3935,8 +3935,8 @@ i915_drop_caches_set(void *data, u64 val)
if (val & DROP_IDLE) {
do {
flush_delayed_work(>gem.retire_work);
- drain_delayed_work(>gem.idle_work);
} while (READ_ONCE(i915->gt.awake));
+ flush_work(>gem.idle_work);
}
if (val & DROP_FREED)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 886a30243fe3..2560f38f9f60 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2037,7 +2037,7 @@ struct drm_i915_private {
* arrive within a small period of time, we fire
* off the idle_work.
*/
- struct delayed_work idle_work;
+ struct work_struct idle_work;
} gem;
/* For i945gm vblank irq vs. C3 workaround */
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 49b0ce594f20..ae91ad7cb31e 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -29,12 +29,12 @@ static void i915_gem_park(struct drm_i915_private *i915)
static void idle_work_handler(struct work_struct *work)
{
struct drm_i915_private *i915 =
- container_of(work, typeof(*i915), gem.idle_work.work);
+ container_of(work, typeof(*i915), gem.idle_work);
mutex_lock(>drm.struct_mutex);
intel_wakeref_lock(>gt.wakeref);
- if (!intel_wakeref_active(>gt.wakeref))
+ if (!intel_wakeref_active(>gt.wakeref) && !work_pending(work))
i915_gem_park(i915);
intel_wakeref_unlock(>gt.wakeref);
@@ -74,9 +74,7 @@ static int pm_notifier(struct notifier_block *nb,
break;
case INTEL_GT_PARK:
- mod_delayed_work(i915->wq,
->gem.idle_work,
-msecs_to_jiffies(100));
+ queue_work(i915->wq, >gem.idle_work);
break;
}
@@ -142,16 +140,11 @@ void i915_gem_suspend(struct drm_i915_private *i915)
* Assert that we successfully flushed all the work and
* reset the GPU back to its idle, low power state.
*/
- GEM_BUG_ON(i915->gt.awake);
- cancel_delayed_work_sync(>gpu_error.hangcheck_work);
-
drain_delayed_work(>gem.retire_work);
+ GEM_BUG_ON(i915->gt.awake);
+ flush_work(>gem.idle_work);
- /*
-* As the idle_work is rearming if it detects a race, play safe and
-* repeat the flush until it is definitely idle.
-*/
- drain_delayed_work(>gem.idle_work);
+ cancel_delayed_work_sync(>gpu_error.hangcheck_work);
i915_gem_drain_freed_objects(i915);
@@ -242,7 +235,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
void i915_gem_init__pm(struct drm_i915_private *i915)
{
- INIT_DELAYED_WORK(>gem.idle_work, idle_work_handler);
+ INIT_WORK(>gem.idle_work, idle_work_handler);
INIT_DELAYED_WORK(>gem.retire_work, retire_work_handler);
i915->gem.pm_notifier.notifier_call = pm_notifier;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index 088b2aa05dcd..b926d1cd165d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -509,7 +509,7 @@ static void disable_retire_worker(struct drm_i915_private
*i915)
intel_gt_pm_get(i915);
cancel_delayed_work_sync(>gem.retire_work);
- cancel_delayed_work_sync(>gem.idle_work);
+ flush_work(>gem.idle_work);
}
static void restore_retire_worker(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
[Intel-gfx] [PATCH 5/5] drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches)
If the user is racing a call to debugfs/i915_drop_caches with ongoing
submission from another thread/process, we may never end up idling the
GPU and be uninterruptibly spinning in debugfs/i915_drop_caches trying
to catch an idle moment.
Just flush the work once, that should be enough to park the system under
correct conditions. Outside of those we either have a driver bug or the
user is racing themselves. Sadly, because the user may be provoking the
unwanted situation we can't put a warn here to attract attention to a
probable bug.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7e8898d0b78b..2ecefacb1e66 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3933,9 +3933,7 @@ i915_drop_caches_set(void *data, u64 val)
fs_reclaim_release(GFP_KERNEL);
if (val & DROP_IDLE) {
- do {
- flush_delayed_work(>gem.retire_work);
- } while (READ_ONCE(i915->gt.awake));
+ flush_delayed_work(>gem.retire_work);
flush_work(>gem.idle_work);
}
--
2.20.1
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[Intel-gfx] [PATCH 4/5] drm/i915: Cancel retire_worker on parking
Replace the racy continuation check within retire_work with a definite
kill-switch on idling. The race was being exposed by gem_concurrent_blit
where the retire_worker would be terminated too early leaving us
spinning in debugfs/i915_drop_caches with nothing flushing the
retirement queue.
Although that the igt is trying to idle from one child while submitting
from another may be a contributing factor as to why it runs so slowly...
Testcase: igt/gem_concurrent_blit
Fixes: 79ffac8599c4 ("drm/i915: Invert the GEM wakeref hierarchy")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_pm.c | 18 --
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 -
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index ae91ad7cb31e..b239b55f84cd 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -30,15 +30,23 @@ static void idle_work_handler(struct work_struct *work)
{
struct drm_i915_private *i915 =
container_of(work, typeof(*i915), gem.idle_work);
+ bool restart = true;
+ cancel_delayed_work_sync(>gem.retire_work);
mutex_lock(>drm.struct_mutex);
intel_wakeref_lock(>gt.wakeref);
- if (!intel_wakeref_active(>gt.wakeref) && !work_pending(work))
+ if (!intel_wakeref_active(>gt.wakeref) && !work_pending(work)) {
i915_gem_park(i915);
+ restart = false;
+ }
intel_wakeref_unlock(>gt.wakeref);
mutex_unlock(>drm.struct_mutex);
+ if (restart)
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
}
static void retire_work_handler(struct work_struct *work)
@@ -52,10 +60,9 @@ static void retire_work_handler(struct work_struct *work)
mutex_unlock(>drm.struct_mutex);
}
- if (intel_wakeref_active(>gt.wakeref))
- queue_delayed_work(i915->wq,
- >gem.retire_work,
- round_jiffies_up_relative(HZ));
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
}
static int pm_notifier(struct notifier_block *nb,
@@ -140,7 +147,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
* Assert that we successfully flushed all the work and
* reset the GPU back to its idle, low power state.
*/
- drain_delayed_work(>gem.retire_work);
GEM_BUG_ON(i915->gt.awake);
flush_work(>gem.idle_work);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index d919f512042c..9fd02025d382 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -58,7 +58,6 @@ static void mock_device_release(struct drm_device *dev)
i915_gem_contexts_lost(i915);
mutex_unlock(>drm.struct_mutex);
- drain_delayed_work(>gem.retire_work);
flush_work(>gem.idle_work);
i915_gem_drain_workqueue(i915);
--
2.20.1
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus
== Series Details == Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus URL : https://patchwork.freedesktop.org/series/60119/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Don't skip audio enable if ELD is bogus Okay! Commit: drm/i915: hsw+ audio regs are per-transocder -O:drivers/gpu/drm/i915/intel_audio.c:485:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:482:15: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus
== Series Details == Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus URL : https://patchwork.freedesktop.org/series/60119/ State : warning == Summary == $ dim checkpatch origin/drm-tip e685e5944a53 drm/i915: Don't skip audio enable if ELD is bogus b8472fe8ca94 drm/i915: hsw+ audio regs are per-transocder -:30: WARNING:LONG_LINE: line over 100 characters #30: FILE: drivers/gpu/drm/i915/i915_reg.h:9017: +#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) -:35: WARNING:LONG_LINE: line over 100 characters #35: FILE: drivers/gpu/drm/i915/i915_reg.h:9021: +#define HSW_AUD_M_CTS_ENABLE(trans)_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) -:43: WARNING:LONG_LINE: line over 100 characters #43: FILE: drivers/gpu/drm/i915/i915_reg.h:9028: +#define HSW_AUD_DIP_ELD_CTRL(trans)_MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) -:55: WARNING:LONG_LINE: line over 100 characters #55: FILE: drivers/gpu/drm/i915/i915_reg.h:9038: +#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) total: 0 errors, 4 warnings, 0 checks, 195 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix setting 10 bit deep color mode
On Mon, Apr 29, 2019 at 05:00:28PM -0700, Aditya Swarup wrote: > From: Ville Syrjälä > > There is a bug in hdmi_deep_color_possible() - we compare pipe_bpp > <= 8*3 which returns true every time for hdmi_deep_color_possible 12 bit > deep color mode test in intel_hdmi_compute_config().(Even when the > requested color mode is 10 bit through max bpc property) > > Comparing pipe_bpp with bpc * 3 takes care of this condition where > requested max bpc is 10 bit, so hdmi_deep_color_possible with 12 bit > returns false when requested max bpc is 10. > > Signed-off-by: Ville Syrjälä How did my sob appear on this? Pretty sure I didn't actually put it here. > Signed-off-by: Aditya Swarup > Cc: Jani Nikula > Cc: Manasi Navare > Cc: Clinton Taylor > --- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index 991eb362ef4f..74f2dcb8b1ad 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -2159,7 +2159,7 @@ static bool hdmi_deep_color_possible(const struct > intel_crtc_state *crtc_state, > if (bpc == 10 && INTEL_GEN(dev_priv) < 11) > return false; > > - if (crtc_state->pipe_bpp <= 8*3) > + if (crtc_state->pipe_bpp < bpc * 3) > return false; > > if (!crtc_state->has_hdmi_sink) > -- > 2.17.1 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Corrupt DSI picture fix for GeminiLake (rev3)
== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake (rev3) URL : https://patchwork.freedesktop.org/series/60084/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12911 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60084/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_12911 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] ([fdo#108602] / [fdo#108744]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([fdo#103841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-7500u: [PASS][5] -> [WARN][6] ([fdo#109483]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: [DMESG-FAIL][7] ([fdo#110235]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html - fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#110235]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html * igt@i915_selftest@live_hangcheck: - fi-icl-y: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-icl-y/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/fi-icl-y/igt@i915_selftest@live_hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-glk-dsi: [FAIL][13] ([fdo#103167]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-glk-dsi/igt@kms_frontbuffer_track...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/fi-glk-dsi/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (53 -> 46) -- Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes - * Linux: CI_DRM_6017 -> Patchwork_12911 CI_DRM_6017: 69c3a37af9430650d1fc2ad4d0786898694d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12911: b84ff6ec314f950cef86396a816751669e006d1b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b84ff6ec314f drm/i915: Corrupt DSI picture fix for GeminiLake == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12911/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Corrupt DSI picture fix for GeminiLake (rev3)
== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake (rev3) URL : https://patchwork.freedesktop.org/series/60084/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Corrupt DSI picture fix for GeminiLake -O:drivers/gpu/drm/i915/intel_cdclk.c:2266:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2266:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2275:29: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add single combo phy init/unit functions
== Series Details == Series: drm/i915: add single combo phy init/unit functions URL : https://patchwork.freedesktop.org/series/60112/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12910 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60112/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12910 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108569]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12910/fi-icl-u3/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([fdo#103841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12910/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [DMESG-FAIL][5] ([fdo#110235]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12910/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (53 -> 44) -- Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-skl-6260u fi-ctg-p8600 fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_6017 -> Patchwork_12910 CI_DRM_6017: 69c3a37af9430650d1fc2ad4d0786898694d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12910: 13493cf9238da928e7b0e66a0e198c5ba87f4f9a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 13493cf9238d drm/i915: add single combo phy init/unit functions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12910/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Fix setting 10 bit deep color mode
== Series Details == Series: drm/i915/icl: Fix setting 10 bit deep color mode URL : https://patchwork.freedesktop.org/series/60080/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12901_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12901_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12901_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12901_full: ### IGT changes ### Possible regressions * igt@gem_mmap_gtt@forked-big-copy-odd: - shard-skl: NOTRUN -> [INCOMPLETE][1] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-skl8/igt@gem_mmap_...@forked-big-copy-odd.html * igt@kms_pipe_crc_basic@read-crc-pipe-b: - shard-skl: [PASS][2] -> [INCOMPLETE][3] +9 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl7/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-skl3/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html Known issues Here are the changes found in Patchwork_12901_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@basic-bsd: - shard-apl: [PASS][4] -> [INCOMPLETE][5] ([fdo#103927]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-apl4/igt@gem_exec_ba...@basic-bsd.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-apl3/igt@gem_exec_ba...@basic-bsd.html * igt@kms_cursor_crc@cursor-64x21-offscreen: - shard-skl: [PASS][6] -> [FAIL][7] ([fdo#103232]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl2/igt@kms_cursor_...@cursor-64x21-offscreen.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-skl8/igt@kms_cursor_...@cursor-64x21-offscreen.html * igt@kms_cursor_crc@cursor-64x64-rapid-movement: - shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([fdo#107713]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb3/igt@kms_cursor_...@cursor-64x64-rapid-movement.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-iclb8/igt@kms_cursor_...@cursor-64x64-rapid-movement.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][10] -> [FAIL][11] ([fdo#103355]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html * igt@kms_flip@2x-flip-vs-dpms: - shard-hsw: [PASS][12] -> [INCOMPLETE][13] ([fdo#103540]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-hsw5/igt@kms_f...@2x-flip-vs-dpms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-hsw8/igt@kms_f...@2x-flip-vs-dpms.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][14] -> [FAIL][15] ([fdo#105363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-glk8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-glk: [PASS][16] -> [INCOMPLETE][17] ([fdo#103359] / [k.org#198133]) +4 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk5/igt@kms_f...@flip-vs-suspend-interruptible.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-glk8/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-skl: [PASS][18] -> [INCOMPLETE][19] ([fdo#109507]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl1/igt@kms_f...@flip-vs-suspend-interruptible.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-skl2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +8 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12901/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
[Intel-gfx] [PATCH] drm/i915: Drop the _INCOMPLETE for has_infoframe
From: Ville Syrjälä We have full infoframe readout now so we can replace the PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe) with the normal PIPE_CONF_CHECK_BOOL(has_infoframe). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 03a2a708bc0f..e9d95e7acfe9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12329,7 +12329,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_BOOL(hdmi_scrambling); PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); - PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe); + PIPE_CONF_CHECK_BOOL(has_infoframe); PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Don't skip audio enable if ELD is bogus
From: Ville Syrjälä
We've already committed to enabling audio when intel_audio_codec_enable()
is called. We can't back out even if the ELD has turned sour in the
meantime. So just spew some debug log and plow ahead. Otherwise the
state checker gets unhappy when audio isn't enabled when it is
expected to be.
I suppose we really ought to precompute the ELD as well, but
let's just toss in a FIXME for the future.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103841
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_audio.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index bca4cc025d3d..68a24dada44c 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -644,8 +644,10 @@ void intel_audio_codec_enable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
+ /* FIXME precompute the ELD in .compute_config() */
if (!connector->eld[0])
- return;
+ DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n",
+ connector->base.id, connector->name);
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id,
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: hsw+ audio regs are per-transocder
From: Ville Syrjälä
s/pipe/transcoder/ when dealing with hsw+ audio registers. This
won't actually make any real difference since there is no audio
on the EDP transcoder. But this should avoid a bit of confusion
when cross checking against the spec.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h| 12 +++
drivers/gpu/drm/i915/intel_audio.c | 55 ++
2 files changed, 32 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f0a0866c802..926e058d09ee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9010,32 +9010,32 @@ enum {
/* HSW Audio */
#define _HSW_AUD_CONFIG_A 0x65000
#define _HSW_AUD_CONFIG_B 0x65100
-#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A,
_HSW_AUD_CONFIG_B)
+#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A,
_HSW_AUD_CONFIG_B)
#define _HSW_AUD_MISC_CTRL_A 0x65010
#define _HSW_AUD_MISC_CTRL_B 0x65110
-#define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
+#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans,
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
#define _HSW_AUD_M_CTS_ENABLE_A0x65028
#define _HSW_AUD_M_CTS_ENABLE_B0x65128
-#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define HSW_AUD_M_CTS_ENABLE(trans)_MMIO_TRANS(trans,
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
#define AUD_CONFIG_M_MASK0xf
#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
-#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe,
_HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
+#define HSW_AUD_DIP_ELD_CTRL(trans)_MMIO_TRANS(trans,
_HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
/* Audio Digital Converter */
#define _HSW_AUD_DIG_CNVT_10x65080
#define _HSW_AUD_DIG_CNVT_20x65180
-#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1,
_HSW_AUD_DIG_CNVT_2)
+#define AUD_DIG_CNVT(trans)_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1,
_HSW_AUD_DIG_CNVT_2)
#define DIP_PORT_SEL_MASK 0x3
#define _HSW_AUD_EDID_DATA_A 0x65050
#define _HSW_AUD_EDID_DATA_B 0x65150
-#define HSW_AUD_EDID_DATA(pipe)_MMIO_PIPE(pipe,
_HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
+#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans,
_HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 68a24dada44c..5c0b73f63843 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -319,9 +319,8 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct i915_audio_component *acomp = dev_priv->audio_component;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
- enum pipe pipe = crtc->pipe;
const struct dp_aud_n_m *nm;
int rate;
u32 tmp;
@@ -333,7 +332,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
else
DRM_DEBUG_KMS("using automatic Maud, Naud\n");
- tmp = I915_READ(HSW_AUD_CFG(pipe));
+ tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
@@ -345,9 +344,9 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
tmp |= AUD_CONFIG_N_PROG_ENABLE;
}
- I915_WRITE(HSW_AUD_CFG(pipe), tmp);
+ I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
- tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
+ tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
tmp &= ~AUD_CONFIG_M_MASK;
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
@@ -358,7 +357,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
tmp |= AUD_M_CTS_M_PROG_ENABLE;
}
- I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
+ I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
}
static void
@@ -367,15 +366,14 @@ hsw_hdmi_audio_config_update(struct intel_encoder
*encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct i915_audio_component *acomp = dev_priv->audio_component;
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2) URL : https://patchwork.freedesktop.org/series/59180/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12909 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59180/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12909 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#108602] / [fdo#108744]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] ([fdo#103841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: [DMESG-FAIL][7] ([fdo#110235]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html - fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#110235]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (53 -> 46) -- Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes - * Linux: CI_DRM_6017 -> Patchwork_12909 CI_DRM_6017: 69c3a37af9430650d1fc2ad4d0786898694d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12909: 2c852563912f45b23742afe4674abc1315116070 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2c852563912f drm/i915: Simplify some icl pll calculations a9bdced0ca89 drm/i915: Use mul_u32_u32() more == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12909/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h
On Tue, 2019-04-30 at 12:02 +0300, Jani Nikula wrote:
> On Mon, 29 Apr 2019, Stuart Summers wrote:
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 47
> >
> > drivers/gpu/drm/i915/intel_device_info.h | 47
> >
> > 2 files changed, 47 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index f5ff6b7a756a..5127b4ff92bf 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct
> > sseu_dev_info *sseu)
> > return value;
> > }
> >
> > +static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > +{
> > + unsigned int i, total = 0;
> > +
> > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > + total += hweight8(sseu->subslice_mask[i]);
> > +
> > + return total;
> > +}
> > +
> > static inline unsigned int
> > sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8
> > slice)
> > {
> > return hweight8(sseu->subslice_mask[slice]);
> > }
> >
> > +static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> > + int slice, int subslice)
> > +{
> > + int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > + BITS_PER_BYTE);
> > + int slice_stride = sseu->max_subslices * subslice_stride;
> > +
> > + return slice * slice_stride + subslice * subslice_stride;
> > +}
> > +
> > +static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> > + int slice, int subslice)
> > +{
> > + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > + u16 eu_mask = 0;
> > +
> > + for (i = 0;
> > +i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > + eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> > + (i * BITS_PER_BYTE);
> > + }
> > +
> > + return eu_mask;
> > +}
> > +
> > +static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> > + int slice, int subslice, u16 eu_mask)
> > +{
> > + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > +
> > + for (i = 0;
> > +i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {an't be
> > + sseu->eu_mask[offset + i] =
> > + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> > + }
> > +}
> > +
>
> I'd appreciate follow-up to rename these functions
> intel_sseu_*. Functions in intel_foo.[ch] should be named
> intel_foo_*().
Makes sense.
>
> Also, I'm starting to wonder the benefits of the plethora of inline
> functions we use. Should we move them to the .c file? It can't be a
> perf
> thing can it?
These are mostly called at driver load time, so no, shouldn't be a
performance issue. I don't have a preference either way, so no problem
moving these as suggested.
Thanks,
Stuart
>
> BR,
> Jani.
>
> > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> > const struct intel_sseu *req_sseu);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 5a2e17d6146b..6412a9c72898 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -218,53 +218,6 @@ struct intel_driver_caps {
> > bool has_logical_contexts:1;
> > };
> >
> > -static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > -{
> > - unsigned int i, total = 0;
> > -
> > - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > - total += hweight8(sseu->subslice_mask[i]);
> > -
> > - return total;
> > -}
> > -
> > -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> > - int slice, int subslice)
> > -{
> > - int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > - BITS_PER_BYTE);
> > - int slice_stride = sseu->max_subslices * subslice_stride;
> > -
> > - return slice * slice_stride + subslice * subslice_stride;
> > -}
> > -
> > -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> > - int slice, int subslice)
> > -{
> > - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > - u16 eu_mask = 0;
> > -
> > - for (i = 0;
> > -i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > - eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> > - (i * BITS_PER_BYTE);
> > - }
> > -
> > - return eu_mask;
> > -}
> > -
> > -static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> > - int slice, int subslice, u16 eu_mask)
> > -{
> > - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > -
> > - for (i = 0;
> >
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Expand subslice mask
On Tue, 2019-04-30 at 12:03 +0300, Jani Nikula wrote:
> On Mon, 29 Apr 2019, Stuart Summers wrote:
> > Currently, the subslice_mask runtime parameter is stored as an
> > array of subslices per slice. Expand the subslice mask array to
> > better match what is presented to userspace through the
> > I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
> > then calculated:
> > slice * subslice stride + subslice index / 8
> >
> > v2: fix spacing in set_sseu_info args
> > use set_sseu_info to initialize sseu data when building
> > device status in debugfs
> > rename variables in intel_engine_types.h to avoid checkpatch
> > warnings
> > v3: update headers in intel_sseu.h
> >
> > Cc: Daniele Ceraolo Spurio
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +-
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++--
> > drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 45 +-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> > drivers/gpu/drm/i915/i915_debugfs.c | 43 +++---
> > drivers/gpu/drm/i915/i915_drv.c | 6 +-
> > drivers/gpu/drm/i915/i915_gpu_error.c| 5 +-
> > drivers/gpu/drm/i915/i915_query.c| 10 +-
> > drivers/gpu/drm/i915/intel_device_info.c | 139 +++--
> > --
> > 10 files changed, 183 insertions(+), 108 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index f7308479d511..8922358ee6c6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -908,7 +908,7 @@ u32 intel_calculate_mcr_s_ss_select(struct
> > drm_i915_private *dev_priv)
> > const struct sseu_dev_info *sseu = _INFO(dev_priv)-
> > >sseu;
> > u32 mcr_s_ss_select;
> > u32 slice = fls(sseu->slice_mask);
> > - u32 subslice = fls(sseu->subslice_mask[slice]);
> > + u32 subslice = fls(sseu->subslice_mask[slice * sseu-
> > >ss_stride]);
> >
> > if (IS_GEN(dev_priv, 10))
> > mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> > @@ -984,6 +984,7 @@ void intel_engine_get_instdone(struct
> > intel_engine_cs *engine,
> >struct intel_instdone *instdone)
> > {
> > struct drm_i915_private *dev_priv = engine->i915;
> > + struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
>
> const?
>
> > struct intel_uncore *uncore = engine->uncore;
> > u32 mmio_base = engine->mmio_base;
> > int slice;
> > @@ -1001,7 +1002,8 @@ void intel_engine_get_instdone(struct
> > intel_engine_cs *engine,
> >
> > instdone->slice_common =
> > intel_uncore_read(uncore, GEN7_SC_INSTDONE);
> > - for_each_instdone_slice_subslice(dev_priv, slice,
> > subslice) {
> > + for_each_instdone_slice_subslice(dev_priv, sseu, slice,
> > +subslice) {
> > instdone->sampler[slice][subslice] =
> > read_subslice_reg(dev_priv, slice,
> > subslice,
> > GEN7_SAMPLER_INSTDONE
> > );
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index d972c339309c..fa70528963a4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const
> > struct intel_engine_cs *engine)
> > return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> > }
> >
> > -#define instdone_slice_mask(dev_priv__) \
> > - (IS_GEN(dev_priv__, 7) ? \
> > -1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
> > -
> > -#define instdone_subslice_mask(dev_priv__) \
> > - (IS_GEN(dev_priv__, 7) ? \
> > -1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
> > -
> > -#define for_each_instdone_slice_subslice(dev_priv__, slice__,
> > subslice__) \
> > - for ((slice__) = 0, (subslice__) = 0; \
> > -(slice__) < I915_MAX_SLICES; \
> > -(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
> > (subslice__) + 1 : 0, \
> > - (slice__) += ((subslice__) == 0)) \
> > - for_each_if((BIT(slice__) &
> > instdone_slice_mask(dev_priv__)) && \
> > - (BIT(subslice__) &
> > instdone_subslice_mask(dev_priv__)))
> > +#define instdone_has_slice(dev_priv___, sseu___, slice___) \
> > + ((IS_GEN(dev_priv___, 7) ? \
> > + 1 : (sseu___)->slice_mask) & \
> > + BIT(slice___)) \
> > +
> > +#define instdone_has_subslice(dev_priv__, sseu__, slice__,
> > subslice__) \
> > + ((IS_GEN(dev_priv__, 7) ? \
> > + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
> > + subslice__ / BITS_PER_BYTE]) & \
> > +BIT(subslice__ % BITS_PER_BYTE)) \
> > +
> >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2) URL : https://patchwork.freedesktop.org/series/59180/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Use mul_u32_u32() more -O:drivers/gpu/drm/i915/intel_display.c:7049:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:7049:26: warning: expression using sizeof(void) Commit: drm/i915: Simplify some icl pll calculations Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf: add struct dma_buf_attach_info v2
== Series Details == Series: dma-buf: add struct dma_buf_attach_info v2 URL : https://patchwork.freedesktop.org/series/60107/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12908 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60107/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12908 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([fdo#103841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Possible fixes * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [DMESG-FAIL][5] ([fdo#110235]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (53 -> 45) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-byt-clapper Build changes - * Linux: CI_DRM_6017 -> Patchwork_12908 CI_DRM_6017: 69c3a37af9430650d1fc2ad4d0786898694d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12908: e090409de568c7a2d9aef8d96902b3c38a9a1e6c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e090409de568 dma-buf: add struct dma_buf_attach_info v2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12908/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-buf: add struct dma_buf_attach_info v2
== Series Details == Series: dma-buf: add struct dma_buf_attach_info v2 URL : https://patchwork.freedesktop.org/series/60107/ State : warning == Summary == $ dim checkpatch origin/drm-tip e090409de568 dma-buf: add struct dma_buf_attach_info v2 -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: Add a structure for the parameters of dma_buf_attach, this makes it much easier -:353: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Christian König ' total: 0 errors, 2 warnings, 0 checks, 260 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Wait for the struct_mutex on idling
== Series Details == Series: series starting with [1/2] drm/i915: Wait for the struct_mutex on idling URL : https://patchwork.freedesktop.org/series/60098/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12907 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12907 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12907, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/60098/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12907: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - fi-kbl-r: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-r/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12907/fi-kbl-r/igt@i915_selftest@live_execlists.html Known issues Here are the changes found in Patchwork_12907 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_workarounds: - fi-snb-2600:[PASS][3] -> [INCOMPLETE][4] ([fdo#105411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-snb-2600/igt@i915_selftest@live_workarounds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12907/fi-snb-2600/igt@i915_selftest@live_workarounds.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] ([fdo#103841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12907/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: [DMESG-FAIL][7] ([fdo#110235]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12907/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html - fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#110235]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12907/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (53 -> 44) -- Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_6017 -> Patchwork_12907 CI_DRM_6017: 69c3a37af9430650d1fc2ad4d0786898694d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12907: c144d3af59602fcb4ddb218a788c961e47317432 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c144d3af5960 drm/i915: Cancel retire_worker on parking f2b3d409c989 drm/i915: Wait for the struct_mutex on idling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12907/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev8)
== Series Details == Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev8) URL : https://patchwork.freedesktop.org/series/58912/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12900_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12900_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12900_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12900_full: ### IGT changes ### Possible regressions * igt@gem_caching@read-writes: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl9/igt@gem_cach...@read-writes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-skl9/igt@gem_cach...@read-writes.html * igt@gem_mmap_gtt@forked-big-copy-odd: - shard-skl: NOTRUN -> [INCOMPLETE][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-skl2/igt@gem_mmap_...@forked-big-copy-odd.html Warnings * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size: - shard-skl: [SKIP][4] ([fdo#109271]) -> [INCOMPLETE][5] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl6/igt@kms_cursor_leg...@cursorb-vs-flipa-varying-size.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-skl8/igt@kms_cursor_leg...@cursorb-vs-flipa-varying-size.html Known issues Here are the changes found in Patchwork_12900_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_cpu_reloc@forked: - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb4/igt@gem_cpu_re...@forked.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-iclb3/igt@gem_cpu_re...@forked.html * igt@i915_pm_rpm@pm-tiling: - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#107807]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl10/igt@i915_pm_...@pm-tiling.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-skl9/igt@i915_pm_...@pm-tiling.html * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-snb: [PASS][10] -> [SKIP][11] ([fdo#109271] / [fdo#109278]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-snb1/igt@kms_b...@extended-pageflip-modeset-hang-oldfb-render-b.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-snb6/igt@kms_b...@extended-pageflip-modeset-hang-oldfb-render-b.html * igt@kms_cursor_crc@cursor-64x21-offscreen: - shard-skl: [PASS][12] -> [FAIL][13] ([fdo#103232]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl2/igt@kms_cursor_...@cursor-64x21-offscreen.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-skl3/igt@kms_cursor_...@cursor-64x21-offscreen.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-glk: [PASS][14] -> [INCOMPLETE][15] ([fdo#103359] / [k.org#198133]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk5/igt@kms_f...@flip-vs-suspend-interruptible.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-glk7/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([fdo#108566]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-apl8/igt@kms_f...@flip-vs-suspend-interruptible.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-apl8/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-snb: [PASS][18] -> [INCOMPLETE][19] ([fdo#105411]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-snb5/igt@kms_f...@flip-vs-suspend-interruptible.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-snb1/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@nonexisting-fb-interruptible: - shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([fdo#107713]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb3/igt@kms_f...@nonexisting-fb-interruptible.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12900/shard-iclb4/igt@kms_f...@nonexisting-fb-interruptible.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][22] -> [FAIL][23]
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used
On 4/30/2019 4:09 PM, Ville Syrjälä wrote:
On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote:
On 4/26/2019 8:07 PM, Ville Syrjälä wrote:
On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
On 4/13/2019 12:00 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The pipe has a special HDR mode with higher precision when only
HDR planes are active. Let's use it.
Curiously this fixes the kms_color gamma/degamma tests when
using a HDR plane, which is always the case unless one hacks
the test to use an SDR plane. If one does hack the test to use
an SDR plane it does pass already.
I have no actual explanation how the output after the gamma
LUT can be different between the two modes. The way the tests
are written should mean that the output should be identical
between the solid color vs. the gradient. But clearly that
somehow doesn't hold true for the HDR planes in non-HDR pipe
mode. Anyways, as long as we stick to one type of plane the
test should produce sensible results now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 7 +++
drivers/gpu/drm/i915/intel_sprite.h | 12
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ad2f0a03f28..90d60ecd3317 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5767,6 +5767,7 @@ enum {
#define _PIPE_MISC_B0x71030
#define PIPEMISC_YUV420_ENABLE(1 << 27)
#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
+#define PIPEMISC_HDR_MODE(1 << 23) /* icl+ */
#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
#define PIPEMISC_DITHER_BPC_MASK (7 << 5)
#define PIPEMISC_DITHER_8_BPC (0 << 5)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 490bd49ff42a..d0dbdbd5db3f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4055,6 +4055,9 @@ static void intel_update_pipe_config(const struct
intel_crtc_state *old_crtc_sta
ironlake_pfit_disable(old_crtc_state);
}
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
}
@@ -8869,6 +8872,10 @@ static void bdw_set_pipemisc(const struct
intel_crtc_state *crtc_state)
val |= PIPEMISC_YUV420_ENABLE |
PIPEMISC_YUV420_MODE_FULL_BLEND;
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ (crtc_state->active_planes & ~icl_hdr_plane_mask()) == 0)
+ val |= PIPEMISC_HDR_MODE;
+
Shouldn't we check if the content being played on plane is HDR before
enabling this bit (even though I am not sure if there is any harm in
doing that)? Or maybe check the connector->output_hdr_metadata ? Most of
the times we would be sending SDR buffers on this plane. What happens
exactly when we set this bit ? The bspec says:
"This field enables the HDR mode, allowing for higher precision output
from the HDR supporting planes and bypassing the SDR planes in blending. "
I think the bit is just misnamed (like most things with "HDR" in their
name). It's just a "gimme moar precision" bit.
Lets make this a bit more clear, may be rename the bit to
PIPEMISC_HDR_PRECISION_MODE instead?
Then it won't match the spec.
Well we are keeping HDR_MODE aren't we ? may be
PIPEMISC_HDR_MODE_PRECISION if that makes us closer to spec ?
- Shashank
With that change, this patch is
Reviewed-by: Shashank Sharma
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2)
== Series Details == Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2) URL : https://patchwork.freedesktop.org/series/60072/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12906 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12906 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12906, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/60072/revisions/2/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12906: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-6600u/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12906/fi-skl-6600u/igt@i915_selftest@live_execlists.html Known issues Here are the changes found in Patchwork_12906 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([fdo#103841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12906/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-apl-guc: [PASS][5] -> [DMESG-WARN][6] ([fdo#110512]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-apl-guc/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12906/fi-apl-guc/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-apl-guc: [DMESG-WARN][7] ([fdo#110512]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-apl-guc/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12906/fi-apl-guc/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: [DMESG-FAIL][9] ([fdo#110235]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12906/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html - fi-skl-gvtdvm: [DMESG-FAIL][11] ([fdo#110235]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6017/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12906/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [fdo#110512]: https://bugs.freedesktop.org/show_bug.cgi?id=110512 Participating hosts (53 -> 42) -- Missing(11): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-ivb-3770 fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_6017 -> Patchwork_12906 CI_DRM_6017: 69c3a37af9430650d1fc2ad4d0786898694d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12906: a440a6ecfb86e62bbde7077ed784163da920faf1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a440a6ecfb86 drm/i915/execlists: Don't apply priority boost for resets 7b1444ed17a5 drm/i915: Disable semaphore busywaits on saturated systems 6754404a7ba7 drm/i915: Delay semaphore submission until the start of the signaler bdd5fb2484ed drm/i915: Only reschedule the submission tasklet if preemption is possible cf066d2068a7 drm/i915: Wait for the struct_mutex on idling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12906/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Cancel retire_worker on parking
On 30/04/2019 10:44, Chris Wilson wrote:
Replace the racy continuation check within retire_work with a definite
kill-switch on idling. The race was being exposed by gem_concurrent_blit
where the retire_worker would be terminated too early leaving us
spinning in debugfs/i915_drop_caches with nothing flushing the
retirement queue.
Although that the igt is trying to idle from one child while submitting
from another may be a contributing factor as to why it runs so slowly...
Testcase: igt/gem_concurrent_blit
Fixes: 79ffac8599c4 ("drm/i915: Invert the GEM wakeref hierarchy")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_pm.c| 27 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 3 +--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 3b6e8d5be8e1..88be810758ae 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -46,15 +46,23 @@ static void idle_work_handler(struct work_struct *work)
{
struct drm_i915_private *i915 =
container_of(work, typeof(*i915), gem.idle_work.work);
+ bool restart = true;
+ cancel_delayed_work_sync(>gem.retire_work);
mutex_lock(>drm.struct_mutex);
Wouldn't it be better to cancel_delayed_work and then
i915_retire_requests under the lock?
With cancel_delayed_work_sync outside struct_mutex it sounds it could
miss a retire pass.
intel_wakeref_lock(>gt.wakeref);
- if (!intel_wakeref_active(>gt.wakeref))
+ if (!intel_wakeref_active(>gt.wakeref)) {
i915_gem_park(i915);
+ restart = false;
+ }
intel_wakeref_unlock(>gt.wakeref);
mutex_unlock(>drm.struct_mutex);
+ if (restart)
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
}
static void retire_work_handler(struct work_struct *work)
@@ -68,10 +76,9 @@ static void retire_work_handler(struct work_struct *work)
mutex_unlock(>drm.struct_mutex);
}
- if (intel_wakeref_active(>gt.wakeref))
- queue_delayed_work(i915->wq,
- >gem.retire_work,
- round_jiffies_up_relative(HZ));
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
So retire runs until idle stops it - that sounds okay.
}
static int pm_notifier(struct notifier_block *nb,
@@ -159,15 +166,9 @@ void i915_gem_suspend(struct drm_i915_private *i915)
* reset the GPU back to its idle, low power state.
*/
GEM_BUG_ON(i915->gt.awake);
- cancel_delayed_work_sync(>gpu_error.hangcheck_work);
-
- drain_delayed_work(>gem.retire_work);
+ flush_delayed_work(>gem.idle_work);
- /*
-* As the idle_work is rearming if it detects a race, play safe and
-* repeat the flush until it is definitely idle.
-*/
- drain_delayed_work(>gem.idle_work);
+ cancel_delayed_work_sync(>gpu_error.hangcheck_work);
i915_gem_drain_freed_objects(i915);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index e4033d0576c4..ce54f8dc13cc 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -58,8 +58,7 @@ static void mock_device_release(struct drm_device *dev)
i915_gem_contexts_lost(i915);
mutex_unlock(>drm.struct_mutex);
- drain_delayed_work(>gem.retire_work);
- drain_delayed_work(>gem.idle_work);
+ flush_delayed_work(>gem.idle_work);
i915_gem_drain_workqueue(i915);
mutex_lock(>drm.struct_mutex);
I am now thinking debugfs does not have to do things indirectly via
flush and drain. How about it calls what it needs directly? Unless I am
missing something that could be done separate to this patch and would
also fix the drop_caches spinning problem.
Regards,
Tvrtko
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2)
== Series Details == Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2) URL : https://patchwork.freedesktop.org/series/60072/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Wait for the struct_mutex on idling Okay! Commit: drm/i915: Only reschedule the submission tasklet if preemption is possible -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) Commit: drm/i915: Delay semaphore submission until the start of the signaler Okay! Commit: drm/i915: Disable semaphore busywaits on saturated systems +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/execlists: Don't apply priority boost for resets Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings
== Series Details == Series: series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings URL : https://patchwork.freedesktop.org/series/60094/ State : failure == Summary == Applying: drm/i915: Fix the pipe state timing mismatch warnings Applying: drm/i915: Fix pipe config mismatch for bpp, output format error: sha1 information is lacking or useless (drivers/gpu/drm/i915/icl_dsi.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915: Fix pipe config mismatch for bpp, output format When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, April 30, 2019 6:16 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp,
> output format
>
> On Tue, 30 Apr 2019, "Kulkarni, Vandita" wrote:
> >> -Original Message-
> >> From: Nikula, Jani
> >> Sent: Tuesday, April 30, 2019 3:03 PM
> >> To: Kulkarni, Vandita ; intel-
> >> g...@lists.freedesktop.org
> >> Cc: Syrjala, Ville ; Shankar, Uma
> >> ; Kulkarni, Vandita
> >>
> >> Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp,
> >> output format
> >>
> >> On Tue, 30 Apr 2019, Vandita Kulkarni wrote:
> >> > Read back the pixel fomrat register and get the bpp.
> >> >
> >> > v2: Read the PIPE_MISC register (Jani).
> >> >
> >> > Signed-off-by: Vandita Kulkarni
> >> > ---
> >> > drivers/gpu/drm/i915/icl_dsi.c | 3 +++
> >> > drivers/gpu/drm/i915/intel_dsi.h | 1 +
> >> > drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
> >> > 3 files changed, 5 insertions(+), 1 deletion(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> >> > b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644
> >> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> >> > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct
> >> > intel_encoder *encoder, {
> >> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> >> > +struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> >> >
> >> > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> >> > pipe_config->port_clock =
> >> > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct
> >> intel_encoder *encoder,
> >> > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> >> > gen11_dsi_get_timings(encoder, pipe_config);
> >> > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> >> > +pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
> >> > }
> >> >
> >> > static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> >> > @@
> >> > -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct
> >> intel_encoder *encoder,
> >> > struct drm_display_mode *adjusted_mode =
> >> >
> >> > _config->base.adjusted_mode;
> >> >
> >> > +pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> >> > intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> >> > intel_pch_panel_fitting(crtc, pipe_config,
> >> > conn_state->scaling_mode);
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_dsi.h
> >> > b/drivers/gpu/drm/i915/intel_dsi.h
> >> > index 705a609..cb9e3b9 100644
> >> > --- a/drivers/gpu/drm/i915/intel_dsi.h
> >> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
> >> > @@ -166,6 +166,7 @@ enum drm_mode_status
> >> > intel_dsi_mode_valid(struct drm_connector *connector, struct
> >> > intel_dsi_host *intel_dsi_host_init(struct
> >> intel_dsi *intel_dsi,
> >> > const struct
> >> > mipi_dsi_host_ops
> >> *funcs,
> >> > enum port port);
> >> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
> >>
> >> Until now this was internal to vlv_dsi.c and it was fine. Now, I
> >> think I'd move this to intel_display.c alongside haswell_set_pipemisc.
> > Ok, so I ll move thjs to intel_display.c and call it from
> > haswell_get_pipe_config for is_dsi and gen >= 9
>
> I'd actually prefer to call it from dsi encoder code instead.
Ok. Will do that.
Thanks,
Vandita
>
> BR,
> Jani.
>
> > Thanks,
> > Vandita
> >>
> >> Ville already has patches to rename haswell_set_pipemisc to
> bdw_set_pipemisc.
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> >
> >> > /* vlv_dsi_pll.c */
> >> > int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git
> >> > a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> >> > index b4c6583..790ada8 100644
> >> > --- a/drivers/gpu/drm/i915/vlv_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> >> > @@ -260,7 +260,7 @@ static void band_gap_reset(struct
> >> > drm_i915_private
> >> *dev_priv)
> >> > vlv_flisdsi_put(dev_priv);
> >> > }
> >> >
> >> > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> >> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> >> > {
> >> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > u32 tmp;
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
___
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[Intel-gfx] [PATCH v4] drm/i915: Corrupt DSI picture fix for GeminiLake
Currently due to regression CI machine
displays show corrupt picture.
Problem is when CDCLK is as low as 79200, picture gets
unstable, while DSI and DE pll values were
confirmed to be correct.
Limiting to 158400 as agreed with Ville.
We could not come up with any better solution
yet, as PLL divider values both for MIPI(DSI PLL) and
CDCLK(DE PLL) are correct, however seems that due to some
boundary conditions, when clocking is too low we get
wrong timings for DSI display.
Similar workaround exists for VLV though, so just
took similar condition into use. At least that way
GLK platform will start to be usable again, with
current drm-tip.
v2: Fixed commit subject as suggested.
v3: Added generic bugs(crc failures, screen not init
for GLK DSI which might be affected).
v4: Added references tag for bugs affected.
Signed-off-by: Stanislav Lisovskiy
Acked-by: Ville Syrjälä
References: https://bugs.freedesktop.org/show_bug.cgi?id=109267
References: https://bugs.freedesktop.org/show_bug.cgi?id=103184
---
drivers/gpu/drm/i915/intel_cdclk.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index ae40a8679314..2b23f8500362 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const struct
intel_crtc_state *crtc_state)
IS_VALLEYVIEW(dev_priv))
min_cdclk = max(32, min_cdclk);
+ /*
+* On Geminilake once the CDCLK gets as low as 79200
+* picture gets unstable, despite that values are
+* correct for DSI PLL and DE PLL.
+*/
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+ IS_GEMINILAKE(dev_priv))
+ min_cdclk = max(158400, min_cdclk);
+
if (min_cdclk > dev_priv->max_cdclk_freq) {
DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
min_cdclk, dev_priv->max_cdclk_freq);
--
2.17.1
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Factor out combo PHY lane power setup helper
On Tue, Apr 30, 2019 at 03:44:00PM +0300, Jani Nikula wrote:
> On Thu, 25 Apr 2019, Imre Deak wrote:
> > Factor out the combo PHY lane power configuration code to a separate
> > helper; it will be also needed by the next patch adding the same
> > configuration for DDI ports.
> >
> > Add support for DDI ports and lane reversal as preparation for the next
> > patch.
> >
> > The PWR_DOWN_LN_1 value is unspecified in the BSpec register description
> > so remove it.
> >
> > v2:
> > - Fix up the wrong assumption that the encodings are the same for DDI
> > and DSI ports. (Jani)
> >
>
> Both patches look good to me, but I'm afraid patch 1 conflicts with the
> header refactoring I pushed earlier, as well as the function name
> changes in [1]. I think I'd like the function here to be renamed
> accordingly.
>
> Other than that, for both,
>
> Reviewed-by: Jani Nikula
Thanks. Yes, that naming scheme makes sense, will do the rename before
pushing the patches.
>
> [1]
> http://patchwork.freedesktop.org/patch/msgid/20190430124128.23606-1-jani.nik...@intel.com
>
>
> > Cc: Jani Nikula
> > Cc: Madhav Chauhan
> > Cc: Ville Syrjala
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/i915_drv.h| 3 ++
> > drivers/gpu/drm/i915/i915_reg.h| 1 -
> > drivers/gpu/drm/i915/icl_dsi.c | 26 ++---
> > drivers/gpu/drm/i915/intel_combo_phy.c | 52
> > ++
> > 4 files changed, 58 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index dc74d33c20aa..87f24d92e355 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3515,6 +3515,9 @@ void icl_combo_phys_init(struct drm_i915_private
> > *dev_priv);
> > void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> > void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
> > void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> > +void icl_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
> > + enum port port, bool is_dsi,
> > + int lane_count, bool lane_reversal);
> >
> > int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> > int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index b74824f0b5b1..e332b9f69a4a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1813,7 +1813,6 @@ enum i915_power_well_id {
> > #define PWR_DOWN_LN_3 (0x8 << 4)
> > #define PWR_DOWN_LN_2_1_0 (0x7 << 4)
> > #define PWR_DOWN_LN_1_0 (0x3 << 4)
> > -#define PWR_DOWN_LN_1 (0x2 << 4)
> > #define PWR_DOWN_LN_3_1 (0xa << 4)
> > #define PWR_DOWN_LN_3_1_0 (0xb << 4)
> > #define PWR_DOWN_LN_MASK (0xf << 4)
> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> > index 9d962ea1e635..f2113d3798b0 100644
> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > @@ -363,30 +363,10 @@ static void gen11_dsi_power_up_lanes(struct
> > intel_encoder *encoder)
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> > enum port port;
> > - u32 tmp;
> > - u32 lane_mask;
> >
> > - switch (intel_dsi->lane_count) {
> > - case 1:
> > - lane_mask = PWR_DOWN_LN_3_1_0;
> > - break;
> > - case 2:
> > - lane_mask = PWR_DOWN_LN_3_1;
> > - break;
> > - case 3:
> > - lane_mask = PWR_DOWN_LN_3;
> > - break;
> > - case 4:
> > - default:
> > - lane_mask = PWR_UP_ALL_LANES;
> > - break;
> > - }
> > -
> > - for_each_dsi_port(port, intel_dsi->ports) {
> > - tmp = I915_READ(ICL_PORT_CL_DW10(port));
> > - tmp &= ~PWR_DOWN_LN_MASK;
> > - I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
> > - }
> > + for_each_dsi_port(port, intel_dsi->ports)
> > + icl_combo_phy_power_up_lanes(dev_priv, port, true,
> > +intel_dsi->lane_count, false);
> > }
> >
> > static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> > *encoder)
> > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> > b/drivers/gpu/drm/i915/intel_combo_phy.c
> > index 2bf4359d7e41..5478808886f1 100644
> > --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> > @@ -203,6 +203,58 @@ static bool icl_combo_phy_verify_state(struct
> > drm_i915_private *dev_priv,
> > return ret;
> > }
> >
> > +void icl_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
> > + enum port port, bool is_dsi,
> > +
Re: [Intel-gfx] [PATCH v3] drm/i915: Corrupt DSI picture fix for GeminiLake
On Tue, 30 Apr 2019, Stanislav Lisovskiy wrote:
> Currently due to regression CI machine
> displays show corrupt picture.
> Problem is when CDCLK is as low as 79200, picture gets
> unstable, while DSI and DE pll values were
> confirmed to be correct.
> Limiting to 158400 as agreed with Ville.
>
> We could not come up with any better solution
> yet, as PLL divider values both for MIPI(DSI PLL) and
> CDCLK(DE PLL) are correct, however seems that due to some
> boundary conditions, when clocking is too low we get
> wrong timings for DSI display.
> Similar workaround exists for VLV though, so just
> took similar condition into use. At least that way
> GLK platform will start to be usable again, with
> current drm-tip.
>
> v2: Fixed commit subject as suggested.
>
> v3: Added generic bugs(crc failures, screen not init
> for GLK DSI which might be affected).
>
> Signed-off-by: Stanislav Lisovskiy
> Acked-by: Ville Syrjälä
> Generic bugs affected:
> https://bugs.freedesktop.org/show_bug.cgi?id=109267
> https://bugs.freedesktop.org/show_bug.cgi?id=103184
If this fixes them,
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109267
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103184
If this is related to them,
References: https://bugs.freedesktop.org/show_bug.cgi?id=109267
References: https://bugs.freedesktop.org/show_bug.cgi?id=103184
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index ae40a8679314..2b23f8500362 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> IS_VALLEYVIEW(dev_priv))
> min_cdclk = max(32, min_cdclk);
>
> + /*
> + * On Geminilake once the CDCLK gets as low as 79200
> + * picture gets unstable, despite that values are
> + * correct for DSI PLL and DE PLL.
> + */
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> + IS_GEMINILAKE(dev_priv))
> + min_cdclk = max(158400, min_cdclk);
> +
> if (min_cdclk > dev_priv->max_cdclk_freq) {
> DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
> min_cdclk, dev_priv->max_cdclk_freq);
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format
On Tue, 30 Apr 2019, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Tuesday, April 30, 2019 3:03 PM
>> To: Kulkarni, Vandita ; intel-
>> g...@lists.freedesktop.org
>> Cc: Syrjala, Ville ; Shankar, Uma
>> ; Kulkarni, Vandita
>> Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output
>> format
>>
>> On Tue, 30 Apr 2019, Vandita Kulkarni wrote:
>> > Read back the pixel fomrat register and get the bpp.
>> >
>> > v2: Read the PIPE_MISC register (Jani).
>> >
>> > Signed-off-by: Vandita Kulkarni
>> > ---
>> > drivers/gpu/drm/i915/icl_dsi.c | 3 +++
>> > drivers/gpu/drm/i915/intel_dsi.h | 1 +
>> > drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
>> > 3 files changed, 5 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> > b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644
>> > --- a/drivers/gpu/drm/i915/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct
>> > intel_encoder *encoder, {
>> >struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> >struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>> > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
>> >
>> >/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
>> >pipe_config->port_clock =
>> > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct
>> intel_encoder *encoder,
>> >pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
>> >gen11_dsi_get_timings(encoder, pipe_config);
>> >pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>> > + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
>> > }
>> >
>> > static int gen11_dsi_compute_config(struct intel_encoder *encoder, @@
>> > -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,
>> >struct drm_display_mode *adjusted_mode =
>> >_config->base.adjusted_mode;
>> >
>> > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> >intel_fixed_panel_mode(fixed_mode, adjusted_mode);
>> >intel_pch_panel_fitting(crtc, pipe_config,
>> > conn_state->scaling_mode);
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>> > b/drivers/gpu/drm/i915/intel_dsi.h
>> > index 705a609..cb9e3b9 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.h
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> > @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct
>> > drm_connector *connector, struct intel_dsi_host
>> > *intel_dsi_host_init(struct
>> intel_dsi *intel_dsi,
>> > const struct mipi_dsi_host_ops
>> *funcs,
>> > enum port port);
>> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
>>
>> Until now this was internal to vlv_dsi.c and it was fine. Now, I think I'd
>> move this
>> to intel_display.c alongside haswell_set_pipemisc.
> Ok, so I ll move thjs to intel_display.c and call it from
> haswell_get_pipe_config for is_dsi and gen >= 9
I'd actually prefer to call it from dsi encoder code instead.
BR,
Jani.
> Thanks,
> Vandita
>>
>> Ville already has patches to rename haswell_set_pipemisc to bdw_set_pipemisc.
>>
>> BR,
>> Jani.
>>
>>
>> >
>> > /* vlv_dsi_pll.c */
>> > int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git
>> > a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
>> > index b4c6583..790ada8 100644
>> > --- a/drivers/gpu/drm/i915/vlv_dsi.c
>> > +++ b/drivers/gpu/drm/i915/vlv_dsi.c
>> > @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private
>> *dev_priv)
>> >vlv_flisdsi_put(dev_priv);
>> > }
>> >
>> > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>> > {
>> >struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >u32 tmp;
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Factor out combo PHY lane power setup helper
On Thu, 25 Apr 2019, Imre Deak wrote:
> Factor out the combo PHY lane power configuration code to a separate
> helper; it will be also needed by the next patch adding the same
> configuration for DDI ports.
>
> Add support for DDI ports and lane reversal as preparation for the next
> patch.
>
> The PWR_DOWN_LN_1 value is unspecified in the BSpec register description
> so remove it.
>
> v2:
> - Fix up the wrong assumption that the encodings are the same for DDI
> and DSI ports. (Jani)
>
Both patches look good to me, but I'm afraid patch 1 conflicts with the
header refactoring I pushed earlier, as well as the function name
changes in [1]. I think I'd like the function here to be renamed
accordingly.
Other than that, for both,
Reviewed-by: Jani Nikula
[1]
http://patchwork.freedesktop.org/patch/msgid/20190430124128.23606-1-jani.nik...@intel.com
> Cc: Jani Nikula
> Cc: Madhav Chauhan
> Cc: Ville Syrjala
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.h| 3 ++
> drivers/gpu/drm/i915/i915_reg.h| 1 -
> drivers/gpu/drm/i915/icl_dsi.c | 26 ++---
> drivers/gpu/drm/i915/intel_combo_phy.c | 52
> ++
> 4 files changed, 58 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dc74d33c20aa..87f24d92e355 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3515,6 +3515,9 @@ void icl_combo_phys_init(struct drm_i915_private
> *dev_priv);
> void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
> void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
> +void icl_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
> + enum port port, bool is_dsi,
> + int lane_count, bool lane_reversal);
>
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b74824f0b5b1..e332b9f69a4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1813,7 +1813,6 @@ enum i915_power_well_id {
> #define PWR_DOWN_LN_3 (0x8 << 4)
> #define PWR_DOWN_LN_2_1_0 (0x7 << 4)
> #define PWR_DOWN_LN_1_0 (0x3 << 4)
> -#define PWR_DOWN_LN_1 (0x2 << 4)
> #define PWR_DOWN_LN_3_1 (0xa << 4)
> #define PWR_DOWN_LN_3_1_0 (0xb << 4)
> #define PWR_DOWN_LN_MASK(0xf << 4)
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 9d962ea1e635..f2113d3798b0 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -363,30 +363,10 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> enum port port;
> - u32 tmp;
> - u32 lane_mask;
>
> - switch (intel_dsi->lane_count) {
> - case 1:
> - lane_mask = PWR_DOWN_LN_3_1_0;
> - break;
> - case 2:
> - lane_mask = PWR_DOWN_LN_3_1;
> - break;
> - case 3:
> - lane_mask = PWR_DOWN_LN_3;
> - break;
> - case 4:
> - default:
> - lane_mask = PWR_UP_ALL_LANES;
> - break;
> - }
> -
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_PORT_CL_DW10(port));
> - tmp &= ~PWR_DOWN_LN_MASK;
> - I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
> - }
> + for_each_dsi_port(port, intel_dsi->ports)
> + icl_combo_phy_power_up_lanes(dev_priv, port, true,
> + intel_dsi->lane_count, false);
> }
>
> static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> b/drivers/gpu/drm/i915/intel_combo_phy.c
> index 2bf4359d7e41..5478808886f1 100644
> --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> @@ -203,6 +203,58 @@ static bool icl_combo_phy_verify_state(struct
> drm_i915_private *dev_priv,
> return ret;
> }
>
> +void icl_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
> + enum port port, bool is_dsi,
> + int lane_count, bool lane_reversal)
> +{
> + u8 lane_mask;
> + u32 val;
> +
> + if (is_dsi) {
> + WARN_ON(lane_reversal);
> +
> + switch (lane_count) {
> + case 1:
> + lane_mask = PWR_DOWN_LN_3_1_0;
> + break;
> + case
Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, April 30, 2019 3:03 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville ; Shankar, Uma
> ; Kulkarni, Vandita
> Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output
> format
>
> On Tue, 30 Apr 2019, Vandita Kulkarni wrote:
> > Read back the pixel fomrat register and get the bpp.
> >
> > v2: Read the PIPE_MISC register (Jani).
> >
> > Signed-off-by: Vandita Kulkarni
> > ---
> > drivers/gpu/drm/i915/icl_dsi.c | 3 +++
> > drivers/gpu/drm/i915/intel_dsi.h | 1 +
> > drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
> > 3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644
> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct
> > intel_encoder *encoder, {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> >
> > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> > pipe_config->port_clock =
> > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct
> intel_encoder *encoder,
> > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> > gen11_dsi_get_timings(encoder, pipe_config);
> > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> > + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
> > }
> >
> > static int gen11_dsi_compute_config(struct intel_encoder *encoder, @@
> > -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
> > struct drm_display_mode *adjusted_mode =
> > _config->base.adjusted_mode;
> >
> > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> > intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> > intel_pch_panel_fitting(crtc, pipe_config,
> > conn_state->scaling_mode);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.h
> > b/drivers/gpu/drm/i915/intel_dsi.h
> > index 705a609..cb9e3b9 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.h
> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
> > @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct
> > drm_connector *connector, struct intel_dsi_host *intel_dsi_host_init(struct
> intel_dsi *intel_dsi,
> >const struct mipi_dsi_host_ops
> *funcs,
> >enum port port);
> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
>
> Until now this was internal to vlv_dsi.c and it was fine. Now, I think I'd
> move this
> to intel_display.c alongside haswell_set_pipemisc.
Ok, so I ll move thjs to intel_display.c and call it from
haswell_get_pipe_config for is_dsi and gen >= 9
Thanks,
Vandita
>
> Ville already has patches to rename haswell_set_pipemisc to bdw_set_pipemisc.
>
> BR,
> Jani.
>
>
> >
> > /* vlv_dsi_pll.c */
> > int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git
> > a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> > index b4c6583..790ada8 100644
> > --- a/drivers/gpu/drm/i915/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> > @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private
> *dev_priv)
> > vlv_flisdsi_put(dev_priv);
> > }
> >
> > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > u32 tmp;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH] drm/i915: add single combo phy init/unit functions
Work on the principle that files should prefer not to expose platform
specific functions.
v2: Rebase
Cc: Imre Deak
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_combo_phy.c | 24
drivers/gpu/drm/i915/intel_combo_phy.h | 6 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +-
3 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
b/drivers/gpu/drm/i915/intel_combo_phy.c
index 5c7eb6c..a8660d 100644
--- a/drivers/gpu/drm/i915/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/intel_combo_phy.c
@@ -148,7 +148,7 @@ static bool cnl_combo_phy_verify_state(struct
drm_i915_private *dev_priv)
return ret;
}
-void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
+static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
{
u32 val;
@@ -168,7 +168,7 @@ void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
I915_WRITE(CNL_PORT_CL1CM_DW5, val);
}
-void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
+static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
{
u32 val;
@@ -204,7 +204,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
return ret;
}
-void icl_combo_phys_init(struct drm_i915_private *dev_priv)
+static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
{
enum port port;
@@ -233,7 +233,7 @@ void icl_combo_phys_init(struct drm_i915_private *dev_priv)
}
}
-void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
+static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
{
enum port port;
@@ -254,3 +254,19 @@ void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
I915_WRITE(ICL_PORT_COMP_DW0(port), val);
}
}
+
+void intel_combo_phy_init(struct drm_i915_private *i915)
+{
+ if (INTEL_GEN(i915) >= 11)
+ icl_combo_phys_init(i915);
+ else if (IS_CANNONLAKE(i915))
+ cnl_combo_phys_init(i915);
+}
+
+void intel_combo_phy_uninit(struct drm_i915_private *i915)
+{
+ if (INTEL_GEN(i915) >= 11)
+ icl_combo_phys_uninit(i915);
+ else if (IS_CANNONLAKE(i915))
+ cnl_combo_phys_uninit(i915);
+}
diff --git a/drivers/gpu/drm/i915/intel_combo_phy.h
b/drivers/gpu/drm/i915/intel_combo_phy.h
index f7f1e5..3ecb1e 100644
--- a/drivers/gpu/drm/i915/intel_combo_phy.h
+++ b/drivers/gpu/drm/i915/intel_combo_phy.h
@@ -8,9 +8,7 @@
struct drm_i915_private;
-void icl_combo_phys_init(struct drm_i915_private *dev_priv);
-void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
-void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
-void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
+void intel_combo_phy_init(struct drm_i915_private *dev_priv);
+void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
#endif /* __INTEL_COMBO_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 30e7cb..be7119 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1140,7 +1140,7 @@ static void gen9_dc_off_power_well_enable(struct
drm_i915_private *dev_priv,
* PHY's HW context for port B is lost after DC transitions,
* so we need to restore it manually.
*/
- icl_combo_phys_init(dev_priv);
+ intel_combo_phy_init(dev_priv);
}
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
@@ -3779,7 +3779,7 @@ static void cnl_display_core_init(struct drm_i915_private
*dev_priv, bool resume
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
/* 2-3. */
- cnl_combo_phys_init(dev_priv);
+ intel_combo_phy_init(dev_priv);
/*
* 4. Enable Power Well 1 (PG1).
@@ -3828,7 +3828,7 @@ static void cnl_display_core_uninit(struct
drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
/* 5. */
- cnl_combo_phys_uninit(dev_priv);
+ intel_combo_phy_uninit(dev_priv);
}
void icl_display_core_init(struct drm_i915_private *dev_priv,
@@ -3843,7 +3843,7 @@ void icl_display_core_init(struct drm_i915_private
*dev_priv,
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
/* 2. Initialize all combo phys */
- icl_combo_phys_init(dev_priv);
+ intel_combo_phy_init(dev_priv);
/*
* 3. Enable Power Well 1 (PG1).
@@ -3893,7 +3893,7 @@ void icl_display_core_uninit(struct drm_i915_private
*dev_priv)
mutex_unlock(_domains->lock);
/* 5. */
- icl_combo_phys_uninit(dev_priv);
+ intel_combo_phy_uninit(dev_priv);
}
static void chv_phy_control_init(struct drm_i915_private *dev_priv)
--
2.20.1
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Wait for the struct_mutex on idling
On 30/04/2019 10:44, Chris Wilson wrote:
When the system is idling, contention for struct_mutex should be low and
so we will be more efficient to wait for a contended mutex than
reschedule.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_pm.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 3554d55dae35..3b6e8d5be8e1 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -47,13 +47,7 @@ static void idle_work_handler(struct work_struct *work)
struct drm_i915_private *i915 =
container_of(work, typeof(*i915), gem.idle_work.work);
- if (!mutex_trylock(>drm.struct_mutex)) {
- /* Currently busy, come back later */
- mod_delayed_work(i915->wq,
->gem.idle_work,
-msecs_to_jiffies(50));
- return;
- }
+ mutex_lock(>drm.struct_mutex);
intel_wakeref_lock(>gt.wakeref);
if (!intel_wakeref_active(>gt.wakeref))
I don't see any real downsides to this indeed.
Reviewed-by: Tvrtko Ursulin
Possible tweak could be to leave this as is, maybe just not go for the
reduced idle timer on re-schedule, but add a cancel_delayed_work on the
unparking side of things. That way any mutex activity without actual
device unparking would only slightly delay going idle, while idle_work
would retain it's minimal disturbance of the mutex.
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH 00/21] drm/i915: the great header refactoring, part two
On Tue, 30 Apr 2019, Chris Wilson wrote: > Quoting Jani Nikula (2019-04-29 13:29:18) >> Continue the header refactoring started in part one [1]. >> >> BR, >> Jani. >> >> [1] https://patchwork.freedesktop.org/series/59022/ >> >> >> Jani Nikula (21): >> drm/i915: ensure more headers remain self-contained >> drm/i915: make intel_bios.h self-contained >> drm/i915/dvo: rename dvo.h to intel_dvo_dev.h and make self-contained >> drm/i915: make intel_dpll_mgr.h self-contained >> drm/i915: move dsi init functions to intel_dsi.h >> drm/i915: extract intel_fifo_underrun.h from intel_drv.h >> drm/i915: extract intel_dp_link_training.h from intel_drv.h >> drm/i915: extract intel_dp_aux_backlight.h from intel_drv.h >> drm/i915: extract i915_irq.h from intel_drv.h and i915_drv.h >> drm/i915: extract intel_hotplug.h from intel_drv.h and i915_drv.h >> drm/i915: extract intel_bios.h functions from i915_drv.h >> drm/i915: extract intel_quirks.h from intel_drv.h >> drm/i915: extract intel_overlay.h from intel_drv.h and i915_drv.h >> drm/i915: extract intel_vdsc.h from intel_drv.h and i915_drv.h >> drm/i915: extract intel_dp_mst.h from intel_drv.h >> drm/i915: extract intel_dsi_dcs_backlight.h from intel_drv.h >> drm/i915: extract intel_atomic.h from intel_drv.h >> drm/i915: extract intel_runtime_pm.h from intel_drv.h >> drm/i915: move some leftovers to intel_pm.h from i915_drv.h >> drm/i915: extract intel_combo_phy.h from i915_drv.h >> drm/i915: add single combo phy init/unit functions > > I read them all and they look sane. I trust the HDRTEST infrastructure > to spot any typos, so > > Reviewed-by: Chris Wilson Thanks, pushed everything except the last one which conflicts. Will post a rebased version. I don't think any of these could cause the reported CI incompletes. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915: Corrupt DSI picture fix for GeminiLake
Currently due to regression CI machine
displays show corrupt picture.
Problem is when CDCLK is as low as 79200, picture gets
unstable, while DSI and DE pll values were
confirmed to be correct.
Limiting to 158400 as agreed with Ville.
We could not come up with any better solution
yet, as PLL divider values both for MIPI(DSI PLL) and
CDCLK(DE PLL) are correct, however seems that due to some
boundary conditions, when clocking is too low we get
wrong timings for DSI display.
Similar workaround exists for VLV though, so just
took similar condition into use. At least that way
GLK platform will start to be usable again, with
current drm-tip.
v2: Fixed commit subject as suggested.
v3: Added generic bugs(crc failures, screen not init
for GLK DSI which might be affected).
Signed-off-by: Stanislav Lisovskiy
Acked-by: Ville Syrjälä
Generic bugs affected:
https://bugs.freedesktop.org/show_bug.cgi?id=109267
https://bugs.freedesktop.org/show_bug.cgi?id=103184
---
drivers/gpu/drm/i915/intel_cdclk.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index ae40a8679314..2b23f8500362 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const struct
intel_crtc_state *crtc_state)
IS_VALLEYVIEW(dev_priv))
min_cdclk = max(32, min_cdclk);
+ /*
+* On Geminilake once the CDCLK gets as low as 79200
+* picture gets unstable, despite that values are
+* correct for DSI PLL and DE PLL.
+*/
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+ IS_GEMINILAKE(dev_priv))
+ min_cdclk = max(158400, min_cdclk);
+
if (min_cdclk > dev_priv->max_cdclk_freq) {
DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
min_cdclk, dev_priv->max_cdclk_freq);
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for i915: disable framebuffer compression on GeminiLake
== Series Details == Series: i915: disable framebuffer compression on GeminiLake URL : https://patchwork.freedesktop.org/series/60090/ State : success == Summary == CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12904 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60090/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12904 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: [PASS][1] -> [DMESG-WARN][2] ([fdo#108965]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-kbl-8809g/igt@amdgpu/amd_ba...@userptr.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/fi-kbl-8809g/igt@amdgpu/amd_ba...@userptr.html * igt@gem_exec_suspend@basic-s4-devices: - fi-skl-lmem:[PASS][3] -> [INCOMPLETE][4] ([fdo#104108] / [fdo#107773]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-skl-lmem/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/fi-skl-lmem/igt@gem_exec_susp...@basic-s4-devices.html Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-y: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-icl-y/igt@gem_ctx_cre...@basic-files.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/fi-icl-y/igt@gem_ctx_cre...@basic-files.html * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602] / [fdo#108744]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 Participating hosts (51 -> 46) -- Additional (2): fi-skl-guc fi-icl-u2 Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6014 -> Patchwork_12904 CI_DRM_6014: b5b621db8397c5c726f5493095682f14d295429d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12904: e0a51c14603fca6028fc72bf0e1808892a8916d8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e0a51c14603f i915: disable framebuffer compression on GeminiLake == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12904/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2)
== Series Details == Series: drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2) URL : https://patchwork.freedesktop.org/series/60062/ State : success == Summary == CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12903 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60062/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12903 that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [k.org#198133]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-glk-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/fi-glk-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-y: [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-icl-y/igt@gem_ctx_cre...@basic-files.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/fi-icl-y/igt@gem_ctx_cre...@basic-files.html * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [INCOMPLETE][5] ([fdo#108602] / [fdo#108744]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (51 -> 44) -- Additional (1): fi-skl-guc Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6014 -> Patchwork_12903 CI_DRM_6014: b5b621db8397c5c726f5493095682f14d295429d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12903: 101e3b1621dbafe381f7e127f931a0f534c82fb6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 101e3b1621db drm/i915/csr: alpha_support doesn't depend on csr or vice versa == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12903/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Wait for the struct_mutex on idling
== Series Details == Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling URL : https://patchwork.freedesktop.org/series/60072/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12899_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12899_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12899_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12899_full: ### IGT changes ### Possible regressions * igt@gem_caching@read-writes: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl9/igt@gem_cach...@read-writes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-skl2/igt@gem_cach...@read-writes.html * igt@perf_pmu@busy-accuracy-2-vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][3] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-skl6/igt@perf_...@busy-accuracy-2-vcs0.html Known issues Here are the changes found in Patchwork_12899_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@mock_requests: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([fdo#110550]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl1/igt@i915_selftest@mock_requests.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-skl3/igt@i915_selftest@mock_requests.html * igt@kms_cursor_crc@cursor-128x42-onscreen: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([fdo#108972]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl3/igt@kms_cursor_...@cursor-128x42-onscreen.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-skl10/igt@kms_cursor_...@cursor-128x42-onscreen.html * igt@kms_cursor_crc@cursor-64x21-offscreen: - shard-skl: [PASS][8] -> [FAIL][9] ([fdo#103232]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl2/igt@kms_cursor_...@cursor-64x21-offscreen.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-skl6/igt@kms_cursor_...@cursor-64x21-offscreen.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#103184] / [fdo#103232]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl8/igt@kms_draw_...@draw-method-xrgb2101010-mmap-wc-ytiled.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-skl6/igt@kms_draw_...@draw-method-xrgb2101010-mmap-wc-ytiled.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][12] -> [FAIL][13] ([fdo#105363]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk4/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@2x-flip-vs-suspend: - shard-hsw: [PASS][14] -> [INCOMPLETE][15] ([fdo#103540]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-hsw5/igt@kms_f...@2x-flip-vs-suspend.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-hsw5/igt@kms_f...@2x-flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#109507]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl1/igt@kms_f...@flip-vs-suspend-interruptible.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-skl5/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-snb: [PASS][18] -> [INCOMPLETE][19] ([fdo#105411]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-snb5/igt@kms_f...@flip-vs-suspend-interruptible.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-snb1/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12899/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html *
[Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2
Add a structure for the parameters of dma_buf_attach, this makes it much easier
to add new parameters later on.
v2: rebase cleanup and fix all new implementations as well
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 13 +++--
drivers/gpu/drm/armada/armada_gem.c | 6 +-
drivers/gpu/drm/drm_prime.c | 6 +-
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 6 +-
drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 6 +-
drivers/gpu/drm/tegra/gem.c | 6 +-
drivers/gpu/drm/udl/udl_dmabuf.c| 6 +-
.../common/videobuf2/videobuf2-dma-contig.c | 6 +-
.../media/common/videobuf2/videobuf2-dma-sg.c | 6 +-
drivers/misc/fastrpc.c | 6 +-
drivers/staging/media/tegra-vde/tegra-vde.c | 6 +-
drivers/xen/gntdev-dmabuf.c | 4
include/linux/dma-buf.h | 17 +++--
13 files changed, 76 insertions(+), 18 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 3ae6c0c2cc02..e295e76a8c57 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -535,8 +535,9 @@ EXPORT_SYMBOL_GPL(dma_buf_put);
/**
* dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
* calls attach() of dma_buf_ops to allow device-specific attach functionality
- * @dmabuf:[in]buffer to attach device to.
- * @dev: [in]device to be attached.
+ * @info: [in]holds all the attach related information provided
+ * by the importer. see dma_buf_attach_info
+ * for further details.
*
* Returns struct dma_buf_attachment pointer for this attachment. Attachments
* must be cleaned up by calling dma_buf_detach().
@@ -550,20 +551,20 @@ EXPORT_SYMBOL_GPL(dma_buf_put);
* accessible to @dev, and cannot be moved to a more suitable place. This is
* indicated with the error code -EBUSY.
*/
-struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
- struct device *dev)
+struct dma_buf_attachment *dma_buf_attach(const struct dma_buf_attach_info
*info)
{
+ struct dma_buf *dmabuf = info->dmabuf;
struct dma_buf_attachment *attach;
int ret;
- if (WARN_ON(!dmabuf || !dev))
+ if (WARN_ON(!dmabuf || !info->dev))
return ERR_PTR(-EINVAL);
attach = kzalloc(sizeof(*attach), GFP_KERNEL);
if (!attach)
return ERR_PTR(-ENOMEM);
- attach->dev = dev;
+ attach->dev = info->dev;
attach->dmabuf = dmabuf;
mutex_lock(>lock);
diff --git a/drivers/gpu/drm/armada/armada_gem.c
b/drivers/gpu/drm/armada/armada_gem.c
index 642d0e70d0f8..19c47821032f 100644
--- a/drivers/gpu/drm/armada/armada_gem.c
+++ b/drivers/gpu/drm/armada/armada_gem.c
@@ -501,6 +501,10 @@ armada_gem_prime_export(struct drm_device *dev, struct
drm_gem_object *obj,
struct drm_gem_object *
armada_gem_prime_import(struct drm_device *dev, struct dma_buf *buf)
{
+ struct dma_buf_attach_info attach_info = {
+ .dev = dev->dev,
+ .dmabuf = buf
+ };
struct dma_buf_attachment *attach;
struct armada_gem_object *dobj;
@@ -516,7 +520,7 @@ armada_gem_prime_import(struct drm_device *dev, struct
dma_buf *buf)
}
}
- attach = dma_buf_attach(buf, dev->dev);
+ attach = dma_buf_attach(_info);
if (IS_ERR(attach))
return ERR_CAST(attach);
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index dc079efb3b0f..1dd70fc095ee 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -710,6 +710,10 @@ struct drm_gem_object *drm_gem_prime_import_dev(struct
drm_device *dev,
struct dma_buf *dma_buf,
struct device *attach_dev)
{
+ struct dma_buf_attach_info attach_info = {
+ .dev = attach_dev,
+ .dmabuf = dma_buf
+ };
struct dma_buf_attachment *attach;
struct sg_table *sgt;
struct drm_gem_object *obj;
@@ -730,7 +734,7 @@ struct drm_gem_object *drm_gem_prime_import_dev(struct
drm_device *dev,
if (!dev->driver->gem_prime_import_sg_table)
return ERR_PTR(-EINVAL);
- attach = dma_buf_attach(dma_buf, attach_dev);
+ attach = dma_buf_attach(_info);
if (IS_ERR(attach))
return ERR_CAST(attach);
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 5a101a9462d8..978054157c64 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -277,6 +277,10 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_dmabuf_ops = {
struct drm_gem_object
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Corrupt DSI picture fix for GeminiLake
== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake URL : https://patchwork.freedesktop.org/series/60084/ State : success == Summary == CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12902 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60084/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12902 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#110235]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-y: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-icl-y/igt@gem_ctx_cre...@basic-files.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-icl-y/igt@gem_ctx_cre...@basic-files.html * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602] / [fdo#108744]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6014/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (51 -> 42) -- Additional (1): fi-skl-guc Missing(10): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6014 -> Patchwork_12902 CI_DRM_6014: b5b621db8397c5c726f5493095682f14d295429d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12902: 15f80f2efc96d825897faef3fb6ff532f8617aba @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 15f80f2efc96 drm/i915: Corrupt DSI picture fix for GeminiLake == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12902/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used
On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote:
>
> On 4/26/2019 8:07 PM, Ville Syrjälä wrote:
> > On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
> >> On 4/13/2019 12:00 AM, Ville Syrjala wrote:
> >>> From: Ville Syrjälä
> >>>
> >>> The pipe has a special HDR mode with higher precision when only
> >>> HDR planes are active. Let's use it.
> >>>
> >>> Curiously this fixes the kms_color gamma/degamma tests when
> >>> using a HDR plane, which is always the case unless one hacks
> >>> the test to use an SDR plane. If one does hack the test to use
> >>> an SDR plane it does pass already.
> >>>
> >>> I have no actual explanation how the output after the gamma
> >>> LUT can be different between the two modes. The way the tests
> >>> are written should mean that the output should be identical
> >>> between the solid color vs. the gradient. But clearly that
> >>> somehow doesn't hold true for the HDR planes in non-HDR pipe
> >>> mode. Anyways, as long as we stick to one type of plane the
> >>> test should produce sensible results now.
> >>>
> >>> Signed-off-by: Ville Syrjälä
> >>> ---
> >>>drivers/gpu/drm/i915/i915_reg.h | 1 +
> >>>drivers/gpu/drm/i915/intel_display.c | 7 +++
> >>>drivers/gpu/drm/i915/intel_sprite.h | 12
> >>>3 files changed, 16 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >>> b/drivers/gpu/drm/i915/i915_reg.h
> >>> index 8ad2f0a03f28..90d60ecd3317 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -5767,6 +5767,7 @@ enum {
> >>>#define _PIPE_MISC_B 0x71030
> >>>#define PIPEMISC_YUV420_ENABLE (1 << 27)
> >>>#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
> >>> +#define PIPEMISC_HDR_MODE (1 << 23) /* icl+ */
> >>>#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
> >>>#define PIPEMISC_DITHER_BPC_MASK (7 << 5)
> >>>#define PIPEMISC_DITHER_8_BPC(0 << 5)
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>> b/drivers/gpu/drm/i915/intel_display.c
> >>> index 490bd49ff42a..d0dbdbd5db3f 100644
> >>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -4055,6 +4055,9 @@ static void intel_update_pipe_config(const struct
> >>> intel_crtc_state *old_crtc_sta
> >>> ironlake_pfit_disable(old_crtc_state);
> >>> }
> >>>
> >>> + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> >>> + bdw_set_pipemisc(new_crtc_state);
> >>> +
> >>> if (INTEL_GEN(dev_priv) >= 11)
> >>> icl_set_pipe_chicken(crtc);
> >>>}
> >>> @@ -8869,6 +8872,10 @@ static void bdw_set_pipemisc(const struct
> >>> intel_crtc_state *crtc_state)
> >>> val |= PIPEMISC_YUV420_ENABLE |
> >>> PIPEMISC_YUV420_MODE_FULL_BLEND;
> >>>
> >>> + if (INTEL_GEN(dev_priv) >= 11 &&
> >>> + (crtc_state->active_planes & ~icl_hdr_plane_mask()) == 0)
> >>> + val |= PIPEMISC_HDR_MODE;
> >>> +
> >> Shouldn't we check if the content being played on plane is HDR before
> >> enabling this bit (even though I am not sure if there is any harm in
> >> doing that)? Or maybe check the connector->output_hdr_metadata ? Most of
> >> the times we would be sending SDR buffers on this plane. What happens
> >> exactly when we set this bit ? The bspec says:
> >>
> >> "This field enables the HDR mode, allowing for higher precision output
> >> from the HDR supporting planes and bypassing the SDR planes in blending. "
> > I think the bit is just misnamed (like most things with "HDR" in their
> > name). It's just a "gimme moar precision" bit.
>
> Lets make this a bit more clear, may be rename the bit to
> PIPEMISC_HDR_PRECISION_MODE instead?
Then it won't match the spec.
>
> With that change, this patch is
>
> Reviewed-by: Shashank Sharma
>
> >
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Corrupt DSI picture fix for GeminiLake
== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake URL : https://patchwork.freedesktop.org/series/60084/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Corrupt DSI picture fix for GeminiLake -O:drivers/gpu/drm/i915/intel_cdclk.c:2266:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2266:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2275:29: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake
HI,
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: tiistai 30. huhtikuuta 2019 11.01
> To: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com
> Cc: Saarinen, Jani ; Peres, Martin
>
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for
> GeminiLake
>
> On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote:
> > On Tue, 30 Apr 2019, Stanislav Lisovskiy <
> > stanislav.lisovs...@intel.com> wrote:
> > > Currently due to regression CI machine displays show corrupt
> > > picture.
> > > Problem is when CDCLK is as low as 79200, picture gets unstable,
> > > while DSI and DE pll values were confirmed to be correct.
> > > Limiting to 158400 as agreed with Ville.
> > >
> > > We could not come up with any better solution yet, as PLL divider
> > > values both for MIPI(DSI PLL) and CDCLK(DE PLL) are correct, however
> > > seems that due to some boundary conditions, when clocking is too low
> > > we get wrong timings for DSI display.
> > > Similar workaround exists for VLV though, so just took similar
> > > condition into use. At least that way GLK platform will start to be
> > > usable again, with current drm-tip.
> > >
> > > v2: Fixed commit subject as suggested.
> > >
> > > Signed-off-by: Stanislav Lisovskiy
> > > Acked-by: Ville Syrjälä
> >
> > Do we have a bugzilla link?
> >
> > BR,
> > Jani.
>
> No, or at least I'm not aware of. I just got a machine from CI for
> investigation :) I
> guess it might be worth to create a bug for that.
>
>
> Martin: do we have a bug for CI GLK issue?
We did had some bugs, but not sure if those are related to this issue.
>
> -Stanislav
>
> >
> >
> > > ---
> > > drivers/gpu/drm/i915/intel_cdclk.c | 9 +
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index ae40a8679314..2b23f8500362 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const
> > > struct intel_crtc_state *crtc_state)
> > > IS_VALLEYVIEW(dev_priv))
> > > min_cdclk = max(32, min_cdclk);
> > >
> > > + /*
> > > + * On Geminilake once the CDCLK gets as low as 79200
> > > + * picture gets unstable, despite that values are
> > > + * correct for DSI PLL and DE PLL.
> > > + */
> > > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > > + IS_GEMINILAKE(dev_priv))
> > > + min_cdclk = max(158400, min_cdclk);
> > > +
> > > if (min_cdclk > dev_priv->max_cdclk_freq) {
> > > DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d
> kHz)\n",
> > > min_cdclk, dev_priv->max_cdclk_freq);
> >
> >
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Re: [Intel-gfx] [PATCH 00/21] drm/i915: the great header refactoring, part two
Quoting Jani Nikula (2019-04-29 13:29:18) > Continue the header refactoring started in part one [1]. > > BR, > Jani. > > [1] https://patchwork.freedesktop.org/series/59022/ > > > Jani Nikula (21): > drm/i915: ensure more headers remain self-contained > drm/i915: make intel_bios.h self-contained > drm/i915/dvo: rename dvo.h to intel_dvo_dev.h and make self-contained > drm/i915: make intel_dpll_mgr.h self-contained > drm/i915: move dsi init functions to intel_dsi.h > drm/i915: extract intel_fifo_underrun.h from intel_drv.h > drm/i915: extract intel_dp_link_training.h from intel_drv.h > drm/i915: extract intel_dp_aux_backlight.h from intel_drv.h > drm/i915: extract i915_irq.h from intel_drv.h and i915_drv.h > drm/i915: extract intel_hotplug.h from intel_drv.h and i915_drv.h > drm/i915: extract intel_bios.h functions from i915_drv.h > drm/i915: extract intel_quirks.h from intel_drv.h > drm/i915: extract intel_overlay.h from intel_drv.h and i915_drv.h > drm/i915: extract intel_vdsc.h from intel_drv.h and i915_drv.h > drm/i915: extract intel_dp_mst.h from intel_drv.h > drm/i915: extract intel_dsi_dcs_backlight.h from intel_drv.h > drm/i915: extract intel_atomic.h from intel_drv.h > drm/i915: extract intel_runtime_pm.h from intel_drv.h > drm/i915: move some leftovers to intel_pm.h from i915_drv.h > drm/i915: extract intel_combo_phy.h from i915_drv.h > drm/i915: add single combo phy init/unit functions I read them all and they look sane. I trust the HDRTEST infrastructure to spot any typos, so Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 19/21] drm/i915: move some leftovers to intel_pm.h from i915_drv.h
Quoting Joonas Lahtinen (2019-04-30 08:24:07)
> Quoting Jani Nikula (2019-04-29 16:03:33)
> > On Mon, 29 Apr 2019, Chris Wilson wrote:
> > > Quoting Jani Nikula (2019-04-29 13:29:37)
> > >> Commit 696173b064c6 ("drm/i915: extract intel_pm.h from intel_drv.h")
> > >> missed the declarations in i915_drv.h.
> > >
> > > Fwiw, I want to pull these along with gt powermanagement and rps into
> > > gt/intel_gt_pm.c and a few friends.
> > >
> > > Doesn't make much difference for this patch; just planned obsolescence.
> >
> > I'm fine either way, via this patch or directly.
> >
> > In general I like how it's easier to look at the new headers and wonder
> > why on earth some functions are in the files they are, and try to come
> > up with better division into files.
> >
> > ---
> >
> > I'm also trying to probe feedback on some style guidelines I might like
> > to enforce in the future:
> >
> > 1) A file and the non-static functions in it should have the same
> >prefix, i.e. intel_foo.c has functions prefixed intel_foo_*.
> >
> > 2) No file should have platform specific non-static functions, i.e. all
> >the non-static functions should be intel_foo_* and this should
> >internally split to platform_foo_* instead of leaving the if ladders
> >or function pointer initializations to the callers.
>
> Agreed on these. GEM side has been moving to this direction slowly.
>
> > So, thoughts on naming the functions intel_gt_pm_* upon moving them?
>
> Sounds reasonable to me.
And indeed the patches from last year where already making that
transformation :)
Next generation of patches are aiming to split up the different
functions under the intel_gt_pm umbrella, but still following the same
principle.
-Chris
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[Intel-gfx] [PATCH 1/2] drm/i915: Wait for the struct_mutex on idling
When the system is idling, contention for struct_mutex should be low and
so we will be more efficient to wait for a contended mutex than
reschedule.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_pm.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 3554d55dae35..3b6e8d5be8e1 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -47,13 +47,7 @@ static void idle_work_handler(struct work_struct *work)
struct drm_i915_private *i915 =
container_of(work, typeof(*i915), gem.idle_work.work);
- if (!mutex_trylock(>drm.struct_mutex)) {
- /* Currently busy, come back later */
- mod_delayed_work(i915->wq,
->gem.idle_work,
-msecs_to_jiffies(50));
- return;
- }
+ mutex_lock(>drm.struct_mutex);
intel_wakeref_lock(>gt.wakeref);
if (!intel_wakeref_active(>gt.wakeref))
--
2.20.1
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[Intel-gfx] [PATCH 2/2] drm/i915: Cancel retire_worker on parking
Replace the racy continuation check within retire_work with a definite
kill-switch on idling. The race was being exposed by gem_concurrent_blit
where the retire_worker would be terminated too early leaving us
spinning in debugfs/i915_drop_caches with nothing flushing the
retirement queue.
Although that the igt is trying to idle from one child while submitting
from another may be a contributing factor as to why it runs so slowly...
Testcase: igt/gem_concurrent_blit
Fixes: 79ffac8599c4 ("drm/i915: Invert the GEM wakeref hierarchy")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_pm.c| 27 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 3 +--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 3b6e8d5be8e1..88be810758ae 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -46,15 +46,23 @@ static void idle_work_handler(struct work_struct *work)
{
struct drm_i915_private *i915 =
container_of(work, typeof(*i915), gem.idle_work.work);
+ bool restart = true;
+ cancel_delayed_work_sync(>gem.retire_work);
mutex_lock(>drm.struct_mutex);
intel_wakeref_lock(>gt.wakeref);
- if (!intel_wakeref_active(>gt.wakeref))
+ if (!intel_wakeref_active(>gt.wakeref)) {
i915_gem_park(i915);
+ restart = false;
+ }
intel_wakeref_unlock(>gt.wakeref);
mutex_unlock(>drm.struct_mutex);
+ if (restart)
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
}
static void retire_work_handler(struct work_struct *work)
@@ -68,10 +76,9 @@ static void retire_work_handler(struct work_struct *work)
mutex_unlock(>drm.struct_mutex);
}
- if (intel_wakeref_active(>gt.wakeref))
- queue_delayed_work(i915->wq,
- >gem.retire_work,
- round_jiffies_up_relative(HZ));
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
}
static int pm_notifier(struct notifier_block *nb,
@@ -159,15 +166,9 @@ void i915_gem_suspend(struct drm_i915_private *i915)
* reset the GPU back to its idle, low power state.
*/
GEM_BUG_ON(i915->gt.awake);
- cancel_delayed_work_sync(>gpu_error.hangcheck_work);
-
- drain_delayed_work(>gem.retire_work);
+ flush_delayed_work(>gem.idle_work);
- /*
-* As the idle_work is rearming if it detects a race, play safe and
-* repeat the flush until it is definitely idle.
-*/
- drain_delayed_work(>gem.idle_work);
+ cancel_delayed_work_sync(>gpu_error.hangcheck_work);
i915_gem_drain_freed_objects(i915);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index e4033d0576c4..ce54f8dc13cc 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -58,8 +58,7 @@ static void mock_device_release(struct drm_device *dev)
i915_gem_contexts_lost(i915);
mutex_unlock(>drm.struct_mutex);
- drain_delayed_work(>gem.retire_work);
- drain_delayed_work(>gem.idle_work);
+ flush_delayed_work(>gem.idle_work);
i915_gem_drain_workqueue(i915);
mutex_lock(>drm.struct_mutex);
--
2.20.1
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[Intel-gfx] [PATCH v2] drm/i915: Only reschedule the submission tasklet if preemption is possible
If we couple the scheduler more tightly with the execlists policy, we
can apply the preemption policy to the question of whether we need to
kick the tasklet at all for this priority bump.
v2: Rephrase it as a core i915 policy and not an execlists foible.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 18 --
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 7 ++-
drivers/gpu/drm/i915/i915_request.c | 2 --
drivers/gpu/drm/i915/i915_scheduler.c | 18 +++---
drivers/gpu/drm/i915/i915_scheduler.h | 18 ++
drivers/gpu/drm/i915/intel_guc_submission.c | 3 ++-
7 files changed, 39 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 3e53f53bc52b..317712d6f7e6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -106,24 +106,6 @@ hangcheck_action_to_str(const enum
intel_engine_hangcheck_action a)
void intel_engines_set_scheduler_caps(struct drm_i915_private *i915);
-static inline bool __execlists_need_preempt(int prio, int last)
-{
- /*
-* Allow preemption of low -> normal -> high, but we do
-* not allow low priority tasks to preempt other low priority
-* tasks under the impression that latency for low priority
-* tasks does not matter (as much as background throughput),
-* so kiss.
-*
-* More naturally we would write
-* prio >= max(0, last);
-* except that we wish to prevent triggering preemption at the same
-* priority level: the task that is running should remain running
-* to preserve FIFO ordering of dependencies.
-*/
- return prio > max(I915_PRIORITY_NORMAL - 1, last);
-}
-
static inline void
execlists_set_active(struct intel_engine_execlists *execlists,
unsigned int bit)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 01f58a152a9e..4cb87d96deb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -251,8 +251,8 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
* ourselves, ignore the request.
*/
last_prio = effective_prio(rq);
- if (!__execlists_need_preempt(engine->execlists.queue_priority_hint,
- last_prio))
+ if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
+last_prio))
return false;
/*
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 84538f69185b..4b042893dc0e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -638,14 +638,19 @@ static struct i915_request *dummy_request(struct
intel_engine_cs *engine)
GEM_BUG_ON(i915_request_completed(rq));
i915_sw_fence_init(>submit, dummy_notify);
- i915_sw_fence_commit(>submit);
+ set_bit(I915_FENCE_FLAG_ACTIVE, >fence.flags);
return rq;
}
static void dummy_request_free(struct i915_request *dummy)
{
+ /* We have to fake the CS interrupt to kick the next request */
+ i915_sw_fence_commit(>submit);
+
i915_request_mark_complete(dummy);
+ dma_fence_signal(>fence);
+
i915_sched_node_fini(>sched);
i915_sw_fence_fini(>submit);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index af8c9fa5e066..2e22da66a56c 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1358,9 +1358,7 @@ long i915_request_wait(struct i915_request *rq,
if (flags & I915_WAIT_PRIORITY) {
if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
gen6_rps_boost(rq);
- local_bh_disable(); /* suspend tasklets for reprioritisation */
i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
- local_bh_enable(); /* kick tasklets en masse */
}
wait.tsk = current;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 39bc4f54e272..88d18600f5db 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -261,16 +261,20 @@ sched_lock_engine(const struct i915_sched_node *node,
return engine;
}
-static bool inflight(const struct i915_request *rq,
-const struct intel_engine_cs *engine)
+static inline int rq_prio(const struct i915_request *rq)
{
- const struct i915_request *active;
+ return rq->sched.attr.priority | __NO_PREEMPTION;
+}
+
+static bool kick_tasklet(const struct intel_engine_cs *engine, int prio)
+{
+
Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format
On Tue, 30 Apr 2019, Vandita Kulkarni wrote:
> Read back the pixel fomrat register and get the bpp.
>
> v2: Read the PIPE_MISC register (Jani).
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 3 +++
> drivers/gpu/drm/i915/intel_dsi.h | 1 +
> drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
> 3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index dbb2712..5cc58b2 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct intel_encoder
> *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
>
> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> pipe_config->port_clock =
> @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct intel_encoder
> *encoder,
> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> gen11_dsi_get_timings(encoder, pipe_config);
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
> }
>
> static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> @@ -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
> struct drm_display_mode *adjusted_mode =
> _config->base.adjusted_mode;
>
> + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h
> b/drivers/gpu/drm/i915/intel_dsi.h
> index 705a609..cb9e3b9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct
> drm_connector *connector,
> struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
> const struct mipi_dsi_host_ops
> *funcs,
> enum port port);
> +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
Until now this was internal to vlv_dsi.c and it was fine. Now, I think
I'd move this to intel_display.c alongside haswell_set_pipemisc.
Ville already has patches to rename haswell_set_pipemisc to
bdw_set_pipemisc.
BR,
Jani.
>
> /* vlv_dsi_pll.c */
> int vlv_dsi_pll_compute(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index b4c6583..790ada8 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private
> *dev_priv)
> vlv_flisdsi_put(dev_priv);
> }
>
> -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 tmp;
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add N & CTS values for 10/12 bit deep color
On Thu, 04 Apr 2019, Aditya Swarup wrote:
> On Tue, Apr 02, 2019 at 05:14:40AM -0700, Aditya Swarup wrote:
>> Adding N & CTS values for 10/12 bit deep color from Appendix C
>> table in HDMI 2.0 spec. The correct values for N is not chosen
>> automatically by hardware for deep color modes.
>>
>> v2: Remove redundant code and make it generic.(Jani)
>>
>> Signed-off-by: Aditya Swarup
>> Cc: Clint Taylor
>> Cc: Ville Syrjälä
>> Cc: Jani Nikula
>> Cc: Manasi Navare
>> ---
>> drivers/gpu/drm/i915/intel_audio.c | 82 +-
>> 1 file changed, 69 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_audio.c
>> b/drivers/gpu/drm/i915/intel_audio.c
>> index 502b57ce72ab..ad53b04fa5a2 100644
>> --- a/drivers/gpu/drm/i915/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>> @@ -70,6 +70,13 @@ struct dp_aud_n_m {
>> u16 n;
>> };
>>
>> +struct hdmi_aud_ncts_table {
>> +int sample_rate;
>> +int clock;
>> +int n;
>> +int cts;
>> +};
>> +
>> /* Values according to DP 1.4 Table 2-104 */
>> static const struct dp_aud_n_m dp_aud_n_m[] = {
>> { 32000, LC_162M, 1024, 10125 },
>> @@ -146,12 +153,7 @@ static const struct {
>> #define TMDS_594M 594000
>> #define TMDS_593M 593407
>>
>> -static const struct {
>> -int sample_rate;
>> -int clock;
>> -int n;
>> -int cts;
>> -} hdmi_aud_ncts[] = {
>> +static const struct hdmi_aud_ncts_table hdmi_aud_ncts_24bpp[] = {
>> { 32000, TMDS_296M, 5824, 421875 },
>> { 32000, TMDS_297M, 3072, 222750 },
>> { 32000, TMDS_593M, 5824, 843750 },
>> @@ -182,6 +184,49 @@ static const struct {
>> { 192000, TMDS_594M, 24576, 594000 },
>> };
>>
>> +/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
>> +/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
>> +#define TMDS_371M 371250
>> +#define TMDS_370M 370878
>> +
>> +static const struct hdmi_aud_ncts_table hdmi_aud_ncts_30bpp[] = {
>> +{ 32000, TMDS_370M, 5824, 527344 },
>> +{ 32000, TMDS_371M, 6144, 556875 },
>> +{ 44100, TMDS_370M, 8918, 585938 },
>> +{ 44100, TMDS_371M, 4704, 309375 },
>> +{ 88200, TMDS_370M, 17836, 585938 },
>> +{ 88200, TMDS_371M, 9408, 309375 },
>> +{ 176400, TMDS_370M, 35672, 585938 },
>> +{ 176400, TMDS_371M, 18816, 309375 },
>> +{ 48000, TMDS_370M, 11648, 703125 },
>> +{ 48000, TMDS_371M, 5120, 309375 },
>> +{ 96000, TMDS_370M, 23296, 703125 },
>> +{ 96000, TMDS_371M, 10240, 309375 },
>> +{ 192000, TMDS_370M, 46592, 703125 },
>> +{ 192000, TMDS_371M, 20480, 309375 },
>> +};
>> +
>> +/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
>> +#define TMDS_445_5M 445500
>> +#define TMDS_445M 445054
>> +
>> +static const struct hdmi_aud_ncts_table hdmi_aud_ncts_36bpp[] = {
>> +{ 32000, TMDS_445M, 5824, 632813 },
>> +{ 32000, TMDS_445_5M, 4096, 445500 },
>> +{ 44100, TMDS_445M, 8918, 703125 },
>> +{ 44100, TMDS_445_5M, 4704, 371250 },
>> +{ 88200, TMDS_445M, 17836, 703125 },
>> +{ 88200, TMDS_445_5M, 9408, 371250 },
>> +{ 176400, TMDS_445M, 35672, 703125 },
>> +{ 176400, TMDS_445_5M, 18816, 371250 },
>> +{ 48000, TMDS_445M, 5824, 421875 },
>> +{ 48000, TMDS_445_5M, 5120, 371250 },
>> +{ 96000, TMDS_445M, 11648, 421875 },
>> +{ 96000, TMDS_445_5M, 10240, 371250 },
>> +{ 192000, TMDS_445M, 23296, 421875 },
>> +{ 192000, TMDS_445_5M, 20480, 371250 },
>> +};
>> +
>> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
>> static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state
>> *crtc_state)
>> {
>> @@ -210,16 +255,27 @@ static u32 audio_config_hdmi_pixel_clock(const struct
>> intel_crtc_state *crtc_sta
>> static int audio_config_hdmi_get_n(const struct intel_crtc_state
>> *crtc_state,
>> int rate)
>> {
>> -const struct drm_display_mode *adjusted_mode =
>> -_state->base.adjusted_mode;
>> -int i;
>> +const struct hdmi_aud_ncts_table *hdmi_ncts_table;
>> +int i, size = 0;
>> +
>> +if (crtc_state->pipe_bpp == 36) {
>> +hdmi_ncts_table = hdmi_aud_ncts_36bpp;
>> +size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
>> +} else if (crtc_state->pipe_bpp == 30) {
>> +hdmi_ncts_table = hdmi_aud_ncts_30bpp;
>> +size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
>> +} else {
>> +hdmi_ncts_table = hdmi_aud_ncts_24bpp;
>> +size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
>> +}
>>
>> -for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
>> -if (rate == hdmi_aud_ncts[i].sample_rate &&
>> -adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
>> -return hdmi_aud_ncts[i].n;
>> +for (i = 0; i < size; i++) {
>> +if (rate == hdmi_ncts_table[i].sample_rate &&
>> +crtc_state->port_clock == hdmi_ncts_table[i].clock) {
>> +return hdmi_ncts_table[i].n;
>>
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ville
>Syrjälä
>Sent: Friday, April 26, 2019 8:07 PM
>To: Sharma, Shashank
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if
>only
>HDR planes are used
>
>On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
>>
>> On 4/13/2019 12:00 AM, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > The pipe has a special HDR mode with higher precision when only HDR
>> > planes are active. Let's use it.
>> >
>> > Curiously this fixes the kms_color gamma/degamma tests when using a
>> > HDR plane, which is always the case unless one hacks the test to use
>> > an SDR plane. If one does hack the test to use an SDR plane it does
>> > pass already.
>> >
>> > I have no actual explanation how the output after the gamma LUT can
>> > be different between the two modes. The way the tests are written
>> > should mean that the output should be identical between the solid
>> > color vs. the gradient. But clearly that somehow doesn't hold true
>> > for the HDR planes in non-HDR pipe mode. Anyways, as long as we
>> > stick to one type of plane the test should produce sensible results
>> > now.
>> >
>> > Signed-off-by: Ville Syrjälä
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 1 +
>> > drivers/gpu/drm/i915/intel_display.c | 7 +++
>> > drivers/gpu/drm/i915/intel_sprite.h | 12
>> > 3 files changed, 16 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index 8ad2f0a03f28..90d60ecd3317
>> > 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -5767,6 +5767,7 @@ enum {
>> > #define _PIPE_MISC_B 0x71030
>> > #define PIPEMISC_YUV420_ENABLE (1 << 27)
>> > #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
>> > +#define PIPEMISC_HDR_MODE (1 << 23) /* icl+ */
>> > #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
>> > #define PIPEMISC_DITHER_BPC_MASK (7 << 5)
>> > #define PIPEMISC_DITHER_8_BPC (0 << 5)
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > b/drivers/gpu/drm/i915/intel_display.c
>> > index 490bd49ff42a..d0dbdbd5db3f 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -4055,6 +4055,9 @@ static void intel_update_pipe_config(const struct
>intel_crtc_state *old_crtc_sta
>> >ironlake_pfit_disable(old_crtc_state);
>> >}
>> >
>> > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>> > + bdw_set_pipemisc(new_crtc_state);
>> > +
>> >if (INTEL_GEN(dev_priv) >= 11)
>> >icl_set_pipe_chicken(crtc);
>> > }
>> > @@ -8869,6 +8872,10 @@ static void bdw_set_pipemisc(const struct
>intel_crtc_state *crtc_state)
>> >val |= PIPEMISC_YUV420_ENABLE |
>> >PIPEMISC_YUV420_MODE_FULL_BLEND;
>> >
>> > + if (INTEL_GEN(dev_priv) >= 11 &&
>> > + (crtc_state->active_planes & ~icl_hdr_plane_mask()) == 0)
>> > + val |= PIPEMISC_HDR_MODE;
>> > +
>>
>> Shouldn't we check if the content being played on plane is HDR before
>> enabling this bit (even though I am not sure if there is any harm in
>> doing that)? Or maybe check the connector->output_hdr_metadata ? Most
>> of the times we would be sending SDR buffers on this plane. What
>> happens exactly when we set this bit ? The bspec says:
>>
>> "This field enables the HDR mode, allowing for higher precision output
>> from the HDR supporting planes and bypassing the SDR planes in blending. "
>
>I think the bit is just misnamed (like most things with "HDR" in their name).
>It's just a
>"gimme moar precision" bit.
Yeah AFAIU this bit just enables pipe to work at higher precision mode which
should be ok
if we actually require lower precision (SDR cases) and shouldn't cause any
problem. And will
be a must if actual HDR data is processed on the planes which will require
higher precision.
However enabling this always for HDR planes irrespective of content is actually
fixing the crc
errors.
This patch is
Reviewed-by: Uma Shankar
And
Tested-by: Uma Shankar
>
>--
>Ville Syrjälä
>Intel
>___
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>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Disable semaphore busywaits on saturated systems
Quoting Tvrtko Ursulin (2019-04-30 09:55:59) > > On 29/04/2019 19:00, Chris Wilson wrote: > So I am still leaning towards being cautious and just abandoning > semaphores for now. Fwiw, we have another 4 weeks to pull the plug for 5.2. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Disable semaphore busywaits on saturated systems
Quoting Tvrtko Ursulin (2019-04-30 09:55:59) > > On 29/04/2019 19:00, Chris Wilson wrote: > > Asking the GPU to busywait on a memory address, perhaps not unexpectedly > > in hindsight for a shared system, leads to bus contention that affects > > CPU programs trying to concurrently access memory. This can manifest as > > a drop in transcode throughput on highly over-saturated workloads. > > > > The only clue offered by perf, is that the bus-cycles (perf stat -e > > bus-cycles) jumped by 50% when enabling semaphores. This corresponds > > with extra CPU active cycles being attributed to intel_idle's mwait. > > > > This patch introduces a heuristic to try and detect when more than one > > client is submitting to the GPU pushing it into an oversaturated state. > > As we already keep track of when the semaphores are signaled, we can > > inspect their state on submitting the busywait batch and if we planned > > to use a semaphore but were too late, conclude that the GPU is > > overloaded and not try to use semaphores in future requests. In > > practice, this means we optimistically try to use semaphores for the > > first frame of a transcode job split over multiple engines, and fail is > > there are multiple clients active and continue not to use semaphores for > > the subsequent frames in the sequence. Periodically, trying to > > optimistically switch semaphores back on whenever the client waits to > > catch up with the transcode results. > > > > [snipped long benchmark results] > > > Indicating that we've recovered the regression from enabling semaphores > > on this saturated setup, with a hint towards an overall improvement. > > > > Very similar, but of smaller magnitude, results are observed on both > > Skylake(gt2) and Kabylake(gt4). This may be due to the reduced impact of > > bus-cycles, where we see a 50% hit on Broxton, it is only 10% on the big > > core, in this particular test. > > > > One observation to make here is that for a greedy client trying to > > maximise its own throughput, using semaphores is the right choice. It is > > only the holistic system-wide view that semaphores of one client > > impacts another and reduces the overall throughput where we would choose > > to disable semaphores. > > Since we acknowledge problem is the shared nature of the iGPU, my > concern is that we still cannot account for both partners here when > deciding to omit semaphore emission. In other words we trade bus > throughput for submission latency. > > Assuming a light GPU task (in the sense of not oversubscribing, but with > ping-pong inter-engine dependencies), simultaneous to a heavier CPU > task, our latency improvement still imposes a performance penalty on the > latter. Maybe, maybe not. I think you have to be in the position where there is no GPU latency to be gained for the increased bus traffic to lose. > For instance a consumer level single stream transcoding session with CPU > heavy part of the pipeline, or a CPU intensive game. > > (Ideally we would need a bus saturation signal to feed into our logic, > not just engine saturation. Which I don't think is possible.) > > So I am still leaning towards being cautious and just abandoning > semaphores for now. Being greedy, the single consumer case is compelling. The same benchmarks see 5-10% throughput improvement for the single client (depending on machine). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Expand subslice mask
On Mon, 29 Apr 2019, Stuart Summers wrote:
> Currently, the subslice_mask runtime parameter is stored as an
> array of subslices per slice. Expand the subslice mask array to
> better match what is presented to userspace through the
> I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
> then calculated:
> slice * subslice stride + subslice index / 8
>
> v2: fix spacing in set_sseu_info args
> use set_sseu_info to initialize sseu data when building
> device status in debugfs
> rename variables in intel_engine_types.h to avoid checkpatch
> warnings
> v3: update headers in intel_sseu.h
>
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++--
> drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
> drivers/gpu/drm/i915/gt/intel_sseu.h | 45 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 43 +++---
> drivers/gpu/drm/i915/i915_drv.c | 6 +-
> drivers/gpu/drm/i915/i915_gpu_error.c| 5 +-
> drivers/gpu/drm/i915/i915_query.c| 10 +-
> drivers/gpu/drm/i915/intel_device_info.c | 139 +++
> 10 files changed, 183 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index f7308479d511..8922358ee6c6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -908,7 +908,7 @@ u32 intel_calculate_mcr_s_ss_select(struct
> drm_i915_private *dev_priv)
> const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
> u32 mcr_s_ss_select;
> u32 slice = fls(sseu->slice_mask);
> - u32 subslice = fls(sseu->subslice_mask[slice]);
> + u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
>
> if (IS_GEN(dev_priv, 10))
> mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> @@ -984,6 +984,7 @@ void intel_engine_get_instdone(struct intel_engine_cs
> *engine,
> struct intel_instdone *instdone)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> + struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
const?
> struct intel_uncore *uncore = engine->uncore;
> u32 mmio_base = engine->mmio_base;
> int slice;
> @@ -1001,7 +1002,8 @@ void intel_engine_get_instdone(struct intel_engine_cs
> *engine,
>
> instdone->slice_common =
> intel_uncore_read(uncore, GEN7_SC_INSTDONE);
> - for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
> + for_each_instdone_slice_subslice(dev_priv, sseu, slice,
> + subslice) {
> instdone->sampler[slice][subslice] =
> read_subslice_reg(dev_priv, slice, subslice,
> GEN7_SAMPLER_INSTDONE);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index d972c339309c..fa70528963a4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct
> intel_engine_cs *engine)
> return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> }
>
> -#define instdone_slice_mask(dev_priv__) \
> - (IS_GEN(dev_priv__, 7) ? \
> - 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
> -
> -#define instdone_subslice_mask(dev_priv__) \
> - (IS_GEN(dev_priv__, 7) ? \
> - 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
> -
> -#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> - for ((slice__) = 0, (subslice__) = 0; \
> - (slice__) < I915_MAX_SLICES; \
> - (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
> (subslice__) + 1 : 0, \
> -(slice__) += ((subslice__) == 0)) \
> - for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) &&
> \
> - (BIT(subslice__) &
> instdone_subslice_mask(dev_priv__)))
> +#define instdone_has_slice(dev_priv___, sseu___, slice___) \
> + ((IS_GEN(dev_priv___, 7) ? \
> + 1 : (sseu___)->slice_mask) & \
> + BIT(slice___)) \
> +
> +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
> + ((IS_GEN(dev_priv__, 7) ? \
> + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
> + subslice__ / BITS_PER_BYTE]) & \
> + BIT(subslice__ % BITS_PER_BYTE)) \
> +
> +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_,
> subslice_) \
> + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
> + (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h
On Mon, 29 Apr 2019, Stuart Summers wrote:
> Signed-off-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.h | 47
> drivers/gpu/drm/i915/intel_device_info.h | 47
> 2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index f5ff6b7a756a..5127b4ff92bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info
> *sseu)
> return value;
> }
>
> +static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
> *sseu)
> +{
> + unsigned int i, total = 0;
> +
> + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> + total += hweight8(sseu->subslice_mask[i]);
> +
> + return total;
> +}
> +
> static inline unsigned int
> sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> {
> return hweight8(sseu->subslice_mask[slice]);
> }
>
> +static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> + int slice, int subslice)
> +{
> + int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> +BITS_PER_BYTE);
> + int slice_stride = sseu->max_subslices * subslice_stride;
> +
> + return slice * slice_stride + subslice * subslice_stride;
> +}
> +
> +static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> +int slice, int subslice)
> +{
> + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> + u16 eu_mask = 0;
> +
> + for (i = 0;
> + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> + eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> + (i * BITS_PER_BYTE);
> + }
> +
> + return eu_mask;
> +}
> +
> +static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> + int slice, int subslice, u16 eu_mask)
> +{
> + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> +
> + for (i = 0;
> + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> + sseu->eu_mask[offset + i] =
> + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> + }
> +}
> +
I'd appreciate follow-up to rename these functions
intel_sseu_*. Functions in intel_foo.[ch] should be named intel_foo_*().
Also, I'm starting to wonder the benefits of the plethora of inline
functions we use. Should we move them to the .c file? It can't be a perf
thing can it?
BR,
Jani.
> u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
>const struct intel_sseu *req_sseu);
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 5a2e17d6146b..6412a9c72898 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -218,53 +218,6 @@ struct intel_driver_caps {
> bool has_logical_contexts:1;
> };
>
> -static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
> *sseu)
> -{
> - unsigned int i, total = 0;
> -
> - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> - total += hweight8(sseu->subslice_mask[i]);
> -
> - return total;
> -}
> -
> -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> - int slice, int subslice)
> -{
> - int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> -BITS_PER_BYTE);
> - int slice_stride = sseu->max_subslices * subslice_stride;
> -
> - return slice * slice_stride + subslice * subslice_stride;
> -}
> -
> -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> -int slice, int subslice)
> -{
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> - u16 eu_mask = 0;
> -
> - for (i = 0;
> - i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> - eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> - (i * BITS_PER_BYTE);
> - }
> -
> - return eu_mask;
> -}
> -
> -static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> - int slice, int subslice, u16 eu_mask)
> -{
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> -
> - for (i = 0;
> - i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> - sseu->eu_mask[offset + i] =
> - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> - }
> -}
> -
> const char *intel_platform_name(enum intel_platform platform);
>
> void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
--
Jani Nikula, Intel Open Source Graphics Center
___
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Disable semaphore busywaits on saturated systems
On 29/04/2019 19:00, Chris Wilson wrote:
Asking the GPU to busywait on a memory address, perhaps not unexpectedly
in hindsight for a shared system, leads to bus contention that affects
CPU programs trying to concurrently access memory. This can manifest as
a drop in transcode throughput on highly over-saturated workloads.
The only clue offered by perf, is that the bus-cycles (perf stat -e
bus-cycles) jumped by 50% when enabling semaphores. This corresponds
with extra CPU active cycles being attributed to intel_idle's mwait.
This patch introduces a heuristic to try and detect when more than one
client is submitting to the GPU pushing it into an oversaturated state.
As we already keep track of when the semaphores are signaled, we can
inspect their state on submitting the busywait batch and if we planned
to use a semaphore but were too late, conclude that the GPU is
overloaded and not try to use semaphores in future requests. In
practice, this means we optimistically try to use semaphores for the
first frame of a transcode job split over multiple engines, and fail is
there are multiple clients active and continue not to use semaphores for
the subsequent frames in the sequence. Periodically, trying to
optimistically switch semaphores back on whenever the client waits to
catch up with the transcode results.
[snipped long benchmark results]
Indicating that we've recovered the regression from enabling semaphores
on this saturated setup, with a hint towards an overall improvement.
Very similar, but of smaller magnitude, results are observed on both
Skylake(gt2) and Kabylake(gt4). This may be due to the reduced impact of
bus-cycles, where we see a 50% hit on Broxton, it is only 10% on the big
core, in this particular test.
One observation to make here is that for a greedy client trying to
maximise its own throughput, using semaphores is the right choice. It is
only the holistic system-wide view that semaphores of one client
impacts another and reduces the overall throughput where we would choose
to disable semaphores.
Since we acknowledge problem is the shared nature of the iGPU, my
concern is that we still cannot account for both partners here when
deciding to omit semaphore emission. In other words we trade bus
throughput for submission latency.
Assuming a light GPU task (in the sense of not oversubscribing, but with
ping-pong inter-engine dependencies), simultaneous to a heavier CPU
task, our latency improvement still imposes a performance penalty on the
latter.
For instance a consumer level single stream transcoding session with CPU
heavy part of the pipeline, or a CPU intensive game.
(Ideally we would need a bus saturation signal to feed into our logic,
not just engine saturation. Which I don't think is possible.)
So I am still leaning towards being cautious and just abandoning
semaphores for now.
Regards,
Tvrtko
The most noticeable negactive impact this has is on the no-op
microbenchmarks, which are also very notable for having no cpu bus load.
In particular, this increases the runtime and energy consumption of
gem_exec_whisper.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Dmitry Rogozhkin
Cc: Dmitry Ermilov
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gt/intel_context.c | 2 ++
drivers/gpu/drm/i915/gt/intel_context_types.h | 3 ++
drivers/gpu/drm/i915/i915_request.c | 28 ++-
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 1f1761fc6597..5b31e1e05ddd 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -116,6 +116,7 @@ intel_context_init(struct intel_context *ce,
ce->engine = engine;
ce->ops = engine->cops;
ce->sseu = engine->sseu;
+ ce->saturated = 0;
INIT_LIST_HEAD(>signal_link);
INIT_LIST_HEAD(>signals);
@@ -158,6 +159,7 @@ void intel_context_enter_engine(struct intel_context *ce)
void intel_context_exit_engine(struct intel_context *ce)
{
+ ce->saturated = 0;
intel_engine_pm_put(ce->engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index d5a7dbd0daee..963a312430e6 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -13,6 +13,7 @@
#include
#include "i915_active_types.h"
+#include "intel_engine_types.h"
#include "intel_sseu.h"
struct i915_gem_context;
@@ -52,6 +53,8 @@ struct intel_context {
atomic_t pin_count;
struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
+ intel_engine_mask_t saturated; /* submitting semaphores too late? */
+
/**
* active_tracker: Active tracker for the external rq activity
* on this intel_context object.
diff --git a/drivers/gpu/drm/i915/i915_request.c
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
On Mon, 29 Apr 2019, Stuart Summers wrote:
> In the GETPARAM ioctl handler, use a local variable to consolidate
> usage of SSEU runtime info.
>
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/i915_drv.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index aacc8dd6ecfd..b6ce7580d414 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -321,6 +321,7 @@ static int i915_getparam_ioctl(struct drm_device *dev,
> void *data,
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct pci_dev *pdev = dev_priv->drm.pdev;
> + struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
const?
> drm_i915_getparam_t *param = data;
> int value;
>
> @@ -374,12 +375,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
> void *data,
> value = i915_cmd_parser_get_version(dev_priv);
> break;
> case I915_PARAM_SUBSLICE_TOTAL:
> - value = sseu_subslice_total(_INFO(dev_priv)->sseu);
> + value = sseu_subslice_total(sseu);
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_EU_TOTAL:
> - value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
> + value = sseu->eu_total;
> if (!value)
> return -ENODEV;
> break;
> @@ -396,7 +397,7 @@ static int i915_getparam_ioctl(struct drm_device *dev,
> void *data,
> value = HAS_POOLED_EU(dev_priv);
> break;
> case I915_PARAM_MIN_EU_IN_POOL:
> - value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
> + value = sseu->min_eu_in_pool;
> break;
> case I915_PARAM_HUC_STATUS:
> value = intel_huc_check_status(_priv->huc);
> @@ -446,12 +447,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
> void *data,
> value = intel_engines_has_context_isolation(dev_priv);
> break;
> case I915_PARAM_SLICE_MASK:
> - value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
> + value = sseu->slice_mask;
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_SUBSLICE_MASK:
> - value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
> + value = sseu->subslice_mask[0];
> if (!value)
> return -ENODEV;
> break;
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add register definitions for Multi Segmented gamma
On 4/29/2019 7:42 PM, Jani Nikula wrote:
On Fri, 26 Apr 2019, Shashank Sharma wrote:
From: Uma Shankar
Add macros to define multi segmented gamma registers
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74824f0b5b1..fc50e85ca895 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7198,6 +7198,7 @@ enum {
#define GAMMA_MODE_MODE_10BIT(1 << 0)
#define GAMMA_MODE_MODE_12BIT(2 << 0)
#define GAMMA_MODE_MODE_SPLIT(3 << 0)
+#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0)
/* DMC/CSR */
#define CSR_PROGRAM(i)_MMIO(0x8 + (i) * 4)
@@ -10144,6 +10145,22 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Add registers for Gen11 Multi Segmented Gamma Mode */
+#define _PAL_PREC_MULTI_SEG_INDEX_A0x4A408
+#define _PAL_PREC_MULTI_SEG_INDEX_B0x4AC08
+#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT BIT(15)
+#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK (0x1f << 0)
See REG_BIT() and REG_FIELD_PREP() at the top of the file.
BR,
Jani.
Got it Jani, Thanks !
Regards
Shashank
+
+#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
+#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+
+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_INDEX_A, \
+ _PAL_PREC_MULTI_SEG_INDEX_B)
+#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_DATA_A, \
+ _PAL_PREC_MULTI_SEG_DATA_B)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
___
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