Re: [Intel-gfx] [PATCH v2 3/7] lib/hexdump.c: Optionally suppress lines of repeated bytes
On 5/8/19 12:01 AM, Alastair D'Silva wrote: > From: Alastair D'Silva > > Some buffers may only be partially filled with useful data, while the rest > is padded (typically with 0x00 or 0xff). > > This patch introduces a flag to allow the supression of lines of repeated > bytes, which are replaced with '** Skipped %u bytes of value 0x%x **' > > An inline wrapper function is provided for backwards compatibility with > existing code, which maintains the original behaviour. > > Signed-off-by: Alastair D'Silva > --- > include/linux/printk.h | 25 +--- > lib/hexdump.c | 91 -- > 2 files changed, 99 insertions(+), 17 deletions(-) > Hi, Did you do "make htmldocs" or something similar on this? > diff --git a/lib/hexdump.c b/lib/hexdump.c > index 3943507bc0e9..d61a1e4f19fa 100644 > --- a/lib/hexdump.c > +++ b/lib/hexdump.c > @@ -212,8 +212,44 @@ int hex_dump_to_buffer(const void *buf, size_t len, int > rowsize, int groupsize, > EXPORT_SYMBOL(hex_dump_to_buffer); > > #ifdef CONFIG_PRINTK > + > +/** > + * Check if a buffer contains only a single byte value > + * @buf: pointer to the buffer > + * @len: the size of the buffer in bytes > + * @val: outputs the value if if the bytes are identical Does this work without a function name? Documentation/doc-guide/kernel-doc.rst says the general format is: /** * function_name() - Brief description of function. * @arg1: Describe the first argument. * @arg2: Describe the second argument. *One can provide multiple line descriptions *for arguments. * > + */ > /** > - * print_hex_dump - print a text hex dump to syslog for a binary blob of data > + * print_hex_dump_ext: dump a binary blob of data to syslog in hexadecimal Also not in the general documented format. > * @level: kernel log level (e.g. KERN_DEBUG) > * @prefix_str: string to prefix each line with; > * caller supplies trailing spaces for alignment if desired -- ~Randy ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable Multi-segmented-gamma for ICL (rev3)
== Series Details == Series: Enable Multi-segmented-gamma for ICL (rev3) URL : https://patchwork.freedesktop.org/series/60126/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6065_full -> Patchwork_12989_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12989_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12989_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12989_full: ### IGT changes ### Possible regressions * igt@kms_color@pipe-b-ctm-0-25: - shard-iclb: [PASS][1] -> [FAIL][2] +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb2/igt@kms_co...@pipe-b-ctm-0-25.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb2/igt@kms_co...@pipe-b-ctm-0-25.html Known issues Here are the changes found in Patchwork_12989_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-apl3/igt@gem_ctx_isolat...@bcs0-s3.html * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#104097]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb4/igt@i915_pm_...@i2c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb6/igt@i915_pm_...@i2c.html * igt@i915_pm_rpm@legacy-planes-dpms: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#107807]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl7/igt@i915_pm_...@legacy-planes-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl1/igt@i915_pm_...@legacy-planes-dpms.html * igt@kms_color@pipe-b-gamma: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#104782]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb1/igt@kms_co...@pipe-b-gamma.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb7/igt@kms_co...@pipe-b-gamma.html * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108] / [fdo#107773]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl4/igt@kms_cursor_...@cursor-256x256-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl10/igt@kms_cursor_...@cursor-256x256-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#102887] / [fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk7/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-glk2/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-x-tiled: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#108303]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb8/igt@kms_flip_til...@flip-x-tiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb8/igt@kms_flip_til...@flip-x-tiled.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: - shard-glk: [PASS][21] -> [SKIP][22] ([fdo#109271] / [fdo#109278]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk9/igt@kms_plane_scal...@pipe-b-scaler-with-pixel-format.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/shard-glk1/igt@kms_plane_scal...@pipe-b-scaler-with-pixel-format.html *
[Intel-gfx] ✓ Fi.CI.IGT: success for Add HDR Metadata Parsing and handling in DRM layer (rev9)
== Series Details == Series: Add HDR Metadata Parsing and handling in DRM layer (rev9) URL : https://patchwork.freedesktop.org/series/25091/ State : success == Summary == CI Bug Log - changes from CI_DRM_6065_full -> Patchwork_12988_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12988_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-iclb: [PASS][1] -> [FAIL][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb2/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-iclb6/igt@gem_tiled_swapp...@non-threaded.html - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([fdo#108686]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-apl1/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-apl2/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_suspend@forcewake: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-apl6/igt@i915_susp...@forcewake.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-apl4/igt@i915_susp...@forcewake.html * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl3/igt@kms_cursor_...@cursor-64x64-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-skl5/igt@kms_cursor_...@cursor-64x64-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#102887] / [fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk7/igt@kms_f...@flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#100368]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl3/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-skl3/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: - shard-glk: [PASS][17] -> [SKIP][18] ([fdo#109271] / [fdo#109278]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk9/igt@kms_plane_scal...@pipe-b-scaler-with-pixel-format.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-glk2/igt@kms_plane_scal...@pipe-b-scaler-with-pixel-format.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-iclb4/igt@kms_psr@psr2_sprite_plane_onoff.html * igt@kms_vblank@pipe-c-accuracy-idle: - shard-glk: [PASS][21] -> [FAIL][22] ([fdo#102583]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-glk3/igt@kms_vbl...@pipe-c-accuracy-idle.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-glk3/igt@kms_vbl...@pipe-c-accuracy-idle.html Possible fixes * igt@gem_workarounds@suspend-resume-context: - shard-skl: [INCOMPLETE][23] ([fdo#104108] / [fdo#107773]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/shard-skl1/igt@gem_workarou...@suspend-resume-context.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/shard-skl3/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@dpms-lpsp: - shard-skl: [INCOMPLETE][25] ([fdo#107807]) -> [PASS][26] +2
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL
On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> ICL has so many planes that it can easily exceed the maximum
> effective memory bandwidth of the system. We must therefore check
> that we don't exceed that limit.
>
> The algorithm is very magic number heavy and lacks sufficient
> explanation for now. We also have no sane way to query the
> memory clock and timings, so we must rely on a combination of
> raw readout from the memory controller and hardcoded assumptions.
> The memory controller values obviously change as the system
> jumps between the different SAGV points, so we try to stabilize
> it first by disabling SAGV for the duration of the readout.
>
> The utilized bandwidth is tracked via a device wide atomic
> private object. That is actually not robust because we can't
> afford to enforce strict global ordering between the pipes.
> Thus I think I'll need to change this to simply chop up the
> available bandwidth between all the active pipes. Each pipe
> can then do whatever it wants as long as it doesn't exceed
> its budget. That scheme will also require that we assume that
> any number of planes could be active at any time.
>
> TODO: make it robust and deal with all the open questions
>
> v2: Sleep longer after disabling SAGV
> v3: Poll for the dclk to get raised (seen it take 250ms!)
> If the system has 2133MT/s memory then we pointlessly
> wait one full second :(
> v4: Use the new pcode interface to get the qgv points rather
> that using hardcoded numbers
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.c | 229
> ++
> drivers/gpu/drm/i915/i915_drv.h | 10 +
> drivers/gpu/drm/i915/i915_reg.h | 3 +
> drivers/gpu/drm/i915/intel_atomic_plane.c | 20 ++
> drivers/gpu/drm/i915/intel_atomic_plane.h | 2 +
> drivers/gpu/drm/i915/intel_bw.c | 181 +
> drivers/gpu/drm/i915/intel_bw.h | 46 +
> drivers/gpu/drm/i915/intel_display.c | 40 +++-
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 10 files changed, 533 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/intel_bw.c
> create mode 100644 drivers/gpu/drm/i915/intel_bw.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 68106fe35a04..139a0fc19390 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -138,6 +138,7 @@ i915-y += intel_audio.o \
> intel_atomic.o \
> intel_atomic_plane.o \
> intel_bios.o \
> + intel_bw.o \
> intel_cdclk.o \
> intel_color.o \
> intel_combo_phy.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 5ed864752c7b..b7fa7b51c2e2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -70,6 +70,7 @@
> #include "intel_overlay.h"
> #include "intel_pipe_crc.h"
> #include "intel_pm.h"
> +#include "intel_sideband.h"
> #include "intel_sprite.h"
> #include "intel_uc.h"
>
> @@ -1435,6 +1436,232 @@ bxt_get_dram_info(struct drm_i915_private
> *dev_priv)
> return 0;
> }
>
> +struct intel_qgv_point {
> + u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
> +};
> +
> +struct intel_sagv_info {
> + struct intel_qgv_point points[3];
> + u8 num_points;
> + u8 num_channels;
> + u8 t_bl;
> + enum intel_dram_type dram_type;
> +};
> +
> +static int icl_pcode_read_mem_global_info(struct drm_i915_private
> *dev_priv,
> + struct intel_sagv_info *si)
> +{
> + u32 val = 0;
> + int ret;
> +
> + ret = sandybridge_pcode_read(dev_priv,
> + ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
> + , NULL);
> + if (ret)
> + return ret;
> +
> + switch (val & 0xf) {
> + case 0:
> + si->dram_type = INTEL_DRAM_DDR4;
> + break;
> + case 1:
> + si->dram_type = INTEL_DRAM_DDR3;
> + break;
> + case 2:
> + si->dram_type = INTEL_DRAM_LPDDR3;
> + break;
> + case 3:
> + si->dram_type = INTEL_DRAM_LPDDR3;
> + break;
> + default:
> + MISSING_CASE(val & 0xf);
> + break;
> + }
> +
> + si->num_channels = (val & 0xf0) >> 4;
> + si->num_points = (val & 0xf00) >> 8;
> +
> + si->t_bl = si->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
> +
> + return 0;
> +}
> +
> +static int icl_pcode_read_qgv_point_info(struct drm_i915_private
> *dev_priv,
> + struct intel_qgv_point *sp,
> + int point)
Are we trying to retrieve the dram timing parameters to calculate the
latency? If so can that be
[Intel-gfx] [PULL] drm-misc-next-fixes
Hi Da.*, So last week when I said we were ready for merge window... I lied. Lots of stuff to sneak in this week including 6 patches that came from -misc-next. Fortunately they _just_ missed the feature freeze so I was able to tag and merge them here. Most of what is here is panfrost fixes, which is understandable given its age, I expect this trend will continue this release as it becomes more mature. The sole msm patch is here b/c that's all Rob and I have for -fixes in msm atm and it was easier to just stuff it in here. drm-misc-next-fixes-2019-05-08: - A handful of fixes from -next that just missed feature freeze - More panfrost fixes that went directly in -misc-next-fixes (various) - Fix searchpaths during build (Masahiro) - msm patch to fix the driver for chips without zap shader (Rob) - Fix freeing imported buffers in drm_gem_cma_free_object() (Noralf) Cc: Masahiro Yamada Cc: Rob Clark Cc: Noralf Trønnes Cheers, Sean The following changes since commit 761e473f6b23f206862d904a1a5fcbc012656b47: drm/gem: Fix sphinx warnings (2019-04-25 10:02:10 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2019-05-08 for you to fetch changes up to 15273ffd7efdf6e9f21c4e4beef6539229167343: drm/msm/a6xx: No zap shader is not an error (2019-05-08 16:00:54 -0400) - A handful of fixes from -next that just missed feature freeze - More panfrost fixes that went directly in -misc-next-fixes (various) - Fix searchpaths during build (Masahiro) - msm patch to fix the driver for chips without zap shader (Rob) - Fix freeing imported buffers in drm_gem_cma_free_object() (Noralf) Cc: Masahiro Yamada Cc: Rob Clark Cc: Noralf Trønnes Mario Kleiner (1): drm: Fix timestamp docs for variable refresh properties. Masahiro Yamada (1): drm: prefix header search paths with $(srctree)/ Noralf Trønnes (1): drm/cma-helper: Fix drm_gem_cma_free_object() Rob Clark (1): drm/msm/a6xx: No zap shader is not an error Robin Murphy (4): drm/panfrost: Set DMA masks earlier drm/panfrost: Disable PM on probe failure drm/panfrost: Don't scream about deferred probe drm/panfrost: Show stored feature registers Sean Paul (1): Merge panfrost-fixes into drm-misc-next-fixes Steven Price (2): drm/panfrost: Add missing include drm/panfrost: depend on !GENERIC_ATOMIC64 when using COMPILE_TEST Tomeu Vizoso (2): drm/panfrost: Prevent concurrent resets drm/panfrost: Add sanity checks to submit IOCTL Vicente Bergas (1): drm/rockchip: shutdown drm subsystem on shutdown YueHaibing (1): drm/panfrost: Make panfrost_gem_free_object() static drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/arm/display/komeda/Makefile | 4 +-- drivers/gpu/drm/drm_connector.c | 6 drivers/gpu/drm/drm_gem_cma_helper.c| 8 ++--- drivers/gpu/drm/i915/gvt/Makefile | 2 +- drivers/gpu/drm/msm/Makefile| 6 ++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 1 + drivers/gpu/drm/nouveau/Kbuild | 8 ++--- drivers/gpu/drm/panfrost/Kconfig| 2 +- drivers/gpu/drm/panfrost/panfrost_devfreq.c | 1 + drivers/gpu/drm/panfrost/panfrost_device.c | 1 + drivers/gpu/drm/panfrost/panfrost_device.h | 1 + drivers/gpu/drm/panfrost/panfrost_drv.c | 47 ++--- drivers/gpu/drm/panfrost/panfrost_gem.c | 2 +- drivers/gpu/drm/panfrost/panfrost_gpu.c | 19 +++- drivers/gpu/drm/panfrost/panfrost_job.c | 4 +++ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 9 ++ 17 files changed, 75 insertions(+), 48 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register
On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The pcode mailbox has two data registers. So far we've only ever used
> the one, but that's about to change. Expose the second data register
> to
> the callers of sandybridge_pcode_read().
>
> Signed-off-by: Ville Syrjälä
LGTM
Reviewed-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/intel_pm.c | 12 +++-
> drivers/gpu/drm/i915/intel_sideband.c | 15 +--
> drivers/gpu/drm/i915/intel_sideband.h | 3 ++-
> 4 files changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 14cd83e9ea8b..203088f6f269 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1494,7 +1494,7 @@ static int gen6_drpc_info(struct seq_file *m)
>
> if (INTEL_GEN(dev_priv) <= 7)
> sandybridge_pcode_read(dev_priv,
> GEN6_PCODE_READ_RC6VIDS,
> -);
> +, NULL);
>
> seq_printf(m, "RC1e Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> @@ -1777,7 +1777,7 @@ static int i915_ring_freq_table(struct seq_file
> *m, void *unused)
> ia_freq = gpu_freq;
> sandybridge_pcode_read(dev_priv,
> GEN6_PCODE_READ_MIN_FREQ_TABLE,
> -_freq);
> +_freq, NULL);
> seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> intel_gpu_freq(dev_priv, (gpu_freq *
>(IS_GEN9_BC(dev_pr
> iv) ||
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index ef9fc77f8162..b043a96e123c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2822,7 +2822,7 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> val = 0; /* data0 to be programmed to 0 for first set
> */
> ret = sandybridge_pcode_read(dev_priv,
>GEN9_PCODE_READ_MEM_LATENC
> Y,
> - );
> + , NULL);
>
> if (ret) {
> DRM_ERROR("SKL Mailbox read error = %d\n",
> ret);
> @@ -2841,7 +2841,7 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> val = 1; /* data0 to be programmed to 1 for second set
> */
> ret = sandybridge_pcode_read(dev_priv,
>GEN9_PCODE_READ_MEM_LATENC
> Y,
> - );
> + , NULL);
> if (ret) {
> DRM_ERROR("SKL Mailbox read error = %d\n",
> ret);
> return;
> @@ -7061,7 +7061,7 @@ static void gen6_init_rps_frequencies(struct
> drm_i915_private *dev_priv)
>
> if (sandybridge_pcode_read(dev_priv,
> HSW_PCODE_DYNAMIC_DUTY_CYCLE
> _CONTROL,
> -_status) == 0)
> +_status, NULL) == 0)
> rps->efficient_freq =
> clamp_t(u8,
> ((ddcc_status >> 8) & 0xff),
> @@ -7408,7 +7408,8 @@ static void gen6_enable_rc6(struct
> drm_i915_private *dev_priv)
> GEN6_RC_CTL_HW_ENABLE);
>
> rc6vids = 0;
> - ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
> );
> + ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
> + , NULL);
> if (IS_GEN(dev_priv, 6) && ret) {
> DRM_DEBUG_DRIVER("Couldn't check for BIOS
> workaround\n");
> } else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids
> & 0xff) < 450)) {
> @@ -8555,7 +8556,8 @@ void intel_init_gt_powersave(struct
> drm_i915_private *dev_priv)
> IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
> u32 params = 0;
>
> - sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS,
> );
> + sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS,
> +, NULL);
> if (params & BIT(31)) { /* OC supported */
> DRM_DEBUG_DRIVER("Overclocking supported, max:
> %dMHz, overclock: %dMHz\n",
>(rps->max_freq & 0xff) * 50,
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> b/drivers/gpu/drm/i915/intel_sideband.c
> index 87b5a14c7ca8..a115625e980c 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -374,7 +374,7 @@ static
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Multi-segmented-gamma for ICL (rev3)
== Series Details ==
Series: Enable Multi-segmented-gamma for ICL (rev3)
URL : https://patchwork.freedesktop.org/series/60126/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6065 -> Patchwork_12989
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/
Known issues
Here are the changes found in Patchwork_12989 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([fdo#107709])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-bsw-kefka/igt@i915_selftest@live_evict.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-bsw-kefka/igt@i915_selftest@live_evict.html
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278])
+2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-skl-6770hq/igt@kms_b...@basic-flip-c.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-skl-6770hq/igt@kms_b...@basic-flip-c.html
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
Possible fixes
* igt@i915_selftest@live_hangcheck:
- {fi-icl-y}: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-icl-y/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-icl-y/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: [INCOMPLETE][11] ([fdo#103927] / [fdo#110624]) ->
[DMESG-FAIL][12] ([fdo#110620])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
* igt@runner@aborted:
- fi-apl-guc: [FAIL][13] ([fdo#110624]) -> [FAIL][14] ([fdo#110622])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-apl-guc/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/fi-apl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620
[fdo#110622]: https://bugs.freedesktop.org/show_bug.cgi?id=110622
[fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624
Participating hosts (53 -> 45)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6065 -> Patchwork_12989
CI_DRM_6065: 4ce82224f3c40ee55f11a505b57247f8f540990a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4973: 3e3ff0e48989abd25fce4916e85e8fef20a3c63a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12989: 4020491ef16ee377ff619d71ad828cf682db3ecd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4020491ef16e drm/i915/icl: Add Multi-segmented gamma support
ec51ec6a38e3 drm/i915: Rename ivb_load_lut_10_max
904edca45871 drm/i915/icl: Add register definitions for Multi Segmented gamma
1f1169d2b4ac drm/i915: Change gamma/degamma_lut_size data type to u32
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12989/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/icl: Add Multi-segmented gamma support
We (Me and Uma) confirmed the ICL register programming sequence, by
dumping the registers.
The correct sequence should be:
ilk_lut_12p4_udw
ilk_lut_12p4_ldw
We passed maximum value LUT (1.0) and saw only blue output, if
programmed in opposite sequence.
Programming in above mentioned sequence gives a proper white output.
Regards
Shashank
On 5/8/2019 6:35 PM, Sharma, Shashank wrote:
On 5/7/2019 7:57 PM, Ville Syrjälä wrote:
On Tue, May 07, 2019 at 07:26:44PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from value range between 0.0 to
1.0,
ICL's multi-segment has 3 different sections:
- superfine segment: 9 values, ranges between 0 - 1/(128 * 256)
- fine segment: 257 values, ranges between 0 - 1/(128)
- corase segment: 257 values, ranges between 0 - 1
This patch:
- Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 *
256),
so that userspace can program with highest precision supported.
- Changes default gamma mode (non-legacy) to multi-segmented-gamma
mode.
- Adds functions to program/detect multi-segment gamma.
V2: Addressed review comments from Ville
- separate function for superfine and fine segments.
- remove enum for segments.
- reuse last entry of the LUT as gc_max value.
- replace if() cond with switch...case in icl_load_luts.
- add an entry variable, instead of 'word'
V3: Addressed review comments from Ville
- extra newline
- s/entry/color/
- remove LUT size checks
- program ilk_lut_12p4_ldw value before ilk_lut_12p4_udw
- Change the comments in description of fine and coarse segments,
and try to make more sense.
- use 8 * 128 instead of 1024
- add 1 entry in LUT for GCMAX
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Suggested-by: Ville Syrjälä
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_color.c | 127
-
2 files changed, 124 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c
b/drivers/gpu/drm/i915/i915_pci.c
index ffa2ee70a03d..2f99b585d44b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -749,7 +749,7 @@ static const struct intel_device_info
intel_cannonlake_info = {
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1, \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
+ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 6c341bea514c..c1a9506fd069 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -41,6 +41,8 @@
#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
#define LEGACY_LUT_LENGTH 256
+#define ICL_GAMMA_MULTISEG_LUT_LENGTH (256 * 128 * 8)
Unused.
Got it
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32
fixed point
* format). This macro takes the coefficient we want transformed
and the
@@ -767,6 +769,116 @@ static void glk_load_luts(const struct
intel_crtc_state *crtc_state)
}
}
+/* ilk+ "12.4" interpolated format (high 10 bits) */
+static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
+{
+ return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
+ (color->blue >> 6);
+}
+
+/* ilk+ "12.4" interpolated format (low 6 bits) */
+static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
+{
+ return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
+ (color->blue & 0x3f);
Blue is missing the shift.
Ok,
I'm not 100% sure if the ldw vs. udw are the right way around. The spec
has at times been inconsistent with the odd vs. even descriptions,
sometimes even contradicting itself. Also it never really defines
whether it starts counting dwords from from 0 or 1, so not sure what
odd and even actually mean. Can I presume someone has checked this
on actual hardware?
Well, the property was getting set properly, and the display looked
ok, but dint dump the values in registers. Can check it now.
+}
+
+static void
+icl_load_gcmax(const struct intel_crtc_state *crtc_state,
+ const struct drm_color_lut *color)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ /* Fixme: LUT entries are 16 bit only, so we can prog 0x
max */
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
+
[Intel-gfx] [PATCH v4 0/4] Enable Multi-segmented-gamma for ICL
This patch series enables programming of Multi-segmented-gamma palette for ICL. Shashank Sharma (3): drm/i915: Change gamma/degamma_lut_size data type to u32 drm/i915: Rename ivb_load_lut_10_max drm/i915/icl: Add Multi-segmented gamma support Uma Shankar (1): drm/i915/icl: Add register definitions for Multi Segmented gamma drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 19 ++- drivers/gpu/drm/i915/intel_color.c | 140 +-- drivers/gpu/drm/i915/intel_device_info.h | 4 +- 4 files changed, 150 insertions(+), 15 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32
Currently, data type of gamma_lut_size & degamma_lut_size elements
in intel_device_info is u16, which means it can accommodate maximum
64k values. In case of ICL multisegmented gamma, the size of gamma
LUT is 256K.
This patch changes the data type of both of these elements to u32.
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Uma Shankar
V4: Added Uma's r-b.
Reviewed-by: Uma Shankar
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_device_info.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..67677c356716 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -179,8 +179,8 @@ struct intel_device_info {
int cursor_offsets[I915_MAX_PIPES];
struct color_luts {
- u16 degamma_lut_size;
- u16 gamma_lut_size;
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
u32 degamma_lut_tests;
u32 gamma_lut_tests;
} color;
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 4/4] drm/i915/icl: Add Multi-segmented gamma support
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from value range between 0.0 to 1.0,
ICL's multi-segment has 3 different sections:
- superfine segment: 9 values, ranges between 0 - 1/(128 * 256)
- fine segment: 257 values, ranges between 0 - 1/(128)
- corase segment: 257 values, ranges between 0 - 1
This patch:
- Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 * 256),
so that userspace can program with highest precision supported.
- Changes default gamma mode (non-legacy) to multi-segmented-gamma mode.
- Adds functions to program/detect multi-segment gamma.
V2: Addressed review comments from Ville
- separate function for superfine and fine segments.
- remove enum for segments.
- reuse last entry of the LUT as gc_max value.
- replace if() cond with switch...case in icl_load_luts.
- add an entry variable, instead of 'word'
V3: Addressed review comments from Ville
- extra newline
- s/entry/color/
- remove LUT size checks
- program ilk_lut_12p4_ldw value before ilk_lut_12p4_udw
- Change the comments in description of fine and coarse segments,
and try to make more sense.
- use 8 * 128 instead of 1024
- add 1 entry in LUT for GCMAX
V4: Addressed review comments from Ville
- Remove unused macro
- missing shift entry in blue
- pick correct entry for GCMAX
- Added Ville's R-B
Note: Tested and confirmed the programming sequence of odd/even
registers in the HW. The correct sequence should be:
ilk_lut_12p4_udw
ilk_lut_12p4_ldw
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Reviewed-by: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c| 2 +-
drivers/gpu/drm/i915/intel_color.c | 126 -
2 files changed, 123 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d7c07a947497..24305238b4ea 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -747,7 +747,7 @@ static const struct intel_device_info intel_cannonlake_info
= {
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1, \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
+ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 6c341bea514c..22ccbeacbee2 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -41,6 +41,7 @@
#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
#define LEGACY_LUT_LENGTH 256
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -767,6 +768,116 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
}
}
+/* ilk+ "12.4" interpolated format (high 10 bits) */
+static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
+{
+ return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
+ (color->blue >> 6);
+}
+
+/* ilk+ "12.4" interpolated format (low 6 bits) */
+static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
+{
+ return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
+ (color->blue & 0x3f << 4);
+}
+
+static void
+icl_load_gcmax(const struct intel_crtc_state *crtc_state,
+ const struct drm_color_lut *color)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ /* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+}
+
+static void
+icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
+ const struct drm_color_lut *lut = blob->data;
+ enum pipe pipe = crtc->pipe;
+ u32 i;
+
+ /*
+* Every entry in the multi-segment LUT is corresponding to a superfine
+* segment step which is 1/(8 * 128 * 256).
+*
+* Superfine segment has 9
[Intel-gfx] [PATCH v4 2/4] drm/i915/icl: Add register definitions for Multi Segmented gamma
From: Uma Shankar
Add macros to define multi segmented gamma registers
V2: Addressed Ville's comments:
Add gen-lable before bit definition
Addressed Jani's comment
- Use REG_GENMASK() and REG_BIT()
V3: Addressed Ville's comments:
- Put comments at the end of line.
- Change the comment at start of ICL multisegmented gamma registers.
Added Ville's r-b
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/i915_reg.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e97c47fca645..8b77c067e26b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7198,7 +7198,8 @@ enum {
#define GAMMA_MODE_MODE_8BIT (0 << 0)
#define GAMMA_MODE_MODE_10BIT (1 << 0)
#define GAMMA_MODE_MODE_12BIT (2 << 0)
-#define GAMMA_MODE_MODE_SPLIT (3 << 0)
+#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
+#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
/* DMC/CSR */
#define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
@@ -10145,6 +10146,22 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* ICL Multi segmented gamma */
+#define _PAL_PREC_MULTI_SEG_INDEX_A0x4A408
+#define _PAL_PREC_MULTI_SEG_INDEX_B0x4AC08
+#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
+#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
+
+#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
+#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+
+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_INDEX_A, \
+ _PAL_PREC_MULTI_SEG_INDEX_B)
+#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_DATA_A, \
+ _PAL_PREC_MULTI_SEG_DATA_B)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
2.17.1
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[Intel-gfx] [PATCH v4 3/4] drm/i915: Rename ivb_load_lut_10_max
This patch renames function ivb_load_lut_10_max to
ivb_load_lut_ext_max.
V3: Added Vill'es r-b.
Cc: Uma Shankar
Suggested-by: Ville Syrjala
Reviewed-by: Ville Syrjala
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_color.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 962db1236970..6c341bea514c 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -607,7 +607,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
-static void ivb_load_lut_10_max(struct intel_crtc *crtc)
+static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -640,7 +640,7 @@ static void ivb_load_luts(const struct intel_crtc_state
*crtc_state)
} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(512));
} else {
@@ -648,7 +648,7 @@ static void ivb_load_luts(const struct intel_crtc_state
*crtc_state)
ivb_load_lut_10(crtc, blob,
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
@@ -663,7 +663,7 @@ static void bdw_load_luts(const struct intel_crtc_state
*crtc_state)
} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
PAL_PREC_INDEX_VALUE(512));
} else {
@@ -671,7 +671,7 @@ static void bdw_load_luts(const struct intel_crtc_state
*crtc_state)
bdw_load_lut_10(crtc, blob,
PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
@@ -763,7 +763,7 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
i9xx_load_luts(crtc_state);
} else {
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
@@ -780,7 +780,7 @@ static void icl_load_luts(const struct intel_crtc_state
*crtc_state)
i9xx_load_luts(crtc_state);
} else {
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
- ivb_load_lut_10_max(crtc);
+ ivb_load_lut_ext_max(crtc);
}
}
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for Add HDR Metadata Parsing and handling in DRM layer (rev9)
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev9)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6065 -> Patchwork_12988
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/
Known issues
Here are the changes found in Patchwork_12988 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([fdo#107709])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-bsw-kefka/igt@i915_selftest@live_evict.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/fi-bsw-kefka/igt@i915_selftest@live_evict.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#109485])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@i915_selftest@live_hangcheck:
- {fi-icl-y}: [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-icl-y/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/fi-icl-y/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: [INCOMPLETE][7] ([fdo#103927] / [fdo#110624]) ->
[INCOMPLETE][8] ([fdo#103927])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6065/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624
Participating hosts (53 -> 45)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6065 -> Patchwork_12988
CI_DRM_6065: 4ce82224f3c40ee55f11a505b57247f8f540990a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4973: 3e3ff0e48989abd25fce4916e85e8fef20a3c63a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12988: 8bd7456bcc7f7323e227ab42d9539edc6cb078fd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8bd7456bcc7f drm/i915: Add state readout for DRM infoframe
40ccaedcd208 video/hdmi: Add Unpack function for DRM infoframe
0c8ec025a0ff drm/i915: Added DRM Infoframe handling for BYT/CHT
a2c9e4ca880d drm/i915: Set Infoframe for non modeset case for HDR
2c0cd563ef64 drm/i915:Enabled Modeset when HDR Infoframe changes
2068040dcd3c drm/i915: Enable infoframes on GLK+ for HDR
a3bd3148742b drm: Add HLG EOTF
e59e2225c608 drm/i915: Write HDR infoframe and send to panel
a4cac5224d14 drm/i915: Attach HDR metadata property to connector
421fb3c1ee47 drm: Enable HDR infoframe support
7d53c237452a drm: Parse HDR metadata info from EDID
d278f4561318 drm: Add reference counting on HDR metadata blob
b14249ae3b1a drm: Add HDR source metadata property
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12988/
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add HDR Metadata Parsing and handling in DRM layer (rev9)
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev9)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b14249ae3b1a drm: Add HDR source metadata property
-:70: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#70: FILE: drivers/gpu/drm/drm_atomic_uapi.c:733:
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >hdr_output_metadata,
total: 0 errors, 0 warnings, 1 checks, 153 lines checked
d278f4561318 drm: Add reference counting on HDR metadata blob
7d53c237452a drm: Parse HDR metadata info from EDID
421fb3c1ee47 drm: Enable HDR infoframe support
a4cac5224d14 drm/i915: Attach HDR metadata property to connector
e59e2225c608 drm/i915: Write HDR infoframe and send to panel
a3bd3148742b drm: Add HLG EOTF
2068040dcd3c drm/i915: Enable infoframes on GLK+ for HDR
-:54: WARNING:LONG_LINE: line over 100 characters
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:8190:
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans,
_GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
total: 0 errors, 1 warnings, 0 checks, 81 lines checked
2c0cd563ef64 drm/i915:Enabled Modeset when HDR Infoframe changes
-:86: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#86: FILE: drivers/gpu/drm/i915/intel_hdmi.c:833:
+ if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
+ connector->hdr_sink_metadata.hdmi_type1.eotf)) {
total: 0 errors, 0 warnings, 1 checks, 60 lines checked
a2c9e4ca880d drm/i915: Set Infoframe for non modeset case for HDR
0c8ec025a0ff drm/i915: Added DRM Infoframe handling for BYT/CHT
40ccaedcd208 video/hdmi: Add Unpack function for DRM infoframe
8bd7456bcc7f drm/i915: Add state readout for DRM infoframe
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[Intel-gfx] [v9 00/13] Add HDR Metadata Parsing and handling in DRM layer
This patch series enables HDR support in drm. It basically defines HDR metadata structures, property to pass content (after blending) metadata from user space compositors to driver. Dynamic Range and Mastering infoframe creation and sending. ToDo: 1. We need to get the color framework in place for all planes which support HDR content in hardware. This is already in progres and patches are out for review in mailing list. 2. UserSpace/Compositors: Blending policies and metadata blob creation and passing to driver. Work is already in progress by Intel's middleware teams on wayland and the patches for the same are in review. A POC has already been developed by Ville based on wayland. Please refer below link to see the component interactions and usage: https://lists.freedesktop.org/archives/wayland-devel/2017-December/036403.html v2: Updated Ville's POC changes to the patch series.Incorporated cleanups and fixes from Ville. Rebase on latest drm-tip. v3: Fixed a warning causing builds to break on CI. No major change. v4: Addressed Shashank's review comments. v5: Rebase on top of Ville's infoframe refactoring changes. Fixed non modeset case for HDR metadata update. Dropped a redundant patch. v6: Addressed Shashank's review comments and added RB's received. v7: Squashed 2 patches, dropped 1 change and addressed Brian Starkey's and Shashank's review comments. v8: Addressed Jonas Karlman review comments. Added Shashank's RB to the series, fixed a WARN_ON on BYT/CHT. v9: Addressed Ville and Jonas Karlman's review comments. Added the infoframe state readout and metadata reference count. Note: This is already tested with Kodi and a confirmation from team kodi has been received. Branch details for the same as below: https://github.com/xbmc/xbmc/tree/feature_drmprime-vaapi Jonas Karlman (1): drm: Add reference counting on HDR metadata blob Uma Shankar (10): drm: Add HDR source metadata property drm: Parse HDR metadata info from EDID drm: Enable HDR infoframe support drm/i915: Attach HDR metadata property to connector drm/i915: Write HDR infoframe and send to panel drm/i915:Enabled Modeset when HDR Infoframe changes drm/i915: Set Infoframe for non modeset case for HDR drm/i915: Added DRM Infoframe handling for BYT/CHT video/hdmi: Add Unpack function for DRM infoframe drm/i915: Add state readout for DRM infoframe Ville Syrjälä (2): drm: Add HLG EOTF drm/i915: Enable infoframes on GLK+ for HDR drivers/gpu/drm/drm_atomic.c | 2 + drivers/gpu/drm/drm_atomic_state_helper.c | 6 + drivers/gpu/drm/drm_atomic_uapi.c | 13 ++ drivers/gpu/drm/drm_connector.c | 6 + drivers/gpu/drm/drm_edid.c| 101 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_atomic.c | 14 +- drivers/gpu/drm/i915/intel_ddi.c | 17 +++ drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 100 - drivers/video/hdmi.c | 240 ++ include/drm/drm_connector.h | 11 ++ include/drm/drm_edid.h| 5 + include/drm/drm_mode_config.h | 6 + include/linux/hdmi.h | 55 +++ include/uapi/drm/drm_mode.h | 23 +++ 17 files changed, 598 insertions(+), 7 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 04/13] drm: Enable HDR infoframe support
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Added the const version of infoframe for DRM metadata
for HDR.
v2: Rebase and added Ville's POC changes.
v3: No Change
v4: Addressed Shashank's review comments and merged the
patch making drm infoframe function arguments as constant.
v5: Rebase
v6: Fixed checkpatch warnings with --strict option. Addressed
Shashank's review comments and added his RB.
v7: Addressed Brian Starkey's review comments. Merged 2 patches
into one.
v8: Addressed Jonas Karlman review comments.
Signed-off-by: Uma Shankar
Signed-off-by: Ville Syrjälä
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_edid.c | 48
drivers/video/hdmi.c | 186 +
include/drm/drm_edid.h | 5 ++
include/linux/hdmi.h | 27 +++
4 files changed, 266 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fe2c29b..5f48965 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4906,6 +4906,54 @@ static bool is_hdmi2_sink(struct drm_connector
*connector)
}
/**
+ * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI AVI infoframe with
+ * HDR metadata from userspace
+ * @frame: HDMI AVI infoframe
+ * @hdr_source_metadata: hdr_source_metadata info from userspace
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int
+drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
+ struct hdr_output_metadata *hdr_metadata)
+{
+ int err;
+
+ if (!frame || !hdr_metadata)
+ return true;
+
+ err = hdmi_drm_infoframe_init(frame);
+ if (err < 0)
+ return err;
+
+ DRM_DEBUG_KMS("type = %x\n", frame->type);
+
+ frame->length = sizeof(struct hdr_metadata_infoframe);
+
+ frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
+ frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
+
+ memcpy(>display_primaries,
+ _metadata->hdmi_metadata_type1.display_primaries, 12);
+
+ memcpy(>white_point,
+ _metadata->hdmi_metadata_type1.white_point, 4);
+
+ frame->max_display_mastering_luminance =
+
hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
+ frame->min_display_mastering_luminance =
+
hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
+ frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
+ frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
+
+ hdmi_infoframe_log(KERN_CRIT, NULL,
+ (union hdmi_infoframe *)frame);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
+
+/**
* drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
* data from a DRM display mode
* @frame: HDMI AVI infoframe
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 799ae49..717ed7fb 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -650,6 +650,146 @@ ssize_t hdmi_vendor_infoframe_pack(struct
hdmi_vendor_infoframe *frame,
return 0;
}
+/**
+ * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and
+ * mastering infoframe
+ * @frame: HDMI DRM infoframe
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame)
+{
+ memset(frame, 0, sizeof(*frame));
+
+ frame->type = HDMI_INFOFRAME_TYPE_DRM;
+ frame->version = 1;
+
+ return 0;
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_init);
+
+static int hdmi_drm_infoframe_check_only(const struct hdmi_drm_infoframe
*frame)
+{
+ if (frame->type != HDMI_INFOFRAME_TYPE_DRM ||
+ frame->version != 1)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * hdmi_drm_infoframe_check() - check a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ *
+ * Validates that the infoframe is consistent.
+ * Returns 0 on success or a negative error code on failure.
+ */
+int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame)
+{
+ return hdmi_drm_infoframe_check_only(frame);
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_check);
+
+/**
+ * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer
+ * @frame: HDMI DRM infoframe
+ * @buffer: destination buffer
+ * @size: size of buffer
+ *
+ * Packs the information contained in the @frame structure into a binary
+ * representation that can be written into the corresponding controller
+ * registers. Also computes the checksum as required by section 5.3.5 of
+ * the HDMI
[Intel-gfx] [v9 05/13] drm/i915: Attach HDR metadata property to connector
Attach HDR metadata property to connector object. v2: Rebase v3: Updated the property name as per updated name while creating hdr metadata property Signed-off-by: Uma Shankar Reviewed-by: Shashank Sharma --- drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 2a4086c..92597d8 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2724,6 +2724,8 @@ static void intel_hdmi_destroy(struct drm_connector *connector) drm_connector_attach_content_type_property(connector); connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; + drm_object_attach_property(>base, + connector->dev->mode_config.hdr_output_metadata_property, 0); if (!HAS_GMCH(dev_priv)) drm_connector_attach_max_bpc_property(connector, 8, 12); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 09/13] drm/i915:Enabled Modeset when HDR Infoframe changes
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
v2: Addressed Shashank's review comments.
v3: Added Shashank's RB.
v4: Addressed Ville's review comments.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_atomic.c | 14 +-
drivers/gpu/drm/i915/intel_hdmi.c | 17 +
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 58b8049..6b985e8 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -105,6 +105,16 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
return -EINVAL;
}
+static bool blob_equal(const struct drm_property_blob *a,
+ const struct drm_property_blob *b)
+{
+ if (a && b)
+ return a->length == b->length &&
+ !memcmp(a->data, b->data, a->length);
+
+ return !a == !b;
+}
+
int intel_digital_connector_atomic_check(struct drm_connector *conn,
struct drm_connector_state *new_state)
{
@@ -132,7 +142,9 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
new_conn_state->base.colorspace != old_conn_state->base.colorspace
||
new_conn_state->base.picture_aspect_ratio !=
old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
- new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode)
+ new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode ||
+ !blob_equal(new_conn_state->base.hdr_output_metadata,
+ old_conn_state->base.hdr_output_metadata))
crtc_state->mode_changed = true;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 92bc347..db9c82b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -806,6 +806,11 @@ void intel_read_infoframe(struct intel_encoder *encoder,
return true;
}
+static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
+{
+ return sink_eotf & BIT(output_eotf);
+}
+
static bool
intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -813,11 +818,23 @@ void intel_read_infoframe(struct intel_encoder *encoder,
{
struct hdmi_drm_infoframe *frame = _state->infoframes.drm.drm;
struct hdr_output_metadata *hdr_metadata;
+ struct drm_connector *connector = conn_state->connector;
int ret;
+ if (!conn_state->hdr_output_metadata ||
+ conn_state->hdr_output_metadata->length == 0)
+ return true;
+
hdr_metadata = (struct hdr_output_metadata *)
conn_state->hdr_output_metadata->data;
+ /* Sink EOTF is Bit map while infoframe is absolute values */
+ if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
+ connector->hdr_sink_metadata.hdmi_type1.eotf)) {
+ DRM_ERROR("EOTF Not Supported\n");
+ return true;
+ }
+
ret = drm_hdmi_infoframe_set_hdr_metadata(frame, hdr_metadata);
if (ret < 0) {
DRM_ERROR("couldn't set HDR metadata in infoframe\n");
--
1.9.1
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[Intel-gfx] [v9 07/13] drm: Add HLG EOTF
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve and the upper half
of the signal values use a logarithmic curve.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Addressed Jonas Karlman's review comment and dropped the i915
tag from header.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_edid.c | 3 ++-
include/linux/hdmi.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5f48965..73b33ad 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3857,7 +3857,8 @@ static uint8_t eotf_supported(const u8 *edid_ext)
return edid_ext[2] &
(BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
-BIT(HDMI_EOTF_SMPTE_ST2084));
+BIT(HDMI_EOTF_SMPTE_ST2084) |
+BIT(HDMI_EOTF_BT_2100_HLG));
}
static uint8_t hdr_metadata_type(const u8 *edid_ext)
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 7edafcf..3d7f10f 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -161,6 +161,7 @@ enum hdmi_eotf {
HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
HDMI_EOTF_SMPTE_ST2084,
+ HDMI_EOTF_BT_2100_HLG,
};
struct hdmi_avi_infoframe {
--
1.9.1
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[Intel-gfx] [v9 13/13] drm/i915: Add state readout for DRM infoframe
Added state readout for DRM infoframe and enabled state validation for DRM infoframe. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_ddi.c | 4 drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_hdmi.c| 4 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index d37526b..3a38f32 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3849,6 +3849,10 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_infoframe(encoder, pipe_config, HDMI_INFOFRAME_TYPE_VENDOR, _config->infoframes.hdmi); + if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) + intel_read_infoframe(encoder, pipe_config, +HDMI_INFOFRAME_TYPE_DRM, +_config->infoframes.drm); } static enum intel_output_type diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a351c8e..74b5189 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12231,6 +12231,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv) PIPE_CONF_CHECK_INFOFRAME(avi); PIPE_CONF_CHECK_INFOFRAME(spd); PIPE_CONF_CHECK_INFOFRAME(hdmi); + PIPE_CONF_CHECK_INFOFRAME(drm); #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 224d33e..3886065 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1867,6 +1867,10 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, intel_read_infoframe(encoder, pipe_config, HDMI_INFOFRAME_TYPE_VENDOR, _config->infoframes.hdmi); + if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) + intel_read_infoframe(encoder, pipe_config, +HDMI_INFOFRAME_TYPE_DRM, +_config->infoframes.drm); } static void intel_enable_hdmi_audio(struct intel_encoder *encoder, -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 08/13] drm/i915: Enable infoframes on GLK+ for HDR
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
v3: Addressed Shashank's review comment.
v4: Added Shashank's RB.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 22 +-
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e97c47f..d3f5510 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4694,6 +4694,7 @@ enum {
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
#define DRM_DIP_ENABLE (1 << 28)
+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET(1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
#define VSC_SELECT_SHIFT 25
@@ -8146,6 +8147,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
#define _HSW_VIDEO_DIP_VS_ECC_A0x60280
#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
@@ -8159,6 +8161,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
#define _HSW_VIDEO_DIP_VS_ECC_B0x61280
#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
@@ -8184,6 +8187,7 @@ enum {
#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans,
_GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_ECC(trans, i)_MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 980900b..92bc347 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -152,6 +152,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return VIDEO_DIP_ENABLE_SPD_HSW;
case HDMI_INFOFRAME_TYPE_VENDOR:
return VIDEO_DIP_ENABLE_VS_HSW;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return VIDEO_DIP_ENABLE_DRM_GLK;
default:
MISSING_CASE(type);
return 0;
@@ -177,6 +179,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_VENDOR:
return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
default:
MISSING_CASE(type);
return INVALID_MMIO_REG;
@@ -560,10 +564,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
*encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
+ u32 mask;
- return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
- VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
+ VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ mask |= VIDEO_DIP_ENABLE_DRM_GLK;
+
+ return val & mask;
}
static const u8 infoframe_type_to_idx[] = {
@@ -1182,7 +1192,8 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+VIDEO_DIP_ENABLE_DRM_GLK);
if (!enable) {
I915_WRITE(reg, val);
@@ -1211,7 +1222,8 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
* ToDo: Gen9 also can support HDR with LSPCON.
* Support for the same to be enabled later.
[Intel-gfx] [v9 11/13] drm/i915: Added DRM Infoframe handling for BYT/CHT
BYT/CHT doesn't support DRM Infoframe. This caused a WARN_ON due to a missing CASE while executing intel_hdmi_infoframes_enabled function. This patch fixes the same. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index e559a940..224d33e 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -129,6 +129,8 @@ static u32 g4x_infoframe_enable(unsigned int type) return VIDEO_DIP_ENABLE_SPD; case HDMI_INFOFRAME_TYPE_VENDOR: return VIDEO_DIP_ENABLE_VENDOR; + case HDMI_INFOFRAME_TYPE_DRM: + return 0; default: MISSING_CASE(type); return 0; -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 12/13] video/hdmi: Add Unpack function for DRM infoframe
Added unpack function for DRM infoframe for dynamic
range and mastering infoframe readout.
Suggested-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 54
include/linux/hdmi.h | 1 +
2 files changed, 55 insertions(+)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 717ed7fb..110d405 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1801,6 +1801,57 @@ static int hdmi_audio_infoframe_unpack(struct
hdmi_audio_infoframe *frame,
}
/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_init(frame);
+ if (ret)
+ return ret;
+
+ frame->length = ptr[2];
+ ptr += HDMI_INFOFRAME_HEADER_SIZE;
+
+ frame->eotf = ptr[0] & 0x7;
+ frame->metadata_type = ptr[1] & 0x7;
+
+ memcpy(>display_primaries, [2], 12);
+ memcpy(>white_point, [14], 4);
+
+ frame->max_display_mastering_luminance = (ptr[19] << 8) | ptr[18];
+ frame->min_display_mastering_luminance = (ptr[21] << 8) | ptr[20];
+ frame->max_cll = (ptr[23] << 8) | ptr[22];
+ frame->max_fall = (ptr[25] << 8) | ptr[24];
+
+ return 0;
+}
+
+/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
* @frame: HDMI infoframe
* @buffer: source buffer
@@ -1826,6 +1877,9 @@ int hdmi_infoframe_unpack(union hdmi_infoframe *frame,
case HDMI_INFOFRAME_TYPE_AVI:
ret = hdmi_avi_infoframe_unpack(>avi, buffer, size);
break;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ ret = hdmi_drm_infoframe_unpack(>drm, buffer, size);
+ break;
case HDMI_INFOFRAME_TYPE_SPD:
ret = hdmi_spd_infoframe_unpack(>spd, buffer, size);
break;
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 3d7f10f..ee55ba5 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -56,6 +56,7 @@ enum hdmi_infoframe_type {
#define HDMI_AVI_INFOFRAME_SIZE13
#define HDMI_SPD_INFOFRAME_SIZE25
#define HDMI_AUDIO_INFOFRAME_SIZE 10
+#define HDMI_DRM_INFOFRAME_SIZE26
#define HDMI_INFOFRAME_SIZE(type) \
(HDMI_INFOFRAME_HEADER_SIZE + HDMI_ ## type ## _INFOFRAME_SIZE)
--
1.9.1
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[Intel-gfx] [v9 10/13] drm/i915: Set Infoframe for non modeset case for HDR
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
drivers/gpu/drm/i915/intel_hdmi.c | 7 +--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd5277d..d37526b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3559,6 +3559,10 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *intel_dig_port =
+ enc_to_dig_port(>base);
+
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
@@ -3568,6 +3572,15 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
else if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
intel_hdcp_disable(to_intel_connector(conn_state->connector));
+
+ /* Set the infoframe for NON modeset cases as well */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ conn_state->hdr_metadata_changed)
+ intel_dig_port->set_infoframes(encoder,
+
crtc_state->has_infoframe,
+ crtc_state, conn_state);
+ }
}
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index db9c82b..e559a940 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1204,8 +1204,11 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
u32 val = I915_READ(reg);
- assert_hdmi_transcoder_func_disabled(dev_priv,
-crtc_state->cpu_transcoder);
+ /* DRM Infoframe can be send with transcoder enabled */
+ if (!((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ conn_state->hdr_metadata_changed))
+ assert_hdmi_transcoder_func_disabled(dev_priv,
+
crtc_state->cpu_transcoder);
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
--
1.9.1
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[Intel-gfx] [v9 06/13] drm/i915: Write HDR infoframe and send to panel
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe calculation in compute config.
v6: Addressed Shashank's review comment. Added HDR metadata
support from GEN10 onwards as per Shashank's recommendation.
v7: Addressed Shashank's review comments
v8: Added Shashank's RB.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 48 +++
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 247893e..bc32b2c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -910,6 +910,7 @@ struct intel_crtc_state {
union hdmi_infoframe avi;
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
+ union hdmi_infoframe drm;
} infoframes;
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 92597d8..980900b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -573,6 +573,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
*encoder,
HDMI_INFOFRAME_TYPE_AVI,
HDMI_INFOFRAME_TYPE_SPD,
HDMI_INFOFRAME_TYPE_VENDOR,
+ HDMI_INFOFRAME_TYPE_DRM,
};
u32 intel_hdmi_infoframe_enable(unsigned int type)
@@ -795,6 +796,30 @@ void intel_read_infoframe(struct intel_encoder *encoder,
return true;
}
+static bool
+intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
+struct intel_crtc_state *crtc_state,
+struct drm_connector_state *conn_state)
+{
+ struct hdmi_drm_infoframe *frame = _state->infoframes.drm.drm;
+ struct hdr_output_metadata *hdr_metadata;
+ int ret;
+
+ hdr_metadata = (struct hdr_output_metadata *)
+ conn_state->hdr_output_metadata->data;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(frame, hdr_metadata);
+ if (ret < 0) {
+ DRM_ERROR("couldn't set HDR metadata in infoframe\n");
+ return false;
+ }
+
+ crtc_state->infoframes.enable |=
+ intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
+
+ return true;
+}
+
static void g4x_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
@@ -1180,6 +1205,16 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_write_infoframe(encoder, crtc_state,
HDMI_INFOFRAME_TYPE_VENDOR,
_state->infoframes.hdmi);
+
+ /*
+* Support HDR Metadata from Gen10 onwards
+* ToDo: Gen9 also can support HDR with LSPCON.
+* Support for the same to be enabled later.
+*/
+ if (INTEL_GEN(dev_priv) >= 10)
+ intel_write_infoframe(encoder, crtc_state,
+ HDMI_INFOFRAME_TYPE_DRM,
+ _state->infoframes.drm);
}
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
@@ -2386,6 +2421,19 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
return -EINVAL;
}
+ /*
+* Support HDR Metadata from Gen10 onwards
+* ToDo: Gen9 also can support HDR with LSPCON.
+* Support for the same to be enabled later.
+*/
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config,
+ conn_state)) {
+ DRM_DEBUG_KMS("bad DRM infoframe\n");
+ return -EINVAL;
+ }
+ }
+
return 0;
}
--
1.9.1
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[Intel-gfx] [v9 02/13] drm: Add reference counting on HDR metadata blob
From: Jonas Karlman This adds reference count for HDR metadata blob, handled as part of duplicate and destroy connector state functions. Signed-off-by: Jonas Karlman Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_state_helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index ac929f6..8f49952 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -391,6 +391,10 @@ void drm_atomic_helper_connector_reset(struct drm_connector *connector) drm_connector_get(connector); state->commit = NULL; + if (state->hdr_output_metadata) + drm_property_blob_get(state->hdr_output_metadata); + state->hdr_metadata_changed = false; + /* Don't copy over a writeback job, they are used only once */ state->writeback_job = NULL; } @@ -438,6 +442,8 @@ struct drm_connector_state * if (state->writeback_job) drm_writeback_cleanup_job(state->writeback_job); + + drm_property_blob_put(state->hdr_output_metadata); } EXPORT_SYMBOL(__drm_atomic_helper_connector_destroy_state); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 01/13] drm: Add HDR source metadata property
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
It also implements get() and set() functions for HDR output
metadata property.The blob data is received from userspace and
saved in connector state, the same is returned as blob in get
property call to userspace.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
v3: No Change
v4: Addressed Shashank's review comments
v5: Rebase.
v6: Addressed Brian Starkey's review comments, defined
new structure with header for dynamic metadata scalability.
Merge get/set property functions for metadata in this patch.
v7: Addressed Jonas Karlman review comments and defined separate
structure for infoframe to better align with CTA 861.G spec. Added
Shashank's RB.
v8: Addressed Ville's review comments. Moved sink metadata structure
out of uapi headers as suggested by Jonas Karlman.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_atomic.c | 2 ++
drivers/gpu/drm/drm_atomic_uapi.c | 13 +
drivers/gpu/drm/drm_connector.c | 6 ++
include/drm/drm_connector.h | 11 +++
include/drm/drm_mode_config.h | 6 ++
include/linux/hdmi.h | 26 ++
include/uapi/drm/drm_mode.h | 23 +++
7 files changed, 87 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5eb4013..8b9c126 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -881,6 +881,8 @@ static void drm_atomic_connector_print_state(struct
drm_printer *p,
drm_printf(p, "connector[%u]: %s\n", connector->base.id,
connector->name);
drm_printf(p, "\tcrtc=%s\n", state->crtc ? state->crtc->name :
"(null)");
+ drm_printf(p, "\thdr_metadata_changed=%d\n",
+ state->hdr_metadata_changed);
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
if (state->writeback_job && state->writeback_job->fb)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 428d826..2ecc79e 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -676,6 +676,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
{
struct drm_device *dev = connector->dev;
struct drm_mode_config *config = >mode_config;
+ bool replaced = false;
+ int ret;
if (property == config->prop_crtc_id) {
struct drm_crtc *crtc = drm_crtc_find(dev, file_priv, val);
@@ -726,6 +728,14 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*/
if (state->link_status != DRM_LINK_STATUS_GOOD)
state->link_status = val;
+ } else if (property == config->hdr_output_metadata_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >hdr_output_metadata,
+ val,
+ -1, sizeof(struct hdr_output_metadata),
+ );
+ state->hdr_metadata_changed |= replaced;
+ return ret;
} else if (property == config->aspect_ratio_property) {
state->picture_aspect_ratio = val;
} else if (property == config->content_type_property) {
@@ -814,6 +824,9 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*val = state->colorspace;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
+ } else if (property == config->hdr_output_metadata_property) {
+ *val = state->hdr_output_metadata ?
+ state->hdr_output_metadata->base.id : 0;
} else if (property == connector->content_protection_property) {
*val = state->content_protection;
} else if (property == config->writeback_fb_id_property) {
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index b34c3d3..365ace0 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1058,6 +1058,12 @@ int drm_connector_create_standard_properties(struct
drm_device *dev)
return -ENOMEM;
dev->mode_config.non_desktop_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "HDR_OUTPUT_METADATA", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.hdr_output_metadata_property = prop;
+
return 0;
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index f43f40d..e54674b 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -603,6 +603,13 @@ struct drm_connector_state {
* and
[Intel-gfx] [v9 03/13] drm: Parse HDR metadata info from EDID
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
v5: Addressed Shashank's comment and added his RB.
v6: Addressed Jonas Karlman review comments.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_edid.c | 52 ++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 852bdd8..fe2c29b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2852,6 +2852,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
#define VIDEO_BLOCK 0x02
#define VENDOR_BLOCK0x03
#define SPEAKER_BLOCK 0x04
+#define HDR_STATIC_METADATA_BLOCK 0x6
#define USE_EXTENDED_TAG 0x07
#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
#define EXT_VIDEO_DATA_BLOCK_420 0x0E
@@ -3599,6 +3600,12 @@ static int add_3d_struct_modes(struct drm_connector
*connector, u16 structure,
}
static int
+cea_db_payload_len_ext(const u8 *db)
+{
+ return (db[0] & 0x1f) - 1;
+}
+
+static int
cea_db_extended_tag(const u8 *db)
{
return db[1];
@@ -3834,6 +3841,49 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
+{
+ if (cea_db_tag(db) != USE_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != HDR_STATIC_METADATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static uint8_t eotf_supported(const u8 *edid_ext)
+{
+ return edid_ext[2] &
+ (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
+BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
+BIT(HDMI_EOTF_SMPTE_ST2084));
+}
+
+static uint8_t hdr_metadata_type(const u8 *edid_ext)
+{
+ return edid_ext[3] &
+ BIT(HDMI_STATIC_METADATA_TYPE1);
+}
+
+static void
+drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
+{
+ u16 len;
+
+ len = cea_db_payload_len_ext(db);
+ connector->hdr_sink_metadata.hdmi_type1.eotf = eotf_supported(db);
+ connector->hdr_sink_metadata.hdmi_type1.metadata_type =
+ hdr_metadata_type(db);
+
+ if (len >= 4)
+ connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
+ if (len >= 5)
+ connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
+ if (len >= 6)
+ connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
+}
+
static void
drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
{
@@ -4461,6 +4511,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_y420cmdb_bitmap(connector, db);
if (cea_db_is_vcdb(db))
drm_parse_vcdb(connector, db);
+ if (cea_db_is_hdmi_hdr_metadata_block(db))
+ drm_parse_hdr_metadata_block(connector, db);
}
}
--
1.9.1
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Re: [Intel-gfx] [PATCH v6 5/6] drm/i915/dp: Change a link bandwidth computation for DP
On Wed, May 08, 2019 at 11:17:56AM +0300, Gwan-gyeong Mun wrote:
> Data M/N calculations were assumed a bpp as RGB format. But when we are
> using YCbCr 4:2:0 output format on DP, we should change bpp calculations
> as YCbCr 4:2:0 format. The pipe_bpp value was assumed RGB format,
> therefore, it was multiplied with 3. But YCbCr 4:2:0 requires a multiplier
> value to 1.5.
> Therefore we need to divide pipe_bpp to 2 while DP output uses YCbCr4:2:0
> format.
> - RGB format bpp = bpc x 3
> - YCbCr 4:2:0 format bpp = bpc x 1.5
>
> But Link M/N values are calculated and applied based on the Full Clock for
> YCbCr 4:2:0. And DP YCbCr 4:2:0 does not need to pixel clock double for
> a dotclock caluation. Only for HDMI YCbCr 4:2:0 needs to pixel clock double
> for a dot clock calculation.
>
> And it adds missed bpc values for a programming of VSC Header.
> It only affects dp and edp port which use YCbCr 4:2:0 output format.
> And for now, it does not consider a use case of DSC + YCbCr 4:2:0.
>
> v2:
> Addressed review comments from Ville.
> Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings().
> Because the pipe is running at the full bpp, keep pipe_bpp as RGB
> even though YCbCr 4:2:0 output format is used.
> Add a link bandwidth computation for YCbCr4:2:0 output format.
>
> v3:
> Addressed reivew comments from Ville.
> In order to make codes simple, it adds and uses intel_dp_output_bpp()
> function.
>
> v6:
> Link M/N values are calculated and applied based on the Full Clock for
> YCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode as it
> requires only half of the RGB case.
> - Link M/N values are calculated and applied based on the Full Clock
> - Data M/N values needs to be calculated considering the data is half
> due to subsampling
> Remove a doubling of pixel clock on a dot clock calculator for
> DP YCbCr 4:2:0.
> Rebase and remove a duplicate setting of vsc_sdp.DB17.
> Add a setting of dynamic range bit to vsc_sdp.DB17.
> Change Content Type bit to "Graphics" from "Not defined".
> Change a dividing of pipe_bpp to muliplying to constant values on a
> switch-case statement.
>
> Cc: Ville Syrjälä
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> drivers/gpu/drm/i915/intel_dp.c | 42 +---
> 2 files changed, 41 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 4441c5ba71fb..e22a0898b957 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1457,7 +1457,8 @@ static void ddi_dotclock_get(struct intel_crtc_state
> *pipe_config)
> else
> dotclock = pipe_config->port_clock;
>
> - if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> + !intel_crtc_has_dp_encoder(pipe_config))
> dotclock *= 2;
>
> if (pipe_config->pixel_multiplier)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 74aad8830a80..c75e2bbe612a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1842,6 +1842,19 @@ intel_dp_adjust_compliance_config(struct intel_dp
> *intel_dp,
> }
> }
>
> +static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state,
> int bpp)
> +{
> + /*
> + * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> + * format of the number of bytes per pixel will be half the number
> + * of bytes of RGB pixel.
> + */
> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + bpp /= 2;
> +
> + return bpp;
> +}
> +
> /* Optimize link config in order: max bpp, min clock, min lanes */
> static int
> intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> @@ -2212,7 +2225,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (pipe_config->dsc_params.compression_enable)
> output_bpp = pipe_config->dsc_params.compressed_bpp;
> else
> - output_bpp = pipe_config->pipe_bpp;
> + output_bpp = intel_dp_output_bpp(pipe_config,
> pipe_config->pipe_bpp);
>
> intel_link_compute_m_n(output_bpp,
> pipe_config->lane_count,
> @@ -4439,7 +4452,30 @@ intel_pixel_encoding_setup_vsc(struct intel_dp
> *intel_dp,
>* 011b = 12bpc.
>* 100b = 16bpc.
>*/
> - vsc_sdp.DB17 = 0x1;
> + switch (crtc_state->pipe_bpp) {
> + case 24: /* 8bpc */
> + vsc_sdp.DB17 = 0x1;
> + break;
> + case 30: /* 10bpc */
> + vsc_sdp.DB17 = 0x2;
> + break;
> + case 36: /* 12bpc */
> + vsc_sdp.DB17 = 0x3;
> + break;
> + case 48: /* 16bpc */
> + vsc_sdp.DB17 = 0x4;
> + break;
> +
Re: [Intel-gfx] [PATCH v6 3/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
On Wed, May 08, 2019 at 11:17:54AM +0300, Gwan-gyeong Mun wrote:
> Function intel_pixel_encoding_setup_vsc handles vsc header and data block
> setup for pixel encoding / colorimetry format.
>
> Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
> for pixel encoding / colorimetry format as per dp 1.4a spec,
> section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
> table 2-120:VSC SDP Payload for DB16 through DB18.
>
> v2:
> Minor style fix. [Maarten]
> Refer to commit ids instead of patchwork. [Maarten]
>
> v6: Rebase
>
> Cc: Maarten Lankhorst
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 73
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 76 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index cd5277d98b03..2f1688ea5a2c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3391,6 +3391,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
>
> intel_edp_backlight_on(crtc_state, conn_state);
> intel_psr_enable(intel_dp, crtc_state);
> + intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
I wonder if this is a bit too late. But we do it for PSR here, so I
guess we should think about this for both cases. We should actually
add full readout + state checker for the VSC SDP for both cases as
well. But that can be done later.
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> if (crtc_state->has_audio)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 06a3417a88d1..74aad8830a80 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4394,6 +4394,79 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp
> *intel_dp,
> return 0;
> }
>
> +static void
> +intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
> +const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct dp_vsc_sdp vsc_sdp;
> +
> + if (!intel_dp->attached_connector->base.ycbcr_420_allowed)
> + return;
> +
> + /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
> + memset(_sdp, 0, sizeof(vsc_sdp));
Can be replaced with '= {}' in the declaration.
> + vsc_sdp.sdp_header.HB0 = 0;
> + vsc_sdp.sdp_header.HB1 = 0x7;
> +
> + /* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> + * Colorimetry Format indication. A DP Source device is allowed
> + * to indicate the pixel encoding/colorimetry format to the DP Sink
> + * device with VSC SDP only when the DP Sink device supports it
> + * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
> register
> + * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3) is set to
> 1)
> + */
Are we checking that bit somewhere? I suppose the sink might a bit nuts
if it declares 420_only modes without that set, but maybe it should be
checked anyway.
Also non-standard comment format all over. Should be
/*
* blah
*/
> + vsc_sdp.sdp_header.HB2 = 0x5;
> +
> + /* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> + * Colorimetry Format indication (HB2 = 05h).
> + */
> + vsc_sdp.sdp_header.HB3 = 0x13;
> + /* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
> + * DB16[3:0] DP 1.4a spec, Table 2-120
> + */
> +
> + /* Commit id (25edf91501b8 "drm/i915: prepare csc unit for YCBCR420
> output")
> + * uses the BT.709 color space to perform RGB->YCBCR conversion.
> + */
I don't think referring to specific commit here is particularly helpful.
The situation will change anyway at some point.
> + vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
> + vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
> +
> + /* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
> + * the following Component Bit Depth values are defined:
> + * 001b = 8bpc.
> + * 010b = 10bpc.
> + * 011b = 12bpc.
> + * 100b = 16bpc.
> + */
> + vsc_sdp.DB17 = 0x1;
Don't we need to base this on pipe_bpp?
And I'm thinking we want the CEA bit set here as well.
> +
> + /*
> + * Content Type (Bits 2:0)
> + * 000b = Not defined.
> + * 001b = Graphics.
> + * 010b = Photo.
> + * 011b = Video.
> + * 100b = Game
> + * All other values are RESERVED.
> + * Note: See CTA-861-G for the definition and expected
> + * processing by a stream sink for the above contect types.
> + */
> + vsc_sdp.DB18 = 0;
Hmm. I guess we could add the content type prop for DP too.
But that's something for the future.
All the magic numbers should be defined somewhere in the core dp header.
But that could be done
Re: [Intel-gfx] [PATCH v6 2/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
On Wed, May 08, 2019 at 11:17:53AM +0300, Gwan-gyeong Mun wrote:
> SDP VSC Header and Data Block follow DP 1.4a spec, section 2.2.5.7.5,
> chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".
>
> Signed-off-by: Gwan-gyeong Mun
> Reviewed-by: Maarten Lankhorst
> ---
> include/drm/drm_dp_helper.h | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 97ce790a5b5a..3793bea7b7fe 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1096,6 +1096,23 @@ struct edp_vsc_psr {
> u8 DB8_31[24]; /* Reserved */
> } __packed;
>
> +struct dp_vsc_sdp {
> + struct dp_sdp_header sdp_header;
> + u8 DB0; /* Stereo Interface */
> + u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
> + u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
> + u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
> + u8 DB4; /* CRC value bits 7:0 of the G or Y component */
> + u8 DB5; /* CRC value bits 15:8 of the G or Y component */
> + u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
> + u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
> + u8 DB8_15[8]; /* Reserved */
> + u8 DB16; /* Pixel Encoding and Colorimetry Formats */
> + u8 DB17; /* Dynamic Range and Component Bit Depth */
> + u8 DB18; /* Content Type */
> + u8 DB19_31[13]; /* Reserved */
> +} __packed;
Isn't this the same thing we have for edp already? Just rename the edp
struct and add the missing stuff?
> +
> #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
> #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
> #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
> --
> 2.21.0
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix skl plane scaling for planner YUV buffers
== Series Details == Series: drm/i915: Fix skl plane scaling for planner YUV buffers URL : https://patchwork.freedesktop.org/series/60414/ State : success == Summary == CI Bug Log - changes from CI_DRM_6063_full -> Patchwork_12987_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12987_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl1/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-apl6/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([fdo#108686]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk1/igt@gem_tiled_swapp...@non-threaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107773]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl2/igt@i915_pm_backlight@fade_with_suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-skl7/igt@i915_pm_backlight@fade_with_suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [fdo#110403]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103166]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-x.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format: - shard-glk: [PASS][13] -> [SKIP][14] ([fdo#109271] / [fdo#109278]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk9/igt@kms_plane_scal...@pipe-a-scaler-with-pixel-format.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-glk4/igt@kms_plane_scal...@pipe-a-scaler-with-pixel-format.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-iclb7/igt@kms_psr@psr2_sprite_blt.html Possible fixes * igt@gem_ctx_isolation@vecs0-s3: - shard-kbl: [DMESG-WARN][17] ([fdo#108566]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-kbl1/igt@gem_ctx_isolat...@vecs0-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-kbl1/igt@gem_ctx_isolat...@vecs0-s3.html * igt@i915_pm_rpm@sysfs-read: - shard-skl: [INCOMPLETE][19] ([fdo#107807]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl1/igt@i915_pm_...@sysfs-read.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-skl2/igt@i915_pm_...@sysfs-read.html * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl4/igt@i915_susp...@sysfs-reader.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-apl2/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@cursor-64x21-onscreen: - shard-apl: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24] +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl4/igt@kms_cursor_...@cursor-64x21-onscreen.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/shard-apl5/igt@kms_cursor_...@cursor-64x21-onscreen.html * igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge:
[Intel-gfx] [PATCH v4 04/11] drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state
From: Sean Paul
Everyone who implements connector_helper_funcs->atomic_check reaches
into the connector state to get the atomic state. Instead of continuing
this pattern, change the callback signature to just give atomic state
and let the driver determine what it does and does not need from it.
Eventually all atomic functions should do this, but that's just too much
busy work for me.
Changes in v3:
- Added to the set
Changes in v4:
- None
Link to v3:
https://patchwork.freedesktop.org/patch/msgid/20190502194956.218441-5-s...@poorly.run
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Ben Skeggs
Cc: Laurent Pinchart
Cc: Kieran Bingham
Cc: Eric Anholt
Acked-by: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/drm_atomic_helper.c | 4 ++--
drivers/gpu/drm/i915/intel_atomic.c | 8 +---
drivers/gpu/drm/i915/intel_dp_mst.c | 7 ---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sdvo.c| 9 +
drivers/gpu/drm/i915/intel_tv.c | 8 +---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++--
drivers/gpu/drm/rcar-du/rcar_lvds.c | 12 +++-
drivers/gpu/drm/vc4/vc4_txp.c| 7 ---
include/drm/drm_modeset_helper_vtables.h | 2 +-
10 files changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index e8b7187a8494..ee945d6f1cba 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -683,7 +683,7 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
}
if (funcs->atomic_check)
- ret = funcs->atomic_check(connector,
new_connector_state);
+ ret = funcs->atomic_check(connector, state);
if (ret)
return ret;
@@ -725,7 +725,7 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
continue;
if (funcs->atomic_check)
- ret = funcs->atomic_check(connector,
new_connector_state);
+ ret = funcs->atomic_check(connector, state);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index b844e8840c6f..e8a5b82e9242 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -103,12 +103,14 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
}
int intel_digital_connector_atomic_check(struct drm_connector *conn,
-struct drm_connector_state *new_state)
+struct drm_atomic_state *state)
{
+ struct drm_connector_state *new_state =
+ drm_atomic_get_new_connector_state(state, conn);
struct intel_digital_connector_state *new_conn_state =
to_intel_digital_connector_state(new_state);
struct drm_connector_state *old_state =
- drm_atomic_get_old_connector_state(new_state->state, conn);
+ drm_atomic_get_old_connector_state(state, conn);
struct intel_digital_connector_state *old_conn_state =
to_intel_digital_connector_state(old_state);
struct drm_crtc_state *crtc_state;
@@ -118,7 +120,7 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
if (!new_state->crtc)
return 0;
- crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
new_state->crtc);
+ crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
/*
* These properties are handled by fastset, and might not end
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 19d81cef2ab6..89cfec128ba0 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -143,9 +143,10 @@ static int intel_dp_mst_compute_config(struct
intel_encoder *encoder,
static int
intel_dp_mst_atomic_check(struct drm_connector *connector,
- struct drm_connector_state *new_conn_state)
+ struct drm_atomic_state *state)
{
- struct drm_atomic_state *state = new_conn_state->state;
+ struct drm_connector_state *new_conn_state =
+ drm_atomic_get_new_connector_state(state, connector);
struct drm_connector_state *old_conn_state =
drm_atomic_get_old_connector_state(state, connector);
struct intel_connector *intel_connector =
@@ -155,7 +156,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
struct drm_dp_mst_topology_mgr *mgr;
int ret;
- ret = intel_digital_connector_atomic_check(connector, new_conn_state);
+ ret =
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reboot CI if forcewake fails
== Series Details == Series: drm/i915: Reboot CI if forcewake fails URL : https://patchwork.freedesktop.org/series/60412/ State : success == Summary == CI Bug Log - changes from CI_DRM_6063_full -> Patchwork_12986_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12986_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-snb6/igt@gem_...@reset-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-snb4/igt@gem_...@reset-stress.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl7/igt@gem_workarou...@suspend-resume.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-apl5/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107773] / [fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl5/igt@i915_pm_...@system-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-skl3/igt@i915_pm_...@system-suspend.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-glk: [PASS][7] -> [SKIP][8] ([fdo#109271]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk1/igt@i915_pm_...@system-suspend-execbuf.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-glk3/igt@i915_pm_...@system-suspend-execbuf.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-glk9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format: - shard-glk: [PASS][17] -> [SKIP][18] ([fdo#109271] / [fdo#109278]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk9/igt@kms_plane_scal...@pipe-a-scaler-with-pixel-format.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-glk8/igt@kms_plane_scal...@pipe-a-scaler-with-pixel-format.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-iclb4/igt@kms_psr@psr2_sprite_blt.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-glk: [PASS][21] -> [INCOMPLETE][22] ([fdo#103359] / [k.org#198133]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk8/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/shard-glk3/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html Possible fixes * igt@gem_ctx_isolation@vecs0-s3: - shard-kbl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-kbl1/igt@gem_ctx_isolat...@vecs0-s3.html [24]:
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 16/21] gem_wsim: Some more example workloads
On 08/05/2019 14:56, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-05-08 14:50:41) On 08/05/2019 13:27, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-05-08 13:10:53) From: Tvrtko Ursulin A few additional workloads useful for experimenting with scheduling. Signed-off-by: Tvrtko Ursulin Are the extra modes & .wsim supported by scripts/media-bench.pl? i.e. can I just run media-bench.pl and have it exercise all the new features? Not sure what you mean by extra modes? If all new wsim commands then no. They are not in the default media-bench.pl set. The workloads from this patch are not in that set so are just for reference. That's what I meant, are the new example.wsim with explicit engine maps and so I presume inter-mixing of load-balanced workloads with other work included in the default set run by ./scripts/media-bench.pl It's not in the default set but manual workloads can be given to media-bench.pl using the -w switch. String passed there is passed onto gem_wsim directly so one or more workloads can be manually specified. What's the minimum amount of effort I need to exercise all the new features of gem_wsim? :) frame-split-60fps.wsim uses almost all new features: preemption control, engine map, load balance, bond, submit fence and the "endless" batch. Only missing is SSEU control for which I did not add an example workload (there is a snippet in README though) since the access to uapi is blocked outside the gen11 special case. To use that the i915 IS_GEN11 check in set_sseu needs to be lifted as well. Virtual engine (gem_wsim -b i915) is supported by media-bench.pl even with the old/default set of workloads. The catch is old wsim workloads use VCS to mean any VCS and in those cases -b i915 will set up the virtual engine automatically/transparently. So those old workloads can be ran both with userspace or i915 balancing. And seems to still be working. I'd hope so, I mostly do test things! :) Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
Quoting Mika Kuoppala (2019-05-08 15:00:11) > Chris Wilson writes: > > > Quoting Mika Kuoppala (2019-05-08 13:30:46) > >> Chris Wilson writes: > >> > >> > After realising we need to sample RING_START to detect context switches > >> > from preemption events that do not allow for the seqno to advance, we > >> > can also realise that the seqno itself is just a distance along the ring > >> > and so can be replaced by sampling RING_HEAD. > >> > > >> > Signed-off-by: Chris Wilson > >> > Cc: Mika Kuoppala > >> > --- > >> > static enum intel_engine_hangcheck_action > >> > @@ -156,7 +156,7 @@ hangcheck_get_action(struct intel_engine_cs *engine, > >> > if (engine->hangcheck.last_ring != hc->ring) > >> > return ENGINE_ACTIVE_SEQNO; > >> > > >> > - if (engine->hangcheck.last_seqno != hc->seqno) > >> > + if (engine->hangcheck.last_head != hc->head) > >> > return ENGINE_ACTIVE_SEQNO; > >> > >> Change the enum also? > > > > Pffifle. As far as hangcheck goes RING_START:RING_HEAD comprise its > > seqno. > > > > Makes for a good talking point in a few years time :) > > Fair enough. > > > > >> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > >> > b/drivers/gpu/drm/i915/gt/intel_lrc.c > >> > index d1a54d2c3d5d..f1d62746e066 100644 > >> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > >> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > >> > @@ -2275,12 +2275,6 @@ static u32 *gen8_emit_fini_breadcrumb(struct > >> > i915_request *request, u32 *cs) > >> > request->timeline->hwsp_offset, > >> > 0); > >> > > >> > - cs = gen8_emit_ggtt_write(cs, > >> > - > >> > intel_engine_next_hangcheck_seqno(request->engine), > >> > - I915_GEM_HWS_HANGCHECK_ADDR, > >> > - MI_FLUSH_DW_STORE_INDEX); > >> > - > >> > - > >> > *cs++ = MI_USER_INTERRUPT; > >> > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; > >> > > >> > @@ -2297,14 +2291,11 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct > >> > i915_request *request, u32 *cs) > >> > request->timeline->hwsp_offset, > >> > > >> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > >> > PIPE_CONTROL_DEPTH_CACHE_FLUSH | > >> > - PIPE_CONTROL_DC_FLUSH_ENABLE | > >> > - PIPE_CONTROL_FLUSH_ENABLE | > >> > - PIPE_CONTROL_CS_STALL); > >> > >> ??? > > > > Kabylake sends the interrupt too early otherwise. The hangcheck write > > saved us by pure accident. > > I read the diff wrong at first try also, was concerned that we lost cs stall. > Regardless this could benefit from a comment explaining the need to > force sync for the intr. Indeed, that is sensible since it's an empirical result and worth validating again later. Done and pushed, thanks. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
Chris Wilson writes: > Quoting Mika Kuoppala (2019-05-08 13:30:46) >> Chris Wilson writes: >> >> > After realising we need to sample RING_START to detect context switches >> > from preemption events that do not allow for the seqno to advance, we >> > can also realise that the seqno itself is just a distance along the ring >> > and so can be replaced by sampling RING_HEAD. >> > >> > Signed-off-by: Chris Wilson >> > Cc: Mika Kuoppala >> > --- >> > static enum intel_engine_hangcheck_action >> > @@ -156,7 +156,7 @@ hangcheck_get_action(struct intel_engine_cs *engine, >> > if (engine->hangcheck.last_ring != hc->ring) >> > return ENGINE_ACTIVE_SEQNO; >> > >> > - if (engine->hangcheck.last_seqno != hc->seqno) >> > + if (engine->hangcheck.last_head != hc->head) >> > return ENGINE_ACTIVE_SEQNO; >> >> Change the enum also? > > Pffifle. As far as hangcheck goes RING_START:RING_HEAD comprise its > seqno. > > Makes for a good talking point in a few years time :) Fair enough. > >> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c >> > b/drivers/gpu/drm/i915/gt/intel_lrc.c >> > index d1a54d2c3d5d..f1d62746e066 100644 >> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >> > @@ -2275,12 +2275,6 @@ static u32 *gen8_emit_fini_breadcrumb(struct >> > i915_request *request, u32 *cs) >> > request->timeline->hwsp_offset, >> > 0); >> > >> > - cs = gen8_emit_ggtt_write(cs, >> > - >> > intel_engine_next_hangcheck_seqno(request->engine), >> > - I915_GEM_HWS_HANGCHECK_ADDR, >> > - MI_FLUSH_DW_STORE_INDEX); >> > - >> > - >> > *cs++ = MI_USER_INTERRUPT; >> > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; >> > >> > @@ -2297,14 +2291,11 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct >> > i915_request *request, u32 *cs) >> > request->timeline->hwsp_offset, >> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH >> > | >> > PIPE_CONTROL_DEPTH_CACHE_FLUSH | >> > - PIPE_CONTROL_DC_FLUSH_ENABLE | >> > - PIPE_CONTROL_FLUSH_ENABLE | >> > - PIPE_CONTROL_CS_STALL); >> >> ??? > > Kabylake sends the interrupt too early otherwise. The hangcheck write > saved us by pure accident. I read the diff wrong at first try also, was concerned that we lost cs stall. Regardless this could benefit from a comment explaining the need to force sync for the intr. Was happy to see measure_breadcrumb_dw() paying off. Also leaning to it for alignment forcing. Reviewed-by: Mika Kuoppala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 16/21] gem_wsim: Some more example workloads
Quoting Tvrtko Ursulin (2019-05-08 14:50:41) > > On 08/05/2019 13:27, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-05-08 13:10:53) > >> From: Tvrtko Ursulin > >> > >> A few additional workloads useful for experimenting with scheduling. > >> > >> Signed-off-by: Tvrtko Ursulin > > > > Are the extra modes & .wsim supported by scripts/media-bench.pl? > > i.e. can I just run media-bench.pl and have it exercise all the new > > features? > > Not sure what you mean by extra modes? If all new wsim commands then no. > They are not in the default media-bench.pl set. The workloads from this > patch are not in that set so are just for reference. That's what I meant, are the new example.wsim with explicit engine maps and so I presume inter-mixing of load-balanced workloads with other work included in the default set run by ./scripts/media-bench.pl What's the minimum amount of effort I need to exercise all the new features of gem_wsim? :) > Virtual engine (gem_wsim -b i915) is supported by media-bench.pl even > with the old/default set of workloads. > > The catch is old wsim workloads use VCS to mean any VCS and in those > cases -b i915 will set up the virtual engine > automatically/transparently. So those old workloads can be ran both with > userspace or i915 balancing. And seems to still be working. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix skl plane scaling for planner YUV buffers
On Wed, May 08, 2019 at 05:34:37PM +0530, Shashank Sharma wrote:
> From: Lukas Rusak
>
> Plane scaling for YUV planar formats should be max 2 times.
Nope. Spec says it should be < 2.0 on pre-glk, and < 3.0 on glk+.
>
> Cc: Maarten Lankhorst
> Cc: Juha-pekka Heikkila
> Cc: Shashank Sharma
>
> Signed-off-by: Lukas Rusak
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 -
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a351c8e219ba..2ac0a55a9c9f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13897,7 +13897,7 @@ skl_max_scale(const struct intel_crtc_state
> *crtc_state,
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int max_scale, mult;
> + int max_scale, mult, remainder;
> int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
>
> if (!crtc_state->base.enable)
> @@ -13914,12 +13914,15 @@ skl_max_scale(const struct intel_crtc_state
> *crtc_state,
>
> /*
>* skl max scale is lower of:
> - *close to 3 but not 3, -1 is for that purpose
> - *or
> - *cdclk/crtc_clock
> + * for planar YUV formats: 2
> + * or
> + * for other formats: close to 3 but not 3, -1 is for that purpose
> + * or
> + * cdclk/crtc_clock
>*/
> mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
> - tmpclk1 = (1 << 16) * mult - 1;
> + remainder = is_planar_yuv_format(pixel_format) ? 0 : 1;
> + tmpclk1 = (1 << 16) * mult - remainder;
> tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> max_scale = min(tmpclk1, tmpclk2);
>
> --
> 2.17.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Intel
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 16/21] gem_wsim: Some more example workloads
On 08/05/2019 13:27, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-05-08 13:10:53) From: Tvrtko Ursulin A few additional workloads useful for experimenting with scheduling. Signed-off-by: Tvrtko Ursulin Are the extra modes & .wsim supported by scripts/media-bench.pl? i.e. can I just run media-bench.pl and have it exercise all the new features? Not sure what you mean by extra modes? If all new wsim commands then no. They are not in the default media-bench.pl set. The workloads from this patch are not in that set so are just for reference. Virtual engine (gem_wsim -b i915) is supported by media-bench.pl even with the old/default set of workloads. The catch is old wsim workloads use VCS to mean any VCS and in those cases -b i915 will set up the virtual engine automatically/transparently. So those old workloads can be ran both with userspace or i915 balancing. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32
>-Original Message-
>From: Sharma, Shashank
>Sent: Tuesday, May 7, 2019 7:27 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Sharma, Shashank ; Ville Syrjälä
>; Maarten Lankhorst
>; Shankar, Uma
>Subject: [PATCH v3 1/4] drm/i915: Change gamma/degamma_lut_size data type to
>u32
>
>Currently, data type of gamma_lut_size & degamma_lut_size elements in
>intel_device_info is u16, which means it can accommodate maximum 64k values. In
>case of ICL multisegmented gamma, the size of gamma LUT is 256K.
>
>This patch changes the data type of both of these elements to u32.
Looks ok to me.
Reviewed-by: Uma Shankar
>Cc: Ville Syrjälä
>Cc: Maarten Lankhorst
>Cc: Uma Shankar
>
>Signed-off-by: Shashank Sharma
>---
> drivers/gpu/drm/i915/intel_device_info.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h
>b/drivers/gpu/drm/i915/intel_device_info.h
>index 5a2e17d6146b..67677c356716 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -179,8 +179,8 @@ struct intel_device_info {
> int cursor_offsets[I915_MAX_PIPES];
>
> struct color_luts {
>- u16 degamma_lut_size;
>- u16 gamma_lut_size;
>+ u32 degamma_lut_size;
>+ u32 gamma_lut_size;
> u32 degamma_lut_tests;
> u32 gamma_lut_tests;
> } color;
>--
>2.17.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix skl plane scaling for planner YUV buffers
== Series Details ==
Series: drm/i915: Fix skl plane scaling for planner YUV buffers
URL : https://patchwork.freedesktop.org/series/60414/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12987
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/
Known issues
Here are the changes found in Patchwork_12987 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_exec_basic@readonly-render:
- {fi-icl-y}: [INCOMPLETE][1] ([fdo#107713]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
Warnings
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: [INCOMPLETE][3] ([fdo#103927]) -> [DMESG-FAIL][4]
([fdo#110620])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
* igt@runner@aborted:
- fi-apl-guc: [FAIL][5] ([fdo#110624]) -> [FAIL][6] ([fdo#110622])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/fi-apl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620
[fdo#110622]: https://bugs.freedesktop.org/show_bug.cgi?id=110622
[fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624
Participating hosts (53 -> 43)
--
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6063 -> Patchwork_12987
CI_DRM_6063: 44ae4003d35743cbc7883825c5fe777d136b5247 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12987: 9d192441ea8a923c733c1130ff274994c9164aa2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9d192441ea8a drm/i915: Fix skl plane scaling for planner YUV buffers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12987/
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Re: [Intel-gfx] [PATCH 03/16] lib, treewide: add new match_string() helper/macro
On Wed, May 08, 2019 at 04:11:28PM +0300, Andy Shevchenko wrote: > On Wed, May 08, 2019 at 02:28:29PM +0300, Alexandru Ardelean wrote: > > This change re-introduces `match_string()` as a macro that uses > > ARRAY_SIZE() to compute the size of the array. > > The macro is added in all the places that do > > `match_string(_a, ARRAY_SIZE(_a), s)`, since the change is pretty > > straightforward. > > Can you split include/linux/ change from the rest? That would break the build, why do you want it split out? This makes sense all as a single patch to me. thanks, greg k-h ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/16] lib, treewide: add new match_string() helper/macro
On Wed, May 08, 2019 at 02:28:29PM +0300, Alexandru Ardelean wrote:
> This change re-introduces `match_string()` as a macro that uses
> ARRAY_SIZE() to compute the size of the array.
> The macro is added in all the places that do
> `match_string(_a, ARRAY_SIZE(_a), s)`, since the change is pretty
> straightforward.
Can you split include/linux/ change from the rest?
>
> Signed-off-by: Alexandru Ardelean
> ---
> drivers/clk/bcm/clk-bcm2835.c| 4 +---
> drivers/gpio/gpiolib-of.c| 2 +-
> drivers/gpu/drm/i915/intel_pipe_crc.c| 2 +-
> drivers/mfd/omap-usb-host.c | 2 +-
> drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c | 2 +-
> drivers/pci/pcie/aer.c | 2 +-
> drivers/usb/common/common.c | 4 ++--
> drivers/usb/typec/class.c| 8 +++-
> drivers/usb/typec/tps6598x.c | 2 +-
> drivers/vfio/vfio.c | 4 +---
> include/linux/string.h | 9 +
> sound/firewire/oxfw/oxfw.c | 2 +-
> sound/soc/codecs/max98088.c | 2 +-
> sound/soc/codecs/max98095.c | 2 +-
> 14 files changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index a775f6a1f717..1ab388590ead 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1390,9 +1390,7 @@ static struct clk_hw *bcm2835_register_clock(struct
> bcm2835_cprman *cprman,
> for (i = 0; i < data->num_mux_parents; i++) {
> parents[i] = data->parents[i];
>
> - ret = __match_string(cprman_parent_names,
> - ARRAY_SIZE(cprman_parent_names),
> - parents[i]);
> + ret = match_string(cprman_parent_names, parents[i]);
> if (ret >= 0)
> parents[i] = cprman->real_parent_names[ret];
> }
> diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
> index 27d6f04ab58e..71e886869d78 100644
> --- a/drivers/gpio/gpiolib-of.c
> +++ b/drivers/gpio/gpiolib-of.c
> @@ -279,7 +279,7 @@ static struct gpio_desc *of_find_regulator_gpio(struct
> device *dev, const char *
> if (!con_id)
> return ERR_PTR(-ENOENT);
>
> - i = __match_string(whitelist, ARRAY_SIZE(whitelist), con_id);
> + i = match_string(whitelist, con_id);
> if (i < 0)
> return ERR_PTR(-ENOENT);
>
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index 286fad1f0e08..6fc4f3d3d1f6 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -449,7 +449,7 @@ display_crc_ctl_parse_source(const char *buf, enum
> intel_pipe_crc_source *s)
> return 0;
> }
>
> - i = __match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
> + i = match_string(pipe_crc_sources, buf);
> if (i < 0)
> return i;
>
> diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
> index 9aaacb5bdb26..53dff34c0afc 100644
> --- a/drivers/mfd/omap-usb-host.c
> +++ b/drivers/mfd/omap-usb-host.c
> @@ -509,7 +509,7 @@ static int usbhs_omap_get_dt_pdata(struct device *dev,
> continue;
>
> /* get 'enum usbhs_omap_port_mode' from port mode string */
> - ret = __match_string(port_modes, ARRAY_SIZE(port_modes), mode);
> + ret = match_string(port_modes, mode);
> if (ret < 0) {
> dev_warn(dev, "Invalid port%d-mode \"%s\" in device
> tree\n",
> i, mode);
> diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
> b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
> index 59ce3ff35553..778b4dfd8b75 100644
> --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
> +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
> @@ -667,7 +667,7 @@ iwl_dbgfs_bt_force_ant_write(struct iwl_mvm *mvm, char
> *buf,
> };
> int ret, bt_force_ant_mode;
>
> - ret = __match_string(modes_str, ARRAY_SIZE(modes_str), buf);
> + ret = match_string(modes_str, buf);
> if (ret < 0)
> return ret;
>
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index 41a0773a1cbc..2278caba109c 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -203,7 +203,7 @@ void pcie_ecrc_get_policy(char *str)
> {
> int i;
>
> - i = __match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
> + i = match_string(ecrc_policy_str, str);
> if (i < 0)
> return;
>
> diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
> index bca0c404c6ca..5a651d311d38 100644
> --- a/drivers/usb/common/common.c
> +++
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/icl: Add Multi-segmented gamma support
On 5/7/2019 7:57 PM, Ville Syrjälä wrote:
On Tue, May 07, 2019 at 07:26:44PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from value range between 0.0 to 1.0,
ICL's multi-segment has 3 different sections:
- superfine segment: 9 values, ranges between 0 - 1/(128 * 256)
- fine segment: 257 values, ranges between 0 - 1/(128)
- corase segment: 257 values, ranges between 0 - 1
This patch:
- Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 * 256),
so that userspace can program with highest precision supported.
- Changes default gamma mode (non-legacy) to multi-segmented-gamma mode.
- Adds functions to program/detect multi-segment gamma.
V2: Addressed review comments from Ville
- separate function for superfine and fine segments.
- remove enum for segments.
- reuse last entry of the LUT as gc_max value.
- replace if() cond with switch...case in icl_load_luts.
- add an entry variable, instead of 'word'
V3: Addressed review comments from Ville
- extra newline
- s/entry/color/
- remove LUT size checks
- program ilk_lut_12p4_ldw value before ilk_lut_12p4_udw
- Change the comments in description of fine and coarse segments,
and try to make more sense.
- use 8 * 128 instead of 1024
- add 1 entry in LUT for GCMAX
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Suggested-by: Ville Syrjälä
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c| 2 +-
drivers/gpu/drm/i915/intel_color.c | 127 -
2 files changed, 124 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ffa2ee70a03d..2f99b585d44b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -749,7 +749,7 @@ static const struct intel_device_info intel_cannonlake_info
= {
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1, \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
+ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 6c341bea514c..c1a9506fd069 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -41,6 +41,8 @@
#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
#define LEGACY_LUT_LENGTH 256
+#define ICL_GAMMA_MULTISEG_LUT_LENGTH (256 * 128 * 8)
Unused.
Got it
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -767,6 +769,116 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
}
}
+/* ilk+ "12.4" interpolated format (high 10 bits) */
+static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
+{
+ return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
+ (color->blue >> 6);
+}
+
+/* ilk+ "12.4" interpolated format (low 6 bits) */
+static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
+{
+ return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
+ (color->blue & 0x3f);
Blue is missing the shift.
Ok,
I'm not 100% sure if the ldw vs. udw are the right way around. The spec
has at times been inconsistent with the odd vs. even descriptions,
sometimes even contradicting itself. Also it never really defines
whether it starts counting dwords from from 0 or 1, so not sure what
odd and even actually mean. Can I presume someone has checked this
on actual hardware?
Well, the property was getting set properly, and the display looked ok,
but dint dump the values in registers. Can check it now.
+}
+
+static void
+icl_load_gcmax(const struct intel_crtc_state *crtc_state,
+ const struct drm_color_lut *color)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ /* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+}
+
+static void
+icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv =
Re: [Intel-gfx] [PATCH] drm/i915: Reboot CI if forcewake fails
Quoting Mika Kuoppala (2019-05-08 13:18:06) > Chris Wilson writes: > > > If the HW fail to ack a change in forcewake status, the machine is as > > good as dead -- it may recover, but in reality it missed the mmio > > updates and is now in a very inconsistent state. If it happens, we can't > > trust the CI results (or at least the fails may be genuine but due to > > the HW being dead and not the actual test!) so reboot the machine (CI > > checks for a kernel taint in between each test and reboots if the > > machine is tainted). > > > > Signed-off-by: Chris Wilson > > Cc: Mika Kuoppala > > Cc: Tvrtko Ursulin [snip] > Reviewed-by: Mika Kuoppala And pushed, thanks for the review. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix skl plane scaling for planner YUV buffers
== Series Details == Series: drm/i915: Fix skl plane scaling for planner YUV buffers URL : https://patchwork.freedesktop.org/series/60414/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix skl plane scaling for planner YUV buffers -O:drivers/gpu/drm/i915/intel_display.c:13924:21: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_display.c:13924:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13927:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13927:21: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
Quoting Mika Kuoppala (2019-05-08 13:30:46) > Chris Wilson writes: > > > After realising we need to sample RING_START to detect context switches > > from preemption events that do not allow for the seqno to advance, we > > can also realise that the seqno itself is just a distance along the ring > > and so can be replaced by sampling RING_HEAD. > > > > Signed-off-by: Chris Wilson > > Cc: Mika Kuoppala > > --- > > static enum intel_engine_hangcheck_action > > @@ -156,7 +156,7 @@ hangcheck_get_action(struct intel_engine_cs *engine, > > if (engine->hangcheck.last_ring != hc->ring) > > return ENGINE_ACTIVE_SEQNO; > > > > - if (engine->hangcheck.last_seqno != hc->seqno) > > + if (engine->hangcheck.last_head != hc->head) > > return ENGINE_ACTIVE_SEQNO; > > Change the enum also? Pffifle. As far as hangcheck goes RING_START:RING_HEAD comprise its seqno. Makes for a good talking point in a few years time :) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > > b/drivers/gpu/drm/i915/gt/intel_lrc.c > > index d1a54d2c3d5d..f1d62746e066 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > > @@ -2275,12 +2275,6 @@ static u32 *gen8_emit_fini_breadcrumb(struct > > i915_request *request, u32 *cs) > > request->timeline->hwsp_offset, > > 0); > > > > - cs = gen8_emit_ggtt_write(cs, > > - > > intel_engine_next_hangcheck_seqno(request->engine), > > - I915_GEM_HWS_HANGCHECK_ADDR, > > - MI_FLUSH_DW_STORE_INDEX); > > - > > - > > *cs++ = MI_USER_INTERRUPT; > > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; > > > > @@ -2297,14 +2291,11 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct > > i915_request *request, u32 *cs) > > request->timeline->hwsp_offset, > > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > > PIPE_CONTROL_DEPTH_CACHE_FLUSH | > > - PIPE_CONTROL_DC_FLUSH_ENABLE | > > - PIPE_CONTROL_FLUSH_ENABLE | > > - PIPE_CONTROL_CS_STALL); > > ??? Kabylake sends the interrupt too early otherwise. The hangcheck write saved us by pure accident. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
Chris Wilson writes:
> After realising we need to sample RING_START to detect context switches
> from preemption events that do not allow for the seqno to advance, we
> can also realise that the seqno itself is just a distance along the ring
> and so can be replaced by sampling RING_HEAD.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 15 -
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 5 ++-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +-
> drivers/gpu/drm/i915/gt/intel_hangcheck.c| 8 ++---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++-
> drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 32 ++--
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++--
> 7 files changed, 17 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 06d785533502..9359b3a7ad9c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -215,8 +215,6 @@ intel_write_status_page(struct intel_engine_cs *engine,
> int reg, u32 value)
> */
> #define I915_GEM_HWS_PREEMPT 0x32
> #define I915_GEM_HWS_PREEMPT_ADDR(I915_GEM_HWS_PREEMPT * sizeof(u32))
> -#define I915_GEM_HWS_HANGCHECK 0x34
> -#define I915_GEM_HWS_HANGCHECK_ADDR (I915_GEM_HWS_HANGCHECK * sizeof(u32))
> #define I915_GEM_HWS_SEQNO 0x40
> #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO *
> sizeof(u32))
> #define I915_GEM_HWS_SCRATCH 0x80
> @@ -548,17 +546,4 @@ static inline bool inject_preempt_hang(struct
> intel_engine_execlists *execlists)
>
> #endif
>
> -static inline u32
> -intel_engine_next_hangcheck_seqno(struct intel_engine_cs *engine)
> -{
> - return engine->hangcheck.next_seqno =
> - next_pseudo_random32(engine->hangcheck.next_seqno);
> -}
> -
> -static inline u32
> -intel_engine_get_hangcheck_seqno(struct intel_engine_cs *engine)
> -{
> - return intel_read_status_page(engine, I915_GEM_HWS_HANGCHECK);
> -}
> -
> #endif /* _INTEL_RINGBUFFER_H_ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 416d7e2e6f8c..4c3753c1b573 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -721,6 +721,7 @@ static int measure_breadcrumb_dw(struct intel_engine_cs
> *engine)
> goto out_timeline;
>
> dw = engine->emit_fini_breadcrumb(>rq, frame->cs) - frame->cs;
> + GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
>
> i915_timeline_unpin(>timeline);
>
> @@ -1444,9 +1445,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
> drm_printf(m, "*** WEDGED ***\n");
>
> drm_printf(m, "\tAwake? %d\n", atomic_read(>wakeref.count));
> - drm_printf(m, "\tHangcheck %x:%x [%d ms]\n",
> -engine->hangcheck.last_seqno,
> -engine->hangcheck.next_seqno,
> + drm_printf(m, "\tHangcheck: %d ms ago\n",
> jiffies_to_msecs(jiffies -
> engine->hangcheck.action_timestamp));
> drm_printf(m, "\tReset count: %d (global %d)\n",
> i915_reset_engine_count(error, engine),
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index c0ab11b12e14..e381c1c73902 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -54,8 +54,7 @@ struct intel_instdone {
> struct intel_engine_hangcheck {
> u64 acthd;
> u32 last_ring;
> - u32 last_seqno;
> - u32 next_seqno;
> + u32 last_head;
> unsigned long action_timestamp;
> struct intel_instdone instdone;
> };
> diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> index 721ab74a382f..3a4d09b80fa0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> @@ -28,7 +28,7 @@
> struct hangcheck {
> u64 acthd;
> u32 ring;
> - u32 seqno;
> + u32 head;
> enum intel_engine_hangcheck_action action;
> unsigned long action_timestamp;
> int deadlock;
> @@ -134,16 +134,16 @@ static void hangcheck_load_sample(struct
> intel_engine_cs *engine,
> struct hangcheck *hc)
> {
> hc->acthd = intel_engine_get_active_head(engine);
> - hc->seqno = intel_engine_get_hangcheck_seqno(engine);
> hc->ring = ENGINE_READ(engine, RING_START);
> + hc->head = ENGINE_READ(engine, RING_HEAD);
> }
>
> static void hangcheck_store_sample(struct intel_engine_cs *engine,
> const struct hangcheck *hc)
> {
> engine->hangcheck.acthd = hc->acthd;
> - engine->hangcheck.last_seqno = hc->seqno;
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reboot CI if forcewake fails
== Series Details ==
Series: drm/i915: Reboot CI if forcewake fails
URL : https://patchwork.freedesktop.org/series/60412/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12986
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/
Known issues
Here are the changes found in Patchwork_12986 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
Possible fixes
* igt@gem_exec_basic@readonly-render:
- {fi-icl-y}: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
Warnings
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: [INCOMPLETE][5] ([fdo#103927]) -> [DMESG-FAIL][6]
([fdo#110620])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
* igt@runner@aborted:
- fi-apl-guc: [FAIL][7] ([fdo#110624]) -> [FAIL][8] ([fdo#110622])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/fi-apl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620
[fdo#110622]: https://bugs.freedesktop.org/show_bug.cgi?id=110622
[fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624
Participating hosts (53 -> 45)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6063 -> Patchwork_12986
CI_DRM_6063: 44ae4003d35743cbc7883825c5fe777d136b5247 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12986: d0634a52dcb114fe2343e6921503473018e1121f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d0634a52dcb1 drm/i915: Reboot CI if forcewake fails
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12986/
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Reboot CI if forcewake fails
Quoting Mika Kuoppala (2019-05-08 13:18:06) > Chris Wilson writes: > > > If the HW fail to ack a change in forcewake status, the machine is as > > good as dead -- it may recover, but in reality it missed the mmio > > updates and is now in a very inconsistent state. If it happens, we can't > > trust the CI results (or at least the fails may be genuine but due to > > the HW being dead and not the actual test!) so reboot the machine (CI > > checks for a kernel taint in between each test and reboots if the > > machine is tainted). > > > > Signed-off-by: Chris Wilson > > Cc: Mika Kuoppala > > Cc: Tvrtko Ursulin > > Sounds and looks reasonable. Should we also taint if we have > unclaimed mmio after init sequence? The unclaimed mmio throws a WARN so it naturally gets the add_taint(TAINT_WARN) and CI reboots already. Otherwise, yes :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 16/21] gem_wsim: Some more example workloads
Quoting Tvrtko Ursulin (2019-05-08 13:10:53) > From: Tvrtko Ursulin > > A few additional workloads useful for experimenting with scheduling. > > Signed-off-by: Tvrtko Ursulin Are the extra modes & .wsim supported by scripts/media-bench.pl? i.e. can I just run media-bench.pl and have it exercise all the new features? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/16] mmc: sdhci-xenon: use new match_string() helper/macro
On Wed, May 08, 2019 at 02:28:35PM +0300, Alexandru Ardelean wrote:
> -static const char * const phy_types[] = {
> - "emmc 5.0 phy",
> - "emmc 5.1 phy"
> -};
> -
> enum xenon_phy_type_enum {
> EMMC_5_0_PHY,
> EMMC_5_1_PHY,
> NR_PHY_TYPES
There is no need for NR_PHY_TYPES now so you could remove that as well.
regards,
dan carpenter
___
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Re: [Intel-gfx] [PATCH] drm/i915: Reboot CI if forcewake fails
Chris Wilson writes:
> If the HW fail to ack a change in forcewake status, the machine is as
> good as dead -- it may recover, but in reality it missed the mmio
> updates and is now in a very inconsistent state. If it happens, we can't
> trust the CI results (or at least the fails may be genuine but due to
> the HW being dead and not the actual test!) so reboot the machine (CI
> checks for a kernel taint in between each test and reboots if the
> machine is tainted).
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
Sounds and looks reasonable. Should we also taint if we have
unclaimed mmio after init sequence?
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 11 +++
> drivers/gpu/drm/i915/intel_uncore.c | 8 ++--
> 3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 419b3415370b..464369bc55ad 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1042,7 +1042,7 @@ void i915_reset(struct drm_i915_private *i915,
>* rather than continue on into oblivion. For everyone else,
>* the system should still plod along, but they have been warned!
>*/
> - add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
> + add_taint_for_CI(TAINT_WARN);
> error:
> __i915_gem_set_wedged(i915);
> goto finish;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0a6ec61496f1..d0257808734c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3375,4 +3375,15 @@ static inline u32 i915_scratch_offset(const struct
> drm_i915_private *i915)
> return i915_ggtt_offset(i915->gt.scratch);
> }
>
> +static inline void add_taint_for_CI(unsigned int taint)
> +{
> + /*
> + * The system is "ok", just about surviving for the user, but
> + * CI results are now unreliable as the HW is very suspect.
> + * CI checks the taint state after every test and will reboot
> + * the machine if the kernel is tainted.
> + */
> + add_taint(taint, LOCKDEP_STILL_OK);
> +}
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index d1d51e1121e2..6ec1bc97b665 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -111,9 +111,11 @@ wait_ack_set(const struct intel_uncore_forcewake_domain
> *d,
> static inline void
> fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
> {
> - if (wait_ack_clear(d, FORCEWAKE_KERNEL))
> + if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
> DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
> intel_uncore_forcewake_domain_to_str(d->id));
> + add_taint_for_CI(TAINT_WARN); /* CI unreliable */
> + }
> }
>
> enum ack_type {
> @@ -186,9 +188,11 @@ fw_domain_get(const struct intel_uncore_forcewake_domain
> *d)
> static inline void
> fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
> {
> - if (wait_ack_set(d, FORCEWAKE_KERNEL))
> + if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
> DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
> intel_uncore_forcewake_domain_to_str(d->id));
> + add_taint_for_CI(TAINT_WARN); /* CI unreliable */
> + }
> }
>
> static inline void
> --
> 2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 01/21] scripts/trace.pl: Fix after intel_engine_notify removal
Quoting Tvrtko Ursulin (2019-05-08 13:10:38) > From: Tvrtko Ursulin > > After the removal of engine global seqnos and the corresponding > intel_engine_notify tracepoints the script needs to be adjusted to cope > with the new state of things. > > To keep working it switches over using the dma_fence:dma_fence_signaled: > tracepoint and keeps one extra internal map to connect the ctx-seqno pairs > with engines. Is the map suitable for the planned (by me) s/i915_request_wait_begin/dma_fence_wait_begin/ I guess it should be. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 07/21] gem_wsim: Factor out common error handling
From: Tvrtko Ursulin
There is a repeated pattern with error handling which can be moved to a
macro to for better readability in the command parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 244 +++---
1 file changed, 88 insertions(+), 156 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 609e64f3d9c8..ef97311a6879 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -289,6 +289,27 @@ parse_dependencies(unsigned int nr_steps, struct w_step
*w, char *_desc)
return 0;
}
+static void __attribute__((format(printf, 1, 2)))
+wsim_err(const char *fmt, ...)
+{
+ va_list ap;
+
+ if (!verbose)
+ return;
+
+ va_start(ap, fmt);
+ vfprintf(stderr, fmt, ap);
+ va_end(ap);
+}
+
+#define check_arg(cond, fmt, ...) \
+{ \
+ if (cond) { \
+ wsim_err(fmt, __VA_ARGS__); \
+ return NULL; \
+ } \
+}
+
static struct workload *
parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w)
{
@@ -319,14 +340,9 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
if ((field = strtok_r(fstart, ".", )) !=
NULL) {
tmp = atoi(field);
- if (tmp <= 0) {
- if (verbose)
- fprintf(stderr,
- "Invalid delay
at step %u!\n",
- nr_steps);
- return NULL;
- }
-
+ check_arg(tmp <= 0,
+ "Invalid delay at step %u!\n",
+ nr_steps);
step.type = DELAY;
step.delay = tmp;
goto add_step;
@@ -335,14 +351,9 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
if ((field = strtok_r(fstart, ".", )) !=
NULL) {
tmp = atoi(field);
- if (tmp <= 0) {
- if (verbose)
- fprintf(stderr,
- "Invalid period
at step %u!\n",
- nr_steps);
- return NULL;
- }
-
+ check_arg(tmp <= 0,
+ "Invalid period at step
%u!\n",
+ nr_steps);
step.type = PERIOD;
step.period = tmp;
goto add_step;
@@ -352,25 +363,17 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
while ((field = strtok_r(fstart, ".", )) !=
NULL) {
tmp = atoi(field);
- if (tmp <= 0 && nr == 0) {
- if (verbose)
- fprintf(stderr,
- "Invalid
context at step %u!\n",
- nr_steps);
- return NULL;
- }
-
- if (nr == 0) {
+ check_arg(nr == 0 && tmp <= 0,
+ "Invalid context at step
%u!\n",
+ nr_steps);
+ check_arg(nr > 1,
+ "Invalid priority format at
step %u!\n",
+ nr_steps);
+
+ if (nr == 0)
step.context = tmp;
- } else if (nr == 1) {
+ else
step.priority = tmp;
- } else {
- if (verbose)
-
[Intel-gfx] [PATCH i-g-t 16/21] gem_wsim: Some more example workloads
From: Tvrtko Ursulin A few additional workloads useful for experimenting with scheduling. Signed-off-by: Tvrtko Ursulin --- benchmarks/wsim/frame-split-60fps.wsim | 16 benchmarks/wsim/high-composited-game.wsim | 11 +++ benchmarks/wsim/media-1080p-player.wsim | 5 + benchmarks/wsim/medium-composited-game.wsim | 9 + 4 files changed, 41 insertions(+) create mode 100644 benchmarks/wsim/frame-split-60fps.wsim create mode 100644 benchmarks/wsim/high-composited-game.wsim create mode 100644 benchmarks/wsim/media-1080p-player.wsim create mode 100644 benchmarks/wsim/medium-composited-game.wsim diff --git a/benchmarks/wsim/frame-split-60fps.wsim b/benchmarks/wsim/frame-split-60fps.wsim new file mode 100644 index ..cfbfcd39be7d --- /dev/null +++ b/benchmarks/wsim/frame-split-60fps.wsim @@ -0,0 +1,16 @@ +X.1.0 +M.1.VCS1 +B.1 +X.2.0 +M.2.VCS2 +B.2 +b.2.1.VCS1 +f +1.DEFAULT.4000-6000.f-1.0 +2.DEFAULT.4000-6000.s-1.0 +a.-3 +3.RCS.2000-4000.-3/-2.0 +3.VECS.2000.-1.0 +4.BCS.1000.-1.0 +s.-2 +p.16667 diff --git a/benchmarks/wsim/high-composited-game.wsim b/benchmarks/wsim/high-composited-game.wsim new file mode 100644 index ..a90a2b2be95b --- /dev/null +++ b/benchmarks/wsim/high-composited-game.wsim @@ -0,0 +1,11 @@ +1.RCS.500.0.0 +1.RCS.2000.0.0 +1.RCS.2000.0.0 +1.RCS.2000.0.0 +1.RCS.2000.0.0 +1.RCS.2000.0.0 +1.RCS.2000.0.0 +P.2.1 +2.BCS.1000.-2.0 +2.RCS.2000.-1.1 +p.16667 diff --git a/benchmarks/wsim/media-1080p-player.wsim b/benchmarks/wsim/media-1080p-player.wsim new file mode 100644 index ..bcbb0cfd2ad3 --- /dev/null +++ b/benchmarks/wsim/media-1080p-player.wsim @@ -0,0 +1,5 @@ +1.VCS.5000-1.0.0 +2.RCS.1000-2000.-1.0 +P.3.1 +3.BCS.1000.-2.0 +p.16667 diff --git a/benchmarks/wsim/medium-composited-game.wsim b/benchmarks/wsim/medium-composited-game.wsim new file mode 100644 index ..580883516168 --- /dev/null +++ b/benchmarks/wsim/medium-composited-game.wsim @@ -0,0 +1,9 @@ +1.RCS.1000-2000.0.0 +1.RCS.1000-2000.0.0 +1.RCS.1000-2000.0.0 +1.RCS.1000-2000.0.0 +1.RCS.1000-2000.0.0 +P.2.1 +2.BCS.1000.-2.0 +2.RCS.2000.-1.1 +p.16667 -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 19/21] gem_wsim: Per context SSEU control
From: Tvrtko Ursulin
A new workload command ('S') is added which allows per context slice
(re-)configuration.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 69 +++---
benchmarks/wsim/README | 23 +-
2 files changed, 80 insertions(+), 12 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 64dd251a25eb..ed5acee02e20 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -87,6 +87,7 @@ enum w_type
LOAD_BALANCE,
BOND,
TERMINATE,
+ SSEU
};
struct deps
@@ -136,6 +137,7 @@ struct w_step
uint64_t bond_mask;
enum intel_engine_id bond_master;
};
+ int sseu;
};
/* Implementation details */
@@ -171,6 +173,7 @@ struct ctx {
bool targets_instance;
bool wants_balance;
unsigned int static_vcs;
+ uint64_t sseu;
};
struct workload
@@ -241,6 +244,7 @@ static unsigned int context_vcs_rr;
static int verbose = 1;
static int fd;
+static struct drm_i915_gem_context_param_sseu device_sseu;
#define SWAPVCS(1<<0)
#define SEQNO (1<<1)
@@ -456,6 +460,27 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
int_field(SYNC, target,
tmp >= 0 || ((int)nr_steps + tmp) < 0,
"Invalid sync target at step %u!\n");
+ } else if (!strcmp(field, "S")) {
+ unsigned int nr = 0;
+ while ((field = strtok_r(fstart, ".", ))) {
+ tmp = atoi(field);
+ check_arg(tmp <= 0 && nr == 0,
+ "Invalid context at step
%u!\n",
+ nr_steps);
+ check_arg(nr > 1,
+ "Invalid SSEU format at step
%u!\n",
+ nr_steps);
+
+ if (nr == 0)
+ step.context = tmp;
+ else if (nr == 1)
+ step.sseu = tmp;
+
+ nr++;
+ }
+
+ step.type = SSEU;
+ goto add_step;
} else if (!strcmp(field, "t")) {
int_field(THROTTLE, throttle,
tmp < 0,
@@ -1071,24 +1096,24 @@ static void __ctx_set_prio(uint32_t ctx_id, unsigned
int prio)
gem_context_set_param(fd, );
}
-static void
-set_ctx_sseu(uint32_t ctx)
+static uint64_t
+set_ctx_sseu(uint32_t ctx, uint64_t slice_mask)
{
- struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param_sseu sseu = device_sseu;
struct drm_i915_gem_context_param param = { };
- sseu.class = I915_ENGINE_CLASS_RENDER;
- sseu.instance = 0;
+ if (slice_mask == -1)
+ slice_mask = device_sseu.slice_mask;
+
+ sseu.slice_mask = slice_mask;
param.ctx_id = ctx;
param.param = I915_CONTEXT_PARAM_SSEU;
param.value = (uintptr_t)
- gem_context_get_param(fd, );
-
- sseu.slice_mask = 1;
-
gem_context_set_param(fd, );
+
+ return slice_mask;
}
static int
@@ -1287,6 +1312,7 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
igt_assert(ctx_id);
ctx->id = ctx_id;
+ ctx->sseu = device_sseu.slice_mask;
if (flags & GLOBAL_BALANCE) {
ctx->static_vcs = context_vcs_rr;
@@ -1439,8 +1465,10 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
gem_context_set_param(fd, );
}
- if (wrk->sseu)
- set_ctx_sseu(arg.ctx_id);
+ if (wrk->sseu) {
+ /* Set to slice 0 only, one slice. */
+ ctx->sseu = set_ctx_sseu(ctx_id, 1);
+ }
}
/* Record default preemption. */
@@ -2409,6 +2437,13 @@ static void *run_workload(void *data)
w->type == LOAD_BALANCE ||
w->type == BOND) {
continue;
+ } else if (w->type == SSEU) {
+ if (w->sseu != wrk->ctx_list[w->context].sseu) {
+ wrk->ctx_list[w->context].sseu =
+
[Intel-gfx] [PATCH i-g-t 05/21] wsim/media-bench: i915 balancing
From: Tvrtko Ursulin
Support i915 virtual engine from gem_wsim (-b i915) and media-bench.pl
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 281 ++---
scripts/media-bench.pl | 9 +-
2 files changed, 244 insertions(+), 46 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index afb9644dd7f0..1084e95fa8df 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -142,6 +142,14 @@ struct w_step
DECLARE_EWMA(uint64_t, rt, 4, 2)
+struct ctx {
+ uint32_t id;
+ int priority;
+ bool targets_instance;
+ bool wants_balance;
+ unsigned int static_vcs;
+};
+
struct workload
{
unsigned int id;
@@ -163,11 +171,7 @@ struct workload
struct timespec repeat_start;
unsigned int nr_ctxs;
- struct {
- uint32_t id;
- int priority;
- unsigned int static_vcs;
- } *ctx_list;
+ struct ctx *ctx_list;
int sync_timeline;
uint32_t sync_seqno;
@@ -224,6 +228,7 @@ static int fd;
#define HEARTBEAT (1<<7)
#define GLOBAL_BALANCE (1<<8)
#define DEPSYNC(1<<9)
+#define I915 (1<<10)
#define SEQNO_IDX(engine) ((engine) * 16)
#define SEQNO_OFFSET(engine) (SEQNO_IDX(engine) * sizeof(uint32_t))
@@ -841,7 +846,11 @@ eb_set_engine(struct drm_i915_gem_execbuffer2 *eb,
if (engine == VCS2 && (flags & VCS2REMAP))
engine = BCS;
- eb->flags = eb_engine_map[engine];
+ if ((flags & I915) && engine == VCS) {
+ eb->flags = 0;
+ } else {
+ eb->flags = eb_engine_map[engine];
+ }
}
static void
@@ -867,6 +876,23 @@ get_status_objects(struct workload *wrk)
return wrk->status_object;
}
+static struct ctx *
+__get_ctx(struct workload *wrk, struct w_step *w)
+{
+ return >ctx_list[w->context * 2];
+}
+
+static uint32_t
+get_ctxid(struct workload *wrk, struct w_step *w)
+{
+ struct ctx *ctx = __get_ctx(wrk, w);
+
+ if (ctx->targets_instance && ctx->wants_balance && w->engine == VCS)
+ return wrk->ctx_list[w->context * 2 + 1].id;
+ else
+ return wrk->ctx_list[w->context * 2].id;
+}
+
static void
alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags)
{
@@ -919,7 +945,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w,
unsigned int flags)
w->eb.buffers_ptr = to_user_pointer(w->obj);
w->eb.buffer_count = j + 1;
- w->eb.rsvd1 = wrk->ctx_list[w->context].id;
+ w->eb.rsvd1 = get_ctxid(wrk, w);
if (flags & SWAPVCS && engine == VCS1)
engine = VCS2;
@@ -932,17 +958,29 @@ alloc_step_batch(struct workload *wrk, struct w_step *w,
unsigned int flags)
printf("%x|", w->obj[i].handle);
printf(" %10lu flags=%llx bb=%x[%u] ctx[%u]=%u\n",
w->bb_sz, w->eb.flags, w->bb_handle, j, w->context,
- wrk->ctx_list[w->context].id);
+ get_ctxid(wrk, w));
#endif
}
+static void __ctx_set_prio(uint32_t ctx_id, unsigned int prio)
+{
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx_id,
+ .param = I915_CONTEXT_PARAM_PRIORITY,
+ .value = prio,
+ };
+
+ if (prio)
+ gem_context_set_param(fd, );
+}
+
static void
prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
{
unsigned int ctx_vcs = 0;
int max_ctx = -1;
struct w_step *w;
- int i;
+ int i, j;
wrk->id = id;
wrk->prng = rand();
@@ -973,44 +1011,183 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
}
}
+ /*
+* Pre-scan workload steps to allocate context list storage.
+*/
for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) {
- if ((int)w->context > max_ctx) {
- int delta = w->context + 1 - wrk->nr_ctxs;
+ int ctx = w->context * 2 + 1; /* Odd slots are special. */
+ int delta;
+
+ if (ctx <= max_ctx)
+ continue;
+
+ delta = ctx + 1 - wrk->nr_ctxs;
- wrk->nr_ctxs += delta;
- wrk->ctx_list = realloc(wrk->ctx_list,
- wrk->nr_ctxs *
- sizeof(*wrk->ctx_list));
- memset(>ctx_list[wrk->nr_ctxs - delta], 0,
- delta * sizeof(*wrk->ctx_list));
+ wrk->nr_ctxs += delta;
+ wrk->ctx_list = realloc(wrk->ctx_list,
+ wrk->nr_ctxs * sizeof(*wrk->ctx_list));
+ memset(>ctx_list[wrk->nr_ctxs - delta], 0,
+ delta * sizeof(*wrk->ctx_list));
+
+
[Intel-gfx] [PATCH i-g-t 20/21] gem_wsim: Allow RCS virtual engine with SSEU control
From: Tvrtko Ursulin
To allow exercising the SSEU configuration in combination with Virtual
Engine, allow RCS to be specified in the engine map and use appropriate
index based addressing when applying SSEU configuration to it.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 51 ++-
1 file changed, 36 insertions(+), 15 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index ed5acee02e20..7990ab41f6fa 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -381,7 +381,7 @@ static int parse_engine_map(struct w_step *step, const char
*_str)
if ((int)engine < 0)
return -1;
- if (engine != VCS1 && engine != VCS2)
+ if (engine != VCS1 && engine != VCS2 && engine != RCS)
return -1; /* TODO */
step->engine_map_count++;
@@ -1097,7 +1097,7 @@ static void __ctx_set_prio(uint32_t ctx_id, unsigned int
prio)
}
static uint64_t
-set_ctx_sseu(uint32_t ctx, uint64_t slice_mask)
+set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask)
{
struct drm_i915_gem_context_param_sseu sseu = device_sseu;
struct drm_i915_gem_context_param param = { };
@@ -1105,10 +1105,17 @@ set_ctx_sseu(uint32_t ctx, uint64_t slice_mask)
if (slice_mask == -1)
slice_mask = device_sseu.slice_mask;
+ if (ctx->engine_map && ctx->wants_balance) {
+ sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX;
+ sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID;
+ sseu.engine.engine_instance = 0;
+ }
+
sseu.slice_mask = slice_mask;
- param.ctx_id = ctx;
+ param.ctx_id = ctx->id;
param.param = I915_CONTEXT_PARAM_SSEU;
+ param.size = sizeof(sseu);
param.value = (uintptr_t)
gem_context_set_param(fd, );
@@ -1377,10 +1384,17 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
ctx->engine_map_count;
for (j = 0; j < ctx->engine_map_count; j++) {
- load_balance.engines[j].engine_class =
- I915_ENGINE_CLASS_VIDEO; /*
FIXME */
- load_balance.engines[j].engine_instance
=
- ctx->engine_map[j] - VCS1; /*
FIXME */
+ if (ctx->engine_map[j] == RCS) {
+
load_balance.engines[j].engine_class =
+
I915_ENGINE_CLASS_RENDER;
+
load_balance.engines[j].engine_instance =
+ 0; /* FIXME */
+ } else {
+
load_balance.engines[j].engine_class =
+
I915_ENGINE_CLASS_VIDEO; /* FIXME */
+
load_balance.engines[j].engine_instance =
+ ctx->engine_map[j] -
VCS1; /* FIXME */
+ }
}
} else {
set_engines.extensions = 0;
@@ -1393,10 +1407,16 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
I915_ENGINE_CLASS_INVALID_NONE;
for (j = 1; j <= ctx->engine_map_count; j++) {
- set_engines.engines[j].engine_class =
- I915_ENGINE_CLASS_VIDEO; /* FIXME */
- set_engines.engines[j].engine_instance =
- ctx->engine_map[j - 1] - VCS1; /* FIXME
*/
+ if (ctx->engine_map[j - 1] == RCS) {
+ set_engines.engines[j].engine_class =
+ I915_ENGINE_CLASS_RENDER;
+ set_engines.engines[j].engine_instance
= 0; /* FIXME */
+ } else {
+ set_engines.engines[j].engine_class =
+ I915_ENGINE_CLASS_VIDEO; /*
FIXME */
+ set_engines.engines[j].engine_instance =
+ ctx->engine_map[j - 1] - VCS1;
/* FIXME */
+ }
}
for (j = 0; j < ctx->bond_count; j++) {
@@ -1467,7 +1487,7 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
if (wrk->sseu) {
[Intel-gfx] [PATCH i-g-t 08/21] gem_wsim: More wsim_err
From: Tvrtko Ursulin
A few more opportunities to compact the code by using the error logging
helper.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 54 ---
1 file changed, 15 insertions(+), 39 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index ef97311a6879..f1fcef5dcfba 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2396,9 +2396,7 @@ int main(int argc, char **argv)
switch (c) {
case 'W':
if (master_workload >= 0) {
- if (verbose)
- fprintf(stderr,
- "Only one master workload can
be given!\n");
+ wsim_err("Only one master workload can be
given!\n");
return 1;
}
master_workload = nr_w_args;
@@ -2411,9 +2409,7 @@ int main(int argc, char **argv)
break;
case 'a':
if (append_workload_arg) {
- if (verbose)
- fprintf(stderr,
- "Only one append workload can
be given!\n");
+ wsim_err("Only one append workload can be
given!\n");
return 1;
}
append_workload_arg = optarg;
@@ -2474,10 +2470,8 @@ int main(int argc, char **argv)
}
if (!balancer) {
- if (verbose)
- fprintf(stderr,
- "Unknown balancing mode
'%s'!\n",
- optarg);
+ wsim_err("Unknown balancing mode '%s'!\n",
+optarg);
return 1;
}
break;
@@ -2490,14 +2484,12 @@ int main(int argc, char **argv)
}
if ((flags & HEARTBEAT) && !(flags & SEQNO)) {
- if (verbose)
- fprintf(stderr, "Heartbeat needs a seqno based
balancer!\n");
+ wsim_err("Heartbeat needs a seqno based balancer!\n");
return 1;
}
if ((flags & VCS2REMAP) && (flags & I915)) {
- if (verbose)
- fprintf(stderr, "VCS remapping not supported with i915
balancing!\n");
+ wsim_err("VCS remapping not supported with i915 balancing!\n");
return 1;
}
@@ -2514,31 +2506,24 @@ int main(int argc, char **argv)
}
if (!nr_w_args) {
- if (verbose)
- fprintf(stderr, "No workload descriptor(s)!\n");
+ wsim_err("No workload descriptor(s)!\n");
return 1;
}
if (nr_w_args > 1 && clients > 1) {
- if (verbose)
- fprintf(stderr,
- "Cloned clients cannot be combined with
multiple workloads!\n");
+ wsim_err("Cloned clients cannot be combined with multiple
workloads!\n");
return 1;
}
if ((flags & GLOBAL_BALANCE) && !balancer) {
- if (verbose)
- fprintf(stderr,
- "Balancer not specified in global balancing
mode!\n");
+ wsim_err("Balancer not specified in global balancing mode!\n");
return 1;
}
if (append_workload_arg) {
append_workload_arg =
load_workload_descriptor(append_workload_arg);
if (!append_workload_arg) {
- if (verbose)
- fprintf(stderr,
- "Failed to load append workload
descriptor!\n");
+ wsim_err("Failed to load append workload
descriptor!\n");
return 1;
}
}
@@ -2547,9 +2532,7 @@ int main(int argc, char **argv)
struct w_arg arg = { NULL, append_workload_arg, 0 };
app_w = parse_workload(, flags, NULL);
if (!app_w) {
- if (verbose)
- fprintf(stderr,
- "Failed to parse append workload!\n");
+ wsim_err("Failed to parse append workload!\n");
return 1;
}
}
@@ -2561,18 +2544,13 @@ int main(int argc, char **argv)
w_args[i].desc = load_workload_descriptor(w_args[i].filename);
if (!w_args[i].desc) {
- if (verbose)
- fprintf(stderr,
-
[Intel-gfx] [PATCH i-g-t 18/21] gem_wsim: Command line switch for specifying low slice count workloads
From: Tvrtko Ursulin
A new command line switch ('-s') is added which toggles the low slice
count mode for workloads following on the command line.
This enables easy benchmarking of the effect of running the existing media
workloads in parallel against another client. For example:
./gem_wsim -n ... -v -r 600 -W master.wsim -s -w media_nn480.wsim
Adding or removing the '-s' switch before the second workload enables
analyzing the cost of dynamic SSEU switching impacted to the first
(master) workload.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 44 +++
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 97821b723b02..64dd251a25eb 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -100,6 +100,7 @@ struct w_arg {
char *filename;
char *desc;
int prio;
+ bool sseu;
};
struct bond {
@@ -179,6 +180,7 @@ struct workload
unsigned int nr_steps;
struct w_step *steps;
int prio;
+ bool sseu;
pthread_t thread;
bool run;
@@ -251,6 +253,7 @@ static int fd;
#define GLOBAL_BALANCE (1<<8)
#define DEPSYNC(1<<9)
#define I915 (1<<10)
+#define SSEU (1<<11)
#define SEQNO_IDX(engine) ((engine) * 16)
#define SEQNO_OFFSET(engine) (SEQNO_IDX(engine) * sizeof(uint32_t))
@@ -696,6 +699,7 @@ add_step:
wrk->nr_steps = nr_steps;
wrk->steps = steps;
wrk->prio = arg->prio;
+ wrk->sseu = arg->sseu;
free(desc);
@@ -741,6 +745,7 @@ clone_workload(struct workload *_wrk)
memset(wrk, 0, sizeof(*wrk));
wrk->prio = _wrk->prio;
+ wrk->sseu = _wrk->sseu;
wrk->nr_steps = _wrk->nr_steps;
wrk->steps = calloc(wrk->nr_steps, sizeof(struct w_step));
igt_assert(wrk->steps);
@@ -1066,6 +1071,26 @@ static void __ctx_set_prio(uint32_t ctx_id, unsigned int
prio)
gem_context_set_param(fd, );
}
+static void
+set_ctx_sseu(uint32_t ctx)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param param = { };
+
+ sseu.class = I915_ENGINE_CLASS_RENDER;
+ sseu.instance = 0;
+
+ param.ctx_id = ctx;
+ param.param = I915_CONTEXT_PARAM_SSEU;
+ param.value = (uintptr_t)
+
+ gem_context_get_param(fd, );
+
+ sseu.slice_mask = 1;
+
+ gem_context_set_param(fd, );
+}
+
static int
prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags)
{
@@ -1413,6 +1438,9 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
gem_context_set_param(fd, );
}
+
+ if (wrk->sseu)
+ set_ctx_sseu(arg.ctx_id);
}
/* Record default preemption. */
@@ -2585,6 +2613,8 @@ static void print_help(void)
" -R Round-robin initial VCS assignment per client.\n"
" -H Send heartbeat on synchronisation points with seqno based\n"
" balancers. Gives better engine busyness view in some
cases.\n"
+" -s Turn on small SSEU config for the next workload on the\n"
+" command line. Subsequent -s switches it off.\n"
" -S Synchronize the sequence of random batch durations
between\n"
" clients.\n"
" -G Global load balancing - a single load balancer will be
shared\n"
@@ -2627,11 +2657,12 @@ static char *load_workload_descriptor(char *filename)
}
static struct w_arg *
-add_workload_arg(struct w_arg *w_args, unsigned int nr_args, char *w_arg, int
prio)
+add_workload_arg(struct w_arg *w_args, unsigned int nr_args, char *w_arg,
+int prio, bool sseu)
{
w_args = realloc(w_args, sizeof(*w_args) * nr_args);
igt_assert(w_args);
- w_args[nr_args - 1] = (struct w_arg) { w_arg, NULL, prio };
+ w_args[nr_args - 1] = (struct w_arg) { w_arg, NULL, prio, sseu };
return w_args;
}
@@ -2724,7 +2755,8 @@ int main(int argc, char **argv)
init_clocks();
- while ((c = getopt(argc, argv, "hqv2RSHxGdc:n:r:w:W:a:t:b:p:")) != -1) {
+ while ((c = getopt(argc, argv,
+ "hqv2RsSHxGdc:n:r:w:W:a:t:b:p:")) != -1) {
switch (c) {
case 'W':
if (master_workload >= 0) {
@@ -2734,7 +2766,8 @@ int main(int argc, char **argv)
master_workload = nr_w_args;
/* Fall through */
case 'w':
- w_args = add_workload_arg(w_args, ++nr_w_args, optarg,
prio);
+ w_args = add_workload_arg(w_args, ++nr_w_args, optarg,
+ prio, flags & SSEU);
break;
case 'p':
prio = atoi(optarg);
@@
[Intel-gfx] [PATCH i-g-t 13/21] gem_wsim: Compact int command parsing with a macro
From: Tvrtko Ursulin
Parsing an integer workload descriptor field is a common pattern which we
can extract to a helper macro and by doing so further improve the
readability of the main parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 80 ++-
1 file changed, 25 insertions(+), 55 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 4dbfc3e922a9..c2e13d9939c2 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -370,6 +370,15 @@ static int parse_engine_map(struct w_step *step, const
char *_str)
return 0;
}
+#define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \
+ if ((field = strtok_r(fstart, ".", ))) { \
+ tmp = atoi(field); \
+ check_arg(_COND_, _ERR_, nr_steps); \
+ step.type = _STEP_; \
+ step._FIELD_ = tmp; \
+ goto add_step; \
+ } \
+
static struct workload *
parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w)
{
@@ -397,25 +406,11 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
fstart = NULL;
if (!strcmp(field, "d")) {
- if ((field = strtok_r(fstart, ".", ))) {
- tmp = atoi(field);
- check_arg(tmp <= 0,
- "Invalid delay at step %u!\n",
- nr_steps);
- step.type = DELAY;
- step.delay = tmp;
- goto add_step;
- }
+ int_field(DELAY, delay, tmp <= 0,
+ "Invalid delay at step %u!\n");
} else if (!strcmp(field, "p")) {
- if ((field = strtok_r(fstart, ".", ))) {
- tmp = atoi(field);
- check_arg(tmp <= 0,
- "Invalid period at step
%u!\n",
- nr_steps);
- step.type = PERIOD;
- step.period = tmp;
- goto add_step;
- }
+ int_field(PERIOD, period, tmp <= 0,
+ "Invalid period at step %u!\n");
} else if (!strcmp(field, "P")) {
unsigned int nr = 0;
while ((field = strtok_r(fstart, ".", ))) {
@@ -438,46 +433,21 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
step.type = CTX_PRIORITY;
goto add_step;
} else if (!strcmp(field, "s")) {
- if ((field = strtok_r(fstart, ".", ))) {
- tmp = atoi(field);
- check_arg(tmp >= 0 ||
- ((int)nr_steps + tmp) < 0,
- "Invalid sync target at step
%u!\n",
- nr_steps);
- step.type = SYNC;
- step.target = tmp;
- goto add_step;
- }
+ int_field(SYNC, target,
+ tmp >= 0 || ((int)nr_steps + tmp) < 0,
+ "Invalid sync target at step %u!\n");
} else if (!strcmp(field, "t")) {
- if ((field = strtok_r(fstart, ".", ))) {
- tmp = atoi(field);
- check_arg(tmp < 0,
- "Invalid throttle at step
%u!\n",
- nr_steps);
- step.type = THROTTLE;
- step.throttle = tmp;
- goto add_step;
- }
+ int_field(THROTTLE, throttle,
+ tmp < 0,
+ "Invalid throttle at step %u!\n");
} else if (!strcmp(field, "q")) {
- if ((field = strtok_r(fstart, ".", ))) {
- tmp = atoi(field);
-
[Intel-gfx] [PATCH i-g-t 10/21] gem_wsim: Extract str to engine lookup
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 5245692df6eb..f654decb24cc 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -318,6 +318,18 @@ wsim_err(const char *fmt, ...)
} \
}
+static int str_to_engine(const char *str)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(ring_str_map); i++) {
+ if (!strcasecmp(str, ring_str_map[i]))
+ return i;
+ }
+
+ return -1;
+}
+
static struct workload *
parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w)
{
@@ -480,22 +492,18 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
}
if ((field = strtok_r(fstart, ".", )) != NULL) {
- unsigned int old_valid = valid;
-
fstart = NULL;
- for (i = 0; i < ARRAY_SIZE(ring_str_map); i++) {
- if (!strcasecmp(field, ring_str_map[i])) {
- step.engine = i;
- if (step.engine == BCS)
- bcs_used = true;
- valid++;
- break;
- }
- }
-
- check_arg(old_valid == valid,
+ i = str_to_engine(field);
+ check_arg(i < 0,
"Invalid engine id at step %u!\n", nr_steps);
+ if (i >= 0)
+ valid++;
+
+ step.engine = i;
+
+ if (step.engine == BCS)
+ bcs_used = true;
}
if ((field = strtok_r(fstart, ".", )) != NULL) {
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 14/21] gem_wsim: Engine map load balance command
From: Tvrtko Ursulin
A new workload command for enabling a load balanced context map (aka
Virtual Engine). Example usage:
B.1
This turns on load balancing for context one, assuming it has already been
configured with an engine map. Only DEFAULT engine specifier can be used
with load balanced engine maps.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 73 ++
benchmarks/wsim/README | 18 +++
2 files changed, 84 insertions(+), 7 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index c2e13d9939c2..b610a603f7b0 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -83,7 +83,8 @@ enum w_type
SW_FENCE_SIGNAL,
CTX_PRIORITY,
PREEMPTION,
- ENGINE_MAP
+ ENGINE_MAP,
+ LOAD_BALANCE,
};
struct deps
@@ -121,6 +122,7 @@ struct w_step
unsigned int engine_map_count;
enum intel_engine_id *engine_map;
};
+ bool load_balance;
};
/* Implementation details */
@@ -501,6 +503,25 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
step.type = PREEMPTION;
goto add_step;
+ } else if (!strcmp(field, "B")) {
+ unsigned int nr = 0;
+ while ((field = strtok_r(fstart, ".", ))) {
+ tmp = atoi(field);
+ check_arg(nr == 0 && tmp <= 0,
+ "Invalid context at step
%u!\n",
+ nr_steps);
+ check_arg(nr > 0,
+ "Invalid load balance format
at step %u!\n",
+ nr_steps);
+
+ step.context = tmp;
+ step.load_balance = true;
+
+ nr++;
+ }
+
+ step.type = LOAD_BALANCE;
+ goto add_step;
}
if (!field) {
@@ -833,7 +854,7 @@ find_engine_in_map(struct ctx *ctx, enum intel_engine_id
engine)
return i + 1;
}
- igt_assert(0);
+ igt_assert(ctx->wants_balance);
return 0;
}
@@ -1044,12 +1065,19 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
wrk->ctx_list[j].engine_map = w->engine_map;
wrk->ctx_list[j].engine_map_count =
w->engine_map_count;
+ } else if (w->type == LOAD_BALANCE) {
+ if (!wrk->ctx_list[j].engine_map) {
+ wsim_err("Load balancing needs an
engine map!\n");
+ return 1;
+ }
+ wrk->ctx_list[j].wants_balance =
+ w->load_balance;
}
}
wrk->ctx_list[j].targets_instance = targets;
if (flags & I915)
- wrk->ctx_list[j].wants_balance = balance;
+ wrk->ctx_list[j].wants_balance |= balance;
}
/*
@@ -1063,10 +1091,19 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
if (w->type != BATCH)
continue;
- if (wrk->ctx_list[j].engine_map && w->engine == VCS) {
+ if (wrk->ctx_list[j].engine_map &&
+ !wrk->ctx_list[j].wants_balance &&
+ (w->engine == VCS || w->engine == DEFAULT)) {
wsim_err("Batches targetting engine maps must
use explicit engines!\n");
return -1;
}
+
+ if (wrk->ctx_list[j].engine_map &&
+ wrk->ctx_list[j].wants_balance &&
+ w->engine != DEFAULT) {
+ wsim_err("Batches targetting load balanced maps
must not use explicit engines!\n");
+ return -1;
+ }
}
}
@@ -,7 +1148,8 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
break;
}
- if (!ctx->engine_map && !ctx->targets_instance)
+ if ((!ctx->engine_map && !ctx->targets_instance) ||
+
[Intel-gfx] [PATCH i-g-t 12/21] gem_wsim: Save some lines by changing to implicit NULL checking
From: Tvrtko Ursulin
We can improve the parsing loop readability a bit more by avoiding some
line breaks caused by explicit NULL checks.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index e6b7b8f5335d..4dbfc3e922a9 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -385,7 +385,7 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
igt_assert(desc);
- while ((_token = strtok_r(tstart, ",", )) != NULL) {
+ while ((_token = strtok_r(tstart, ",", ))) {
tstart = NULL;
token = strdup(_token);
igt_assert(token);
@@ -393,12 +393,11 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
valid = 0;
memset(, 0, sizeof(step));
- if ((field = strtok_r(fstart, ".", )) != NULL) {
+ if ((field = strtok_r(fstart, ".", ))) {
fstart = NULL;
if (!strcmp(field, "d")) {
- if ((field = strtok_r(fstart, ".", )) !=
- NULL) {
+ if ((field = strtok_r(fstart, ".", ))) {
tmp = atoi(field);
check_arg(tmp <= 0,
"Invalid delay at step %u!\n",
@@ -408,8 +407,7 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
goto add_step;
}
} else if (!strcmp(field, "p")) {
- if ((field = strtok_r(fstart, ".", )) !=
- NULL) {
+ if ((field = strtok_r(fstart, ".", ))) {
tmp = atoi(field);
check_arg(tmp <= 0,
"Invalid period at step
%u!\n",
@@ -420,8 +418,7 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
}
} else if (!strcmp(field, "P")) {
unsigned int nr = 0;
- while ((field = strtok_r(fstart, ".", )) !=
- NULL) {
+ while ((field = strtok_r(fstart, ".", ))) {
tmp = atoi(field);
check_arg(nr == 0 && tmp <= 0,
"Invalid context at step
%u!\n",
@@ -441,8 +438,7 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
step.type = CTX_PRIORITY;
goto add_step;
} else if (!strcmp(field, "s")) {
- if ((field = strtok_r(fstart, ".", )) !=
- NULL) {
+ if ((field = strtok_r(fstart, ".", ))) {
tmp = atoi(field);
check_arg(tmp >= 0 ||
((int)nr_steps + tmp) < 0,
@@ -453,8 +449,7 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
goto add_step;
}
} else if (!strcmp(field, "t")) {
- if ((field = strtok_r(fstart, ".", )) !=
- NULL) {
+ if ((field = strtok_r(fstart, ".", ))) {
tmp = atoi(field);
check_arg(tmp < 0,
"Invalid throttle at step
%u!\n",
@@ -464,8 +459,7 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
goto add_step;
}
} else if (!strcmp(field, "q")) {
- if ((field = strtok_r(fstart, ".", )) !=
- NULL) {
+ if ((field = strtok_r(fstart, ".", ))) {
tmp = atoi(field);
check_arg(tmp < 0,
"Invalid qd throttle at step
%u!\n",
@@ -475,8 +469,7 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
goto add_step;
}
[Intel-gfx] [PATCH i-g-t 11/21] gem_wsim: Engine map support
From: Tvrtko Ursulin
Support new i915 uAPI for configuring contexts with engine maps.
Please refer to the README file for more detailed explanation.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 212 ++---
benchmarks/wsim/README | 17 +++-
2 files changed, 192 insertions(+), 37 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index f654decb24cc..e6b7b8f5335d 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -57,6 +57,7 @@
#include "ewma.h"
enum intel_engine_id {
+ DEFAULT,
RCS,
BCS,
VCS,
@@ -81,7 +82,8 @@ enum w_type
SW_FENCE,
SW_FENCE_SIGNAL,
CTX_PRIORITY,
- PREEMPTION
+ PREEMPTION,
+ ENGINE_MAP
};
struct deps
@@ -115,6 +117,10 @@ struct w_step
int throttle;
int fence_signal;
int priority;
+ struct {
+ unsigned int engine_map_count;
+ enum intel_engine_id *engine_map;
+ };
};
/* Implementation details */
@@ -142,6 +148,8 @@ DECLARE_EWMA(uint64_t, rt, 4, 2)
struct ctx {
uint32_t id;
int priority;
+ unsigned int engine_map_count;
+ enum intel_engine_id *engine_map;
bool targets_instance;
bool wants_balance;
unsigned int static_vcs;
@@ -200,10 +208,10 @@ struct workload
int fd;
bool first;
unsigned int num_engines;
- unsigned int engine_map[5];
+ unsigned int engine_map[NUM_ENGINES];
uint64_t t_prev;
- uint64_t prev[5];
- double busy[5];
+ uint64_t prev[NUM_ENGINES];
+ double busy[NUM_ENGINES];
} busy_balancer;
};
@@ -234,6 +242,7 @@ static int fd;
#define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x)
static const char *ring_str_map[NUM_ENGINES] = {
+ [DEFAULT] = "DEFAULT",
[RCS] = "RCS",
[BCS] = "BCS",
[VCS] = "VCS",
@@ -330,6 +339,37 @@ static int str_to_engine(const char *str)
return -1;
}
+static int parse_engine_map(struct w_step *step, const char *_str)
+{
+ char *token, *tctx = NULL, *tstart = (char *)_str;
+
+ while ((token = strtok_r(tstart, "|", ))) {
+ enum intel_engine_id engine;
+
+ tstart = NULL;
+
+ if (!strcmp(token, "DEFAULT"))
+ return -1;
+ else if (!strcmp(token, "VCS"))
+ return -1;
+
+ engine = str_to_engine(token);
+ if ((int)engine < 0)
+ return -1;
+
+ if (engine != VCS1 && engine != VCS2)
+ return -1; /* TODO */
+
+ step->engine_map_count++;
+ step->engine_map = realloc(step->engine_map,
+ step->engine_map_count *
+ sizeof(step->engine_map[0]));
+ step->engine_map[step->engine_map_count - 1] = engine;
+ }
+
+ return 0;
+}
+
static struct workload *
parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w)
{
@@ -448,6 +488,33 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
} else if (!strcmp(field, "f")) {
step.type = SW_FENCE;
goto add_step;
+ } else if (!strcmp(field, "M")) {
+ unsigned int nr = 0;
+ while ((field = strtok_r(fstart, ".", )) !=
+ NULL) {
+ tmp = atoi(field);
+ check_arg(nr == 0 && tmp <= 0,
+ "Invalid context at step
%u!\n",
+ nr_steps);
+ check_arg(nr > 1,
+ "Invalid engine map format at
step %u!\n",
+ nr_steps);
+
+ if (nr == 0) {
+ step.context = tmp;
+ } else {
+ tmp = parse_engine_map(,
+ field);
+ check_arg(tmp < 0,
+ "Invalid engine map
list at step %u!\n",
+ nr_steps);
+ }
+
+ nr++;
+ }
+
+
[Intel-gfx] [PATCH i-g-t 17/21] gem_wsim: Infinite batch support
From: Tvrtko Ursulin
For simulating frame split workloads it is useful to express a batch which
ends at the same time as the parallel submission on the respective bonded
engine. For this we add support for infinite batch durations and the batch
terminate command ('T'). Syntax looks like this:
1.RCS.*.0.0
T.-1
First step starts an infinite batch, and second command terminates the
infinite batch with the usual relative workload step addressing.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 119 +++--
benchmarks/wsim/README | 9 +-
benchmarks/wsim/frame-split-60fps.wsim | 6 +-
3 files changed, 102 insertions(+), 32 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index cc6f4a742c12..97821b723b02 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -86,6 +86,7 @@ enum w_type
ENGINE_MAP,
LOAD_BALANCE,
BOND,
+ TERMINATE,
};
struct deps
@@ -113,6 +114,7 @@ struct w_step
unsigned int context;
unsigned int engine;
struct duration duration;
+ bool unbound_duration;
struct deps data_deps;
struct deps fence_deps;
int emit_fence;
@@ -143,7 +145,7 @@ struct w_step
struct drm_i915_gem_execbuffer2 eb;
struct drm_i915_gem_exec_object2 *obj;
- struct drm_i915_gem_relocation_entry reloc[4];
+ struct drm_i915_gem_relocation_entry reloc[5];
unsigned long bb_sz;
uint32_t bb_handle;
uint32_t *seqno_value;
@@ -153,6 +155,7 @@ struct w_step
uint32_t *rt1_address;
uint32_t *latch_value;
uint32_t *latch_address;
+ uint32_t *recursive_bb_start;
};
DECLARE_EWMA(uint64_t, rt, 4, 2)
@@ -491,6 +494,10 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
step.type = ENGINE_MAP;
goto add_step;
+ } else if (!strcmp(field, "T")) {
+ int_field(TERMINATE, target,
+ tmp >= 0 || ((int)nr_steps + tmp) < 0,
+ "Invalid terminate target at step
%u!\n");
} else if (!strcmp(field, "X")) {
unsigned int nr = 0;
while ((field = strtok_r(fstart, ".", ))) {
@@ -605,23 +612,28 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
fstart = NULL;
- tmpl = strtol(field, , 10);
- check_arg(tmpl <= 0 || tmpl == LONG_MIN ||
- tmpl == LONG_MAX,
- "Invalid duration at step %u!\n", nr_steps);
- step.duration.min = tmpl;
-
- if (sep && *sep == '-') {
- tmpl = strtol(sep + 1, NULL, 10);
- check_arg(tmpl <= 0 ||
- tmpl <= step.duration.min ||
- tmpl == LONG_MIN ||
+ if (field[0] == '*') {
+ step.unbound_duration = true;
+ } else {
+ tmpl = strtol(field, , 10);
+ check_arg(tmpl <= 0 || tmpl == LONG_MIN ||
tmpl == LONG_MAX,
- "Invalid duration range at step
%u!\n",
+ "Invalid duration at step %u!\n",
nr_steps);
- step.duration.max = tmpl;
- } else {
- step.duration.max = step.duration.min;
+ step.duration.min = tmpl;
+
+ if (sep && *sep == '-') {
+ tmpl = strtol(sep + 1, NULL, 10);
+ check_arg(tmpl <= 0 ||
+ tmpl <= step.duration.min ||
+ tmpl == LONG_MIN ||
+ tmpl == LONG_MAX,
+ "Invalid duration range at step
%u!\n",
+ nr_steps);
+ step.duration.max = tmpl;
+ } else {
+ step.duration.max = step.duration.min;
+ }
}
valid++;
@@ -781,7 +793,7 @@ init_bb(struct w_step *w, unsigned int flags)
unsigned int i;
uint32_t *ptr;
- if (!arb_period)
+ if (w->unbound_duration || !arb_period)
[Intel-gfx] [PATCH i-g-t 21/21] tests/i915_query: Engine discovery tests
From: Tvrtko Ursulin
Test the new engine discovery query.
Signed-off-by: Tvrtko Ursulin
---
tests/i915/i915_query.c | 247
1 file changed, 247 insertions(+)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 7d0c0e3a061c..ecbec3ae141d 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid)
free(topo_info);
}
+static bool query_engine_info_supported(int fd)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_ENGINE_INFO,
+ };
+
+ return __i915_query_items(fd, , 1) == 0 && item.length > 0;
+}
+
+static void engines_invalid(int fd)
+{
+ struct drm_i915_query_engine_info *engines;
+ struct drm_i915_query_item item;
+ unsigned int len;
+
+ /* Flags is MBZ. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.flags = 1;
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ /* Length not zero and not greater or equal required size. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = 1;
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ /* Query correct length. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ i915_query_items(fd, , 1);
+ igt_assert(item.length >= 0);
+ len = item.length;
+
+ engines = malloc(len);
+ igt_assert(engines);
+
+ /* Ivalid pointer. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EFAULT);
+
+ /* All fields in engines query are MBZ and only filled by the kernel. */
+
+ memset(engines, 0, len);
+ engines->num_engines = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ memset(engines, 0, len);
+ engines->rsvd[0] = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ memset(engines, 0, len);
+ engines->rsvd[1] = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ memset(engines, 0, len);
+ engines->rsvd[2] = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ free(engines);
+
+ igt_assert(len <= 4096);
+ engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON,
+ -1, 0);
+ igt_assert(engines != MAP_FAILED);
+
+ /* PROT_NONE is similar to unmapped area. */
+ memset(engines, 0, len);
+ igt_assert_eq(mprotect(engines, len, PROT_NONE), 0);
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EFAULT);
+ igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0);
+
+ /* Read-only so kernel cannot fill the data back. */
+ memset(engines, 0, len);
+ igt_assert_eq(mprotect(engines, len, PROT_READ), 0);
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EFAULT);
+
+ munmap(engines, 4096);
+}
+
+static bool
+has_engine(struct drm_i915_query_engine_info *engines,
+ unsigned class, unsigned instance)
+{
+ unsigned int i;
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct drm_i915_engine_info *engine =
+ (struct drm_i915_engine_info *)>engines[i];
+
+ if (engine->engine.engine_class == class &&
+ engine->engine.engine_instance == instance)
+ return true;
+ }
+
+ return false;
+}
+
+static void engines(int fd)
+{
+ struct drm_i915_query_engine_info *engines;
+ struct drm_i915_query_item item;
+ unsigned int len, i;
+
+ engines =
[Intel-gfx] [PATCH i-g-t 15/21] gem_wsim: Engine bond command
From: Tvrtko Ursulin
Engine bonds are an i915 uAPI applicable to load balanced contexts with
engine map. They allow expression rules of engine selection between two
contexts when submissions are also tied with submit fences.
Please refer to the README for a more detailed description.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 107 ++---
benchmarks/wsim/README | 50 +++
2 files changed, 150 insertions(+), 7 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index b610a603f7b0..cc6f4a742c12 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -85,6 +85,7 @@ enum w_type
PREEMPTION,
ENGINE_MAP,
LOAD_BALANCE,
+ BOND,
};
struct deps
@@ -100,6 +101,11 @@ struct w_arg {
int prio;
};
+struct bond {
+ uint64_t mask;
+ enum intel_engine_id master;
+};
+
struct w_step
{
/* Workload step metadata */
@@ -123,6 +129,10 @@ struct w_step
enum intel_engine_id *engine_map;
};
bool load_balance;
+ struct {
+ uint64_t bond_mask;
+ enum intel_engine_id bond_master;
+ };
};
/* Implementation details */
@@ -152,6 +162,8 @@ struct ctx {
int priority;
unsigned int engine_map_count;
enum intel_engine_id *engine_map;
+ unsigned int bond_count;
+ struct bond *bonds;
bool targets_instance;
bool wants_balance;
unsigned int static_vcs;
@@ -522,6 +534,40 @@ parse_workload(struct w_arg *arg, unsigned int flags,
struct workload *app_w)
step.type = LOAD_BALANCE;
goto add_step;
+ } else if (!strcmp(field, "b")) {
+ unsigned int nr = 0;
+ while ((field = strtok_r(fstart, ".", ))) {
+ tmp = atoi(field);
+ check_arg(nr == 0 && tmp <= 0,
+ "Invalid context at step
%u!\n",
+ nr_steps);
+ check_arg(nr == 1 &&
+ (tmp < -1 || tmp == 0),
+ "Invalid siblings mask at
step %u!\n",
+ nr_steps);
+ check_arg(nr > 2,
+ "Invalid bond format at step
%u!\n",
+ nr_steps);
+
+ if (nr == 0) {
+ step.context = tmp;
+ } else if (nr == 1) {
+ step.bond_mask = tmp;
+ } else if (nr == 2) {
+ tmp = str_to_engine(field);
+ check_arg(tmp <= 0 ||
+ tmp == VCS ||
+ tmp == DEFAULT,
+ "Invalid master
engine at step %u!\n",
+ nr_steps);
+ step.bond_master = tmp;
+ }
+
+ nr++;
+ }
+
+ step.type = BOND;
+ goto add_step;
}
if (!field) {
@@ -1049,6 +1095,8 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
* Transfer over engine map configuration from the workload step.
*/
for (j = 0; j < wrk->nr_ctxs; j += 2) {
+ struct ctx *ctx = >ctx_list[j];
+
bool targets = false;
bool balance = false;
@@ -1062,16 +1110,28 @@ prepare_workload(unsigned int id, struct workload *wrk,
unsigned int flags)
else
targets = true;
} else if (w->type == ENGINE_MAP) {
- wrk->ctx_list[j].engine_map = w->engine_map;
- wrk->ctx_list[j].engine_map_count =
- w->engine_map_count;
+ ctx->engine_map = w->engine_map;
+ ctx->engine_map_count = w->engine_map_count;
} else if (w->type == LOAD_BALANCE) {
- if (!wrk->ctx_list[j].engine_map)
[Intel-gfx] [PATCH i-g-t 09/21] gem_wsim: Submit fence support
From: Tvrtko Ursulin
Add support for submit fences in a way similar to how normal input fences
are handled. Eg:
1.RCS.500-1000.0.0
1.VCS1.3000.s-1.0
1.VCS2.3000.s-2.0
Submit fences are signalled when the originating request enters the
submission backend.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 20
benchmarks/wsim/README | 17 +
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index f1fcef5dcfba..5245692df6eb 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -87,6 +87,7 @@ enum w_type
struct deps
{
int nr;
+ bool submit_fence;
int *list;
};
@@ -253,17 +254,23 @@ parse_dependencies(unsigned int nr_steps, struct w_step
*w, char *_desc)
w->data_deps.list == w->fence_deps.list);
while ((token = strtok_r(tstart, "/", )) != NULL) {
+ bool submit_fence = false;
char *str = token;
struct deps *deps;
int dep;
tstart = NULL;
- if (strlen(token) > 1 && token[0] == 'f') {
+ if (str[0] == '-' || (str[0] >= '0' && str[0] <= '9')) {
+ deps = >data_deps;
+ } else {
+ if (str[0] == 's')
+ submit_fence = true;
+ else if (str[0] != 'f')
+ return -1;
+
deps = >fence_deps;
str++;
- } else {
- deps = >data_deps;
}
dep = atoi(str);
@@ -281,6 +288,7 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w,
char *_desc)
sizeof(*deps->list) * deps->nr);
igt_assert(deps->list);
deps->list[deps->nr - 1] = dep;
+ deps->submit_fence = submit_fence;
}
}
@@ -1921,7 +1929,11 @@ do_eb(struct workload *wrk, struct w_step *w, enum
intel_engine_id engine,
igt_assert(tgt >= 0 && tgt < w->idx);
igt_assert(wrk->steps[tgt].emit_fence > 0);
- w->eb.flags |= I915_EXEC_FENCE_IN;
+ if (w->fence_deps.submit_fence)
+ w->eb.flags |= I915_EXEC_FENCE_SUBMIT;
+ else
+ w->eb.flags |= I915_EXEC_FENCE_IN;
+
w->eb.rsvd2 = wrk->steps[tgt].emit_fence;
}
diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README
index 205cd6c93afb..4786f116b4ac 100644
--- a/benchmarks/wsim/README
+++ b/benchmarks/wsim/README
@@ -114,6 +114,23 @@ runnable. When the second RCS batch completes the
standalone fence is signaled
which allows the two VCS batches to be executed. Finally we wait until the both
VCS batches have completed before starting the (optional) next iteration.
+Submit fences
+-
+
+Submit fences are a type of input fence which are signalled when the
originating
+batch buffer is submitted to the GPU. (In contrary to normal sync fences, which
+are signalled when completed.)
+
+Submit fences have the identical syntax as the sync fences with the lower-case
+'s' being used to select them. Eg:
+
+ 1.RCS.500-1000.0.0
+ 1.VCS1.3000.s-1.0
+ 1.VCS2.3000.s-2.0
+
+Here VCS1 and VCS2 batches will only be submitted for executing once the RCS
+batch enters the GPU.
+
Context priority
--
2.19.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 06/21] gem_wsim: Use IGT uapi headers
From: Tvrtko Ursulin
We are moving towards bumping the uAPI headers more often instead of using
too much local struct/ioctl/param definitions since the latter are more
challenging for rebase and maintenance.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 1084e95fa8df..609e64f3d9c8 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -41,7 +41,6 @@
#include
#include
-
#include "intel_chipset.h"
#include "intel_reg.h"
#include "drm.h"
@@ -57,9 +56,6 @@
#include "ewma.h"
-#define LOCAL_I915_EXEC_FENCE_IN (1<<16)
-#define LOCAL_I915_EXEC_FENCE_OUT (1<<17)
-
enum intel_engine_id {
RCS,
BCS,
@@ -864,7 +860,7 @@ eb_update_flags(struct w_step *w, enum intel_engine_id
engine,
igt_assert(w->emit_fence <= 0);
if (w->emit_fence)
- w->eb.flags |= LOCAL_I915_EXEC_FENCE_OUT;
+ w->eb.flags |= I915_EXEC_FENCE_OUT;
}
static struct drm_i915_gem_exec_object2 *
@@ -1993,16 +1989,16 @@ do_eb(struct workload *wrk, struct w_step *w, enum
intel_engine_id engine,
igt_assert(tgt >= 0 && tgt < w->idx);
igt_assert(wrk->steps[tgt].emit_fence > 0);
- w->eb.flags |= LOCAL_I915_EXEC_FENCE_IN;
+ w->eb.flags |= I915_EXEC_FENCE_IN;
w->eb.rsvd2 = wrk->steps[tgt].emit_fence;
}
- if (w->eb.flags & LOCAL_I915_EXEC_FENCE_OUT)
+ if (w->eb.flags & I915_EXEC_FENCE_OUT)
gem_execbuf_wr(fd, >eb);
else
gem_execbuf(fd, >eb);
- if (w->eb.flags & LOCAL_I915_EXEC_FENCE_OUT) {
+ if (w->eb.flags & I915_EXEC_FENCE_OUT) {
w->emit_fence = w->eb.rsvd2 >> 32;
igt_assert(w->emit_fence > 0);
}
--
2.19.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 02/21] headers: bump
From: Tvrtko Ursulin
Catch up to drm-tip headers.
Signed-off-by: Tvrtko Ursulin
---
include/drm-uapi/amdgpu_drm.h | 52 +++-
include/drm-uapi/drm.h | 36 ++
include/drm-uapi/drm_mode.h | 4 +-
include/drm-uapi/i915_drm.h | 209 +++-
include/drm-uapi/lima_drm.h | 169 ++
include/drm-uapi/msm_drm.h | 14 +++
include/drm-uapi/nouveau_drm.h | 51
include/drm-uapi/panfrost_drm.h | 142 ++
include/drm-uapi/v3d_drm.h | 28 +
9 files changed, 699 insertions(+), 6 deletions(-)
create mode 100644 include/drm-uapi/lima_drm.h
create mode 100644 include/drm-uapi/panfrost_drm.h
diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index be84e43c1e19..4788730dbe78 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -210,6 +210,9 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
/* indicate some job from this context once cause gpu hang */
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
+/* indicate some errors are detected by RAS */
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
/* Context priority level */
#define AMDGPU_CTX_PRIORITY_UNSET -2048
@@ -272,13 +275,14 @@ union drm_amdgpu_vm {
/* sched ioctl */
#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
+#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
struct drm_amdgpu_sched_in {
/* AMDGPU_SCHED_OP_* */
__u32 op;
__u32 fd;
__s32 priority;
- __u32 flags;
+ __u32 ctx_id;
};
union drm_amdgpu_sched {
@@ -523,6 +527,9 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
+#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT0x08
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@@ -565,6 +572,11 @@ union drm_amdgpu_cs {
* caches (L2/vL1/sL1/I$). */
#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
+/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
+ * This will reset wave ID counters for the IB.
+ */
+#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
+
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@@ -598,6 +610,12 @@ struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
+struct drm_amdgpu_cs_chunk_syncobj {
+ __u32 handle;
+ __u32 flags;
+ __u64 point;
+};
+
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD2
@@ -673,6 +691,7 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
/* Subquery id: Query DMCU firmware version */
#define AMDGPU_INFO_FW_DMCU 0x12
+ #define AMDGPU_INFO_FW_TA 0x13
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED0x0f
/* the used VRAM size */
@@ -726,6 +745,37 @@ struct drm_amdgpu_cs_chunk_data {
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
+/* query ras mask of enabled features*/
+#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
+
+/* RAS MASK: UMC (VRAM) */
+#define AMDGPU_INFO_RAS_ENABLED_UMC(1 << 0)
+/* RAS MASK: SDMA */
+#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
+/* RAS MASK: GFX */
+#define AMDGPU_INFO_RAS_ENABLED_GFX(1 << 2)
+/* RAS MASK: MMHUB */
+#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
+/* RAS MASK: ATHUB */
+#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
+/* RAS MASK: PCIE */
+#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
+/* RAS MASK: HDP */
+#define AMDGPU_INFO_RAS_ENABLED_HDP(1 << 6)
+/* RAS MASK: XGMI */
+#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
+/* RAS MASK: DF */
+#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
+/* RAS MASK: SMN */
+#define AMDGPU_INFO_RAS_ENABLED_SMN(1 << 9)
+/* RAS MASK: SEM */
+#define AMDGPU_INFO_RAS_ENABLED_SEM(1 << 10)
+/* RAS MASK: MP0 */
+#define AMDGPU_INFO_RAS_ENABLED_MP0(1 << 11)
+/* RAS MASK: MP1 */
+#define AMDGPU_INFO_RAS_ENABLED_MP1(1 << 12)
+/* RAS MASK: FUSE */
+#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
index
[Intel-gfx] [PATCH i-g-t 04/21] trace.pl: Virtual engine preemption support
From: Tvrtko Ursulin
Use the 'completed?' tracepoint field to detect more robustly when a
request has been preempted and remove it from the engine database if so.
Otherwise the script can hit a scenario where the same global seqno will
be mentioned multiple times (on an engine seqno) which aborts processing.
Signed-off-by: Tvrtko Ursulin
---
scripts/trace.pl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index 6cc332bb6e2a..cb7cc46df22e 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -483,17 +483,17 @@ while (<>) {
$ringmap{$rings{$ring}} = $ring;
$db{$key} = \%req;
} elsif ($tp_name eq 'i915:i915_request_out:') {
- my $gkey;
-
die unless exists $ctxengines{$ctx};
- $gkey = db_key($ctxengines{$ctx}, $ctx, $seqno);
-
if ($tp{'completed?'}) {
+ my $gkey;
+
die unless exists $db{$key};
die unless exists $db{$key}->{'start'};
die if exists $db{$key}->{'end'};
+ $gkey = db_key($ctxengines{$ctx}, $ctx, $seqno);
+
$db{$key}->{'end'} = $time;
$db{$key}->{'notify'} = $notify{$gkey}
if exists $notify{$gkey};
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 00/21] Media scalability tooling
From: Tvrtko Ursulin Mostly work to support Virtual Engine in trace.pl and gem_wsim complementing the set of IGTs written by Chris. Also includes trace.pl update for after engine seqno removal and engine discovery tests. Altogether it allows benchamrking and tracing the simulated media workloads in combination with Virtual Engine (and frame split) on Gen9, but also needs follow up work to add support for new Icelake vcs2 engine. Tvrtko Ursulin (21): scripts/trace.pl: Fix after intel_engine_notify removal headers: bump trace.pl: Virtual engine support trace.pl: Virtual engine preemption support wsim/media-bench: i915 balancing gem_wsim: Use IGT uapi headers gem_wsim: Factor out common error handling gem_wsim: More wsim_err gem_wsim: Submit fence support gem_wsim: Extract str to engine lookup gem_wsim: Engine map support gem_wsim: Save some lines by changing to implicit NULL checking gem_wsim: Compact int command parsing with a macro gem_wsim: Engine map load balance command gem_wsim: Engine bond command gem_wsim: Some more example workloads gem_wsim: Infinite batch support gem_wsim: Command line switch for specifying low slice count workloads gem_wsim: Per context SSEU control gem_wsim: Allow RCS virtual engine with SSEU control tests/i915_query: Engine discovery tests benchmarks/gem_wsim.c | 1207 ++- benchmarks/wsim/README | 134 +- benchmarks/wsim/frame-split-60fps.wsim | 18 + benchmarks/wsim/high-composited-game.wsim | 11 + benchmarks/wsim/media-1080p-player.wsim |5 + benchmarks/wsim/medium-composited-game.wsim |9 + include/drm-uapi/amdgpu_drm.h | 52 +- include/drm-uapi/drm.h | 36 + include/drm-uapi/drm_mode.h |4 +- include/drm-uapi/i915_drm.h | 209 +++- include/drm-uapi/lima_drm.h | 169 +++ include/drm-uapi/msm_drm.h | 14 + include/drm-uapi/nouveau_drm.h | 51 + include/drm-uapi/panfrost_drm.h | 142 +++ include/drm-uapi/v3d_drm.h | 28 + scripts/media-bench.pl |9 +- scripts/trace.pl| 318 +++-- tests/i915/i915_query.c | 247 18 files changed, 2246 insertions(+), 417 deletions(-) create mode 100644 benchmarks/wsim/frame-split-60fps.wsim create mode 100644 benchmarks/wsim/high-composited-game.wsim create mode 100644 benchmarks/wsim/media-1080p-player.wsim create mode 100644 benchmarks/wsim/medium-composited-game.wsim create mode 100644 include/drm-uapi/lima_drm.h create mode 100644 include/drm-uapi/panfrost_drm.h -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 01/21] scripts/trace.pl: Fix after intel_engine_notify removal
From: Tvrtko Ursulin
After the removal of engine global seqnos and the corresponding
intel_engine_notify tracepoints the script needs to be adjusted to cope
with the new state of things.
To keep working it switches over using the dma_fence:dma_fence_signaled:
tracepoint and keeps one extra internal map to connect the ctx-seqno pairs
with engines.
It also needs to key the completion events on the full engine/ctx/seqno
tokens, and adjust correspondingly the timeline sorting logic.
v2:
* Do not use late notifications (received after context complete) when
splitting up coalesced requests. They are now much more likely and can
not be used.
Signed-off-by: Tvrtko Ursulin
---
scripts/trace.pl | 82
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index 18f9f3b18396..95dc3a645e8e 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -27,7 +27,8 @@ use warnings;
use 5.010;
my $gid = 0;
-my (%db, %queue, %submit, %notify, %rings, %ctxdb, %ringmap, %reqwait,
%ctxtimelines);
+my (%db, %queue, %submit, %notify, %rings, %ctxdb, %ringmap, %reqwait,
+%ctxtimelines, %ctxengines);
my @freqs;
my $max_items = 3000;
@@ -66,7 +67,7 @@ Notes:
i915:i915_request_submit, \
i915:i915_request_in, \
i915:i915_request_out, \
- i915:intel_engine_notify, \
+ dma_fence:dma_fence_signaled, \
i915:i915_request_wait_begin, \
i915:i915_request_wait_end \
[command-to-be-profiled]
@@ -161,7 +162,7 @@ sub arg_trace
'i915:i915_request_submit',
'i915:i915_request_in',
'i915:i915_request_out',
- 'i915:intel_engine_notify',
+ 'dma_fence:dma_fence_signaled',
'i915:i915_request_wait_begin',
'i915:i915_request_wait_end' );
@@ -312,13 +313,6 @@ sub db_key
return $ring . '/' . $ctx . '/' . $seqno;
}
-sub global_key
-{
- my ($ring, $seqno) = @_;
-
- return $ring . '/' . $seqno;
-}
-
sub sanitize_ctx
{
my ($ctx, $ring) = @_;
@@ -419,6 +413,8 @@ while (<>) {
$req{'ring'} = $ring;
$req{'seqno'} = $seqno;
$req{'ctx'} = $ctx;
+ die if exists $ctxengines{$ctx} and $ctxengines{$ctx} ne $ring;
+ $ctxengines{$ctx} = $ring;
$ctxtimelines{$ctx . '/' . $ring} = 1;
$req{'name'} = $ctx . '/' . $seqno;
$req{'global'} = $tp{'global'};
@@ -429,16 +425,29 @@ while (<>) {
$ringmap{$rings{$ring}} = $ring;
$db{$key} = \%req;
} elsif ($tp_name eq 'i915:i915_request_out:') {
- my $gkey = global_key($ring, $tp{'global'});
+ my $gkey;
+
+ die unless exists $ctxengines{$ctx};
+
+ $gkey = db_key($ctxengines{$ctx}, $ctx, $seqno);
+
+ if ($tp{'completed?'}) {
+ die unless exists $db{$key};
+ die unless exists $db{$key}->{'start'};
+ die if exists $db{$key}->{'end'};
+
+ $db{$key}->{'end'} = $time;
+ $db{$key}->{'notify'} = $notify{$gkey}
+ if exists $notify{$gkey};
+ } else {
+ delete $db{$key};
+ }
+ } elsif ($tp_name eq 'dma_fence:dma_fence_signaled:') {
+ my $gkey;
- die unless exists $db{$key};
- die unless exists $db{$key}->{'start'};
- die if exists $db{$key}->{'end'};
+ die unless exists $ctxengines{$tp{'context'}};
- $db{$key}->{'end'} = $time;
- $db{$key}->{'notify'} = $notify{$gkey} if exists $notify{$gkey};
- } elsif ($tp_name eq 'i915:intel_engine_notify:') {
- my $gkey = global_key($ring, $seqno);
+ $gkey = db_key($ctxengines{$tp{'context'}}, $tp{'context'},
$tp{'seqno'});
$notify{$gkey} = $time unless exists $notify{$gkey};
} elsif ($tp_name eq 'i915:intel_gpu_freq_change:') {
@@ -452,7 +461,7 @@ while (<>) {
# find the largest seqno to be used for timeline sorting purposes.
my $max_seqno = 0;
foreach my $key (keys %db) {
- my $gkey = global_key($db{$key}->{'ring'}, $db{$key}->{'global'});
+ my $gkey = db_key($db{$key}->{'ring'}, $db{$key}->{'ctx'},
$db{$key}->{'seqno'});
die unless exists $db{$key}->{'start'};
@@ -478,14 +487,13 @@ my $key_count = scalar(keys %db);
my %engine_timelines;
-sub sortEngine {
- my $as = $db{$a}->{'global'};
- my $bs = $db{$b}->{'global'};
+sub
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD (rev4)
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD (rev4)
URL : https://patchwork.freedesktop.org/series/60403/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12985
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12985 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12985, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12985/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12985:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-icl-u3: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12985/fi-icl-u3/igt@run...@aborted.html
New tests
-
New tests have been introduced between CI_DRM_6063 and Patchwork_12985:
### New IGT tests (1) ###
* igt@i915_selftest@live_mman:
- Statuses : 38 pass(s)
- Exec time: [4.46, 57.68] s
Known issues
Here are the changes found in Patchwork_12985 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_parallel@basic:
- fi-apl-guc: [PASS][2] -> [FAIL][3] ([fdo#109474] / [fdo#110512])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@gem_exec_paral...@basic.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12985/fi-apl-guc/igt@gem_exec_paral...@basic.html
* igt@gem_exec_reloc@basic-gtt:
- fi-apl-guc: [PASS][4] -> [FAIL][5] ([fdo#109474])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@gem_exec_re...@basic-gtt.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12985/fi-apl-guc/igt@gem_exec_re...@basic-gtt.html
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [PASS][6] -> [DMESG-FAIL][7] ([fdo#110235])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12985/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_execlists:
- fi-icl-u3: [PASS][8] -> [INCOMPLETE][9] ([fdo#107713])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-icl-u3/igt@i915_selftest@live_execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12985/fi-icl-u3/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: [PASS][10] -> [INCOMPLETE][11] ([fdo#108602] /
[fdo#108744])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12985/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109474]: https://bugs.freedesktop.org/show_bug.cgi?id=109474
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110512]: https://bugs.freedesktop.org/show_bug.cgi?id=110512
Participating hosts (53 -> 42)
--
Missing(11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-skl-6260u fi-kbl-guc fi-ctg-p8600 fi-pnv-d510 fi-byt-clapper
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6063 -> Patchwork_12985
CI_DRM_6063: 44ae4003d35743cbc7883825c5fe777d136b5247 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12985: f3a02b00de822331e44bd7f08aa53ffbfcdf8f4c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f3a02b00de82 drm/i915/execlists: Minimalistic timeslicing
fac27574d0e9 drm/i915/execlists: Preempt-to-busy
fa40ebec0d94 drm/i915: Flush the execution-callbacks on retiring
fa5d8af7b06b drm/i915: Replace engine->timeline with a plain list
c964292d3f9a drm/i915: Stop retiring along engine
1637bc4b6181 drm/i915: Keep contexts pinned until after the next kernel context
switch
583bed163977 drm/i915: Rename intel_context.active to .inflight
242b3ceead01 drm/i915: Move object close under its own lock
ce78a3d23c6b drm/i915: Drop the deferred active reference
[Intel-gfx] [PATCH i-g-t 03/21] trace.pl: Virtual engine support
From: Tvrtko Ursulin
Add virtual/queue timelines to both stdout and HTML output.
A new timeline is created for each queue/virtual engine to display
associated requests in queued and runnable states. Once requests are
submitted to a real engine for executing they show up on the physical
engine timeline.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
scripts/trace.pl | 238 +--
1 file changed, 208 insertions(+), 30 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index 95dc3a645e8e..6cc332bb6e2a 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -27,11 +27,16 @@ use warnings;
use 5.010;
my $gid = 0;
-my (%db, %queue, %submit, %notify, %rings, %ctxdb, %ringmap, %reqwait,
+my (%db, %vdb, %queue, %submit, %notify, %rings, %ctxdb, %ringmap, %reqwait,
%ctxtimelines, %ctxengines);
+my (%cids, %ctxmap);
+my $cid = 0;
+my %queues;
my @freqs;
-my $max_items = 3000;
+use constant VENG => '255:254';
+
+my $max_requests = 1000;
my $width_us = 32000;
my $correct_durations = 0;
my %ignore_ring;
@@ -181,21 +186,21 @@ sub arg_trace
return @_;
}
-sub arg_max_items
+sub arg_max_requests
{
my $val;
return unless scalar(@_);
- if ($_[0] eq '--max-items' or $_[0] eq '-m') {
+ if ($_[0] eq '--max-requests' or $_[0] eq '-m') {
shift @_;
$val = shift @_;
- } elsif ($_[0] =~ /--max-items=(\d+)/) {
+ } elsif ($_[0] =~ /--max-requests=(\d+)/) {
shift @_;
$val = $1;
}
- $max_items = int($val) if defined $val;
+ $max_requests = int($val) if defined $val;
return @_;
}
@@ -292,7 +297,7 @@ while (@args) {
@args = arg_avg_delay_stats(@args);
@args = arg_gpu_timeline(@args);
@args = arg_trace(@args);
- @args = arg_max_items(@args);
+ @args = arg_max_requests(@args);
@args = arg_zoom_width(@args);
@args = arg_split_requests(@args);
@args = arg_ignore_ring(@args);
@@ -324,6 +329,13 @@ sub sanitize_ctx
}
}
+sub is_veng
+{
+ my ($class, $instance) = split ':', shift;
+
+ return $instance eq '254';
+}
+
# Main input loop - parse lines and build the internal representation of the
# trace using a hash of requests and some auxilliary data structures.
my $prev_freq = 0;
@@ -366,6 +378,7 @@ while (<>) {
$ctx = $tp{'ctx'};
$orig_ctx = $ctx;
$ctx = sanitize_ctx($ctx, $ring);
+ $ring = VENG if is_veng($ring);
$key = db_key($ring, $ctx, $seqno);
}
}
@@ -374,6 +387,7 @@ while (<>) {
my %rw;
next if exists $reqwait{$key};
+ die if $ring eq VENG and not exists $queues{$ctx};
$rw{'key'} = $key;
$rw{'ring'} = $ring;
@@ -382,9 +396,19 @@ while (<>) {
$rw{'start'} = $time;
$reqwait{$key} = \%rw;
} elsif ($tp_name eq 'i915:i915_request_wait_end:') {
- next unless exists $reqwait{$key};
+ die if $ring eq VENG and not exists $queues{$ctx};
- $reqwait{$key}->{'end'} = $time;
+ if (exists $reqwait{$key}) {
+ $reqwait{$key}->{'end'} = $time;
+ } else { # Virtual engine
+ my $vkey = db_key(VENG, $ctx, $seqno);
+
+ die unless exists $reqwait{$vkey};
+
+ # If the wait started on the virtual engine, attribute
+ # it to it completely.
+ $reqwait{$vkey}->{'end'} = $time;
+ }
} elsif ($tp_name eq 'i915:i915_request_add:') {
if (exists $queue{$key}) {
$ctxdb{$orig_ctx}++;
@@ -395,19 +419,52 @@ while (<>) {
}
$queue{$key} = $time;
+ if ($ring eq VENG and not exists $queues{$ctx}) {
+ $queues{$ctx} = 1 ;
+ $cids{$ctx} = $cid++;
+ $ctxmap{$cids{$ctx}} = $ctx;
+ }
} elsif ($tp_name eq 'i915:i915_request_submit:') {
die if exists $submit{$key};
die unless exists $queue{$key};
+ die if $ring eq VENG and not exists $queues{$ctx};
$submit{$key} = $time;
} elsif ($tp_name eq 'i915:i915_request_in:') {
+ my ($q, $s);
my %req;
# preemption
delete $db{$key} if exists $db{$key};
- die unless exists $queue{$key};
- die unless exists $submit{$key};
+ unless (exists $queue{$key}) {
+ # Virtual engine
+ my $vkey = db_key(VENG, $ctx, $seqno);
+ my %req;
+
+
[Intel-gfx] [PATCH] drm/i915: Fix skl plane scaling for planner YUV buffers
From: Lukas Rusak
Plane scaling for YUV planar formats should be max 2 times.
Cc: Maarten Lankhorst
Cc: Juha-pekka Heikkila
Cc: Shashank Sharma
Signed-off-by: Lukas Rusak
---
drivers/gpu/drm/i915/intel_display.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a351c8e219ba..2ac0a55a9c9f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13897,7 +13897,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int max_scale, mult;
+ int max_scale, mult, remainder;
int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
if (!crtc_state->base.enable)
@@ -13914,12 +13914,15 @@ skl_max_scale(const struct intel_crtc_state
*crtc_state,
/*
* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
-*or
-*cdclk/crtc_clock
+* for planar YUV formats: 2
+* or
+* for other formats: close to 3 but not 3, -1 is for that purpose
+* or
+* cdclk/crtc_clock
*/
mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
- tmpclk1 = (1 << 16) * mult - 1;
+ remainder = is_planar_yuv_format(pixel_format) ? 0 : 1;
+ tmpclk1 = (1 << 16) * mult - remainder;
tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
max_scale = min(tmpclk1, tmpclk2);
--
2.17.1
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD (rev4)
== Series Details == Series: series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD (rev4) URL : https://patchwork.freedesktop.org/series/60403/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD Okay! Commit: drm/i915: Rearrange i915_scheduler.c Okay! Commit: drm/i915: Pass i915_sched_node around internally Okay! Commit: drm/i915: Check for no-op priority changes first Okay! Commit: drm/i915: Bump signaler priority on adding a waiter Okay! Commit: drm/i915: Convert inconsistent static engine tables into an init error Okay! Commit: drm/i915: Seal races between async GPU cancellation, retirement and signaling Okay! Commit: dma-fence: Refactor signaling for manual invocation Okay! Commit: drm/i915: Restore control over ppgtt for context creation ABI Okay! Commit: drm/i915: Allow a context to define its set of engines +drivers/gpu/drm/i915/i915_utils.h:87:13: error: incorrect type in conditional +drivers/gpu/drm/i915/i915_utils.h:87:13: error: undefined identifier '__builtin_mul_overflow' +drivers/gpu/drm/i915/i915_utils.h:87:13:got void +drivers/gpu/drm/i915/i915_utils.h:87:13: warning: call with no type! +drivers/gpu/drm/i915/i915_utils.h:90:13: error: incorrect type in conditional +drivers/gpu/drm/i915/i915_utils.h:90:13: error: undefined identifier '__builtin_add_overflow' +drivers/gpu/drm/i915/i915_utils.h:90:13:got void +drivers/gpu/drm/i915/i915_utils.h:90:13: warning: call with no type! -drivers/gpu/drm/i915/selftests/../i915_utils.h:184:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_utils.h:218:16: warning: expression using sizeof(void) +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: not a function +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: not a function +./include/linux/overflow.h:287:13:got void Commit: drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[] Okay! Commit: drm/i915: Re-expose SINGLE_TIMELINE flags for context creation Okay! Commit: drm/i915: Allow userspace to clone contexts on creation +drivers/gpu/drm/i915/i915_gem_context.c:1859:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1860:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1861:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1862:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1863:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1864:17: error: bad integer constant expression -drivers/gpu/drm/i915/i915_utils.h:87:13: warning: call with no type! -drivers/gpu/drm/i915/i915_utils.h:90:13: warning: call with no type! -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1266:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1266:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:454:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:571:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:571:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:693:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:693:33: warning: expression using sizeof(void) +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: not a function -./include/linux/overflow.h:285:13: warning: call with no type! +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: not a function -./include/linux/overflow.h:287:13: warning: call with no type! +./include/linux/overflow.h:287:13:got void -./include/linux/slab.h:666:13: warning: call with no type! Commit: drm/i915: Load balancing across a virtual engine +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:285:13: warning: call with no type! +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: undefined identifier '__builtin_add_overflow' +./include/linux/overflow.h:287:13:got void +./include/linux/overflow.h:287:13: warning: call with no type! +./include/linux/slab.h:666:13: error: not a function Commit: drm/i915: Apply an execution_mask to the
Re: [Intel-gfx] [PATCH] dma-fence: Refactor signaling for manual invocation
On 08/05/2019 12:25, Chris Wilson wrote:
Move the duplicated code within dma-fence.c into the header for wider
reuse.
For this one I am not sure whether to go with static inlines or
EXPORT_SYMBOL the helpers.
Also you'll need to mention that in the same patch you are optimized the
whole-list-unlink. Presumably, when this goes to dri-devel one day.
But overall it makes sense to me to allow controlled fine control of the
fence signaling from dma-fence core.
Regards,
Tvrtko
Signed-off-by: Chris Wilson
---
drivers/dma-buf/Makefile| 10 +-
drivers/dma-buf/dma-fence-trace.c | 28 +++
drivers/dma-buf/dma-fence.c | 32 +--
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 30 ---
include/linux/dma-fence-types.h | 248 +++
include/linux/dma-fence.h | 251 +++-
6 files changed, 321 insertions(+), 278 deletions(-)
create mode 100644 drivers/dma-buf/dma-fence-trace.c
create mode 100644 include/linux/dma-fence-types.h
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 1f006e083eb9..56e579878f26 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,5 +1,11 @@
-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
-reservation.o seqno-fence.o
+obj-y := \
+ dma-buf.o \
+ dma-fence.o \
+ dma-fence-array.o \
+ dma-fence-chain.o \
+ dma-fence-trace.o \
+ reservation.o \
+ seqno-fence.o
obj-$(CONFIG_SYNC_FILE) += sync_file.o
obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o
obj-$(CONFIG_UDMABUF) += udmabuf.o
diff --git a/drivers/dma-buf/dma-fence-trace.c
b/drivers/dma-buf/dma-fence-trace.c
new file mode 100644
index ..eb6f282be4c0
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-trace.c
@@ -0,0 +1,28 @@
+/*
+ * Fence mechanism for dma-buf and to allow for asynchronous dma access
+ *
+ * Copyright (C) 2012 Canonical Ltd
+ * Copyright (C) 2012 Texas Instruments
+ *
+ * Authors:
+ * Rob Clark
+ * Maarten Lankhorst
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+
+#define CREATE_TRACE_POINTS
+#include
+
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 9bf06042619a..8196a179fdc2 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -24,13 +24,6 @@
#include
#include
-#define CREATE_TRACE_POINTS
-#include
-
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
-
static DEFINE_SPINLOCK(dma_fence_stub_lock);
static struct dma_fence dma_fence_stub;
@@ -136,7 +129,6 @@ EXPORT_SYMBOL(dma_fence_context_alloc);
*/
int dma_fence_signal_locked(struct dma_fence *fence)
{
- struct dma_fence_cb *cur, *tmp;
int ret = 0;
lockdep_assert_held(fence->lock);
@@ -144,7 +136,7 @@ int dma_fence_signal_locked(struct dma_fence *fence)
if (WARN_ON(!fence))
return -EINVAL;
- if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags)) {
+ if (!__dma_fence_signal(fence)) {
ret = -EINVAL;
/*
@@ -152,15 +144,10 @@ int dma_fence_signal_locked(struct dma_fence *fence)
* still run through all callbacks
*/
} else {
- fence->timestamp = ktime_get();
- set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, >flags);
- trace_dma_fence_signaled(fence);
+ __dma_fence_signal__timestamp(fence, ktime_get());
}
- list_for_each_entry_safe(cur, tmp, >cb_list, node) {
- list_del_init(>node);
- cur->func(fence, cur);
- }
+ __dma_fence_signal__notify(fence);
return ret;
}
EXPORT_SYMBOL(dma_fence_signal_locked);
@@ -185,21 +172,14 @@ int dma_fence_signal(struct dma_fence *fence)
if (!fence)
return -EINVAL;
- if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
+ if (!__dma_fence_signal(fence))
return -EINVAL;
- fence->timestamp = ktime_get();
- set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, >flags);
- trace_dma_fence_signaled(fence);
+ __dma_fence_signal__timestamp(fence, ktime_get());
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >flags)) {
- struct dma_fence_cb *cur,
[Intel-gfx] [PATCH] drm/i915: Reboot CI if forcewake fails
If the HW fail to ack a change in forcewake status, the machine is as
good as dead -- it may recover, but in reality it missed the mmio
updates and is now in a very inconsistent state. If it happens, we can't
trust the CI results (or at least the fails may be genuine but due to
the HW being dead and not the actual test!) so reboot the machine (CI
checks for a kernel taint in between each test and reboots if the
machine is tainted).
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 11 +++
drivers/gpu/drm/i915/intel_uncore.c | 8 ++--
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 419b3415370b..464369bc55ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1042,7 +1042,7 @@ void i915_reset(struct drm_i915_private *i915,
* rather than continue on into oblivion. For everyone else,
* the system should still plod along, but they have been warned!
*/
- add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
+ add_taint_for_CI(TAINT_WARN);
error:
__i915_gem_set_wedged(i915);
goto finish;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a6ec61496f1..d0257808734c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3375,4 +3375,15 @@ static inline u32 i915_scratch_offset(const struct
drm_i915_private *i915)
return i915_ggtt_offset(i915->gt.scratch);
}
+static inline void add_taint_for_CI(unsigned int taint)
+{
+ /*
+* The system is "ok", just about surviving for the user, but
+* CI results are now unreliable as the HW is very suspect.
+* CI checks the taint state after every test and will reboot
+* the machine if the kernel is tainted.
+*/
+ add_taint(taint, LOCKDEP_STILL_OK);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index d1d51e1121e2..6ec1bc97b665 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -111,9 +111,11 @@ wait_ack_set(const struct intel_uncore_forcewake_domain *d,
static inline void
fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
{
- if (wait_ack_clear(d, FORCEWAKE_KERNEL))
+ if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
intel_uncore_forcewake_domain_to_str(d->id));
+ add_taint_for_CI(TAINT_WARN); /* CI unreliable */
+ }
}
enum ack_type {
@@ -186,9 +188,11 @@ fw_domain_get(const struct intel_uncore_forcewake_domain
*d)
static inline void
fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
{
- if (wait_ack_set(d, FORCEWAKE_KERNEL))
+ if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
intel_uncore_forcewake_domain_to_str(d->id));
+ add_taint_for_CI(TAINT_WARN); /* CI unreliable */
+ }
}
static inline void
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915: Seal races between async GPU cancellation, retirement and signaling
On 08/05/2019 12:24, Chris Wilson wrote:
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In the near future that may change, and this may upset
our signaling as we can process an interrupt for that request while it
is no longer in flight.
CPU0CPU1
intel_engine_breadcrumbs_irq
(queue request completion)
i915_request_cancel_signaling
... ...
i915_request_enable_signaling
dma_fence_signal
Hence in the time it took us to drop the lock to signal the request, a
preemption event may have occurred and re-queued the request. In the
process, that request would have seen I915_FENCE_FLAG_SIGNAL clear and
so reused the rq->signal_link that was in use on CPU0, leading to bad
pointer chasing in intel_engine_breadcrumbs_irq.
A related issue was that if someone started listening for a signal on a
completed but no longer in-flight request, we missed the opportunity to
immediately signal that request.
Furthermore, as intel_contexts may be immediately released during
request retirement, in order to be entirely sure that
intel_engine_breadcrumbs_irq may no longer dereference the intel_context
(ce->signals and ce->signal_link), we must wait for irq spinlock.
In order to prevent the race, we use a bit in the fence.flags to signal
the transfer onto the signal list inside intel_engine_breadcrumbs_irq.
For simplicity, we use the DMA_FENCE_FLAG_SIGNALED_BIT as it then
quickly signals to any outside observer that the fence is indeed signaled.
v2: Sketch out potential dma-fence API for manual signaling
v3: And the test_and_set_bit()
Fixes: 52c0fdb25c7c ("drm/i915: Replace global breadcrumbs with per-context
interrupt tracking")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/dma-buf/dma-fence.c | 1 +
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 78 +++--
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/intel_guc_submission.c | 1 -
4 files changed, 59 insertions(+), 22 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 3aa8733f832a..9bf06042619a 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -29,6 +29,7 @@
EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
static DEFINE_SPINLOCK(dma_fence_stub_lock);
static struct dma_fence dma_fence_stub;
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index fe455f01aa65..c092bdf5f0bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include "i915_drv.h"
@@ -96,9 +97,39 @@ check_signal_order(struct intel_context *ce, struct
i915_request *rq)
return true;
}
+static bool
+__dma_fence_signal(struct dma_fence *fence)
+{
+ return !test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags);
+}
+
+static void
+__dma_fence_signal__timestamp(struct dma_fence *fence, ktime_t timestamp)
+{
+ fence->timestamp = timestamp;
+ set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, >flags);
+ trace_dma_fence_signaled(fence);
+}
+
+static void
+__dma_fence_signal__notify(struct dma_fence *fence)
+{
+ struct dma_fence_cb *cur, *tmp;
+
+ lockdep_assert_held(fence->lock);
+ lockdep_assert_irqs_disabled();
+
+ list_for_each_entry_safe(cur, tmp, >cb_list, node) {
+ INIT_LIST_HEAD(>node);
+ cur->func(fence, cur);
+ }
+ INIT_LIST_HEAD(>cb_list);
+}
+
void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine)
{
struct intel_breadcrumbs *b = >breadcrumbs;
+ const ktime_t timestamp = ktime_get();
struct intel_context *ce, *cn;
struct list_head *pos, *next;
LIST_HEAD(signal);
@@ -122,6 +153,10 @@ void intel_engine_breadcrumbs_irq(struct intel_engine_cs
*engine)
GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_SIGNAL,
>fence.flags));
+ clear_bit(I915_FENCE_FLAG_SIGNAL, >fence.flags);
+
+ if (!__dma_fence_signal(>fence))
+ continue;
/*
* Queue for execution after dropping the signaling
@@ -129,14 +164,6 @@ void intel_engine_breadcrumbs_irq(struct intel_engine_cs
*engine)
* more signalers to the same context or engine.
*/
i915_request_get(rq);
-
- /*
-* We may race with direct invocation of
-*
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Support for DP YCbCr4:2:0 outputs
== Series Details == Series: drm/i915/dp: Support for DP YCbCr4:2:0 outputs URL : https://patchwork.freedesktop.org/series/60404/ State : success == Summary == CI Bug Log - changes from CI_DRM_6063_full -> Patchwork_12983_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12983_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl6/igt@gem_workarou...@suspend-resume-context.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-apl2/igt@gem_workarou...@suspend-resume-context.html * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl6/igt@kms_cursor_...@cursor-128x128-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl8/igt@kms_cursor_...@cursor-128x128-suspend.html * igt@kms_draw_crc@draw-method-xrgb-render-xtiled: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#103184] / [fdo#103232]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl4/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl1/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107773]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl9/igt@kms_fbcon_...@fbc-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl10/igt@kms_fbcon_...@fbc-suspend.html * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk1/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk4/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move: - shard-hsw: [PASS][13] -> [SKIP][14] ([fdo#109271]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-hsw8/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-hsw6/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb6/igt@kms_frontbuffer_track...@fbc-tilingchange.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb4/igt@kms_frontbuffer_track...@fbc-tilingchange.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format: - shard-glk: [PASS][21] -> [SKIP][22] ([fdo#109271] / [fdo#109278]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk9/igt@kms_plane_scal...@pipe-a-scaler-with-pixel-format.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk5/igt@kms_plane_scal...@pipe-a-scaler-with-pixel-format.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [24]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD (rev4)
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD (rev4)
URL : https://patchwork.freedesktop.org/series/60403/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e7ad7ff7e483 drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
91a757861669 drm/i915: Rearrange i915_scheduler.c
388db2b0c7a6 drm/i915: Pass i915_sched_node around internally
f4522862f19a drm/i915: Check for no-op priority changes first
007c8b9dcc4b drm/i915: Bump signaler priority on adding a waiter
bfcd51b8596a drm/i915: Convert inconsistent static engine tables into an init
error
753e000c7a33 drm/i915: Seal races between async GPU cancellation, retirement
and signaling
559d9dee1ecb dma-fence: Refactor signaling for manual invocation
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#30:
new file mode 100644
-:35: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#35: FILE: drivers/dma-buf/dma-fence-trace.c:1:
+/*
-:195: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#195: FILE: include/linux/dma-fence-types.h:1:
+/*
-:266: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#266: FILE: include/linux/dma-fence-types.h:72:
+ spinlock_t *lock;
total: 0 errors, 3 warnings, 1 checks, 669 lines checked
692fdcbeb38c drm/i915: Restore control over ppgtt for context creation ABI
-:81: WARNING:LONG_LINE: line over 100 characters
#81: FILE: include/uapi/drm/i915_drm.h:420:
+#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
-:82: WARNING:LONG_LINE: line over 100 characters
#82: FILE: include/uapi/drm/i915_drm.h:421:
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
-:82: WARNING:SPACING: space prohibited between function name and open
parenthesis '('
#82: FILE: include/uapi/drm/i915_drm.h:421:
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
-:82: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#82: FILE: include/uapi/drm/i915_drm.h:421:
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
total: 1 errors, 3 warnings, 0 checks, 64 lines checked
82ba6f07ab8b drm/i915: Allow a context to define its set of engines
-:437: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#437: FILE: drivers/gpu/drm/i915/i915_utils.h:110:
+#define check_struct_size(p, member, n, sz) \
+ likely(__check_struct_size(sizeof(*(p)), \
+ sizeof(*(p)->member) +
__must_be_array((p)->member), \
+ n, sz))
-:437: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible
side-effects?
#437: FILE: drivers/gpu/drm/i915/i915_utils.h:110:
+#define check_struct_size(p, member, n, sz) \
+ likely(__check_struct_size(sizeof(*(p)), \
+ sizeof(*(p)->member) +
__must_be_array((p)->member), \
+ n, sz))
-:437: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'member' may be better as
'(member)' to avoid precedence issues
#437: FILE: drivers/gpu/drm/i915/i915_utils.h:110:
+#define check_struct_size(p, member, n, sz) \
+ likely(__check_struct_size(sizeof(*(p)), \
+ sizeof(*(p)->member) +
__must_be_array((p)->member), \
+ n, sz))
total: 0 errors, 0 warnings, 3 checks, 428 lines checked
94d7eb79a37a drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local
ctx->engine[]
a699c113a8e2 drm/i915: Re-expose SINGLE_TIMELINE flags for context creation
b60419b1ad85 drm/i915: Allow userspace to clone contexts on creation
-:213: ERROR:BRACKET_SPACE: space prohibited before open square bracket '['
#213: FILE: drivers/gpu/drm/i915/i915_gem_context.c:1858:
+#define MAP(x, y) [ilog2(I915_CONTEXT_CLONE_##x)] = y
total: 1 errors, 0 warnings, 0 checks, 235 lines checked
263014777cd1 drm/i915: Load balancing across a virtual engine
ff8dbcf5aaa5 drm/i915: Apply an execution_mask to the virtual_engine
b4069da09690 drm/i915: Extend execution fence to support a callback
75381837ffb3 drm/i915/execlists: Virtual engine bonding
d1ad066b91b5 drm/i915: Allow specification of parallel execbuf
d5d4ec7726a0 drm/i915: Split GEM object type definition to its own header
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#25:
new file mode 100644
-:59: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#59: FILE: drivers/gpu/drm/i915/gem/i915_gem_object_types.h:1:
+/*
-:60: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag
Re: [Intel-gfx] [PATCH 14/40] drm/i915: Load balancing across a virtual engine
On 08/05/2019 12:17, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 11:29:34)
On 08/05/2019 09:06, Chris Wilson wrote:
+static int live_virtual_engine(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_engine_cs *siblings[MAX_ENGINE_INSTANCE + 1];
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ unsigned int class, inst;
+ int err = -ENODEV;
+
+ if (USES_GUC_SUBMISSION(i915))
+ return 0;
+
+ mutex_lock(>drm.struct_mutex);
+
+ for_each_engine(engine, i915, id) {
+ err = nop_virtual_engine(i915, , 1, 1, 0);
+ if (err) {
+ pr_err("Failed to wrap engine %s: err=%d\n",
+engine->name, err);
+ goto out_unlock;
+ }
+ }
+
+ for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
+ int nsibling, n;
+
+ nsibling = 0;
+ for (inst = 0; inst <= MAX_ENGINE_INSTANCE; inst++) {
+ if (!i915->engine_class[class][inst])
+ break;
I previous review I said I think this should be continue instead of
break so vcs0 + vcs2 skus can also be tested.
Completely missed that, sorry.
+
+ siblings[nsibling++] = i915->engine_class[class][inst];
+ }
+ if (nsibling < 2)
+ continue;
And also that single engine VE could be tested just as well, unless I am
missing something.
There's no such thing as single engine VE. The current design requires
that this type of struct virtual_engine encompasses more than one engine
(failing that we break the single request scheduling, although might be
able to lift that with timeslicing but the early results were not
favourable); the single engine being a regular intel_context instance.
Yeah my bad, the auto-magic replacement with physical engine happens one
level higher than what this selftest is operating on.
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH] drm/i915: Load balancing across a virtual engine
On 08/05/2019 12:23, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load. The virtual engine has a single timeline across all
engines (it operates as a single queue), so it is not able to concurrently
run batches across multiple engines by itself; that is left up to the user
to submit multiple concurrent batches to multiple queues. Multiple users
will be load balanced across the system.
The mechanism used for load balancing in this patch is a late greedy
balancer. When a request is ready for execution, it is added to each
engine's queue, and when an engine is ready for its next request it
claims it from the virtual engine. The first engine to do so, wins, i.e.
the request is executed at the earliest opportunity (idle moment) in the
system.
As not all HW is created equal, the user is still able to skip the
virtual engine and execute the batch on a specific engine, all within the
same queue. It will then be executed in order on the correct engine,
with execution on other virtual engines being moved away due to the load
detection.
A couple of areas for potential improvement left!
- The virtual engine always take priority over equal-priority tasks.
Mostly broken up by applying FQ_CODEL rules for prioritising new clients,
and hopefully the virtual and real engines are not then congested (i.e.
all work is via virtual engines, or all work is to the real engine).
- We require the breadcrumb irq around every virtual engine request. For
normal engines, we eliminate the need for the slow round trip via
interrupt by using the submit fence and queueing in order. For virtual
engines, we have to allow any job to transfer to a new ring, and cannot
coalesce the submissions, so require the completion fence instead,
forcing the persistent use of interrupts.
- We only drip feed single requests through each virtual engine and onto
the physical engines, even if there was enough work to fill all ELSP,
leaving small stalls with an idle CS event at the end of every request.
Could we be greedy and fill both slots? Being lazy is virtuous for load
distribution on less-than-full workloads though.
Other areas of improvement are more general, such as reducing lock
contention, reducing dispatch overhead, looking at direct submission
rather than bouncing around tasklets etc.
sseu: Lift the restriction to allow sseu to be reconfigured on virtual
engines composed of RENDER_CLASS (rcs).
v2: macroize check_user_mbz()
v3: Cancel virtual engines on wedging
v4: Commence commenting
v5: Replace 64b sibling_mask with a list of class:instance
v6: Drop the one-element array in the uabi
v7: Assert it is an virtual engine in to_virtual_engine()
v8: Skip over holes in [class][inst] so we can selftest with (vcs0, vcs2)
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 683 ++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 9 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
drivers/gpu/drm/i915/i915_gem.h | 5 +
drivers/gpu/drm/i915/i915_gem_context.c | 116 +++-
drivers/gpu/drm/i915/i915_scheduler.c| 19 +-
drivers/gpu/drm/i915/i915_timeline_types.h | 1 +
include/uapi/drm/i915_drm.h | 39 ++
9 files changed, 1032 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index e381c1c73902..7b47e00fa082 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -227,6 +227,7 @@ struct intel_engine_execlists {
* @queue: queue of requests, in priority lists
*/
struct rb_root_cached queue;
+ struct rb_root_cached virtual;
/**
* @csb_write: control register for Context Switch buffer
@@ -445,6 +446,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
unsigned int flags;
/*
@@ -534,6 +536,12 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
+static inline bool
+intel_engine_is_virtual(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_IS_VIRTUAL;
+}
+
#define instdone_slice_mask(dev_priv__) \
(IS_GEN(dev_priv__, 7) ? \
1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index
[Intel-gfx] [PATCH] drm/i915: Seal races between async GPU cancellation, retirement and signaling
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In the near future that may change, and this may upset
our signaling as we can process an interrupt for that request while it
is no longer in flight.
CPU0CPU1
intel_engine_breadcrumbs_irq
(queue request completion)
i915_request_cancel_signaling
... ...
i915_request_enable_signaling
dma_fence_signal
Hence in the time it took us to drop the lock to signal the request, a
preemption event may have occurred and re-queued the request. In the
process, that request would have seen I915_FENCE_FLAG_SIGNAL clear and
so reused the rq->signal_link that was in use on CPU0, leading to bad
pointer chasing in intel_engine_breadcrumbs_irq.
A related issue was that if someone started listening for a signal on a
completed but no longer in-flight request, we missed the opportunity to
immediately signal that request.
Furthermore, as intel_contexts may be immediately released during
request retirement, in order to be entirely sure that
intel_engine_breadcrumbs_irq may no longer dereference the intel_context
(ce->signals and ce->signal_link), we must wait for irq spinlock.
In order to prevent the race, we use a bit in the fence.flags to signal
the transfer onto the signal list inside intel_engine_breadcrumbs_irq.
For simplicity, we use the DMA_FENCE_FLAG_SIGNALED_BIT as it then
quickly signals to any outside observer that the fence is indeed signaled.
v2: Sketch out potential dma-fence API for manual signaling
v3: And the test_and_set_bit()
Fixes: 52c0fdb25c7c ("drm/i915: Replace global breadcrumbs with per-context
interrupt tracking")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/dma-buf/dma-fence.c | 1 +
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 78 +++--
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/intel_guc_submission.c | 1 -
4 files changed, 59 insertions(+), 22 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 3aa8733f832a..9bf06042619a 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -29,6 +29,7 @@
EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
static DEFINE_SPINLOCK(dma_fence_stub_lock);
static struct dma_fence dma_fence_stub;
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index fe455f01aa65..c092bdf5f0bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include "i915_drv.h"
@@ -96,9 +97,39 @@ check_signal_order(struct intel_context *ce, struct
i915_request *rq)
return true;
}
+static bool
+__dma_fence_signal(struct dma_fence *fence)
+{
+ return !test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags);
+}
+
+static void
+__dma_fence_signal__timestamp(struct dma_fence *fence, ktime_t timestamp)
+{
+ fence->timestamp = timestamp;
+ set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, >flags);
+ trace_dma_fence_signaled(fence);
+}
+
+static void
+__dma_fence_signal__notify(struct dma_fence *fence)
+{
+ struct dma_fence_cb *cur, *tmp;
+
+ lockdep_assert_held(fence->lock);
+ lockdep_assert_irqs_disabled();
+
+ list_for_each_entry_safe(cur, tmp, >cb_list, node) {
+ INIT_LIST_HEAD(>node);
+ cur->func(fence, cur);
+ }
+ INIT_LIST_HEAD(>cb_list);
+}
+
void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine)
{
struct intel_breadcrumbs *b = >breadcrumbs;
+ const ktime_t timestamp = ktime_get();
struct intel_context *ce, *cn;
struct list_head *pos, *next;
LIST_HEAD(signal);
@@ -122,6 +153,10 @@ void intel_engine_breadcrumbs_irq(struct intel_engine_cs
*engine)
GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_SIGNAL,
>fence.flags));
+ clear_bit(I915_FENCE_FLAG_SIGNAL, >fence.flags);
+
+ if (!__dma_fence_signal(>fence))
+ continue;
/*
* Queue for execution after dropping the signaling
@@ -129,14 +164,6 @@ void intel_engine_breadcrumbs_irq(struct intel_engine_cs
*engine)
* more signalers to the same context or engine.
*/
i915_request_get(rq);
-
- /*
-* We may race with direct invocation of
-* dma_fence_signal(), e.g. i915_request_retire(),
-
[Intel-gfx] [PATCH] dma-fence: Refactor signaling for manual invocation
Move the duplicated code within dma-fence.c into the header for wider
reuse.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/Makefile| 10 +-
drivers/dma-buf/dma-fence-trace.c | 28 +++
drivers/dma-buf/dma-fence.c | 32 +--
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 30 ---
include/linux/dma-fence-types.h | 248 +++
include/linux/dma-fence.h | 251 +++-
6 files changed, 321 insertions(+), 278 deletions(-)
create mode 100644 drivers/dma-buf/dma-fence-trace.c
create mode 100644 include/linux/dma-fence-types.h
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 1f006e083eb9..56e579878f26 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,5 +1,11 @@
-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
-reservation.o seqno-fence.o
+obj-y := \
+ dma-buf.o \
+ dma-fence.o \
+ dma-fence-array.o \
+ dma-fence-chain.o \
+ dma-fence-trace.o \
+ reservation.o \
+ seqno-fence.o
obj-$(CONFIG_SYNC_FILE)+= sync_file.o
obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o
obj-$(CONFIG_UDMABUF) += udmabuf.o
diff --git a/drivers/dma-buf/dma-fence-trace.c
b/drivers/dma-buf/dma-fence-trace.c
new file mode 100644
index ..eb6f282be4c0
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-trace.c
@@ -0,0 +1,28 @@
+/*
+ * Fence mechanism for dma-buf and to allow for asynchronous dma access
+ *
+ * Copyright (C) 2012 Canonical Ltd
+ * Copyright (C) 2012 Texas Instruments
+ *
+ * Authors:
+ * Rob Clark
+ * Maarten Lankhorst
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+
+#define CREATE_TRACE_POINTS
+#include
+
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 9bf06042619a..8196a179fdc2 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -24,13 +24,6 @@
#include
#include
-#define CREATE_TRACE_POINTS
-#include
-
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
-
static DEFINE_SPINLOCK(dma_fence_stub_lock);
static struct dma_fence dma_fence_stub;
@@ -136,7 +129,6 @@ EXPORT_SYMBOL(dma_fence_context_alloc);
*/
int dma_fence_signal_locked(struct dma_fence *fence)
{
- struct dma_fence_cb *cur, *tmp;
int ret = 0;
lockdep_assert_held(fence->lock);
@@ -144,7 +136,7 @@ int dma_fence_signal_locked(struct dma_fence *fence)
if (WARN_ON(!fence))
return -EINVAL;
- if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags)) {
+ if (!__dma_fence_signal(fence)) {
ret = -EINVAL;
/*
@@ -152,15 +144,10 @@ int dma_fence_signal_locked(struct dma_fence *fence)
* still run through all callbacks
*/
} else {
- fence->timestamp = ktime_get();
- set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, >flags);
- trace_dma_fence_signaled(fence);
+ __dma_fence_signal__timestamp(fence, ktime_get());
}
- list_for_each_entry_safe(cur, tmp, >cb_list, node) {
- list_del_init(>node);
- cur->func(fence, cur);
- }
+ __dma_fence_signal__notify(fence);
return ret;
}
EXPORT_SYMBOL(dma_fence_signal_locked);
@@ -185,21 +172,14 @@ int dma_fence_signal(struct dma_fence *fence)
if (!fence)
return -EINVAL;
- if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
+ if (!__dma_fence_signal(fence))
return -EINVAL;
- fence->timestamp = ktime_get();
- set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, >flags);
- trace_dma_fence_signaled(fence);
+ __dma_fence_signal__timestamp(fence, ktime_get());
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >flags)) {
- struct dma_fence_cb *cur, *tmp;
-
spin_lock_irqsave(fence->lock, flags);
- list_for_each_entry_safe(cur, tmp, >cb_list, node) {
- list_del_init(>node);
- cur->func(fence, cur);
- }
+ __dma_fence_signal__notify(fence);
spin_unlock_irqrestore(fence->lock, flags);
}
return 0;
diff --git
[Intel-gfx] [PATCH] drm/i915: Load balancing across a virtual engine
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load. The virtual engine has a single timeline across all
engines (it operates as a single queue), so it is not able to concurrently
run batches across multiple engines by itself; that is left up to the user
to submit multiple concurrent batches to multiple queues. Multiple users
will be load balanced across the system.
The mechanism used for load balancing in this patch is a late greedy
balancer. When a request is ready for execution, it is added to each
engine's queue, and when an engine is ready for its next request it
claims it from the virtual engine. The first engine to do so, wins, i.e.
the request is executed at the earliest opportunity (idle moment) in the
system.
As not all HW is created equal, the user is still able to skip the
virtual engine and execute the batch on a specific engine, all within the
same queue. It will then be executed in order on the correct engine,
with execution on other virtual engines being moved away due to the load
detection.
A couple of areas for potential improvement left!
- The virtual engine always take priority over equal-priority tasks.
Mostly broken up by applying FQ_CODEL rules for prioritising new clients,
and hopefully the virtual and real engines are not then congested (i.e.
all work is via virtual engines, or all work is to the real engine).
- We require the breadcrumb irq around every virtual engine request. For
normal engines, we eliminate the need for the slow round trip via
interrupt by using the submit fence and queueing in order. For virtual
engines, we have to allow any job to transfer to a new ring, and cannot
coalesce the submissions, so require the completion fence instead,
forcing the persistent use of interrupts.
- We only drip feed single requests through each virtual engine and onto
the physical engines, even if there was enough work to fill all ELSP,
leaving small stalls with an idle CS event at the end of every request.
Could we be greedy and fill both slots? Being lazy is virtuous for load
distribution on less-than-full workloads though.
Other areas of improvement are more general, such as reducing lock
contention, reducing dispatch overhead, looking at direct submission
rather than bouncing around tasklets etc.
sseu: Lift the restriction to allow sseu to be reconfigured on virtual
engines composed of RENDER_CLASS (rcs).
v2: macroize check_user_mbz()
v3: Cancel virtual engines on wedging
v4: Commence commenting
v5: Replace 64b sibling_mask with a list of class:instance
v6: Drop the one-element array in the uabi
v7: Assert it is an virtual engine in to_virtual_engine()
v8: Skip over holes in [class][inst] so we can selftest with (vcs0, vcs2)
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 683 ++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 9 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
drivers/gpu/drm/i915/i915_gem.h | 5 +
drivers/gpu/drm/i915/i915_gem_context.c | 116 +++-
drivers/gpu/drm/i915/i915_scheduler.c| 19 +-
drivers/gpu/drm/i915/i915_timeline_types.h | 1 +
include/uapi/drm/i915_drm.h | 39 ++
9 files changed, 1032 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index e381c1c73902..7b47e00fa082 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -227,6 +227,7 @@ struct intel_engine_execlists {
* @queue: queue of requests, in priority lists
*/
struct rb_root_cached queue;
+ struct rb_root_cached virtual;
/**
* @csb_write: control register for Context Switch buffer
@@ -445,6 +446,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
unsigned int flags;
/*
@@ -534,6 +536,12 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
+static inline bool
+intel_engine_is_virtual(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_IS_VIRTUAL;
+}
+
#define instdone_slice_mask(dev_priv__) \
(IS_GEN(dev_priv__, 7) ? \
1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f1d62746e066..bc388df39802 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD
URL : https://patchwork.freedesktop.org/series/60403/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12984
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12984/
New tests
-
New tests have been introduced between CI_DRM_6063 and Patchwork_12984:
### New IGT tests (1) ###
* igt@i915_selftest@live_mman:
- Statuses : 42 pass(s)
- Exec time: [4.50, 57.25] s
Known issues
Here are the changes found in Patchwork_12984 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([fdo#108511])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12984/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@gem_exec_basic@readonly-render:
- {fi-icl-y}: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12984/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
Participating hosts (53 -> 43)
--
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-pnv-d510 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6063 -> Patchwork_12984
CI_DRM_6063: 44ae4003d35743cbc7883825c5fe777d136b5247 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12984: 9bf3a26c75f2ad0800b50d5eaf9a6f40d90254bd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9bf3a26c75f2 drm/i915/execlists: Minimalistic timeslicing
c3f5d7c6f6cc drm/i915/execlists: Preempt-to-busy
3ab6fd267bc8 drm/i915: Flush the execution-callbacks on retiring
f29e29f63664 drm/i915: Replace engine->timeline with a plain list
4bcdd4c21eeb drm/i915: Stop retiring along engine
16ad5ab86e98 drm/i915: Keep contexts pinned until after the next kernel context
switch
ff7e06f46eef drm/i915: Rename intel_context.active to .inflight
06e6fa4897ee drm/i915: Move object close under its own lock
5ec5ae3c8224 drm/i915: Drop the deferred active reference
a0342667999c drm/i915: Move GEM client throttling to its own file
3853ef7d5efd drm/i915: Move GEM object busy checking to its own file
37093e2cfcb7 drm/i915: Move GEM object waiting to its own file
82fa4ffba0ac drm/i915: Move GEM object domain management from struct_mutex to
local
e95a11a1ae00 drm/i915: Pull scatterlist utils out of i915_gem.h
8be66d73a04c drm/i915: Move more GEM objects under gem/
1786d7cb9bc6 drm/i915: Move GEM domain management to its own file
4734074d136c drm/i915: Move mmap and friends to its own file
35b7895848a6 drm/i915: Move phys objects to its own file
fb33bd9448ad drm/i915: Move shmem object setup to its own file
3483581bdd02 drm/i915: Move object->pages API to i915_gem_object.[ch]
39f76472714f drm/i915: Pull GEM ioctls interface to its own file
b688a0332163 drm/i915: Split GEM object type definition to its own header
00c6c2e19f78 drm/i915: Allow specification of parallel execbuf
7afded600522 drm/i915/execlists: Virtual engine bonding
f0417a49d538 drm/i915: Extend execution fence to support a callback
266984fb2212 drm/i915: Apply an execution_mask to the virtual_engine
69947c56c90e drm/i915: Load balancing across a virtual engine
fc7ed4a4ef81 drm/i915: Allow userspace to clone contexts on creation
5bbcdc2dae1c drm/i915: Re-expose SINGLE_TIMELINE flags for context creation
7af4301e09f7 drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local
ctx->engine[]
d257fe3e40a0 drm/i915: Allow a context to define its set of engines
1415c169395e drm/i915: Restore control over ppgtt for context creation ABI
eb869674ac86 dma-fence: Refactor signaling for manual invocation
0f169a3e02f6 drm/i915: Seal races between async GPU cancellation, retirement
and signaling
483a8a8f05cf drm/i915: Convert inconsistent static engine tables into an init
error
4c36ecd8e737 drm/i915: Bump signaler priority on adding a waiter
fad4daf02033 drm/i915: Check for no-op priority changes first
fea1b40e0ff4 drm/i915: Pass i915_sched_node around internally
5f78625e4a23 drm/i915:
Re: [Intel-gfx] [PATCH 14/40] drm/i915: Load balancing across a virtual engine
Quoting Tvrtko Ursulin (2019-05-08 11:29:34)
>
> On 08/05/2019 09:06, Chris Wilson wrote:
> > +static int live_virtual_engine(void *arg)
> > +{
> > + struct drm_i915_private *i915 = arg;
> > + struct intel_engine_cs *siblings[MAX_ENGINE_INSTANCE + 1];
> > + struct intel_engine_cs *engine;
> > + enum intel_engine_id id;
> > + unsigned int class, inst;
> > + int err = -ENODEV;
> > +
> > + if (USES_GUC_SUBMISSION(i915))
> > + return 0;
> > +
> > + mutex_lock(>drm.struct_mutex);
> > +
> > + for_each_engine(engine, i915, id) {
> > + err = nop_virtual_engine(i915, , 1, 1, 0);
> > + if (err) {
> > + pr_err("Failed to wrap engine %s: err=%d\n",
> > +engine->name, err);
> > + goto out_unlock;
> > + }
> > + }
> > +
> > + for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
> > + int nsibling, n;
> > +
> > + nsibling = 0;
> > + for (inst = 0; inst <= MAX_ENGINE_INSTANCE; inst++) {
> > + if (!i915->engine_class[class][inst])
> > + break;
>
> I previous review I said I think this should be continue instead of
> break so vcs0 + vcs2 skus can also be tested.
Completely missed that, sorry.
> > +
> > + siblings[nsibling++] =
> > i915->engine_class[class][inst];
> > + }
> > + if (nsibling < 2)
> > + continue;
>
> And also that single engine VE could be tested just as well, unless I am
> missing something.
There's no such thing as single engine VE. The current design requires
that this type of struct virtual_engine encompasses more than one engine
(failing that we break the single request scheduling, although might be
able to lift that with timeslicing but the early results were not
favourable); the single engine being a regular intel_context instance.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
== Series Details == Series: series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD URL : https://patchwork.freedesktop.org/series/60403/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD Okay! Commit: drm/i915: Rearrange i915_scheduler.c Okay! Commit: drm/i915: Pass i915_sched_node around internally Okay! Commit: drm/i915: Check for no-op priority changes first Okay! Commit: drm/i915: Bump signaler priority on adding a waiter Okay! Commit: drm/i915: Convert inconsistent static engine tables into an init error Okay! Commit: drm/i915: Seal races between async GPU cancellation, retirement and signaling Okay! Commit: dma-fence: Refactor signaling for manual invocation Okay! Commit: drm/i915: Restore control over ppgtt for context creation ABI Okay! Commit: drm/i915: Allow a context to define its set of engines +drivers/gpu/drm/i915/i915_utils.h:87:13: error: incorrect type in conditional +drivers/gpu/drm/i915/i915_utils.h:87:13: error: undefined identifier '__builtin_mul_overflow' +drivers/gpu/drm/i915/i915_utils.h:87:13:got void +drivers/gpu/drm/i915/i915_utils.h:87:13: warning: call with no type! +drivers/gpu/drm/i915/i915_utils.h:90:13: error: incorrect type in conditional +drivers/gpu/drm/i915/i915_utils.h:90:13: error: undefined identifier '__builtin_add_overflow' +drivers/gpu/drm/i915/i915_utils.h:90:13:got void +drivers/gpu/drm/i915/i915_utils.h:90:13: warning: call with no type! -drivers/gpu/drm/i915/selftests/../i915_utils.h:184:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_utils.h:218:16: warning: expression using sizeof(void) +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: not a function +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: not a function +./include/linux/overflow.h:287:13:got void Commit: drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[] Okay! Commit: drm/i915: Re-expose SINGLE_TIMELINE flags for context creation Okay! Commit: drm/i915: Allow userspace to clone contexts on creation +drivers/gpu/drm/i915/i915_gem_context.c:1859:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1860:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1861:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1862:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1863:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1864:17: error: bad integer constant expression -drivers/gpu/drm/i915/i915_utils.h:87:13: warning: call with no type! -drivers/gpu/drm/i915/i915_utils.h:90:13: warning: call with no type! -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1266:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1266:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:454:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:571:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:571:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:693:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:693:33: warning: expression using sizeof(void) +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: not a function -./include/linux/overflow.h:285:13: warning: call with no type! +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: not a function -./include/linux/overflow.h:287:13: warning: call with no type! +./include/linux/overflow.h:287:13:got void -./include/linux/slab.h:666:13: warning: call with no type! Commit: drm/i915: Load balancing across a virtual engine +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:285:13: warning: call with no type! +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: undefined identifier '__builtin_add_overflow' +./include/linux/overflow.h:287:13:got void +./include/linux/overflow.h:287:13: warning: call with no type! +./include/linux/slab.h:666:13: error: not a function Commit: drm/i915: Apply an execution_mask to the virtual_engine
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/40] drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
== Series Details ==
Series: series starting with [01/40] drm/i915/hangcheck: Replace
hangcheck.seqno with RING_HEAD
URL : https://patchwork.freedesktop.org/series/60403/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
67b421614964 drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
5f78625e4a23 drm/i915: Rearrange i915_scheduler.c
fea1b40e0ff4 drm/i915: Pass i915_sched_node around internally
fad4daf02033 drm/i915: Check for no-op priority changes first
4c36ecd8e737 drm/i915: Bump signaler priority on adding a waiter
483a8a8f05cf drm/i915: Convert inconsistent static engine tables into an init
error
0f169a3e02f6 drm/i915: Seal races between async GPU cancellation, retirement
and signaling
eb869674ac86 dma-fence: Refactor signaling for manual invocation
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#30:
new file mode 100644
-:35: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#35: FILE: drivers/dma-buf/dma-fence-trace.c:1:
+/*
-:173: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#173: FILE: include/linux/dma-fence-types.h:1:
+/*
-:244: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#244: FILE: include/linux/dma-fence-types.h:72:
+ spinlock_t *lock;
total: 0 errors, 3 warnings, 1 checks, 641 lines checked
1415c169395e drm/i915: Restore control over ppgtt for context creation ABI
-:81: WARNING:LONG_LINE: line over 100 characters
#81: FILE: include/uapi/drm/i915_drm.h:420:
+#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
-:82: WARNING:LONG_LINE: line over 100 characters
#82: FILE: include/uapi/drm/i915_drm.h:421:
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
-:82: WARNING:SPACING: space prohibited between function name and open
parenthesis '('
#82: FILE: include/uapi/drm/i915_drm.h:421:
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
-:82: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#82: FILE: include/uapi/drm/i915_drm.h:421:
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
total: 1 errors, 3 warnings, 0 checks, 64 lines checked
d257fe3e40a0 drm/i915: Allow a context to define its set of engines
-:437: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#437: FILE: drivers/gpu/drm/i915/i915_utils.h:110:
+#define check_struct_size(p, member, n, sz) \
+ likely(__check_struct_size(sizeof(*(p)), \
+ sizeof(*(p)->member) +
__must_be_array((p)->member), \
+ n, sz))
-:437: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible
side-effects?
#437: FILE: drivers/gpu/drm/i915/i915_utils.h:110:
+#define check_struct_size(p, member, n, sz) \
+ likely(__check_struct_size(sizeof(*(p)), \
+ sizeof(*(p)->member) +
__must_be_array((p)->member), \
+ n, sz))
-:437: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'member' may be better as
'(member)' to avoid precedence issues
#437: FILE: drivers/gpu/drm/i915/i915_utils.h:110:
+#define check_struct_size(p, member, n, sz) \
+ likely(__check_struct_size(sizeof(*(p)), \
+ sizeof(*(p)->member) +
__must_be_array((p)->member), \
+ n, sz))
total: 0 errors, 0 warnings, 3 checks, 428 lines checked
7af4301e09f7 drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local
ctx->engine[]
5bbcdc2dae1c drm/i915: Re-expose SINGLE_TIMELINE flags for context creation
fc7ed4a4ef81 drm/i915: Allow userspace to clone contexts on creation
-:213: ERROR:BRACKET_SPACE: space prohibited before open square bracket '['
#213: FILE: drivers/gpu/drm/i915/i915_gem_context.c:1858:
+#define MAP(x, y) [ilog2(I915_CONTEXT_CLONE_##x)] = y
total: 1 errors, 0 warnings, 0 checks, 235 lines checked
69947c56c90e drm/i915: Load balancing across a virtual engine
266984fb2212 drm/i915: Apply an execution_mask to the virtual_engine
f0417a49d538 drm/i915: Extend execution fence to support a callback
7afded600522 drm/i915/execlists: Virtual engine bonding
00c6c2e19f78 drm/i915: Allow specification of parallel execbuf
b688a0332163 drm/i915: Split GEM object type definition to its own header
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#25:
new file mode 100644
-:59: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#59: FILE: drivers/gpu/drm/i915/gem/i915_gem_object_types.h:1:
+/*
-:60: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix fastset vs. pfit on/off on HSW EDP transcoder
Op 25-04-2019 om 18:29 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> On HSW the pipe A panel fitter lives inside the display power well,
> and the input MUX for the EDP transcoder needs to be configured
> appropriately to route the data through the power well as needed.
> Changing the MUX setting is not allowed while the pipe is active,
> so we need to force a full modeset whenever we need to change it.
>
> Currently we may end up doing a fastset which won't change the
> MUX settings, but it will drop the power well reference, and that
> kills the pipe.
>
> Cc: sta...@vger.kernel.org
> Cc: Hans de Goede
> Cc: Maarten Lankhorst
> Fixes: d19f958db23c ("drm/i915: Enable fastset for non-boot modesets.")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +
> drivers/gpu/drm/i915/intel_pipe_crc.c | 13 ++---
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c67f165b466c..691c9a929164 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12133,6 +12133,7 @@ intel_pipe_config_compare(struct drm_i915_private
> *dev_priv,
> struct intel_crtc_state *pipe_config,
> bool adjust)
> {
> + struct intel_crtc *crtc = to_intel_crtc(current_config->base.crtc);
> bool ret = true;
> bool fixup_inherited = adjust &&
> (current_config->base.mode.private_flags &
> I915_MODE_FLAG_INHERITED) &&
> @@ -12354,6 +12355,14 @@ intel_pipe_config_compare(struct drm_i915_private
> *dev_priv,
> PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
> PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
>
> + /*
> + * Changing the EDP transcoder input mux
> + * (A_ONOFF vs. A_ON) requires a full modeset.
> + */
> + if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
> + current_config->cpu_transcoder == TRANSCODER_EDP)
> + PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
I guess it depends if we want to make it a blocker or not..
> +
> if (!adjust) {
> PIPE_CONF_CHECK_I(pipe_src_w);
> PIPE_CONF_CHECK_I(pipe_src_h);
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index e94b5b1bc1b7..e7c7be4911c1 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -311,10 +311,17 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc
> *crtc, bool enable)
> pipe_config->base.mode_changed = pipe_config->has_psr;
> pipe_config->crc_enabled = enable;
>
> - if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A) {
> + if (IS_HASWELL(dev_priv) &&
> + pipe_config->base.active && crtc->pipe == PIPE_A &&
> + pipe_config->cpu_transcoder == TRANSCODER_EDP) {
> + bool old_need_power_well = pipe_config->pch_pfit.enabled ||
> + pipe_config->pch_pfit.force_thru;
> + bool new_need_power_well = pipe_config->pch_pfit.enabled ||
> + enable;
> +
> pipe_config->pch_pfit.force_thru = enable;
> - if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
> - pipe_config->pch_pfit.enabled != enable)
> +
> + if (old_need_power_well != new_need_power_well)
> pipe_config->base.connectors_changed = true;
Could we get rid of this logic and set mode_changed instead?
Ah, I see that is done in 2/2, much less surprises then. :)
In that case, for both:
Reviewed-by: Maarten Lankhorst
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Re: [Intel-gfx] [PATCH 11/40] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
On 08/05/2019 09:06, Chris Wilson wrote:
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on virtual engines that
are local to the context and do not have a valid global class:instance
lookup.
Note that due to the ambiguity in using class:instance with
ctx->engines[], if a user supplied engine map is active the user must
specify the engine to alter by its index into the ctx->engines[].
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 24
include/uapi/drm/i915_drm.h | 3 ++-
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 21bfcd529097..5fdb44714a5c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1363,6 +1363,7 @@ static int set_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_context *ce;
struct intel_sseu sseu;
+ unsigned long lookup;
int ret;
if (args->size < sizeof(user_sseu))
@@ -1375,10 +1376,17 @@ static int set_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- ce = lookup_user_engine(ctx, 0, _sseu.engine);
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ ce = lookup_user_engine(ctx, lookup, _sseu.engine);
if (IS_ERR(ce))
return PTR_ERR(ce);
@@ -1795,6 +1803,7 @@ static int get_sseu(struct i915_gem_context *ctx,
{
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_context *ce;
+ unsigned long lookup;
int err;
if (args->size == 0)
@@ -1806,10 +1815,17 @@ static int get_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- ce = lookup_user_engine(ctx, 0, _sseu.engine);
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ ce = lookup_user_engine(ctx, lookup, _sseu.engine);
if (IS_ERR(ce))
return PTR_ERR(ce);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 8e1bb22926e4..82bd488ed0d1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1576,9 +1576,10 @@ struct drm_i915_gem_context_param_sseu {
struct i915_engine_class_instance engine;
/*
-* Unused for now. Must be cleared to zero.
+* Unknown flags must be cleared to zero.
*/
__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 14/40] drm/i915: Load balancing across a virtual engine
On 08/05/2019 09:06, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load. The virtual engine has a single timeline across all
engines (it operates as a single queue), so it is not able to concurrently
run batches across multiple engines by itself; that is left up to the user
to submit multiple concurrent batches to multiple queues. Multiple users
will be load balanced across the system.
The mechanism used for load balancing in this patch is a late greedy
balancer. When a request is ready for execution, it is added to each
engine's queue, and when an engine is ready for its next request it
claims it from the virtual engine. The first engine to do so, wins, i.e.
the request is executed at the earliest opportunity (idle moment) in the
system.
As not all HW is created equal, the user is still able to skip the
virtual engine and execute the batch on a specific engine, all within the
same queue. It will then be executed in order on the correct engine,
with execution on other virtual engines being moved away due to the load
detection.
A couple of areas for potential improvement left!
- The virtual engine always take priority over equal-priority tasks.
Mostly broken up by applying FQ_CODEL rules for prioritising new clients,
and hopefully the virtual and real engines are not then congested (i.e.
all work is via virtual engines, or all work is to the real engine).
- We require the breadcrumb irq around every virtual engine request. For
normal engines, we eliminate the need for the slow round trip via
interrupt by using the submit fence and queueing in order. For virtual
engines, we have to allow any job to transfer to a new ring, and cannot
coalesce the submissions, so require the completion fence instead,
forcing the persistent use of interrupts.
- We only drip feed single requests through each virtual engine and onto
the physical engines, even if there was enough work to fill all ELSP,
leaving small stalls with an idle CS event at the end of every request.
Could we be greedy and fill both slots? Being lazy is virtuous for load
distribution on less-than-full workloads though.
Other areas of improvement are more general, such as reducing lock
contention, reducing dispatch overhead, looking at direct submission
rather than bouncing around tasklets etc.
sseu: Lift the restriction to allow sseu to be reconfigured on virtual
engines composed of RENDER_CLASS (rcs).
v2: macroize check_user_mbz()
v3: Cancel virtual engines on wedging
v4: Commence commenting
v5: Replace 64b sibling_mask with a list of class:instance
v6: Drop the one-element array in the uabi
v7: Assert it is an virtual engine in to_virtual_engine()
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 683 ++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 9 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
drivers/gpu/drm/i915/i915_gem.h | 5 +
drivers/gpu/drm/i915/i915_gem_context.c | 116 +++-
drivers/gpu/drm/i915/i915_scheduler.c| 19 +-
drivers/gpu/drm/i915/i915_timeline_types.h | 1 +
include/uapi/drm/i915_drm.h | 39 ++
9 files changed, 1032 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index e381c1c73902..7b47e00fa082 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -227,6 +227,7 @@ struct intel_engine_execlists {
* @queue: queue of requests, in priority lists
*/
struct rb_root_cached queue;
+ struct rb_root_cached virtual;
/**
* @csb_write: control register for Context Switch buffer
@@ -445,6 +446,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
unsigned int flags;
/*
@@ -534,6 +536,12 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
+static inline bool
+intel_engine_is_virtual(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_IS_VIRTUAL;
+}
+
#define instdone_slice_mask(dev_priv__) \
(IS_GEN(dev_priv__, 7) ? \
1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f1d62746e066..bc388df39802 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Support for DP YCbCr4:2:0 outputs
== Series Details ==
Series: drm/i915/dp: Support for DP YCbCr4:2:0 outputs
URL : https://patchwork.freedesktop.org/series/60404/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12983
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/
Known issues
Here are the changes found in Patchwork_12983 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_exec_basic@readonly-render:
- {fi-icl-y}: [INCOMPLETE][1] ([fdo#107713]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/fi-icl-y/igt@gem_exec_ba...@readonly-render.html
Warnings
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: [INCOMPLETE][3] ([fdo#103927]) -> [INCOMPLETE][4]
([fdo#103927] / [fdo#110624])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624
Participating hosts (53 -> 45)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6063 -> Patchwork_12983
CI_DRM_6063: 44ae4003d35743cbc7883825c5fe777d136b5247 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12983: a902ce4da59ae0f2543950e07ed2678808966a5c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a902ce4da59a drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
1472073c7d9d drm/i915/dp: Change a link bandwidth computation for DP
8bf6ac92cc19 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
c0865d08f8ad drm/i915/dp: Program VSC Header and DB for Pixel
Encoding/Colorimetry Format
3189eb1879bc drm: Add a VSC structure for handling Pixel Encoding/Colorimetry
Formats
e1fd5f42e42e drm/i915/dp: Add a config function for YCBCR420 outputs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/
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Re: [Intel-gfx] [PATCH 12/40] drm/i915: Re-expose SINGLE_TIMELINE flags for context creation
On 08/05/2019 09:06, Chris Wilson wrote:
The SINGLE_TIMELINE flag can be used to create a context such that all
engine instances within that context share a common timeline. This can
be useful for mixing operations between real and virtual engines, or
when using a composite context for a single client API context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 4
include/uapi/drm/i915_drm.h | 3 ++-
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5fdb44714a5c..9cd671298daf 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -96,8 +96,6 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
-#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1 << 1)
-
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
static struct i915_global_gem_context {
@@ -505,8 +503,6 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
unsigned int flags)
lockdep_assert_held(_priv->drm.struct_mutex);
- BUILD_BUG_ON(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &
-~I915_CONTEXT_CREATE_FLAGS_UNKNOWN);
if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &&
!HAS_EXECLISTS(dev_priv))
return ERR_PTR(-EINVAL);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 82bd488ed0d1..957ba8e60e02 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1469,8 +1469,9 @@ struct drm_i915_gem_context_create_ext {
__u32 ctx_id; /* output: id of new context*/
__u32 flags;
#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
- (-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
+ (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
__u64 extensions;
};
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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