[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: use ranges for voltage level lookup
== Series Details ==
Series: drm/i915/icl: use ranges for voltage level lookup
URL : https://patchwork.freedesktop.org/series/61742/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6213 -> Patchwork_13198
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/
Known issues
Here are the changes found in Patchwork_13198 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6213/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([fdo#108511])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6213/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6213/fi-icl-u3/igt@kms_pipe_crc_ba...@read-crc-pipe-a.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/fi-icl-u3/igt@kms_pipe_crc_ba...@read-crc-pipe-a.html
Possible fixes
* igt@gem_basic@create-close:
- fi-cml-u: [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6213/fi-cml-u/igt@gem_ba...@create-close.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/fi-cml-u/igt@gem_ba...@create-close.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [INCOMPLETE][9] ([fdo#109831] / [fdo#109964]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6213/fi-kbl-7560u/igt@i915_module_l...@reload-with-fault-injection.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/fi-kbl-7560u/igt@i915_module_l...@reload-with-fault-injection.html
* igt@vgem_basic@dmabuf-fence-before:
- fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6213/fi-icl-dsi/igt@vgem_ba...@dmabuf-fence-before.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/fi-icl-dsi/igt@vgem_ba...@dmabuf-fence-before.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109831]: https://bugs.freedesktop.org/show_bug.cgi?id=109831
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (53 -> 48)
--
Additional (1): fi-cml-u2
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6213 -> Patchwork_13198
CI_DRM_6213: f384132bcdd8670478b99a2a71753e1595305dce @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5046: 2d244aed69165753f3adbbd6468db073dc1acf9a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13198: bd9728aa9b8fcb0ef4430cf2d4b580cd70d6a88c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bd9728aa9b8f drm/i915/icl: use ranges for voltage level lookup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13198/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Vulkan performance query support (rev4)
== Series Details == Series: drm/i915: Vulkan performance query support (rev4) URL : https://patchwork.freedesktop.org/series/60916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6195_full -> Patchwork_13180_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13180_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13180_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13180_full: ### IGT changes ### Possible regressions * igt@perf@buffer-fill: - shard-apl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-apl1/igt@p...@buffer-fill.html * igt@perf@create-destroy-userspace-config: - shard-glk: [PASS][2] -> [DMESG-WARN][3] +11 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-glk9/igt@p...@create-destroy-userspace-config.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-glk4/igt@p...@create-destroy-userspace-config.html * igt@perf@disabled-read-error: - shard-skl: [PASS][4] -> [INCOMPLETE][5] +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl10/igt@p...@disabled-read-error.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-skl1/igt@p...@disabled-read-error.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-skl: [PASS][6] -> [DMESG-WARN][7] +10 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl10/igt@p...@gen8-unprivileged-single-ctx-counters.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-skl2/igt@p...@gen8-unprivileged-single-ctx-counters.html * igt@perf@invalid-create-userspace-config: - shard-kbl: [PASS][8] -> [DMESG-WARN][9] +11 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-kbl7/igt@p...@invalid-create-userspace-config.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-kbl7/igt@p...@invalid-create-userspace-config.html * igt@perf@invalid-oa-exponent: - shard-hsw: [PASS][10] -> [DMESG-WARN][11] +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw2/igt@p...@invalid-oa-exponent.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw7/igt@p...@invalid-oa-exponent.html - shard-iclb: [PASS][12] -> [DMESG-WARN][13] +10 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb6/igt@p...@invalid-oa-exponent.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-iclb4/igt@p...@invalid-oa-exponent.html * igt@perf@low-oa-exponent-permissions: - shard-apl: [PASS][14] -> [DMESG-WARN][15] +9 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-apl1/igt@p...@low-oa-exponent-permissions.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-apl2/igt@p...@low-oa-exponent-permissions.html * igt@runner@aborted: - shard-hsw: NOTRUN -> ([FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27]) ([fdo#108770]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw8/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw1/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw8/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw6/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw7/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw1/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw7/igt@run...@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw1/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw7/igt@run...@aborted.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw1/igt@run...@aborted.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw7/igt@run...@aborted.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/shard-hsw8/igt@run...@aborted.html - shard-kbl: NOTRUN -> ([FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31]) [28]:
[Intel-gfx] [PATCH] drm/i915/icl: use ranges for voltage level lookup
Spec shows voltage level 0 as 307.2, 312, or lower and suggests to use
range checks. Prepare for having other frequencies in these ranges by
not comparing the exact frequency.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_cdclk.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 6988c6cbc362..b175a2926caf 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1865,21 +1865,18 @@ static void icl_set_cdclk(struct drm_i915_private
*dev_priv,
static u8 icl_calc_voltage_level(int cdclk)
{
- switch (cdclk) {
- case 5:
- case 307200:
- case 312000:
+ if (cdclk <= 312000)
return 0;
- case 556800:
- case 552000:
+
+ if (cdclk <= 556800)
return 1;
- default:
- MISSING_CASE(cdclk);
- /* fall through */
- case 652800:
- case 648000:
+
+ if (cdclk <= 652800)
return 2;
- }
+
+ MISSING_CASE(cdclk);
+
+ return 2;
}
static void icl_get_cdclk(struct drm_i915_private *dev_priv,
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: rename header test build commands to avoid conflicts
== Series Details ==
Series: drm/i915: rename header test build commands to avoid conflicts
URL : https://patchwork.freedesktop.org/series/61655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6195_full -> Patchwork_13179_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_13179_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_balancer@smoke}:
- shard-iclb: [PASS][1] -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb1/igt@gem_exec_balan...@smoke.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-iclb6/igt@gem_exec_balan...@smoke.html
Known issues
Here are the changes found in Patchwork_13179_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb5/igt@gem_...@in-flight-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-iclb7/igt@gem_...@in-flight-suspend.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [PASS][5] -> [FAIL][6] ([fdo#108686])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-kbl6/igt@gem_tiled_swapp...@non-threaded.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-kbl3/igt@gem_tiled_swapp...@non-threaded.html
* igt@i915_pm_rpm@i2c:
- shard-hsw: [PASS][7] -> [FAIL][8] ([fdo#104097])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw7/igt@i915_pm_...@i2c.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-hsw1/igt@i915_pm_...@i2c.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#103184] / [fdo#103232])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl6/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-xtiled.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-skl7/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-xtiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#102887] / [fdo#105363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-hsw8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +7 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
- shard-hsw: [PASS][15] -> [SKIP][16] ([fdo#109271]) +26 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw6/igt@kms_frontbuffer_track...@fbc-2p-primscrn-cur-indfb-draw-render.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +2
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-apl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#99912])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-kbl3/igt@kms_setm...@basic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/shard-kbl2/igt@kms_setm...@basic.html
Possible fixes
* {igt@gem_exec_balancer@bonded-imm}:
- shard-iclb: [FAIL][23] ->
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl (rev2)
== Series Details ==
Series: drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl (rev2)
URL : https://patchwork.freedesktop.org/series/61299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6195_full -> Patchwork_13178_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_13178_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_balancer@bonded-cork}:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb6/igt@gem_exec_balan...@bonded-cork.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-iclb2/igt@gem_exec_balan...@bonded-cork.html
Known issues
Here are the changes found in Patchwork_13178_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_basic@basic-vcs0:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-apl4/igt@gem_exec_ba...@basic-vcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-apl7/igt@gem_exec_ba...@basic-vcs0.html
* igt@gem_mmap_gtt@hang:
- shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#109677])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb3/igt@gem_mmap_...@hang.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-iclb5/igt@gem_mmap_...@hang.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-glk3/igt@gem_tiled_swapp...@non-threaded.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-glk9/igt@gem_tiled_swapp...@non-threaded.html
* igt@kms_color@pipe-a-ctm-0-25:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108682])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl6/igt@kms_co...@pipe-a-ctm-0-25.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-skl2/igt@kms_co...@pipe-a-ctm-0-25.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103184] / [fdo#103232])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl6/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-xtiled.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-skl2/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-xtiled.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
- shard-hsw: [PASS][13] -> [SKIP][14] ([fdo#109271]) +32 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw8/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-hsw1/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: [PASS][15] -> [FAIL][16] ([fdo#103060])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-glk2/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-glk4/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-skl5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#109507])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-skl6/igt@kms_f...@flip-vs-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-skl10/igt@kms_f...@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +6 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb7/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/shard-iclb6/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +1
similar issue
[23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: always use Command Transport Buffers
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: always use Command
Transport Buffers
URL : https://patchwork.freedesktop.org/series/61739/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6211 -> Patchwork_13197
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13197/
Known issues
Here are the changes found in Patchwork_13197 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13197/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
Possible fixes
* igt@gem_exec_reloc@basic-gtt-noreloc:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-icl-u3/igt@gem_exec_re...@basic-gtt-noreloc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13197/fi-icl-u3/igt@gem_exec_re...@basic-gtt-noreloc.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][5] ([fdo#103167]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13197/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (54 -> 46)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-ivb-3770 fi-icl-dsi fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6211 -> Patchwork_13197
CI_DRM_6211: 1f1b3034e607fb7676cea89d5cb7134b7526dd96 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5045: de204870261c0ccda668ef8abc8b756b6e679b4a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13197: 2819ce018651eff5113b00fbb829ed9cd1e3f3e8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2819ce018651 drm/i915/wopcm: update default size for gen11+
43636eec1ebb drm/i915/guc: always use Command Transport Buffers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13197/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Display uncore
== Series Details == Series: Display uncore URL : https://patchwork.freedesktop.org/series/61735/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6211 -> Patchwork_13196 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13196 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13196, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13196: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html - fi-kbl-r: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html - fi-skl-6770hq: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-skl-6770hq/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-skl-6770hq/igt@gem_exec_susp...@basic-s3.html - fi-byt-n2820: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-byt-n2820/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-byt-n2820/igt@gem_exec_susp...@basic-s3.html - fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-cfl-8109u/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-cfl-8109u/igt@gem_exec_susp...@basic-s3.html - fi-skl-lmem:[PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-skl-lmem/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-skl-lmem/igt@gem_exec_susp...@basic-s3.html - fi-skl-6260u: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-skl-6260u/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-skl-6260u/igt@gem_exec_susp...@basic-s3.html - fi-snb-2600:[PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html - fi-whl-u: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-whl-u/igt@gem_exec_susp...@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-whl-u/igt@gem_exec_susp...@basic-s3.html - fi-bdw-gvtdvm: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s3.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s3.html - fi-skl-iommu: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-skl-iommu/igt@gem_exec_susp...@basic-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-skl-iommu/igt@gem_exec_susp...@basic-s3.html - fi-kbl-7567u: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-kbl-7567u/igt@gem_exec_susp...@basic-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-kbl-7567u/igt@gem_exec_susp...@basic-s3.html - fi-glk-dsi: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-glk-dsi/igt@gem_exec_susp...@basic-s3.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-glk-dsi/igt@gem_exec_susp...@basic-s3.html - fi-snb-2520m: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-snb-2520m/igt@gem_exec_susp...@basic-s3.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13196/fi-snb-2520m/igt@gem_exec_susp...@basic-s3.html - fi-kbl-x1275: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-kbl-x1275/igt@gem_exec_susp...@basic-s3.html [30]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/crc-debugfs: Also sprinkle irqrestore over early exits
== Series Details ==
Series: drm/crc-debugfs: Also sprinkle irqrestore over early exits
URL : https://patchwork.freedesktop.org/series/61731/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6211 -> Patchwork_13195
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/
Known issues
Here are the changes found in Patchwork_13195 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-wait-default:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +4
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#110235])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_reloc@basic-gtt-noreloc:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-icl-u3/igt@gem_exec_re...@basic-gtt-noreloc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/fi-icl-u3/igt@gem_exec_re...@basic-gtt-noreloc.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-blb-e6850/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-rte:
- fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713] / [fdo#108840]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-icl-dsi/igt@i915_pm_...@basic-rte.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/fi-icl-dsi/igt@i915_pm_...@basic-rte.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6211/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-apl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6211 -> Patchwork_13195
CI_DRM_6211: 1f1b3034e607fb7676cea89d5cb7134b7526dd96 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5045: de204870261c0ccda668ef8abc8b756b6e679b4a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13195: 31e4149411c896edd12e066dba9875bc0c06acda @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
31e4149411c8 drm/crc-debugfs: Also sprinkle irqrestore over early exits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13195/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Assume combo PHY HBR3 will be inherited by future platforms
Yes, this makes more sense.
Reviewed-by: Clint Taylor
-Clint
On 6/6/19 11:09 AM, Matt Roper wrote:
We shouldn't assume that HBR3 on combo PHYs is an EHL-specific
capability. Let's follow the standard i915 convention of assuming
future platforms will inherit all features of the latest platform.
Fixes: b71438606343 ("drm/i915/ehl: Support HBR3 on EHL combo PHY")
Cc: Manasi Navare
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b099a9dc28fd..4e2a06513e7d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -332,7 +332,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
enum port port = dig_port->base.port;
if (intel_port_is_combophy(dev_priv, port) &&
- !IS_ELKHARTLAKE(dev_priv) &&
+ IS_ICELAKE(dev_priv) &&
!intel_dp_is_edp(intel_dp))
return 54;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/guc: always use Command Transport Buffers
Now that we've moved the Gen9 GuC blobs to version 32 we have CTB
support on all gens, so no need to restrict the usage to Gen11+.
Note that MMIO communication is still required for CTB initialization.
v2: fix commit message nits (Michal)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_guc.c | 45
drivers/gpu/drm/i915/intel_guc.h | 1 -
drivers/gpu/drm/i915/intel_guc_ct.c | 14
drivers/gpu/drm/i915/intel_uc.c | 19 ++
7 files changed, 10 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dfe4b11ee423..82e55c65289a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2393,7 +2393,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
* properties, so we have separate macros to test them.
*/
#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
-#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e761ea86b481..482f1d0f1770 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -746,7 +746,6 @@ static const struct intel_device_info intel_cannonlake_info
= {
}, \
GEN(11), \
.ddb_size = 2048, \
- .has_guc_ct = 1, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d67dedf0cbd8..1fb8b50df7df 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -112,7 +112,6 @@ enum intel_ppgtt_type {
func(has_reset_engine); \
func(has_fpga_dbg); \
func(has_guc); \
- func(has_guc_ct); \
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index b88c349c4fa6..43232242d167 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -56,7 +56,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
enum forcewake_domains fw_domains = 0;
unsigned int i;
- if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(dev_priv) >= 11) {
guc->send_regs.base =
i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
@@ -232,11 +232,9 @@ int intel_guc_init(struct intel_guc *guc)
goto err_log;
GEM_BUG_ON(!guc->ads_vma);
- if (HAS_GUC_CT(dev_priv)) {
- ret = intel_guc_ct_init(>ct);
- if (ret)
- goto err_ads;
- }
+ ret = intel_guc_ct_init(>ct);
+ if (ret)
+ goto err_ads;
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
@@ -262,8 +260,7 @@ void intel_guc_fini(struct intel_guc *guc)
i915_ggtt_disable_guc(dev_priv);
- if (HAS_GUC_CT(dev_priv))
- intel_guc_ct_fini(>ct);
+ intel_guc_ct_fini(>ct);
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(>log);
@@ -430,9 +427,8 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*action, u32 len,
GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
/* If CT is available, we expect to use MMIO only during init/fini */
- GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
- *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
- *action !=
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
+ GEM_BUG_ON(*action !=
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
+ *action !=
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
mutex_lock(>send_mutex);
intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
@@ -481,33 +477,6 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*action, u32 len,
return ret;
}
-void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- u32 msg, val;
-
- /*
-* Sample the log buffer flush related bits & clear them out now
-* itself from the message identity register to minimize the
-* probability of losing a flush interrupt, when there are back
-* to back flush interrupts.
-* There can be a
[Intel-gfx] [CI 2/2] drm/i915/wopcm: update default size for gen11+
The size has been increased to 2MB starting from Gen11. GuC and HuC FWs
fit in 1MB so we were fine even with the legacy define, but let's still
move to the correct one before the blobs grow to avoid being caught off
guard in the future.
v2: return early if the platform doesn't have GuC, fix nits (Michal)
Bspec: 12690
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_wopcm.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..78c8167cfd94 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -41,8 +41,9 @@
* context).
*/
-/* Default WOPCM size 1MB. */
-#define GEN9_WOPCM_SIZE(1024 * 1024)
+/* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
+#define GEN11_WOPCM_SIZE (SZ_2M)
+#define GEN9_WOPCM_SIZE(SZ_1M)
/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
#define WOPCM_RESERVED_SIZE(16 * 1024)
@@ -71,7 +72,15 @@
*/
void intel_wopcm_init_early(struct intel_wopcm *wopcm)
{
- wopcm->size = GEN9_WOPCM_SIZE;
+ struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
+
+ if (!HAS_GUC(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11)
+ wopcm->size = GEN11_WOPCM_SIZE;
+ else
+ wopcm->size = GEN9_WOPCM_SIZE;
DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Display uncore
== Series Details == Series: Display uncore URL : https://patchwork.freedesktop.org/series/61735/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: use vfuncs for reg_read/write_fw_domains Okay! Commit: drm/i915: kill uncore_sanitize Okay! Commit: drm/i915: dynamically allocate forcewake domains Okay! Commit: drm/i915: explicitly prune forcewake domain Okay! Commit: drm/i915: split out uncore_mmio_debug +drivers/gpu/drm/i915/intel_uncore.c:1181:1: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1181:1: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1181:1: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1181:1: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1182:1: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1182:1: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1182:1: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1182:1: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1183:1: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1183:1: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1183:1: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1183:1: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1247:1: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1248:1: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1249:1: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1273:1: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1273:1: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1273:1: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1274:1: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1274:1: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1274:1: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1275:1: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1275:1: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +drivers/gpu/drm/i915/intel_uncore.c:1275:1: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block Commit: drm/i915: drop forcewake_user_get/put Okay! Commit: drm/i915: introduce display_uncore Okay! Commit: drm/i915: move intel_hdmi to de_uncore Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Display uncore
== Series Details ==
Series: Display uncore
URL : https://patchwork.freedesktop.org/series/61735/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ce3c9cc8889e drm/i915: use vfuncs for reg_read/write_fw_domains
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible
side-effects?
#58: FILE: drivers/gpu/drm/i915/intel_uncore.c:1155:
+#define __gen_reg_read_funcs(func) \
+static enum forcewake_domains \
+func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
+ return __##func##_reg_read_fw_domains(uncore,
i915_mmio_reg_offset(reg)); \
+} \
+\
+__gen_read(func, 8) \
+__gen_read(func, 16) \
+__gen_read(func, 32) \
+__gen_read(func, 64)
-:81: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#81: FILE: drivers/gpu/drm/i915/intel_uncore.c:1231:
}
+__gen6_write(8)
-:112: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible
side-effects?
#112: FILE: drivers/gpu/drm/i915/intel_uncore.c:1247:
+#define __gen_reg_write_funcs(func) \
+static enum forcewake_domains \
+func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
+ return __##func##_reg_write_fw_domains(uncore,
i915_mmio_reg_offset(reg)); \
+} \
+\
+__gen_write(func, 8) \
+__gen_write(func, 16) \
+__gen_write(func, 32)
-:131: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible
side-effects?
#131: FILE: drivers/gpu/drm/i915/intel_uncore.c:1265:
+#define ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, x) \
do { \
(uncore)->funcs.mmio_writeb = x##_write8; \
(uncore)->funcs.mmio_writew = x##_write16; \
(uncore)->funcs.mmio_writel = x##_write32; \
} while (0)
-:139: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible
side-effects?
#139: FILE: drivers/gpu/drm/i915/intel_uncore.c:1272:
+#define ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, x) \
do { \
(uncore)->funcs.mmio_readb = x##_read8; \
(uncore)->funcs.mmio_readw = x##_read16; \
-:147: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible
side-effects?
#147: FILE: drivers/gpu/drm/i915/intel_uncore.c:1280:
+#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
+do { \
+ ASSIGN_WRITE_MMIO_VFUNCS_NO_FW((uncore), x); \
+ (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
+} while (0)
-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible
side-effects?
#153: FILE: drivers/gpu/drm/i915/intel_uncore.c:1286:
+#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
+do { \
+ ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, x); \
+ (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
+} while (0)
total: 0 errors, 0 warnings, 7 checks, 258 lines checked
b98535f0b0c8 drm/i915: kill uncore_sanitize
e3497827e11a drm/i915: dynamically allocate forcewake domains
-:31: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#31: FILE: drivers/gpu/drm/i915/intel_uncore.c:1287:
+static int fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
-:105: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements
should be enclosed in a do - while loop
#105: FILE: drivers/gpu/drm/i915/intel_uncore.c:1366:
+#define __fw_domain_init(id, set, ack) \
+ ret = fw_domain_init(uncore, id, set, ack); \
+ if (ret) \
+ goto out_clean;
-:105: WARNING:MACRO_WITH_FLOW_CONTROL: Macros with flow control statements
should be avoided
#105: FILE: drivers/gpu/drm/i915/intel_uncore.c:1366:
+#define __fw_domain_init(id, set, ack) \
+ ret = fw_domain_init(uncore, id, set, ack); \
+ if (ret) \
+ goto out_clean;
-:105: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#105: FILE: drivers/gpu/drm/i915/intel_uncore.c:1366:
+#define __fw_domain_init(id, set, ack) \
+ ret = fw_domain_init(uncore, id, set, ack); \
+ if (ret) \
+ goto out_clean;
total: 1 errors, 2 warnings, 1 checks, 277 lines checked
fd56799f4e3b drm/i915: explicitly prune forcewake domain
da903ca61fad drm/i915: split out uncore_mmio_debug
25c3e5c16e11 drm/i915: drop forcewake_user_get/put
8a0edebef2c6 drm/i915: introduce display_uncore
33f4d6c7a398 drm/i915: move intel_hdmi to de_uncore
-:813: WARNING:LINE_SPACING: Missing a blank line after declarations
#813: FILE: drivers/gpu/drm/i915/intel_hdmi.c:3139:
+ u32 temp = intel_uncore_read(_priv->de_uncore,
PEG_BAND_GAP_DATA);
+ intel_uncore_write(_priv->de_uncore, PEG_BAND_GAP_DATA,
total: 0 errors, 1 warnings, 0 checks, 755 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/crc-debugfs: Also sprinkle irqrestore over early exits
== Series Details == Series: drm/crc-debugfs: Also sprinkle irqrestore over early exits URL : https://patchwork.freedesktop.org/series/61731/ State : warning == Summary == $ dim checkpatch origin/drm-tip 31e4149411c8 drm/crc-debugfs: Also sprinkle irqrestore over early exits -:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 16 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 5/8] drm/i915: split out uncore_mmio_debug
On 6/6/19 2:52 PM, Daniele Ceraolo Spurio wrote:
Multiple uncore structures will share the debug infrastructure, so
move it to a common place and add extra locking around it.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 66 -
drivers/gpu/drm/i915/intel_uncore.h | 10 -
4 files changed, 58 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9094736af5da..8fdd668eb7c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -897,6 +897,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
spin_lock_init(_priv->irq_lock);
spin_lock_init(_priv->gpu_error.lock);
+ spin_lock_init(_priv->mmio_debug.lock);
This should be intel_uncore_mmio_debug_init_early() and done before
intel_uncore_init_early, I forgot to squash the fix in.
Daniele
mutex_init(_priv->backlight_lock);
mutex_init(_priv->sb_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0539b837df5..5522132a2ad2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1398,6 +1398,7 @@ struct drm_i915_private {
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
struct intel_uncore uncore;
+ struct intel_uncore_mmio_debug mmio_debug;
struct i915_virtual_gpu vgpu;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 7ebea00207a6..8e42476ea4a7 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -34,6 +34,13 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+void
+intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
+{
+ spin_lock_init(_debug->lock);
+ mmio_debug->unclaimed_mmio_check = 1;
+}
+
static const char * const forcewake_domain_names[] = {
"render",
"blitter",
@@ -473,6 +480,8 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
bool ret = false;
+ lockdep_assert_held(>debug->lock);
+
if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
ret |= fpga_check_for_unclaimed_mmio(uncore);
@@ -489,7 +498,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
unsigned int restore_forcewake)
{
/* clear out unclaimed reg detection bit */
- if (check_for_unclaimed_mmio(uncore))
+ if (intel_uncore_unclaimed_mmio(uncore))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
/* WaDisableShadowRegForCpd:chv */
@@ -595,18 +604,20 @@ void intel_uncore_forcewake_get(struct intel_uncore
*uncore,
void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
{
spin_lock_irq(>lock);
+ spin_lock_irq(>debug->lock);
if (!uncore->user_forcewake.count++) {
intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
/* Save and disable mmio debugging for the user bypass */
uncore->user_forcewake.saved_mmio_check =
- uncore->unclaimed_mmio_check;
+ uncore->debug->unclaimed_mmio_check;
uncore->user_forcewake.saved_mmio_debug =
i915_modparams.mmio_debug;
- uncore->unclaimed_mmio_check = 0;
+ uncore->debug->unclaimed_mmio_check = 0;
i915_modparams.mmio_debug = 0;
}
+ spin_unlock_irq(>debug->lock);
spin_unlock_irq(>lock);
}
@@ -620,18 +631,20 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
{
spin_lock_irq(>lock);
+ spin_lock_irq(>debug->lock);
if (!--uncore->user_forcewake.count) {
- if (intel_uncore_unclaimed_mmio(uncore))
+ if (check_for_unclaimed_mmio(uncore))
dev_info(uncore_to_i915(uncore)->drm.dev,
"Invalid mmio detected during user access\n");
- uncore->unclaimed_mmio_check =
+ uncore->debug->unclaimed_mmio_check =
uncore->user_forcewake.saved_mmio_check;
i915_modparams.mmio_debug =
uncore->user_forcewake.saved_mmio_debug;
intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
}
+ spin_unlock_irq(>debug->lock);
spin_unlock_irq(>lock);
}
@@ -1044,12 +1057,19 @@ static inline void
unclaimed_reg_debug(struct intel_uncore *uncore,
const i915_reg_t reg,
const bool read,
- const bool before)
+ const
[Intel-gfx] [RFC 5/8] drm/i915: split out uncore_mmio_debug
Multiple uncore structures will share the debug infrastructure, so
move it to a common place and add extra locking around it.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 66 -
drivers/gpu/drm/i915/intel_uncore.h | 10 -
4 files changed, 58 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9094736af5da..8fdd668eb7c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -897,6 +897,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
spin_lock_init(_priv->irq_lock);
spin_lock_init(_priv->gpu_error.lock);
+ spin_lock_init(_priv->mmio_debug.lock);
mutex_init(_priv->backlight_lock);
mutex_init(_priv->sb_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0539b837df5..5522132a2ad2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1398,6 +1398,7 @@ struct drm_i915_private {
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
struct intel_uncore uncore;
+ struct intel_uncore_mmio_debug mmio_debug;
struct i915_virtual_gpu vgpu;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 7ebea00207a6..8e42476ea4a7 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -34,6 +34,13 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+void
+intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
+{
+ spin_lock_init(_debug->lock);
+ mmio_debug->unclaimed_mmio_check = 1;
+}
+
static const char * const forcewake_domain_names[] = {
"render",
"blitter",
@@ -473,6 +480,8 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
bool ret = false;
+ lockdep_assert_held(>debug->lock);
+
if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
ret |= fpga_check_for_unclaimed_mmio(uncore);
@@ -489,7 +498,7 @@ static void __intel_uncore_early_sanitize(struct
intel_uncore *uncore,
unsigned int restore_forcewake)
{
/* clear out unclaimed reg detection bit */
- if (check_for_unclaimed_mmio(uncore))
+ if (intel_uncore_unclaimed_mmio(uncore))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
/* WaDisableShadowRegForCpd:chv */
@@ -595,18 +604,20 @@ void intel_uncore_forcewake_get(struct intel_uncore
*uncore,
void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
{
spin_lock_irq(>lock);
+ spin_lock_irq(>debug->lock);
if (!uncore->user_forcewake.count++) {
intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
/* Save and disable mmio debugging for the user bypass */
uncore->user_forcewake.saved_mmio_check =
- uncore->unclaimed_mmio_check;
+ uncore->debug->unclaimed_mmio_check;
uncore->user_forcewake.saved_mmio_debug =
i915_modparams.mmio_debug;
- uncore->unclaimed_mmio_check = 0;
+ uncore->debug->unclaimed_mmio_check = 0;
i915_modparams.mmio_debug = 0;
}
+ spin_unlock_irq(>debug->lock);
spin_unlock_irq(>lock);
}
@@ -620,18 +631,20 @@ void intel_uncore_forcewake_user_get(struct intel_uncore
*uncore)
void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
{
spin_lock_irq(>lock);
+ spin_lock_irq(>debug->lock);
if (!--uncore->user_forcewake.count) {
- if (intel_uncore_unclaimed_mmio(uncore))
+ if (check_for_unclaimed_mmio(uncore))
dev_info(uncore_to_i915(uncore)->drm.dev,
"Invalid mmio detected during user access\n");
- uncore->unclaimed_mmio_check =
+ uncore->debug->unclaimed_mmio_check =
uncore->user_forcewake.saved_mmio_check;
i915_modparams.mmio_debug =
uncore->user_forcewake.saved_mmio_debug;
intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
}
+ spin_unlock_irq(>debug->lock);
spin_unlock_irq(>lock);
}
@@ -1044,12 +1057,19 @@ static inline void
unclaimed_reg_debug(struct intel_uncore *uncore,
const i915_reg_t reg,
const bool read,
- const bool before)
+ const bool before,
+ unsigned long *irqflags)
{
if (likely(!i915_modparams.mmio_debug))
return;
+ if (before)
+
[Intel-gfx] [RFC 6/8] drm/i915: drop forcewake_user_get/put
Now that we've split out the mmio_debug, we can manipulate that
independently from the debugfs and just call the normal forcewake
get/put functions.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 80 +
drivers/gpu/drm/i915/intel_uncore.h | 14 ++---
5 files changed, 45 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f212241a2758..7e69829008e6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1391,7 +1391,7 @@ static int i915_forcewake_domains(struct seq_file *m,
void *data)
unsigned int tmp;
seq_printf(m, "user.bypass_count = %u\n",
- uncore->user_forcewake.count);
+ atomic_read(>user_forcewake_count));
for_each_fw_domain(fw_domain, uncore, tmp)
seq_printf(m, "%s.wake_count = %u\n",
@@ -4219,7 +4219,11 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
return 0;
file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915);
- intel_uncore_forcewake_user_get(>uncore);
+
+ if (atomic_inc_return(>user_forcewake_count) == 1) {
+ intel_uncore_forcewake_get(>uncore, FORCEWAKE_ALL);
+ intel_uncore_mmio_debug_suspend(>mmio_debug);
+ }
return 0;
}
@@ -4231,9 +4235,14 @@ static int i915_forcewake_release(struct inode *inode,
struct file *file)
if (INTEL_GEN(i915) < 6)
return 0;
- intel_uncore_forcewake_user_put(>uncore);
- intel_runtime_pm_put(i915,
-(intel_wakeref_t)(uintptr_t)file->private_data);
+ if (atomic_dec_and_test(>user_forcewake_count)) {
+ if (intel_uncore_unclaimed_mmio(>uncore))
+ dev_info(i915->drm.dev,
+"Invalid mmio detected during user access\n");
+
+ intel_uncore_mmio_debug_resume(>mmio_debug);
+ intel_uncore_forcewake_put(>uncore, FORCEWAKE_ALL);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8fdd668eb7c7..024f270f6f00 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2187,7 +2187,7 @@ static int i915_drm_suspend_late(struct drm_device *dev,
bool hibernation)
out:
enable_rpm_wakeref_asserts(dev_priv);
- if (!dev_priv->uncore.user_forcewake.count)
+ if (!atomic_read(_priv->user_forcewake_count))
intel_runtime_pm_cleanup(dev_priv);
return ret;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5522132a2ad2..dc6b3e4af575 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1399,6 +1399,7 @@ struct drm_i915_private {
struct intel_uncore uncore;
struct intel_uncore_mmio_debug mmio_debug;
+ atomic_t user_forcewake_count;
struct i915_virtual_gpu vgpu;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8e42476ea4a7..c460426b0562 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -41,6 +41,28 @@ intel_uncore_mmio_debug_init_early(struct
intel_uncore_mmio_debug *mmio_debug)
mmio_debug->unclaimed_mmio_check = 1;
}
+/* Save and disable mmio debugging for the user bypass */
+void intel_uncore_mmio_debug_suspend(struct intel_uncore_mmio_debug
*mmio_debug)
+{
+ spin_lock_irq(_debug->lock);
+ if (!mmio_debug->suspended) {
+ mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
+ mmio_debug->unclaimed_mmio_check = 0;
+ mmio_debug->suspended = true;
+ }
+ spin_unlock_irq(_debug->lock);
+}
+
+void intel_uncore_mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
+{
+ spin_lock_irq(_debug->lock);
+ if (mmio_debug->suspended) {
+ mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
+ mmio_debug->suspended = false;
+ }
+ spin_unlock_irq(_debug->lock);
+}
+
static const char * const forcewake_domain_names[] = {
"render",
"blitter",
@@ -482,6 +504,9 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore)
lockdep_assert_held(>debug->lock);
+ if (uncore->debug->suspended)
+ return false;
+
if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
ret |= fpga_check_for_unclaimed_mmio(uncore);
@@ -593,61 +618,6 @@ void intel_uncore_forcewake_get(struct intel_uncore
*uncore,
spin_unlock_irqrestore(>lock, irqflags);
}
-/**
- * intel_uncore_forcewake_user_get - claim
[Intel-gfx] [RFC 8/8] drm/i915: move intel_hdmi to de_uncore
As an example of usage of the new structure
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_hdmi.c | 275 --
1 file changed, 151 insertions(+), 124 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 097bfa504ece..2d0a551a4c0b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -72,7 +72,8 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
- WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
+ WARN(intel_uncore_read(_priv->de_uncore, intel_hdmi->hdmi_reg) &
+enabled_bits,
"HDMI port enabled, expecting disabled\n");
}
@@ -80,7 +81,8 @@ static void
assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder)
{
- WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
+ WARN(intel_uncore_read(_priv->de_uncore,
+ TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
TRANS_DDI_FUNC_ENABLE,
"HDMI transcoder function enabled, expecting disabled\n");
}
@@ -208,7 +210,8 @@ static void g4x_write_infoframe(struct intel_encoder
*encoder,
{
const u32 *data = frame;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 val = I915_READ(VIDEO_DIP_CTL);
+ struct intel_uncore *uncore = _priv->de_uncore;
+ u32 val = intel_uncore_read(uncore, VIDEO_DIP_CTL);
int i;
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
@@ -218,22 +221,22 @@ static void g4x_write_infoframe(struct intel_encoder
*encoder,
val &= ~g4x_infoframe_enable(type);
- I915_WRITE(VIDEO_DIP_CTL, val);
+ intel_uncore_write(uncore, VIDEO_DIP_CTL, val);
for (i = 0; i < len; i += 4) {
- I915_WRITE(VIDEO_DIP_DATA, *data);
+ intel_uncore_write(uncore, VIDEO_DIP_DATA, *data);
data++;
}
/* Write every possible data byte to force correct ECC calculation. */
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
- I915_WRITE(VIDEO_DIP_DATA, 0);
+ intel_uncore_write(uncore, VIDEO_DIP_DATA, 0);
val |= g4x_infoframe_enable(type);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC;
- I915_WRITE(VIDEO_DIP_CTL, val);
- POSTING_READ(VIDEO_DIP_CTL);
+ intel_uncore_write(uncore, VIDEO_DIP_CTL, val);
+ intel_uncore_posting_read(uncore, VIDEO_DIP_CTL);
}
static void g4x_read_infoframe(struct intel_encoder *encoder,
@@ -242,25 +245,26 @@ static void g4x_read_infoframe(struct intel_encoder
*encoder,
void *frame, ssize_t len)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_uncore *uncore = _priv->de_uncore;
u32 val, *data = frame;
int i;
- val = I915_READ(VIDEO_DIP_CTL);
+ val = intel_uncore_read(uncore, VIDEO_DIP_CTL);
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
val |= g4x_infoframe_index(type);
- I915_WRITE(VIDEO_DIP_CTL, val);
+ intel_uncore_write(uncore, VIDEO_DIP_CTL, val);
for (i = 0; i < len; i += 4)
- *data++ = I915_READ(VIDEO_DIP_DATA);
+ *data++ = intel_uncore_read(uncore, VIDEO_DIP_DATA);
}
static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 val = I915_READ(VIDEO_DIP_CTL);
+ u32 val = intel_uncore_read(_priv->de_uncore, VIDEO_DIP_CTL);
if ((val & VIDEO_DIP_ENABLE) == 0)
return 0;
@@ -279,9 +283,10 @@ static void ibx_write_infoframe(struct intel_encoder
*encoder,
{
const u32 *data = frame;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_uncore *uncore = _priv->de_uncore;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
- u32 val = I915_READ(reg);
+ u32 val = intel_uncore_read(uncore, reg);
int i;
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
@@ -291,22 +296,22 @@ static void ibx_write_infoframe(struct intel_encoder
*encoder,
val &= ~g4x_infoframe_enable(type);
- I915_WRITE(reg, val);
+ intel_uncore_write(uncore, reg, val);
for (i = 0; i < len; i += 4) {
- I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+ intel_uncore_write(uncore, TVIDEO_DIP_DATA(intel_crtc->pipe),
*data);
data++;
}
/* Write every possible
[Intel-gfx] [RFC 4/8] drm/i915: explicitly prune forcewake domain
When we know which engines we're fusing off we can immediately remove
the corresponding forcewake domain, no need to go though the masks
again.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 2 --
drivers/gpu/drm/i915/intel_device_info.c | 4 +++
drivers/gpu/drm/i915/intel_uncore.c | 32
drivers/gpu/drm/i915/intel_uncore.h | 3 ++-
4 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 05ee328e3f66..9094736af5da 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -995,8 +995,6 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
intel_device_info_init_mmio(dev_priv);
- intel_uncore_prune_mmio_domains(_priv->uncore);
-
intel_uc_init_mmio(dev_priv);
ret = intel_engines_init_mmio(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 97f742530fa1..48d159d9e42a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1027,6 +1027,8 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
if (!(BIT(i) & vdbox_mask)) {
info->engine_mask &= ~BIT(_VCS(i));
+ intel_uncore_fw_domain_prune(_priv->uncore,
+FW_DOMAIN_ID_MEDIA_VDBOX0
+ i);
DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
continue;
}
@@ -1048,6 +1050,8 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
if (!(BIT(i) & vebox_mask)) {
info->engine_mask &= ~BIT(_VECS(i));
+ intel_uncore_fw_domain_prune(_priv->uncore,
+FW_DOMAIN_ID_MEDIA_VEBOX0
+ i);
DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
}
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 30650e6e2f54..7ebea00207a6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1659,35 +1659,13 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
* the forcewake domains. Prune them, to make sure they only reference existing
* engines.
*/
-void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
+void intel_uncore_fw_domain_prune(struct intel_uncore *uncore,
+ enum forcewake_domain_id domain_id)
{
- struct drm_i915_private *i915 = uncore_to_i915(uncore);
-
- if (INTEL_GEN(i915) >= 11) {
- enum forcewake_domains fw_domains = uncore->fw_domains;
- enum forcewake_domain_id domain_id;
- int i;
-
- for (i = 0; i < I915_MAX_VCS; i++) {
- domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
-
- if (HAS_ENGINE(i915, _VCS(i)))
- continue;
-
- if (fw_domains & BIT(domain_id))
- fw_domain_fini(uncore, domain_id);
- }
-
- for (i = 0; i < I915_MAX_VECS; i++) {
- domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
-
- if (HAS_ENGINE(i915, _VECS(i)))
- continue;
+ if (WARN_ON(!(uncore->fw_domains & BIT(domain_id
+ return;
- if (fw_domains & BIT(domain_id))
- fw_domain_fini(uncore, domain_id);
- }
- }
+ fw_domain_fini(uncore, domain_id);
}
void intel_uncore_fini_mmio(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 2bb80962e7c5..b2de47da053f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -179,7 +179,8 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore)
void intel_uncore_init_early(struct intel_uncore *uncore);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
-void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore);
+void intel_uncore_fw_domain_prune(struct intel_uncore *uncore,
+ enum forcewake_domain_id domain_id);
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
void intel_uncore_fini_mmio(struct intel_uncore *uncore);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 3/8] drm/i915: dynamically allocate forcewake domains
In an upcoming patch we will introduce a display uncore with no forcewake
domains, so let's avoid wasting memory and be ready to allocate only what
we need.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uncore.c | 141 +---
drivers/gpu/drm/i915/intel_uncore.h | 13 +--
2 files changed, 92 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index ef7eed9237a0..30650e6e2f54 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -344,7 +344,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
{
struct intel_uncore_forcewake_domain *domain =
container_of(timer, struct intel_uncore_forcewake_domain, timer);
- struct intel_uncore *uncore = forcewake_domain_to_uncore(domain);
+ struct intel_uncore *uncore = domain->uncore;
unsigned long irqflags;
assert_rpm_device_not_suspended(uncore->rpm);
@@ -1283,23 +1283,24 @@ do { \
(uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
} while (0)
-static void fw_domain_init(struct intel_uncore *uncore,
+static int fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
i915_reg_t reg_set,
i915_reg_t reg_ack)
{
struct intel_uncore_forcewake_domain *d;
- if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
- return;
-
- d = >fw_domain[domain_id];
+ GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
+ GEM_BUG_ON(uncore->fw_domain[domain_id]);
- WARN_ON(d->wake_count);
+ d = kzalloc(sizeof(*d), GFP_KERNEL);
+ if (!d)
+ return -ENOMEM;
WARN_ON(!i915_mmio_reg_valid(reg_set));
WARN_ON(!i915_mmio_reg_valid(reg_ack));
+ d->uncore = uncore;
d->wake_count = 0;
d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
@@ -1325,6 +1326,10 @@ static void fw_domain_init(struct intel_uncore *uncore,
uncore->fw_domains |= BIT(domain_id);
fw_domain_reset(d);
+
+ uncore->fw_domain[domain_id] = d;
+
+ return 0;
}
static void fw_domain_fini(struct intel_uncore *uncore,
@@ -1332,78 +1337,93 @@ static void fw_domain_fini(struct intel_uncore *uncore,
{
struct intel_uncore_forcewake_domain *d;
- if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
- return;
+ GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
- d = >fw_domain[domain_id];
+ d = fetch_and_zero(>fw_domain[domain_id]);
+ uncore->fw_domains &= ~BIT(domain_id);
- WARN_ON(d->wake_count);
- WARN_ON(hrtimer_cancel(>timer));
- memset(d, 0, sizeof(*d));
+ if (d) {
+ WARN_ON(d->wake_count);
+ WARN_ON(hrtimer_cancel(>timer));
+ kfree(d);
+ }
+}
- uncore->fw_domains &= ~BIT(domain_id);
+static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
+{
+ struct intel_uncore_forcewake_domain *d;
+ int tmp;
+
+ for_each_fw_domain(d, uncore, tmp)
+ fw_domain_fini(uncore, d->id);
}
-static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
+static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore_to_i915(uncore);
+ int ret;
+
+#define __fw_domain_init(id, set, ack) \
+ ret = fw_domain_init(uncore, id, set, ack); \
+ if (ret) \
+ goto out_clean;
if (!intel_uncore_has_forcewake(uncore))
- return;
+ return 0;
if (INTEL_GEN(i915) >= 11) {
int i;
- uncore->funcs.force_wake_get =
- fw_domains_get_with_fallback;
+ uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
uncore->funcs.force_wake_put = fw_domains_put;
- fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
- FORCEWAKE_RENDER_GEN9,
- FORCEWAKE_ACK_RENDER_GEN9);
- fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
- FORCEWAKE_BLITTER_GEN9,
- FORCEWAKE_ACK_BLITTER_GEN9);
+ __fw_domain_init(FW_DOMAIN_ID_RENDER,
+FORCEWAKE_RENDER_GEN9,
+FORCEWAKE_ACK_RENDER_GEN9);
+ __fw_domain_init(FW_DOMAIN_ID_BLITTER,
+FORCEWAKE_BLITTER_GEN9,
+FORCEWAKE_ACK_BLITTER_GEN9);
+
for (i = 0; i < I915_MAX_VCS; i++) {
if (!HAS_ENGINE(i915, _VCS(i)))
continue;
- fw_domain_init(uncore,
[Intel-gfx] [RFC 0/8] Display uncore
Very rough RFC on splitting GT and display register access to give an idea of what I was aiming at since this came back into discussion on IRC. The first few patches are mainly cleanup and reduction of the usage of uncore_to_i915. I originally planned to kill uncore_to_i915 entirely but I see more users are appearing in patches in flight so I've dropped the removal patch and added an hack to the function ot handle 2 uncores (yes, I really really want to avoid getting a pointer to i915!). I'm not convinced in regard to the mmio_debug implementation (patch 5), so if people think this split make sense any feedback in that area is welcome. Any feedback in other areas is obviously just as welcome. The last patch is an example of adaptation for the HDMI code. Suggested-by: Chris Wilson Cc: Chris Wilson Cc: Ville Syrjälä Daniele Ceraolo Spurio (8): drm/i915: use vfuncs for reg_read/write_fw_domains drm/i915: kill uncore_sanitize drm/i915: dynamically allocate forcewake domains drm/i915: explicitly prune forcewake domain drm/i915: split out uncore_mmio_debug drm/i915: drop forcewake_user_get/put drm/i915: introduce display_uncore drm/i915: move intel_hdmi to de_uncore drivers/gpu/drm/i915/i915_debugfs.c | 19 +- drivers/gpu/drm/i915/i915_drv.c | 31 +- drivers/gpu/drm/i915/i915_drv.h | 8 +- drivers/gpu/drm/i915/intel_device_info.c | 4 + drivers/gpu/drm/i915/intel_hdmi.c| 275 +- drivers/gpu/drm/i915/intel_uncore.c | 507 +-- drivers/gpu/drm/i915/intel_uncore.h | 55 +- drivers/gpu/drm/i915/selftests/mock_uncore.c | 4 +- 8 files changed, 475 insertions(+), 428 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/8] drm/i915: kill uncore_sanitize
uncore_sanitize performs no action on the uncore structure and just
calls intel_sanitize_gt_powersave, so we can just call the latter
directly.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 12 ++--
drivers/gpu/drm/i915/intel_uncore.c | 9 -
drivers/gpu/drm/i915/intel_uncore.h | 1 -
3 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1af6751e1b36..05ee328e3f66 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1622,7 +1622,8 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
pm_qos_add_request(_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
- intel_uncore_sanitize(dev_priv);
+ /* BIOS often leaves RC6 enabled, but disable it for hw init */
+ intel_sanitize_gt_powersave(dev_priv);
intel_gt_init_workarounds(dev_priv);
i915_gem_load_init_fences(dev_priv);
@@ -1915,6 +1916,9 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
out_cleanup_hw:
i915_driver_cleanup_hw(dev_priv);
i915_ggtt_cleanup_hw(dev_priv);
+
+ /* Paranoia: make sure we have disabled everything before we exit. */
+ intel_sanitize_gt_powersave(dev_priv);
out_cleanup_mmio:
i915_driver_cleanup_mmio(dev_priv);
out_runtime_pm_put:
@@ -1984,6 +1988,10 @@ static void i915_driver_release(struct drm_device *dev)
i915_gem_fini(dev_priv);
i915_ggtt_cleanup_hw(dev_priv);
+
+ /* Paranoia: make sure we have disabled everything before we exit. */
+ intel_sanitize_gt_powersave(dev_priv);
+
i915_driver_cleanup_mmio(dev_priv);
enable_rpm_wakeref_asserts(dev_priv);
@@ -2349,7 +2357,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
hsw_disable_pc8(dev_priv);
}
- intel_uncore_sanitize(dev_priv);
+ intel_sanitize_gt_powersave(dev_priv);
intel_power_domains_resume(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index c3be79c4957b..ef7eed9237a0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -537,12 +537,6 @@ void intel_uncore_runtime_resume(struct intel_uncore
*uncore)
iosf_mbi_register_pmic_bus_access_notifier(>pmic_bus_access_nb);
}
-void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
-{
- /* BIOS often leaves RC6 enabled, but disable it for hw init */
- intel_sanitize_gt_powersave(dev_priv);
-}
-
static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
@@ -1664,9 +1658,6 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore
*uncore)
void intel_uncore_fini_mmio(struct intel_uncore *uncore)
{
- /* Paranoia: make sure we have disabled everything before we exit. */
- intel_uncore_sanitize(uncore_to_i915(uncore));
-
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
>pmic_bus_access_nb);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 72ef8b262930..bf06b6b16892 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -182,7 +182,6 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore)
return uncore->flags & UNCORE_HAS_FIFO;
}
-void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
void intel_uncore_init_early(struct intel_uncore *uncore);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 1/8] drm/i915: use vfuncs for reg_read/write_fw_domains
Instead of going through the if-else chain every time, let's save the
function in the uncore structure. Note that the new functions are
purposely not used from the reg read/write functions to keep the
inlining there.
While at it, use the new macro to call the old ones to clean the code a
bit.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uncore.c | 172 ---
drivers/gpu/drm/i915/intel_uncore.h | 5 +
drivers/gpu/drm/i915/selftests/mock_uncore.c | 4 +-
3 files changed, 75 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index f78668123f02..c3be79c4957b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -901,6 +901,12 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
+static enum forcewake_domains
+gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
+{
+ return FORCEWAKE_RENDER;
+}
+
#define __gen8_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
@@ -1145,26 +1151,23 @@ func##_read##x(struct intel_uncore *uncore, i915_reg_t
reg, bool trace) { \
val = __raw_uncore_read##x(uncore, reg); \
GEN6_READ_FOOTER; \
}
-#define __gen6_read(x) __gen_read(gen6, x)
-#define __fwtable_read(x) __gen_read(fwtable, x)
-#define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
-
-__gen11_fwtable_read(8)
-__gen11_fwtable_read(16)
-__gen11_fwtable_read(32)
-__gen11_fwtable_read(64)
-__fwtable_read(8)
-__fwtable_read(16)
-__fwtable_read(32)
-__fwtable_read(64)
-__gen6_read(8)
-__gen6_read(16)
-__gen6_read(32)
-__gen6_read(64)
-
-#undef __gen11_fwtable_read
-#undef __fwtable_read
-#undef __gen6_read
+
+#define __gen_reg_read_funcs(func) \
+static enum forcewake_domains \
+func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
+ return __##func##_reg_read_fw_domains(uncore,
i915_mmio_reg_offset(reg)); \
+} \
+\
+__gen_read(func, 8) \
+__gen_read(func, 16) \
+__gen_read(func, 32) \
+__gen_read(func, 64)
+
+__gen_reg_read_funcs(gen11_fwtable);
+__gen_reg_read_funcs(fwtable);
+__gen_reg_read_funcs(gen6);
+
+#undef __gen_reg_read_funcs
#undef GEN6_READ_FOOTER
#undef GEN6_READ_HEADER
@@ -1225,6 +1228,9 @@ gen6_write##x(struct intel_uncore *uncore, i915_reg_t
reg, u##x val, bool trace)
__raw_uncore_write##x(uncore, reg, val); \
GEN6_WRITE_FOOTER; \
}
+__gen6_write(8)
+__gen6_write(16)
+__gen6_write(32)
#define __gen_write(func, x) \
static void \
@@ -1237,38 +1243,33 @@ func##_write##x(struct intel_uncore *uncore, i915_reg_t
reg, u##x val, bool trac
__raw_uncore_write##x(uncore, reg, val); \
GEN6_WRITE_FOOTER; \
}
-#define __gen8_write(x) __gen_write(gen8, x)
-#define __fwtable_write(x) __gen_write(fwtable, x)
-#define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
-
-__gen11_fwtable_write(8)
-__gen11_fwtable_write(16)
-__gen11_fwtable_write(32)
-__fwtable_write(8)
-__fwtable_write(16)
-__fwtable_write(32)
-__gen8_write(8)
-__gen8_write(16)
-__gen8_write(32)
-__gen6_write(8)
-__gen6_write(16)
-__gen6_write(32)
-#undef __gen11_fwtable_write
-#undef __fwtable_write
-#undef __gen8_write
-#undef __gen6_write
+#define __gen_reg_write_funcs(func) \
+static enum forcewake_domains \
+func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
+ return __##func##_reg_write_fw_domains(uncore,
i915_mmio_reg_offset(reg)); \
+} \
+\
+__gen_write(func, 8) \
+__gen_write(func, 16) \
+__gen_write(func, 32)
+
+__gen_reg_write_funcs(gen11_fwtable);
+__gen_reg_write_funcs(fwtable);
+__gen_reg_write_funcs(gen8);
+
+#undef __gen_reg_write_funcs
#undef GEN6_WRITE_FOOTER
#undef GEN6_WRITE_HEADER
-#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
+#define ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, x) \
do { \
(uncore)->funcs.mmio_writeb = x##_write8; \
(uncore)->funcs.mmio_writew = x##_write16; \
(uncore)->funcs.mmio_writel = x##_write32; \
} while (0)
-#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
+#define ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, x) \
do { \
(uncore)->funcs.mmio_readb = x##_read8; \
(uncore)->funcs.mmio_readw = x##_read16; \
@@ -1276,6 +1277,17 @@ do { \
(uncore)->funcs.mmio_readq = x##_read64; \
} while (0)
+#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
+do { \
+ ASSIGN_WRITE_MMIO_VFUNCS_NO_FW((uncore), x); \
+ (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
+} while (0)
+
+#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
+do { \
+ ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, x); \
+ (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
+} while (0)
static void fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
@@ -1559,11 +1571,11 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
[Intel-gfx] [RFC 7/8] drm/i915: introduce display_uncore
A forcewake-less uncore to be used to decouple GT accesses from display
ones to avoid serializing them when there is no need.
All the uncore suspend/resume functions are forcewake-related, so no
need to call them for display_uncore.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 14 +++---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_uncore.c | 23 +--
drivers/gpu/drm/i915/intel_uncore.h | 9 -
4 files changed, 41 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 024f270f6f00..635024cad005 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -893,7 +893,8 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
intel_device_info_subplatform_init(dev_priv);
- intel_uncore_init_early(_priv->uncore);
+ intel_uncore_init_early(_priv->uncore, 0);
+ intel_uncore_init_early(_priv->de_uncore, UNCORE_IS_DISPLAY);
spin_lock_init(_priv->irq_lock);
spin_lock_init(_priv->gpu_error.lock);
@@ -991,6 +992,10 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
if (ret < 0)
goto err_bridge;
+ ret = intel_uncore_init_mmio(_priv->de_uncore);
+ if (ret < 0)
+ goto err_uncore;
+
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
@@ -1000,14 +1005,16 @@ static int i915_driver_init_mmio(struct
drm_i915_private *dev_priv)
ret = intel_engines_init_mmio(dev_priv);
if (ret)
- goto err_uncore;
+ goto err_mchbar;
i915_gem_init_mmio(dev_priv);
return 0;
-err_uncore:
+err_mchbar:
intel_teardown_mchbar(dev_priv);
+ intel_uncore_fini_mmio(_priv->de_uncore);
+err_uncore:
intel_uncore_fini_mmio(_priv->uncore);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -1022,6 +1029,7 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
intel_teardown_mchbar(dev_priv);
+ intel_uncore_fini_mmio(_priv->de_uncore);
intel_uncore_fini_mmio(_priv->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dc6b3e4af575..87dcc7addc53 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1398,6 +1398,7 @@ struct drm_i915_private {
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
struct intel_uncore uncore;
+ struct intel_uncore de_uncore;
struct intel_uncore_mmio_debug mmio_debug;
atomic_t user_forcewake_count;
@@ -2013,7 +2014,10 @@ static inline struct drm_i915_private
*huc_to_i915(struct intel_huc *huc)
static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore
*uncore)
{
- return container_of(uncore, struct drm_i915_private, uncore);
+ if (intel_uncore_is_display(uncore))
+ return container_of(uncore, struct drm_i915_private, de_uncore);
+ else
+ return container_of(uncore, struct drm_i915_private, uncore);
}
/* Simple iterator over all initialised engines */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index c460426b0562..64479a746f56 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -549,6 +549,9 @@ static void __intel_uncore_early_sanitize(struct
intel_uncore *uncore,
void intel_uncore_suspend(struct intel_uncore *uncore)
{
+ if (!intel_uncore_is_display(uncore))
+ return;
+
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
>pmic_bus_access_nb);
@@ -560,6 +563,9 @@ void intel_uncore_resume_early(struct intel_uncore *uncore)
{
unsigned int restore_forcewake;
+ if (!intel_uncore_is_display(uncore))
+ return;
+
restore_forcewake = fetch_and_zero(>fw_domains_saved);
__intel_uncore_early_sanitize(uncore, restore_forcewake);
@@ -568,6 +574,9 @@ void intel_uncore_resume_early(struct intel_uncore *uncore)
void intel_uncore_runtime_resume(struct intel_uncore *uncore)
{
+ if (!intel_uncore_is_display(uncore))
+ return;
+
iosf_mbi_register_pmic_bus_access_notifier(>pmic_bus_access_nb);
}
@@ -1556,9 +1565,10 @@ static void uncore_mmio_cleanup(struct intel_uncore
*uncore)
pci_iounmap(pdev, uncore->regs);
}
-void intel_uncore_init_early(struct intel_uncore *uncore)
+void intel_uncore_init_early(struct intel_uncore *uncore, u32 flags)
{
spin_lock_init(>lock);
+ uncore->flags = flags;
}
int intel_uncore_init_mmio(struct
Re: [Intel-gfx] [RFC] drm: Do not call drm_probe_ddc() when connector force isn't specified
On Thu, Jun 06, 2019 at 02:56:53PM +0300, Jani Nikula wrote:
> On Thu, 06 Jun 2019, Daniel Vetter wrote:
> > On Thu, Jun 6, 2019 at 9:38 AM Harish Chegondi
> > wrote:
> >>
> >> This would allow the EDID override to be handled correctly in
> >> drm_do_get_edid() for cases where EDID data is missing or corrupt.
> >>
> >> All drm_probe_ddc() does is call drm_do_probe_ddc_edid( , , , 1)
> >> which probes the display by reading 1 byte of EDID data via I2C.
> >> This patch removes the call to drm_probe_ddc() from drm_get_edid()
> >> but drm_get_edid() calls drm_do_get_edid() which first handles
> >> the EDID override case and then calls
> >> drm_do_probe_ddc_edid( , , ,EDID_LENGTH) via function pointer
> >> argument get_edid_block. So, the display device is still being
> >> probed by reading EDID_LENGTH bytes of EDID data via I2C.
> >>
> >> Cc: Jani Nikula
> >> Cc: Ville Syrjälä
> >> Signed-off-by: Harish Chegondi
> >> References: https://bugs.freedesktop.org/show_bug.cgi?id=107583
> >
> > Since it's a regression we need to annotate this correctly, for the
> > next version please include:
> >
> > Fixes: 53fd40a90f3c ("drm: handle override and firmware EDID at
> > drm_do_get_edid() level")
> > Cc: # v4.15+
> >
> > So there's a pile more drm_probe_ddc calls all around in drivers, but
> > I reviewed them all, and they're all in ->detect callbacks. So not
> > affecting the regression we're discussing here. Looking at
> > drm_do_get_edid this should also not result in more failures. The only
> > thing this changes is that drm_do_get_edid will retry a bunch more
> > times if nothing is connected (4 times, instead of just the one probe
> > that drm_probe_ddc does). I guess we can restore that if anyone cares,
> > should at least mention it in the commit message.
> >
> > Reviewed-by: Daniel Vetter
>
> Like I explained in my reply, this essentially makes override/firmware
> EDID a connector force for the case where hotplug detect isn't used or
> reliable. That's a regression for another set of people...
>
> BR,
> Jani.
Hi Jani,
Can you please give more details on which regression this patch may
cause. Any specific test setup and IGT test would be helpful.
I will re-work my patch to make sure it doesn't cause any regression.
The CI BAT report didn't indicate any regressions for this patch.
Thank You
Harish.
>
>
> >
> >
> >> ---
> >> drivers/gpu/drm/drm_edid.c | 3 ---
> >> 1 file changed, 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> >> index d87f574feeca..41c420706532 100644
> >> --- a/drivers/gpu/drm/drm_edid.c
> >> +++ b/drivers/gpu/drm/drm_edid.c
> >> @@ -1724,9 +1724,6 @@ struct edid *drm_get_edid(struct drm_connector
> >> *connector,
> >> if (connector->force == DRM_FORCE_OFF)
> >> return NULL;
> >>
> >> - if (connector->force == DRM_FORCE_UNSPECIFIED &&
> >> !drm_probe_ddc(adapter))
> >> - return NULL;
> >
> > Trouble is there's a lot more drm_probe_ddc calls all over, and a lot of
> > these
> >> -
> >> edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
> >> if (edid)
> >> drm_get_displayid(connector, edid);
> >> --
> >> 2.21.0
> >>
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/crc-debugfs: Also sprinkle irqrestore over early exits
I. was. blind.
Caught with vkms, which has some really slow crc computation function.
Fixes: 1882018a70e0 ("drm/crc-debugfs: User irqsafe spinlock in
drm_crtc_add_crc_entry")
Cc: Rodrigo Siqueira
Cc: Tomeu Vizoso
Cc: Emil Velikov
Cc: Benjamin Gaignard
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_debugfs_crc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs_crc.c
b/drivers/gpu/drm/drm_debugfs_crc.c
index 7f35b5ba1924..d2f102f01515 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -402,7 +402,7 @@ int drm_crtc_add_crc_entry(struct drm_crtc *crtc, bool
has_frame,
/* Caller may not have noticed yet that userspace has stopped reading */
if (!crc->entries) {
- spin_unlock(>lock);
+ spin_unlock_irqrestore(>lock, flags);
return -EINVAL;
}
@@ -413,7 +413,7 @@ int drm_crtc_add_crc_entry(struct drm_crtc *crtc, bool
has_frame,
bool was_overflow = crc->overflow;
crc->overflow = true;
- spin_unlock(>lock);
+ spin_unlock_irqrestore(>lock, flags);
if (!was_overflow)
DRM_ERROR("Overflow of CRC buffer, userspace reads too
slow.\n");
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Update MOCS table for EHL
On Thu, May 30, 2019 at 4:40 PM Matt Roper wrote:
>
> EHL defines two new MOCS table entries but is otherwise compatible with
> the ICL MOCS table.
>
> These table entries (16 and 17) should still be considered unused for
> ICL and as such their behavior remains undefined for that platform.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 79df66022d3a..1f9db50b1869 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -200,6 +200,14 @@ static const struct drm_i915_mocs_entry
> broxton_mocs_table[] = {
> MOCS_ENTRY(15, \
>LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
>L3_3_WB), \
> + /* Bypass LLC - Uncached (EHL+) */ \
> + MOCS_ENTRY(16, \
> + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
> + L3_1_UC), \
> + /* Bypass LLC - L3 (Read-Only) (EHL+) */ \
> + MOCS_ENTRY(17, \
> + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
> + L3_3_WB), \
> /* Self-Snoop - L3 + LLC */ \
> MOCS_ENTRY(18, \
>LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
> --
Reviewed-by: Lucas De Marchi
Lucas De Marchi
> 2.14.5
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Deal with machines that expose less than three QGV points
Verified that patch fixes the issue. My ICL with SAGV forced to max now boots
to desktop with display.
This patch resolves my issue completely. Thanks for your help!
~Felix DeGrood
-Original Message-
From: Ville Syrjala
Sent: Thursday, June 06, 2019 5:42 AM
To: intel-gfx@lists.freedesktop.org
Cc: Degrood, Felix J ; Janes, Mark A
; Roper, Matthew D ; Taylor,
Clinton A
Subject: [PATCH] drm/i915: Deal with machines that expose less than three QGV
points
From: Ville Syrjälä
When SAGV is forced to disabled/min/med/max in the BIOS pcode will only hand us
a single QGV point instead of the normal three. Fix the code to deal with that
instead declaring the bandwidth limit to be 0 MB/s (and thus preventing any
planes from being enabled).
Also shrink the max_bw sturct a bit while at it, and change the deratedbw type
to unsigned since the code returns the bw as an unsigned int.
Since we now keep track of how many qgv points we got from pcode we can drop
the earlier check added for the "pcode doesn't support the memory subsystem
query" case.
Cc: felix.j.degr...@intel.com
Cc: Mark Janes
Cc: Matt Roper
Cc: Clint Taylor
Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on
ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++-- drivers/gpu/drm/i915/intel_bw.c |
15 ++-
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89bf1e34feaa..f4c7afebfa27 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1738,8 +1738,9 @@ struct drm_i915_private {
} dram_info;
struct intel_bw_info {
- int num_planes;
- int deratedbw[3];
+ unsigned int deratedbw[3]; /* for each QGV point */
+ u8 num_qgv_points;
+ u8 num_planes;
} max_bw[6];
struct drm_private_obj bw_obj;
diff --git a/drivers/gpu/drm/i915/intel_bw.c b/drivers/gpu/drm/i915/intel_bw.c
index 753ac3165061..7b908e10d32e 100644
--- a/drivers/gpu/drm/i915/intel_bw.c
+++ b/drivers/gpu/drm/i915/intel_bw.c
@@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv)
clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
+ bi->num_qgv_points = qi.num_points;
+
for (j = 0; j < qi.num_points; j++) {
const struct intel_qgv_point *sp = [j];
int ct, bw;
@@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv)
bi->deratedbw[j] = min(maxdebw,
bw * 9 / 10); /* 90% */
- DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d
deratedbw=%d\n",
+ DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d
deratedbw=%u\n",
i, j, bi->num_planes, bi->deratedbw[j]);
}
@@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private
*dev_priv, {
int i;
- /* Did we initialize the bw limits successfully? */
- if (dev_priv->max_bw[0].num_planes == 0)
- return UINT_MAX;
-
for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
const struct intel_bw_info *bi =
_priv->max_bw[i];
+ /*
+* Pcode will not expose all QGV points when
+* SAGV is forced to off/min/med/max.
+*/
+ if (qgv_point >= bi->num_qgv_points)
+ return UINT_MAX;
+
if (num_planes >= bi->num_planes)
return bi->deratedbw[qgv_point];
}
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Assume combo PHY HBR3 will be inherited by future platforms
== Series Details ==
Series: drm/i915: Assume combo PHY HBR3 will be inherited by future platforms
URL : https://patchwork.freedesktop.org/series/61724/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6210 -> Patchwork_13194
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/
Known issues
Here are the changes found in Patchwork_13194 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@basic-default:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#108569])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-icl-u2/igt@gem_ctx_swi...@basic-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-icl-u2/igt@gem_ctx_swi...@basic-default.html
* igt@gem_exec_fence@basic-busy-default:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-icl-y/igt@gem_exec_fe...@basic-busy-default.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-icl-y/igt@gem_exec_fe...@basic-busy-default.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [DMESG-WARN][11] ([fdo#106107]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-kbl-7560u/igt@i915_module_l...@reload-with-fault-injection.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-kbl-7560u/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][13] ([fdo#105541]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [DMESG-FAIL][15] ([fdo#110235]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: [DMESG-WARN][17] ([fdo#107709]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-bsw-kefka/igt@i915_selftest@live_evict.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-bsw-kefka/igt@i915_selftest@live_evict.html
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20] +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][21] ([fdo#103167]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-read:
- fi-icl-dsi: [INCOMPLETE][23] ([fdo#107713]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6210/fi-icl-dsi/igt@prime_v...@basic-fence-read.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13194/fi-icl-dsi/igt@prime_v...@basic-fence-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]:
[Intel-gfx] [PATCH] drm/i915: Assume combo PHY HBR3 will be inherited by future platforms
We shouldn't assume that HBR3 on combo PHYs is an EHL-specific
capability. Let's follow the standard i915 convention of assuming
future platforms will inherit all features of the latest platform.
Fixes: b71438606343 ("drm/i915/ehl: Support HBR3 on EHL combo PHY")
Cc: Manasi Navare
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b099a9dc28fd..4e2a06513e7d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -332,7 +332,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
enum port port = dig_port->base.port;
if (intel_port_is_combophy(dev_priv, port) &&
- !IS_ELKHARTLAKE(dev_priv) &&
+ IS_ICELAKE(dev_priv) &&
!intel_dp_is_edp(intel_dp))
return 54;
--
2.14.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_balancer: Fix typo in memcpy
Fixes: c26e76418f49 ("tests/gem_exec_balancer: Manually calculate VLA struct
sizes")
Signed-off-by: Chris Wilson
Cc: Arkadiusz Hiler
---
tests/i915/gem_exec_balancer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index bb4911e17..b2074486a 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -123,7 +123,7 @@ static int __set_engines(int i915, uint32_t ctx,
};
engines->extensions = 0;
- memcpy(engines->engines, ci, sizeof(*ci));
+ memcpy(engines->engines, ci, count * sizeof(*ci));
return __gem_context_set_param(i915, );
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Support HBR3 on EHL combo PHY
On Thu, Jun 06, 2019 at 09:09:08AM -0700, Lucas De Marchi wrote: > On Thu, Jun 06, 2019 at 09:00:56AM -0700, Rodrigo Vivi wrote: > > On Wed, Jun 05, 2019 at 03:15:22PM -0700, Matt Roper wrote: > > > On Wed, Jun 05, 2019 at 02:51:08PM -0700, Manasi Navare wrote: > > > > On Wed, Jun 05, 2019 at 02:18:32PM -0700, Matt Roper wrote: > > > > > Unlike ICL, EHL's combo PHYs can support HBR3 data rates. Note that > > > > > this just extends the upper limit; we will continue to honor the max > > > > > data rate specified in the VBT in cases where it is lower than HBR3. > > > > > > > > > > Signed-off-by: Matt Roper > > > > > > > > Yes looks good to me. > > > > > > > > Reviewed-by: Manasi Navare > > > > > > > > Manasi > > > > > > Thanks for the quick review. CI looks happy too, so pushed to dinq. > > > > > > > > > Matt > > > > > > > > > > > > --- > > > > > drivers/gpu/drm/i915/intel_dp.c | 1 + > > > > > 1 file changed, 1 insertion(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > > > > b/drivers/gpu/drm/i915/intel_dp.c > > > > > index 24b56b2a76c8..b099a9dc28fd 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > > > @@ -332,6 +332,7 @@ static int icl_max_source_rate(struct intel_dp > > > > > *intel_dp) > > > > > enum port port = dig_port->base.port; > > > > > > > > > > if (intel_port_is_combophy(dev_priv, port) && > > > > > + !IS_ELKHARTLAKE(dev_priv) && > > > > I wonder if we shouldn't use IS_ICELAKE instead of !IS_ELKHARTLAKE here... > > but it seems to late... > > if we apply the principle we have been adopting of always using the last > platform for the next one... I agree, this should be IS_ICELAKE(). Makes sense. I assumed this was something more tied to EHL's lack of TC ports rather than something that would necessarily be carried forward to future platforms, but as you point out I probably shouldn't make guesses about future platforms like that and should just follow our existing convention of inheriting all features. I'll send a follow-up patch to flip this to IS_ICELAKE in a little bit. Matt > > Lucas De Marchi > > > > > But something to remember to pay attention on any upcoming platform... > > > > > > > !intel_dp_is_edp(intel_dp)) > > > > > return 54; > > > > > > > > > > -- > > > > > 2.14.5 > > > > > > > > > > ___ > > > > > Intel-gfx mailing list > > > > > Intel-gfx@lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > > Matt Roper > > > Graphics Software Engineer > > > IoTG Platform Enabling & Development > > > Intel Corporation > > > (916) 356-2795 > > > ___ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] Documentation/i915: Fix kernel-doc references to moved gem files
== Series Details == Series: series starting with [1/2] Documentation/i915: Fix kernel-doc references to moved gem files URL : https://patchwork.freedesktop.org/series/61645/ State : success == Summary == CI Bug Log - changes from CI_DRM_6194_full -> Patchwork_13177_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13177_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-hsw: [PASS][1] -> [FAIL][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-hsw1/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-hsw1/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_rpm@fences-dpms: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108840]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-iclb3/igt@i915_pm_...@fences-dpms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-iclb2/igt@i915_pm_...@fences-dpms.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-apl7/igt@kms_cursor_...@pipe-b-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-apl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#104873]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-glk2/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: - shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) +17 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-hsw7/igt@kms_frontbuffer_track...@fbc-2p-primscrn-spr-indfb-onoff.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-spr-indfb-onoff.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-skl6/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-a-query-idle-hang: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-iclb8/igt@kms_vbl...@pipe-a-query-idle-hang.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-iclb7/igt@kms_vbl...@pipe-a-query-idle-hang.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/shard-skl6/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/shard-skl2/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html Possible fixes * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +4 similar issues [23]:
Re: [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_latency: Measure the latency of context switching
Quoting Mika Kuoppala (2019-06-05 16:04:09)
> Chris Wilson writes:
>
> > Measure the baseline latency between contexts in order to directly
> > compare that with the additional cost of preemption.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > tests/i915/gem_exec_latency.c | 230 ++
> > 1 file changed, 230 insertions(+)
> >
> > diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
> > index e56d62780..e88fbbc6a 100644
> > --- a/tests/i915/gem_exec_latency.c
> > +++ b/tests/i915/gem_exec_latency.c
> > @@ -410,6 +410,86 @@ static void latency_from_ring(int fd,
> > }
> > }
> >
> > +static void execution_latency(int i915, unsigned int ring, const char
> > *name)
> > +{
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = gem_create(i915, 4095),
> > + };
> > + struct drm_i915_gem_execbuffer2 execbuf = {
> > + .buffers_ptr = to_user_pointer(),
> > + .buffer_count = 1,
> > + .flags = ring | LOCAL_I915_EXEC_NO_RELOC |
> > LOCAL_I915_EXEC_HANDLE_LUT,
> > + };
> > + const unsigned int mmio_base = 0x2000;
> > + const unsigned int cs_timestamp = mmio_base + 0x358;
> > + volatile uint32_t *timestamp;
> > + uint32_t *cs, *result;
> > +
> > + timestamp =
> > + (volatile uint32_t *)((volatile char *)igt_global_mmio +
> > cs_timestamp);
> > +
> > + obj.handle = gem_create(i915, 4096);
> > + obj.flags = EXEC_OBJECT_PINNED;
> > + result = gem_mmap__wc(i915, obj.handle, 0, 4096, PROT_WRITE);
> > +
> > + for (int i = 0; i < 16; i++) {
> > + cs = result + 16 * i;
> > + *cs++ = 0x24 << 23 | 2; /* SRM */
> > + *cs++ = cs_timestamp;
> > + *cs++ = 4096 - 16 * 4 + i * 4;
> > + *cs++ = 0;
> > + *cs++ = 0xa << 23;
>
> Why not MI_BATCH_BUFFER_END? To emphasize that we have
> multiple batches inside a bo?
I wrote MI_BATCH_BUFFER_END... Oh, I see, no, I was just using the
values for no other reason than habit.
> > + }
> > +
> > + cs = result + 1024 - 16;
> > +
> > + for (int length = 2; length <= 16; length <<= 1) {
> > + struct igt_mean submit, batch, total;
> > + int last = length - 1;
> > +
> > + igt_mean_init();
> > + igt_mean_init();
> > + igt_mean_init();
> > +
> > + igt_until_timeout(2) {
> > + uint32_t now, end;
> > +
> > + cs[last] = 0;
> > +
> > + now = *timestamp;
> > + for (int i = 0; i < length; i++) {
> > + execbuf.batch_start_offset = 64 * i;
> > + gem_execbuf(i915, );
> > + }
> > + while (!((volatile uint32_t *)cs)[last])
> > + ;
> > + end = *timestamp;
> > +
> > + igt_mean_add(, (cs[0] - now) * rcs_clock);
> > + igt_mean_add(, (cs[last] - cs[0]) * rcs_clock /
> > last);
>
> Just curious of what do you use of inter batch latency?
EPARSE.
> Oh and do we need to to take the rcs_clock resolution into account
> on result calculation. Prolly not as it seems to be ticking fast enough
> for 0.1us accuracy.
It just provides the lower granularity to results. It doesn't alter the
calculations or presentation, just that quantum beneath which we cannot
measure.
Considering that the CS cannot go faster than its clock, it doesn't
affect anything.
> > + igt_mean_add(, (end - now) * rcs_clock);
> > + }
> > +
> > + igt_info("%sx%d Submission latency: %.2f±%.2fus\n",
> > + name, length,
> > + 1e-3 * igt_mean_get(),
> > + 1e-3 * sqrt(igt_mean_get_variance()));
> > +
> > + igt_info("%sx%d Inter-batch latency: %.2f±%.2fus\n",
> > + name, length,
> > + 1e-3 * igt_mean_get(),
> > + 1e-3 * sqrt(igt_mean_get_variance()));
> > +
> > + igt_info("%sx%d End-to-end latency: %.2f±%.2fus\n",
> > + name, length,
> > + 1e-3 * igt_mean_get(),
> > + 1e-3 * sqrt(igt_mean_get_variance()));
> > + }
> > +
> > + munmap(result, 4096);
> > + gem_close(i915, obj.handle);
> > +}
> > +
> > static void
> > __submit_spin(int fd, igt_spin_t *spin, unsigned int flags)
> > {
> > @@ -616,6 +696,142 @@ rthog_latency_on_ring(int fd, unsigned int engine,
> > const char *name, unsigned in
> > munmap(results, MMAP_SZ);
> > }
> >
> > +static void context_switch(int i915,
> > +unsigned int engine, const char *name,
> > +unsigned int flags)
> > +{
> > + struct drm_i915_gem_exec_object2 obj[2];
> > + struct drm_i915_gem_relocation_entry
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Support HBR3 on EHL combo PHY
On Thu, Jun 06, 2019 at 09:00:56AM -0700, Rodrigo Vivi wrote: On Wed, Jun 05, 2019 at 03:15:22PM -0700, Matt Roper wrote: On Wed, Jun 05, 2019 at 02:51:08PM -0700, Manasi Navare wrote: > On Wed, Jun 05, 2019 at 02:18:32PM -0700, Matt Roper wrote: > > Unlike ICL, EHL's combo PHYs can support HBR3 data rates. Note that > > this just extends the upper limit; we will continue to honor the max > > data rate specified in the VBT in cases where it is lower than HBR3. > > > > Signed-off-by: Matt Roper > > Yes looks good to me. > > Reviewed-by: Manasi Navare > > Manasi Thanks for the quick review. CI looks happy too, so pushed to dinq. Matt > > > --- > > drivers/gpu/drm/i915/intel_dp.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 24b56b2a76c8..b099a9dc28fd 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -332,6 +332,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp) > > enum port port = dig_port->base.port; > > > > if (intel_port_is_combophy(dev_priv, port) && > > + !IS_ELKHARTLAKE(dev_priv) && I wonder if we shouldn't use IS_ICELAKE instead of !IS_ELKHARTLAKE here... but it seems to late... if we apply the principle we have been adopting of always using the last platform for the next one... I agree, this should be IS_ICELAKE(). Lucas De Marchi But something to remember to pay attention on any upcoming platform... > > !intel_dp_is_edp(intel_dp)) > > return 54; > > > > -- > > 2.14.5 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Support HBR3 on EHL combo PHY
On Wed, Jun 05, 2019 at 03:15:22PM -0700, Matt Roper wrote: > On Wed, Jun 05, 2019 at 02:51:08PM -0700, Manasi Navare wrote: > > On Wed, Jun 05, 2019 at 02:18:32PM -0700, Matt Roper wrote: > > > Unlike ICL, EHL's combo PHYs can support HBR3 data rates. Note that > > > this just extends the upper limit; we will continue to honor the max > > > data rate specified in the VBT in cases where it is lower than HBR3. > > > > > > Signed-off-by: Matt Roper > > > > Yes looks good to me. > > > > Reviewed-by: Manasi Navare > > > > Manasi > > Thanks for the quick review. CI looks happy too, so pushed to dinq. > > > Matt > > > > > > --- > > > drivers/gpu/drm/i915/intel_dp.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > > b/drivers/gpu/drm/i915/intel_dp.c > > > index 24b56b2a76c8..b099a9dc28fd 100644 > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > @@ -332,6 +332,7 @@ static int icl_max_source_rate(struct intel_dp > > > *intel_dp) > > > enum port port = dig_port->base.port; > > > > > > if (intel_port_is_combophy(dev_priv, port) && > > > + !IS_ELKHARTLAKE(dev_priv) && I wonder if we shouldn't use IS_ICELAKE instead of !IS_ELKHARTLAKE here... but it seems to late... But something to remember to pay attention on any upcoming platform... > > > !intel_dp_is_edp(intel_dp)) > > > return 54; > > > > > > -- > > > 2.14.5 > > > > > > ___ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/7] drm/i915: Allow page pinning to be in the background
Quoting Matthew Auld (2019-06-05 15:03:03)
> On Mon, 3 Jun 2019 at 18:49, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > index 7868dd48d931..68262231f56f 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > @@ -72,21 +72,18 @@ void __i915_gem_object_set_pages(struct
> > drm_i915_gem_object *obj,
> >
> > spin_unlock(>mm.obj_lock);
> > }
> > +
> > + complete_all(>mm.completion);
> > }
>
> Worth having __i915_gem_object_set_pages_error(struct
> drm_i915_gem_object, int err) at some point?
I don't think it's required, in my current sketch, actually setting the
obj->mm.pages is central:
static void
get_pages_worker(struct work_struct *_work)
{
struct get_pages_work *work = container_of(_work, typeof(*work), work);
struct drm_i915_gem_object *obj = work->ctx.object;
struct sg_table *pages;
unsigned int sizes = 0;
if (!work->dma.error) {
pages = obj->ops->get_pages(>ctx, );
if (!IS_ERR(pages))
__set_pages(obj, pages, sizes);
else
dma_fence_set_error(>dma, PTR_ERR(pages));
} else {
pages = ERR_PTR(work->dma.error);
}
obj->mm.pages = pages;
complete_all(>mm.completion);
atomic_dec(>mm.pages_pin_count);
i915_gem_object_put(obj);
put_task_struct(work->ctx.task);
dma_fence_signal(>dma);
dma_fence_put(>dma);
}
That may all change with blitter integration :)
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V8 i-g-t] tests/kms_flip: Skip VBlank tests in modules without VBlank
On 06/06, Ser, Simon wrote:
> On Tue, 2019-06-04 at 23:30 -0300, Rodrigo Siqueira wrote:
> > The kms_flip test relies on VBlank support, and this situation may
> > exclude some virtual drivers to take advantage of this set of tests.
> > This commit adds a mechanism that checks if a module has VBlank. If the
> > target module has VBlank support, kms_flip will run all the VBlank
> > tests; otherwise, the VBlank tests will be skipped. Additionally, this
> > commit improves the test coverage by checks if the function
> > drmWaitVBlank() returns EOPNOTSUPP (i.e., no VBlank support).
> >
> > V7: Changes since V6
> > - Skip TEST_DPMS with TEST_MODESET and TEST_EBUSY if the device does
> >not support vblank
>
> Hmm, I'm not sure I understand this line. If I'm reading this correctly
> it refers to this line:
>
> if (!(o->flags & (TEST_DPMS | TEST_MODESET | TEST_NO_VBLANK)))
>
> So the check was previously skipped on TEST_DPMS and TEST_MODESET. It's
> now skipped on TEST_NO_VBLANK too. So I'm a little confused with the
> changelog line: should it say "skip seq number checking it the device
> doesn't support vblank"?
>
> Am I missing something?
>
> Apart from this, the patch itself looks good to me.
Hi Simon,
Thank you for your review.
About the changelog message, I'll update it to:
Skip seq number checking and busy flip if the device doesn't support vblank
Can I add your Reviewed-by before applying this patch?
> > V6: Set errno to zero before call drmWaitVBlank() (Chris Wilson)
> >
> > V5: Drop the DRM_VBLANK_NEXTONMISS (Chris Wilson)
> >
> > V4: Replace DRM_VBLANK_ABSOLUTE by DRM_VBLANK_RELATIVE and
> > DRM_VBLANK_NEXTONMISS
> >
> > V3: Add documentation (Daniel Vetter)
> >
> > V2: Add new branch coverage to check if VBlank is enabled or not and
> > update commit message
> >
> > V1: Chris Wilson
> > - Change function name from igt_there_is_vblank to kms_has_vblank
> > - Move vblank function check from igt_aux to igt_kms
> > - Utilizes memset in dummy_vbl variable
> > - Directly return the result of drmWaitVBlank()
> >
> > Signed-off-by: Rodrigo Siqueira
> > ---
> > lib/igt_kms.c| 21 +
> > lib/igt_kms.h| 2 ++
> > tests/kms_flip.c | 24 +++-
> > 3 files changed, 46 insertions(+), 1 deletion(-)
> >
> > diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> > index d7d711a7..8a465f67 100644
> > --- a/lib/igt_kms.c
> > +++ b/lib/igt_kms.c
> > @@ -1673,6 +1673,27 @@ void igt_assert_plane_visible(int fd, enum pipe
> > pipe, int plane_index, bool visi
> > igt_assert_eq(visible, visibility);
> > }
> >
> > +/**
> > + * kms_has_vblank:
> > + * @fd: DRM fd
> > + *
> > + * Get the VBlank errno after an attempt to call drmWaitVBlank(). This
> > + * function is useful for checking if a driver has support or not for
> > VBlank.
> > + *
> > + * Returns: true if target driver has VBlank support, otherwise return
> > false.
> > + */
> > +bool kms_has_vblank(int fd)
> > +{
> > + drmVBlank dummy_vbl;
> > +
> > + memset(_vbl, 0, sizeof(drmVBlank));
> > + dummy_vbl.request.type = DRM_VBLANK_RELATIVE;
> > +
> > + errno = 0;
> > + drmWaitVBlank(fd, _vbl);
> > + return (errno != EOPNOTSUPP);
> > +}
> > +
> > /*
> > * A small modeset API
> > */
> > diff --git a/lib/igt_kms.h b/lib/igt_kms.h
> > index 4ac28131..5b5cf274 100644
> > --- a/lib/igt_kms.h
> > +++ b/lib/igt_kms.h
> > @@ -229,6 +229,8 @@ void kmstest_wait_for_pageflip(int fd);
> > unsigned int kmstest_get_vblank(int fd, int pipe, unsigned int flags);
> > void igt_assert_plane_visible(int fd, enum pipe pipe, int plane_index,
> > bool visibility);
> >
> > +bool kms_has_vblank(int fd);
> > +
> > /*
> > * A small modeset API
> > */
> > diff --git a/tests/kms_flip.c b/tests/kms_flip.c
> > index d7c1f9cf..2a158d97 100755
> > --- a/tests/kms_flip.c
> > +++ b/tests/kms_flip.c
> > @@ -71,6 +71,7 @@
> > #define TEST_SUSPEND (1 << 26)
> > #define TEST_BO_TOOBIG (1 << 28)
> >
> > +#define TEST_NO_VBLANK (1 << 29)
> > #define TEST_BASIC (1 << 30)
> >
> > #define EVENT_FLIP (1 << 0)
> > @@ -126,6 +127,18 @@ struct event_state {
> > int seq_step;
> > };
> >
> > +static bool vblank_dependence(int flags)
> > +{
> > + int vblank_flags = TEST_VBLANK | TEST_VBLANK_BLOCK |
> > + TEST_VBLANK_ABSOLUTE | TEST_VBLANK_EXPIRED_SEQ |
> > + TEST_CHECK_TS | TEST_VBLANK_RACE | TEST_EBUSY;
> > +
> > + if (flags & vblank_flags)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > static float timeval_float(const struct timeval *tv)
> > {
> > return tv->tv_sec + tv->tv_usec / 100.0f;
> > @@ -494,7 +507,7 @@ static void check_state(const struct test_output *o,
> > const struct event_state *e
> > /* check only valid if no modeset happens in between, that increments by
> > * (1 << 23) on each step. This bounding matches the one in
> > *
Re: [Intel-gfx] [PATCH 2/7] drm/i915/sdvo: Implement proper HDMI audio support for SDVO
On Tue, Apr 09, 2019 at 11:00:10PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 09, 2019 at 05:40:49PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Our SDVO audio support is pretty bogus. We can't push audio over the
> > SDVO bus, so trying to enable audio in the SDVO control register doesn't
> > do anything. In fact it looks like the SDVO encoder will always mix in
> > the audio coming over HDA, and there's no (at least documented) way to
> > disable that from our side. So HDMI audio does work currently but only by
> > luck really. What is missing though is the ELD.
>
> Hmm. Looks like I forgot to update this text after the gen3 bug was
> reported. The situation is that audio works on gen4 by luck. On gen3
> it got broken by the referenced commit since we no longer enable
> HDMI encoding on the SDVO device (that will stop audio transmission
> entirely).
>
> >
> > To pass the ELD to the audio driver we need to write it to magic buffer
> > in the SDVO encoder hardware which then gets pulled out via HDA in the
> > other end. Ie. pretty much the same thing we had for native HDMI before
> > we started to just pass the ELD between the drivers. This sort of
> > explains why we even have that silly hardware buffer with native HDMI.
> >
> > $ cat /proc/asound/card0/eld#1.0
> > -monitor_present0
> > -eld_valid 0
> > +monitor_present1
> > +eld_valid 1
> > +monitor_name LG TV
> > +connection_typeHDMI
> > +...
> >
> > This also fixes our state readout since we can now query the SDVO
> > encoder about the state of the "ELD valid" and "presence detect"
> > bits. As mentioned those don't actually control whether audio
> > gets sent over the HDMI cable, but it's the best we can do.
> >
> > Cc: sta...@vger.kernel.org
> > Cc: Daniel Vetter
> > Cc: zar...@gmail.com
> > Tested-by: zar...@gmail.com
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108976
> > Fixes: de44e256b92c ("drm/i915/sdvo: Shut up state checker with hdmi cards
> > on gen3")
> > Signed-off-by: Ville Syrjälä
Matches the sdvo specs and bspec (SDVO_AUDIO_ENABLE is a reserved/MBZ
bit on GEN3,3.5, and on GEN4 it's probably HDMI specific, since there is
no audio traffic over the SDVO bus):
Reviewed-by: Imre Deak
Btw, is it guaranteed that we have a valid ELD when
force_audio == HDMI_AUDIO_ON ?
> > ---
> > drivers/gpu/drm/i915/intel_sdvo.c | 58 +-
> > drivers/gpu/drm/i915/intel_sdvo_regs.h | 3 ++
> > 2 files changed, 50 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
> > b/drivers/gpu/drm/i915/intel_sdvo.c
> > index 61db07244296..7f64352a3413 100644
> > --- a/drivers/gpu/drm/i915/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> > @@ -916,6 +916,13 @@ static bool intel_sdvo_set_colorimetry(struct
> > intel_sdvo *intel_sdvo,
> > return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY,
> > , 1);
> > }
> >
> > +static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
> > + u8 audio_state)
> > +{
> > + return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
> > + _state, 1);
> > +}
> > +
> > #if 0
> > static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
> > {
> > @@ -1487,11 +1494,6 @@ static void intel_sdvo_pre_enable(struct
> > intel_encoder *intel_encoder,
> > else
> > sdvox |= SDVO_PIPE_SEL(crtc->pipe);
> >
> > - if (crtc_state->has_audio) {
> > - WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
> > - sdvox |= SDVO_AUDIO_ENABLE;
> > - }
> > -
> > if (INTEL_GEN(dev_priv) >= 4) {
> > /* done in crtc_mode_set as the dpll_md reg must be written
> > early */
> > } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
> > @@ -1635,8 +1637,13 @@ static void intel_sdvo_get_config(struct
> > intel_encoder *encoder,
> > if (sdvox & HDMI_COLOR_RANGE_16_235)
> > pipe_config->limited_color_range = true;
> >
> > - if (sdvox & SDVO_AUDIO_ENABLE)
> > - pipe_config->has_audio = true;
> > + if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
> > +, 1)) {
> > + u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT;
> > +
> > + if ((val & mask) == mask)
> > + pipe_config->has_audio = true;
> > + }
> >
> > if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
> > , 1)) {
> > @@ -1647,6 +1654,32 @@ static void intel_sdvo_get_config(struct
> > intel_encoder *encoder,
> > intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
> > }
> >
> > +static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
> > +{
> > + intel_sdvo_set_audio_state(intel_sdvo, 0);
> > +}
> > +
> > +static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
> > +
Re: [Intel-gfx] [PATCH] drm/i915: Report an earlier wedged event when suspending the engines
Chris Wilson writes: > Quoting Chris Wilson (2019-05-31 12:32:45) >> On i915_gem_load_power_context() we do care whether or not we succeed in >> completing the switch back to the kernel context (via idling the >> engines). Currently, we detect if an error occurs while we wait, but we >> do not report one if it occurred beforehand (and the status of the >> switch is undefined). Check the current terminally wedged status on >> entering the wait, and report it after flushing the requests, as if it >> had occurred during our own wait. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110824 >> Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Deal with machines that expose less than three QGV points
== Series Details == Series: drm/i915: Deal with machines that expose less than three QGV points URL : https://patchwork.freedesktop.org/series/61713/ State : success == Summary == CI Bug Log - changes from CI_DRM_6206 -> Patchwork_13193 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/ Known issues Here are the changes found in Patchwork_13193 that come from known issues: ### IGT changes ### Issues hit * igt@gem_flink_basic@flink-lifetime: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html * igt@i915_selftest@live_hangcheck: - fi-icl-u2: [PASS][3] -> [DMESG-FAIL][4] ([fdo#110429]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u2/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-icl-u2/igt@i915_selftest@live_hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@vgem_basic@unload: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@vgem_ba...@unload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-icl-u3/igt@vgem_ba...@unload.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#110429]: https://bugs.freedesktop.org/show_bug.cgi?id=110429 Participating hosts (55 -> 46) -- Missing(9): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6206 -> Patchwork_13193 CI_DRM_6206: 14ef563cbee376503d3551992d71f2f075e7462c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13193: 4db3e33d99e94d919fa1a7a2dc06efa6cbdaa1d7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4db3e33d99e9 drm/i915: Deal with machines that expose less than three QGV points == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/4] drm/i915: move pm related declarations to intel_pm.h
== Series Details ==
Series: series starting with [v2,1/4] drm/i915: move pm related declarations to
intel_pm.h
URL : https://patchwork.freedesktop.org/series/61712/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6206 -> Patchwork_13192
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13192/
Known issues
Here are the changes found in Patchwork_13192 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13192/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13192/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][5] ([fdo#103167]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13192/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@vgem_basic@unload:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@vgem_ba...@unload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13192/fi-icl-u3/igt@vgem_ba...@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
Participating hosts (55 -> 47)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6206 -> Patchwork_13192
CI_DRM_6206: 14ef563cbee376503d3551992d71f2f075e7462c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13192: 9c892d83fb61667982cd00eab279cc6aec3426b4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9c892d83fb61 drm/i915/frontbuffer: remove obsolete comment about mark busy/idle
c0e8d69cd97e drm/i915: move more atomic plane declarations to
intel_atomic_plane.h
02f7fd1c9f5c drm/i915: remove some unused declarations from intel_drv.h
27c96b0a5a73 drm/i915: move pm related declarations to intel_pm.h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13192/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/21] drm/i915: Consolidate some open coded mmio rmw
On Thu, Jun 06, 2019 at 10:36:35AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Replace some gen6/7 open coded rmw with intel_uncore_rmw.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +
> 1 file changed, 18 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index b2c2dc99bf8a..fe9cd4ea9671 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1697,13 +1697,10 @@ static void gen7_ppgtt_enable(struct intel_uncore
> *uncore)
> {
> struct drm_i915_private *i915 = uncore_to_i915(uncore);
> struct intel_engine_cs *engine;
> - u32 ecochk, ecobits;
> enum intel_engine_id id;
> + u32 ecochk;
>
> - ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
> - intel_uncore_write(uncore,
> -GAC_ECO_BITS,
> -ecobits | ECOBITS_PPGTT_CACHE64B);
> + intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
>
> ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
> if (IS_HASWELL(i915)) {
> @@ -1724,22 +1721,20 @@ static void gen7_ppgtt_enable(struct intel_uncore
> *uncore)
>
> static void gen6_ppgtt_enable(struct intel_uncore *uncore)
> {
> - u32 ecochk, gab_ctl, ecobits;
> + intel_uncore_rmw(uncore,
> + GAC_ECO_BITS,
> + 0,
> + ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
>
> - ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
> - intel_uncore_write(uncore,
> -GAC_ECO_BITS,
> -ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
> + intel_uncore_rmw(uncore,
> + GAB_CTL,
> + 0,
> + GAB_CTL_CONT_AFTER_PAGEFAULT);
>
> - gab_ctl = intel_uncore_read(uncore, GAB_CTL);
> - intel_uncore_write(uncore,
> -GAB_CTL,
> -gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
> -
> - ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
> - intel_uncore_write(uncore,
> -GAM_ECOCHK,
> -ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
> + intel_uncore_rmw(uncore,
> + GAM_ECOCHK,
> + 0,
> + ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>
> if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
> intel_uncore_write(uncore,
> @@ -2234,11 +2229,10 @@ static void gtt_write_workarounds(struct intel_uncore
> *uncore)
>*/
> if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
> INTEL_GEN(i915) <= 10)
> - intel_uncore_write(uncore,
> -GEN8_GAMW_ECO_DEV_RW_IA,
> -intel_uncore_read(uncore,
> - GEN8_GAMW_ECO_DEV_RW_IA) |
> -GAMW_ECO_ENABLE_64K_IPS_FIELD);
> + intel_uncore_rmw(uncore,
> + GEN8_GAMW_ECO_DEV_RW_IA,
> + 0,
> + GAMW_ECO_ENABLE_64K_IPS_FIELD);
> }
>
> int i915_ppgtt_init_hw(struct intel_uncore *uncore)
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move object close under its own lock
== Series Details ==
Series: drm/i915: Move object close under its own lock
URL : https://patchwork.freedesktop.org/series/61710/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6206 -> Patchwork_13191
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13191/
Known issues
Here are the changes found in Patchwork_13191 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +3
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13191/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
Possible fixes
* igt@vgem_basic@unload:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@vgem_ba...@unload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13191/fi-icl-u3/igt@vgem_ba...@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246
Participating hosts (55 -> 46)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6206 -> Patchwork_13191
CI_DRM_6206: 14ef563cbee376503d3551992d71f2f075e7462c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13191: e5fac7d890760b143667f9b887d751757ae1af29 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e5fac7d89076 drm/i915: Move object close under its own lock
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13191/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt
On Thu, Jun 06, 2019 at 10:36:38AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> These functions operate on ggtt so make them take that directly as
> parameter.
This patch makes me wonder where we really want and need to go.
We need to move out of dev_priv and global i915...
but do we need to go and reduce to all minimal stuff used like
uncore and ggtt or could we find a middle solution where
each group has its own "class"?
like this guc stuff would keep the intel_guc, but the i915_gem
stuff or intel_gt stuff would have their own structs where
we have everything needed for that group?
>
> At the same time move the USES_GUC conditional down to
> intel_guc_reserve_ggtt_top for symmetry with
> intel_guc_reserved_gtt_size.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++
> drivers/gpu/drm/i915/intel_guc.c| 18 --
> drivers/gpu/drm/i915/intel_guc.h| 6 +++---
> 3 files changed, 17 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d3b3676d10f3..d967a4e9ceb0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
> *dev_priv)
>* why.
>*/
> ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> -intel_guc_reserved_gtt_size(_priv->guc));
> +intel_guc_reserved_gtt_size(ggtt));
>
> ret = intel_vgt_balloon(ggtt);
> if (ret)
> @@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private
> *dev_priv)
> if (ret)
> return ret;
>
> - if (USES_GUC(dev_priv)) {
> - ret = intel_guc_reserve_ggtt_top(_priv->guc);
> - if (ret)
> - goto err_reserve;
> - }
> + ret = intel_guc_reserve_ggtt_top(ggtt);
> + if (ret)
> + goto err_reserve;
>
> /* Clear any non-preallocated blocks */
> drm_mm_for_each_hole(entry, >vm.mm, hole_start, hole_end) {
> @@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
> *dev_priv)
> return 0;
>
> err_appgtt:
> - intel_guc_release_ggtt_top(_priv->guc);
> + intel_guc_release_ggtt_top(ggtt);
> err_reserve:
> drm_mm_remove_node(>error_capture);
> return ret;
> @@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
> *dev_priv)
> if (drm_mm_node_allocated(>error_capture))
> drm_mm_remove_node(>error_capture);
>
> - intel_guc_release_ggtt_top(_priv->guc);
> + intel_guc_release_ggtt_top(ggtt);
>
> if (drm_mm_initialized(>vm.mm)) {
> intel_vgt_deballoon(ggtt);
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index b88c349c4fa6..633248b7da25 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc
> *guc, u32 size)
>
> /**
> * intel_guc_reserved_gtt_size()
> - * @guc: intel_guc structure
> + * @ggtt:Pointer to struct i915_ggtt
> *
> * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are
> using
> * GuC we can't have any objects pinned in that region. This function returns
> @@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct
> intel_guc *guc, u32 size)
> * 0 if GuC is not present or not in use.
> * Otherwise, the GuC WOPCM size.
> */
> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
> {
> - return guc_to_i915(guc)->wopcm.guc.size;
> + return ggtt->vm.i915->wopcm.guc.size;
> }
>
> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
> {
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> - struct i915_ggtt *ggtt = >ggtt;
> u64 size;
> int ret;
>
> + if (!USES_GUC(ggtt->vm.i915))
> + return 0;
> +
> size = ggtt->vm.total - GUC_GGTT_TOP;
>
> ret = i915_gem_gtt_reserve(>vm, >uc_fw, size,
> @@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
> return ret;
> }
>
> -void intel_guc_release_ggtt_top(struct intel_guc *guc)
> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
> {
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> - struct i915_ggtt *ggtt = >ggtt;
> -
> if (drm_mm_node_allocated(>uc_fw))
> drm_mm_remove_node(>uc_fw);
> }
> diff --git a/drivers/gpu/drm/i915/intel_guc.h
> b/drivers/gpu/drm/i915/intel_guc.h
> index cbfed7a77c8b..55ea14176c5e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32
> rsa_offset);
> int
Re: [Intel-gfx] [PATCH 21/21] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
On Thu, Jun 06, 2019 at 10:36:39AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> These two are only used from within i915_gem_gtt.c and can trivially be
> made static.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 8
> drivers/gpu/drm/i915/i915_gem_gtt.h | 3 ---
> 2 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d967a4e9ceb0..bd7a078f4b49 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2834,7 +2834,7 @@ static void i915_gtt_color_adjust(const struct
> drm_mm_node *node,
> *end -= I915_GTT_PAGE_SIZE;
> }
>
> -int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
> +static int init_aliasing_ppgtt(struct drm_i915_private *i915)
> {
> struct i915_ggtt *ggtt = >ggtt;
> struct i915_hw_ppgtt *ppgtt;
> @@ -2874,7 +2874,7 @@ int i915_gem_init_aliasing_ppgtt(struct
> drm_i915_private *i915)
> return err;
> }
>
> -void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
> +static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
> {
> struct i915_ggtt *ggtt = >ggtt;
> struct i915_hw_ppgtt *ppgtt;
> @@ -2942,7 +2942,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
> *dev_priv)
> ggtt->vm.clear_range(>vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
>
> if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> - ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> + ret = init_aliasing_ppgtt(dev_priv);
> if (ret)
> goto err_appgtt;
> }
> @@ -2969,7 +2969,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
> *dev_priv)
> ggtt->vm.closed = true;
>
> mutex_lock(_priv->drm.struct_mutex);
> - i915_gem_fini_aliasing_ppgtt(dev_priv);
> + fini_aliasing_ppgtt(dev_priv);
>
> list_for_each_entry_safe(vma, vn, >vm.bound_list, vm_link)
> WARN_ON(i915_vma_unbind(vma));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 80703162c99a..6893ae015dce 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -617,9 +617,6 @@ const struct intel_ppat_entry *
> intel_ppat_get(struct drm_i915_private *i915, u8 value);
> void intel_ppat_put(const struct intel_ppat_entry *entry);
>
> -int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
> -void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
> -
> int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
> int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
> int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt
On Thu, 06 Jun 2019 14:23:09 +0200, Tvrtko Ursulin
wrote:
On 06/06/2019 12:58, Michal Wajdeczko wrote:
On Thu, 06 Jun 2019 11:36:38 +0200, Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
These functions operate on ggtt so make them take that directly as
parameter.
Not quite.
Function intel_guc_reserved_gtt_size() operates on struct intel_guc
and is defined in intel_guc.c for proper layering, so NAK here.
But it doesn't really. It operates on intel_wopcm if we want to be true.
oops, I forgot that finally we placed wopcm directly under i915 (initially
it was declared inside intel_guc)
u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
{
return ggtt->vm.i915->wopcm.guc.size;
}
And GuC portion it needs is just one part of struct intel_wopcm - so
whether or not this function must live in intel_guc.c and so how hard we
should see this as layering violation is not so clear in my opinion.
agreed. so we have two options:
move this function to intel_wopcm.h as:
static inline u32 intel_wopcm_guc_size(struct intel_wopcm *wopcm)
{
GEM_BUG_ON(!wopcm->guc.size);
return wopcm->guc.size;
}
and update existing callers or update just old one to:
u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
{
return intel_wopcm_guc_size(_to_i915(guc)->wopcm);
}
Unless it will need to actually use intel_guc in the future.
There was a plan to create struct intel_uc with wopcm, guc and huc.
Not sure if it is still applicable.
For other two intel_guc_reserve|release_ggtt_top() I would rather:
- rename them to i915_ggtt_reserve|release_guc_top(),
- move to i915_gem_ggtt.c
- make them static
Fair, will do.
Regards,
Tvrtko
Michal
At the same time move the USES_GUC conditional down to
intel_guc_reserve_ggtt_top for symmetry with
intel_guc_reserved_gtt_size.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++
drivers/gpu/drm/i915/intel_guc.c| 18 --
drivers/gpu/drm/i915/intel_guc.h| 6 +++---
3 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d3b3676d10f3..d967a4e9ceb0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
* why.
*/
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
- intel_guc_reserved_gtt_size(_priv->guc));
+ intel_guc_reserved_gtt_size(ggtt));
ret = intel_vgt_balloon(ggtt);
if (ret)
@@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
if (ret)
return ret;
-if (USES_GUC(dev_priv)) {
-ret = intel_guc_reserve_ggtt_top(_priv->guc);
-if (ret)
-goto err_reserve;
-}
+ret = intel_guc_reserve_ggtt_top(ggtt);
+if (ret)
+goto err_reserve;
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, >vm.mm, hole_start, hole_end) {
@@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
return 0;
err_appgtt:
-intel_guc_release_ggtt_top(_priv->guc);
+intel_guc_release_ggtt_top(ggtt);
err_reserve:
drm_mm_remove_node(>error_capture);
return ret;
@@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct
drm_i915_private *dev_priv)
if (drm_mm_node_allocated(>error_capture))
drm_mm_remove_node(>error_capture);
-intel_guc_release_ggtt_top(_priv->guc);
+intel_guc_release_ggtt_top(ggtt);
if (drm_mm_initialized(>vm.mm)) {
intel_vgt_deballoon(ggtt);
diff --git a/drivers/gpu/drm/i915/intel_guc.c
b/drivers/gpu/drm/i915/intel_guc.c
index b88c349c4fa6..633248b7da25 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct
intel_guc *guc, u32 size)
/**
* intel_guc_reserved_gtt_size()
- * @guc:intel_guc structure
+ * @ggtt:Pointer to struct i915_ggtt
*
* The GuC WOPCM mapping shadows the lower part of the GGTT, so if we
are using
* GuC we can't have any objects pinned in that region. This function
returns
@@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct
intel_guc *guc, u32 size)
* 0 if GuC is not present or not in use.
* Otherwise, the GuC WOPCM size.
*/
-u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
+u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
{
-return guc_to_i915(guc)->wopcm.guc.size;
+return ggtt->vm.i915->wopcm.guc.size;
}
-int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
+int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
{
-struct drm_i915_private *i915 = guc_to_i915(guc);
-struct i915_ggtt *ggtt = >ggtt;
u64 size;
int ret;
+if (!USES_GUC(ggtt->vm.i915))
+return 0;
+
size = ggtt->vm.total - GUC_GGTT_TOP;
Re: [Intel-gfx] [PATCH i-g-t] gitlab-ci: add build for MIPS
On Wed, Jun 05, 2019 at 09:18:09PM +0100, Guillaume Tucker wrote: > Add Docker image and Gitlab CI steps to run builds for the MIPS > architecture using Debian Buster. > > Signed-off-by: Guillaume Tucker > --- > .gitlab-ci.yml | 28 > Dockerfile.debian-mips | 38 ++ > meson-cross-mips.txt | 12 > 3 files changed, 78 insertions(+) > create mode 100644 Dockerfile.debian-mips > create mode 100644 meson-cross-mips.txt > > diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml > index 771143a9ea95..e390f8f472d5 100644 > --- a/.gitlab-ci.yml > +++ b/.gitlab-ci.yml > @@ -90,6 +90,17 @@ build:tests-debian-meson-arm64: > paths: >- build > > +build:tests-debian-meson-mips: > + image: $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-mips:latest > + stage: build > + script: > +- export PKG_CONFIG_PATH=/usr/lib/mips-linux-gnu/pkgconfig/ > +- meson --cross-file meson-cross-mips.txt build > +- ninja -C build > + artifacts: > +paths: > + - build > + > build:tests-debian-autotools: >image: $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian:latest >stage: build > @@ -221,6 +232,23 @@ containers:igt-debian-arm64: > - docker build -t $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-arm64 -f > Dockerfile.debian-arm64 . > - docker push $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-arm64 > > +containers:igt-debian-mips: > + stage: containers > + image: docker:stable > + only: > +changes: > + - Dockerfile.debian-mips > + - .gitlab-ci.yml > + services: > +- docker:dind > + variables: > +DOCKER_HOST: tcp://docker:2375 > +DOCKER_DRIVER: overlay2 > + script: > +- docker login -u gitlab-ci-token -p $CI_JOB_TOKEN $CI_REGISTRY > +- docker build -t $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-mips -f > Dockerfile.debian-mips . > +- docker push $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-mips > + > containers:igt-fedora: >stage: containers >image: docker:stable > diff --git a/Dockerfile.debian-mips b/Dockerfile.debian-mips > new file mode 100644 > index ..2612b7b148e3 > --- /dev/null > +++ b/Dockerfile.debian-mips > @@ -0,0 +1,38 @@ > +FROM debian:buster Any particular reason you went here for buster instead of stretch-backports like with other images? I am not very fluent in Debian. Other than that looks good to land after the atomic compatibility fixes. > + > +RUN apt-get update > +RUN apt-get install -y \ > + flex \ > + bison \ > + pkg-config \ > + x11proto-dri2-dev \ > + python-docutils \ > + valgrind \ > + peg > + > +RUN dpkg --add-architecture mips > +RUN apt-get update > +RUN apt-get install -y \ > + gcc-mips-linux-gnu \ > + libpciaccess-dev:mips \ > + libkmod-dev:mips \ > + libprocps-dev:mips \ > + libunwind-dev:mips \ > + libdw-dev:mips \ > + zlib1g-dev:mips \ > + liblzma-dev:mips \ > + libcairo-dev:mips \ > + libpixman-1-dev:mips \ > + libudev-dev:mips \ > + libgsl-dev:mips \ > + libasound2-dev:mips \ > + libjson-c-dev:mips \ > + libcurl4-openssl-dev:mips \ > + libxrandr-dev:mips \ > + libxv-dev:mips > + > +RUN apt-get install -y \ > + meson \ > + libdrm-dev:mips \ > + qemu-user \ > + qemu-user-static > diff --git a/meson-cross-mips.txt b/meson-cross-mips.txt > new file mode 100644 > index ..6350d677e0bc > --- /dev/null > +++ b/meson-cross-mips.txt > @@ -0,0 +1,12 @@ > +[binaries] > +c = '/usr/bin/mips-linux-gnu-gcc' > +ar = '/usr/bin/mips-linux-gnu-gcc-ar' > +strip = '/usr/bin/mips-linux-gnu-strip' > +pkgconfig = 'pkg-config' > +exe_wrapper = 'qemu-mips' > + > +[host_machine] > +system = 'linux' > +cpu_family = 'mips' > +cpu = 'mips' > +endian = 'big' > -- > 2.20.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dmc: protect against reading random memory
On Wed, Jun 05, 2019 at 04:55:35PM -0700, Lucas De Marchi wrote:
> While loading the DMC firmware we were double checking the headers made
> sense, but in no place we checked that we were actually reading memory
> we were supposed to. This could be wrong in case the firmware file is
> truncated or malformed.
>
> Before this patch:
> # ls -l /lib/firmware/i915/icl_dmc_ver1_07.bin
> -rw-r--r-- 1 root root 25716 Feb 1 12:26 icl_dmc_ver1_07.bin
> # truncate -s 25700 /lib/firmware/i915/icl_dmc_ver1_07.bin
> # modprobe i915
> # dmesg| grep -i dmc
> [drm:intel_csr_ucode_init [i915]] Loading i915/icl_dmc_ver1_07.bin
> [drm] Finished loading DMC firmware i915/icl_dmc_ver1_07.bin (v1.7)
>
> i.e. it loads random data. Now it fails like below:
> [drm:intel_csr_ucode_init [i915]] Loading i915/icl_dmc_ver1_07.bin
> [drm:csr_load_work_fn [i915]] *ERROR* Truncated DMC firmware, rejecting.
> i915 :00:02.0: Failed to load DMC firmware
> i915/icl_dmc_ver1_07.bin. Disabling runtime power management.
> i915 :00:02.0: DMC firmware homepage:
> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915
>
> Before reading any part of the firmware file, validate the input first.
>
> Fixes: eb805623d8b1 ("drm/i915/skl: Add support to load SKL CSR firmware.")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
>
> This has been extracted from the bigger series
> https://patchwork.freedesktop.org/series/61016/ in a way that can be
> propagated to stable.
Thanks!
>
> drivers/gpu/drm/i915/intel_csr.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index 4527b9662330..bf0eebd385b9 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -303,10 +303,17 @@ static u32 *parse_csr_fw(struct drm_i915_private
> *dev_priv,
> u32 dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
> u32 i;
> u32 *dmc_payload;
> + size_t fsize;
>
> if (!fw)
> return NULL;
>
> + fsize = sizeof(struct intel_css_header) +
> + sizeof(struct intel_package_header) +
> + sizeof(struct intel_dmc_header);
> + if (fsize > fw->size)
> + goto error_truncated;
> +
> /* Extract CSS Header information*/
> css_header = (struct intel_css_header *)fw->data;
> if (sizeof(struct intel_css_header) !=
> @@ -366,6 +373,9 @@ static u32 *parse_csr_fw(struct drm_i915_private
> *dev_priv,
> /* Convert dmc_offset into number of bytes. By default it is in dwords*/
> dmc_offset *= 4;
> readcount += dmc_offset;
> + fsize += dmc_offset;
> + if (fsize > fw->size)
> + goto error_truncated;
>
> /* Extract dmc_header information. */
> dmc_header = (struct intel_dmc_header *)>data[readcount];
> @@ -397,6 +407,10 @@ static u32 *parse_csr_fw(struct drm_i915_private
> *dev_priv,
>
> /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
> nbytes = dmc_header->fw_size * 4;
> + fsize += nbytes;
> + if (fsize > fw->size)
> + goto error_truncated;
> +
> if (nbytes > csr->max_fw_size) {
> DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
> return NULL;
> @@ -410,6 +424,10 @@ static u32 *parse_csr_fw(struct drm_i915_private
> *dev_priv,
> }
>
> return memcpy(dmc_payload, >data[readcount], nbytes);
> +
> +error_truncated:
> + DRM_ERROR("Truncated DMC firmware, rejecting.\n");
> + return NULL;
> }
>
> static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
> --
> 2.21.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Kill INTEL_SUBPLATFORM_AML
On Wed, Jun 05, 2019 at 06:05:23PM -0700, Souza, Jose wrote:
> This is the same as WHL, we added the AML separated just in case it
> needed some different workaround or code path but looks like it don't
> need at all.
>
> Any objection with this change Rodrigo?
Nope.
Reviewed-by: Rodrigo Vivi
>
> On Wed, 2019-06-05 at 19:29 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > All AML parts are either KBL ULX or CFL ULX so there is no point
> > in keeping INTEL_SUBPLATFORM_AML around. As these are the only
> > CFL ULX parts (normal CFL didn't have Y SKUs) so we'll just
> > replace IS_AML_ULX with IS_CFL_ULX (it was already paired with
> > IS_KBL_ULX which accounts for the other half of the AML parts).
> >
> > Cc: Tvrtko Ursulin
> > Cc: José Roberto de Souza
> > Cc: Rodrigo Vivi
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 5 ++---
> > drivers/gpu/drm/i915/intel_ddi.c | 8 +---
> > drivers/gpu/drm/i915/intel_device_info.c | 6 --
> > drivers/gpu/drm/i915/intel_device_info.h | 1 -
> > 4 files changed, 7 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 89bf1e34feaa..16ea0e6077cf 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2213,9 +2213,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> > #define IS_KBL_ULX(dev_priv) \
> > IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> > -#define IS_AML_ULX(dev_priv) \
> > - (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE,
> > INTEL_SUBPLATFORM_AML) || \
> > -IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE,
> > INTEL_SUBPLATFORM_AML))
> > #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
> > INTEL_INFO(dev_priv)->gt == 2)
> > #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
> > @@ -2228,6 +2225,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > INTEL_INFO(dev_priv)->gt == 3)
> > #define IS_CFL_ULT(dev_priv) \
> > IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE,
> > INTEL_SUBPLATFORM_ULT)
> > +#define IS_CFL_ULX(dev_priv) \
> > + IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE,
> > INTEL_SUBPLATFORM_ULX)
> > #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> > INTEL_INFO(dev_priv)->gt == 2)
> > #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 350eaf54f01f..65c02b260c98 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -615,7 +615,7 @@ skl_get_buf_trans_dp(struct drm_i915_private
> > *dev_priv, int *n_entries)
> > static const struct ddi_buf_trans *
> > kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int
> > *n_entries)
> > {
> > - if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
> > + if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
> > *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
> > return kbl_y_ddi_translations_dp;
> > } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
> > @@ -631,7 +631,8 @@ static const struct ddi_buf_trans *
> > skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int
> > *n_entries)
> > {
> > if (dev_priv->vbt.edp.low_vswing) {
> > - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> > IS_AML_ULX(dev_priv)) {
> > + if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> > + IS_CFL_ULX(dev_priv)) {
> > *n_entries =
> > ARRAY_SIZE(skl_y_ddi_translations_edp);
> > return skl_y_ddi_translations_edp;
> > } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)
> > ||
> > @@ -653,7 +654,8 @@ skl_get_buf_trans_edp(struct drm_i915_private
> > *dev_priv, int *n_entries)
> > static const struct ddi_buf_trans *
> > skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int
> > *n_entries)
> > {
> > - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> > IS_AML_ULX(dev_priv)) {
> > + if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> > + IS_CFL_ULX(dev_priv)) {
> > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
> > return skl_y_ddi_translations_hdmi;
> > } else {
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 19437e8ec6fa..7135d8dc32a7 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -787,9 +787,6 @@ static const u16 subplatform_ulx_ids[] = {
> > INTEL_SKL_ULX_GT2_IDS(0),
> > INTEL_KBL_ULX_GT1_IDS(0),
> > INTEL_KBL_ULX_GT2_IDS(0),
> > -};
> > -
> > -static const u16 subplatform_aml_ids[] = {
> >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Deal with machines that expose less than three QGV points
== Series Details == Series: drm/i915: Deal with machines that expose less than three QGV points URL : https://patchwork.freedesktop.org/series/61713/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Deal with machines that expose less than three QGV points -O:drivers/gpu/drm/i915/intel_bw.c:195:44: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_bw.c:195:44: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_bw.c:197:44: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_bw.c:197:44: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Deal with machines that expose less than three QGV points
From: Ville Syrjälä
When SAGV is forced to disabled/min/med/max in the BIOS pcode will
only hand us a single QGV point instead of the normal three. Fix
the code to deal with that instead declaring the bandwidth limit
to be 0 MB/s (and thus preventing any planes from being enabled).
Also shrink the max_bw sturct a bit while at it, and change the
deratedbw type to unsigned since the code returns the bw as
an unsigned int.
Since we now keep track of how many qgv points we got from pcode
we can drop the earlier check added for the "pcode doesn't
support the memory subsystem query" case.
Cc: felix.j.degr...@intel.com
Cc: Mark Janes
Cc: Matt Roper
Cc: Clint Taylor
Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on
ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/intel_bw.c | 15 ++-
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89bf1e34feaa..f4c7afebfa27 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1738,8 +1738,9 @@ struct drm_i915_private {
} dram_info;
struct intel_bw_info {
- int num_planes;
- int deratedbw[3];
+ unsigned int deratedbw[3]; /* for each QGV point */
+ u8 num_qgv_points;
+ u8 num_planes;
} max_bw[6];
struct drm_private_obj bw_obj;
diff --git a/drivers/gpu/drm/i915/intel_bw.c b/drivers/gpu/drm/i915/intel_bw.c
index 753ac3165061..7b908e10d32e 100644
--- a/drivers/gpu/drm/i915/intel_bw.c
+++ b/drivers/gpu/drm/i915/intel_bw.c
@@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv)
clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
+ bi->num_qgv_points = qi.num_points;
+
for (j = 0; j < qi.num_points; j++) {
const struct intel_qgv_point *sp = [j];
int ct, bw;
@@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv)
bi->deratedbw[j] = min(maxdebw,
bw * 9 / 10); /* 90% */
- DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d
deratedbw=%d\n",
+ DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d
deratedbw=%u\n",
i, j, bi->num_planes, bi->deratedbw[j]);
}
@@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private
*dev_priv,
{
int i;
- /* Did we initialize the bw limits successfully? */
- if (dev_priv->max_bw[0].num_planes == 0)
- return UINT_MAX;
-
for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
const struct intel_bw_info *bi =
_priv->max_bw[i];
+ /*
+* Pcode will not expose all QGV points when
+* SAGV is forced to off/min/med/max.
+*/
+ if (qgv_point >= bi->num_qgv_points)
+ return UINT_MAX;
+
if (num_planes >= bi->num_planes)
return bi->deratedbw[qgv_point];
}
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Implicit dev_priv removal
== Series Details ==
Series: Implicit dev_priv removal
URL : https://patchwork.freedesktop.org/series/61705/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6205 -> Patchwork_13190
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/
Known issues
Here are the changes found in Patchwork_13190 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-no-prefault:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-u3/igt@gem_mmap_...@basic-read-no-prefault.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-u3/igt@gem_mmap_...@basic-read-no-prefault.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([fdo#107709])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-bsw-kefka/igt@i915_selftest@live_evict.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-bsw-kefka/igt@i915_selftest@live_evict.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-icl-dsi: [PASS][7] -> [DMESG-WARN][8] ([fdo#106107])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [DMESG-WARN][13] ([fdo#106387]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (53 -> 47)
--
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6205 -> Patchwork_13190
CI_DRM_6205: 6021addc939f244fd19e8142aa5ce838e5fa2901 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13190: d4566f34339dba02be6572acdf7ef4943cd86d30 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d4566f34339d drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
1cda79f98e38 drm/i915: Make GuC GGTT reservation work on ggtt
e465b03ce165 drm/i915: Convert intel_vgt_(de)balloon to uncore
6e633291b272 drm/i915: Convert i915_gem_init_hw to uncore
fd20c02086dd drm/i915: Consolidate some open coded mmio rmw
f0e98038c584 drm/i915: Convert i915_ppgtt_init_hw to uncore
b320ea58c2e1 drm/i915: Convert intel_mocs_init_l3cc_table to uncore
83da7c8ed5bc drm/i915: Convert gt workarounds to uncore
9d1ee9205692 drm/i915: Convert init_unused_rings to uncore
f6f9bb0e5889 drm/i915: Convert i915_gem_init_swizzling to
Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/frontbuffer: remove obsolete comment about mark busy/idle
Quoting Jani Nikula (2019-06-06 13:22:03) > This no longer exists. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_frontbuffer.c | 6 -- > 1 file changed, 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c > b/drivers/gpu/drm/i915/intel_frontbuffer.c > index aa34e33b6087..d6036b9ad16a 100644 > --- a/drivers/gpu/drm/i915/intel_frontbuffer.c > +++ b/drivers/gpu/drm/i915/intel_frontbuffer.c > @@ -53,14 +53,8 @@ > * busyness. There is no direct way to detect idleness. Instead an idle timer > * work delayed work should be started from the flush and flip functions and > * cancelled as soon as busyness is detected. > - * > - * Note that there's also an older frontbuffer activity tracking scheme which > - * just tracks general activity. This is done by the various mark_busy and > - * mark_idle functions. For display power management features using these > - * functions is deprecated and should be avoided. > */ Finally \o/ That has annoyed me for a long time, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915: move more atomic plane declarations to intel_atomic_plane.h
Quoting Jani Nikula (2019-06-06 13:22:02) > Some function declarations in intel_drv.h were missed when > intel_atomic_plane.h was created. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_atomic_plane.h | 16 > drivers/gpu/drm/i915/intel_drv.h | 12 > 2 files changed, 16 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.h > b/drivers/gpu/drm/i915/intel_atomic_plane.h > index 0a9651376d0e..24320041498d 100644 > --- a/drivers/gpu/drm/i915/intel_atomic_plane.h > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.h > @@ -6,7 +6,11 @@ > #ifndef __INTEL_ATOMIC_PLANE_H__ > #define __INTEL_ATOMIC_PLANE_H__ > > +#include > + > +struct drm_crtc_state; > struct drm_plane; > +struct drm_property; > struct intel_atomic_state; > struct intel_crtc; > struct intel_crtc_state; > @@ -38,5 +42,17 @@ int intel_plane_atomic_check_with_state(const struct > intel_crtc_state *old_crtc_ > struct intel_crtc_state *crtc_state, > const struct intel_plane_state > *old_plane_state, > struct intel_plane_state > *intel_state); > +int intel_plane_atomic_get_property(struct drm_plane *plane, > + const struct drm_plane_state *state, > + struct drm_property *property, > + u64 *val); > +int intel_plane_atomic_set_property(struct drm_plane *plane, > + struct drm_plane_state *state, > + struct drm_property *property, > + u64 val); > +int intel_plane_atomic_calc_changes(const struct intel_crtc_state > *old_crtc_state, > + struct drm_crtc_state *crtc_state, > + const struct intel_plane_state > *old_plane_state, > + struct drm_plane_state *plane_state); intel_plane_atomic vs intel_atomic_plane.h that must be hitting the ocd sweetspot. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: remove some unused declarations from intel_drv.h
Quoting Jani Nikula (2019-06-06 13:22:01) > intel_mark_busy(), intel_mark_idle(), and skl_cdclk_get_vco() no longer > exist. > > Signed-off-by: Jani Nikula Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: move pm related declarations to intel_pm.h
Quoting Jani Nikula (2019-06-06 13:22:00) > Move more missed declarations from i915_drv.h to intel_pm.h. > > Signed-off-by: Jani Nikula Must send the intel_gt_pm conversions... Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt
On 06/06/2019 12:58, Michal Wajdeczko wrote:
On Thu, 06 Jun 2019 11:36:38 +0200, Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
These functions operate on ggtt so make them take that directly as
parameter.
Not quite.
Function intel_guc_reserved_gtt_size() operates on struct intel_guc
and is defined in intel_guc.c for proper layering, so NAK here.
But it doesn't really. It operates on intel_wopcm if we want to be true.
u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
{
return ggtt->vm.i915->wopcm.guc.size;
}
And GuC portion it needs is just one part of struct intel_wopcm - so
whether or not this function must live in intel_guc.c and so how hard we
should see this as layering violation is not so clear in my opinion.
Unless it will need to actually use intel_guc in the future.
For other two intel_guc_reserve|release_ggtt_top() I would rather:
- rename them to i915_ggtt_reserve|release_guc_top(),
- move to i915_gem_ggtt.c
- make them static
Fair, will do.
Regards,
Tvrtko
Michal
At the same time move the USES_GUC conditional down to
intel_guc_reserve_ggtt_top for symmetry with
intel_guc_reserved_gtt_size.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++
drivers/gpu/drm/i915/intel_guc.c | 18 --
drivers/gpu/drm/i915/intel_guc.h | 6 +++---
3 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d3b3676d10f3..d967a4e9ceb0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
* why.
*/
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
- intel_guc_reserved_gtt_size(_priv->guc));
+ intel_guc_reserved_gtt_size(ggtt));
ret = intel_vgt_balloon(ggtt);
if (ret)
@@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
if (ret)
return ret;
- if (USES_GUC(dev_priv)) {
- ret = intel_guc_reserve_ggtt_top(_priv->guc);
- if (ret)
- goto err_reserve;
- }
+ ret = intel_guc_reserve_ggtt_top(ggtt);
+ if (ret)
+ goto err_reserve;
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, >vm.mm, hole_start, hole_end) {
@@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
return 0;
err_appgtt:
- intel_guc_release_ggtt_top(_priv->guc);
+ intel_guc_release_ggtt_top(ggtt);
err_reserve:
drm_mm_remove_node(>error_capture);
return ret;
@@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct
drm_i915_private *dev_priv)
if (drm_mm_node_allocated(>error_capture))
drm_mm_remove_node(>error_capture);
- intel_guc_release_ggtt_top(_priv->guc);
+ intel_guc_release_ggtt_top(ggtt);
if (drm_mm_initialized(>vm.mm)) {
intel_vgt_deballoon(ggtt);
diff --git a/drivers/gpu/drm/i915/intel_guc.c
b/drivers/gpu/drm/i915/intel_guc.c
index b88c349c4fa6..633248b7da25 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct
intel_guc *guc, u32 size)
/**
* intel_guc_reserved_gtt_size()
- * @guc: intel_guc structure
+ * @ggtt: Pointer to struct i915_ggtt
*
* The GuC WOPCM mapping shadows the lower part of the GGTT, so if we
are using
* GuC we can't have any objects pinned in that region. This function
returns
@@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct
intel_guc *guc, u32 size)
* 0 if GuC is not present or not in use.
* Otherwise, the GuC WOPCM size.
*/
-u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
+u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
{
- return guc_to_i915(guc)->wopcm.guc.size;
+ return ggtt->vm.i915->wopcm.guc.size;
}
-int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
+int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
- struct i915_ggtt *ggtt = >ggtt;
u64 size;
int ret;
+ if (!USES_GUC(ggtt->vm.i915))
+ return 0;
+
size = ggtt->vm.total - GUC_GGTT_TOP;
ret = i915_gem_gtt_reserve(>vm, >uc_fw, size,
@@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc
*guc)
return ret;
}
-void intel_guc_release_ggtt_top(struct intel_guc *guc)
+void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
- struct i915_ggtt *ggtt = >ggtt;
-
if (drm_mm_node_allocated(>uc_fw))
drm_mm_remove_node(>uc_fw);
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h
b/drivers/gpu/drm/i915/intel_guc.h
index cbfed7a77c8b..55ea14176c5e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct
[Intel-gfx] [PATCH v2 2/4] drm/i915: remove some unused declarations from intel_drv.h
intel_mark_busy(), intel_mark_idle(), and skl_cdclk_get_vco() no longer exist. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_drv.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d0aeb383024a..e3f2b9976ead 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1468,8 +1468,6 @@ void intel_add_fb_offsets(int *x, int *y, unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); -void intel_mark_busy(struct drm_i915_private *dev_priv); -void intel_mark_idle(struct drm_i915_private *dev_priv); int intel_display_suspend(struct drm_device *dev); void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); void intel_encoder_destroy(struct drm_encoder *encoder); @@ -1578,7 +1576,6 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) void intel_prepare_reset(struct drm_i915_private *dev_priv); void intel_finish_reset(struct drm_i915_private *dev_priv); -unsigned int skl_cdclk_get_vco(unsigned int freq); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/4] drm/i915: move more atomic plane declarations to intel_atomic_plane.h
Some function declarations in intel_drv.h were missed when intel_atomic_plane.h was created. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_atomic_plane.h | 16 drivers/gpu/drm/i915/intel_drv.h | 12 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.h b/drivers/gpu/drm/i915/intel_atomic_plane.h index 0a9651376d0e..24320041498d 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/intel_atomic_plane.h @@ -6,7 +6,11 @@ #ifndef __INTEL_ATOMIC_PLANE_H__ #define __INTEL_ATOMIC_PLANE_H__ +#include + +struct drm_crtc_state; struct drm_plane; +struct drm_property; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; @@ -38,5 +42,17 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ struct intel_crtc_state *crtc_state, const struct intel_plane_state *old_plane_state, struct intel_plane_state *intel_state); +int intel_plane_atomic_get_property(struct drm_plane *plane, + const struct drm_plane_state *state, + struct drm_property *property, + u64 *val); +int intel_plane_atomic_set_property(struct drm_plane *plane, + struct drm_plane_state *state, + struct drm_property *property, + u64 val); +int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, + struct drm_crtc_state *crtc_state, + const struct intel_plane_state *old_plane_state, + struct drm_plane_state *plane_state); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index e3f2b9976ead..3e337317f77e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1535,18 +1535,6 @@ int intel_prepare_plane_fb(struct drm_plane *plane, struct drm_plane_state *new_state); void intel_cleanup_plane_fb(struct drm_plane *plane, struct drm_plane_state *old_state); -int intel_plane_atomic_get_property(struct drm_plane *plane, - const struct drm_plane_state *state, - struct drm_property *property, - u64 *val); -int intel_plane_atomic_set_property(struct drm_plane *plane, - struct drm_plane_state *state, - struct drm_property *property, - u64 val); -int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, - struct drm_crtc_state *crtc_state, - const struct intel_plane_state *old_plane_state, - struct drm_plane_state *plane_state); void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, enum pipe pipe); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/4] drm/i915: move pm related declarations to intel_pm.h
Move more missed declarations from i915_drv.h to intel_pm.h. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 10 -- drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/intel_pm.h | 9 + 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 89bf1e34feaa..c5af680f79c8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2500,10 +2500,6 @@ extern void i915_driver_unload(struct drm_device *dev); extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); -extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); -extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); -extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); -extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv); @@ -2831,13 +2827,7 @@ extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, extern void intel_display_resume(struct drm_device *dev); extern void i915_redisable_vga(struct drm_i915_private *dev_priv); extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); -extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); -extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); -extern void intel_rps_mark_interactive(struct drm_i915_private *i915, - bool interactive); -extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, - bool enable); int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index ca8f4226e598..11c451358fb8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -44,6 +44,7 @@ #include "intel_fifo_underrun.h" #include "intel_hotplug.h" #include "intel_lpe_audio.h" +#include "intel_pm.h" #include "intel_psr.h" /** diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 17339c99440c..1b489fa399e1 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -77,5 +77,14 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg); u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); +unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); +unsigned long i915_mch_val(struct drm_i915_private *dev_priv); +unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); +void i915_update_gfx_val(struct drm_i915_private *dev_priv); + +bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); +int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); +void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive); +bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); #endif /* __INTEL_PM_H__ */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/4] drm/i915/frontbuffer: remove obsolete comment about mark busy/idle
This no longer exists. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_frontbuffer.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c index aa34e33b6087..d6036b9ad16a 100644 --- a/drivers/gpu/drm/i915/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/intel_frontbuffer.c @@ -53,14 +53,8 @@ * busyness. There is no direct way to detect idleness. Instead an idle timer * work delayed work should be started from the flush and flip functions and * cancelled as soon as busyness is detected. - * - * Note that there's also an older frontbuffer activity tracking scheme which - * just tracks general activity. This is done by the various mark_busy and - * mark_idle functions. For display power management features using these - * functions is deprecated and should be avoided. */ - #include "i915_drv.h" #include "intel_dp.h" #include "intel_drv.h" -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: rename header test build commands to avoid conflicts
On Thu, 06 Jun 2019, Masahiro Yamada wrote: > On Thu, Jun 6, 2019 at 4:57 PM Jani Nikula wrote: >> >> You're totally right, it needs to be fixed in your tree. For that, I >> think the best option is your fixup patch #2. > > > OK, I will squash patch #2. Many thanks! BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: rename header test build commands to avoid conflicts
On Thu, Jun 6, 2019 at 4:57 PM Jani Nikula wrote: > > You're totally right, it needs to be fixed in your tree. For that, I > think the best option is your fixup patch #2. OK, I will squash patch #2. -- Best Regards Masahiro Yamada ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-fixes
Quoting Zhenyu Wang (2019-06-05 11:49:03) > > Hi, > > More gvt fixes for 5.2-rc. This fixed one regression when enabling > debug build of i915 guest, guest ring state fix after execution > for hang check, and with two misc fixes from klocwork check. Pulled this. Thanks for the PR. Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave & Daniel, No i915 fixes this week, but forwarding the GVT pull request still. One GVT regression fix for debug build of i915 guest, guest ring state fix after execution for hang check and a couple of static checker fixes. CI is being clogged curently, but we really don't have that much GVT coverage anyway, so sending the PR before leaving. Git log is confused/wrong here, dim status indicates 5 unmerged patches at the time of sending, and those are the GVT patches. See the tag gvt-fixes-2019-06-05 for details. Once you pull this, Jani gets to move DIF to -rc4 next week. Regards, Joonas PS. At the time of pulling, you can check if CI_DIF_380 full IGT run results have appeared in: https://intel-gfx-ci.01.org/tree/drm-intel-fixes/combined-alt.html *** drm-intel-fixes-2019-06-06: - Include gvt-fixes-2019-06-05 The following changes since commit cd6c84d8f0cdc911df435bb075ba22ce3c605b07: Linux 5.2-rc2 (2019-05-26 16:49:19 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-06-06 for you to fetch changes up to fa2eb819ddf9bf671077f3711441208532118a5c: Merge tag 'gvt-fixes-2019-06-05' of https://github.com/intel/gvt-linux into drm-intel-fixes (2019-06-05 12:27:50 +0300) - Include gvt-fixes-2019-06-05 Aleksei Gimbitskii (2): drm/i915/gvt: Check if cur_pt_type is valid drm/i915/gvt: Assign NULL to the pointer after memory free. Colin Xu (3): drm/i915/gvt: Update force-to-nonpriv register whitelist drm/i915/gvt: Fix GFX_MODE handling drm/i915/gvt: Fix vGPU CSFE_CHICKEN1_REG mmio handler Gao, Fred (1): drm/i915/gvt: Fix cmd length of VEB_DI_IECP Joonas Lahtinen (2): Merge tag 'gvt-fixes-2019-05-30' of https://github.com/intel/gvt-linux into drm-intel-fixes Merge tag 'gvt-fixes-2019-06-05' of https://github.com/intel/gvt-linux into drm-intel-fixes Tina Zhang (1): drm/i915/gvt: Initialize intel_gvt_gtt_entry in stack Tvrtko Ursulin (1): drm/i915/icl: Add WaDisableBankHangMode Weinan Li (1): drm/i915/gvt: add F_CMD_ACCESS flag for wa regs Xiaolin Zhang (1): drm/i915/gvt: save RING_HEAD into vreg when vgpu switched out Xiong Zhang (1): drm/i915/gvt: refine ggtt range validation drivers/gpu/drm/i915/gvt/cmd_parser.c| 2 +- drivers/gpu/drm/i915/gvt/gtt.c | 38 ++--- drivers/gpu/drm/i915/gvt/handlers.c | 49 +++- drivers/gpu/drm/i915/gvt/reg.h | 2 ++ drivers/gpu/drm/i915/gvt/scheduler.c | 25 drivers/gpu/drm/i915/gvt/scheduler.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_workarounds.c | 6 8 files changed, 108 insertions(+), 18 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt
On Thu, 06 Jun 2019 11:36:38 +0200, Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
These functions operate on ggtt so make them take that directly as
parameter.
Not quite.
Function intel_guc_reserved_gtt_size() operates on struct intel_guc
and is defined in intel_guc.c for proper layering, so NAK here.
For other two intel_guc_reserve|release_ggtt_top() I would rather:
- rename them to i915_ggtt_reserve|release_guc_top(),
- move to i915_gem_ggtt.c
- make them static
Michal
At the same time move the USES_GUC conditional down to
intel_guc_reserve_ggtt_top for symmetry with
intel_guc_reserved_gtt_size.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++
drivers/gpu/drm/i915/intel_guc.c| 18 --
drivers/gpu/drm/i915/intel_guc.h| 6 +++---
3 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d3b3676d10f3..d967a4e9ceb0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
* why.
*/
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
- intel_guc_reserved_gtt_size(_priv->guc));
+ intel_guc_reserved_gtt_size(ggtt));
ret = intel_vgt_balloon(ggtt);
if (ret)
@@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
if (ret)
return ret;
- if (USES_GUC(dev_priv)) {
- ret = intel_guc_reserve_ggtt_top(_priv->guc);
- if (ret)
- goto err_reserve;
- }
+ ret = intel_guc_reserve_ggtt_top(ggtt);
+ if (ret)
+ goto err_reserve;
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, >vm.mm, hole_start, hole_end) {
@@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
return 0;
err_appgtt:
- intel_guc_release_ggtt_top(_priv->guc);
+ intel_guc_release_ggtt_top(ggtt);
err_reserve:
drm_mm_remove_node(>error_capture);
return ret;
@@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
if (drm_mm_node_allocated(>error_capture))
drm_mm_remove_node(>error_capture);
- intel_guc_release_ggtt_top(_priv->guc);
+ intel_guc_release_ggtt_top(ggtt);
if (drm_mm_initialized(>vm.mm)) {
intel_vgt_deballoon(ggtt);
diff --git a/drivers/gpu/drm/i915/intel_guc.c
b/drivers/gpu/drm/i915/intel_guc.c
index b88c349c4fa6..633248b7da25 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct
intel_guc *guc, u32 size)
/**
* intel_guc_reserved_gtt_size()
- * @guc: intel_guc structure
+ * @ggtt: Pointer to struct i915_ggtt
*
* The GuC WOPCM mapping shadows the lower part of the GGTT, so if we
are using
* GuC we can't have any objects pinned in that region. This function
returns
@@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct
intel_guc *guc, u32 size)
* 0 if GuC is not present or not in use.
* Otherwise, the GuC WOPCM size.
*/
-u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
+u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
{
- return guc_to_i915(guc)->wopcm.guc.size;
+ return ggtt->vm.i915->wopcm.guc.size;
}
-int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
+int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
- struct i915_ggtt *ggtt = >ggtt;
u64 size;
int ret;
+ if (!USES_GUC(ggtt->vm.i915))
+ return 0;
+
size = ggtt->vm.total - GUC_GGTT_TOP;
ret = i915_gem_gtt_reserve(>vm, >uc_fw, size,
@@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc
*guc)
return ret;
}
-void intel_guc_release_ggtt_top(struct intel_guc *guc)
+void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
- struct i915_ggtt *ggtt = >ggtt;
-
if (drm_mm_node_allocated(>uc_fw))
drm_mm_remove_node(>uc_fw);
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h
b/drivers/gpu/drm/i915/intel_guc.h
index cbfed7a77c8b..55ea14176c5e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32
rsa_offset);
int intel_guc_suspend(struct intel_guc *guc);
int intel_guc_resume(struct intel_guc *guc);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32
size);
-u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
-int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
-void
Re: [Intel-gfx] [RFC] drm: Do not call drm_probe_ddc() when connector force isn't specified
On Thu, 06 Jun 2019, Daniel Vetter wrote:
> On Thu, Jun 6, 2019 at 9:38 AM Harish Chegondi
> wrote:
>>
>> This would allow the EDID override to be handled correctly in
>> drm_do_get_edid() for cases where EDID data is missing or corrupt.
>>
>> All drm_probe_ddc() does is call drm_do_probe_ddc_edid( , , , 1)
>> which probes the display by reading 1 byte of EDID data via I2C.
>> This patch removes the call to drm_probe_ddc() from drm_get_edid()
>> but drm_get_edid() calls drm_do_get_edid() which first handles
>> the EDID override case and then calls
>> drm_do_probe_ddc_edid( , , ,EDID_LENGTH) via function pointer
>> argument get_edid_block. So, the display device is still being
>> probed by reading EDID_LENGTH bytes of EDID data via I2C.
>>
>> Cc: Jani Nikula
>> Cc: Ville Syrjälä
>> Signed-off-by: Harish Chegondi
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=107583
>
> Since it's a regression we need to annotate this correctly, for the
> next version please include:
>
> Fixes: 53fd40a90f3c ("drm: handle override and firmware EDID at
> drm_do_get_edid() level")
> Cc: # v4.15+
>
> So there's a pile more drm_probe_ddc calls all around in drivers, but
> I reviewed them all, and they're all in ->detect callbacks. So not
> affecting the regression we're discussing here. Looking at
> drm_do_get_edid this should also not result in more failures. The only
> thing this changes is that drm_do_get_edid will retry a bunch more
> times if nothing is connected (4 times, instead of just the one probe
> that drm_probe_ddc does). I guess we can restore that if anyone cares,
> should at least mention it in the commit message.
>
> Reviewed-by: Daniel Vetter
Like I explained in my reply, this essentially makes override/firmware
EDID a connector force for the case where hotplug detect isn't used or
reliable. That's a regression for another set of people...
BR,
Jani.
>
>
>> ---
>> drivers/gpu/drm/drm_edid.c | 3 ---
>> 1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index d87f574feeca..41c420706532 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -1724,9 +1724,6 @@ struct edid *drm_get_edid(struct drm_connector
>> *connector,
>> if (connector->force == DRM_FORCE_OFF)
>> return NULL;
>>
>> - if (connector->force == DRM_FORCE_UNSPECIFIED &&
>> !drm_probe_ddc(adapter))
>> - return NULL;
>
> Trouble is there's a lot more drm_probe_ddc calls all over, and a lot of these
>> -
>> edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
>> if (edid)
>> drm_get_displayid(connector, edid);
>> --
>> 2.21.0
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Skip context_barrier emission for unused contexts
On 06/06/2019 12:37, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-06-06 12:28:23)
On 06/06/2019 12:06, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-06-06 10:19:10)
On 06/06/2019 10:09, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-06-05 11:40:27)
On 04/06/2019 16:24, Chris Wilson wrote:
The intent was to skip unused HW contexts by checking ce->state.
However, this only works for execlists where the ppGTT pointers is
stored inside the HW context. For gen7, the ppGTT is alongside the
logical state and must be updated on all active engines but, crucially,
only on active engines. As we need different checks, and to keep
context_barrier_task() agnostic, pass in the predicate.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110836
Fixes: 62c8e423450d ("drm/i915: Skip unused contexts for
context_barrier_task()")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++-
.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 08721ef62e4e..6819b598d226 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -902,6 +902,7 @@ static void cb_retire(struct i915_active *base)
I915_SELFTEST_DECLARE(static intel_engine_mask_t
context_barrier_inject_fault);
static int context_barrier_task(struct i915_gem_context *ctx,
intel_engine_mask_t engines,
+ bool (*skip)(struct intel_context *ce, void
*data),
int (*emit)(struct i915_request *rq, void
*data),
void (*task)(void *data),
void *data)
@@ -931,7 +932,10 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
break;
}
- if (!(ce->engine->mask & engines) || !ce->state)
+ if (!(ce->engine->mask & engines))
+ continue;
+
+ if (skip && skip(ce, data))
continue;
rq = intel_context_create_request(ce);
@@ -1058,6 +1062,14 @@ static int emit_ppgtt_update(struct i915_request *rq,
void *data)
return 0;
}
+static bool skip_ppgtt_update(struct intel_context *ce, void *data)
+{
+ if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
+ return !ce->state;
+ else
+ return !atomic_read(>pin_count);
Would "return !atomic_read(>pin_count) || !ce->state;" work and
avoid the somewhat irky HAS_LOGICAL_RING_CONTEXTS check?
No, because we need the barrier on gen7 !rcs which doesn't have
ce->state (but does need to switch mm).
That's not the path which would be covered by !atomic_read(>pin_count) ?
And when pin_count > 0 it would then skip due to !ce->state, leading us
back to the current problem.
Brain fart.. Okay.. but pin_count check itself is not sufficient for
both platforms? Can't we skip pin_count == 0 && ce->state != NULL on
execlists?
Alas not. It is really is a divergence in HW behaviour.
For execlists, we need to modifying an existing context image, but may
skip if there is no image at all (as it will be constructed with the
right registers).
For gen7, we need to take care of the supplementary pinning of
ctx->ppgtt. That is done for us on the first context_pin, but when
pin_count > 0, we must fiddle. Fiddly fiddling. There's probably a way
to resolve it without having to pull so much lower level detail into
i915_gem_context.c, I am not seeing it atm (and honestly not looking too
hard ;).
Okay, I don't fancy looking too hard either. It was only a discussion
about a potential optimisation to begin with. So without much further ado:
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Report an earlier wedged event when suspending the engines
Quoting Chris Wilson (2019-05-31 12:32:45) > On i915_gem_load_power_context() we do care whether or not we succeed in > completing the switch back to the kernel context (via idling the > engines). Currently, we detect if an error occurs while we wait, but we > do not report one if it occurred beforehand (and the status of the > switch is undefined). Check the current terminally wedged status on > entering the wait, and report it after flushing the requests, as if it > had occurred during our own wait. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110824 > Signed-off-by: Chris Wilson ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move object close under its own lock
== Series Details == Series: drm/i915: Move object close under its own lock URL : https://patchwork.freedesktop.org/series/61710/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Move object close under its own lock +./include/linux/reservation.h:220:20: warning: dereference of noderef expression +./include/linux/reservation.h:220:45: warning: dereference of noderef expression ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Skip context_barrier emission for unused contexts
Quoting Tvrtko Ursulin (2019-06-06 12:28:23)
>
> On 06/06/2019 12:06, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-06 10:19:10)
> >>
> >> On 06/06/2019 10:09, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-06-05 11:40:27)
>
> On 04/06/2019 16:24, Chris Wilson wrote:
> > The intent was to skip unused HW contexts by checking ce->state.
> > However, this only works for execlists where the ppGTT pointers is
> > stored inside the HW context. For gen7, the ppGTT is alongside the
> > logical state and must be updated on all active engines but, crucially,
> > only on active engines. As we need different checks, and to keep
> > context_barrier_task() agnostic, pass in the predicate.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110836
> > Fixes: 62c8e423450d ("drm/i915: Skip unused contexts for
> > context_barrier_task()")
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++-
> > .../drm/i915/gem/selftests/i915_gem_context.c | 19
> > +++
> > 2 files changed, 29 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index 08721ef62e4e..6819b598d226 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -902,6 +902,7 @@ static void cb_retire(struct i915_active *base)
> > I915_SELFTEST_DECLARE(static intel_engine_mask_t
> > context_barrier_inject_fault);
> > static int context_barrier_task(struct i915_gem_context *ctx,
> > intel_engine_mask_t engines,
> > + bool (*skip)(struct intel_context *ce,
> > void *data),
> > int (*emit)(struct i915_request *rq,
> > void *data),
> > void (*task)(void *data),
> > void *data)
> > @@ -931,7 +932,10 @@ static int context_barrier_task(struct
> > i915_gem_context *ctx,
> > break;
> > }
> >
> > - if (!(ce->engine->mask & engines) || !ce->state)
> > + if (!(ce->engine->mask & engines))
> > + continue;
> > +
> > + if (skip && skip(ce, data))
> > continue;
> >
> > rq = intel_context_create_request(ce);
> > @@ -1058,6 +1062,14 @@ static int emit_ppgtt_update(struct i915_request
> > *rq, void *data)
> > return 0;
> > }
> >
> > +static bool skip_ppgtt_update(struct intel_context *ce, void *data)
> > +{
> > + if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
> > + return !ce->state;
> > + else
> > + return !atomic_read(>pin_count);
>
> Would "return !atomic_read(>pin_count) || !ce->state;" work and
> avoid the somewhat irky HAS_LOGICAL_RING_CONTEXTS check?
> >>>
> >>> No, because we need the barrier on gen7 !rcs which doesn't have
> >>> ce->state (but does need to switch mm).
> >>
> >> That's not the path which would be covered by !atomic_read(>pin_count)
> >> ?
> >
> > And when pin_count > 0 it would then skip due to !ce->state, leading us
> > back to the current problem.
>
> Brain fart.. Okay.. but pin_count check itself is not sufficient for
> both platforms? Can't we skip pin_count == 0 && ce->state != NULL on
> execlists?
Alas not. It is really is a divergence in HW behaviour.
For execlists, we need to modifying an existing context image, but may
skip if there is no image at all (as it will be constructed with the
right registers).
For gen7, we need to take care of the supplementary pinning of
ctx->ppgtt. That is done for us on the first context_pin, but when
pin_count > 0, we must fiddle. Fiddly fiddling. There's probably a way
to resolve it without having to pull so much lower level detail into
i915_gem_context.c, I am not seeing it atm (and honestly not looking too
hard ;).
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm: Do not call drm_probe_ddc() when connector force isn't specified
On Thu, Jun 6, 2019 at 9:38 AM Harish Chegondi
wrote:
>
> This would allow the EDID override to be handled correctly in
> drm_do_get_edid() for cases where EDID data is missing or corrupt.
>
> All drm_probe_ddc() does is call drm_do_probe_ddc_edid( , , , 1)
> which probes the display by reading 1 byte of EDID data via I2C.
> This patch removes the call to drm_probe_ddc() from drm_get_edid()
> but drm_get_edid() calls drm_do_get_edid() which first handles
> the EDID override case and then calls
> drm_do_probe_ddc_edid( , , ,EDID_LENGTH) via function pointer
> argument get_edid_block. So, the display device is still being
> probed by reading EDID_LENGTH bytes of EDID data via I2C.
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: Harish Chegondi
> References: https://bugs.freedesktop.org/show_bug.cgi?id=107583
Since it's a regression we need to annotate this correctly, for the
next version please include:
Fixes: 53fd40a90f3c ("drm: handle override and firmware EDID at
drm_do_get_edid() level")
Cc: # v4.15+
So there's a pile more drm_probe_ddc calls all around in drivers, but
I reviewed them all, and they're all in ->detect callbacks. So not
affecting the regression we're discussing here. Looking at
drm_do_get_edid this should also not result in more failures. The only
thing this changes is that drm_do_get_edid will retry a bunch more
times if nothing is connected (4 times, instead of just the one probe
that drm_probe_ddc does). I guess we can restore that if anyone cares,
should at least mention it in the commit message.
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_edid.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index d87f574feeca..41c420706532 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1724,9 +1724,6 @@ struct edid *drm_get_edid(struct drm_connector
> *connector,
> if (connector->force == DRM_FORCE_OFF)
> return NULL;
>
> - if (connector->force == DRM_FORCE_UNSPECIFIED &&
> !drm_probe_ddc(adapter))
> - return NULL;
Trouble is there's a lot more drm_probe_ddc calls all over, and a lot of these
> -
> edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
> if (edid)
> drm_get_displayid(connector, edid);
> --
> 2.21.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Skip context_barrier emission for unused contexts
On 06/06/2019 12:06, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-06-06 10:19:10)
On 06/06/2019 10:09, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-06-05 11:40:27)
On 04/06/2019 16:24, Chris Wilson wrote:
The intent was to skip unused HW contexts by checking ce->state.
However, this only works for execlists where the ppGTT pointers is
stored inside the HW context. For gen7, the ppGTT is alongside the
logical state and must be updated on all active engines but, crucially,
only on active engines. As we need different checks, and to keep
context_barrier_task() agnostic, pass in the predicate.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110836
Fixes: 62c8e423450d ("drm/i915: Skip unused contexts for
context_barrier_task()")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++-
.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 08721ef62e4e..6819b598d226 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -902,6 +902,7 @@ static void cb_retire(struct i915_active *base)
I915_SELFTEST_DECLARE(static intel_engine_mask_t
context_barrier_inject_fault);
static int context_barrier_task(struct i915_gem_context *ctx,
intel_engine_mask_t engines,
+ bool (*skip)(struct intel_context *ce, void
*data),
int (*emit)(struct i915_request *rq, void
*data),
void (*task)(void *data),
void *data)
@@ -931,7 +932,10 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
break;
}
- if (!(ce->engine->mask & engines) || !ce->state)
+ if (!(ce->engine->mask & engines))
+ continue;
+
+ if (skip && skip(ce, data))
continue;
rq = intel_context_create_request(ce);
@@ -1058,6 +1062,14 @@ static int emit_ppgtt_update(struct i915_request *rq,
void *data)
return 0;
}
+static bool skip_ppgtt_update(struct intel_context *ce, void *data)
+{
+ if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
+ return !ce->state;
+ else
+ return !atomic_read(>pin_count);
Would "return !atomic_read(>pin_count) || !ce->state;" work and
avoid the somewhat irky HAS_LOGICAL_RING_CONTEXTS check?
No, because we need the barrier on gen7 !rcs which doesn't have
ce->state (but does need to switch mm).
That's not the path which would be covered by !atomic_read(>pin_count) ?
And when pin_count > 0 it would then skip due to !ce->state, leading us
back to the current problem.
Brain fart.. Okay.. but pin_count check itself is not sufficient for
both platforms? Can't we skip pin_count == 0 && ce->state != NULL on
execlists?
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Move object close under its own lock
Use i915_gem_object_lock() to guard the LUT and active reference to
allow us to break free of struct_mutex for handling GEM_CLOSE.
Testcase: igt/gem_close_race
Testcase: igt/gem_exec_parallel
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 80 ++-
.../gpu/drm/i915/gem/i915_gem_context_types.h | 12 +--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 25 --
drivers/gpu/drm/i915/gem/i915_gem_object.c| 38 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
.../gpu/drm/i915/gem/selftests/mock_context.c | 1 -
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
drivers/gpu/drm/i915/i915_timeline.c | 13 +--
drivers/gpu/drm/i915/i915_vma.c | 48 +++
drivers/gpu/drm/i915/i915_vma.h | 17 ++--
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
13 files changed, 139 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 08721ef62e4e..6cac1c144c79 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -95,24 +95,45 @@ void i915_lut_handle_free(struct i915_lut_handle *lut)
static void lut_close(struct i915_gem_context *ctx)
{
- struct i915_lut_handle *lut, *ln;
struct radix_tree_iter iter;
void __rcu **slot;
- list_for_each_entry_safe(lut, ln, >handles_list, ctx_link) {
- list_del(>obj_link);
- i915_lut_handle_free(lut);
- }
- INIT_LIST_HEAD(>handles_list);
+ lockdep_assert_held(>mutex);
rcu_read_lock();
radix_tree_for_each_slot(slot, >handles_vma, , 0) {
struct i915_vma *vma = rcu_dereference_raw(*slot);
+ struct drm_i915_gem_object *obj = vma->obj;
+ struct i915_lut_handle *lut;
+
+ if (!kref_get_unless_zero(>base.refcount))
+ continue;
- radix_tree_iter_delete(>handles_vma, , slot);
+ rcu_read_unlock();
+ i915_gem_object_lock(obj);
+ list_for_each_entry(lut, >lut_list, obj_link) {
+ if (lut->ctx != ctx)
+ continue;
- vma->open_count--;
- i915_vma_put(vma);
+ if (lut->handle != iter.index)
+ continue;
+
+ list_del(>obj_link);
+ break;
+ }
+ i915_gem_object_unlock(obj);
+ rcu_read_lock();
+
+ if (>obj_link != >lut_list) {
+ i915_lut_handle_free(lut);
+ radix_tree_iter_delete(>handles_vma, , slot);
+ if (atomic_dec_and_test(>open_count) &&
+ !i915_vma_is_ggtt(vma))
+ i915_vma_close(vma);
+ i915_gem_object_put(obj);
+ }
+
+ i915_gem_object_put(obj);
}
rcu_read_unlock();
}
@@ -250,15 +271,9 @@ static void free_engines(struct i915_gem_engines *e)
__free_engines(e, e->num_engines);
}
-static void free_engines_rcu(struct work_struct *wrk)
+static void free_engines_rcu(struct rcu_head *rcu)
{
- struct i915_gem_engines *e =
- container_of(wrk, struct i915_gem_engines, rcu.work);
- struct drm_i915_private *i915 = e->i915;
-
- mutex_lock(>drm.struct_mutex);
- free_engines(e);
- mutex_unlock(>drm.struct_mutex);
+ free_engines(container_of(rcu, struct i915_gem_engines, rcu));
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
@@ -271,7 +286,7 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- e->i915 = ctx->i915;
+ init_rcu_head(>rcu);
for_each_engine(engine, ctx->i915, id) {
struct intel_context *ce;
@@ -359,7 +374,10 @@ void i915_gem_context_release(struct kref *ref)
static void context_close(struct i915_gem_context *ctx)
{
+ mutex_lock(>mutex);
+
i915_gem_context_set_closed(ctx);
+ ctx->file_priv = ERR_PTR(-EBADF);
/*
* This context will never again be assinged to HW, so we can
@@ -374,7 +392,7 @@ static void context_close(struct i915_gem_context *ctx)
*/
lut_close(ctx);
- ctx->file_priv = ERR_PTR(-EBADF);
+ mutex_unlock(>mutex);
i915_gem_context_put(ctx);
}
@@ -429,7 +447,6 @@ __create_context(struct drm_i915_private *dev_priv)
RCU_INIT_POINTER(ctx->engines, e);
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
- INIT_LIST_HEAD(>handles_list);
Re: [Intel-gfx] [RFC] drm: Do not call drm_probe_ddc() when connector force isn't specified
On Thu, 06 Jun 2019, Harish Chegondi wrote:
> This would allow the EDID override to be handled correctly in
> drm_do_get_edid() for cases where EDID data is missing or corrupt.
>
> All drm_probe_ddc() does is call drm_do_probe_ddc_edid( , , , 1)
> which probes the display by reading 1 byte of EDID data via I2C.
> This patch removes the call to drm_probe_ddc() from drm_get_edid()
> but drm_get_edid() calls drm_do_get_edid() which first handles
> the EDID override case and then calls
> drm_do_probe_ddc_edid( , , ,EDID_LENGTH) via function pointer
> argument get_edid_block. So, the display device is still being
> probed by reading EDID_LENGTH bytes of EDID data via I2C.
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: Harish Chegondi
> References: https://bugs.freedesktop.org/show_bug.cgi?id=107583
> ---
> drivers/gpu/drm/drm_edid.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index d87f574feeca..41c420706532 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1724,9 +1724,6 @@ struct edid *drm_get_edid(struct drm_connector
> *connector,
> if (connector->force == DRM_FORCE_OFF)
> return NULL;
>
> - if (connector->force == DRM_FORCE_UNSPECIFIED &&
> !drm_probe_ddc(adapter))
> - return NULL;
> -
> edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
> if (edid)
> drm_get_displayid(connector, edid);
We've had the drm_probe_ddc() since 61e57a8d72f2 ("drm/edid: Fix
secondary block fetch.") in 2010. The commit message does not shed any
light on why this was added, though I assume early and fast bail out
when the DDC isn't there.
In any case, this patch solves one problem, but creates another. It
loses the ability to use DDC probe to detect display presence when using
firmware/override EDID, i.e. the firmware/override EDID effectively
leads to connector forcing.
In the referenced bug, the problem is that hotplug detect works, but DDC
does not. Using connector forcing to work around the issue leads to
losing hotplug detect.
IMO the override/firmware EDID should be orthogonal to hotplug detect,
regardless of whether the detect is achieved via source hardware detect
or DDC.
If you need to allow for cases where one or the other hotplug detect
methods is bust, the only viable solution is to add another level of
connector force to bypass drm_probe_ddc() above, yet rely on hardware
hotplug detect. Say, DRM_FORCE_ON_DDC.
It does mean the folks affected by the referenced bug would need to work
around their experienced regression by adding a connector force, *but*
we are talking about folks with broken displays.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V8 i-g-t] tests/kms_flip: Skip VBlank tests in modules without VBlank
On Tue, 2019-06-04 at 23:30 -0300, Rodrigo Siqueira wrote:
> The kms_flip test relies on VBlank support, and this situation may
> exclude some virtual drivers to take advantage of this set of tests.
> This commit adds a mechanism that checks if a module has VBlank. If the
> target module has VBlank support, kms_flip will run all the VBlank
> tests; otherwise, the VBlank tests will be skipped. Additionally, this
> commit improves the test coverage by checks if the function
> drmWaitVBlank() returns EOPNOTSUPP (i.e., no VBlank support).
>
> V7: Changes since V6
> - Skip TEST_DPMS with TEST_MODESET and TEST_EBUSY if the device does
>not support vblank
Hmm, I'm not sure I understand this line. If I'm reading this correctly
it refers to this line:
if (!(o->flags & (TEST_DPMS | TEST_MODESET | TEST_NO_VBLANK)))
So the check was previously skipped on TEST_DPMS and TEST_MODESET. It's
now skipped on TEST_NO_VBLANK too. So I'm a little confused with the
changelog line: should it say "skip seq number checking it the device
doesn't support vblank"?
Am I missing something?
Apart from this, the patch itself looks good to me.
> V6: Set errno to zero before call drmWaitVBlank() (Chris Wilson)
>
> V5: Drop the DRM_VBLANK_NEXTONMISS (Chris Wilson)
>
> V4: Replace DRM_VBLANK_ABSOLUTE by DRM_VBLANK_RELATIVE and
> DRM_VBLANK_NEXTONMISS
>
> V3: Add documentation (Daniel Vetter)
>
> V2: Add new branch coverage to check if VBlank is enabled or not and
> update commit message
>
> V1: Chris Wilson
> - Change function name from igt_there_is_vblank to kms_has_vblank
> - Move vblank function check from igt_aux to igt_kms
> - Utilizes memset in dummy_vbl variable
> - Directly return the result of drmWaitVBlank()
>
> Signed-off-by: Rodrigo Siqueira
> ---
> lib/igt_kms.c| 21 +
> lib/igt_kms.h| 2 ++
> tests/kms_flip.c | 24 +++-
> 3 files changed, 46 insertions(+), 1 deletion(-)
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index d7d711a7..8a465f67 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -1673,6 +1673,27 @@ void igt_assert_plane_visible(int fd, enum pipe pipe,
> int plane_index, bool visi
> igt_assert_eq(visible, visibility);
> }
>
> +/**
> + * kms_has_vblank:
> + * @fd: DRM fd
> + *
> + * Get the VBlank errno after an attempt to call drmWaitVBlank(). This
> + * function is useful for checking if a driver has support or not for VBlank.
> + *
> + * Returns: true if target driver has VBlank support, otherwise return false.
> + */
> +bool kms_has_vblank(int fd)
> +{
> + drmVBlank dummy_vbl;
> +
> + memset(_vbl, 0, sizeof(drmVBlank));
> + dummy_vbl.request.type = DRM_VBLANK_RELATIVE;
> +
> + errno = 0;
> + drmWaitVBlank(fd, _vbl);
> + return (errno != EOPNOTSUPP);
> +}
> +
> /*
> * A small modeset API
> */
> diff --git a/lib/igt_kms.h b/lib/igt_kms.h
> index 4ac28131..5b5cf274 100644
> --- a/lib/igt_kms.h
> +++ b/lib/igt_kms.h
> @@ -229,6 +229,8 @@ void kmstest_wait_for_pageflip(int fd);
> unsigned int kmstest_get_vblank(int fd, int pipe, unsigned int flags);
> void igt_assert_plane_visible(int fd, enum pipe pipe, int plane_index, bool
> visibility);
>
> +bool kms_has_vblank(int fd);
> +
> /*
> * A small modeset API
> */
> diff --git a/tests/kms_flip.c b/tests/kms_flip.c
> index d7c1f9cf..2a158d97 100755
> --- a/tests/kms_flip.c
> +++ b/tests/kms_flip.c
> @@ -71,6 +71,7 @@
> #define TEST_SUSPEND (1 << 26)
> #define TEST_BO_TOOBIG (1 << 28)
>
> +#define TEST_NO_VBLANK (1 << 29)
> #define TEST_BASIC (1 << 30)
>
> #define EVENT_FLIP (1 << 0)
> @@ -126,6 +127,18 @@ struct event_state {
> int seq_step;
> };
>
> +static bool vblank_dependence(int flags)
> +{
> + int vblank_flags = TEST_VBLANK | TEST_VBLANK_BLOCK |
> +TEST_VBLANK_ABSOLUTE | TEST_VBLANK_EXPIRED_SEQ |
> +TEST_CHECK_TS | TEST_VBLANK_RACE | TEST_EBUSY;
> +
> + if (flags & vblank_flags)
> + return true;
> +
> + return false;
> +}
> +
> static float timeval_float(const struct timeval *tv)
> {
> return tv->tv_sec + tv->tv_usec / 100.0f;
> @@ -494,7 +507,7 @@ static void check_state(const struct test_output *o,
> const struct event_state *e
> /* check only valid if no modeset happens in between, that increments by
>* (1 << 23) on each step. This bounding matches the one in
>* DRM_IOCTL_WAIT_VBLANK. */
> - if (!(o->flags & (TEST_DPMS | TEST_MODESET)))
> + if (!(o->flags & (TEST_DPMS | TEST_MODESET | TEST_NO_VBLANK)))
> igt_assert_f(es->current_seq - (es->last_seq + o->seq_step) <=
> 1UL << 23,
>"unexpected %s seq %u, should be >= %u\n",
>es->name, es->current_seq, es->last_seq +
> o->seq_step);
> @@ -1176,6 +1189,7 @@ static void run_test_on_crtc_set(struct test_output *o,
> int
Re: [Intel-gfx] [PATCH] drm/i915: Skip context_barrier emission for unused contexts
Quoting Tvrtko Ursulin (2019-06-06 10:19:10)
>
> On 06/06/2019 10:09, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-05 11:40:27)
> >>
> >> On 04/06/2019 16:24, Chris Wilson wrote:
> >>> The intent was to skip unused HW contexts by checking ce->state.
> >>> However, this only works for execlists where the ppGTT pointers is
> >>> stored inside the HW context. For gen7, the ppGTT is alongside the
> >>> logical state and must be updated on all active engines but, crucially,
> >>> only on active engines. As we need different checks, and to keep
> >>> context_barrier_task() agnostic, pass in the predicate.
> >>>
> >>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110836
> >>> Fixes: 62c8e423450d ("drm/i915: Skip unused contexts for
> >>> context_barrier_task()")
> >>> Signed-off-by: Chris Wilson
> >>> Cc: Tvrtko Ursulin
> >>> ---
> >>>drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++-
> >>>.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++
> >>>2 files changed, 29 insertions(+), 5 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> index 08721ef62e4e..6819b598d226 100644
> >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> @@ -902,6 +902,7 @@ static void cb_retire(struct i915_active *base)
> >>>I915_SELFTEST_DECLARE(static intel_engine_mask_t
> >>> context_barrier_inject_fault);
> >>>static int context_barrier_task(struct i915_gem_context *ctx,
> >>>intel_engine_mask_t engines,
> >>> + bool (*skip)(struct intel_context *ce, void
> >>> *data),
> >>>int (*emit)(struct i915_request *rq, void
> >>> *data),
> >>>void (*task)(void *data),
> >>>void *data)
> >>> @@ -931,7 +932,10 @@ static int context_barrier_task(struct
> >>> i915_gem_context *ctx,
> >>>break;
> >>>}
> >>>
> >>> - if (!(ce->engine->mask & engines) || !ce->state)
> >>> + if (!(ce->engine->mask & engines))
> >>> + continue;
> >>> +
> >>> + if (skip && skip(ce, data))
> >>>continue;
> >>>
> >>>rq = intel_context_create_request(ce);
> >>> @@ -1058,6 +1062,14 @@ static int emit_ppgtt_update(struct i915_request
> >>> *rq, void *data)
> >>>return 0;
> >>>}
> >>>
> >>> +static bool skip_ppgtt_update(struct intel_context *ce, void *data)
> >>> +{
> >>> + if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
> >>> + return !ce->state;
> >>> + else
> >>> + return !atomic_read(>pin_count);
> >>
> >> Would "return !atomic_read(>pin_count) || !ce->state;" work and
> >> avoid the somewhat irky HAS_LOGICAL_RING_CONTEXTS check?
> >
> > No, because we need the barrier on gen7 !rcs which doesn't have
> > ce->state (but does need to switch mm).
>
> That's not the path which would be covered by !atomic_read(>pin_count) ?
And when pin_count > 0 it would then skip due to !ce->state, leading us
back to the current problem.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/21] Implicit dev_priv removal
On 06/06/2019 11:05, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-06-06 10:36:18) From: Tvrtko Ursulin Mostly patches reworking the code and GEM init paths to remove some implicit dev_priv dependencies (I915_READ/I915_WRITE), plus some small tweaks to tidy GEM init paths to use more logical input parameters (enabled by the conversion to uncore mmio accessors). Passing intel_uncore to non intel_uncore functions during init, I disagree with as it makes the layering violations worse for no apparent gain. For gem_init_hw it is questionable I agree. Idea was that it logically makes sense to pass what is functionally used. And for majority this seems to be uncore with i915 being used only for "what gen am I" checks. But I haven't converted the guc related bits, or the intel_engines_init also doesn't fit. So yes, it's not super clean so I can drop that bit for now. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/21] drm/i915: Make i915_check_and_clear_faults take uncore
On 06/06/2019 10:57, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-06 10:36:27)
>> From: Tvrtko Ursulin
>>
>> Continuing the conversion and elimination of implicit dev_priv.
>>
>> Signed-off-by: Tvrtko Ursulin
>> Suggested-by: Rodrigo Vivi
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.c | 2 +-
>> drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ---
>> drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
>> 4 files changed, 21 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 0e9b74f52503..3554d0dd7b1a 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private
>> *i915)
>>
>> RUNTIME_INFO(i915)->num_engines = hweight32(mask);
>>
>> - i915_check_and_clear_faults(i915);
>> + i915_check_and_clear_faults(>uncore);
>
> I am not sold on that. Especially as it is then unwrapped back to i915.
It isn't really, not on the logical level. This is the body:
void i915_check_and_clear_faults(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore_to_i915(uncore);
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
if (INTEL_GEN(i915) >= 8)
gen8_check_faults(uncore);
else if (INTEL_GEN(i915) >= 6)
gen6_check_faults(uncore);
else
return;
uncore_clear_error_registers(uncore, ALL_ENGINES);
}
So the idea being i915 is used only for "what gen am I checkes",
while the actual functionality operates on uncore.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/21] drm/i915: Make i915_clear_error_registers take uncore
On 06/06/2019 10:50, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-06-06 10:36:23)
From: Tvrtko Ursulin
The function mostly uses uncore so make the argument reflect that.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_reset.c | 8
drivers/gpu/drm/i915/gt/intel_reset.h | 5 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index a6ecfdc735c4..ca5c6dd28203 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1166,10 +1166,10 @@ static void gen8_clear_engine_error_register(struct
intel_engine_cs *engine)
GEN6_RING_FAULT_REG_POSTING_READ(engine);
}
-void i915_clear_error_registers(struct drm_i915_private *i915,
- intel_engine_mask_t engine_mask)
+void uncore_clear_error_registers(struct intel_uncore *uncore,
+ intel_engine_mask_t engine_mask)
{
- struct intel_uncore *uncore = >uncore;
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
u32 eir;
if (!IS_GEN(i915, 2))
@@ -1253,7 +1253,7 @@ void i915_handle_error(struct drm_i915_private *i915,
if (flags & I915_ERROR_CAPTURE) {
i915_capture_error_state(i915, engine_mask, msg);
- i915_clear_error_registers(i915, engine_mask);
+ uncore_clear_error_registers(>uncore, engine_mask);
}
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
b/drivers/gpu/drm/i915/gt/intel_reset.h
index 4f3c1acac1a3..2c57dc6c26f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -12,6 +12,7 @@
#include
#include "gt/intel_engine_types.h"
+#include "intel_uncore.h"
struct drm_i915_private;
struct i915_request;
@@ -25,8 +26,8 @@ void i915_handle_error(struct drm_i915_private *i915,
const char *fmt, ...);
#define I915_ERROR_CAPTURE BIT(0)
-void i915_clear_error_registers(struct drm_i915_private *i915,
- intel_engine_mask_t engine_mask);
+void uncore_clear_error_registers(struct intel_uncore *uncore,
+ intel_engine_mask_t engine_mask);
intel_uncore_*
void i915_reset(struct drm_i915_private *i915,
intel_engine_mask_t stalled_mask,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 84104e9cc507..0fe568cfabe0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2358,7 +2358,7 @@ void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv)
else
return;
- i915_clear_error_registers(dev_priv, ALL_ENGINES);
+ uncore_clear_error_registers(_priv->uncore, ALL_ENGINES);
}
And honestly I would prefer just to move i915_check_and_clear_faults if
that seems reasonable.
Move to intel_reset.c? AFAICS sounds reasonable.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/21] drm/i915: Remove impossible path from i915_gem_init_swizzling
On 06/06/2019 11:01, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-06-06 10:36:29) From: Tvrtko Ursulin Gen8+ does not have swizziling so function will exit on the top most check. At the same time convert the BUG to MISSING_CASE for a little more debug info. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8eee9ecf0adf..7512c804d4b7 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1216,10 +1216,8 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); else if (IS_GEN(dev_priv, 7)) I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); - else if (IS_GEN(dev_priv, 8)) - I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); But that is the register we would need to set if we choose to reenable swizzling for whatever mysterious reason. On Gen8 after all this time? I can drop the patch if you think that's a possibility. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Implicit dev_priv removal
== Series Details == Series: Implicit dev_priv removal URL : https://patchwork.freedesktop.org/series/61705/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Reset only affected engines when handling error capture Okay! Commit: drm/i915: Tidy engine mask types in hangcheck Okay! Commit: drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric Okay! Commit: drm/i915: Extract engine fault reset to a helper Okay! Commit: drm/i915: Make i915_clear_error_registers take uncore Okay! Commit: drm/i915: Convert some more bits to use engine mmio accessors Okay! Commit: drm/i915: Make read_subslice_reg take uncore Okay! Commit: drm/i915: Tidy intel_execlists_submission_init Okay! Commit: drm/i915: Make i915_check_and_clear_faults take uncore Okay! Commit: drm/i915: Move scheduler caps init to i915_gem_init Okay! Commit: drm/i915: Remove impossible path from i915_gem_init_swizzling Okay! Commit: drm/i915: Convert i915_gem_init_swizzling to uncore Okay! Commit: drm/i915: Convert init_unused_rings to uncore Okay! Commit: drm/i915: Convert gt workarounds to uncore Okay! Commit: drm/i915: Convert intel_mocs_init_l3cc_table to uncore Okay! Commit: drm/i915: Convert i915_ppgtt_init_hw to uncore Okay! Commit: drm/i915: Consolidate some open coded mmio rmw Okay! Commit: drm/i915: Convert i915_gem_init_hw to uncore Okay! Commit: drm/i915: Convert intel_vgt_(de)balloon to uncore -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void) Commit: drm/i915: Make GuC GGTT reservation work on ggtt -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void) Commit: drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Implicit dev_priv removal
== Series Details ==
Series: Implicit dev_priv removal
URL : https://patchwork.freedesktop.org/series/61705/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
970f22aa796e drm/i915: Reset only affected engines when handling error capture
118c531673db drm/i915: Tidy engine mask types in hangcheck
487a7e723cb2 drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible
side-effects?
#21: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:71:
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+ intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible
side-effects?
#24: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:74:
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+ intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible
side-effects?
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~clear__; \
+ __val |= set__; \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
-:27: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'clear__' may be better as
'(clear__)' to avoid precedence issues
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~clear__; \
+ __val |= set__; \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
total: 0 errors, 0 warnings, 4 checks, 52 lines checked
dcdc5de72696 drm/i915: Extract engine fault reset to a helper
b55202be923f drm/i915: Make i915_clear_error_registers take uncore
98b9f03fb517 drm/i915: Convert some more bits to use engine mmio accessors
c2931187c171 drm/i915: Make read_subslice_reg take uncore
757bf4f8daeb drm/i915: Tidy intel_execlists_submission_init
245580be209a drm/i915: Make i915_check_and_clear_faults take uncore
edcc073dabcf drm/i915: Move scheduler caps init to i915_gem_init
182392e93cd0 drm/i915: Remove impossible path from i915_gem_init_swizzling
f6f9bb0e5889 drm/i915: Convert i915_gem_init_swizzling to uncore
9d1ee9205692 drm/i915: Convert init_unused_rings to uncore
83da7c8ed5bc drm/i915: Convert gt workarounds to uncore
b320ea58c2e1 drm/i915: Convert intel_mocs_init_l3cc_table to uncore
f0e98038c584 drm/i915: Convert i915_ppgtt_init_hw to uncore
fd20c02086dd drm/i915: Consolidate some open coded mmio rmw
6e633291b272 drm/i915: Convert i915_gem_init_hw to uncore
-:126: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#126: FILE: drivers/gpu/drm/i915/i915_gem.c:1337:
+ BUG_ON(!i915->kernel_context);
total: 0 errors, 1 warnings, 0 checks, 115 lines checked
e465b03ce165 drm/i915: Convert intel_vgt_(de)balloon to uncore
1cda79f98e38 drm/i915: Make GuC GGTT reservation work on ggtt
d4566f34339d drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/21] Implicit dev_priv removal
Quoting Tvrtko Ursulin (2019-06-06 10:36:18) > From: Tvrtko Ursulin > > Mostly patches reworking the code and GEM init paths to remove some implicit > dev_priv dependencies (I915_READ/I915_WRITE), plus some small tweaks to tidy > GEM init paths to use more logical input parameters (enabled by the conversion > to uncore mmio accessors). Passing intel_uncore to non intel_uncore functions during init, I disagree with as it makes the layering violations worse for no apparent gain. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/21] drm/i915: Remove impossible path from i915_gem_init_swizzling
Quoting Tvrtko Ursulin (2019-06-06 10:36:29) > From: Tvrtko Ursulin > > Gen8+ does not have swizziling so function will exit on the top most check. > > At the same time convert the BUG to MISSING_CASE for a little more debug > info. > > Signed-off-by: Tvrtko Ursulin > --- > drivers/gpu/drm/i915/i915_gem.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 8eee9ecf0adf..7512c804d4b7 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -1216,10 +1216,8 @@ void i915_gem_init_swizzling(struct drm_i915_private > *dev_priv) > I915_WRITE(ARB_MODE, > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); > else if (IS_GEN(dev_priv, 7)) > I915_WRITE(ARB_MODE, > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); > - else if (IS_GEN(dev_priv, 8)) > - I915_WRITE(GAMTARBMODE, > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); But that is the register we would need to set if we choose to reenable swizzling for whatever mysterious reason. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/21] drm/i915: Move scheduler caps init to i915_gem_init
Quoting Tvrtko Ursulin (2019-06-06 10:36:28) > From: Tvrtko Ursulin > > This step is more about the GEM and less about the hardware so move it to > the more appropriate place. Just happens to be the wrong place. It needs to be reset after we restart the HW as the capabilities do change following wedging. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/21] drm/i915: Make i915_check_and_clear_faults take uncore
Quoting Tvrtko Ursulin (2019-06-06 10:36:27) > From: Tvrtko Ursulin > > Continuing the conversion and elimination of implicit dev_priv. > > Signed-off-by: Tvrtko Ursulin > Suggested-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 34 --- > drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- > 4 files changed, 21 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 0e9b74f52503..3554d0dd7b1a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915) > > RUNTIME_INFO(i915)->num_engines = hweight32(mask); > > - i915_check_and_clear_faults(i915); > + i915_check_and_clear_faults(>uncore); I am not sold on that. Especially as it is then unwrapped back to i915. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/21] drm/i915: Make read_subslice_reg take uncore
Quoting Tvrtko Ursulin (2019-06-06 10:36:25) > From: Tvrtko Ursulin > > The function mostly uses uncore so make it use it. > > Signed-off-by: Tvrtko Ursulin > Suggested-by: Rodrigo Vivi I'd probably pass engine and take uncore = engine->uncore. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/21] drm/i915: Tidy intel_execlists_submission_init
Quoting Tvrtko Ursulin (2019-06-06 10:36:26) > From: Tvrtko Ursulin > > Get to uncore from the engine for better logic organization and use > already available i915 everywhere. > > Signed-off-by: Tvrtko Ursulin > Suggested-by: Rodrigo Vivi Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] GEM shrinker and vm.overcommit_memory=2
In fairly recent past, it was not possible to run desktop systems using vm.overcommit_memory=2 if they used Intel graphics because without the OOM killer, the shrinker would never run. Instead, regular memory allocations would fail eventually. In addition, the i915 Mesa driver assumed malloc would never fail. So eventually, the whole desktop infrastructure would crash with a NULL pointer dereference somewhere in Mesa. Is running with vm.overcommit_memory=2 a supported configuration? I expect that vm.overcommit_memory=2 mode could be an interesting operating mode for OpenCL workloads. Thanks, Florian ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/21] drm/i915: Convert some more bits to use engine mmio accessors
Quoting Tvrtko Ursulin (2019-06-06 10:36:24)
> From: Tvrtko Ursulin
>
> Remove a couple dev_priv locals as a consequence.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 27 ++---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++--
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_guc_submission.c | 4 +--
> 5 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index fed704802c57..f27b6c002627 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2021,31 +2021,30 @@ static int intel_init_workaround_bb(struct
> intel_engine_cs *engine)
>
> static void enable_execlists(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->i915;
> -
> intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>
> - if (INTEL_GEN(dev_priv) >= 11)
> - I915_WRITE(RING_MODE_GEN7(engine),
> - _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
> + if (INTEL_GEN(engine->i915) >= 11)
> + ENGINE_WRITE(engine,
> +RING_MODE_GEN7,
> +
> _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
> else
> - I915_WRITE(RING_MODE_GEN7(engine),
> - _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
> + ENGINE_WRITE(engine,
> +RING_MODE_GEN7,
> +_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
>
> - I915_WRITE(RING_MI_MODE(engine->mmio_base),
> - _MASKED_BIT_DISABLE(STOP_RING));
> + ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>
> - I915_WRITE(RING_HWS_PGA(engine->mmio_base),
> - i915_ggtt_offset(engine->status_page.vma));
> - POSTING_READ(RING_HWS_PGA(engine->mmio_base));
> + ENGINE_WRITE(engine,
> +RING_HWS_PGA,
> +i915_ggtt_offset(engine->status_page.vma));
> + ENGINE_POSTING_READ(engine, RING_HWS_PGA);
> }
>
> static bool unexpected_starting_state(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->i915;
> bool unexpected = false;
>
> - if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
> + if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
> DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
> unexpected = true;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0fe568cfabe0..3ba970f2db28 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1713,8 +1713,9 @@ static void gen7_ppgtt_enable(struct drm_i915_private
> *dev_priv)
>
> for_each_engine(engine, dev_priv, id) {
> /* GFX_MODE is per-ring on gen7+ */
> - I915_WRITE(RING_MODE_GEN7(engine),
> - _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> + ENGINE_WRITE(engine,
> +RING_MODE_GEN7,
> +_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2f85de034d8f..193a93857d99 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1219,7 +1219,7 @@ static void error_record_engine_registers(struct
> i915_gpu_state *error,
> if (HAS_PPGTT(dev_priv)) {
> int i;
>
> - ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
> + ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
>
> if (IS_GEN(dev_priv, 6)) {
> ee->vm_info.pp_dir_base =
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1b9ae48d1abe..8a8b34a13d2e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2698,7 +2698,7 @@ enum i915_power_well_id {
>
> #define GFX_MODE _MMIO(0x2520)
> #define GFX_MODE_GEN7 _MMIO(0x229c)
> -#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
> +#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
> #define GFX_RUN_LIST_ENABLE (1 << 15)
> #define GFX_INTERRUPT_STEERING (1 << 14)
> #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index a4f98ccef0fe..89592ef778b8 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -1306,7
Re: [Intel-gfx] [PATCH 05/21] drm/i915: Make i915_clear_error_registers take uncore
Quoting Chris Wilson (2019-06-06 10:50:17) > Quoting Tvrtko Ursulin (2019-06-06 10:36:23) > > -void i915_clear_error_registers(struct drm_i915_private *i915, > > - intel_engine_mask_t engine_mask); > > +void uncore_clear_error_registers(struct intel_uncore *uncore, > > + intel_engine_mask_t engine_mask); > > intel_uncore_* It also upsets the loose rule that functions should be exported from the object_name.c -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/21] drm/i915: Make i915_clear_error_registers take uncore
Quoting Tvrtko Ursulin (2019-06-06 10:36:23)
> From: Tvrtko Ursulin
>
> The function mostly uses uncore so make the argument reflect that.
>
> Signed-off-by: Tvrtko Ursulin
> Suggested-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 8
> drivers/gpu/drm/i915/gt/intel_reset.h | 5 +++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> 3 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index a6ecfdc735c4..ca5c6dd28203 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1166,10 +1166,10 @@ static void gen8_clear_engine_error_register(struct
> intel_engine_cs *engine)
> GEN6_RING_FAULT_REG_POSTING_READ(engine);
> }
>
> -void i915_clear_error_registers(struct drm_i915_private *i915,
> - intel_engine_mask_t engine_mask)
> +void uncore_clear_error_registers(struct intel_uncore *uncore,
> + intel_engine_mask_t engine_mask)
> {
> - struct intel_uncore *uncore = >uncore;
> + struct drm_i915_private *i915 = uncore_to_i915(uncore);
> u32 eir;
>
> if (!IS_GEN(i915, 2))
> @@ -1253,7 +1253,7 @@ void i915_handle_error(struct drm_i915_private *i915,
>
> if (flags & I915_ERROR_CAPTURE) {
> i915_capture_error_state(i915, engine_mask, msg);
> - i915_clear_error_registers(i915, engine_mask);
> + uncore_clear_error_registers(>uncore, engine_mask);
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
> b/drivers/gpu/drm/i915/gt/intel_reset.h
> index 4f3c1acac1a3..2c57dc6c26f7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.h
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.h
> @@ -12,6 +12,7 @@
> #include
>
> #include "gt/intel_engine_types.h"
> +#include "intel_uncore.h"
>
> struct drm_i915_private;
> struct i915_request;
> @@ -25,8 +26,8 @@ void i915_handle_error(struct drm_i915_private *i915,
>const char *fmt, ...);
> #define I915_ERROR_CAPTURE BIT(0)
>
> -void i915_clear_error_registers(struct drm_i915_private *i915,
> - intel_engine_mask_t engine_mask);
> +void uncore_clear_error_registers(struct intel_uncore *uncore,
> + intel_engine_mask_t engine_mask);
intel_uncore_*
>
> void i915_reset(struct drm_i915_private *i915,
> intel_engine_mask_t stalled_mask,
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 84104e9cc507..0fe568cfabe0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2358,7 +2358,7 @@ void i915_check_and_clear_faults(struct
> drm_i915_private *dev_priv)
> else
> return;
>
> - i915_clear_error_registers(dev_priv, ALL_ENGINES);
> + uncore_clear_error_registers(_priv->uncore, ALL_ENGINES);
> }
And honestly I would prefer just to move i915_check_and_clear_faults if
that seems reasonable.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/21] drm/i915: Reset only affected engines when handling error capture
On 06/06/2019 10:44, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-06-06 10:36:19) From: Tvrtko Ursulin Pass down the engine mask to i915_clear_error_registers so only affected engines can be reset on the Gen6/7 path. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson The only downside is that it makes it look more designed. What do you mean? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/21] drm/i915: Extract engine fault reset to a helper
Quoting Tvrtko Ursulin (2019-06-06 10:36:22) > From: Tvrtko Ursulin > > Just tidying the flow a bit. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/21] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
Quoting Tvrtko Ursulin (2019-06-06 10:36:21) > From: Tvrtko Ursulin > > Similar to earlier conversions, eliminate the implicit dev_priv by > introducing some helpers which take the engine parameter (since the > register itself is per engine). > > Signed-off-by: Tvrtko Ursulin Only 2 (borderline 3) uses, marginal, but Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/21] drm/i915: Tidy engine mask types in hangcheck
Quoting Tvrtko Ursulin (2019-06-06 10:36:20) > From: Tvrtko Ursulin > > We can use intel_engine_mask_t to align with the rest of the codebase. > > Signed-off-by: Tvrtko Ursulin Ok, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/21] drm/i915: Reset only affected engines when handling error capture
Quoting Tvrtko Ursulin (2019-06-06 10:36:19) > From: Tvrtko Ursulin > > Pass down the engine mask to i915_clear_error_registers so only affected > engines can be reset on the Gen6/7 path. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson The only downside is that it makes it look more designed. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/21] drm/i915: Convert intel_vgt_(de)balloon to uncore
From: Tvrtko Ursulin
More removal of implicit dev_priv from using old mmio accessors.
Furthermore these calls really operate on ggtt so it logically makes sense
if they take it as parameter.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_vgpu.c| 24 ++--
drivers/gpu/drm/i915/i915_vgpu.h| 4 ++--
3 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fe9cd4ea9671..d3b3676d10f3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2914,7 +2914,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
intel_guc_reserved_gtt_size(_priv->guc));
- ret = intel_vgt_balloon(dev_priv);
+ ret = intel_vgt_balloon(ggtt);
if (ret)
return ret;
@@ -2982,7 +2982,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
intel_guc_release_ggtt_top(_priv->guc);
if (drm_mm_initialized(>vm.mm)) {
- intel_vgt_deballoon(dev_priv);
+ intel_vgt_deballoon(ggtt);
i915_address_space_fini(>vm);
}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 94d3992b599d..41ed9a3f52b4 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -117,17 +117,17 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt,
* This function is called to deallocate the ballooned-out graphic memory, when
* driver is unloaded or when ballooning fails.
*/
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
+void intel_vgt_deballoon(struct i915_ggtt *ggtt)
{
int i;
- if (!intel_vgpu_active(dev_priv))
+ if (!intel_vgpu_active(ggtt->vm.i915))
return;
DRM_DEBUG("VGT deballoon.\n");
for (i = 0; i < 4; i++)
- vgt_deballoon_space(_priv->ggtt, _info.space[i]);
+ vgt_deballoon_space(ggtt, _info.space[i]);
}
static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -195,22 +195,26 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
* Returns:
* zero on success, non-zero if configuration invalid or ballooning failed
*/
-int intel_vgt_balloon(struct drm_i915_private *dev_priv)
+int intel_vgt_balloon(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = _priv->ggtt;
+ struct intel_uncore *uncore = >vm.i915->uncore;
unsigned long ggtt_end = ggtt->vm.total;
unsigned long mappable_base, mappable_size, mappable_end;
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
- if (!intel_vgpu_active(dev_priv))
+ if (!intel_vgpu_active(ggtt->vm.i915))
return 0;
- mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
- mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
- unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
- unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
+ mappable_base =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
+ mappable_size =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
+ unmappable_base =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
+ unmappable_size =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
mappable_end = mappable_base + mappable_size;
unmappable_end = unmappable_base + unmappable_size;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index ebe1b7bced98..e918f418503f 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,7 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
}
-int intel_vgt_balloon(struct drm_i915_private *dev_priv);
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+int intel_vgt_balloon(struct i915_ggtt *ggtt);
+void intel_vgt_deballoon(struct i915_ggtt *ggtt);
#endif /* _I915_VGPU_H_ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
