Re: [Intel-gfx] [PATCH v5 01/24] drm: Include ddc adapter pointer in struct drm_connector
Hi Andrzej.
Patch looks good, but one kernel-doc detail.
On Wed, Jul 24, 2019 at 03:59:23PM +0200, Andrzej Pietrasiewicz wrote:
> Add generic code which creates symbolic links in sysfs, pointing to ddc
> interface used by a particular video output. For example:
>
> ls -l /sys/class/drm/card0-HDMI-A-1/ddc
> lrwxrwxrwx 1 root root 0 Jun 24 10:42 /sys/class/drm/card0-HDMI-A-1/ddc \
> -> ../../../../soc/1388.i2c/i2c-2
>
> This makes it easy for user to associate a display with its ddc adapter
> and use e.g. ddcutil to control the chosen monitor.
>
> This patch adds an i2c_adapter pointer to struct drm_connector. Particular
> drivers can then use it instead of using their own private instance. If a
> connector contains a ddc, then create a symbolic link in sysfs.
>
> Signed-off-by: Andrzej Pietrasiewicz
> Acked-by: Daniel Vetter
> Reviewed-by: Andrzej Hajda
> ---
> drivers/gpu/drm/drm_sysfs.c | 8
> include/drm/drm_connector.h | 11 +++
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
> index ad10810bc972..e962a9d45f7e 100644
> --- a/drivers/gpu/drm/drm_sysfs.c
> +++ b/drivers/gpu/drm/drm_sysfs.c
> @@ -14,6 +14,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -294,6 +295,9 @@ int drm_sysfs_connector_add(struct drm_connector
> *connector)
> /* Let userspace know we have a new connector */
> drm_sysfs_hotplug_event(dev);
>
> + if (connector->ddc)
> + return sysfs_create_link(&connector->kdev->kobj,
> + &connector->ddc->dev.kobj, "ddc");
> return 0;
> }
>
> @@ -301,6 +305,10 @@ void drm_sysfs_connector_remove(struct drm_connector
> *connector)
> {
> if (!connector->kdev)
> return;
> +
> + if (connector->ddc)
> + sysfs_remove_link(&connector->kdev->kobj, "ddc");
> +
> DRM_DEBUG("removing \"%s\" from sysfs\n",
> connector->name);
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 4c30d751487a..33a6fff85fdb 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -41,6 +41,7 @@ struct drm_property;
> struct drm_property_blob;
> struct drm_printer;
> struct edid;
> +struct i2c_adapter;
>
> enum drm_connector_force {
> DRM_FORCE_UNSPECIFIED,
> @@ -1311,6 +1312,16 @@ struct drm_connector {
>* [0]: progressive, [1]: interlaced
>*/
> int audio_latency[2];
> +
> + /**
> + * @ddc: associated ddc adapter.
> + * A connector usually has its associated ddc adapter. If a driver uses
> + * this field, then an appropriate symbolic link is created in connector
> + * sysfs directory to make it easy for the user to tell which i2c
> + * adapter is for a particular display.
> + */
> + struct i2c_adapter *ddc;
To help the reader could you add in the above a reference to
drm_connector_init_with_ddc() sp the reader is told how to init this
field.
Either add it in PATCH 2 - or merge patch 1 and 2.
Sam
> +
> /**
>* @null_edid_counter: track sinks that give us all zeros for the EDID.
>* Needed to workaround some HW bugs where we get all 0s
> --
> 2.17.1
___
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Re: [Intel-gfx] [PATCH v5 02/24] drm: Add drm_connector_init() variant with ddc
Hi Andrzej.
On Wed, Jul 24, 2019 at 03:59:24PM +0200, Andrzej Pietrasiewicz wrote:
> Allow passing ddc adapter pointer to the init function. Even if
> drm_connector_init() sometime in the future decides to e.g. memset() all
> connector fields to zeros, the newly added function ensures that at its
> completion the ddc member of connector is correctly set.
>
> Signed-off-by: Andrzej Pietrasiewicz
> ---
> drivers/gpu/drm/drm_connector.c | 19 +++
> include/drm/drm_connector.h | 5 +
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 068d4b05f1be..06fbfc44fb48 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -296,6 +296,25 @@ int drm_connector_init(struct drm_device *dev,
> }
> EXPORT_SYMBOL(drm_connector_init);
>
> +int drm_connector_init_with_ddc(struct drm_device *dev,
> + struct drm_connector *connector,
> + const struct drm_connector_funcs *funcs,
> + int connector_type,
> + struct i2c_adapter *ddc)
> +{
This is good, with this helper there is no longer any confusion about
ordering.
drm_connector_init_with_ddc() is part of the public interface for
drm_connector and needs kernel-doc documentation.
Sam
> + int ret;
> +
> + ret = drm_connector_init(dev, connector, funcs, connector_type);
> + if (ret)
> + return ret;
> +
> + /* provide ddc symlink in sysfs */
> + connector->ddc = ddc;
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(drm_connector_init_with_ddc);
> +
> /**
> * drm_connector_attach_edid_property - attach edid property.
> * @connector: the connector
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 33a6fff85fdb..937fda9c1374 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1410,6 +1410,11 @@ int drm_connector_init(struct drm_device *dev,
> struct drm_connector *connector,
> const struct drm_connector_funcs *funcs,
> int connector_type);
> +int drm_connector_init_with_ddc(struct drm_device *dev,
> + struct drm_connector *connector,
> + const struct drm_connector_funcs *funcs,
> + int connector_type,
> + struct i2c_adapter *ddc);
> void drm_connector_attach_edid_property(struct drm_connector *connector);
> int drm_connector_register(struct drm_connector *connector);
> void drm_connector_unregister(struct drm_connector *connector);
> --
> 2.17.1
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/3] drm/i915: Fix GuC documentation links
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Fix GuC documentation links
URL : https://patchwork.freedesktop.org/series/64237/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6551_full -> Patchwork_13751_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_13751_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13751_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_13751_full:
### IGT changes ###
Possible regressions
* igt@kms_color@pipe-a-ctm-0-5:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-glk7/igt@kms_co...@pipe-a-ctm-0-5.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-glk2/igt@kms_co...@pipe-a-ctm-0-5.html
### Piglit changes ###
Possible regressions
* spec@!opengl 1.1@copypixels-draw-sync (NEW):
- {pig-snb-2600}: NOTRUN -> [FAIL][3]
[3]: None
New tests
-
New tests have been introduced between CI_DRM_6551_full and
Patchwork_13751_full:
### New Piglit tests (1) ###
* spec@!opengl 1.1@copypixels-draw-sync:
- Statuses : 1 fail(s)
- Exec time: [11.20] s
Known issues
Here are the changes found in Patchwork_13751_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_import_export@import-close-race-flink:
- shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb7/igt@drm_import_exp...@import-close-race-flink.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-iclb7/igt@drm_import_exp...@import-close-race-flink.html
* igt@gem_ctx_isolation@vcs0-s3:
- shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([fdo#107713] /
[fdo#109100])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb7/igt@gem_ctx_isolat...@vcs0-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-iclb3/igt@gem_ctx_isolat...@vcs0-s3.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#110854])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@gem_exec_balan...@smoke.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-iclb6/igt@gem_exec_balan...@smoke.html
* igt@gem_tiled_swapping@non-threaded:
- shard-hsw: [PASS][10] -> [FAIL][11] ([fdo#108686])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-hsw4/igt@gem_tiled_swapp...@non-threaded.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-hsw7/igt@gem_tiled_swapp...@non-threaded.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([fdo#105604] /
[fdo#105763])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-kbl4/igt@kms_big...@x-tiled-32bpp-rotate-180.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-kbl6/igt@kms_big...@x-tiled-32bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([fdo#108566]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][16] -> [FAIL][17] ([fdo#105363])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-glk6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [PASS][18] -> [INCOMPLETE][19] ([fdo#103540])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-hsw8/igt@kms_f...@flip-vs-suspend.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-hsw4/igt@kms_f...@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([fdo#108566]) +7
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-apl7/igt@kms_frontbuffer_track...@fbc-suspend.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/shard-apl7/igt@kms_frontbuffer_track...@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcp
Re: [Intel-gfx] [PATCH] drm/i915/guc: init submission structures as part of guc_init
On Thu, 25 Jul 2019 19:46:55 +0200, Daniele Ceraolo Spurio wrote: guc->stage_desc_pool is required as part of the init parameters and there is no reason we have to init them after HuC. This fixes a NULL ptr dereference due to guc->stage_desc_pool not being set (no fixes tag since GuC submission can't be enabled yet). Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Chris Wilson --- Reviewed-by: Michal Wajdeczko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/uc: Don't sanitize guc_log_level modparam
On Thu, 25 Jul 2019 23:44:08 +0200, Chris Wilson wrote: Quoting Michal Wajdeczko (2019-07-25 21:51:06) We are already storing runtime value of log level in private field, so there is no need to modify modparam. There is an aspect of communicating the clamped value back to the user. Does that have any value or alternative? Actual (clamped or default) value of the GuC log level is exposed in i915_guc_log_level debugfs entry. User can modify it from there too. Michal ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
On 7/26/2019 5:54 AM, Lucas De Marchi wrote:
From: José Roberto de Souza
Tiger Lake has a new register offset for DC5 and DC6 residency counters.
v2:
- Rename registers since they are not in the CSR memory range
(requested by Anshuman)
- Fix type (requested by Matthew)
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Looks Good to me.
Reviewed-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 24787bb48c9f..6dbd85b38759 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct intel_csr *csr;
+ i915_reg_t dc5_reg, dc6_reg = {};
if (!HAS_CSR(dev_priv))
return -ENODEV;
@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void
*unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (WARN_ON(INTEL_GEN(dev_priv) > 11))
- goto out;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+ dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+ } else {
+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
+SKL_CSR_DC3_DC5_COUNT;
+ if (!IS_GEN9_LP(dev_priv))
+ dc6_reg = SKL_CSR_DC5_DC6_COUNT;
+ }
- seq_printf(m, "DC3 -> DC5 count: %d\n",
- I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
- SKL_CSR_DC3_DC5_COUNT));
- if (!IS_GEN9_LP(dev_priv))
- seq_printf(m, "DC5 -> DC6 count: %d\n",
- I915_READ(SKL_CSR_DC5_DC6_COUNT));
+ seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
+ if (dc6_reg.reg)
+ seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
out:
seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..e999ce94b45c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7268,6 +7268,8 @@ enum {
#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
+#define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
+#define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: register moves
== Series Details ==
Series: Tiger Lake: register moves
URL : https://patchwork.freedesktop.org/series/64277/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13767
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/
Known issues
Here are the changes found in Patchwork_13767 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@vgem_basic@unload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@vgem_ba...@unload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u3/igt@vgem_ba...@unload.html
Possible fixes
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_e...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u3/igt@gem_ctx_e...@basic.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [DMESG-FAIL][9] ([fdo#110899]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u3: [TIMEOUT][17] ([fdo#109673] / [fdo#111214]) ->
[TIMEOUT][18] ([fdo#111214])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@i915_module_l...@reload.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13767/fi-icl-u3/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (53 -> 46)
--
Additional (1): fi-pnv-d510
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13767
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gt: Add to timeline requires the timeline mutex
== Series Details == Series: series starting with [1/2] drm/i915/gt: Add to timeline requires the timeline mutex URL : https://patchwork.freedesktop.org/series/64227/ State : success == Summary == CI Bug Log - changes from CI_DRM_6551_full -> Patchwork_13750_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_6551_full and Patchwork_13750_full: ### New IGT tests (2) ### * igt@i915_selftest@live_gem_contexts: - Statuses : 6 pass(s) - Exec time: [5.25, 34.05] s * igt@i915_selftest@live_gt_contexts: - Statuses : 6 pass(s) - Exec time: [0.44, 2.26] s Known issues Here are the changes found in Patchwork_13750_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-iclb7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-apl6/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-apl4/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-apl3/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-apl5/igt@gem_workarou...@suspend-resume-context.html * igt@i915_suspend@fence-restore-untiled: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-kbl2/igt@i915_susp...@fence-restore-untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-kbl2/igt@i915_susp...@fence-restore-untiled.html * igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-apl3/igt@kms_draw_...@draw-method-xrgb-mmap-gtt-untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-apl5/igt@kms_draw_...@draw-method-xrgb-mmap-gtt-untiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-glk6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_plane@plane-position-covered-pipe-a-planes: - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-snb2/igt@kms_pl...@plane-position-covered-pipe-a-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-snb2/igt@kms_pl...@plane-position-covered-pipe-a-planes.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-y.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/shard-iclb7/igt@kms_psr@psr2_cursor_render.html Possible fixes
[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: MOCS table handling
== Series Details ==
Series: Tiger Lake: MOCS table handling
URL : https://patchwork.freedesktop.org/series/64275/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13766
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/
Known issues
Here are the changes found in Patchwork_13766 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2520m: [PASS][1] -> [INCOMPLETE][2] ([fdo#105411])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109635 ])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_e...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-icl-u3/igt@gem_ctx_e...@basic.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [DMESG-FAIL][7] ([fdo#110899]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][9] ([fdo#109271] / [fdo#109278]) -> [PASS][10]
+2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-icl-u4}:[FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u3: [TIMEOUT][13] ([fdo#109673] / [fdo#111214]) ->
[TIMEOUT][14] ([fdo#111214])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@i915_module_l...@reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) ->
[DMESG-FAIL][16] ([fdo#44])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13766/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899
[fdo#44]: https://bugs.freedesktop.org/show_bug.cgi?id=44
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (53 -> 44)
--
Additional (1): fi-pnv-d510
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-apl-guc fi-cfl-8109u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13766
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13766: f17795a44dfc9451d3c550ab014ffacacf8e28f7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linu
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake: MOCS table handling
== Series Details == Series: Tiger Lake: MOCS table handling URL : https://patchwork.freedesktop.org/series/64275/ State : warning == Summary == $ dim checkpatch origin/drm-tip 80a9b7285063 drm/i915/tgl: Move fault registers to their new offset 9efbb1606638 drm/i915/tgl: Define MOCS entries for Tigerlake -:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #16: terminology to what it actually is: L1 is implicitly enabled (from Daniele) total: 0 errors, 1 warnings, 0 checks, 65 lines checked 169b3fd24700 drm/i915/tgl: Tigerlake only has global MOCS registers -:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #17: v2: Move the changes to the fault registers to a separate commit - the old ones total: 0 errors, 1 warnings, 0 checks, 123 lines checked f17795a44dfc drm/i915: Move MOCS setup to intel_mocs.c ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: add workarounds
== Series Details ==
Series: Tiger Lake: add workarounds
URL : https://patchwork.freedesktop.org/series/64274/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13765
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/
Known issues
Here are the changes found in Patchwork_13765 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_client:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_client.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-dsi/igt@i915_selftest@live_client.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109483] / [fdo#109635 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [DMESG-FAIL][7] ([fdo#110899]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][9] ([fdo#109271] / [fdo#109278]) -> [PASS][10]
+2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][11] ([fdo#109380]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899
Participating hosts (53 -> 45)
--
Additional (1): fi-pnv-d510
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-cfl-8109u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13765
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13765: 8cbecca9298f056e49ab192affdce16880baf9b8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8cbecca9298f drm/i915/tgl: Implement Wa_1406941453
603fa049e1f1 drm/i915/tgl: Implement Wa_1604555607
385a308bbf68 drm/i915/tgl: Introduce initial T
[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: DKL phy PLLs
== Series Details == Series: Tiger Lake: DKL phy PLLs URL : https://patchwork.freedesktop.org/series/64273/ State : success == Summary == CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13764 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/ Known issues Here are the changes found in Patchwork_13764 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_cre...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u3/igt@gem_ctx_cre...@basic.html * igt@i915_module_load@reload-with-fault-injection: - fi-snb-2600:[PASS][3] -> [INCOMPLETE][4] ([fdo#105411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-snb-2600/igt@i915_module_l...@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-snb-2600/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108569]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u3/igt@i915_selftest@live_hangcheck.html Possible fixes * igt@gem_ctx_exec@basic: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_e...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u3/igt@gem_ctx_e...@basic.html * igt@i915_selftest@live_blt: - fi-icl-dsi: [DMESG-FAIL][9] ([fdo#110899]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-dsi/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][15] ([fdo#103167]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [SKIP][17] ([fdo#109271]) -> [PASS][18] +23 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899 Participating hosts (53 -> 45) -- Additional (1): fi-pnv-d510 Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6557 -> Patchwork_13764 CI-20190529: 20190529 CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13764: 547d8a64866c1c4f5dc2dd468a06e1acba7e56a1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 547d8a64866c drm/i915/tgl: Add support for dkl pll write 6839f83e8899 drm/i915/tgl: start
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Do not rely on for loop caching the mask
== Series Details == Series: drm/i915: Do not rely on for loop caching the mask URL : https://patchwork.freedesktop.org/series/64225/ State : success == Summary == CI Bug Log - changes from CI_DRM_6551_full -> Patchwork_13749_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13749_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-dirty-create: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@gem_ctx_isolat...@vecs0-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-iclb7/igt@gem_ctx_isolat...@vecs0-dirty-create.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#109507]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-skl5/igt@kms_f...@flip-vs-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-skl2/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-apl6/igt@kms_f...@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-apl5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-y.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#108341]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb8/igt@kms_psr@no_drrs.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-iclb6/igt@kms_psr@psr2_cursor_render.html * igt@kms_setmode@basic: - shard-apl: [PASS][21] -> [FAIL][22] ([fdo#99912]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-apl4/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-apl8/igt@kms_setm...@basic.html - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-skl8/igt@kms_setm...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-skl6/igt@kms_setm...@basic.html Possible fixes * igt@gem_eio@reset-stress: - shard-snb: [FAIL][25] ([fdo#109661]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/shard-snb7/igt@gem_...@reset-stress.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/shard-snb7/igt@gem_...@reset-stress.html * igt@gem_softpin@noreloc-s3: -
[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: interrupts
== Series Details ==
Series: Tiger Lake: interrupts
URL : https://patchwork.freedesktop.org/series/64272/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13763
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/
Known issues
Here are the changes found in Patchwork_13763 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_busy@busy-all:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_b...@busy-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-u3/igt@gem_b...@busy-all.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_addfb_basic@small-bo:
- fi-icl-dsi: [PASS][5] -> [DMESG-WARN][6] ([fdo#106107])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@kms_addfb_ba...@small-bo.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-dsi/igt@kms_addfb_ba...@small-bo.html
Possible fixes
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_e...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-u3/igt@gem_ctx_e...@basic.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [DMESG-FAIL][9] ([fdo#110899]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-icl-u4}:[FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u3: [TIMEOUT][17] ([fdo#109673] / [fdo#111214]) ->
[TIMEOUT][18] ([fdo#111214])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@i915_module_l...@reload.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13763/fi-icl-u3/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (53 -> 44)
--
Additional (1): fi-pnv-d510
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-cfl-8109u fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13763
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13763: 9a914e22b8745e91590459f767fe35
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_*
on initialization
URL : https://patchwork.freedesktop.org/series/64271/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13762
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/
Known issues
Here are the changes found in Patchwork_13762 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
Possible fixes
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_e...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/fi-icl-u3/igt@gem_ctx_e...@basic.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [DMESG-FAIL][5] ([fdo#110899]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#109485]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
- {fi-icl-u4}:[FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u3: [TIMEOUT][11] ([fdo#109673] / [fdo#111214]) ->
[TIMEOUT][12] ([fdo#111214])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/fi-icl-u3/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (53 -> 45)
--
Additional (1): fi-pnv-d510
Missing(9): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13762
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13762: db0eba333e54d2da09958333d2157d509a89ec16 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
db0eba333e54 drm/i915/tgl: update ddi/tc clock_off bits
1ef0fa9d7e98 drm/i915/tgl: select correct bit for port select
43f991ca3886 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13762/
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
== Series Details == Series: series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization URL : https://patchwork.freedesktop.org/series/64271/ State : warning == Summary == $ dim checkpatch origin/drm-tip 43f991ca3886 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization 1ef0fa9d7e98 drm/i915/tgl: select correct bit for port select db0eba333e54 drm/i915/tgl: update ddi/tc clock_off bits -:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #27: FILE: drivers/gpu/drm/i915/i915_reg.h:9745: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ + (tc_port) + 12 : \ + (tc_port) - PORT_TC4 + 21)) total: 0 errors, 0 warnings, 1 checks, 11 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Replace hangcheck by heartbeats
== Series Details == Series: drm/i915: Replace hangcheck by heartbeats URL : https://patchwork.freedesktop.org/series/64269/ State : failure == Summary == Applying: drm/i915: Replace hangcheck by heartbeats Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/Kconfig.profile Falling back to patching base and 3-way merge... Removing drivers/gpu/drm/i915/gt/intel_hangcheck.c Auto-merging drivers/gpu/drm/i915/Kconfig.profile CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/Kconfig.profile error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Replace hangcheck by heartbeats When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Reorder params in intel_uc_fw_fetch
Quoting Patchwork (2019-07-26 00:51:44) > == Series Details == > > Series: drm/i915/uc: Reorder params in intel_uc_fw_fetch > URL : https://patchwork.freedesktop.org/series/64265/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13758 > > > Summary > --- > > **SUCCESS** And with sanity confirmed, pushed. Thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/3] Tiger Lake: register moves
Patches extracted from https://patchwork.freedesktop.org/series/63670/ and rebased. Jordan Justen (1): drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register José Roberto de Souza (1): drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Michel Thierry (1): drm/i915/tgl: add support for reading the timestamp frequency drivers/gpu/drm/i915/i915_debugfs.c | 21 + drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 4 files changed, 17 insertions(+), 10 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915/tgl: add support for reading the timestamp frequency
From: Michel Thierry
There are no changes with respect to GEN11, which Paulo wrote.
This gets rid of the "Missing switch case in read_timestamp_frequency"
message at boot for Tiger Lake.
Cc: Paulo Zanoni
Cc: Lionel Landwerlin
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..a3017d16b7f3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -716,7 +716,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private
*dev_priv)
}
return freq;
- } else if (INTEL_GEN(dev_priv) <= 11) {
+ } else if (INTEL_GEN(dev_priv) <= 12) {
u32 ctc_reg = I915_READ(CTC_MODE);
u32 freq = 0;
--
2.21.0
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[Intel-gfx] [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
From: Jordan Justen
This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.
Based on the ICL patch by Paulo Zanoni and CNL patch by Nanley Chery.
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Jordan Justen
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 475ab3d4d91d..2b839acfa0f6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1776,7 +1776,7 @@ static const struct reg_whitelist {
} reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .gen_mask = INTEL_GEN_MASK(4, 11),
+ .gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
} };
--
2.21.0
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[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
From: José Roberto de Souza
Tiger Lake has a new register offset for DC5 and DC6 residency counters.
v2:
- Rename registers since they are not in the CSR memory range
(requested by Anshuman)
- Fix type (requested by Matthew)
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 24787bb48c9f..6dbd85b38759 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct intel_csr *csr;
+ i915_reg_t dc5_reg, dc6_reg = {};
if (!HAS_CSR(dev_priv))
return -ENODEV;
@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void
*unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (WARN_ON(INTEL_GEN(dev_priv) > 11))
- goto out;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+ dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+ } else {
+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
+SKL_CSR_DC3_DC5_COUNT;
+ if (!IS_GEN9_LP(dev_priv))
+ dc6_reg = SKL_CSR_DC5_DC6_COUNT;
+ }
- seq_printf(m, "DC3 -> DC5 count: %d\n",
- I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
- SKL_CSR_DC3_DC5_COUNT));
- if (!IS_GEN9_LP(dev_priv))
- seq_printf(m, "DC5 -> DC6 count: %d\n",
- I915_READ(SKL_CSR_DC5_DC6_COUNT));
+ seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
+ if (dc6_reg.reg)
+ seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
out:
seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..e999ce94b45c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7268,6 +7268,8 @@ enum {
#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
+#define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
+#define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
--
2.21.0
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Move MOCS setup to intel_mocs.c
Quoting Lucas De Marchi (2019-07-26 01:12:08)
> From: Tvrtko Ursulin
>
> Hide the details of MOCS setup from i915_gem by moving both current calls
> into one in intel_mocs_init.
>
> Cc: Stuart Summers
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Stuart Summers
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-21-lucas.demar...@intel.com
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 15 +++
> drivers/gpu/drm/i915/gt/intel_mocs.h | 3 +--
> drivers/gpu/drm/i915/i915_gem.c | 3 +--
> 3 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 9399c0ec08f1..d437d35f3347 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -411,14 +411,13 @@ void intel_mocs_init_engine(struct intel_engine_cs
> *engine)
> *
> * This function initializes the MOCS global registers.
> */
> -void intel_mocs_init_global(struct intel_gt *gt)
> +static void intel_mocs_init_global(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> struct drm_i915_mocs_table table;
> unsigned int index;
>
> - if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> - return;
> + GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
>
> if (!get_mocs_settings(gt, &table))
> return;
> @@ -587,7 +586,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
> *
> * Return: Nothing.
> */
> -void intel_mocs_init_l3cc_table(struct intel_gt *gt)
> +static void intel_mocs_init_l3cc_table(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> struct drm_i915_mocs_table table;
> @@ -665,3 +664,11 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
>
> return 0;
> }
> +
> +void intel_mocs_init(struct intel_gt *gt)
* quietly mutters intel_gt_init_mocs() (to be called from
intel_gt_init() [or better name], formerly known as i915_gem_init_hw).
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Capture vma contents outside of spinlock
== Series Details == Series: series starting with [1/5] drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64268/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13760 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13760 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13760, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13760: ### IGT changes ### Possible regressions * igt@gem_exec_create@basic: - fi-bsw-kefka: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-bsw-kefka/igt@gem_exec_cre...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-bsw-kefka/igt@gem_exec_cre...@basic.html * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html - fi-kbl-r: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html - fi-skl-6770hq: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-skl-6770hq/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-skl-6770hq/igt@gem_exec_susp...@basic-s3.html - fi-byt-n2820: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-byt-n2820/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-byt-n2820/igt@gem_exec_susp...@basic-s3.html - fi-skl-lmem:[PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-skl-lmem/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-skl-lmem/igt@gem_exec_susp...@basic-s3.html - fi-skl-6260u: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-skl-6260u/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-skl-6260u/igt@gem_exec_susp...@basic-s3.html - fi-snb-2600:[PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html - fi-whl-u: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-whl-u/igt@gem_exec_susp...@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-whl-u/igt@gem_exec_susp...@basic-s3.html - fi-ilk-650: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html - fi-elk-e7500: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-elk-e7500/igt@gem_exec_susp...@basic-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-elk-e7500/igt@gem_exec_susp...@basic-s3.html - fi-bdw-gvtdvm: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s3.html - fi-cfl-guc: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-cfl-guc/igt@gem_exec_susp...@basic-s3.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-cfl-guc/igt@gem_exec_susp...@basic-s3.html - fi-skl-iommu: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-skl-iommu/igt@gem_exec_susp...@basic-s3.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13760/fi-skl-iommu/igt@gem_exec_susp...@basic-s3.html - fi-kbl-7567u: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-ti
[Intel-gfx] [PATCH 4/4] drm/i915: Move MOCS setup to intel_mocs.c
From: Tvrtko Ursulin
Hide the details of MOCS setup from i915_gem by moving both current calls
into one in intel_mocs_init.
Cc: Stuart Summers
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-21-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 15 +++
drivers/gpu/drm/i915/gt/intel_mocs.h | 3 +--
drivers/gpu/drm/i915/i915_gem.c | 3 +--
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 9399c0ec08f1..d437d35f3347 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -411,14 +411,13 @@ void intel_mocs_init_engine(struct intel_engine_cs
*engine)
*
* This function initializes the MOCS global registers.
*/
-void intel_mocs_init_global(struct intel_gt *gt)
+static void intel_mocs_init_global(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
unsigned int index;
- if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
- return;
+ GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
if (!get_mocs_settings(gt, &table))
return;
@@ -587,7 +586,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
*
* Return: Nothing.
*/
-void intel_mocs_init_l3cc_table(struct intel_gt *gt)
+static void intel_mocs_init_l3cc_table(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
@@ -665,3 +664,11 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
return 0;
}
+
+void intel_mocs_init(struct intel_gt *gt)
+{
+ intel_mocs_init_l3cc_table(gt);
+
+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ intel_mocs_init_global(gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h
b/drivers/gpu/drm/i915/gt/intel_mocs.h
index aa3a2df07c82..2c5cbf213819 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -55,8 +55,7 @@ struct intel_engine_cs;
struct intel_gt;
int intel_rcs_context_init_mocs(struct i915_request *rq);
-void intel_mocs_init_l3cc_table(struct intel_gt *gt);
-void intel_mocs_init_global(struct intel_gt *gt);
+void intel_mocs_init(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 323218854b94..f57ce0d560dd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1252,8 +1252,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
goto out;
}
- intel_mocs_init_global(gt);
- intel_mocs_init_l3cc_table(gt);
+ intel_mocs_init(gt);
intel_engines_set_scheduler_caps(i915);
--
2.21.0
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[Intel-gfx] [PATCH 0/4] Tiger Lake: MOCS table handling
v2 of the MOCS patches originally at https://patchwork.freedesktop.org/series/63670/ handling the review comments received. This needs the accompanying IGT patches so it doesn't regress on Ice Lake: https://patchwork.freedesktop.org/series/64263/ Lucas De Marchi (1): drm/i915/tgl: Move fault registers to their new offset Michel Thierry (1): drm/i915/tgl: Tigerlake only has global MOCS registers Tomasz Lis (1): drm/i915/tgl: Define MOCS entries for Tigerlake Tvrtko Ursulin (1): drm/i915: Move MOCS setup to intel_mocs.c drivers/gpu/drm/i915/gt/intel_gt.c | 24 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 93 +++- drivers/gpu/drm/i915/gt/intel_mocs.h | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c| 18 - drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 5 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 9 files changed, 135 insertions(+), 15 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915/tgl: Tigerlake only has global MOCS registers
From: Michel Thierry
Until Icelake, each engine had its own set of 64 MOCS registers. In
order to simplify, Tigerlake moves to only 64 Global MOCS registers,
which are no longer part of the engine context. Since these registers
are now global, they also only need to be initialized once.
From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
management (5:4) fields and cannot be programmed to 'use the value from
Private PAT', because these fields are no longer part of the PPAT. Also
cacheability control (1:0) field has changed, 00 no longer means 'use
controls from page table', but uncacheable (UC).
v2: Move the changes to the fault registers to a separate commit - the old ones
overlap with the range used by the new global MOCS (requested by
Daniele)
Cc: Daniele Ceraolo Spurio
Cc: Tomasz Lis
Signed-off-by: Michel Thierry
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 47
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c| 6 ++-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
8 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index ca370c7487f9..9399c0ec08f1 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -377,6 +377,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unsigned int index;
u32 unused_value;
+ /* Platforms with global MOCS do not need per-engine initialization. */
+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ return;
+
/* Called under a blanket forcewake */
assert_forcewakes_active(uncore, FORCEWAKE_ALL);
@@ -401,6 +405,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unused_value);
}
+/**
+ * intel_mocs_init_global() - program the global mocs registers
+ * gt: pointer to struct intel_gt
+ *
+ * This function initializes the MOCS global registers.
+ */
+void intel_mocs_init_global(struct intel_gt *gt)
+{
+ struct intel_uncore *uncore = gt->uncore;
+ struct drm_i915_mocs_table table;
+ unsigned int index;
+
+ if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ return;
+
+ if (!get_mocs_settings(gt, &table))
+ return;
+
+ if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
+ return;
+
+ for (index = 0; index < table.size; index++)
+ intel_uncore_write(uncore,
+ GEN12_GLOBAL_MOCS(index),
+ table.table[index].control_value);
+
+ /*
+* Ok, now set the unused entries to uncached. These entries
+* are officially undefined and no contract for the contents
+* and settings is given for these entries.
+*
+* Entry 0 in the table is uncached - so we are just writing
+* that value to all the used entries.
+*/
+ for (; index < table.n_entries; index++)
+ intel_uncore_write(uncore,
+ GEN12_GLOBAL_MOCS(index),
+ table.table[0].control_value);
+}
+
/**
* emit_mocs_control_table() - emit the mocs control table
* @rq:Request to set up the MOCS table for.
@@ -604,6 +648,9 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
struct drm_i915_mocs_table t;
int ret;
+ if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
+ return 0;
+
if (get_mocs_settings(rq->engine->gt, &t)) {
/* Program the RCS control registers */
ret = emit_mocs_control_table(rq, &t);
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h
b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 8b9813e6f9ac..aa3a2df07c82 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -56,6 +56,7 @@ struct intel_gt;
int intel_rcs_context_init_mocs(struct i915_request *rq);
void intel_mocs_init_l3cc_table(struct intel_gt *gt);
+void intel_mocs_init_global(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59d4a1146039..a9509bdeb2fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2280,6 +2280,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
+#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
(INTEL_INFO(dev_priv)->has_global_mocs)
+
#define INTEL_PCH_DEVICE_ID_MASK
[Intel-gfx] [PATCH 1/4] drm/i915/tgl: Move fault registers to their new offset
The fault registers moved to another offset. The old location is now
taken by the global MOCS registers, to be added in a follow up change.
Based on previous patches by Michel Thierry .
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_gt.c| 24
drivers/gpu/drm/i915/i915_gpu_error.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f7e69db4019d..caa07eb20a64 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -79,7 +79,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
I915_MASTER_ERROR_INTERRUPT);
}
- if (INTEL_GEN(i915) >= 8) {
+ if (INTEL_GEN(i915) >= 12) {
+ rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
+ intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
+ } else if (INTEL_GEN(i915) >= 8) {
rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
} else if (INTEL_GEN(i915) >= 6) {
@@ -117,14 +120,27 @@ static void gen6_check_faults(struct intel_gt *gt)
static void gen8_check_faults(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
- u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
+ i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
+ u32 fault;
+
+ if (INTEL_GEN(gt->i915) >= 12) {
+ fault_reg = GEN12_RING_FAULT_REG;
+ fault_data0_reg = GEN12_FAULT_TLB_DATA0;
+ fault_data1_reg = GEN12_FAULT_TLB_DATA1;
+ } else {
+ fault_reg = GEN8_RING_FAULT_REG;
+ fault_data0_reg = GEN8_FAULT_TLB_DATA0;
+ fault_data1_reg = GEN8_FAULT_TLB_DATA1;
+ }
+ fault = intel_uncore_read(uncore, fault_reg);
if (fault & RING_FAULT_VALID) {
u32 fault_data0, fault_data1;
u64 fault_addr;
- fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
- fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
+ fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
+ fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
+
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 56dfc2650836..41a14f40a8c7 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1106,7 +1106,10 @@ static void error_record_engine_registers(struct
i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 6) {
ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
- if (INTEL_GEN(dev_priv) >= 8)
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG);
+ else if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else
ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
@@ -1497,7 +1500,12 @@ static void capture_reg_state(struct i915_gpu_state
*error)
if (IS_GEN(i915, 7))
error->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
- if (INTEL_GEN(i915) >= 8) {
+ if (INTEL_GEN(i915) >= 12) {
+ error->fault_data0 = intel_uncore_read(uncore,
+ GEN12_FAULT_TLB_DATA0);
+ error->fault_data1 = intel_uncore_read(uncore,
+ GEN12_FAULT_TLB_DATA1);
+ } else if (INTEL_GEN(i915) >= 8) {
error->fault_data0 = intel_uncore_read(uncore,
GEN8_FAULT_TLB_DATA0);
error->fault_data1 = intel_uncore_read(uncore,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..19e72f0c73d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2490,6 +2490,7 @@ enum i915_power_well_id {
#define RENDER_HWS_PGA_GEN7_MMIO(0x04080)
#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
#define GEN8_RING_FAULT_REG_MMIO(0x4094)
+#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
@@ -2633,6 +2634,8 @@ enum i915_power_well_id {
#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b1
[Intel-gfx] [PATCH 2/4] drm/i915/tgl: Define MOCS entries for Tigerlake
From: Tomasz Lis
The MOCS table is published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Two of the 3 legacy entries used for gen9 are no longer expected to work.
Although we are changing the gen11 table, those changes are supposed to
be backward compatible since we are only touching previously undefined
entries.
v2: Add the missing entries in 49-51 range and replace "HW reserved"
terminology to what it actually is: L1 is implicitly enabled (from Daniele)
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
Signed-off-by: Tomasz Lis
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 37 +---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 290a5e9b90b9..ca370c7487f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
/* (e)LLC caching options */
+/*
+ * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
+ * the same as LE_UC
+ */
#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
#define LE_1_UC_LE_CACHEABILITY(1)
#define LE_2_WT_LE_CACHEABILITY(2)
@@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
* of bspec.
*
* Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon. For the time
- * being they will be initialized to PTE.
+ * userspace is concerned and shouldn't be relied upon. For Gen < 12
+ * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
+ * PTE. We use the same value, but that actually means Uncached.
*
* The last two entries are reserved by the hardware. For ICL+ they
* should be initialized according to bspec and never used, for older
@@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry
broxton_mocs_table[] = {
};
#define GEN11_MOCS_ENTRIES \
- /* Base - Uncached (Deprecated) */ \
+ /* Gen11: Base - Uncached (Deprecated) */ \
+ /* Gen12+: Base - Error (Reserved for Non-Use) */ \
MOCS_ENTRY(I915_MOCS_UNCACHED, \
LE_1_UC | LE_TC_1_LLC, \
L3_1_UC), \
/* Base - L3 + LeCC:PAT (Deprecated) */ \
+ /* Gen12+: Base - Reserved */ \
MOCS_ENTRY(I915_MOCS_PTE, \
LE_0_PAGETABLE | LE_TC_1_LLC, \
L3_3_WB), \
@@ -233,6 +240,30 @@ static const struct drm_i915_mocs_entry
broxton_mocs_table[] = {
MOCS_ENTRY(23, \
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
L3_3_WB), \
+ /* Gen12+: Implicitly enable L1 - HDC:L1 + L3 + LLC */ \
+ MOCS_ENTRY(48, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_3_WB), \
+ /* Gen12+: Implicitly enable L1 - HDC:L1 + L3 */ \
+ MOCS_ENTRY(49, \
+ LE_1_UC | LE_TC_1_LLC, \
+ L3_3_WB), \
+ /* Gen12+: Implicitly enable L1 - HDC:L1 + LLC */ \
+ MOCS_ENTRY(50, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_1_UC), \
+ /* Gen12+: Implicitly enable L1 - HDC:L1 */ \
+ MOCS_ENTRY(51, \
+ LE_1_UC | LE_TC_1_LLC, \
+ L3_1_UC), \
+ /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
+ MOCS_ENTRY(60, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_1_UC), \
+ /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
+ MOCS_ENTRY(61, \
+ LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
+ L3_3_WB), \
/* HW Reserved - SW program but never use */ \
MOCS_ENTRY(62, \
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
--
2.21.0
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607
Quoting Lucas De Marchi (2019-07-26 01:02:25)
> From: Michel Thierry
>
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
>
> Signed-off-by: Michel Thierry
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a6eb9c6e87ec..3235ef355dfd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -572,6 +572,13 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> + u32 val;
> +
> + /* Wa_1604555607:tgl */
> + val = intel_uncore_read(engine->uncore, FF_MODE2);
> + val &= ~FF_MODE2_TDS_TIMER_MASK;
> + val |= FF_MODE2_TDS_TIMER_128;
> + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
It will do a rmw on application, so you just need
wa_write_masked_or(wal, FF_MODE2,
FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 54ea25be..fbbb89f6ca2f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7771,6 +7771,11 @@ enum {
> #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
> #define PER_PIXEL_ALPHA_BYPASS_EN(1 << 7)
>
> +#define FF_MODE2 _MMIO(0x6604)
> +#define FF_MODE2_TDS_TIMER_SHIFT (16)
> +#define FF_MODE2_TDS_TIMER_128 (4 << FF_MODE2_TDS_TIMER_SHIFT)
> +#define FF_MODE2_TDS_TIMER_MASK (0xff << FF_MODE2_TDS_TIMER_SHIFT)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-Chris
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Capture vma contents outside of spinlock
== Series Details == Series: series starting with [1/5] drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64268/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Capture vma contents outside of spinlock -O:drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) Commit: drm/i915/gt: Add to timeline requires the timeline mutex Okay! Commit: drm/i915: Unshare the idle-barrier from other kernel requests Okay! Commit: drm/i915/execlists: Force preemption + +./drivers/gpu/drm/i915/i915_utils.h:232:16: warning: expression using sizeof(void) +Error in reading or end of file. Commit: drm/i915: Replace hangcheck by heartbeats + +Error in reading or end of file. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Capture vma contents outside of spinlock (rev2)
== Series Details == Series: drm/i915: Capture vma contents outside of spinlock (rev2) URL : https://patchwork.freedesktop.org/series/64256/ State : success == Summary == CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13759 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/ Known issues Here are the changes found in Patchwork_13759 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-gtt-read: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#109483]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html Possible fixes * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-blb-e6850/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_contexts: - fi-icl-dsi: [INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-dsi/igt@i915_selftest@live_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-icl-dsi/igt@i915_selftest@live_contexts.html * igt@i915_selftest@live_hangcheck: - fi-kbl-guc: [INCOMPLETE][9] ([fdo#108744]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [SKIP][11] ([fdo#109271] / [fdo#109278]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: [FAIL][13] ([fdo#103167]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html - fi-icl-u2: [FAIL][15] ([fdo#103167]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-skl-6600u: [INCOMPLETE][17] ([fdo#104108]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@prime_vgem@basic-gtt: - fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-u3/igt@prime_v...@basic-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13759/fi-icl-u3/igt@prime_v...@basic-gtt.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 Participating hosts (52 -> 45) -- Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6555 -> Patchwork_13759 CI-20190529: 20190529 CI_DRM_6555: 6272e6f4ea0ac59d6fde2d7af908c797cc56366a @ git://anongit.f
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Capture vma contents outside of spinlock
== Series Details == Series: series starting with [1/5] drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64268/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7bdf4e249991 drm/i915: Capture vma contents outside of spinlock 4e2d37f6031f drm/i915/gt: Add to timeline requires the timeline mutex 37c72d9a4ebe drm/i915: Unshare the idle-barrier from other kernel requests -:112: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #112: new file mode 100644 -:117: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #117: FILE: drivers/gpu/drm/i915/gt/selftest_context.c:1: +/* -:118: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #118: FILE: drivers/gpu/drm/i915/gt/selftest_context.c:2: + * SPDX-License-Identifier: GPL-2.0 total: 0 errors, 3 warnings, 0 checks, 519 lines checked f74342594bf0 drm/i915/execlists: Force preemption 163441e2261a drm/i915: Replace hangcheck by heartbeats -:123: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #123: new file mode 100644 -:128: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #128: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:1: +/* -:129: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #129: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:2: + * SPDX-License-Identifier: MIT -:171: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to using 'heartbeat', this function's name, in a string #171: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:44: + "stopped heartbeat on %s", engine->name); -:230: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #230: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:1: +/* -:231: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #231: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:2: + * SPDX-License-Identifier: MIT total: 0 errors, 6 warnings, 0 checks, 551 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607
From: Michel Thierry
Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 5 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a6eb9c6e87ec..3235ef355dfd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -572,6 +572,13 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ u32 val;
+
+ /* Wa_1604555607:tgl */
+ val = intel_uncore_read(engine->uncore, FF_MODE2);
+ val &= ~FF_MODE2_TDS_TIMER_MASK;
+ val |= FF_MODE2_TDS_TIMER_128;
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 54ea25be..fbbb89f6ca2f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7771,6 +7771,11 @@ enum {
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PER_PIXEL_ALPHA_BYPASS_EN(1 << 7)
+#define FF_MODE2 _MMIO(0x6604)
+#define FF_MODE2_TDS_TIMER_SHIFT (16)
+#define FF_MODE2_TDS_TIMER_128 (4 << FF_MODE2_TDS_TIMER_SHIFT)
+#define FF_MODE2_TDS_TIMER_MASK (0xff << FF_MODE2_TDS_TIMER_SHIFT)
+
/* PCH */
#define PCH_DISPLAY_BASE 0xcu
--
2.21.0
___
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[Intel-gfx] [PATCH 0/3] Tiger Lake: add workarounds
Same patches as extracted from https://patchwork.freedesktop.org/series/63670/ and rebased. Michel Thierry (3): drm/i915/tgl: Introduce initial Tigerlake Workarounds drm/i915/tgl: Implement Wa_1604555607 drm/i915/tgl: Implement Wa_1406941453 drivers/gpu/drm/i915/gt/intel_lrc.c | 2 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 +++-- drivers/gpu/drm/i915/i915_reg.h | 11 + drivers/gpu/drm/i915/intel_pm.c | 4 +- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 5 files changed, 66 insertions(+), 5 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds
From: Michel Thierry
Inherit workarounds from previous platforms that are still valid for
Tigerlake.
WaPipelineFlushCoherentLines:tgl (changed register but has same name)
WaSendPushConstantsFromMMIO:tgl
WaAllowUMDToModifySamplerMode:tgl
WaRsForcewakeAddDelayForAck:tgl
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++--
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
5 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 884dfc1cb033..893c58df8be0 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2069,6 +2069,8 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
return 0;
switch (INTEL_GEN(engine->i915)) {
+ case 12:
+ return 0;
case 11:
return 0;
case 10:
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..a6eb9c6e87ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
}
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine, wal);
@@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
GAMT_CHKN_DISABLE_L3_COH_PIPE);
}
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1183,6 +1197,17 @@ static void icl_whitelist_build(struct intel_engine_cs
*engine)
}
}
+static void tgl_whitelist_build(struct intel_engine_cs *engine)
+{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ /* WaSendPushConstantsFromMMIO:tgl */
+ whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifySamplerMode:tgl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1190,7 +1215,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs
*engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_whitelist_build(engine);
+ else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(engine);
@@ -1240,6 +1267,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_GEN(i915, 12)) {
+ /* WaPipelineFlushCoherentLines:tgl */
+ wa_write_or(wal,
+ GEN12_L3SQCREG2,
+ GEN12_LQSC_FLUSH_COHERENT_LINES);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..54ea25be 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7729,6 +7729,9 @@ enum {
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
#define GEN8_LQSC_FLUSH_COHERENT_LINES(1 << 21)
+#define GEN12_L3SQCREG2_MMIO(0xb104)
+#define GEN12_LQSC_FLUSH_COHERENT_LINES (1 << 24)
+
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#def
[Intel-gfx] [PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453
From: Michel Thierry
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3235ef355dfd..830ccd416a29 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1279,6 +1279,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal,
GEN12_L3SQCREG2,
GEN12_LQSC_FLUSH_COHERENT_LINES);
+
+ /* Wa_1406941453:tgl */
+ wa_masked_en(wal,
+SAMPLER_MODE,
+SAMPLER_ENABLE_SMALL_PL);
}
if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbbb89f6ca2f..71efb37f54a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8965,6 +8965,9 @@ enum {
#define GEN9_DG_MIRROR_FIX_ENABLE(1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
+#define SAMPLER_MODE _MMIO(0xe18c)
+#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
+
#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
#define FLOW_CONTROL_ENABLE (1 << 15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE(1 << 8)
--
2.21.0
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[Intel-gfx] [PATCH 3/5] drm/i915/tgl: Add DKL phy pll state calculations
From: Vandita Kulkarni
Reuse the existing calculate icl_calc_mg_pll_state() function.
Since the pll variables are calculated differently for DKL phy, add
support for the same.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59 ---
1 file changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 7eefd63a8b7e..3a1348ea6714 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2625,7 +2625,8 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port
tc_port)
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
-struct intel_dpll_hw_state *state)
+struct intel_dpll_hw_state *state,
+bool is_dkl)
{
u32 dco_min_freq, dco_max_freq;
int div1_vals[] = {7, 5, 3, 2};
@@ -2647,8 +2648,13 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool
is_dp, bool use_ssc,
continue;
if (div2 >= 2) {
- a_divratio = is_dp ? 10 : 5;
- tlinedrv = 2;
+ if (is_dkl) {
+ a_divratio = 5;
+ tlinedrv = 1;
+ } else {
+ a_divratio = is_dp ? 10 : 5;
+ tlinedrv = 2;
+ }
} else {
a_divratio = 5;
tlinedrv = 0;
@@ -2698,7 +2704,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool
is_dp, bool use_ssc,
* adapted to integer-only calculation, that's why it looks so different.
*/
static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
- struct intel_dpll_hw_state *pll_state)
+ struct intel_dpll_hw_state *pll_state,
+ bool is_dkl)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
int refclk_khz = dev_priv->cdclk.hw.ref;
@@ -2715,7 +2722,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state
*crtc_state,
memset(pll_state, 0, sizeof(*pll_state));
if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
- pll_state)) {
+ pll_state, is_dkl)) {
DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
return false;
}
@@ -2723,8 +2730,11 @@ static bool icl_calc_mg_pll_state(struct
intel_crtc_state *crtc_state,
m1div = 2;
m2div_int = dco_khz / (refclk_khz * m1div);
if (m2div_int > 255) {
- m1div = 4;
- m2div_int = dco_khz / (refclk_khz * m1div);
+ if (!is_dkl) {
+ m1div = 4;
+ m2div_int = dco_khz / (refclk_khz * m1div);
+ }
+
if (m2div_int > 255) {
DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
clock);
@@ -2753,6 +2763,12 @@ static bool icl_calc_mg_pll_state(struct
intel_crtc_state *crtc_state,
iref_trim = 28;
iref_pulse_w = 1;
break;
+
+ /*
+* TODO: spec adds a case for ndiv = 4 when refclk > 80MHz,
+* however this doesn't seem possible from the input.
+* See Issue 17526.
+*/
default:
MISSING_CASE(refclk_khz);
return false;
@@ -2805,7 +2821,31 @@ static bool icl_calc_mg_pll_state(struct
intel_crtc_state *crtc_state,
ssc_steplog = 4;
/* write pll_state calculations */
- {
+ if (is_dkl) {
+ pll_state->mg_pll_div0 =
+ DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
+ DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
+ DKL_PLL_DIV0_FBPREDIV(m1div) |
+ DKL_PLL_DIV0_FBDIV_INT(m2div_int);
+
+ pll_state->mg_pll_div1 =
+ DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
+ DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
+
+ pll_state->mg_pll_ssc =
+ DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
+ DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
+ DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
+ (use_ssc ? DKL_PLL_SSC_EN : 0);
+
+ pll_state->mg_pll_tdc_coldst
[Intel-gfx] [PATCH 1/5] drm/i915/tgl: Add DKL phy pll registers
From: Vandita Kulkarni
These are the registers needed to program Dekel PHY. Some register
definitions reuse the MG PHY definitions. Add a comment on those so we
don't need to duplicate the functions for programming them.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 94 +
1 file changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..0ea556abee1a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9976,6 +9976,100 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PLL_DIV0 0x200
+#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
+#define DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16)
+#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
+#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << 8)
+#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << 8)
+#define DKL_PLL_DIV0_FBDIV_INT(x)((x) << 0)
+#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
+#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+
+#define _DKL_PLL_DIV1 0x204
+#define DKL_PLL_DIV1_IREF_TRIM(x)((x) << 16)
+#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
+#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV1)
+
+#define _DKL_PLL_SSC 0x210
+#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
+#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
+#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
+#define DKL_PLL_SSC_STEP_LEN_MASK(0xFF << 16)
+#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
+#define DKL_PLL_SSC_STEP_NUM_MASK(0x7 << 11)
+#define DKL_PLL_SSC_EN (1 << 9)
+#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_SSC)
+
+#define _DKL_PLL_BIAS 0x214
+#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
+#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << 8)
+#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0xFF << 8)
+#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_BIAS)
+
+#define _DKL_PLL_TDC_COLDST_BIAS 0x218
+#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
+#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
+#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
+#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
+#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
+_DKL_PHY1_BASE, \
+_DKL_PHY2_BASE) + \
+_DKL_PLL_TDC_COLDST_BIAS)
+
+#define _DKL_REFCLKIN_CTL 0x12C
+/* Bits are the same as MG_REFCLKIN_CTL */
+#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_REFCLKIN_CTL)
+
+#define _DKL_CLKTOP2_HSCLKCTL 0xD4
+/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
+#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP2_HSCLKCTL)
+
+#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
+/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
+#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
+
[Intel-gfx] [PATCH 0/5] Tiger Lake: DKL phy PLLs
Mostly the same patches as https://patchwork.freedesktop.org/series/63670/. Rebased. Lucas De Marchi (2): drm/i915/tgl: re-indent code to prepare for DKL changes drm/i915/tgl: start adding the DKL PLLs to use on TC ports Vandita Kulkarni (3): drm/i915/tgl: Add DKL phy pll registers drm/i915/tgl: Add DKL phy pll state calculations drm/i915/tgl: Add support for dkl pll write drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 335 ++ drivers/gpu/drm/i915/i915_reg.h | 94 + 2 files changed, 368 insertions(+), 61 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/tgl: start adding the DKL PLLs to use on TC ports
The disable function can be the same as for MG phy since the same
registers are used. The others are different as registers change -
prepare for that using an empty dkl_pll_write() to be implemented later.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 98 ++-
1 file changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 3a1348ea6714..049b68e0c61c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3158,6 +3158,60 @@ static bool mg_pll_get_hw_state(struct drm_i915_private
*dev_priv,
return ret;
}
+static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll,
+struct intel_dpll_hw_state *hw_state)
+{
+ const enum intel_dpll_id id = pll->info->id;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+ intel_wakeref_t wakeref;
+ bool ret = false;
+ u32 val;
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv,
+POWER_DOMAIN_DISPLAY_CORE);
+ if (!wakeref)
+ return false;
+
+ val = I915_READ(MG_PLL_ENABLE(tc_port));
+ if (!(val & PLL_ENABLE))
+ goto out;
+
+ /*
+* All registers read here have the same HIP_INDEX_REG even though
+* they are on different building blocks
+*/
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ hw_state->mg_refclkin_ctl = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+
+ hw_state->mg_clktop2_hsclkctl =
+ I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ hw_state->mg_clktop2_hsclkctl &=
+ MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
+
+ hw_state->mg_clktop2_coreclkctl1 =
+ I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ hw_state->mg_clktop2_coreclkctl1 &=
+ MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
+ hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port));
+ hw_state->mg_pll_ssc = I915_READ(DKL_PLL_SSC(tc_port));
+ hw_state->mg_pll_bias = I915_READ(DKL_PLL_BIAS(tc_port));
+ hw_state->mg_pll_tdc_coldst_bias =
+ I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+
+ ret = true;
+out:
+ intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
+ return ret;
+}
+
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state,
@@ -3292,6 +3346,12 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
}
+static void dkl_pll_write(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /* TODO */
+}
+
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
@@ -3399,6 +3459,31 @@ static void mg_pll_enable(struct drm_i915_private
*dev_priv,
/* DVFS post sequence would be here. See the comment above. */
}
+static void dkl_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /*
+* From spec: MG register instances are being used for TypeC in
general. The
+* same MG register instances should be programmed for Dekel PLLs as
well
+*/
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_power_enable(dev_priv, pll, enable_reg);
+
+ dkl_pll_write(dev_priv, pll);
+
+ /*
+* DVFS pre sequence would be here, but in our driver the cdclk code
+* paths should already be setting the appropriate voltage, hence we do
+* nothing here.
+*/
+
+ icl_pll_enable(dev_priv, pll, enable_reg);
+
+ /* DVFS post sequence would be here. See the comment above. */
+}
+
static void icl_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
@@ -3543,11 +3628,22 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
+ .enable = dkl_pll_enable,
+ .disable = mg_pll_disable,
+ .get_hw_s
[Intel-gfx] [PATCH 2/5] drm/i915/tgl: re-indent code to prepare for DKL changes
The final save operation into pll_state of the calculations done will
be different for DKL PHY. Prepare for that by reindenting code so it's
easier to check for correctness. This one has no change in behavior.
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Atwood
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-10-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 119 ++
1 file changed, 66 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f9bdf8514a53..7eefd63a8b7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2804,60 +2804,73 @@ static bool icl_calc_mg_pll_state(struct
intel_crtc_state *crtc_state,
}
ssc_steplog = 4;
- pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
- MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
- MG_PLL_DIV0_FBDIV_INT(m2div_int);
-
- pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
-MG_PLL_DIV1_DITHER_DIV_2 |
-MG_PLL_DIV1_NDIVRATIO(1) |
-MG_PLL_DIV1_FBPREDIV(m1div);
-
- pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
- MG_PLL_LF_AFCCNTSEL_512 |
- MG_PLL_LF_GAINCTRL(1) |
- MG_PLL_LF_INT_COEFF(int_coeff) |
- MG_PLL_LF_PROP_COEFF(prop_coeff);
-
- pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
- MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
- MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
- MG_PLL_FRAC_LOCK_DCODITHEREN |
- MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
- if (use_ssc || m2div_rem > 0)
- pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
-
- pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
- MG_PLL_SSC_TYPE(2) |
- MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
- MG_PLL_SSC_STEPNUM(ssc_steplog) |
- MG_PLL_SSC_FLLEN |
- MG_PLL_SSC_STEPSIZE(ssc_stepsize);
-
- pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
- MG_PLL_TDC_COLDST_IREFINT_EN |
-
MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
- MG_PLL_TDC_TDCOVCCORR_EN |
- MG_PLL_TDC_TDCSEL(3);
-
- pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
-MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
-MG_PLL_BIAS_BIAS_BONUS(10) |
-MG_PLL_BIAS_BIASCAL_EN |
-MG_PLL_BIAS_CTRIM(12) |
-MG_PLL_BIAS_VREF_RDAC(4) |
-MG_PLL_BIAS_IREFTRIM(iref_trim);
-
- if (refclk_khz == 38400) {
- pll_state->mg_pll_tdc_coldst_bias_mask =
MG_PLL_TDC_COLDST_COLDSTART;
- pll_state->mg_pll_bias_mask = 0;
- } else {
- pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
- pll_state->mg_pll_bias_mask = -1U;
- }
+ /* write pll_state calculations */
+ {
+ pll_state->mg_pll_div0 =
+ (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
+ MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
+ MG_PLL_DIV0_FBDIV_INT(m2div_int);
+
+ pll_state->mg_pll_div1 =
+ MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
+ MG_PLL_DIV1_DITHER_DIV_2 |
+ MG_PLL_DIV1_NDIVRATIO(1) |
+ MG_PLL_DIV1_FBPREDIV(m1div);
+
+ pll_state->mg_pll_lf =
+ MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
+ MG_PLL_LF_AFCCNTSEL_512 |
+ MG_PLL_LF_GAINCTRL(1) |
+ MG_PLL_LF_INT_COEFF(int_coeff) |
+ MG_PLL_LF_PROP_COEFF(prop_coeff);
+
+ pll_state->mg_pll_frac_lock =
+ MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
+ MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
+ MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
+ MG_PLL_FRAC_LOCK_DCODITHEREN |
+ MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
+ if (use_ssc || m2div_rem > 0)
+ pll_state->mg_pll_frac_lock |=
+
[Intel-gfx] [PATCH 5/5] drm/i915/tgl: Add support for dkl pll write
From: Vandita Kulkarni
Add a new function to write to dkl phy pll registers. As per the
spec all the registers are read modify write.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 049b68e0c61c..5606a83326e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3349,7 +3349,70 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
static void dkl_pll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- /* TODO */
+ struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
+ u32 val;
+
+ /*
+* All registers programmed here have the same HIP_INDEX_REG even
+* though on different building block
+*/
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ /* All the registers are RMW */
+ val = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+ val |= hw_state->mg_refclkin_ctl;
+ I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+ val |= hw_state->mg_clktop2_coreclkctl1;
+ I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+ val |= hw_state->mg_clktop2_hsclkctl;
+ I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV0(tc_port));
+ val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK |
+ DKL_PLL_DIV0_PROP_COEFF_MASK |
+ DKL_PLL_DIV0_FBPREDIV_MASK |
+ DKL_PLL_DIV0_FBDIV_INT_MASK);
+ val |= hw_state->mg_pll_div0;
+ I915_WRITE(DKL_PLL_DIV0(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV1(tc_port));
+ val = ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
+ DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
+ val |= hw_state->mg_pll_div1;
+ I915_WRITE(DKL_PLL_DIV1(tc_port), val);
+
+ val = I915_READ(DKL_PLL_SSC(tc_port));
+ val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+ DKL_PLL_SSC_STEP_LEN_MASK |
+ DKL_PLL_SSC_STEP_NUM_MASK |
+ DKL_PLL_SSC_EN);
+ val |= hw_state->mg_pll_ssc;
+ I915_WRITE(DKL_PLL_SSC(tc_port), val);
+
+ val = I915_READ(DKL_PLL_BIAS(tc_port));
+ val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
+ DKL_PLL_BIAS_FBDIV_FRAC_MASK);
+ val |= hw_state->mg_pll_bias;
+ I915_WRITE(DKL_PLL_BIAS(tc_port), val);
+
+ val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
+ DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
+ val |= hw_state->mg_pll_tdc_coldst_bias;
+ I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+
+ POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
}
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
--
2.21.0
___
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Re: [Intel-gfx] [PATCH] drm/i915: Replace hangcheck by heartbeats
Quoting Bloomfield, Jon (2019-07-26 00:41:49) > > -Original Message- > > From: Chris Wilson > > Sent: Thursday, July 25, 2019 4:28 PM > > To: Bloomfield, Jon ; intel- > > g...@lists.freedesktop.org > > Cc: Joonas Lahtinen ; Ursulin, Tvrtko > > > > Subject: RE: [PATCH] drm/i915: Replace hangcheck by heartbeats > > > > Quoting Bloomfield, Jon (2019-07-26 00:21:47) > > > > -Original Message- > > > > From: Chris Wilson > > > > Sent: Thursday, July 25, 2019 4:17 PM > > > > To: intel-gfx@lists.freedesktop.org > > > > Cc: Chris Wilson ; Joonas Lahtinen > > > > ; Ursulin, Tvrtko > > ; > > > > Bloomfield, Jon > > > > Subject: [PATCH] drm/i915: Replace hangcheck by heartbeats > > > > > > > > Replace sampling the engine state every so often with a periodic > > > > heartbeat request to measure the health of an engine. This is coupled > > > > with the forced-preemption to allow long running requests to survive so > > > > long as they do not block other users. > > > > > > Can you explain why we would need this at all if we have > > > forced-preemption? > > > Forced preemption guarantees that an engine cannot interfere with the > > timely > > > execution of other contexts. If it hangs, but nothing else wants to use > > > the > > engine > > > then do we care? > > > > We may not have something else waiting to use the engine, but we may > > have users waiting for the response where we need to detect the GPU hang > > to prevent an infinite wait / stuck processes and infinite power drain. > > I'm not sure I buy that logic. Being able to pre-empt doesn't imply it will > ever end. As written a context can sit forever, apparently making progress > but never actually returning a response to the user. If the user isn't happy > with the progress they will kill the process. So we haven't solved the > user responsiveness here. All we've done is eliminated the potential to > run one class of otherwise valid workload. Indeed, one of the conditions I have in mind for endless is rlimits. The user + admin should be able to specify that a context not exceed so much runtime, and if we ever get a scheduler, we can write that as a budget (along with deadlines). > Same argument goes for power. Just because it yields when other contexts > want to run doesn't mean it won't consume lots of power indefinitely. I can > equally write a CPU program to burn lots of power, forever, and it won't get > nuked. I agree, and continue to dislike letting hogs have free reign. > TDR made sense when it was the only way to ensure contexts could always > make forward progress. But force-preemption does everything we need to > ensure that as far as I can tell. No. Force-preemption (preemption-by-reset) is arbitrarily shooting mostly innocent contexts, that had the misfortune to not yield quick enough. It is data loss and a dos (given enough concentration could probably be used by third parties to shoot down completely innocent clients), and so should be used as a last resort shotgun and not be confused as being a scalpel. And given our history and current situation, resets are still a liability. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Reorder params in intel_uc_fw_fetch
== Series Details ==
Series: drm/i915/uc: Reorder params in intel_uc_fw_fetch
URL : https://patchwork.freedesktop.org/series/64265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13758
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/
Known issues
Here are the changes found in Patchwork_13758 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][1] ([fdo#107718]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2520m: [INCOMPLETE][3] ([fdo#105411]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_selftest@live_contexts:
- fi-icl-dsi: [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-dsi/igt@i915_selftest@live_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-icl-dsi/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][7] ([fdo#108744]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][9] ([fdo#109380]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
- {fi-icl-u4}:[FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6600u: [INCOMPLETE][17] ([fdo#104108]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-gtt:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6555/fi-icl-u3/igt@prime_v...@basic-gtt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13758/fi-icl-u3/igt@prime_v...@basic-gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (52 -> 45)
--
Additional (1): fi-cfl-8109u
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-
[Intel-gfx] [PATCH 3/3] drm/i915/tgl: handle DP aux interrupts
For Tiger Lake the DE Port Interrupt Definition bits changed, so use the
new bit definitions.
Cc: Jose Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-7-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 16 +++-
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e43582be24e6..fbe13bacd5b7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2951,19 +2951,25 @@ static void gen11_hpd_irq_handler(struct
drm_i915_private *dev_priv, u32 iir)
static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
- u32 mask = GEN8_AUX_CHANNEL_A;
+ u32 mask;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ /* TODO: Add AUX entries for USBC */
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB |
+ TGL_DE_PORT_AUX_DDIC;
+ mask = GEN8_AUX_CHANNEL_A;
if (INTEL_GEN(dev_priv) >= 9)
mask |= GEN9_AUX_CHANNEL_B |
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_CNL_WITH_PORT_F(dev_priv))
+ if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
mask |= CNL_AUX_CHANNEL_F;
- if (INTEL_GEN(dev_priv) >= 11)
- mask |= ICL_AUX_CHANNEL_E |
- CNL_AUX_CHANNEL_F;
+ if (IS_GEN(dev_priv, 11))
+ mask |= ICL_AUX_CHANNEL_E;
return mask;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cf1d3a2f17a9..7126e3466b58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7418,6 +7418,9 @@ enum {
#define GEN8_PORT_DP_A_HOTPLUG(1 << 3)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A(1 << 0)
+#define TGL_DE_PORT_AUX_DDIC (1 << 2)
+#define TGL_DE_PORT_AUX_DDIB (1 << 1)
+#define TGL_DE_PORT_AUX_DDIA (1 << 0)
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
--
2.21.0
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[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Update north display hotplug detection to TGL connections
From: José Roberto de Souza
TGL has 3 combophys and 6 TC/TBT ports, so it has 2 more TC/TBT ports
than ICL and the PORT_C on TGL is a combophy.
So here adding a new hpd north table and function to detect long
pulse for TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-6-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 51 +
drivers/gpu/drm/i915/i915_reg.h | 12 ++--
2 files changed, 56 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 34527cdd9388..e43582be24e6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -58,6 +58,8 @@
* and related files, but that will be described in separate chapters.
*/
+typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+
static const u32 hpd_ilk[HPD_NUM_PINS] = {
[HPD_PORT_A] = DE_DP_A_HOTPLUG,
};
@@ -135,6 +137,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
[HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
};
+static const u32 hpd_gen12[HPD_NUM_PINS] = {
+ [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
+ [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
+ [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
+ [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
+ [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
+ [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG
+};
+
static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
[HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
@@ -1694,6 +1705,26 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin
pin, u32 val)
}
}
+static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_D:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+ case HPD_PORT_E:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+ case HPD_PORT_F:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+ case HPD_PORT_G:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+ case HPD_PORT_H:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+ case HPD_PORT_I:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+ default:
+ return false;
+ }
+}
+
static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -2881,6 +2912,16 @@ static void gen11_hpd_irq_handler(struct
drm_i915_private *dev_priv, u32 iir)
u32 pin_mask = 0, long_mask = 0;
u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
+ long_pulse_detect_func long_pulse_detect;
+ const u32 *hpd;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ long_pulse_detect = gen12_port_hotplug_long_detect;
+ hpd = hpd_gen12;
+ } else {
+ long_pulse_detect = gen11_port_hotplug_long_detect;
+ hpd = hpd_gen11;
+ }
if (trigger_tc) {
u32 dig_hotplug_reg;
@@ -2889,8 +2930,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private
*dev_priv, u32 iir)
I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
- dig_hotplug_reg, hpd_gen11,
- gen11_port_hotplug_long_detect);
+ dig_hotplug_reg, hpd, long_pulse_detect);
}
if (trigger_tbt) {
@@ -2900,8 +2940,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private
*dev_priv, u32 iir)
I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
- dig_hotplug_reg, hpd_gen11,
- gen11_port_hotplug_long_detect);
+ dig_hotplug_reg, hpd, long_pulse_detect);
}
if (pin_mask)
@@ -3928,9 +3967,11 @@ static void gen11_hpd_detection_setup(struct
drm_i915_private *dev_priv)
static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
+ const u32 *hpd;
u32 val;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
+ hpd = INTEL_GEN(dev_priv) >= 12 ? hpd_gen12 : hpd_gen11;
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd);
hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
val = I915_READ(GEN11_DE_HPD_IMR);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c5
[Intel-gfx] [PATCH 0/3] Tiger Lake: interrupts
North and south interrupts. Updated version of the patches extracted from https://patchwork.freedesktop.org/series/63670/ José Roberto de Souza (1): drm/i915/tgl: Update north display hotplug detection to TGL connections Lucas De Marchi (2): drm/i915/tgl: Add hpd interrupt handling drm/i915/tgl: handle DP aux interrupts drivers/gpu/drm/i915/display/intel_hotplug.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_irq.c | 195 +-- drivers/gpu/drm/i915/i915_reg.h | 43 +++- 4 files changed, 224 insertions(+), 24 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Add hpd interrupt handling
Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
is refactored to be shared with TGP.
While we increase the number of pins, add a BUILD_BUG_ON() to avoid
going over the number of bits allowed.
v2: use BITS_PER_TYPE and correct type for BUILD_BUG_ON() check
(requested by Ville)
Cc: Ville Syrjälä
Cc: Jose Souza
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_irq.c | 128 +--
drivers/gpu/drm/i915/i915_reg.h | 28 +++-
4 files changed, 154 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 342587d91d57..c844ae4480af 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private
*dev_priv,
if (IS_CNL_WITH_PORT_F(dev_priv))
return HPD_PORT_E;
return HPD_PORT_F;
+ case PORT_G:
+ return HPD_PORT_G;
+ case PORT_H:
+ return HPD_PORT_H;
+ case PORT_I:
+ return HPD_PORT_I;
default:
MISSING_CASE(port);
return HPD_NONE;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59d4a1146039..a2e6b495f033 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -153,6 +153,10 @@ enum hpd_pin {
HPD_PORT_D,
HPD_PORT_E,
HPD_PORT_F,
+ HPD_PORT_G,
+ HPD_PORT_H,
+ HPD_PORT_I,
+
HPD_NUM_PINS
};
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a17d4fd17962..34527cdd9388 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -150,6 +150,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
[HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
};
+static const u32 hpd_tgp[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
+ [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
+ [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
+ [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
+ [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
+ [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
+ [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
+ [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
+ [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
+};
+
static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier)
{
@@ -1724,6 +1736,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin
pin, u32 val)
}
}
+static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return val & ICP_DDIA_HPD_LONG_DETECT;
+ case HPD_PORT_B:
+ return val & ICP_DDIB_HPD_LONG_DETECT;
+ case HPD_PORT_C:
+ return val & TGP_DDIC_HPD_LONG_DETECT;
+ default:
+ return false;
+ }
+}
+
+static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_D:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+ case HPD_PORT_E:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+ case HPD_PORT_F:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+ case HPD_PORT_G:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+ case HPD_PORT_H:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+ case HPD_PORT_I:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+ default:
+ return false;
+ }
+}
+
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -1803,6 +1849,8 @@ static void intel_get_hpd_pins(struct drm_i915_private
*dev_priv,
{
enum hpd_pin pin;
+ BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
+
for_each_hpd_pin(pin) {
if ((hpd[pin] & hotplug_trigger) == 0)
continue;
@@ -2561,6 +2609,43 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir,
gmbus_irq_handler(dev_priv);
}
+static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+{
+ u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
+ u32 pin_mask = 0, long_mask = 0;
+
+ if (ddi_hotplug_trigger) {
+ u32 dig_hotplug_reg;
+
+ dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
+ I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
+
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ ddi_hotplug_trigg
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Capture vma contents outside of spinlock (rev2)
== Series Details == Series: drm/i915: Capture vma contents outside of spinlock (rev2) URL : https://patchwork.freedesktop.org/series/64256/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Capture vma contents outside of spinlock -O:drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
According to the spec when initializing the display in TGL we should not
set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the
power well hooks from ICL so only set this register on gen < 12.
v2: Generalize check for gen 12 (suggested by José)
v3: Rebase after enum phy introduction
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Reviewed-by: Matt Atwood
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-2-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 93a148684c53..dd2a50b8ba0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
- val = I915_READ(ICL_PORT_CL_DW12(phy));
- I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
+ if (INTEL_GEN(dev_priv) < 12) {
+ val = I915_READ(ICL_PORT_CL_DW12(phy));
+ I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
+ }
hsw_wait_for_power_well_enable(dev_priv, power_well);
@@ -487,8 +489,10 @@ icl_combo_phy_aux_power_well_disable(struct
drm_i915_private *dev_priv,
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
- val = I915_READ(ICL_PORT_CL_DW12(phy));
- I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
+ if (INTEL_GEN(dev_priv) < 12) {
+ val = I915_READ(ICL_PORT_CL_DW12(phy));
+ I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
+ }
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
--
2.21.0
___
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[Intel-gfx] [CI 3/3] drm/i915/tgl: update ddi/tc clock_off bits
From: Mahesh Kumar
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Cc: Matt Roper
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Reviewed-by: Matt Atwood
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-4-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3035a48a2527..d2b76121d863 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9742,8 +9742,9 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << _PICK(phy, 10, 11, 24))
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
- 21 : (tc_port) + 12))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - PORT_TC4 +
21))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
--
2.21.0
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Re: [Intel-gfx] [PATCH] drm/i915: Replace hangcheck by heartbeats
> -Original Message- > From: Chris Wilson > Sent: Thursday, July 25, 2019 4:28 PM > To: Bloomfield, Jon ; intel- > g...@lists.freedesktop.org > Cc: Joonas Lahtinen ; Ursulin, Tvrtko > > Subject: RE: [PATCH] drm/i915: Replace hangcheck by heartbeats > > Quoting Bloomfield, Jon (2019-07-26 00:21:47) > > > -Original Message- > > > From: Chris Wilson > > > Sent: Thursday, July 25, 2019 4:17 PM > > > To: intel-gfx@lists.freedesktop.org > > > Cc: Chris Wilson ; Joonas Lahtinen > > > ; Ursulin, Tvrtko > ; > > > Bloomfield, Jon > > > Subject: [PATCH] drm/i915: Replace hangcheck by heartbeats > > > > > > Replace sampling the engine state every so often with a periodic > > > heartbeat request to measure the health of an engine. This is coupled > > > with the forced-preemption to allow long running requests to survive so > > > long as they do not block other users. > > > > Can you explain why we would need this at all if we have forced-preemption? > > Forced preemption guarantees that an engine cannot interfere with the > timely > > execution of other contexts. If it hangs, but nothing else wants to use the > engine > > then do we care? > > We may not have something else waiting to use the engine, but we may > have users waiting for the response where we need to detect the GPU hang > to prevent an infinite wait / stuck processes and infinite power drain. I'm not sure I buy that logic. Being able to pre-empt doesn't imply it will ever end. As written a context can sit forever, apparently making progress but never actually returning a response to the user. If the user isn't happy with the progress they will kill the process. So we haven't solved the user responsiveness here. All we've done is eliminated the potential to run one class of otherwise valid workload. Same argument goes for power. Just because it yields when other contexts want to run doesn't mean it won't consume lots of power indefinitely. I can equally write a CPU program to burn lots of power, forever, and it won't get nuked. TDR made sense when it was the only way to ensure contexts could always make forward progress. But force-preemption does everything we need to ensure that as far as I can tell. > > There is also the secondary task of flushing idle barriers. > > > Power, obviously. But I'm not everything can be pre-empted. If a compute > > context is running on an engine, and no other contexts require that engine, > > then is it right to nuke it just because it's busy in a long running > > thread? > > Yes. Unless you ask that we implement GPU-isolation where not even the > kernel is allowed to use a particular set of engines. > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/3] drm/i915/tgl: select correct bit for port select
From: Mahesh Kumar
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
v2 (Lucas):
- Nuke TRANS_DDI_PORT_NONE since it's 0: we are already clearing
{TGL_,}TRANS_DDI_PORT_MASK (suggested by Ville)
- Also cover haswell_get_ddi_port_state() in intel_display.c that was
missing
- Define macros using the _SHIFT macros so we don't lose other users
Cc: Ville Syrjälä
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Reviewed-by: Matt Atwood
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-3-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++-
drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
drivers/gpu/drm/i915/i915_reg.h | 11 +++--
3 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 18bc0f2690c9..c6f38c7b397d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1773,7 +1773,10 @@ void intel_ddi_enable_transcoder_func(const struct
intel_crtc_state *crtc_state)
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
- temp |= TRANS_DDI_SELECT_PORT(port);
+ if (INTEL_GEN(dev_priv) >= 12)
+ temp |= TGL_TRANS_DDI_SELECT_PORT(port);
+ else
+ temp |= TRANS_DDI_SELECT_PORT(port);
switch (crtc_state->pipe_bpp) {
case 18:
@@ -1853,8 +1856,13 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
u32 val = I915_READ(reg);
- val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
- val |= TRANS_DDI_PORT_NONE;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
+TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ } else {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
+TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ }
I915_WRITE(reg, val);
if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2006,10 +2014,19 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
mst_pipe_mask = 0;
for_each_pipe(dev_priv, p) {
enum transcoder cpu_transcoder = (enum transcoder)p;
+ unsigned int port_mask, ddi_select;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ port_mask = TGL_TRANS_DDI_PORT_MASK;
+ ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
+ } else {
+ port_mask = TRANS_DDI_PORT_MASK;
+ ddi_select = TRANS_DDI_SELECT_PORT(port);
+ }
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
+ if ((tmp & port_mask) != ddi_select)
continue;
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2126,9 +2143,14 @@ void intel_ddi_enable_pipe_clock(const struct
intel_crtc_state *crtc_state)
enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_PORT(port));
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_PORT(port));
+ }
}
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2136,9 +2158,14 @@ void intel_ddi_disable_pipe_clock(const struct
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_DISABLED);
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_DISABLED);
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_DISABLED);
+ }
}
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
di
Re: [Intel-gfx] [PATCH] drm/i915: Replace hangcheck by heartbeats
Quoting Bloomfield, Jon (2019-07-26 00:21:47) > > -Original Message- > > From: Chris Wilson > > Sent: Thursday, July 25, 2019 4:17 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: Chris Wilson ; Joonas Lahtinen > > ; Ursulin, Tvrtko > > ; > > Bloomfield, Jon > > Subject: [PATCH] drm/i915: Replace hangcheck by heartbeats > > > > Replace sampling the engine state every so often with a periodic > > heartbeat request to measure the health of an engine. This is coupled > > with the forced-preemption to allow long running requests to survive so > > long as they do not block other users. > > Can you explain why we would need this at all if we have forced-preemption? > Forced preemption guarantees that an engine cannot interfere with the timely > execution of other contexts. If it hangs, but nothing else wants to use the > engine > then do we care? We may not have something else waiting to use the engine, but we may have users waiting for the response where we need to detect the GPU hang to prevent an infinite wait / stuck processes and infinite power drain. There is also the secondary task of flushing idle barriers. > Power, obviously. But I'm not everything can be pre-empted. If a compute > context is running on an engine, and no other contexts require that engine, > then is it right to nuke it just because it's busy in a long running thread? Yes. Unless you ask that we implement GPU-isolation where not even the kernel is allowed to use a particular set of engines. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Replace hangcheck by heartbeats
> -Original Message- > From: Chris Wilson > Sent: Thursday, July 25, 2019 4:17 PM > To: intel-gfx@lists.freedesktop.org > Cc: Chris Wilson ; Joonas Lahtinen > ; Ursulin, Tvrtko ; > Bloomfield, Jon > Subject: [PATCH] drm/i915: Replace hangcheck by heartbeats > > Replace sampling the engine state every so often with a periodic > heartbeat request to measure the health of an engine. This is coupled > with the forced-preemption to allow long running requests to survive so > long as they do not block other users. Can you explain why we would need this at all if we have forced-preemption? Forced preemption guarantees that an engine cannot interfere with the timely execution of other contexts. If it hangs, but nothing else wants to use the engine then do we care? Power, obviously. But I'm not everything can be pre-empted. If a compute context is running on an engine, and no other contexts require that engine, then is it right to nuke it just because it's busy in a long running thread? > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Tvrtko Ursulin > Cc: Jon Bloomfield > --- > Note, strictly this still requires struct_mutex-free retirement for the > corner case where the idle-worker is ineffective and we get a backlog of > requests on the kernel ring. Or if the legacy ringbuffer is full... > When we are able to retire from outside of struct_mutex we can do the > full idle-barrier and idle-work from here. > --- > drivers/gpu/drm/i915/Kconfig.profile | 11 + > drivers/gpu/drm/i915/Makefile | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 - > drivers/gpu/drm/i915/gt/intel_engine.h| 32 -- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +- > .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 99 + > .../gpu/drm/i915/gt/intel_engine_heartbeat.h | 17 + > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +- > drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +- > drivers/gpu/drm/i915/gt/intel_gt.c| 1 - > drivers/gpu/drm/i915/gt/intel_gt.h| 4 - > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 - > drivers/gpu/drm/i915/gt/intel_gt_types.h | 9 - > drivers/gpu/drm/i915/gt/intel_hangcheck.c | 360 -- > drivers/gpu/drm/i915/gt/intel_reset.c | 3 +- > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 4 - > drivers/gpu/drm/i915/i915_debugfs.c | 86 - > drivers/gpu/drm/i915/i915_drv.c | 6 +- > drivers/gpu/drm/i915/i915_drv.h | 1 - > drivers/gpu/drm/i915/i915_gpu_error.c | 37 +- > drivers/gpu/drm/i915/i915_gpu_error.h | 2 - > drivers/gpu/drm/i915/i915_params.c| 5 - > drivers/gpu/drm/i915/i915_params.h| 1 - > 23 files changed, 151 insertions(+), 562 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h > delete mode 100644 drivers/gpu/drm/i915/gt/intel_hangcheck.c > > diff --git a/drivers/gpu/drm/i915/Kconfig.profile > b/drivers/gpu/drm/i915/Kconfig.profile > index 3184e8491333..aafb57f84169 100644 > --- a/drivers/gpu/drm/i915/Kconfig.profile > +++ b/drivers/gpu/drm/i915/Kconfig.profile > @@ -37,3 +37,14 @@ config DRM_I915_PREEMPT_TIMEOUT > to execute. > > May be 0 to disable the timeout. > + > +config DRM_I915_HEARTBEAT_INTERVAL > + int "Interval between heartbeat pulses (ms)" > + default 2500 # microseconds > + help > + While active the driver uses a periodic request, a heartbeat, to > + check the wellness of the GPU and to regularly flush state changes > + (idle barriers). > + > + May be 0 to disable heartbeats and therefore disable automatic GPU > + hang detection. > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 524516251a40..18201852d68d 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -73,10 +73,10 @@ gt-y += \ > gt/intel_breadcrumbs.o \ > gt/intel_context.o \ > gt/intel_engine_cs.o \ > + gt/intel_engine_heartbeat.o \ > gt/intel_engine_pm.o \ > gt/intel_gt.o \ > gt/intel_gt_pm.o \ > - gt/intel_hangcheck.o \ > gt/intel_lrc.o \ > gt/intel_renderstate.o \ > gt/intel_reset.o \ > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c > b/drivers/gpu/drm/i915/gem/i915_gem_pm.c > index b5561cbdc5ea..a5a0aefcc04c 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c > @@ -170,8 +170,6 @@ void i915_gem_suspend(struct drm_i915_private > *i915) > GEM_BUG_ON(i915->gt.awake); > flush_work(&i915->gem.idle_work); > > - cancel_delayed_work_sync(&i915->gt.hangcheck.work); > - > i915_gem_drain_freed_objects(i915); > > intel_uc_suspend(&i915->gt.uc); > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h > b
[Intel-gfx] [PATCH] drm/i915: Replace hangcheck by heartbeats
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Jon Bloomfield
---
Note, strictly this still requires struct_mutex-free retirement for the
corner case where the idle-worker is ineffective and we get a backlog of
requests on the kernel ring. Or if the legacy ringbuffer is full...
When we are able to retire from outside of struct_mutex we can do the
full idle-barrier and idle-work from here.
---
drivers/gpu/drm/i915/Kconfig.profile | 11 +
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 -
drivers/gpu/drm/i915/gt/intel_engine.h| 32 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 99 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 17 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 1 -
drivers/gpu/drm/i915/gt/intel_gt.h| 4 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 9 -
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 360 --
drivers/gpu/drm/i915/gt/intel_reset.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 86 -
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gpu_error.c | 37 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 -
drivers/gpu/drm/i915/i915_params.c| 5 -
drivers/gpu/drm/i915/i915_params.h| 1 -
23 files changed, 151 insertions(+), 562 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
delete mode 100644 drivers/gpu/drm/i915/gt/intel_hangcheck.c
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 3184e8491333..aafb57f84169 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -37,3 +37,14 @@ config DRM_I915_PREEMPT_TIMEOUT
to execute.
May be 0 to disable the timeout.
+
+config DRM_I915_HEARTBEAT_INTERVAL
+ int "Interval between heartbeat pulses (ms)"
+ default 2500 # microseconds
+ help
+ While active the driver uses a periodic request, a heartbeat, to
+ check the wellness of the GPU and to regularly flush state changes
+ (idle barriers).
+
+ May be 0 to disable heartbeats and therefore disable automatic GPU
+ hang detection.
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 524516251a40..18201852d68d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -73,10 +73,10 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
gt/intel_gt.o \
gt/intel_gt_pm.o \
- gt/intel_hangcheck.o \
gt/intel_lrc.o \
gt/intel_renderstate.o \
gt/intel_reset.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index b5561cbdc5ea..a5a0aefcc04c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -170,8 +170,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
GEM_BUG_ON(i915->gt.awake);
flush_work(&i915->gem.idle_work);
- cancel_delayed_work_sync(&i915->gt.hangcheck.work);
-
i915_gem_drain_freed_objects(i915);
intel_uc_suspend(&i915->gt.uc);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index db5c73ce86ee..38eeb4320c97 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -90,38 +90,6 @@ struct drm_printer;
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW
to
* do the writes, and that must have qw aligned offsets, simply pretend it's
8b.
*/
-enum intel_engine_hangcheck_action {
- ENGINE_IDLE = 0,
- ENGINE_WAIT,
- ENGINE_ACTIVE_SEQNO,
- ENGINE_ACTIVE_HEAD,
- ENGINE_ACTIVE_SUBUNITS,
- ENGINE_WAIT_KICK,
- ENGINE_DEAD,
-};
-
-static inline const char *
-hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
-{
- switch (a) {
- case ENGINE_IDLE:
- return "idle";
- case ENGINE_WAIT:
- return "wait";
- case ENGINE_ACTIVE_SEQNO:
-
[Intel-gfx] [PATCH 3/5] drm/i915: Unshare the idle-barrier from other kernel requests
Under some circumstances (see intel_context_prepare_remote_request), we
may use a request along a kernel context to modify the logical state of
another. To keep the target context in place while the request executes,
we take an active reference on it using the kernel timeline. This is the
same timeline as we use for the idle-barrier, and so we end up reusing
the same active node. Except that the idle barrier is special and cannot
be reused in this manner! Give the idle-barrier a reserved timeline
index (0) so that it will always be unique (give or take we may issue
multiple idle barriers across multiple engines).
Reported-by: Lionel Landwerlin
Fixes: ce476c80b8bf ("drm/i915: Keep contexts pinned until after the next
kernel context switch")
Fixes: a9877da2d629 ("drm/i915/oa: Reconfigure contexts on the fly")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Tested-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_context.c | 40 ++-
drivers/gpu/drm/i915/gt/intel_context.h | 13 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 310 ++
drivers/gpu/drm/i915/i915_active.c| 69 +++-
.../drm/i915/selftests/i915_live_selftests.h | 3 +-
5 files changed, 398 insertions(+), 37 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_context.c
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index d64b45f7ec6d..211ac6568a5d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -162,23 +162,41 @@ static int __intel_context_active(struct i915_active
*active)
if (err)
goto err_ring;
+ return 0;
+
+err_ring:
+ intel_ring_unpin(ce->ring);
+err_put:
+ intel_context_put(ce);
+ return err;
+}
+
+int intel_context_active_acquire(struct intel_context *ce)
+{
+ int err;
+
+ err = i915_active_acquire(&ce->active);
+ if (err)
+ return err;
+
/* Preallocate tracking nodes */
if (!i915_gem_context_is_kernel(ce->gem_context)) {
err = i915_active_acquire_preallocate_barrier(&ce->active,
ce->engine);
- if (err)
- goto err_state;
+ if (err) {
+ i915_active_release(&ce->active);
+ return err;
+ }
}
return 0;
+}
-err_state:
- __context_unpin_state(ce->state);
-err_ring:
- intel_ring_unpin(ce->ring);
-err_put:
- intel_context_put(ce);
- return err;
+void intel_context_active_release(struct intel_context *ce)
+{
+ /* Nodes preallocated in intel_context_active() */
+ i915_active_acquire_barrier(&ce->active);
+ i915_active_release(&ce->active);
}
void
@@ -297,3 +315,7 @@ struct i915_request *intel_context_create_request(struct
intel_context *ce)
return rq;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_context.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 23c7e4c0ce7c..07f9924de48f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -104,17 +104,8 @@ static inline void intel_context_exit(struct intel_context
*ce)
ce->ops->exit(ce);
}
-static inline int intel_context_active_acquire(struct intel_context *ce)
-{
- return i915_active_acquire(&ce->active);
-}
-
-static inline void intel_context_active_release(struct intel_context *ce)
-{
- /* Nodes preallocated in intel_context_active() */
- i915_active_acquire_barrier(&ce->active);
- i915_active_release(&ce->active);
-}
+int intel_context_active_acquire(struct intel_context *ce);
+void intel_context_active_release(struct intel_context *ce);
static inline struct intel_context *intel_context_get(struct intel_context *ce)
{
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
new file mode 100644
index ..e3b45fe747ae
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -0,0 +1,310 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+#include "intel_gt.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_flush_test.h"
+#include "selftests/mock_drm.h"
+
+static int request_sync(struct i915_request *rq)
+{
+ long timeout;
+ int err = 0;
+
+ i915_request_get(rq);
+
+ i915_request_add(rq);
+ timeout = i915_request_wait(rq, 0, HZ / 10);
+ if (timeout < 0)
+ err = timeout;
+ else
+ i915_request_retire_upto(rq);
+
+ i915_request_put(rq);
+
+ return err;
+}
+
+static int context_sync(struct intel_context *ce)
+{
+ struct intel_timeline *tl = c
[Intel-gfx] [PATCH 1/5] drm/i915: Capture vma contents outside of spinlock
Currently we use the engine->active.lock to ensure that the request is
not retired as we capture the data. However, we only need to ensure that
the vma are not removed prior to use acquiring their contents, and
since we have already relinquished our stop-machine protection, we
assume that the user will not be overwriting the contents before we are
able to record them.
In order to capture the vma outside of the spinlock, we acquire a
reference and mark the vma as active to prevent it from being unbound.
However, since it is tricky allocate an entry in the fence tree (doing
so would require taking a mutex) while inside the engine spinlock, we
use an atomic bit and special case the handling for i915_active_wait.
The core benefit is that we can use some non-atomic methods for mapping
the device pages, we can remove the slow compression phase out of atomic
context (i.e. stop antagonising the nmi-watchdog), and no we longer need
large reserves of atomic pages.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111215
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_active.c | 34 ++-
drivers/gpu/drm/i915/i915_active.h | 3 +
drivers/gpu/drm/i915/i915_active_types.h | 3 +
drivers/gpu/drm/i915/i915_gpu_error.c| 112 ---
4 files changed, 117 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 13f304a29fc8..22341c62c204 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -196,6 +196,7 @@ void __i915_active_init(struct drm_i915_private *i915,
debug_active_init(ref);
ref->i915 = i915;
+ ref->flags = 0;
ref->active = active;
ref->retire = retire;
ref->tree = RB_ROOT;
@@ -262,6 +263,34 @@ void i915_active_release(struct i915_active *ref)
active_retire(ref);
}
+static void __active_ungrab(struct i915_active *ref)
+{
+ clear_and_wake_up_bit(I915_ACTIVE_GRAB_BIT, &ref->flags);
+}
+
+bool i915_active_trygrab(struct i915_active *ref)
+{
+ debug_active_assert(ref);
+
+ if (test_and_set_bit(I915_ACTIVE_GRAB_BIT, &ref->flags))
+ return false;
+
+ if (!atomic_add_unless(&ref->count, 1, 0)) {
+ __active_ungrab(ref);
+ return false;
+ }
+
+ return true;
+}
+
+void i915_active_ungrab(struct i915_active *ref)
+{
+ GEM_BUG_ON(!test_bit(I915_ACTIVE_GRAB_BIT, &ref->flags));
+
+ active_retire(ref);
+ __active_ungrab(ref);
+}
+
int i915_active_wait(struct i915_active *ref)
{
struct active_node *it, *n;
@@ -270,7 +299,7 @@ int i915_active_wait(struct i915_active *ref)
might_sleep();
might_lock(&ref->mutex);
- if (RB_EMPTY_ROOT(&ref->tree))
+ if (i915_active_is_idle(ref))
return 0;
err = mutex_lock_interruptible(&ref->mutex);
@@ -292,6 +321,9 @@ int i915_active_wait(struct i915_active *ref)
if (err)
return err;
+ if (wait_on_bit(&ref->flags, I915_ACTIVE_GRAB_BIT, TASK_KILLABLE))
+ return -EINTR;
+
if (!i915_active_is_idle(ref))
return -EBUSY;
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 134166d31251..ba68b077ec6c 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -395,6 +395,9 @@ int i915_active_acquire(struct i915_active *ref);
void i915_active_release(struct i915_active *ref);
void __i915_active_release_nested(struct i915_active *ref, int subclass);
+bool i915_active_trygrab(struct i915_active *ref);
+void i915_active_ungrab(struct i915_active *ref);
+
static inline bool
i915_active_is_idle(const struct i915_active *ref)
{
diff --git a/drivers/gpu/drm/i915/i915_active_types.h
b/drivers/gpu/drm/i915/i915_active_types.h
index 5b0a3024ce24..74743dd0d5f0 100644
--- a/drivers/gpu/drm/i915/i915_active_types.h
+++ b/drivers/gpu/drm/i915/i915_active_types.h
@@ -36,6 +36,9 @@ struct i915_active {
struct mutex mutex;
atomic_t count;
+ unsigned long flags;
+#define I915_ACTIVE_GRAB_BIT 0
+
int (*active)(struct i915_active *ref);
void (*retire)(struct i915_active *ref);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 56dfc2650836..674d341a23f6 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -298,7 +298,7 @@ static void *compress_next_page(struct compress *c,
if (dst->page_count >= dst->num_pages)
return ERR_PTR(-ENOSPC);
- page = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
+ page = pool_alloc(&c->pool, ALLOW_FAIL);
if (!page)
return ERR_PTR(-ENOMEM);
@@ -327,8 +327,6 @@ static int compress_page(struct compress *c,
if (zlib_deflate(zstream, Z_NO_FLUSH) !=
[Intel-gfx] [PATCH 4/5] drm/i915/execlists: Force preemption
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of flagging unresponsive contexts more frequently (i.e. instead
of using an ~10s hangcheck, we now evict at ~100ms). The challenge of
lies in picking a timeout that can be reasonably serviced by HW for
typical workloads, balancing the existing clients against the needs for
responsiveness.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Kconfig.profile | 12 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 62 ++--
2 files changed, 71 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 48df8889a88a..3184e8491333 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -25,3 +25,15 @@ config DRM_I915_SPIN_REQUEST
May be 0 to disable the initial spin. In practice, we estimate
the cost of enabling the interrupt (if currently disabled) to be
a few microseconds.
+
+config DRM_I915_PREEMPT_TIMEOUT
+ int "Preempt timeout (ms)"
+ default 100 # milliseconds
+ help
+ How long to wait (in milliseconds) for a preemption event to occur
+ when submitting a new context via execlists. If the current context
+ does not hit an arbitration point and yield to HW before the timer
+ expires, the HW will be reset to allow the more important context
+ to execute.
+
+ May be 0 to disable the timeout.
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 884dfc1cb033..b85ee12c2451 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -945,6 +945,21 @@ static void record_preemption(struct
intel_engine_execlists *execlists)
(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
}
+static unsigned long preempt_expires(void)
+{
+ const unsigned long timeout =
+ msecs_to_jiffies_timeout(CONFIG_DRM_I915_PREEMPT_TIMEOUT);
+
+ /*
+* Paranoia to make sure the compiler computes the timeout before
+* loading 'jiffies' as jiffies is volatile and may be updated in
+* the background by a timer tick. All to reduce the complexity
+* of the addition and reduce the risk of losing a jiffie.
+*/
+ barrier();
+ return jiffies + timeout;
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -1283,6 +1298,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*port = execlists_schedule_in(last, port - execlists->pending);
memset(port + 1, 0, (last_port - port) * sizeof(*port));
execlists_submit_ports(engine);
+ if (CONFIG_DRM_I915_PREEMPT_TIMEOUT)
+ mod_timer(&execlists->timer, preempt_expires());
} else {
ring_set_paused(engine, 0);
}
@@ -1467,13 +1484,45 @@ static void process_csb(struct intel_engine_cs *engine)
invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
}
-static void __execlists_submission_tasklet(struct intel_engine_cs *const
engine)
+static bool __execlists_submission_tasklet(struct intel_engine_cs *const
engine)
{
lockdep_assert_held(&engine->active.lock);
process_csb(engine);
- if (!engine->execlists.pending[0])
+ if (!engine->execlists.pending[0]) {
execlists_dequeue(engine);
+ return true;
+ }
+
+ return false;
+}
+
+static void preempt_reset(struct intel_engine_cs *engine)
+{
+ const unsigned int bit = I915_RESET_ENGINE + engine->id;
+ unsigned long *lock = &engine->gt->reset.flags;
+
+ if (test_and_set_bit(bit, lock))
+ return;
+
+ /* Mark this tasklet as disabled to avoid waiting for it to complete */
+ tasklet_disable_nosync(&engine->execlists.tasklet);
+
+ intel_engine_reset(engine, "preemption time out");
+
+ tasklet_enable(&engine->execlists.tasklet);
+ clear_and_wake_up_bit(bit, lock);
+}
+
+static bool preempt_timeout(struct intel_engine_cs *const engine)
+{
+ if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT)
+ return false;
+
+ if (!intel_engine_has_preemption(engine))
+ return false;
+
+ return !timer_pending(&engine->execlists.timer);
}
/*
@@ -1484,10 +1533,17 @@ static void execlists_submission_tasklet(unsigned long
data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
unsigned long flags;
+ bool reset = false;
[Intel-gfx] [PATCH 2/5] drm/i915/gt: Add to timeline requires the timeline mutex
Modifying a remote context requires careful serialisation with requests
on that context, and that serialisation requires us to take their
timeline->mutex. Make it so.
Note that while struct_mutex rules, we can't create more than one
request in parallel, but that age is soon coming to an end.
v2: Though it doesn't affect the current users, contexts may share
timelines so check if we already hold the right mutex.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 9292b6ca5e9c..d64b45f7ec6d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -254,10 +254,18 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
/* Only suitable for use in remotely modifying this context */
GEM_BUG_ON(rq->hw_context == ce);
- /* Queue this switch after all other activity by this context. */
- err = i915_active_request_set(&tl->last_request, rq);
- if (err)
- return err;
+ if (rq->timeline != tl) { /* beware timeline sharing */
+ err = mutex_lock_interruptible_nested(&tl->mutex,
+ SINGLE_DEPTH_NESTING);
+ if (err)
+ return err;
+
+ /* Queue this switch after current activity by this context. */
+ err = i915_active_request_set(&tl->last_request, rq);
+ if (err)
+ goto unlock;
+ }
+ lockdep_assert_held(&tl->mutex);
/*
* Guarantee context image and the timeline remains pinned until the
@@ -267,7 +275,12 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
* words transfer the pinned ce object to tracked active request.
*/
GEM_BUG_ON(i915_active_is_idle(&ce->active));
- return i915_active_ref(&ce->active, rq->fence.context, rq);
+ err = i915_active_ref(&ce->active, rq->fence.context, rq);
+
+unlock:
+ if (rq->timeline != tl)
+ mutex_unlock(&tl->mutex);
+ return err;
}
struct i915_request *intel_context_create_request(struct intel_context *ce)
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Replace hangcheck by heartbeats
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Jon Bloomfield
---
Note, strictly this still requires struct_mutex-free retirement for the
corner case where the idle-worker is ineffective and we get a backlog of
requests on the kernel ring. Or if the legacy ringbuffer is full...
When we are able to retire from outside of struct_mutex we can do the
full idle-barrier and idle-work from here.
---
drivers/gpu/drm/i915/Kconfig.profile | 11 +
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/intel_engine.h| 32 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 96 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 17 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 1 -
drivers/gpu/drm/i915/gt/intel_gt.h| 4 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 -
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 360 --
drivers/gpu/drm/i915/gt/intel_reset.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 3 -
drivers/gpu/drm/i915/i915_debugfs.c | 86 -
drivers/gpu/drm/i915/i915_drv.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gpu_error.c | 37 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 -
drivers/gpu/drm/i915/i915_params.c| 5 -
drivers/gpu/drm/i915/i915_params.h| 1 -
21 files changed, 148 insertions(+), 547 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
delete mode 100644 drivers/gpu/drm/i915/gt/intel_hangcheck.c
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 3184e8491333..aafb57f84169 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -37,3 +37,14 @@ config DRM_I915_PREEMPT_TIMEOUT
to execute.
May be 0 to disable the timeout.
+
+config DRM_I915_HEARTBEAT_INTERVAL
+ int "Interval between heartbeat pulses (ms)"
+ default 2500 # microseconds
+ help
+ While active the driver uses a periodic request, a heartbeat, to
+ check the wellness of the GPU and to regularly flush state changes
+ (idle barriers).
+
+ May be 0 to disable heartbeats and therefore disable automatic GPU
+ hang detection.
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 524516251a40..18201852d68d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -73,10 +73,10 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
gt/intel_gt.o \
gt/intel_gt_pm.o \
- gt/intel_hangcheck.o \
gt/intel_lrc.o \
gt/intel_renderstate.o \
gt/intel_reset.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index db5c73ce86ee..38eeb4320c97 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -90,38 +90,6 @@ struct drm_printer;
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW
to
* do the writes, and that must have qw aligned offsets, simply pretend it's
8b.
*/
-enum intel_engine_hangcheck_action {
- ENGINE_IDLE = 0,
- ENGINE_WAIT,
- ENGINE_ACTIVE_SEQNO,
- ENGINE_ACTIVE_HEAD,
- ENGINE_ACTIVE_SUBUNITS,
- ENGINE_WAIT_KICK,
- ENGINE_DEAD,
-};
-
-static inline const char *
-hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
-{
- switch (a) {
- case ENGINE_IDLE:
- return "idle";
- case ENGINE_WAIT:
- return "wait";
- case ENGINE_ACTIVE_SEQNO:
- return "active seqno";
- case ENGINE_ACTIVE_HEAD:
- return "active head";
- case ENGINE_ACTIVE_SUBUNITS:
- return "active subunits";
- case ENGINE_WAIT_KICK:
- return "wait kick";
- case ENGINE_DEAD:
- return "dead";
- }
-
- return "unknown";
-}
void intel_engines_set_scheduler_caps(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 65cbf1d9118d..89f4a3825b77 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/inte
[Intel-gfx] [CI] drm/i915: Capture vma contents outside of spinlock
Currently we use the engine->active.lock to ensure that the request is
not retired as we capture the data. However, we only need to ensure that
the vma are not removed prior to use acquiring their contents, and
since we have already relinquished our stop-machine protection, we
assume that the user will not be overwriting the contents before we are
able to record them.
In order to capture the vma outside of the spinlock, we acquire a
reference and mark the vma as active to prevent it from being unbound.
However, since it is tricky allocate an entry in the fence tree (doing
so would require taking a mutex) while inside the engine spinlock, we
use an atomic bit and special case the handling for i915_active_wait.
The core benefit is that we can use some non-atomic methods for mapping
the device pages, we can remove the slow compression phase out of atomic
context (i.e. stop antagonising the nmi-watchdog), and no we longer need
large reserves of atomic pages.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111215
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_active.c | 34 ++-
drivers/gpu/drm/i915/i915_active.h | 3 +
drivers/gpu/drm/i915/i915_active_types.h | 3 +
drivers/gpu/drm/i915/i915_gpu_error.c| 112 ---
4 files changed, 117 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 13f304a29fc8..22341c62c204 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -196,6 +196,7 @@ void __i915_active_init(struct drm_i915_private *i915,
debug_active_init(ref);
ref->i915 = i915;
+ ref->flags = 0;
ref->active = active;
ref->retire = retire;
ref->tree = RB_ROOT;
@@ -262,6 +263,34 @@ void i915_active_release(struct i915_active *ref)
active_retire(ref);
}
+static void __active_ungrab(struct i915_active *ref)
+{
+ clear_and_wake_up_bit(I915_ACTIVE_GRAB_BIT, &ref->flags);
+}
+
+bool i915_active_trygrab(struct i915_active *ref)
+{
+ debug_active_assert(ref);
+
+ if (test_and_set_bit(I915_ACTIVE_GRAB_BIT, &ref->flags))
+ return false;
+
+ if (!atomic_add_unless(&ref->count, 1, 0)) {
+ __active_ungrab(ref);
+ return false;
+ }
+
+ return true;
+}
+
+void i915_active_ungrab(struct i915_active *ref)
+{
+ GEM_BUG_ON(!test_bit(I915_ACTIVE_GRAB_BIT, &ref->flags));
+
+ active_retire(ref);
+ __active_ungrab(ref);
+}
+
int i915_active_wait(struct i915_active *ref)
{
struct active_node *it, *n;
@@ -270,7 +299,7 @@ int i915_active_wait(struct i915_active *ref)
might_sleep();
might_lock(&ref->mutex);
- if (RB_EMPTY_ROOT(&ref->tree))
+ if (i915_active_is_idle(ref))
return 0;
err = mutex_lock_interruptible(&ref->mutex);
@@ -292,6 +321,9 @@ int i915_active_wait(struct i915_active *ref)
if (err)
return err;
+ if (wait_on_bit(&ref->flags, I915_ACTIVE_GRAB_BIT, TASK_KILLABLE))
+ return -EINTR;
+
if (!i915_active_is_idle(ref))
return -EBUSY;
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 134166d31251..ba68b077ec6c 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -395,6 +395,9 @@ int i915_active_acquire(struct i915_active *ref);
void i915_active_release(struct i915_active *ref);
void __i915_active_release_nested(struct i915_active *ref, int subclass);
+bool i915_active_trygrab(struct i915_active *ref);
+void i915_active_ungrab(struct i915_active *ref);
+
static inline bool
i915_active_is_idle(const struct i915_active *ref)
{
diff --git a/drivers/gpu/drm/i915/i915_active_types.h
b/drivers/gpu/drm/i915/i915_active_types.h
index 5b0a3024ce24..74743dd0d5f0 100644
--- a/drivers/gpu/drm/i915/i915_active_types.h
+++ b/drivers/gpu/drm/i915/i915_active_types.h
@@ -36,6 +36,9 @@ struct i915_active {
struct mutex mutex;
atomic_t count;
+ unsigned long flags;
+#define I915_ACTIVE_GRAB_BIT 0
+
int (*active)(struct i915_active *ref);
void (*retire)(struct i915_active *ref);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 56dfc2650836..674d341a23f6 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -298,7 +298,7 @@ static void *compress_next_page(struct compress *c,
if (dst->page_count >= dst->num_pages)
return ERR_PTR(-ENOSPC);
- page = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
+ page = pool_alloc(&c->pool, ALLOW_FAIL);
if (!page)
return ERR_PTR(-ENOMEM);
@@ -327,8 +327,6 @@ static int compress_page(struct compress *c,
if (zlib_deflate(zstream, Z_NO_FLUSH) !=
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Don't sanitize guc_log_level modparam
== Series Details == Series: drm/i915/uc: Don't sanitize guc_log_level modparam URL : https://patchwork.freedesktop.org/series/64264/ State : success == Summary == CI Bug Log - changes from CI_DRM_6553 -> Patchwork_13757 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/ Known issues Here are the changes found in Patchwork_13757 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html * igt@i915_module_load@reload-with-fault-injection: - fi-snb-2520m: [PASS][3] -> [INCOMPLETE][4] ([fdo#105411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_execlists: - fi-bwr-2160:[PASS][5] -> [DMESG-WARN][6] ([fdo#15]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-bwr-2160/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-bwr-2160/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_hangcheck: - fi-bwr-2160:[PASS][7] -> [DMESG-FAIL][8] ([fdo#15]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html * igt@kms_busy@basic-flip-c: - fi-kbl-7500u: [PASS][9] -> [SKIP][10] ([fdo#109271] / [fdo#109278]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html Possible fixes * igt@i915_selftest@live_contexts: - fi-icl-dsi: [DMESG-WARN][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-icl-dsi/igt@i915_selftest@live_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-icl-dsi/igt@i915_selftest@live_contexts.html * igt@i915_selftest@live_hangcheck: - fi-kbl-guc: [INCOMPLETE][13] ([fdo#108744]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#15]: https://bugs.freedesktop.org/show_bug.cgi?id=15 Participating hosts (55 -> 46) -- Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6553 -> Patchwork_13757 CI-20190529: 20190529 CI_DRM_6553: 2480f03103d155b398d2a4f3bb8245877f9b1b8e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13757: 126a500d97cf450bc82f52d602fe2396002ad4d7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 126a500d97cf drm/i915/uc: Don't sanitize guc_log_level modparam == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13757/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove redundant user_access_end() from __copy_from_user() error path
== Series Details ==
Series: drm/i915: Remove redundant user_access_end() from __copy_from_user()
error path
URL : https://patchwork.freedesktop.org/series/64262/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6553 -> Patchwork_13756
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_13756 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13756, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13756:
### IGT changes ###
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][1] ([fdo#109485]) -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Known issues
Here are the changes found in Patchwork_13756 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278])
+2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278])
+2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#109569])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
Possible fixes
* igt@gem_exec_reloc@basic-gtt:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html
* igt@i915_selftest@live_contexts:
- fi-icl-dsi: [DMESG-WARN][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-icl-dsi/igt@i915_selftest@live_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-icl-dsi/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][13] ([fdo#108744]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][15] ([fdo#109380]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-crc-fast:
- {fi-icl-u4}:[FAIL][17] ([fdo#111045] / [fdo#111046 ]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][19] ([fdo#109271]) -> [PASS][20] +23 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6553/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13756/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#
Re: [Intel-gfx] [PATCH] drm/i915: Remove redundant user_access_end() from __copy_from_user() error path
On Thu, 25 Jul 2019, Josh Poimboeuf wrote:
> Objtool reports:
>
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o: warning: objtool:
> .altinstr_replacement+0x36: redundant UACCESS disable
>
> __copy_from_user() already does both STAC and CLAC, so the
> user_access_end() in its error path adds an extra unnecessary CLAC.
>
> Fixes: 0b2c8f8b6b0c ("i915: fix missing user_access_end() in page fault
> exception case")
> Reported-by: Thomas Gleixner
> Reported-by: Sedat Dilek
> Acked-by: Peter Zijlstra (Intel)
> Tested-by: Nick Desaulniers
> Tested-by: Sedat Dilek
> Link: https://github.com/ClangBuiltLinux/linux/issues/617
> Signed-off-by: Josh Poimboeuf
Reviewed-by: Thomas Gleixner
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/uc: Don't sanitize guc_log_level modparam
Quoting Michal Wajdeczko (2019-07-25 21:51:06) > We are already storing runtime value of log level in private > field, so there is no need to modify modparam. There is an aspect of communicating the clamped value back to the user. Does that have any value or alternative? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/uc: Reorder params in intel_uc_fw_fetch
Quoting Michal Wajdeczko (2019-07-25 22:03:14) > All intel_uc_fw_* functions are taking uc_fw as first param > except intel_uc_fw_fetch() which is taking i915. Fix that. > > Signed-off-by: Michal Wajdeczko > Cc: Daniele Ceraolo Spurio Has a certain logic to it, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/23] drm/i915/gt: Move the [class][inst] lookup for engines onto the GT
On 7/23/19 11:38 AM, Chris Wilson wrote:
To maintain a fast lookup from a GT centric irq handler, we want the
engine lookup tables on the intel_gt. To avoid having multiple copies of
the same multi-dimension lookup table, move the generic user engine
lookup into an rbtree (for fast and flexible indexing).
v2: Split uabi_instance cf uabi_class
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
But I'd like an ack from Tvrtko as well since I know he has some similar
planned changes around this as well.
Daniele
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine.h | 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 53 +---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++-
drivers/gpu/drm/i915/gt/intel_engine_user.c | 66
drivers/gpu/drm/i915/gt/intel_engine_user.h | 20 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 +++--
drivers/gpu/drm/i915/i915_drv.h | 7 ++-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_pmu.c | 3 +-
drivers/gpu/drm/i915/i915_query.c| 2 +-
drivers/gpu/drm/i915/i915_trace.h| 10 +--
14 files changed, 138 insertions(+), 60 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_user.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_user.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 524516251a40..fafc3763dc2d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -74,6 +74,7 @@ gt-y += \
gt/intel_context.o \
gt/intel_engine_cs.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_pm.o \
gt/intel_hangcheck.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 18b226bc5e3a..e31431fa141e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -70,6 +70,7 @@
#include
#include "gt/intel_lrc_reg.h"
+#include "gt/intel_engine_user.h"
#include "i915_gem_context.h"
#include "i915_globals.h"
@@ -1740,7 +1741,7 @@ get_engines(struct i915_gem_context *ctx,
if (e->engines[n]) {
ci.engine_class = e->engines[n]->engine->uabi_class;
- ci.engine_instance = e->engines[n]->engine->instance;
+ ci.engine_instance =
e->engines[n]->engine->uabi_instance;
}
if (copy_to_user(&user->engines[n], &ci, sizeof(ci))) {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index db5c73ce86ee..30856383e4c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -432,9 +432,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
struct drm_printer *m,
const char *header, ...);
-struct intel_engine_cs *
-intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);
-
static inline void intel_engine_context_in(struct intel_engine_cs *engine)
{
unsigned long flags;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 65cbf1d9118d..ed5c4e161e6e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -32,6 +32,7 @@
#include "intel_engine.h"
#include "intel_engine_pm.h"
+#include "intel_engine_user.h"
#include "intel_context.h"
#include "intel_lrc.h"
#include "intel_reset.h"
@@ -285,9 +286,7 @@ static void intel_engine_sanitize_mmio(struct
intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u);
}
-static int
-intel_engine_setup(struct drm_i915_private *dev_priv,
- enum intel_engine_id id)
+static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
struct intel_engine_cs *engine;
@@ -303,10 +302,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
return -EINVAL;
- if (GEM_DEBUG_WARN_ON(dev_priv->engine_class[info->class][info->instance]))
+ if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
return -EINVAL;
- GEM_BUG_ON(dev_priv->engine[id]);
engine = kzalloc(sizeof(*engine), GFP_KERNEL);
if (!engine)
return -ENOMEM;
@@ -315,12 +313,12 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
engine->id = id;
engine->mask = BIT(id);
- engine->i915 =
Re: [Intel-gfx] [PATCH] drm/i915: Capture vma contents outside of spinlock
Quoting Matthew Auld (2019-07-25 22:04:33) > On Thu, 25 Jul 2019 at 19:24, Chris Wilson wrote: > > > > Currently we use the engine->active.lock to ensure that the request is > > not retired as we capture the data. However, we only need to ensure that > > the vma are not removed prior to use acquiring their contents, and > > since we have already relinquished our stop-machine protection, we > > assume that the user will not be overwriting the contents before we are > > able to record them. > > > > In order to capture the vma outside of the spinlock, we acquire a > > reference and mark the vma as active to prevent it from being unbound. > > However, since it is tricky allocate an entry in the fence tree (doing > > so would require taking a mutex) while inside the engine spinlock, we > > use an atomic bit and special case the handling for i915_active_wait. > > > > The core benefit is that we can use some non-atomic methods for mapping > > the device pages, we can remove the slow compression phase out of atomic > > context (i.e. stop antagonising the nmi-watchdog), and no we longer need > > large reserves of atomic pages. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111215 > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/i915_active.c | 34 ++- > > drivers/gpu/drm/i915/i915_active.h | 3 + > > drivers/gpu/drm/i915/i915_active_types.h | 3 + > > drivers/gpu/drm/i915/i915_gpu_error.c| 113 --- > > 4 files changed, 118 insertions(+), 35 deletions(-) > > > > > > > static struct drm_i915_error_object * > > @@ -1370,6 +1399,7 @@ gem_record_rings(struct i915_gpu_state *error, struct > > compress *compress) > > struct intel_engine_cs *engine = i915->engine[i]; > > struct drm_i915_error_engine *ee = &error->engine[i]; > > struct i915_request *request; > > + struct capture_vma *capture; > > Not even setting capture = NULL? gcc is a very forgiving compiler it seems. Well spotted, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Capture vma contents outside of spinlock
On Thu, 25 Jul 2019 at 19:24, Chris Wilson wrote: > > Currently we use the engine->active.lock to ensure that the request is > not retired as we capture the data. However, we only need to ensure that > the vma are not removed prior to use acquiring their contents, and > since we have already relinquished our stop-machine protection, we > assume that the user will not be overwriting the contents before we are > able to record them. > > In order to capture the vma outside of the spinlock, we acquire a > reference and mark the vma as active to prevent it from being unbound. > However, since it is tricky allocate an entry in the fence tree (doing > so would require taking a mutex) while inside the engine spinlock, we > use an atomic bit and special case the handling for i915_active_wait. > > The core benefit is that we can use some non-atomic methods for mapping > the device pages, we can remove the slow compression phase out of atomic > context (i.e. stop antagonising the nmi-watchdog), and no we longer need > large reserves of atomic pages. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111215 > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/i915_active.c | 34 ++- > drivers/gpu/drm/i915/i915_active.h | 3 + > drivers/gpu/drm/i915/i915_active_types.h | 3 + > drivers/gpu/drm/i915/i915_gpu_error.c| 113 --- > 4 files changed, 118 insertions(+), 35 deletions(-) > > static struct drm_i915_error_object * > @@ -1370,6 +1399,7 @@ gem_record_rings(struct i915_gpu_state *error, struct > compress *compress) > struct intel_engine_cs *engine = i915->engine[i]; > struct drm_i915_error_engine *ee = &error->engine[i]; > struct i915_request *request; > + struct capture_vma *capture; Not even setting capture = NULL? Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/uc: Reorder params in intel_uc_fw_fetch
All intel_uc_fw_* functions are taking uc_fw as first param
except intel_uc_fw_fetch() which is taking i915. Fix that.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 +++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 4 ++--
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b1815abecf30..8205b3c81048 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -355,10 +355,10 @@ void intel_uc_fetch_firmwares(struct intel_uc *uc)
if (!intel_uc_is_using_guc(uc))
return;
- intel_uc_fw_fetch(i915, &uc->guc.fw);
+ intel_uc_fw_fetch(&uc->guc.fw, i915);
if (intel_uc_is_using_huc(uc))
- intel_uc_fw_fetch(i915, &uc->huc.fw);
+ intel_uc_fw_fetch(&uc->huc.fw, i915);
}
void intel_uc_cleanup_firmwares(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 168d368bcd3e..676ee84ef6ab 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -190,10 +190,8 @@ void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
*
* Fetch uC firmware into GEM obj.
*/
-void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
- struct intel_uc_fw *uc_fw)
+void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private
*i915)
{
- struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
const struct firmware *fw = NULL;
struct uc_css_header *css;
@@ -202,7 +200,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
GEM_BUG_ON(!intel_uc_fw_supported(uc_fw));
- err = request_firmware(&fw, uc_fw->path, &pdev->dev);
+ err = request_firmware(&fw, uc_fw->path, i915->drm.dev);
if (err)
goto fail;
@@ -295,7 +293,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
- obj = i915_gem_object_create_shmem_from_data(dev_priv,
+ obj = i915_gem_object_create_shmem_from_data(i915,
fw->data, fw->size);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
index ff684c0c808e..eddbb237fabe 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
@@ -169,8 +169,8 @@ static inline u32 intel_uc_fw_get_upload_size(struct
intel_uc_fw *uc_fw)
void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
enum intel_uc_fw_type type,
struct drm_i915_private *i915);
-void intel_uc_fw_fetch(struct drm_i915_private *i915,
- struct intel_uc_fw *uc_fw);
+void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw,
+ struct drm_i915_private *i915);
void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw);
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, struct intel_gt *gt,
u32 wopcm_offset, u32 dma_flags);
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/uc: Don't sanitize guc_log_level modparam
We are already storing runtime value of log level in private
field, so there is no need to modify modparam.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 29 -
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 50 --
2 files changed, 28 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 77fda1e85d3b..3460deca12c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -443,6 +443,29 @@ static void guc_log_capture_logs(struct intel_guc_log *log)
guc_action_flush_log_complete(guc);
}
+static u32 __get_default_log_level(struct intel_guc_log *log)
+{
+ /* A negative value means "use platform/config default" */
+ if (i915_modparams.guc_log_level < 0) {
+ return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
+ IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ?
+ GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_NON_VERBOSE;
+ }
+
+ if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
+ DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
+"guc_log_level", i915_modparams.guc_log_level,
+"verbosity too high");
+ return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
+ IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ?
+ GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_DISABLED;
+ }
+
+ GEM_BUG_ON(i915_modparams.guc_log_level < GUC_LOG_LEVEL_DISABLED);
+ GEM_BUG_ON(i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX);
+ return i915_modparams.guc_log_level;
+}
+
int intel_guc_log_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
@@ -482,7 +505,11 @@ int intel_guc_log_create(struct intel_guc_log *log)
log->vma = vma;
- log->level = i915_modparams.guc_log_level;
+ log->level = __get_default_log_level(log);
+ DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
+log->level, enableddisabled(log->level),
+yesno(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
+GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
return 0;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b1815abecf30..4ace47c0978f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -74,23 +74,6 @@ static int __get_platform_enable_guc(struct intel_uc *uc)
return enable_guc;
}
-static int __get_default_guc_log_level(struct intel_uc *uc)
-{
- int guc_log_level;
-
- if (!intel_uc_fw_supported(&uc->guc.fw) || !intel_uc_is_using_guc(uc))
- guc_log_level = GUC_LOG_LEVEL_DISABLED;
- else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
-IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
- guc_log_level = GUC_LOG_LEVEL_MAX;
- else
- guc_log_level = GUC_LOG_LEVEL_NON_VERBOSE;
-
- /* Any platform specific fine-tuning can be done here */
-
- return guc_log_level;
-}
-
/**
* sanitize_options_early - sanitize uC related modparam options
* @uc: the intel_uc structure
@@ -100,13 +83,6 @@ static int __get_default_guc_log_level(struct intel_uc *uc)
* modparam varies between platforms and it is hardcoded in driver code.
* Any other modparam value is only monitored against availability of the
* related hardware or firmware definitions.
- *
- * In case of "guc_log_level" option this function will attempt to modify
- * it only if it was initially set to "auto(-1)" or if initial value was
- * "enable(1..4)" on platforms without the GuC. Default value for this
- * modparam varies between platforms and is usually set to "disable(0)"
- * unless GuC is enabled on given platform and the driver is compiled with
- * debug config when this modparam will default to "enable(1..4)".
*/
static void sanitize_options_early(struct intel_uc *uc)
{
@@ -149,34 +125,8 @@ static void sanitize_options_early(struct intel_uc *uc)
i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
}
- /* A negative value means "use platform/config default" */
- if (i915_modparams.guc_log_level < 0)
- i915_modparams.guc_log_level =
- __get_default_guc_log_level(uc);
-
- if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(uc)) {
- DRM_WARN("Incompatible option detected: guc_log_level=%d, "
-"but GuC is not enabled!\n",
-i915_modparams.guc_log_level);
- i915_modparams.guc_log_level = 0;
- }
-
- if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
- DRM_WARN("Incompatible option detected: %
[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips" (rev3)
== Series Details == Series: Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips" (rev3) URL : https://patchwork.freedesktop.org/series/64212/ State : success == Summary == CI Bug Log - changes from CI_DRM_6549_full -> Patchwork_13748_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13748_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb4/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb4/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-iclb7/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#110741]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-skl1/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#109507]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb4/igt@kms_f...@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-iclb3/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-x.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb2/igt@kms_psr2_su@page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-iclb6/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html Possible fixes * igt@gem_tiled_swapping@non-threaded: - shard-kbl: [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-kbl3/igt@gem_tiled_swapp...@non-threaded.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13748/shard-kbl4/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_self
[Intel-gfx] [PATCH] drm/i915: Remove redundant user_access_end() from __copy_from_user() error path
Objtool reports:
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o: warning: objtool:
.altinstr_replacement+0x36: redundant UACCESS disable
__copy_from_user() already does both STAC and CLAC, so the
user_access_end() in its error path adds an extra unnecessary CLAC.
Fixes: 0b2c8f8b6b0c ("i915: fix missing user_access_end() in page fault
exception case")
Reported-by: Thomas Gleixner
Reported-by: Sedat Dilek
Acked-by: Peter Zijlstra (Intel)
Tested-by: Nick Desaulniers
Tested-by: Sedat Dilek
Link: https://github.com/ClangBuiltLinux/linux/issues/617
Signed-off-by: Josh Poimboeuf
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 20 +--
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5fae0e50aad0..41dab9ea33cd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1628,6 +1628,7 @@ static int check_relocations(const struct
drm_i915_gem_exec_object2 *entry)
static int eb_copy_relocations(const struct i915_execbuffer *eb)
{
+ struct drm_i915_gem_relocation_entry *relocs;
const unsigned int count = eb->buffer_count;
unsigned int i;
int err;
@@ -1635,7 +1636,6 @@ static int eb_copy_relocations(const struct
i915_execbuffer *eb)
for (i = 0; i < count; i++) {
const unsigned int nreloc = eb->exec[i].relocation_count;
struct drm_i915_gem_relocation_entry __user *urelocs;
- struct drm_i915_gem_relocation_entry *relocs;
unsigned long size;
unsigned long copied;
@@ -1663,14 +1663,8 @@ static int eb_copy_relocations(const struct
i915_execbuffer *eb)
if (__copy_from_user((char *)relocs + copied,
(char __user *)urelocs + copied,
-len)) {
-end_user:
- user_access_end();
-end:
- kvfree(relocs);
- err = -EFAULT;
- goto err;
- }
+len))
+ goto end;
copied += len;
} while (copied < size);
@@ -1699,10 +1693,14 @@ static int eb_copy_relocations(const struct
i915_execbuffer *eb)
return 0;
+end_user:
+ user_access_end();
+end:
+ kvfree(relocs);
+ err = -EFAULT;
err:
while (i--) {
- struct drm_i915_gem_relocation_entry *relocs =
- u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
+ relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
if (eb->exec[i].relocation_count)
kvfree(relocs);
}
--
2.20.1
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Update drawing for firmware layout
Quoting Daniele Ceraolo Spurio (2019-07-25 21:16:23) > > > On 7/25/19 7:13 AM, Michal Wajdeczko wrote: > > Sphinx was rendering firmware layout as html table, but since > > we want to add sizes relations switch to plain text graphics. > > > > v2: also update text and do it before move (Daniele) > > > > Signed-off-by: Michal Wajdeczko > > Cc: Daniele Ceraolo Spurio > > Reviewed-by: Daniele Ceraolo Spurio And pushed, thanks for the fixes and updates. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Update drawing for firmware layout
On 7/25/19 7:13 AM, Michal Wajdeczko wrote:
Sphinx was rendering firmware layout as html table, but since
we want to add sizes relations switch to plain text graphics.
v2: also update text and do it before move (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
---
Documentation/gpu/i915.rst | 12
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 31 ++---
2 files changed, 20 insertions(+), 23 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c2173d120492..3e233f9d675f 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -430,6 +430,12 @@ WOPCM Layout
GuC
===
+Firmware Layout
+---
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+ :doc: Firmware Layout
+
GuC-specific firmware loader
@@ -445,12 +451,6 @@ GuC-based command submission
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
:internal:
-GuC Firmware Layout
-
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
- :doc: GuC Firmware Layout
-
GuC Address Space
-
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 30cca3a29323..108b386c52ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -122,23 +122,20 @@
#define GUC_CTL_MAX_DWORDS(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
/**
- * DOC: GuC Firmware Layout
+ * DOC: Firmware Layout
*
- * The GuC firmware layout looks like this:
+ * The GuC/HuC firmware layout looks like this::
*
- * +---+
- * | uc_css_header |
- * | |
- * | contains major/minor version |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * | modulus key |
- * +---+
- * | exponent val |
- * +---+
+ *
+==+
+ * | Firmware blob
|
+ *
+===+===++++
+ * | CSS header | uCode | RSA key | modulus | exponent
|
+ *
+===+===++++
+ * <-header size-> <---header size continued --->
+ * <--- size --->
+ * <-key size->
+ *<-mod size->
+ * <-exp size->
*
* The firmware may or may not have modulus key and exponent data. The header,
* uCode and RSA signature are must-have components that will be used by
driver.
@@ -155,8 +152,8 @@
* 4. Modulus and exponent key are not required by driver. They may not appear
*in fw. So driver will load a truncated firmware in this case.
*
- * HuC firmware layout is same as GuC firmware.
- * Only HuC version information is saved in a different way.
+ * The only difference between GuC and HuC firmwares is how the version
+ * information is saved.
*/
struct uc_css_header {
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Vulkan performance query support (rev10)
== Series Details == Series: drm/i915: Vulkan performance query support (rev10) URL : https://patchwork.freedesktop.org/series/60916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6549_full -> Patchwork_13747_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13747_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13747_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13747_full: ### IGT changes ### Possible regressions * igt@perf@blocking: - shard-hsw: [PASS][1] -> [DMESG-WARN][2] +11 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-hsw1/igt@p...@blocking.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-hsw5/igt@p...@blocking.html - shard-apl: NOTRUN -> [DMESG-WARN][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-apl7/igt@p...@blocking.html * igt@perf@create-destroy-userspace-config: - shard-glk: [PASS][4] -> [DMESG-WARN][5] +9 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-glk4/igt@p...@create-destroy-userspace-config.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-glk1/igt@p...@create-destroy-userspace-config.html * igt@perf@enable-disable: - shard-iclb: [PASS][6] -> [DMESG-WARN][7] +9 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb3/igt@p...@enable-disable.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-iclb2/igt@p...@enable-disable.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-skl: [PASS][8] -> [DMESG-WARN][9] +6 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-skl10/igt@p...@gen8-unprivileged-single-ctx-counters.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-skl10/igt@p...@gen8-unprivileged-single-ctx-counters.html * igt@perf@invalid-oa-format-id: - shard-kbl: [PASS][10] -> [DMESG-WARN][11] +9 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-kbl2/igt@p...@invalid-oa-format-id.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-kbl2/igt@p...@invalid-oa-format-id.html * igt@perf@low-oa-exponent-permissions: - shard-apl: [PASS][12] -> [DMESG-WARN][13] +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-apl7/igt@p...@low-oa-exponent-permissions.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-apl4/igt@p...@low-oa-exponent-permissions.html - shard-skl: [PASS][14] -> [TIMEOUT][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-skl6/igt@p...@low-oa-exponent-permissions.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-skl8/igt@p...@low-oa-exponent-permissions.html * igt@perf@non-sampling-read-error: - shard-skl: [PASS][16] -> [INCOMPLETE][17] +4 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-skl4/igt@p...@non-sampling-read-error.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-skl7/igt@p...@non-sampling-read-error.html * igt@perf@short-reads: - shard-skl: NOTRUN -> [DMESG-WARN][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-skl6/igt@p...@short-reads.html Warnings * igt@perf@short-reads: - shard-kbl: [FAIL][19] ([fdo#103183]) -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-kbl6/igt@p...@short-reads.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-kbl6/igt@p...@short-reads.html Known issues Here are the changes found in Patchwork_13747_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / [fdo#109100]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb8/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13747/shard-iclb7/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-apl2/igt@g
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Capture vma contents outside of spinlock
== Series Details == Series: drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64256/ State : success == Summary == CI Bug Log - changes from CI_DRM_6552 -> Patchwork_13755 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/ Known issues Here are the changes found in Patchwork_13755 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108569]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109483] / [fdo#109635 ]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: [PASS][5] -> [FAIL][6] ([fdo#103167]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html - fi-icl-dsi: [PASS][7] -> [DMESG-WARN][8] ([fdo#106107]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_exec_reloc@basic-write-gtt: - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [SKIP][11] ([fdo#109271] / [fdo#109278]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 Participating hosts (55 -> 46) -- Additional (1): fi-pnv-d510 Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6552 -> Patchwork_13755 CI-20190529: 20190529 CI_DRM_6552: f9b5c6777cb0082fb7461ea8a57206b8de2d70dd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13755: d93e6d5f8083fdfa299c7e7da283a88802094607 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d93e6d5f8083 drm/i915: Capture vma contents outside of spinlock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13755/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Capture vma contents outside of spinlock
== Series Details == Series: drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64256/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Capture vma contents outside of spinlock -O:drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gpu_error.c:1007:21: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
On 2019-07-25 00:32, Lucas De Marchi wrote:
On Thu, Jul 18, 2019 at 10:09:27AM -0700, Daniele Ceraolo Spurio wrote:
On 7/18/19 6:08 AM, Ville Syrjälä wrote:
On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
From: Tomasz Lis
The MOCS table is published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Two of the 3 legacy entries used for gen9 are no longer expected to
work.
Although we are changing the gen11 table, those changes are
supposed to
be backward compatible since we are only touching previously undefined
entries.
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
Signed-off-by: Tomasz Lis
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 290a5e9b90b9..259e7bec0a63 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but
configured. */
/* (e)LLC caching options */
+/*
+ * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it
means
+ * the same as LE_UC
+ */
#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
#define LE_1_UC _LE_CACHEABILITY(1)
#define LE_2_WT _LE_CACHEABILITY(2)
@@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
* of bspec.
*
* Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon. For the time
- * being they will be initialized to PTE.
+ * userspace is concerned and shouldn't be relied upon. For Gen < 12
+ * they will be initialized to PTE. Gen >= 12 onwards don't have a
setting for
+ * PTE. We use the same value, but that actually means Uncached.
*
* The last two entries are reserved by the hardware. For ICL+ they
* should be initialized according to bspec and never used, for older
@@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry
broxton_mocs_table[] = {
};
#define GEN11_MOCS_ENTRIES \
- /* Base - Uncached (Deprecated) */ \
+ /* Gen11: Base - Uncached (Deprecated) */ \
+ /* Gen12+: Base - Error (Reserved for Non-Use) */ \
MOCS_ENTRY(I915_MOCS_UNCACHED, \
LE_1_UC | LE_TC_1_LLC, \
L3_1_UC), \
/* Base - L3 + LeCC:PAT (Deprecated) */ \
+ /* Gen12+: Base - Reserved */ \
MOCS_ENTRY(I915_MOCS_PTE, \
LE_0_PAGETABLE | LE_TC_1_LLC, \
L3_3_WB), \
@@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry
broxton_mocs_table[] = {
MOCS_ENTRY(23, \
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) |
LE_SCC(7), \
L3_3_WB), \
+ /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
Why is this marked as reserved? From the looks of things 48-61 should
just be normal entries that userspace can select to get HDC L1$. And
looks like icl already has that stuff. So someone should probably
figure
out if Mesa/etc. can make use of the HDC L1$, and if so we should add
the relevant MOCS entries for icl as well.
Here the reserved terminology is indeed misleading. The 48-59 range
is a "special" range where L1 usage is implicitly enabled by the HW,
as there is no explicit L1 toggle in the MOCS registers. The reserved
here means that the range shouldn't be used for "normal" MOCS
settings, but SW can freely use these entries as needed. Similarly,
MOCS 60 and 61 are reserved for other special purposes, but are still
usable by SW. The only entries SW shouldn't touch are 62 and 63.
Regarding ICL, Gen11 HW doesn't have the capability so no new entries
are required there.
It might be a good idea to find a better word for it than "reserved".
Not only for this patch, but to be used everywhere, especially the spec.
But that exceeds the scope of this review.
+ MOCS_ENTRY(48, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_3_WB), \
+ /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
The specs have MOCS 49-51 defined as well.
humn... it seems they got added later.
I'm not sure anymore if we should update igt so it doesn't expect those
entries to be set to PTE or if we should stop reusing the same table for
ICL and TGL. Spec doesn't mention the compatibility of this table with
gen 11 anymore. Thoughts?
It doesn't sound right to change the implementation decision to keep them
together, only because this allows to keep tests intact.
I don't believe there's a reason to verify undefined entries in IGT.
Sometimes we do want to verify our specific implementation instead of
pure specs compliance; but I don't see a reason for this should be the
case here.
The existing MOCS entries are supposed to be unchangeable (in
[Intel-gfx] [PATCH] drm/i915: Capture vma contents outside of spinlock
Currently we use the engine->active.lock to ensure that the request is
not retired as we capture the data. However, we only need to ensure that
the vma are not removed prior to use acquiring their contents, and
since we have already relinquished our stop-machine protection, we
assume that the user will not be overwriting the contents before we are
able to record them.
In order to capture the vma outside of the spinlock, we acquire a
reference and mark the vma as active to prevent it from being unbound.
However, since it is tricky allocate an entry in the fence tree (doing
so would require taking a mutex) while inside the engine spinlock, we
use an atomic bit and special case the handling for i915_active_wait.
The core benefit is that we can use some non-atomic methods for mapping
the device pages, we can remove the slow compression phase out of atomic
context (i.e. stop antagonising the nmi-watchdog), and no we longer need
large reserves of atomic pages.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111215
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 34 ++-
drivers/gpu/drm/i915/i915_active.h | 3 +
drivers/gpu/drm/i915/i915_active_types.h | 3 +
drivers/gpu/drm/i915/i915_gpu_error.c| 113 ---
4 files changed, 118 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 13f304a29fc8..9cf2d5fe5eae 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -196,6 +196,7 @@ void __i915_active_init(struct drm_i915_private *i915,
debug_active_init(ref);
ref->i915 = i915;
+ ref->flags = 0;
ref->active = active;
ref->retire = retire;
ref->tree = RB_ROOT;
@@ -262,6 +263,34 @@ void i915_active_release(struct i915_active *ref)
active_retire(ref);
}
+static void __active_ungrab(struct i915_active *ref)
+{
+ clear_and_wake_up_bit(I915_ACTIVE_GRAB, &ref->flags);
+}
+
+bool i915_active_trygrab(struct i915_active *ref)
+{
+ debug_active_assert(ref);
+
+ if (test_and_set_bit(I915_ACTIVE_GRAB, &ref->flags))
+ return false;
+
+ if (!atomic_add_unless(&ref->count, 1, 0)) {
+ __active_ungrab(ref);
+ return false;
+ }
+
+ return true;
+}
+
+void i915_active_ungrab(struct i915_active *ref)
+{
+ GEM_BUG_ON(!test_bit(I915_ACTIVE_GRAB, &ref->flags));
+
+ active_retire(ref);
+ __active_ungrab(ref);
+}
+
int i915_active_wait(struct i915_active *ref)
{
struct active_node *it, *n;
@@ -270,7 +299,7 @@ int i915_active_wait(struct i915_active *ref)
might_sleep();
might_lock(&ref->mutex);
- if (RB_EMPTY_ROOT(&ref->tree))
+ if (i915_active_is_idle(ref))
return 0;
err = mutex_lock_interruptible(&ref->mutex);
@@ -292,6 +321,9 @@ int i915_active_wait(struct i915_active *ref)
if (err)
return err;
+ if (wait_on_bit(&ref->flags, I915_ACTIVE_GRAB, TASK_KILLABLE))
+ return -EINTR;
+
if (!i915_active_is_idle(ref))
return -EBUSY;
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 134166d31251..ba68b077ec6c 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -395,6 +395,9 @@ int i915_active_acquire(struct i915_active *ref);
void i915_active_release(struct i915_active *ref);
void __i915_active_release_nested(struct i915_active *ref, int subclass);
+bool i915_active_trygrab(struct i915_active *ref);
+void i915_active_ungrab(struct i915_active *ref);
+
static inline bool
i915_active_is_idle(const struct i915_active *ref)
{
diff --git a/drivers/gpu/drm/i915/i915_active_types.h
b/drivers/gpu/drm/i915/i915_active_types.h
index 5b0a3024ce24..967bdf2f5dda 100644
--- a/drivers/gpu/drm/i915/i915_active_types.h
+++ b/drivers/gpu/drm/i915/i915_active_types.h
@@ -36,6 +36,9 @@ struct i915_active {
struct mutex mutex;
atomic_t count;
+ unsigned long flags;
+#define I915_ACTIVE_GRAB 0
+
int (*active)(struct i915_active *ref);
void (*retire)(struct i915_active *ref);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 56dfc2650836..4d01ae1461ea 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -298,7 +298,7 @@ static void *compress_next_page(struct compress *c,
if (dst->page_count >= dst->num_pages)
return ERR_PTR(-ENOSPC);
- page = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
+ page = pool_alloc(&c->pool, ALLOW_FAIL);
if (!page)
return ERR_PTR(-ENOMEM);
@@ -327,8 +327,6 @@ static int compress_page(struct compress *c,
if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
return -EIO;
-
-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: init submission structures as part of guc_init
== Series Details ==
Series: drm/i915/guc: init submission structures as part of guc_init
URL : https://patchwork.freedesktop.org/series/64254/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6552 -> Patchwork_13754
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/
Known issues
Here are the changes found in Patchwork_13754 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#108569])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#110387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@gem_exec_reloc@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][7] ([fdo#109271] / [fdo#109278]) -> [PASS][8]
+2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][9] ([fdo#109380]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][11] ([fdo#109271]) -> [PASS][12] +23 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [SKIP][13] ([fdo#109271]) -> [PASS][14] +23 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
Participating hosts (55 -> 46)
--
Additional (1): fi-pnv-d510
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6552 -> Patchwork_13754
CI-20190529: 20190529
CI_DRM_6552: f9b5c6777cb0082fb7461ea8a57206b8de2d70dd @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13754: 55c45b08bcdcbb9d63b91b9181370dc82e009dd4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
55c45b08bcdc drm/i915/guc: init submission structures as part of guc_init
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13754/
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips" (rev4)
== Series Details == Series: Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips" (rev4) URL : https://patchwork.freedesktop.org/series/64212/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6552 -> Patchwork_13753 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13753 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13753, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13753: ### IGT changes ### Possible regressions * igt@i915_module_load@reload: - fi-skl-6700k2: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-skl-6700k2/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-skl-6700k2/igt@i915_module_l...@reload.html - fi-skl-guc: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-skl-guc/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-skl-guc/igt@i915_module_l...@reload.html * igt@runner@aborted: - fi-bxt-j4205: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-bxt-j4205/igt@run...@aborted.html - fi-whl-u: NOTRUN -> [FAIL][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-whl-u/igt@run...@aborted.html - fi-cml-u2: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-cml-u2/igt@run...@aborted.html - fi-cml-u: NOTRUN -> [FAIL][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-cml-u/igt@run...@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-bxt-dsi/igt@run...@aborted.html - fi-apl-guc: NOTRUN -> [FAIL][10] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-apl-guc/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-bdw-5557u/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_13753 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][12] -> [INCOMPLETE][13] ([fdo#107718]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html Possible fixes * igt@gem_exec_reloc@basic-write-gtt: - fi-icl-u3: [DMESG-WARN][14] ([fdo#107724]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html * igt@i915_module_load@reload: - fi-icl-u3: [TIMEOUT][16] ([fdo#111214]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u3/igt@i915_module_l...@reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-icl-u3/igt@i915_module_l...@reload.html Warnings * igt@i915_module_load@reload: - fi-icl-u2: [TIMEOUT][18] ([fdo#111214]) -> [DMESG-WARN][19] ([fdo#110595]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u2/igt@i915_module_l...@reload.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13753/fi-icl-u2/igt@i915_module_l...@reload.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595 [fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214 Participating hosts (55 -> 45) -- Additional (1): fi-pnv-d510 Missing(11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-icl-y fi-icl-guc fi-icl-dsi fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6552 -> Patchwork_13753 CI-20190529: 20190529 CI_DRM_6552: f9b5c6777cb0082fb7461ea8a57206b8de2d70dd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13753: 4c375059e361b3b8
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Unshare the idle-barrier from other kernel requests (rev4)
== Series Details ==
Series: drm/i915: Unshare the idle-barrier from other kernel requests (rev4)
URL : https://patchwork.freedesktop.org/series/64171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6549_full -> Patchwork_13746_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_13746_full:
### IGT changes ###
Possible regressions
* {igt@i915_selftest@live_gt_contexts} (NEW):
- shard-hsw: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-hsw2/igt@i915_selftest@live_gt_contexts.html
- shard-snb: NOTRUN -> [DMESG-FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-snb5/igt@i915_selftest@live_gt_contexts.html
New tests
-
New tests have been introduced between CI_DRM_6549_full and
Patchwork_13746_full:
### New IGT tests (2) ###
* igt@i915_selftest@live_gem_contexts:
- Statuses : 7 pass(s)
- Exec time: [5.06, 34.34] s
* igt@i915_selftest@live_gt_contexts:
- Statuses : 2 dmesg-fail(s) 5 pass(s)
- Exec time: [0.39, 2.33] s
Known issues
Here are the changes found in Patchwork_13746_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-skl10/igt@gem_ctx_isolat...@rcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-skl4/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@i915_pm_rpm@i2c:
- shard-hsw: [PASS][5] -> [FAIL][6] ([fdo#104097])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-hsw4/igt@i915_pm_...@i2c.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-hsw2/igt@i915_pm_...@i2c.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-apl3/igt@i915_susp...@debugfs-reader.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-apl5/igt@i915_susp...@debugfs-reader.html
* igt@kms_busy@basic-modeset-a:
- shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-apl3/igt@kms_b...@basic-modeset-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-apl1/igt@kms_b...@basic-modeset-a.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +7 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-y.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-y.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642] / [fdo#111068])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb2/igt@kms_psr2_su@page_flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-iclb7/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#108341])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb6/igt@kms_psr@no_drrs.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +5 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#99912])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6549/shard-kbl6/igt@kms_setm...@basic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13746/shard-kbl4/igt@kms_setm...@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +5
similar issues
[23]:
https://intel-gfx-ci.01.org/t
[Intel-gfx] [PATCH] drm/i915/guc: init submission structures as part of guc_init
guc->stage_desc_pool is required as part of the init parameters and
there is no reason we have to init them after HuC. This fixes a NULL
ptr dereference due to guc->stage_desc_pool not being set (no fixes
tag since GuC submission can't be enabled yet).
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 15 +++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 16
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 1ea6a9e50c02..13fbbffd05c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -290,6 +290,16 @@ int intel_guc_init(struct intel_guc *guc)
if (ret)
goto err_ads;
+ if (intel_uc_is_using_guc_submission(>->uc)) {
+ /*
+* This is stuff we need to have available at fw load time
+* if we are planning to enable submission later
+*/
+ ret = intel_guc_submission_init(guc);
+ if (ret)
+ goto err_ct;
+ }
+
/* now that everything is perma-pinned, initialize the parameters */
guc_init_params(guc);
@@ -298,6 +308,8 @@ int intel_guc_init(struct intel_guc *guc)
return 0;
+err_ct:
+ intel_guc_ct_fini(&guc->ct);
err_ads:
intel_guc_ads_destroy(guc);
err_log:
@@ -317,6 +329,9 @@ void intel_guc_fini(struct intel_guc *guc)
i915_ggtt_disable_guc(gt->ggtt);
+ if (intel_uc_is_using_guc_submission(>->uc))
+ intel_guc_submission_fini(guc);
+
intel_guc_ct_fini(&guc->ct);
intel_guc_ads_destroy(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b1815abecf30..8eef85696ec2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -397,21 +397,8 @@ int intel_uc_init(struct intel_uc *uc)
goto err_guc;
}
- if (intel_uc_is_using_guc_submission(uc)) {
- /*
-* This is stuff we need to have available at fw load time
-* if we are planning to enable submission later
-*/
- ret = intel_guc_submission_init(guc);
- if (ret)
- goto err_huc;
- }
-
return 0;
-err_huc:
- if (intel_uc_is_using_huc(uc))
- intel_huc_fini(huc);
err_guc:
intel_guc_fini(guc);
return ret;
@@ -426,9 +413,6 @@ void intel_uc_fini(struct intel_uc *uc)
GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
- if (intel_uc_is_using_guc_submission(uc))
- intel_guc_submission_fini(guc);
-
if (intel_uc_is_using_huc(uc))
intel_huc_fini(&uc->huc);
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips" (rev4)
== Series Details == Series: Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips" (rev4) URL : https://patchwork.freedesktop.org/series/64212/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4c375059e361 Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips" -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13745/fi-icl-u2/igt@i915_module_l...@reload.html -:117: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif #117: FILE: sound/pci/hda/patch_hdmi.c:2578: +#if 0 // XXX -:130: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif #130: FILE: sound/pci/hda/patch_hdmi.c:2600: +#if 0 // XXX -:141: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 3 warnings, 0 checks, 36 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Define GuC firmware version for Comet Lake (rev5)
== Series Details == Series: drm/i915/guc: Define GuC firmware version for Comet Lake (rev5) URL : https://patchwork.freedesktop.org/series/62969/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6552 -> Patchwork_13752 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13752 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13752, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13752: ### IGT changes ### Possible regressions * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html Known issues Here are the changes found in Patchwork_13752 that come from known issues: ### IGT changes ### Issues hit * igt@gem_basic@bad-close: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u3/igt@gem_ba...@bad-close.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-icl-u3/igt@gem_ba...@bad-close.html * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rpm@module-reload: - fi-icl-dsi: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#108840]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-dsi/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-icl-dsi/igt@i915_pm_...@module-reload.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][9] -> [FAIL][10] ([fdo#103167]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_exec_reloc@basic-write-gtt: - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [SKIP][17] ([fdo#109271]) -> [PASS][18] +23 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6552/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13752/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (55 -> 46) -- Additional (1): fi-pnv-d510 Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6552 -> Patchw
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Fix GuC documentation links
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Fix GuC documentation links
URL : https://patchwork.freedesktop.org/series/64237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6551 -> Patchwork_13751
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/
Known issues
Here are the changes found in Patchwork_13751 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278])
+2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278])
+2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [PASS][7] -> [WARN][8] ([fdo#109380])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#109485])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [PASS][11] -> [SKIP][12] ([fdo#109271]) +23 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-skl-gvtdvm: [TIMEOUT][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-skl-gvtdvm/igt@gem_ctx_cre...@basic-files.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-skl-gvtdvm/igt@gem_ctx_cre...@basic-files.html
* {igt@gem_ctx_switch@rcs0}:
- {fi-icl-guc}: [INCOMPLETE][15] ([fdo#107713]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][17] ([fdo#107718]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2520m: [INCOMPLETE][19] ([fdo#105411]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_chamelium@hdmi-crc-fast:
- {fi-icl-u4}:[FAIL][21] ([fdo#111045] / [fdo#111046 ]) ->
[PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][23] ([fdo#103167]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][25] ([fdo#103167]) -> [PASS][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13751
[Intel-gfx] [PULL] drm-misc-fixes
Hi all, Substitute-Maarten here for another pull request. This week is pretty light, as you would expect. I merged a leftover nugget from drm-misc-next that didn't make -rc1 and am abusing covering for Maarten by sneaking in a handful of msm changes to avoid having to send 2 pulls. drm-misc-fixes-2019-07-25: - pick up the cmdline fix which missed the merge window (Dmitry) - a handful of msm fixes so i don't have to spin up msm-fixes (Various) - fix -Wunused-but-set-variable warning in drm_framebuffer (Qian) Cc: Dmitry Osipenko Cc: Rob Clark Cc: Qian Cai Cheers, Sean The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b: Linus 5.3-rc1 (2019-07-21 14:05:38 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-07-25 for you to fetch changes up to bbb6fc43f131f77fcb7ae8081f6d7c51396a2120: drm: silence variable 'conn' set but not used (2019-07-22 16:04:53 -0400) - pick up the cmdline fix which missed the merge window (Dmitry) - a handful of msm fixes so i don't have to spin up msm-fixes (Various) - fix -Wunused-but-set-variable warning in drm_framebuffer (Qian) Cc: Dmitry Osipenko Cc: Rob Clark Cc: Qian Cai Brian Masney (1): drm/msm: correct NULL pointer dereference in context_init Dmitry Osipenko (1): drm/modes: Don't apply cmdline's rotation if it wasn't specified Qian Cai (1): drm: silence variable 'conn' set but not used Rob Clark (1): drm/msm: stop abusing dma_map/unmap for cache Sean Paul (1): Merge drm-misc-next-fixes-2019-07-18 into drm-misc-fixes Shubhashree Dhar (1): drm/msm/dpu: Correct dpu encoder spinlock initialization drivers/gpu/drm/drm_client_modeset.c| 2 +- drivers/gpu/drm/drm_framebuffer.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +-- drivers/gpu/drm/msm/msm_drv.c | 2 +- drivers/gpu/drm/msm/msm_gem.c | 4 ++-- 5 files changed, 6 insertions(+), 7 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915: Fix GuC documentation links
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Fix GuC documentation links
URL : https://patchwork.freedesktop.org/series/64237/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5ed7463b65ac drm/i915: Fix GuC documentation links
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#9:
References: commit 0f261b241d9c ("drm/i915/uc: move GuC and HuC files under
gt/uc/")
total: 0 errors, 1 warnings, 0 checks, 33 lines checked
e6ce40273824 drm/i915/uc: Update drawing for firmware layout
e1e2f6e499d8 drm/i915/uc: Move uc firmware layout definitions to dedicated file
-:120: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#120:
new file mode 100644
-:173: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#173: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h:49:
+* key, modulus key and exponent data. */
total: 0 errors, 2 warnings, 0 checks, 166 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Add to timeline requires the timeline mutex
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Add to timeline requires the
timeline mutex
URL : https://patchwork.freedesktop.org/series/64227/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6551 -> Patchwork_13750
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/
New tests
-
New tests have been introduced between CI_DRM_6551 and Patchwork_13750:
### New IGT tests (2) ###
* igt@i915_selftest@live_gem_contexts:
- Statuses : 46 pass(s)
- Exec time: [0.40, 28.30] s
* igt@i915_selftest@live_gt_contexts:
- Statuses : 46 pass(s)
- Exec time: [0.38, 1.34] s
Known issues
Here are the changes found in Patchwork_13750 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][1] -> [SKIP][2] ([fdo#109271] / [fdo#109278])
+2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [PASS][3] -> [WARN][4] ([fdo#109380])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271]) +23 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-skl-gvtdvm: [TIMEOUT][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-skl-gvtdvm/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-skl-gvtdvm/igt@gem_ctx_cre...@basic-files.html
* {igt@gem_ctx_switch@rcs0}:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2520m: [INCOMPLETE][13] ([fdo#105411]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [INCOMPLETE][15] ([fdo#107713] / [fdo#108840]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-icl-dsi/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-icl-u4}:[FAIL][17] ([fdo#109485]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][19] ([fdo#103167]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][21] ([fdo#103167]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@vgem_basic@setversion:
- fi-icl-dsi: [DMESG-WARN][23] ([fdo#106107]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-dsi/igt@vgem_ba...@setversion.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13750/fi-icl-dsi/igt@vgem_ba...@set
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Do not rely on for loop caching the mask
== Series Details ==
Series: drm/i915: Do not rely on for loop caching the mask
URL : https://patchwork.freedesktop.org/series/64225/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6551 -> Patchwork_13749
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/
Known issues
Here are the changes found in Patchwork_13749 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_addfb_basic@invalid-set-prop-any:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-dsi/igt@kms_addfb_ba...@invalid-set-prop-any.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-icl-dsi/igt@kms_addfb_ba...@invalid-set-prop-any.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278])
+2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [PASS][5] -> [WARN][6] ([fdo#109380])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#109485])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [PASS][9] -> [SKIP][10] ([fdo#109271]) +23 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-skl-gvtdvm: [TIMEOUT][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-skl-gvtdvm/igt@gem_ctx_cre...@basic-files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-skl-gvtdvm/igt@gem_ctx_cre...@basic-files.html
* {igt@gem_ctx_switch@rcs0}:
- {fi-icl-guc}: [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][15] ([fdo#107718]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2520m: [INCOMPLETE][17] ([fdo#105411]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][19] ([fdo#103167]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [SKIP][21] ([fdo#109271]) -> [PASS][22] +23 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6551/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13749/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bug
Re: [Intel-gfx] [PATCH] drm/i915/guc: Define GuC firmware version for Comet Lake
On 7/25/19 7:27 AM, Michal Wajdeczko wrote: From GT perspective, Comet Lake is just Coffe Lake rev 5, but there is dedicated GuC firmware for it. According to Anusha there is also a dedicated HuC FW for it, which should be coming out soon, so we should probably wait and add them both at the same time since we still don't have a use for GuC by itself (because submission is still off). Daniele Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 789b3d7228a4..3519418b17ce 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -35,6 +35,7 @@ */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ fw_def(ICELAKE,0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ + fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Revert "ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips"
On Thu, 25 Jul 2019 15:57:10 +0200, Chris Wilson wrote: > > Quoting Takashi Iwai (2019-07-25 14:45:10) > > On Thu, 25 Jul 2019 12:49:12 +0200, > > Chris Wilson wrote: > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13745/fi-icl-u2/igt@i915_module_l...@reload.html > > > <4> [383.858354] snd_hda_intel :00:1f.3: azx_get_response timeout, > > > switching to polling mode: last cmd=0x20170500 > > > <4> [384.860261] snd_hda_intel :00:1f.3: No response from codec, > > > disabling MSI: last cmd=0x20170500 > > > <3> [556.636243] snd_hda_codec_hdmi hdaudioC0D2: Unable to sync register > > > 0x2f8100. -11 > > > > Looking at the logs around this, you can find: > > > > <7>[ 380.741747] [IGT] i915_module_load: executing > > <7>[ 380.745788] [IGT] i915_module_load: starting subtest reload > > <4>[ 383.858354] snd_hda_intel :00:1f.3: azx_get_response timeout, > > switching to polling mode: last cmd=0x20170500 > > <4>[ 384.860261] snd_hda_intel :00:1f.3: No response from codec, > > disabling MSI: last cmd=0x20170500 > > <3>[ 556.636243] snd_hda_codec_hdmi hdaudioC0D2: Unable to sync register > > 0x2f8100. -11 > > <3>[ 556.636243] snd_hda_codec_hdmi hdaudioC0D2: Unable to sync register > > 0x2f8100. -11 > > <7>[ 556.636556] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port B > > <7>[ 556.636681] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port B > > <7>[ 556.636775] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port B > > <7>[ 556.636865] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port C > > <7>[ 556.636959] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port C > > <7>[ 556.637042] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port C > > <7>[ 556.637134] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port D > > <7>[ 556.637312] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port D > > <7>[ 556.637445] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port E > > <7>[ 556.637557] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port E > > <7>[ 556.637664] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port E > > <7>[ 556.637751] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port F > > <7>[ 556.637825] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port F > > <7>[ 556.637900] [drm:i915_audio_component_get_eld [i915]] Not valid for > > port F > > <7>[ 556.679134] [IGT] i915_module_load: executing > > <7>[ 556.681585] [IGT] i915_module_load: starting subtest reload-no-display > > > > What does it actually do? First off, there is a big gap in the > > timestamps between 384 and 556. > > Therein is where our current problem lies. Looking at the run just before > this pair of commits, > > <6> [405.838716] [IGT] i915_module_load: executing > <6> [405.841651] [IGT] i915_module_load: starting subtest reload > <4> [408.976245] snd_hda_intel :00:1f.3: azx_get_response timeout, > switching to polling mode: last cmd=0x202f8100 > <4> [409.980171] snd_hda_intel :00:1f.3: No response from codec, > disabling MSI: last cmd=0x202f8100 > <3> [410.985180] snd_hda_intel :00:1f.3: azx_get_response timeout, > switching to single_cmd mode: last cmd=0x202f8100 > <3> [411.227736] snd_hda_codec_hdmi hdaudioC0D2: Unable to sync register > 0x2f8100. -5 > <7> [411.227849] [drm:i915_audio_component_get_eld [i915]] Not valid for port > B > <7> [411.227886] [drm:i915_audio_component_get_eld [i915]] Not valid for port > B > <7> [411.227917] [drm:i915_audio_component_get_eld [i915]] Not valid for port > C > <7> [411.227947] [drm:i915_audio_component_get_eld [i915]] Not valid for port > C > <7> [411.228004] [drm:i915_audio_component_get_eld [i915]] Not valid for port > C > <7> [411.228041] [drm:i915_audio_component_get_eld [i915]] Not valid for port > D > <7> [411.228077] [drm:i915_audio_component_get_eld [i915]] Not valid for port > D > <7> [411.228125] [drm:i915_audio_component_get_eld [i915]] Not valid for port > D > <7> [411.228160] [drm:i915_audio_component_get_eld [i915]] Not valid for port > E > <7> [411.228187] [drm:i915_audio_component_get_eld [i915]] Not valid for port > E > <7> [411.228214] [drm:i915_audio_component_get_eld [i915]] Not valid for port > E > <7> [411.228239] [drm:i915_audio_component_get_eld [i915]] Not valid for port > F > <7> [411.228265] [drm:i915_audio_component_get_eld [i915]] Not valid for port > F > <7> [411.228291] [drm:i915_audio_component_get_eld [i915]] Not valid for port > F > > Same error, but no delay. OK, that sheds some light. With the recent fix using the write-sync, each verb execution is synchronous and waits for the codec response. And judging from the log, at this state, the codec doesn't respond properly, so each verb execution gets some delay. This accumulated as a large delay in the end, now appearing as a significant timeout error. S
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Add to timeline requires the timeline mutex
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Add to timeline requires the
timeline mutex
URL : https://patchwork.freedesktop.org/series/64227/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
400f113b3b2b drm/i915/gt: Add to timeline requires the timeline mutex
7b3634ed02fa drm/i915: Unshare the idle-barrier from other kernel requests
-:112: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#112:
new file mode 100644
-:117: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#117: FILE: drivers/gpu/drm/i915/gt/selftest_context.c:1:
+/*
-:118: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#118: FILE: drivers/gpu/drm/i915/gt/selftest_context.c:2:
+ * SPDX-License-Identifier: GPL-2.0
-:372: WARNING:LONG_LINE: line over 100 characters
#372: FILE: drivers/gpu/drm/i915/gt/selftest_context.c:256:
+ pr_err("remote context is not active; expected
idle-barrier (pass %d)\n", pass);
total: 0 errors, 4 warnings, 0 checks, 528 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] i915/gem_ctx_shared: Avoid clflush by using WC for readback
On Tue, 23 Jul 2019 at 17:17, Chris Wilson wrote: > > As we never officially write to the scratch buffer, the kernel will > leave it in the CPU read domain upon execution. Our attempt to > invalidate the CPU cache on !llc is therefore skipped as the kernel > doesn't believe the backing store has been invalidated. Use a WC mmap to > avoid the CPU cache for readback, and add an extra sanity check that the > scratch buffer is found at the same location after execution. (This > sanity check does not affect the failure rate on bsw, that is only fixed > after realising that we do not clflush for the invalidate prior to the > read). > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87 > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: Define GuC firmware version for Comet Lake
From GT perspective, Comet Lake is just Coffe Lake rev 5, but there is dedicated GuC firmware for it. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 789b3d7228a4..3519418b17ce 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -35,6 +35,7 @@ */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ fw_def(ICELAKE,0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ + fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/3] drm/i915/uc: Move uc firmware layout definitions to dedicated file
Generic uc firmware layout definitions are unlikely to change and
are separate to other GuC specific definitions.
v2: reordered
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
---
Documentation/gpu/i915.rst | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 67 -
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 78
4 files changed, 80 insertions(+), 68 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 3e233f9d675f..0e322688be5c 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -433,7 +433,7 @@ GuC
Firmware Layout
---
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
:doc: Firmware Layout
GuC-specific firmware loader
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 108b386c52ec..06a9bdfb0faf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -121,73 +121,6 @@
#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
-/**
- * DOC: Firmware Layout
- *
- * The GuC/HuC firmware layout looks like this::
- *
- *
+==+
- * | Firmware blob
|
- *
+===+===++++
- * | CSS header | uCode | RSA key | modulus | exponent
|
- *
+===+===++++
- * <-header size-> <---header size continued --->
- * <--- size --->
- * <-key size->
- *<-mod size->
- * <-exp size->
- *
- * The firmware may or may not have modulus key and exponent data. The header,
- * uCode and RSA signature are must-have components that will be used by
driver.
- * Length of each components, which is all in dwords, can be found in header.
- * In the case that modulus and exponent are not present in fw, a.k.a truncated
- * image, the length value still appears in header.
- *
- * Driver will do some basic fw size validation based on the following rules:
- *
- * 1. Header, uCode and RSA are must-have components.
- * 2. All firmware components, if they present, are in the sequence illustrated
- *in the layout table above.
- * 3. Length info of each component can be found in header, in dwords.
- * 4. Modulus and exponent key are not required by driver. They may not appear
- *in fw. So driver will load a truncated firmware in this case.
- *
- * The only difference between GuC and HuC firmwares is how the version
- * information is saved.
- */
-
-struct uc_css_header {
- u32 module_type;
- /* header_size includes all non-uCode bits, including css_header, rsa
-* key, modulus key and exponent data. */
- u32 header_size_dw;
- u32 header_version;
- u32 module_id;
- u32 module_vendor;
- u32 date;
-#define CSS_DATE_DAY (0xFF << 0)
-#define CSS_DATE_MONTH (0xFF << 8)
-#define CSS_DATE_YEAR (0x << 16)
- u32 size_dw; /* uCode plus header_size_dw */
- u32 key_size_dw;
- u32 modulus_size_dw;
- u32 exponent_size_dw;
- u32 time;
-#define CSS_TIME_HOUR (0xFF << 0)
-#define CSS_DATE_MIN (0xFF << 8)
-#define CSS_DATE_SEC (0x << 16)
- char username[8];
- char buildnumber[12];
- u32 sw_version;
-#define CSS_SW_VERSION_GUC_MAJOR (0xFF << 16)
-#define CSS_SW_VERSION_GUC_MINOR (0xFF << 8)
-#define CSS_SW_VERSION_GUC_PATCH (0xFF << 0)
-#define CSS_SW_VERSION_HUC_MAJOR (0x << 16)
-#define CSS_SW_VERSION_HUC_MINOR (0x << 0)
- u32 reserved[14];
- u32 header_info;
-} __packed;
-
/* Work item for submitting workloads into work queue of GuC. */
struct guc_wq_item {
u32 header;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 789b3d7228a4..168d368bcd3e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -27,6 +27,7 @@
#include
#include "intel_uc_fw.h"
+#include "intel_uc_fw_abi.h"
#include "i915_drv.h"
/*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
new file mode 100644
index ..e58d8c1
[Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Update drawing for firmware layout
Sphinx was rendering firmware layout as html table, but since
we want to add sizes relations switch to plain text graphics.
v2: also update text and do it before move (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
Documentation/gpu/i915.rst | 12
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 31 ++---
2 files changed, 20 insertions(+), 23 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c2173d120492..3e233f9d675f 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -430,6 +430,12 @@ WOPCM Layout
GuC
===
+Firmware Layout
+---
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+ :doc: Firmware Layout
+
GuC-specific firmware loader
@@ -445,12 +451,6 @@ GuC-based command submission
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
:internal:
-GuC Firmware Layout
-
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
- :doc: GuC Firmware Layout
-
GuC Address Space
-
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 30cca3a29323..108b386c52ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -122,23 +122,20 @@
#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
/**
- * DOC: GuC Firmware Layout
+ * DOC: Firmware Layout
*
- * The GuC firmware layout looks like this:
+ * The GuC/HuC firmware layout looks like this::
*
- * +---+
- * | uc_css_header |
- * | |
- * | contains major/minor version |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * | modulus key |
- * +---+
- * | exponent val |
- * +---+
+ *
+==+
+ * | Firmware blob
|
+ *
+===+===++++
+ * | CSS header | uCode | RSA key | modulus | exponent
|
+ *
+===+===++++
+ * <-header size-> <---header size continued --->
+ * <--- size --->
+ * <-key size->
+ *<-mod size->
+ * <-exp size->
*
* The firmware may or may not have modulus key and exponent data. The header,
* uCode and RSA signature are must-have components that will be used by
driver.
@@ -155,8 +152,8 @@
* 4. Modulus and exponent key are not required by driver. They may not appear
*in fw. So driver will load a truncated firmware in this case.
*
- * HuC firmware layout is same as GuC firmware.
- * Only HuC version information is saved in a different way.
+ * The only difference between GuC and HuC firmwares is how the version
+ * information is saved.
*/
struct uc_css_header {
--
2.19.2
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