Re: [Intel-gfx] [PATCH 20/34] xen: convert put_page() to put_user_page*()
On 02.08.19 04:19, john.hubb...@gmail.com wrote:
From: John Hubbard
For pages that were retained via get_user_pages*(), release those pages
via the new put_user_page*() routines, instead of via put_page() or
release_pages().
This is part a tree-wide conversion, as described in commit fc1d8e7cca2d
("mm: introduce put_user_page*(), placeholder versions").
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: xen-de...@lists.xenproject.org
Signed-off-by: John Hubbard
---
drivers/xen/gntdev.c | 5 +
drivers/xen/privcmd.c | 7 +--
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c
index 4c339c7e66e5..2586b3df2bb6 100644
--- a/drivers/xen/gntdev.c
+++ b/drivers/xen/gntdev.c
@@ -864,10 +864,7 @@ static int gntdev_get_page(struct gntdev_copy_batch
*batch, void __user *virt,
static void gntdev_put_pages(struct gntdev_copy_batch *batch)
{
- unsigned int i;
-
- for (i = 0; i < batch->nr_pages; i++)
- put_page(batch->pages[i]);
+ put_user_pages(batch->pages, batch->nr_pages);
batch->nr_pages = 0;
}
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index 2f5ce7230a43..29e461dbee2d 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/xen/privcmd.c
@@ -611,15 +611,10 @@ static int lock_pages(
static void unlock_pages(struct page *pages[], unsigned int nr_pages)
{
- unsigned int i;
-
if (!pages)
return;
- for (i = 0; i < nr_pages; i++) {
- if (pages[i])
- put_page(pages[i]);
- }
+ put_user_pages(pages, nr_pages);
You are not handling the case where pages[i] is NULL here. Or am I
missing a pending patch to put_user_pages() here?
Juergen
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Atomically acquire the gt_pm wakeref (rev4)
== Series Details == Series: drm/i915/pmu: Atomically acquire the gt_pm wakeref (rev4) URL : https://patchwork.freedesktop.org/series/64543/ State : success == Summary == CI Bug Log - changes from CI_DRM_6610 -> Patchwork_13845 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/ Known issues Here are the changes found in Patchwork_13845 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload-with-fault-injection: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#109483]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-mmap: - fi-byt-n2820: [PASS][7] -> [INCOMPLETE][8] ([fdo#102657] / [fdo#111276]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html - fi-pnv-d510:[PASS][9] -> [INCOMPLETE][10] ([fdo#110740] / [fdo#111276]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - fi-pnv-d510:[PASS][11] -> [INCOMPLETE][12] ([fdo#110740]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-pnv-d510/igt@prime_v...@basic-fence-read.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-pnv-d510/igt@prime_v...@basic-fence-read.html - fi-gdg-551: [PASS][13] -> [INCOMPLETE][14] ([fdo#108316]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-gdg-551/igt@prime_v...@basic-fence-read.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-gdg-551/igt@prime_v...@basic-fence-read.html - fi-icl-u3: [PASS][15] -> [DMESG-WARN][16] ([fdo#107724]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-icl-u3/igt@prime_v...@basic-fence-read.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-icl-u3/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-sync-default: - fi-bxt-dsi: [PASS][17] -> [FAIL][18] ([fdo#111277]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html Possible fixes * igt@gem_basic@create-close: - fi-skl-6770hq: [DMESG-WARN][19] ([fdo#105541]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-skl-6770hq/igt@gem_ba...@create-close.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-skl-6770hq/igt@gem_ba...@create-close.html * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][21] ([fdo#107718]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@prime_vgem@basic-busy-default: - fi-bxt-j4205: [FAIL][23] ([fdo#111277]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-bxt-j4205/igt@prime_v...@basic-busy-default.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-bxt-j4205/igt@prime_v...@basic-busy-default.html * igt@prime_vgem@basic-fence-mmap: - fi-elk-e7500: [INCOMPLETE][25] ([fdo#103989] / [fdo#111276]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6610/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13845/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Get transcoder power domain before reading its register
On Thu, 2019-08-01 at 17:41 -0700, Lucas De Marchi wrote:
> On Thu, Aug 01, 2019 at 04:28:11PM -0700, Jose Souza wrote:
> > When getting the pipes attached to encoder if it is not a eDP
> > encoder
> > it iterates over all pipes and read a transcoder register.
> > But it should not read a transcoder register before get its power
> > domain.
> >
> > It was not a issue in gens older than 12 because if it only had
> > port A connected it would be attached to EDP and it would skip all
> > the transcoders readout, if it had more than one port connected,
> > pipe B would cause PG3 to be on and it contains all other
> > transcoders.
> >
> > But on gen 12 there is no EDP transcoder so it is always iterating
> > over all pipes and if only one sink is connected, PG3 is kept off
> > and reading other transcoders registers would cause a
> > unclaimed read warning.
> >
> > So here getting the power domain of the transcoder only if it is
> > enabled, otherwise it is not connected to the DDI.
> >
> > Cc: Lucas De Marchi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index fb58845020dc..660bb001be35 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2015,6 +2015,12 @@ static void
> > intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
> > for_each_pipe(dev_priv, p) {
> > enum transcoder cpu_transcoder = (enum transcoder)p;
> > unsigned int port_mask, ddi_select;
> > + intel_wakeref_t trans_wakeref;
> > +
> > + trans_wakeref =
> > intel_display_power_get_if_enabled(dev_priv,
> > + POWE
> > R_DOMAIN_TRANSCODER(cpu_transcoder));
>
> And on Tiger Lake POWER_DOMAIN_TRANSCODER_B,
> POWER_DOMAIN_TRANSCODER_C
> and POWER_DOMAIN_TRANSCODER_D are on PW3. POWER_DOMAIN_TRANSCODER_A
> is
> on PW1.
>
> Looks correct.
>
> Reviewed-by: Lucas De Marchi
>
> Are the warnings now fixed?
With only eDP connected yes, we still have a few with eDP+HDMI.
>
> thanks
> Lucas De Marchi
>
>
>
>
> > + if (!trans_wakeref)
> > + continue;
> >
> > if (INTEL_GEN(dev_priv) >= 12) {
> > port_mask = TGL_TRANS_DDI_PORT_MASK;
> > @@ -2025,6 +2031,8 @@ static void
> > intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
> > }
> >
> > tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > + intel_display_power_put(dev_priv,
> > POWER_DOMAIN_TRANSCODER(cpu_transcoder),
> > + trans_wakeref);
> >
> > if ((tmp & port_mask) != ddi_select)
> > continue;
> > --
> > 2.22.0
> >
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to
On Thu, 2019-08-01 at 17:50 -0700, Lucas De Marchi wrote:
> On Thu, Aug 01, 2019 at 04:28:12PM -0700, Jose Souza wrote:
> > On TGL this register do not map directly to port, it was already
> > handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when
> > reading it.
> >
> > Cc: Lucas De Marchi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 --
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 9e4ee29fd0fc..b9526aa402f9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -10353,11 +10353,17 @@ static void
> > haswell_get_ddi_port_state(struct intel_crtc *crtc,
> >
> > tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config-
> > >cpu_transcoder));
> >
> > - if (INTEL_GEN(dev_priv) >= 12)
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
> > TGL_TRANS_DDI_PORT_SHIFT;
> > - else
> > + /*
> > +* Register values: none = 0, DDIA = 1... while PORT_A
> > = 0...
> > +* so subtract one
> > +*/
> > + port--;
>
> port = TGL_PORT_TRANS_DDI_SELECT(tmp)
>
> and put the macro right below the TGL_TRANS_DDI_SELECT_PORT() so the
> intent is explicit and we don't forget again. Then you can remove the
> comment.
I liked the idea of add a macro but not sure about this name, going to
think in a better one.
>
> any chance of tmp being none and the -1 underflow?
I guess the intention of have 0 = none is DP MST but we are programing
the DDI_SELECT even on slaves, if we stop to do that we would need to
do changes in this function.
>
> Lucas De Marchi
>
>
> > + } else {
> > port = (tmp & TRANS_DDI_PORT_MASK) >>
> > TRANS_DDI_PORT_SHIFT;
> > + }
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > icelake_get_ddi_pll(dev_priv, port, pipe_config);
> > --
> > 2.22.0
> >
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to
On Thu, Aug 01, 2019 at 04:28:12PM -0700, Jose Souza wrote:
On TGL this register do not map directly to port, it was already
handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when
reading it.
Cc: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9e4ee29fd0fc..b9526aa402f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10353,11 +10353,17 @@ static void haswell_get_ddi_port_state(struct
intel_crtc *crtc,
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
- if (INTEL_GEN(dev_priv) >= 12)
+ if (INTEL_GEN(dev_priv) >= 12) {
port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
TGL_TRANS_DDI_PORT_SHIFT;
- else
+ /*
+* Register values: none = 0, DDIA = 1... while PORT_A = 0...
+* so subtract one
+*/
+ port--;
port = TGL_PORT_TRANS_DDI_SELECT(tmp)
and put the macro right below the TGL_TRANS_DDI_SELECT_PORT() so the
intent is explicit and we don't forget again. Then you can remove the
comment.
any chance of tmp being none and the -1 underflow?
Lucas De Marchi
+ } else {
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
+ }
if (INTEL_GEN(dev_priv) >= 11)
icelake_get_ddi_pll(dev_priv, port, pipe_config);
--
2.22.0
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Get transcoder power domain before reading its register
On Thu, Aug 01, 2019 at 04:28:11PM -0700, Jose Souza wrote:
When getting the pipes attached to encoder if it is not a eDP encoder
it iterates over all pipes and read a transcoder register.
But it should not read a transcoder register before get its power
domain.
It was not a issue in gens older than 12 because if it only had
port A connected it would be attached to EDP and it would skip all
the transcoders readout, if it had more than one port connected,
pipe B would cause PG3 to be on and it contains all other
transcoders.
But on gen 12 there is no EDP transcoder so it is always iterating
over all pipes and if only one sink is connected, PG3 is kept off
and reading other transcoders registers would cause a
unclaimed read warning.
So here getting the power domain of the transcoder only if it is
enabled, otherwise it is not connected to the DDI.
Cc: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index fb58845020dc..660bb001be35 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2015,6 +2015,12 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
for_each_pipe(dev_priv, p) {
enum transcoder cpu_transcoder = (enum transcoder)p;
unsigned int port_mask, ddi_select;
+ intel_wakeref_t trans_wakeref;
+
+ trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
+
POWER_DOMAIN_TRANSCODER(cpu_transcoder));
And on Tiger Lake POWER_DOMAIN_TRANSCODER_B, POWER_DOMAIN_TRANSCODER_C
and POWER_DOMAIN_TRANSCODER_D are on PW3. POWER_DOMAIN_TRANSCODER_A is
on PW1.
Looks correct.
Reviewed-by: Lucas De Marchi
Are the warnings now fixed?
thanks
Lucas De Marchi
+ if (!trans_wakeref)
+ continue;
if (INTEL_GEN(dev_priv) >= 12) {
port_mask = TGL_TRANS_DDI_PORT_MASK;
@@ -2025,6 +2031,8 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
}
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ intel_display_power_put(dev_priv,
POWER_DOMAIN_TRANSCODER(cpu_transcoder),
+ trans_wakeref);
if ((tmp & port_mask) != ddi_select)
continue;
--
2.22.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Get transcoder power domain before reading its register
== Series Details ==
Series: series starting with [1/2] drm/i915: Get transcoder power domain before
reading its register
URL : https://patchwork.freedesktop.org/series/64571/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6608 -> Patchwork_13844
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/
Known issues
Here are the changes found in Patchwork_13844 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#108569])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278])
+2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [PASS][5] -> [WARN][6] ([fdo#109380])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109483])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [PASS][9] -> [SKIP][10] ([fdo#109271]) +23 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@prime_vgem@basic-fence-read:
- fi-bsw-kefka: [PASS][11] -> [INCOMPLETE][12] ([fdo#111278])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-sync-default:
- fi-bxt-j4205: [PASS][13] -> [FAIL][14] ([fdo#111277])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
Possible fixes
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-mmap:
- fi-byt-j1900: [INCOMPLETE][17] ([fdo#102657] / [fdo#111276]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-byt-j1900/igt@prime_v...@basic-fence-mmap.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-byt-j1900/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- fi-pnv-d510:[INCOMPLETE][19] ([fdo#110740]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-pnv-d510/igt@prime_v...@basic-fence-read.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-pnv-d510/igt@prime_v...@basic-fence-read.html
- fi-gdg-551: [INCOMPLETE][21] ([fdo#108316]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-gdg-551/igt@prime_v...@basic-fence-read.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-gdg-551/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-wait-default:
- fi-bxt-j4205: [FAIL][23] ([fdo#111277]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6608/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13844/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#107713]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Get transcoder power domain before reading its register
== Series Details == Series: series starting with [1/2] drm/i915: Get transcoder power domain before reading its register URL : https://patchwork.freedesktop.org/series/64571/ State : warning == Summary == $ dim checkpatch origin/drm-tip bfb6c8381b43 drm/i915: Get transcoder power domain before reading its register -:43: WARNING:LONG_LINE: line over 100 characters #43: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:2021: + POWER_DOMAIN_TRANSCODER(cpu_transcoder)); total: 0 errors, 1 warnings, 0 checks, 20 lines checked c8a8fef007fe drm/i915/tgl: Fix the read of the DDI that transcoder is attached to ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 6/8] drm/i915/display/icl: Enable master-slaves in trans port sync mode in correct order
On Thu, Aug 01, 2019 at 05:07:48PM +0200, Maarten Lankhorst wrote:
> Op 01-08-2019 om 01:24 schreef Manasi Navare:
> > Thanks Maarten for your review comments, please see my responses/questions
> > below:
> >
> > On Tue, Jul 30, 2019 at 12:53:30PM +0200, Maarten Lankhorst wrote:
> >> Op 24-06-2019 om 23:08 schreef Manasi Navare:
> >>> As per the display enable sequence, we need to follow the enable sequence
> >>> for slaves first with DP_TP_CTL set to Idle and configure the transcoder
> >>> port sync register to select the corersponding master, then follow the
> >>> enable sequence for master leaving DP_TP_CTL to idle.
> >>> At this point the transcoder port sync mode is configured and enabled
> >>> and the Vblanks of both ports are synchronized so then set DP_TP_CTL
> >>> for the slave and master to Normal and do post crtc enable updates.
> >>>
> >>> v2:
> >>> * Create a icl_update_crtcs hook (Maarten, Danvet)
> >>> * This sequence only for CRTCs in trans port sync mode (Maarten)
> >>>
> >>> Cc: Daniel Vetter
> >>> Cc: Ville Syrjälä
> >>> Cc: Maarten Lankhorst
> >>> Cc: Matt Roper
> >>> Signed-off-by: Manasi Navare
> >>> ---
> >>> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> >>> drivers/gpu/drm/i915/display/intel_display.c | 217 ++-
> >>> drivers/gpu/drm/i915/display/intel_display.h | 4 +
> >>> 3 files changed, 221 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> >>> b/drivers/gpu/drm/i915/display/intel_ddi.c
> >>> index 7925a176f900..bceb7e4b1877 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >>> @@ -3154,7 +3154,8 @@ static void intel_ddi_pre_enable_dp(struct
> >>> intel_encoder *encoder,
> >>> true);
> >>> intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> >>> intel_dp_start_link_train(intel_dp);
> >>> - if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> >>> + if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
> >>> + !is_trans_port_sync_mode(crtc_state))
> >>> intel_dp_stop_link_train(intel_dp);
> >>>
> >>> intel_ddi_enable_fec(encoder, crtc_state);
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >>> b/drivers/gpu/drm/i915/display/intel_display.c
> >>> index 7156b1b4c6c5..f88d3a929e36 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>> @@ -520,6 +520,26 @@ needs_modeset(const struct drm_crtc_state *state)
> >>> return drm_atomic_crtc_needs_modeset(state);
> >>> }
> >>>
> >>> +bool
> >>> +is_trans_port_sync_mode(const struct intel_crtc_state *state)
> >>> +{
> >>> + return (state->master_transcoder != INVALID_TRANSCODER ||
> >>> + state->sync_mode_slaves_mask);
> >>> +}
> >>> +
> >>> +static bool
> >>> +is_trans_port_sync_slave(const struct intel_crtc_state *state)
> >>> +{
> >>> + return state->master_transcoder != INVALID_TRANSCODER;
> >>> +}
> >>> +
> >>> +static bool
> >>> +is_trans_port_sync_master(const struct intel_crtc_state *state)
> >>> +{
> >>> + return (state->master_transcoder == INVALID_TRANSCODER &&
> >>> + state->sync_mode_slaves_mask);
> >>> +}
> >>> +
> >>> /*
> >>> * Platform specific helpers to calculate the port PLL loopback-
> >>> (clock.m),
> >>> * and post-divider (clock.p) values, pre- (clock.vco) and post-divided
> >>> fast
> >>> @@ -13944,9 +13964,200 @@ static void skl_commit_modeset_enables(struct
> >>> drm_atomic_state *state)
> >>> progress = true;
> >>> }
> >>> } while (progress);
> >>> +}
> >>>
> >>> +static void icl_commit_modeset_enables(struct drm_atomic_state *state)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> >>> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> >>> + struct drm_crtc *crtc;
> >>> + struct intel_crtc *intel_crtc;
> >>> + struct drm_crtc_state *old_crtc_state, *new_crtc_state;
> >>> + struct intel_crtc_state *cstate;
> >>> + unsigned int updated = 0;
> >>> + bool progress;
> >>> + enum pipe pipe;
> >>> + int i;
> >>> + u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> >>> + u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
> >>> + struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
> >> Add old_entries as well, merge master + slave
> > I didnt understand what you meant by merge master+slaves? You mean add also
> > the
> > master and slave that are already enabled?
>
> Instead of 2 separate allocations, only have a single allocation that
> contains the slave and master
> ddb during modeset/fastset.
So I will call this master_slave_entries[I915_MAX_PIPES] and have a separate
for loop for
ddb allocations of the master and slaves that involved in the current modeset
correct?
if (new_crtc_state->active && needs_modeset() && master_or_slave)
Add to master_slave_entries
Sounds good?
[Intel-gfx] [CI] drm/i915/pmu: Atomically acquire the gt_pm wakeref
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
v2: Take engine->wakeref for engine sampling
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 8 +-
drivers/gpu/drm/i915/i915_pmu.c | 40 ---
2 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 527894fe1345..e8a18d4b27c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -9,7 +9,8 @@
#include
-struct intel_gt;
+#include "intel_gt_types.h"
+#include "intel_wakeref.h"
enum {
INTEL_GT_UNPARK,
@@ -19,6 +20,11 @@ enum {
void intel_gt_pm_get(struct intel_gt *gt);
void intel_gt_pm_put(struct intel_gt *gt);
+static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
+{
+ return intel_wakeref_get_if_active(>wakeref);
+}
+
void intel_gt_pm_init_early(struct intel_gt *gt);
void intel_gt_sanitize(struct intel_gt *gt, bool force);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e0e0180bca7c..c2e5f6d5c1e0 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,8 @@
#include
#include "gt/intel_engine.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
#include "i915_pmu.h"
@@ -165,30 +167,26 @@ static void
engines_sample(struct intel_gt *gt, unsigned int period_ns)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- intel_wakeref_t wakeref;
- unsigned long flags;
if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
- wakeref = 0;
- if (READ_ONCE(gt->awake))
- wakeref = intel_runtime_pm_get_if_in_use(>runtime_pm);
- if (!wakeref)
- return;
-
- spin_lock_irqsave(>lock, flags);
for_each_engine(engine, i915, id) {
struct intel_engine_pmu *pmu = >pmu;
+ unsigned long flags;
bool busy;
u32 val;
+ if (!intel_engine_pm_get_if_awake(engine))
+ continue;
+
+ spin_lock_irqsave(>uncore->lock, flags);
+
val = ENGINE_READ_FW(engine, RING_CTL);
if (val == 0) /* powerwell off => engine idle */
- continue;
+ goto skip;
if (val & RING_WAIT)
add_sample(>sample[I915_SAMPLE_WAIT], period_ns);
@@ -209,10 +207,11 @@ engines_sample(struct intel_gt *gt, unsigned int
period_ns)
}
if (busy)
add_sample(>sample[I915_SAMPLE_BUSY], period_ns);
- }
- spin_unlock_irqrestore(>lock, flags);
- intel_runtime_pm_put(>runtime_pm, wakeref);
+skip:
+ spin_unlock_irqrestore(>uncore->lock, flags);
+ intel_engine_pm_put(engine);
+ }
}
static void
@@ -232,15 +231,10 @@ frequency_sample(struct intel_gt *gt, unsigned int
period_ns)
u32 val;
val = i915->gt_pm.rps.cur_freq;
- if (gt->awake) {
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm_if_in_use(>runtime_pm,
- wakeref) {
- val = intel_uncore_read_notrace(uncore,
- GEN6_RPSTAT1);
- val = intel_get_cagf(i915, val);
- }
+ if (intel_gt_pm_get_if_awake(gt)) {
+ val = intel_uncore_read_notrace(uncore, GEN6_RPSTAT1);
+ val = intel_get_cagf(i915, val);
+ intel_gt_pm_put(gt);
}
add_sample_mult(>sample[__I915_SAMPLE_FREQ_ACT],
--
2.23.0.rc0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to
On TGL this register do not map directly to port, it was already
handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when
reading it.
Cc: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9e4ee29fd0fc..b9526aa402f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10353,11 +10353,17 @@ static void haswell_get_ddi_port_state(struct
intel_crtc *crtc,
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
- if (INTEL_GEN(dev_priv) >= 12)
+ if (INTEL_GEN(dev_priv) >= 12) {
port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
TGL_TRANS_DDI_PORT_SHIFT;
- else
+ /*
+* Register values: none = 0, DDIA = 1... while PORT_A = 0...
+* so subtract one
+*/
+ port--;
+ } else {
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
+ }
if (INTEL_GEN(dev_priv) >= 11)
icelake_get_ddi_pll(dev_priv, port, pipe_config);
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Get transcoder power domain before reading its register
When getting the pipes attached to encoder if it is not a eDP encoder
it iterates over all pipes and read a transcoder register.
But it should not read a transcoder register before get its power
domain.
It was not a issue in gens older than 12 because if it only had
port A connected it would be attached to EDP and it would skip all
the transcoders readout, if it had more than one port connected,
pipe B would cause PG3 to be on and it contains all other
transcoders.
But on gen 12 there is no EDP transcoder so it is always iterating
over all pipes and if only one sink is connected, PG3 is kept off
and reading other transcoders registers would cause a
unclaimed read warning.
So here getting the power domain of the transcoder only if it is
enabled, otherwise it is not connected to the DDI.
Cc: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index fb58845020dc..660bb001be35 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2015,6 +2015,12 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
for_each_pipe(dev_priv, p) {
enum transcoder cpu_transcoder = (enum transcoder)p;
unsigned int port_mask, ddi_select;
+ intel_wakeref_t trans_wakeref;
+
+ trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
+
POWER_DOMAIN_TRANSCODER(cpu_transcoder));
+ if (!trans_wakeref)
+ continue;
if (INTEL_GEN(dev_priv) >= 12) {
port_mask = TGL_TRANS_DDI_PORT_MASK;
@@ -2025,6 +2031,8 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
}
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ intel_display_power_put(dev_priv,
POWER_DOMAIN_TRANSCODER(cpu_transcoder),
+ trans_wakeref);
if ((tmp & port_mask) != ddi_select)
continue;
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for add more probe failures (rev5)
== Series Details == Series: add more probe failures (rev5) URL : https://patchwork.freedesktop.org/series/64390/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6607 -> Patchwork_13843 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13843 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13843, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13843: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-guc: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-skl-guc/igt@i915_module_l...@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-skl-guc/igt@i915_module_l...@reload-with-fault-injection.html - fi-kbl-guc: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-kbl-guc/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-kbl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@runner@aborted: - fi-cfl-guc: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-cfl-guc/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_13843 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-wait-default: - fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][10] -> [DMESG-WARN][11] ([fdo#102614]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-mmap: - fi-bwr-2160:[PASS][12] -> [INCOMPLETE][13] ([fdo#111276]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-bwr-2160/igt@prime_v...@basic-fence-mmap.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-bwr-2160/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - fi-bsw-kefka: [PASS][14] -> [INCOMPLETE][15] ([fdo#111278]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-sync-default: - fi-bxt-j4205: [PASS][16] -> [FAIL][17] ([fdo#111277]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html * igt@prime_vgem@basic-write: - fi-gdg-551: [PASS][18] -> [FAIL][19] ([fdo#111276]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-gdg-551/igt@prime_v...@basic-write.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-gdg-551/igt@prime_v...@basic-write.html Possible fixes * igt@gem_mmap_gtt@basic-small-bo-tiledx: - fi-glk-dsi: [INCOMPLETE][20] ([fdo#103359] / [k.org#198133]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-glk-dsi/igt@gem_mmap_...@basic-small-bo-tiledx.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-glk-dsi/igt@gem_mmap_...@basic-small-bo-tiledx.html * igt@i915_pm_rpm@module-reload: - fi-skl-6260u: [INCOMPLETE][22] ([fdo#107807]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-skl-6260u/igt@i915_pm_...@module-reload.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13843/fi-skl-6260u/igt@i915_pm_...@module-reload.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
== Series Details ==
Series: series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm
wakeref
URL : https://patchwork.freedesktop.org/series/64562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6607 -> Patchwork_13842
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/
Known issues
Here are the changes found in Patchwork_13842 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_vgem@basic-fence-read:
- fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2] ([fdo#111278])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
- fi-pnv-d510:[PASS][3] -> [INCOMPLETE][4] ([fdo#110740])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-pnv-d510/igt@prime_v...@basic-fence-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-pnv-d510/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-sync-default:
- fi-bxt-j4205: [PASS][5] -> [FAIL][6] ([fdo#111277]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
* igt@prime_vgem@basic-write:
- fi-gdg-551: [PASS][7] -> [FAIL][8] ([fdo#111276])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-gdg-551/igt@prime_v...@basic-write.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-gdg-551/igt@prime_v...@basic-write.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- fi-glk-dsi: [INCOMPLETE][11] ([fdo#103359] / [k.org#198133]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-glk-dsi/igt@gem_mmap_...@basic-small-bo-tiledx.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-glk-dsi/igt@gem_mmap_...@basic-small-bo-tiledx.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6260u: [INCOMPLETE][13] ([fdo#107807]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-skl-6260u/igt@i915_pm_...@module-reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-skl-6260u/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_reset:
- fi-icl-u3: [INCOMPLETE][15] ([fdo#107713]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-icl-u3/igt@i915_selftest@live_reset.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-icl-u3/igt@i915_selftest@live_reset.html
* igt@prime_vgem@basic-fence-mmap:
- fi-byt-n2820: [INCOMPLETE][17] ([fdo#102657] / [fdo#111276]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html
- fi-elk-e7500: [INCOMPLETE][19] ([fdo#103989] / [fdo#111276]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][21] ([fdo#109271]) -> [FAIL][22] ([fdo#110829])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]:
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Flush extra hard after writing relocations through the GTT
On Tue, Jul 30, 2019 at 12:21:51PM +0100, Chris Wilson wrote:
> Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
> flush for pwrite_gtt") was that we needed to our full write barrier
> before changing the GGTT PTE to ensure that our indirect writes through
> the GTT landed before the PTE changed (and the writes end up in a
> different page). That also applies to our GGTT relocation path.
>
> Signed-off-by: Chris Wilson
> Cc: sta...@vger.kernel.org
Reviewed-by: Prathap Kumar Valsan
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 8a2047c4e7c3..01901dad33f7 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1019,11 +1019,12 @@ static void reloc_cache_reset(struct reloc_cache
> *cache)
> kunmap_atomic(vaddr);
> i915_gem_object_finish_access((struct drm_i915_gem_object
> *)cache->node.mm);
> } else {
> - wmb();
> + struct i915_ggtt *ggtt = cache_to_ggtt(cache);
> +
> + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> io_mapping_unmap_atomic((void __iomem *)vaddr);
> - if (cache->node.allocated) {
> - struct i915_ggtt *ggtt = cache_to_ggtt(cache);
>
> + if (cache->node.allocated) {
> ggtt->vm.clear_range(>vm,
>cache->node.start,
>cache->node.size);
> @@ -1078,6 +1079,7 @@ static void *reloc_iomap(struct drm_i915_gem_object
> *obj,
> void *vaddr;
>
> if (cache->vaddr) {
> + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> io_mapping_unmap_atomic((void __force __iomem *)
> unmask_page(cache->vaddr));
> } else {
> struct i915_vma *vma;
> @@ -1119,7 +1121,6 @@ static void *reloc_iomap(struct drm_i915_gem_object
> *obj,
>
> offset = cache->node.start;
> if (cache->node.allocated) {
> - wmb();
> ggtt->vm.insert_page(>vm,
>i915_gem_object_get_dma_address(obj, page),
>offset, I915_CACHE_NONE, 0);
> --
> 2.22.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Force spin-batch to cause a hang as required
== Series Details == Series: Force spin-batch to cause a hang as required URL : https://patchwork.freedesktop.org/series/64495/ State : success == Summary == CI Bug Log - changes from CI_DRM_6590_full -> IGTPW_3311_full Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/64495/revisions/1/mbox/ Known issues Here are the changes found in IGTPW_3311_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-fd: - shard-apl: ([PASS][1], [PASS][2]) -> ([DMESG-WARN][3], [PASS][4]) ([fdo#108566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-apl2/igt@gem_workarou...@suspend-resume-fd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-apl1/igt@gem_workarou...@suspend-resume-fd.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-apl6/igt@gem_workarou...@suspend-resume-fd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-apl7/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_hangman@hangcheck-unterminated: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-iclb1/igt@i915_hang...@hangcheck-unterminated.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-iclb1/igt@i915_hang...@hangcheck-unterminated.html * igt@i915_suspend@debugfs-reader: - shard-apl: ([PASS][7], [PASS][8]) -> ([DMESG-WARN][9], [DMESG-WARN][10]) ([fdo#108566]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-apl3/igt@i915_susp...@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-apl5/igt@i915_susp...@debugfs-reader.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-apl2/igt@i915_susp...@debugfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-apl4/igt@i915_susp...@debugfs-reader.html - shard-snb: ([PASS][11], [PASS][12]) -> ([PASS][13], [DMESG-WARN][14]) ([fdo#102365]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-snb1/igt@i915_susp...@debugfs-reader.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-snb7/igt@i915_susp...@debugfs-reader.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-snb7/igt@i915_susp...@debugfs-reader.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-snb1/igt@i915_susp...@debugfs-reader.html * igt@kms_atomic@plane_overlay_legacy: - shard-snb: ([PASS][15], [PASS][16]) -> ([PASS][17], [SKIP][18]) ([fdo#109271]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-snb5/igt@kms_atomic@plane_overlay_legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-snb4/igt@kms_atomic@plane_overlay_legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-snb6/igt@kms_atomic@plane_overlay_legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-snb4/igt@kms_atomic@plane_overlay_legacy.html * igt@kms_atomic_transition@plane-all-modeset-transition: - shard-hsw: ([PASS][19], [PASS][20]) -> ([DMESG-WARN][21], [PASS][22]) ([fdo#102614]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-hsw4/igt@kms_atomic_transit...@plane-all-modeset-transition.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-hsw8/igt@kms_atomic_transit...@plane-all-modeset-transition.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-hsw5/igt@kms_atomic_transit...@plane-all-modeset-transition.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-hsw4/igt@kms_atomic_transit...@plane-all-modeset-transition.html * igt@kms_busy@extended-pageflip-hang-newfb-render-a: - shard-snb: ([PASS][23], [PASS][24]) -> ([SKIP][25], [PASS][26]) ([fdo#109271] / [fdo#109278]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-snb6/igt@kms_b...@extended-pageflip-hang-newfb-render-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-snb2/igt@kms_b...@extended-pageflip-hang-newfb-render-a.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-snb4/igt@kms_b...@extended-pageflip-hang-newfb-render-a.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3311/shard-snb6/igt@kms_b...@extended-pageflip-hang-newfb-render-a.html * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: - shard-glk: [PASS][27] -> ([PASS][28], [FAIL][29]) ([fdo#104873]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6590/shard-glk4/igt@kms_cursor_leg...@2x-flip-vs-cursor-atomic.html [28]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/pmu: Make more struct i915_pmu centric
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/pmu: Make more struct i915_pmu
centric
URL : https://patchwork.freedesktop.org/series/64557/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6606 -> Patchwork_13841
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/
Known issues
Here are the changes found in Patchwork_13841 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#108840])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-icl-dsi/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@prime_vgem@basic-busy-default:
- fi-bsw-kefka: [PASS][5] -> [FAIL][6] ([fdo#111277])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-bsw-kefka/igt@prime_v...@basic-busy-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-bsw-kefka/igt@prime_v...@basic-busy-default.html
- fi-bxt-j4205: [PASS][7] -> [FAIL][8] ([fdo#111277])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-bxt-j4205/igt@prime_v...@basic-busy-default.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-bxt-j4205/igt@prime_v...@basic-busy-default.html
* igt@prime_vgem@basic-fence-mmap:
- fi-byt-j1900: [PASS][9] -> [INCOMPLETE][10] ([fdo#102657] /
[fdo#111276])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-byt-j1900/igt@prime_v...@basic-fence-mmap.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-byt-j1900/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- fi-gdg-551: [PASS][11] -> [INCOMPLETE][12] ([fdo#108316])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-gdg-551/igt@prime_v...@basic-fence-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-gdg-551/igt@prime_v...@basic-fence-read.html
- fi-bwr-2160:[PASS][13] -> [INCOMPLETE][14] ([fdo#111278])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-write:
- fi-icl-u3: [PASS][15] -> [DMESG-WARN][16] ([fdo#107724])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-icl-u3/igt@prime_v...@basic-write.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-icl-u3/igt@prime_v...@basic-write.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u2: [INCOMPLETE][17] ([fdo#107713]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][19] ([fdo#08]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][21] ([fdo#109271] / [fdo#109278]) ->
[PASS][22] +2 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [SKIP][23] ([fdo#109271] / [fdo#109278]) ->
[PASS][24] +2 similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13841/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][25] ([fdo#109380]) -> [PASS][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6606/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[26]:
[Intel-gfx] [CI 1/3] drm/i915: Add i915 to i915_inject_probe_failure
With i915 added to i915_inject_probe_failure we can use dedicated
printk when injecting artificial load failure.
Also make this function look like other i915 functions that return
error code and make it more flexible to return any provided error
code instead of previously assumed -ENODEV.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/display/intel_connector.c| 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 27 ++-
drivers/gpu/drm/i915/i915_drv.h | 12 +
drivers/gpu/drm/i915/i915_gem.c | 10 +++
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
drivers/gpu/drm/i915/intel_wopcm.c| 2 +-
9 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c
b/drivers/gpu/drm/i915/display/intel_connector.c
index d0163d86c42a..cf8823ce9606 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -118,7 +118,7 @@ int intel_connector_register(struct drm_connector
*connector)
if (ret)
goto err;
- if (i915_inject_probe_failure()) {
+ if (i915_inject_probe_failure(to_i915(connector->dev))) {
ret = -EFAULT;
goto err_backlight;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 65cbf1d9118d..8bd9a9adf4a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -426,7 +426,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
WARN_ON(engine_mask &
GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(i915))
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 79f89d348196..402ada99c385 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -83,19 +83,20 @@ static struct drm_driver driver;
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
static unsigned int i915_probe_fail_count;
-bool __i915_inject_probe_failure(const char *func, int line)
+int __i915_inject_load_error(struct drm_i915_private *i915, int err,
+const char *func, int line)
{
if (i915_probe_fail_count >= i915_modparams.inject_load_failure)
- return false;
+ return 0;
- if (++i915_probe_fail_count == i915_modparams.inject_load_failure) {
- DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
-i915_modparams.inject_load_failure, func, line);
- i915_modparams.inject_load_failure = 0;
- return true;
- }
+ if (++i915_probe_fail_count < i915_modparams.inject_load_failure)
+ return 0;
- return false;
+ __i915_printk(i915, KERN_INFO,
+ "Injecting failure %d at checkpoint %u [%s:%d]\n",
+ err, i915_modparams.inject_load_failure, func, line);
+ i915_modparams.inject_load_failure = 0;
+ return err;
}
bool i915_error_injected(void)
@@ -687,7 +688,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
struct pci_dev *pdev = dev_priv->drm.pdev;
int ret;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
if (HAS_DISPLAY(dev_priv)) {
@@ -894,7 +895,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
{
int ret = 0;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
intel_device_info_subplatform_init(dev_priv);
@@ -985,7 +986,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
{
int ret;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
if (i915_get_bridge_dev(dev_priv))
@@ -1530,7 +1531,7 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
struct pci_dev *pdev = dev_priv->drm.pdev;
int ret;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
intel_device_info_runtime_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74ab76247018..9e9085b9067b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -122,19 +122,21 @@
#if
[Intel-gfx] [CI 0/3] add more probe failures
v3: fix Gen9 issue discovered by the v2 v4: rebased Michal Wajdeczko (3): drm/i915: Add i915 to i915_inject_probe_failure drm/i915/uc: Inject probe errors into intel_uc_init_hw drm/i915/wopcm: Don't fail on WOPCM partitioning failure .../gpu/drm/i915/display/intel_connector.c| 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 +++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 29 +++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 drivers/gpu/drm/i915/i915_drv.c | 27 + drivers/gpu/drm/i915/i915_drv.h | 12 drivers/gpu/drm/i915/i915_gem.c | 18 --- drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/intel_gvt.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 2 +- drivers/gpu/drm/i915/intel_wopcm.c| 30 +-- drivers/gpu/drm/i915/intel_wopcm.h| 2 +- 13 files changed, 82 insertions(+), 55 deletions(-) -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/3] drm/i915/wopcm: Don't fail on WOPCM partitioning failure
We don't have to immediately fail on WOPCM partitioning, we can wait
until we will start programming WOPCM registers. This should give us
more options if we decide to restore fallback in case of GuC failures.
v3: rebased
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 5 +
drivers/gpu/drm/i915/i915_gem.c | 6 +-
drivers/gpu/drm/i915/intel_wopcm.c| 28 +--
drivers/gpu/drm/i915/intel_wopcm.h| 2 +-
4 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index c4b015b0287e..6e2f8f010800 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -380,6 +380,11 @@ static int uc_init_wopcm(struct intel_uc *uc)
u32 mask;
int err;
+ if (unlikely(!base || !size)) {
+ i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ return -E2BIG;
+ }
+
GEM_BUG_ON(!intel_uc_supports_guc(uc));
GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2436cd598e6e..deaca3c2416d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1441,10 +1441,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
return ret;
intel_uc_fetch_firmwares(_priv->gt.uc);
-
- ret = intel_wopcm_init(_priv->wopcm);
- if (ret)
- goto err_uc_fw;
+ intel_wopcm_init(_priv->wopcm);
/* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -1568,7 +1565,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-err_uc_fw:
intel_uc_cleanup_firmwares(_priv->gt.uc);
if (ret != -EIO) {
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 291881937d97..4c22143ee84f 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -156,12 +156,10 @@ static inline int check_hw_restriction(struct
drm_i915_private *i915,
* This function will partition WOPCM space based on GuC and HuC firmware sizes
* and will allocate max remaining for use by GuC. This function will also
* enforce platform dependent hardware restrictions on GuC WOPCM offset and
- * size. It will fail the WOPCM init if any of these checks were failed, so
that
- * the following GuC firmware uploading would be aborted.
- *
- * Return: 0 on success, non-zero error code on failure.
+ * size. It will fail the WOPCM init if any of these checks fail, so that the
+ * following WOPCM registers setup and GuC firmware uploading would be aborted.
*/
-int intel_wopcm_init(struct intel_wopcm *wopcm)
+void intel_wopcm_init(struct intel_wopcm *wopcm)
{
struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
u32 guc_fw_size = intel_uc_fw_get_upload_size(>gt.uc.guc.fw);
@@ -173,23 +171,25 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
int err;
if (!USES_GUC(i915))
- return 0;
+ return;
GEM_BUG_ON(!wopcm->size);
+ GEM_BUG_ON(wopcm->guc.base);
+ GEM_BUG_ON(wopcm->guc.size);
if (i915_inject_probe_failure(i915))
- return -E2BIG;
+ return;
if (guc_fw_size >= wopcm->size) {
DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
guc_fw_size / 1024);
- return -E2BIG;
+ return;
}
if (huc_fw_size >= wopcm->size) {
DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
huc_fw_size / 1024);
- return -E2BIG;
+ return;
}
guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
@@ -197,7 +197,7 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
guc_wopcm_base / 1024);
- return -E2BIG;
+ return;
}
guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
@@ -211,16 +211,16 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
(guc_fw_size + guc_wopcm_rsvd) / 1024,
guc_wopcm_size / 1024);
- return -E2BIG;
+ return;
}
err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
[Intel-gfx] [CI 2/3] drm/i915/uc: Inject probe errors into intel_uc_init_hw
Inject probe errors into intel_uc_init_hw to make sure we
correctly handle any uC initialization failure.
To avoid complains from CI about injected errors use
i915_probe_error to lower message level.
v2: _sanitize instead _reset to correctly handle Gen9 retries
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson #v1
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 24
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 +
drivers/gpu/drm/i915/i915_gem.c | 2 +-
4 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d642b167a389..2a30956dc37b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -139,6 +139,10 @@ int intel_huc_auth(struct intel_huc *huc)
GEM_BUG_ON(!intel_uc_fw_is_loaded(>fw));
GEM_BUG_ON(intel_huc_is_authenticated(huc));
+ ret = i915_inject_load_error(gt->i915, -ENXIO);
+ if (ret)
+ goto fail;
+
ret = intel_guc_auth_huc(guc,
intel_guc_ggtt_offset(guc, huc->rsa_data));
if (ret) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index d1b08b28b1ad..c4b015b0287e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -41,6 +41,10 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
int ret;
u32 guc_status;
+ ret = i915_inject_load_error(gt->i915, -ENXIO);
+ if (ret)
+ return ret;
+
ret = intel_reset_guc(gt);
if (ret) {
DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
@@ -209,6 +213,10 @@ static int guc_enable_communication(struct intel_guc *guc)
GEM_BUG_ON(guc_communication_enabled(guc));
+ ret = i915_inject_load_error(i915, -ENXIO);
+ if (ret)
+ return ret;
+
ret = intel_guc_ct_enable(>ct);
if (ret)
return ret;
@@ -340,7 +348,7 @@ void intel_uc_fini(struct intel_uc *uc)
intel_guc_fini(guc);
}
-static void __uc_sanitize(struct intel_uc *uc)
+static int __uc_sanitize(struct intel_uc *uc)
{
struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
@@ -350,7 +358,7 @@ static void __uc_sanitize(struct intel_uc *uc)
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
- __intel_uc_reset_hw(uc);
+ return __intel_uc_reset_hw(uc);
}
void intel_uc_sanitize(struct intel_uc *uc)
@@ -378,6 +386,10 @@ static int uc_init_wopcm(struct intel_uc *uc)
GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
+ err = i915_inject_load_error(gt->i915, -ENXIO);
+ if (err)
+ return err;
+
mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
size | GUC_WOPCM_SIZE_LOCKED);
@@ -434,7 +446,7 @@ int intel_uc_init_hw(struct intel_uc *uc)
* Always reset the GuC just before (re)loading, so
* that the state and timing are fairly predictable
*/
- ret = __intel_uc_reset_hw(uc);
+ ret = __uc_sanitize(uc);
if (ret)
goto err_out;
@@ -478,6 +490,10 @@ int intel_uc_init_hw(struct intel_uc *uc)
goto err_communication;
}
+ ret = i915_inject_load_error(i915, -ENXIO);
+ if (ret)
+ goto err_communication;
+
dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
guc->fw.major_ver_found, guc->fw.minor_ver_found);
dev_info(i915->drm.dev, "GuC submission %s\n",
@@ -504,7 +520,7 @@ int intel_uc_init_hw(struct intel_uc *uc)
if (GEM_WARN_ON(ret == -EIO))
ret = -EINVAL;
- dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
+ i915_probe_error(i915, "GuC initialization failed %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 650ad6037b74..d2ff70bef574 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -443,8 +443,13 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, struct
intel_gt *gt,
/* make sure the status was cleared the last time we reset the uc */
GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw));
+ err = i915_inject_load_error(gt->i915, -ENOEXEC);
+ if (err)
+ return err;
+
if (!intel_uc_fw_is_available(uc_fw))
return -ENOEXEC;
+
/* Call custom loader */
intel_uc_fw_ggtt_bind(uc_fw, gt);
err =
[Intel-gfx] ✗ Fi.CI.BAT: failure for add more probe failures (rev4)
== Series Details == Series: add more probe failures (rev4) URL : https://patchwork.freedesktop.org/series/64390/ State : failure == Summary == Applying: drm/i915: Add i915 to i915_inject_probe_failure Applying: drm/i915/uc: Inject probe errors into intel_uc_init_hw Applying: drm/i915/wopcm: Don't fail on WOPCM partitioning failure error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gt/uc/intel_uc.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0003 drm/i915/wopcm: Don't fail on WOPCM partitioning failure When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915/pmu: Make more struct i915_pmu centric (rev3)
Quoting Patchwork (2019-08-01 22:22:58) > == Series Details == > > Series: series starting with [1/5] drm/i915/pmu: Make more struct i915_pmu > centric (rev3) > URL : https://patchwork.freedesktop.org/series/64550/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13839 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_13839 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_13839, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/ > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_13839: > > ### IGT changes ### > > Possible regressions > > * igt@i915_module_load@reload: > - fi-kbl-r: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-r/igt@i915_module_l...@reload.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-kbl-r/igt@i915_module_l...@reload.html Hmm, we need more trickery for kfree_const. Oh, it only applies to .rodata of the vmlinux and not modules :( Sorry. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915/pmu: Make more struct i915_pmu centric (rev3)
== Series Details == Series: series starting with [1/5] drm/i915/pmu: Make more struct i915_pmu centric (rev3) URL : https://patchwork.freedesktop.org/series/64550/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13839 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13839 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13839, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13839: ### IGT changes ### Possible regressions * igt@i915_module_load@reload: - fi-kbl-r: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-r/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-kbl-r/igt@i915_module_l...@reload.html - fi-whl-u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-whl-u/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-whl-u/igt@i915_module_l...@reload.html - fi-skl-iommu: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-iommu/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-skl-iommu/igt@i915_module_l...@reload.html - fi-hsw-4770r: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-hsw-4770r/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-hsw-4770r/igt@i915_module_l...@reload.html - fi-skl-6700k2: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-6700k2/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-skl-6700k2/igt@i915_module_l...@reload.html - fi-bsw-kefka: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bsw-kefka/igt@i915_module_l...@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-bsw-kefka/igt@i915_module_l...@reload.html - fi-bdw-5557u: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bdw-5557u/igt@i915_module_l...@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-bdw-5557u/igt@i915_module_l...@reload.html - fi-skl-guc: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-guc/igt@i915_module_l...@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-skl-guc/igt@i915_module_l...@reload.html - fi-kbl-guc: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-guc/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-kbl-guc/igt@i915_module_l...@reload.html - fi-cfl-8109u: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-cfl-8109u/igt@i915_module_l...@reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-cfl-8109u/igt@i915_module_l...@reload.html - fi-kbl-7500u: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7500u/igt@i915_module_l...@reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-kbl-7500u/igt@i915_module_l...@reload.html - fi-cfl-8700k: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-cfl-8700k/igt@i915_module_l...@reload.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-cfl-8700k/igt@i915_module_l...@reload.html - fi-snb-2520m: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-snb-2520m/igt@i915_module_l...@reload.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-snb-2520m/igt@i915_module_l...@reload.html - fi-cfl-guc: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-cfl-guc/igt@i915_module_l...@reload.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13839/fi-cfl-guc/igt@i915_module_l...@reload.html - fi-skl-6770hq: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-6770hq/igt@i915_module_l...@reload.html [30]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Atomically acquire the gt_pm wakeref (rev3)
== Series Details ==
Series: drm/i915/pmu: Atomically acquire the gt_pm wakeref (rev3)
URL : https://patchwork.freedesktop.org/series/64543/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13838
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/
Known issues
Here are the changes found in Patchwork_13838 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_param@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u3/igt@gem_ctx_pa...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-icl-u3/igt@gem_ctx_pa...@basic.html
* igt@prime_vgem@basic-fence-mmap:
- fi-byt-n2820: [PASS][3] -> [INCOMPLETE][4] ([fdo#102657] /
[fdo#111276])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html
- fi-elk-e7500: [PASS][5] -> [INCOMPLETE][6] ([fdo#103989] /
[fdo#111276])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
- fi-bwr-2160:[PASS][7] -> [INCOMPLETE][8] ([fdo#111276])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bwr-2160/igt@prime_v...@basic-fence-mmap.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-bwr-2160/igt@prime_v...@basic-fence-mmap.html
- fi-gdg-551: [PASS][9] -> [INCOMPLETE][10] ([fdo#108316] /
[fdo#111276])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-gdg-551/igt@prime_v...@basic-fence-mmap.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-gdg-551/igt@prime_v...@basic-fence-mmap.html
Possible fixes
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u3/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#08]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][15] ([fdo#109380]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#109485]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][19] ([fdo#109271]) -> [PASS][20] +23 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@prime_vgem@basic-fence-mmap:
- fi-pnv-d510:[INCOMPLETE][21] ([fdo#110740] / [fdo#111276]) ->
[PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-sync-default:
- fi-bxt-j4205: [FAIL][23] ([fdo#111277]) -> [PASS][24] +1 similar
issue
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
- fi-bxt-dsi: [FAIL][25] ([fdo#111277]) -> [PASS][26] +1 similar
issue
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13838/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html
{name}: This element is suppressed. This means
[Intel-gfx] ✓ Fi.CI.BAT: success for Don't sanitize enable_guc (rev4)
== Series Details == Series: Don't sanitize enable_guc (rev4) URL : https://patchwork.freedesktop.org/series/64446/ State : success == Summary == CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13837 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/ Known issues Here are the changes found in Patchwork_13837 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html * igt@prime_vgem@basic-wait-default: - fi-bxt-j4205: [PASS][3] -> [FAIL][4] ([fdo#111277]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html Possible fixes * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][5] ([fdo#08]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [SKIP][7] ([fdo#109271] / [fdo#109278]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html * igt@kms_busy@basic-flip-c: - fi-kbl-7500u: [SKIP][9] ([fdo#109271] / [fdo#109278]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-sync-default: - fi-bxt-dsi: [FAIL][13] ([fdo#111277]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 [fdo#111277]: https://bugs.freedesktop.org/show_bug.cgi?id=111277 Participating hosts (47 -> 43) -- Additional (2): fi-icl-dsi fi-apl-guc Missing(6): fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6605 -> Patchwork_13837 CI-20190529: 20190529 CI_DRM_6605: 09970f7b8f1336416254cfac87f196578e3c1d13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5120: b3138fbea79d5d7935e53530b90efe3e816236f4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13837: 031e371daac306fe0c1d1efb00320d1de141cd71 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 031e371daac3 drm/i915/uc: Stop sanitizing enable_guc modparam a702e91f3944 drm/i915/guc: Use dedicated flag to track submission mode 8808a185a10d drm/i915/uc: Consider enable_guc modparam during fw selection 193a653eb7a8 drm/i915/uc: Rename intel_uc_is_using* into intel_uc_supports* == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13837/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Flush extra hard after writing relocations through the GTT
Quoting Kumar Valsan, Prathap (2019-08-01 21:33:44)
> On Tue, Jul 30, 2019 at 12:21:51PM +0100, Chris Wilson wrote:
> > Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
> > flush for pwrite_gtt") was that we needed to our full write barrier
> > before changing the GGTT PTE to ensure that our indirect writes through
> > the GTT landed before the PTE changed (and the writes end up in a
> > different page). That also applies to our GGTT relocation path.
>
> Chris,
>
> As i understand, changing the GGTT PTE also an indirect write. If so, isn't a
> wmb()
> should be good enough.
Ha! If only that was true.
-Chris
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Flush extra hard after writing relocations through the GTT
On Tue, Jul 30, 2019 at 12:21:51PM +0100, Chris Wilson wrote:
> Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
> flush for pwrite_gtt") was that we needed to our full write barrier
> before changing the GGTT PTE to ensure that our indirect writes through
> the GTT landed before the PTE changed (and the writes end up in a
> different page). That also applies to our GGTT relocation path.
Chris,
As i understand, changing the GGTT PTE also an indirect write. If so, isn't a
wmb()
should be good enough.
Thanks,
Prathap
>
> Signed-off-by: Chris Wilson
> Cc: sta...@vger.kernel.org
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 8a2047c4e7c3..01901dad33f7 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1019,11 +1019,12 @@ static void reloc_cache_reset(struct reloc_cache
> *cache)
> kunmap_atomic(vaddr);
> i915_gem_object_finish_access((struct drm_i915_gem_object
> *)cache->node.mm);
> } else {
> - wmb();
> + struct i915_ggtt *ggtt = cache_to_ggtt(cache);
> +
> + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> io_mapping_unmap_atomic((void __iomem *)vaddr);
> - if (cache->node.allocated) {
> - struct i915_ggtt *ggtt = cache_to_ggtt(cache);
>
> + if (cache->node.allocated) {
> ggtt->vm.clear_range(>vm,
>cache->node.start,
>cache->node.size);
> @@ -1078,6 +1079,7 @@ static void *reloc_iomap(struct drm_i915_gem_object
> *obj,
> void *vaddr;
>
> if (cache->vaddr) {
> + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> io_mapping_unmap_atomic((void __force __iomem *)
> unmask_page(cache->vaddr));
> } else {
> struct i915_vma *vma;
> @@ -1119,7 +1121,6 @@ static void *reloc_iomap(struct drm_i915_gem_object
> *obj,
>
> offset = cache->node.start;
> if (cache->node.allocated) {
> - wmb();
> ggtt->vm.insert_page(>vm,
>i915_gem_object_get_dma_address(obj, page),
>offset, I915_CACHE_NONE, 0);
> --
> 2.22.0
>
> ___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next
Hi Dave and Daniel, Here goes the first pull request targeting 5.4. It mostly comes with a lot of platform enabling patches and reworks and simplification around locking mechanisms, ppgtt allocation, engines and intel_gt in general. There were 2 silent backmerges that should be transparent for you. drm-intel-next-2019-07-30: - More changes on simplifying locking mechanisms (Chris) - Selftests fixes and improvements (Chris) - More work around engine tracking for better handling (Chris, Tvrtko) - HDCP debug and info improvements (Ram, Ashuman) - Add DSI properties (Vandita) - Rework on sdvo support for better debuggability before fixing bugs (Ville) - Display PLLs fixes and improvements, specially targeting Ice Lake (Imre, Matt, Ville) - Perf fixes and improvements (Lionel) - Enumerate scratch buffers (Lionel) - Add infra to hold off preemption on a request (Lionel) - Ice Lake color space fixes (Uma) - Type-C fixes and improvements (Lucas) - Fix and improvements around workarounds (Chris, John, Tvrtko) - GuC related fixes and improvements (Chris, Daniele, Michal, Tvrtko) - Fix on VLV/CHV display power domain (Ville) - Improvements around Watermark (Ville) - Favor intel_ types on intel_atomic functions (Ville) - Don’t pass stack garbage to pcode (Ville) - Improve display tracepoints (Steven) - Don’t overestimate 4:2:0 link symbol clock (Ville) - Add support for 4th pipe and transcoder (Lucas) - Introduce initial support for Tiger Lake platform (Daniele, Lucas, Mahesh, Jose, Imre, Mika, Vandita, Rodrigo, Michel) - PPGTT allocation simplification (Chris) - Standardize function names and suffixes to make clean, symmetric and let checkpatch happy (Janusz) - Skip SINK_COUNT read on CH7511 (Ville) - Fix on kernel documentation (Chris, Michal) - Add modular FIA (Anusha, Lucas) - Fix EHL display (Matt, Vivek) - Enable hotplug retry (Imre, Jose) - Disable preemption under GVT (Chris) - OA; Reconfigure context on the fly (Chris) - Fixes and improvements around engine reset. (Chris) - Small clean up on display pipe fault mask (Ville) - Make sure cdclk is high enough for DP audio on VLV/CHV (Ville) - Drop some wmb() and improve pwrite flush (Chris) - Fix critical PSR regression (DK) - Remove unused variables (YueHaibing) - Use dev_get_drvdata for simplification (Chunhong) - Use upstream version of header tests (Jani) drm-intel-next-2019-07-08: - Signal fence completion from i915_request_wait (Chris) - Fixes and improvements around rings pin/unpin (Chris) - Display uncore prep patches (Daniele) - Execlists preemption improvements (Chris) - Selftests fixes and improvements (Chris) - More Elkhartlake enabling work (Vandita, Jose, Matt, Vivek) - Defer address space cleanup to an RCU worker (Chris) - Implicit dev_priv removal and GT compartmentalization and other related follow-ups (Tvrtko, Chris) - Prevent dereference of engine before NULL check in error capture (Chris) - GuC related fixes (Daniele, Robert) - Many changes on active tracking, timelines and locking mechanisms (Chris) - Disable SAMPLER_STATE prefetching on Gen11 (HW W/a) (Kenneth) - I915_perf fixes (Lionel) - Add Ice Lake PCI ID (Mika) - eDP backlight fix (Lee) - Fix various gen2 tracepoints (Ville) - Some irq vfunc clean-up and improvements (Ville) - Move OA files to separated folder (Michal) - Display self contained headers clean-up (Jani) - Preparation for 4th pile (Lucas) - Move atomic commit, watermark and other places to use more intel_crtc_state (Maarten) - Many Ice Lake Type C and Thunderbolt fixes (Imre) - Fix some Ice Lake hw w/a whitelist regs (Lionel) - Fix memleak in runtime wakeref tracking (Mika) - Remove unused Private PPAT manager (Michal) - Don't check PPGTT presence on PPGTT-only platforms (Michal) - Fix ICL DSI suspend/resume (Chris) - Fix ICL Bandwidth issues (Ville) - Add N & CTS values for 10/12 bit deep color (Aditya) - Moving more GT related stuff under gt folder (Chris) - Forcewake related fixes (Chris) - Show support for accurate sw PMU busyness tracking (Chris) - Handle gtt double alloc failures (Chris) - Upgrade to new GuC version (Michal) - Improve w/a debug dumps and pull engine w/a initialization into a common (Chris) - Look for instdone on all engines at hangcheck (Tvrtko) - Engine lookup simplification (Chris) - Many plane color formats fixes and improvements (Ville) - Fix some compilation issues (YueHaibing) - GTT page directory clean up and improvements (Mika) Thanks, Rodrigo. The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b: Linus 5.3-rc1 (2019-07-21 14:05:38 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2019-07-30 for you to fetch changes up to e0e712fe42ef67bdf45fc348767d1d0a4eeba77f: drm/i915: Update DRIVER_DATE to 20190730 (2019-07-30 11:50:24 -0700) - More changes on simplifying locking mechanisms (Chris) - Selftests fixes and improvements
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Drop the fudge warning on ring restart for ctg/elk
== Series Details ==
Series: drm/i915: Drop the fudge warning on ring restart for ctg/elk
URL : https://patchwork.freedesktop.org/series/64546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13836
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/
Known issues
Here are the changes found in Patchwork_13836 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_vgem@basic-busy-default:
- fi-bxt-dsi: [PASS][1] -> [FAIL][2] ([fdo#111277])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-dsi/igt@prime_v...@basic-busy-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-bxt-dsi/igt@prime_v...@basic-busy-default.html
* igt@prime_vgem@basic-fence-mmap:
- fi-gdg-551: [PASS][3] -> [INCOMPLETE][4] ([fdo#108316] /
[fdo#111276])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-gdg-551/igt@prime_v...@basic-fence-mmap.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-gdg-551/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- fi-bwr-2160:[PASS][5] -> [INCOMPLETE][6] ([fdo#111278])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-wait-default:
- fi-bxt-j4205: [PASS][7] -> [FAIL][8] ([fdo#111277])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html
Possible fixes
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u3/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][11] ([fdo#109380]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][13] ([fdo#109271]) -> [PASS][14] +23 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
* igt@prime_vgem@basic-fence-read:
- fi-pnv-d510:[INCOMPLETE][17] ([fdo#110740]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-pnv-d510/igt@prime_v...@basic-fence-read.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-pnv-d510/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-sync-default:
- fi-bxt-j4205: [FAIL][19] ([fdo#111277]) -> [PASS][20] +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html
- fi-bxt-dsi: [FAIL][21] ([fdo#111277]) -> [PASS][22] +1 similar
issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13836/fi-bxt-dsi/igt@prime_v...@basic-sync-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108316]: https://bugs.freedesktop.org/show_bug.cgi?id=108316
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#110740]: https://bugs.freedesktop.org/show_bug.cgi?id=110740
[fdo#111276]:
Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
Quoting Chris Wilson (2019-08-01 19:26:57) > As we track when we put the GT device to sleep upon idling, we can use > that callback to sample the current rc6 counters and record the > timestamp for estimating samples after that point while asleep. > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105010 > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/vgem: fix cache synchronization on arm/arm64"
== Series Details == Series: Revert "drm/vgem: fix cache synchronization on arm/arm64" URL : https://patchwork.freedesktop.org/series/64544/ State : success == Summary == CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13835 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/ Known issues Here are the changes found in Patchwork_13835 that come from known issues: ### IGT changes ### Issues hit * igt@kms_busy@basic-flip-c: - fi-skl-6770hq: [PASS][1] -> [SKIP][2] ([fdo#109271] / [fdo#109278]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-6770hq/igt@kms_b...@basic-flip-c.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-skl-6770hq/igt@kms_b...@basic-flip-c.html * igt@kms_flip@basic-flip-vs-dpms: - fi-skl-6770hq: [PASS][3] -> [SKIP][4] ([fdo#109271]) +23 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html * igt@vgem_basic@unload: - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u3/igt@vgem_ba...@unload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-icl-u3/igt@vgem_ba...@unload.html Possible fixes * igt@i915_module_load@reload: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u3/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-icl-u3/igt@i915_module_l...@reload.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][11] ([fdo#103167]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-mmap: - fi-ilk-650: [INCOMPLETE][13] ([fdo#111276]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-ilk-650/igt@prime_v...@basic-fence-mmap.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-ilk-650/igt@prime_v...@basic-fence-mmap.html - fi-blb-e6850: [INCOMPLETE][15] ([fdo#111276]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-blb-e6850/igt@prime_v...@basic-fence-mmap.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-blb-e6850/igt@prime_v...@basic-fence-mmap.html - fi-bsw-kefka: [INCOMPLETE][17] ([fdo#111276]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bsw-kefka/igt@prime_v...@basic-fence-mmap.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-bsw-kefka/igt@prime_v...@basic-fence-mmap.html - fi-pnv-d510:[INCOMPLETE][19] ([fdo#110740] / [fdo#111276]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - fi-ilk-650: [INCOMPLETE][21] ([fdo#105596]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-ilk-650/igt@prime_v...@basic-fence-read.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-ilk-650/igt@prime_v...@basic-fence-read.html - fi-elk-e7500: [INCOMPLETE][23] ([fdo#103989]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-elk-e7500/igt@prime_v...@basic-fence-read.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-elk-e7500/igt@prime_v...@basic-fence-read.html - fi-byt-n2820: [INCOMPLETE][25] ([fdo#102657]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-byt-n2820/igt@prime_v...@basic-fence-read.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13835/fi-byt-n2820/igt@prime_v...@basic-fence-read.html - fi-pnv-d510:[INCOMPLETE][27] ([fdo#110740]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-pnv-d510/igt@prime_v...@basic-fence-read.html [28]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Pass intel_context to igt_spinner (rev3)
== Series Details == Series: drm/i915/selftests: Pass intel_context to igt_spinner (rev3) URL : https://patchwork.freedesktop.org/series/64440/ State : success == Summary == CI Bug Log - changes from CI_DRM_6587_full -> Patchwork_13818_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13818_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-snb: ([PASS][1], [PASS][2]) -> ([PASS][3], [FAIL][4]) ([fdo#109661]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-snb7/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-snb4/igt@gem_...@unwedge-stress.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-snb1/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#109100]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-iclb1/igt@gem_fence_thr...@bo-write-verify-threaded-y.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-iclb7/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@gem_fence_thrash@bo-write-verify-y: - shard-apl: ([PASS][7], [PASS][8]) -> ([PASS][9], [INCOMPLETE][10]) ([fdo#103927]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-apl6/igt@gem_fence_thr...@bo-write-verify-y.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-apl7/igt@gem_fence_thr...@bo-write-verify-y.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-apl3/igt@gem_fence_thr...@bo-write-verify-y.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-apl5/igt@gem_fence_thr...@bo-write-verify-y.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-skl1/igt@gem_soft...@noreloc-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-skl5/igt@gem_soft...@noreloc-s3.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#110741]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@all-pipes-torture-bo: - shard-glk: ([PASS][15], [PASS][16]) -> ([DMESG-WARN][17], [PASS][18]) ([fdo#107122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-glk4/igt@kms_cursor_leg...@all-pipes-torture-bo.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-glk8/igt@kms_cursor_leg...@all-pipes-torture-bo.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-glk1/igt@kms_cursor_leg...@all-pipes-torture-bo.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-glk7/igt@kms_cursor_leg...@all-pipes-torture-bo.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: ([PASS][19], [PASS][20]) -> ([FAIL][21], [FAIL][22]) ([fdo#105363]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-glk5/igt@kms_f...@2x-flip-vs-expired-vblank.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-glk7/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@modeset-vs-vblank-race: - shard-apl: ([PASS][23], [PASS][24]) -> ([FAIL][25], [PASS][26]) ([fdo#103060]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-apl4/igt@kms_f...@modeset-vs-vblank-race.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-apl6/igt@kms_f...@modeset-vs-vblank-race.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-apl6/igt@kms_f...@modeset-vs-vblank-race.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13818/shard-apl7/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-iclb: [PASS][27] -> [FAIL][28] ([fdo#103167]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6587/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-onoff.html [28]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/vgem: fix cache synchronization on arm/arm64"
== Series Details ==
Series: Revert "drm/vgem: fix cache synchronization on arm/arm64"
URL : https://patchwork.freedesktop.org/series/64544/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
18f70bceaf5b Revert "drm/vgem: fix cache synchronization on arm/arm64"
-:52: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#52: FILE: drivers/gpu/drm/vgem/vgem_drv.c:97:
+ page = shmem_read_mapping_page(
-:58: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be at the same
indent
#58: FILE: drivers/gpu/drm/vgem/vgem_drv.c:103:
+ } else switch (PTR_ERR(page)) {
+ case -ENOSPC:
+ case -ENOMEM:
[...]
+ case -EBUSY:
[...]
+ case -EFAULT:
+ case -EINVAL:
[...]
+ default:
-:58: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line
#58: FILE: drivers/gpu/drm/vgem/vgem_drv.c:103:
+ } else switch (PTR_ERR(page)) {
-:76: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#76: FILE: drivers/gpu/drm/vgem/vgem_drv.c:121:
+ }
total: 2 errors, 0 warnings, 2 checks, 183 lines checked
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for HDCP2.2 Phase II (rev14)
== Series Details ==
Series: HDCP2.2 Phase II (rev14)
URL : https://patchwork.freedesktop.org/series/57232/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6605 -> Patchwork_13834
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_13834 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13834, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13834:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload-with-fault-injection:
- fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html
* {igt@kms_content_protection@srm} (NEW):
- fi-cfl-8109u: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-cfl-8109u/igt@kms_content_protect...@srm.html
- {fi-icl-u4}:NOTRUN -> [SKIP][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-icl-u4/igt@kms_content_protect...@srm.html
- fi-icl-dsi: NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-icl-dsi/igt@kms_content_protect...@srm.html
- fi-skl-lmem:NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-skl-lmem/igt@kms_content_protect...@srm.html
- fi-apl-guc: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-apl-guc/igt@kms_content_protect...@srm.html
- fi-icl-u3: NOTRUN -> [FAIL][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-icl-u3/igt@kms_content_protect...@srm.html
- fi-cml-u2: NOTRUN -> [SKIP][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-cml-u2/igt@kms_content_protect...@srm.html
New tests
-
New tests have been introduced between CI_DRM_6605 and Patchwork_13834:
### New IGT tests (1) ###
* igt@kms_content_protection@srm:
- Statuses : 4 fail(s) 5 pass(s) 34 skip(s)
- Exec time: [0.0, 130.44] s
Known issues
Here are the changes found in Patchwork_13834 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_addfb_basic@size-max:
- fi-icl-u3: [PASS][10] -> [DMESG-WARN][11] ([fdo#107724])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u3/igt@kms_addfb_ba...@size-max.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-icl-u3/igt@kms_addfb_ba...@size-max.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-7500u: [PASS][12] -> [DMESG-WARN][13] ([fdo#103558] /
[fdo#105602])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-kbl-7500u/igt@kms_chamel...@dp-hpd-fast.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-kbl-7500u/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: [PASS][14] -> [SKIP][15] ([fdo#109271]) +23 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
* igt@prime_vgem@basic-fence-mmap:
- fi-elk-e7500: [PASS][16] -> [INCOMPLETE][17] ([fdo#103989] /
[fdo#111276])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- fi-bsw-kefka: [PASS][18] -> [INCOMPLETE][19] ([fdo#111278])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
Possible fixes
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][20] ([fdo#107724]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6605/fi-icl-u3/igt@i915_module_l...@reload.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13834/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][22] ([fdo#08]) -> [PASS][23]
[Intel-gfx] [PATCH 1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
v2: Take engine->wakeref for engine sampling
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 8 +-
drivers/gpu/drm/i915/i915_pmu.c | 40 ---
2 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 527894fe1345..e8a18d4b27c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -9,7 +9,8 @@
#include
-struct intel_gt;
+#include "intel_gt_types.h"
+#include "intel_wakeref.h"
enum {
INTEL_GT_UNPARK,
@@ -19,6 +20,11 @@ enum {
void intel_gt_pm_get(struct intel_gt *gt);
void intel_gt_pm_put(struct intel_gt *gt);
+static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
+{
+ return intel_wakeref_get_if_active(>wakeref);
+}
+
void intel_gt_pm_init_early(struct intel_gt *gt);
void intel_gt_sanitize(struct intel_gt *gt, bool force);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..4d7cabeea687 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,8 @@
#include
#include "gt/intel_engine.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
#include "i915_pmu.h"
@@ -161,27 +163,24 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
- intel_wakeref_t wakeref;
- unsigned long flags;
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
- wakeref = 0;
- if (READ_ONCE(dev_priv->gt.awake))
- wakeref = intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
- if (!wakeref)
- return;
-
- spin_lock_irqsave(_priv->uncore.lock, flags);
for_each_engine(engine, dev_priv, id) {
struct intel_engine_pmu *pmu = >pmu;
+ unsigned long flags;
bool busy;
u32 val;
+ if (!intel_engine_pm_get_if_awake(engine))
+ continue;
+
+ spin_lock_irqsave(_priv->uncore.lock, flags);
+
val = I915_READ_FW(RING_CTL(engine->mmio_base));
if (val == 0) /* powerwell off => engine idle */
- continue;
+ goto skip;
if (val & RING_WAIT)
add_sample(>sample[I915_SAMPLE_WAIT], period_ns);
@@ -202,10 +201,11 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
}
if (busy)
add_sample(>sample[I915_SAMPLE_BUSY], period_ns);
- }
- spin_unlock_irqrestore(_priv->uncore.lock, flags);
- intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+skip:
+ spin_unlock_irqrestore(_priv->uncore.lock, flags);
+ intel_engine_pm_put(engine);
+ }
}
static void
@@ -222,15 +222,11 @@ frequency_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
u32 val;
val = dev_priv->gt_pm.rps.cur_freq;
- if (dev_priv->gt.awake) {
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
- wakeref) {
- val =
intel_uncore_read_notrace(_priv->uncore,
- GEN6_RPSTAT1);
- val = intel_get_cagf(dev_priv, val);
- }
+ if (intel_gt_pm_get_if_awake(_priv->gt)) {
+ val = intel_uncore_read_notrace(_priv->uncore,
+ GEN6_RPSTAT1);
+ val = intel_get_cagf(dev_priv, val);
+ intel_gt_pm_put(_priv->gt);
}
add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
--
2.23.0.rc0
___
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[Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 ++---
drivers/gpu/drm/i915/i915_pmu.c | 122 ++--
drivers/gpu/drm/i915/i915_pmu.h | 4 +-
3 files changed, 71 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 24787bb48c9f..a96e630d3f86 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -39,6 +39,7 @@
#include "display/intel_psr.h"
#include "gem/i915_gem_context.h"
+#include "gt/intel_gt_pm.h"
#include "gt/intel_reset.h"
#include "gt/uc/intel_guc_submission.h"
@@ -4057,13 +4058,11 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- file->private_data =
- (void *)(uintptr_t)intel_runtime_pm_get(>runtime_pm);
- intel_uncore_forcewake_user_get(>uncore);
+ intel_gt_pm_get(gt);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
return 0;
}
@@ -4071,13 +4070,11 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- intel_uncore_forcewake_user_put(>uncore);
- intel_runtime_pm_put(>runtime_pm,
-(intel_wakeref_t)(uintptr_t)file->private_data);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_put(>uncore);
+ intel_gt_pm_put(gt);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 4d7cabeea687..680618bd385c 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -114,17 +114,50 @@ static bool pmu_needs_timer(struct drm_i915_private
*i915, bool gpu_active)
return enable;
}
+static u64 __get_rc6(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ u64 val;
+
+ val = intel_rc6_residency_ns(i915,
+IS_VALLEYVIEW(i915) ?
+VLV_GT_RENDER_RC6 :
+GEN6_GT_GFX_RC6);
+
+ if (HAS_RC6p(i915))
+ val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+
+ if (HAS_RC6pp(i915))
+ val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+
+ return val;
+}
+
void i915_pmu_gt_parked(struct drm_i915_private *i915)
{
+ u64 val;
+
if (!i915->pmu.base.event_init)
return;
+ val = 0;
+ if (i915->pmu.sample[__I915_SAMPLE_RC6].cur)
+ val = __get_rc6(>gt);
+
spin_lock_irq(>pmu.lock);
+
+ if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
+ i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
+ i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
+ }
+ i915->pmu.sleep_timestamp = jiffies;
+
/*
* Signal sampling timer to stop if only engine events are enabled and
* GPU went idle.
*/
i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
+
spin_unlock_irq(>pmu.lock);
}
@@ -145,10 +178,23 @@ void i915_pmu_gt_unparked(struct drm_i915_private *i915)
return;
spin_lock_irq(>pmu.lock);
+
/*
* Re-enable sampling timer when GPU goes active.
*/
__i915_pmu_maybe_start_timer(i915);
+
+ /* Estimate how long we slept and accumulate that into rc6 counters */
+ if (i915->pmu.sample[__I915_SAMPLE_RC6].cur) {
+ u64 val;
+
+ val = jiffies - i915->pmu.sleep_timestamp;
+ val = jiffies_to_nsecs(val);
+ val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
+
+ i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
+ }
+
spin_unlock_irq(>pmu.lock);
}
@@ -417,36 +463,17 @@ static int i915_pmu_event_init(struct perf_event *event)
return 0;
}
-static u64 __get_rc6(struct drm_i915_private *i915)
+static u64 get_rc6(struct intel_gt *gt)
{
- u64 val;
-
- val = intel_rc6_residency_ns(i915,
-IS_VALLEYVIEW(i915) ?
-VLV_GT_RENDER_RC6 :
-GEN6_GT_GFX_RC6);
-
- if (HAS_RC6p(i915))
-
Re: [Intel-gfx] [RFC][PATCH 0/2] drm: PATH prop for all connectors?
On 2019-08-01 5:51 a.m., Pekka Paalanen wrote: > On Tue, 16 Jul 2019 14:59:58 + > "Li, Sun peng (Leo)" wrote: > >> On 2019-07-11 3:29 a.m., Pekka Paalanen wrote: >>> Wait, one can write udev rules for connectors and stuff? >>> How? What can they do? >> >> I was using it to generate user-friendly device names for the mst aux >> implementation: >> https://patchwork.freedesktop.org/patch/315900/?series=63237=2 > > Hi, > > what is that device node used for? > > Are the "by-path" symlinks to help a display server associate the > right device node with the right DRM KMS connector resource? I intended it to be something more descriptive than the '/dev/drm_dp_aux0, drm_dp_aux1, drm_dp_aux2, ...' names, to help users identify the connector they're addressing in the mst topology. I guess it could also be used for the purpose you mention as well. Of course, we'd need more reliable and persistent PATH props first. The patch was dropped until this happens. Leo > > The patch commit message did not explain what the names are > actually used for. > > > Thanks, > pq > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP2.2 Phase II (rev14)
== Series Details ==
Series: HDCP2.2 Phase II (rev14)
URL : https://patchwork.freedesktop.org/series/57232/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ce79e1d0d5a1 drm: Add Content protection type property
-:146: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#146: FILE: drivers/gpu/drm/drm_hdcp.c:351:
+};
+DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
-:191: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#191: FILE: drivers/gpu/drm/drm_hdcp.c:404:
+ prop = drm_property_create_enum(dev, 0, "HDCP Content Type",
+ drm_hdcp_content_type_enum_list,
-:192: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#192: FILE: drivers/gpu/drm/drm_hdcp.c:405:
+ ARRAY_SIZE(
total: 0 errors, 0 warnings, 3 checks, 189 lines checked
5a8acad0bc86 drm/i915: Attach content type property
add126230c60 drm: uevent for connector status change
3b164c38b461 drm/hdcp: update content protection property with uevent
-:104: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#104: FILE: drivers/gpu/drm/drm_hdcp.c:448:
+ drm_sysfs_connector_status_event(connector,
+dev->mode_config.content_protection_property);
total: 0 errors, 0 warnings, 1 checks, 74 lines checked
f052ab943daa drm/i915: update the hdcp state with uevent
26394e4cc3b2 drm/hdcp: reference for srm file format
___
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Allow sharing the idle-barrier from other kernel requests
Quoting Tvrtko Ursulin (2019-08-01 18:24:50)
>
> On 30/07/2019 12:21, Chris Wilson wrote:
> > @@ -224,8 +283,15 @@ int i915_active_ref(struct i915_active *ref,
> > goto out;
> > }
> >
> > - if (!i915_active_request_isset(active))
> > - atomic_inc(>count);
> > + if (is_barrier(active)) { /* proto-node used by our idle barrier */
> > + __active_del_barrier(ref, node_from_active(active));
> > + RCU_INIT_POINTER(active->request, NULL);
> > + INIT_LIST_HEAD(>link);
>
> So this, when prepare_remote_request calls it on ce->active, will remove
> the idle barrier from the engine->barriers_list and immediately transfer
> it to the rq->active_list?
Yes. So long as the context matches the idle-barrier, i.e. we are
operating on this context from the kernel_context.
> Then when this request is retired we know the
> context is idle?
So long as the context itself hasn't claimed a new active reference for
its own requests.
> But what if it is the same context? Then it is not idle yet.
Correct, but that would only happens for the kernel_context, which is the
special case where we force idle on parking and exclude from the
deferred active-barrier (as it would continually defer instead of
parking).
> > +static inline bool is_idle_barrier(struct active_node *node, u64 idx)
> > +{
> > + return node->timeline == idx &&
> > !i915_active_request_isset(>base);
> > +}
> > +
> > +static struct active_node *idle_barrier(struct i915_active *ref, u64 idx)
> > +{
> > + struct rb_node *prev, *p;
> > +
> > + if (RB_EMPTY_ROOT(>tree))
> > + return NULL;
> > +
> > + mutex_lock(>mutex);
> > + GEM_BUG_ON(i915_active_is_idle(ref));
> > +
> > + /*
> > + * Try to reuse any existing barrier nodes already allocated for this
> > + * i915_active, due to overlapping active phases there is likely a
>
> For this i915_active or for this idx? It is this i915_active by
> definition, no? And idx also has to match in both loops below.
idx is a timeline, which although would normally be unique in the tree,
due to the active-barrier we may have more than one instance, because we
may have overlapping i915_active phases of activity.
This function exists to try and reuse any of the older phases that we
could not reap as we never completely idled. (Before we would
accidentally keep growing the tree with new nodes until we hit a point
where we retired the idle timeline after parking.)
> > + * node kept alive (as we reuse before parking). We prefer to reuse
> > + * completely idle barriers (less hassle in manipulating the llists),
> > + * but otherwise any will do.
> > + */
> > + if (ref->cache && is_idle_barrier(ref->cache, idx)) {
> > + p = >cache->node;
> > + goto match;
> > + }
> > +
> > + prev = NULL;
> > + p = ref->tree.rb_node;
> > + while (p) {
> > + struct active_node *node =
> > + rb_entry(p, struct active_node, node);
> > +
> > + if (is_idle_barrier(node, idx))
> > + goto match;
> > +
> > + prev = p;
> > + if (node->timeline < idx)
> > + p = p->rb_right;
> > + else
> > + p = p->rb_left;
> > + }
> > +
> > + for (p = prev; p; p = rb_next(p)) {
> > + struct active_node *node =
> > + rb_entry(p, struct active_node, node);
> > +
> > + if (node->timeline > idx)
> > + break;
> > +
> > + if (node->timeline < idx)
> > + continue;
> > +
> > + if (!i915_active_request_isset(>base))
> > + goto match;
>
> Isn't this idle barrier, so same as above? How can above not find it,
> and find it here?
We didn't check all nodes, only followed the binary tree down one
branch to find the starting point. I anticipate we may end up with more
than one idle-barrier in the tree.
> > +
> > + if (is_barrier(>base) && __active_del_barrier(ref,
> > node))
> > + goto match;
>
> And this is yet unused barrier with the right idx. Under what
> circumstances can __active_del_barrier fail then? I think a comment is
> needed.
__active_del_barrier() here can theoretically race with
i915_request_add_active_barriers(). In the other callsite, we must be
holding the kernel_context timeline mutex and so cannot be concurrently
calling add_active_barriers(). [Here is the weakness of using
__active_del_barrier(), in order to reuse an activated idle-barrier, we
may cause add_active_barriers() to miss the others and so postpone the
retirement of other contexts. Under the current scheme of parking, that
is not an issue. In the future, it means retirement may miss a
heartbeat.]
> > + if (!i915_active_request_isset(>base)) {
> > +
Re: [Intel-gfx] [linux-next] mm/i915: i915_gemfs_init() NULL dereference
Quoting Sergey Senozhatsky (2019-07-31 17:48:29)
> @@ -36,19 +38,35 @@ int i915_gemfs_init(struct drm_i915_private *i915)
> struct super_block *sb = gemfs->mnt_sb;
> /* FIXME: Disabled until we get W/A for read BW issue. */
> char options[] = "huge=never";
> - int flags = 0;
> int err;
>
> - err = sb->s_op->remount_fs(sb, , options);
> - if (err) {
> - kern_unmount(gemfs);
> - return err;
> - }
> + fc = fs_context_for_reconfigure(sb->s_root, 0, 0);
> + if (IS_ERR(fc))
> + goto err;
> +
> + if (!fc->ops->parse_monolithic)
> + goto err;
> +
> + err = fc->ops->parse_monolithic(fc, options);
> + if (err)
> + goto err;
> +
> + if (!fc->ops->reconfigure)
It would be odd for fs_context_for_reconfigure() to allow creation of a
context if that context couldn't perform a reconfigre, nevertheless that
seems to be the case.
> + goto err;
> +
> + err = fc->ops->reconfigure(fc);
> + if (err)
> + goto err;
Only thing that stands out is that we should put_fs_context() here as
well. I guess it's better than poking at the SB_INFO directly ourselves.
I think though we shouldn't bail if we can't change the thp setting, and
just accept whatever with a warning.
Looks like the API is already available in dinq, so we can apply this
ahead of the next merge window.
-Chris
___
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Allow sharing the idle-barrier from other kernel requests
On 30/07/2019 12:21, Chris Wilson wrote:
By placing our idle-barriers in the i915_active fence tree, we expose
those for reuse by other components that are issuing requests along the
kernel_context. Reusing the proto-barrier active_node is perfectly fine
as the new request implies a context-switch, and so an opportune point
to run the idle-barrier. However, the proto-barrier is not equivalent
to a normal active_node and care must be taken to avoid dereferencing the
ERR_PTR used as its request marker.
Reported-by: Lionel Landwerlin
Fixes: ce476c80b8bf ("drm/i915: Keep contexts pinned until after the next kernel
context switch")
Fixes: a9877da2d629 ("drm/i915/oa: Reconfigure contexts on the fly")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 40 ++-
drivers/gpu/drm/i915/gt/intel_context.h | 13 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 310 ++
drivers/gpu/drm/i915/i915_active.c| 246 +++---
drivers/gpu/drm/i915/i915_active.h| 2 +-
drivers/gpu/drm/i915/i915_active_types.h | 2 +-
.../drm/i915/selftests/i915_live_selftests.h | 3 +-
8 files changed, 555 insertions(+), 63 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_context.c
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index d64b45f7ec6d..211ac6568a5d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -162,23 +162,41 @@ static int __intel_context_active(struct i915_active
*active)
if (err)
goto err_ring;
+ return 0;
+
+err_ring:
+ intel_ring_unpin(ce->ring);
+err_put:
+ intel_context_put(ce);
+ return err;
+}
+
+int intel_context_active_acquire(struct intel_context *ce)
+{
+ int err;
+
+ err = i915_active_acquire(>active);
+ if (err)
+ return err;
+
/* Preallocate tracking nodes */
if (!i915_gem_context_is_kernel(ce->gem_context)) {
err = i915_active_acquire_preallocate_barrier(>active,
ce->engine);
- if (err)
- goto err_state;
+ if (err) {
+ i915_active_release(>active);
+ return err;
+ }
}
return 0;
+}
-err_state:
- __context_unpin_state(ce->state);
-err_ring:
- intel_ring_unpin(ce->ring);
-err_put:
- intel_context_put(ce);
- return err;
+void intel_context_active_release(struct intel_context *ce)
+{
+ /* Nodes preallocated in intel_context_active() */
+ i915_active_acquire_barrier(>active);
+ i915_active_release(>active);
}
void
@@ -297,3 +315,7 @@ struct i915_request *intel_context_create_request(struct
intel_context *ce)
return rq;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_context.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 23c7e4c0ce7c..07f9924de48f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -104,17 +104,8 @@ static inline void intel_context_exit(struct intel_context
*ce)
ce->ops->exit(ce);
}
-static inline int intel_context_active_acquire(struct intel_context *ce)
-{
- return i915_active_acquire(>active);
-}
-
-static inline void intel_context_active_release(struct intel_context *ce)
-{
- /* Nodes preallocated in intel_context_active() */
- i915_active_acquire_barrier(>active);
- i915_active_release(>active);
-}
+int intel_context_active_acquire(struct intel_context *ce);
+void intel_context_active_release(struct intel_context *ce);
static inline struct intel_context *intel_context_get(struct intel_context *ce)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index e74fbf04a68d..ce54092475da 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -90,7 +90,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
/* Check again on the next retirement. */
engine->wakeref_serial = engine->serial + 1;
- i915_request_add_barriers(rq);
+ i915_request_add_active_barriers(rq);
__i915_request_commit(rq);
return false;
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
new file mode 100644
index ..d39b5594cb02
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -0,0 +1,310 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+#include "intel_gt.h"
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Remove DDI IO power domain from PG3 power domains
== Series Details == Series: drm/i915/icl: Remove DDI IO power domain from PG3 power domains URL : https://patchwork.freedesktop.org/series/64465/ State : success == Summary == CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13816_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13816_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_cs_tlb@vcs2: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_cs_...@vcs2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-iclb4/igt@gem_cs_...@vcs2.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> ([PASS][4], [DMESG-WARN][5]) ([fdo#108566]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl1/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-kbl1/igt@gem_ctx_isolat...@rcs0-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#110854]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_exec_balan...@smoke.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - shard-apl: [PASS][8] -> ([INCOMPLETE][9], [PASS][10]) ([fdo#103927]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl2/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-apl8/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103232]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-64x21-sliding.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-64x21-sliding.html * igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge: - shard-snb: [PASS][13] -> [SKIP][14] ([fdo#109271] / [fdo#109278]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-snb4/igt@kms_cursor_edge_w...@pipe-a-64x64-bottom-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-snb7/igt@kms_cursor_edge_w...@pipe-a-64x64-bottom-edge.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103184] / [fdo#103232]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@kms_draw_...@draw-method-rgb565-pwrite-xtiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-iclb7/igt@kms_draw_...@draw-method-rgb565-pwrite-xtiled.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][17] -> ([PASS][18], [FAIL][19]) ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-glk8/igt@kms_f...@flip-vs-expired-vblank.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-glk5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-x-tiled: - shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145] / [fdo#108303]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl9/igt@kms_flip_til...@flip-x-tiled.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-skl8/igt@kms_flip_til...@flip-x-tiled.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-skl: [PASS][22] -> [INCOMPLETE][23] ([fdo#104108]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl2/igt@kms_frontbuffer_track...@fbc-suspend.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-skl5/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-skl: [PASS][24] -> [FAIL][25] ([fdo#103167]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl4/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13816/shard-skl2/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/gt: Move gt_cleanup_early out of gem_cleanup_early
== Series Details == Series: series starting with [v3,1/3] drm/i915/gt: Move gt_cleanup_early out of gem_cleanup_early URL : https://patchwork.freedesktop.org/series/64522/ State : success == Summary == CI Bug Log - changes from CI_DRM_6603 -> Patchwork_13832 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/ Known issues Here are the changes found in Patchwork_13832 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [PASS][5] -> [WARN][6] ([fdo#109380]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html * igt@prime_vgem@basic-fence-mmap: - fi-byt-n2820: [PASS][9] -> [INCOMPLETE][10] ([fdo#102657] / [fdo#111276]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html - fi-elk-e7500: [PASS][11] -> [INCOMPLETE][12] ([fdo#103989] / [fdo#111276]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-sync-default: - fi-bxt-j4205: [PASS][13] -> [FAIL][14] ([fdo#111277]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-bxt-j4205/igt@prime_v...@basic-sync-default.html * igt@prime_vgem@basic-wait-default: - fi-bsw-kefka: [PASS][15] -> [FAIL][16] ([fdo#111277]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-bsw-kefka/igt@prime_v...@basic-wait-default.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-bsw-kefka/igt@prime_v...@basic-wait-default.html Possible fixes * igt@i915_selftest@live_evict: - fi-icl-dsi: [INCOMPLETE][17] ([fdo#107713]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-icl-dsi/igt@i915_selftest@live_evict.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-icl-dsi/igt@i915_selftest@live_evict.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][19] ([fdo#107713] / [fdo#108569]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-icl-u3/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][21] ([fdo#109483] / [fdo#109635 ]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#109485]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13832/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-fence-flip: - fi-kbl-7500u: [SKIP][25] ([fdo#109271]) -> [PASS][26] +23 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html [26]:
Re: [Intel-gfx] [PATCH 03/23] drm/i915: Remove lrc default desc from GEM context
Quoting Tvrtko Ursulin (2019-08-01 17:22:27) > > On 01/08/2019 17:00, Chris Wilson wrote: > Who kidnapped real Chris? :D We could merge the mask clearing and reduce > pin to one conditional and one and, shift, or. :) Don't worry in about 24 patches time, we can remove the branches. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Compute has_drrs after compute has_psr
== Series Details == Series: series starting with [1/2] drm/i915: Compute has_drrs after compute has_psr URL : https://patchwork.freedesktop.org/series/64516/ State : success == Summary == CI Bug Log - changes from CI_DRM_6603 -> Patchwork_13831 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/ Known issues Here are the changes found in Patchwork_13831 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-icl-u3/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-icl-u3/igt@i915_module_l...@reload.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [PASS][3] -> [WARN][4] ([fdo#109380]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271]) +23 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html * igt@prime_vgem@basic-fence-mmap: - fi-elk-e7500: [PASS][7] -> [INCOMPLETE][8] ([fdo#103989] / [fdo#111276]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - fi-bsw-kefka: [PASS][9] -> [INCOMPLETE][10] ([fdo#111278]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-wait-default: - fi-bsw-kefka: [PASS][11] -> [FAIL][12] ([fdo#111277]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-bsw-kefka/igt@prime_v...@basic-wait-default.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-bsw-kefka/igt@prime_v...@basic-wait-default.html Possible fixes * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][13] ([fdo#107718]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-blb-e6850/igt@i915_module_l...@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_evict: - fi-icl-dsi: [INCOMPLETE][15] ([fdo#107713]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-icl-dsi/igt@i915_selftest@live_evict.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-icl-dsi/igt@i915_selftest@live_evict.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-icl-u3/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][19] ([fdo#109483] / [fdo#109635 ]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][21] ([fdo#103167]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-flip: - fi-ilk-650: [DMESG-WARN][23] ([fdo#106387]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-ilk-650/igt@prime_v...@basic-fence-flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13831/fi-ilk-650/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - fi-byt-j1900: [INCOMPLETE][25] ([fdo#102657] / [fdo#111276]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6603/fi-byt-j1900/igt@prime_v...@basic-fence-mmap.html [26]:
[Intel-gfx] [CI 4/4] drm/i915/pmu: Make get_rc6 take intel_gt
From: Tvrtko Ursulin
RC6 is a GT state so make the function parameter reflect that.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 5cf9a47a0c43..e0e0180bca7c 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -431,8 +431,9 @@ static int i915_pmu_event_init(struct perf_event *event)
return 0;
}
-static u64 __get_rc6(struct drm_i915_private *i915)
+static u64 __get_rc6(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
u64 val;
val = intel_rc6_residency_ns(i915,
@@ -449,9 +450,10 @@ static u64 __get_rc6(struct drm_i915_private *i915)
return val;
}
-static u64 get_rc6(struct drm_i915_private *i915)
+static u64 get_rc6(struct intel_gt *gt)
{
#if IS_ENABLED(CONFIG_PM)
+ struct drm_i915_private *i915 = gt->i915;
struct intel_runtime_pm *rpm = >runtime_pm;
struct i915_pmu *pmu = >pmu;
intel_wakeref_t wakeref;
@@ -460,7 +462,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
wakeref = intel_runtime_pm_get_if_in_use(rpm);
if (wakeref) {
- val = __get_rc6(i915);
+ val = __get_rc6(gt);
intel_runtime_pm_put(rpm, wakeref);
/*
@@ -523,7 +525,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
return val;
#else
- return __get_rc6(i915);
+ return __get_rc6(gt);
#endif
}
@@ -566,7 +568,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
val = count_interrupts(i915);
break;
case I915_PMU_RC6_RESIDENCY:
- val = get_rc6(i915);
+ val = get_rc6(>gt);
break;
}
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/4] drm/i915/pmu: Convert sampling to gt
From: Tvrtko Ursulin
Engines and frequencies are a GT thing so adjust sampling routines to
match.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 09265b6b78b2..5cf9a47a0c43 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -162,9 +162,10 @@ add_sample(struct i915_pmu_sample *sample, u32 val)
}
static void
-engines_sample(struct drm_i915_private *i915, unsigned int period_ns)
+engines_sample(struct intel_gt *gt, unsigned int period_ns)
{
- struct intel_uncore *uncore = >uncore;
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
intel_wakeref_t wakeref;
@@ -174,7 +175,7 @@ engines_sample(struct drm_i915_private *i915, unsigned int
period_ns)
return;
wakeref = 0;
- if (READ_ONCE(i915->gt.awake))
+ if (READ_ONCE(gt->awake))
wakeref = intel_runtime_pm_get_if_in_use(>runtime_pm);
if (!wakeref)
return;
@@ -221,34 +222,35 @@ add_sample_mult(struct i915_pmu_sample *sample, u32 val,
u32 mul)
}
static void
-frequency_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
+frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
- if (dev_priv->pmu.enable &
- config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct i915_pmu *pmu = >pmu;
+
+ if (pmu->enable & config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
u32 val;
- val = dev_priv->gt_pm.rps.cur_freq;
- if (dev_priv->gt.awake) {
+ val = i915->gt_pm.rps.cur_freq;
+ if (gt->awake) {
intel_wakeref_t wakeref;
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
+ with_intel_runtime_pm_if_in_use(>runtime_pm,
wakeref) {
- val =
intel_uncore_read_notrace(_priv->uncore,
+ val = intel_uncore_read_notrace(uncore,
GEN6_RPSTAT1);
- val = intel_get_cagf(dev_priv, val);
+ val = intel_get_cagf(i915, val);
}
}
- add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
- intel_gpu_freq(dev_priv, val),
+ add_sample_mult(>sample[__I915_SAMPLE_FREQ_ACT],
+ intel_gpu_freq(i915, val),
period_ns / 1000);
}
- if (dev_priv->pmu.enable &
- config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
- add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_REQ],
- intel_gpu_freq(dev_priv,
- dev_priv->gt_pm.rps.cur_freq),
+ if (pmu->enable & config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
+ add_sample_mult(>sample[__I915_SAMPLE_FREQ_REQ],
+ intel_gpu_freq(i915, i915->gt_pm.rps.cur_freq),
period_ns / 1000);
}
}
@@ -258,6 +260,7 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
struct i915_pmu *pmu = >pmu;
+ struct intel_gt *gt = >gt;
unsigned int period_ns;
ktime_t now;
@@ -274,8 +277,8 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
* grabbing the forcewake. However the potential error from timer call-
* back delay greatly dominates this so we keep it simple.
*/
- engines_sample(i915, period_ns);
- frequency_sample(i915, period_ns);
+ engines_sample(gt, period_ns);
+ frequency_sample(gt, period_ns);
hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
--
2.20.1
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[Intel-gfx] [CI 2/4] drm/i915/pmu: Convert engine sampling to uncore mmio
From: Tvrtko Ursulin
Drops one macro using implicit dev_priv.
v2:
* Use ENGINE_READ_FW. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 12008966b00e..09265b6b78b2 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -162,29 +162,30 @@ add_sample(struct i915_pmu_sample *sample, u32 val)
}
static void
-engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
+engines_sample(struct drm_i915_private *i915, unsigned int period_ns)
{
+ struct intel_uncore *uncore = >uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
intel_wakeref_t wakeref;
unsigned long flags;
- if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
+ if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
wakeref = 0;
- if (READ_ONCE(dev_priv->gt.awake))
- wakeref = intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
+ if (READ_ONCE(i915->gt.awake))
+ wakeref = intel_runtime_pm_get_if_in_use(>runtime_pm);
if (!wakeref)
return;
- spin_lock_irqsave(_priv->uncore.lock, flags);
- for_each_engine(engine, dev_priv, id) {
+ spin_lock_irqsave(>lock, flags);
+ for_each_engine(engine, i915, id) {
struct intel_engine_pmu *pmu = >pmu;
bool busy;
u32 val;
- val = I915_READ_FW(RING_CTL(engine->mmio_base));
+ val = ENGINE_READ_FW(engine, RING_CTL);
if (val == 0) /* powerwell off => engine idle */
continue;
@@ -202,15 +203,15 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
*/
busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT);
if (!busy) {
- val = I915_READ_FW(RING_MI_MODE(engine->mmio_base));
+ val = ENGINE_READ_FW(engine, RING_MI_MODE);
busy = !(val & MODE_IDLE);
}
if (busy)
add_sample(>sample[I915_SAMPLE_BUSY], period_ns);
}
- spin_unlock_irqrestore(_priv->uncore.lock, flags);
+ spin_unlock_irqrestore(>lock, flags);
- intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+ intel_runtime_pm_put(>runtime_pm, wakeref);
}
static void
--
2.20.1
___
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[Intel-gfx] [CI 1/4] drm/i915/pmu: Make more struct i915_pmu centric
From: Tvrtko Ursulin
Just tidy the code a bit by removing a sea of overly verbose i915->pmu.*.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 194 +---
1 file changed, 104 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..12008966b00e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -74,8 +74,9 @@ static unsigned int event_enabled_bit(struct perf_event
*event)
return config_enabled_bit(event->attr.config);
}
-static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
+static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
{
+ struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
u64 enable;
/*
@@ -83,7 +84,7 @@ static bool pmu_needs_timer(struct drm_i915_private *i915,
bool gpu_active)
*
* We start with a bitmask of all currently enabled events.
*/
- enable = i915->pmu.enable;
+ enable = pmu->enable;
/*
* Mask out all the ones which do not need the timer, or in
@@ -114,24 +115,26 @@ static bool pmu_needs_timer(struct drm_i915_private
*i915, bool gpu_active)
void i915_pmu_gt_parked(struct drm_i915_private *i915)
{
- if (!i915->pmu.base.event_init)
+ struct i915_pmu *pmu = >pmu;
+
+ if (!pmu->base.event_init)
return;
- spin_lock_irq(>pmu.lock);
+ spin_lock_irq(>lock);
/*
* Signal sampling timer to stop if only engine events are enabled and
* GPU went idle.
*/
- i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
- spin_unlock_irq(>pmu.lock);
+ pmu->timer_enabled = pmu_needs_timer(pmu, false);
+ spin_unlock_irq(>lock);
}
-static void __i915_pmu_maybe_start_timer(struct drm_i915_private *i915)
+static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
{
- if (!i915->pmu.timer_enabled && pmu_needs_timer(i915, true)) {
- i915->pmu.timer_enabled = true;
- i915->pmu.timer_last = ktime_get();
- hrtimer_start_range_ns(>pmu.timer,
+ if (!pmu->timer_enabled && pmu_needs_timer(pmu, true)) {
+ pmu->timer_enabled = true;
+ pmu->timer_last = ktime_get();
+ hrtimer_start_range_ns(>timer,
ns_to_ktime(PERIOD), 0,
HRTIMER_MODE_REL_PINNED);
}
@@ -139,15 +142,17 @@ static void __i915_pmu_maybe_start_timer(struct
drm_i915_private *i915)
void i915_pmu_gt_unparked(struct drm_i915_private *i915)
{
- if (!i915->pmu.base.event_init)
+ struct i915_pmu *pmu = >pmu;
+
+ if (!pmu->base.event_init)
return;
- spin_lock_irq(>pmu.lock);
+ spin_lock_irq(>lock);
/*
* Re-enable sampling timer when GPU goes active.
*/
- __i915_pmu_maybe_start_timer(i915);
- spin_unlock_irq(>pmu.lock);
+ __i915_pmu_maybe_start_timer(pmu);
+ spin_unlock_irq(>lock);
}
static void
@@ -251,15 +256,16 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
{
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
+ struct i915_pmu *pmu = >pmu;
unsigned int period_ns;
ktime_t now;
- if (!READ_ONCE(i915->pmu.timer_enabled))
+ if (!READ_ONCE(pmu->timer_enabled))
return HRTIMER_NORESTART;
now = ktime_get();
- period_ns = ktime_to_ns(ktime_sub(now, i915->pmu.timer_last));
- i915->pmu.timer_last = now;
+ period_ns = ktime_to_ns(ktime_sub(now, pmu->timer_last));
+ pmu->timer_last = now;
/*
* Strictly speaking the passed in period may not be 100% accurate for
@@ -443,6 +449,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
{
#if IS_ENABLED(CONFIG_PM)
struct intel_runtime_pm *rpm = >runtime_pm;
+ struct i915_pmu *pmu = >pmu;
intel_wakeref_t wakeref;
unsigned long flags;
u64 val;
@@ -458,16 +465,16 @@ static u64 get_rc6(struct drm_i915_private *i915)
* previously.
*/
- spin_lock_irqsave(>pmu.lock, flags);
+ spin_lock_irqsave(>lock, flags);
- if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
- i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
- i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
+ if (val >= pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
+ pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
+ pmu->sample[__I915_SAMPLE_RC6].cur = val;
} else {
- val =
Re: [Intel-gfx] [PATCH 03/23] drm/i915: Remove lrc default desc from GEM context
On 01/08/2019 17:00, Chris Wilson wrote:
Quoting Chris Wilson (2019-08-01 16:48:33)
Quoting Tvrtko Ursulin (2019-08-01 16:29:53)
For instance Icelake engine dependent stuff sneaked into
intel_lrc.c/lrc_desriptors at some point, which is also against the
spirit of caching. If we were to move the cached value in ce then we
would be able to remove that and have it once again minimal in there.
Well we can set all bits but hw_id/lrca at init time. How about if I run
that past you?
static u64
-lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
+base_lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
{
- struct i915_gem_context *ctx = ce->gem_context;
u64 desc;
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
@@ -426,18 +425,12 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
if (IS_GEN(engine->i915, 8))
desc |= GEN8_CTX_L3LLC_COHERENT;
- desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
- /* bits 12-31 */
/*
* The following 32bits are copied into the OA reports (dword 2).
* Consider updating oa_get_render_ctx_id in i915_perf.c when changing
* anything below.
*/
if (INTEL_GEN(engine->i915) >= 11) {
- GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
- desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
- /* bits 37-47 */
-
desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
/* bits 48-53
*/
@@ -445,8 +438,29 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
/* bits 61-63
*/
+ }
+
+ return desc;
+}
+
+static u64
+update_lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
+{
+ struct i915_gem_context *ctx = ce->gem_context;
+ u64 desc = ce->lrc_desc;
+
+ desc &= ~GENMASK_ULL(31, 12);
+ desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
+
+ if (INTEL_GEN(engine->i915) >= 11) {
+ GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
+
+ desc &= ~GENMASK_ULL(47, 37);
+ desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
} else {
GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
+
+ desc &= ~GENMASK_ULL(52, 32);
desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52
*/
}
@@ -1631,7 +1645,7 @@ __execlists_context_pin(struct intel_context *ce,
if (ret)
goto unpin_map;
- ce->lrc_desc = lrc_descriptor(ce, engine);
+ ce->lrc_desc = update_lrc_descriptor(ce, engine);
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
__execlists_update_reg_state(ce, engine);
@@ -3126,6 +3140,8 @@ static int execlists_context_deferred_alloc(struct
intel_context *ce,
ce->ring = ring;
ce->state = vma;
+ ce->lrc_desc = base_lrc_descriptor(ce, engine);
+
return 0;
error_ring_free:
That's pretty much the same amount of work in context_pin. I'm not
convinced that caching between pins achieves very much.
Concur?
Who kidnapped real Chris? :D We could merge the mask clearing and reduce
pin to one conditional and one and, shift, or. :)
Okay, have it your way.
Regards,
Tvrtko
___
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for add more probe failures (rev3)
On Thu, 01 Aug 2019 17:27:22 +0200, Chris Wilson wrote: <7> [229.655762] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin <7> [229.656489] [drm:intel_uc_fw_upload [i915]] HuC fw xfer completed <6> [229.656490] [drm] HuC: Loaded firmware i915/kbl_huc_ver02_00_1810.bin (version 2.0) we loaded HuC fw here <7> [229.656579] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/kbl_guc_33.0.0.bin <6> [229.656639] i915 :00:02.0: [drm:__i915_inject_load_error [i915]] Injecting failure -8 at checkpoint 15 [intel_uc_fw_upload:427] <7> [229.656688] [drm:intel_uc_init_hw [i915]] GuC fw load failed: -8; will reset and retry 2 more time(s) <7> [229.656739] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin <3> [229.656740] intel_uc_fw_upload:425 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)) and now we try again (Gen9 feature!) That looks significant. So, success? \o/ Yes! the other good news is ICL was clean! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/3] drm/i915: Add i915 to i915_inject_probe_failure
With i915 added to i915_inject_probe_failure we can use dedicated
printk when injecting artificial load failure.
Also make this function look like other i915 functions that return
error code and make it more flexible to return any provided error
code instead of previously assumed -ENODEV.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/display/intel_connector.c| 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 27 ++-
drivers/gpu/drm/i915/i915_drv.h | 12 +
drivers/gpu/drm/i915/i915_gem.c | 10 +++
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
drivers/gpu/drm/i915/intel_wopcm.c| 2 +-
9 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c
b/drivers/gpu/drm/i915/display/intel_connector.c
index d0163d86c42a..cf8823ce9606 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -118,7 +118,7 @@ int intel_connector_register(struct drm_connector
*connector)
if (ret)
goto err;
- if (i915_inject_probe_failure()) {
+ if (i915_inject_probe_failure(to_i915(connector->dev))) {
ret = -EFAULT;
goto err_backlight;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 65cbf1d9118d..8bd9a9adf4a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -426,7 +426,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
WARN_ON(engine_mask &
GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(i915))
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 761726818a22..cdbc334726b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -83,19 +83,20 @@ static struct drm_driver driver;
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
static unsigned int i915_probe_fail_count;
-bool __i915_inject_probe_failure(const char *func, int line)
+int __i915_inject_load_error(struct drm_i915_private *i915, int err,
+const char *func, int line)
{
if (i915_probe_fail_count >= i915_modparams.inject_load_failure)
- return false;
+ return 0;
- if (++i915_probe_fail_count == i915_modparams.inject_load_failure) {
- DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
-i915_modparams.inject_load_failure, func, line);
- i915_modparams.inject_load_failure = 0;
- return true;
- }
+ if (++i915_probe_fail_count < i915_modparams.inject_load_failure)
+ return 0;
- return false;
+ __i915_printk(i915, KERN_INFO,
+ "Injecting failure %d at checkpoint %u [%s:%d]\n",
+ err, i915_modparams.inject_load_failure, func, line);
+ i915_modparams.inject_load_failure = 0;
+ return err;
}
bool i915_error_injected(void)
@@ -687,7 +688,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
struct pci_dev *pdev = dev_priv->drm.pdev;
int ret;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
if (HAS_DISPLAY(dev_priv)) {
@@ -894,7 +895,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
{
int ret = 0;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
intel_device_info_subplatform_init(dev_priv);
@@ -985,7 +986,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
{
int ret;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
if (i915_get_bridge_dev(dev_priv))
@@ -1530,7 +1531,7 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
struct pci_dev *pdev = dev_priv->drm.pdev;
int ret;
- if (i915_inject_probe_failure())
+ if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
intel_device_info_runtime_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4f492c05d065..a92fcd5df79b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -122,19 +122,21 @@
#if
[Intel-gfx] [CI 2/3] drm/i915/uc: Inject probe errors into intel_uc_init_hw
Inject probe errors into intel_uc_init_hw to make sure we
correctly handle any uC initialization failure.
To avoid complains from CI about injected errors use
i915_probe_error to lower message level.
v2: _sanitize instead _reset to correctly handle Gen9 retries
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson #v1
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 24
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 +
drivers/gpu/drm/i915/i915_gem.c | 2 +-
4 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index c9535caba844..a696ce0fec62 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -139,6 +139,10 @@ int intel_huc_auth(struct intel_huc *huc)
GEM_BUG_ON(!intel_uc_fw_is_loaded(>fw));
GEM_BUG_ON(intel_huc_is_authenticated(huc));
+ ret = i915_inject_load_error(gt->i915, -ENXIO);
+ if (ret)
+ goto fail;
+
ret = intel_guc_auth_huc(guc,
intel_guc_ggtt_offset(guc, huc->rsa_data));
if (ret) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 66b226be6759..db16eef7795d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -41,6 +41,10 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
int ret;
u32 guc_status;
+ ret = i915_inject_load_error(gt->i915, -ENXIO);
+ if (ret)
+ return ret;
+
ret = intel_reset_guc(gt);
if (ret) {
DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
@@ -245,6 +249,10 @@ static int guc_enable_communication(struct intel_guc *guc)
GEM_BUG_ON(guc_communication_enabled(guc));
+ ret = i915_inject_load_error(i915, -ENXIO);
+ if (ret)
+ return ret;
+
ret = intel_guc_ct_enable(>ct);
if (ret)
return ret;
@@ -376,7 +384,7 @@ void intel_uc_fini(struct intel_uc *uc)
intel_guc_fini(guc);
}
-static void __uc_sanitize(struct intel_uc *uc)
+static int __uc_sanitize(struct intel_uc *uc)
{
struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
@@ -386,7 +394,7 @@ static void __uc_sanitize(struct intel_uc *uc)
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
- __intel_uc_reset_hw(uc);
+ return __intel_uc_reset_hw(uc);
}
void intel_uc_sanitize(struct intel_uc *uc)
@@ -414,6 +422,10 @@ static int uc_init_wopcm(struct intel_uc *uc)
GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
+ err = i915_inject_load_error(gt->i915, -ENXIO);
+ if (err)
+ return err;
+
mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
size | GUC_WOPCM_SIZE_LOCKED);
@@ -470,7 +482,7 @@ int intel_uc_init_hw(struct intel_uc *uc)
* Always reset the GuC just before (re)loading, so
* that the state and timing are fairly predictable
*/
- ret = __intel_uc_reset_hw(uc);
+ ret = __uc_sanitize(uc);
if (ret)
goto err_out;
@@ -514,6 +526,10 @@ int intel_uc_init_hw(struct intel_uc *uc)
goto err_communication;
}
+ ret = i915_inject_load_error(i915, -ENXIO);
+ if (ret)
+ goto err_communication;
+
dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
guc->fw.major_ver_found, guc->fw.minor_ver_found);
dev_info(i915->drm.dev, "GuC submission %s\n",
@@ -540,7 +556,7 @@ int intel_uc_init_hw(struct intel_uc *uc)
if (GEM_WARN_ON(ret == -EIO))
ret = -EINVAL;
- dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
+ i915_probe_error(i915, "GuC initialization failed %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index ac91e3efd02b..734b20bf635f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -424,8 +424,13 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, struct
intel_gt *gt,
/* make sure the status was cleared the last time we reset the uc */
GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw));
+ err = i915_inject_load_error(gt->i915, -ENOEXEC);
+ if (err)
+ return err;
+
if (!intel_uc_fw_is_available(uc_fw))
return -ENOEXEC;
+
/* Call custom loader */
intel_uc_fw_ggtt_bind(uc_fw, gt);
err =
[Intel-gfx] [CI 0/3] add more probe failures
v3: fix Gen9 issue discovered by the v2 Michal Wajdeczko (3): drm/i915: Add i915 to i915_inject_probe_failure drm/i915/uc: Inject probe errors into intel_uc_init_hw drm/i915/wopcm: Don't fail on WOPCM partitioning failure .../gpu/drm/i915/display/intel_connector.c| 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 +++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 29 +++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 drivers/gpu/drm/i915/i915_drv.c | 27 + drivers/gpu/drm/i915/i915_drv.h | 12 drivers/gpu/drm/i915/i915_gem.c | 18 --- drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/intel_gvt.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 2 +- drivers/gpu/drm/i915/intel_wopcm.c| 30 +-- drivers/gpu/drm/i915/intel_wopcm.h| 2 +- 13 files changed, 82 insertions(+), 55 deletions(-) -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/3] drm/i915/wopcm: Don't fail on WOPCM partitioning failure
We don't have to immediately fail on WOPCM partitioning, we can wait
until we will start programming WOPCM registers. This should give us
more options if we decide to restore fallback in case of GuC failures.
v2: rebased
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 5 +
drivers/gpu/drm/i915/i915_gem.c | 6 +-
drivers/gpu/drm/i915/intel_wopcm.c| 28 +--
drivers/gpu/drm/i915/intel_wopcm.h| 2 +-
4 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index db16eef7795d..985d863b879d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -416,6 +416,11 @@ static int uc_init_wopcm(struct intel_uc *uc)
u32 mask;
int err;
+ if (unlikely(!base || !size)) {
+ i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ return -E2BIG;
+ }
+
GEM_BUG_ON(!intel_uc_is_using_guc(uc));
GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 54a10c8c4dff..278fa44815e2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1441,10 +1441,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
return ret;
intel_uc_fetch_firmwares(_priv->gt.uc);
-
- ret = intel_wopcm_init(_priv->wopcm);
- if (ret)
- goto err_uc_fw;
+ intel_wopcm_init(_priv->wopcm);
/* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -1568,7 +1565,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-err_uc_fw:
intel_uc_cleanup_firmwares(_priv->gt.uc);
if (ret != -EIO) {
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 291881937d97..4c22143ee84f 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -156,12 +156,10 @@ static inline int check_hw_restriction(struct
drm_i915_private *i915,
* This function will partition WOPCM space based on GuC and HuC firmware sizes
* and will allocate max remaining for use by GuC. This function will also
* enforce platform dependent hardware restrictions on GuC WOPCM offset and
- * size. It will fail the WOPCM init if any of these checks were failed, so
that
- * the following GuC firmware uploading would be aborted.
- *
- * Return: 0 on success, non-zero error code on failure.
+ * size. It will fail the WOPCM init if any of these checks fail, so that the
+ * following WOPCM registers setup and GuC firmware uploading would be aborted.
*/
-int intel_wopcm_init(struct intel_wopcm *wopcm)
+void intel_wopcm_init(struct intel_wopcm *wopcm)
{
struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
u32 guc_fw_size = intel_uc_fw_get_upload_size(>gt.uc.guc.fw);
@@ -173,23 +171,25 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
int err;
if (!USES_GUC(i915))
- return 0;
+ return;
GEM_BUG_ON(!wopcm->size);
+ GEM_BUG_ON(wopcm->guc.base);
+ GEM_BUG_ON(wopcm->guc.size);
if (i915_inject_probe_failure(i915))
- return -E2BIG;
+ return;
if (guc_fw_size >= wopcm->size) {
DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
guc_fw_size / 1024);
- return -E2BIG;
+ return;
}
if (huc_fw_size >= wopcm->size) {
DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
huc_fw_size / 1024);
- return -E2BIG;
+ return;
}
guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
@@ -197,7 +197,7 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
guc_wopcm_base / 1024);
- return -E2BIG;
+ return;
}
guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
@@ -211,16 +211,16 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
(guc_fw_size + guc_wopcm_rsvd) / 1024,
guc_wopcm_size / 1024);
- return -E2BIG;
+ return;
}
err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
Re: [Intel-gfx] [PATCH 03/23] drm/i915: Remove lrc default desc from GEM context
Quoting Chris Wilson (2019-08-01 16:48:33)
> Quoting Tvrtko Ursulin (2019-08-01 16:29:53)
> > For instance Icelake engine dependent stuff sneaked into
> > intel_lrc.c/lrc_desriptors at some point, which is also against the
> > spirit of caching. If we were to move the cached value in ce then we
> > would be able to remove that and have it once again minimal in there.
>
> Well we can set all bits but hw_id/lrca at init time. How about if I run
> that past you?
static u64
-lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
+base_lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
{
- struct i915_gem_context *ctx = ce->gem_context;
u64 desc;
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
@@ -426,18 +425,12 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
if (IS_GEN(engine->i915, 8))
desc |= GEN8_CTX_L3LLC_COHERENT;
- desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
- /* bits 12-31 */
/*
* The following 32bits are copied into the OA reports (dword 2).
* Consider updating oa_get_render_ctx_id in i915_perf.c when changing
* anything below.
*/
if (INTEL_GEN(engine->i915) >= 11) {
- GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
- desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
- /* bits 37-47 */
-
desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
/* bits 48-53 */
@@ -445,8 +438,29 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
/* bits 61-63 */
+ }
+
+ return desc;
+}
+
+static u64
+update_lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
+{
+ struct i915_gem_context *ctx = ce->gem_context;
+ u64 desc = ce->lrc_desc;
+
+ desc &= ~GENMASK_ULL(31, 12);
+ desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
+
+ if (INTEL_GEN(engine->i915) >= 11) {
+ GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
+
+ desc &= ~GENMASK_ULL(47, 37);
+ desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
} else {
GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
+
+ desc &= ~GENMASK_ULL(52, 32);
desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
}
@@ -1631,7 +1645,7 @@ __execlists_context_pin(struct intel_context *ce,
if (ret)
goto unpin_map;
- ce->lrc_desc = lrc_descriptor(ce, engine);
+ ce->lrc_desc = update_lrc_descriptor(ce, engine);
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
__execlists_update_reg_state(ce, engine);
@@ -3126,6 +3140,8 @@ static int execlists_context_deferred_alloc(struct
intel_context *ce,
ce->ring = ring;
ce->state = vma;
+ ce->lrc_desc = base_lrc_descriptor(ce, engine);
+
return 0;
error_ring_free:
That's pretty much the same amount of work in context_pin. I'm not
convinced that caching between pins achieves very much.
Concur?
-Chris
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[Intel-gfx] [PATCH v4 5/5] drm/i915/pmu: Support multiple GPUs
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devices
handled by us. Integrated devices keep the legacy name preserving
backward compatibility.
v2:
* Detect IGP and keep legacy name. (Michal)
* Use PCI device name as suffix. (Michal, Chris)
v3:
* Constify the name. (Chris)
* Use pci_domain_nr. (Chris)
v4:
* Fix kfree_const usage. (Chris)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Michal Wajdeczko
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 25 +++--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e0e0180bca7c..e0fea227077e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1053,6 +1053,15 @@ static void i915_pmu_unregister_cpuhp_state(struct
i915_pmu *pmu)
cpuhp_remove_multi_state(cpuhp_slot);
}
+static bool is_igp(struct pci_dev *pdev)
+{
+ /* IGP is :00:02.0 */
+ return pci_domain_nr(pdev->bus) == 0 &&
+ pdev->bus->number == 0 &&
+ PCI_SLOT(pdev->devfn) == 2 &&
+ PCI_FUNC(pdev->devfn) == 0;
+}
+
void i915_pmu_register(struct drm_i915_private *i915)
{
struct i915_pmu *pmu = >pmu;
@@ -1083,10 +1092,19 @@ void i915_pmu_register(struct drm_i915_private *i915)
hrtimer_init(>timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
pmu->timer.function = i915_sample;
- ret = perf_pmu_register(>base, "i915", -1);
- if (ret)
+ if (!is_igp(i915->drm.pdev))
+ pmu->name = kasprintf(GFP_KERNEL,
+ "i915-%s",
+ dev_name(i915->drm.dev));
+ else
+ pmu->name = "i915";
+ if (!pmu->name)
goto err;
+ ret = perf_pmu_register(>base, pmu->name, -1);
+ if (ret)
+ goto err_name;
+
ret = i915_pmu_register_cpuhp_state(pmu);
if (ret)
goto err_unreg;
@@ -1095,6 +1113,8 @@ void i915_pmu_register(struct drm_i915_private *i915)
err_unreg:
perf_pmu_unregister(>base);
+err_name:
+ kfree_const(pmu->name);
err:
pmu->base.event_init = NULL;
free_event_attributes(pmu);
@@ -1116,5 +1136,6 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
perf_pmu_unregister(>base);
pmu->base.event_init = NULL;
+ kfree_const(pmu->name);
free_event_attributes(pmu);
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 4fc4f2478301..ff24f3bb0102 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -46,6 +46,10 @@ struct i915_pmu {
* @base: PMU base.
*/
struct pmu base;
+ /**
+* @name: Name as registered with perf core.
+*/
+ const char *name;
/**
* @lock: Lock protecting enable mask and ref count handling.
*/
--
2.20.1
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Re: [Intel-gfx] [PATCH 03/23] drm/i915: Remove lrc default desc from GEM context
Quoting Tvrtko Ursulin (2019-08-01 16:29:53) > > On 01/08/2019 12:13, Chris Wilson wrote: > > Quoting Chris Wilson (2019-08-01 11:57:06) > >> Quoting Tvrtko Ursulin (2019-08-01 09:53:15) > >>> We could store it in ce then. We already have well defined control > >>> points for when vm changes when all are updated. > >> > >> We are storing it in ce; it's not like we recompute it all that often, > >> and when we do it's because we have rebound the vma. > >> > >>> If done like this then it looks like assigning ctx->hw_id could also do > >>> the default_desc update, so that we can avoid even more work done at pin > >>> time. > >> > >> What ctx->hw_id? You are imagining things again :-p > >> > >> Remember that we only do this on first pin from idle, not every pin. > > > > Fwiw, I quickly looked at only doing it if the vma is rebound, but > > that's move branches just to save a couple. The low frequency at which > > we have to actually compute this (walk a few more branches inside an > > already branchy contxt_pin) doesn't seem to justify the extra storage for > > me. It's not like we are recomputing lrc_desc on every submit as it once > > was. > > On every submit if last request got retired in the meantime, no, for > instance bursty loads? Yeah it is very inconsequential but at some point > we made an effort to cache as much as possible what is invariant so it > saddens me a bit to remove that. Once we have hw_id out of the way, we only need to set the bottom 32b here. > For instance Icelake engine dependent stuff sneaked into > intel_lrc.c/lrc_desriptors at some point, which is also against the > spirit of caching. If we were to move the cached value in ce then we > would be able to remove that and have it once again minimal in there. Well we can set all bits but hw_id/lrca at init time. How about if I run that past you? > Not only just minimal, but not separated in two separate places. I guess > this patch improves things in that respect - consolidates the lrc_desc > computation once again. > > I did not get the part about VMA re-binding. I did not suggest to move > the lrca offset into cache as well. I was just thinking about the gen, > engine and vm dependent bits could naturally go into > i915_gem_context.c/default_desc_template. Just need to take (engine, > hw_id, vm). I'm just thinking about the bit that changes inside ce->lrc_desc. > And virtual engine would have to re-compute it when moving engines. Hm.. > we don't seem to do that? Only when pinning we set it up based on > sibling[0] so how it all works? We don't re-pin when moving engine I > thought. No. We don't. Whoops. Good job clearly nothing uses that then. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/pmu: Support multiple GPUs
Quoting Tvrtko Ursulin (2019-08-01 16:08:04) > @@ -1095,6 +1113,9 @@ void i915_pmu_register(struct drm_i915_private *i915) > > err_unreg: > perf_pmu_unregister(>base); > +err_name: > + if (!is_igp(i915->drm.pdev)) > + kfree_const(pmu->name); With the kfree_const() magic you don't need to test again for !is_igp(), it applies that for you by only freeing if it is not a static string. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: add syncobj timeline support
On 01/08/2019 18:16, Chris Wilson wrote: Quoting Lionel Landwerlin (2019-08-01 15:29:34) On 31/07/2019 23:03, Chris Wilson wrote: Quoting Lionel Landwerlin (2019-07-31 15:07:33) ... I think I have convinced myself that with the split between wait before, signal after combined with the rule that seqno point along the syncobj are monotonic, you should not be able to generate an AB-BA deadlock between concurrent clients. Can you come up with an example that would deadlock? Timeline holds 2,1; a wait on 2 will fail with -EINVAL to userspace. (Though possibly perfectly valid behaviour on the part of the user.) Timeline holds 2, with 1 being submitted. A wait on 1 waits on 2 instead. If 1 gains a dependency on A (e.g. bad userspace or an You mean : 1 gains a dependency on 2? implicit fence, it's a concurrent wait/submit so expect the worst, i.e. userspace has to be racing with itself to get into this mess), you now have a deadlock. Not quite sure I see why... 2 doesn't have any dependency on 1, it just happens to have a number higher. -Lionel (The assumption being that the syncpt along the timeline are themselves not strictly ordered, and considering they are external syncobj, that seems like a reasonable generalisation.) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915/pmu: Support multiple GPUs
On 01/08/2019 16:20, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-08-01 16:10:14) On 01/08/2019 15:54, Chris Wilson wrote: Works for me, I wonder what PeterZ will say... In what sense? Just wondering if he has a plan for hotpluggable pmu devices. I can certainly imagine his surprise in the future when he finds an adhoc scheme in a random driver. There is time to run this past him. I'll send something out. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/23] drm/i915: Remove lrc default desc from GEM context
On 01/08/2019 12:13, Chris Wilson wrote: Quoting Chris Wilson (2019-08-01 11:57:06) Quoting Tvrtko Ursulin (2019-08-01 09:53:15) We could store it in ce then. We already have well defined control points for when vm changes when all are updated. We are storing it in ce; it's not like we recompute it all that often, and when we do it's because we have rebound the vma. If done like this then it looks like assigning ctx->hw_id could also do the default_desc update, so that we can avoid even more work done at pin time. What ctx->hw_id? You are imagining things again :-p Remember that we only do this on first pin from idle, not every pin. Fwiw, I quickly looked at only doing it if the vma is rebound, but that's move branches just to save a couple. The low frequency at which we have to actually compute this (walk a few more branches inside an already branchy contxt_pin) doesn't seem to justify the extra storage for me. It's not like we are recomputing lrc_desc on every submit as it once was. On every submit if last request got retired in the meantime, no, for instance bursty loads? Yeah it is very inconsequential but at some point we made an effort to cache as much as possible what is invariant so it saddens me a bit to remove that. For instance Icelake engine dependent stuff sneaked into intel_lrc.c/lrc_desriptors at some point, which is also against the spirit of caching. If we were to move the cached value in ce then we would be able to remove that and have it once again minimal in there. Not only just minimal, but not separated in two separate places. I guess this patch improves things in that respect - consolidates the lrc_desc computation once again. I did not get the part about VMA re-binding. I did not suggest to move the lrca offset into cache as well. I was just thinking about the gen, engine and vm dependent bits could naturally go into i915_gem_context.c/default_desc_template. Just need to take (engine, hw_id, vm). And virtual engine would have to re-compute it when moving engines. Hm.. we don't seem to do that? Only when pinning we set it up based on sibling[0] so how it all works? We don't re-pin when moving engine I thought. Aside that, if you are still not convinced my argument makes sense, you can have my ack. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for add more probe failures (rev3)
Quoting Patchwork (2019-08-01 16:22:20) > == Series Details == > > Series: add more probe failures (rev3) > URL : https://patchwork.freedesktop.org/series/64390/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13830 > > > Summary > --- > > **FAILURE** > Possible regressions > > * igt@i915_module_load@reload-with-fault-injection: > - fi-cfl-guc: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html > - fi-skl-guc: [PASS][3] -> [INCOMPLETE][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-skl-guc/igt@i915_module_l...@reload-with-fault-injection.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-skl-guc/igt@i915_module_l...@reload-with-fault-injection.html > - fi-kbl-guc: [PASS][5] -> [INCOMPLETE][6] >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-guc/igt@i915_module_l...@reload-with-fault-injection.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-kbl-guc/igt@i915_module_l...@reload-with-fault-injection.html <7> [229.652594] [drm:intel_uc_fw_fetch [i915]] GuC fw size 182912 ptr 70788d09 <7> [229.652626] [drm:intel_uc_fw_fetch [i915]] GuC fw version 33.0 (wanted 33.0) <7> [229.652895] [drm:intel_uc_fw_fetch [i915]] HuC fw size 218688 ptr 70788d09 <7> [229.652925] [drm:intel_uc_fw_fetch [i915]] HuC fw version 2.0 (wanted 2.0) <7> [229.653095] [drm:intel_wopcm_init [i915]] Calculated GuC WOPCM Region: [240KiB, 784KiB) <7> [229.653142] [drm:i915_init_ggtt [i915]] clearing unused GTT space: [1000, fee0] <7> [229.653522] [drm:intel_engines_setup [i915]] Initialized 5 engine workarounds on rcs0 <7> [229.653556] [drm:intel_engines_setup [i915]] Initialized 4 whitelist workarounds on rcs0 <7> [229.653609] [drm:__intel_engine_init_ctx_wa [i915]] Initialized 14 context workarounds on rcs0 <7> [229.653920] [drm:i915_gem_contexts_init [i915]] logical context support initialized <7> [229.654996] [drm:intel_guc_log_create [i915]] guc_log_level=5 (enabled, verbose:yes, verbosity:3) <7> [229.655251] [drm:intel_guc_init [i915]] param[ 0] = 0x0 <7> [229.655284] [drm:intel_guc_init [i915]] param[ 1] = 0xc9fd3 <7> [229.655314] [drm:intel_guc_init [i915]] param[ 2] = 0x0 <7> [229.655344] [drm:intel_guc_init [i915]] param[ 3] = 0x4000 <7> [229.655374] [drm:intel_guc_init [i915]] param[ 4] = 0x3 <7> [229.655418] [drm:intel_guc_init [i915]] param[ 5] = 0x1b8 <7> [229.655446] [drm:intel_guc_init [i915]] param[ 6] = 0x0 <7> [229.655473] [drm:intel_guc_init [i915]] param[ 7] = 0x0 <7> [229.655501] [drm:intel_guc_init [i915]] param[ 8] = 0x0 <7> [229.655528] [drm:intel_guc_init [i915]] param[ 9] = 0x0 <7> [229.66] [drm:intel_guc_init [i915]] param[10] = 0x0 <7> [229.655583] [drm:intel_guc_init [i915]] param[11] = 0x0 <7> [229.655610] [drm:intel_guc_init [i915]] param[12] = 0x0 <7> [229.655637] [drm:intel_guc_init [i915]] param[13] = 0x0 <7> [229.655762] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin <7> [229.656489] [drm:intel_uc_fw_upload [i915]] HuC fw xfer completed <6> [229.656490] [drm] HuC: Loaded firmware i915/kbl_huc_ver02_00_1810.bin (version 2.0) <7> [229.656579] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/kbl_guc_33.0.0.bin <6> [229.656639] i915 :00:02.0: [drm:__i915_inject_load_error [i915]] Injecting failure -8 at checkpoint 15 [intel_uc_fw_upload:427] <7> [229.656688] [drm:intel_uc_init_hw [i915]] GuC fw load failed: -8; will reset and retry 2 more time(s) <7> [229.656739] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin <3> [229.656740] intel_uc_fw_upload:425 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)) <4> [229.656798] [ cut here ] <2> [229.656800] kernel BUG at drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:425! <4> [229.656813] invalid opcode: [#1] PREEMPT SMP PTI <4> [229.656817] CPU: 1 PID: 3279 Comm: i915_module_loa Tainted: G U 5.3.0-rc2-CI-Patchwork_13830+ #1 <4> [229.656822] Hardware name: Micro-Star International Co., Ltd. MS-7B54/Z370M MORTAR (MS-7B54), BIOS 1.10 12/28/2017 <4> [229.656857] RIP: 0010:intel_uc_fw_upload+0x314/0x3b0 [i915] <4> [229.656861] Code: 0b 51 ed e0 48 8b 35 a3 13 1c 00 49 c7 c0 ac 69 38 a0 b9 a9 01 00 00 48 c7 c2 a0 df 32 a0 48 c7 c7 cf 93 25 a0 e8 3c 34 f4 e0 <0f> 0b 48 c7 c1 98 e5 35 a0 ba 79 00 00 00 48 c7 c6 c0 df 32 a0 48 <4> [229.656870] RSP: 0018:c9aff948 EFLAGS: 00010286 <4> [229.656873] RAX: 000e RBX: 8882214fc4b0 RCX: <4> [229.656877] RDX: 0001 RSI: 0008 RDI: 0034
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Atomically acquire the gt_pm wakeref
Quoting Tvrtko Ursulin (2019-08-01 15:55:29) > > On 01/08/2019 15:39, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-08-01 15:21:17) > >> I guess I'll be rebasing mine, at some point. :) > > > > I anticipated you merging it at some point. > > This patch to my series or what? Your series to update the locals, those first patches should be non-controversial. The fixup is trivial either way. > > Had a thought, and we don't need gt_pm for the engine sampling, but > > rather intel_engine_pm_get_if_awake. > > I thought about it, but since we iterate all engines did not see a real > benefit. Wouldn't harm either, only some more CPU cycles in the loop, so > up to you. But also likely to save some work on larger devices if they are mostly idle, which I hope they typically are. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for add more probe failures (rev3)
== Series Details == Series: add more probe failures (rev3) URL : https://patchwork.freedesktop.org/series/64390/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13830 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13830 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13830, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13830: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-guc: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-skl-guc/igt@i915_module_l...@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-skl-guc/igt@i915_module_l...@reload-with-fault-injection.html - fi-kbl-guc: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-guc/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-kbl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@runner@aborted: - fi-cfl-guc: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-cfl-guc/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_13830 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-small-bo-tiledy: - fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html * igt@i915_module_load@reload-with-fault-injection: - fi-apl-guc: [PASS][10] -> [INCOMPLETE][11] ([fdo#103927]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-apl-guc/igt@i915_module_l...@reload-with-fault-injection.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-apl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [PASS][12] -> [WARN][13] ([fdo#109380]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [PASS][14] -> [SKIP][15] ([fdo#109271]) +23 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html * igt@prime_vgem@basic-fence-mmap: - fi-byt-j1900: [PASS][16] -> [INCOMPLETE][17] ([fdo#102657] / [fdo#111276]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-byt-j1900/igt@prime_v...@basic-fence-mmap.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-byt-j1900/igt@prime_v...@basic-fence-mmap.html - fi-gdg-551: [PASS][18] -> [INCOMPLETE][19] ([fdo#108316] / [fdo#111276]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-gdg-551/igt@prime_v...@basic-fence-mmap.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-gdg-551/igt@prime_v...@basic-fence-mmap.html - fi-pnv-d510:[PASS][20] -> [INCOMPLETE][21] ([fdo#110740] / [fdo#111276]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - fi-bsw-kefka: [PASS][22] -> [INCOMPLETE][23] ([fdo#111278]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13830/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
Re: [Intel-gfx] [PATCH 5/5] drm/i915/pmu: Support multiple GPUs
Quoting Tvrtko Ursulin (2019-08-01 16:10:14) > > On 01/08/2019 15:54, Chris Wilson wrote: > > Works for me, I wonder what PeterZ will say... > > In what sense? Just wondering if he has a plan for hotpluggable pmu devices. I can certainly imagine his surprise in the future when he finds an adhoc scheme in a random driver. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: add syncobj timeline support
Quoting Lionel Landwerlin (2019-08-01 15:29:34)
> On 31/07/2019 23:03, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-07-31 15:07:33)
> >> -static struct drm_syncobj **
> >> -get_fence_array(struct drm_i915_gem_execbuffer2 *args,
> >> - struct drm_file *file)
> >> +static struct i915_eb_fences *
> >> +get_timeline_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
> >> +{
> >> + struct drm_i915_gem_execbuffer_ext_timeline_fences
> >> *timeline_fences =
> >> + >extensions.timeline_fences;
> >> + struct drm_i915_gem_exec_fence __user *user_fences;
> >> + struct i915_eb_fences *fences;
> >> + u64 __user *user_values;
> >> + u64 num_fences, num_user_fences = timeline_fences->fence_count;
> >> + unsigned long n;
> >> + int err;
> >> +
> >> + /* Check multiplication overflow for access_ok() and
> >> kvmalloc_array() */
> >> + BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
> >> + if (num_user_fences > min_t(unsigned long,
> >> + ULONG_MAX / sizeof(*user_fences),
> >> + SIZE_MAX / sizeof(*fences)))
> >> + return ERR_PTR(-EINVAL);
> >> +
> >> + user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
> >> + if (!access_ok(user_fences, num_user_fences *
> >> sizeof(*user_fences)))
> >> + return ERR_PTR(-EFAULT);
> >> +
> >> + user_values = u64_to_user_ptr(timeline_fences->values_ptr);
> >> + if (!access_ok(user_values, num_user_fences *
> >> sizeof(*user_values)))
> >> + return ERR_PTR(-EFAULT);
> >> +
> >> + fences = kvmalloc_array(num_user_fences, sizeof(*fences),
> >> + __GFP_NOWARN | GFP_KERNEL);
> >> + if (!fences)
> >> + return ERR_PTR(-ENOMEM);
> >> +
> >> + BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
> >> +~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
> >> +
> >> + for (n = 0, num_fences = 0; n < timeline_fences->fence_count; n++)
> >> {
> >> + struct drm_i915_gem_exec_fence user_fence;
> >> + struct drm_syncobj *syncobj;
> >> + struct dma_fence *fence = NULL;
> >> + u64 point;
> >> +
> >> + if (__copy_from_user(_fence, user_fences++,
> >> sizeof(user_fence))) {
> >> + err = -EFAULT;
> >> + goto err;
> >> + }
> >> +
> >> + if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
> >> + err = -EINVAL;
> >> + goto err;
> >> + }
> >> +
> >> + if (__get_user(point, user_values++)) {
> >> + err = -EFAULT;
> >> + goto err;
> >> + }
> >> +
> >> + syncobj = drm_syncobj_find(eb->file, user_fence.handle);
> >> + if (!syncobj) {
> >> + DRM_DEBUG("Invalid syncobj handle provided\n");
> >> + err = -ENOENT;
> >> + goto err;
> >> + }
> >> +
> >> + if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
> >> + fence = drm_syncobj_fence_get(syncobj);
> >> + if (!fence) {
> >> + DRM_DEBUG("Syncobj handle has no fence\n");
> >> + drm_syncobj_put(syncobj);
> >> + err = -EINVAL;
> >> + goto err;
> >> + }
> >> +
> >> + err = dma_fence_chain_find_seqno(, point);
> >> + if (err) {
> >> + DRM_DEBUG("Syncobj handle missing
> >> requested point %llu\n", point);
> >> + drm_syncobj_put(syncobj);
> >> + goto err;
> >> + }
> >> +
> >> + /* A point might have been signaled already and
> >> +* garbage collected from the timeline. In this
> >> case
> >> +* just ignore the point and carry on.
> >> +*/
> >> + if (!fence) {
> >> + drm_syncobj_put(syncobj);
> >> + continue;
> >> + }
> >> + }
> >> +
> >> + /*
> >> +* For timeline syncobjs we need to preallocate chains for
> >> +* later signaling.
> >> +*/
> >> + if (point != 0 && user_fence.flags &
> >> I915_EXEC_FENCE_SIGNAL) {
> > if (dma_fence_chain_find_seqno() == 0)
> > return -EINVAL;
> >
> > as an early sanity check?
> >
> >> + fences[num_fences].chain_fence =
> >> +
> >>
[Intel-gfx] ✓ Fi.CI.IGT: success for Initial TGL submission changes
== Series Details == Series: Initial TGL submission changes URL : https://patchwork.freedesktop.org/series/64461/ State : success == Summary == CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13815_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13815_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][5] -> ([PASS][6], [INCOMPLETE][7]) ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl8/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl9/igt@gem_exec_susp...@basic-s3.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-skl4/igt@gem_exec_susp...@basic-s3.html * igt@gem_pwrite@huge-cpu-backwards: - shard-hsw: [PASS][8] -> ([INCOMPLETE][9], [PASS][10]) ([fdo#103540]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-hsw7/igt@gem_pwr...@huge-cpu-backwards.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw5/igt@gem_pwr...@huge-cpu-backwards.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw6/igt@gem_pwr...@huge-cpu-backwards.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][11] -> ([DMESG-WARN][12], [DMESG-WARN][13]) ([fdo#108566]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl4/igt@gem_soft...@noreloc-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl6/igt@gem_soft...@noreloc-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-kbl4/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_fence_blits@normal: - shard-iclb: [PASS][14] -> [INCOMPLETE][15] ([fdo#107713]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@gem_tiled_fence_bl...@normal.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb1/igt@gem_tiled_fence_bl...@normal.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][16] -> ([PASS][17], [FAIL][18]) ([fdo#105767]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-hsw2/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103184] / [fdo#103232]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@kms_draw_...@draw-method-rgb565-pwrite-xtiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-iclb8/igt@kms_draw_...@draw-method-rgb565-pwrite-xtiled.html * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-glk: [PASS][21] -> ([FAIL][22], [PASS][23]) ([fdo#103060]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-glk9/igt@kms_f...@2x-dpms-vs-vblank-race-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-glk4/igt@kms_f...@2x-dpms-vs-vblank-race-interruptible.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-glk7/igt@kms_f...@2x-dpms-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt: - shard-hsw: [PASS][24] -> ([PASS][25], [SKIP][26]) ([fdo#109271]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-hsw4/igt@kms_frontbuffer_track...@fbc-2p-primscrn-indfb-plflip-blt.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw5/igt@kms_frontbuffer_track...@fbc-2p-primscrn-indfb-plflip-blt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13815/shard-hsw2/igt@kms_frontbuffer_track...@fbc-2p-primscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt: -
Re: [Intel-gfx] [PATCH 5/5] drm/i915/pmu: Support multiple GPUs
On 01/08/2019 15:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-08-01 15:17:32)
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devices
handled by us. Integrated devices keep the legacy name preserving
backward compatibility.
v2:
* Detect IGP and keep legacy name. (Michal)
* Use PCI device name as suffix. (Michal, Chris)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Michal Wajdeczko
---
Is our GPU always ":00:02.0"? CI will tell me.
It always has been. (With a few additional 2.1 for Windows95 multihead
where each head had to be a unique device!)
One hopes that by now it is firmly ingrained that it will always be
kept to 00:02.0.
Re-assuring, thanks! However still some tests to do before I am happy
this is upstream worthy, not least CI.
---
drivers/gpu/drm/i915/i915_pmu.c | 27 +--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e0e0180bca7c..9a404d85c4e9 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1053,6 +1053,15 @@ static void i915_pmu_unregister_cpuhp_state(struct
i915_pmu *pmu)
cpuhp_remove_multi_state(cpuhp_slot);
}
+static bool is_igp(struct pci_dev *pdev)
+{
+ /* IGP is :00:02.0 */
+ return pdev->bus->parent == NULL &&
pci_domain_nr(pdev->bus) == 0 ?
Aha, thanks!
+ pdev->bus->number == 0 &&
+ PCI_SLOT(pdev->devfn) == 2 &&
+ PCI_FUNC(pdev->devfn) == 0;
I am surprised there isn't already a convenience function. None that I
could find.
+}
+
void i915_pmu_register(struct drm_i915_private *i915)
{
struct i915_pmu *pmu = >pmu;
@@ -1083,10 +1092,19 @@ void i915_pmu_register(struct drm_i915_private *i915)
hrtimer_init(>timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
pmu->timer.function = i915_sample;
- ret = perf_pmu_register(>base, "i915", -1);
- if (ret)
+ if (!is_igp(i915->drm.pdev))
+ pmu->name = kasprintf(GFP_KERNEL,
+ "i915-%s",
+ dev_name(i915->drm.dev));
+ else
+ pmu->name = "i915";
Makes sense, and quite a neat solution.
+ if (!pmu->name)
goto err;
+ ret = perf_pmu_register(>base, pmu->name, -1);
+ if (ret)
+ goto err_name;
+
ret = i915_pmu_register_cpuhp_state(pmu);
if (ret)
goto err_unreg;
@@ -1095,6 +1113,9 @@ void i915_pmu_register(struct drm_i915_private *i915)
err_unreg:
perf_pmu_unregister(>base);
+err_name:
+ if (!is_igp(i915->drm.pdev))
+ kfree(pmu->name);
kfree_const(pmu->name);
err:
pmu->base.event_init = NULL;
free_event_attributes(pmu);
@@ -1116,5 +1137,7 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
perf_pmu_unregister(>base);
pmu->base.event_init = NULL;
+ if (!is_igp(i915->drm.pdev))
+ kfree(pmu->name);
kfree_const(pmu->name);
Works for me, I wonder what PeterZ will say...
In what sense?
Reviewed-by: Chris Wilson
Thanks,
Tvrtko
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ehl: Don't forget to handle port C's hotplug interrupts (rev2)
Pushed to dinq. Thanks Jose for the review. Matt On Thu, Aug 01, 2019 at 01:19:04PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/ehl: Don't forget to handle port C's hotplug interrupts > (rev2) > URL : https://patchwork.freedesktop.org/series/64452/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13812_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_13812_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_balancer@smoke: > - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_exec_balan...@smoke.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb3/igt@gem_exec_balan...@smoke.html > > * igt@gem_exec_suspend@basic-s3: > - shard-kbl: [PASS][3] -> ([PASS][4], [DMESG-WARN][5]) > ([fdo#108566]) +10 similar issues >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl1/igt@gem_exec_susp...@basic-s3.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-kbl7/igt@gem_exec_susp...@basic-s3.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-kbl4/igt@gem_exec_susp...@basic-s3.html > > * igt@gem_fence_thrash@bo-write-verify-threaded-y: > - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([fdo#107713] / > [fdo#109100]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb3/igt@gem_fence_thr...@bo-write-verify-threaded-y.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb1/igt@gem_fence_thr...@bo-write-verify-threaded-y.html > > * igt@gem_partial_pwrite_pread@write-uncached: > - shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([fdo#107713]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb7/igt@gem_partial_pwrite_pr...@write-uncached.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb7/igt@gem_partial_pwrite_pr...@write-uncached.html > > * igt@kms_cursor_crc@pipe-a-cursor-suspend: > - shard-skl: [PASS][10] -> ([INCOMPLETE][11], [PASS][12]) > ([fdo#110741]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-suspend.html > > * igt@kms_cursor_legacy@cursor-vs-flip-legacy: > - shard-snb: [PASS][13] -> ([PASS][14], [SKIP][15]) > ([fdo#109271]) +1 similar issue >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-snb2/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-snb5/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-snb4/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html > > * igt@kms_flip@flip-vs-expired-vblank: > - shard-skl: [PASS][16] -> ([PASS][17], [FAIL][18]) > ([fdo#105363]) >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html > > * igt@kms_flip_tiling@flip-changes-tiling-yf: > - shard-skl: [PASS][19] -> ([PASS][20], [FAIL][21]) > ([fdo#108228] / [fdo#108303]) >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl7/igt@kms_flip_til...@flip-changes-tiling-yf.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl1/igt@kms_flip_til...@flip-changes-tiling-yf.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl3/igt@kms_flip_til...@flip-changes-tiling-yf.html > > * igt@kms_frontbuffer_tracking@basic: > - shard-iclb: [PASS][22] -> [FAIL][23] ([fdo#103167]) +3 similar > issues >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@kms_frontbuffer_track...@basic.html >[23]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb1/igt@kms_frontbuffer_track...@basic.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt: > - shard-snb: [PASS][24] -> [SKIP][25] ([fdo#109271]) +2 similar > issues >[24]: >
[Intel-gfx] [PATCH v3 5/5] drm/i915/pmu: Support multiple GPUs
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devices
handled by us. Integrated devices keep the legacy name preserving
backward compatibility.
v2:
* Detect IGP and keep legacy name. (Michal)
* Use PCI device name as suffix. (Michal, Chris)
v3:
* Constify the name. (Chris)
* Use pci_domain_nr. (Chris)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Michal Wajdeczko
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 27 +--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e0e0180bca7c..c732adac3136 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1053,6 +1053,15 @@ static void i915_pmu_unregister_cpuhp_state(struct
i915_pmu *pmu)
cpuhp_remove_multi_state(cpuhp_slot);
}
+static bool is_igp(struct pci_dev *pdev)
+{
+ /* IGP is :00:02.0 */
+ return pci_domain_nr(pdev->bus) == 0 &&
+ pdev->bus->number == 0 &&
+ PCI_SLOT(pdev->devfn) == 2 &&
+ PCI_FUNC(pdev->devfn) == 0;
+}
+
void i915_pmu_register(struct drm_i915_private *i915)
{
struct i915_pmu *pmu = >pmu;
@@ -1083,10 +1092,19 @@ void i915_pmu_register(struct drm_i915_private *i915)
hrtimer_init(>timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
pmu->timer.function = i915_sample;
- ret = perf_pmu_register(>base, "i915", -1);
- if (ret)
+ if (!is_igp(i915->drm.pdev))
+ pmu->name = kasprintf(GFP_KERNEL,
+ "i915-%s",
+ dev_name(i915->drm.dev));
+ else
+ pmu->name = "i915";
+ if (!pmu->name)
goto err;
+ ret = perf_pmu_register(>base, pmu->name, -1);
+ if (ret)
+ goto err_name;
+
ret = i915_pmu_register_cpuhp_state(pmu);
if (ret)
goto err_unreg;
@@ -1095,6 +1113,9 @@ void i915_pmu_register(struct drm_i915_private *i915)
err_unreg:
perf_pmu_unregister(>base);
+err_name:
+ if (!is_igp(i915->drm.pdev))
+ kfree_const(pmu->name);
err:
pmu->base.event_init = NULL;
free_event_attributes(pmu);
@@ -1116,5 +1137,7 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
perf_pmu_unregister(>base);
pmu->base.event_init = NULL;
+ if (!is_igp(i915->drm.pdev))
+ kfree_const(pmu->name);
free_event_attributes(pmu);
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 4fc4f2478301..ff24f3bb0102 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -46,6 +46,10 @@ struct i915_pmu {
* @base: PMU base.
*/
struct pmu base;
+ /**
+* @name: Name as registered with perf core.
+*/
+ const char *name;
/**
* @lock: Lock protecting enable mask and ref count handling.
*/
--
2.20.1
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Re: [Intel-gfx] [PATCH v3 6/8] drm/i915/display/icl: Enable master-slaves in trans port sync mode in correct order
Op 01-08-2019 om 01:24 schreef Manasi Navare:
> Thanks Maarten for your review comments, please see my responses/questions
> below:
>
> On Tue, Jul 30, 2019 at 12:53:30PM +0200, Maarten Lankhorst wrote:
>> Op 24-06-2019 om 23:08 schreef Manasi Navare:
>>> As per the display enable sequence, we need to follow the enable sequence
>>> for slaves first with DP_TP_CTL set to Idle and configure the transcoder
>>> port sync register to select the corersponding master, then follow the
>>> enable sequence for master leaving DP_TP_CTL to idle.
>>> At this point the transcoder port sync mode is configured and enabled
>>> and the Vblanks of both ports are synchronized so then set DP_TP_CTL
>>> for the slave and master to Normal and do post crtc enable updates.
>>>
>>> v2:
>>> * Create a icl_update_crtcs hook (Maarten, Danvet)
>>> * This sequence only for CRTCs in trans port sync mode (Maarten)
>>>
>>> Cc: Daniel Vetter
>>> Cc: Ville Syrjälä
>>> Cc: Maarten Lankhorst
>>> Cc: Matt Roper
>>> Signed-off-by: Manasi Navare
>>> ---
>>> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
>>> drivers/gpu/drm/i915/display/intel_display.c | 217 ++-
>>> drivers/gpu/drm/i915/display/intel_display.h | 4 +
>>> 3 files changed, 221 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>>> index 7925a176f900..bceb7e4b1877 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>>> @@ -3154,7 +3154,8 @@ static void intel_ddi_pre_enable_dp(struct
>>> intel_encoder *encoder,
>>> true);
>>> intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
>>> intel_dp_start_link_train(intel_dp);
>>> - if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>>> + if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
>>> + !is_trans_port_sync_mode(crtc_state))
>>> intel_dp_stop_link_train(intel_dp);
>>>
>>> intel_ddi_enable_fec(encoder, crtc_state);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>> index 7156b1b4c6c5..f88d3a929e36 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -520,6 +520,26 @@ needs_modeset(const struct drm_crtc_state *state)
>>> return drm_atomic_crtc_needs_modeset(state);
>>> }
>>>
>>> +bool
>>> +is_trans_port_sync_mode(const struct intel_crtc_state *state)
>>> +{
>>> + return (state->master_transcoder != INVALID_TRANSCODER ||
>>> + state->sync_mode_slaves_mask);
>>> +}
>>> +
>>> +static bool
>>> +is_trans_port_sync_slave(const struct intel_crtc_state *state)
>>> +{
>>> + return state->master_transcoder != INVALID_TRANSCODER;
>>> +}
>>> +
>>> +static bool
>>> +is_trans_port_sync_master(const struct intel_crtc_state *state)
>>> +{
>>> + return (state->master_transcoder == INVALID_TRANSCODER &&
>>> + state->sync_mode_slaves_mask);
>>> +}
>>> +
>>> /*
>>> * Platform specific helpers to calculate the port PLL loopback- (clock.m),
>>> * and post-divider (clock.p) values, pre- (clock.vco) and post-divided
>>> fast
>>> @@ -13944,9 +13964,200 @@ static void skl_commit_modeset_enables(struct
>>> drm_atomic_state *state)
>>> progress = true;
>>> }
>>> } while (progress);
>>> +}
>>>
>>> +static void icl_commit_modeset_enables(struct drm_atomic_state *state)
>>> +{
>>> + struct drm_i915_private *dev_priv = to_i915(state->dev);
>>> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>>> + struct drm_crtc *crtc;
>>> + struct intel_crtc *intel_crtc;
>>> + struct drm_crtc_state *old_crtc_state, *new_crtc_state;
>>> + struct intel_crtc_state *cstate;
>>> + unsigned int updated = 0;
>>> + bool progress;
>>> + enum pipe pipe;
>>> + int i;
>>> + u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
>>> + u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
>>> + struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
>> Add old_entries as well, merge master + slave
> I didnt understand what you meant by merge master+slaves? You mean add also
> the
> master and slave that are already enabled?
Instead of 2 separate allocations, only have a single allocation that contains
the slave and master
ddb during modeset/fastset.
This will allow it to be updated as a single crtc. This is useful for modeset
enable/disable as a single sequence, and could
potentiallybe useful for normal page flips as well to reduce tearing.
>>> +
>>> + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
>>> new_crtc_state, i)
>>> + /* ignore allocations for crtc's that have been turned off. */
>>> + if (new_crtc_state->active)
>>> + entries[i] =
>>> to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
>> Can be changed
[Intel-gfx] ✓ Fi.CI.BAT: success for mm/i915: i915_gemfs_init() NULL dereference (rev2)
== Series Details ==
Series: mm/i915: i915_gemfs_init() NULL dereference (rev2)
URL : https://patchwork.freedesktop.org/series/63977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13828
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/
Known issues
Here are the changes found in Patchwork_13828 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload-no-display:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [PASS][3] -> [WARN][4] ([fdo#109380])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@prime_vgem@basic-fence-mmap:
- fi-pnv-d510:[PASS][9] -> [INCOMPLETE][10] ([fdo#110740] /
[fdo#111276])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-wait-default:
- fi-bxt-j4205: [PASS][11] -> [FAIL][12] ([fdo#111277]) +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html
- fi-bxt-dsi: [PASS][13] -> [FAIL][14] ([fdo#111277]) +1 similar
issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-bxt-dsi/igt@prime_v...@basic-wait-default.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-bxt-dsi/igt@prime_v...@basic-wait-default.html
Possible fixes
* igt@gem_mmap@basic:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-u3/igt@gem_m...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-icl-u3/igt@gem_m...@basic.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][17] ([fdo#08]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}:[INCOMPLETE][19] ([fdo#107713] / [fdo#108569]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [FAIL][21] ([fdo#109483] / [fdo#109635 ]) ->
[PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][23] ([fdo#109485]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13828/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [SKIP][25] ([fdo#109271]) -> [PASS][26] +23 similar
issues
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[26]:
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Atomically acquire the gt_pm wakeref
On 01/08/2019 15:39, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-08-01 15:21:17)
On 01/08/2019 13:20, Chris Wilson wrote:
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
No automagic drop!
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 8 +++-
drivers/gpu/drm/i915/i915_pmu.c | 23 ---
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index ba960e1fc209..016298483de7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -9,7 +9,8 @@
#include
-struct intel_gt;
+#include "intel_gt_types.h"
+#include "intel_wakeref.h"
enum {
INTEL_GT_UNPARK,
@@ -19,6 +20,11 @@ enum {
void intel_gt_pm_get(struct intel_gt *gt);
void intel_gt_pm_put(struct intel_gt *gt);
+static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
+{
+ return intel_wakeref_get_if_active(>wakeref);
+}
+
void intel_gt_pm_init_early(struct intel_gt *gt);
void intel_gt_sanitize(struct intel_gt *gt, bool force);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..e71192804996 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,7 @@
#include
#include "gt/intel_engine.h"
+#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
#include "i915_pmu.h"
@@ -161,16 +162,12 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
- intel_wakeref_t wakeref;
unsigned long flags;
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
- wakeref = 0;
- if (READ_ONCE(dev_priv->gt.awake))
- wakeref = intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
- if (!wakeref)
+ if (!intel_gt_pm_get_if_awake(_priv->gt))
return;
spin_lock_irqsave(_priv->uncore.lock, flags);
@@ -205,7 +202,7 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned
int period_ns)
}
spin_unlock_irqrestore(_priv->uncore.lock, flags);
- intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+ intel_gt_pm_put(_priv->gt);
}
static void
@@ -222,15 +219,11 @@ frequency_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
u32 val;
val = dev_priv->gt_pm.rps.cur_freq;
- if (dev_priv->gt.awake) {
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
- wakeref) {
- val = intel_uncore_read_notrace(_priv->uncore,
- GEN6_RPSTAT1);
- val = intel_get_cagf(dev_priv, val);
- }
+ if (intel_gt_pm_get_if_awake(_priv->gt)) {
+ val = intel_uncore_read_notrace(_priv->uncore,
+ GEN6_RPSTAT1);
+ val = intel_get_cagf(dev_priv, val);
+ intel_gt_pm_put(_priv->gt);
}
add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
I guess I'll be rebasing mine, at some point. :)
I anticipated you merging it at some point.
This patch to my series or what?
Had a thought, and we don't need gt_pm for the engine sampling, but
rather intel_engine_pm_get_if_awake.
I thought about it, but since we iterate all engines did not see a real
benefit. Wouldn't harm either, only some more CPU cycles in the loop, so
up to you.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/pmu: Support multiple GPUs
Quoting Tvrtko Ursulin (2019-08-01 15:17:32)
> From: Tvrtko Ursulin
>
> With discrete graphics system can have both integrated and discrete GPU
> handled by i915.
>
> Currently we use a fixed name ("i915") when registering as the uncore PMU
> provider which stops working in this case.
>
> To fix this we add the PCI device name string to non-integrated devices
> handled by us. Integrated devices keep the legacy name preserving
> backward compatibility.
>
> v2:
> * Detect IGP and keep legacy name. (Michal)
> * Use PCI device name as suffix. (Michal, Chris)
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> Cc: Michal Wajdeczko
> ---
> Is our GPU always ":00:02.0"? CI will tell me.
It always has been. (With a few additional 2.1 for Windows95 multihead
where each head had to be a unique device!)
One hopes that by now it is firmly ingrained that it will always be
kept to 00:02.0.
> ---
> drivers/gpu/drm/i915/i915_pmu.c | 27 +--
> drivers/gpu/drm/i915/i915_pmu.h | 4
> 2 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index e0e0180bca7c..9a404d85c4e9 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -1053,6 +1053,15 @@ static void i915_pmu_unregister_cpuhp_state(struct
> i915_pmu *pmu)
> cpuhp_remove_multi_state(cpuhp_slot);
> }
>
> +static bool is_igp(struct pci_dev *pdev)
> +{
> + /* IGP is :00:02.0 */
> + return pdev->bus->parent == NULL &&
pci_domain_nr(pdev->bus) == 0 ?
> + pdev->bus->number == 0 &&
> + PCI_SLOT(pdev->devfn) == 2 &&
> + PCI_FUNC(pdev->devfn) == 0;
I am surprised there isn't already a convenience function. None that I
could find.
> +}
> +
> void i915_pmu_register(struct drm_i915_private *i915)
> {
> struct i915_pmu *pmu = >pmu;
> @@ -1083,10 +1092,19 @@ void i915_pmu_register(struct drm_i915_private *i915)
> hrtimer_init(>timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> pmu->timer.function = i915_sample;
>
> - ret = perf_pmu_register(>base, "i915", -1);
> - if (ret)
> + if (!is_igp(i915->drm.pdev))
> + pmu->name = kasprintf(GFP_KERNEL,
> + "i915-%s",
> + dev_name(i915->drm.dev));
> + else
> + pmu->name = "i915";
Makes sense, and quite a neat solution.
> + if (!pmu->name)
> goto err;
>
> + ret = perf_pmu_register(>base, pmu->name, -1);
> + if (ret)
> + goto err_name;
> +
> ret = i915_pmu_register_cpuhp_state(pmu);
> if (ret)
> goto err_unreg;
> @@ -1095,6 +1113,9 @@ void i915_pmu_register(struct drm_i915_private *i915)
>
> err_unreg:
> perf_pmu_unregister(>base);
> +err_name:
> + if (!is_igp(i915->drm.pdev))
> + kfree(pmu->name);
kfree_const(pmu->name);
> err:
> pmu->base.event_init = NULL;
> free_event_attributes(pmu);
> @@ -1116,5 +1137,7 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
>
> perf_pmu_unregister(>base);
> pmu->base.event_init = NULL;
> + if (!is_igp(i915->drm.pdev))
> + kfree(pmu->name);
kfree_const(pmu->name);
Works for me, I wonder what PeterZ will say...
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/13] drm/amdgpu: Provide ddc symlink in dm connector's sysfs directory
== Series Details == Series: series starting with [01/13] drm/amdgpu: Provide ddc symlink in dm connector's sysfs directory URL : https://patchwork.freedesktop.org/series/64510/ State : failure == Summary == Applying: drm/amdgpu: Provide ddc symlink in dm connector's sysfs directory Applying: drm/radeon: Eliminate possible use of an uninitialized variable Using index info to reconstruct a base tree... M drivers/gpu/drm/radeon/radeon_connectors.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/radeon/radeon_connectors.c CONFLICT (content): Merge conflict in drivers/gpu/drm/radeon/radeon_connectors.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/radeon: Eliminate possible use of an uninitialized variable When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/pmu: Make get_rc6 take intel_gt
Quoting Tvrtko Ursulin (2019-08-01 15:17:31)
> From: Tvrtko Ursulin
>
> RC6 is a GT state so make the function parameter reflect that.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_pmu.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 5cf9a47a0c43..e0e0180bca7c 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -431,8 +431,9 @@ static int i915_pmu_event_init(struct perf_event *event)
> return 0;
> }
>
> -static u64 __get_rc6(struct drm_i915_private *i915)
> +static u64 __get_rc6(struct intel_gt *gt)
> {
> + struct drm_i915_private *i915 = gt->i915;
This ties nicely into a patch that moved the rc6 state beneath
intel_gt...
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH v2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
v2: Take engine->wakeref for engine sampling
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin #v1
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 8 +-
drivers/gpu/drm/i915/i915_pmu.c | 40 ---
2 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index ba960e1fc209..016298483de7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -9,7 +9,8 @@
#include
-struct intel_gt;
+#include "intel_gt_types.h"
+#include "intel_wakeref.h"
enum {
INTEL_GT_UNPARK,
@@ -19,6 +20,11 @@ enum {
void intel_gt_pm_get(struct intel_gt *gt);
void intel_gt_pm_put(struct intel_gt *gt);
+static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
+{
+ return intel_wakeref_get_if_active(>wakeref);
+}
+
void intel_gt_pm_init_early(struct intel_gt *gt);
void intel_gt_sanitize(struct intel_gt *gt, bool force);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..4d7cabeea687 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,8 @@
#include
#include "gt/intel_engine.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
#include "i915_pmu.h"
@@ -161,27 +163,24 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
- intel_wakeref_t wakeref;
- unsigned long flags;
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
- wakeref = 0;
- if (READ_ONCE(dev_priv->gt.awake))
- wakeref = intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
- if (!wakeref)
- return;
-
- spin_lock_irqsave(_priv->uncore.lock, flags);
for_each_engine(engine, dev_priv, id) {
struct intel_engine_pmu *pmu = >pmu;
+ unsigned long flags;
bool busy;
u32 val;
+ if (!intel_engine_pm_get_if_awake(engine))
+ continue;
+
+ spin_lock_irqsave(_priv->uncore.lock, flags);
+
val = I915_READ_FW(RING_CTL(engine->mmio_base));
if (val == 0) /* powerwell off => engine idle */
- continue;
+ goto skip;
if (val & RING_WAIT)
add_sample(>sample[I915_SAMPLE_WAIT], period_ns);
@@ -202,10 +201,11 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
}
if (busy)
add_sample(>sample[I915_SAMPLE_BUSY], period_ns);
- }
- spin_unlock_irqrestore(_priv->uncore.lock, flags);
- intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+skip:
+ spin_unlock_irqrestore(_priv->uncore.lock, flags);
+ intel_engine_pm_put(engine);
+ }
}
static void
@@ -222,15 +222,11 @@ frequency_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
u32 val;
val = dev_priv->gt_pm.rps.cur_freq;
- if (dev_priv->gt.awake) {
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
- wakeref) {
- val =
intel_uncore_read_notrace(_priv->uncore,
- GEN6_RPSTAT1);
- val = intel_get_cagf(dev_priv, val);
- }
+ if (intel_gt_pm_get_if_awake(_priv->gt)) {
+ val = intel_uncore_read_notrace(_priv->uncore,
+ GEN6_RPSTAT1);
+ val = intel_get_cagf(dev_priv, val);
+ intel_gt_pm_put(_priv->gt);
}
add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
--
2.23.0.rc0
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: Atomically acquire the gt_pm wakeref
Quoting Tvrtko Ursulin (2019-08-01 15:21:17)
>
> On 01/08/2019 13:20, Chris Wilson wrote:
> > Currently, we only sample if the intel_gt is awake, but we acquire our
> > own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
> > own wakeref, we can atomically test and acquire that wakeref instead.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > No automagic drop!
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_pm.h | 8 +++-
> > drivers/gpu/drm/i915/i915_pmu.c | 23 ---
> > 2 files changed, 15 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > index ba960e1fc209..016298483de7 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > @@ -9,7 +9,8 @@
> >
> > #include
> >
> > -struct intel_gt;
> > +#include "intel_gt_types.h"
> > +#include "intel_wakeref.h"
> >
> > enum {
> > INTEL_GT_UNPARK,
> > @@ -19,6 +20,11 @@ enum {
> > void intel_gt_pm_get(struct intel_gt *gt);
> > void intel_gt_pm_put(struct intel_gt *gt);
> >
> > +static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
> > +{
> > + return intel_wakeref_get_if_active(>wakeref);
> > +}
> > +
> > void intel_gt_pm_init_early(struct intel_gt *gt);
> >
> > void intel_gt_sanitize(struct intel_gt *gt, bool force);
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.c
> > b/drivers/gpu/drm/i915/i915_pmu.c
> > index eff86483bec0..e71192804996 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.c
> > +++ b/drivers/gpu/drm/i915/i915_pmu.c
> > @@ -8,6 +8,7 @@
> > #include
> >
> > #include "gt/intel_engine.h"
> > +#include "gt/intel_gt_pm.h"
> >
> > #include "i915_drv.h"
> > #include "i915_pmu.h"
> > @@ -161,16 +162,12 @@ engines_sample(struct drm_i915_private *dev_priv,
> > unsigned int period_ns)
> > {
> > struct intel_engine_cs *engine;
> > enum intel_engine_id id;
> > - intel_wakeref_t wakeref;
> > unsigned long flags;
> >
> > if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
> > return;
> >
> > - wakeref = 0;
> > - if (READ_ONCE(dev_priv->gt.awake))
> > - wakeref =
> > intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
> > - if (!wakeref)
> > + if (!intel_gt_pm_get_if_awake(_priv->gt))
> > return;
> >
> > spin_lock_irqsave(_priv->uncore.lock, flags);
> > @@ -205,7 +202,7 @@ engines_sample(struct drm_i915_private *dev_priv,
> > unsigned int period_ns)
> > }
> > spin_unlock_irqrestore(_priv->uncore.lock, flags);
> >
> > - intel_runtime_pm_put(_priv->runtime_pm, wakeref);
> > + intel_gt_pm_put(_priv->gt);
> > }
> >
> > static void
> > @@ -222,15 +219,11 @@ frequency_sample(struct drm_i915_private *dev_priv,
> > unsigned int period_ns)
> > u32 val;
> >
> > val = dev_priv->gt_pm.rps.cur_freq;
> > - if (dev_priv->gt.awake) {
> > - intel_wakeref_t wakeref;
> > -
> > - with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
> > - wakeref) {
> > - val =
> > intel_uncore_read_notrace(_priv->uncore,
> > - GEN6_RPSTAT1);
> > - val = intel_get_cagf(dev_priv, val);
> > - }
> > + if (intel_gt_pm_get_if_awake(_priv->gt)) {
> > + val = intel_uncore_read_notrace(_priv->uncore,
> > + GEN6_RPSTAT1);
> > + val = intel_get_cagf(dev_priv, val);
> > + intel_gt_pm_put(_priv->gt);
> > }
> >
> > add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
> >
>
> I guess I'll be rebasing mine, at some point. :)
I anticipated you merging it at some point.
Had a thought, and we don't need gt_pm for the engine sampling, but
rather intel_engine_pm_get_if_awake.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: timeline semaphore support (rev3)
== Series Details == Series: drm/i915: timeline semaphore support (rev3) URL : https://patchwork.freedesktop.org/series/61032/ State : success == Summary == CI Bug Log - changes from CI_DRM_6602 -> Patchwork_13827 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/ Known issues Here are the changes found in Patchwork_13827 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@gem_workarounds@basic-read: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-u3/igt@gem_workarou...@basic-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-icl-u3/igt@gem_workarou...@basic-read.html * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [PASS][5] -> [FAIL][6] ([fdo#108511]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [PASS][7] -> [WARN][8] ([fdo#109380]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-dsi: [PASS][9] -> [FAIL][10] ([fdo#103167]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [PASS][11] -> [SKIP][12] ([fdo#109271]) +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html * igt@prime_vgem@basic-fence-mmap: - fi-byt-n2820: [PASS][13] -> [INCOMPLETE][14] ([fdo#102657] / [fdo#111276]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-byt-n2820/igt@prime_v...@basic-fence-mmap.html - fi-pnv-d510:[PASS][15] -> [INCOMPLETE][16] ([fdo#110740] / [fdo#111276]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-pnv-d510/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - fi-gdg-551: [PASS][17] -> [INCOMPLETE][18] ([fdo#108316]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-gdg-551/igt@prime_v...@basic-fence-read.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-gdg-551/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-wait-default: - fi-bxt-j4205: [PASS][19] -> [FAIL][20] ([fdo#111277]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-bxt-j4205/igt@prime_v...@basic-wait-default.html - fi-bxt-dsi: [PASS][21] -> [FAIL][22] ([fdo#111277]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-bxt-dsi/igt@prime_v...@basic-wait-default.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-bxt-dsi/igt@prime_v...@basic-wait-default.html Possible fixes * igt@gem_mmap@basic: - fi-icl-u3: [DMESG-WARN][23] ([fdo#107724]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-icl-u3/igt@gem_m...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-icl-u3/igt@gem_m...@basic.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][25] ([fdo#08]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6602/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13827/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: add syncobj timeline support
On 31/07/2019 23:03, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-31 15:07:33)
-static struct drm_syncobj **
-get_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_file *file)
+static struct i915_eb_fences *
+get_timeline_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
+{
+ struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences =
+ >extensions.timeline_fences;
+ struct drm_i915_gem_exec_fence __user *user_fences;
+ struct i915_eb_fences *fences;
+ u64 __user *user_values;
+ u64 num_fences, num_user_fences = timeline_fences->fence_count;
+ unsigned long n;
+ int err;
+
+ /* Check multiplication overflow for access_ok() and kvmalloc_array() */
+ BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
+ if (num_user_fences > min_t(unsigned long,
+ ULONG_MAX / sizeof(*user_fences),
+ SIZE_MAX / sizeof(*fences)))
+ return ERR_PTR(-EINVAL);
+
+ user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
+ if (!access_ok(user_fences, num_user_fences * sizeof(*user_fences)))
+ return ERR_PTR(-EFAULT);
+
+ user_values = u64_to_user_ptr(timeline_fences->values_ptr);
+ if (!access_ok(user_values, num_user_fences * sizeof(*user_values)))
+ return ERR_PTR(-EFAULT);
+
+ fences = kvmalloc_array(num_user_fences, sizeof(*fences),
+ __GFP_NOWARN | GFP_KERNEL);
+ if (!fences)
+ return ERR_PTR(-ENOMEM);
+
+ BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
+~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
+
+ for (n = 0, num_fences = 0; n < timeline_fences->fence_count; n++) {
+ struct drm_i915_gem_exec_fence user_fence;
+ struct drm_syncobj *syncobj;
+ struct dma_fence *fence = NULL;
+ u64 point;
+
+ if (__copy_from_user(_fence, user_fences++,
sizeof(user_fence))) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ err = -EINVAL;
+ goto err;
+ }
+
+ if (__get_user(point, user_values++)) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
+ if (!syncobj) {
+ DRM_DEBUG("Invalid syncobj handle provided\n");
+ err = -ENOENT;
+ goto err;
+ }
+
+ if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
+ fence = drm_syncobj_fence_get(syncobj);
+ if (!fence) {
+ DRM_DEBUG("Syncobj handle has no fence\n");
+ drm_syncobj_put(syncobj);
+ err = -EINVAL;
+ goto err;
+ }
+
+ err = dma_fence_chain_find_seqno(, point);
+ if (err) {
+ DRM_DEBUG("Syncobj handle missing requested point
%llu\n", point);
+ drm_syncobj_put(syncobj);
+ goto err;
+ }
+
+ /* A point might have been signaled already and
+* garbage collected from the timeline. In this case
+* just ignore the point and carry on.
+*/
+ if (!fence) {
+ drm_syncobj_put(syncobj);
+ continue;
+ }
+ }
+
+ /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+ if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
if (dma_fence_chain_find_seqno() == 0)
return -EINVAL;
as an early sanity check?
+ fences[num_fences].chain_fence =
+ kmalloc(sizeof(*fences[num_fences].chain_fence),
+ GFP_KERNEL);
+ if (!fences[num_fences].chain_fence) {
+ dma_fence_put(fence);
+ drm_syncobj_put(syncobj);
+ err = -ENOMEM;
+ DRM_DEBUG("Unable to alloc chain_fence\n");
+ goto err;
+ }
+ } else {
+ fences[num_fences].chain_fence = NULL;
+ }
+
+ fences[num_fences].syncobj = ptr_pack_bits(syncobj,
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Atomically acquire the gt_pm wakeref
On 01/08/2019 13:20, Chris Wilson wrote:
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
No automagic drop!
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 8 +++-
drivers/gpu/drm/i915/i915_pmu.c | 23 ---
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index ba960e1fc209..016298483de7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -9,7 +9,8 @@
#include
-struct intel_gt;
+#include "intel_gt_types.h"
+#include "intel_wakeref.h"
enum {
INTEL_GT_UNPARK,
@@ -19,6 +20,11 @@ enum {
void intel_gt_pm_get(struct intel_gt *gt);
void intel_gt_pm_put(struct intel_gt *gt);
+static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
+{
+ return intel_wakeref_get_if_active(>wakeref);
+}
+
void intel_gt_pm_init_early(struct intel_gt *gt);
void intel_gt_sanitize(struct intel_gt *gt, bool force);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..e71192804996 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,7 @@
#include
#include "gt/intel_engine.h"
+#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
#include "i915_pmu.h"
@@ -161,16 +162,12 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
- intel_wakeref_t wakeref;
unsigned long flags;
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
- wakeref = 0;
- if (READ_ONCE(dev_priv->gt.awake))
- wakeref = intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
- if (!wakeref)
+ if (!intel_gt_pm_get_if_awake(_priv->gt))
return;
spin_lock_irqsave(_priv->uncore.lock, flags);
@@ -205,7 +202,7 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned
int period_ns)
}
spin_unlock_irqrestore(_priv->uncore.lock, flags);
- intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+ intel_gt_pm_put(_priv->gt);
}
static void
@@ -222,15 +219,11 @@ frequency_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
u32 val;
val = dev_priv->gt_pm.rps.cur_freq;
- if (dev_priv->gt.awake) {
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
- wakeref) {
- val =
intel_uncore_read_notrace(_priv->uncore,
- GEN6_RPSTAT1);
- val = intel_get_cagf(dev_priv, val);
- }
+ if (intel_gt_pm_get_if_awake(_priv->gt)) {
+ val = intel_uncore_read_notrace(_priv->uncore,
+ GEN6_RPSTAT1);
+ val = intel_get_cagf(dev_priv, val);
+ intel_gt_pm_put(_priv->gt);
}
add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
I guess I'll be rebasing mine, at some point. :)
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] Linux 5.2, usb: typec: Support for Alternate Modes
Hi Matthew, On Thu, Aug 01, 2019 at 01:16:34PM +0100, Matthew Nicholson wrote: > [Resending as plain text email with attachments.] > > Hi, > The kernel version testing I'm testing on is: v5.2.4-arch1 > I have disabled gmd, which seems to struggle with not being able to > configure displays and becomes unresponsive. > I'm running startx and have an xprofile script that is setting the > displays with xrandr. > > *1. dmesg output* > I have attached two copies of dmesg and lsmod ouputs. > Both are for v5.2.4, one set is where ucsi_acpi is blacklisted, > another with no blacklisted modules. > > *2. The exact XPS13 version* > XPS 13 (9370) Developer edition, ships with Ubuntu. > i7-8550U Processor > > *3. BIOS version* > The output from fwupdmgr get-devices is attached. > XPS 13 9370 Thunderbolt Controller: v33.00 > XPS 13 9370 System Firmware: v0.1.10.0 > Synaptics VMM3332 inside Dell WD15/TB16/TB18 wired Dock: v3.10.002 > > At boot the firmware version listed is 1.10.0 > > *Can you unload the UCSI driver to see if it has any effect?* > No changes in being display functionality. I tried to unload and to > blacklist with config file in /etc/modprode.d In that case the problem is not caused by the Type-C drivers. This is more likely a regression in the Thunderbolt drivers, or the graphics drivers. Adding Mika and the graphics guys. Mika is the Thunderbolt maintainer in Linux kernel. He's away now, but he'll be back on Monday. > When ucsi_acpi is not blacked the error message: > > typec_displayport port1-partner.0: failed to enter mode You can ignore that message for now. It is not fatal in this case. It happens because on this platform the embedded controller firmware does not allow the operating system to do anything to the alternate modes besides detecting them, not even enter or exit them (so the firmware handles the alternate modes on its own). The DisplayPort alt mode driver in Linux kernel does not know that, so it tries to enter DisplayPort mode (most likely the firmware has already entered the mode at this point). That attempt fails, and the driver prints the message, but it really is not fatal in any way. I'll see what could be done about that message, but for now you can just ignore it. > is displayed in dmseg and in getty. > > *Are you able to build you own test kernels?* > It is not something that I have done but it is something I should be able to > do. > > A few more details. > The external monitors are detected and listed as available in xrandr. > I can enable one of them at a time, however attempting to enable both > of them will fail. > The returned error message is: > xrandr: Configure crtc 2 failed > > > On Tue, 30 Jul 2019 at 15:27, Heikki Krogerus > wrote: > > > > Hi Matthew, > > > > Copying the respective mailing list. > > > > On Wed, Jul 17, 2019 at 09:22:10AM +0100, Matthew Nicholson wrote: > > > Hi, > > > > > > Thanks for your work on the linux. > > > > > > I am using dell xps13 with a wd15 type-c docking station, on Archlinux. > > > Under kernel version 5.2 (and 5.2.1) I was running into some issue with > > > having the docking station connected to multiple monitors (Only one > > > monitor > > > would work at a time). > > > I tried to get the monitors working under X/xrandr and wayland/gnome. > > > The issue is not present after downgrading back to linux 5.1.7. > > > > > > I am wondering what I should do to report this or help testing. > > > > I'm going to need some details about your platform: > > > > 1. dmesg output > > 2. The exact XPS13 version > > 3. BIOS version > > > > The UCSI driver got support for alternate modes in v5.2, so I'm > > guessing that is causing this problem, but to be sure, can you unload > > the UCSI driver to see if it has any effect? > > > > % modprobe -r ucsi_acpi > > > > Are you able to build you own test kernels? thanks, -- heikki ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915/pmu: Convert engine sampling to uncore mmio
From: Tvrtko Ursulin
Drops one macro using implicit dev_priv.
v2:
* Use ENGINE_READ_FW. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 12008966b00e..09265b6b78b2 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -162,29 +162,30 @@ add_sample(struct i915_pmu_sample *sample, u32 val)
}
static void
-engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
+engines_sample(struct drm_i915_private *i915, unsigned int period_ns)
{
+ struct intel_uncore *uncore = >uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
intel_wakeref_t wakeref;
unsigned long flags;
- if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
+ if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
wakeref = 0;
- if (READ_ONCE(dev_priv->gt.awake))
- wakeref = intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
+ if (READ_ONCE(i915->gt.awake))
+ wakeref = intel_runtime_pm_get_if_in_use(>runtime_pm);
if (!wakeref)
return;
- spin_lock_irqsave(_priv->uncore.lock, flags);
- for_each_engine(engine, dev_priv, id) {
+ spin_lock_irqsave(>lock, flags);
+ for_each_engine(engine, i915, id) {
struct intel_engine_pmu *pmu = >pmu;
bool busy;
u32 val;
- val = I915_READ_FW(RING_CTL(engine->mmio_base));
+ val = ENGINE_READ_FW(engine, RING_CTL);
if (val == 0) /* powerwell off => engine idle */
continue;
@@ -202,15 +203,15 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
*/
busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT);
if (!busy) {
- val = I915_READ_FW(RING_MI_MODE(engine->mmio_base));
+ val = ENGINE_READ_FW(engine, RING_MI_MODE);
busy = !(val & MODE_IDLE);
}
if (busy)
add_sample(>sample[I915_SAMPLE_BUSY], period_ns);
}
- spin_unlock_irqrestore(_priv->uncore.lock, flags);
+ spin_unlock_irqrestore(>lock, flags);
- intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+ intel_runtime_pm_put(>runtime_pm, wakeref);
}
static void
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915/pmu: Make more struct i915_pmu centric
From: Tvrtko Ursulin
Just tidy the code a bit by removing a sea of overly verbose i915->pmu.*.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 194 +---
1 file changed, 104 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..12008966b00e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -74,8 +74,9 @@ static unsigned int event_enabled_bit(struct perf_event
*event)
return config_enabled_bit(event->attr.config);
}
-static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
+static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
{
+ struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
u64 enable;
/*
@@ -83,7 +84,7 @@ static bool pmu_needs_timer(struct drm_i915_private *i915,
bool gpu_active)
*
* We start with a bitmask of all currently enabled events.
*/
- enable = i915->pmu.enable;
+ enable = pmu->enable;
/*
* Mask out all the ones which do not need the timer, or in
@@ -114,24 +115,26 @@ static bool pmu_needs_timer(struct drm_i915_private
*i915, bool gpu_active)
void i915_pmu_gt_parked(struct drm_i915_private *i915)
{
- if (!i915->pmu.base.event_init)
+ struct i915_pmu *pmu = >pmu;
+
+ if (!pmu->base.event_init)
return;
- spin_lock_irq(>pmu.lock);
+ spin_lock_irq(>lock);
/*
* Signal sampling timer to stop if only engine events are enabled and
* GPU went idle.
*/
- i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
- spin_unlock_irq(>pmu.lock);
+ pmu->timer_enabled = pmu_needs_timer(pmu, false);
+ spin_unlock_irq(>lock);
}
-static void __i915_pmu_maybe_start_timer(struct drm_i915_private *i915)
+static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
{
- if (!i915->pmu.timer_enabled && pmu_needs_timer(i915, true)) {
- i915->pmu.timer_enabled = true;
- i915->pmu.timer_last = ktime_get();
- hrtimer_start_range_ns(>pmu.timer,
+ if (!pmu->timer_enabled && pmu_needs_timer(pmu, true)) {
+ pmu->timer_enabled = true;
+ pmu->timer_last = ktime_get();
+ hrtimer_start_range_ns(>timer,
ns_to_ktime(PERIOD), 0,
HRTIMER_MODE_REL_PINNED);
}
@@ -139,15 +142,17 @@ static void __i915_pmu_maybe_start_timer(struct
drm_i915_private *i915)
void i915_pmu_gt_unparked(struct drm_i915_private *i915)
{
- if (!i915->pmu.base.event_init)
+ struct i915_pmu *pmu = >pmu;
+
+ if (!pmu->base.event_init)
return;
- spin_lock_irq(>pmu.lock);
+ spin_lock_irq(>lock);
/*
* Re-enable sampling timer when GPU goes active.
*/
- __i915_pmu_maybe_start_timer(i915);
- spin_unlock_irq(>pmu.lock);
+ __i915_pmu_maybe_start_timer(pmu);
+ spin_unlock_irq(>lock);
}
static void
@@ -251,15 +256,16 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
{
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
+ struct i915_pmu *pmu = >pmu;
unsigned int period_ns;
ktime_t now;
- if (!READ_ONCE(i915->pmu.timer_enabled))
+ if (!READ_ONCE(pmu->timer_enabled))
return HRTIMER_NORESTART;
now = ktime_get();
- period_ns = ktime_to_ns(ktime_sub(now, i915->pmu.timer_last));
- i915->pmu.timer_last = now;
+ period_ns = ktime_to_ns(ktime_sub(now, pmu->timer_last));
+ pmu->timer_last = now;
/*
* Strictly speaking the passed in period may not be 100% accurate for
@@ -443,6 +449,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
{
#if IS_ENABLED(CONFIG_PM)
struct intel_runtime_pm *rpm = >runtime_pm;
+ struct i915_pmu *pmu = >pmu;
intel_wakeref_t wakeref;
unsigned long flags;
u64 val;
@@ -458,16 +465,16 @@ static u64 get_rc6(struct drm_i915_private *i915)
* previously.
*/
- spin_lock_irqsave(>pmu.lock, flags);
+ spin_lock_irqsave(>lock, flags);
- if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
- i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
- i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
+ if (val >= pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
+ pmu->sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
+ pmu->sample[__I915_SAMPLE_RC6].cur = val;
} else {
- val =
[Intel-gfx] [PATCH 4/5] drm/i915/pmu: Make get_rc6 take intel_gt
From: Tvrtko Ursulin
RC6 is a GT state so make the function parameter reflect that.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 5cf9a47a0c43..e0e0180bca7c 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -431,8 +431,9 @@ static int i915_pmu_event_init(struct perf_event *event)
return 0;
}
-static u64 __get_rc6(struct drm_i915_private *i915)
+static u64 __get_rc6(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
u64 val;
val = intel_rc6_residency_ns(i915,
@@ -449,9 +450,10 @@ static u64 __get_rc6(struct drm_i915_private *i915)
return val;
}
-static u64 get_rc6(struct drm_i915_private *i915)
+static u64 get_rc6(struct intel_gt *gt)
{
#if IS_ENABLED(CONFIG_PM)
+ struct drm_i915_private *i915 = gt->i915;
struct intel_runtime_pm *rpm = >runtime_pm;
struct i915_pmu *pmu = >pmu;
intel_wakeref_t wakeref;
@@ -460,7 +462,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
wakeref = intel_runtime_pm_get_if_in_use(rpm);
if (wakeref) {
- val = __get_rc6(i915);
+ val = __get_rc6(gt);
intel_runtime_pm_put(rpm, wakeref);
/*
@@ -523,7 +525,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
return val;
#else
- return __get_rc6(i915);
+ return __get_rc6(gt);
#endif
}
@@ -566,7 +568,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
val = count_interrupts(i915);
break;
case I915_PMU_RC6_RESIDENCY:
- val = get_rc6(i915);
+ val = get_rc6(>gt);
break;
}
}
--
2.20.1
___
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[Intel-gfx] [PATCH 3/5] drm/i915/pmu: Convert sampling to gt
From: Tvrtko Ursulin
Engines and frequencies are a GT thing so adjust sampling routines to
match.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 09265b6b78b2..5cf9a47a0c43 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -162,9 +162,10 @@ add_sample(struct i915_pmu_sample *sample, u32 val)
}
static void
-engines_sample(struct drm_i915_private *i915, unsigned int period_ns)
+engines_sample(struct intel_gt *gt, unsigned int period_ns)
{
- struct intel_uncore *uncore = >uncore;
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
intel_wakeref_t wakeref;
@@ -174,7 +175,7 @@ engines_sample(struct drm_i915_private *i915, unsigned int
period_ns)
return;
wakeref = 0;
- if (READ_ONCE(i915->gt.awake))
+ if (READ_ONCE(gt->awake))
wakeref = intel_runtime_pm_get_if_in_use(>runtime_pm);
if (!wakeref)
return;
@@ -221,34 +222,35 @@ add_sample_mult(struct i915_pmu_sample *sample, u32 val,
u32 mul)
}
static void
-frequency_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
+frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
- if (dev_priv->pmu.enable &
- config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct i915_pmu *pmu = >pmu;
+
+ if (pmu->enable & config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
u32 val;
- val = dev_priv->gt_pm.rps.cur_freq;
- if (dev_priv->gt.awake) {
+ val = i915->gt_pm.rps.cur_freq;
+ if (gt->awake) {
intel_wakeref_t wakeref;
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
+ with_intel_runtime_pm_if_in_use(>runtime_pm,
wakeref) {
- val =
intel_uncore_read_notrace(_priv->uncore,
+ val = intel_uncore_read_notrace(uncore,
GEN6_RPSTAT1);
- val = intel_get_cagf(dev_priv, val);
+ val = intel_get_cagf(i915, val);
}
}
- add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
- intel_gpu_freq(dev_priv, val),
+ add_sample_mult(>sample[__I915_SAMPLE_FREQ_ACT],
+ intel_gpu_freq(i915, val),
period_ns / 1000);
}
- if (dev_priv->pmu.enable &
- config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
- add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_REQ],
- intel_gpu_freq(dev_priv,
- dev_priv->gt_pm.rps.cur_freq),
+ if (pmu->enable & config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
+ add_sample_mult(>sample[__I915_SAMPLE_FREQ_REQ],
+ intel_gpu_freq(i915, i915->gt_pm.rps.cur_freq),
period_ns / 1000);
}
}
@@ -258,6 +260,7 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
struct i915_pmu *pmu = >pmu;
+ struct intel_gt *gt = >gt;
unsigned int period_ns;
ktime_t now;
@@ -274,8 +277,8 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
* grabbing the forcewake. However the potential error from timer call-
* back delay greatly dominates this so we keep it simple.
*/
- engines_sample(i915, period_ns);
- frequency_sample(i915, period_ns);
+ engines_sample(gt, period_ns);
+ frequency_sample(gt, period_ns);
hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
--
2.20.1
___
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[Intel-gfx] [PATCH 5/5] drm/i915/pmu: Support multiple GPUs
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devices
handled by us. Integrated devices keep the legacy name preserving
backward compatibility.
v2:
* Detect IGP and keep legacy name. (Michal)
* Use PCI device name as suffix. (Michal, Chris)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Michal Wajdeczko
---
Is our GPU always ":00:02.0"? CI will tell me.
---
drivers/gpu/drm/i915/i915_pmu.c | 27 +--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e0e0180bca7c..9a404d85c4e9 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1053,6 +1053,15 @@ static void i915_pmu_unregister_cpuhp_state(struct
i915_pmu *pmu)
cpuhp_remove_multi_state(cpuhp_slot);
}
+static bool is_igp(struct pci_dev *pdev)
+{
+ /* IGP is :00:02.0 */
+ return pdev->bus->parent == NULL &&
+ pdev->bus->number == 0 &&
+ PCI_SLOT(pdev->devfn) == 2 &&
+ PCI_FUNC(pdev->devfn) == 0;
+}
+
void i915_pmu_register(struct drm_i915_private *i915)
{
struct i915_pmu *pmu = >pmu;
@@ -1083,10 +1092,19 @@ void i915_pmu_register(struct drm_i915_private *i915)
hrtimer_init(>timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
pmu->timer.function = i915_sample;
- ret = perf_pmu_register(>base, "i915", -1);
- if (ret)
+ if (!is_igp(i915->drm.pdev))
+ pmu->name = kasprintf(GFP_KERNEL,
+ "i915-%s",
+ dev_name(i915->drm.dev));
+ else
+ pmu->name = "i915";
+ if (!pmu->name)
goto err;
+ ret = perf_pmu_register(>base, pmu->name, -1);
+ if (ret)
+ goto err_name;
+
ret = i915_pmu_register_cpuhp_state(pmu);
if (ret)
goto err_unreg;
@@ -1095,6 +1113,9 @@ void i915_pmu_register(struct drm_i915_private *i915)
err_unreg:
perf_pmu_unregister(>base);
+err_name:
+ if (!is_igp(i915->drm.pdev))
+ kfree(pmu->name);
err:
pmu->base.event_init = NULL;
free_event_attributes(pmu);
@@ -1116,5 +1137,7 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
perf_pmu_unregister(>base);
pmu->base.event_init = NULL;
+ if (!is_igp(i915->drm.pdev))
+ kfree(pmu->name);
free_event_attributes(pmu);
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 4fc4f2478301..8d7a388dcdc7 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -46,6 +46,10 @@ struct i915_pmu {
* @base: PMU base.
*/
struct pmu base;
+ /**
+* @name: Name as registered with perf core.
+*/
+ char *name;
/**
* @lock: Lock protecting enable mask and ref count handling.
*/
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v7,1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function
== Series Details == Series: series starting with [v7,1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function URL : https://patchwork.freedesktop.org/series/64457/ State : success == Summary == CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13813_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13813_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][3] -> ([PASS][4], [DMESG-WARN][5]) ([fdo#108686]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl1/igt@gem_tiled_swapp...@non-threaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-apl6/igt@gem_tiled_swapp...@non-threaded.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-apl5/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][6] -> ([DMESG-WARN][7], [DMESG-WARN][8]) ([fdo#108566]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][9] -> ([PASS][10], [FAIL][11]) ([fdo#103232]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-size-change.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-skl2/igt@kms_cursor_...@pipe-c-cursor-size-change.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-size-change.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][12] -> ([DMESG-WARN][13], [PASS][14]) ([fdo#108566]) +9 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-kbl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-kbl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-hsw: [PASS][15] -> ([INCOMPLETE][16], [PASS][17]) ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-hsw7/igt@kms_f...@2x-flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend-interruptible.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-hsw6/igt@kms_f...@2x-flip-vs-suspend-interruptible.html * igt@kms_flip@2x-plain-flip-ts-check-interruptible: - shard-glk: [PASS][18] -> ([PASS][19], [FAIL][20]) ([fdo#100368]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-glk1/igt@kms_f...@2x-plain-flip-ts-check-interruptible.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-glk8/igt@kms_f...@2x-plain-flip-ts-check-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-glk3/igt@kms_f...@2x-plain-flip-ts-check-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][21] -> ([PASS][22], [INCOMPLETE][23]) ([fdo#109507]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl6/igt@kms_f...@flip-vs-suspend-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-skl2/igt@kms_f...@flip-vs-suspend-interruptible.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-skl5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip_tiling@flip-x-tiled: - shard-skl: [PASS][24] -> [FAIL][25] ([fdo#108145] / [fdo#108303]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl9/igt@kms_flip_til...@flip-x-tiled.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13813/shard-skl9/igt@kms_flip_til...@flip-x-tiled.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-iclb: [PASS][26] -> [FAIL][27] ([fdo#103167]) +2 similar issues [26]:
[Intel-gfx] [CI v2 4/4] drm/i915/uc: Stop sanitizing enable_guc modparam
As we already track GuC/HuC uses by other means than modparam
there is no point in sanitizing it. Just scan modparam for
major discrepancies between what was requested vs actual.
v2: rebased, reworded info messages
v3: oops
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 92 ---
1 file changed, 28 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 5d674e418e5e..bdec21f97589 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -55,78 +55,42 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
return ret;
}
-static int __get_platform_enable_guc(struct intel_uc *uc)
+static void __confirm_options(struct intel_uc *uc)
{
- struct intel_uc_fw *guc_fw = >guc.fw;
- struct intel_uc_fw *huc_fw = >huc.fw;
- int enable_guc = 0;
-
- if (!HAS_GT_UC(uc_to_gt(uc)->i915))
- return 0;
-
- /* We don't want to enable GuC/HuC on pre-Gen11 by default */
- if (INTEL_GEN(uc_to_gt(uc)->i915) < 11)
- return 0;
-
- if (intel_uc_fw_supported(guc_fw) && intel_uc_fw_supported(huc_fw))
- enable_guc |= ENABLE_GUC_LOAD_HUC;
-
- return enable_guc;
-}
-
-/**
- * sanitize_options_early - sanitize uC related modparam options
- * @uc: the intel_uc structure
- *
- * In case of "enable_guc" option this function will attempt to modify
- * it only if it was initially set to "auto(-1)". Default value for this
- * modparam varies between platforms and it is hardcoded in driver code.
- * Any other modparam value is only monitored against availability of the
- * related hardware or firmware definitions.
- */
-static void sanitize_options_early(struct intel_uc *uc)
-{
- struct intel_uc_fw *guc_fw = >guc.fw;
- struct intel_uc_fw *huc_fw = >huc.fw;
-
- /* A negative value means "use platform default" */
- if (i915_modparams.enable_guc < 0)
- i915_modparams.enable_guc = __get_platform_enable_guc(uc);
-
- DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
+ DRM_DEBUG_DRIVER("enable_guc=%d (guc:%s submission:%s huc:%s)\n",
i915_modparams.enable_guc,
+yesno(intel_uc_supports_guc(uc)),
yesno(intel_uc_supports_guc_submission(uc)),
yesno(intel_uc_supports_huc(uc)));
- /* Verify GuC firmware availability */
- if (intel_uc_supports_guc(uc) && !intel_uc_fw_supported(guc_fw)) {
- DRM_WARN("Incompatible option detected: enable_guc=%d, "
-"but GuC is not supported!\n",
-i915_modparams.enable_guc);
- DRM_INFO("Disabling GuC/HuC loading!\n");
- i915_modparams.enable_guc = 0;
- }
+ if (i915_modparams.enable_guc == -1)
+ return;
- /* Verify HuC firmware availability */
- if (intel_uc_supports_huc(uc) && !intel_uc_fw_supported(huc_fw)) {
- DRM_WARN("Incompatible option detected: enable_guc=%d, "
-"but HuC is not supported!\n",
-i915_modparams.enable_guc);
- DRM_INFO("Disabling HuC loading!\n");
- i915_modparams.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
+ if (i915_modparams.enable_guc == 0) {
+ GEM_BUG_ON(intel_uc_supports_guc(uc));
+ GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
+ GEM_BUG_ON(intel_uc_supports_huc(uc));
+ return;
}
- /* XXX: GuC submission is unavailable for now */
- if (intel_uc_supports_guc_submission(uc)) {
- DRM_INFO("Incompatible option detected: enable_guc=%d, "
-"but GuC submission is not supported!\n",
-i915_modparams.enable_guc);
- DRM_INFO("Switching to non-GuC submission mode!\n");
- i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
- }
+ if (!intel_uc_supports_guc(uc))
+ DRM_INFO("Incompatible option enable_guc=%d - %s\n",
+i915_modparams.enable_guc, "GuC is not supported!");
+
+ if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC &&
+ !intel_uc_supports_huc(uc))
+ DRM_INFO("Incompatible option enable_guc=%d - %s\n",
+i915_modparams.enable_guc, "HuC is not supported!");
+
+ if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION &&
+ !intel_uc_supports_guc_submission(uc))
+ DRM_INFO("Incompatible option enable_guc=%d - %s\n",
+i915_modparams.enable_guc, "GuC submission is N/A");
- /* Make sure that sanitization was done */
- GEM_BUG_ON(i915_modparams.enable_guc < 0);
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ehl: Don't forget to handle port C's hotplug interrupts (rev2)
== Series Details == Series: drm/i915/ehl: Don't forget to handle port C's hotplug interrupts (rev2) URL : https://patchwork.freedesktop.org/series/64452/ State : success == Summary == CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13812_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13812_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][3] -> ([PASS][4], [DMESG-WARN][5]) ([fdo#108566]) +10 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl1/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-kbl7/igt@gem_exec_susp...@basic-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-kbl4/igt@gem_exec_susp...@basic-s3.html * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb3/igt@gem_fence_thr...@bo-write-verify-threaded-y.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb1/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@gem_partial_pwrite_pread@write-uncached: - shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([fdo#107713]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb7/igt@gem_partial_pwrite_pr...@write-uncached.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb7/igt@gem_partial_pwrite_pr...@write-uncached.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][10] -> ([INCOMPLETE][11], [PASS][12]) ([fdo#110741]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_legacy@cursor-vs-flip-legacy: - shard-snb: [PASS][13] -> ([PASS][14], [SKIP][15]) ([fdo#109271]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-snb2/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-snb5/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-snb4/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][16] -> ([PASS][17], [FAIL][18]) ([fdo#105363]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [PASS][19] -> ([PASS][20], [FAIL][21]) ([fdo#108228] / [fdo#108303]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl7/igt@kms_flip_til...@flip-changes-tiling-yf.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl1/igt@kms_flip_til...@flip-changes-tiling-yf.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-skl3/igt@kms_flip_til...@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@basic: - shard-iclb: [PASS][22] -> [FAIL][23] ([fdo#103167]) +3 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb2/igt@kms_frontbuffer_track...@basic.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-iclb1/igt@kms_frontbuffer_track...@basic.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt: - shard-snb: [PASS][24] -> [SKIP][25] ([fdo#109271]) +2 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-snb5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-plflip-blt.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13812/shard-snb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt: - shard-hsw:
Re: [Intel-gfx] [CI 4/4] drm/i915/uc: Stop sanitizing enable_guc modparam
On Thu, 01 Aug 2019 00:33:21 +0200, Michal Wajdeczko wrote: + if (i915_modparams.enable_guc & ~(ENABLE_GUC_SUBMISSION || + ENABLE_GUC_LOAD_HUC)) oops, again ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Drop the fudge warning on ring restart for ctg/elk
Since we have already stopped the ring, cleared the ring, disabled the
ring (and verifying the ring is clear), a later debug message that the
ring is no longer clear serves no function. It appears it restarts
anyway, and we verify that the ring started correctly afterwards.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 8d24a49e5139..3633ad0e952f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -644,6 +644,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
+ /* WaClearRingBufHeadRegAtInit:ctg,elk */
if (!stop_ring(engine)) {
/* G45 ring initialization often fails to reset head to zero */
DRM_DEBUG_DRIVER("%s head not reset to zero "
@@ -675,19 +676,16 @@ static int xcs_resume(struct intel_engine_cs *engine)
intel_engine_reset_breadcrumbs(engine);
/* Enforce ordering by reading HEAD register back */
- ENGINE_READ(engine, RING_HEAD);
+ ENGINE_POSTING_READ(engine, RING_HEAD);
- /* Initialize the ring. This must happen _after_ we've cleared the ring
+ /*
+* Initialize the ring. This must happen _after_ we've cleared the ring
* registers with the above sequence (the readback of the HEAD registers
* also enforces ordering), otherwise the hw might lose the new ring
-* register values. */
+* register values.
+*/
ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
- /* WaClearRingBufHeadRegAtInit:ctg,elk */
- if (ENGINE_READ(engine, RING_HEAD))
- DRM_DEBUG_DRIVER("%s initialization failed [head=%08x],
fudging\n",
-engine->name, ENGINE_READ(engine, RING_HEAD));
-
/* Check that the ring offsets point within the ring! */
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
--
2.23.0.rc0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Revert "drm/vgem: fix cache synchronization on arm/arm64"
commit 7e9e5ead55be ("drm/vgem: fix cache synchronization on arm/arm64")
broke all of the !llc i915-vgem coherency tests in CI, and left the HW
very, very unhappy (which is even more scary).
Fixes: 7e9e5ead55be ("drm/vgem: fix cache synchronization on arm/arm64")
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Rob Clark
Cc: Sean Paul
---
drivers/gpu/drm/vgem/vgem_drv.c | 130
1 file changed, 47 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index b98689fb0d5d..5bd60ded3d81 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -54,16 +54,10 @@ static struct vgem_device {
struct platform_device *platform;
} *vgem_device;
-static void sync_and_unpin(struct drm_vgem_gem_object *bo);
-static struct page **pin_and_sync(struct drm_vgem_gem_object *bo);
-
static void vgem_gem_free_object(struct drm_gem_object *obj)
{
struct drm_vgem_gem_object *vgem_obj = to_vgem_bo(obj);
- if (!obj->import_attach)
- sync_and_unpin(vgem_obj);
-
kvfree(vgem_obj->pages);
mutex_destroy(_obj->pages_lock);
@@ -91,15 +85,40 @@ static vm_fault_t vgem_gem_fault(struct vm_fault *vmf)
return VM_FAULT_SIGBUS;
mutex_lock(>pages_lock);
- if (!obj->pages)
- pin_and_sync(obj);
if (obj->pages) {
get_page(obj->pages[page_offset]);
vmf->page = obj->pages[page_offset];
ret = 0;
}
mutex_unlock(>pages_lock);
+ if (ret) {
+ struct page *page;
+
+ page = shmem_read_mapping_page(
+ file_inode(obj->base.filp)->i_mapping,
+ page_offset);
+ if (!IS_ERR(page)) {
+ vmf->page = page;
+ ret = 0;
+ } else switch (PTR_ERR(page)) {
+ case -ENOSPC:
+ case -ENOMEM:
+ ret = VM_FAULT_OOM;
+ break;
+ case -EBUSY:
+ ret = VM_FAULT_RETRY;
+ break;
+ case -EFAULT:
+ case -EINVAL:
+ ret = VM_FAULT_SIGBUS;
+ break;
+ default:
+ WARN_ON(PTR_ERR(page));
+ ret = VM_FAULT_SIGBUS;
+ break;
+ }
+ }
return ret;
}
@@ -265,93 +284,32 @@ static const struct file_operations vgem_driver_fops = {
.release= drm_release,
};
-/* Called under pages_lock, except in free path (where it can't race): */
-static void sync_and_unpin(struct drm_vgem_gem_object *bo)
-{
- struct drm_device *dev = bo->base.dev;
-
- if (bo->table) {
- dma_sync_sg_for_cpu(dev->dev, bo->table->sgl,
- bo->table->nents, DMA_BIDIRECTIONAL);
- sg_free_table(bo->table);
- kfree(bo->table);
- bo->table = NULL;
- }
-
- if (bo->pages) {
- drm_gem_put_pages(>base, bo->pages, true, true);
- bo->pages = NULL;
- }
-}
-
-static struct page **pin_and_sync(struct drm_vgem_gem_object *bo)
-{
- struct drm_device *dev = bo->base.dev;
- int npages = bo->base.size >> PAGE_SHIFT;
- struct page **pages;
- struct sg_table *sgt;
-
- WARN_ON(!mutex_is_locked(>pages_lock));
-
- pages = drm_gem_get_pages(>base);
- if (IS_ERR(pages)) {
- bo->pages_pin_count--;
- mutex_unlock(>pages_lock);
- return pages;
- }
-
- sgt = drm_prime_pages_to_sg(pages, npages);
- if (IS_ERR(sgt)) {
- dev_err(dev->dev,
- "failed to allocate sgt: %ld\n",
- PTR_ERR(bo->table));
- drm_gem_put_pages(>base, pages, false, false);
- mutex_unlock(>pages_lock);
- return ERR_CAST(bo->table);
- }
-
- /*
-* Flush the object from the CPU cache so that importers
-* can rely on coherent indirect access via the exported
-* dma-address.
-*/
- dma_sync_sg_for_device(dev->dev, sgt->sgl,
- sgt->nents, DMA_BIDIRECTIONAL);
-
- bo->pages = pages;
- bo->table = sgt;
-
- return pages;
-}
-
static struct page **vgem_pin_pages(struct drm_vgem_gem_object *bo)
{
- struct page **pages;
-
mutex_lock(>pages_lock);
- if (bo->pages_pin_count++ == 0 && !bo->pages) {
- pages = pin_and_sync(bo);
- } else {
- WARN_ON(!bo->pages);
- pages = bo->pages;
+ if
Re: [Intel-gfx] [PATCH 3/3] drm/i915/oa: update the generated files
Quoting Jani Nikula (2019-07-30 12:34:32) > Update the generated files to make the headers self-contained, switch to > the kernel preferred SPDX comment format, and update the copyright > year. Also add the Makefile stanza to run header tests on the files. > > Other changes produced by gputop i915-perf-kernelgen.py were manually > stripped out, and left to the folks who actually know something about > the OA stuff. > > Cc: Chris Wilson > Cc: Lionel Landwerlin > Signed-off-by: Jani Nikula Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: add SPDX headers to subdir Makefiles
Quoting Jani Nikula (2019-07-30 12:34:31) > Add the SPDX headers. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/Makefile | 2 ++ > drivers/gpu/drm/i915/gem/Makefile | 2 ++ > drivers/gpu/drm/i915/gt/Makefile | 2 ++ > drivers/gpu/drm/i915/gt/uc/Makefile | 2 ++ > 4 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/Makefile > b/drivers/gpu/drm/i915/display/Makefile > index 173c305d7866..624b6fba1b9c 100644 > --- a/drivers/gpu/drm/i915/display/Makefile > +++ b/drivers/gpu/drm/i915/display/Makefile > @@ -1,3 +1,5 @@ > +# SPDX-License-Identifier: MIT I thought the build system was GPL -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Report resv_obj allocation failure
== Series Details == Series: drm/i915: Report resv_obj allocation failure URL : https://patchwork.freedesktop.org/series/64450/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6586_full -> Patchwork_13811_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13811_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13811_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13811_full: ### IGT changes ### Possible regressions * igt@i915_hangman@error-state-capture-rcs0: - shard-apl: [PASS][1] -> ([PASS][2], [DMESG-WARN][3]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl6/igt@i915_hang...@error-state-capture-rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-apl8/igt@i915_hang...@error-state-capture-rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-apl4/igt@i915_hang...@error-state-capture-rcs0.html Known issues Here are the changes found in Patchwork_13811_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][4] -> ([PASS][5], [DMESG-WARN][6]) ([fdo#108566]) +5 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-apl8/igt@gem_ctx_isolat...@bcs0-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-apl2/igt@gem_ctx_isolat...@bcs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-apl7/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb1/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][9] -> ([PASS][10], [DMESG-WARN][11]) ([fdo#108566]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-kbl4/igt@gem_soft...@noreloc-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-kbl7/igt@gem_soft...@noreloc-s3.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-kbl4/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][12] -> ([PASS][13], [DMESG-WARN][14]) ([fdo#108686]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-glk3/igt@gem_tiled_swapp...@non-threaded.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-glk9/igt@gem_tiled_swapp...@non-threaded.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] / [fdo#108569]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-iclb6/igt@i915_selftest@live_hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-iclb8/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][17] -> ([INCOMPLETE][18], [PASS][19]) ([fdo#104108]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl1/igt@i915_susp...@forcewake.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-skl6/igt@i915_susp...@forcewake.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-skl1/igt@i915_susp...@forcewake.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][20] -> ([PASS][21], [INCOMPLETE][22]) ([fdo#110741]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][23] -> ([FAIL][24], [PASS][25]) ([fdo#103232]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6586/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-size-change.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13811/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-size-change.html [25]:
[Intel-gfx] [PATCH] drm/i915/pmu: Atomically acquire the gt_pm wakeref
Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
No automagic drop!
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 8 +++-
drivers/gpu/drm/i915/i915_pmu.c | 23 ---
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index ba960e1fc209..016298483de7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -9,7 +9,8 @@
#include
-struct intel_gt;
+#include "intel_gt_types.h"
+#include "intel_wakeref.h"
enum {
INTEL_GT_UNPARK,
@@ -19,6 +20,11 @@ enum {
void intel_gt_pm_get(struct intel_gt *gt);
void intel_gt_pm_put(struct intel_gt *gt);
+static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
+{
+ return intel_wakeref_get_if_active(>wakeref);
+}
+
void intel_gt_pm_init_early(struct intel_gt *gt);
void intel_gt_sanitize(struct intel_gt *gt, bool force);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..e71192804996 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,7 @@
#include
#include "gt/intel_engine.h"
+#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
#include "i915_pmu.h"
@@ -161,16 +162,12 @@ engines_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
- intel_wakeref_t wakeref;
unsigned long flags;
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
return;
- wakeref = 0;
- if (READ_ONCE(dev_priv->gt.awake))
- wakeref = intel_runtime_pm_get_if_in_use(_priv->runtime_pm);
- if (!wakeref)
+ if (!intel_gt_pm_get_if_awake(_priv->gt))
return;
spin_lock_irqsave(_priv->uncore.lock, flags);
@@ -205,7 +202,7 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned
int period_ns)
}
spin_unlock_irqrestore(_priv->uncore.lock, flags);
- intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+ intel_gt_pm_put(_priv->gt);
}
static void
@@ -222,15 +219,11 @@ frequency_sample(struct drm_i915_private *dev_priv,
unsigned int period_ns)
u32 val;
val = dev_priv->gt_pm.rps.cur_freq;
- if (dev_priv->gt.awake) {
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm,
- wakeref) {
- val =
intel_uncore_read_notrace(_priv->uncore,
- GEN6_RPSTAT1);
- val = intel_get_cagf(dev_priv, val);
- }
+ if (intel_gt_pm_get_if_awake(_priv->gt)) {
+ val = intel_uncore_read_notrace(_priv->uncore,
+ GEN6_RPSTAT1);
+ val = intel_get_cagf(dev_priv, val);
+ intel_gt_pm_put(_priv->gt);
}
add_sample_mult(_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
--
2.23.0.rc0
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/oa: add content to Makefile
On Tue, 30 Jul 2019, Michal Wajdeczko wrote:
> On Tue, 30 Jul 2019 13:34:30 +0200, Jani Nikula
> wrote:
>
>> Apparently the empty Makefile has caused some confusion. Add the
>> subdir-cc-flags-y as in 7fcc7ca549d4 ("drm/i915: add header search path
>> to subdir Makefiles") which should be useful.
>>
>> The generated headers still aren't self-contained, so can't add that.
>>
>> References:
>> http://marc.info/?i=80bf2204-558a-6d3f-c493-bf17b891f...@infradead.org
>> Cc: Chris Wilson
>> Cc: Lionel Landwerlin
>> Cc: Michal Wajdeczko
>> Signed-off-by: Jani Nikula
>>
>
> Reviewed-by: Michal Wajdeczko
Thanks, pushed the one patch to dinq. May I trouble you for review on
patches 2 and 3 as well please?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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