[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Keep the engine awake while we keep for preemption
== Series Details == Series: drm/i915/selftests: Keep the engine awake while we keep for preemption URL : https://patchwork.freedesktop.org/series/66601/ State : success == Summary == CI Bug Log - changes from CI_DRM_6881_full -> Patchwork_14379_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_6881_full and Patchwork_14379_full: ### New Piglit tests (7) ### * spec@arb_gpu_shader5@texturegather@vs-rgb-0-int-cubearray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@vs-rgb-1-int-cubearray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@vs-rgb-2-int-cube: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@vs-rgb-2-int-2darray-const: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-0-int-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-1-int-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-2-int-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_14379_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb5/igt@gem_exec_sched...@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_pwrite@big-cpu-forwards: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-apl1/igt@gem_pwr...@big-cpu-forwards.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-apl7/igt@gem_pwr...@big-cpu-forwards.html * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([fdo#105763] / [fdo#106538]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-glk6/igt@i915_pm_...@modeset-stress-extra-wait.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-glk8/igt@i915_pm_...@modeset-stress-extra-wait.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#110741]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#104873]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-glk9/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-suspend: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] / [fdo#109507]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb2/igt@kms_f...@flip-vs-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-iclb3/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html *
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Support for DP HDR outputs (rev7)
== Series Details == Series: drm/i915/dp: Support for DP HDR outputs (rev7) URL : https://patchwork.freedesktop.org/series/65656/ State : success == Summary == CI Bug Log - changes from CI_DRM_6881_full -> Patchwork_14378_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14378_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@preempt-blt: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-apl6/igt@gem_exec_sched...@preempt-blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-apl3/igt@gem_exec_sched...@preempt-blt.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +22 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108] / [fdo#107807]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-skl6/igt@i915_pm_...@system-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-skl2/igt@i915_pm_...@system-suspend.html * igt@kms_flip_tiling@flip-y-tiled: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#108303]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb8/igt@kms_flip_til...@flip-y-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-iclb6/igt@kms_flip_til...@flip-y-tiled.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-apl2/igt@kms_frontbuffer_track...@fbc-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-apl4/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-skl10/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@perf@polling: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#110728]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-skl2/igt@p...@polling.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-skl9/igt@p...@polling.html * igt@tools_test@tools_test: - shard-hsw: [PASS][23] -> [SKIP][24] ([fdo#109271]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/shard-hsw1/igt@tools_test@tools_test.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/shard-hsw5/igt@tools_test@tools_test.html Possible fixes * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][25] ([fdo#110854]) -> [PASS][26] [25]:
Re: [Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Lucas De Marchi
> Sent: Friday, August 23, 2019 1:21 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vetter, Daniel ; Pandiyan, Dhinakaran
>
> Subject: [Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render
> decompression
>
> From: Dhinakaran Pandiyan
>
> Gen-12 decompression is supported with Y-tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a ratio
> of
> 1:256. Gen-12 display decompression is incompatible with buffers
> compressed by earlier GPUs, so make use of a new modifier to identify
> gen-12 compression. Another notable change is that decompression is
> supported on all planes except cursor and on all pipes. This patch adds
> decompression support for [A,X]BGR888 pixel formats.
>
> Bspec: 18437
>
> v2: Fix checkpatch warnings (Lucas)
>
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Cc: Daniel Vetter
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 63 +---
> drivers/gpu/drm/i915/display/intel_sprite.c | 23 ---
> 2 files changed, 71 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 109d4fd961c6..190adbffe055 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> if (color_plane == 1)
> return 128;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + if (color_plane == 1)
> + return cpp;
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> @@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + return 4 * 4 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> @@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>
> static bool is_surface_linear(u64 modifier, int color_plane) {
> - return modifier == DRM_FORMAT_MOD_LINEAR;
> + return modifier == DRM_FORMAT_MOD_LINEAR ||
> +(modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
> +color_plane == 1);
> }
>
> static u32 intel_adjust_aligned_offset(int *x, int *y, @@ -2429,6 +2436,7
> @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> return I915_TILING_X;
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
Shouldn’t this modifier be added to skl_max_plane_width as well?
Thanks,
Radhakrishna Sripada
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> * us a ratio of one byte in the CCS for each 8x16 pixels in the
> * main surface.
> */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
> { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> @@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[]
> = {
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, };
>
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair
> +in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1
> +Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having
> +dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> +pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, };
> +
> static const struct
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Enable guc logging on guc log relay write (rev2)
== Series Details ==
Series: drm/i915/guc: Enable guc logging on guc log relay write (rev2)
URL : https://patchwork.freedesktop.org/series/66502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6885 -> Patchwork_14392
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14392:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14392 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927] /
[fdo#111381])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724] /
[fdo#111214])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-6770hq: [PASS][9] -> [INCOMPLETE][10] ([fdo#111519])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_reset:
- fi-icl-u3: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@i915_selftest@live_reset.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-icl-u3/igt@i915_selftest@live_reset.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][13] ([fdo#111600]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- {fi-tgl-u}: [INCOMPLETE][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][19] ([fdo#103167]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][21] ([fdo#107724]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-icl-u3/igt@prime_v...@basic-busy-default.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][23] ([fdo#111096]) -> [FAIL][24] ([fdo#111407])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[Intel-gfx] [RFC v2] drm/i915/guc: Enable guc logging on guc log relay write
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
v2: Style changes and fix typos. Add guc_log_relay_stop()
function. (Daniele)
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 53 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c| 22 +++--
3 files changed, 62 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 36332064de9c..e26c7748358b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -226,7 +226,7 @@ static void guc_read_update_log_buffer(struct intel_guc_log
*log)
mutex_lock(>relay.lock);
- if (WARN_ON(!intel_guc_log_relay_enabled(log)))
+ if (WARN_ON(!intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -361,6 +361,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
{
mutex_init(>relay.lock);
INIT_WORK(>relay.flush_work, capture_logs_work);
+ log->relay.started = false;
}
static int guc_log_relay_create(struct intel_guc_log *log)
@@ -546,7 +547,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32
level)
return ret;
}
-bool intel_guc_log_relay_enabled(const struct intel_guc_log *log)
+bool intel_guc_log_relay_created(const struct intel_guc_log *log)
{
return log->relay.buf_addr;
}
@@ -560,7 +561,7 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
mutex_lock(>relay.lock);
- if (intel_guc_log_relay_enabled(log)) {
+ if (intel_guc_log_relay_created(log)) {
ret = -EEXIST;
goto out_unlock;
}
@@ -585,6 +586,21 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
mutex_unlock(>relay.lock);
+ return 0;
+
+out_relay:
+ guc_log_relay_destroy(log);
+out_unlock:
+ mutex_unlock(>relay.lock);
+
+ return ret;
+}
+
+int intel_guc_log_relay_start(struct intel_guc_log *log)
+{
+ if (log->relay.started)
+ return -EEXIST;
+
guc_log_enable_flush_events(log);
/*
@@ -594,14 +610,9 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
*/
queue_work(system_highpri_wq, >relay.flush_work);
- return 0;
-
-out_relay:
- guc_log_relay_destroy(log);
-out_unlock:
- mutex_unlock(>relay.lock);
+ log->relay.started = true;
- return ret;
+ return 0;
}
void intel_guc_log_relay_flush(struct intel_guc_log *log)
@@ -610,6 +621,9 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
+ if (!log->relay.started)
+ return;
+
/*
* Before initiating the forceful flush, wait for any pending/ongoing
* flush to complete otherwise forceful flush may not actually happen.
@@ -623,18 +637,33 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
guc_log_capture_logs(log);
}
-void intel_guc_log_relay_close(struct intel_guc_log *log)
+/*
+ * Stops the relay log. Called from intel_guc_log_relay_close(), so no
+ * possibility of race with start/flush since relay_write cannot race
+ * relay_close.
+ */
+static void guc_log_relay_stop(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ if (!log->relay.started)
+ return;
+
guc_log_disable_flush_events(log);
intel_synchronize_irq(i915);
flush_work(>relay.flush_work);
+ log->relay.started = false;
+}
+
+void intel_guc_log_relay_close(struct intel_guc_log *log)
+{
+ guc_log_relay_stop(log);
+
mutex_lock(>relay.lock);
- GEM_BUG_ON(!intel_guc_log_relay_enabled(log));
+ GEM_BUG_ON(!intel_guc_log_relay_created(log));
guc_log_unmap(log);
guc_log_relay_destroy(log);
mutex_unlock(>relay.lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
index 6f764879acb1..c252c022c5fc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
@@ -47,6 +47,7 @@ struct intel_guc_log {
struct i915_vma *vma;
struct {
void *buf_addr;
+ bool started;
struct work_struct flush_work;
struct rchan *channel;
struct mutex lock;
@@ -65,8 +66,9 @@ int
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
== Series Details ==
Series: series starting with [1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66626/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6885 -> Patchwork_14391
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/
Known issues
Here are the changes found in Patchwork_14391 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][1] ([fdo#103167]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][3] ([fdo#103167]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/fi-icl-u3/igt@prime_v...@basic-busy-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
Participating hosts (55 -> 45)
--
Missing(10): fi-ilk-m540 fi-tgl-u fi-tgl-u2 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6885 -> Patchwork_14391
CI-20190529: 20190529
CI_DRM_6885: 11786d27cb029a083556ac9b82e33d74e250ce26 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14391: 7ee697d002d1a6fd689927b519efc233e479026c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7ee697d002d1 HAX: force enable_guc=2
3a37f385bcf4 drm/i915/uc: Update HuC firmware naming convention and load latest
HuC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
== Series Details == Series: series starting with [1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66626/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3a37f385bcf4 drm/i915/uc: Update HuC firmware naming convention and load latest HuC 7ee697d002d1 HAX: force enable_guc=2 -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dmc: Update ICL DMC version to v1.09
On Wed, 2019-09-11 at 12:21 -0700, Anusha Srivatsa wrote: > We have a new version of DMC for ICL - v1.09. > > This version adds the Half Refresh Rate capability > into DMC. Reviewed-by: José Roberto de Souza > > Cc: José Roberto de Souza > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/intel_csr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_csr.c > b/drivers/gpu/drm/i915/intel_csr.c > index 546577e39b4e..09870a31b4f0 100644 > --- a/drivers/gpu/drm/i915/intel_csr.c > +++ b/drivers/gpu/drm/i915/intel_csr.c > @@ -44,8 +44,8 @@ > #define TGL_CSR_MAX_FW_SIZE 0x6000 > MODULE_FIRMWARE(TGL_CSR_PATH); > > -#define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin" > -#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) > +#define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin" > +#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) > #define ICL_CSR_MAX_FW_SIZE 0x6000 > MODULE_FIRMWARE(ICL_CSR_PATH); > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH AUTOSEL 5.2 13/23] drm/i915/userptr: Acquire the page lock around set_page_dirty()
On Thu, Sep 12, 2019 at 11:51:33PM +0300, Thomas Backlund wrote:
Den 03-09-2019 kl. 19:24, skrev Sasha Levin:
From: Chris Wilson
[ Upstream commit aa56a292ce623734ddd30f52d73f527d1f3529b5 ]
set_page_dirty says:
For pages with a mapping this should be done under the page lock
for the benefit of asynchronous memory errors who prefer a
consistent dirty state. This rule can be broken in some special
cases, but should be better not to.
Under those rules, it is only safe for us to use the plain set_page_dirty
calls for shmemfs/anonymous memory. Userptr may be used with real
mappings and so needs to use the locked version (set_page_dirty_lock).
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203317
Fixes: 5cc9ed4b9a7a ("drm/i915: Introduce mapping of user pages into video memory
(userptr) ioctl")
References: 6dcc693bc57f ("ext4: warn when page is dirtied without buffers")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: sta...@vger.kernel.org
Reviewed-by: Tvrtko Ursulin
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708140327.26825-1-ch...@chris-wilson.co.uk
(cherry picked from commit cb6d7c7dc7ff8cace666ddec66334117a6068ce2)
Signed-off-by: Jani Nikula
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 8079ea3af1039..b1fc15c7f5997 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -678,7 +678,15 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj,
for_each_sgt_page(page, sgt_iter, pages) {
if (obj->mm.dirty)
- set_page_dirty(page);
+ /*
+* As this may not be anonymous memory (e.g. shmem)
+* but exist on a real mapping, we have to lock
+* the page in order to dirty it -- holding
+* the page reference is not sufficient to
+* prevent the inode from being truncated.
+* Play safe and take the lock.
+*/
+ set_page_dirty_lock(page);
mark_page_accessed(page);
put_page(page);
Please drop this one from all 5.2 and 4.19 stable queues
It has now been reverted in Linus tree:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=505a8ec7e11ae5236c4a154a1e24ef49a8349600
Now dropped, thank you.
--
Thanks,
Sasha
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
Make both GuC and HuC to use "." as the separator. Hardcode the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC. The current convention being: _uc_..patch.bin Update the versions of HuC being loaded of the platforms. SKL - v2.0.0 BXT - v2.0.0 KBL - v4.0.0 GLK - v4.0.0 CFL - KBL v4.0.0 ICL - v9.0.0 CML - v4.0.0 v2: Remove the separator parameter altogether from __MAKE_UC_FW_PATH.(Daniele) - Squash all firmware update patches (Daniele) v3: s/huc/HuC - Correct the order of platforms - Change REVID of cml to 5(Michal) - Code space changes in huc_def (Daniele) Suggested-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off-by: Anusha Srivatsa Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 296a82603be0..ea9a807abd4f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -39,26 +39,27 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * Must be ordered based on platform + revid, from newer to older. */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ - fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ - fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ - fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01, 8, 2893)) \ - fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 1398)) - -#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ + fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ + fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) + +#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \ "i915/" \ __stringify(prefix_) name_ \ - __stringify(major_) separator_ \ - __stringify(minor_) separator_ \ + __stringify(major_) "." \ + __stringify(minor_) "." \ __stringify(patch_) ".bin" #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \ - __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_) + __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_) #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \ - __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_) + __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_) /* All blobs need to be declared via MODULE_FIRMWARE() */ #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] HAX: force enable_guc=2
Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index d29ade3b7de6..f9fbb1f2fabf 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, 2) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Extend MI_SEMAPHORE_WAIT
== Series Details ==
Series: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT
URL : https://patchwork.freedesktop.org/series/66625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6885 -> Patchwork_14389
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14389:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
Known issues
Here are the changes found in Patchwork_14389 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-cfl-8109u: [PASS][3] -> [INCOMPLETE][4] ([fdo#106070])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html
- fi-icl-u3: [PASS][5] -> [DMESG-FAIL][6] ([fdo#111678])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][9] ([fdo#111600]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][11] ([fdo#103167]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-icl-u3/igt@prime_v...@basic-busy-default.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111096]) -> [FAIL][18] ([fdo#111407])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (55 -> 48)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6885 -> Patchwork_14389
CI-20190529: 20190529
CI_DRM_6885: 11786d27cb029a083556ac9b82e33d74e250ce26 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14389:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/4] drm/i915/tgl: Introduce gen12 forcewake ranges (rev3)
== Series Details == Series: series starting with [1/4] drm/i915/tgl: Introduce gen12 forcewake ranges (rev3) URL : https://patchwork.freedesktop.org/series/66608/ State : failure == Summary == Applying: drm/i915/tgl: Introduce gen12 forcewake ranges Applying: drm/i915/tgl: s/ss/eu fuse reading support Applying: drm/i915/tgl: Re-enable rc6 Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_pci.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_pci.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_pci.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0003 drm/i915/tgl: Re-enable rc6 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
== Series Details ==
Series: series starting with [1/2] drm/connector: Share with non-atomic drivers
the function to get the single encoder
URL : https://patchwork.freedesktop.org/series/66619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6885 -> Patchwork_14387
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14387:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_close_race@basic-threads:
- {fi-tgl-u2}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-tgl-u2/igt@gem_close_r...@basic-threads.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14387 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][7] -> [INCOMPLETE][8] ([fdo#107718])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@prime_vgem@basic-read:
- fi-icl-u3: [PASS][9] -> [DMESG-WARN][10] ([fdo#107724])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-icl-u3/igt@prime_v...@basic-read.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][11] ([fdo#111600]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- {fi-tgl-u}: [INCOMPLETE][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-icl-u3/igt@prime_v...@basic-busy-default.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][21] ([fdo#111096]) -> [FAIL][22] ([fdo#111407])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]:
Re: [Intel-gfx] [RFC] drm/i915/guc: Enable guc logging on guc log relay write
On 9/11/19 2:28 PM, Fosha, Robert M wrote:
On 9/10/19 5:48 PM, Daniele Ceraolo Spurio wrote:
On 9/10/19 3:46 PM, Robert M. Fosha wrote:
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 38 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 2 ++
drivers/gpu/drm/i915/i915_debugfs.c | 27 +--
3 files changed, 56 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 36332064de9c..9a98270d05b6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -361,6 +361,7 @@ void intel_guc_log_init_early(struct
intel_guc_log *log)
{
mutex_init(>relay.lock);
INIT_WORK(>relay.flush_work, capture_logs_work);
+ log->relay_started = false;
}
static int guc_log_relay_create(struct intel_guc_log *log)
@@ -585,15 +586,6 @@ int intel_guc_log_relay_open(struct
intel_guc_log *log)
mutex_unlock(>relay.lock);
- guc_log_enable_flush_events(log);
-
- /*
- * When GuC is logging without us relaying to userspace, we're
ignoring
- * the flush notification. This means that we need to
unconditionally
- * flush on relay enabling, since GuC only notifies us once.
- */
- queue_work(system_highpri_wq, >relay.flush_work);
-
return 0;
out_relay:
@@ -604,12 +596,38 @@ int intel_guc_log_relay_open(struct
intel_guc_log *log)
return ret;
}
+int intel_guc_log_relay_start(struct intel_guc_log *log)
+{
+ int ret = 0;
+
+ if (log->relay_started) {
+ ret = -EEXIST;
+ } else {
style: for this kind of checks, we usually just return early instead
of using an if-else, i.e.:
if (log->relay_started)
return -EEXIST;
[...] /* code */
return 0;
+ guc_log_enable_flush_events(log);
+
+ /*
+ * When GuC is logging without us relaying to userspace, we're
+ * ignoring the flush notification. This means that we need to
+ * unconditionally * flush on relay enabling, since GuC only
stray "*"
+ * notifies us once.
+ */
+ queue_work(system_highpri_wq, >relay.flush_work);
+
+ log->relay_started = false;
s/false/true/
+ }
+
+ return ret;
+}
+
void intel_guc_log_relay_flush(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
+ if (!log->relay_started)
+ return;
+
/*
* Before initiating the forceful flush, wait for any
pending/ongoing
* flush to complete otherwise forceful flush may not actually
happen.
@@ -638,6 +656,8 @@ void intel_guc_log_relay_close(struct
intel_guc_log *log)
guc_log_unmap(log);
guc_log_relay_destroy(log);
mutex_unlock(>relay.lock);
+
+ log->relay_started = false;
For symmetry, it might be worth adding a guc_log_relay_stop:
Should it be intel_guc_log_relay_stop to be consistent with naming of
other functions?
intel_* prefix is usually only used for non-static functions
static void guc_log_relay_stop(...)
{
if (!log->relay_started)
return;
guc_log_disable_flush_events(log);
intel_synchronize_irq(i915);
flush_work(>relay.flush_work);
log->relay_started = false;
}
and call it from intel_guc_log_relay_close().
Also, it should be impossible to race the start/flush with the stop
because the relay_write can't race the relay_close, but it might be
worth a comment in case we decide to have guc_log_relay_stop()
callable from the debugfs in the future.
How about this comment just above the relay_stop function:
/*
* Stops the relay log. Called from intel_guc_log_relay_close(), so no
* possibility of race with start/flush since relay_write cannot race
* relay_close.
*/
LGTM.
Daniele
}
void intel_guc_log_handle_flush_event(struct intel_guc_log *log)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
index 6f764879acb1..ecf7a49416b4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
@@ -44,6 +44,7 @@ struct intel_guc;
struct intel_guc_log {
u32 level;
+ bool relay_started;
this should move inside the relay structure below. Just "started" will
be enough as a name at that point because the structure is already
called relay.
struct i915_vma *vma;
struct {
void *buf_addr;
@@ -67,6 +68,7 @@ void
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: Show the logical context ring state on dumping (rev3)
== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping (rev3) URL : https://patchwork.freedesktop.org/series/66422/ State : failure == Summary == Applying: drm/i915: Show the logical context ring state on dumping Applying: drm/i915/selftests: Verify the LRC register layout between init and HW Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_lrc.c M drivers/gpu/drm/i915/gt/intel_lrc_reg.h M drivers/gpu/drm/i915/gt/selftest_lrc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/selftest_lrc.c Auto-merging drivers/gpu/drm/i915/gt/intel_lrc_reg.h Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_lrc.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915/selftests: Verify the LRC register layout between init and HW When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
== Series Details == Series: series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66619/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/connector: Share with non-atomic drivers the function to get the single encoder +drivers/gpu/drm/drm_crtc_helper.c:467:20: warning: symbol 'drm_connector_get_single_encoder' was not declared. Should it be static? Commit: drm/connector: Allow max possible encoders to attach to a connector +drivers/gpu/drm/drm_crtc_helper.c:467:20: warning: symbol 'drm_connector_get_single_encoder' was not declared. Should it be static? -O:drivers/gpu/drm/drm_crtc_helper.c:467:20: warning: symbol 'drm_connector_get_single_encoder' was not declared. Should it be static? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
== Series Details == Series: series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66619/ State : warning == Summary == $ dim checkpatch origin/drm-tip 87c2a5a45bc0 drm/connector: Share with non-atomic drivers the function to get the single encoder fbd5f383c05e drm/connector: Allow max possible encoders to attach to a connector -:497: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'connector' - possible side-effects? #497: FILE: include/drm/drm_connector.h:1612: +#define drm_connector_for_each_possible_encoder(connector, encoder) \ + drm_for_each_encoder_mask(encoder, (connector)->dev, \ + (connector)->possible_encoders) total: 0 errors, 0 warnings, 1 checks, 390 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't mix srcu tag and negative error codes (rev2)
== Series Details ==
Series: drm/i915: Don't mix srcu tag and negative error codes (rev2)
URL : https://patchwork.freedesktop.org/series/66524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6885 -> Patchwork_14386
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14386:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14386 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][5] ([fdo#111600]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- {fi-tgl-u}: [INCOMPLETE][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/fi-icl-u3/igt@prime_v...@basic-busy-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (55 -> 48)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6885 -> Patchwork_14386
CI-20190529: 20190529
CI_DRM_6885: 11786d27cb029a083556ac9b82e33d74e250ce26 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14386: 1d7b9bb125ec99302e03e20bfe623e52cd23273b @
[Intel-gfx] ✓ Fi.CI.IGT: success for Mdev: support mutiple kinds of devices
== Series Details == Series: Mdev: support mutiple kinds of devices URL : https://patchwork.freedesktop.org/series/66588/ State : success == Summary == CI Bug Log - changes from CI_DRM_6877_full -> Patchwork_14376_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14376_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@basic-hang-rcs0: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([fdo#103540]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-hsw4/igt@gem_b...@basic-hang-rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-hsw8/igt@gem_b...@basic-hang-rcs0.html * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_eio@reset-stress: - shard-snb: [PASS][5] -> [FAIL][6] ([fdo#109661]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-snb6/igt@gem_...@reset-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-snb4/igt@gem_...@reset-stress.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-skl9/igt@i915_susp...@debugfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-skl10/igt@i915_susp...@debugfs-reader.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-glk4/igt@kms_f...@2x-flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-glk3/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103927]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-apl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-iclb2/igt@kms_psr2_su@page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-iclb8/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_setmode@basic: - shard-apl: [PASS][25] -> [FAIL][26] ([fdo#99912]) [25]:
[Intel-gfx] [PATCH] drm/i915/tgl: Extend MI_SEMAPHORE_WAIT
On Tigerlake, MI_SEMAPHORE_WAIT grew an extra dword, so be sure to
update the length field and emit that extra parameter and any padding
noop as required.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 69 ++--
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 21 --
4 files changed, 81 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index fbad403ab7ac..ad6ba92f4d65 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -112,6 +112,7 @@
#define MI_SEMAPHORE_SIGNALMI_INSTR(0x1b, 0) /* GEN8+ */
#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
+#define MI_SEMAPHORE_WAIT_GEN12MI_INSTR(0x1c, 3) /* GEN12+ */
#define MI_SEMAPHORE_POLL(1 << 15)
#define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
#define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a3f0e4999744..840ea473f9ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2879,6 +2879,22 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct
i915_request *request, u32 *cs)
return gen8_emit_fini_breadcrumb_footer(request, cs);
}
+static u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *request,
+ u32 *cs)
+{
+ cs = gen8_emit_ggtt_write_rcs(cs,
+ request->fence.seqno,
+ request->timeline->hwsp_offset,
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TILE_CACHE_FLUSH |
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_DC_FLUSH_ENABLE |
+ PIPE_CONTROL_FLUSH_ENABLE);
+
+ return gen8_emit_fini_breadcrumb_footer(request, cs);
+}
+
/*
* Note that the CS instruction pre-parser will not stall on the breadcrumb
* flush and will continue pre-fetching the instructions after it before the
@@ -2897,7 +2913,48 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct
i915_request *request, u32 *cs)
* All the above applies only to the instructions themselves. Non-inline data
* used by the instructions is not pre-fetched.
*/
-static u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *request,
+
+static u32 *gen12_emit_preempt_busywait(struct i915_request *request, u32 *cs)
+{
+ *cs++ = MI_SEMAPHORE_WAIT_GEN12 |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ *cs++ = 0;
+ *cs++ = intel_hws_preempt_address(request->engine);
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = MI_NOOP;
+
+ return cs;
+}
+
+static __always_inline u32*
+gen12_emit_fini_breadcrumb_footer(struct i915_request *request, u32 *cs)
+{
+ *cs++ = MI_USER_INTERRUPT;
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ if (intel_engine_has_semaphores(request->engine))
+ cs = gen12_emit_preempt_busywait(request, cs);
+
+ request->tail = intel_ring_offset(request, cs);
+ assert_ring_tail_valid(request->ring, request->tail);
+
+ return gen8_emit_wa_tail(request, cs);
+}
+
+static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
+{
+ cs = gen8_emit_ggtt_write(cs,
+ request->fence.seqno,
+ request->timeline->hwsp_offset,
+ 0);
+
+ return gen12_emit_fini_breadcrumb_footer(request, cs);
+}
+
+static u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *request,
u32 *cs)
{
cs = gen8_emit_ggtt_write_rcs(cs,
@@ -2910,7 +2967,7 @@ static u32 *gen11_emit_fini_breadcrumb_rcs(struct
i915_request *request,
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
- return gen8_emit_fini_breadcrumb_footer(request, cs);
+ return gen12_emit_fini_breadcrumb_footer(request, cs);
}
static void execlists_park(struct intel_engine_cs *engine)
@@ -2939,9 +2996,6 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
- if (INTEL_GEN(engine->i915) >= 12) /* XXX disabled for debugging */
- engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES;
-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Don't mix srcu tag and negative error codes (rev2)
== Series Details == Series: drm/i915: Don't mix srcu tag and negative error codes (rev2) URL : https://patchwork.freedesktop.org/series/66524/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Don't mix srcu tag and negative error codes +drivers/gpu/drm/i915/gt/intel_reset.c:1217:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block -O:drivers/gpu/drm/i915/gt/intel_reset.c:1217:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations.
Op 12-09-2019 om 20:05 schreef Ville Syrjälä: > On Thu, Sep 12, 2019 at 06:01:57PM +0200, Maarten Lankhorst wrote: >> Hey, >> >> Op 12-09-2019 om 16:34 schreef Sasha Levin: >>> Hi, >>> >>> [This is an automated email] >>> >>> This commit has been processed because it contains a "Fixes:" tag, >>> fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and >>> Slice Count for DSC. >>> >>> The bot has tested the following trees: v5.2.14. >>> >>> v5.2.14: Failed to apply! Possible dependencies: >>> Unable to calculate >>> >>> >>> NOTE: The patch will not be queued to stable trees until it is upstream. >>> >>> How should we proceed with this patch? >>> >>> -- >>> Thanks, >>> Sasha >> Why is this bot asking for patches on the trybot mailing list? > Did you forget --suppress-cc=all ? > Ah that's it, thanks! :) ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/connector: Allow max possible encoders to attach to a connector
Currently we restrict the number of encoders that can be linked to
a connector to 3, increase it to match the maximum number of encoders
that can be initialized(32).
To more effiently do that lets switch from an array of encoder ids to
bitmask.
v2: Fixing missed return on amdgpu_dm_connector_to_encoder()
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Alex Deucher
Cc: dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
Reviewed-by: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
.../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +-
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 -
drivers/gpu/drm/drm_client_modeset.c | 3 +-
drivers/gpu/drm/drm_connector.c | 31 +--
drivers/gpu/drm/drm_crtc_helper.c | 9 --
drivers/gpu/drm/drm_probe_helper.c| 3 +-
drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.c | 7 ++---
drivers/gpu/drm/radeon/radeon_connectors.c| 27 ++--
include/drm/drm_connector.h | 18 +--
12 files changed, 55 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index ece55c8fa673..d8729285f731 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -217,11 +217,10 @@ amdgpu_connector_update_scratch_regs(struct drm_connector
*connector,
struct drm_encoder *encoder;
const struct drm_connector_helper_funcs *connector_funcs =
connector->helper_private;
bool connected;
- int i;
best_encoder = connector_funcs->best_encoder(connector);
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if ((encoder == best_encoder) && (status ==
connector_status_connected))
connected = true;
else
@@ -236,9 +235,8 @@ amdgpu_connector_find_encoder(struct drm_connector
*connector,
int encoder_type)
{
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (encoder->encoder_type == encoder_type)
return encoder;
}
@@ -347,10 +345,9 @@ static struct drm_encoder *
amdgpu_connector_best_single_encoder(struct drm_connector *connector)
{
struct drm_encoder *encoder;
- int i;
/* pick the first one */
- drm_connector_for_each_possible_encoder(connector, encoder, i)
+ drm_connector_for_each_possible_encoder(connector, encoder)
return encoder;
return NULL;
@@ -1065,9 +1062,8 @@ amdgpu_connector_dvi_detect(struct drm_connector
*connector, bool force)
/* find analog encoder */
if (amdgpu_connector->dac_load_detect) {
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
continue;
@@ -1117,9 +1113,8 @@ amdgpu_connector_dvi_encoder(struct drm_connector
*connector)
{
struct amdgpu_connector *amdgpu_connector =
to_amdgpu_connector(connector);
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (amdgpu_connector->use_digital == true) {
if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
return encoder;
@@ -1134,7 +1129,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector
*connector)
/* then check use digitial */
/* pick the first one */
- drm_connector_for_each_possible_encoder(connector, encoder, i)
+ drm_connector_for_each_possible_encoder(connector, encoder)
return encoder;
return NULL;
@@ -1271,9 +1266,8 @@ u16
amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
{
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
[Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
This 3 non-atomic drivers all have the same function getting the
only encoder available in the connector, also atomic drivers have
this fallback. So moving it a common place and sharing between atomic
and non-atomic drivers.
While at it I also removed the mention of
drm_atomic_helper_best_encoder() that was renamed in
commit 297e30b5d9b6 ("drm/atomic-helper: Unexport
drm_atomic_helper_best_encoder").
v3: moving drm_connector_get_single_encoder to drm_kms_helper module
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Laurent Pinchart
Cc: dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/ast/ast_mode.c | 12
drivers/gpu/drm/drm_atomic_helper.c| 15 ++-
drivers/gpu/drm/drm_crtc_helper.c | 17 -
drivers/gpu/drm/drm_crtc_helper_internal.h | 3 +++
drivers/gpu/drm/mgag200/mgag200_mode.c | 11 ---
drivers/gpu/drm/udl/udl_connector.c| 8
include/drm/drm_modeset_helper_vtables.h | 6 +++---
7 files changed, 24 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index d349c721501c..eef95e1af06b 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -687,17 +687,6 @@ static void ast_encoder_destroy(struct drm_encoder
*encoder)
kfree(encoder);
}
-
-static struct drm_encoder *ast_best_single_encoder(struct drm_connector
*connector)
-{
- int enc_id = connector->encoder_ids[0];
- /* pick the encoder ids */
- if (enc_id)
- return drm_encoder_find(connector->dev, NULL, enc_id);
- return NULL;
-}
-
-
static const struct drm_encoder_funcs ast_enc_funcs = {
.destroy = ast_encoder_destroy,
};
@@ -847,7 +836,6 @@ static void ast_connector_destroy(struct drm_connector
*connector)
static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
.mode_valid = ast_mode_valid,
.get_modes = ast_get_modes,
- .best_encoder = ast_best_single_encoder,
};
static const struct drm_connector_funcs ast_connector_funcs = {
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 4706439fb490..9d7e4da6c292 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -97,17 +97,6 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state
*state,
}
}
-/*
- * For connectors that support multiple encoders, either the
- * .atomic_best_encoder() or .best_encoder() operation must be implemented.
- */
-static struct drm_encoder *
-pick_single_encoder_for_connector(struct drm_connector *connector)
-{
- WARN_ON(connector->encoder_ids[1]);
- return drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[0]);
-}
-
static int handle_conflicting_encoders(struct drm_atomic_state *state,
bool disable_conflicting_encoders)
{
@@ -135,7 +124,7 @@ static int handle_conflicting_encoders(struct
drm_atomic_state *state,
else if (funcs->best_encoder)
new_encoder = funcs->best_encoder(connector);
else
- new_encoder =
pick_single_encoder_for_connector(connector);
+ new_encoder =
drm_connector_get_single_encoder(connector);
if (new_encoder) {
if (encoder_mask & drm_encoder_mask(new_encoder)) {
@@ -359,7 +348,7 @@ update_connector_routing(struct drm_atomic_state *state,
else if (funcs->best_encoder)
new_encoder = funcs->best_encoder(connector);
else
- new_encoder = pick_single_encoder_for_connector(connector);
+ new_encoder = drm_connector_get_single_encoder(connector);
if (!new_encoder) {
DRM_DEBUG_ATOMIC("No suitable encoder found for
[CONNECTOR:%d:%s]\n",
diff --git a/drivers/gpu/drm/drm_crtc_helper.c
b/drivers/gpu/drm/drm_crtc_helper.c
index a51824a7e7c1..4a7447a53cea 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -460,6 +460,17 @@ drm_crtc_helper_disable(struct drm_crtc *crtc)
__drm_helper_disable_unused_functions(dev);
}
+/*
+ * For connectors that support multiple encoders, either the
+ * .atomic_best_encoder() or .best_encoder() operation must be implemented.
+ */
+struct drm_encoder *
+drm_connector_get_single_encoder(struct drm_connector *connector)
+{
+ WARN_ON(connector->encoder_ids[1]);
+ return drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[0]);
+}
+
/**
* drm_crtc_helper_set_config - set a new config from userspace
* @set: mode set configuration
@@ -625,7 +636,11 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set,
new_encoder = connector->encoder;
for (ro = 0; ro <
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: introduce INTEL_DISPLAY_ENABLED()
== Series Details == Series: drm/i915: introduce INTEL_DISPLAY_ENABLED() URL : https://patchwork.freedesktop.org/series/66610/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6883 -> Patchwork_14385 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14385 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14385, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14385: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@module-reload: - fi-cfl-8700k: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-cfl-8700k/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-cfl-8700k/igt@i915_pm_...@module-reload.html - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-kbl-x1275/igt@i915_pm_...@module-reload.html - fi-skl-guc: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-skl-guc/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-skl-guc/igt@i915_pm_...@module-reload.html - fi-cfl-guc: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-cfl-guc/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-cfl-guc/igt@i915_pm_...@module-reload.html - fi-skl-iommu: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-skl-iommu/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-skl-iommu/igt@i915_pm_...@module-reload.html - fi-whl-u: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-whl-u/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-whl-u/igt@i915_pm_...@module-reload.html - fi-skl-6260u: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-skl-6260u/igt@i915_pm_...@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-skl-6260u/igt@i915_pm_...@module-reload.html - fi-skl-6770hq: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-skl-6770hq/igt@i915_pm_...@module-reload.html - fi-bdw-5557u: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-bdw-5557u/igt@i915_pm_...@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-bdw-5557u/igt@i915_pm_...@module-reload.html - fi-kbl-r: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-kbl-r/igt@i915_pm_...@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-kbl-r/igt@i915_pm_...@module-reload.html - fi-skl-lmem:[PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-skl-lmem/igt@i915_pm_...@module-reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-skl-lmem/igt@i915_pm_...@module-reload.html - fi-hsw-peppy: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-hsw-peppy/igt@i915_pm_...@module-reload.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-hsw-peppy/igt@i915_pm_...@module-reload.html - fi-cfl-8109u: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-cfl-8109u/igt@i915_pm_...@module-reload.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-cfl-8109u/igt@i915_pm_...@module-reload.html - fi-skl-6600u: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-skl-6600u/igt@i915_pm_...@module-reload.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14385/fi-skl-6600u/igt@i915_pm_...@module-reload.html - fi-skl-6700k2: [PASS][29] -> [DMESG-WARN][30] [29]:
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Disable preemption while being debugged
Quoting Daniele Ceraolo Spurio (2019-09-12 19:45:27) > > > On 9/12/19 6:23 AM, Chris Wilson wrote: > > We see failures where the context continues executing past a > > preemption event, eventually leading to situations where a request has > > executed before we have event submitted it to HW! It seems like tgl is > > AFAIK on TGL the CS can detect tail updates in the image of a running > context even if the lrc hasn't been resubmitted via the elsp. Could that > be related to the early execution of requests? I haven't looked at the > failure logs, so forgive me if I'm completely off-mark :) We only update the CTX_RING_TAIL just prior to [re]submitting the context. But fun and games ensue around preemption where we often have to rewind the RING_TAIL. Still we should never push it behind RING_HEAD (so long as our semaphore is solid), so it should never be able to go past any of the previous RING_TAIL updates we made. At the moment, I'm just focusing on trimming back the features until we have a solid platform and then we will be better place to be able to look at what is going wrong. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: introduce INTEL_DISPLAY_ENABLED()
== Series Details == Series: drm/i915: introduce INTEL_DISPLAY_ENABLED() URL : https://patchwork.freedesktop.org/series/66610/ State : warning == Summary == $ dim checkpatch origin/drm-tip 427d67464aa8 drm/i915: introduce INTEL_DISPLAY_ENABLED() -:135: WARNING:LONG_LINE: line over 100 characters #135: FILE: drivers/gpu/drm/i915/i915_drv.h:2196: +#define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) total: 0 errors, 1 warnings, 0 checks, 89 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/tgl: Introduce gen12 forcewake ranges (rev2)
== Series Details ==
Series: series starting with [1/4] drm/i915/tgl: Introduce gen12 forcewake
ranges (rev2)
URL : https://patchwork.freedesktop.org/series/66608/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6883 -> Patchwork_14384
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/
Known issues
Here are the changes found in Patchwork_14384 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109483])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [PASS][9] -> [FAIL][10] ([fdo#103167])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][11] -> [DMESG-WARN][12] ([fdo#106387]) +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724] / [fdo#111214]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-icl-u3/igt@i915_module_l...@reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][15] ([fdo#08]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [FAIL][17] ([fdo#109483]) -> [DMESG-WARN][18]
([fdo#102505] / [fdo#110390])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111096]) -> [FAIL][20] ([fdo#111407])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6883/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14384/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
[fdo#111096]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/tgl: Introduce gen12 forcewake ranges (rev2)
== Series Details == Series: series starting with [1/4] drm/i915/tgl: Introduce gen12 forcewake ranges (rev2) URL : https://patchwork.freedesktop.org/series/66608/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: Introduce gen12 forcewake ranges +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block Commit: drm/i915/tgl: s/ss/eu fuse reading support Okay! Commit: drm/i915/tgl: Re-enable rc6 Okay! Commit: drm/i915/tgl: Disable preemption while being debugged Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Disable preemption while being debugged
On 9/12/19 6:23 AM, Chris Wilson wrote:
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
AFAIK on TGL the CS can detect tail updates in the image of a running
context even if the lrc hasn't been resubmitted via the elsp. Could that
be related to the early execution of requests? I haven't looked at the
failure logs, so forgive me if I'm completely off-mark :)
Daniele
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for our semaphore waits around preemption.
v2: And disable internal semaphore usage
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
drivers/gpu/drm/i915/i915_pci.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 47d766ccea71..a3f0e4999744 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2939,6 +2939,9 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
+ if (INTEL_GEN(engine->i915) >= 12) /* XXX disabled for debugging */
+ engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES;
+
if (engine->class != COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) >= 12)
engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
}
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..2ca34a5cf7d3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -798,6 +798,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.has_rc6 = false, /* XXX disabled for debugging */
+ .has_logical_ring_preemption = false, /* XXX disabled for debugging */
};
#undef GEN
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
On Thu, Sep 12, 2019 at 09:42:11AM +0300, Jani Nikula wrote: > On Wed, 11 Sep 2019, Manasi Navare wrote: > > On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote: > >> On Tue, 10 Sep 2019, Manasi Navare wrote: > >> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote: > >> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: > >> >> > On Sun, 08 Sep 2019, Manasi Navare wrote: > >> >> > > This patch series addresses all review comments and now the enable > >> >> > > and > >> >> > > disable paths follow the method of obtaining slave states from > >> >> > > master > >> >> > > and updating master-slaves in correct order during master modeset. > >> >> > > >> >> > Main high level question: what does it take to enable this on gen9+? > >> >> > >> >> As per the Bspec project platforms, the first platform that supports > >> >> this is > >> >> ICL > >> > > >> > Hi Jani, > >> > > >> > Apparently the Bspec caused some confusion, after double checking with > >> > the > >> > HW teams here, this feature is enabled starting BDW for the SST > >> > connectors > >> > and only the MST support is new to Gen 11+. > >> > > >> > So i guess I can change the patches to add support starting BDW and > >> > this should also fix the 5K tiled display issue that Ankit has been > >> > working on > >> > >> Thanks! I don't mind getting the patches merged for ICL+ at first, and > >> updating to cover older gens in follow-up. > > > > So you are suggesting that i keep the patches as is and have them get > > merged first and then i could change the GEN checks to add support for > > BDW+? > > I'm saying it's up to you. Whatever makes most sense to you. If you're > at the brink of getting the ICL patches merged, there's not much point > in rehashing and delaying that, is there? Yes I agree, thanks a lot Jani for your inputs/suggestions. I will push for the reviews on these for ICL+ and get these merged first. Manasi > > BR, > Jani. > > > > > > Regards > > Manasi > > > >> > >> BR, > >> Jani. > >> > >> > >> > > >> > Manasi > >> > > >> >> > >> >> Regards > >> >> Manasi > >> >> > >> >> > > >> >> > BR, > >> >> > Jani. > >> >> > > >> >> > > >> >> > -- > >> >> > Jani Nikula, Intel Open Source Graphics Center > >> >> ___ > >> >> Intel-gfx mailing list > >> >> Intel-gfx@lists.freedesktop.org > >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/execlists: Add a paranoid flush of the CSB pointers upon reset
== Series Details == Series: series starting with [1/2] drm/i915/execlists: Add a paranoid flush of the CSB pointers upon reset URL : https://patchwork.freedesktop.org/series/66586/ State : success == Summary == CI Bug Log - changes from CI_DRM_6876_full -> Patchwork_14375_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14375_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-iclb2/igt@gem_exec_sched...@out-order-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-iclb3/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_fence_thrash@bo-write-verify-threaded-none: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-iclb3/igt@gem_fence_thr...@bo-write-verify-threaded-none.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-iclb7/igt@gem_fence_thr...@bo-write-verify-threaded-none.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-skl1/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-skl7/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#104873]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-glk1/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-fences-interruptible: - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-apl1/igt@kms_f...@flip-vs-fences-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-apl1/igt@kms_f...@flip-vs-fences-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#109507]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-skl3/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-skl5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14375/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_primary_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6876/shard-iclb2/igt@kms_psr@psr2_primary_render.html [24]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: Disable preemption while being debugged (rev2)
== Series Details ==
Series: drm/i915/tgl: Disable preemption while being debugged (rev2)
URL : https://patchwork.freedesktop.org/series/66607/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6882 -> Patchwork_14383
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14383 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14383, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14383:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14383 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_self_import@basic-llseek-size:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@prime_self_imp...@basic-llseek-size.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-icl-u3/igt@prime_self_imp...@basic-llseek-size.html
Possible fixes
* igt@gem_sync@basic-store-each:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111647]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-tgl-u/igt@gem_s...@basic-store-each.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-tgl-u/igt@gem_s...@basic-store-each.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][9] ([fdo#106107] / [fdo#106350]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-mmap:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14383/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
Participating hosts (55 -> 47)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6882 -> Patchwork_14383
CI-20190529: 20190529
CI_DRM_6882: a7f950bbf06a55e6a47934b2891ef595f97165d4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14383: cf55679c12de6e371bd9d7213b9f701b3632e562 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cf55679c12de drm/i915/tgl: Disable preemption while being debugged
== Logs ==
For more details see:
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/userptr: Acquire the page lock around set_page_dirty()"
== Series Details ==
Series: Revert "drm/i915/userptr: Acquire the page lock around set_page_dirty()"
URL : https://patchwork.freedesktop.org/series/66605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6882 -> Patchwork_14382
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14382:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14382 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-apl-guc/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-apl-guc/igt@gem_exec_susp...@basic-s3.html
* igt@prime_vgem@basic-fence-read:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@prime_v...@basic-fence-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-icl-u3/igt@prime_v...@basic-fence-read.html
Possible fixes
* igt@gem_sync@basic-store-each:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111647]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-tgl-u/igt@gem_s...@basic-store-each.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-tgl-u/igt@gem_s...@basic-store-each.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][9] ([fdo#106107] / [fdo#106350]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-mmap:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][15] ([fdo#110595] / [fdo#111214]) ->
[DMESG-WARN][16] ([fdo#106107] / [fdo#110595] / [fdo#111214])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u2/igt@i915_module_l...@reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/fi-icl-u2/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
Participating hosts (55 -> 48)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6882 -> Patchwork_14382
CI-20190529: 20190529
CI_DRM_6882: a7f950bbf06a55e6a47934b2891ef595f97165d4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178:
Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations.
On Thu, Sep 12, 2019 at 06:01:57PM +0200, Maarten Lankhorst wrote: > Hey, > > Op 12-09-2019 om 16:34 schreef Sasha Levin: > > Hi, > > > > [This is an automated email] > > > > This commit has been processed because it contains a "Fixes:" tag, > > fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and > > Slice Count for DSC. > > > > The bot has tested the following trees: v5.2.14. > > > > v5.2.14: Failed to apply! Possible dependencies: > > Unable to calculate > > > > > > NOTE: The patch will not be queued to stable trees until it is upstream. > > > > How should we proceed with this patch? > > > > -- > > Thanks, > > Sasha > > Why is this bot asking for patches on the trybot mailing list? Did you forget --suppress-cc=all ? -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915/tgl: Introduce gen12 forcewake ranges
On 9/12/19 6:38 AM, Mika Kuoppala wrote:
From: Michel Thierry
The media ranges extend beyond what gen11 gives so we can't piggypack
on gen11 ranges, even on read side.
Introduce a table for gen12 and accessors for it.
v2: correctly implement gen12_fwtable_write/read (Daniele)
v3: update with ranges from bspec.
v4: avoid GEN11_NEEDS_FORCEWAKE on read size (Mika)
If we think the overhead of the unneeded BSEARCH is not too bad, should
we remove this from the other accessors as well? Having only the gen12
paths behave differently feels inconsistent. We should recoup the cost
later with the display uncore split (if I manage to find time to get
back to it).
BSpec: 18331.
This should be 52078 for TGL.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 75 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..18e8314641a8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -910,6 +910,9 @@ static const struct intel_forcewake_range __vlv_fw_ranges[]
= {
__fwd; \
})
+#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
+ find_fw_domain(uncore, offset)
+
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
@@ -935,6 +938,20 @@ static const i915_reg_t gen11_shadowed_regs[] = {
/* TODO: Other registers are not yet used */
};
+static const i915_reg_t gen12_shadowed_regs[] = {
+ RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
+ GEN6_RPNSWREQ, /* 0xA008 */
+ GEN6_RC_VIDEO_FREQ, /* 0xA00C */
+ RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
+ RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C (base) */
+ RING_TAIL(GEN11_BSD2_RING_BASE),/* 0x1C4000 (base) */
+ RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
+ RING_TAIL(GEN11_BSD3_RING_BASE),/* 0x1D (base) */
+ RING_TAIL(GEN11_BSD4_RING_BASE),/* 0x1D4000 (base) */
+ RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
+ /* TODO: Other registers are not yet used */
+};
+
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
{
u32 offset = i915_mmio_reg_offset(*reg);
@@ -957,6 +974,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
+__is_genX_shadowed(12)
static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1010,6 +1028,15 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
__fwd; \
})
+#define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (!is_gen12_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
@@ -1080,6 +1107,46 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
};
+/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __gen12_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
+ GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
+
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix i915_interrupt_info debugfs with display off on VLV
== Series Details ==
Series: Fix i915_interrupt_info debugfs with display off on VLV
URL : https://patchwork.freedesktop.org/series/66604/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6882 -> Patchwork_14381
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14381:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_create@basic:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-tgl-u/igt@gem_exec_cre...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-tgl-u/igt@gem_exec_cre...@basic.html
* igt@i915_pm_rpm@debugfs-read:
- {fi-tgl-u}: NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-tgl-u/igt@i915_pm_...@debugfs-read.html
- {fi-tgl-u2}:NOTRUN -> [SKIP][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-tgl-u2/igt@i915_pm_...@debugfs-read.html
Known issues
Here are the changes found in Patchwork_14381 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724] /
[fdo#111214])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-icl-u3/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- fi-apl-guc: [DMESG-WARN][7] ([fdo#109385] / [fdo#111652 ]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-apl-guc/igt@gem_exec_gttf...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-apl-guc/igt@gem_exec_gttf...@basic.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][9] ([fdo#106107] / [fdo#106350]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-mmap:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111652 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111652
Participating hosts (55 -> 48)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* IGT: IGT_5178 -> IGTPW_3448
* Linux: CI_DRM_6882 -> Patchwork_14381
CI-20190529: 20190529
CI_DRM_6882: a7f950bbf06a55e6a47934b2891ef595f97165d4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3448: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3448/
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14381: f4047ef7f200512107c549a8115aa828284e9a17 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f4047ef7f200 drm/i915: Get the correct wakeref for reading HOTPLUG_EN et al.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Use GT parked for estimating RC6 while asleep (rev8)
== Series Details ==
Series: drm/i915/pmu: Use GT parked for estimating RC6 while asleep (rev8)
URL : https://patchwork.freedesktop.org/series/56583/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6882 -> Patchwork_14380
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14380:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-tgl-u/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
Known issues
Here are the changes found in Patchwork_14380 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][4] -> [DMESG-WARN][5] ([fdo#107724]) +2
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@gem_flink_ba...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-icl-u3/igt@gem_flink_ba...@basic.html
Possible fixes
* igt@gem_sync@basic-store-each:
- {fi-tgl-u}: [INCOMPLETE][6] ([fdo#111647]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-tgl-u/igt@gem_s...@basic-store-each.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-tgl-u/igt@gem_s...@basic-store-each.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][8] ([fdo#106107] / [fdo#106350]) ->
[PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][10] ([fdo#107718]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-mmap:
- fi-icl-u3: [DMESG-WARN][12] ([fdo#107724]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
Participating hosts (55 -> 48)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6882 -> Patchwork_14380
CI-20190529: 20190529
CI_DRM_6882: a7f950bbf06a55e6a47934b2891ef595f97165d4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14380: 21caec7e01dacf3e25d519ba4ac4986fd43cf93d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
21caec7e01da drm/i915/pmu: Use GT parked for estimating RC6 while asleep
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14380/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
Hi "Jos??, Thank you for the patch! Yet something to improve: [auto build test ERROR on linus/master] [cannot apply to v5.3-rc8 next-20190904] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Jos-Roberto-de-Souza/drm-connector-Share-with-non-atomic-drivers-the-function-to-get-the-single-encoder/20190912-213415 config: x86_64-randconfig-g003-201936 (attached as .config) compiler: gcc-7 (Debian 7.4.0-11) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 If you fix the issue, kindly add following tag Reported-by: kbuild test robot All errors (new ones prefixed by >>): >> ERROR: "drm_connector_get_single_encoder" >> [drivers/gpu/drm/drm_kms_helper.ko] undefined! --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Don't mix srcu tag and negative error codes
While srcu may use an integer tag, it does not exclude potential error
codes and so may overlap with our own use of -EINTR. Use a separate
outparam to store the tag, and report the error code separately. While
changing the function signature allow the caller to choose whether or not
the potential wait may be interrupted.
Fixes: 2caffbf11762 ("drm/i915: Revoke mmaps and prevent access to fence
registers across reset")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
Drop state parameters, the potential user evaporated.
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/intel_reset.c| 8 +++-
drivers/gpu/drm/i915/gt/intel_reset.h| 2 +-
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 82db2b783123..1748e63156a2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -245,11 +245,9 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
wakeref = intel_runtime_pm_get(rpm);
- srcu = intel_gt_reset_trylock(ggtt->vm.gt);
- if (srcu < 0) {
- ret = srcu;
+ ret = intel_gt_reset_trylock(ggtt->vm.gt, );
+ if (ret)
goto err_rpm;
- }
ret = i915_mutex_lock_interruptible(dev);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 296bbc7745fb..8327220ac558 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1214,10 +1214,8 @@ void intel_gt_handle_error(struct intel_gt *gt,
intel_runtime_pm_put(>i915->runtime_pm, wakeref);
}
-int intel_gt_reset_trylock(struct intel_gt *gt)
+int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
{
- int srcu;
-
might_lock(>reset.backoff_srcu);
might_sleep();
@@ -1232,10 +1230,10 @@ int intel_gt_reset_trylock(struct intel_gt *gt)
rcu_read_lock();
}
- srcu = srcu_read_lock(>reset.backoff_srcu);
+ *srcu = srcu_read_lock(>reset.backoff_srcu);
rcu_read_unlock();
- return srcu;
+ return 0;
}
void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
b/drivers/gpu/drm/i915/gt/intel_reset.h
index 37a987b17108..52c00199e069 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -38,7 +38,7 @@ int intel_engine_reset(struct intel_engine_cs *engine,
void __i915_request_reset(struct i915_request *rq, bool guilty);
-int __must_check intel_gt_reset_trylock(struct intel_gt *gt);
+int __must_check intel_gt_reset_trylock(struct intel_gt *gt, int *srcu);
void intel_gt_reset_unlock(struct intel_gt *gt, int tag);
void intel_gt_set_wedged(struct intel_gt *gt);
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations.
Hey, Op 12-09-2019 om 16:34 schreef Sasha Levin: > Hi, > > [This is an automated email] > > This commit has been processed because it contains a "Fixes:" tag, > fixing commit: d9218c8f6cf4 drm/i915/dp: Add helpers for Compressed BPP and > Slice Count for DSC. > > The bot has tested the following trees: v5.2.14. > > v5.2.14: Failed to apply! Possible dependencies: > Unable to calculate > > > NOTE: The patch will not be queued to stable trees until it is upstream. > > How should we proceed with this patch? > > -- > Thanks, > Sasha Why is this bot asking for patches on the trybot mailing list? ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2)
== Series Details == Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2) URL : https://patchwork.freedesktop.org/series/66537/ State : success == Summary == CI Bug Log - changes from CI_DRM_6875_full -> Patchwork_14374_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14374_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl5/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-apl5/igt@gem_...@unwedge-stress.html * igt@gem_exec_schedule@in-order-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +13 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@gem_exec_sched...@in-order-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb6/igt@gem_exec_sched...@in-order-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl3/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-apl2/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103166]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-x.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([fdo#106885]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl1/igt@kms_plane_multi...@atomic-pipe-a-tiling-yf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-skl7/igt@kms_plane_multi...@atomic-pipe-a-tiling-yf.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [DMESG-WARN][17] ([fdo#108566]) -> [PASS][18] +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_eio@reset-stress: - shard-glk: [FAIL][19] ([fdo#109661]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-glk3/igt@gem_...@reset-stress.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-glk3/igt@gem_...@reset-stress.html * igt@gem_exec_schedule@fifo-bsd: - shard-iclb: [SKIP][21] ([fdo#111325]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@gem_exec_sched...@fifo-bsd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb6/igt@gem_exec_sched...@fifo-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [SKIP][23] ([fdo#109276]) -> [PASS][24] +11 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@kms_atomic_transition@2x-modeset-transitions: - shard-hsw:
Re: [Intel-gfx] [PATCH v7 04/11] drm: revocation check at drm subsystem
On 2019-09-12 2:54 a.m., Ramalingam C wrote: > On 2019-09-12 at 00:15:32 +, Harry Wentland wrote: >> Adding a couple AMD guys. >> >> I know this is already merged but I have a few questions after some >> internal discussions. >> >> On 2019-05-07 12:27 p.m., Ramalingam C wrote: >>> On every hdcp revocation check request SRM is read from fw file >>> /lib/firmware/display_hdcp_srm.bin >>> >> >> According to section 5 of the HDCP 2.3 spec [1] a device compliant with >> HDCP 2.0 and higher must be capable of storing and updating the SRM in >> non-volatile memory. Section 5.2 describes how this SRM needs to be >> updated when a new version is served alongside protected content. >> >> Isn't /lib/firmware intended for static firmware making updates to the >> folder problematic for anyone but the system's package maintainer? I've >> heard /lib might even be treated as read-only in certain environments. >> This would mean it'd be impossible to support HDCP 2.x on those systems. >> >> Wouldn't it be easier to provide a sysfs entry for SRM that allows >> userspace (e.g. system startup/shutdown scripts) to (a) retrieve the SRM >> from the HDCP implementation for non-volatile storage and (b) to pass >> the SRM to the HDCP implementation for revocation checking? > > This uAPI is decided considering below points: > > userspace will handle the non-volatile storage of the SRM table and it's > upgrade > with latest versions received from content providers etc. > > Prior to any HDCP auth request userspace will write the latest SRM into > the /lib/firmware. > > And regarding the interface, binary sysfs based implementation [1] was > opposed by Greg KH. > And after the discussion on different alternate i/fs [2] request > firmware is choosen. > > [1]. https://patchwork.freedesktop.org/patch/296442/?series=57232=5uAPI > [2]. https://patchwork.freedesktop.org/patch/296439/?series=57232=5 > > I hope this addresses the questions above. > Interesting discussion. Thanks for sharing. It sounds like Greg's main concern was with the fact that DRM parses the binary. In our case we'll need to pass the blob to FW without touching it. A device sysfs sounds like a better use-case for that. On the other hand certain people are interested to have a non-FW approach to content protection for which your approach seems to work best. I still don't know how this solution can get HDCP 2.x certified. I was under the impression HDCP 2.x required a protected execution environment with stricter requirements than x86 kernel space can provide. Harry > -Ram > > >> >> [1] >> https://www.digital-cp.com/sites/default/files/HDCP%20on%20HDMI%20Specification%20Rev2_3.pdf >> >> Thanks, >> Harry >> >>> SRM table is parsed and stored at drm_hdcp.c, with functions exported >>> for the services for revocation check from drivers (which >>> implements the HDCP authentication) >>> >>> This patch handles the HDCP1.4 and 2.2 versions of SRM table. >>> >>> v2: >>> moved the uAPI to request_firmware_direct() [Daniel] >>> v3: >>> kdoc added. [Daniel] >>> srm_header unified and bit field definitions are removed. [Daniel] >>> locking improved. [Daniel] >>> vrl length violation is fixed. [Daniel] >>> v4: >>> s/__swab16/be16_to_cpu [Daniel] >>> be24_to_cpu is done through a global func [Daniel] >>> Unused variables are removed. [Daniel] >>> unchecked return values are dropped from static funcs [Daniel] >>> >>> Signed-off-by: Ramalingam C >>> Acked-by: Satyeshwar Singh >>> Reviewed-by: Daniel Vetter >>> --- >>> Documentation/gpu/drm-kms-helpers.rst | 6 + >>> drivers/gpu/drm/Makefile | 2 +- >>> drivers/gpu/drm/drm_hdcp.c| 333 ++ >>> drivers/gpu/drm/drm_internal.h| 4 + >>> drivers/gpu/drm/drm_sysfs.c | 2 + >>> include/drm/drm_hdcp.h| 24 ++ >>> 6 files changed, 370 insertions(+), 1 deletion(-) >>> create mode 100644 drivers/gpu/drm/drm_hdcp.c >>> >>> diff --git a/Documentation/gpu/drm-kms-helpers.rst >>> b/Documentation/gpu/drm-kms-helpers.rst >>> index 14102ae035dc..0fe726a6ee67 100644 >>> --- a/Documentation/gpu/drm-kms-helpers.rst >>> +++ b/Documentation/gpu/drm-kms-helpers.rst >>> @@ -181,6 +181,12 @@ Panel Helper Reference >>> .. kernel-doc:: drivers/gpu/drm/drm_panel_orientation_quirks.c >>> :export: >>> >>> +HDCP Helper Functions Reference >>> +=== >>> + >>> +.. kernel-doc:: drivers/gpu/drm/drm_hdcp.c >>> + :export: >>> + >>> Display Port Helper Functions Reference >>> === >>> >>> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile >>> index 72f5036d9bfa..dd02e9dec810 100644 >>> --- a/drivers/gpu/drm/Makefile >>> +++ b/drivers/gpu/drm/Makefile >>> @@ -17,7 +17,7 @@ drm-y :=drm_auth.o drm_cache.o \ >>> drm_plane.o drm_color_mgmt.o drm_print.o \ >>> drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \ >>>
Re: [Intel-gfx] [PATCH 2/4] drm/i915/tgl: s/ss/eu fuse reading support
On 12/09/2019 16:35, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-12 16:18:08)
On 12/09/2019 14:38, Mika Kuoppala wrote:
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 469dc512cca3..30c542144016 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2033,8 +2033,10 @@ struct drm_i915_query {
* (data[X / 8] >> (X % 8)) & 1
*
* - the subslice mask for each slice with one bit per subslice telling
- * whether a subslice is available. The availability of subslice Y in slice
- * X can be queried with the following formula :
+ * whether a subslice is available. Gen12 has dual-subslices, which are
+ * similar to two gen11 subslices. For gen12, this array represents dual-
It's ugly in user facing documentation if we cannot decide whether it is
Gen12 or gen12. Gen12 special case also probably warrants to be in its
own paragraph.
Here it was using sentence capitalisation, which suits it if we are
treating it as an ordinary noun. If went with a proper noun, then Gen12
throughout. I might be wrong, but my impression is that we've
historically used ordinary nouns (gen5-8, gen11, etc).
My bad.
Regards,
Tvrtko
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Keep the engine awake while we keep for preemption
== Series Details ==
Series: drm/i915/selftests: Keep the engine awake while we keep for preemption
URL : https://patchwork.freedesktop.org/series/66601/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6881 -> Patchwork_14379
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/
Known issues
Here are the changes found in Patchwork_14379 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- {fi-icl-guc}: [INCOMPLETE][3] ([fdo#107713] / [fdo#111381]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111407]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/fi-icl-u3/igt@prime_v...@basic-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (55 -> 48)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6881 -> Patchwork_14379
CI-20190529: 20190529
CI_DRM_6881: 286c68100c5d35297c759db87c9f4d8604365fa0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14379: 1e14a32622c879f7d26c45a3a4f40711cc5c6b5c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1e14a32622c8 drm/i915/selftests: Keep the engine awake while we keep for
preemption
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14379/
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/tgl: s/ss/eu fuse reading support
Quoting Tvrtko Ursulin (2019-09-12 16:18:08)
>
> On 12/09/2019 14:38, Mika Kuoppala wrote:
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 469dc512cca3..30c542144016 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -2033,8 +2033,10 @@ struct drm_i915_query {
> >* (data[X / 8] >> (X % 8)) & 1
> >*
> >* - the subslice mask for each slice with one bit per subslice telling
> > - * whether a subslice is available. The availability of subslice Y in
> > slice
> > - * X can be queried with the following formula :
> > + * whether a subslice is available. Gen12 has dual-subslices, which are
> > + * similar to two gen11 subslices. For gen12, this array represents dual-
>
> It's ugly in user facing documentation if we cannot decide whether it is
> Gen12 or gen12. Gen12 special case also probably warrants to be in its
> own paragraph.
Here it was using sentence capitalisation, which suits it if we are
treating it as an ordinary noun. If went with a proper noun, then Gen12
throughout. I might be wrong, but my impression is that we've
historically used ordinary nouns (gen5-8, gen11, etc).
-Chris
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[Intel-gfx] [CI RESEND] drm/i915: introduce INTEL_DISPLAY_ENABLED()
Prepare for making a distinction between not having display and having
disabled display. Add INTEL_DISPLAY_ENABLED() and use it where
HAS_DISPLAY() is used. This is initially duplication, as disabling
display still leads to ->pipe_mask = 0 and HAS_DISPLAY() being false.
Since INTEL_DISPLAY_ENABLED() will not make sense unless HAS_DISPLAY()
is true, include a warning for catching misuses making decisions on
INTEL_DISPLAY_ENABLED() when HAS_DISPLAY() is false.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
Acked-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c| 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_pch.c | 2 +-
7 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index efb39f350b19..1def550c68c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1833,7 +1833,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
const struct bdb_header *bdb;
u8 __iomem *bios = NULL;
- if (!HAS_DISPLAY(dev_priv)) {
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) {
DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a19f8c73f2e0..2c0cb32235c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15366,7 +15366,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_pps_init(dev_priv);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
if (INTEL_GEN(dev_priv) >= 12) {
@@ -17273,7 +17273,7 @@ intel_display_capture_error_state(struct
drm_i915_private *dev_priv)
BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index d59eee5c5d9c..68338669f054 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -444,7 +444,7 @@ int intel_fbdev_init(struct drm_device *dev)
struct intel_fbdev *ifbdev;
int ret;
- if (WARN_ON(!HAS_DISPLAY(dev_priv)))
+ if (WARN_ON(!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)))
return -ENODEV;
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index d6775a005726..3d4d19ac1d14 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -836,7 +836,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
unsigned int pin;
int ret;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0dfcb40f3162..9904f762f4bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -338,7 +338,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
- if (HAS_DISPLAY(dev_priv)) {
+ if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
ret = drm_vblank_init(_priv->drm,
INTEL_NUM_PIPES(dev_priv));
if (ret)
@@ -389,7 +389,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
intel_overlay_setup(dev_priv);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return 0;
ret = intel_fbdev_init(dev);
@@ -1378,7 +1378,7 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
} else
DRM_ERROR("Failed to register driver for userspace access!\n");
- if (HAS_DISPLAY(dev_priv)) {
+ if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
/* Must be done after probing outputs */
Re: [Intel-gfx] [CI RESEND] drm/i915: convert device info num_pipes to pipe_mask
On Wed, 11 Sep 2019, Jani Nikula wrote:
> Replace device info number of pipes with a bit mask of available
> pipes. This will prove handy in the future. There's still a bunch of
> future work to do to actually allow a non-consecutive mask of pipes, but
> it's a start. No functional changes.
>
> Cc: Chris Wilson
> Cc: José Roberto de Souza
> Cc: Ville Syrjälä
> Reviewed-by: José Roberto de Souza
> Acked-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
And pushed, thanks for the review, on to the next one...
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c | 24
> drivers/gpu/drm/i915/intel_device_info.c | 10 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 4 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 84fb0245cf62..bf600888b3f1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2188,9 +2188,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define GT_FREQUENCY_MULTIPLIER 50
> #define GEN9_FREQ_SCALER 3
>
> -#define INTEL_NUM_PIPES(dev_priv) (INTEL_INFO(dev_priv)->num_pipes)
> +#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
>
> -#define HAS_DISPLAY(dev_priv) (INTEL_NUM_PIPES(dev_priv) > 0)
> +#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
>
> static inline bool intel_vtd_active(void)
> {
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b3cc8560696b..698116276441 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -147,7 +147,7 @@
> #define I830_FEATURES \
> GEN(2), \
> .is_mobile = 1, \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_overlay = 1, \
> .display.cursor_needs_physical = 1, \
> .display.overlay_needs_physical = 1, \
> @@ -165,7 +165,7 @@
>
> #define I845_FEATURES \
> GEN(2), \
> - .num_pipes = 1, \
> + .pipe_mask = BIT(PIPE_A), \
> .display.has_overlay = 1, \
> .display.overlay_needs_physical = 1, \
> .display.has_gmch = 1, \
> @@ -203,7 +203,7 @@ static const struct intel_device_info intel_i865g_info = {
>
> #define GEN3_FEATURES \
> GEN(3), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .engine_mask = BIT(RCS0), \
> @@ -287,7 +287,7 @@ static const struct intel_device_info
> intel_pineview_m_info = {
>
> #define GEN4_FEATURES \
> GEN(4), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> @@ -337,7 +337,7 @@ static const struct intel_device_info intel_gm45_info = {
>
> #define GEN5_FEATURES \
> GEN(5), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_snoop = true, \
> @@ -363,7 +363,7 @@ static const struct intel_device_info
> intel_ironlake_m_info = {
>
> #define GEN6_FEATURES \
> GEN(6), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -411,7 +411,7 @@ static const struct intel_device_info
> intel_sandybridge_m_gt2_info = {
>
> #define GEN7_FEATURES \
> GEN(7), \
> - .num_pipes = 3, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -462,7 +462,7 @@ static const struct intel_device_info
> intel_ivybridge_q_info = {
> GEN7_FEATURES,
> PLATFORM(INTEL_IVYBRIDGE),
> .gt = 2,
> - .num_pipes = 0, /* legal, last one wins */
> + .pipe_mask = 0, /* legal, last one wins */
> .has_l3_dpf = 1,
> };
>
> @@ -470,7 +470,7 @@ static const struct intel_device_info
> intel_valleyview_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> .is_lp = 1,
> - .num_pipes = 2,
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> .has_rps = true,
> @@ -560,7 +560,7 @@ static const struct intel_device_info
> intel_broadwell_gt3_info = {
> static const struct intel_device_info intel_cherryview_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> - .num_pipes = 3,
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> .display.has_hotplug = 1,
> .is_lp = 1,
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> @@
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Support for DP HDR outputs (rev7)
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev7)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6881 -> Patchwork_14378
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14378:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_hugepages:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-tgl-u/igt@i915_selftest@live_hugepages.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/fi-tgl-u/igt@i915_selftest@live_hugepages.html
Known issues
Here are the changes found in Patchwork_14378 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-blb-e6850/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713] / [fdo#111381]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/fi-icl-u3/igt@prime_v...@basic-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (55 -> 47)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ivb-3770 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6881 -> Patchwork_14378
CI-20190529: 20190529
CI_DRM_6881: 286c68100c5d35297c759db87c9f4d8604365fa0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14378: dc6319620af21e019e5ba6a4339377bf6a3c4188 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dc6319620af2 drm/i915/dp: Attach HDR metadata property to DP connector
01c4f85366ea drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static
Metadata
bfe7bebb71ff drm/i915: Add new GMP register size for GEN11
1f97326edf73 drm/i915/dp: Attach colorspace property
957fde635591 drm: Add DisplayPort colorspace property
21b7ae259887 drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA
8a72a1bab7d6 drm/i915/dp: Extend program of VSC Header and DB for Colorimetry
Format
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14378/
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915/tgl: s/ss/eu fuse reading support
On 12/09/2019 14:38, Mika Kuoppala wrote:
From: Daniele Ceraolo Spurio
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly representative of hardware resources, present userspace
with a subslice_mask made up of DSS bits instead.
Bspec: 29547
Bspec: 12247
Cc: Kelvin Gardiner
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
CC: Radhakrishna Sripada
Cc: Michel Thierry #v1
Cc: Daniele Ceraolo Spurio
Cc: José Roberto de Souza
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: James Ausmus
Signed-off-by: Oscar Mateo
Signed-off-by: Sudeep Dutt
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 87 ++--
include/uapi/drm/i915_drm.h | 6 +-
5 files changed, 76 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4070f6ff1db6..d1d225204f09 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -18,12 +18,13 @@ struct drm_i915_private;
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS(10) /* HSW upper bound */
+#define GEN_MAX_EUS(16) /* TGL upper bound */
#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
+ u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -40,12 +41,6 @@ struct sseu_dev_info {
u8 ss_stride;
u8 eu_stride;
-
- /* We don't have more than 8 eus per subslice at the moment and as we
-* store eus enabled using bits, no need to multiply by eus per
-* subslice.
-*/
- u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
Comment indeed looks obsolete even with old GEM_MAX_EUS.
Howewer more importantly, was the code broken before? Now we size
considering the stride, but before GEN_MAX_EU_STRIDE was
GEN_SSEU_STRIDE(GEN_MAX_EUS) = DIV_ROUND_UP(10, BITS_PER_BYTE) = 2, no?
So wasn't the array too small?
P.S. Moving the position of the field is just noise?
};
/*
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..f2b92be44adf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3820,7 +3820,8 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ if (info->sseu.has_subslice_pg &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..47847135a11f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index d9b5baaef5d0..792ca3202073 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,13 +182,73 @@ static u16 compute_eu_total(const struct sseu_dev_info
*sseu)
return total;
}
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
+ u8 s_en, u32 ss_en, u16 eu_en)
+{
+ int s, ss;
+
+ /* ss_en represents entire subslice mask across all slices */
+ if (sseu->max_slices * sseu->max_subslices >
+ sizeof(ss_en) * BITS_PER_BYTE) {
+ DRM_ERROR("Invalid topology, max_slices: %d, max_subslices
%d\n",
+ sseu->max_slices, sseu->max_subslices);
+ return;
+ }
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if ((s_en & BIT(s)) == 0)
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: convert device info num_pipes to pipe_mask (rev2)
== Series Details == Series: drm/i915: convert device info num_pipes to pipe_mask (rev2) URL : https://patchwork.freedesktop.org/series/66567/ State : success == Summary == CI Bug Log - changes from CI_DRM_6875_full -> Patchwork_14372_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14372_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@in-order-bsd2: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +15 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@gem_exec_sched...@in-order-bsd2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-iclb7/igt@gem_exec_sched...@in-order-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#104873]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-glk5/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-glk5/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#111609]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-glk1/igt@kms_f...@dpms-vs-vblank-race-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-glk8/igt@kms_f...@dpms-vs-vblank-race-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#109507]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl1/igt@kms_f...@flip-vs-suspend-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-skl2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@modeset-vs-vblank-race: - shard-apl: [PASS][11] -> [FAIL][12] ([fdo#111609]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl1/igt@kms_f...@modeset-vs-vblank-race.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-apl6/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] / [fdo#110042]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-iclb7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-skl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14372/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@perf@polling: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#110728]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6875/shard-skl2/igt@p...@polling.html [24]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Show the logical context ring state on dumping (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Show the logical context ring
state on dumping (rev2)
URL : https://patchwork.freedesktop.org/series/66422/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6881 -> Patchwork_14377
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14377 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14377, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14377:
### IGT changes ###
Possible regressions
* igt@gem_exec_suspend@basic:
- fi-icl-u3: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u3/igt@gem_exec_susp...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-icl-u3/igt@gem_exec_susp...@basic.html
New tests
-
New tests have been introduced between CI_DRM_6881 and Patchwork_14377:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_lrc:
- Statuses : 40 pass(s)
- Exec time: [0.40, 2.08] s
Known issues
Here are the changes found in Patchwork_14377 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-close:
- fi-skl-6770hq: [PASS][3] -> [DMESG-WARN][4] ([fdo#105541])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-skl-6770hq/igt@gem_ba...@create-close.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-skl-6770hq/igt@gem_ba...@create-close.html
* igt@gem_close_race@basic-threads:
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u2/igt@gem_close_r...@basic-threads.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-icl-u2/igt@gem_close_r...@basic-threads.html
* igt@gem_ctx_switch@legacy-render:
- fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927] /
[fdo#111381])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-apl-guc/igt@gem_ctx_swi...@legacy-render.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-apl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: [PASS][9] -> [DMESG-WARN][10] ([fdo#105128] /
[fdo#107139])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [PASS][11] -> [DMESG-WARN][12] ([fdo#107724])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][13] -> [DMESG-WARN][14] ([fdo#106387]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- {fi-icl-guc}: [INCOMPLETE][15] ([fdo#107713] / [fdo#111381]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6881/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14377/fi-icl-u3/igt@prime_v...@basic-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105128]:
Re: [Intel-gfx] [PATCH] Revert "drm/i915/userptr: Acquire the page lock around set_page_dirty()"
On 12/09/2019 13:56, Chris Wilson wrote:
The userptr put_pages can be called from inside try_to_unmap, and so
enters with the page lock held on one of the object's backing pages. We
cannot take the page lock ourselves for fear of recursion.
Reported-by: Lionel Landwerlin
Reported-by: Martin Wilck
Reported-by: Leo Kraav
Fixes: aa56a292ce62 ("drm/i915/userptr: Acquire the page lock around
set_page_dirty()")
References: https://bugzilla.kernel.org/show_bug.cgi?id=203317
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 74da35611d7c..11b231c187c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -672,15 +672,7 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj,
for_each_sgt_page(page, sgt_iter, pages) {
if (obj->mm.dirty)
- /*
-* As this may not be anonymous memory (e.g. shmem)
-* but exist on a real mapping, we have to lock
-* the page in order to dirty it -- holding
-* the page reference is not sufficient to
-* prevent the inode from being truncated.
-* Play safe and take the lock.
-*/
- set_page_dirty_lock(page);
+ set_page_dirty(page);
mark_page_accessed(page);
put_page(page);
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Show the logical context ring state on dumping (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping (rev2) URL : https://patchwork.freedesktop.org/series/66422/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4abf44a40a29 drm/i915: Show the logical context ring state on dumping bb73c5536563 drm/i915/selftests: Verify the LRC register layout between init and HW -:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #60: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:473: +#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) -:61: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #61: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:474: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:474: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) total: 1 errors, 0 warnings, 2 checks, 1087 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Disable preemption while being debugged
Chris Wilson writes:
> We see failures where the context continues executing past a
> preemption event, eventually leading to situations where a request has
> executed before we have event submitted it to HW! It seems like tgl is
> ignoring our RING_TAIL updates, but more likely is that there is a
> missing update required for our semaphore waits around preemption.
>
> v2: And disable internal semaphore usage
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 47d766ccea71..a3f0e4999744 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2939,6 +2939,9 @@ void intel_execlists_set_default_submission(struct
> intel_engine_cs *engine)
> engine->flags |= I915_ENGINE_HAS_PREEMPTION;
> }
>
> + if (INTEL_GEN(engine->i915) >= 12) /* XXX disabled for debugging */
> + engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES;
> +
> if (engine->class != COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) >= 12)
> engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
> }
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b3cc8560696b..2ca34a5cf7d3 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -798,6 +798,7 @@ static const struct intel_device_info
> intel_tigerlake_12_info = {
> .engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .has_rc6 = false, /* XXX disabled for debugging */
> + .has_logical_ring_preemption = false, /* XXX disabled for debugging */
> };
>
> #undef GEN
> --
> 2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 09/10] drm/i915/dsb: Enable DSB for gen12.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..1fd2a364891a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,7 +787,8 @@ static const struct intel_device_info
intel_elkhartlake_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- .has_global_mocs = 1
+ .has_global_mocs = 1, \
+ .display.has_dsb = 1
Looks good to me, feel free to use:
Reviewed-by: Shashank Sharma
- Shashank
static const struct intel_device_info intel_tigerlake_12_info = {
GEN12_FEATURES,
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 07/10] drm/i915/dsb: function to trigger workload execution of DSB.
On 9/12/2019 7:09 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2b0ffc0afb74..eea86afb0583 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -212,3 +212,45 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tail;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(>cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ dsb->free_pos = 0;
+ intel_dsb_disable_engine(dsb);
I am still not very convince if a commit function should be void, I
would still want it to return success or failure, so that we would know
if the last operation was successful or not.
I would wait Jani N to comment here, on what he feels about this.
The question becomes, what do you *do* with the return value? If none of
the callers are going to use it, don't return it.
I was thinking we should check the return value of the DSB commit (if
not writes), so that we would be aware that the register programming
failed, and later even can think about a fallback method. Too ambitious ?
- Shashank
BR,
Jani.
- Shashank
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 9b2522f20bfb..7389c8c5b665 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -43,5 +43,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dbaa49f5c74..c77b5066d8dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11687,6 +11687,8 @@ enum skl_power_gate {
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
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[Intel-gfx] [PATCH 2/4] drm/i915/tgl: s/ss/eu fuse reading support
From: Daniele Ceraolo Spurio
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly representative of hardware resources, present userspace
with a subslice_mask made up of DSS bits instead.
v2: GEM_BUG_ON on mask size (Lionel)
Bspec: 29547
Bspec: 12247
Cc: Kelvin Gardiner
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
CC: Radhakrishna Sripada
Cc: Michel Thierry #v1
Cc: Daniele Ceraolo Spurio
Cc: José Roberto de Souza
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: James Ausmus
Signed-off-by: Oscar Mateo
Signed-off-by: Sudeep Dutt
Signed-off-by: Stuart Summers
Signed-off-by: Mika Kuoppala
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 83 ++--
include/uapi/drm/i915_drm.h | 6 +-
5 files changed, 72 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4070f6ff1db6..d1d225204f09 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -18,12 +18,13 @@ struct drm_i915_private;
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS(10) /* HSW upper bound */
+#define GEN_MAX_EUS(16) /* TGL upper bound */
#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
+ u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -40,12 +41,6 @@ struct sseu_dev_info {
u8 ss_stride;
u8 eu_stride;
-
- /* We don't have more than 8 eus per subslice at the moment and as we
-* store eus enabled using bits, no need to multiply by eus per
-* subslice.
-*/
- u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
};
/*
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..f2b92be44adf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3820,7 +3820,8 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ if (info->sseu.has_subslice_pg &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..47847135a11f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index d9b5baaef5d0..8516731985eb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,13 +182,69 @@ static u16 compute_eu_total(const struct sseu_dev_info
*sseu)
return total;
}
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
+ u8 s_en, u32 ss_en, u16 eu_en)
+{
+ int s, ss;
+
+ /* ss_en represents entire subslice mask across all slices */
+ GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
+ sizeof(ss_en) * BITS_PER_BYTE);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if ((s_en & BIT(s)) == 0)
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+
+ intel_sseu_set_subslices(sseu, s, ss_en);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
+ sseu_set_eus(sseu, s, ss, eu_en);
+ }
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+ u8
Re: [Intel-gfx] [PATCH 2/4] drm/i915/tgl: s/ss/eu fuse reading support
On 12/09/2019 16:38, Mika Kuoppala wrote:
From: Daniele Ceraolo Spurio
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly representative of hardware resources, present userspace
with a subslice_mask made up of DSS bits instead.
Bspec: 29547
Bspec: 12247
Cc: Kelvin Gardiner
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
CC: Radhakrishna Sripada
Cc: Michel Thierry #v1
Cc: Daniele Ceraolo Spurio
Cc: José Roberto de Souza
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: James Ausmus
Signed-off-by: Oscar Mateo
Signed-off-by: Sudeep Dutt
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 87 ++--
include/uapi/drm/i915_drm.h | 6 +-
5 files changed, 76 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4070f6ff1db6..d1d225204f09 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -18,12 +18,13 @@ struct drm_i915_private;
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS(10) /* HSW upper bound */
+#define GEN_MAX_EUS(16) /* TGL upper bound */
#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
+ u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -40,12 +41,6 @@ struct sseu_dev_info {
u8 ss_stride;
u8 eu_stride;
-
- /* We don't have more than 8 eus per subslice at the moment and as we
-* store eus enabled using bits, no need to multiply by eus per
-* subslice.
-*/
- u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
};
/*
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..f2b92be44adf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3820,7 +3820,8 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ if (info->sseu.has_subslice_pg &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..47847135a11f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index d9b5baaef5d0..792ca3202073 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,13 +182,73 @@ static u16 compute_eu_total(const struct sseu_dev_info
*sseu)
return total;
}
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
+ u8 s_en, u32 ss_en, u16 eu_en)
+{
+ int s, ss;
+
+ /* ss_en represents entire subslice mask across all slices */
+ if (sseu->max_slices * sseu->max_subslices >
+ sizeof(ss_en) * BITS_PER_BYTE) {
+ DRM_ERROR("Invalid topology, max_slices: %d, max_subslices
%d\n",
+ sseu->max_slices, sseu->max_subslices);
Don't you want a GEM_BUG_ON() here to match the rest of the code?
Seems like a driver bug if we reach that case.
Otherwise :
Acked-by: Lionel Landwerlin
Cheers,
-Lionel
+ return;
+ }
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if ((s_en & BIT(s)) == 0)
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+
+ intel_sseu_set_subslices(sseu, s, ss_en);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
+
Re: [Intel-gfx] [PATCH v6 07/10] drm/i915/dsb: function to trigger workload execution of DSB.
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
> On 9/12/2019 12:41 AM, Animesh Manna wrote:
>> Batch buffer will be created through dsb-reg-write function which can have
>> single/multiple request based on usecase and once the buffer is ready
>> commit function will trigger the execution of the batch buffer. All
>> the registers will be updated simultaneously.
>>
>> v1: Initial version.
>> v2: Optimized code few places. (Chris)
>> v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
>>
>> Cc: Imre Deak
>> Cc: Jani Nikula
>> Cc: Rodrigo Vivi
>> Cc: Shashank Sharma
>> Signed-off-by: Animesh Manna
>> ---
>> drivers/gpu/drm/i915/display/intel_dsb.c | 42
>> drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> 3 files changed, 45 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
>> b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index 2b0ffc0afb74..eea86afb0583 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -212,3 +212,45 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
>> i915_reg_t reg, u32 val)
>> (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
>> i915_mmio_reg_offset(reg);
>> }
>> +
>> +void intel_dsb_commit(struct intel_dsb *dsb)
>> +{
>> +struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> +struct drm_device *dev = crtc->base.dev;
>> +struct drm_i915_private *dev_priv = to_i915(dev);
>> +enum pipe pipe = crtc->pipe;
>> +u32 tail;
>> +
>> +if (!dsb->free_pos)
>> +return;
>> +
>> +if (!intel_dsb_enable_engine(dsb))
>> +goto reset;
>> +
>> +if (is_dsb_busy(dsb)) {
>> +DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
>> +goto reset;
>> +}
>> +I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
>> +
>> +tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
>> +if (tail > dsb->free_pos * 4)
>> +memset(>cmd_buf[dsb->free_pos], 0,
>> + (tail - dsb->free_pos * 4));
>> +
>> +if (is_dsb_busy(dsb)) {
>> +DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
>> +goto reset;
>> +}
>> +DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
>> + i915_ggtt_offset(dsb->vma), tail);
>> +I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
>> +if (wait_for(!is_dsb_busy(dsb), 1)) {
>> +DRM_ERROR("Timed out waiting for DSB workload completion.\n");
>> +goto reset;
>> +}
>> +
>> +reset:
>> +dsb->free_pos = 0;
>> +intel_dsb_disable_engine(dsb);
>
> I am still not very convince if a commit function should be void, I
> would still want it to return success or failure, so that we would know
> if the last operation was successful or not.
>
> I would wait Jani N to comment here, on what he feels about this.
The question becomes, what do you *do* with the return value? If none of
the callers are going to use it, don't return it.
BR,
Jani.
>
> - Shashank
>
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
>> b/drivers/gpu/drm/i915/display/intel_dsb.h
>> index 9b2522f20bfb..7389c8c5b665 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -43,5 +43,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
>> void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>> u32 val);
>> +void intel_dsb_commit(struct intel_dsb *dsb);
>>
>> #endif
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 2dbaa49f5c74..c77b5066d8dd 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -11687,6 +11687,8 @@ enum skl_power_gate {
>> #define _DSBSL_INSTANCE_BASE 0x70B00
>> #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
>> (pipe) * 0x1000 + (id) * 100)
>> +#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
>> +#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
>> #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
>> #define DSB_ENABLE (1 << 31)
>> #define DSB_STATUS (1 << 0)
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH 1/4] drm/i915/tgl: Introduce gen12 forcewake ranges
From: Michel Thierry
The media ranges extend beyond what gen11 gives so we can't piggypack
on gen11 ranges, even on read side.
Introduce a table for gen12 and accessors for it.
v2: correctly implement gen12_fwtable_write/read (Daniele)
v3: update with ranges from bspec.
v4: avoid GEN11_NEEDS_FORCEWAKE on read size (Mika)
BSpec: 18331.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 75 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..18e8314641a8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -910,6 +910,9 @@ static const struct intel_forcewake_range __vlv_fw_ranges[]
= {
__fwd; \
})
+#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
+ find_fw_domain(uncore, offset)
+
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
@@ -935,6 +938,20 @@ static const i915_reg_t gen11_shadowed_regs[] = {
/* TODO: Other registers are not yet used */
};
+static const i915_reg_t gen12_shadowed_regs[] = {
+ RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
+ GEN6_RPNSWREQ, /* 0xA008 */
+ GEN6_RC_VIDEO_FREQ, /* 0xA00C */
+ RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
+ RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C (base) */
+ RING_TAIL(GEN11_BSD2_RING_BASE),/* 0x1C4000 (base) */
+ RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
+ RING_TAIL(GEN11_BSD3_RING_BASE),/* 0x1D (base) */
+ RING_TAIL(GEN11_BSD4_RING_BASE),/* 0x1D4000 (base) */
+ RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
+ /* TODO: Other registers are not yet used */
+};
+
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
{
u32 offset = i915_mmio_reg_offset(*reg);
@@ -957,6 +974,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
+__is_genX_shadowed(12)
static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1010,6 +1028,15 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
__fwd; \
})
+#define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (!is_gen12_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
@@ -1080,6 +1107,46 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
};
+/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __gen12_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
+ GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
+
[Intel-gfx] [PATCH 3/4] drm/i915/tgl: Re-enable rc6
We think that we got rc6 problems sorted out. Flip the switch
and let CI expose our tendency to naive optimism.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..fbe98a2db88e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -797,7 +797,6 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.display.has_modular_fia = 1,
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
- .has_rc6 = false, /* XXX disabled for debugging */
};
#undef GEN
--
2.17.1
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[Intel-gfx] [PATCH 2/4] drm/i915/tgl: s/ss/eu fuse reading support
From: Daniele Ceraolo Spurio
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly representative of hardware resources, present userspace
with a subslice_mask made up of DSS bits instead.
Bspec: 29547
Bspec: 12247
Cc: Kelvin Gardiner
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
CC: Radhakrishna Sripada
Cc: Michel Thierry #v1
Cc: Daniele Ceraolo Spurio
Cc: José Roberto de Souza
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: James Ausmus
Signed-off-by: Oscar Mateo
Signed-off-by: Sudeep Dutt
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 87 ++--
include/uapi/drm/i915_drm.h | 6 +-
5 files changed, 76 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4070f6ff1db6..d1d225204f09 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -18,12 +18,13 @@ struct drm_i915_private;
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS(10) /* HSW upper bound */
+#define GEN_MAX_EUS(16) /* TGL upper bound */
#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
+ u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -40,12 +41,6 @@ struct sseu_dev_info {
u8 ss_stride;
u8 eu_stride;
-
- /* We don't have more than 8 eus per subslice at the moment and as we
-* store eus enabled using bits, no need to multiply by eus per
-* subslice.
-*/
- u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
};
/*
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..f2b92be44adf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3820,7 +3820,8 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ if (info->sseu.has_subslice_pg &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..47847135a11f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index d9b5baaef5d0..792ca3202073 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,13 +182,73 @@ static u16 compute_eu_total(const struct sseu_dev_info
*sseu)
return total;
}
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
+ u8 s_en, u32 ss_en, u16 eu_en)
+{
+ int s, ss;
+
+ /* ss_en represents entire subslice mask across all slices */
+ if (sseu->max_slices * sseu->max_subslices >
+ sizeof(ss_en) * BITS_PER_BYTE) {
+ DRM_ERROR("Invalid topology, max_slices: %d, max_subslices
%d\n",
+ sseu->max_slices, sseu->max_subslices);
+ return;
+ }
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if ((s_en & BIT(s)) == 0)
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+
+ intel_sseu_set_subslices(sseu, s, ss_en);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
+ sseu_set_eus(sseu, s, ss, eu_en);
+ }
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+
[Intel-gfx] [PATCH 4/4] drm/i915/tgl: Disable preemption while being debugged
From: Chris Wilson
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for our semaphore waits around preemption.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fbe98a2db88e..1f17d59c862c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -797,6 +797,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.display.has_modular_fia = 1,
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .has_logical_ring_preemption = false, /* XXX disabled for debugging */
};
#undef GEN
--
2.17.1
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Re: [Intel-gfx] [PATCH v6 07/10] drm/i915/dsb: function to trigger workload execution of DSB.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2b0ffc0afb74..eea86afb0583 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -212,3 +212,45 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tail;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(>cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ dsb->free_pos = 0;
+ intel_dsb_disable_engine(dsb);
I am still not very convince if a commit function should be void, I
would still want it to return success or failure, so that we would know
if the last operation was successful or not.
I would wait Jani N to comment here, on what he feels about this.
- Shashank
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 9b2522f20bfb..7389c8c5b665 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -43,5 +43,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dbaa49f5c74..c77b5066d8dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11687,6 +11687,8 @@ enum skl_power_gate {
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
#define DSB_CTRL(pipe, id)_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
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Re: [Intel-gfx] [PATCH v6 06/10] drm/i915/dsb: functions to enable/disable DSB engine.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control register. (Shashank)
v3: cosmetic changes done. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b1da2b06263a..2b0ffc0afb74 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -26,6 +26,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
}
+static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl |= DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
+static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl &= ~DSB_ENABLE;
Do we really need to care about reading the reg val first and then
disabling it ? I can understand that for enable().
How about this:
if (!dsb_is_busy()) {
I915_WRITE(DSB_CTRL(pipe, dsb->id), 0);
POSTING_READ();
return true;
}
DRM_DEBUG_KMS("DSB engine is busy.\n");
return false;
But this is optional suggestion, you can take a call on this.
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9188a0b53538..2dbaa49f5c74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11688,6 +11688,7 @@ enum skl_power_gate {
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
#define DSB_CTRL(pipe, id)_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
With or without suggested change above: Feel free to use
Reviewed-by: Shashank Sharma
- Shashank
#endif /* _I915_REG_H_ */
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Support for DP HDR outputs (rev6)
== Series Details == Series: drm/i915/dp: Support for DP HDR outputs (rev6) URL : https://patchwork.freedesktop.org/series/65656/ State : success == Summary == CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14371_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14371_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-apl3/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-apl8/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb4/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-apl7/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-apl3/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_legacy@cursor-vs-flip-legacy: - shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#103355]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-hsw2/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-msflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167] / [fdo#110378]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-rte.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-rte.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-x.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_cursor_mmap_gtt: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html * igt@kms_setmode@basic: - shard-apl: [PASS][19] -> [FAIL][20] ([fdo#99912]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-apl2/igt@kms_setm...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-apl6/igt@kms_setm...@basic.html * igt@prime_busy@after-bsd2: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +21 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb2/igt@prime_b...@after-bsd2.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb3/igt@prime_b...@after-bsd2.html Possible fixes * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [SKIP][23] ([fdo#110841]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14371/shard-iclb3/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [SKIP][25] ([fdo#111325]) -> [PASS][26] +7 similar issues [25]:
Re: [Intel-gfx] [PATCH v3 00/37] Introduce memory region concept (including device local memory)
Quoting Dave Airlie (2019-08-13 22:20:52) > On Sat, 10 Aug 2019 at 08:26, Matthew Auld wrote: > > > > In preparation for upcoming devices with device local memory, introduce the > > concept of different memory regions, and a simple buddy allocator to manage > > them in i915. > > > > One of the concerns raised from v1 was around not using enough of TTM, > > which is > > a fair criticism, so trying to get better alignment here is something we are > > investigating, though currently that is still WIP so in the meantime v3 > > still > > continues to push more of the low-level details forward, but not yet the TTM > > interactions. > > Can we bump the TTM work up the ladder here, as is I'm not willing to > accept any of this code upstream without some serious analysis, this > isn't a case of me making a nice suggestion and you having the option > to ignore it. Don't make me shout. Thanks for a reminder. TTM analysis was ongoing on the background and we now reserved enough time to conclude on how to best align with TTM in short-term and long-term. We decided to bite the bullet and apply dma_resv as the outer-most locking in i915 codepaths to align with the TTM locking. As a conclusion to those discussions we documented guidelines how to align with TTM locking: https://patchwork.freedesktop.org/patch/328266/ As refactoring of locking fundamentals of the driver is a massive undergoing with many opens along the path, we'd like to propose a staged approach to avoid stalling the upstream work while it's being done. Our first suggested step would be merging the i915 local memory related internal code reworks to unblock the display work. This step should not cause any conflicts with TTM. Following step would be to merge proposed memory allocation/ management uAPIs with TTM related functionality behind them for early debug. They would be protected by DRM_I915_DEBUG_EARLY_API kernel config flag (depending on EXPERT & STAGING & BROKEN). This would allow us to keep debugging these new IOCTLs with Mesa etc. while we rework the locking. The protection still leaving us a possibility to correcting the uAPIs if/when there is need after reworking the locking around dma_resv progresses. Draft of such proposal here: https://patchwork.freedesktop.org/patch/327908/ The final step (a rather long one) would be then to complete the locking rework in the driver and lift the DEBUG_EARLY_API protection once the locking has been sorted. If you could confirm the above plan sounds reasonable to you, we may then proceed with it. Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 04/11] drm: revocation check at drm subsystem
Adding a couple AMD guys.
I know this is already merged but I have a few questions after some
internal discussions.
On 2019-05-07 12:27 p.m., Ramalingam C wrote:
> On every hdcp revocation check request SRM is read from fw file
> /lib/firmware/display_hdcp_srm.bin
>
According to section 5 of the HDCP 2.3 spec [1] a device compliant with
HDCP 2.0 and higher must be capable of storing and updating the SRM in
non-volatile memory. Section 5.2 describes how this SRM needs to be
updated when a new version is served alongside protected content.
Isn't /lib/firmware intended for static firmware making updates to the
folder problematic for anyone but the system's package maintainer? I've
heard /lib might even be treated as read-only in certain environments.
This would mean it'd be impossible to support HDCP 2.x on those systems.
Wouldn't it be easier to provide a sysfs entry for SRM that allows
userspace (e.g. system startup/shutdown scripts) to (a) retrieve the SRM
from the HDCP implementation for non-volatile storage and (b) to pass
the SRM to the HDCP implementation for revocation checking?
[1]
https://www.digital-cp.com/sites/default/files/HDCP%20on%20HDMI%20Specification%20Rev2_3.pdf
Thanks,
Harry
> SRM table is parsed and stored at drm_hdcp.c, with functions exported
> for the services for revocation check from drivers (which
> implements the HDCP authentication)
>
> This patch handles the HDCP1.4 and 2.2 versions of SRM table.
>
> v2:
> moved the uAPI to request_firmware_direct() [Daniel]
> v3:
> kdoc added. [Daniel]
> srm_header unified and bit field definitions are removed. [Daniel]
> locking improved. [Daniel]
> vrl length violation is fixed. [Daniel]
> v4:
> s/__swab16/be16_to_cpu [Daniel]
> be24_to_cpu is done through a global func [Daniel]
> Unused variables are removed. [Daniel]
> unchecked return values are dropped from static funcs [Daniel]
>
> Signed-off-by: Ramalingam C
> Acked-by: Satyeshwar Singh
> Reviewed-by: Daniel Vetter
> ---
> Documentation/gpu/drm-kms-helpers.rst | 6 +
> drivers/gpu/drm/Makefile | 2 +-
> drivers/gpu/drm/drm_hdcp.c| 333 ++
> drivers/gpu/drm/drm_internal.h| 4 +
> drivers/gpu/drm/drm_sysfs.c | 2 +
> include/drm/drm_hdcp.h| 24 ++
> 6 files changed, 370 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/drm_hdcp.c
>
> diff --git a/Documentation/gpu/drm-kms-helpers.rst
> b/Documentation/gpu/drm-kms-helpers.rst
> index 14102ae035dc..0fe726a6ee67 100644
> --- a/Documentation/gpu/drm-kms-helpers.rst
> +++ b/Documentation/gpu/drm-kms-helpers.rst
> @@ -181,6 +181,12 @@ Panel Helper Reference
> .. kernel-doc:: drivers/gpu/drm/drm_panel_orientation_quirks.c
> :export:
>
> +HDCP Helper Functions Reference
> +===
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_hdcp.c
> + :export:
> +
> Display Port Helper Functions Reference
> ===
>
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 72f5036d9bfa..dd02e9dec810 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -17,7 +17,7 @@ drm-y :=drm_auth.o drm_cache.o \
> drm_plane.o drm_color_mgmt.o drm_print.o \
> drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \
> drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \
> - drm_atomic_uapi.o
> + drm_atomic_uapi.o drm_hdcp.o
>
> drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o
> drm_dma.o drm_scatter.o drm_lock.o
> drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
> diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> new file mode 100644
> index ..5e5409505c31
> --- /dev/null
> +++ b/drivers/gpu/drm/drm_hdcp.c
> @@ -0,0 +1,333 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Intel Corporation.
> + *
> + * Authors:
> + * Ramalingam C
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +
> +struct hdcp_srm {
> + u32 revoked_ksv_cnt;
> + u8 *revoked_ksv_list;
> +
> + /* Mutex to protect above struct member */
> + struct mutex mutex;
> +} *srm_data;
> +
> +static inline void drm_hdcp_print_ksv(const u8 *ksv)
> +{
> + DRM_DEBUG("\t%#02x, %#02x, %#02x, %#02x, %#02x\n",
> + ksv[0], ksv[1], ksv[2], ksv[3], ksv[4]);
> +}
> +
> +static u32 drm_hdcp_get_revoked_ksv_count(const u8 *buf, u32 vrls_length)
> +{
> + u32 parsed_bytes = 0, ksv_count = 0, vrl_ksv_cnt, vrl_sz;
> +
> + while (parsed_bytes < vrls_length) {
> + vrl_ksv_cnt = *buf;
> + ksv_count += vrl_ksv_cnt;
> +
> + vrl_sz = (vrl_ksv_cnt * DRM_HDCP_KSV_LEN) + 1;
> + buf += vrl_sz;
> + parsed_bytes
Re: [Intel-gfx] [PATCH v6 08/10] drm/i915/dsb: Enable gamma lut programming using DSB.
On 9/12/2019 6:37 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in future
based on need.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
v3:
- modified the code as per single dsb instance per crtc. (Shashank)
- Added dsb get/put call in platform specific load_lut hook. (Jani)
- removed dsb pointer from dev_priv. (Jani)
v4: simplified code by dropping ref-count implementation. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 57 +-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 318308dc136c..b6b9f0e5166b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -611,12 +611,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
When you've done enough kernel programming, you learn to expect get/put
to be paired, and assume it's a bug if this isn't the case.
Already have done it in my previous version,
https://patchwork.freedesktop.org/patch/329481/?series=63013=5
https://patchwork.freedesktop.org/patch/329482/?series=63013=5
Can you please suggest if it is ok?
Regards,
Animesh
So yeah, I did say it's okay not to have refcounting at first, *but* the
expectation that get/put go in pairs is so deeply ingrained that I
didn't even think to say you shouldn't have this kind of asymmetry.
So this creates a problem, how do we pass the dsb pointer here, as
without refcounting you can't actually have the put here as well,
because you throw the stuff out before the commit.
Maybe the easy answer is that we should just do the get and put at
intel_crtc_init and intel_crtc_destroy. Or we could do it at atomic
check and free.
Ville, which approach would conflict with your future vblank worker
stuff the least?
BR,
Jani.
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -624,9 +625,12 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
* from 3.0 to 7.0
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ 1 << 16);
}
}
@@ -787,22 +791,22 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
}
static void
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
const struct drm_color_lut *lut = blob->data;
[Intel-gfx] [PATCH v2] drm/i915/tgl: Disable preemption while being debugged
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for our semaphore waits around preemption.
v2: And disable internal semaphore usage
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
drivers/gpu/drm/i915/i915_pci.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 47d766ccea71..a3f0e4999744 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2939,6 +2939,9 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
+ if (INTEL_GEN(engine->i915) >= 12) /* XXX disabled for debugging */
+ engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES;
+
if (engine->class != COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) >= 12)
engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
}
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..2ca34a5cf7d3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -798,6 +798,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.has_rc6 = false, /* XXX disabled for debugging */
+ .has_logical_ring_preemption = false, /* XXX disabled for debugging */
};
#undef GEN
--
2.23.0
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Re: [Intel-gfx] [PATCH v6 05/10] drm/i915/dsb: Check DSB engine status.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 7 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 9e2927f869b9..b1da2b06263a 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -17,6 +17,15 @@
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK0xf
+static inline bool is_dsb_busy(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..9188a0b53538 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11683,4 +11683,11 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)(1 << (tc_port))
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE 0x70B00
+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
+(pipe) * 0x1000 + (id) * 100)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
Looks good to me,
Please feel free to use Reviewed-by: Shashank Sharma
- Shashank
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Re: [Intel-gfx] [PATCH v6 03/10] drm/i915/dsb: single register write function for DSB.
On 9/12/2019 6:37 PM, Animesh Manna wrote:
On 9/12/2019 6:30 PM, Sharma, Shashank wrote:
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank"
wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 30
drivers/gpu/drm/i915/display/intel_dsb.h | 9 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 7c1b1574788c..e2c383352145 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,13 @@
#define DSB_BUF_SIZE (2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_INDEXED_WRITE 0x9
We are not using this macro here, this should go to the Batch
/INDEXED_WRITE patch.
+#define DSB_BYTE_EN 0xF
+#define DSB_BYTE_EN_SHIFT 20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -66,5 +73,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(>vma, 0);
mutex_unlock(>drm.struct_mutex);
dsb->cmd_buf = NULL;
+ dsb->free_pos = 0;
+ }
+}
+
I hope this addition of braces are due to diff's adjustment.
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
why shouldn't we do a I915_WRITE(reg, val) here too? This is single
register write, and we can handle this.
That would assume it's okay to directly mmio write this and the
subsequent values, and write the batch already stored in the buffer
afterwards.
This is single write API, so I won't expect this to be called in an
indexed context, also, we have exceeded the buffer size already, so
no subsequent DSB write would be possible anyways. But I can still
see it would be some kind of mess only, so doesn't really matter if
we do this I915_write or not :).
Adding I915_WRITE can be done, but I feel better to break the
functionality where we have buffer overflow and based on that we can
fine tune the buffer size.
If a set of register is targetted to write through DSB then some
writing through MMIO and and rest writing though DSB may not a nice
thing.
So added only debug log to capture the issue.
Regards,
Animesh
Yeah, broken this way or other, better to warn as soon as possible.
With the above macro comment fixed,
Please feel free to use Reviewed-by: Shashank Sharma
- Shashank
- Shashank
BR,
Jani.
+ return;
}
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE <<
DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 27eb68eb5392..31b87dcfe160 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -21,10 +23,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+ * free_pos will point the first free entry position
+ * and help in calculating tail of command buffer.
+ */
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
#endif
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[Intel-gfx] [PATCH] drm/i915/tgl: Disable preemption while being debugged
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for our semaphore waits around preemption.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..2ca34a5cf7d3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -798,6 +798,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.has_rc6 = false, /* XXX disabled for debugging */
+ .has_logical_ring_preemption = false, /* XXX disabled for debugging */
};
#undef GEN
--
2.23.0
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Re: [Intel-gfx] [PATCH v6 04/10] drm/i915/dsb: Indexed register write function for DSB.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code comment. (Shashank)
v4: cosmetic changes done. (Shashank)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 65
drivers/gpu/drm/i915/display/intel_dsb.h | 8 +++
2 files changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index e2c383352145..9e2927f869b9 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -15,6 +15,7 @@
#define DSB_OPCODE_INDEXED_WRITE 0x9
#define DSB_BYTE_EN 0xF
#define DSB_BYTE_EN_SHIFT 20
+#define DSB_REG_VALUE_MASK 0xf
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
@@ -77,6 +78,70 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+ u32 reg_val;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
+ }
+
+ /*
+* For example the buffer will look like below for 3 dwords for auto
+* increment register:
+* ++
+* | size = 3 | offset &| value1 | value2 | value3 | zero |
+* | | opcode |||||
+* ++
+* + + +++++
+* 0 4 812 16 20 24
+* Byte
+*
+* As every instruction is 8 byte aligned the index of dsb instruction
+* will start always from even number while dealing with u32 array. If
+* we are writing odd no of dwords, Zeros will be added in the end for
+* padding.
+*/
+ reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+ if (reg_val != i915_mmio_reg_offset(reg)) {
+ /* Every instruction should be 8 byte aligned. */
+ dsb->free_pos = ALIGN(dsb->free_pos, 2);
+
+ dsb->ins_start_offset = dsb->free_pos;
+
+ /* Update the size. */
+ buf[dsb->free_pos++] = 1;
+
+ /* Update the opcode and reg. */
+ buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
+ DSB_OPCODE_SHIFT) |
+ i915_mmio_reg_offset(reg);
+
+ /* Update the value. */
+ buf[dsb->free_pos++] = val;
+ } else {
+ /* Update the new value. */
+ buf[dsb->free_pos++] = val;
+
+ /* Update the size. */
+ buf[dsb->ins_start_offset]++;
+ }
+
+ /* if number of data words is odd, then the last dword should be 0.*/
+ if (dsb->free_pos & 0x1)
+ buf[dsb->free_pos] = 0;
So we are adding 0 on every even position while writing buffer and
letting the next write to overwrite it. Can be done in commit() in the
end too, but I think its more or less same.
+}
+
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 31b87dcfe160..9b2522f20bfb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -29,11 +29,19 @@ struct intel_dsb {
* and help in calculating tail of command buffer.
*/
int free_pos;
+
+ /*
+* ins_start_offset will help to store start address
+* of the dsb instuction of auto-increment register.
+*/
+ u32 ins_start_offset;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val);
#endif
Looks good to me,
Please feel free to use Reviewed-by: Shashank Sharma
-
Re: [Intel-gfx] [PATCH v6 03/10] drm/i915/dsb: single register write function for DSB.
On 9/12/2019 6:30 PM, Sharma, Shashank wrote:
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank"
wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 30
drivers/gpu/drm/i915/display/intel_dsb.h | 9 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 7c1b1574788c..e2c383352145 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,13 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT24
+#define DSB_OPCODE_MMIO_WRITE0x1
+#define DSB_OPCODE_INDEXED_WRITE0x9
We are not using this macro here, this should go to the Batch
/INDEXED_WRITE patch.
+#define DSB_BYTE_EN0xF
+#define DSB_BYTE_EN_SHIFT20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -66,5 +73,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(>vma, 0);
mutex_unlock(>drm.struct_mutex);
dsb->cmd_buf = NULL;
+dsb->free_pos = 0;
+}
+}
+
I hope this addition of braces are due to diff's adjustment.
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
+{
+struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+u32 *buf = dsb->cmd_buf;
+
+if (!buf) {
+I915_WRITE(reg, val);
+return;
+}
+
+if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+DRM_DEBUG_KMS("DSB buffer overflow\n");
why shouldn't we do a I915_WRITE(reg, val) here too? This is single
register write, and we can handle this.
That would assume it's okay to directly mmio write this and the
subsequent values, and write the batch already stored in the buffer
afterwards.
This is single write API, so I won't expect this to be called in an
indexed context, also, we have exceeded the buffer size already, so no
subsequent DSB write would be possible anyways. But I can still see it
would be some kind of mess only, so doesn't really matter if we do
this I915_write or not :).
Adding I915_WRITE can be done, but I feel better to break the
functionality where we have buffer overflow and based on that we can
fine tune the buffer size.
If a set of register is targetted to write through DSB then some writing
through MMIO and and rest writing though DSB may not a nice thing.
So added only debug log to capture the issue.
Regards,
Animesh
- Shashank
BR,
Jani.
+return;
}
+
+buf[dsb->free_pos++] = val;
+buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE <<
DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 27eb68eb5392..31b87dcfe160 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -21,10 +23,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+/*
+ * free_pos will point the first free entry position
+ * and help in calculating tail of command buffer.
+ */
+int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
#endif
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Re: [Intel-gfx] [PATCH v6 08/10] drm/i915/dsb: Enable gamma lut programming using DSB.
On Thu, 12 Sep 2019, Animesh Manna wrote:
> Gamma lut programming can be programmed using DSB
> where bulk register programming can be done using indexed
> register write which takes number of data and the mmio offset
> to be written.
>
> Currently enabled for 12-bit gamma LUT which is enabled by
> default and later 8-bit/10-bit will be enabled in future
> based on need.
>
> v1: Initial version.
> v2: Directly call dsb-api at callsites. (Jani)
> v3:
> - modified the code as per single dsb instance per crtc. (Shashank)
> - Added dsb get/put call in platform specific load_lut hook. (Jani)
> - removed dsb pointer from dev_priv. (Jani)
> v4: simplified code by dropping ref-count implementation. (Shashank)
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Shashank Sharma
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 57 +-
> 1 file changed, 35 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 318308dc136c..b6b9f0e5166b 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -611,12 +611,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_dsb *dsb = intel_dsb_get(crtc);
When you've done enough kernel programming, you learn to expect get/put
to be paired, and assume it's a bug if this isn't the case.
So yeah, I did say it's okay not to have refcounting at first, *but* the
expectation that get/put go in pairs is so deeply ingrained that I
didn't even think to say you shouldn't have this kind of asymmetry.
So this creates a problem, how do we pass the dsb pointer here, as
without refcounting you can't actually have the put here as well,
because you throw the stuff out before the commit.
Maybe the easy answer is that we should just do the get and put at
intel_crtc_init and intel_crtc_destroy. Or we could do it at atomic
check and free.
Ville, which approach would conflict with your future vblank worker
stuff the least?
BR,
Jani.
> enum pipe pipe = crtc->pipe;
>
> /* Program the max register to clamp values > 1.0. */
> - I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
> - I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
> - I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
> + intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
> + intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
> + intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
>
> /*
>* Program the gc max 2 register to clamp values > 1.0.
> @@ -624,9 +625,12 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
>* from 3.0 to 7.0
>*/
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> - I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
> - I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
> - I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
> + intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
> + 1 << 16);
> + intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
> + 1 << 16);
> + intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
> + 1 << 16);
> }
> }
>
> @@ -787,22 +791,22 @@ icl_load_gcmax(const struct intel_crtc_state
> *crtc_state,
> const struct drm_color_lut *color)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_dsb *dsb = intel_dsb_get(crtc);
> enum pipe pipe = crtc->pipe;
>
> /* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
> + intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
> + intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
> + intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
> }
>
> static void
> icl_program_gamma_superfine_segment(const struct intel_crtc_state
> *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> + struct intel_dsb *dsb = intel_dsb_get(crtc);
> enum pipe pipe = crtc->pipe;
> u32 i;
>
> @@ -813,15 +817,16 @@ icl_program_gamma_superfine_segment(const struct
>
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Get the correct wakeref for reading HOTPLUG_EN et al.
Quoting Arkadiusz Hiler (2019-09-12 13:54:18)
> Without it we get:
> Unclaimed read from register 0x1e1110
> WARNING: CPU: 2 PID: 1029 at drivers/gpu/drm/i915/intel_uncore.c:1101
> __unclaimed_reg_debug+0x40/0x50 [i915]
> Call Trace:
> fwtable_read32+0x233/0x300 [i915]
> i915_interrupt_info+0xa73/0xd60 [i915]
> seq_read+0xdb/0x3c0
> full_proxy_read+0x51/0x80
> vfs_read+0x9e/0x160
> ksys_read+0x8f/0xe0
> do_syscall_64+0x55/0x1c0
> entry_SYSCALL_64_after_hwframe+0x49/0xbe
>
> Cc: Chris Wilson
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109824
> Signed-off-by: Arkadiusz Hiler
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index e5835337f022..29f3436167a2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -534,6 +534,7 @@ static int i915_interrupt_info(struct seq_file *m, void
> *data)
>
> gen8_display_interrupt_info(m);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> + intel_wakeref_t pref;
checkpath will complain about missing newline between variable block and
code.
> seq_printf(m, "Display IER:\t%08x\n",
>I915_READ(VLV_IER));
> seq_printf(m, "Display IIR:\t%08x\n",
> @@ -544,7 +545,6 @@ static int i915_interrupt_info(struct seq_file *m, void
> *data)
>I915_READ(VLV_IMR));
> for_each_pipe(dev_priv, pipe) {
> enum intel_display_power_domain power_domain;
> - intel_wakeref_t pref;
>
> power_domain = POWER_DOMAIN_PIPE(pipe);
> pref = intel_display_power_get_if_enabled(dev_priv,
> @@ -578,12 +578,14 @@ static int i915_interrupt_info(struct seq_file *m, void
> *data)
> seq_printf(m, "PM IMR:\t\t%08x\n",
>I915_READ(GEN6_PMIMR));
>
> + pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> seq_printf(m, "Port hotplug:\t%08x\n",
>I915_READ(PORT_HOTPLUG_EN));
> seq_printf(m, "DPFLIPSTAT:\t%08x\n",
>I915_READ(VLV_DPFLIPSTAT));
> seq_printf(m, "DPINVGTT:\t%08x\n",
>I915_READ(DPINVGTT));
> + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
Seems reasonable explanation.
Reviewed-by: Chris Wilson
Hopefully, that is enough. If not, we need to ask Imre what the correct
power domain should be :)
-Chris
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Re: [Intel-gfx] [PATCH v6 03/10] drm/i915/dsb: single register write function for DSB.
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 30
drivers/gpu/drm/i915/display/intel_dsb.h | 9 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 7c1b1574788c..e2c383352145 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,13 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_INDEXED_WRITE 0x9
We are not using this macro here, this should go to the Batch
/INDEXED_WRITE patch.
+#define DSB_BYTE_EN0xF
+#define DSB_BYTE_EN_SHIFT 20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -66,5 +73,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(>vma, 0);
mutex_unlock(>drm.struct_mutex);
dsb->cmd_buf = NULL;
+ dsb->free_pos = 0;
+ }
+}
+
I hope this addition of braces are due to diff's adjustment.
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
why shouldn't we do a I915_WRITE(reg, val) here too? This is single
register write, and we can handle this.
That would assume it's okay to directly mmio write this and the
subsequent values, and write the batch already stored in the buffer
afterwards.
This is single write API, so I won't expect this to be called in an
indexed context, also, we have exceeded the buffer size already, so no
subsequent DSB write would be possible anyways. But I can still see it
would be some kind of mess only, so doesn't really matter if we do this
I915_write or not :).
- Shashank
BR,
Jani.
+ return;
}
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 27eb68eb5392..31b87dcfe160 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -21,10 +23,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+* free_pos will point the first free entry position
+* and help in calculating tail of command buffer.
+*/
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
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[PATCH] Revert "drm/i915/userptr: Acquire the page lock around set_page_dirty()"
The userptr put_pages can be called from inside try_to_unmap, and so
enters with the page lock held on one of the object's backing pages. We
cannot take the page lock ourselves for fear of recursion.
Reported-by: Lionel Landwerlin
Reported-by: Martin Wilck
Reported-by: Leo Kraav
Fixes: aa56a292ce62 ("drm/i915/userptr: Acquire the page lock around
set_page_dirty()")
References: https://bugzilla.kernel.org/show_bug.cgi?id=203317
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 74da35611d7c..11b231c187c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -672,15 +672,7 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj,
for_each_sgt_page(page, sgt_iter, pages) {
if (obj->mm.dirty)
- /*
-* As this may not be anonymous memory (e.g. shmem)
-* but exist on a real mapping, we have to lock
-* the page in order to dirty it -- holding
-* the page reference is not sufficient to
-* prevent the inode from being truncated.
-* Play safe and take the lock.
-*/
- set_page_dirty_lock(page);
+ set_page_dirty(page);
mark_page_accessed(page);
put_page(page);
--
2.23.0
[Intel-gfx] [PATCH 1/1] drm/i915: Get the correct wakeref for reading HOTPLUG_EN et al.
Without it we get:
Unclaimed read from register 0x1e1110
WARNING: CPU: 2 PID: 1029 at drivers/gpu/drm/i915/intel_uncore.c:1101
__unclaimed_reg_debug+0x40/0x50 [i915]
Call Trace:
fwtable_read32+0x233/0x300 [i915]
i915_interrupt_info+0xa73/0xd60 [i915]
seq_read+0xdb/0x3c0
full_proxy_read+0x51/0x80
vfs_read+0x9e/0x160
ksys_read+0x8f/0xe0
do_syscall_64+0x55/0x1c0
entry_SYSCALL_64_after_hwframe+0x49/0xbe
Cc: Chris Wilson
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109824
Signed-off-by: Arkadiusz Hiler
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..29f3436167a2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -534,6 +534,7 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
gen8_display_interrupt_info(m);
} else if (IS_VALLEYVIEW(dev_priv)) {
+ intel_wakeref_t pref;
seq_printf(m, "Display IER:\t%08x\n",
I915_READ(VLV_IER));
seq_printf(m, "Display IIR:\t%08x\n",
@@ -544,7 +545,6 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
I915_READ(VLV_IMR));
for_each_pipe(dev_priv, pipe) {
enum intel_display_power_domain power_domain;
- intel_wakeref_t pref;
power_domain = POWER_DOMAIN_PIPE(pipe);
pref = intel_display_power_get_if_enabled(dev_priv,
@@ -578,12 +578,14 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
seq_printf(m, "PM IMR:\t\t%08x\n",
I915_READ(GEN6_PMIMR));
+ pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
seq_printf(m, "Port hotplug:\t%08x\n",
I915_READ(PORT_HOTPLUG_EN));
seq_printf(m, "DPFLIPSTAT:\t%08x\n",
I915_READ(VLV_DPFLIPSTAT));
seq_printf(m, "DPINVGTT:\t%08x\n",
I915_READ(DPINVGTT));
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
} else if (!HAS_PCH_SPLIT(dev_priv)) {
seq_printf(m, "Interrupt enable:%08x\n",
--
2.21.0
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[Intel-gfx] [PATCH 0/1] Fix i915_interrupt_info debugfs with display off on VLV
Cover letter to use https://intel-gfx-ci.01.org/test-with.html https://patchwork.freedesktop.org/patch/330337/?series=66602 Test-with: 20190912123320.13131-1-arkadiusz.hi...@intel.com Arkadiusz Hiler (1): drm/i915: Get the correct wakeref for reading HOTPLUG_EN et al. drivers/gpu/drm/i915/i915_debugfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 03/10] drm/i915/dsb: single register write function for DSB.
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
> On 9/12/2019 12:41 AM, Animesh Manna wrote:
>> DSB support single register write through opcode 0x1. Generic
>> api created which accumulate all single register write in a batch
>> buffer and once DSB is triggered, it will program all the registers
>> at the same time.
>>
>> v1: Initial version.
>> v2: Unused macro removed and cosmetic changes done. (Shashank)
>> v3: set free_pos to zero in dsb-put() instead dsb-get() and
>> a cosmetic change. (Shashank)
>>
>> Cc: Jani Nikula
>> Cc: Rodrigo Vivi
>> Cc: Shashank Sharma
>> Signed-off-by: Animesh Manna
>> ---
>> drivers/gpu/drm/i915/display/intel_dsb.c | 30
>> drivers/gpu/drm/i915/display/intel_dsb.h | 9 +++
>> 2 files changed, 39 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
>> b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index 7c1b1574788c..e2c383352145 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -9,6 +9,13 @@
>>
>> #define DSB_BUF_SIZE(2 * PAGE_SIZE)
>>
>> +/* DSB opcodes. */
>> +#define DSB_OPCODE_SHIFT24
>> +#define DSB_OPCODE_MMIO_WRITE 0x1
>> +#define DSB_OPCODE_INDEXED_WRITE0x9
> We are not using this macro here, this should go to the Batch
> /INDEXED_WRITE patch.
>> +#define DSB_BYTE_EN 0xF
>> +#define DSB_BYTE_EN_SHIFT 20
>> +
>> struct intel_dsb *
>> intel_dsb_get(struct intel_crtc *crtc)
>> {
>> @@ -66,5 +73,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
>> i915_vma_unpin_and_release(>vma, 0);
>> mutex_unlock(>drm.struct_mutex);
>> dsb->cmd_buf = NULL;
>> +dsb->free_pos = 0;
>> +}
>> +}
>> +
> I hope this addition of braces are due to diff's adjustment.
>> +void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>> +{
>> +struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> +struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +u32 *buf = dsb->cmd_buf;
>> +
>> +if (!buf) {
>> +I915_WRITE(reg, val);
>> +return;
>> +}
>> +
>> +if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
>> +DRM_DEBUG_KMS("DSB buffer overflow\n");
> why shouldn't we do a I915_WRITE(reg, val) here too? This is single
> register write, and we can handle this.
That would assume it's okay to directly mmio write this and the
subsequent values, and write the batch already stored in the buffer
afterwards.
BR,
Jani.
>> +return;
>> }
>> +
>> +buf[dsb->free_pos++] = val;
>> +buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
>> + (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
>> + i915_mmio_reg_offset(reg);
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
>> b/drivers/gpu/drm/i915/display/intel_dsb.h
>> index 27eb68eb5392..31b87dcfe160 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -6,6 +6,8 @@
>> #ifndef _INTEL_DSB_H
>> #define _INTEL_DSB_H
>>
>> +#include "i915_reg.h"
>> +
>> struct intel_crtc;
>> struct i915_vma;
>>
>> @@ -21,10 +23,17 @@ struct intel_dsb {
>> enum dsb_id id;
>> u32 *cmd_buf;
>> struct i915_vma *vma;
>> +
>> +/*
>> + * free_pos will point the first free entry position
>> + * and help in calculating tail of command buffer.
>> + */
>> +int free_pos;
>> };
>>
>> struct intel_dsb *
>> intel_dsb_get(struct intel_crtc *crtc);
>> void intel_dsb_put(struct intel_dsb *dsb);
>> +void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
>>
>> #endif
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v6 03/10] drm/i915/dsb: single register write function for DSB.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 30
drivers/gpu/drm/i915/display/intel_dsb.h | 9 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 7c1b1574788c..e2c383352145 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,13 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_INDEXED_WRITE 0x9
We are not using this macro here, this should go to the Batch
/INDEXED_WRITE patch.
+#define DSB_BYTE_EN0xF
+#define DSB_BYTE_EN_SHIFT 20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -66,5 +73,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(>vma, 0);
mutex_unlock(>drm.struct_mutex);
dsb->cmd_buf = NULL;
+ dsb->free_pos = 0;
+ }
+}
+
I hope this addition of braces are due to diff's adjustment.
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
why shouldn't we do a I915_WRITE(reg, val) here too? This is single
register write, and we can handle this.
+ return;
}
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 27eb68eb5392..31b87dcfe160 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -21,10 +23,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+* free_pos will point the first free entry position
+* and help in calculating tail of command buffer.
+*/
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
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[Intel-gfx] [CI] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
intel_gt_pm_wait_for_idle
v4: No need for parked/unparked estimation if !CONFIG_PM
v5: Keep timer park/unpark logic as was
v6: Refactor duplicated estimate/update rc6 logic
v7: Pull intel_get_pm_get_if_awake() out from the pmu->lock.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105010
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 22 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 22 +--
drivers/gpu/drm/i915/i915_pmu.c | 242 +--
drivers/gpu/drm/i915/i915_pmu.h | 4 +-
5 files changed, 170 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 3bd764104d41..a11ad4d914ca 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -141,6 +141,24 @@ bool i915_gem_load_power_context(struct drm_i915_private
*i915)
return switch_to_kernel_context_sync(>gt);
}
+static void user_forcewake(struct intel_gt *gt, bool suspend)
+{
+ int count = atomic_read(>user_wakeref);
+
+ /* Inside suspend/resume so single threaded, no races to worry about. */
+ if (likely(!count))
+ return;
+
+ intel_gt_pm_get(gt);
+ if (suspend) {
+ GEM_BUG_ON(count > atomic_read(>wakeref.count));
+ atomic_sub(count, >wakeref.count);
+ } else {
+ atomic_add(count, >wakeref.count);
+ }
+ intel_gt_pm_put(gt);
+}
+
void i915_gem_suspend(struct drm_i915_private *i915)
{
GEM_TRACE("\n");
@@ -148,6 +166,8 @@ void i915_gem_suspend(struct drm_i915_private *i915)
intel_wakeref_auto(>ggtt.userfault_wakeref, 0);
flush_workqueue(i915->wq);
+ user_forcewake(>gt, true);
+
mutex_lock(>drm.struct_mutex);
/*
@@ -259,6 +279,8 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (!i915_gem_load_power_context(i915))
goto err_wedged;
+ user_forcewake(>gt, false);
+
out_unlock:
intel_uncore_forcewake_put(>uncore, FORCEWAKE_ALL);
mutex_unlock(>drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index dc295c196d11..3039cef64b11 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -50,6 +50,7 @@ struct intel_gt {
} timelines;
struct intel_wakeref wakeref;
+ atomic_t user_wakeref;
struct list_head closed_vma;
spinlock_t closed_lock; /* guards the list of closed_vma */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..f3ae525b77c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3995,13 +3995,12 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- file->private_data =
- (void *)(uintptr_t)intel_runtime_pm_get(>runtime_pm);
- intel_uncore_forcewake_user_get(>uncore);
+ atomic_inc(>user_wakeref);
+ intel_gt_pm_get(gt);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
return 0;
}
@@ -4009,13 +4008,12 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- intel_uncore_forcewake_user_put(>uncore);
- intel_runtime_pm_put(>runtime_pm,
-(intel_wakeref_t)(uintptr_t)file->private_data);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_put(>uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>user_wakeref);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 623ad32303a1..3310353890fb 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -116,22 +116,124 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
gpu_active)
return enable;
}
-void i915_pmu_gt_parked(struct drm_i915_private *i915)
+static u64 __get_rc6(const struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct
Re: 5.3-rc3: Frozen graphics with kcompactd migrating i915 pages
Quoting Linus Torvalds (2019-09-12 12:59:25)
> On Thu, Sep 12, 2019 at 12:51 PM Martin Wilck wrote:
> >
> > Is there an alternative to reverting aa56a292ce62 ("drm/i915/userptr:
> > Acquire the page lock around set_page_dirty()")? And if we do, what
> > would be the consequences? Would other patches need to be reverted,
> > too?
>
> Looking at that commit, and the backtrace of the lockup, I think that
> reverting it is the correct thing to do.
>
> You can't take the page lock in invalidate_range(), since it's called
> from try_to_unmap(), which is called with the page lock already held.
>
> So commit aa56a292ce62 is just fundamentally completely wrong and
> should be reverted.
There's still the dilemma that we get called without the page lock, but
at this moment in time in order to hit 5.3, it needs a revert sent
directly to Linus.
-Chris
Re: [Intel-gfx] [PATCH v6 02/10] drm/i915/dsb: DSB context creation.
On Thu, 12 Sep 2019, Animesh Manna wrote:
> This patch adds a function, which will internally get the gem buffer
> for DSB engine. The GEM buffer is from global GTT, and is mapped into
> CPU domain, contains the data + opcode to be feed to DSB engine.
>
> v1: Initial version.
>
> v2:
> - removed some unwanted code. (Chris)
> - Used i915_gem_object_create_internal instead of _shmem. (Chris)
> - cmd_buf_tail removed and can be derived through vma object. (Chris)
>
> v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
>
> v4: for simplification and based on current usage added single dsb
> object in intel_crtc. (Shashank)
>
> v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
>
> Cc: Imre Deak
> Cc: Michel Thierry
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Shashank Sharma
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_display_types.h| 3 +
> drivers/gpu/drm/i915/display/intel_dsb.c | 70 +++
> drivers/gpu/drm/i915/display/intel_dsb.h | 30
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 5 files changed, 105 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 658b930d34a8..6313e7b4bd78 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -172,6 +172,7 @@ i915-y += \
> display/intel_display_power.o \
> display/intel_dpio_phy.o \
> display/intel_dpll_mgr.o \
> + display/intel_dsb.o \
> display/intel_fbc.o \
> display/intel_fifo_underrun.o \
> display/intel_frontbuffer.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5cc4b810d9e..49c902b00484 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1033,6 +1033,9 @@ struct intel_crtc {
>
> /* scalers available on this crtc */
> int num_scalers;
> +
> + /* per pipe DSB related info */
> + struct intel_dsb dsb;
> };
>
> struct intel_plane {
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> new file mode 100644
> index ..7c1b1574788c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +
> +#define DSB_BUF_SIZE(2 * PAGE_SIZE)
> +
> +struct intel_dsb *
> +intel_dsb_get(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + struct intel_dsb *dsb = >dsb;
> + intel_wakeref_t wakeref;
> +
> + if ((!HAS_DSB(i915)) || dsb->cmd_buf)
> + return dsb;
This might work now, but this is racy.
> +
> + dsb->id = DSB1;
> + wakeref = intel_runtime_pm_get(>runtime_pm);
> +
> + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> + if (IS_ERR(obj))
> + goto err;
> +
> + mutex_lock(>drm.struct_mutex);
> + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
> + mutex_unlock(>drm.struct_mutex);
> + if (IS_ERR(vma)) {
> + DRM_ERROR("Vma creation failed\n");
> + i915_gem_object_put(obj);
> + goto err;
> + }
> +
> + dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> + if (IS_ERR(dsb->cmd_buf)) {
> + DRM_ERROR("Command buffer creation failed\n");
> + i915_vma_unpin_and_release(, 0);
> + dsb->cmd_buf = NULL;
> + goto err;
> + }
> + dsb->vma = vma;
> +
> +err:
> + intel_runtime_pm_put(>runtime_pm, wakeref);
> + return dsb;
> +}
> +
> +void intel_dsb_put(struct intel_dsb *dsb)
> +{
> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> + if (!dsb)
> + return;
If dsb == NULL, the above dereference probably oopses before this check.
BR,
Jani.
> +
> + if (dsb->cmd_buf) {
> + mutex_lock(>drm.struct_mutex);
> + i915_gem_object_unpin_map(dsb->vma->obj);
> + i915_vma_unpin_and_release(>vma, 0);
> + mutex_unlock(>drm.struct_mutex);
> + dsb->cmd_buf = NULL;
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> new file mode 100644
> index ..27eb68eb5392
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -0,0 +1,30 @@
> +/*
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/tgl: Add missing ddi clock select during DP init sequence
== Series Details == Series: series starting with [1/4] drm/i915/tgl: Add missing ddi clock select during DP init sequence URL : https://patchwork.freedesktop.org/series/66556/ State : success == Summary == CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14370_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14370_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-queue-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-apl6/igt@gem_workarou...@suspend-resume-context.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([fdo#103540]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-hsw2/igt@kms_f...@flip-vs-suspend-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-hsw4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#111609]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-glk8/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-glk1/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_cursor_mmap_gtt: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_gtt.html * igt@perf@polling: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#110728]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-skl6/igt@p...@polling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-skl10/igt@p...@polling.html * igt@prime_busy@after-bsd2: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109276]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb2/igt@prime_b...@after-bsd2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-iclb3/igt@prime_b...@after-bsd2.html Possible fixes * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [SKIP][21] ([fdo#110841]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-iclb3/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24] +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/shard-iclb4/igt@gem_exec_sched...@preempt-bsd.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14370/shard-iclb8/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_exec_schedule@promotion-bsd1:
Re: [Intel-gfx] [PATCH v7] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
Quoting Tvrtko Ursulin (2019-09-12 13:38:47) > > On 12/09/2019 12:32, Chris Wilson wrote: > > + if (val) > > + /* > > + * If we are coming back from being runtime suspended we must > > + * be careful not to report a larger value than returned > > + * previously. > > + */ > > The comment is a bit dislocated from the logic so feels it would better > go into __pmu_update_rc6. > > > + val = __pmu_update_rc6(pmu, val); > > + else > > + /* > > + * We were runtime suspended. > > s/were/are/, or maybe it is "think we are". :) "We think we are" captures my anxiety. Moving both into their respective routines. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
On 12/09/2019 12:32, Chris Wilson wrote:
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
intel_gt_pm_wait_for_idle
v4: No need for parked/unparked estimation if !CONFIG_PM
v5: Keep timer park/unpark logic as was
v6: Refactor duplicated estimate/update rc6 logic
v7: Pull intel_get_pm_get_if_awake() out from the pmu->lock.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105010
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 22 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 22 +-
drivers/gpu/drm/i915/i915_pmu.c | 244 +--
drivers/gpu/drm/i915/i915_pmu.h | 4 +-
5 files changed, 171 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 3bd764104d41..a11ad4d914ca 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -141,6 +141,24 @@ bool i915_gem_load_power_context(struct drm_i915_private
*i915)
return switch_to_kernel_context_sync(>gt);
}
+static void user_forcewake(struct intel_gt *gt, bool suspend)
+{
+ int count = atomic_read(>user_wakeref);
+
+ /* Inside suspend/resume so single threaded, no races to worry about. */
+ if (likely(!count))
+ return;
+
+ intel_gt_pm_get(gt);
+ if (suspend) {
+ GEM_BUG_ON(count > atomic_read(>wakeref.count));
+ atomic_sub(count, >wakeref.count);
+ } else {
+ atomic_add(count, >wakeref.count);
+ }
+ intel_gt_pm_put(gt);
+}
+
void i915_gem_suspend(struct drm_i915_private *i915)
{
GEM_TRACE("\n");
@@ -148,6 +166,8 @@ void i915_gem_suspend(struct drm_i915_private *i915)
intel_wakeref_auto(>ggtt.userfault_wakeref, 0);
flush_workqueue(i915->wq);
+ user_forcewake(>gt, true);
+
mutex_lock(>drm.struct_mutex);
/*
@@ -259,6 +279,8 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (!i915_gem_load_power_context(i915))
goto err_wedged;
+ user_forcewake(>gt, false);
+
out_unlock:
intel_uncore_forcewake_put(>uncore, FORCEWAKE_ALL);
mutex_unlock(>drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index dc295c196d11..3039cef64b11 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -50,6 +50,7 @@ struct intel_gt {
} timelines;
struct intel_wakeref wakeref;
+ atomic_t user_wakeref;
struct list_head closed_vma;
spinlock_t closed_lock; /* guards the list of closed_vma */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..f3ae525b77c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3995,13 +3995,12 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- file->private_data =
- (void *)(uintptr_t)intel_runtime_pm_get(>runtime_pm);
- intel_uncore_forcewake_user_get(>uncore);
+ atomic_inc(>user_wakeref);
+ intel_gt_pm_get(gt);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
return 0;
}
@@ -4009,13 +4008,12 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- intel_uncore_forcewake_user_put(>uncore);
- intel_runtime_pm_put(>runtime_pm,
-(intel_wakeref_t)(uintptr_t)file->private_data);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_put(>uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>user_wakeref);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 8e251e719390..e63649b86915 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -116,22 +116,124 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
gpu_active)
return enable;
}
-void i915_pmu_gt_parked(struct drm_i915_private *i915)
+static u64 __get_rc6(const struct intel_gt *gt)
{
+ struct drm_i915_private
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Skip busyness sampling when and where not needed
On 11/09/2019 17:50, Patchwork wrote:
== Series Details ==
Series: drm/i915/pmu: Skip busyness sampling when and where not needed
URL : https://patchwork.freedesktop.org/series/66541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6872 -> Patchwork_14363
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/
Known issues
Here are the changes found in Patchwork_14363 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724] /
[fdo#111214])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4] ([fdo#111514])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
* igt@kms_addfb_basic@invalid-set-prop-any:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@kms_addfb_ba...@invalid-set-prop-any.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@kms_addfb_ba...@invalid-set-prop-any.html
Possible fixes
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6872 -> Patchwork_14363
CI-20190529: 20190529
CI_DRM_6872: b27acd37b7dedf49557d6e41a3ee046c3f5d99ba @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14363: 48733870bba853158fe3f7c529866078838f6198 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
48733870bba8 drm/i915/pmu: Skip busyness sampling when and where not needed
Pushed, thanks for the review!
Regards,
Tvrtko
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 02/10] drm/i915/dsb: DSB context creation.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can be derived through vma object. (Chris)
v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
v4: for simplification and based on current usage added single dsb
object in intel_crtc. (Shashank)
v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dsb.c | 70 +++
drivers/gpu/drm/i915/display/intel_dsb.h | 30
drivers/gpu/drm/i915/i915_drv.h | 1 +
5 files changed, 105 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 658b930d34a8..6313e7b4bd78 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -172,6 +172,7 @@ i915-y += \
display/intel_display_power.o \
display/intel_dpio_phy.o \
display/intel_dpll_mgr.o \
+ display/intel_dsb.o \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..49c902b00484 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1033,6 +1033,9 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
+
+ /* per pipe DSB related info */
+ struct intel_dsb dsb;
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
new file mode 100644
index ..7c1b1574788c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+
+#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ struct intel_dsb *dsb = >dsb;
Minor nitpick, if we move this line above next to i915, all the
initialized variables will be together.
+ intel_wakeref_t wakeref;
+
+ if ((!HAS_DSB(i915)) || dsb->cmd_buf)
+ return dsb;
+
+ dsb->id = DSB1;
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj))
This is also an error condition, deserves a DRM_ERROR() too.
+ goto err;
+
+ mutex_lock(>drm.struct_mutex);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ mutex_unlock(>drm.struct_mutex);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("Vma creation failed\n");
+ i915_gem_object_put(obj);
+ goto err;
+ }
+
+ dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(dsb->cmd_buf)) {
+ DRM_ERROR("Command buffer creation failed\n");
+ i915_vma_unpin_and_release(, 0);
+ dsb->cmd_buf = NULL;
+ goto err;
+ }
+ dsb->vma = vma;
+
+err:
+ intel_runtime_pm_put(>runtime_pm, wakeref);
+ return dsb;
+}
+
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (!dsb)
+ return;
+
+ if (dsb->cmd_buf) {
+ mutex_lock(>drm.struct_mutex);
+ i915_gem_object_unpin_map(dsb->vma->obj);
+ i915_vma_unpin_and_release(>vma, 0);
+ mutex_unlock(>drm.struct_mutex);
+ dsb->cmd_buf = NULL;
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
new file mode 100644
index ..27eb68eb5392
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DSB_H
+#define _INTEL_DSB_H
+
Re: 5.3-rc3: Frozen graphics with kcompactd migrating i915 pages
Hi Chris,
On Tue, 2019-09-10 at 17:20 +0300, Leho Kraav wrote:
> On Fri, Aug 09, 2019 at 01:53:43PM +0100, Chris Wilson wrote:
> > Quoting Martin Wilck (2019-08-09 13:41:42)
> > > This happened to me today, running kernel 5.3.0-rc3-1.g571863b-
> > > default
> > > (5.3-rc3 with just a few patches on top), after starting a KVM
> > > virtual
> > > machine. The X screen was frozen. Remote login via ssh was still
> > > possible, thus I was able to retrieve basic logs.
> > >
> > > sysrq-w showed two blocked processes (kcompactd0 and KVM). After
> > > a
> > > minute, the same two processes were still blocked. KVM seems to
> > > try to
> > > acquire a lock that kcompactd is holding. kcompactd is waiting
> > > for IO
> > > to complete on pages owned by the i915 driver.
> >
> > My bad, it's known. We haven't decided on whether to revert the
> > unfortunate recursive locking (and so hit another warn elsewhere)
> > or to
> > ignore the dirty pages (and so risk losing data across swap).
> >
> > cb6d7c7dc7ff ("drm/i915/userptr: Acquire the page lock around
> > set_page_dirty()")
> > -Chris
>
> Hi Chris. Is this exactly what I'm hitting at
> https://bugs.freedesktop.org/show_bug.cgi?id=111500 perhaps?
>
> It reliably breaks the graphics userland, as the machine consistently
> freezes at any random moment.
>
> Any workaround options, even if with a performance penalty? Revert
> cb6d7c7dc7ff but side effects?
>
> 5.3 has useful NVMe power mgmt updates for laptops, I'd like to stick
> with the newest if possible.
There's a considerable risk that many users will start seeing this
regression when 5.3 is released. I am not aware of a workaround.
Is there an alternative to reverting aa56a292ce62 ("drm/i915/userptr:
Acquire the page lock around set_page_dirty()")? And if we do, what
would be the consequences? Would other patches need to be reverted,
too?
Thanks,
Martin
[Intel-gfx] [PATCH] drm/i915/selftests: Keep the engine awake while we keep for preemption
Keep the engine awake to ensure that we don't inject any pm-idle
requests.
References: https://bugs.freedesktop.org/show_bug.cgi?id=08
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d791158988d6..26d05bd1bdc8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -897,6 +897,10 @@ static int live_suppress_self_preempt(void *arg)
if (!intel_engine_has_preemption(engine))
continue;
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ goto err_wedged;
+
+ intel_engine_pm_get(engine);
engine->execlists.preempt_hang.count = 0;
rq_a = spinner_create_request(,
@@ -904,12 +908,14 @@ static int live_suppress_self_preempt(void *arg)
MI_NOOP);
if (IS_ERR(rq_a)) {
err = PTR_ERR(rq_a);
+ intel_engine_pm_put(engine);
goto err_client_b;
}
i915_request_add(rq_a);
if (!igt_wait_for_spinner(, rq_a)) {
pr_err("First client failed to start\n");
+ intel_engine_pm_put(engine);
goto err_wedged;
}
@@ -921,6 +927,7 @@ static int live_suppress_self_preempt(void *arg)
MI_NOOP);
if (IS_ERR(rq_b)) {
err = PTR_ERR(rq_b);
+ intel_engine_pm_put(engine);
goto err_client_b;
}
i915_request_add(rq_b);
@@ -931,6 +938,7 @@ static int live_suppress_self_preempt(void *arg)
if (!igt_wait_for_spinner(, rq_b)) {
pr_err("Second client failed to start\n");
+ intel_engine_pm_put(engine);
goto err_wedged;
}
@@ -944,10 +952,12 @@ static int live_suppress_self_preempt(void *arg)
engine->name,
engine->execlists.preempt_hang.count,
depth);
+ intel_engine_pm_put(engine);
err = -EINVAL;
goto err_client_b;
}
+ intel_engine_pm_put(engine);
if (igt_flush_test(i915, I915_WAIT_LOCKED))
goto err_wedged;
}
--
2.23.0
___
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Re: [Intel-gfx] [PATCH v6 01/10] drm/i915/dsb: feature flag added for display state buffer.
On 9/12/2019 12:41 AM, Animesh Manna wrote:
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2ea11123e933..6c6af007f29d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1863,6 +1863,8 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
INTEL_INFO(dev_priv)->gen == (n))
+#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
+
/*
* Return true if revision is in range [since,until] inclusive.
*
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 92e0c2e0954c..e206f298f48e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -135,6 +135,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
Looks good to me,
Feel free to use: Reviewed-by: Shashank Sharma
- Shashank
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Mdev: support mutiple kinds of devices
== Series Details ==
Series: Mdev: support mutiple kinds of devices
URL : https://patchwork.freedesktop.org/series/66588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6877 -> Patchwork_14376
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14376:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_close_race@basic-threads:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/fi-tgl-u/igt@gem_close_r...@basic-threads.html
Known issues
Here are the changes found in Patchwork_14376 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][2] -> [INCOMPLETE][3] ([fdo#107713] /
[fdo#108569])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][4] -> [DMESG-WARN][5] ([fdo#107724]) +2
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
Possible fixes
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][6] ([fdo#107718]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/fi-blb-e6850/igt@i915_module_l...@reload.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_execlists:
- {fi-kbl-soraka}:[DMESG-FAIL][8] ([fdo#08]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][10] ([fdo#111096]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_busy@basic-wait-after-default:
- fi-icl-u3: [DMESG-WARN][12] ([fdo#107724]) -> [PASS][13] +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6877/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (53 -> 47)
--
Additional (2): fi-tgl-u fi-tgl-u2
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6877 -> Patchwork_14376
CI-20190529: 20190529
CI_DRM_6877: 3b81bdb5c914e9bd1dc870ec0696fd6c7c867878 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14376: 1029a6c22da143dddb882b2d6eb40add5afa0f93 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1029a6c22da1 mdev: introduce device specific ops
6368bc7c0c50 mdev: device id support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14376/
___
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Re: [Intel-gfx] 5.3-rc3: Frozen graphics with kcompactd migrating i915 pages
On Thu, Sep 12, 2019 at 12:51 PM Martin Wilck wrote:
>
> Is there an alternative to reverting aa56a292ce62 ("drm/i915/userptr:
> Acquire the page lock around set_page_dirty()")? And if we do, what
> would be the consequences? Would other patches need to be reverted,
> too?
Looking at that commit, and the backtrace of the lockup, I think that
reverting it is the correct thing to do.
You can't take the page lock in invalidate_range(), since it's called
from try_to_unmap(), which is called with the page lock already held.
So commit aa56a292ce62 is just fundamentally completely wrong and
should be reverted.
Linus
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Ensure the context is reloaded after a GPU reset
Quoting Mika Kuoppala (2019-09-12 12:53:01) > Chris Wilson writes: > > > After we manipulate the context to allow replay after a GPU reset, force > > that context to be reloaded. This should be a layer of paranoia, for if > > the GPU was reset, the context will no longer be resident! > > > > Signed-off-by: Chris Wilson > > Cc: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > > b/drivers/gpu/drm/i915/gt/intel_lrc.c > > index dbc90da2341a..47d766ccea71 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > > @@ -2445,6 +2445,7 @@ static void __execlists_reset(struct intel_engine_cs > > *engine, bool stalled) > > intel_ring_update_space(ce->ring); > > __execlists_reset_reg_state(ce, engine); > > __execlists_update_reg_state(ce, engine); > > + ce->lrc_desc |= CTX_DESC_FORCE_RESTORE; /* paranoid: GPU was > > reset! */ > > The CCID should be reset also, but I see no harm to be explicit. Yeah, I think it's developing into a healthy enough pattern. If we ever manipulate anything inside the image itself, we should probably force the restore. A bit more mulling over that, I like the current comment :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: 5.3-rc3: Frozen graphics with kcompactd migrating i915 pages
On Thu, Sep 12, 2019 at 11:23:09AM +, Martin Wilck wrote:
>
> There's a considerable risk that many users will start seeing this
> regression when 5.3 is released. I am not aware of a workaround.
>
> Is there an alternative to reverting aa56a292ce62 ("drm/i915/userptr:
> Acquire the page lock around set_page_dirty()")? And if we do, what
> would be the consequences? Would other patches need to be reverted,
> too?
I've been running with revert patch for a couple of days and have not
encountered any kernel warnings thus far, nor any other ill effects that
could be attributed to this locking mechanism.
But I'm far from familiar with these subsystems.
Graphics does not hang anymore.
I've also received developer feedback in private that this really should
be fixed before 5.3 release.
--
Leho Kraav, senior technology & digital marketing architect
