Re: [Intel-gfx] [Nouveau] [PATCH v6 08/17] drm/ttm: use gem vma_node
On Wed, 11 Sep 2019 at 07:53, Thierry Reding wrote:
>
> On Sat, Sep 07, 2019 at 09:58:46PM -0400, Ilia Mirkin wrote:
> > On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding
> > wrote:
> > >
> > > On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote:
> > > > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote:
> > > > >
> > > > > Hi,
> > > > >
> > > > > > > Changing the order doesn't look hard. Patch attached (untested,
> > > > > > > have no
> > > > > > > test hardware). But maybe I missed some detail ...
> > > > > >
> > > > > > I came up with something very similar by splitting up
> > > > > > nouveau_bo_new()
> > > > > > into allocation and initialization steps, so that when necessary
> > > > > > the GEM
> > > > > > object can be initialized in between. I think that's slightly more
> > > > > > flexible and easier to understand than a boolean flag.
> > > > >
> > > > > Yes, that should work too.
> > > > >
> > > > > Acked-by: Gerd Hoffmann
> > > > Acked-by: Ben Skeggs
> > >
> > > Thanks guys, applied to drm-misc-next.
> >
> > Hi Thierry,
> >
> > Initial investigations suggest that this commit currently in drm-next
> >
> > commit 019cbd4a4feb3aa3a917d78e7110e3011bbff6d5
> > Author: Thierry Reding
> > Date: Wed Aug 14 11:00:48 2019 +0200
> >
> > drm/nouveau: Initialize GEM object before TTM object
> >
> > breaks nouveau userspace which tries to allocate GEM objects with a
> > non-page-aligned size. Previously nouveau_gem_new would just call
> > nouveau_bo_init which would call nouveau_bo_fixup_align before
> > initializing the GEM object. With this change, it is done after. What
> > do you think -- OK to just move that bit of logic into the new
> > nouveau_bo_alloc() (and make size/align be pointers so that they can
> > be fixed up?)
>
> Hi Ilia,
>
> sorry, got side-tracked earlier and forgot to send this out. I'll turn
> this into a proper patch, but if you manage to find the time to test
> this while I work out the userspace issues that are preventing me from
> testing this more thoroughly, that'd be great.
I can confirm both I can reproduce the bug, and that the fix here
appears to do the trick nicely.
Ben.
>
> Thierry
>
> --- >8 ---
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
> b/drivers/gpu/drm/nouveau/nouveau_bo.c
> index e918b437af17..7d5ede756711 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> @@ -186,8 +186,8 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
> }
>
> struct nouveau_bo *
> -nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32 flags, u32 tile_mode,
> -u32 tile_flags)
> +nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags,
> +u32 tile_mode, u32 tile_flags)
> {
> struct nouveau_drm *drm = cli->drm;
> struct nouveau_bo *nvbo;
> @@ -195,8 +195,8 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32
> flags, u32 tile_mode,
> struct nvif_vmm *vmm = cli->svm.cli ? >svm.vmm : >vmm.vmm;
> int i, pi = -1;
>
> - if (!size) {
> - NV_WARN(drm, "skipped size %016llx\n", size);
> + if (!*size) {
> + NV_WARN(drm, "skipped size %016llx\n", *size);
> return ERR_PTR(-EINVAL);
> }
>
> @@ -266,7 +266,7 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32
> flags, u32 tile_mode,
> pi = i;
>
> /* Stop once the buffer is larger than the current page size.
> */
> - if (size >= 1ULL << vmm->page[i].shift)
> + if (*size >= 1ULL << vmm->page[i].shift)
> break;
> }
>
> @@ -281,6 +281,8 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32
> flags, u32 tile_mode,
> }
> nvbo->page = vmm->page[pi].shift;
>
> + nouveau_bo_fixup_align(nvbo, flags, align, size);
> +
> return nvbo;
> }
>
> @@ -292,12 +294,11 @@ nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int
> align, u32 flags,
> size_t acc_size;
> int ret;
>
> - acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
> -
> - nouveau_bo_fixup_align(nvbo, flags, , );
> nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
> nouveau_bo_placement_set(nvbo, flags, 0);
>
> + acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
> +
> ret = ttm_bo_init(nvbo->bo.bdev, >bo, size, type,
> >placement, align >> PAGE_SHIFT, false,
> acc_size, sg, robj, nouveau_bo_del_ttm);
> @@ -318,7 +319,8 @@ nouveau_bo_new(struct nouveau_cli *cli, u64 size, int
> align,
> struct nouveau_bo *nvbo;
> int ret;
>
> - nvbo = nouveau_bo_alloc(cli, size, flags, tile_mode, tile_flags);
> + nvbo = nouveau_bo_alloc(cli, , , flags, tile_mode,
> + tile_flags);
> if (IS_ERR(nvbo))
> return PTR_ERR(nvbo);
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Show the logical context ring state on dumping
== Series Details ==
Series: series starting with [1/2] drm/i915: Show the logical context ring
state on dumping
URL : https://patchwork.freedesktop.org/series/66729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6896 -> Patchwork_14416
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/
New tests
-
New tests have been introduced between CI_DRM_6896 and Patchwork_14416:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_lrc:
- Statuses : 44 pass(s)
- Exec time: [0.38, 1.37] s
Known issues
Here are the changes found in Patchwork_14416 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#106070] /
[fdo#111514])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111096])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u2}:[FAIL][5] ([fdo#111562] / [fdo#111597]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][7] ([fdo#102505] / [fdo#110390]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- {fi-icl-u4}:[FAIL][9] ([fdo#111045]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#55]: https://bugs.freedesktop.org/show_bug.cgi?id=55
[fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6896 -> Patchwork_14416
CI-20190529: 20190529
CI_DRM_6896: 666925d1b342cca839902dd418eea383e69f373e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5183: 6ddc1a143495baa68dbc909f2a8819ec03c31c8e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14416: 02b6497df0ad653dcd85aba401a7c069d0adb8e8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
02b6497df0ad drm/i915/selftests: Verify the LRC register layout between init
and HW
d33259a24579 drm/i915: Show the logical context ring state on dumping
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14416/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Show the logical context ring state on dumping
== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping URL : https://patchwork.freedesktop.org/series/66729/ State : warning == Summary == $ dim checkpatch origin/drm-tip d33259a24579 drm/i915: Show the logical context ring state on dumping 02b6497df0ad drm/i915/selftests: Verify the LRC register layout between init and HW -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:474: +#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) -:62: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #62: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:475: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #62: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:475: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) total: 1 errors, 0 warnings, 2 checks, 1125 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Verify the LRC register layout between init and HW
Before we submit the first context to HW, we need to construct a valid
image of the register state. This layout is defined by the HW and should
match the layout generated by HW when it saves the context image.
Asserting that this should be equivalent should help avoid any undefined
behaviour and verify that we haven't missed anything important!
Of course, having insisted that the initial register state within the
LRC should match that returned by HW, we need to ensure that it does.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 669 --
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 62 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 142
drivers/gpu/drm/i915/i915_perf.c | 35 +-
drivers/gpu/drm/i915/i915_perf.h | 5 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 649 insertions(+), 267 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index f1c0e5d958f3..3eb3c4fab110 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1115,7 +1115,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq,
offset = i915_ggtt_offset(ce->state) +
LRC_STATE_PN * PAGE_SIZE +
-(CTX_R_PWR_CLK_STATE + 1) * 4;
+CTX_R_PWR_CLK_STATE * 4;
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = lower_32_bits(offset);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a3f0e4999744..cdbaf46a7847 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -230,9 +230,10 @@ static int __execlists_context_alloc(struct intel_context
*ce,
struct intel_engine_cs *engine);
static void execlists_init_reg_state(u32 *reg_state,
-struct intel_context *ce,
-struct intel_engine_cs *engine,
-struct intel_ring *ring);
+const struct intel_context *ce,
+const struct intel_engine_cs *engine,
+const struct intel_ring *ring,
+bool close);
static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
{
@@ -464,6 +465,411 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
return desc;
}
+static u32 *set_offsets(u32 *regs,
+ const u8 *data,
+ const struct intel_engine_cs *engine)
+#define NOP(x) (BIT(7) | (x))
+#define LRI(count, flags) ((flags) << 6 | (count))
+#define POSTED BIT(0)
+#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
+#define REG16(x) \
+ (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \
+ (((x) >> 2) & 0x7f)
+#define END() 0
+{
+ const u32 base = engine->mmio_base;
+
+ while (*data) {
+ u8 count, flags;
+
+ if (*data & BIT(7)) { /* skip */
+ regs += *data++ & ~BIT(7);
+ continue;
+ }
+
+ count = *data & 0x3f;
+ flags = *data >> 6;
+ data++;
+
+ *regs = MI_LOAD_REGISTER_IMM(count);
+ if (flags & POSTED)
+ *regs |= MI_LRI_FORCE_POSTED;
+ if (INTEL_GEN(engine->i915) >= 11)
+ *regs |= MI_LRI_CS_MMIO;
+ regs++;
+
+ GEM_BUG_ON(!count);
+ do {
+ u32 offset = 0;
+ u8 v;
+
+ do {
+ v = *data++;
+ offset <<= 7;
+ offset |= v & ~BIT(7);
+ } while (v & BIT(7));
+
+ *regs = base + (offset << 2);
+ regs += 2;
+ } while (--count);
+ }
+
+ return regs;
+}
+
+static const u8 gen8_xcs_offsets[] = {
+ NOP(1),
+ LRI(11, 0),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x11c),
+ REG(0x114),
+ REG(0x118),
+
+ NOP(9),
+ LRI(9, 0),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(13),
+ LRI(2, 0),
+ REG16(0x200),
+ REG(0x028),
+
+ END(),
+};
+
+static const u8 gen9_xcs_offsets[] = {
+ NOP(1),
+
[Intel-gfx] [PATCH 1/2] drm/i915: Show the logical context ring state on dumping
Include the active context register state when dumping the engine.
Suggested-by: Mika Kuoppala
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index a8014c59b388..3c176b0f4b45 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1404,6 +1404,11 @@ void intel_engine_dump(struct intel_engine_cs *engine,
rq->timeline->hwsp_offset);
print_request_ring(m, rq);
+
+ if (rq->hw_context->lrc_reg_state) {
+ drm_printf(m, "Logical Ring Context:\n");
+ hexdump(m, rq->hw_context->lrc_reg_state, PAGE_SIZE);
+ }
}
spin_unlock_irqrestore(>active.lock, flags);
--
2.23.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
== Series Details ==
Series: series starting with [1/2] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/66726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6896 -> Patchwork_14415
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/
Known issues
Here are the changes found in Patchwork_14415 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-ilk-650: [PASS][1] -> [DMESG-WARN][2] ([fdo#106387])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-ilk-650/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-ilk-650/igt@debugfs_test@read_all_entries.html
* igt@gem_mmap_gtt@basic-write-no-prefault:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [PASS][5] -> [FAIL][6] ([fdo#103375]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109483] / [fdo#109635 ])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#109483])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][11] -> [FAIL][12] ([fdo#111407])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u2}:[FAIL][13] ([fdo#111562] / [fdo#111597]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
* igt@kms_chamelium@hdmi-edid-read:
- {fi-icl-u4}:[FAIL][15] ([fdo#111045]) -> [PASS][16] +1 similar
issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14415/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
Participating hosts (52 -> 43)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-snb-2520m fi-icl-y
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
== Series Details ==
Series: series starting with [1/2] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/66726/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f54627385b19 dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0fc89b6802ba ("dma-fence: Simply
wrap dma_fence_signal_locked with dma_fence_signal")'
#14:
See also 0fc89b6802ba ("dma-fence: Simply wrap dma_fence_signal_locked
total: 1 errors, 0 warnings, 0 checks, 24 lines checked
2e450b7867f5 drm/mm: Pack allocated/scanned boolean into a bitfield
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do so. This ensure that should an implementation be trying
to flush the cb_list (by signaling) on retirement before freeing the
fence, it can do so in a race-free manner.
See also 0fc89b6802ba ("dma-fence: Simply wrap dma_fence_signal_locked
with dma_fence_signal").
Signed-off-by: Chris Wilson
---
drivers/dma-buf/dma-fence.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 2c136aee3e79..587727089134 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -285,19 +285,18 @@ void dma_fence_enable_sw_signaling(struct dma_fence
*fence)
{
unsigned long flags;
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
+ return;
+
+ spin_lock_irqsave(fence->lock, flags);
if (!test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
>flags) &&
- !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags) &&
fence->ops->enable_signaling) {
trace_dma_fence_enable_signal(fence);
-
- spin_lock_irqsave(fence->lock, flags);
-
if (!fence->ops->enable_signaling(fence))
dma_fence_signal_locked(fence);
-
- spin_unlock_irqrestore(fence->lock, flags);
}
+ spin_unlock_irqrestore(fence->lock, flags);
}
EXPORT_SYMBOL(dma_fence_enable_sw_signaling);
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/mm: Pack allocated/scanned boolean into a bitfield
The ulterior motive to switching the booleans over to bitops is to
allow use of the allocated flag as a bitlock.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_mm.c | 36 +++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 6 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 16 -
drivers/gpu/drm/i915/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 4 +--
drivers/gpu/drm/selftests/test-drm_mm.c | 14
drivers/gpu/drm/vc4/vc4_crtc.c| 2 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
drivers/gpu/drm/vc4/vc4_plane.c | 4 +--
include/drm/drm_mm.h | 7 ++--
12 files changed, 52 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 4581c5387372..211967006cec 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -174,7 +174,7 @@ static void drm_mm_interval_tree_add_node(struct
drm_mm_node *hole_node,
node->__subtree_last = LAST(node);
- if (hole_node->allocated) {
+ if (drm_mm_node_allocated(hole_node)) {
rb = _node->rb;
while (rb) {
parent = rb_entry(rb, struct drm_mm_node, rb);
@@ -424,9 +424,9 @@ int drm_mm_reserve_node(struct drm_mm *mm, struct
drm_mm_node *node)
node->mm = mm;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
list_add(>node_list, >node_list);
drm_mm_interval_tree_add_node(hole, node);
- node->allocated = true;
node->hole_size = 0;
rm_hole(hole);
@@ -543,9 +543,9 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm,
node->color = color;
node->hole_size = 0;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
list_add(>node_list, >node_list);
drm_mm_interval_tree_add_node(hole, node);
- node->allocated = true;
rm_hole(hole);
if (adj_start > hole_start)
@@ -561,6 +561,11 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm,
}
EXPORT_SYMBOL(drm_mm_insert_node_in_range);
+static inline bool drm_mm_node_scanned_block(const struct drm_mm_node *node)
+{
+ return test_bit(DRM_MM_NODE_SCANNED_BIT, >flags);
+}
+
/**
* drm_mm_remove_node - Remove a memory node from the allocator.
* @node: drm_mm_node to remove
@@ -574,8 +579,8 @@ void drm_mm_remove_node(struct drm_mm_node *node)
struct drm_mm *mm = node->mm;
struct drm_mm_node *prev_node;
- DRM_MM_BUG_ON(!node->allocated);
- DRM_MM_BUG_ON(node->scanned_block);
+ DRM_MM_BUG_ON(!drm_mm_node_allocated(node));
+ DRM_MM_BUG_ON(drm_mm_node_scanned_block(node));
prev_node = list_prev_entry(node, node_list);
@@ -584,11 +589,12 @@ void drm_mm_remove_node(struct drm_mm_node *node)
drm_mm_interval_tree_remove(node, >interval_tree);
list_del(>node_list);
- node->allocated = false;
if (drm_mm_hole_follows(prev_node))
rm_hole(prev_node);
add_hole(prev_node);
+
+ clear_bit_unlock(DRM_MM_NODE_ALLOCATED_BIT, >flags);
}
EXPORT_SYMBOL(drm_mm_remove_node);
@@ -605,7 +611,7 @@ void drm_mm_replace_node(struct drm_mm_node *old, struct
drm_mm_node *new)
{
struct drm_mm *mm = old->mm;
- DRM_MM_BUG_ON(!old->allocated);
+ DRM_MM_BUG_ON(!drm_mm_node_allocated(old));
*new = *old;
@@ -622,8 +628,7 @@ void drm_mm_replace_node(struct drm_mm_node *old, struct
drm_mm_node *new)
>holes_addr);
}
- old->allocated = false;
- new->allocated = true;
+ clear_bit_unlock(DRM_MM_NODE_ALLOCATED_BIT, >flags);
}
EXPORT_SYMBOL(drm_mm_replace_node);
@@ -731,9 +736,9 @@ bool drm_mm_scan_add_block(struct drm_mm_scan *scan,
u64 adj_start, adj_end;
DRM_MM_BUG_ON(node->mm != mm);
- DRM_MM_BUG_ON(!node->allocated);
- DRM_MM_BUG_ON(node->scanned_block);
- node->scanned_block = true;
+ DRM_MM_BUG_ON(!drm_mm_node_allocated(node));
+ DRM_MM_BUG_ON(drm_mm_node_scanned_block(node));
+ __set_bit(DRM_MM_NODE_SCANNED_BIT, >flags);
mm->scan_active++;
/* Remove this block from the node_list so that we enlarge the hole
@@ -818,8 +823,7 @@ bool drm_mm_scan_remove_block(struct drm_mm_scan *scan,
struct drm_mm_node *prev_node;
DRM_MM_BUG_ON(node->mm != scan->mm);
- DRM_MM_BUG_ON(!node->scanned_block);
- node->scanned_block = false;
+ DRM_MM_BUG_ON(!drm_mm_node_scanned_block(node));
DRM_MM_BUG_ON(!node->mm->scan_active);
node->mm->scan_active--;
@@ -837,6 +841,8 @@ bool drm_mm_scan_remove_block(struct drm_mm_scan *scan,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Exercise CS TLB invalidation
== Series Details ==
Series: drm/i915/selftests: Exercise CS TLB invalidation
URL : https://patchwork.freedesktop.org/series/66718/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6896 -> Patchwork_14414
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14414:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gtt:
- {fi-tgl-u}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-tgl-u/igt@i915_selftest@live_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-tgl-u/igt@i915_selftest@live_gtt.html
- {fi-tgl-u2}:[PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-tgl-u2/igt@i915_selftest@live_gtt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-tgl-u2/igt@i915_selftest@live_gtt.html
Known issues
Here are the changes found in Patchwork_14414 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u2}:[FAIL][9] ([fdo#111562] / [fdo#111597]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6896/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6896 -> Patchwork_14414
CI-20190529: 20190529
CI_DRM_6896: 666925d1b342cca839902dd418eea383e69f373e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5183: 6ddc1a143495baa68dbc909f2a8819ec03c31c8e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14414: ec3adb8606d48fd19de69e7ba01659115a97b654 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ec3adb8606d4 drm/i915/selftests: Exercise CS TLB invalidation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Suspend pre-parser across GTT invalidations
== Series Details == Series: drm/i915/tgl: Suspend pre-parser across GTT invalidations URL : https://patchwork.freedesktop.org/series/66703/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14413_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14413_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14413_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14413_full: ### IGT changes ### Possible regressions * igt@kms_flip@flip-vs-suspend-interruptible: - shard-snb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-snb1/igt@kms_f...@flip-vs-suspend-interruptible.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-snb5/igt@kms_f...@flip-vs-suspend-interruptible.html Known issues Here are the changes found in Patchwork_14413_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +19 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb5/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl2/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-apl4/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-skl10/igt@kms_f...@flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-snb: [PASS][13] -> [INCOMPLETE][14] ([fdo#105411]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-snb5/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-snb1/igt@kms_f...@flip-vs-suspend.html - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-hsw8/igt@kms_f...@flip-vs-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-hsw4/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb2/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-apl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#108341]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb8/igt@kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][23] -> [SKIP][24]
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise CS TLB invalidation
== Series Details == Series: drm/i915/selftests: Exercise CS TLB invalidation URL : https://patchwork.freedesktop.org/series/66718/ State : warning == Summary == $ dim checkpatch origin/drm-tip ec3adb8606d4 drm/i915/selftests: Exercise CS TLB invalidation -:208: WARNING:MEMORY_BARRIER: memory barrier without comment #208: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:1881: + wmb(); -:215: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc (sched/core.c) #215: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:1888: + yield(); -:219: WARNING:MEMORY_BARRIER: memory barrier without comment #219: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:1892: + wmb(); total: 0 errors, 3 warnings, 0 checks, 252 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Exercise CS TLB invalidation
Check that we are correctly invalidating the TLB at the start of a
batch after updating the GTT.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 227 ++
1 file changed, 227 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 598c18d10640..f8709b332bd7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -25,13 +25,16 @@
#include
#include
+#include "gem/i915_gem_context.h"
#include "gem/selftests/mock_context.h"
+#include "gt/intel_context.h"
#include "i915_random.h"
#include "i915_selftest.h"
#include "mock_drm.h"
#include "mock_gem_device.h"
+#include "igt_flush_test.h"
static void cleanup_freed_objects(struct drm_i915_private *i915)
{
@@ -1705,6 +1708,229 @@ int i915_gem_gtt_mock_selftests(void)
return err;
}
+static int context_sync(struct intel_context *ce)
+{
+ struct i915_request *rq;
+ long timeout;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ timeout = i915_request_wait(rq, 0, HZ / 5);
+ i915_request_put(rq);
+
+ return timeout < 0 ? -EIO : 0;
+}
+
+static int submit_batch(struct intel_context *ce, u64 addr)
+{
+ struct i915_request *rq;
+ int err;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ err = 0;
+ if (rq->engine->emit_init_breadcrumb) /* detect a hang */
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err == 0)
+ err = rq->engine->emit_bb_start(rq, addr, 0, 0);
+
+ i915_request_add(rq);
+
+ return err;
+}
+
+static int igt_cs_tlb(void *arg)
+{
+ const unsigned int count = PAGE_SIZE / 64;
+ const unsigned int chunk_size = count * PAGE_SIZE;
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *bbe, *out;
+ struct i915_gem_engines_iter it;
+ struct i915_address_space *vm;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct drm_file *file;
+ struct i915_vma *vma;
+ unsigned int i;
+ u32 *result;
+ u32 *batch;
+ int err = 0;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ mutex_lock(>drm.struct_mutex);
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out_unlock;
+ }
+
+ vm = ctx->vm;
+ if (!vm)
+ goto out_unlock;
+
+ bbe = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(bbe)) {
+ err = PTR_ERR(bbe);
+ goto out_unlock;
+ }
+
+ batch = i915_gem_object_pin_map(bbe, I915_MAP_WC);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_bbe;
+ }
+ for (i = 0; i < count; i++) {
+ u32 *cs = batch + i * 64 / sizeof(*cs);
+ u64 addr = (vm->total - PAGE_SIZE) + i * sizeof(u32);
+
+ GEM_BUG_ON(INTEL_GEN(i915) < 6);
+ cs[0] = MI_STORE_DWORD_IMM_GEN4;
+ if (INTEL_GEN(i915) >= 8) {
+ cs[1] = lower_32_bits(addr);
+ cs[2] = upper_32_bits(addr);
+ cs[3] = i;
+ cs[4] = MI_NOOP;
+ cs[5] = MI_BATCH_BUFFER_START_GEN8;
+ } else {
+ cs[1] = 0;
+ cs[2] = lower_32_bits(addr);
+ cs[3] = i;
+ cs[4] = MI_NOOP;
+ cs[5] = MI_BATCH_BUFFER_START;
+ }
+ }
+
+ out = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(out)) {
+ err = PTR_ERR(out);
+ goto out_batch;
+ }
+ i915_gem_object_set_cache_coherency(out, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(out, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_batch;
+ }
+
+ err = i915_vma_pin(vma, 0, 0,
+ PIN_USER |
+ PIN_OFFSET_FIXED |
+ (vm->total - PAGE_SIZE));
+ if (err)
+ goto out_out;
+ GEM_BUG_ON(vma->node.start != vm->total - PAGE_SIZE);
+
+ result = i915_gem_object_pin_map(out, I915_MAP_WB);
+ if (IS_ERR(result)) {
+ err = PTR_ERR(result);
+ goto out_out;
+ }
+
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ IGT_TIMEOUT(end_time);
+ unsigned long pass = 0;
+
+
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
== Series Details == Series: series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66701/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14412_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14412_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +14 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@gem_exec_sched...@preempt-contexts-bsd2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-iclb7/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([fdo#105763] / [fdo#106538]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-glk7/igt@i915_pm_...@modeset-stress-extra-wait.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-glk8/igt@i915_pm_...@modeset-stress-extra-wait.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-snb5/igt@kms_cursor_...@pipe-b-cursor-alpha-transparent.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-snb7/igt@kms_cursor_...@pipe-b-cursor-alpha-transparent.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#105767]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-glk2/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@basic-flip-vs-modeset: - shard-apl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103927]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl7/igt@kms_f...@basic-flip-vs-modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-apl3/igt@kms_f...@basic-flip-vs-modeset.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-apl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-skl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14412/shard-skl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166])
Re: [Intel-gfx] [PATCH 3/3] drm/i915/perf: Add the report format with a non-power-of-2 size
On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote:
Add the report format with size that is not a power of 2. This allows
use of all report formats defined in hardware.
Move the format definition to end to avoid breaking API (Lionel)
Signed-off-by: Umesh Nerlige Ramappa
I think that like any change to the uAPI should be versioned so an
application can know what's available without trying to open the stream
to test whether a given parameter is available.
I would pull the patch in the link before this one :
https://patchwork.freedesktop.org/patch/329723/?series=66418=1
And bump the version number to 2 in this patch.
Cheers,
-Lionel
---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
include/uapi/drm/i915_drm.h | 11 ++-
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 482fca3da7de..781fc5892493 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -312,11 +312,11 @@ static const struct i915_oa_format
hsw_oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A13]= { 0, 64 },
[I915_OA_FORMAT_A29]= { 1, 128 },
[I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
- /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
[I915_OA_FORMAT_B4_C8] = { 4, 64 },
[I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
[I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
[I915_OA_FORMAT_C4_B8] = { 7, 64 },
+ [I915_OA_FORMAT_A29_B8_C8] = { 3, 192 },
};
static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 469dc512cca3..4e2d4e492b06 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1829,12 +1829,13 @@ enum drm_i915_oa_format {
I915_OA_FORMAT_B4_C8, /* HSW only */
I915_OA_FORMAT_A45_B8_C8, /* HSW only */
I915_OA_FORMAT_B4_C8_A16, /* HSW only */
- I915_OA_FORMAT_C4_B8, /* HSW+ */
+ I915_OA_FORMAT_C4_B8, /* HSW only */
- /* Gen8+ */
- I915_OA_FORMAT_A12,
- I915_OA_FORMAT_A12_B8_C8,
- I915_OA_FORMAT_A32u40_A4u32_B8_C8,
+ I915_OA_FORMAT_A12, /* Gen8+ */
+ I915_OA_FORMAT_A12_B8_C8, /* Gen8+ */
+ I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Gen8+ */
+
+ I915_OA_FORMAT_A29_B8_C8, /* HSW only */
I915_OA_FORMAT_MAX /* non-ABI */
};
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915/perf: Add support for report sizes that are not power of 2
On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote:
OA perf unit supports non-power of 2 report sizes. Enable support for
these sizes in the driver.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 59
1 file changed, 21 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 50b6d154fd46..482fca3da7de 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -450,7 +450,7 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
int report_size = stream->oa_buffer.format_size;
unsigned long flags;
- u32 hw_tail;
+ u32 hw_tail, aging_tail;
u64 now;
/* We have to consider the (unlikely) possibility that read() errors
@@ -459,16 +459,17 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
*/
spin_lock_irqsave(>oa_buffer.ptr_lock, flags);
- hw_tail = dev_priv->perf.ops.oa_hw_tail_read(stream);
+ hw_tail = dev_priv->perf.ops.oa_hw_tail_read(stream) - gtt_offset;
+ aging_tail = stream->oa_buffer.aging_tail - gtt_offset;
/* The tail pointer increases in 64 byte increments,
* not in report_size steps...
*/
- hw_tail &= ~(report_size - 1);
+ hw_tail = OA_TAKEN(hw_tail, (OA_TAKEN(hw_tail, aging_tail) %
report_size));
I'm struggling to parse this line above and I'm not 100% sure it's correct.
Could add a comment to explain what is going on?
Thanks,
-Lionel
now = ktime_get_mono_fast_ns();
- if (hw_tail == stream->oa_buffer.aging_tail) {
+ if (hw_tail == aging_tail) {
/* If the HW tail hasn't move since the last check and the HW
* tail has been aging for long enough, declare it the new
* tail.
@@ -486,8 +487,6 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
* a read() in progress.
*/
head = stream->oa_buffer.head - gtt_offset;
-
- hw_tail -= gtt_offset;
tail = hw_tail;
/* Walk the stream backward until we find at least 2 reports
@@ -613,7 +612,18 @@ static int append_oa_sample(struct i915_perf_stream
*stream,
buf += sizeof(header);
if (sample_flags & SAMPLE_OA_REPORT) {
- if (copy_to_user(buf, report, report_size))
+ u8 *oa_buf_end = stream->oa_buffer.vaddr + OA_BUFFER_SIZE;
+ int report_size_partial = oa_buf_end - report;
+
+ if (report_size_partial < report_size) {
+ if (copy_to_user(buf, report, report_size_partial))
+ return -EFAULT;
+ buf += report_size_partial;
+
+ if (copy_to_user(buf, stream->oa_buffer.vaddr,
+ report_size - report_size_partial))
+ return -EFAULT;
+ } else if (copy_to_user(buf, report, report_size))
return -EFAULT;
}
@@ -682,8 +692,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* only be incremented by multiples of the report size (notably also
* all a power of two).
*/
- if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
- tail > OA_BUFFER_SIZE || tail % report_size,
+ if (WARN_ONCE(head > OA_BUFFER_SIZE ||
+ tail > OA_BUFFER_SIZE,
"Inconsistent OA buffer pointers: head = %u, tail = %u\n",
head, tail))
return -EIO;
@@ -697,20 +707,6 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
u32 ctx_id;
u32 reason;
- /*
-* All the report sizes factor neatly into the buffer
-* size so we never expect to see a report split
-* between the beginning and end of the buffer.
-*
-* Given the initial alignment check a misalignment
-* here would imply a driver bug that would result
-* in an overrun.
-*/
- if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
- DRM_ERROR("Spurious OA head ptr: non-integral report
offset\n");
- break;
- }
-
/*
* The reason field includes flags identifying what
* triggered this specific report (mostly timer
@@ -956,8 +952,8 @@ static int gen7_append_oa_reports(struct i915_perf_stream
*stream,
* only be incremented by multiples of the report size (notably also
* all a power of two).
*/
- if (WARN_ONCE(head > OA_BUFFER_SIZE || head %
Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: rework aging tail workaround
On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
Right now the workaround against the OA tail pointer race condition
requires at least twice the internal kernel polling timer to make any
data available.
This changes introduce checks on the OA data written into the circular
buffer to make as much data as possible available on the first
iteration of the polling timer.
v2: Use OA_TAKEN macro without the gtt_offset (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 30 ++---
drivers/gpu/drm/i915/i915_perf.c | 200 ++-
2 files changed, 103 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf600888b3f1..876aeaf3568e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1180,21 +1180,11 @@ struct i915_perf_stream {
spinlock_t ptr_lock;
/**
-* One 'aging' tail pointer and one 'aged' tail pointer ready to
-* used for reading.
-*
-* Initial values of 0x are invalid and imply that an
-* update is required (and should be ignored by an attempted
-* read)
-*/
- struct {
- u32 offset;
- } tails[2];
-
- /**
-* Index for the aged tail ready to read() data up to.
+* The last HW tail reported by HW. The data
+* might not have made it to memory yet
+* though.
*/
- unsigned int aged_tail_idx;
+ u32 aging_tail;
/**
* A monotonic timestamp for when the current aging tail pointer
@@ -1210,6 +1200,12 @@ struct i915_perf_stream {
* OA buffer data to userspace.
*/
u32 head;
+
+ /**
+* The last verified tail that can be read
+* by user space
+*/
+ u32 tail;
} oa_buffer;
};
@@ -1693,6 +1689,12 @@ struct drm_i915_private {
*/
struct ratelimit_state spurious_report_rs;
+ /**
+* For rate limiting any notifications of tail pointer
+* race.
+*/
+ struct ratelimit_state tail_pointer_race;
+
struct i915_oa_config test_config;
u32 gen7_latched_oastatus1;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c1b764233761..50b6d154fd46 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -237,23 +237,14 @@
* for this earlier, as part of the oa_buffer_check to avoid lots of redundant
* read() attempts.
*
- * In effect we define a tail pointer for reading that lags the real tail
- * pointer by at least %OA_TAIL_MARGIN_NSEC nanoseconds, which gives enough
- * time for the corresponding reports to become visible to the CPU.
- *
- * To manage this we actually track two tail pointers:
- * 1) An 'aging' tail with an associated timestamp that is tracked until we
- * can trust the corresponding data is visible to the CPU; at which point
- * it is considered 'aged'.
- * 2) An 'aged' tail that can be used for read()ing.
- *
- * The two separate pointers let us decouple read()s from tail pointer aging.
- *
- * The tail pointers are checked and updated at a limited rate within a hrtimer
- * callback (the same callback that is used for delivering EPOLLIN events)
- *
- * Initially the tails are marked invalid with %INVALID_TAIL_PTR which
- * indicates that an updated tail pointer is needed.
+ * We workaround this issue in oa_buffer_check() by reading the reports in the
+ * OA buffer, starting from the tail reported by the HW until we find 2
+ * consecutive reports with their first 2 dwords of not at 0. Those dwords are
+ * also set to 0 once read and the whole buffer is cleared upon OA buffer
+ * initialization. The first dword is the reason for this report while the
+ * second is the timestamp, making the chances of having those 2 fields at 0
+ * fairly unlikely. A more detailed explanation is available in
+ * oa_buffer_check().
*
* Most of the implementation details for this workaround are in
* oa_buffer_check_unlocked() and _append_oa_reports()
@@ -266,7 +257,6 @@
* enabled without any periodic sampling.
*/
#define OA_TAIL_MARGIN_NSEC 10ULL
-#define INVALID_TAIL_PTR 0x
/* frequency for checking whether the OA unit has written new reports to the
* circular OA buffer...
@@ -457,10 +447,10 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream
*stream)
static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
+ u32 gtt_offset =
[Intel-gfx] [PATCH i-g-t] igt/kms_frontbuffer_tracking: Skip over IGT_DRAW_BLT when there's no BLT
If the blitter is not available, we cannot use it as a source for dirty
rectangles. We shall have to rely on the other engines to create GPU
dirty instead.
v2: Try using lots of subgroup+fixtures
Signed-off-by: Chris Wilson
---
tests/kms_frontbuffer_tracking.c | 58 ++--
1 file changed, 56 insertions(+), 2 deletions(-)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index c788b59ee..eaa4b6ef1 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -3022,6 +3022,9 @@ static void basic_subtest(const struct test_mode *t)
fb1 = params->primary.fb;
for (r = 0, method = 0; method < IGT_DRAW_METHOD_COUNT; method++, r++) {
+ if (method == IGT_DRAW_BLT && !gem_has_blitter(drm.fd))
+ continue;
+
if (r == pattern->n_rects) {
params->primary.fb = (params->primary.fb == fb1) ?
: fb1;
@@ -3248,10 +3251,11 @@ static const char *flip_str(enum flip_type flip)
continue; \
if (!opt.show_hidden && t.fbs == FBS_SHARED && \
(t.plane == PLANE_CUR || t.plane == PLANE_SPR))\
- continue;
+ continue; \
+ igt_subtest_group {
-#define TEST_MODE_ITER_END } } } } } }
+#define TEST_MODE_ITER_END } } } } } } }
struct option long_options[] = {
{ "no-status-check", 0, 0, 's'},
@@ -3297,6 +3301,10 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
}
TEST_MODE_ITER_BEGIN(t)
+ igt_fixture {
+ if (t.method == IGT_DRAW_BLT)
+ gem_require_blitter(drm.fd);
+ }
igt_subtest_f("%s-%s-%s-%s-%s-draw-%s",
feature_str(t.feature),
pipes_str(t.pipes),
@@ -3313,6 +3321,11 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
(!opt.show_hidden && t.method != IGT_DRAW_BLT))
continue;
+ igt_fixture {
+ if (t.method == IGT_DRAW_BLT)
+ gem_require_blitter(drm.fd);
+ }
+
for (t.flip = 0; t.flip < FLIP_COUNT; t.flip++)
igt_subtest_f("%s-%s-%s-%s-%sflip-%s",
feature_str(t.feature),
@@ -3331,6 +3344,11 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
(t.feature & FEATURE_FBC) == 0)
continue;
+ igt_fixture {
+ if (t.method == IGT_DRAW_BLT)
+ gem_require_blitter(drm.fd);
+ }
+
igt_subtest_f("%s-%s-%s-fliptrack",
feature_str(t.feature),
pipes_str(t.pipes),
@@ -3344,6 +3362,11 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
t.plane == PLANE_PRI)
continue;
+ igt_fixture {
+ if (t.method == IGT_DRAW_BLT)
+ gem_require_blitter(drm.fd);
+ }
+
igt_subtest_f("%s-%s-%s-%s-%s-move",
feature_str(t.feature),
pipes_str(t.pipes),
@@ -3367,6 +3390,11 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
t.plane != PLANE_SPR)
continue;
+ igt_fixture {
+ if (t.method == IGT_DRAW_BLT)
+ gem_require_blitter(drm.fd);
+ }
+
igt_subtest_f("%s-%s-%s-%s-%s-fullscreen",
feature_str(t.feature),
pipes_str(t.pipes),
@@ -3383,6 +3411,11 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
(!opt.show_hidden && t.fbs != FBS_INDIVIDUAL))
continue;
+ igt_fixture {
+ if (t.method == IGT_DRAW_BLT)
+ gem_require_blitter(drm.fd);
+ }
+
igt_subtest_f("%s-%s-%s-%s-multidraw",
feature_str(t.feature),
pipes_str(t.pipes),
@@ -3399,6 +3432,11 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
t.method != IGT_DRAW_MMAP_GTT)
continue;
+ igt_fixture {
+ if (t.method == IGT_DRAW_BLT)
+ gem_require_blitter(drm.fd);
+ }
+
igt_subtest_f("%s-farfromfence", feature_str(t.feature))
[Intel-gfx] [PATCH i-g-t] i915: More gem_require_blitter()
Some more tests that used the less common blt interfaces.
Signed-off-by: Chris Wilson
---
tests/i915/gem_bad_reloc.c | 1 +
tests/i915/gem_caching.c | 1 +
tests/i915/gem_exec_blt.c| 1 +
tests/i915/gem_partial_pwrite_pread.c| 1 +
tests/i915/gem_pipe_control_store_loop.c | 1 +
tests/i915/gem_pwrite_pread.c| 1 +
tests/i915/gem_unfence_active_buffers.c | 1 +
tests/i915/gem_unref_active_buffers.c| 1 +
tests/i915/i915_pm_rpm.c | 1 +
9 files changed, 9 insertions(+)
diff --git a/tests/i915/gem_bad_reloc.c b/tests/i915/gem_bad_reloc.c
index 7624cd8e0..c03e5beb3 100644
--- a/tests/i915/gem_bad_reloc.c
+++ b/tests/i915/gem_bad_reloc.c
@@ -191,6 +191,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
}
for (e = intel_execution_engines; e->name; e++) {
diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index 09e1a5f97..ce9e6345f 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -114,6 +114,7 @@ igt_main
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
gem_require_caching(fd);
devid = intel_get_drm_devid(fd);
diff --git a/tests/i915/gem_exec_blt.c b/tests/i915/gem_exec_blt.c
index 94de1a82f..ffb60d0cc 100644
--- a/tests/i915/gem_exec_blt.c
+++ b/tests/i915/gem_exec_blt.c
@@ -312,6 +312,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
sysfs = igt_sysfs_open(fd);
igt_require(sysfs >= 0);
diff --git a/tests/i915/gem_partial_pwrite_pread.c
b/tests/i915/gem_partial_pwrite_pread.c
index 35e39ad7f..49e086edf 100644
--- a/tests/i915/gem_partial_pwrite_pread.c
+++ b/tests/i915/gem_partial_pwrite_pread.c
@@ -253,6 +253,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
devid = intel_get_drm_devid(fd);
diff --git a/tests/i915/gem_pipe_control_store_loop.c
b/tests/i915/gem_pipe_control_store_loop.c
index db23e33d2..b8a21d780 100644
--- a/tests/i915/gem_pipe_control_store_loop.c
+++ b/tests/i915/gem_pipe_control_store_loop.c
@@ -162,6 +162,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
devid = intel_get_drm_devid(fd);
diff --git a/tests/i915/gem_pwrite_pread.c b/tests/i915/gem_pwrite_pread.c
index 3a58eae6a..422db34d8 100644
--- a/tests/i915/gem_pwrite_pread.c
+++ b/tests/i915/gem_pwrite_pread.c
@@ -285,6 +285,7 @@ igt_main_args("s:", NULL, help_str, opt_handler, NULL)
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
dst = gem_create(fd, object_size);
src = gem_create(fd, object_size);
diff --git a/tests/i915/gem_unfence_active_buffers.c
b/tests/i915/gem_unfence_active_buffers.c
index b78fbafa7..a357ec32c 100644
--- a/tests/i915/gem_unfence_active_buffers.c
+++ b/tests/i915/gem_unfence_active_buffers.c
@@ -75,6 +75,7 @@ igt_simple_main
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
diff --git a/tests/i915/gem_unref_active_buffers.c
b/tests/i915/gem_unref_active_buffers.c
index 4fafdd048..b5d482064 100644
--- a/tests/i915/gem_unref_active_buffers.c
+++ b/tests/i915/gem_unref_active_buffers.c
@@ -58,6 +58,7 @@ igt_simple_main
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
igt_assert(bufmgr);
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 2168ff72c..f6749275a 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1266,6 +1266,7 @@ static void gem_execbuf_subtest(void)
uint32_t color;
igt_require_gem(drm_fd);
+ gem_require_blitter(drm_fd);
/* Create and set data while the device is active. */
enable_one_screen_and_wait(_data);
--
2.23.0
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: Enable non-power-of-2 OA report sizes
== Series Details == Series: drm/i915/perf: Enable non-power-of-2 OA report sizes URL : https://patchwork.freedesktop.org/series/66697/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14411_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14411_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@legacy-bsd1-heavy-queue: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl8/igt@gem_ctx_swi...@legacy-bsd1-heavy-queue.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-apl4/igt@gem_ctx_swi...@legacy-bsd1-heavy-queue.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +22 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-iclb5/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl1/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-apl1/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-render.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-x.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html * igt@tools_test@tools_test: - shard-kbl: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-kbl3/igt@tools_test@tools_test.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-kbl1/igt@tools_test@tools_test.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14411/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_eio@reset-stress: - shard-iclb:
[Intel-gfx] ✓ Fi.CI.IGT: success for TGL TC enabling
== Series Details == Series: TGL TC enabling URL : https://patchwork.freedesktop.org/series/66695/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14410_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14410_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_pwrite@big-cpu-forwards: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl6/igt@gem_pwr...@big-cpu-forwards.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-apl3/igt@gem_pwr...@big-cpu-forwards.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl6/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-apl1/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([fdo#105763] / [fdo#106538]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-glk7/igt@i915_pm_...@modeset-stress-extra-wait.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-glk8/igt@i915_pm_...@modeset-stress-extra-wait.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-glk2/igt@kms_f...@2x-flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-glk6/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip_tiling@flip-to-x-tiled: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@kms_flip_til...@flip-to-x-tiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-iclb7/igt@kms_flip_til...@flip-to-x-tiled.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-iclb7/igt@kms_psr@psr2_cursor_render.html * igt@perf@polling: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#110728]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-skl2/igt@p...@polling.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-skl8/igt@p...@polling.html * igt@prime_busy@after-bsd2: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109276]) +17 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@prime_b...@after-bsd2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14410/shard-iclb7/igt@prime_b...@after-bsd2.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +2 similar issues [25]:
