Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607
On 2019-10-01 at 13:16:11 -0700, Lucas De Marchi wrote:
> On Tue, Oct 1, 2019 at 10:36 AM Chris Wilson wrote:
> >
> > Quoting Ramalingam C (2019-10-01 18:26:23)
> > > From: Michel Thierry
> > >
> > > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > > FF_MODE2 is part of the register state context, that's why it is
> > > implemented here.
> > >
> > > v2: Rebased on top of the WA refactoring (Oscar)
> > > v3: Correctly add to ctx_workarounds_init (Michel)
> > >
> > > BSpec: 19363
> > > HSDES: 1604555607
> > > Signed-off-by: Michel Thierry
> > > Signed-off-by: Ramalingam C
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
> > > drivers/gpu/drm/i915/i915_reg.h | 5 +
> > > 2 files changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index ba65e5018978..4049b876492a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct
> > > intel_engine_cs *engine,
> > > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > struct i915_wa_list *wal)
> > > {
> > > + struct drm_i915_private *dev_priv = engine->i915;
> > > + u32 val;
> > > +
> > > /* Wa_1409142259 */
> > > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > + /* Wa_1604555607:tgl */
> > > + val = I915_READ(FF_MODE2);
> >
> > No, you can't use indiscriminate mmio access that may not match the engine
> > (engine->gt->uncore).
> >
> > But really consider doing the rmw as part of the wa.
>
> And:
> https://patchwork.freedesktop.org/patch/319952/?series=64274=1
> https://patchwork.freedesktop.org/patch/317654/?series=63670=2
>
> Please don't simply resend patches that were already reviewed.
Happy if it already getting reviewed. Before sending it, I could have confirmed
with owner of the patch. Sorry for the inconvenience. Lets drop this patch.
-Ram
>
> Lucas De Marchi
>
> >
> > > + val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > + val |= FF_MODE2_TDS_TIMER_128;
> > > + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> > > }
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Lucas De Marchi
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[Intel-gfx] ✗ Fi.CI.IGT: failure for DC3CO Support for TGL (rev14)
== Series Details == Series: DC3CO Support for TGL (rev14) URL : https://patchwork.freedesktop.org/series/64923/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6985_full -> Patchwork_14612_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14612_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14612_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14612_full: ### IGT changes ### Possible regressions * igt@gem_ctx_isolation@rcs0-s3: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb1/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-iclb2/igt@gem_ctx_isolat...@rcs0-s3.html New tests - New tests have been introduced between CI_DRM_6985_full and Patchwork_14612_full: ### New Piglit tests (8) ### * spec@arb_gpu_shader5@texturegather@fs-rgba-2-uint-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@fs-rgba-3-uint-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-0-uint-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-3-uint-2d-const: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@fs-rgba-0-uint-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@fs-rgba-1-uint-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@fs-rgba-2-uint-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@fs-rgba-3-uint-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_14612_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb2/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_flush@basic-wb-ro-before-default: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb8/igt@gem_exec_fl...@basic-wb-ro-before-default.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-iclb7/igt@gem_exec_fl...@basic-wb-ro-before-default.html * igt@gem_exec_reuse@contexts: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#109100]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb5/igt@gem_exec_re...@contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-iclb1/igt@gem_exec_re...@contexts.html * igt@gem_exec_schedule@fifo-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb6/igt@gem_exec_sched...@fifo-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-iclb2/igt@gem_exec_sched...@fifo-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_userptr_blits@dmabuf-sync: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl5/igt@gem_userptr_bl...@dmabuf-sync.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-skl4/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-kbl1/igt@gem_userptr_bl...@dmabuf-unsync.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-kbl6/igt@gem_userptr_bl...@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) [17]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/print: add and use drm_debug_enabled() (rev3)
== Series Details ==
Series: drm/print: add and use drm_debug_enabled() (rev3)
URL : https://patchwork.freedesktop.org/series/66656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6985_full -> Patchwork_14611_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14611_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_eio@kms}:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-glk6/igt@gem_...@kms.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-glk9/igt@gem_...@kms.html
Known issues
Here are the changes found in Patchwork_14611_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb2/igt@gem_exec_balan...@smoke.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-iclb8/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_reuse@contexts:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
[fdo#109100])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb5/igt@gem_exec_re...@contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-iclb7/igt@gem_exec_re...@contexts.html
* igt@gem_exec_schedule@preempt-other-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb5/igt@gem_exec_sched...@preempt-other-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-iclb4/igt@gem_exec_sched...@preempt-other-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +20 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-kbl4/igt@gem_userptr_bl...@dmabuf-sync.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-kbl6/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#109385] /
[fdo#111870]) +1 similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-apl8/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-apl3/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@sync-unmap:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl9/igt@gem_userptr_bl...@sync-unmap.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-skl10/igt@gem_userptr_bl...@sync-unmap.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665] /
[fdo#108767])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-kbl1/igt@i915_susp...@sysfs-reader.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-kbl3/igt@i915_susp...@sysfs-reader.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103232])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#103184] / [fdo#103232])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl2/igt@kms_draw_...@draw-method-xrgb2101010-mmap-cpu-untiled.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/shard-skl9/igt@kms_draw_...@draw-method-xrgb2101010-mmap-cpu-untiled.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103927])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-apl8/igt@kms_f...@flip-vs-expired-vblank.html
[24]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: split out intel_vga_client.[ch]
== Series Details == Series: drm/i915/display: split out intel_vga_client.[ch] URL : https://patchwork.freedesktop.org/series/67447/ State : success == Summary == CI Bug Log - changes from CI_DRM_6985_full -> Patchwork_14608_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14608_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb2/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +25 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-iclb3/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl4/igt@gem_soft...@noreloc-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-skl7/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-glk8/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-kbl4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-kbl7/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-iclb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#109385] / [fdo#111870]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-apl2/igt@gem_userptr_bl...@sync-unmap-after-close.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-apl2/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103232]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271] / [fdo#109278]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-snb2/igt@kms_cursor_edge_w...@pipe-b-256x256-left-edge.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/shard-snb6/igt@kms_cursor_edge_w...@pipe-b-256x256-left-edge.html * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-glk: [PASS][23] -> [FAIL][24] ([fdo#111609]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-glk3/igt@kms_f...@dpms-vs-vblank-race-interruptible.html [24]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Exercise potential false lite-restore (rev5)
== Series Details == Series: drm/i915/selftests: Exercise potential false lite-restore (rev5) URL : https://patchwork.freedesktop.org/series/67438/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14621 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14621 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14621, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14621: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - fi-skl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-guc/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-skl-guc/igt@i915_selftest@live_execlists.html - fi-cfl-guc: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-cfl-guc/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-cfl-guc/igt@i915_selftest@live_execlists.html - fi-skl-iommu: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-iommu/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-skl-iommu/igt@i915_selftest@live_execlists.html - fi-kbl-guc: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-guc/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-kbl-guc/igt@i915_selftest@live_execlists.html - fi-kbl-8809g: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-8809g/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-kbl-8809g/igt@i915_selftest@live_execlists.html - fi-glk-dsi: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-glk-dsi/igt@i915_selftest@live_execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-glk-dsi/igt@i915_selftest@live_execlists.html - fi-kbl-x1275: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-x1275/igt@i915_selftest@live_execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-kbl-x1275/igt@i915_selftest@live_execlists.html - fi-skl-6600u: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-6600u/igt@i915_selftest@live_execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-skl-6600u/igt@i915_selftest@live_execlists.html - fi-bxt-dsi: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bxt-dsi/igt@i915_selftest@live_execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-bxt-dsi/igt@i915_selftest@live_execlists.html - fi-skl-6700k2: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-6700k2/igt@i915_selftest@live_execlists.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-skl-6700k2/igt@i915_selftest@live_execlists.html - fi-skl-6260u: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-6260u/igt@i915_selftest@live_execlists.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-skl-6260u/igt@i915_selftest@live_execlists.html - fi-kbl-r: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-r/igt@i915_selftest@live_execlists.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-kbl-r/igt@i915_selftest@live_execlists.html - fi-skl-lmem:[PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-lmem/igt@i915_selftest@live_execlists.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-skl-lmem/igt@i915_selftest@live_execlists.html - fi-cfl-8109u: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-cfl-8109u/igt@i915_selftest@live_execlists.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14621/fi-cfl-8109u/igt@i915_selftest@live_execlists.html * igt@runner@aborted: - fi-cml-u2:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Describe structure members in documentation
== Series Details == Series: drm/i915: Describe structure members in documentation URL : https://patchwork.freedesktop.org/series/67442/ State : success == Summary == CI Bug Log - changes from CI_DRM_6985_full -> Patchwork_14607_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14607_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +18 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb7/igt@gem_exec_sched...@wide-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl4/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-skl7/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-kbl4/igt@gem_userptr_bl...@dmabuf-sync.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-kbl1/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-hsw1/igt@gem_userptr_bl...@sync-unmap-after-close.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-hsw8/igt@gem_userptr_bl...@sync-unmap-after-close.html - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#109385] / [fdo#111870]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-apl2/igt@gem_userptr_bl...@sync-unmap-after-close.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-apl4/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@gem_workarounds@suspend-resume-context: - shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103665]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-kbl7/igt@gem_workarou...@suspend-resume-context.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-kbl1/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-snb: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-snb1/igt@i915_pm_rc6_reside...@rc6-accuracy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-snb1/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-apl7/igt@i915_susp...@sysfs-reader.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-apl6/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103232]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen: - shard-apl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103927]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-apl3/igt@kms_cursor_...@pipe-c-cursor-128x42-onscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-apl4/igt@kms_cursor_...@pipe-c-cursor-128x42-onscreen.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#103184] / [fdo#103232]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-skl2/igt@kms_draw_...@draw-method-xrgb2101010-mmap-cpu-untiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/shard-skl3/igt@kms_draw_...@draw-method-xrgb2101010-mmap-cpu-untiled.html * igt@kms_fbcon_fbt@psr: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([fdo#106107])
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise potential false lite-restore (rev5)
== Series Details == Series: drm/i915/selftests: Exercise potential false lite-restore (rev5) URL : https://patchwork.freedesktop.org/series/67438/ State : warning == Summary == $ dim checkpatch origin/drm-tip d506cfeafc6e drm/i915/selftests: Exercise potential false lite-restore -:30: WARNING:LEADING_SPACE: please, no spaces at the start of a line #30: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:240: + mutex_acquire(>pin_mutex.dep_map, 2, 0, _RET_IP_);$ -:35: WARNING:LEADING_SPACE: please, no spaces at the start of a line #35: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:245: + mutex_release(>pin_mutex.dep_map, 0, _RET_IP_);$ total: 0 errors, 2 warnings, 0 checks, 236 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mg: Use tc_port instead of port parameter to MG registers
== Series Details ==
Series: drm/i915/mg: Use tc_port instead of port parameter to MG registers
URL : https://patchwork.freedesktop.org/series/67467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14620
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/index.html
Known issues
Here are the changes found in Patchwork_14620 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bxt-dsi/igt@gem_ctx_e...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-bxt-dsi/igt@gem_ctx_e...@basic.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_bl...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724] / [fdo#111214]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-icl-u3/igt@i915_module_l...@reload.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [FAIL][10] ([fdo#111045]
/ [fdo#111096])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14620
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14620: 70d2eaa029e30d92f61ce87205e70e77f0df15ca @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
70d2eaa029e3 drm/i915/mg: Use tc_port instead of port parameter to MG registers
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14620/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Update H2G enable logging action definition
On 9/28/19 3:36 AM, Patchwork wrote: == Series Details == Series: drm/i915/guc: Update H2G enable logging action definition URL : https://patchwork.freedesktop.org/series/67351/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6970_full -> Patchwork_14570_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14570_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14570_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14570_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@system-suspend-execbuf: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/shard-iclb8/igt@i915_pm_...@system-suspend-execbuf.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/shard-iclb1/igt@i915_pm_...@system-suspend-execbuf.html Dmesg warnings are for thunderbolt and do not look to be related to this patch. It looks to be related to fdo#111764. I think patch should be safe to merge. New tests - New tests have been introduced between CI_DRM_6970_full and Patchwork_14570_full: ### New Piglit tests (7) ### * spec@arb_gpu_shader5@texturegather@vs-rgba-2-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@vs-rgba-3-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-0-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-2-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-3-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_14570_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/shard-iclb7/igt@gem_exec_as...@concurrent-writes-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +17 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@i915_pm_rpm@cursor-dpms: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#108840]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/shard-iclb7/igt@i915_pm_...@cursor-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/shard-iclb7/igt@i915_pm_...@cursor-dpms.html * igt@kms_busy@basic-modeset-a: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/shard-iclb4/igt@kms_b...@basic-modeset-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/shard-iclb1/igt@kms_b...@basic-modeset-a.html * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/shard-apl7/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/shard-apl1/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/shard-hsw1/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/shard-hsw1/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#100368]) [15]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mg: Use tc_port instead of port parameter to MG registers
== Series Details == Series: drm/i915/mg: Use tc_port instead of port parameter to MG registers URL : https://patchwork.freedesktop.org/series/67467/ State : warning == Summary == $ dim checkpatch origin/drm-tip 70d2eaa029e3 drm/i915/mg: Use tc_port instead of port parameter to MG registers -:224: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects? #224: FILE: drivers/gpu/drm/i915/i915_reg.h:1959: +#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ + _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) total: 0 errors, 0 warnings, 1 checks, 355 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607
URL : https://patchwork.freedesktop.org/series/67461/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14619
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14619:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_workarounds@basic-read:
- {fi-tgl-u2}:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-tgl-u2/igt@gem_workarou...@basic-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-tgl-u2/igt@gem_workarou...@basic-read.html
- {fi-tgl-u}: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-tgl-u/igt@gem_workarou...@basic-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-tgl-u/igt@gem_workarou...@basic-read.html
Known issues
Here are the changes found in Patchwork_14619 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_bl...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724] / [fdo#111214]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14619
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14619: 52edee18222b7e88f600406fa896bd731de901c6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
52edee18222b drm/i915/tgl: Skip Wa_1604555607 verification at A0
b68066e4e634 drm/i915/tgl: Implement Wa_1604555607
== Logs ==
For more details see:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607
URL : https://patchwork.freedesktop.org/series/67461/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b68066e4e634 drm/i915/tgl: Implement Wa_1604555607
52edee18222b drm/i915/tgl: Skip Wa_1604555607 verification at A0
-:22: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#22: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:995:
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+
-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/i915_drv.h:2071:
+#define IS_TGL_REVID(p, since, until) \
+ (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 2 checks, 49 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use a modparam to restrict exposed engines (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Use a modparam to restrict exposed
engines (rev2)
URL : https://patchwork.freedesktop.org/series/67450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14618
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14618:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_sync@basic-many-each:
- {fi-cml-h}: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-cml-h/igt@gem_s...@basic-many-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/fi-cml-h/igt@gem_s...@basic-many-each.html
* igt@runner@aborted:
- {fi-cml-h}: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/fi-cml-h/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14618 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@rcs0:
- fi-bxt-dsi: [PASS][4] -> [INCOMPLETE][5] ([fdo#103927])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
* igt@gem_mmap_gtt@basic-read:
- fi-icl-u3: [PASS][6] -> [DMESG-WARN][7] ([fdo#107724]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_mmap_...@basic-read.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/fi-icl-u3/igt@gem_mmap_...@basic-read.html
Possible fixes
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][8] ([fdo#107724]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_bl...@basic.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][10] ([fdo#107724] / [fdo#111214]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/fi-icl-u3/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111604]: https://bugs.freedesktop.org/show_bug.cgi?id=111604
[fdo#111714]: https://bugs.freedesktop.org/show_bug.cgi?id=111714
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14618
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14618: 971c66ff56ceb82389ee13876716ab9e41cd7252 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
971c66ff56ce drm/i915/tgl: Restrict availables engines to rcs0 by default
c8be7f867553 drm/i915: Use a modparam to restrict exposed engines
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14618/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for RFT drm/i915/tgl: Re-enable rps (rev3)
== Series Details == Series: RFT drm/i915/tgl: Re-enable rps (rev3) URL : https://patchwork.freedesktop.org/series/67398/ State : success == Summary == CI Bug Log - changes from CI_DRM_6984_full -> Patchwork_14604_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14604_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_read@short-buffer-wakeup: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-apl4/igt@drm_r...@short-buffer-wakeup.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-apl3/igt@drm_r...@short-buffer-wakeup.html * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-apl4/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_isolation@vecs0-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-skl3/igt@gem_ctx_isolat...@vecs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-skl4/igt@gem_ctx_isolat...@vecs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-iclb1/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +10 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-iclb5/igt@gem_exec_sched...@in-order-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-iclb2/igt@gem_exec_sched...@in-order-bsd.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +16 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_request_retire@retire-vma-not-inactive: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-hsw5/igt@gem_request_ret...@retire-vma-not-inactive.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-hsw8/igt@gem_request_ret...@retire-vma-not-inactive.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-kbl6/igt@gem_userptr_bl...@dmabuf-sync.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-kbl7/igt@gem_userptr_bl...@dmabuf-sync.html - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-skl1/igt@gem_userptr_bl...@dmabuf-sync.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-skl7/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-snb4/igt@gem_userptr_bl...@sync-unmap-after-close.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-snb7/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-snb2/igt@i915_pm_rc6_reside...@rc6-accuracy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-snb2/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108] / [fdo#107807]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-skl8/igt@i915_pm_...@system-suspend-execbuf.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/shard-skl1/igt@i915_pm_...@system-suspend-execbuf.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#102670]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/shard-skl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html [26]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Use a modparam to restrict exposed engines (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Use a modparam to restrict exposed engines (rev2) URL : https://patchwork.freedesktop.org/series/67450/ State : warning == Summary == $ dim checkpatch origin/drm-tip c8be7f867553 drm/i915: Use a modparam to restrict exposed engines -:109: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #109: FILE: drivers/gpu/drm/i915/i915_params.c:48: +i915_param_named(engines, uint, 0400, + "Only expose selected command streamers [GPU engines] (0=disable GPU, " total: 0 errors, 0 warnings, 1 checks, 87 lines checked 971c66ff56ce drm/i915/tgl: Restrict availables engines to rcs0 by default ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix audio power up sequence for gen10/11
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix audio power up sequence for
gen10/11
URL : https://patchwork.freedesktop.org/series/67460/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14617
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14617/index.html
Known issues
Here are the changes found in Patchwork_14617 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload-no-display:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14617/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14617/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_bl...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14617/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724] / [fdo#111214]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14617/fi-icl-u3/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (54 -> 43)
--
Missing(11): fi-ilk-m540 fi-cml-h fi-tgl-u2 fi-hsw-4200u fi-byt-squawks
fi-icl-u2 fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14617
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14617: eb4770433c09ab208e1500bfa62b21db7dce58d6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eb4770433c09 drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms
1554bddd7fee drm/i915: Fix audio power up sequence for gen10/11
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14617/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers
On Tue, Oct 01, 2019 at 12:37:29PM -0700, Jose Souza wrote:
All the MG registers is based on the tc_port not port, so
MG_PHY_PORT_LN() was subtracting port and PORT_C what is very
fragile.
So replacing port to tc_port in all MG register macros and users
like we have for DKL.
Cc: Lucas De Marchi
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++
drivers/gpu/drm/i915/i915_reg.h | 100 +++
2 files changed, 81 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b463e51f8b45..3c1e885e0187 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2681,7 +2681,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
u32 level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
u32 n_entries, val;
int ln;
@@ -2697,33 +2697,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
+ val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
val &= ~CRI_USE_FS32;
- I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
+ I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
- val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
+ val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
val &= ~CRI_USE_FS32;
- I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
+ I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
}
/* Program MG_TX_SWINGCTRL with values from vswing table */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
+ val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
val |= CRI_TXDEEMPH_OVERRIDE_17_12(
ddi_translations[level].cri_txdeemph_override_17_12);
- I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
+ I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
- val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
+ val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
val |= CRI_TXDEEMPH_OVERRIDE_17_12(
ddi_translations[level].cri_txdeemph_override_17_12);
- I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
+ I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
}
/* Program MG_TX_DRVCTRL with values from vswing table */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_DRVCTRL(ln, port));
+ val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2731,9 +2731,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
CRI_TXDEEMPH_OVERRIDE_11_6(
ddi_translations[level].cri_txdeemph_override_11_6) |
CRI_TXDEEMPH_OVERRIDE_EN;
- I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
+ I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
- val = I915_READ(MG_TX2_DRVCTRL(ln, port));
+ val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2741,7 +2741,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
CRI_TXDEEMPH_OVERRIDE_11_6(
ddi_translations[level].cri_txdeemph_override_11_6) |
CRI_TXDEEMPH_OVERRIDE_EN;
- I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
+ I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
}
@@ -2752,17 +2752,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
* values from table for which TX1 and TX2 enabled.
*/
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_CLKHUB(ln, port));
+ val = I915_READ(MG_CLKHUB(ln, tc_port));
if (link_clock <
[Intel-gfx] [PATCH v3] drm/i915/selftests: Exercise potential false lite-restore
If execlists's lite-restore is based on the common GEM context tag
rather than the per-intel_context LRCA, then a context switch between
two intel_contexts on the same engine derived from the same GEM context
will perform a lite-restore instead of a full context switch. We can
exploit this by poisoning the ringbuffer of the first context and trying
to trick a simple RING_TAIL update (i.e. lite-restore)
v2: Also check what happens if preempt ce[0] with ce[1] (both instances
on the same engine from the same parent context) [Tvrtko]
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
Mark up the context image adjustment to appease lockdep
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 18 ++-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 176 +
2 files changed, 190 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 9877b6ba13df..2cef06be3882 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -235,6 +235,16 @@ static void execlists_init_reg_state(u32 *reg_state,
const struct intel_ring *ring,
bool close);
+static void __context_pin_acquire(struct intel_context *ce)
+{
+ mutex_acquire(>pin_mutex.dep_map, 2, 0, _RET_IP_);
+}
+
+static void __context_pin_release(struct intel_context *ce)
+{
+ mutex_release(>pin_mutex.dep_map, 0, _RET_IP_);
+}
+
static void mark_eio(struct i915_request *rq)
{
if (!i915_request_signaled(rq))
@@ -2761,7 +2771,7 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
/* Proclaim we have exclusive access to the context image! */
- mutex_acquire(>pin_mutex.dep_map, 2, 0, _THIS_IP_);
+ __context_pin_acquire(ce);
rq = active_request(rq);
if (!rq) {
@@ -2825,7 +2835,7 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
__execlists_reset_reg_state(ce, engine);
__execlists_update_reg_state(ce, engine);
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE; /* paranoid: GPU was reset! */
- mutex_release(>pin_mutex.dep_map, 0, _THIS_IP_);
+ __context_pin_release(ce);
unwind:
/* Push back any incomplete requests for replay after the reset. */
@@ -4439,7 +4449,7 @@ void intel_lr_context_reset(struct intel_engine_cs
*engine,
bool scrub)
{
GEM_BUG_ON(!intel_context_is_pinned(ce));
- mutex_acquire(>pin_mutex.dep_map, 2, 0, _THIS_IP_);
+ __context_pin_acquire(ce);
/*
* We want a simple context + ring to execute the breadcrumb update.
@@ -4465,7 +4475,7 @@ void intel_lr_context_reset(struct intel_engine_cs
*engine,
intel_ring_update_space(ce->ring);
__execlists_update_reg_state(ce, engine);
- mutex_release(>pin_mutex.dep_map, 0, _THIS_IP_);
+ __context_pin_release(ce);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 93f2fcdc49bf..5936f46eeb08 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -79,6 +79,180 @@ static int live_sanitycheck(void *arg)
return err;
}
+static int live_unlite_restore(struct drm_i915_private *i915, int prio)
+{
+ struct intel_engine_cs *engine;
+ struct i915_gem_context *ctx;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ struct igt_spinner spin;
+ int err = -ENOMEM;
+
+ /*
+* Check that we can correctly context switch between 2 instances
+* on the same engine from the same parent context.
+*/
+
+ mutex_lock(>drm.struct_mutex);
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
+ if (igt_spinner_init(, >gt))
+ goto err_unlock;
+
+ ctx = kernel_context(i915);
+ if (!ctx)
+ goto err_spin;
+
+ err = 0;
+ for_each_engine(engine, i915, id) {
+ struct intel_context *ce[2] = {};
+ struct i915_request *rq[2];
+ struct igt_live_test t;
+ int n;
+
+ if (prio && !intel_engine_has_preemption(engine))
+ continue;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ if (igt_live_test_begin(, i915, __func__, engine->name)) {
+ err = -EIO;
+ break;
+ }
+
+ for (n = 0; n < ARRAY_SIZE(ce); n++) {
+ struct intel_context *tmp;
+
+ tmp = intel_context_create(ctx, engine);
+ if (IS_ERR(tmp)) {
+ err = PTR_ERR(tmp);
+ goto
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Exercise potential false lite-restore (rev4)
== Series Details == Series: drm/i915/selftests: Exercise potential false lite-restore (rev4) URL : https://patchwork.freedesktop.org/series/67438/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14616 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14616 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14616, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14616: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - fi-cfl-8700k: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-cfl-8700k/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-cfl-8700k/igt@i915_selftest@live_execlists.html - fi-bdw-gvtdvm: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bdw-gvtdvm/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-bdw-gvtdvm/igt@i915_selftest@live_execlists.html - fi-skl-guc: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-guc/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-skl-guc/igt@i915_selftest@live_execlists.html - fi-cfl-guc: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-cfl-guc/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-cfl-guc/igt@i915_selftest@live_execlists.html - fi-skl-iommu: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-iommu/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-skl-iommu/igt@i915_selftest@live_execlists.html - fi-whl-u: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-whl-u/igt@i915_selftest@live_execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-whl-u/igt@i915_selftest@live_execlists.html - fi-kbl-7500u: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-7500u/igt@i915_selftest@live_execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-kbl-7500u/igt@i915_selftest@live_execlists.html - fi-kbl-guc: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-guc/igt@i915_selftest@live_execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-kbl-guc/igt@i915_selftest@live_execlists.html - fi-kbl-8809g: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-8809g/igt@i915_selftest@live_execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-kbl-8809g/igt@i915_selftest@live_execlists.html - fi-glk-dsi: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-glk-dsi/igt@i915_selftest@live_execlists.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-glk-dsi/igt@i915_selftest@live_execlists.html - fi-kbl-x1275: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-x1275/igt@i915_selftest@live_execlists.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-kbl-x1275/igt@i915_selftest@live_execlists.html - fi-skl-6600u: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-6600u/igt@i915_selftest@live_execlists.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-skl-6600u/igt@i915_selftest@live_execlists.html - fi-bsw-n3050: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bsw-n3050/igt@i915_selftest@live_execlists.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-bsw-n3050/igt@i915_selftest@live_execlists.html - fi-bsw-kefka: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bsw-kefka/igt@i915_selftest@live_execlists.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14616/fi-bsw-kefka/igt@i915_selftest@live_execlists.html - fi-bxt-dsi: [PASS][29] ->
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise potential false lite-restore (rev4)
== Series Details == Series: drm/i915/selftests: Exercise potential false lite-restore (rev4) URL : https://patchwork.freedesktop.org/series/67438/ State : warning == Summary == $ dim checkpatch origin/drm-tip d13633b978e3 drm/i915/selftests: Exercise potential false lite-restore -:100: CHECK:LINE_SPACING: Please don't use multiple blank lines #100: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:154: + + total: 0 errors, 0 warnings, 1 checks, 186 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Limit MST modes based on plane size too
== Series Details ==
Series: series starting with [1/2] drm/i915: Limit MST modes based on plane
size too
URL : https://patchwork.freedesktop.org/series/67457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14615
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14615:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_switch@rcs0:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-tgl-u/igt@gem_ctx_swi...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-tgl-u/igt@gem_ctx_swi...@rcs0.html
* igt@gem_sync@basic-many-each:
- {fi-cml-h}: [PASS][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-cml-h/igt@gem_s...@basic-many-each.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-cml-h/igt@gem_s...@basic-many-each.html
* igt@runner@aborted:
- {fi-cml-h}: NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-cml-h/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14615 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@rcs0:
- fi-bxt-dsi: [PASS][6] -> [INCOMPLETE][7] ([fdo#103927])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) +2
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][10] ([fdo#107718]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][12] ([fdo#107724]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_bl...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][14] ([fdo#107724] / [fdo#111214]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/fi-icl-u3/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (54 -> 46)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14615
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14615: 5529e13f7d802efa164bcddf628a3304d4c236d1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5529e13f7d80 drm/i915: Polish intel_tv_mode_valid()
b3dd486a4b40 drm/i915: Limit MST modes based on plane size too
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14615/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607
On Tue, Oct 1, 2019 at 10:36 AM Chris Wilson wrote:
>
> Quoting Ramalingam C (2019-10-01 18:26:23)
> > From: Michel Thierry
> >
> > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > FF_MODE2 is part of the register state context, that's why it is
> > implemented here.
> >
> > v2: Rebased on top of the WA refactoring (Oscar)
> > v3: Correctly add to ctx_workarounds_init (Michel)
> >
> > BSpec: 19363
> > HSDES: 1604555607
> > Signed-off-by: Michel Thierry
> > Signed-off-by: Ramalingam C
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
> > drivers/gpu/drm/i915/i915_reg.h | 5 +
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index ba65e5018978..4049b876492a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct
> > intel_engine_cs *engine,
> > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> > {
> > + struct drm_i915_private *dev_priv = engine->i915;
> > + u32 val;
> > +
> > /* Wa_1409142259 */
> > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +
> > + /* Wa_1604555607:tgl */
> > + val = I915_READ(FF_MODE2);
>
> No, you can't use indiscriminate mmio access that may not match the engine
> (engine->gt->uncore).
>
> But really consider doing the rmw as part of the wa.
And:
https://patchwork.freedesktop.org/patch/319952/?series=64274=1
https://patchwork.freedesktop.org/patch/317654/?series=63670=2
Please don't simply resend patches that were already reviewed.
Lucas De Marchi
>
> > + val &= ~FF_MODE2_TDS_TIMER_MASK;
> > + val |= FF_MODE2_TDS_TIMER_128;
> > + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> > }
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: abstract all vgaarb access to intel_vga.[ch]
== Series Details ==
Series: drm/i915/display: abstract all vgaarb access to intel_vga.[ch]
URL : https://patchwork.freedesktop.org/series/67456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14614
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/index.html
Known issues
Here are the changes found in Patchwork_14614 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [PASS][5] -> [FAIL][6] ([fdo#107707])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][7] -> [DMESG-FAIL][8] ([fdo#111678])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_flip@basic-flip-vs-dpms:
- fi-hsw-4770r: [PASS][9] -> [DMESG-WARN][10] ([fdo#105602])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-hsw-4770r/igt@kms_f...@basic-flip-vs-dpms.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-hsw-4770r/igt@kms_f...@basic-flip-vs-dpms.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_bl...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724] / [fdo#111214]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/fi-icl-u3/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6986 -> Patchwork_14614
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14614: 43d2ea1b278af62ba8fdc77a04d9507d15d718f8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
43d2ea1b278a drm/i915/display: abstract all vgaarb access to intel_vga.[ch]
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14614/index.html
___
Intel-gfx
[Intel-gfx] [PATCH] drm/i915/mg: Use tc_port instead of port parameter to MG registers
All the MG registers is based on the tc_port not port, so
MG_PHY_PORT_LN() was subtracting port and PORT_C what is very
fragile.
So replacing port to tc_port in all MG register macros and users
like we have for DKL.
Cc: Lucas De Marchi
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++
drivers/gpu/drm/i915/i915_reg.h | 100 +++
2 files changed, 81 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b463e51f8b45..3c1e885e0187 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2681,7 +2681,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
u32 level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
u32 n_entries, val;
int ln;
@@ -2697,33 +2697,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
+ val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
val &= ~CRI_USE_FS32;
- I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
+ I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
- val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
+ val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
val &= ~CRI_USE_FS32;
- I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
+ I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
}
/* Program MG_TX_SWINGCTRL with values from vswing table */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
+ val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
val |= CRI_TXDEEMPH_OVERRIDE_17_12(
ddi_translations[level].cri_txdeemph_override_17_12);
- I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
+ I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
- val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
+ val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
val |= CRI_TXDEEMPH_OVERRIDE_17_12(
ddi_translations[level].cri_txdeemph_override_17_12);
- I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
+ I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
}
/* Program MG_TX_DRVCTRL with values from vswing table */
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_TX1_DRVCTRL(ln, port));
+ val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2731,9 +2731,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
CRI_TXDEEMPH_OVERRIDE_11_6(
ddi_translations[level].cri_txdeemph_override_11_6) |
CRI_TXDEEMPH_OVERRIDE_EN;
- I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
+ I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
- val = I915_READ(MG_TX2_DRVCTRL(ln, port));
+ val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2741,7 +2741,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
CRI_TXDEEMPH_OVERRIDE_11_6(
ddi_translations[level].cri_txdeemph_override_11_6) |
CRI_TXDEEMPH_OVERRIDE_EN;
- I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
+ I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
}
@@ -2752,17 +2752,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
intel_encoder *encoder,
* values from table for which TX1 and TX2 enabled.
*/
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_CLKHUB(ln, port));
+ val = I915_READ(MG_CLKHUB(ln, tc_port));
if (link_clock < 30)
val |= CFG_LOW_RATE_LKREN_EN;
else
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: abstract all vgaarb access to intel_vga.[ch]
== Series Details == Series: drm/i915/display: abstract all vgaarb access to intel_vga.[ch] URL : https://patchwork.freedesktop.org/series/67456/ State : warning == Summary == $ dim checkpatch origin/drm-tip 43d2ea1b278a drm/i915/display: abstract all vgaarb access to intel_vga.[ch] -:254: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #254: new file mode 100644 -:295: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #295: FILE: drivers/gpu/drm/i915/display/intel_vga.c:37: + udelay(300); total: 0 errors, 1 warnings, 1 checks, 479 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Conclude load -> probe naming convention switch
== Series Details ==
Series: drm/i915: Conclude load -> probe naming convention switch
URL : https://patchwork.freedesktop.org/series/67454/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14613
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14613 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14613, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14613:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-whl-u: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-whl-u/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/fi-whl-u/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14613 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@prime_self_import@basic-with_fd_dup:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_bl...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724] / [fdo#111214]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14613/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
Participating hosts (54 -> 46)
--
Missing(8): fi-ilk-m540 fi-cml-h fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* IGT: IGT_5208 -> IGTPW_3522
* Linux: CI_DRM_6986 -> Patchwork_14613
CI-20190529: 20190529
CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3522: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3522/index.html
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14613: 99ddd1e63a9f12c5c4174784f31c05e4214c0fe2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
99ddd1e63a9f drm/i915: Rename "inject_load_failure" module parameter
f23ba0cec202 drm/i915: Fix i915_inject_load_error() name to read *_probe_*
== Logs ==
For
Re: [Intel-gfx] [PATCH] drm/i915: Fix g4x sprite scaling stride check with GTT remapping
Quoting Ville Syrjala (2019-09-30 19:30:45)
> From: Ville Syrjälä
>
> I forgot to update the g4x sprite scaling stride check when GTT
> remapping was introduced. The stride of the original framebuffer
> is irrelevant when remapping is used and instead we want to check
> the stride of the remapped view.
>
> Also drop the duplicate width_bytes check. We already check that
> a few lines earlier.
>
> Fixes: df79cf441910 ("drm/i915: Store the final plane stride in plane_state")
> Signed-off-by: Ville Syrjälä
So basically .stride = intel_fb_pitch()
Reviewed-by: Chris Wilson
-Chris
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Conclude load -> probe naming convention switch
== Series Details ==
Series: drm/i915: Conclude load -> probe naming convention switch
URL : https://patchwork.freedesktop.org/series/67454/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f23ba0cec202 drm/i915: Fix i915_inject_load_error() name to read *_probe_*
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit f2db53f14d3d ("drm/i915: Replace
"_load" with "_probe" consequently")'
#11:
established by commit f2db53f14d3d ("drm/i915: Replace "_load" with
total: 1 errors, 0 warnings, 0 checks, 158 lines checked
99ddd1e63a9f drm/i915: Rename "inject_load_failure" module parameter
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'Commit f2db53f14d3d ("drm/i915: Replace
"_load" with "_probe" consequently")'
#9:
Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
-:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#34: FILE: drivers/gpu/drm/i915/i915_params.c:169:
+i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
total: 1 errors, 0 warnings, 1 checks, 43 lines checked
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Limit MST modes based on plane size too
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc1 next-20191001]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Limit-MST-modes-based-on-plane-size-too/20191002-010404
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-13) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_dp_mst.c: In function
'intel_dp_mst_mode_valid':
>> drivers/gpu/drm/i915/display/intel_dp_mst.c:449:9: error: implicit
>> declaration of function 'intel_mode_valid_max_plane_size'; did you mean
>> 'drm_mode_validate_size'? [-Werror=implicit-function-declaration]
return intel_mode_valid_max_plane_size(dev_priv, mode);
^~~
drm_mode_validate_size
cc1: some warnings being treated as errors
vim +449 drivers/gpu/drm/i915/display/intel_dp_mst.c
416
417 static enum drm_mode_status
418 intel_dp_mst_mode_valid(struct drm_connector *connector,
419 struct drm_display_mode *mode)
420 {
421 struct drm_i915_private *dev_priv = to_i915(connector->dev);
422 struct intel_connector *intel_connector =
to_intel_connector(connector);
423 struct intel_dp *intel_dp = intel_connector->mst_port;
424 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
425 int max_rate, mode_rate, max_lanes, max_link_clock;
426
427 if (drm_connector_is_unregistered(connector))
428 return MODE_ERROR;
429
430 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
431 return MODE_NO_DBLESCAN;
432
433 max_link_clock = intel_dp_max_link_rate(intel_dp);
434 max_lanes = intel_dp_max_lane_count(intel_dp);
435
436 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
437 mode_rate = intel_dp_link_required(mode->clock, 18);
438
439 /* TODO - validate mode against available PBN for link */
440 if (mode->clock < 1)
441 return MODE_CLOCK_LOW;
442
443 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
444 return MODE_H_ILLEGAL;
445
446 if (mode_rate > max_rate || mode->clock > max_dotclk)
447 return MODE_CLOCK_HIGH;
448
> 449 return intel_mode_valid_max_plane_size(dev_priv, mode);
450 }
451
---
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https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Limit MST modes based on plane size too
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc1 next-20191001]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Limit-MST-modes-based-on-plane-size-too/20191002-010404
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a002-201939 (attached as .config)
compiler: gcc-5 (Ubuntu 5.5.0-12ubuntu1) 5.5.0 20171010
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_dp_mst.c: In function
'intel_dp_mst_mode_valid':
>> drivers/gpu/drm/i915/display/intel_dp_mst.c:449:9: error: implicit
>> declaration of function 'intel_mode_valid_max_plane_size'
>> [-Werror=implicit-function-declaration]
return intel_mode_valid_max_plane_size(dev_priv, mode);
^
cc1: some warnings being treated as errors
vim +/intel_mode_valid_max_plane_size +449
drivers/gpu/drm/i915/display/intel_dp_mst.c
416
417 static enum drm_mode_status
418 intel_dp_mst_mode_valid(struct drm_connector *connector,
419 struct drm_display_mode *mode)
420 {
421 struct drm_i915_private *dev_priv = to_i915(connector->dev);
422 struct intel_connector *intel_connector =
to_intel_connector(connector);
423 struct intel_dp *intel_dp = intel_connector->mst_port;
424 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
425 int max_rate, mode_rate, max_lanes, max_link_clock;
426
427 if (drm_connector_is_unregistered(connector))
428 return MODE_ERROR;
429
430 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
431 return MODE_NO_DBLESCAN;
432
433 max_link_clock = intel_dp_max_link_rate(intel_dp);
434 max_lanes = intel_dp_max_lane_count(intel_dp);
435
436 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
437 mode_rate = intel_dp_link_required(mode->clock, 18);
438
439 /* TODO - validate mode against available PBN for link */
440 if (mode->clock < 1)
441 return MODE_CLOCK_LOW;
442
443 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
444 return MODE_H_ILLEGAL;
445
446 if (mode_rate > max_rate || mode->clock > max_dotclk)
447 return MODE_CLOCK_HIGH;
448
> 449 return intel_mode_valid_max_plane_size(dev_priv, mode);
450 }
451
---
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Description: application/gzip
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc1 next-20191001]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Use-a-modparam-to-restrict-exposed-engines/20191002-003226
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a002-201939 (attached as .config)
compiler: gcc-5 (Ubuntu 5.5.0-12ubuntu1) 5.5.0 20171010
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_gem.c: In function 'i915_gem_init':
>> drivers/gpu/drm/i915/i915_gem.c:1411:3: error: implicit declaration of
>> function 'intel_gt_set_wedged_on_init'
>> [-Werror=implicit-function-declaration]
intel_gt_set_wedged_on_init(_priv->gt);
^
cc1: some warnings being treated as errors
vim +/intel_gt_set_wedged_on_init +1411 drivers/gpu/drm/i915/i915_gem.c
1405
1406 int i915_gem_init(struct drm_i915_private *dev_priv)
1407 {
1408 int ret;
1409
1410 if (!RUNTIME_INFO(dev_priv)->num_engines) {
> 1411 intel_gt_set_wedged_on_init(_priv->gt);
1412 return 0;
1413 }
1414
1415 /* We need to fallback to 4K pages if host doesn't support huge
gtt. */
1416 if (intel_vgpu_active(dev_priv) &&
!intel_vgpu_has_huge_gtt(dev_priv))
1417 mkwrite_device_info(dev_priv)->page_sizes =
1418 I915_GTT_PAGE_SIZE_4K;
1419
1420 intel_timelines_init(dev_priv);
1421
1422 ret = i915_gem_init_userptr(dev_priv);
1423 if (ret)
1424 return ret;
1425
1426 intel_uc_fetch_firmwares(_priv->gt.uc);
1427 intel_wopcm_init(_priv->wopcm);
1428
1429 /* This is just a security blanket to placate dragons.
1430 * On some systems, we very sporadically observe that the first
TLBs
1431 * used by the CS may be stale, despite us poking the TLB
reset. If
1432 * we hold the forcewake during initialisation these problems
1433 * just magically go away.
1434 */
1435 mutex_lock(_priv->drm.struct_mutex);
1436 intel_uncore_forcewake_get(_priv->uncore, FORCEWAKE_ALL);
1437
1438 ret = i915_init_ggtt(dev_priv);
1439 if (ret) {
1440 GEM_BUG_ON(ret == -EIO);
1441 goto err_unlock;
1442 }
1443
1444 ret = i915_gem_init_scratch(dev_priv,
1445 IS_GEN(dev_priv, 2) ? SZ_256K :
PAGE_SIZE);
1446 if (ret) {
1447 GEM_BUG_ON(ret == -EIO);
1448 goto err_ggtt;
1449 }
1450
1451 ret = intel_engines_setup(dev_priv);
1452 if (ret) {
1453 GEM_BUG_ON(ret == -EIO);
1454 goto err_unlock;
1455 }
1456
1457 ret = i915_gem_contexts_init(dev_priv);
1458 if (ret) {
1459 GEM_BUG_ON(ret == -EIO);
1460 goto err_scratch;
1461 }
1462
1463 ret = intel_engines_init(dev_priv);
1464 if (ret) {
1465 GEM_BUG_ON(ret == -EIO);
1466 goto err_context;
1467 }
1468
1469 intel_init_gt_powersave(dev_priv);
1470
1471 intel_uc_init(_priv->gt.uc);
1472
1473 ret = i915_gem_init_hw(dev_priv);
1474 if (ret)
1475 goto err_uc_init;
1476
1477 /* Only when the HW is re-initialised, can we replay the
requests */
1478 ret = intel_gt_resume(_priv->gt);
1479 if (ret)
1480 goto err_init_hw;
1481
1482 /*
1483 * Despite its name intel_init_clock_gating applies both display
1484 * clock gating workarounds; GT mmio workarounds and the
occasional
1485 * GT power context workaround. Worse, sometimes it includes a
context
1486 * register workaround which we need to apply before we record
the
1487 * default HW state for all contexts.
1488 *
1489 * FIXME: break up the workarounds and apply them at the right
time!
1490 */
1491 intel_init_clock_gating(dev_priv);
1492
1493 ret = intel_engines_verify_workarounds(dev_priv);
1
[Intel-gfx] ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev14)
== Series Details ==
Series: DC3CO Support for TGL (rev14)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6985 -> Patchwork_14612
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/index.html
Known issues
Here are the changes found in Patchwork_14612 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_flink_basic@bad-open:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
- {fi-tgl-u2}:[INCOMPLETE][9] ([fdo#111850]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-tgl-u2/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/fi-tgl-u2/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
Participating hosts (51 -> 47)
--
Additional (3): fi-cml-h fi-apl-guc fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6985 -> Patchwork_14612
CI-20190529: 20190529
CI_DRM_6985: 75d23ba38b952a5f3d0fc42baf1df2d15c5e74b1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14612: d45dfbfa58b0d4de9ff126a19ab0dcb448f17ef7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d45dfbfa58b0 drm/i915/tgl: Add DC3CO counter in i915_dmc_info
66a367a59909 drm/i915/tgl: Switch between dc3co and dc5 based on display
idleness
8504d53cbe34 drm/i915/tgl: Do modeset to enable and configure DC3CO exitline
cef357e64b82 drm/i915/tgl: Enable DC3CO state in "DC Off" power well
131d049f0dbc drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
a45d47a9b70c drm/i915/tgl: Add DC3CO required register and bits
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/index.html
___
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[Intel-gfx] [PATCH i-g-t] i915/gem_userptr_blits: Check for allowed GTT mmaps
Having decided to close the GTT mmap of userptr objects loophole in the
kernel, we need to adjust the test suite to avoid tripping over GTT
mmaps when required.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_userptr_blits.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 3fad7d1b3..3f5edaeab 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -69,11 +69,33 @@
static uint32_t userptr_flags = LOCAL_I915_USERPTR_UNSYNCHRONIZED;
+static bool can_gtt_mmap;
+
#define WIDTH 512
#define HEIGHT 512
static uint32_t linear[WIDTH*HEIGHT];
+static bool has_gtt_mmap(int i915)
+{
+ void *ptr, *map;
+ uint32_t handle;
+
+ igt_assert(posix_memalign(, PAGE_SIZE, PAGE_SIZE) == 0);
+
+ gem_userptr(i915, ptr, 4096, 0, 0, );
+ igt_assert(handle != 0);
+
+ map = __gem_mmap__gtt(i915, handle, 4096, PROT_WRITE);
+ if (map)
+ munmap(map, 4096);
+
+ gem_close(i915, handle);
+ free(ptr);
+
+ return map != NULL;
+}
+
static void gem_userptr_test_unsynchronized(void)
{
userptr_flags = LOCAL_I915_USERPTR_UNSYNCHRONIZED;
@@ -853,7 +875,7 @@ static void *umap(int fd, uint32_t handle)
{
void *ptr;
- if (gem_has_llc(fd)) {
+ if (can_gtt_mmap) {
ptr = gem_mmap__gtt(fd, handle, sizeof(linear),
PROT_READ | PROT_WRITE);
} else {
@@ -884,7 +906,7 @@ check_bo(int fd1, uint32_t handle1, int is_userptr, int
fd2, uint32_t handle2)
sigbus_start = (unsigned long)ptr2;
igt_assert(memcmp(ptr1, ptr2, sizeof(linear)) == 0);
- if (gem_has_llc(fd1)) {
+ if (can_gtt_mmap) {
counter++;
memset(ptr1, counter, size);
memset(ptr2, counter, size);
@@ -971,7 +993,7 @@ static int test_dmabuf(void)
free_userptr_bo(fd1, handle);
close(fd1);
- if (gem_has_llc(fd2)) {
+ if (can_gtt_mmap) {
struct sigaction sigact, orig_sigact;
memset(, 0, sizeof(sigact));
@@ -1225,7 +1247,7 @@ static void test_readonly_mmap(int i915)
original = g_compute_checksum_for_data(G_CHECKSUM_SHA1, pages, sz);
ptr = __gem_mmap__gtt(i915, handle, sz, PROT_WRITE);
- igt_assert(ptr == NULL);
+ igt_require(ptr != NULL);
ptr = gem_mmap__gtt(i915, handle, sz, PROT_READ);
gem_close(i915, handle);
@@ -1834,6 +1856,8 @@ igt_main_args("c:", NULL, help_str, opt_handler, NULL)
igt_require_gem(fd);
gem_require_blitter(fd);
+ can_gtt_mmap = has_gtt_mmap(fd) && gem_has_llc(fd);
+
size = sizeof(linear);
aperture_size = gem_aperture_size(fd);
--
2.23.0
___
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc1 next-20191001]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Use-a-modparam-to-restrict-exposed-engines/20191002-003226
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-13) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_gem.c: In function 'i915_gem_init':
>> drivers/gpu/drm/i915/i915_gem.c:1411:3: error: implicit declaration of
>> function 'intel_gt_set_wedged_on_init'; did you mean 'intel_gt_set_wedged'?
>> [-Werror=implicit-function-declaration]
intel_gt_set_wedged_on_init(_priv->gt);
^~~
intel_gt_set_wedged
cc1: some warnings being treated as errors
vim +1411 drivers/gpu/drm/i915/i915_gem.c
1405
1406 int i915_gem_init(struct drm_i915_private *dev_priv)
1407 {
1408 int ret;
1409
1410 if (!RUNTIME_INFO(dev_priv)->num_engines) {
> 1411 intel_gt_set_wedged_on_init(_priv->gt);
1412 return 0;
1413 }
1414
1415 /* We need to fallback to 4K pages if host doesn't support huge
gtt. */
1416 if (intel_vgpu_active(dev_priv) &&
!intel_vgpu_has_huge_gtt(dev_priv))
1417 mkwrite_device_info(dev_priv)->page_sizes =
1418 I915_GTT_PAGE_SIZE_4K;
1419
1420 intel_timelines_init(dev_priv);
1421
1422 ret = i915_gem_init_userptr(dev_priv);
1423 if (ret)
1424 return ret;
1425
1426 intel_uc_fetch_firmwares(_priv->gt.uc);
1427 intel_wopcm_init(_priv->wopcm);
1428
1429 /* This is just a security blanket to placate dragons.
1430 * On some systems, we very sporadically observe that the first
TLBs
1431 * used by the CS may be stale, despite us poking the TLB
reset. If
1432 * we hold the forcewake during initialisation these problems
1433 * just magically go away.
1434 */
1435 mutex_lock(_priv->drm.struct_mutex);
1436 intel_uncore_forcewake_get(_priv->uncore, FORCEWAKE_ALL);
1437
1438 ret = i915_init_ggtt(dev_priv);
1439 if (ret) {
1440 GEM_BUG_ON(ret == -EIO);
1441 goto err_unlock;
1442 }
1443
1444 ret = i915_gem_init_scratch(dev_priv,
1445 IS_GEN(dev_priv, 2) ? SZ_256K :
PAGE_SIZE);
1446 if (ret) {
1447 GEM_BUG_ON(ret == -EIO);
1448 goto err_ggtt;
1449 }
1450
1451 ret = intel_engines_setup(dev_priv);
1452 if (ret) {
1453 GEM_BUG_ON(ret == -EIO);
1454 goto err_unlock;
1455 }
1456
1457 ret = i915_gem_contexts_init(dev_priv);
1458 if (ret) {
1459 GEM_BUG_ON(ret == -EIO);
1460 goto err_scratch;
1461 }
1462
1463 ret = intel_engines_init(dev_priv);
1464 if (ret) {
1465 GEM_BUG_ON(ret == -EIO);
1466 goto err_context;
1467 }
1468
1469 intel_init_gt_powersave(dev_priv);
1470
1471 intel_uc_init(_priv->gt.uc);
1472
1473 ret = i915_gem_init_hw(dev_priv);
1474 if (ret)
1475 goto err_uc_init;
1476
1477 /* Only when the HW is re-initialised, can we replay the
requests */
1478 ret = intel_gt_resume(_priv->gt);
1479 if (ret)
1480 goto err_init_hw;
1481
1482 /*
1483 * Despite its name intel_init_clock_gating applies both display
1484 * clock gating workarounds; GT mmio workarounds and the
occasional
1485 * GT power context workaround. Worse, sometimes it includes a
context
1486 * register workaround which we need to apply before we record
the
1487 * default HW state for all contexts.
1488 *
1489 * FIXME: break up the workarounds and apply them at the right
time!
1490 */
1491 intel_init_clock_gating(dev_priv);
1492
1493 ret = intel_engi
Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0
Quoting Ramalingam C (2019-10-01 18:26:24)
> Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
> Wa_1604555607 associated to that register needs to be skipped.
>
> Signed-off-by: Ramalingam C
> cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 -
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> 2 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4049b876492a..c63d8c3df4d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct
> i915_wa_list *wal)
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> - if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
> +
> + /*
> +* Read of FF_MODE2 is broken on TGL A0.
> +* Hence skip the corresponding WA verification.
> +*/
> + if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
> + i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
> + wa->mask == FF_MODE2_TDS_TIMER_MASK)
> + continue;
This does not scale very well. You will note that wa_verify() already
includes a detail on which bits can be read back from HW.
-Chris
___
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607
Quoting Ramalingam C (2019-10-01 18:26:23)
> From: Michel Thierry
>
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
>
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
>
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ba65e5018978..4049b876492a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> + u32 val;
> +
> /* Wa_1409142259 */
> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> + /* Wa_1604555607:tgl */
> + val = I915_READ(FF_MODE2);
No, you can't use indiscriminate mmio access that may not match the engine
(engine->gt->uncore).
But really consider doing the rmw as part of the wa.
> + val &= ~FF_MODE2_TDS_TIMER_MASK;
> + val |= FF_MODE2_TDS_TIMER_128;
> + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> }
___
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Re: [Intel-gfx] [PATCH] drm/i915/display: abstract all vgaarb access to intel_vga.[ch]
On Tue, Oct 01, 2019 at 06:25:06PM +0300, Jani Nikula wrote:
> Split out the code related to vga client and vgaarb all over the place
> into new intel_vga.[ch]. No functional changes.
>
> Cc: Ville Syrjälä
> Cc: Chris Wilson
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 97 +--
> drivers/gpu/drm/i915/display/intel_display.h | 3 -
> .../drm/i915/display/intel_display_power.c| 24 +--
> drivers/gpu/drm/i915/display/intel_vga.c | 160 ++
> drivers/gpu/drm/i915/display/intel_vga.h | 18 ++
> drivers/gpu/drm/i915/i915_drv.c | 30 +---
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> drivers/gpu/drm/i915/i915_suspend.c | 3 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 1 -
> 10 files changed, 194 insertions(+), 146 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_vga.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_vga.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e04463d85401..d2b53b5add81 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -184,7 +184,8 @@ i915-y += \
> display/intel_psr.o \
> display/intel_quirks.o \
> display/intel_sprite.o \
> - display/intel_tc.o
> + display/intel_tc.o \
> + display/intel_vga.o
> i915-$(CONFIG_ACPI) += \
> display/intel_acpi.o \
> display/intel_opregion.o
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f1328c08f4ad..d99c59e97568 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -31,7 +31,6 @@
> #include
> #include
> #include
> -#include
>
> #include
> #include
> @@ -79,6 +78,7 @@
> #include "intel_sideband.h"
> #include "intel_sprite.h"
> #include "intel_tc.h"
> +#include "intel_vga.h"
>
> /* Primary plane formats for gen <= 3 */
> static const u32 i8xx_primary_formats[] = {
> @@ -4241,7 +4241,7 @@ __intel_display_resume(struct drm_device *dev,
> int i, ret;
>
> intel_modeset_setup_hw_state(dev, ctx);
> - i915_redisable_vga(to_i915(dev));
> + intel_vga_redisable(to_i915(dev));
>
> if (!state)
> return 0;
> @@ -15994,35 +15994,6 @@ void intel_init_display_hooks(struct
> drm_i915_private *dev_priv)
>
> }
>
> -static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
> -{
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - return VLV_VGACNTRL;
> - else if (INTEL_GEN(dev_priv) >= 5)
> - return CPU_VGACNTRL;
> - else
> - return VGACNTRL;
> -}
> -
> -/* Disable the VGA plane that we never use */
> -static void i915_disable_vga(struct drm_i915_private *dev_priv)
> -{
> - struct pci_dev *pdev = dev_priv->drm.pdev;
> - u8 sr1;
> - i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
> -
> - /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
> - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> - outb(SR01, VGA_SR_INDEX);
> - sr1 = inb(VGA_SR_DATA);
> - outb(sr1 | 1<<5, VGA_SR_DATA);
> - vga_put(pdev, VGA_RSRC_LEGACY_IO);
> - udelay(300);
> -
> - I915_WRITE(vga_reg, VGA_DISP_DISABLE);
> - POSTING_READ(vga_reg);
> -}
> -
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> intel_update_cdclk(i915);
> @@ -16288,7 +16259,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
> intel_update_max_cdclk(i915);
>
> /* Just disable it once at startup */
> - i915_disable_vga(i915);
> + intel_vga_disable(i915);
> intel_setup_outputs(i915);
>
> drm_modeset_lock_all(dev);
> @@ -16647,39 +16618,6 @@ static void intel_sanitize_encoder(struct
> intel_encoder *encoder)
> icl_sanitize_encoder_pll_mapping(encoder);
> }
>
> -void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
> -{
> - i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
> -
> - if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
> - DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> - i915_disable_vga(dev_priv);
> - }
> -}
> -
> -void i915_redisable_vga(struct drm_i915_private *dev_priv)
> -{
> - intel_wakeref_t wakeref;
> -
> - /*
> - * This function can be called both from intel_modeset_setup_hw_state or
> - * at a very early point in our resume sequence, where the power well
> - * structures are not yet restored. Since this function is at a very
> - * paranoid "someone might have enabled VGA while we were not looking"
> - * level, just check if the power well is enabled instead of trying to
> - * follow the "don't touch the power well if we don't need it" policy
> - *
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Polish intel_tv_mode_valid()
On Tue, 2019-10-01 at 18:46 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Drop the tv_mode NULL check since intel_tv_mode_find() never > actually returns NULL, and flip the condition around so that > the MODE_OK case is at the end, which is customary to all > the other .mode_valid() implementations. > Reviewed-by: José Roberto de Souza > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_tv.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_tv.c > b/drivers/gpu/drm/i915/display/intel_tv.c > index b70221f5112a..71c3f7e5df7d 100644 > --- a/drivers/gpu/drm/i915/display/intel_tv.c > +++ b/drivers/gpu/drm/i915/display/intel_tv.c > @@ -961,11 +961,10 @@ intel_tv_mode_valid(struct drm_connector > *connector, > return MODE_CLOCK_HIGH; > > /* Ensure TV refresh is close to desired refresh */ > - if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * > 1000) > - < 1000) > - return MODE_OK; > + if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= > 1000) > + return MODE_CLOCK_RANGE; > > - return MODE_CLOCK_RANGE; > + return MODE_OK; > } > > static int ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0
Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
Wa_1604555607 associated to that register needs to be skipped.
Signed-off-by: Ramalingam C
cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 -
drivers/gpu/drm/i915/i915_drv.h | 6 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4049b876492a..c63d8c3df4d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct
i915_wa_list *wal)
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
- if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+
+ /*
+* Read of FF_MODE2 is broken on TGL A0.
+* Hence skip the corresponding WA verification.
+*/
+ if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
+ i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
+ wa->mask == FF_MODE2_TDS_TIMER_MASK)
+ continue;
+
wa_verify(wa,
intel_uncore_read_fw(uncore, wa->reg),
wal->name, "application");
+ }
}
intel_uncore_forcewake_put__locked(uncore, fw);
@@ -1553,6 +1564,15 @@ static int engine_wa_list_verify(struct intel_context
*ce,
if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
continue;
+ /*
+* Read of FF_MODE2 is broken on TGL A0.
+* Hence skip the corresponding WA verification.
+*/
+ if (IS_TGL_REVID(rq->i915, 0, TGL_REVID_A0) &&
+ i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
+ wa->mask == FF_MODE2_TDS_TIMER_MASK)
+ continue;
+
if (!wa_verify(wa, results[i], wal->name, from))
err = -ENXIO;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..05bf0b398ce7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2065,6 +2065,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ICL_REVID(p, since, until) \
(IS_ICELAKE(p) && IS_REVID(p, since, until))
+#define TGL_REVID_A0 0x0
+#define TGL_REVID_B0 0x1
+
+#define IS_TGL_REVID(p, since, until) \
+ (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607
From: Michel Thierry
Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.
v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 5 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ba65e5018978..4049b876492a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ struct drm_i915_private *dev_priv = engine->i915;
+ u32 val;
+
/* Wa_1409142259 */
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+ /* Wa_1604555607:tgl */
+ val = I915_READ(FF_MODE2);
+ val &= ~FF_MODE2_TDS_TIMER_MASK;
+ val |= FF_MODE2_TDS_TIMER_128;
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..ff19b8c80b40 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7775,6 +7775,11 @@ enum {
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PER_PIXEL_ALPHA_BYPASS_EN(1 << 7)
+#define FF_MODE2 _MMIO(0x6604)
+#define FF_MODE2_TDS_TIMER_SHIFT (16)
+#define FF_MODE2_TDS_TIMER_128 (4 << FF_MODE2_TDS_TIMER_SHIFT)
+#define FF_MODE2_TDS_TIMER_MASK (0xff << FF_MODE2_TDS_TIMER_SHIFT)
+
/* PCH */
#define PCH_DISPLAY_BASE 0xcu
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/print: add and use drm_debug_enabled() (rev3)
== Series Details ==
Series: drm/print: add and use drm_debug_enabled() (rev3)
URL : https://patchwork.freedesktop.org/series/66656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6985 -> Patchwork_14611
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/index.html
Known issues
Here are the changes found in Patchwork_14611 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_module_load@reload-no-display:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
- {fi-tgl-u2}:[INCOMPLETE][11] ([fdo#111850]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-tgl-u2/igt@gem_exec_susp...@basic-s4-devices.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-tgl-u2/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][13] ([fdo#102614]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) ->
[FAIL][16] ([fdo#111407])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14611/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
Participating hosts (51 -> 45)
--
Additional (3): fi-cml-h fi-apl-guc fi-pnv-d510
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks
fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6985 -> Patchwork_14611
CI-20190529: 20190529
CI_DRM_6985: 75d23ba38b952a5f3d0fc42baf1df2d15c5e74b1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14611: dee3ed02e6bd5fd3c1ceb728e7db2efe9fe0e0c3 @
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Limit MST modes based on plane size too
On Tue, 2019-10-01 at 18:46 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> When adding the max plane size checks to the .mode_valid() hooks
> I naturally forgot about MST. Take care of that one as well.
Reviewed-by: José Roberto de Souza
>
> Cc: Manasi Navare
> Cc: Sean Paul
> Cc: José Roberto de Souza
> Cc: Maarten Lankhorst
> Fixes: 2d20411e25a3 ("drm/i915: Don't advertise modes that exceed the
> max plane size")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index df4f35c10a69..2203be28ea01 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -424,6 +424,7 @@ static enum drm_mode_status
> intel_dp_mst_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> {
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_connector *intel_connector =
> to_intel_connector(connector);
> struct intel_dp *intel_dp = intel_connector->mst_port;
> int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> @@ -451,7 +452,7 @@ intel_dp_mst_mode_valid(struct drm_connector
> *connector,
> if (mode_rate > max_rate || mode->clock > max_dotclk)
> return MODE_CLOCK_HIGH;
>
> - return MODE_OK;
> + return intel_mode_valid_max_plane_size(dev_priv, mode);
> }
>
> static struct drm_encoder *intel_mst_atomic_best_encoder(struct
> drm_connector *connector,
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 15/23] drm/i915: Link planes in a bigjoiner configuration.
On Tue, Oct 01, 2019 at 09:44:09AM -0700, Matt Roper wrote:
> On Fri, Sep 20, 2019 at 01:42:27PM +0200, Maarten Lankhorst wrote:
> > Make sure that when a plane is set in a bigjoiner mode, we will add
> > their counterpart to the atomic state as well. This will allow us to
> > make sure all state is available when planes are checked.
> >
> > Because of the funny interactions with bigjoiner and planar YUV
> > formats, we may end up adding a lot of planes, so we have to keep
> > iterating until we no longer add any planes.
> >
> > Signed-off-by: Maarten Lankhorst
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 31 +++-
> > .../gpu/drm/i915/display/intel_atomic_plane.h | 4 +
> > drivers/gpu/drm/i915/display/intel_display.c | 142 --
> > .../drm/i915/display/intel_display_types.h| 11 ++
> > 4 files changed, 172 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 964db7774d10..cc088676f0a2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -182,16 +182,36 @@ int intel_plane_atomic_check_with_state(const struct
> > intel_crtc_state *old_crtc_
> >old_plane_state,
> > new_plane_state);
> > }
> >
> > -static struct intel_crtc *
> > -get_crtc_from_states(const struct intel_plane_state *old_plane_state,
> > -const struct intel_plane_state *new_plane_state)
> > -{
> > +struct intel_crtc *
> > +intel_plane_get_crtc_from_states(struct intel_atomic_state *state,
>
> This function name seems ambiguous now since it isn't clear whether
> we're getting the plane's hardware CRTC or its uapi CRTC. Maybe call it
> something like intel_plane_state_get_uapi_crtc()?
I was actually wondering if we shouldn't just do
get_crtc(plane->pipe) here. We still don't expose any planes
that can switch pipes so feels like this stuff is unecessary
complexity we don't particularly need.
>
>
>
> > +const struct intel_plane_state
> > *old_plane_state,
> > +const struct intel_plane_state
> > *new_plane_state)
> > + {
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
> > +
> > if (new_plane_state->base.crtc)
> > return to_intel_crtc(new_plane_state->base.crtc);
> >
> > if (old_plane_state->base.crtc)
> > return to_intel_crtc(old_plane_state->base.crtc);
> >
> > + if (new_plane_state->bigjoiner_slave) {
> > + const struct intel_plane_state *new_master_plane_state =
> > + intel_atomic_get_new_plane_state(state,
> > new_plane_state->bigjoiner_plane);
> > +
> > + if (new_master_plane_state->base.crtc)
> > + return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
> > + }
>
> Will this cause problems if we adjust properties of planes on a a
> uapi-disabled CRTC? E.g., I believe userspace can fiddle with stuff
> like rotation properties on disabled planes/crtcs and now I believe that
> causes us to needlessly pull in the bigjoiner master crtc and
> corresponding plane?
Not sure it's worth the effort to really try to avoid such things. If
userspace keeps fiddling with disabled stuff all the time it feels a
bit broken to me.
On a semi-related note I've occasionally pondered about trying to
filter out nop commits which don't send out events, even on active
planes/crtcs. But I guess that's already starting to be a change to
the semantics so probably not something that could be done without
a new flag/etc.
>
> > +
> > + if (old_plane_state->bigjoiner_slave) {
> > + const struct intel_plane_state *old_master_plane_state =
> > + intel_atomic_get_old_plane_state(state,
> > old_plane_state->bigjoiner_plane);
> > +
> > + if (old_master_plane_state->base.crtc)
> > + return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
> > + }
> > +
> > return NULL;
> > }
> >
> > @@ -206,7 +226,8 @@ static int intel_plane_atomic_check(struct drm_plane
> > *_plane,
> > const struct intel_plane_state *old_plane_state =
> > intel_atomic_get_old_plane_state(state, plane);
> > struct intel_crtc *crtc =
> > - get_crtc_from_states(old_plane_state, new_plane_state);
> > + intel_plane_get_crtc_from_states(state, old_plane_state,
> > +new_plane_state);
> > const struct intel_crtc_state *old_crtc_state;
> > struct intel_crtc_state *new_crtc_state;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > index 33fb85cd3909..901a50e6e2d3 100644
> > ---
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Use a modparam to restrict exposed engines
== Series Details ==
Series: series starting with [1/2] drm/i915: Use a modparam to restrict exposed
engines
URL : https://patchwork.freedesktop.org/series/67450/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6985 -> Patchwork_14610
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14610 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14610, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14610/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14610:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14610/fi-bsw-n3050/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14610 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-bsw-n3050: [PASS][2] -> [INCOMPLETE][3] ([fdo#105876])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14610/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [INCOMPLETE][4] ([fdo#107718]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14610/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][6] ([fdo#102614]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14610/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][8] ([fdo#111045] / [fdo#111096]) -> [FAIL][9]
([fdo#111407])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14610/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111604]: https://bugs.freedesktop.org/show_bug.cgi?id=111604
[fdo#111714]: https://bugs.freedesktop.org/show_bug.cgi?id=111714
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (51 -> 45)
--
Additional (2): fi-cml-h fi-pnv-d510
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6985 -> Patchwork_14610
CI-20190529: 20190529
CI_DRM_6985: 75d23ba38b952a5f3d0fc42baf1df2d15c5e74b1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14610: e38072e0b2fa7bb6638f58c2d2b1d4c1c6075c87 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e38072e0b2fa drm/i915/tgl: Restrict availables engines to rcs0 by default
d9fbdccc5cd1 drm/i915: Use a modparam to restrict exposed engines
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14610/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 15/23] drm/i915: Link planes in a bigjoiner configuration.
On Fri, Sep 20, 2019 at 01:42:27PM +0200, Maarten Lankhorst wrote:
> Make sure that when a plane is set in a bigjoiner mode, we will add
> their counterpart to the atomic state as well. This will allow us to
> make sure all state is available when planes are checked.
>
> Because of the funny interactions with bigjoiner and planar YUV
> formats, we may end up adding a lot of planes, so we have to keep
> iterating until we no longer add any planes.
>
> Signed-off-by: Maarten Lankhorst
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 31 +++-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 4 +
> drivers/gpu/drm/i915/display/intel_display.c | 142 --
> .../drm/i915/display/intel_display_types.h| 11 ++
> 4 files changed, 172 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 964db7774d10..cc088676f0a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -182,16 +182,36 @@ int intel_plane_atomic_check_with_state(const struct
> intel_crtc_state *old_crtc_
> old_plane_state,
> new_plane_state);
> }
>
> -static struct intel_crtc *
> -get_crtc_from_states(const struct intel_plane_state *old_plane_state,
> - const struct intel_plane_state *new_plane_state)
> -{
> +struct intel_crtc *
> +intel_plane_get_crtc_from_states(struct intel_atomic_state *state,
This function name seems ambiguous now since it isn't clear whether
we're getting the plane's hardware CRTC or its uapi CRTC. Maybe call it
something like intel_plane_state_get_uapi_crtc()?
> + const struct intel_plane_state
> *old_plane_state,
> + const struct intel_plane_state
> *new_plane_state)
> + {
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
> +
> if (new_plane_state->base.crtc)
> return to_intel_crtc(new_plane_state->base.crtc);
>
> if (old_plane_state->base.crtc)
> return to_intel_crtc(old_plane_state->base.crtc);
>
> + if (new_plane_state->bigjoiner_slave) {
> + const struct intel_plane_state *new_master_plane_state =
> + intel_atomic_get_new_plane_state(state,
> new_plane_state->bigjoiner_plane);
> +
> + if (new_master_plane_state->base.crtc)
> + return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
> + }
Will this cause problems if we adjust properties of planes on a a
uapi-disabled CRTC? E.g., I believe userspace can fiddle with stuff
like rotation properties on disabled planes/crtcs and now I believe that
causes us to needlessly pull in the bigjoiner master crtc and
corresponding plane?
> +
> + if (old_plane_state->bigjoiner_slave) {
> + const struct intel_plane_state *old_master_plane_state =
> + intel_atomic_get_old_plane_state(state,
> old_plane_state->bigjoiner_plane);
> +
> + if (old_master_plane_state->base.crtc)
> + return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
> + }
> +
> return NULL;
> }
>
> @@ -206,7 +226,8 @@ static int intel_plane_atomic_check(struct drm_plane
> *_plane,
> const struct intel_plane_state *old_plane_state =
> intel_atomic_get_old_plane_state(state, plane);
> struct intel_crtc *crtc =
> - get_crtc_from_states(old_plane_state, new_plane_state);
> + intel_plane_get_crtc_from_states(state, old_plane_state,
> + new_plane_state);
> const struct intel_crtc_state *old_crtc_state;
> struct intel_crtc_state *new_crtc_state;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 33fb85cd3909..901a50e6e2d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -42,5 +42,9 @@ int intel_plane_atomic_calc_changes(const struct
> intel_crtc_state *old_crtc_stat
> struct intel_crtc_state *crtc_state,
> const struct intel_plane_state
> *old_plane_state,
> struct intel_plane_state *plane_state);
> +struct intel_crtc *
> +intel_plane_get_crtc_from_states(struct intel_atomic_state *state,
> + const struct intel_plane_state
> *old_plane_state,
> + const struct intel_plane_state
> *new_plane_state);
>
> #endif /* __INTEL_ATOMIC_PLANE_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index
Re: [Intel-gfx] [PATCH 2/2] drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms
Quoting Kai Vehmanen (2019-10-01 17:35:55) > The CDCLK>=2*BCLK constraint applies to all generations since gen10. > Extend the constraint logic in audio get/put_power(). > > Signed-off-by: Kai Vehmanen > --- > drivers/gpu/drm/i915/display/intel_audio.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c > b/drivers/gpu/drm/i915/display/intel_audio.c > index a731af7ada08..031d7e53c7fa 100644 > --- a/drivers/gpu/drm/i915/display/intel_audio.c > +++ b/drivers/gpu/drm/i915/display/intel_audio.c > @@ -860,7 +860,7 @@ static unsigned long > i915_audio_component_get_power(struct device *kdev) > } > > /* Force CDCLK to 2*BCLK as long as we need audio powered. */ > - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) > + if (INTEL_GEN(dev_priv) >= 10) glk is only gen9 -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: split out intel_vga_client.[ch]
== Series Details ==
Series: drm/i915/display: split out intel_vga_client.[ch]
URL : https://patchwork.freedesktop.org/series/67447/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6985 -> Patchwork_14608
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/index.html
Known issues
Here are the changes found in Patchwork_14608 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_fence@basic-wait-default:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
- {fi-tgl-u2}:[INCOMPLETE][9] ([fdo#111850]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-tgl-u2/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/fi-tgl-u2/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
Participating hosts (51 -> 45)
--
Additional (3): fi-cml-h fi-apl-guc fi-pnv-d510
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6985 -> Patchwork_14608
CI-20190529: 20190529
CI_DRM_6985: 75d23ba38b952a5f3d0fc42baf1df2d15c5e74b1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14608: b1b290f96d251c72f87c81d5878eed6c5282c8ca @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b1b290f96d25 drm/i915/display: split out intel_vga_client.[ch]
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14608/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Use a modparam to restrict exposed engines
== Series Details == Series: series starting with [1/2] drm/i915: Use a modparam to restrict exposed engines URL : https://patchwork.freedesktop.org/series/67450/ State : warning == Summary == $ dim checkpatch origin/drm-tip d9fbdccc5cd1 drm/i915: Use a modparam to restrict exposed engines -:109: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #109: FILE: drivers/gpu/drm/i915/i915_params.c:48: +i915_param_named(engines, uint, 0400, + "Only expose selected command streamers [GPU engines] (0=disable GPU, " total: 0 errors, 0 warnings, 1 checks, 87 lines checked e38072e0b2fa drm/i915/tgl: Restrict availables engines to rcs0 by default ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms
The CDCLK>=2*BCLK constraint applies to all generations since gen10. Extend the constraint logic in audio get/put_power(). Signed-off-by: Kai Vehmanen --- drivers/gpu/drm/i915/display/intel_audio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index a731af7ada08..031d7e53c7fa 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -860,7 +860,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) } /* Force CDCLK to 2*BCLK as long as we need audio powered. */ - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) glk_force_audio_cdclk(dev_priv, true); if (INTEL_GEN(dev_priv) == 11 || INTEL_GEN(dev_priv) == 10) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Fix audio power up sequence for gen10/11
On gen10/11 platforms, driver must set the enable bit of AUD_PIN_BUF_CTL
as part of audio power up sequence.
Failing to do this resulted in errors during display audio codec probe,
and failures during resume from suspend.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 54638d99e021..a731af7ada08 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -862,6 +862,11 @@ static unsigned long i915_audio_component_get_power(struct
device *kdev)
/* Force CDCLK to 2*BCLK as long as we need audio powered. */
if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, true);
+
+ if (INTEL_GEN(dev_priv) == 11 || INTEL_GEN(dev_priv) == 10)
+ I915_WRITE(AUD_PIN_BUF_CTL,
+ (I915_READ(AUD_PIN_BUF_CTL) |
+ AUD_PIN_BUF_ENABLE));
}
return ret;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..daff9058f0e8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9133,6 +9133,8 @@ enum {
#define SKL_AUD_CODEC_WAKE_SIGNAL(1 << 15)
#define AUD_FREQ_CNTRL _MMIO(0x65900)
+#define AUD_PIN_BUF_CTL_MMIO(0x48414)
+#define AUD_PIN_BUF_ENABLE BIT(31)
/*
* HSW - ICL power wells
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Conclude load -> probe naming convention switch
== Series Details == Series: Conclude load -> probe naming convention switch URL : https://patchwork.freedesktop.org/series/67448/ State : failure == Summary == Series 67448 revision 1 Test-with: <20191001132728.14602-1-janusz.krzyszto...@linux.intel.com> not found ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: split out intel_vga_client.[ch]
== Series Details == Series: drm/i915/display: split out intel_vga_client.[ch] URL : https://patchwork.freedesktop.org/series/67447/ State : warning == Summary == $ dim checkpatch origin/drm-tip b1b290f96d25 drm/i915/display: split out intel_vga_client.[ch] -:91: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #91: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 363 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Describe structure members in documentation
== Series Details ==
Series: drm/i915: Describe structure members in documentation
URL : https://patchwork.freedesktop.org/series/67442/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6985 -> Patchwork_14607
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/index.html
Known issues
Here are the changes found in Patchwork_14607 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109483])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_busy@basic-wait-after-default:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
Participating hosts (51 -> 46)
--
Additional (2): fi-cml-h fi-apl-guc
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6985 -> Patchwork_14607
CI-20190529: 20190529
CI_DRM_6985: 75d23ba38b952a5f3d0fc42baf1df2d15c5e74b1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14607: dafb0e4db5d73ca8538b6b512eb69610ef3f7591 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dafb0e4db5d7 drm/i915: Describe structure members in documentation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14607/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/selftests: Exercise potential false lite-restore
If execlists's lite-restore is based on the common GEM context tag
rather than the per-intel_context LRCA, then a context switch between
two intel_contexts on the same engine derived from the same GEM context
will perform a lite-restore instead of a full context switch. We can
exploit this by poisoning the ringbuffer of the first context and trying
to trick a simple RING_TAIL update (i.e. lite-restore)
v2: Also check what happens if preempt ce[0] with ce[1] (both instances
on the same engine from the same parent context) [Tvrtko]
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
Fixup GEM_BUG_ON to look at rq->tail only after it is set!
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 174 +
1 file changed, 174 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 93f2fcdc49bf..f4d6a1b734ae 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -79,6 +79,178 @@ static int live_sanitycheck(void *arg)
return err;
}
+static int live_unlite_restore(struct drm_i915_private *i915, int prio)
+{
+ struct intel_engine_cs *engine;
+ struct i915_gem_context *ctx;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ struct igt_spinner spin;
+ int err = -ENOMEM;
+
+ /*
+* Check that we can correctly context switch between 2 instances
+* on the same engine from the same parent context.
+*/
+
+ mutex_lock(>drm.struct_mutex);
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
+ if (igt_spinner_init(, >gt))
+ goto err_unlock;
+
+ ctx = kernel_context(i915);
+ if (!ctx)
+ goto err_spin;
+
+ err = 0;
+ for_each_engine(engine, i915, id) {
+ struct intel_context *ce[2] = {};
+ struct i915_request *rq[2];
+ struct igt_live_test t;
+ int n;
+
+ if (prio && !intel_engine_has_preemption(engine))
+ continue;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ if (igt_live_test_begin(, i915, __func__, engine->name)) {
+ err = -EIO;
+ break;
+ }
+
+ for (n = 0; n < ARRAY_SIZE(ce); n++) {
+ struct intel_context *tmp;
+
+ tmp = intel_context_create(ctx, engine);
+ if (IS_ERR(tmp)) {
+ err = PTR_ERR(tmp);
+ goto err_ce;
+ }
+
+ err = intel_context_pin(tmp);
+ if (err) {
+ intel_context_put(tmp);
+ goto err_ce;
+ }
+
+ /*
+* Setup the pair of contexts such that if we
+* lite-restore using the RING_TAIL from ce[1] it
+* will execute garbage from ce[0]->ring.
+*/
+ memset(tmp->ring->vaddr,
+ POISON_INUSE, /* IPEHR: 0x5a5a5a5a [hung!] */
+ tmp->ring->vma->size);
+
+ ce[n] = tmp;
+ }
+ GEM_BUG_ON(!ce[1]->ring->size);
+ intel_ring_reset(ce[1]->ring, ce[1]->ring->size / 2);
+ __execlists_update_reg_state(ce[1], engine);
+
+
+ rq[0] = igt_spinner_create_request(, ce[0], MI_ARB_CHECK);
+ if (IS_ERR(rq[0])) {
+ err = PTR_ERR(rq[0]);
+ goto err_ce;
+ }
+
+ i915_request_get(rq[0]);
+ i915_request_add(rq[0]);
+ GEM_BUG_ON(rq[0]->tail > ce[1]->ring->emit);
+
+ if (!igt_wait_for_spinner(, rq[0])) {
+ i915_request_put(rq[0]);
+ goto err_ce;
+ }
+
+ rq[1] = i915_request_create(ce[1]);
+ if (IS_ERR(rq[1])) {
+ err = PTR_ERR(rq[1]);
+ i915_request_put(rq[0]);
+ goto err_ce;
+ }
+
+ if (!prio) {
+ /*
+* Ensure we do the switch to ce[1] on completion.
+*
+* rq[0] is already submitted, so this should reduce
+* to a no-op (a wait on a request on the same engine
+* uses the submit fence, not the completion fence),
+* but it will install a dependency on rq[1] for rq[0]
+* that will prevent the pair being reordered by
+* timeslicing.
+*/
+
[Intel-gfx] [PATCH 1/2] drm/i915: Limit MST modes based on plane size too
From: Ville Syrjälä
When adding the max plane size checks to the .mode_valid() hooks
I naturally forgot about MST. Take care of that one as well.
Cc: Manasi Navare
Cc: Sean Paul
Cc: José Roberto de Souza
Cc: Maarten Lankhorst
Fixes: 2d20411e25a3 ("drm/i915: Don't advertise modes that exceed the max plane
size")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index df4f35c10a69..2203be28ea01 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -424,6 +424,7 @@ static enum drm_mode_status
intel_dp_mst_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_connector *intel_connector = to_intel_connector(connector);
struct intel_dp *intel_dp = intel_connector->mst_port;
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
@@ -451,7 +452,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
if (mode_rate > max_rate || mode->clock > max_dotclk)
return MODE_CLOCK_HIGH;
- return MODE_OK;
+ return intel_mode_valid_max_plane_size(dev_priv, mode);
}
static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector
*connector,
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Polish intel_tv_mode_valid()
From: Ville Syrjälä Drop the tv_mode NULL check since intel_tv_mode_find() never actually returns NULL, and flip the condition around so that the MODE_OK case is at the end, which is customary to all the other .mode_valid() implementations. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_tv.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index b70221f5112a..71c3f7e5df7d 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -961,11 +961,10 @@ intel_tv_mode_valid(struct drm_connector *connector, return MODE_CLOCK_HIGH; /* Ensure TV refresh is close to desired refresh */ - if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) - < 1000) - return MODE_OK; + if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000) + return MODE_CLOCK_RANGE; - return MODE_CLOCK_RANGE; + return MODE_OK; } static int -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: Create dumb buffer from LMEM (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Create dumb buffer from LMEM (rev2)
URL : https://patchwork.freedesktop.org/series/67428/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/gem/i915_gem_domain.o
drivers/gpu/drm/i915/gem/i915_gem_domain.c: In function
‘i915_gem_object_pin_to_display_plane’:
drivers/gpu/drm/i915/gem/i915_gem_domain.c:429:6: error: implicit declaration
of function ‘HAS_LMEM’; did you mean ‘HAS_GMCH’?
[-Werror=implicit-function-declaration]
if (HAS_LMEM(i915))
^~~~
HAS_GMCH
drivers/gpu/drm/i915/gem/i915_gem_domain.c:430:14: error: ‘struct ’
has no member named ‘region’
if (obj->mm.region->type != INTEL_LMEM) {
^
drivers/gpu/drm/i915/gem/i915_gem_domain.c:430:31: error: ‘INTEL_LMEM’
undeclared (first use in this function); did you mean ‘INTEL_GM45’?
if (obj->mm.region->type != INTEL_LMEM) {
^~
INTEL_GM45
drivers/gpu/drm/i915/gem/i915_gem_domain.c:430:31: note: each undeclared
identifier is reported only once for each function it appears in
cc1: all warnings being treated as errors
scripts/Makefile.build:265: recipe for target
'drivers/gpu/drm/i915/gem/i915_gem_domain.o' failed
make[4]: *** [drivers/gpu/drm/i915/gem/i915_gem_domain.o] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1670: recipe for target 'drivers' failed
make: *** [drivers] Error 2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
On Tue, 01 Oct 2019, Ville Syrjälä wrote: > On Tue, Oct 01, 2019 at 05:28:51PM +0300, Jani Nikula wrote: >> On Tue, 01 Oct 2019, Ville Syrjälä wrote: >> > On Tue, Oct 01, 2019 at 03:12:49PM +0100, Chris Wilson wrote: >> >> Quoting Jani Nikula (2019-10-01 14:43:53) >> >> > Split out code related to vga client and vga switcheroo >> >> > register/unregister and state handling from i915_drv.c and >> >> > intel_display.c. >> >> > >> >> > It's a bit difficult to draw the line how much to move to the new file >> >> > from i915_drv.c, but it seemed to me keeping i915_suspend_switcheroo() >> >> > and i915_resume_switcheroo() in place was cleanest. >> >> > >> >> > No functional changes. >> >> > >> >> > Cc: Ville Syrjälä >> >> > Cc: Chris Wilson >> >> > Signed-off-by: Jani Nikula >> >> > >> >> > --- >> >> > >> >> > It's also a bit fuzzy if this is a sensible split anyway. Could also >> >> > name it intel_vga and move these from intel_display.c there? >> >> >> >> My initial thought that the switcheroo interface would remain in core, >> > >> > Yeah the switcheroo stuff should perhaps stays with the rest of the pm >> > hooks. >> >> Okay, so keep all of switcheroo in i915_drv.c, and move all the vgaarb >> stuff (incl the ones I mentioned from intel_display.c) to >> intel_vga.[ch]? > > I can get behind that plan. Patch in your inbox, I'll look into switcheroo later. BR, Jani. > >> >> > >> >> that it is more of a global power state that we currently just use for >> >> the legacy vga switching. >> >> >> >> The patch looks fine, on a pure mechanical pov, >> >> Reviewed-by: Chris Wilson >> >> >> >> For the sake of argument, could you float the split in the other >> >> direction? >> >> Please elaborate. Move switcheroo higher in the call chain? >> >> BR, >> Jani. >> >> >> >> >> >> And maybe Ville has a good opinion on how it is meant to work :) >> >> -Chris >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Initialise breadcrumb lists on the virtual engine (rev2)
== Series Details == Series: drm/i915: Initialise breadcrumb lists on the virtual engine (rev2) URL : https://patchwork.freedesktop.org/series/67373/ State : failure == Summary == Applying: drm/i915: Initialise breadcrumb lists on the virtual engine Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_lrc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: abstract all vgaarb access to intel_vga.[ch]
Split out the code related to vga client and vgaarb all over the place
into new intel_vga.[ch]. No functional changes.
Cc: Ville Syrjälä
Cc: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 97 +--
drivers/gpu/drm/i915/display/intel_display.h | 3 -
.../drm/i915/display/intel_display_power.c| 24 +--
drivers/gpu/drm/i915/display/intel_vga.c | 160 ++
drivers/gpu/drm/i915/display/intel_vga.h | 18 ++
drivers/gpu/drm/i915/i915_drv.c | 30 +---
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/i915_suspend.c | 3 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 -
10 files changed, 194 insertions(+), 146 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_vga.c
create mode 100644 drivers/gpu/drm/i915/display/intel_vga.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e04463d85401..d2b53b5add81 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -184,7 +184,8 @@ i915-y += \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
- display/intel_tc.o
+ display/intel_tc.o \
+ display/intel_vga.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
display/intel_opregion.o
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f1328c08f4ad..d99c59e97568 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -31,7 +31,6 @@
#include
#include
#include
-#include
#include
#include
@@ -79,6 +78,7 @@
#include "intel_sideband.h"
#include "intel_sprite.h"
#include "intel_tc.h"
+#include "intel_vga.h"
/* Primary plane formats for gen <= 3 */
static const u32 i8xx_primary_formats[] = {
@@ -4241,7 +4241,7 @@ __intel_display_resume(struct drm_device *dev,
int i, ret;
intel_modeset_setup_hw_state(dev, ctx);
- i915_redisable_vga(to_i915(dev));
+ intel_vga_redisable(to_i915(dev));
if (!state)
return 0;
@@ -15994,35 +15994,6 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
}
-static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
-{
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- return VLV_VGACNTRL;
- else if (INTEL_GEN(dev_priv) >= 5)
- return CPU_VGACNTRL;
- else
- return VGACNTRL;
-}
-
-/* Disable the VGA plane that we never use */
-static void i915_disable_vga(struct drm_i915_private *dev_priv)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
- u8 sr1;
- i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
-
- /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
- vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(SR01, VGA_SR_INDEX);
- sr1 = inb(VGA_SR_DATA);
- outb(sr1 | 1<<5, VGA_SR_DATA);
- vga_put(pdev, VGA_RSRC_LEGACY_IO);
- udelay(300);
-
- I915_WRITE(vga_reg, VGA_DISP_DISABLE);
- POSTING_READ(vga_reg);
-}
-
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
intel_update_cdclk(i915);
@@ -16288,7 +16259,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
intel_update_max_cdclk(i915);
/* Just disable it once at startup */
- i915_disable_vga(i915);
+ intel_vga_disable(i915);
intel_setup_outputs(i915);
drm_modeset_lock_all(dev);
@@ -16647,39 +16618,6 @@ static void intel_sanitize_encoder(struct
intel_encoder *encoder)
icl_sanitize_encoder_pll_mapping(encoder);
}
-void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
-{
- i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
-
- if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
- DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
- i915_disable_vga(dev_priv);
- }
-}
-
-void i915_redisable_vga(struct drm_i915_private *dev_priv)
-{
- intel_wakeref_t wakeref;
-
- /*
-* This function can be called both from intel_modeset_setup_hw_state or
-* at a very early point in our resume sequence, where the power well
-* structures are not yet restored. Since this function is at a very
-* paranoid "someone might have enabled VGA while we were not looking"
-* level, just check if the power well is enabled instead of trying to
-* follow the "don't touch the power well if we don't need it" policy
-* the rest of the driver uses.
-*/
- wakeref = intel_display_power_get_if_enabled(dev_priv,
-POWER_DOMAIN_VGA);
- if (!wakeref)
- return;
-
-
[Intel-gfx] ✓ Fi.CI.IGT: success for lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers (rev2)
== Series Details == Series: lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers (rev2) URL : https://patchwork.freedesktop.org/series/67405/ State : success == Summary == CI Bug Log - changes from CI_DRM_6981_full -> Patchwork_14602_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14602_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-apl3/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_reloc@basic-write-gtt-active: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-skl10/igt@gem_exec_re...@basic-write-gtt-active.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-skl3/igt@gem_exec_re...@basic-write-gtt-active.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +22 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-iclb2/igt@gem_exec_sched...@out-order-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-iclb8/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][9] -> [FAIL][10] ([fdo#103375]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-kbl7/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-kbl1/igt@gem_exec_susp...@basic-s3.html * igt@gem_userptr_blits@coherency-sync: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-hsw7/igt@gem_userptr_bl...@coherency-sync.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-hsw5/igt@gem_userptr_bl...@coherency-sync.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-kbl1/igt@gem_userptr_bl...@dmabuf-sync.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-kbl3/igt@gem_userptr_bl...@dmabuf-sync.html - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-skl8/igt@gem_userptr_bl...@dmabuf-sync.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-skl10/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-glk1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-glk4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-iclb2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-iclb6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#109385] / [fdo#111870]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-apl6/igt@gem_userptr_bl...@sync-unmap-after-close.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-apl6/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#103184] / [fdo#103232]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-skl3/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14602/shard-skl3/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html *
Re: [Intel-gfx] [PATCH v3] drm/print: add drm_debug_enabled()
On Tuesday, 2019-10-01 17:06:14 +0300, Jani Nikula wrote:
> Add helper to check if a drm debug category is enabled. Convert drm core
> to use it. No functional changes.
>
> v2: Move unlikely() to drm_debug_enabled() (Eric)
>
> v3: Keep unlikely() when combined with other conditions (Eric)
>
> Cc: Eric Engestrom
Reviewed-by: Eric Engestrom
> Acked-by: Alex Deucher
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 2 +-
> drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++---
> drivers/gpu/drm/drm_edid.c| 2 +-
> drivers/gpu/drm/drm_edid_load.c | 2 +-
> drivers/gpu/drm/drm_mipi_dbi.c| 4 ++--
> drivers/gpu/drm/drm_print.c | 4 ++--
> drivers/gpu/drm/drm_vblank.c | 6 +++---
> include/drm/drm_print.h | 5 +
> 8 files changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 7a26bfb5329c..0d466d3b0809 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -1405,7 +1405,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> } else if (arg->flags & DRM_MODE_ATOMIC_NONBLOCK) {
> ret = drm_atomic_nonblocking_commit(state);
> } else {
> - if (unlikely(drm_debug & DRM_UT_STATE))
> + if (drm_debug_enabled(DRM_UT_STATE))
> drm_atomic_print_state(state);
>
> ret = drm_atomic_commit(state);
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index e6801db54d0f..6b14b63b8d62 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -1179,7 +1179,7 @@ static int drm_dp_mst_wait_tx_reply(struct
> drm_dp_mst_branch *mstb,
> }
> }
> out:
> - if (unlikely(ret == -EIO && drm_debug & DRM_UT_DP)) {
> + if (unlikely(ret == -EIO) && drm_debug_enabled(DRM_UT_DP)) {
> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
>
> drm_dp_mst_dump_sideband_msg_tx(, txmsg);
> @@ -2322,7 +2322,7 @@ static int process_single_tx_qlock(struct
> drm_dp_mst_topology_mgr *mgr,
> idx += tosend + 1;
>
> ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
> - if (unlikely(ret && drm_debug & DRM_UT_DP)) {
> + if (unlikely(ret) && drm_debug_enabled(DRM_UT_DP)) {
> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
>
> drm_printf(, "sideband msg failed to send\n");
> @@ -2389,7 +2389,7 @@ static void drm_dp_queue_down_tx(struct
> drm_dp_mst_topology_mgr *mgr,
> mutex_lock(>qlock);
> list_add_tail(>next, >tx_msg_downq);
>
> - if (unlikely(drm_debug & DRM_UT_DP)) {
> + if (drm_debug_enabled(DRM_UT_DP)) {
> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
>
> drm_dp_mst_dump_sideband_msg_tx(, txmsg);
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 3c9703b08491..0552175313cb 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1651,7 +1651,7 @@ static void connector_bad_edid(struct drm_connector
> *connector,
> {
> int i;
>
> - if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
> + if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
> return;
>
> dev_warn(connector->dev->dev,
> diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
> index d38b3b255926..37d8ba3ddb46 100644
> --- a/drivers/gpu/drm/drm_edid_load.c
> +++ b/drivers/gpu/drm/drm_edid_load.c
> @@ -175,7 +175,7 @@ static void *edid_load(struct drm_connector *connector,
> const char *name,
> u8 *edid;
> int fwsize, builtin;
> int i, valid_extensions = 0;
> - bool print_bad_edid = !connector->bad_edid_counter || (drm_debug &
> DRM_UT_KMS);
> + bool print_bad_edid = !connector->bad_edid_counter ||
> drm_debug_enabled(DRM_UT_KMS);
>
> builtin = match_string(generic_edid_name, GENERIC_EDIDS, name);
> if (builtin >= 0) {
> diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c
> index f8154316a3b0..ccfb5b33c5e3 100644
> --- a/drivers/gpu/drm/drm_mipi_dbi.c
> +++ b/drivers/gpu/drm/drm_mipi_dbi.c
> @@ -783,7 +783,7 @@ static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi,
> int dc,
> int i, ret;
> u8 *dst;
>
> - if (drm_debug & DRM_UT_DRIVER)
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
>__func__, dc, max_chunk);
>
> @@ -907,7 +907,7 @@ static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi,
> int dc,
> max_chunk = dbi->tx_buf9_len;
> dst16 = dbi->tx_buf9;
>
> - if (drm_debug & DRM_UT_DRIVER)
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> pr_debug("[drm:%s] dc=%d,
Re: [RFC PATCH] iommu/vt-d: Fix IOMMU field not populated on device hot re-plug
Hi Baolu, On Tuesday, September 3, 2019 9:41:23 AM CEST Janusz Krzysztofik wrote: > Hi Baolu, > > On Tuesday, September 3, 2019 3:29:40 AM CEST Lu Baolu wrote: > > Hi Janusz, > > > > On 9/2/19 4:37 PM, Janusz Krzysztofik wrote: > > >> I am not saying that keeping data is not acceptable. I just want to > > >> check whether there are any other solutions. > > > Then reverting 458b7c8e0dde and applying this patch still resolves the > issue > > > for me. No errors appear when mappings are unmapped on device close > > > after > the > > > device has been removed, and domain info preserved on device removal is > > > successfully reused on device re-plug. > > > > This patch doesn't look good to me although I agree that keeping data is > > acceptable. Any progress with that? Which mailing list should I watch for updates? Thanks, Janusz > > It updates dev->archdata.iommu, but leaves the hardware > > context/pasid table unchanged. This might cause problems somewhere. > > > > > > > > Is there anything else I can do to help? > > > > Can you please tell me how to reproduce the problem? > > The most simple way to reproduce the issue, assuming there are no non-Intel > graphics adapters installed, is to run the following shell commands: > > #!/bin/sh > # load i915 module > modprobe i915 > # open an i915 device and keep it open in background > cat /dev/dri/card0 >/dev/null & > sleep 2 > # simulate device unplug > echo 1 >/sys/class/drm/card0/device/remove > # make the background process close the device on exit > kill $! > > Thanks, > Janusz > > > > Keeping the per > > device domain info while device is unplugged is a bit dangerous because > > info->dev might be a wild pointer. We need to work out a clean fix. > > > > > > > > Thanks, > > > Janusz > > > > > > > Best regards, > > Baolu > > > > > > >
Re: [Intel-gfx] [PATCH 1/4] drm/rect: Add drm_rect_translate_to()
On Tue, Oct 01, 2019 at 12:26:52PM +0300, Jani Nikula wrote:
> On Mon, 30 Sep 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add a helper to translate a rectangle to an absolute position.
> >
> > Signed-off-by: Ville Syrjälä
>
> The series is
>
> Reviewed-by: Jani Nikula
>
Thanks. 1-2 pushed to drm-misc-next.
>
>
> > ---
> > include/drm/drm_rect.h | 14 ++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
> > index 6195820aa5c5..fc7c14627ee2 100644
> > --- a/include/drm/drm_rect.h
> > +++ b/include/drm/drm_rect.h
> > @@ -106,6 +106,20 @@ static inline void drm_rect_translate(struct drm_rect
> > *r, int dx, int dy)
> > r->y2 += dy;
> > }
> >
> > +/**
> > + * drm_rect_translate_to - translate the rectangle to an absolute position
> > + * @r: rectangle to be tranlated
> > + * @x: horizontal position
> > + * @y: vertical position
> > + *
> > + * Move rectangle @r to @x in the horizontal direction,
> > + * and to @y in the vertical direction.
> > + */
> > +static inline void drm_rect_translate_to(struct drm_rect *r, int x, int y)
> > +{
> > + drm_rect_translate(r, x - r->x1, y - r->y1);
> > +}
> > +
> > /**
> > * drm_rect_downscale - downscale a rectangle
> > * @r: rectangle to be downscaled
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for RFT drm/i915/tgl: Re-enable rps (rev3)
== Series Details ==
Series: RFT drm/i915/tgl: Re-enable rps (rev3)
URL : https://patchwork.freedesktop.org/series/67398/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6984 -> Patchwork_14604
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/index.html
Known issues
Here are the changes found in Patchwork_14604 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] /
[fdo#111214])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/fi-icl-u3/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/fi-icl-u3/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927] / [fdo#111381]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_reloc@basic-cpu:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6984/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (53 -> 45)
--
Additional (1): fi-byt-j1900
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-kbl-7500u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6984 -> Patchwork_14604
CI-20190529: 20190529
CI_DRM_6984: 04d34ff324cf346bc962bb43eaa15572cafab08c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14604: 63d2c674198cbd0825a848b6a84c0cd83a65e4cf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
63d2c674198c RFT drm/i915/tgl: Re-enable rps
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14604/index.html
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[Intel-gfx] [PATCH v2 0/2] drm/i915: Conclude load -> probe naming convention switch
Test-with: <20191001142724.16472-2-janusz.krzyszto...@linux.intel.com> The purpose is: * to fix incompatible names of new functions introduced meanwhile, * to complete postponed rename of module parameter. v2: * drop unnecessary statement about custom user applications from commit message of 2/2, there are no such (Chris), * add R-b (thanks Chris), * use correct message ID of (also rerolled) IGT counterpart to be tested with. Janusz Krzysztofik (2): drm/i915: Fix i915_inject_load_error() name to read *_probe_* drm/i915: Rename "inject_load_failure" module parameter .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 ++-- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 ++- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_params.c| 2 +- drivers/gpu/drm/i915/i915_params.h| 2 +- drivers/gpu/drm/i915/i915_utils.c | 14 ++--- drivers/gpu/drm/i915/i915_utils.h | 12 +-- 9 files changed, 34 insertions(+), 32 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915: Rename "inject_load_failure" module parameter
Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
consequently") deliberately left the name of the module parameter
unchanged as that would require a corresponding change on IGT size.
Now as the IGT side change has been submitted, complete the switch to
the "probe" nomenclature.
Suggested-by: Joonas Lahtinen
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_params.c | 2 +-
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/i915_utils.c | 10 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..59a6586dae15 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -165,7 +165,7 @@ i915_param_named_unsafe(enable_dp_mst, bool, 0600,
"Enable multi-stream transport (MST) for new DisplayPort sinks.
(default: true)");
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
-i915_param_named_unsafe(inject_load_failure, uint, 0400,
+i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
#endif
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..8c887413fc70 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -62,7 +62,7 @@ struct drm_printer;
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO)) \
param(int, edp_vswing, 0) \
param(int, reset, 2) \
- param(unsigned int, inject_load_failure, 0) \
+ param(unsigned int, inject_probe_failure, 0) \
param(int, fastboot, -1) \
param(int, enable_dpcd_backlight, 0) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE) \
diff --git a/drivers/gpu/drm/i915/i915_utils.c
b/drivers/gpu/drm/i915/i915_utils.c
index e51bdb05da14..64affb87c284 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -57,22 +57,22 @@ static unsigned int i915_probe_fail_count;
int __i915_inject_probe_error(struct drm_i915_private *i915, int err,
const char *func, int line)
{
- if (i915_probe_fail_count >= i915_modparams.inject_load_failure)
+ if (i915_probe_fail_count >= i915_modparams.inject_probe_failure)
return 0;
- if (++i915_probe_fail_count < i915_modparams.inject_load_failure)
+ if (++i915_probe_fail_count < i915_modparams.inject_probe_failure)
return 0;
__i915_printk(i915, KERN_INFO,
"Injecting failure %d at checkpoint %u [%s:%d]\n",
- err, i915_modparams.inject_load_failure, func, line);
- i915_modparams.inject_load_failure = 0;
+ err, i915_modparams.inject_probe_failure, func, line);
+ i915_modparams.inject_probe_failure = 0;
return err;
}
bool i915_error_injected(void)
{
- return i915_probe_fail_count && !i915_modparams.inject_load_failure;
+ return i915_probe_fail_count && !i915_modparams.inject_probe_failure;
}
#endif
--
2.21.0
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Re: [Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
On Tue, Oct 01, 2019 at 05:28:51PM +0300, Jani Nikula wrote: > On Tue, 01 Oct 2019, Ville Syrjälä wrote: > > On Tue, Oct 01, 2019 at 03:12:49PM +0100, Chris Wilson wrote: > >> Quoting Jani Nikula (2019-10-01 14:43:53) > >> > Split out code related to vga client and vga switcheroo > >> > register/unregister and state handling from i915_drv.c and > >> > intel_display.c. > >> > > >> > It's a bit difficult to draw the line how much to move to the new file > >> > from i915_drv.c, but it seemed to me keeping i915_suspend_switcheroo() > >> > and i915_resume_switcheroo() in place was cleanest. > >> > > >> > No functional changes. > >> > > >> > Cc: Ville Syrjälä > >> > Cc: Chris Wilson > >> > Signed-off-by: Jani Nikula > >> > > >> > --- > >> > > >> > It's also a bit fuzzy if this is a sensible split anyway. Could also > >> > name it intel_vga and move these from intel_display.c there? > >> > >> My initial thought that the switcheroo interface would remain in core, > > > > Yeah the switcheroo stuff should perhaps stays with the rest of the pm > > hooks. > > Okay, so keep all of switcheroo in i915_drv.c, and move all the vgaarb > stuff (incl the ones I mentioned from intel_display.c) to > intel_vga.[ch]? I can get behind that plan. > > > > >> that it is more of a global power state that we currently just use for > >> the legacy vga switching. > >> > >> The patch looks fine, on a pure mechanical pov, > >> Reviewed-by: Chris Wilson > >> > >> For the sake of argument, could you float the split in the other > >> direction? > > Please elaborate. Move switcheroo higher in the call chain? > > BR, > Jani. > > > >> > >> And maybe Ville has a good opinion on how it is meant to work :) > >> -Chris > > -- > Jani Nikula, Intel Open Source Graphics Center -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915: Fix i915_inject_load_error() name to read *_probe_*
Commit 50d84418f586 ("drm/i915: Add i915 to i915_inject_probe_failure")
introduced new functions unfortunately named incompatibly with rules
established by commit f2db53f14d3d ("drm/i915: Replace "_load" with
"_probe" consequently"). Fix it for consistency.
Suggested-by: Michał Wajdeczko
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 ++-
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/i915_utils.c | 4 ++--
drivers/gpu/drm/i915/i915_utils.h | 12 +--
7 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..67e46c2af6df 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1119,7 +1119,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
enum intel_engine_id id;
int err;
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d4625c97b4f9..8295ff971bcc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -35,7 +35,7 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
void *vaddr;
int err;
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
@@ -134,7 +134,7 @@ int intel_huc_auth(struct intel_huc *huc)
if (!intel_uc_fw_is_loaded(>fw))
return -ENOEXEC;
- ret = i915_inject_load_error(gt->i915, -ENXIO);
+ ret = i915_inject_probe_error(gt->i915, -ENXIO);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 71ee7ab035cc..fb0d7bb712ab 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -20,7 +20,7 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
int ret;
u32 guc_status;
- ret = i915_inject_load_error(gt->i915, -ENXIO);
+ ret = i915_inject_probe_error(gt->i915, -ENXIO);
if (ret)
return ret;
@@ -197,7 +197,7 @@ static int guc_enable_communication(struct intel_guc *guc)
GEM_BUG_ON(guc_communication_enabled(guc));
- ret = i915_inject_load_error(i915, -ENXIO);
+ ret = i915_inject_probe_error(i915, -ENXIO);
if (ret)
return ret;
@@ -368,7 +368,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index bd22bf11adad..f6830ec79a66 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -218,29 +218,31 @@ static void __force_fw_fetch_failures(struct intel_uc_fw
*uc_fw,
{
bool user = e == -EINVAL;
- if (i915_inject_load_error(i915, e)) {
+ if (i915_inject_probe_error(i915, e)) {
/* non-existing blob */
uc_fw->path = "";
uc_fw->user_overridden = user;
- } else if (i915_inject_load_error(i915, e)) {
+ } else if (i915_inject_probe_error(i915, e)) {
/* require next major version */
uc_fw->major_ver_wanted += 1;
uc_fw->minor_ver_wanted = 0;
uc_fw->user_overridden = user;
- } else if (i915_inject_load_error(i915, e)) {
+ } else if (i915_inject_probe_error(i915, e)) {
/* require next minor version */
uc_fw->minor_ver_wanted += 1;
uc_fw->user_overridden = user;
- } else if (uc_fw->major_ver_wanted && i915_inject_load_error(i915, e)) {
+ } else if (uc_fw->major_ver_wanted &&
+ i915_inject_probe_error(i915, e)) {
/* require prev major version */
uc_fw->major_ver_wanted -= 1;
uc_fw->minor_ver_wanted = 0;
uc_fw->user_overridden = user;
- } else if (uc_fw->minor_ver_wanted && i915_inject_load_error(i915, e)) {
+ } else if
Re: [Intel-gfx] [PATCH] drm/i915/color: fix broken display in icl+
On Tue, Oct 01, 2019 at 07:58:39PM +0530, Sharma, Swati2 wrote:
> On 01-Oct-19 7:51 PM, Ville Syrjälä wrote:
> > On Tue, Oct 01, 2019 at 11:03:08AM +0300, Jani Nikula wrote:
> >> On Tue, 01 Oct 2019, Swati Sharma wrote:
> >>> Premature gamma lut prepration and loading which was getting
> >>> reflected in first modeset causing different colors on
> >>> screen during boot.
> >>>
> >>> Issue: In BIOS, gamma is disabled by default. However,
> >>> legacy_read_luts() was getting called even before the legacy_load_luts()
> >>> which was setting crtc_state->base.gamma_lut and gamma_lut was
> >>> programmed with junk values which led to visual artifacts (different
> >>> colored screens instead of usual black during boot).
> >>>
> >>> Fix: Calling read_luts() only when gamma is enabled which will happen
> >>> after first modeset.
> >>>
> >>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111809
> >>
> >> I'm confused. Is there a current problem upstream after the revert
> >> 1b8588741fdc ("Revert "drm/i915/color: Extract icl_read_luts()"")?
> >>
> >> Or does this fix a problem that only occurs in conjunction with the
> >> reverted commit? Then say so.
> >>
> >> Note inline.
> >>
> >>> Signed-off-by: Swati Sharma
> >>> ---
> >>> drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> >>> 1 file changed, 3 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >>> b/drivers/gpu/drm/i915/display/intel_display.c
> >>> index f1328c08f4ad..f89aa4bb9f42 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>> @@ -10528,7 +10528,9 @@ static bool haswell_get_pipe_config(struct
> >>> intel_crtc *crtc,
> >>> i9xx_get_pipe_color_config(pipe_config);
> >>> }
> >>>
> >>> - intel_color_get_config(pipe_config);
> >>> + if ((INTEL_GEN(dev_priv) >= 11 && (pipe_config->gamma_mode &
> >>> POST_CSC_GAMMA_ENABLE)) ||
> >>> +(INTEL_GEN(dev_priv) >= 9 && (pipe_config->gamma_enable)))
> >>> + intel_color_get_config(pipe_config);
> >>
> >> Put all of the conditions inside intel_color_get_config().
> >
> > In fact inside the .read_luts() since these checks are platform
> > specific.
> >
> > Also this check is wrong for CHV since it has a separate
> > enable knob for the CGM LUT (gamma_enable only deals with the
> > legacy LUT) >
> Inside read_luts() I already have. But the issue is first read_lut()
> will happen before load_lut() and it will replace
> crtc_state->base.gamma_lut and gamma_lut will be programmed with junk
> values which led to multiple colored screens. So we need a check to call
> intel_color_get_config() itself.
That doesn't make sense. If you're already checking these then
adding a second check won't change anything.
Also state readout is meant to just blindly readout the hardware state.
If the LUT used by the BIOS is enabled and not something we want to
use then we need to sanitize it after the readout.
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/color: fix broken display in icl+
HI,
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjälä
> Sent: tiistai 1. lokakuuta 2019 17.21
> To: Nikula, Jani
> Cc: intel-gfx@lists.freedesktop.org; Nautiyal, Ankit K
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/color: fix broken display in icl+
>
> On Tue, Oct 01, 2019 at 11:03:08AM +0300, Jani Nikula wrote:
> > On Tue, 01 Oct 2019, Swati Sharma wrote:
> > > Premature gamma lut prepration and loading which was getting
> > > reflected in first modeset causing different colors on screen during
> > > boot.
> > >
> > > Issue: In BIOS, gamma is disabled by default. However,
> > > legacy_read_luts() was getting called even before the
> > > legacy_load_luts() which was setting crtc_state->base.gamma_lut and
> > > gamma_lut was programmed with junk values which led to visual
> > > artifacts (different colored screens instead of usual black during boot).
> > >
> > > Fix: Calling read_luts() only when gamma is enabled which will
> > > happen after first modeset.
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111809
> >
> > I'm confused. Is there a current problem upstream after the revert
> > 1b8588741fdc ("Revert "drm/i915/color: Extract icl_read_luts()"")?
> >
> > Or does this fix a problem that only occurs in conjunction with the
> > reverted commit? Then say so.
> >
> > Note inline.
> >
> > > Signed-off-by: Swati Sharma
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index f1328c08f4ad..f89aa4bb9f42 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -10528,7 +10528,9 @@ static bool haswell_get_pipe_config(struct
> intel_crtc *crtc,
> > > i9xx_get_pipe_color_config(pipe_config);
> > > }
> > >
> > > - intel_color_get_config(pipe_config);
> > > + if ((INTEL_GEN(dev_priv) >= 11 && (pipe_config->gamma_mode &
> POST_CSC_GAMMA_ENABLE)) ||
> > > +(INTEL_GEN(dev_priv) >= 9 && (pipe_config->gamma_enable)))
> > > + intel_color_get_config(pipe_config);
> >
> > Put all of the conditions inside intel_color_get_config().
>
> In fact inside the .read_luts() since these checks are platform specific.
>
> Also this check is wrong for CHV since it has a separate enable knob for the
> CGM LUT
> (gamma_enable only deals with the legacy LUT).
Could this be also reason that on BSW I was able to see some color issue with
BSW on latest drm-tip still with Tapani?
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
Quoting Jani Nikula (2019-10-01 15:28:51) > On Tue, 01 Oct 2019, Ville Syrjälä wrote: > > On Tue, Oct 01, 2019 at 03:12:49PM +0100, Chris Wilson wrote: > >> For the sake of argument, could you float the split in the other > >> direction? > > Please elaborate. Move switcheroo higher in the call chain? I was thinking along the lines of pulling switcheroo into i915/i915_vga_client.c and seeing where that lead. I leave the details to the poor soul pulling at the stands of spaghetti. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
On Tue, 01 Oct 2019, Ville Syrjälä wrote: > On Tue, Oct 01, 2019 at 03:12:49PM +0100, Chris Wilson wrote: >> Quoting Jani Nikula (2019-10-01 14:43:53) >> > Split out code related to vga client and vga switcheroo >> > register/unregister and state handling from i915_drv.c and >> > intel_display.c. >> > >> > It's a bit difficult to draw the line how much to move to the new file >> > from i915_drv.c, but it seemed to me keeping i915_suspend_switcheroo() >> > and i915_resume_switcheroo() in place was cleanest. >> > >> > No functional changes. >> > >> > Cc: Ville Syrjälä >> > Cc: Chris Wilson >> > Signed-off-by: Jani Nikula >> > >> > --- >> > >> > It's also a bit fuzzy if this is a sensible split anyway. Could also >> > name it intel_vga and move these from intel_display.c there? >> >> My initial thought that the switcheroo interface would remain in core, > > Yeah the switcheroo stuff should perhaps stays with the rest of the pm hooks. Okay, so keep all of switcheroo in i915_drv.c, and move all the vgaarb stuff (incl the ones I mentioned from intel_display.c) to intel_vga.[ch]? > >> that it is more of a global power state that we currently just use for >> the legacy vga switching. >> >> The patch looks fine, on a pure mechanical pov, >> Reviewed-by: Chris Wilson >> >> For the sake of argument, could you float the split in the other >> direction? Please elaborate. Move switcheroo higher in the call chain? BR, Jani. >> >> And maybe Ville has a good opinion on how it is meant to work :) >> -Chris -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/color: fix broken display in icl+
On 01-Oct-19 7:51 PM, Ville Syrjälä wrote:
On Tue, Oct 01, 2019 at 11:03:08AM +0300, Jani Nikula wrote:
On Tue, 01 Oct 2019, Swati Sharma wrote:
Premature gamma lut prepration and loading which was getting
reflected in first modeset causing different colors on
screen during boot.
Issue: In BIOS, gamma is disabled by default. However,
legacy_read_luts() was getting called even before the legacy_load_luts()
which was setting crtc_state->base.gamma_lut and gamma_lut was
programmed with junk values which led to visual artifacts (different
colored screens instead of usual black during boot).
Fix: Calling read_luts() only when gamma is enabled which will happen
after first modeset.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111809
I'm confused. Is there a current problem upstream after the revert
1b8588741fdc ("Revert "drm/i915/color: Extract icl_read_luts()"")?
Or does this fix a problem that only occurs in conjunction with the
reverted commit? Then say so.
Note inline.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f1328c08f4ad..f89aa4bb9f42 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10528,7 +10528,9 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
i9xx_get_pipe_color_config(pipe_config);
}
- intel_color_get_config(pipe_config);
+ if ((INTEL_GEN(dev_priv) >= 11 && (pipe_config->gamma_mode &
POST_CSC_GAMMA_ENABLE)) ||
+ (INTEL_GEN(dev_priv) >= 9 && (pipe_config->gamma_enable)))
+ intel_color_get_config(pipe_config);
Put all of the conditions inside intel_color_get_config().
In fact inside the .read_luts() since these checks are platform
specific.
Also this check is wrong for CHV since it has a separate
enable knob for the CGM LUT (gamma_enable only deals with the
legacy LUT) >
Inside read_luts() I already have. But the issue is first read_lut()
will happen before load_lut() and it will replace
crtc_state->base.gamma_lut and gamma_lut will be programmed with junk
values which led to multiple colored screens. So we need a check to call
intel_color_get_config() itself.
--
~Swati Sharma
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[Intel-gfx] [PATCH v10 3/6] drm/i915/tgl: Enable DC3CO state in "DC Off" power well
Add target_dc_state and used by set_target_dc_state API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
v8: Uniform checks by using only target_dc_state instead of allowed_dc_mask
in "DC off" power well callback. [Imre]
Adding "DC off" power well id to older platforms. [Imre]
Removed psr2_deep_sleep flag from tgl_set_target_dc_state. [Imre]
v9: Used switch case for target DC state in
gen9_dc_off_power_well_disable(), checking DC3CO state against
allowed DC mask, using WARN_ON() in
tgl_set_target_dc_state(). [Imre]
v10: Code refactoring and using sanitize_target_dc_state(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 80 ---
.../drm/i915/display/intel_display_power.h| 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 73 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0b685c517bcb..67ba92dd8366 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -785,6 +785,52 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+static u32
+sanitize_target_dc_state(struct drm_i915_private *dev_priv,
+u32 target_dc_state)
+{
+ u32 states[] = {
+ DC_STATE_EN_UPTO_DC6,
+ DC_STATE_EN_UPTO_DC5,
+ DC_STATE_EN_DC3CO,
+ DC_STATE_DISABLE,
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
+ if (target_dc_state != states[i])
+ continue;
+
+ if (dev_priv->csr.allowed_dc_mask & target_dc_state)
+ break;
+
+ target_dc_state = states[i + 1];
+ }
+
+ return target_dc_state;
+}
+
+static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
+{
+ DRM_DEBUG_KMS("Enabling DC3CO\n");
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ DRM_DEBUG_KMS("Disabling DC3CO\n");
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+* Delay of 200us DC3CO Exit time B.Spec 49196
+*/
+ usleep_range(200, 210);
+}
+
static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -952,7 +998,8 @@ static void bxt_verify_ddi_phy_power_wells(struct
drm_i915_private *dev_priv)
static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
@@ -968,6 +1015,11 @@ static void gen9_disable_dc_states(struct
drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
+ if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
+ tgl_disable_dc3co(dev_priv);
+ return;
+ }
+
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
dev_priv->display.get_cdclk(dev_priv, _state);
@@ -1000,10 +1052,17 @@ static void gen9_dc_off_power_well_disable(struct
drm_i915_private *dev_priv,
if (!dev_priv->csr.dmc_payload)
return;
- if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ switch (dev_priv->csr.target_dc_state) {
+ case DC_STATE_EN_DC3CO:
+ tgl_enable_dc3co(dev_priv);
+ break;
+ case DC_STATE_EN_UPTO_DC6:
skl_enable_dc6(dev_priv);
- else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ break;
+
[Intel-gfx] [PATCH v10 5/6] drm/i915/tgl: Switch between dc3co and dc5 based on display idleness
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
B.Specs:49196 has a restriction to enable DC3CO only for Video Playback.
It will be worthy to enable DC3CO after completion of each pageflip
and switch back to DC5 when display is idle because driver doesn't
differentiate between video playback and a normal pageflip.
We will use Frontbuffer flush call tgl_dc3co_flush() to enable DC3CO
state only for ORIGIN_FLIP flush call, because DC3CO state has primarily
targeted for VPB use case. We are not interested here for frontbuffer
invalidates calls because that triggers PSR2 exit, which will
explicitly disable DC3CO.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
most PSR2 panel deep sleep entry requirement typically 4 frames.
As PSR2 existing implementation is using minimum 6 idle frames for
deep sleep, it is safer to enable DC5/6 after 6 idle frames
(By scheduling a delayed work of 6 idle frames, once DC3CO has been
enabled after a pageflip).
After manually waiting for 6 idle frames DC5/6 will be enabled and
PSR2 deep sleep idle frames will be restored to 6 idle frames, at this
point DMC will triggers DC5/6 once PSR2 enters to deep sleep after
6 idle frames.
In future when we will enable S/W PSR2 tracking, we can change the
PSR2 required deep sleep idle frames to 1 so DMC can trigger the
DC5/6 immediately after S/W manual waiting of 6 idle frames get
complete.
v2: calculated s/w state to switch over dc3co when there is an
update. [Imre]
Used cancel_delayed_work_sync() in order to avoid any race
with already scheduled delayed work. [Imre]
v3: Cancel_delayed_work_sync() may blocked the commit work.
hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: Used frontbuffer flush mechanism. [Imre]
v5: Used psr.pipe to extract frontbuffer busy bits. [Imre]
Used cancel_delayed_work_sync() in encoder disable path. [Imre]
Used mod_delayed_work() instead of cancelling and scheduling a
delayed work. [Imre]
Used psr.lock in tgl_dc5_idle_thread() to enable psr2 deep
sleep. [Imre]
Removed DC5_REQ_IDLE_FRAMES macro. [Imre]
v6: Used dc3co_exitline check instead of TGL and dc3co allowed_dc_mask
checks, used delayed_work_pending with the psr lock and removed the
psr2_deep_slp_disabled flag. [Imre]
v7: Code refactoring, moved most of functional code to inte_psr.c [Imre]
Using frontbuffer_bits on psr.pipe check instead of
busy_frontbuffer_bits. [Imre]
Calculating dc3co_exit_delay in intel_psr_enable_locked. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 45 +++
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 114 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
4 files changed, 163 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 67ba92dd8366..9fddebfda169 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -886,6 +886,51 @@ lookup_power_well(struct drm_i915_private *dev_priv,
return _priv->power_domains.power_wells[0];
}
+/**
+ * intel_display_power_set_target_dc_state - Set target dc state.
+ * @dev_priv: i915 device
+ * @state: state which needs to be set as target_dc_state.
+ *
+ * This function set the "DC off" power well target_dc_state,
+ * based upon this target_dc_stste, "DC off" power well will
+ * enable desired DC state.
+ */
+void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
+u32 state)
+{
+ struct i915_power_well *power_well;
+ bool dc_off_enabled;
+ struct i915_power_domains *power_domains = _priv->power_domains;
+
+ mutex_lock(_domains->lock);
+ power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
+
+ if (WARN_ON(!power_well))
+ goto unlock;
+
+ state = sanitize_target_dc_state(dev_priv, state);
+
+ if (state == dev_priv->csr.target_dc_state)
+ goto unlock;
+
+ dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
+ power_well);
+ /*
+* If DC off power well is disabled, need to enable and disable the
+* DC off power well to effect target DC state.
+*/
+ if (!dc_off_enabled)
+ power_well->desc->ops->enable(dev_priv, power_well);
+
+ dev_priv->csr.target_dc_state = state;
+
+
[Intel-gfx] [PATCH v10 6/6] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
v1: comment modification for DMC_DBUG3.
using GEN >= 12 check instead of IS_TIGERLAKE()
to print DMC_DEBUG3 counter value.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fec9fb7cc384..a3882e6abf68 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2413,6 +2413,13 @@ static int i915_dmc_info(struct seq_file *m, void
*unused)
if (INTEL_GEN(dev_priv) >= 12) {
dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+ /*
+* NOTE: DMC_DEBUG3 is a general purpose reg.
+* According to B.Specs:49196 DMC f/w reuses DC5/6 counter
+* reg for DC3CO debugging and validation,
+* but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
+*/
+ seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
} else {
dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
SKL_CSR_DC3_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 188d3b382627..e2940501d7a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7267,6 +7267,8 @@ enum {
#define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
#define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
+#define DMC_DEBUG3 _MMIO(0x101090)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE(1 << 29)
--
2.21.0
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[Intel-gfx] [PATCH v10 2/6] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index f1186bc23542..0b685c517bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -711,7 +711,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (INTEL_GEN(dev_priv) >= 11)
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
+ else if (IS_GEN(dev_priv, 11))
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -3940,14 +3944,17 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (INTEL_GEN(dev_priv) >= 11) {
- max_dc = 2;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
* suspend/resume, so allow it unconditionally.
*/
mask = DC_STATE_EN_DC9;
+ } else if (IS_GEN(dev_priv, 11)) {
+ max_dc = 2;
+ mask = DC_STATE_EN_DC9;
} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
max_dc = 2;
mask = 0;
@@ -3966,7 +3973,7 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
requested_dc = enable_dc;
} else if (enable_dc == -1) {
requested_dc = max_dc;
- } else if (enable_dc > max_dc && enable_dc <= 2) {
+ } else if (enable_dc > max_dc && enable_dc <= 4) {
DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
@@ -3975,10 +3982,20 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
requested_dc = max_dc;
}
- if (requested_dc > 1)
+ switch (requested_dc) {
+ case 4:
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+ break;
+ case 3:
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+ break;
+ case 2:
mask |= DC_STATE_EN_UPTO_DC6;
- if (requested_dc > 0)
+ break;
+ case 1:
mask |= DC_STATE_EN_UPTO_DC5;
+ break;
+ }
DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..4f1806f65040 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
- "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+ "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
i915_param_named_unsafe(enable_fbc, int, 0600,
"Enable frame buffer compression for power savings "
--
2.21.0
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Re: [Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
On Tue, Oct 01, 2019 at 03:12:49PM +0100, Chris Wilson wrote: > Quoting Jani Nikula (2019-10-01 14:43:53) > > Split out code related to vga client and vga switcheroo > > register/unregister and state handling from i915_drv.c and > > intel_display.c. > > > > It's a bit difficult to draw the line how much to move to the new file > > from i915_drv.c, but it seemed to me keeping i915_suspend_switcheroo() > > and i915_resume_switcheroo() in place was cleanest. > > > > No functional changes. > > > > Cc: Ville Syrjälä > > Cc: Chris Wilson > > Signed-off-by: Jani Nikula > > > > --- > > > > It's also a bit fuzzy if this is a sensible split anyway. Could also > > name it intel_vga and move these from intel_display.c there? > > My initial thought that the switcheroo interface would remain in core, Yeah the switcheroo stuff should perhaps stays with the rest of the pm hooks. > that it is more of a global power state that we currently just use for > the legacy vga switching. > > The patch looks fine, on a pure mechanical pov, > Reviewed-by: Chris Wilson > > For the sake of argument, could you float the split in the other > direction? > > And maybe Ville has a good opinion on how it is meant to work :) > -Chris -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 1/6] drm/i915/tgl: Add DC3CO required register and bits
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
DC3CO enable bit will be used by driver to make DC3CO
ready for DMC f/w and status bit will be used as DC3CO
entry status.
2. Transcoder EXITLINE register and its bit fields and mask.
Transcoder EXITLINE enable bit represents PSR2 idle frame
reset should be applied at exit line and exitlines mask
represent required number of scanlines at which DC3CO
exit happens.
B.Specs:49196
v1: Use of REG_BIT and using extra space for EXITLINE_ macro
definition. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..188d3b382627 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4144,6 +4144,7 @@ enum {
#define _VTOTAL_A 0x6000c
#define _VBLANK_A 0x60010
#define _VSYNC_A 0x60014
+#define _EXITLINE_A0x60018
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
@@ -4190,11 +4191,16 @@ enum {
#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)_MMIO_TRANS2(trans, _EXITLINE_A)
#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define EXITLINE_ENABLE REG_BIT(31)
+#define EXITLINE_MASKREG_GENMASK(12, 0)
+#define EXITLINE_SHIFT 0
+
/*
* HSW+ eDP PSR registers
*
@@ -10288,6 +10294,8 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN_MMIO(0x45504)
#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO REG_BIT(30)
+#define DC_STATE_DC3CO_STATUS REG_BIT(29)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.21.0
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[Intel-gfx] [PATCH v10 4/6] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset to enable and configure
DC3CO exitline.
v1: Computing dc3co_exitline crtc state from a DP encoder
compute config. [Imre]
Enabling and disabling DC3CO PSR2 transcoder exitline from
encoder pre_enable and post_disable hooks. [Imre]
Computing dc3co_exitline instead of has_dc3co_exitline bool. [Imre]
v2: Code refactoring for symmetry and to avoid exported function. [Imre]
Removing IS_TIGERLAKE check from compute_config, adding PIPE_A
restriction and clearing dc3co_exitline state if crtc is not active
or it is not PSR2 capable in dc3co exitline compute_config. [Imre]
Using GEN >= 12 check in dc3co exitline get_config. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++-
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h| 1 +
3 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b463e51f8b45..032c455446ec 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -45,6 +45,7 @@
#include "intel_lspcon.h"
#include "intel_panel.h"
#include "intel_psr.h"
+#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
@@ -3332,6 +,86 @@ static void intel_ddi_disable_fec_state(struct
intel_encoder *encoder,
POSTING_READ(intel_dp->regs.dp_tp_ctl);
}
+static void
+tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
+{
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ u32 val;
+
+ if (!cstate->dc3co_exitline)
+ return;
+
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static void
+tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
+{
+ u32 val, exit_scanlines;
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+ if (!cstate->dc3co_exitline)
+ return;
+
+ exit_scanlines = cstate->dc3co_exitline;
+ exit_scanlines <<= EXITLINE_SHIFT;
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ val |= exit_scanlines;
+ val |= EXITLINE_ENABLE;
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *cstate)
+{
+ u32 exit_scanlines;
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+
+ cstate->dc3co_exitline = 0;
+
+ if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ return;
+
+ /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
+ if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
+ encoder->port != PORT_A)
+ return;
+
+ if (!cstate->has_psr2 || !cstate->base.active)
+ return;
+
+ /*
+* DC3CO Exit time 200us B.Spec 49196
+* PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+*/
+ exit_scanlines =
+ intel_usecs_to_scanlines(>base.adjusted_mode, 200) + 1;
+
+ if (WARN_ON(exit_scanlines > crtc_vdisplay))
+ return;
+
+ cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
+ DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
+}
+
+static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
+{
+ u32 val;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+ if (INTEL_GEN(dev_priv) < 12)
+ return;
+
+ val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
+
+ if (val & EXITLINE_ENABLE)
+ crtc_state->dc3co_exitline = val & EXITLINE_MASK;
+}
+
static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -3344,6 +3425,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder
*encoder,
int level = intel_ddi_dp_level(intel_dp);
enum transcoder transcoder =
[Intel-gfx] [PATCH v10 0/6] DC3CO Support for TGL
Resending this version v10 after adding Imre's RB and after fixing few code refactoring related comments provided by Imre. Anshuman Gupta (6): drm/i915/tgl: Add DC3CO required register and bits drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask drm/i915/tgl: Enable DC3CO state in "DC Off" power well drm/i915/tgl: Do modeset to enable and configure DC3CO exitline drm/i915/tgl: Switch between dc3co and dc5 based on display idleness drm/i915/tgl: Add DC3CO counter in i915_dmc_info drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_power.c| 154 -- .../drm/i915/display/intel_display_power.h| 3 + .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_psr.c | 114 - drivers/gpu/drm/i915/i915_debugfs.c | 7 + drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_params.c| 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 10 files changed, 371 insertions(+), 19 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/color: fix broken display in icl+
On Tue, Oct 01, 2019 at 11:03:08AM +0300, Jani Nikula wrote:
> On Tue, 01 Oct 2019, Swati Sharma wrote:
> > Premature gamma lut prepration and loading which was getting
> > reflected in first modeset causing different colors on
> > screen during boot.
> >
> > Issue: In BIOS, gamma is disabled by default. However,
> > legacy_read_luts() was getting called even before the legacy_load_luts()
> > which was setting crtc_state->base.gamma_lut and gamma_lut was
> > programmed with junk values which led to visual artifacts (different
> > colored screens instead of usual black during boot).
> >
> > Fix: Calling read_luts() only when gamma is enabled which will happen
> > after first modeset.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111809
>
> I'm confused. Is there a current problem upstream after the revert
> 1b8588741fdc ("Revert "drm/i915/color: Extract icl_read_luts()"")?
>
> Or does this fix a problem that only occurs in conjunction with the
> reverted commit? Then say so.
>
> Note inline.
>
> > Signed-off-by: Swati Sharma
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index f1328c08f4ad..f89aa4bb9f42 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -10528,7 +10528,9 @@ static bool haswell_get_pipe_config(struct
> > intel_crtc *crtc,
> > i9xx_get_pipe_color_config(pipe_config);
> > }
> >
> > - intel_color_get_config(pipe_config);
> > + if ((INTEL_GEN(dev_priv) >= 11 && (pipe_config->gamma_mode &
> > POST_CSC_GAMMA_ENABLE)) ||
> > + (INTEL_GEN(dev_priv) >= 9 && (pipe_config->gamma_enable)))
> > + intel_color_get_config(pipe_config);
>
> Put all of the conditions inside intel_color_get_config().
In fact inside the .read_luts() since these checks are platform
specific.
Also this check is wrong for CHV since it has a separate
enable knob for the CGM LUT (gamma_enable only deals with the
legacy LUT).
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for RFT drm/i915/tgl: Re-enable rps (rev3)
== Series Details == Series: RFT drm/i915/tgl: Re-enable rps (rev3) URL : https://patchwork.freedesktop.org/series/67398/ State : warning == Summary == $ dim checkpatch origin/drm-tip 63d2c674198c RFT drm/i915/tgl: Re-enable rps -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one -:18: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 1 warnings, 0 checks, 7 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Rename "inject_load_failure" module parameter
Quoting Janusz Krzysztofik (2019-10-01 14:45:34)
> Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
> consequently") deliberately left the name of the module parameter
> unchanged as that would require a corresponding change on IGT size.
> Now as the IGT side change has been submitted, complete the switch to
> the "probe" nomenclature.
>
> May affect custom user applications utilizing the old name.
>
> Suggested-by: Joonas Lahtinen
> Signed-off-by: Janusz Krzysztofik
> Cc: Michał Wajdeczko
> Cc: Michał Winiarski
> Cc: Piotr Piórkowski
> Cc: Tomasz Lis
> Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix i915_inject_load_error() name to read *_probe_*
Quoting Janusz Krzysztofik (2019-10-01 14:45:33)
> Commit 50d84418f586 ("drm/i915: Add i915 to i915_inject_probe_failure")
> introduced new functions unfortunately named incompatibly with rules
> established by commit f2db53f14d3d ("drm/i915: Replace "_load" with
> "_probe" consequently"). Fix it for consistency.
>
> Suggested-by: Michał Wajdeczko
> Signed-off-by: Janusz Krzysztofik
> Cc: Michał Wajdeczko
> Cc: Michał Winiarski
> Cc: Piotr Piórkowski
> Cc: Tomasz Lis
> Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
Quoting Jani Nikula (2019-10-01 14:43:53) > Split out code related to vga client and vga switcheroo > register/unregister and state handling from i915_drv.c and > intel_display.c. > > It's a bit difficult to draw the line how much to move to the new file > from i915_drv.c, but it seemed to me keeping i915_suspend_switcheroo() > and i915_resume_switcheroo() in place was cleanest. > > No functional changes. > > Cc: Ville Syrjälä > Cc: Chris Wilson > Signed-off-by: Jani Nikula > > --- > > It's also a bit fuzzy if this is a sensible split anyway. Could also > name it intel_vga and move these from intel_display.c there? My initial thought that the switcheroo interface would remain in core, that it is more of a global power state that we currently just use for the legacy vga switching. The patch looks fine, on a pure mechanical pov, Reviewed-by: Chris Wilson For the sake of argument, could you float the split in the other direction? And maybe Ville has a good opinion on how it is meant to work :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for HAX: Force kmemleak off
== Series Details == Series: HAX: Force kmemleak off URL : https://patchwork.freedesktop.org/series/67436/ State : failure == Summary == Applying: HAX: Force kmemleak off Using index info to reconstruct a base tree... M mm/kmemleak.c Falling back to patching base and 3-way merge... Auto-merging mm/kmemleak.c CONFLICT (content): Merge conflict in mm/kmemleak.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 HAX: Force kmemleak off When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
On Tue, Oct 01, 2019 at 04:43:53PM +0300, Jani Nikula wrote:
> Split out code related to vga client and vga switcheroo
> register/unregister and state handling from i915_drv.c and
> intel_display.c.
The two things don't really have anything in common except both have
"vga" in the name, so not sure it makes sense to put them in the same
place. OTOH they are pretty small so probably not worth it to have two
files.
Also the vgaarb stuff is still broken but I guess no one really cares.
>
> It's a bit difficult to draw the line how much to move to the new file
> from i915_drv.c, but it seemed to me keeping i915_suspend_switcheroo()
> and i915_resume_switcheroo() in place was cleanest.
>
> No functional changes.
>
> Cc: Ville Syrjälä
> Cc: Chris Wilson
> Signed-off-by: Jani Nikula
>
> ---
>
> It's also a bit fuzzy if this is a sensible split anyway. Could also
> name it intel_vga and move these from intel_display.c there?
>
> i915_vgacntrl_reg
> i915_disable_vga
> i915_redisable_vga
> i915_redisable_vga_power_on
Considering that's the only reason we register with vgaarb it probably
makes sense to move them as well.
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 29
> drivers/gpu/drm/i915/display/intel_display.h | 1 -
> .../gpu/drm/i915/display/intel_vga_client.c | 140 ++
> .../gpu/drm/i915/display/intel_vga_client.h | 14 ++
> drivers/gpu/drm/i915/i915_drv.c | 94 +---
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 7 files changed, 166 insertions(+), 118 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_vga_client.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_vga_client.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e04463d85401..ca770463e01f 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -184,7 +184,8 @@ i915-y += \
> display/intel_psr.o \
> display/intel_quirks.o \
> display/intel_sprite.o \
> - display/intel_tc.o
> + display/intel_tc.o \
> + display/intel_vga_client.o
> i915-$(CONFIG_ACPI) += \
> display/intel_acpi.o \
> display/intel_opregion.o
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f1328c08f4ad..6278d62bc87d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17188,35 +17188,6 @@ void intel_modeset_driver_remove(struct
> drm_i915_private *i915)
> intel_fbc_cleanup_cfb(i915);
> }
>
> -/*
> - * set vga decode state - true == enable VGA decode
> - */
> -int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool
> state)
> -{
> - unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL :
> INTEL_GMCH_CTRL;
> - u16 gmch_ctrl;
> -
> - if (pci_read_config_word(dev_priv->bridge_dev, reg, _ctrl)) {
> - DRM_ERROR("failed to read control word\n");
> - return -EIO;
> - }
> -
> - if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
> - return 0;
> -
> - if (state)
> - gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
> - else
> - gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
> -
> - if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
> - DRM_ERROR("failed to write control word\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
>
> struct intel_display_error_state {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 4b9e18e5a263..a7b0d11a3316 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -579,7 +579,6 @@ void intel_display_print_error_state(struct
> drm_i915_error_state_buf *e,
> void intel_modeset_init_hw(struct drm_i915_private *i915);
> int intel_modeset_init(struct drm_i915_private *i915);
> void intel_modeset_driver_remove(struct drm_i915_private *i915);
> -int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool
> state);
> void intel_display_resume(struct drm_device *dev);
> void i915_redisable_vga(struct drm_i915_private *dev_priv);
> void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_vga_client.c
> b/drivers/gpu/drm/i915/display/intel_vga_client.c
> new file mode 100644
> index ..04ef1443f40e
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_vga_client.c
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include
> +
> +#include "i915_drv.h"
> +#include "intel_acpi.h"
> +#include "intel_vga_client.h"
> +
> +static
Re: [Intel-gfx] [PATCH v2 0/9] drm/print: add and use drm_debug_enabled()
On Tue, 01 Oct 2019, Eric Engestrom wrote:
> On Tuesday, 2019-10-01 14:03:55 +0300, Jani Nikula wrote:
>> On Thu, 26 Sep 2019, Eric Engestrom wrote:
>> > On Tuesday, 2019-09-24 15:58:56 +0300, Jani Nikula wrote:
>> >> Hi all, v2 of [1], a little refactoring around drm_debug access to
>> >> abstract it better. There shouldn't be any functional changes.
>> >>
>> >> I'd appreciate acks for merging the lot via drm-misc. If there are any
>> >> objections to that, we'll need to postpone the last patch until
>> >> everything has been merged and converted in drm-next.
>> >>
>> >> BR,
>> >> Jani.
>> >>
>> >> Cc: Eric Engestrom
>> >> Cc: Alex Deucher
>> >> Cc: Christian König
>> >> Cc: David (ChunMing) Zhou
>> >> Cc: amd-...@lists.freedesktop.org
>> >> Cc: Ben Skeggs
>> >> Cc: nouv...@lists.freedesktop.org
>> >> Cc: Rob Clark
>> >> Cc: Sean Paul
>> >> Cc: linux-arm-...@vger.kernel.org
>> >> Cc: freedr...@lists.freedesktop.org
>> >> Cc: Francisco Jerez
>> >> Cc: Lucas Stach
>> >> Cc: Russell King
>> >> Cc: Christian Gmeiner
>> >> Cc: etna...@lists.freedesktop.org
>> >>
>> >>
>> >> [1] cover.1568375189.git.jani.nikula@intel.com">http://mid.mail-archive.com/cover.1568375189.git.jani.nikula@intel.com
>> >>
>> >> Jani Nikula (9):
>> >> drm/print: move drm_debug variable to drm_print.[ch]
>> >> drm/print: add drm_debug_enabled()
>> >> drm/i915: use drm_debug_enabled() to check for debug categories
>> >> drm/print: rename drm_debug to __drm_debug to discourage use
>> >
>> > The above four patches are:
>> > Reviewed-by: Eric Engestrom
>> >
>> > Did you check to make sure the `unlikely()` is propagated correctly
>> > outside the `drm_debug_enabled()` call?
>>
>> I did now.
>>
>> Having drm_debug_enabled() as a macro vs. as an inline function does not
>> seem to make a difference, so I think the inline is clearly preferrable.
>
> Agreed :)
>
>>
>> However, for example
>>
>> unlikely(foo && drm_debug & DRM_UT_DP)
>>
>> does produce code different from
>>
>> (foo && drm_debug_enabled(DRM_UT_DP))
>>
>> indicating that the unlikely() within drm_debug_enabled() does not
>> propagate to the whole condition. It's possible to retain the same
>> assembly output with
>>
>> (unlikely(foo) && drm_debug_enabled(DRM_UT_DP))
>>
>> but it's unclear to me whether this is really worth it, either
>> readability or performance wise.
>>
>> Thoughts?
>
> That kind of code only happens 2 times, both in
> drivers/gpu/drm/drm_dp_mst_topology.c (in patch 2/9), right?
>
> I think your suggestion is the right thing to do here:
>
> - if (unlikely(ret && drm_debug & DRM_UT_DP)) {
> + if (unlikely(ret) && drm_debug_enabled(DRM_UT_DP)) {
>
> It doesn't really cost much in readability (especially compared to what
> it was before), and whether it's important performance wise I couldn't
> tell, but I think it's best to keep the code optimised as it was before
> unless there's a reason to drop it.
>
> Lyude might know more since she wrote 2f015ec6eab69301fdcf5, if you want
> to ping her?
Just ended up sending the updated version with what you suggest and I
agree with; pedantically the change should be a separate patch anyway.
Thanks for your inputs.
BR,
Jani.
>
>>
>> BR,
>> Jani.
>>
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
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[Intel-gfx] [PATCH v3] drm/print: add drm_debug_enabled()
Add helper to check if a drm debug category is enabled. Convert drm core
to use it. No functional changes.
v2: Move unlikely() to drm_debug_enabled() (Eric)
v3: Keep unlikely() when combined with other conditions (Eric)
Cc: Eric Engestrom
Acked-by: Alex Deucher
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_atomic_uapi.c | 2 +-
drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++---
drivers/gpu/drm/drm_edid.c| 2 +-
drivers/gpu/drm/drm_edid_load.c | 2 +-
drivers/gpu/drm/drm_mipi_dbi.c| 4 ++--
drivers/gpu/drm/drm_print.c | 4 ++--
drivers/gpu/drm/drm_vblank.c | 6 +++---
include/drm/drm_print.h | 5 +
8 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 7a26bfb5329c..0d466d3b0809 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1405,7 +1405,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
} else if (arg->flags & DRM_MODE_ATOMIC_NONBLOCK) {
ret = drm_atomic_nonblocking_commit(state);
} else {
- if (unlikely(drm_debug & DRM_UT_STATE))
+ if (drm_debug_enabled(DRM_UT_STATE))
drm_atomic_print_state(state);
ret = drm_atomic_commit(state);
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index e6801db54d0f..6b14b63b8d62 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -1179,7 +1179,7 @@ static int drm_dp_mst_wait_tx_reply(struct
drm_dp_mst_branch *mstb,
}
}
out:
- if (unlikely(ret == -EIO && drm_debug & DRM_UT_DP)) {
+ if (unlikely(ret == -EIO) && drm_debug_enabled(DRM_UT_DP)) {
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
drm_dp_mst_dump_sideband_msg_tx(, txmsg);
@@ -2322,7 +2322,7 @@ static int process_single_tx_qlock(struct
drm_dp_mst_topology_mgr *mgr,
idx += tosend + 1;
ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
- if (unlikely(ret && drm_debug & DRM_UT_DP)) {
+ if (unlikely(ret) && drm_debug_enabled(DRM_UT_DP)) {
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
drm_printf(, "sideband msg failed to send\n");
@@ -2389,7 +2389,7 @@ static void drm_dp_queue_down_tx(struct
drm_dp_mst_topology_mgr *mgr,
mutex_lock(>qlock);
list_add_tail(>next, >tx_msg_downq);
- if (unlikely(drm_debug & DRM_UT_DP)) {
+ if (drm_debug_enabled(DRM_UT_DP)) {
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
drm_dp_mst_dump_sideband_msg_tx(, txmsg);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 3c9703b08491..0552175313cb 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1651,7 +1651,7 @@ static void connector_bad_edid(struct drm_connector
*connector,
{
int i;
- if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
+ if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
return;
dev_warn(connector->dev->dev,
diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
index d38b3b255926..37d8ba3ddb46 100644
--- a/drivers/gpu/drm/drm_edid_load.c
+++ b/drivers/gpu/drm/drm_edid_load.c
@@ -175,7 +175,7 @@ static void *edid_load(struct drm_connector *connector,
const char *name,
u8 *edid;
int fwsize, builtin;
int i, valid_extensions = 0;
- bool print_bad_edid = !connector->bad_edid_counter || (drm_debug &
DRM_UT_KMS);
+ bool print_bad_edid = !connector->bad_edid_counter ||
drm_debug_enabled(DRM_UT_KMS);
builtin = match_string(generic_edid_name, GENERIC_EDIDS, name);
if (builtin >= 0) {
diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c
index f8154316a3b0..ccfb5b33c5e3 100644
--- a/drivers/gpu/drm/drm_mipi_dbi.c
+++ b/drivers/gpu/drm/drm_mipi_dbi.c
@@ -783,7 +783,7 @@ static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi,
int dc,
int i, ret;
u8 *dst;
- if (drm_debug & DRM_UT_DRIVER)
+ if (drm_debug_enabled(DRM_UT_DRIVER))
pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
__func__, dc, max_chunk);
@@ -907,7 +907,7 @@ static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int
dc,
max_chunk = dbi->tx_buf9_len;
dst16 = dbi->tx_buf9;
- if (drm_debug & DRM_UT_DRIVER)
+ if (drm_debug_enabled(DRM_UT_DRIVER))
pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
__func__, dc, max_chunk);
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index 1ade3a917c10..9a25d73c155c 100644
--- a/drivers/gpu/drm/drm_print.c
+++
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Rename "inject_load_failure" module parameter
Hi Chris,
On Tuesday, October 1, 2019 3:57:27 PM CEST Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2019-10-01 14:45:34)
> > Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
> > consequently") deliberately left the name of the module parameter
> > unchanged as that would require a corresponding change on IGT size.
> > Now as the IGT side change has been submitted, complete the switch to
> > the "probe" nomenclature.
> >
> > May affect custom user applications utilizing the old name.
>
> It's an unsafe modparam that only is compiled in for debugging, with no
> long term effect after modprobe. There are no user applications for
> this.
OK, I'll drop that sentence.
Thanks,
Janusz
> -Chris
>
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Rename "inject_load_failure" module parameter
Quoting Janusz Krzysztofik (2019-10-01 14:45:34)
> Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
> consequently") deliberately left the name of the module parameter
> unchanged as that would require a corresponding change on IGT size.
> Now as the IGT side change has been submitted, complete the switch to
> the "probe" nomenclature.
>
> May affect custom user applications utilizing the old name.
It's an unsafe modparam that only is compiled in for debugging, with no
long term effect after modprobe. There are no user applications for
this.
-Chris
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[Intel-gfx] [PATCH 2/2] drm/i915/tgl: Restrict availables engines to rcs0 by default
CI is still unstable whenever we enable more than one engine, and we have not yet found a better hack than restricting it to using just rcs0. However, to allow testing to continue on the other engines by developers, we allow the available set of engines to be overridden on the command line with just the default set limited to [rcs0]. Signed-off-by: Chris Wilson Cc: Andi Shyti Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 690da64ec256..9c8c7c8af394 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -406,6 +406,10 @@ static bool engine_available(struct drm_i915_private *i915, int id) if (!HAS_ENGINE(i915, id)) return false; + /* XXX reduced by default for CI stability XXX */ + if (IS_TIGERLAKE(i915) && i915_modparams.engines == -1u) + return id == RCS0; + if (!(i915_modparams.engines & param_bit[id])) return false; -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Allow the user to restrict the available set of engines via a module
parameter.
Signed-off-by: Chris Wilson
Cc: Stuart Summers
Cc: Andi Shyti
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Martin Peres
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 ---
drivers/gpu/drm/i915/i915_gem.c | 5
drivers/gpu/drm/i915/i915_params.c| 4 +++
drivers/gpu/drm/i915/i915_params.h| 1 +
4 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 80fd072ac719..690da64ec256 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -389,6 +389,29 @@ void intel_engines_cleanup(struct drm_i915_private *i915)
}
}
+static bool engine_available(struct drm_i915_private *i915, int id)
+{
+ /* uAPI -- modparam bits must be consistent between kernels */
+ static const unsigned int param_bit[] = {
+ [RCS0] = BIT(0),
+ [VCS0] = BIT(1),
+ [BCS0] = BIT(2),
+ [VECS0] = BIT(3),
+ [VCS1] = BIT(4),
+ [VCS2] = BIT(5),
+ [VCS3] = BIT(6),
+ [VECS1] = BIT(7),
+ };
+
+ if (!HAS_ENGINE(i915, id))
+ return false;
+
+ if (!(i915_modparams.engines & param_bit[id]))
+ return false;
+
+ return true;
+}
+
/**
* intel_engines_init_mmio() - allocate and prepare the Engine Command
Streamers
* @i915: the i915 device
@@ -397,7 +420,6 @@ void intel_engines_cleanup(struct drm_i915_private *i915)
*/
int intel_engines_init_mmio(struct drm_i915_private *i915)
{
- struct intel_device_info *device_info = mkwrite_device_info(i915);
const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
unsigned int mask = 0;
unsigned int i;
@@ -411,7 +433,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
- if (!HAS_ENGINE(i915, i))
+ if (!engine_available(i915, i))
continue;
err = intel_engine_setup(>gt, i);
@@ -421,14 +443,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
mask |= BIT(i);
}
- /*
-* Catch failures to update intel_engines table when the new engines
-* are added to the driver by a warning and disabling the forgotten
-* engines.
-*/
- if (WARN_ON(mask != engine_mask))
- device_info->engine_mask = mask;
-
+ mkwrite_device_info(i915)->engine_mask = mask;
RUNTIME_INFO(i915)->num_engines = hweight32(mask);
intel_gt_check_and_clear_faults(>gt);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d3fda4cae99..bb25731466a9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1308,6 +1308,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
{
int ret;
+ if (!RUNTIME_INFO(dev_priv)->num_engines) {
+ intel_gt_set_wedged_on_init(_priv->gt);
+ return 0;
+ }
+
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
mkwrite_device_info(dev_priv)->page_sizes =
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..27813bd79aa8 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -44,6 +44,10 @@ i915_param_named(modeset, int, 0400,
"Use kernel modesetting [KMS] (0=disable, "
"1=on, -1=force vga console preference [default])");
+i915_param_named(engines, uint, 0400,
+ "Only expose selected command streamers [GPU engines] (0=disable GPU, "
+ "-1/0x enable all [default]). Each bit corresponds to a
different phyiscal engine: 0=RCS0, 1=VCS0, 2=BCS0, 3=VECS0, 4=VCS1, 5=VCS2,
6=VCS3, 7=VECS1");
+
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f876db78a59a 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,6 +45,7 @@ struct drm_printer;
#define I915_PARAMS_FOR_EACH(param) \
param(char *, vbt_firmware, NULL) \
param(int, modeset, -1) \
+ param(unsigned int, engines, -1) \
param(int, lvds_channel_mode, 0) \
param(int, panel_use_ssc, -1) \
param(int, vbt_sdvo_panel_type, -1) \
--
2.23.0
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[Intel-gfx] [PATCH 2/2] drm/i915: Rename "inject_load_failure" module parameter
Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
consequently") deliberately left the name of the module parameter
unchanged as that would require a corresponding change on IGT size.
Now as the IGT side change has been submitted, complete the switch to
the "probe" nomenclature.
May affect custom user applications utilizing the old name.
Suggested-by: Joonas Lahtinen
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_params.c | 2 +-
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/i915_utils.c | 10 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..59a6586dae15 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -165,7 +165,7 @@ i915_param_named_unsafe(enable_dp_mst, bool, 0600,
"Enable multi-stream transport (MST) for new DisplayPort sinks.
(default: true)");
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
-i915_param_named_unsafe(inject_load_failure, uint, 0400,
+i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
#endif
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..8c887413fc70 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -62,7 +62,7 @@ struct drm_printer;
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO)) \
param(int, edp_vswing, 0) \
param(int, reset, 2) \
- param(unsigned int, inject_load_failure, 0) \
+ param(unsigned int, inject_probe_failure, 0) \
param(int, fastboot, -1) \
param(int, enable_dpcd_backlight, 0) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE) \
diff --git a/drivers/gpu/drm/i915/i915_utils.c
b/drivers/gpu/drm/i915/i915_utils.c
index e51bdb05da14..64affb87c284 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -57,22 +57,22 @@ static unsigned int i915_probe_fail_count;
int __i915_inject_probe_error(struct drm_i915_private *i915, int err,
const char *func, int line)
{
- if (i915_probe_fail_count >= i915_modparams.inject_load_failure)
+ if (i915_probe_fail_count >= i915_modparams.inject_probe_failure)
return 0;
- if (++i915_probe_fail_count < i915_modparams.inject_load_failure)
+ if (++i915_probe_fail_count < i915_modparams.inject_probe_failure)
return 0;
__i915_printk(i915, KERN_INFO,
"Injecting failure %d at checkpoint %u [%s:%d]\n",
- err, i915_modparams.inject_load_failure, func, line);
- i915_modparams.inject_load_failure = 0;
+ err, i915_modparams.inject_probe_failure, func, line);
+ i915_modparams.inject_probe_failure = 0;
return err;
}
bool i915_error_injected(void)
{
- return i915_probe_fail_count && !i915_modparams.inject_load_failure;
+ return i915_probe_fail_count && !i915_modparams.inject_probe_failure;
}
#endif
--
2.21.0
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[Intel-gfx] [PATCH 0/2] Conclude load -> probe naming convention switch
Test-with: <20191001132728.14602-1-janusz.krzyszto...@linux.intel.com> The purpose is: * to fix incompatible names of new functions introduced meanwhile, * to complete postponed rename of module parameter. Will be tested with just submitted IGT counterpart using a trybot submission because I forgot to add a cover letter required for successful joint testing when I was submitting to igt-dev list, sorry. Thanks, Janusz Janusz Krzysztofik (2): drm/i915: Fix i915_inject_load_error() name to read *_probe_* drm/i915: Rename "inject_load_failure" module parameter .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 ++-- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 ++- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_params.c| 2 +- drivers/gpu/drm/i915/i915_params.h| 2 +- drivers/gpu/drm/i915/i915_utils.c | 14 ++--- drivers/gpu/drm/i915/i915_utils.h | 12 +-- 9 files changed, 34 insertions(+), 32 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Fix i915_inject_load_error() name to read *_probe_*
Commit 50d84418f586 ("drm/i915: Add i915 to i915_inject_probe_failure")
introduced new functions unfortunately named incompatibly with rules
established by commit f2db53f14d3d ("drm/i915: Replace "_load" with
"_probe" consequently"). Fix it for consistency.
Suggested-by: Michał Wajdeczko
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 ++-
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/i915_utils.c | 4 ++--
drivers/gpu/drm/i915/i915_utils.h | 12 +--
7 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..67e46c2af6df 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1119,7 +1119,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
enum intel_engine_id id;
int err;
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d4625c97b4f9..8295ff971bcc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -35,7 +35,7 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
void *vaddr;
int err;
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
@@ -134,7 +134,7 @@ int intel_huc_auth(struct intel_huc *huc)
if (!intel_uc_fw_is_loaded(>fw))
return -ENOEXEC;
- ret = i915_inject_load_error(gt->i915, -ENXIO);
+ ret = i915_inject_probe_error(gt->i915, -ENXIO);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 71ee7ab035cc..fb0d7bb712ab 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -20,7 +20,7 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
int ret;
u32 guc_status;
- ret = i915_inject_load_error(gt->i915, -ENXIO);
+ ret = i915_inject_probe_error(gt->i915, -ENXIO);
if (ret)
return ret;
@@ -197,7 +197,7 @@ static int guc_enable_communication(struct intel_guc *guc)
GEM_BUG_ON(guc_communication_enabled(guc));
- ret = i915_inject_load_error(i915, -ENXIO);
+ ret = i915_inject_probe_error(i915, -ENXIO);
if (ret)
return ret;
@@ -368,7 +368,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index bd22bf11adad..f6830ec79a66 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -218,29 +218,31 @@ static void __force_fw_fetch_failures(struct intel_uc_fw
*uc_fw,
{
bool user = e == -EINVAL;
- if (i915_inject_load_error(i915, e)) {
+ if (i915_inject_probe_error(i915, e)) {
/* non-existing blob */
uc_fw->path = "";
uc_fw->user_overridden = user;
- } else if (i915_inject_load_error(i915, e)) {
+ } else if (i915_inject_probe_error(i915, e)) {
/* require next major version */
uc_fw->major_ver_wanted += 1;
uc_fw->minor_ver_wanted = 0;
uc_fw->user_overridden = user;
- } else if (i915_inject_load_error(i915, e)) {
+ } else if (i915_inject_probe_error(i915, e)) {
/* require next minor version */
uc_fw->minor_ver_wanted += 1;
uc_fw->user_overridden = user;
- } else if (uc_fw->major_ver_wanted && i915_inject_load_error(i915, e)) {
+ } else if (uc_fw->major_ver_wanted &&
+ i915_inject_probe_error(i915, e)) {
/* require prev major version */
uc_fw->major_ver_wanted -= 1;
uc_fw->minor_ver_wanted = 0;
uc_fw->user_overridden = user;
- } else if (uc_fw->minor_ver_wanted && i915_inject_load_error(i915, e)) {
+ } else if (uc_fw->minor_ver_wanted &&
+
[Intel-gfx] [PATCH] drm/i915/display: split out intel_vga_client.[ch]
Split out code related to vga client and vga switcheroo
register/unregister and state handling from i915_drv.c and
intel_display.c.
It's a bit difficult to draw the line how much to move to the new file
from i915_drv.c, but it seemed to me keeping i915_suspend_switcheroo()
and i915_resume_switcheroo() in place was cleanest.
No functional changes.
Cc: Ville Syrjälä
Cc: Chris Wilson
Signed-off-by: Jani Nikula
---
It's also a bit fuzzy if this is a sensible split anyway. Could also
name it intel_vga and move these from intel_display.c there?
i915_vgacntrl_reg
i915_disable_vga
i915_redisable_vga
i915_redisable_vga_power_on
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 29
drivers/gpu/drm/i915/display/intel_display.h | 1 -
.../gpu/drm/i915/display/intel_vga_client.c | 140 ++
.../gpu/drm/i915/display/intel_vga_client.h | 14 ++
drivers/gpu/drm/i915/i915_drv.c | 94 +---
drivers/gpu/drm/i915/i915_drv.h | 3 +
7 files changed, 166 insertions(+), 118 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_vga_client.c
create mode 100644 drivers/gpu/drm/i915/display/intel_vga_client.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e04463d85401..ca770463e01f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -184,7 +184,8 @@ i915-y += \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
- display/intel_tc.o
+ display/intel_tc.o \
+ display/intel_vga_client.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
display/intel_opregion.o
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f1328c08f4ad..6278d62bc87d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17188,35 +17188,6 @@ void intel_modeset_driver_remove(struct
drm_i915_private *i915)
intel_fbc_cleanup_cfb(i915);
}
-/*
- * set vga decode state - true == enable VGA decode
- */
-int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
-{
- unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL :
INTEL_GMCH_CTRL;
- u16 gmch_ctrl;
-
- if (pci_read_config_word(dev_priv->bridge_dev, reg, _ctrl)) {
- DRM_ERROR("failed to read control word\n");
- return -EIO;
- }
-
- if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
- return 0;
-
- if (state)
- gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
- else
- gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
-
- if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
- DRM_ERROR("failed to write control word\n");
- return -EIO;
- }
-
- return 0;
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
struct intel_display_error_state {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 4b9e18e5a263..a7b0d11a3316 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -579,7 +579,6 @@ void intel_display_print_error_state(struct
drm_i915_error_state_buf *e,
void intel_modeset_init_hw(struct drm_i915_private *i915);
int intel_modeset_init(struct drm_i915_private *i915);
void intel_modeset_driver_remove(struct drm_i915_private *i915);
-int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state);
void intel_display_resume(struct drm_device *dev);
void i915_redisable_vga(struct drm_i915_private *dev_priv);
void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_vga_client.c
b/drivers/gpu/drm/i915/display/intel_vga_client.c
new file mode 100644
index ..04ef1443f40e
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vga_client.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "i915_drv.h"
+#include "intel_acpi.h"
+#include "intel_vga_client.h"
+
+static int
+intel_vga_client_set_state(struct drm_i915_private *i915, bool enable_decode)
+{
+ unsigned int reg = INTEL_GEN(i915) >= 6 ? SNB_GMCH_CTRL :
INTEL_GMCH_CTRL;
+ u16 gmch_ctrl;
+
+ if (pci_read_config_word(i915->bridge_dev, reg, _ctrl)) {
+ DRM_ERROR("failed to read control word\n");
+ return -EIO;
+ }
+
+ if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
+ return 0;
+
+ if (enable_decode)
+ gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
+ else
+ gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
+
+ if (pci_write_config_word(i915->bridge_dev, reg,
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/userptr: Never allow userptr into the mappable GGTT (rev3)
== Series Details == Series: drm/i915/userptr: Never allow userptr into the mappable GGTT (rev3) URL : https://patchwork.freedesktop.org/series/67349/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6980_full -> Patchwork_14601_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14601_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14601_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14601_full: ### IGT changes ### Possible regressions * igt@gem_tiled_blits@normal: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-kbl7/igt@gem_tiled_bl...@normal.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-kbl4/igt@gem_tiled_bl...@normal.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: [PASS][3] -> [FAIL][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-kbl3/igt@gem_userptr_bl...@dmabuf-sync.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-kbl1/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-hsw7/igt@gem_userptr_bl...@dmabuf-unsync.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-hsw8/igt@gem_userptr_bl...@dmabuf-unsync.html - shard-snb: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-snb1/igt@gem_userptr_bl...@dmabuf-unsync.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-snb1/igt@gem_userptr_bl...@dmabuf-unsync.html * igt@gem_userptr_blits@readonly-mmap-unsync: - shard-apl: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-apl8/igt@gem_userptr_bl...@readonly-mmap-unsync.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-apl7/igt@gem_userptr_bl...@readonly-mmap-unsync.html - shard-glk: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-glk4/igt@gem_userptr_bl...@readonly-mmap-unsync.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-glk6/igt@gem_userptr_bl...@readonly-mmap-unsync.html Warnings * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [DMESG-WARN][13] ([fdo#111870]) -> [FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html - shard-iclb: [DMESG-WARN][15] ([fdo#111870]) -> [FAIL][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-iclb1/igt@gem_userptr_bl...@dmabuf-sync.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-iclb2/igt@gem_userptr_bl...@dmabuf-sync.html - shard-hsw: [DMESG-WARN][17] ([fdo#111870]) -> [FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-hsw1/igt@gem_userptr_bl...@dmabuf-sync.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-hsw4/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-skl: [DMESG-WARN][19] ([fdo#111870]) -> [FAIL][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-skl2/igt@gem_userptr_bl...@dmabuf-unsync.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-skl7/igt@gem_userptr_bl...@dmabuf-unsync.html - shard-kbl: [DMESG-WARN][21] ([fdo#111870]) -> [FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-kbl3/igt@gem_userptr_bl...@dmabuf-unsync.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-kbl1/igt@gem_userptr_bl...@dmabuf-unsync.html Known issues Here are the changes found in Patchwork_14601_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-contexts-immediate: - shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#105957]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-hsw8/igt@gem_...@in-flight-contexts-immediate.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14601/shard-hsw7/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb:
