[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Select DPLL's via mask (rev3)
== Series Details ==
Series: drm/i915: Select DPLL's via mask (rev3)
URL : https://patchwork.freedesktop.org/series/67740/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035_full -> Patchwork_14709_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14709_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-tglb1/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- {shard-tglb}: NOTRUN -> [SKIP][2] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-tglb7/igt@kms_rotation_...@primary-yf-tiled-reflect-x-0.html
Known issues
Here are the changes found in Patchwork_14709_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb1/igt@gem_exec_balan...@smoke.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-iclb8/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl3/igt@gem_exec_fl...@basic-wb-pro-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-apl4/igt@gem_exec_fl...@basic-wb-pro-default.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +6 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb5/igt@gem_exec_sched...@preemptive-hang-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb1/igt@gem_userptr_bl...@dmabuf-unsync.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-snb1/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271]) +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb4/igt@kms_big...@x-tiled-32bpp-rotate-180.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-snb4/igt@kms_big...@x-tiled-32bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +4
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-apl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +3 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#99912])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl3/igt@kms_setm...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-apl2/igt@kms_setm...@basic.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +22 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@prime_b...@hang-bsd2.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/shard-iclb5/igt@prime_b...@hang-bsd2.html
Possible fixes
*
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Give engine->kernel_context distinct timeline lock classes
== Series Details ==
Series: drm/i915/gt: Give engine->kernel_context distinct timeline lock classes
URL : https://patchwork.freedesktop.org/series/67748/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7035_full -> Patchwork_14708_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14708_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14708_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14708_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@in-flight-contexts-1us:
- shard-hsw: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-hsw5/igt@gem_...@in-flight-contexts-1us.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-hsw8/igt@gem_...@in-flight-contexts-1us.html
* igt@gem_exec_whisper@normal:
- shard-skl: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl7/igt@gem_exec_whis...@normal.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-skl7/igt@gem_exec_whis...@normal.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip_tiling@flip-changes-tiling-yf:
- {shard-tglb}: NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-tglb6/igt@kms_flip_til...@flip-changes-tiling-yf.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- {shard-tglb}: [INCOMPLETE][6] ([fdo#111832]) -> [INCOMPLETE][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-tglb2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-tglb2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
Known issues
Here are the changes found in Patchwork_14708_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#104108])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl7/igt@gem_ctx_isolat...@rcs0-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-skl9/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vecs0-s3:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) +4
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl4/igt@gem_ctx_isolat...@vecs0-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-apl4/igt@gem_ctx_isolat...@vecs0-s3.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#110854])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb1/igt@gem_exec_balan...@smoke.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-iclb6/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) +5 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb3/igt@gem_exec_sched...@wide-bsd.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-iclb1/igt@gem_exec_sched...@wide-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-snb7/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
* igt@i915_suspend@fence-restore-untiled:
- shard-snb: [PASS][18] -> [INCOMPLETE][19] ([fdo#105411])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb6/igt@i915_susp...@fence-restore-untiled.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-snb1/igt@i915_susp...@fence-restore-untiled.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][20] -> [FAIL][21] ([fdo#102670])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-suspend-interruptible:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to dev_priv
== Series Details ==
Series: series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67743/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7035_full -> Patchwork_14706_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14706_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14706_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14706_full:
### IGT changes ###
Possible regressions
* igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding:
- shard-apl: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl7/igt@kms_cursor_...@pipe-b-cursor-256x85-sliding.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-256x85-sliding.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_pwrite@big-cpu-forwards:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-tglb4/igt@gem_pwr...@big-cpu-forwards.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- {shard-tglb}: NOTRUN -> [SKIP][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-tglb6/igt@kms_rotation_...@primary-yf-tiled-reflect-x-0.html
Known issues
Here are the changes found in Patchwork_14706_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb1/igt@gem_exec_balan...@smoke.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-iclb7/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +8 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb3/igt@gem_exec_sched...@wide-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) +2
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb1/igt@gem_userptr_bl...@sync-unmap-cycles.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-snb1/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +5
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl1/igt@i915_susp...@sysfs-reader.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-apl7/igt@i915_susp...@sysfs-reader.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#105767])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +4 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +3 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#99912])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl3/igt@kms_setm...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-apl8/igt@kms_setm...@basic.html
* igt@kms_vblank@pipe-c-wait-forked-busy-hang:
- shard-apl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103927]) +1
similar
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Hold request reference over waits
== Series Details == Series: drm/i915/selftests: Hold request reference over waits URL : https://patchwork.freedesktop.org/series/67757/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7037 -> Patchwork_14714 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14714 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14714, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14714: ### IGT changes ### Possible regressions * igt@i915_selftest@live_workarounds: - fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-bsw-n3050/igt@i915_selftest@live_workarounds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-bsw-n3050/igt@i915_selftest@live_workarounds.html - fi-cfl-guc: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-cfl-guc/igt@i915_selftest@live_workarounds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-cfl-guc/igt@i915_selftest@live_workarounds.html - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-glk-dsi/igt@i915_selftest@live_workarounds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-glk-dsi/igt@i915_selftest@live_workarounds.html - fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html - fi-kbl-7500u: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-kbl-7500u/igt@i915_selftest@live_workarounds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-kbl-7500u/igt@i915_selftest@live_workarounds.html - fi-cfl-8109u: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-cfl-8109u/igt@i915_selftest@live_workarounds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-cfl-8109u/igt@i915_selftest@live_workarounds.html - fi-kbl-guc: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-kbl-guc/igt@i915_selftest@live_workarounds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-kbl-guc/igt@i915_selftest@live_workarounds.html - fi-skl-6600u: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-skl-6600u/igt@i915_selftest@live_workarounds.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-skl-6600u/igt@i915_selftest@live_workarounds.html - fi-bdw-5557u: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-bdw-5557u/igt@i915_selftest@live_workarounds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-bdw-5557u/igt@i915_selftest@live_workarounds.html - fi-whl-u: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-whl-u/igt@i915_selftest@live_workarounds.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-whl-u/igt@i915_selftest@live_workarounds.html - fi-apl-guc: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-apl-guc/igt@i915_selftest@live_workarounds.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-apl-guc/igt@i915_selftest@live_workarounds.html - fi-skl-6700k2: NOTRUN -> [DMESG-WARN][23] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-skl-6700k2/igt@i915_selftest@live_workarounds.html - fi-skl-iommu: [PASS][24] -> [DMESG-WARN][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-skl-iommu/igt@i915_selftest@live_workarounds.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-skl-iommu/igt@i915_selftest@live_workarounds.html - fi-skl-lmem:[PASS][26] -> [DMESG-WARN][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-skl-lmem/igt@i915_selftest@live_workarounds.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14714/fi-skl-lmem/igt@i915_selftest@live_workarounds.html - fi-kbl-x1275: [PASS][28] -> [DMESG-WARN][29] [28]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on
SNB-BDW sprites
URL : https://patchwork.freedesktop.org/series/67741/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7035_full -> Patchwork_14705_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14705_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14705_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14705_full:
### IGT changes ###
Possible regressions
* igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
- shard-iclb: [PASS][1] -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb6/igt@kms_plane_scal...@pipe-a-scaler-with-clipping-clamping.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb6/igt@kms_plane_scal...@pipe-a-scaler-with-clipping-clamping.html
* igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping:
- shard-iclb: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb7/igt@kms_plane_scal...@pipe-c-scaler-with-clipping-clamping.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- {shard-tglb}: [PASS][4] -> [INCOMPLETE][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-tglb6/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb7/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html
* igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
- {shard-tglb}: NOTRUN -> [FAIL][6] +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb7/igt@kms_plane_scal...@pipe-b-scaler-with-clipping-clamping.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- {shard-tglb}: NOTRUN -> [SKIP][7] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb3/igt@kms_rotation_...@primary-yf-tiled-reflect-x-0.html
Known issues
Here are the changes found in Patchwork_14705_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +4
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110854])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb1/igt@gem_exec_balan...@smoke.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb6/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-apl: [PASS][12] -> [INCOMPLETE][13] ([fdo#103927])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl3/igt@gem_exec_fl...@basic-wb-pro-default.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl4/igt@gem_exec_fl...@basic-wb-pro-default.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) +4 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb6/igt@gem_exec_sched...@in-order-bsd.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb4/igt@gem_exec_sched...@in-order-bsd.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb1/igt@gem_userptr_bl...@sync-unmap-cycles.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([fdo#103558] /
[fdo#105602]) +30 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl6/igt@kms_cursor_...@pipe-a-cursor-128x128-sliding.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-128x128-sliding.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][20] ->
[Intel-gfx] ✗ Fi.CI.BUILD: failure for linux-next: build failure after merge of the drm-misc tree
== Series Details == Series: linux-next: build failure after merge of the drm-misc tree URL : https://patchwork.freedesktop.org/series/67759/ State : failure == Summary == Applying: linux-next: build failure after merge of the drm-misc tree error: sha1 information is lacking or useless (drivers/gpu/drm/amd/amdkfd/kfd_priv.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 linux-next: build failure after merge of the drm-misc tree When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] linux-next: build failure after merge of the drm-misc tree
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.c:25:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error: drm/drmP.h:
No such file or directory
40 | #include
| ^~~~
In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.c:38:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error: drm/drmP.h:
No such file or directory
40 | #include
| ^~~~
In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.c:26:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error: drm/drmP.h:
No such file or directory
40 | #include
| ^~~~
In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:34:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error: drm/drmP.h:
No such file or directory
40 | #include
| ^~~~
Caused by commit
4e98f871bcff ("drm: delete drmP.h + drm_os_linux.h")
interacting with commit
6b855f7b83d2 ("drm/amdkfd: Check against device cgroup")
from the amdgpu tree.
I added the following merge fix patch for today:
From: Stephen Rothwell
Date: Wed, 9 Oct 2019 11:24:38 +1100
Subject: [PATCH] drm/amdkfd: update for drmP.h removal
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index b8b4485c8f74..41bc0428bfc0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -37,7 +37,9 @@
#include
#include
#include
-#include
+#include
+#include
+#include
#include
#include "amd_shared.h"
@@ -49,8 +51,6 @@
/* GPU ID hash width in bits */
#define KFD_GPU_ID_HASH_WIDTH 16
-struct drm_device;
-
/* Use upper bits of mmap offset to store KFD driver specific information.
* BITS[63:62] - Encode MMAP type
* BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
--
2.23.0
--
Cheers,
Stephen Rothwell
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Catch GTT fault errors for gen11+ planes (rev2)
== Series Details ==
Series: drm/i915: Catch GTT fault errors for gen11+ planes (rev2)
URL : https://patchwork.freedesktop.org/series/67752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7037 -> Patchwork_14713
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14713/index.html
Known issues
Here are the changes found in Patchwork_14713 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-icl-u3/igt@gem_ba...@create-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14713/fi-icl-u3/igt@gem_ba...@create-close.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14713/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111593]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14713/fi-tgl-u/igt@gem_exec_gttf...@basic.html
* igt@gem_tiled_fence_blits@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-icl-u3/igt@gem_tiled_fence_bl...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14713/fi-icl-u3/igt@gem_tiled_fence_bl...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Participating hosts (50 -> 45)
--
Additional (1): fi-icl-dsi
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7037 -> Patchwork_14713
CI-20190529: 20190529
CI_DRM_7037: 4ff590d66f456266150c2c42c194f62338569140 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14713: 5d5d181a8ee8f002ad223781446b91e8c5f727f6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5d5d181a8ee8 drm/i915: Catch GTT fault errors for gen11+ planes
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14713/index.html
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[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/i915_gem_gtt.c
between commit:
1e0a96e50882 ("drm/i915: export color_differs")
from the drm tree and commit:
71724f708997 ("drm/mm: Use helpers for drm_mm_node booleans")
from the drm-misc tree.
I fixed it up (I used the former change) and can carry the fix as
necessary. This is now fixed as far as linux-next is concerned, but any
non trivial conflicts should be mentioned to your upstream maintainer
when your tree is submitted for merging. You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.
--
Cheers,
Stephen Rothwell
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[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/i915_vma.c
between commits:
1e0a96e50882 ("drm/i915: export color_differs")
33dd88992313 ("drm/i915: cleanup cache-coloring")
b290a78b5c3d ("drm/i915: Use helpers for drm_mm_node booleans")
5e053450c1c3 ("drm/i915: Only track bound elements of the GTT")
2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm->mutex")
from the drm tree and commit:
71724f708997 ("drm/mm: Use helpers for drm_mm_node booleans")
from the drm-misc tree.
I fixed it up (the subset of 71724f708997 affecting this file is in
b290a78b5c3d) and can carry the fix as necessary. This is now fixed as
far as linux-next is concerned, but any non trivial conflicts should be
mentioned to your upstream maintainer when your tree is submitted for
merging. You may also want to consider cooperating with the maintainer
of the conflicting tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
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[Intel-gfx] [PATCH] drm/i915/selftests: Hold request reference over waits
Take a reference on the request before submitting it to the HW and then
waiting on it for selftest_workarounds. Once submitted, the request may
be freed by a background worker, unless we take an extra reference for
ourselves.
References: https://bugs.freedesktop.org/show_bug.cgi?id=111926
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/selftest_workarounds.c| 74 +--
1 file changed, 34 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 74952bda9256..8ec26d5f5026 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -33,6 +33,30 @@ struct wa_lists {
} engine[I915_NUM_ENGINES];
};
+static int request_add_sync(struct i915_request *rq, int err)
+{
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+ int err = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (spin && !igt_wait_for_spinner(spin, rq))
+ err = -ETIMEDOUT;
+ i915_request_put(rq);
+
+ return err;
+}
+
static void
reference_lists_init(struct drm_i915_private *i915, struct wa_lists *lists)
{
@@ -243,7 +267,6 @@ switch_to_scratch_context(struct intel_engine_cs *engine,
struct i915_gem_context *ctx;
struct intel_context *ce;
struct i915_request *rq;
- intel_wakeref_t wakeref;
int err = 0;
ctx = kernel_context(engine->i915);
@@ -255,9 +278,7 @@ switch_to_scratch_context(struct intel_engine_cs *engine,
ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
GEM_BUG_ON(IS_ERR(ce));
- rq = ERR_PTR(-ENODEV);
- with_intel_runtime_pm(engine->uncore->rpm, wakeref)
- rq = igt_spinner_create_request(spin, ce, MI_NOOP);
+ rq = igt_spinner_create_request(spin, ce, MI_NOOP);
intel_context_put(ce);
@@ -267,13 +288,7 @@ switch_to_scratch_context(struct intel_engine_cs *engine,
goto err;
}
- i915_request_add(rq);
-
- if (spin && !igt_wait_for_spinner(spin, rq)) {
- pr_err("Spinner failed to start\n");
- err = -ETIMEDOUT;
- }
-
+ err = request_add_spin(rq, spin);
err:
if (err && spin)
igt_spinner_end(spin);
@@ -586,15 +601,11 @@ static int check_dirty_whitelist(struct i915_gem_context
*ctx,
goto err_request;
err_request:
- i915_request_add(rq);
- if (err)
- goto out_batch;
-
- if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ err = request_add_sync(rq, err);
+ if (err) {
pr_err("%s: Futzing %x timedout; cancelling test\n",
engine->name, reg);
intel_gt_set_wedged(>i915->gt);
- err = -EIO;
goto out_batch;
}
@@ -697,7 +708,6 @@ static int live_dirty_whitelist(void *arg)
struct intel_engine_cs *engine;
struct i915_gem_context *ctx;
enum intel_engine_id id;
- intel_wakeref_t wakeref;
struct drm_file *file;
int err = 0;
@@ -706,13 +716,9 @@ static int live_dirty_whitelist(void *arg)
if (INTEL_GEN(i915) < 7) /* minimum requirement for LRI, SRM, LRM */
return 0;
- wakeref = intel_runtime_pm_get(>runtime_pm);
-
file = mock_file(i915);
- if (IS_ERR(file)) {
- err = PTR_ERR(file);
- goto out_rpm;
- }
+ if (IS_ERR(file))
+ return PTR_ERR(file);
ctx = live_context(i915, file);
if (IS_ERR(ctx)) {
@@ -731,8 +737,6 @@ static int live_dirty_whitelist(void *arg)
out_file:
mock_file_free(i915, file);
-out_rpm:
- intel_runtime_pm_put(>runtime_pm, wakeref);
return err;
}
@@ -807,12 +811,7 @@ static int read_whitelisted_registers(struct
i915_gem_context *ctx,
intel_ring_advance(rq, cs);
err_req:
- i915_request_add(rq);
-
- if (i915_request_wait(rq, 0, HZ / 5) < 0)
- err = -EIO;
-
- return err;
+ return request_add_sync(rq, err);
}
static int scrub_whitelisted_registers(struct i915_gem_context *ctx,
@@ -872,9 +871,7 @@ static int scrub_whitelisted_registers(struct
i915_gem_context *ctx,
err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
err_request:
- i915_request_add(rq);
- if (i915_request_wait(rq, 0, HZ / 5) < 0)
- err = -EIO;
+ err = request_add_sync(rq, err);
err_unpin:
i915_gem_object_unpin_map(batch->obj);
@@ -1229,12 +1226,10 @@
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Enable DDI/Port G
== Series Details ==
Series: drm/i915/tgl: Enable DDI/Port G
URL : https://patchwork.freedesktop.org/series/67755/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7037 -> Patchwork_14712
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14712/index.html
Known issues
Here are the changes found in Patchwork_14712 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14712/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14712/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109483] / [fdo#109635 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14712/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111593]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14712/fi-tgl-u/igt@gem_exec_gttf...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Participating hosts (50 -> 43)
--
Additional (1): fi-icl-dsi
Missing(8): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u3
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7037 -> Patchwork_14712
CI-20190529: 20190529
CI_DRM_7037: 4ff590d66f456266150c2c42c194f62338569140 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14712: 039cb0f50dc58633770a60d6f7e57d49335bf465 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
039cb0f50dc5 drm/i915/tgl: Enable DDI/Port G
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14712/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for intel_memory_region bits
== Series Details ==
Series: intel_memory_region bits
URL : https://patchwork.freedesktop.org/series/67738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035_full -> Patchwork_14704_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14704_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- {shard-tglb}: NOTRUN -> [SKIP][1] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-tglb5/igt@kms_rotation_...@primary-yf-tiled-reflect-x-270.html
* {igt@perf_pmu@semaphore-busy-bcs0}:
- shard-skl: [PASS][2] -> [DMESG-WARN][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl2/igt@perf_...@semaphore-busy-bcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-skl3/igt@perf_...@semaphore-busy-bcs0.html
New tests
-
New tests have been introduced between CI_DRM_7035_full and
Patchwork_14704_full:
### New IGT tests (1) ###
* igt@i915_selftest@mock_memory_region:
- Statuses : 7 pass(s)
- Exec time: [1.20, 15.68] s
Known issues
Here are the changes found in Patchwork_14704_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +6 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb5/igt@gem_exec_sched...@preemptive-hang-bsd.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][6] -> [DMESG-WARN][7] ([fdo#111870])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +9
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl6/igt@gem_workarou...@suspend-resume-context.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-apl2/igt@gem_workarou...@suspend-resume-context.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([fdo#104108])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl6/igt@kms_fbcon_...@psr-suspend.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-skl5/igt@kms_fbcon_...@psr-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][12] -> [INCOMPLETE][13] ([fdo#103540])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-hsw7/igt@kms_f...@flip-vs-suspend-interruptible.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-hsw1/igt@kms_f...@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103167]) +5 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109441]) +2 similar
issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][18] -> [FAIL][19] ([fdo#99912])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl3/igt@kms_setm...@basic.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-apl7/igt@kms_setm...@basic.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109276]) +19 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@prime_b...@hang-bsd2.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/shard-iclb3/igt@prime_b...@hang-bsd2.html
Possible fixes
* igt@gem_ctx_shared@exec-single-timeline-bsd:
[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/i915_gem.c
between commits:
b290a78b5c3d ("drm/i915: Use helpers for drm_mm_node booleans")
2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm->mutex")
from the drm tree and commit:
71724f708997 ("drm/mm: Use helpers for drm_mm_node booleans")
from the drm-misc tree.
I fixed it up (b290a78b5c3d and 71724f708997 do basically identical
things to this file ...) and can carry the fix as necessary. This is
now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your
tree is submitted for merging. You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.
--
Cheers,
Stephen Rothwell
pgpf9BkAypVS7.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/i915_drv.c
between commit:
2d6f6f359fd8 ("drm/i915: add i915_driver_modeset_remove()")
from the drm tree and commit:
f2521f7731ed ("drm/i915: switch to
drm_fb_helper_remove_conflicting_pci_framebuffers")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/i915/i915_drv.c
index 15abad5c2d62,1c4ff8b5b0a2..
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -350,44 -422,6 +350,19 @@@ out
return ret;
}
- static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
- {
- struct apertures_struct *ap;
- struct pci_dev *pdev = dev_priv->drm.pdev;
- struct i915_ggtt *ggtt = _priv->ggtt;
- bool primary;
- int ret;
-
- ap = alloc_apertures(1);
- if (!ap)
- return -ENOMEM;
-
- ap->ranges[0].base = ggtt->gmadr.start;
- ap->ranges[0].size = ggtt->mappable_end;
-
- primary =
- pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
-
- ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb",
primary);
-
- kfree(ap);
-
- return ret;
- }
-
+static void i915_driver_modeset_remove(struct drm_i915_private *i915)
+{
+ intel_modeset_driver_remove(i915);
+
+ intel_bios_driver_remove(i915);
+
+ i915_switcheroo_unregister(i915);
+
+ intel_vga_unregister(i915);
+
+ intel_csr_ucode_fini(i915);
+}
+
static void intel_init_dpio(struct drm_i915_private *dev_priv)
{
/*
pgpoTvkW48IFG.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Catch GTT fault errors for gen11+ planes
On Tue, Oct 08, 2019 at 10:34:48PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Catch GTT fault errors for gen11+ planes
> URL : https://patchwork.freedesktop.org/series/67752/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7036 -> Patchwork_14710
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14710 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14710, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14710:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live_coherency:
> - fi-skl-lmem:[PASS][1] -> [TIMEOUT][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-skl-lmem/igt@i915_selftest@live_coherency.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-skl-lmem/igt@i915_selftest@live_coherency.html
GEM_BUG_ON(gt->awake), not related to checking extra display interrupt
bits in this patch. Will request a re-test.
Matt
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14710 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_create@basic-files:
> - fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
>
> * igt@gem_exec_suspend@basic-s4-devices:
> - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
>
>
> Possible fixes
>
> * igt@gem_ctx_switch@rcs0:
> - fi-cml-u2: [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
>
> * igt@gem_tiled_blits@basic:
> - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-icl-u3/igt@gem_tiled_bl...@basic.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-icl-u3/igt@gem_tiled_bl...@basic.html
>
> * igt@i915_module_load@reload:
> - fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-blb-e6850/igt@i915_module_l...@reload.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-blb-e6850/igt@i915_module_l...@reload.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
> [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
> [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
> [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
> [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
>
>
> Participating hosts (51 -> 43)
> --
>
> Missing(8): fi-kbl-soraka fi-ilk-m540 fi-tgl-u fi-hsw-4200u
> fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
>
>
> Build changes
> -
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_7036 -> Patchwork_14710
>
> CI-20190529: 20190529
> CI_DRM_7036: a1b9c6723faeec2ee044e28a8e7e8ffe5aa434a0 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_14710: a199ddec9d887287b74eaac5e723b02169094353 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> a199ddec9d88 drm/i915: Catch GTT fault errors for gen11+ planes
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
between commit:
8a9a982767b7 ("drm/i915: use a separate context for gpu relocs")
from the drm tree and commit:
4ee92c7149da ("drm/mm: Convert drm_mm_node booleans to bitops")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index e8ddc2320efa,493f07806b08..
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@@ -908,8 -902,7 +908,8 @@@ static void reloc_cache_init(struct rel
cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
cache->has_fence = cache->gen < 4;
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
- cache->node.allocated = false;
+ cache->node.flags = 0;
+ cache->ce = NULL;
cache->rq = NULL;
cache->rq_size = 0;
}
pgpRUQmVqqtWB.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Reconfigurable OA queries
Quoting Lionel Landwerlin (2019-10-09 00:14:41) > On 09/10/2019 00:40, Chris Wilson wrote: > > This is Lionel's work to enable OA for Vulkan, greatly bastardised on > > top of the struct_mutex removal. It claims to be doing the right > > thing... > > -Chris > > > > > Thanks a lot of picking this up. > > I'm aware of an issue with patch 9 as I can see requests with perf > queries being preempted. Looking into that, but not quite there yet. Outside of the masking issue where a later request on the same context will mask the nopreempt request, if that nopreempt flag is set on the last submitted request to ELSP[0], we will not allow that context to be preempted before we consider the request to be completed. > I think there is a dependency issue with patch 8. We also use > cliprects_ptr for fences. Hmm, I was expecting the flag validation to be in the first patch to add extension parsing, but we are missing the test if both flags are set, reject the execbuf. > If we start reusing it for extended parameters, we need to make fences > the first extended param. Why? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
HI,
> -Original Message-
> From: Pandiyan, Dhinakaran
> Sent: Friday, October 4, 2019 5:08 PM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville ; Sharma, Shashank
> ; Antognolli, Rafael
> ; Roper, Matthew D
> ; Chery, Nanley G
> ; Ville Syrjala ;
> Kondapally, Kalyan
> Subject: Re: [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel
> Gen 12 render compression with Clear Color
>
> On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> >
> > Cc: Ville Syrjala
> > Cc: Dhinakaran Pandiyan
> > Cc: Kalyan Kondapally
> > Cc: Rafael Antognolli
> > Cc: Nanley Chery
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > include/uapi/drm/drm_fourcc.h | 11 +++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h
> > b/include/uapi/drm/drm_fourcc.h index c4a4e0fdbee5..99c61ee9b61f
> > 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -434,6 +434,17 @@ extern "C" {
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL,
> > 7)
> >
> > +/*
> > + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render
> compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC
> > +is linear
> > + * and at index 1.
>
> Clear color data is fixed size - 64b, that should be in the documentation
> here.
Sure will update the documentation in next rev.
Thanks,
Radhakrishna(RK) Sripada
>
>
> > The clear color is stored at index 2, and the pitch should
> > + * be ignored. A CCS_CC cache line corresponds to an area of 4x1
> > + tiles in the
> That's a CCS cache line, not a CCS_CC cache line, right?
>
> > + * main surface. The main surface pitch is required to be a multiple
> > +of 4 tile
> > + * widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > +fourcc_mod_code(INTEL, 8)
> > +
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > *
___
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Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
Hi Matt,
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, October 4, 2019 4:53 PM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Syrjala, Ville ;
> Sharma, Shashank ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject: Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL
> Render Decompression
>
> On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS
> > is linear and has 4 bits of data for each main surface cache line
> > pair, a ratio of 1:256. Additional Clear Color information is passed
> > from the user-space through an offset in the GEM BO. Add a new
> > modifier to identify and parse new Clear Color information and extend
> > Gen12 render decompression functionality to the newly added modifier.
> >
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjala
> > Cc: Shashank Sharma
> > Cc: Rafael Antognolli
> > Cc: Matt Roper
> > Cc: Nanley G Chery
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> > .../drm/i915/display/intel_display_types.h| 3 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 12 +
> > 4 files changed, 77 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4971c296f951..822237e98f00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> > if (color_plane == 1)
> > return 64;
> > /* fall through */
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + if (color_plane == 1 || color_plane == 2)
> > + return 64;
> > + /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
> > return 128;
> > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> > return 256 * 1024;
> > return 0;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return 16 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> color_plane)
> > return true;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return color_plane == 1;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + return color_plane == 1 || color_plane == 2;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > return color_plane == 1 || color_plane == 3;
> > default:
> > @@ -2458,6 +2465,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return I915_TILING_Y;
> > default:
> > return I915_TILING_NONE;
> > @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, };
> >
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line
> > +pair in the
> > + * main surface. And each 64B CCS cache line represents an area of
> > +4x1 Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having
> > +dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x
> > +32 pixels in
> > + * the main surface. Additional surface is used to pass the Clear
> > +Color
> > + * structure for the driver to program the DE.
> > + */
>
> Rather than duplicating the previous comment's text I'd just say
>
> "Same as gen12_ccs_formats[] above, but with an additional surface used to
> pass..."
Sure will update that in the next rev.
>
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > + { .format =
Re: [Intel-gfx] Reconfigurable OA queries
On 09/10/2019 00:40, Chris Wilson wrote: This is Lionel's work to enable OA for Vulkan, greatly bastardised on top of the struct_mutex removal. It claims to be doing the right thing... -Chris Thanks a lot of picking this up. I'm aware of an issue with patch 9 as I can see requests with perf queries being preempted. Looking into that, but not quite there yet. I think there is a dependency issue with patch 8. We also use cliprects_ptr for fences. If we start reusing it for extended parameters, we need to make fences the first extended param. -Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915/perf: store the associated engine of a stream
== Series Details ==
Series: series starting with [1/9] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67754/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7036 -> Patchwork_14711
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14711:
### IGT changes ###
Possible regressions
* {igt@i915_selftest@live_perf} (NEW):
- fi-hsw-4770r: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-hsw-4770r/igt@i915_selftest@live_perf.html
- fi-hsw-peppy: NOTRUN -> [DMESG-FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-hsw-peppy/igt@i915_selftest@live_perf.html
- fi-hsw-4770:NOTRUN -> [DMESG-FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-hsw-4770/igt@i915_selftest@live_perf.html
New tests
-
New tests have been introduced between CI_DRM_7036 and Patchwork_14711:
### New IGT tests (1) ###
* igt@i915_selftest@live_perf:
- Statuses : 3 dmesg-fail(s) 37 pass(s)
- Exec time: [0.40, 9.05] s
Known issues
Here are the changes found in Patchwork_14711 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][4] -> [INCOMPLETE][5] ([fdo#103927])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@rcs0:
- fi-apl-guc: [PASS][6] -> [INCOMPLETE][7] ([fdo#103927])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][8] -> [FAIL][9] ([fdo#109483])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- fi-cml-u2: [INCOMPLETE][10] ([fdo#110566]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][12] ([fdo#107718]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-blb-e6850/igt@i915_module_l...@reload.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/fi-blb-e6850/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
Participating hosts (51 -> 44)
--
Missing(7): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7036 -> Patchwork_14711
CI-20190529: 20190529
CI_DRM_7036: a1b9c6723faeec2ee044e28a8e7e8ffe5aa434a0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14711: e10189d046631a49ad7b1091530d230bab853abc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e10189d04663 drm/i915/perf: allow holding preemption on filtered ctx
bc30be642f73 drm/i915: add a new perf configuration execbuf parameter
338b278e09c1 drm/i915: introduce a mechanism to extend execbuf2
246ec5b5e2ab drm/i915/perf: execute OA configuration from command stream
099af51a2f41 drm/i915/perf: implement active wait for noa configurations
dfd555bac80c drm/i915: add support for perf configuration queries
94d1efac348c drm/i915/perf: allow for CS OA configs to be created lazily
94943b7df79b drm/i915/perf: introduce a versioning of the i915-perf uapi
f9a4f9fef858 drm/i915/perf: store the associated engine of a stream
== Logs ==
For more details see:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/perf: store the associated engine of a stream
== Series Details ==
Series: series starting with [1/9] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f9a4f9fef858 drm/i915/perf: store the associated engine of a stream
94943b7df79b drm/i915/perf: introduce a versioning of the i915-perf uapi
94d1efac348c drm/i915/perf: allow for CS OA configs to be created lazily
dfd555bac80c drm/i915: add support for perf configuration queries
099af51a2f41 drm/i915/perf: implement active wait for noa configurations
-:45: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#45: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:228:
+#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
^
-:202: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#202: FILE: drivers/gpu/drm/i915/i915_perf.c:1739:
+ DIV64_U64_ROUND_UP(
-:236: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#236: FILE: drivers/gpu/drm/i915/i915_perf.c:1773:
+ batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
-:244: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#244: FILE: drivers/gpu/drm/i915/i915_perf.c:1781:
+ cs = save_restore_register(
-:247: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#247: FILE: drivers/gpu/drm/i915/i915_perf.c:1784:
+ cs = save_restore_register(
-:349: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#349: FILE: drivers/gpu/drm/i915/i915_perf.c:1886:
+ cs = save_restore_register(
-:352: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#352: FILE: drivers/gpu/drm/i915/i915_perf.c:1889:
+ cs = save_restore_register(
-:469: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#469:
new file mode 100644
-:474: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#474: FILE: drivers/gpu/drm/i915/selftests/i915_perf.c:1:
+/*
-:475: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#475: FILE: drivers/gpu/drm/i915/selftests/i915_perf.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 3 warnings, 7 checks, 590 lines checked
246ec5b5e2ab drm/i915/perf: execute OA configuration from command stream
338b278e09c1 drm/i915: introduce a mechanism to extend execbuf2
-:118: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#118: FILE: include/uapi/drm/i915_drm.h:1168:
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS<<1))
^
total: 0 errors, 0 warnings, 1 checks, 92 lines checked
bc30be642f73 drm/i915: add a new perf configuration execbuf parameter
-:27: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#27:
v7: Hold drm.struct_mutex when serializing the request with OA config (Chris)
total: 0 errors, 1 warnings, 0 checks, 279 lines checked
e10189d04663 drm/i915/perf: allow holding preemption on filtered ctx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Catch GTT fault errors for gen11+ planes
== Series Details ==
Series: drm/i915: Catch GTT fault errors for gen11+ planes
URL : https://patchwork.freedesktop.org/series/67752/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7036 -> Patchwork_14710
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14710 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14710, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14710:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_coherency:
- fi-skl-lmem:[PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-skl-lmem/igt@i915_selftest@live_coherency.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-skl-lmem/igt@i915_selftest@live_coherency.html
Known issues
Here are the changes found in Patchwork_14710 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- fi-cml-u2: [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
* igt@gem_tiled_blits@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-icl-u3/igt@gem_tiled_bl...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-icl-u3/igt@gem_tiled_bl...@basic.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7036/fi-blb-e6850/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/fi-blb-e6850/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
Participating hosts (51 -> 43)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-tgl-u fi-hsw-4200u
fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7036 -> Patchwork_14710
CI-20190529: 20190529
CI_DRM_7036: a1b9c6723faeec2ee044e28a8e7e8ffe5aa434a0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14710: a199ddec9d887287b74eaac5e723b02169094353 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a199ddec9d88 drm/i915: Catch GTT fault errors for gen11+ planes
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14710/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/tgl: Enable DDI/Port G
In TGL there we are missing the initialization of port G.
Do the same as for other ports.
Signed-off-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_bios.c | 4
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
5 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 9628b485b179..53c8959acbdd 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1389,6 +1389,7 @@ static enum port dvo_port_to_port(u8 dvo_port)
[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
+ [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
};
enum port port;
int i;
@@ -2248,6 +2249,9 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *dev_priv,
case DP_AUX_F:
aux_ch = AUX_CH_F;
break;
+ case DP_AUX_G:
+ aux_ch = AUX_CH_G;
+ break;
default:
MISSING_CASE(info->alternate_aux_channel);
aux_ch = AUX_CH_A;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1a533ccdb54f..762e2c06a094 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6739,6 +6739,8 @@ enum intel_display_power_domain
intel_port_to_power_domain(enum port port)
return POWER_DOMAIN_PORT_DDI_E_LANES;
case PORT_F:
return POWER_DOMAIN_PORT_DDI_F_LANES;
+ case PORT_G:
+ return POWER_DOMAIN_PORT_DDI_G_LANES;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -6762,6 +6764,8 @@ intel_aux_power_domain(struct intel_digital_port
*dig_port)
return POWER_DOMAIN_AUX_E_TBT;
case AUX_CH_F:
return POWER_DOMAIN_AUX_F_TBT;
+ case AUX_CH_G:
+ return POWER_DOMAIN_AUX_G_TBT;
default:
MISSING_CASE(dig_port->aux_ch);
return POWER_DOMAIN_AUX_C_TBT;
@@ -6781,6 +6785,8 @@ intel_aux_power_domain(struct intel_digital_port
*dig_port)
return POWER_DOMAIN_AUX_E;
case AUX_CH_F:
return POWER_DOMAIN_AUX_F;
+ case AUX_CH_G:
+ return POWER_DOMAIN_AUX_G;
default:
MISSING_CASE(dig_port->aux_ch);
return POWER_DOMAIN_AUX_A;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 2782f23ee887..d8f33701f629 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -271,6 +271,7 @@ enum aux_ch {
AUX_CH_D,
AUX_CH_E, /* ICL+ */
AUX_CH_F,
+ AUX_CH_G,
};
#define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0e45c61d7331..e9dd42a7f420 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1644,6 +1644,7 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp
*intel_dp)
case AUX_CH_D:
case AUX_CH_E:
case AUX_CH_F:
+ case AUX_CH_G:
return DP_AUX_CH_CTL(aux_ch);
default:
MISSING_CASE(aux_ch);
@@ -1664,6 +1665,7 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp
*intel_dp, int index)
case AUX_CH_D:
case AUX_CH_E:
case AUX_CH_F:
+ case AUX_CH_G:
return DP_AUX_CH_DATA(aux_ch, index);
default:
MISSING_CASE(aux_ch);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index dfcd156b5094..e3045ced4bfe 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -291,6 +291,8 @@ struct bdb_general_features {
#define DVO_PORT_HDMIE 12 /* 193 */
#define DVO_PORT_DPF 13 /* N/A */
#define DVO_PORT_HDMIF 14 /* N/A */
+#define DVO_PORT_DPG 15
+#define DVO_PORT_HDMIG 16
#define DVO_PORT_MIPIA 21 /* 171 */
#define DVO_PORT_MIPIB 22 /* 171 */
#define DVO_PORT_MIPIC 23 /* 171 */
@@ -325,6 +327,7 @@ enum vbt_gmbus_ddi {
#define DP_AUX_D 0x30
#define DP_AUX_E
[Intel-gfx] [PATCH 8/9] drm/i915: add a new perf configuration execbuf parameter
From: Lionel Landwerlin
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process making the execbuf with this flag to
also own the perf fd at the time of execbuf.
v2: Add a emit_oa_config() vfunc in the intel_engine_cs (Chris)
Move oa_config vma to active (Chris)
v3: Don't drop the lock for engine lookup (Chris)
Move OA config vma to active before writing the ringbuffer (Chris)
v4: Reuse i915_user_extension_fn
Serialize requests with OA config updates
v5: Check that the chained extension is only present once (Chris)
Unpin oa_vma in main path (Chris)
v6: Use BIT_ULL (Chris)
v7: Hold drm.struct_mutex when serializing the request with OA config (Chris)
v8: Remove active request from engine (Lionel)
v9: Move fetching OA configuration pass engine pinning (Lionel)
Lock VMA before moving to active (Chris)
v10: Fix leak on perf_fd (Lionel)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 124 +-
drivers/gpu/drm/i915/i915_getparam.c | 4 +
include/uapi/drm/i915_drm.h | 44 ++-
3 files changed, 165 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6482141cca1a..bddc357e63bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -24,6 +24,7 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
+#include "i915_perf.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
@@ -47,6 +48,8 @@ enum {
#define __EXEC_INTERNAL_FLAGS (~0u << 30)
#define UPDATE PIN_OFFSET_FIXED
+#define EXTRA_VMA 2
+
#define BATCH_OFFSET_BIAS (256*1024)
#define __I915_EXEC_ILLEGAL_FLAGS \
@@ -273,6 +276,12 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
+
+ struct { /* HW configuration for OA. */
+ struct file *file;
+ struct i915_oa_config *config;
+ struct i915_vma *vma;
+ } oa;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -889,6 +898,12 @@ static void eb_destroy(const struct i915_execbuffer *eb)
if (eb->lut_size > 0)
kfree(eb->buckets);
+
+ if (eb->oa.config) {
+ i915_vma_put(eb->oa.vma);
+ i915_oa_config_put(eb->oa.config);
+ fput(eb->oa.file);
+ }
}
static inline u64
@@ -2045,6 +2060,58 @@ add_to_client(struct i915_request *rq, struct drm_file
*file)
spin_unlock(_priv->mm.lock);
}
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ struct i915_perf_stream *stream;
+ struct i915_perf *perf;
+ int err;
+
+ if (!eb->oa.config)
+ return 0;
+
+ stream = eb->oa.file->private_data;
+ perf = stream->perf;
+
+ err = mutex_lock_interruptible(>lock);
+ if (err)
+ return err;
+
+ if (stream != perf->exclusive_stream) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ if (stream->engine != eb->engine) { /* FIXME: virtual selection */
+ err = -EINVAL;
+ goto out;
+ }
+
+ err = i915_active_fence_set(>active_config, eb->request);
+ if (err)
+ goto out;
+
+ /*
+* If the config hasn't changed, skip reconfiguring the HW (this is
+* subject to a delay we want to avoid has much as possible).
+*
+* After a GPU reset, the oa config will not be recovered.
+*/
+ if (eb->oa.config == stream->oa_config)
+ goto out;
+
+ err = eb->engine->emit_bb_start(eb->request,
+ eb->oa.vma->node.start, 0,
+ I915_DISPATCH_SECURE); /* ggtt */
+ if (err)
+ goto out;
+
+ swap(eb->oa.config, stream->oa_config);
+
+out:
+ mutex_unlock(>lock);
+ return err;
+}
+
static int eb_submit(struct i915_execbuffer *eb)
{
int err;
@@ -2071,6 +2138,10 @@ static int eb_submit(struct i915_execbuffer *eb)
return err;
}
+ err = eb_oa_config(eb);
+ if (err)
+ return err;
+
err = eb->engine->emit_bb_start(eb->request,
eb->batch->node.start +
eb->batch_start_offset,
@@ -2421,7 +2492,39 @@ signal_fence_array(struct i915_execbuffer *eb,
}
}
+static int parse_perf_config(struct i915_user_extension __user *ext, void
*data)
+{
+
[Intel-gfx] [PATCH 7/9] drm/i915: introduce a mechanism to extend execbuf2
From: Lionel Landwerlin
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 34 ++-
include/uapi/drm/i915_drm.h | 22 ++--
2 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 98816c35ffc3..6482141cca1a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -25,6 +25,7 @@
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
enum {
FORCE_CPU_RELOC = 1,
@@ -1946,7 +1947,8 @@ static bool i915_gem_check_execbuffer(struct
drm_i915_gem_execbuffer2 *exec)
return false;
/* Kernel clipping was a DRI1 misfeature */
- if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
+ if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
+I915_EXEC_USE_EXTENSIONS))) {
if (exec->num_cliprects || exec->cliprects_ptr)
return false;
}
@@ -2419,6 +2421,32 @@ signal_fence_array(struct i915_execbuffer *eb,
}
}
+static const i915_user_extension_fn execbuf_extensions[] = {
+};
+
+static int
+eb_parse_extensions(struct i915_execbuffer *eb,
+ const struct drm_i915_gem_execbuffer2 *args)
+{
+ if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
+ return 0;
+
+ /*
+* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
+* have another flag also using it at the same time.
+*/
+ if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
+ return -EINVAL;
+
+ if (args->num_cliprects != 0)
+ return -EINVAL;
+
+ return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
+ execbuf_extensions,
+ ARRAY_SIZE(execbuf_extensions),
+ eb);
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
@@ -2498,6 +2526,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
GEM_BUG_ON(!eb.lut_size);
+ err = eb_parse_extensions(, args);
+ if (unlikely(err))
+ goto err_destroy;
+
err = eb_select_context();
if (unlikely(err))
goto err_destroy;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0c7b2815fbf1..06c5c187264b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1030,8 +1030,15 @@ struct drm_i915_gem_execbuffer2 {
__u32 num_cliprects;
/**
* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
-* is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
-* struct drm_i915_gem_exec_fence *fences.
+* & I915_EXEC_USE_EXTENSIONS are not set.
+*
+* If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
+* of struct drm_i915_gem_exec_fence and num_cliprects is the length
+* of the array.
+*
+* If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
+* single struct drm_i915_gem_base_execbuffer_ext and num_cliprects is
+* 0.
*/
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (0x3f)
@@ -1149,7 +1156,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
+/*
+ * Setting I915_EXEC_USE_EXTENSIONS implies that
+ * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
+ * list of i915_user_extension. Each i915_user_extension node is the base of a
+ * larger structure. The list of supported structures are listed in the
+ * drm_i915_gem_execbuffer_ext enum.
+ */
+#define I915_EXEC_USE_EXTENSIONS (1 << 21)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS<<1))
#define I915_EXEC_CONTEXT_ID_MASK (0x)
#define i915_execbuffer2_set_context_id(eb2, context) \
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/9] drm/i915/perf: implement active wait for noa configurations
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
v4: Fix save/restore helpers (Umesh)
v5: Move noa_wait from drm_i915_private to i915_perf_stream (Lionel)
v6: Add missing struct declarations in i915_perf.h
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 32 +++
drivers/gpu/drm/i915/i915_perf.c | 232 +-
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
drivers/gpu/drm/i915/i915_reg.h | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_perf.c| 196 +++
8 files changed, 478 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_perf.c
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 0987100c786b..8e63cffcabe0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -163,7 +163,8 @@
#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
-#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
+#define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -224,6 +225,7 @@
#define PIPE_CONTROL_CS_STALL(1<<20)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
+#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
#define PIPE_CONTROL_QW_WRITE(1<<14)
#define PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
#define PIPE_CONTROL_DEPTH_STALL (1<<13)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 802f516a3430..be4b263621c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -109,6 +109,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 277f31297f29..d463a28b7475 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3590,6 +3590,37 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+ const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
+
+ /*
+* This would lead to infinite waits as we're doing timestamp
+* difference on the CS with only 32bits.
+*/
+ if (val > mul_u32_u32(U32_MAX, clk))
+ return -EINVAL;
+
+ atomic64_set(>perf.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(>perf.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4340,6 +4371,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", _perf_noa_delay_fops},
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 183f1ac31e36..655980276e96 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -198,6 +198,7 @@
#include
[Intel-gfx] [PATCH 2/9] drm/i915/perf: introduce a versioning of the i915-perf uapi
From: Lionel Landwerlin
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
drivers/gpu/drm/i915/i915_perf.c | 10 ++
drivers/gpu/drm/i915/i915_perf.h | 1 +
include/uapi/drm/i915_drm.h | 21 +
4 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index f4b3cbb1adce..ad33fbe90a28 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -5,6 +5,7 @@
#include "gt/intel_engine_user.h"
#include "i915_drv.h"
+#include "i915_perf.h"
int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
@@ -156,6 +157,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(i915)->has_coherent_ggtt;
break;
+ case I915_PARAM_PERF_REVISION:
+ value = i915_perf_ioctl_version();
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 8fe1b72c07f8..027a1d39f006 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3666,3 +3666,13 @@ void i915_perf_fini(struct drm_i915_private *i915)
memset(>ops, 0, sizeof(perf->ops));
perf->i915 = NULL;
}
+
+/**
+ * i915_perf_ioctl_version - Version of the i915-perf subsystem
+ *
+ * This version number is used by userspace to detect available features.
+ */
+int i915_perf_ioctl_version(void)
+{
+ return 1;
+}
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index ff412fb0dbbf..295e33e8eef7 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -20,6 +20,7 @@ void i915_perf_init(struct drm_i915_private *i915);
void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
+int i915_perf_ioctl_version(void);
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 30c542144016..c50c712b3771 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -611,6 +611,13 @@ typedef struct drm_i915_irq_wait {
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
*/
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+
+/*
+ * Revision of the i915-perf uAPI. The value returned helps determine what
+ * i915-perf features are available. See drm_i915_perf_property_id.
+ */
+#define I915_PARAM_PERF_REVISION 54
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1844,23 +1851,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@@ -1870,6 +1885,8 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
@@ -1901,6 +1918,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@@ -1908,6 +1927,8 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
+ *
+ *
[Intel-gfx] [PATCH 1/9] drm/i915/perf: store the associated engine of a stream
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 29 +++---
drivers/gpu/drm/i915/i915_perf_types.h | 5 +
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..8fe1b72c07f8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -347,6 +348,7 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @engine: The engine (typically rcs0) being monitored by the OA unit
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +365,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -2127,7 +2131,13 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
int format_size;
int ret;
- /* If the sysfs metrics/ directory wasn't registered for some
+ if (!props->engine) {
+ DRM_DEBUG("OA engine not specified\n");
+ return -EINVAL;
+ }
+
+ /*
+* If the sysfs metrics/ directory wasn't registered for some
* reason then don't let userspace try their luck with config
* IDs
*/
@@ -2146,7 +2156,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -ENODEV;
}
- /* To avoid the complexity of having to accurately filter
+ /*
+* To avoid the complexity of having to accurately filter
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
@@ -2164,6 +2175,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
format_size = perf->oa_formats[props->oa_format].size;
+ stream->engine = props->engine;
+
stream->sample_flags |= SAMPLE_OA_REPORT;
stream->sample_size += format_size;
@@ -2192,7 +2205,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
goto err_config;
}
- /* PRM - observability performance counters:
+ /*
+* PRM - observability performance counters:
*
* OACONTROL, performance counter enable, note:
*
@@ -2796,6 +2810,15 @@ static int read_properties_unlocked(struct i915_perf
*perf,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = intel_engine_lookup_user(perf->i915,
+I915_ENGINE_CLASS_RENDER,
+0);
+ if (!props->engine) {
+ DRM_DEBUG("No RENDER-capable engines\n");
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..82cd3b295037 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -140,6 +140,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+* @engine: Engine associated with this performance stream.
+*/
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/9] drm/i915/perf: execute OA configuration from command stream
From: Lionel Landwerlin
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke things from the CPU.
Since we have a command buffer prepared for the execbuffer side of
things, we can reuse that approach here too.
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
v3: Take global lock to pin global
v4: Create i915 request in emit_oa_config() to avoid deadlocks (Lionel)
v5: Move locking to the stream (Lionel)
v6: Move active reconfiguration request into i915_perf_stream (Lionel)
v7: Pin VMA outside request creation (Chris)
Lock VMA before move to active (Chris)
v8: Fix double free on stream->initial_oa_config_bo (Lionel)
Don't allow interruption when waiting on active config request
(Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 105 -
drivers/gpu/drm/i915/i915_perf_types.h | 14 +++-
2 files changed, 63 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 655980276e96..05d6e10ac9fe 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1902,56 +1902,54 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
return 0;
err_unpin:
- __i915_vma_unpin(vma);
+ i915_vma_unpin_and_release(, 0);
err_unref:
i915_gem_object_put(bo);
return ret;
}
-static void config_oa_regs(struct intel_uncore *uncore,
- const struct i915_oa_reg *regs,
- u32 n_regs)
+static int emit_oa_config(struct i915_perf_stream *stream)
{
- u32 i;
+ struct i915_vma *vma = stream->initial_oa_vma;
+ struct i915_request *rq;
+ int err;
- for (i = 0; i < n_regs; i++) {
- const struct i915_oa_reg *reg = regs + i;
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ if (err)
+ goto err_vma_unpin;
- intel_uncore_write(uncore, reg->addr, reg->value);
+ rq = i915_request_create(stream->engine->kernel_context);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_add_request;
}
-}
-static void delay_after_mux(void)
-{
- /*
-* It apparently takes a fairly long time for a new MUX
-* configuration to be be applied after these register writes.
-* This delay duration was derived empirically based on the
-* render_basic config but hopefully it covers the maximum
-* configuration latency.
-*
-* As a fallback, the checks in _append_oa_reports() to skip
-* invalid OA reports do also seem to work to discard reports
-* generated before this config has completed - albeit not
-* silently.
-*
-* Unfortunately this is essentially a magic number, since we
-* don't currently know of a reliable mechanism for predicting
-* how long the MUX config will take to apply and besides
-* seeing invalid reports we don't know of a reliable way to
-* explicitly check that the MUX config has landed.
-*
-* It's even possible we've miss characterized the underlying
-* problem - it just seems like the simplest explanation why
-* a delay at this location would mitigate any invalid reports.
-*/
- usleep_range(15000, 2);
+ err = i915_active_fence_set(>perf->active_config, rq);
+ if (err)
+ goto err_add_request;
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, 0);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, 0);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_add_request;
+
+ err = rq->engine->emit_bb_start(rq,
+ vma->node.start, 0,
+ I915_DISPATCH_SECURE);
+err_add_request:
+ i915_request_add(rq);
+err_vma_unpin:
+ i915_vma_unpin(vma);
+
+ return err;
}
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->gt->uncore;
- const struct i915_oa_config *oa_config = stream->oa_config;
/*
* PRM:
@@ -1968,13 +1966,7 @@ static int hsw_enable_metric_set(struct i915_perf_stream
*stream)
intel_uncore_rmw(uncore, GEN6_UCGCTL1,
0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
- config_oa_regs(uncore, oa_config->mux_regs, oa_config->mux_regs_len);
- delay_after_mux();
-
- config_oa_regs(uncore, oa_config->b_counter_regs,
-
[Intel-gfx] Reconfigurable OA queries
This is Lionel's work to enable OA for Vulkan, greatly bastardised on top of the struct_mutex removal. It claims to be doing the right thing... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/9] drm/i915: add support for perf configuration queries
From: Lionel Landwerlin
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
v5: Drop lock when copying config content to userspace (Chris)
v6: Drop lock when copying config list to userspace (Chris)
Fix deadlock when calling i915_perf_get_oa_config() under
perf.metrics_lock (Lionel)
Add i915_oa_config_get() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 295 ++
include/uapi/drm/i915_drm.h | 62 ++-
3 files changed, 357 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5bd912c01db8..183f1ac31e36 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3644,8 +3644,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
GEM_BUG_ON(*arg != oa_config->id);
- sysfs_remove_group(perf->metrics_kobj,
- _config->sysfs_metric);
+ sysfs_remove_group(perf->metrics_kobj, _config->sysfs_metric);
idr_remove(>metrics_idr, *arg);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index abac5042da2b..6a68ecc7bb5f 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -7,6 +7,7 @@
#include
#include "i915_drv.h"
+#include "i915_perf.h"
#include "i915_query.h"
#include
@@ -140,10 +141,304 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+* We'll just put the number of registers, and won't copy the
+* register.
+*/
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg
*kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_perf_oa_config __user *user_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config));
+ struct drm_i915_perf_oa_config user_config;
+ struct i915_perf *perf = >perf;
+ struct i915_oa_config *oa_config;
+ char uuid[UUID_STRING_LEN + 1];
+ u64 config_id;
+ u32 flags, total_size;
+ int ret;
+
+ if (!perf->i915)
+ return -ENODEV;
+
+ total_size =
+ sizeof(struct drm_i915_query_perf_config) +
+ sizeof(struct drm_i915_perf_oa_config);
+
+ if (query_item->length == 0)
+ return total_size;
+
+ if (query_item->length < total_size) {
+
[Intel-gfx] [PATCH 9/9] drm/i915/perf: allow holding preemption on filtered ctx
From: Lionel Landwerlin
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of command buffer concept meant that
queries' duration could span multiple command buffers.
With that restriction gone in Vulkan, we would like to simplify
measuring performance just by measuring the deltas between the counter
snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
more complex scheme we currently have in the GL driver, using 2
MI_RECORD_PERF_COUNT commands and doing some post processing on the
stream of OA reports, coming from the global OA buffer, to remove any
unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
Disabling preemption only apply to a single context with which want to
query performance counters for and is considered a privileged
operation, by default protected by CAP_SYS_ADMIN. It is possible to
enable it for a normal user by disabling the paranoid stream setting.
v2: Store preemption setting in intel_context (Chris)
v3: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +
drivers/gpu/drm/i915/i915_perf.c | 31 +--
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
include/uapi/drm/i915_drm.h | 11 +++
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index bddc357e63bf..2c1cae09f8fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2090,6 +2090,14 @@ static int eb_oa_config(struct i915_execbuffer *eb)
if (err)
goto out;
+ /*
+* If the perf stream was opened with hold preemption, flag the
+* request properly so that the priority of the request is bumped once
+* it reaches the execlist ports.
+*/
+ if (stream->hold_preemption)
+ eb->request->flags |= I915_REQUEST_NOPREEMPT;
+
/*
* If the config hasn't changed, skip reconfiguring the HW (this is
* subject to a delay we want to avoid has much as possible).
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 05d6e10ac9fe..a6719b353f0a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -344,6 +344,8 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* struct perf_open_properties - for validated properties given to open a
stream
* @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
* @single_context: Whether a single or all gpu contexts should be monitored
+ * @hold_preemption: Whether the preemption is disabled for the filtered
+ * context
* @ctx_handle: A gem ctx handle for use with @single_context
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
@@ -359,6 +361,7 @@ struct perf_open_properties {
u32 sample_flags;
u64 single_context:1;
+ u64 hold_preemption:1;
u64 ctx_handle;
/* OA sampling state */
@@ -2557,6 +2560,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
if (WARN_ON(stream->oa_buffer.format_size == 0))
return -EINVAL;
+ stream->hold_preemption = props->hold_preemption;
+
stream->oa_buffer.format =
perf->oa_formats[props->oa_format].format;
@@ -3082,6 +3087,15 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
}
}
+ if (props->hold_preemption) {
+ if (!props->single_context) {
+ DRM_DEBUG("preemption disable with no context\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ privileged_op = true;
+ }
+
/*
* On Haswell the OA unit supports clock gating off for a specific
* context and in this mode there's no visibility of metrics for the
@@ -3096,7 +3110,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
* MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
* enable the OA unit by default.
*/
- if (IS_HASWELL(perf->i915) && specific_ctx)
+ if (IS_HASWELL(perf->i915) && specific_ctx && !props->hold_preemption)
privileged_op = false;
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
@@ -3106,7 +3120,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
[Intel-gfx] [PATCH 3/9] drm/i915/perf: allow for CS OA configs to be created lazily
From: Lionel Landwerlin
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
v2: No need for locking on object OA config object creation (Chris)
Flush cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
v4: Fix oa config unref/put when not found (Lionel)
v5: Allocate BOs for configurations on the stream instead of globally
(Lionel)
v6: Fix 64bit division (Chris)
v7: Store allocated config BOs into the stream (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 264 ---
drivers/gpu/drm/i915/i915_perf.h | 31 +++
drivers/gpu/drm/i915/i915_perf_types.h | 24 +-
4 files changed, 275 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index b0227ab2fe1b..0987100c786b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -138,6 +138,7 @@
/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
#define MI_LRI_CS_MMIO (1<<19)
#define MI_LRI_FORCE_POSTED (1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT(1<<22)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 027a1d39f006..5bd912c01db8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -369,52 +369,215 @@ struct perf_open_properties {
struct intel_engine_cs *engine;
};
+struct i915_oa_config_bo {
+ struct list_head link;
+
+ struct i915_oa_config *oa_config;
+ struct i915_vma *vma;
+};
+
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
-static void free_oa_config(struct i915_oa_config *oa_config)
+void i915_oa_config_release(struct kref *ref)
{
+ struct i915_oa_config *oa_config =
+ container_of(ref, typeof(*oa_config), ref);
+
if (!PTR_ERR(oa_config->flex_regs))
kfree(oa_config->flex_regs);
if (!PTR_ERR(oa_config->b_counter_regs))
kfree(oa_config->b_counter_regs);
if (!PTR_ERR(oa_config->mux_regs))
kfree(oa_config->mux_regs);
- kfree(oa_config);
+
+ kfree_rcu(oa_config, rcu);
}
-static void put_oa_config(struct i915_oa_config *oa_config)
+struct i915_oa_config *
+i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
{
- if (!atomic_dec_and_test(_config->ref_count))
- return;
+ struct i915_oa_config *oa_config;
- free_oa_config(oa_config);
+ rcu_read_lock();
+ if (metrics_set == 1)
+ oa_config = >test_config;
+ else
+ oa_config = idr_find(>metrics_idr, metrics_set);
+ if (oa_config)
+ oa_config = i915_oa_config_get(oa_config);
+ rcu_read_unlock();
+
+ return oa_config;
}
-static int get_oa_config(struct i915_perf *perf,
-int metrics_set,
-struct i915_oa_config **out_config)
+static u32 *write_cs_mi_lri(u32 *cs,
+ const struct i915_oa_reg *reg_data,
+ u32 n_regs)
{
- int ret;
+ u32 i;
- if (metrics_set == 1) {
- *out_config = >test_config;
- atomic_inc(>test_config.ref_count);
- return 0;
+ for (i = 0; i < n_regs; i++) {
+ if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
+ u32 n_lri = min_t(u32,
+ n_regs - i,
+ MI_LOAD_REGISTER_IMM_MAX_REGS);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
+ }
+ *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
+ *cs++ = reg_data[i].value;
}
- ret = mutex_lock_interruptible(>metrics_lock);
- if (ret)
- return ret;
+ return cs;
+}
- *out_config = idr_find(>metrics_idr, metrics_set);
- if (!*out_config)
- ret = -EINVAL;
- else
- atomic_inc(&(*out_config)->ref_count);
+static int num_lri_dwords(int num_regs)
+{
+ int count = 0;
-
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for intel_memory_region bits
Quoting Patchwork (2019-10-08 19:17:44) > == Series Details == > > Series: intel_memory_region bits > URL : https://patchwork.freedesktop.org/series/67738/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14704 > > > Summary > --- > > **SUCCESS** > > No regressions found. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/index.html Seems to be passing sanity checks and mock tests, so pushed! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Catch GTT fault errors for gen11+ planes
Gen11+ has more hardware planes than gen9 so we need to test additional
pipe interrupt register bits to recognize any GTT faults that happen on
these extra planes.
Bspec: 50335
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h | 8
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f2371b6083c6..5499450c1524 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2589,7 +2589,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 9)
+ if (INTEL_GEN(dev_priv) >= 11)
+ return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
+ else if (INTEL_GEN(dev_priv) >= 9)
return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
else
return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6d67bd238cfe..24311fee7009 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7373,6 +7373,9 @@ enum {
#define GEN8_PIPE_VSYNC (1 << 1)
#define GEN8_PIPE_VBLANK (1 << 0)
#define GEN9_PIPE_CURSOR_FAULT(1 << 11)
+#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
+#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
+#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
#define GEN9_PIPE_PLANE4_FAULT(1 << 10)
#define GEN9_PIPE_PLANE3_FAULT(1 << 9)
#define GEN9_PIPE_PLANE2_FAULT(1 << 8)
@@ -7392,6 +7395,11 @@ enum {
GEN9_PIPE_PLANE3_FAULT | \
GEN9_PIPE_PLANE2_FAULT | \
GEN9_PIPE_PLANE1_FAULT)
+#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
+ (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
+GEN11_PIPE_PLANE7_FAULT | \
+GEN11_PIPE_PLANE6_FAULT | \
+GEN11_PIPE_PLANE5_FAULT)
#define GEN8_DE_PORT_ISR _MMIO(0x0)
#define GEN8_DE_PORT_IMR _MMIO(0x4)
--
2.21.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Give engine->kernel_context distinct timeline lock classes
On Tue, 8 Oct 2019 at 19:59, Chris Wilson wrote: > > Assign a separate lockclass to the perma-pinned timelines of the > kernel_context, such that we can use them from within the user timelines > should we ever need to inject GPU operations to fixup faults during > request construction. > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Select DPLL's via mask (rev3)
== Series Details ==
Series: drm/i915: Select DPLL's via mask (rev3)
URL : https://patchwork.freedesktop.org/series/67740/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14709
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/index.html
Known issues
Here are the changes found in Patchwork_14709 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [INCOMPLETE][3] ([fdo#110566]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][5] ([fdo#107713]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111045] / [fdo#111096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7035 -> Patchwork_14709
CI-20190529: 20190529
CI_DRM_7035: 6256c298ba41f295206104fb6eaa067dde46a4d9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14709: 165d25fa4f3dc6a32162c0b8f98d676075b7fe33 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
165d25fa4f3d drm/i915: Select DPLL's via mask
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14709/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Give engine->kernel_context distinct timeline lock classes
== Series Details ==
Series: drm/i915/gt: Give engine->kernel_context distinct timeline lock classes
URL : https://patchwork.freedesktop.org/series/67748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14708
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/index.html
Known issues
Here are the changes found in Patchwork_14708 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_cpu_reloc@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_cpu_re...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/fi-icl-u3/igt@gem_cpu_re...@basic.html
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#109100])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927] /
[fdo#111381])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-apl-guc/igt@gem_ctx_swi...@legacy-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/fi-apl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][7] -> [DMESG-FAIL][8] ([fdo#111678])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [INCOMPLETE][9] ([fdo#110566]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111045] / [fdo#111096]) ->
[FAIL][12] ([fdo#111407])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (51 -> 44)
--
Missing(7): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7035 -> Patchwork_14708
CI-20190529: 20190529
CI_DRM_7035: 6256c298ba41f295206104fb6eaa067dde46a4d9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14708: ec149f282c0a186842e9247a4d7825da372e1fa9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ec149f282c0a drm/i915/gt: Give engine->kernel_context distinct timeline lock
classes
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14708/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH -next] treewide: remove unused argument in lock_release()
On Tue, Oct 08, 2019 at 06:33:51PM +0200, Daniel Vetter wrote:
> On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> > Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> > in __lock_release"), @nested is no longer used in lock_release(), so
> > remove it from all lock_release() calls and friends.
> >
> > Signed-off-by: Qian Cai
>
> Ack on the concept and for the drm parts (and feel free to keep the ack if
> you inevitably have to respin this later on). Might result in some
> conflicts, but welp we need to keep Linus busy :-)
>
> Acked-by: Daniel Vetter
Thanks Daniel!
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2.
On Fri, Oct 04, 2019 at 01:35:05PM +0200, Maarten Lankhorst wrote:
> When the clock is higher than the dotclock, try with 2 pipes enabled.
> If we can enable 2, then we will go into big joiner mode, and steal
> the adjacent crtc.
>
> This only links the crtc's in software, no hardware or plane
> programming is done yet. Blobs are also copied from the master's
> crtc_state, so it doesn't depend at commit time on the other
> crtc_state.
>
> Changes since v1:
> - Rename pipe timings to transcoder timings, as they are now different.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 15 +-
> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 218 --
> .../drm/i915/display/intel_display_types.h| 11 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 25 +-
> 5 files changed, 234 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 4783d7ff4fcf..a5b11bd9da68 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -228,25 +228,26 @@ void intel_crtc_free_hw_state(struct intel_crtc_state
> *crtc_state)
> intel_crtc_put_color_blobs(crtc_state);
> }
>
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state)
> {
> intel_crtc_put_color_blobs(crtc_state);
>
> - if (crtc_state->uapi.degamma_lut)
> + if (from_crtc_state->uapi.degamma_lut)
> crtc_state->hw.degamma_lut =
> - drm_property_blob_get(crtc_state->uapi.degamma_lut);
> +
> drm_property_blob_get(from_crtc_state->uapi.degamma_lut);
> else
> crtc_state->hw.degamma_lut = NULL;
>
> - if (crtc_state->uapi.gamma_lut)
> + if (from_crtc_state->uapi.gamma_lut)
> crtc_state->hw.gamma_lut =
> - drm_property_blob_get(crtc_state->uapi.gamma_lut);
> + drm_property_blob_get(from_crtc_state->uapi.gamma_lut);
> else
> crtc_state->hw.gamma_lut = NULL;
>
> - if (crtc_state->uapi.ctm)
> + if (from_crtc_state->uapi.ctm)
> crtc_state->hw.ctm =
> - drm_property_blob_get(crtc_state->uapi.ctm);
> + drm_property_blob_get(from_crtc_state->uapi.ctm);
> else
> crtc_state->hw.ctm = NULL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 42be91e0772a..8da84d64aa04 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -36,7 +36,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct
> drm_crtc *crtc);
> void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state);
> void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state
> *from_crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index caab8cfddcbd..c2b3c7b6f39b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -123,7 +123,7 @@ static void ironlake_pch_clock_get(struct intel_crtc
> *crtc,
> static int intel_framebuffer_init(struct intel_framebuffer *ifb,
> struct drm_i915_gem_object *obj,
> struct drm_mode_fb_cmd2 *mode_cmd);
> -static void intel_set_pipe_timings(const struct intel_crtc_state
> *crtc_state);
> +static void intel_set_transcoder_timings(const struct intel_crtc_state
> *crtc_state);
> static void intel_set_pipe_src_size(const struct intel_crtc_state
> *crtc_state);
> static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
> *crtc_state,
>const struct intel_link_m_n *m_n,
> @@ -6308,7 +6308,7 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> + intel_set_transcoder_timings(pipe_config);
> intel_set_pipe_src_size(pipe_config);
>
> if (pipe_config->has_pch_encoder) {
> @@ -6435,7 +6435,7 @@ static void
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
== Series Details ==
Series: drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
URL : https://patchwork.freedesktop.org/series/67736/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7033_full -> Patchwork_14703_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14703_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- {shard-tglb}: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-tglb1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
- {shard-tglb}: [PASS][2] -> [INCOMPLETE][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-tglb1/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-tglb6/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- {shard-tglb}: NOTRUN -> [SKIP][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-tglb6/igt@kms_rotation_...@primary-yf-tiled-reflect-x-0.html
Known issues
Here are the changes found in Patchwork_14703_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +12 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-iclb2/igt@gem_exec_sched...@in-order-bsd2.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-iclb6/igt@gem_exec_sched...@in-order-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +3 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-iclb5/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_pwrite@big-cpu-backwards:
- shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-apl3/igt@gem_pwr...@big-cpu-backwards.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-apl4/igt@gem_pwr...@big-cpu-backwards.html
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] /
[fdo#108686])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-iclb2/igt@gem_tiled_swapp...@non-threaded.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-iclb1/igt@gem_tiled_swapp...@non-threaded.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-hsw7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +4
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-apl7/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][19] -> [FAIL][20] ([fdo#103355])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-hsw1/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#105363])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html
[22]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Select DPLL's via mask (rev2)
== Series Details ==
Series: drm/i915: Select DPLL's via mask (rev2)
URL : https://patchwork.freedesktop.org/series/67740/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14707
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14707 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14707, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14707:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_hangcheck:
- fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_chamelium@common-hpd-after-suspend:
- {fi-icl-u4}:[DMESG-WARN][3] ([fdo#102505]) -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u4/igt@kms_chamel...@common-hpd-after-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/fi-icl-u4/igt@kms_chamel...@common-hpd-after-suspend.html
Known issues
Here are the changes found in Patchwork_14707 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u}: [INCOMPLETE][13] ([fdo#111747]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7035 -> Patchwork_14707
CI-20190529: 20190529
CI_DRM_7035: 6256c298ba41f295206104fb6eaa067dde46a4d9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14707: 9f19f31761837c7d1bdd38338cba24aa81782dfd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9f19f3176183 drm/i915: Select DPLL's via mask
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14707/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to dev_priv
== Series Details ==
Series: series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67743/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14706
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/index.html
Known issues
Here are the changes found in Patchwork_14706 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-write-gtt:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][5] -> [WARN][6] ([fdo#109483])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7035 -> Patchwork_14706
CI-20190529: 20190529
CI_DRM_7035: 6256c298ba41f295206104fb6eaa067dde46a4d9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14706: 6dece98d74194acab3101676766a41220f4ad509 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6dece98d7419 drm/i915/tgl: Read SAGV block time from PCODE
b44bcf0ca073 drm/i915: Move SAGV block time to dev_priv
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/index.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Give engine->kernel_context distinct timeline lock classes
Assign a separate lockclass to the perma-pinned timelines of the
kernel_context, such that we can use them from within the user timelines
should we ever need to inject GPU operations to fixup faults during
request construction.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 7e2aa7a6bef0..5aa1371f6a0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,6 +736,7 @@ intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass)
static struct intel_context *
create_kernel_context(struct intel_engine_cs *engine)
{
+ static struct lock_class_key kernel;
struct intel_context *ce;
int err;
@@ -751,6 +752,14 @@ create_kernel_context(struct intel_engine_cs *engine)
return ERR_PTR(err);
}
+ /*
+* Give our perma-pinned kernel timelines a separate lockdep class,
+* so that we can use them from within the normal user timelines
+* should we need to inject GPU operations during their request
+* construction.
+*/
+ lockdep_set_class(>timeline->mutex, );
+
return ce;
}
--
2.23.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to dev_priv
== Series Details ==
Series: series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67743/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b44bcf0ca073 drm/i915: Move SAGV block time to dev_priv
-:61: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#61: FILE: drivers/gpu/drm/i915/intel_pm.c:3657:
+ return;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 69 lines checked
6dece98d7419 drm/i915/tgl: Read SAGV block time from PCODE
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on
SNB-BDW sprites
URL : https://patchwork.freedesktop.org/series/67741/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14705
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/index.html
Known issues
Here are the changes found in Patchwork_14705 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [INCOMPLETE][5] ([fdo#110566]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111747]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7035 -> Patchwork_14705
CI-20190529: 20190529
CI_DRM_7035: 6256c298ba41f295206104fb6eaa067dde46a4d9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14705: cca2b959c9a9dd108b59504b3cceed096c61d162 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cca2b959c9a9 drm/i915: Eliminate redundancy in intel_primary_plane_create()
709d12b04c69 drm/i915: Do not enable HDR mode when color keying is active
ce206c719838 drm/i915: Reject ckey+fp16 on skl+
5c3dbeb08683 drm/i915: Sort format arrays consistently
13c5f2cb6cb3 drm/i915: Add 10bpc formats with alpha for icl+
966514314aea drm/i915: Expose C8 on VLV/CHV sprite planes
5030b840ef0b drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
0e88079e0ae0 drm/i915: Expose alpha formats on VLV/CHV primary planes
c4acf9d20614 drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for intel_memory_region bits
== Series Details ==
Series: intel_memory_region bits
URL : https://patchwork.freedesktop.org/series/67738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14704
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/index.html
Known issues
Here are the changes found in Patchwork_14704 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][1] -> [INCOMPLETE][2] ([fdo#110740])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-read:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@prime_v...@basic-fence-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/fi-icl-u3/igt@prime_v...@basic-fence-read.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109663]: https://bugs.freedesktop.org/show_bug.cgi?id=109663
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#110740]: https://bugs.freedesktop.org/show_bug.cgi?id=110740
Participating hosts (51 -> 44)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y fi-bdw-samus
fi-byt-clapper fi-skl-6700k2
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7035 -> Patchwork_14704
CI-20190529: 20190529
CI_DRM_7035: 6256c298ba41f295206104fb6eaa067dde46a4d9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14704: b534adaf17f68f0ed47100c6327d9a98c24bc5d3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b534adaf17f6 drm/i915/region: support volatile objects
beb9b59b5868 drm/i915/region: support contiguous allocations
46562367c0c6 drm/i915: introduce intel_memory_region
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14704/index.html
___
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Re: [Intel-gfx] [PATCH 14/24] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v2.
On Fri, Oct 04, 2019 at 01:35:04PM +0200, Maarten Lankhorst wrote:
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> eDP does not support bigjoiner, so do not expose bigjoiner only
> modes on the eDP port.
>
> Changes since v1:
> - Disallow bigjoiner on eDP.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 92 +++--
> 1 file changed, 72 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4297738655c6..5c7323af08b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -244,7 +244,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> }
>
> static int
> -intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
> +intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp, bool
> allow_bigjoiner)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = _dig_port->base;
> @@ -254,6 +254,9 @@ intel_dp_downstream_max_dotclock(struct intel_dp
> *intel_dp)
>
> int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
>
> + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11)
> + max_dotclk *= 2;
> +
This code is now rather confusing. OK, this function is already misnamed
because it checks both the source and downstream dotclock limits.
I suspect this should all look a bit more like:
source_max_dotclock()
{
if (port_can_do_bigjoiner && dsc_supported)
return 2*max_dotclock;
else
return max_dotclock;
}
max_dotclock = source_max_dotclock();
ds_max_dotclock = ds_max_dotclock()
if (ds_max_dotclock)
max_dotclock = min(max_dotclock, ds_max_dotclock);
> if (type != DP_DS_PORT_TYPE_VGA)
> return max_dotclk;
>
> @@ -506,7 +509,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
>
> static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> u32 link_clock, u32 lane_count,
> -u32 mode_clock, u32 mode_hdisplay)
> +u32 mode_clock, u32 mode_hdisplay,
> +bool bigjoiner)
> {
> u32 bits_per_pixel, max_bpp_small_joiner_ram;
> int i;
> @@ -524,6 +528,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> mode_hdisplay;
> +
> + if (bigjoiner)
> + max_bpp_small_joiner_ram *= 2;
> +
> DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
>
> /*
> @@ -532,6 +540,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
>*/
> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>
> + if (bigjoiner) {
> + u32 max_bpp_bigjoiner =
> + i915->max_cdclk_freq * 48 /
> + intel_dp_mode_to_fec_clock(mode_clock);
> +
> + DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
> + bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> + }
> +
> /* Error out if the max bpp is less than smallest allowed valid bpp */
> if (bits_per_pixel < valid_dsc_bpp[0]) {
> DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
> @@ -554,7 +571,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> }
>
> static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> -int mode_clock, int mode_hdisplay)
> +int mode_clock, int mode_hdisplay,
> +bool bigjoiner)
> {
> u8 min_slice_count, i;
> int max_slice_width;
> @@ -579,12 +597,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp
> *intel_dp,
>
> /* Find the closest match to the valid slice count values */
> for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
> - if (valid_dsc_slicecount[i] >
> - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> - false))
> + u8 test_slice_count = bigjoiner ?
> + 2 * valid_dsc_slicecount[i] :
> + valid_dsc_slicecount[i];
> +
> + if (test_slice_count >
> + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
> break;
> - if (min_slice_count <= valid_dsc_slicecount[i])
> - return valid_dsc_slicecount[i];
> +
> +
Re: [Intel-gfx] [PATCH 12/24] drm/i915: Split plane hw and uapi state
On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
> Splitting plane state is easier than splitting crtc_state,
> before plane check we copy the drm properties to hw so we can
> do the same in bigjoiner later on.
>
> We copy the state after we did all the modeset handling, but fortunately
> i915 seems to be split correctly and nothing during modeset looks
> at plane_state.
>
> Signed-off-by: Maarten Lankhorst
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> .../drm/i915/display/intel_display_types.h| 22 +--
> 4 files changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 01937896d69c..cc154cfa3381 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> intel_state->vma = NULL;
> intel_state->flags = 0;
>
> + /* will be set in intel_plane_atomic_check_with_state() */
> + memset(_state->hw, 0, sizeof(intel_state->hw));
That seems wrong for the case where we add the plane after the
plane check has already been done.
I think we should maintain the current state unless the plane check
will overwrite it.
> +
> return _state->uapi;
> }
>
> @@ -112,6 +115,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
> WARN_ON(plane_state->vma);
>
> __drm_atomic_helper_plane_destroy_state(_state->uapi);
> + if (plane_state->hw.fb)
> + drm_framebuffer_put(plane_state->hw.fb);
> kfree(plane_state);
> }
>
> @@ -138,15 +143,34 @@ unsigned int intel_plane_data_rate(const struct
> intel_crtc_state *crtc_state,
> return cpp * crtc_state->pixel_rate;
> }
>
> +void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> +const struct intel_plane_state
> *from_plane_state)
> +{
> + plane_state->hw.crtc = from_plane_state->uapi.crtc;
> + plane_state->hw.fb = from_plane_state->uapi.fb;
> + if (plane_state->hw.fb)
> + drm_framebuffer_get(plane_state->hw.fb);
> +
> + plane_state->hw.alpha = from_plane_state->uapi.alpha;
> + plane_state->hw.pixel_blend_mode =
> + from_plane_state->uapi.pixel_blend_mode;
> + plane_state->hw.rotation = from_plane_state->uapi.rotation;
> + plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
> + plane_state->hw.color_range = from_plane_state->uapi.color_range;
> +}
> +
> int intel_plane_atomic_check_with_state(const struct intel_crtc_state
> *old_crtc_state,
> struct intel_crtc_state *new_crtc_state,
> const struct intel_plane_state
> *old_plane_state,
> struct intel_plane_state
> *new_plane_state)
> {
> struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
> - const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> + const struct drm_framebuffer *fb;
> int ret;
>
> + intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
> + fb = new_plane_state->hw.fb;
> +
> new_crtc_state->active_planes &= ~BIT(plane->id);
> new_crtc_state->nv12_planes &= ~BIT(plane->id);
> new_crtc_state->c8_planes &= ~BIT(plane->id);
> @@ -373,6 +397,7 @@ intel_atomic_get_plane_state_after_check(struct
> intel_atomic_state *state,
> {
> struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> + const struct intel_plane_state *old_plane_state;
>
> if (plane_state)
> return plane_state;
> @@ -381,6 +406,16 @@ intel_atomic_get_plane_state_after_check(struct
> intel_atomic_state *state,
> if (IS_ERR(plane_state))
> return plane_state;
>
> + old_plane_state = intel_atomic_get_old_plane_state(state, plane);
> +
> + /*
> + * copy HW parameters since they're zero'd on duplication, to prevent
> + * accidentally using stale state.
> + */
> + plane_state->hw = old_plane_state->hw;
> + if (plane_state->hw.fb)
> + drm_framebuffer_get(plane_state->hw.fb);
> +
> new_crtc_state->update_planes |= BIT(plane->id);
> return plane_state;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index cb7ef4f9eafd..fd4b96013454 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs
> intel_plane_helper_funcs;
>
> unsigned int intel_plane_data_rate(const
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for intel_memory_region bits
== Series Details == Series: intel_memory_region bits URL : https://patchwork.freedesktop.org/series/67738/ State : warning == Summary == $ dim checkpatch origin/drm-tip 46562367c0c6 drm/i915: introduce intel_memory_region -:60: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #60: new file mode 100644 -:117: CHECK:SPACING: No space is necessary after a cast #117: FILE: drivers/gpu/drm/i915/gem/i915_gem_region.c:53: + prev_end = (resource_size_t) - 1; -:117: ERROR:SPACING: space prohibited after that '-' (ctx:WxW) #117: FILE: drivers/gpu/drm/i915/gem/i915_gem_region.c:53: + prev_end = (resource_size_t) - 1; ^ -:612: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #612: FILE: drivers/gpu/drm/i915/intel_memory_region.h:44: + struct mutex mm_lock; total: 1 errors, 1 warnings, 2 checks, 786 lines checked beb9b59b5868 drm/i915/region: support contiguous allocations -:318: WARNING:LINE_SPACING: Missing a blank line after declarations #318: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:130: + LIST_HEAD(holes); + I915_RND_STATE(prng); total: 0 errors, 1 warnings, 0 checks, 393 lines checked b534adaf17f6 drm/i915/region: support volatile objects ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Select DPLL's via mask
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware workarounds and such).
v2:
- Replace GENMASK() with or'd BIT()'s to make the specific DPLLs more
explicit. (Ville)
- s/unsigned/unsigned long/. (Lucas)
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 ++-
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5e9e84c94a15..ec10fa7d3c69 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -247,8 +247,7 @@ static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *pll_state,
- enum intel_dpll_id range_min,
- enum intel_dpll_id range_max)
+ unsigned long dpll_mask)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll, *unused_pll = NULL;
@@ -257,7 +256,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
shared_dpll = intel_atomic_get_shared_dpll_state(>base);
- for (i = range_min; i <= range_max; i++) {
+ WARN_ON(dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+
+ for_each_set_bit(i, _mask, I915_NUM_PLLS) {
pll = _priv->shared_dplls[i];
/* Only want to check enabled timings first */
@@ -464,8 +465,8 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
} else {
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_PCH_PLL_A,
-DPLL_ID_PCH_PLL_B);
+BIT(DPLL_ID_PCH_PLL_B) |
+BIT(DPLL_ID_PCH_PLL_A));
}
if (!pll)
@@ -814,7 +815,8 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
+BIT(DPLL_ID_WRPLL2) |
+BIT(DPLL_ID_WRPLL1));
if (!pll)
return NULL;
@@ -877,7 +879,7 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SPLL, DPLL_ID_SPLL);
+BIT(DPLL_ID_SPLL));
} else {
return false;
}
@@ -1447,13 +1449,13 @@ static bool skl_get_dpll(struct intel_atomic_state
*state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL0);
+BIT(DPLL_ID_SKL_DPLL0));
else
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL1,
-DPLL_ID_SKL_DPLL3);
+BIT(DPLL_ID_SKL_DPLL3) |
+BIT(DPLL_ID_SKL_DPLL2) |
+BIT(DPLL_ID_SKL_DPLL1));
if (!pll)
return false;
@@ -2401,8 +2403,9 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL2);
+BIT(DPLL_ID_SKL_DPLL2) |
+BIT(DPLL_ID_SKL_DPLL1) |
+BIT(DPLL_ID_SKL_DPLL0));
if (!pll) {
DRM_DEBUG_KMS("No PLL selected\n");
return false;
@@ -2975,7 +2978,7 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum port port = encoder->port;
- bool has_dpll4 = false;
+
[Intel-gfx] [CI v3 2/2] drm/i915/tgl: Read SAGV block time from PCODE
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc067fc57ab..0fb9030b89f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8878,6 +8878,7 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0ffcafe97216..e2aca3e81d28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
static void
skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ u32 val = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+ if (!ret) {
+ dev_priv->sagv_block_time_us = val;
+ return;
+ }
+
+ DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+ } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
--
2.22.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v3 1/2] drm/i915: Move SAGV block time to dev_priv
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.
v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)
v3: Change sagv_block_time_us to u32 (Lucas), Change fallback value to
-1 (Lucas), use intel_has_sagv for setup check rather than hand-rolling
(Lucas)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 33 -
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bcfb355aab4d..cb747706d469 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1266,6 +1266,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
+ u32 sagv_block_time_us;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..0ffcafe97216 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+ if (IS_GEN(dev_priv, 11)) {
+ dev_priv->sagv_block_time_us = 10;
+ return;
+ } else if (IS_GEN(dev_priv, 10)) {
+ dev_priv->sagv_block_time_us = 20;
+ return;
+ } else if (IS_GEN(dev_priv, 9)) {
+ dev_priv->sagv_block_time_us = 30;
+ return;
+ } else {
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ }
+
+ /* Default to an unusable block time */
+ dev_priv->sagv_block_time_us = -1;
+}
+
/*
* SAGV dynamically adjusts the system agent voltage and clock frequencies
* depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9))
- sagv_block_time_us = 30;
- else if (IS_GEN(dev_priv, 10))
- sagv_block_time_us = 20;
- else
- sagv_block_time_us = 10;
-
/*
* If there are no active CRTCs, no additional checks need be performed
*/
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us)
return false;
}
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
+ if (intel_has_sagv(dev_priv))
+ skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
--
2.22.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
> Use this in all the places where we try to acquire planes after the planes
> atomic_check().
>
> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
> but seems like it will be in the future. To add some paranoia, add all planes
> rather than active planes, because of bigjoiner and planar YUV support having
> extra planes outside of the core's view that wouldn't be added otherwise.
If the plane isn't active what good does adding it do?
Maybe the only real exception I can think of is the watermarks
and the primary vs. gamma/csc_enable on pre-skl, but those are
already handled correctly.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 41 +--
> .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +
> drivers/gpu/drm/i915/display/intel_cdclk.c| 15 ---
> drivers/gpu/drm/i915/display/intel_color.c| 7 ++--
> .../drm/i915/display/intel_display_types.h| 6 +++
> drivers/gpu/drm/i915/intel_pm.c | 14 ---
> 6 files changed, 66 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c5a552a69752..e6cb85d41c8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private
> *dev_priv,
> struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_plane *plane = NULL;
> - struct intel_plane *intel_plane;
> - struct intel_plane_state *plane_state = NULL;
> struct intel_crtc_scaler_state *scaler_state =
> _state->scaler_state;
> struct drm_atomic_state *drm_state = crtc_state->base.state;
> - struct intel_atomic_state *intel_state =
> to_intel_atomic_state(drm_state);
> + struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
> int num_scalers_need;
> int i;
>
> @@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
> *dev_priv,
>
> /* walkthrough scaler_users bits and start assigning scalers */
> for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
> + struct intel_plane_state *plane_state = NULL;
> int *scaler_id;
> const char *name;
> int idx;
> @@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private
> *dev_priv,
> /* panel fitter case: assign as a crtc scaler */
> scaler_id = _state->scaler_id;
> } else {
> - name = "PLANE";
> + struct intel_plane *plane;
>
> /* plane scaler case: assign as a plane scaler */
> /* find the plane that set the bit as scaler_user */
> - plane = drm_state->planes[i].ptr;
>
> /*
>* to enable/disable hq mode, add planes that are using
> scaler
>* into this transaction
>*/
> - if (!plane) {
> - struct drm_plane_state *state;
> -
> + if (!drm_state->planes[i].ptr) {
> /*
>* GLK+ scalers don't have a HQ mode so it
>* isn't necessary to change between HQ and dyn
> mode
> @@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private
> *dev_priv,
> if (INTEL_GEN(dev_priv) >= 10 ||
> IS_GEMINILAKE(dev_priv))
> continue;
>
> - plane = drm_plane_from_index(_priv->drm, i);
> - state = drm_atomic_get_plane_state(drm_state,
> plane);
> - if (IS_ERR(state)) {
> - DRM_DEBUG_KMS("Failed to add [PLANE:%d]
> to drm_state\n",
> - plane->base.id);
> - return PTR_ERR(state);
> + plane =
> to_intel_plane(drm_plane_from_index(_priv->drm, i));
> + plane_state =
> +
> intel_atomic_get_plane_state_after_check(state,
> +
> crtc_state,
> +
> plane);
> + if (IS_ERR(plane_state)) {
> + DRM_DEBUG_KMS("Failed to add [PLANE:%d]
> to drm_state: %li\n",
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Flush submission tasklet before waiting/retiring
== Series Details == Series: drm/i915/gt: Flush submission tasklet before waiting/retiring URL : https://patchwork.freedesktop.org/series/67732/ State : success == Summary == CI Bug Log - changes from CI_DRM_7032_full -> Patchwork_14701_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14701_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb5/igt@gem_exec_sched...@in-order-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-iclb1/igt@gem_exec_sched...@in-order-bsd.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb1/igt@gem_exec_sched...@out-order-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-iclb6/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@preempt-hang-vebox: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb4/igt@gem_exec_sched...@preempt-hang-vebox.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-iclb7/igt@gem_exec_sched...@preempt-hang-vebox.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html * igt@kms_busy@extended-modeset-hang-oldfb-render-c: - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-apl6/igt@kms_b...@extended-modeset-hang-oldfb-render-c.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-apl4/igt@kms_b...@extended-modeset-hang-oldfb-render-c.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-apl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-apl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@pipe-c-torture-bo: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#107122]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-apl2/igt@kms_cursor_leg...@pipe-c-torture-bo.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-apl8/igt@kms_cursor_leg...@pipe-c-torture-bo.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-move.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#108341]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb2/igt@kms_psr@no_drrs.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/shard-iclb1/igt@kms_psr@no_drrs.html *
Re: [Intel-gfx] [PATCH] drm/i915: Select DPLL's via mask
On Tue, Oct 08, 2019 at 07:28:45PM +0300, Ville Syrjälä wrote:
On Tue, Oct 08, 2019 at 09:12:52AM -0700, Matt Roper wrote:
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware workarounds and such).
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 42 +--
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5e9e84c94a15..14e040658b12 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -247,8 +247,7 @@ static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *pll_state,
- enum intel_dpll_id range_min,
- enum intel_dpll_id range_max)
+ unsigned long dpll_mask)
I don't like seeing lone longs hanging around since they
change meaning between 32bit and 64bit builds. Always makes
me suspicious.
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll, *unused_pll = NULL;
@@ -257,7 +256,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
shared_dpll = intel_atomic_get_shared_dpll_state(>base);
- for (i = range_min; i <= range_max; i++) {
+ WARN_ON(dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+
+ for_each_set_bit(i, _mask, I915_NUM_PLLS) {
But I guess this guy demands one :(
We are generally safe when the limit is much lower than the word sizes
we care about. I915_NUM_PLLS is currently 9 and I don't think it will go
near 32.
@@ -2975,7 +2975,7 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum port port = encoder->port;
- bool has_dpll4 = false;
+ unsigned dpll_mask;
for consistency this should be unsigned long too.
Lucas De Marchi
if (!icl_calc_dpll_state(crtc_state, encoder, _dpll->hw_state)) {
DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
@@ -2984,13 +2984,13 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
}
if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
- has_dpll4 = true;
+ dpll_mask = GENMASK(DPLL_ID_EHL_DPLL4, DPLL_ID_ICL_DPLL0);
+ else
+ dpll_mask = GENMASK(DPLL_ID_ICL_DPLL1, DPLL_ID_ICL_DPLL0);
port_dpll->pll = intel_find_shared_dpll(state, crtc,
_dpll->hw_state,
- DPLL_ID_ICL_DPLL0,
- has_dpll4 ? DPLL_ID_EHL_DPLL4
- : DPLL_ID_ICL_DPLL1);
+ dpll_mask);
if (!port_dpll->pll) {
DRM_DEBUG_KMS("No combo PHY PLL found for [ENCODER:%d:%s]\n",
encoder->base.base.id, encoder->base.name);
@@ -3023,8 +3023,7 @@ static bool icl_get_tc_phy_dplls(struct
intel_atomic_state *state,
port_dpll->pll = intel_find_shared_dpll(state, crtc,
_dpll->hw_state,
- DPLL_ID_ICL_TBTPLL,
- DPLL_ID_ICL_TBTPLL);
+ BIT(DPLL_ID_ICL_TBTPLL));
if (!port_dpll->pll) {
DRM_DEBUG_KMS("No TBT-ALT PLL found\n");
return false;
@@ -3043,8 +3042,7 @@ static bool icl_get_tc_phy_dplls(struct
intel_atomic_state *state,
encoder->port));
port_dpll->pll = intel_find_shared_dpll(state, crtc,
_dpll->hw_state,
- dpll_id,
- dpll_id);
+ BIT(dpll_id));
if (!port_dpll->pll) {
DRM_DEBUG_KMS("No MG PHY PLL found\n");
goto err_unreference_tbt_pll;
--
2.21.0
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--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] [PATCH -next] treewide: remove unused argument in lock_release()
On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> in __lock_release"), @nested is no longer used in lock_release(), so
> remove it from all lock_release() calls and friends.
>
> Signed-off-by: Qian Cai
Ack on the concept and for the drm parts (and feel free to keep the ack if
you inevitably have to respin this later on). Might result in some
conflicts, but welp we need to keep Linus busy :-)
Acked-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_connector.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 6 +++---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> drivers/tty/tty_ldsem.c | 8
> fs/dcache.c | 2 +-
> fs/jbd2/transaction.c | 4 ++--
> fs/kernfs/dir.c | 4 ++--
> fs/ocfs2/dlmglue.c| 2 +-
> include/linux/jbd2.h | 2 +-
> include/linux/lockdep.h | 21 ++---
> include/linux/percpu-rwsem.h | 4 ++--
> include/linux/rcupdate.h | 2 +-
> include/linux/rwlock_api_smp.h| 16
> include/linux/seqlock.h | 4 ++--
> include/linux/spinlock_api_smp.h | 8
> include/linux/ww_mutex.h | 2 +-
> include/net/sock.h| 2 +-
> kernel/bpf/stackmap.c | 2 +-
> kernel/cpu.c | 2 +-
> kernel/locking/lockdep.c | 3 +--
> kernel/locking/mutex.c| 4 ++--
> kernel/locking/rtmutex.c | 6 +++---
> kernel/locking/rwsem.c| 10 +-
> kernel/printk/printk.c| 10 +-
> kernel/sched/core.c | 2 +-
> lib/locking-selftest.c| 24
> mm/memcontrol.c | 2 +-
> net/core/sock.c | 2 +-
> tools/lib/lockdep/include/liblockdep/common.h | 3 +--
> tools/lib/lockdep/include/liblockdep/mutex.h | 2 +-
> tools/lib/lockdep/include/liblockdep/rwlock.h | 2 +-
> tools/lib/lockdep/preload.c | 16
> 33 files changed, 90 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 4c766624b20d..4a8b2e5c2af6 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -719,7 +719,7 @@ void drm_connector_list_iter_end(struct
> drm_connector_list_iter *iter)
> __drm_connector_put_safe(iter->conn);
> spin_unlock_irqrestore(>connector_list_lock, flags);
> }
> - lock_release(_list_iter_dep_map, 0, _RET_IP_);
> + lock_release(_list_iter_dep_map, _RET_IP_);
> }
> EXPORT_SYMBOL(drm_connector_list_iter_end);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> index edd21d14e64f..1a51b3598d63 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> @@ -509,14 +509,14 @@ void i915_gem_shrinker_taints_mutex(struct
> drm_i915_private *i915,
> I915_MM_SHRINKER, 0, _RET_IP_);
>
> mutex_acquire(>dep_map, 0, 0, _RET_IP_);
> - mutex_release(>dep_map, 0, _RET_IP_);
> + mutex_release(>dep_map, _RET_IP_);
>
> - mutex_release(>drm.struct_mutex.dep_map, 0, _RET_IP_);
> + mutex_release(>drm.struct_mutex.dep_map, _RET_IP_);
>
> fs_reclaim_release(GFP_KERNEL);
>
> if (unlock)
> - mutex_release(>drm.struct_mutex.dep_map, 0, _RET_IP_);
> + mutex_release(>drm.struct_mutex.dep_map, _RET_IP_);
> }
>
> #define obj_to_i915(obj__) to_i915((obj__)->base.dev)
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 65b5ca74b394..7f647243b3b9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -52,7 +52,7 @@ static inline unsigned long __timeline_mark_lock(struct
> intel_context *ce)
> static inline void __timeline_mark_unlock(struct intel_context *ce,
> unsigned long flags)
> {
> - mutex_release(>timeline->mutex.dep_map, 0, _THIS_IP_);
> + mutex_release(>timeline->mutex.dep_map, _THIS_IP_);
> local_irq_restore(flags);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index a53777dd371c..e1f1be4d0531 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1456,7
Re: [Intel-gfx] [PATCH] drm/i915: Select DPLL's via mask
On Tue, Oct 08, 2019 at 09:12:52AM -0700, Matt Roper wrote:
> This slightly simplifies the EHL DPLL4 handling and also gives us more
> flexibility in the future in case we need to skip the use of specific
> PLL's (e.g., due to hardware workarounds and such).
>
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 42 +--
> 1 file changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 5e9e84c94a15..14e040658b12 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -247,8 +247,7 @@ static struct intel_shared_dpll *
> intel_find_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_dpll_hw_state *pll_state,
> -enum intel_dpll_id range_min,
> -enum intel_dpll_id range_max)
> +unsigned long dpll_mask)
I don't like seeing lone longs hanging around since they
change meaning between 32bit and 64bit builds. Always makes
me suspicious.
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll, *unused_pll = NULL;
> @@ -257,7 +256,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
>
> shared_dpll = intel_atomic_get_shared_dpll_state(>base);
>
> - for (i = range_min; i <= range_max; i++) {
> + WARN_ON(dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
> +
> + for_each_set_bit(i, _mask, I915_NUM_PLLS) {
But I guess this guy demands one :(
> pll = _priv->shared_dplls[i];
>
> /* Only want to check enabled timings first */
> @@ -464,8 +465,8 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
> } else {
> pll = intel_find_shared_dpll(state, crtc,
>_state->dpll_hw_state,
> - DPLL_ID_PCH_PLL_A,
> - DPLL_ID_PCH_PLL_B);
> + GENMASK(DPLL_ID_PCH_PLL_B,
> + DPLL_ID_PCH_PLL_A));
I wonder if it wouldn't be better to always do BIT(A)|BIT(B)...
so that we won't get bitten if someone ever inserts new DPLL
IDs in the middle of the enum?
Anyways, seems at least as good as the current thing:
Reviewed-by: Ville Syrjälä
> }
>
> if (!pll)
> @@ -814,7 +815,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
>
> pll = intel_find_shared_dpll(state, crtc,
>_state->dpll_hw_state,
> - DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
> + GENMASK(DPLL_ID_WRPLL2, DPLL_ID_WRPLL1));
>
> if (!pll)
> return NULL;
> @@ -877,7 +878,7 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
>
> pll = intel_find_shared_dpll(state, crtc,
>_state->dpll_hw_state,
> - DPLL_ID_SPLL, DPLL_ID_SPLL);
> + BIT(DPLL_ID_SPLL));
> } else {
> return false;
> }
> @@ -1447,13 +1448,12 @@ static bool skl_get_dpll(struct intel_atomic_state
> *state,
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> pll = intel_find_shared_dpll(state, crtc,
>_state->dpll_hw_state,
> - DPLL_ID_SKL_DPLL0,
> - DPLL_ID_SKL_DPLL0);
> + BIT(DPLL_ID_SKL_DPLL0));
> else
> pll = intel_find_shared_dpll(state, crtc,
>_state->dpll_hw_state,
> - DPLL_ID_SKL_DPLL1,
> - DPLL_ID_SKL_DPLL3);
> + GENMASK(DPLL_ID_SKL_DPLL3,
> + DPLL_ID_SKL_DPLL1));
> if (!pll)
> return false;
>
> @@ -2401,8 +2401,8 @@ static bool cnl_get_dpll(struct intel_atomic_state
> *state,
>
> pll = intel_find_shared_dpll(state, crtc,
>_state->dpll_hw_state,
> - DPLL_ID_SKL_DPLL0,
> - DPLL_ID_SKL_DPLL2);
> + GENMASK(DPLL_ID_SKL_DPLL2,
> + DPLL_ID_SKL_DPLL0));
> if (!pll) {
> DRM_DEBUG_KMS("No PLL selected\n");
> return false;
> @@ -2975,7 +2975,7 @@ static bool icl_get_combo_phy_dpll(struct
> intel_atomic_state *state,
>
Re: [Intel-gfx] [PATCH] drm/i915: Select DPLL's via mask
On Tue, Oct 08, 2019 at 09:12:52AM -0700, Matt Roper wrote:
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware workarounds and such).
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 42 +--
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5e9e84c94a15..14e040658b12 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -247,8 +247,7 @@ static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *pll_state,
- enum intel_dpll_id range_min,
- enum intel_dpll_id range_max)
+ unsigned long dpll_mask)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll, *unused_pll = NULL;
@@ -257,7 +256,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
shared_dpll = intel_atomic_get_shared_dpll_state(>base);
- for (i = range_min; i <= range_max; i++) {
+ WARN_ON(dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+
+ for_each_set_bit(i, _mask, I915_NUM_PLLS) {
pll = _priv->shared_dplls[i];
/* Only want to check enabled timings first */
@@ -464,8 +465,8 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
} else {
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_PCH_PLL_A,
-DPLL_ID_PCH_PLL_B);
+GENMASK(DPLL_ID_PCH_PLL_B,
+DPLL_ID_PCH_PLL_A));
}
if (!pll)
@@ -814,7 +815,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
+GENMASK(DPLL_ID_WRPLL2, DPLL_ID_WRPLL1));
if (!pll)
return NULL;
@@ -877,7 +878,7 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SPLL, DPLL_ID_SPLL);
+BIT(DPLL_ID_SPLL));
} else {
return false;
}
@@ -1447,13 +1448,12 @@ static bool skl_get_dpll(struct intel_atomic_state
*state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL0);
+BIT(DPLL_ID_SKL_DPLL0));
else
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL1,
-DPLL_ID_SKL_DPLL3);
+GENMASK(DPLL_ID_SKL_DPLL3,
+ DPLL_ID_SKL_DPLL1));
if (!pll)
return false;
@@ -2401,8 +2401,8 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL2);
+GENMASK(DPLL_ID_SKL_DPLL2,
+DPLL_ID_SKL_DPLL0));
if (!pll) {
DRM_DEBUG_KMS("No PLL selected\n");
return false;
@@ -2975,7 +2975,7 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum port port = encoder->port;
- bool has_dpll4 = false;
+ unsigned dpll_mask;
if (!icl_calc_dpll_state(crtc_state, encoder, _dpll->hw_state)) {
DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
@@ -2984,13 +2984,13 @@ static bool icl_get_combo_phy_dpll(struct
[Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
From: Ville Syrjälä
According to the spec color keying is not supported with
fp16 pixel formats on skl+. Reject that combo.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index cc9e5c9668b1..d6cd46e3f738 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
return 0;
}
+static bool format_is_fp16(u32 format)
+{
+ switch (format) {
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return true;
+ default:
+ return false;
+ }
+}
+
static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
return -EINVAL;
}
+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
+ DRM_DEBUG_KMS("Color keying not supported with fp16 formats\n");
+ return -EINVAL;
+ }
+
return 0;
}
--
2.21.0
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[Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
From: Ville Syrjälä
Let's try to keep the pixel format arrays somewhat sorted:
1. RGB before YUV
2. smaller bpp before larger bpp
3. X before A
4. RGB before BGR
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 20 ++--
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1cdcd0ea0564..a8124f01bdb2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -83,8 +83,8 @@
/* Primary plane formats for gen <= 3 */
static const u32 i8xx_primary_formats[] = {
DRM_FORMAT_C8,
- DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB,
};
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index aaabeaf11ae9..cc9e5c9668b1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2002,10 +2002,10 @@ static const u64 i9xx_plane_format_modifiers[] = {
};
static const u32 snb_plane_formats[] = {
- DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
- DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2015,10 +2015,10 @@ static const u32 snb_plane_formats[] = {
static const u32 vlv_plane_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
- DRM_FORMAT_ABGR,
- DRM_FORMAT_ARGB,
- DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
@@ -2030,14 +2030,14 @@ static const u32 vlv_plane_formats[] = {
static const u32 chv_pipe_b_sprite_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
- DRM_FORMAT_ABGR,
- DRM_FORMAT_ARGB,
- DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
- DRM_FORMAT_XBGR2101010,
- DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
--
2.21.0
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[Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
From: Ville Syrjälä
SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 633fa8069348..90b0e65420a5 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1054,6 +1054,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
sprctl |= SPRITE_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR2101010:
+ sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX;
+ break;
+ case DRM_FORMAT_XRGB2101010:
+ sprctl |= SPRITE_FORMAT_RGBX101010;
+ break;
case DRM_FORMAT_YUYV:
sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
break;
@@ -1288,6 +1294,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
dvscntr |= DVS_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR2101010:
+ dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
+ break;
+ case DRM_FORMAT_XRGB2101010:
+ dvscntr |= DVS_FORMAT_RGBX101010;
+ break;
case DRM_FORMAT_YUYV:
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
break;
@@ -1983,6 +1995,8 @@ static const u64 i9xx_plane_format_modifiers[] = {
static const u32 snb_plane_formats[] = {
DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2193,6 +2207,8 @@ static bool snb_sprite_format_mod_supported(struct
drm_plane *_plane,
switch (format) {
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
--
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[Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes
From: Ville Syrjälä
Currently we expose VLV/CHV alpha blending only on the sprite
planes, but the primary planes can do it as well. Let's flip
it on.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 57 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1a533ccdb54f..1cdcd0ea0564 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -98,6 +98,20 @@ static const u32 i965_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+};
+
static const u64 i9xx_format_modifiers[] = {
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2952,6 +2966,8 @@ static int i9xx_format_to_fourcc(int format)
switch (format) {
case DISPPLANE_8BPP:
return DRM_FORMAT_C8;
+ case DISPPLANE_BGRA555:
+ return DRM_FORMAT_ARGB1555;
case DISPPLANE_BGRX555:
return DRM_FORMAT_XRGB1555;
case DISPPLANE_BGRX565:
@@ -2961,10 +2977,18 @@ static int i9xx_format_to_fourcc(int format)
return DRM_FORMAT_XRGB;
case DISPPLANE_RGBX888:
return DRM_FORMAT_XBGR;
+ case DISPPLANE_BGRA888:
+ return DRM_FORMAT_ARGB;
+ case DISPPLANE_RGBA888:
+ return DRM_FORMAT_ABGR;
case DISPPLANE_BGRX101010:
return DRM_FORMAT_XRGB2101010;
case DISPPLANE_RGBX101010:
return DRM_FORMAT_XBGR2101010;
+ case DISPPLANE_BGRA101010:
+ return DRM_FORMAT_ARGB2101010;
+ case DISPPLANE_RGBA101010:
+ return DRM_FORMAT_ABGR2101010;
}
}
@@ -3639,6 +3663,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB1555:
dspcntr |= DISPPLANE_BGRX555;
break;
+ case DRM_FORMAT_ARGB1555:
+ dspcntr |= DISPPLANE_BGRA555;
+ break;
case DRM_FORMAT_RGB565:
dspcntr |= DISPPLANE_BGRX565;
break;
@@ -3648,12 +3675,24 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XBGR:
dspcntr |= DISPPLANE_RGBX888;
break;
+ case DRM_FORMAT_ARGB:
+ dspcntr |= DISPPLANE_BGRA888;
+ break;
+ case DRM_FORMAT_ABGR:
+ dspcntr |= DISPPLANE_RGBA888;
+ break;
case DRM_FORMAT_XRGB2101010:
dspcntr |= DISPPLANE_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
dspcntr |= DISPPLANE_RGBX101010;
break;
+ case DRM_FORMAT_ARGB2101010:
+ dspcntr |= DISPPLANE_BGRA101010;
+ break;
+ case DRM_FORMAT_ABGR2101010:
+ dspcntr |= DISPPLANE_RGBA101010;
+ break;
default:
MISSING_CASE(fb->format->format);
return 0;
@@ -14634,8 +14673,12 @@ static bool i965_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
return modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED;
default:
@@ -14855,7 +14898,19 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ formats = vlv_primary_formats;
+ num_formats = ARRAY_SIZE(vlv_primary_formats);
+ modifiers = i9xx_format_modifiers;
+
+ plane->max_stride = i9xx_plane_max_stride;
+ plane->update_plane = i9xx_update_plane;
+ plane->disable_plane = i9xx_disable_plane;
+ plane->get_hw_state = i9xx_plane_get_hw_state;
+ plane->check_plane = i9xx_plane_check;
+
+ plane_funcs = _plane_funcs;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
formats =
[Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
From: Ville Syrjälä
CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the the primary
plane. Add the require bits to expose the new formats.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++--
drivers/gpu/drm/i915/i915_reg.h | 14 +
2 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 90b0e65420a5..fb36da58390a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -861,6 +861,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_ABGR2101010:
sprctl |= SP_FORMAT_RGBA1010102;
break;
+ case DRM_FORMAT_XRGB2101010:
+ sprctl |= SP_FORMAT_BGRX1010102;
+ break;
+ case DRM_FORMAT_ARGB2101010:
+ sprctl |= SP_FORMAT_BGRA1010102;
+ break;
case DRM_FORMAT_XBGR:
sprctl |= SP_FORMAT_RGBX;
break;
@@ -2017,6 +2023,22 @@ static const u32 vlv_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static const u32 chv_pipe_b_sprite_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -2241,6 +2263,8 @@ static bool vlv_sprite_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_ARGB2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -2637,8 +2661,13 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
plane->get_hw_state = vlv_plane_get_hw_state;
plane->check_plane = vlv_sprite_check;
- formats = vlv_plane_formats;
- num_formats = ARRAY_SIZE(vlv_plane_formats);
+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
+ formats = chv_pipe_b_sprite_formats;
+ num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
+ } else {
+ formats = vlv_plane_formats;
+ num_formats = ARRAY_SIZE(vlv_plane_formats);
+ }
modifiers = i9xx_plane_format_modifiers;
plane_funcs = _sprite_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd75eff1266..74bb5a6cbe4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6545,12 +6545,14 @@ enum {
#define SP_ENABLE(1 << 31)
#define SP_GAMMA_ENABLE (1 << 30)
#define SP_PIXFORMAT_MASK(0xf << 26)
-#define SP_FORMAT_YUV422 (0 << 26)
-#define SP_FORMAT_BGR565 (5 << 26)
-#define SP_FORMAT_BGRX (6 << 26)
-#define SP_FORMAT_BGRA (7 << 26)
-#define SP_FORMAT_RGBX1010102(8 << 26)
-#define SP_FORMAT_RGBA1010102(9 << 26)
+#define SP_FORMAT_YUV422 (0x0 << 26)
+#define SP_FORMAT_BGR565 (0x5 << 26)
+#define SP_FORMAT_BGRX (0x6 << 26)
+#define SP_FORMAT_BGRA (0x7 << 26)
+#define SP_FORMAT_RGBX1010102(0x8 << 26)
+#define SP_FORMAT_RGBA1010102(0x9 << 26)
+#define SP_FORMAT_BGRX1010102(0xa << 26) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102(0xb << 26) /* CHV pipe B */
#define SP_FORMAT_RGBX (0xe << 26)
#define SP_FORMAT_RGBA (0xf << 26)
#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
--
2.21.0
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[Intel-gfx] [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+
From: Ville Syrjälä
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 4cd0982dc8a2..aaabeaf11ae9 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_XRGB16161616F,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ARGB16161616F,
--
2.21.0
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[Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create()
From: Ville Syrjälä
Lots of redundant assignments inside intel_primary_plane_create().
Get rid of them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 43 +++-
1 file changed, 14 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c553a3417891..2acec838fb8e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14873,7 +14873,6 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
unsigned int possible_crtcs;
- const u64 *modifiers;
const u32 *formats;
int num_formats;
int ret, zpos;
@@ -14908,53 +14907,39 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
formats = vlv_primary_formats;
num_formats = ARRAY_SIZE(vlv_primary_formats);
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
-
- plane_funcs = _plane_funcs;
} else if (INTEL_GEN(dev_priv) >= 4) {
formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
-
- plane_funcs = _plane_funcs;
} else {
formats = i8xx_primary_formats;
num_formats = ARRAY_SIZE(i8xx_primary_formats);
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
+ }
+ if (INTEL_GEN(dev_priv) >= 4)
+ plane_funcs = _plane_funcs;
+ else
plane_funcs = _plane_funcs;
- }
+
+ plane->max_stride = i9xx_plane_max_stride;
+ plane->update_plane = i9xx_update_plane;
+ plane->disable_plane = i9xx_disable_plane;
+ plane->get_hw_state = i9xx_plane_get_hw_state;
+ plane->check_plane = i9xx_plane_check;
possible_crtcs = BIT(pipe);
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(_priv->drm, >base,
possible_crtcs, plane_funcs,
- formats, num_formats, modifiers,
+ formats, num_formats,
+ i9xx_format_modifiers,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
ret = drm_universal_plane_init(_priv->drm, >base,
possible_crtcs, plane_funcs,
- formats, num_formats, modifiers,
+ formats, num_formats,
+ i9xx_format_modifiers,
DRM_PLANE_TYPE_PRIMARY,
"plane %c",
plane_name(plane->i9xx_plane));
--
2.21.0
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[Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active
From: Ville Syrjälä
The spec says that color keying and HDR mode are mutually exclusive.
So let's not enable HDR mode when color keying is active.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 13 ++---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 98b7766eaa7a..f64204f6f37f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
+ new_crtc_state->ckey_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
new_plane_state->base.visible = false;
@@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
fb->format->format == DRM_FORMAT_C8)
new_crtc_state->c8_planes |= BIT(plane->id);
+ if (new_plane_state->base.visible &&
+ new_plane_state->ckey.flags)
+ new_crtc_state->ckey_planes |= BIT(plane->id);
+
if (new_plane_state->base.visible || old_plane_state->base.visible)
new_crtc_state->update_planes |= BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a8124f01bdb2..c553a3417891 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct
intel_crtc_state *crtc_state)
POSTING_READ(PIPECONF(cpu_transcoder));
}
+static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state)
+{
+ u8 ckey_planes = crtc_state->ckey_planes;
+ u8 sdr_planes = crtc_state->active_planes &
+ ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR));
+
+ return !ckey_planes && !sdr_planes;
+}
+
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct
intel_crtc_state *crtc_state)
val |= PIPEMISC_YUV420_ENABLE |
PIPEMISC_YUV420_MODE_FULL_BLEND;
- if (INTEL_GEN(dev_priv) >= 11 &&
- (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
- BIT(PLANE_CURSOR))) == 0)
+ if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state))
val |= PIPEMISC_HDR_MODE_PRECISION;
I915_WRITE(PIPEMISC(crtc->pipe), val);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40390d855815..4935ea41d3e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -949,6 +949,7 @@ struct intel_crtc_state {
u8 active_planes;
u8 nv12_planes;
u8 c8_planes;
+ u8 ckey_planes;
/* bitmask of planes that will be updated during the commit */
u8 update_planes;
--
2.21.0
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[Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
From: Ville Syrjälä
VLV/CHV sprite planes also support the C8 format. Let's expose that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index fb36da58390a..4cd0982dc8a2 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_VYUY:
sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
break;
+ case DRM_FORMAT_C8:
+ sprctl |= SP_FORMAT_8BPP;
+ break;
case DRM_FORMAT_RGB565:
sprctl |= SP_FORMAT_BGR565;
break;
@@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = {
};
static const u32 vlv_plane_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR,
DRM_FORMAT_ARGB,
@@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = {
};
static const u32 chv_pipe_b_sprite_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR,
DRM_FORMAT_ARGB,
@@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct
drm_plane *_plane,
}
switch (format) {
+ case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
case DRM_FORMAT_ABGR:
case DRM_FORMAT_ARGB:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74bb5a6cbe4f..577468928ffa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6546,6 +6546,7 @@ enum {
#define SP_GAMMA_ENABLE (1 << 30)
#define SP_PIXFORMAT_MASK(0xf << 26)
#define SP_FORMAT_YUV422 (0x0 << 26)
+#define SP_FORMAT_8BPP (0x2 << 26)
#define SP_FORMAT_BGR565 (0x5 << 26)
#define SP_FORMAT_BGRX (0x6 << 26)
#define SP_FORMAT_BGRA (0x7 << 26)
--
2.21.0
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[Intel-gfx] [PATCH] drm/i915: Select DPLL's via mask
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware workarounds and such).
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 42 +--
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5e9e84c94a15..14e040658b12 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -247,8 +247,7 @@ static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *pll_state,
- enum intel_dpll_id range_min,
- enum intel_dpll_id range_max)
+ unsigned long dpll_mask)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll, *unused_pll = NULL;
@@ -257,7 +256,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
shared_dpll = intel_atomic_get_shared_dpll_state(>base);
- for (i = range_min; i <= range_max; i++) {
+ WARN_ON(dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+
+ for_each_set_bit(i, _mask, I915_NUM_PLLS) {
pll = _priv->shared_dplls[i];
/* Only want to check enabled timings first */
@@ -464,8 +465,8 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
} else {
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_PCH_PLL_A,
-DPLL_ID_PCH_PLL_B);
+GENMASK(DPLL_ID_PCH_PLL_B,
+DPLL_ID_PCH_PLL_A));
}
if (!pll)
@@ -814,7 +815,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
+GENMASK(DPLL_ID_WRPLL2, DPLL_ID_WRPLL1));
if (!pll)
return NULL;
@@ -877,7 +878,7 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SPLL, DPLL_ID_SPLL);
+BIT(DPLL_ID_SPLL));
} else {
return false;
}
@@ -1447,13 +1448,12 @@ static bool skl_get_dpll(struct intel_atomic_state
*state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL0);
+BIT(DPLL_ID_SKL_DPLL0));
else
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL1,
-DPLL_ID_SKL_DPLL3);
+GENMASK(DPLL_ID_SKL_DPLL3,
+ DPLL_ID_SKL_DPLL1));
if (!pll)
return false;
@@ -2401,8 +2401,8 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
pll = intel_find_shared_dpll(state, crtc,
_state->dpll_hw_state,
-DPLL_ID_SKL_DPLL0,
-DPLL_ID_SKL_DPLL2);
+GENMASK(DPLL_ID_SKL_DPLL2,
+DPLL_ID_SKL_DPLL0));
if (!pll) {
DRM_DEBUG_KMS("No PLL selected\n");
return false;
@@ -2975,7 +2975,7 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum port port = encoder->port;
- bool has_dpll4 = false;
+ unsigned dpll_mask;
if (!icl_calc_dpll_state(crtc_state, encoder, _dpll->hw_state)) {
DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
@@ -2984,13 +2984,13 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
}
if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
-
Re: [Intel-gfx] [PATCH 2/3] drm/i915/region: support contiguous allocations
Quoting Matthew Auld (2019-10-08 17:01:15) > Some kernel internal objects may need to be allocated as a contiguous > block, also thinking ahead the various kernel io_mapping interfaces seem > to expect it, although this is purely a limitation in the kernel > API...so perhaps something to be improved. > > Signed-off-by: Matthew Auld > Cc: Joonas Lahtinen > Cc: Abdiel Janulgue > Cc: Michael J Ruhl Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-10-08 17:01:14)
> +static void close_objects(struct intel_memory_region *mem,
> + struct list_head *objects)
> +{
> + struct drm_i915_private *i915 = mem->i915;
> + struct drm_i915_gem_object *obj, *on;
> +
> + list_for_each_entry_safe(obj, on, objects, st_link) {
> + if (i915_gem_object_has_pinned_pages(obj))
> + i915_gem_object_unpin_pages(obj);
> + /* No polluting the memory region between tests */
> + __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> + i915_gem_object_put(obj);
> + list_del(>st_link);
I would quietly reorder this so we list_del before kref_put.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH 3/3] drm/i915/region: support volatile objects
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c| 17 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 12
.../gpu/drm/i915/gem/i915_gem_object_types.h| 9 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 17 -
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 12
drivers/gpu/drm/i915/intel_memory_region.c | 5 +
drivers/gpu/drm/i915/intel_memory_region.h | 6 ++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 ++---
9 files changed, 68 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 0c41e04ab8fa..5ae694c24df4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -117,13 +117,6 @@ static int i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
goto err;
}
- /* Mark the pages as dontneed whilst they are still pinned. As soon
-* as they are unpinned they are allowed to be reaped by the shrinker,
-* and the caller is expected to repopulate - the contents of this
-* object are only valid whilst active and pinned.
-*/
- obj->mm.madv = I915_MADV_DONTNEED;
-
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -143,7 +136,6 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
internal_free_pages(pages);
obj->mm.dirty = false;
- obj->mm.madv = I915_MADV_WILLNEED;
}
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
@@ -188,6 +180,15 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
drm_gem_private_object_init(>drm, >base, size);
i915_gem_object_init(obj, _gem_object_internal_ops);
+ /*
+* Mark the object as volatile, such that the pages are marked as
+* dontneed whilst they are still pinned. As soon as they are unpinned
+* they are allowed to be reaped by the shrinker, and the caller is
+* expected to repopulate - the contents of this object are only valid
+* whilst active and pinned.
+*/
+ i915_gem_object_set_volatile(obj);
+
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index dfd16d65630f..c5e14c9c805c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -145,6 +145,18 @@ i915_gem_object_is_contiguous(const struct
drm_i915_gem_object *obj)
return obj->flags & I915_BO_ALLOC_CONTIGUOUS;
}
+static inline bool
+i915_gem_object_is_volatile(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_VOLATILE;
+}
+
+static inline void
+i915_gem_object_set_volatile(struct drm_i915_gem_object *obj)
+{
+ obj->flags |= I915_BO_ALLOC_VOLATILE;
+}
+
static inline bool
i915_gem_object_type_has(const struct drm_i915_gem_object *obj,
unsigned long flags)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index c6a712cf7d7a..a387e3ee728b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -121,7 +121,8 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
/*
* Is the object to be mapped as read-only to the GPU
@@ -172,6 +173,12 @@ struct drm_i915_gem_object {
* List of memory region blocks allocated for this object.
*/
struct list_head blocks;
+ /**
+* Element within memory_region->objects or region->purgeable
+* if the object is marked as DONTNEED. Access is protected by
+* region->obj_lock.
+*/
+ struct list_head region_link;
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 2e941f093a20..b0ec0959c13f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -18,6 +18,9 @@ void
[Intel-gfx] [PATCH 0/3] intel_memory_region bits
First block of patches from the 'LMEM basics' series. Matthew Auld (3): drm/i915: introduce intel_memory_region drm/i915/region: support contiguous allocations drm/i915/region: support volatile objects drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/gem/i915_gem_internal.c | 17 +- drivers/gpu/drm/i915/gem/i915_gem_object.h| 18 ++ .../gpu/drm/i915/gem/i915_gem_object_types.h | 20 ++ drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 + drivers/gpu/drm/i915/gem/i915_gem_region.c| 169 +++ drivers/gpu/drm/i915/gem/i915_gem_region.h| 29 ++ .../gpu/drm/i915/gem/selftests/huge_pages.c | 97 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_memory_region.c| 203 + drivers/gpu/drm/i915/intel_memory_region.h| 90 ++ drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 +- .../drm/i915/selftests/i915_mock_selftests.h | 1 + .../drm/i915/selftests/intel_memory_region.c | 280 ++ .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + drivers/gpu/drm/i915/selftests/mock_region.c | 59 drivers/gpu/drm/i915/selftests/mock_region.h | 16 + 17 files changed, 995 insertions(+), 19 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/region: support contiguous allocations
Some kernel internal objects may need to be allocated as a contiguous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Cc: Michael J Ruhl
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 15 +-
drivers/gpu/drm/i915/gem/i915_gem_region.h| 3 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 71
drivers/gpu/drm/i915/intel_memory_region.c| 9 +-
drivers/gpu/drm/i915/intel_memory_region.h| 3 +-
.../drm/i915/selftests/intel_memory_region.c | 165 ++
drivers/gpu/drm/i915/selftests/mock_region.c | 2 +-
9 files changed, 239 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 086a9bf5adcc..dfd16d65630f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -139,6 +139,12 @@ i915_gem_object_is_readonly(const struct
drm_i915_gem_object *obj)
return obj->base.vma_node.readonly;
}
+static inline bool
+i915_gem_object_is_contiguous(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_CONTIGUOUS;
+}
+
static inline bool
i915_gem_object_type_has(const struct drm_i915_gem_object *obj,
unsigned long flags)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 11390586cfe1..c6a712cf7d7a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -119,6 +119,10 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
+ unsigned long flags;
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index fad3a94641e9..89708b3fa03d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -23,10 +23,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
{
struct intel_memory_region *mem = obj->mm.region;
struct list_head *blocks = >mm.blocks;
- unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
resource_size_t size = obj->base.size;
resource_size_t prev_end;
struct i915_buddy_block *block;
+ unsigned int flags;
struct sg_table *st;
struct scatterlist *sg;
unsigned int sg_page_sizes;
@@ -41,6 +41,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
return -ENOMEM;
}
+ flags = I915_ALLOC_MIN_PAGE_SIZE;
+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
+ flags |= I915_ALLOC_CONTIGUOUS;
+
ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
if (ret)
goto err_free_sg;
@@ -55,7 +59,8 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
list_for_each_entry(block, blocks, link) {
u64 block_size, offset;
- block_size = i915_buddy_block_size(>mm, block);
+ block_size = min_t(u64, size,
+ i915_buddy_block_size(>mm, block));
offset = i915_buddy_block_offset(block);
GEM_BUG_ON(overflows_type(block_size, sg->length));
@@ -96,10 +101,12 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
}
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem)
+ struct intel_memory_region *mem,
+ unsigned long flags)
{
INIT_LIST_HEAD(>mm.blocks);
obj->mm.region = intel_memory_region_get(mem);
+ obj->flags |= flags;
}
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj)
@@ -120,6 +127,8 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
* future.
*/
+ GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index ebddc86d78f7..f2ff6f8bff74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -17,7 +17,8 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
[Intel-gfx] [PATCH 1/3] drm/i915: introduce intel_memory_region
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of course device. At some point we are probably going to want
use a common struct here, such that we are better aligned with say TTM.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Niranjana Vishwanathapura
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 2 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 145 +
drivers/gpu/drm/i915/gem/i915_gem_region.h| 28 +++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 78 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_memory_region.c| 191 ++
drivers/gpu/drm/i915/intel_memory_region.h| 83
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 115 +++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
drivers/gpu/drm/i915/selftests/mock_region.c | 59 ++
drivers/gpu/drm/i915/selftests/mock_region.h | 16 ++
13 files changed, 729 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a6006aa715ff..e791d9323b51 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -51,6 +51,7 @@ i915-y += i915_drv.o \
i915_utils.o \
intel_csr.o \
intel_device_info.o \
+ intel_memory_region.o \
intel_pch.o \
intel_pm.o \
intel_runtime_pm.o \
@@ -121,6 +122,7 @@ gem-y += \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
gem/i915_gem_pm.o \
+ gem/i915_gem_region.o \
gem/i915_gem_shmem.o \
gem/i915_gem_shrinker.o \
gem/i915_gem_stolen.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index c00b4f077f9e..11390586cfe1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -160,6 +160,15 @@ struct drm_i915_gem_object {
atomic_t pages_pin_count;
atomic_t shrink_pin;
+ /**
+* Memory region for this object.
+*/
+ struct intel_memory_region *region;
+ /**
+* List of memory region blocks allocated for this object.
+*/
+ struct list_head blocks;
+
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
new file mode 100644
index ..fad3a94641e9
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "i915_gem_region.h"
+#include "i915_drv.h"
+
+void
+i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ __intel_memory_region_put_pages_buddy(obj->mm.region, >mm.blocks);
+
+ obj->mm.dirty = false;
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = >mm.blocks;
+ unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
+ resource_size_t size = obj->base.size;
+ resource_size_t prev_end;
+ struct i915_buddy_block *block;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_page_sizes;
+ int ret;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size), GFP_KERNEL)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
+ if (ret)
+ goto err_free_sg;
+
+ GEM_BUG_ON(list_empty(blocks));
+
+ sg = st->sgl;
+ st->nents = 0;
+ sg_page_sizes = 0;
+ prev_end = (resource_size_t) - 1;
+
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
== Series Details ==
Series: drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
URL : https://patchwork.freedesktop.org/series/67736/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7033 -> Patchwork_14703
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/index.html
Known issues
Here are the changes found in Patchwork_14703 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111045] / [fdo#111096])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-guc}: [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][5] ([fdo#109483]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7033 -> Patchwork_14703
CI-20190529: 20190529
CI_DRM_7033: 6bfe790ee0b4b350f112fb580bab4c05dcdffa16 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5217: b2e51cc6dfcf198afbd9c5e51fbb4b40d930627e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14703: aa2d638d01cf5c50a95e1424cbbb1ba525c09f51 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
aa2d638d01cf drm/i915/selftests: Assign the intel_runtime_pm pointer for
mock_uncore
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
On Tue, 2019-10-01 at 14:54 +0100, Chris Wilson wrote:
> Allow the user to restrict the available set of engines via a module
> parameter.
>
> Signed-off-by: Chris Wilson
> Cc: Stuart Summers
> Cc: Andi Shyti
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Martin Peres
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 -
> --
> drivers/gpu/drm/i915/i915_gem.c | 5
> drivers/gpu/drm/i915/i915_params.c| 4 +++
> drivers/gpu/drm/i915/i915_params.h| 1 +
> 4 files changed, 35 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 80fd072ac719..690da64ec256 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -389,6 +389,29 @@ void intel_engines_cleanup(struct
> drm_i915_private *i915)
> }
> }
>
> +static bool engine_available(struct drm_i915_private *i915, int id)
> +{
> + /* uAPI -- modparam bits must be consistent between kernels */
> + static const unsigned int param_bit[] = {
> + [RCS0] = BIT(0),
> + [VCS0] = BIT(1),
> + [BCS0] = BIT(2),
> + [VECS0] = BIT(3),
> + [VCS1] = BIT(4),
> + [VCS2] = BIT(5),
> + [VCS3] = BIT(6),
> + [VECS1] = BIT(7),
> + };
To be a little controversial here... I don't see how this is better
than just matching to our currently available engines for the platform.
The user will still need to look in the code to determine what engines
are available. I understand this restricts us to a static module
parameter across kernel revisions, but at the same time, this will add
a maintenance burden for an unsafe feature, something not used
regularly. And it seems like this will be easy to get stale over time.
> +
> + if (!HAS_ENGINE(i915, id))
> + return false;
> +
> + if (!(i915_modparams.engines & param_bit[id]))
> + return false;
> +
> + return true;
> +}
> +
> /**
> * intel_engines_init_mmio() - allocate and prepare the Engine
> Command Streamers
> * @i915: the i915 device
> @@ -397,7 +420,6 @@ void intel_engines_cleanup(struct
> drm_i915_private *i915)
> */
> int intel_engines_init_mmio(struct drm_i915_private *i915)
> {
> - struct intel_device_info *device_info =
> mkwrite_device_info(i915);
> const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
> unsigned int mask = 0;
> unsigned int i;
> @@ -411,7 +433,7 @@ int intel_engines_init_mmio(struct
> drm_i915_private *i915)
> return -ENODEV;
>
> for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
> - if (!HAS_ENGINE(i915, i))
> + if (!engine_available(i915, i))
> continue;
>
> err = intel_engine_setup(>gt, i);
> @@ -421,14 +443,7 @@ int intel_engines_init_mmio(struct
> drm_i915_private *i915)
> mask |= BIT(i);
> }
>
> - /*
> - * Catch failures to update intel_engines table when the new
> engines
> - * are added to the driver by a warning and disabling the
> forgotten
> - * engines.
> - */
> - if (WARN_ON(mask != engine_mask))
> - device_info->engine_mask = mask;
> -
> + mkwrite_device_info(i915)->engine_mask = mask;
> RUNTIME_INFO(i915)->num_engines = hweight32(mask);
>
> intel_gt_check_and_clear_faults(>gt);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index 3d3fda4cae99..bb25731466a9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1308,6 +1308,11 @@ int i915_gem_init(struct drm_i915_private
> *dev_priv)
> {
> int ret;
>
> + if (!RUNTIME_INFO(dev_priv)->num_engines) {
> + intel_gt_set_wedged_on_init(_priv->gt);
> + return 0;
> + }
Wait, why do we want to force a wedge if no engines are present? This
seems like an intentional limitation if we get to this point, so it
doesn't seem necessary to me to force this.
> +
> /* We need to fallback to 4K pages if host doesn't support huge
> gtt. */
> if (intel_vgpu_active(dev_priv) &&
> !intel_vgpu_has_huge_gtt(dev_priv))
> mkwrite_device_info(dev_priv)->page_sizes =
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 296452f9efe4..27813bd79aa8 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -44,6 +44,10 @@ i915_param_named(modeset, int, 0400,
> "Use kernel modesetting [KMS] (0=disable, "
> "1=on, -1=force vga console preference [default])");
>
> +i915_param_named(engines, uint, 0400,
> + "Only expose selected command streamers [GPU engines]
> (0=disable GPU, "
> + "-1/0x enable all [default]). Each bit corresponds to a
> different
Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Restrict availables engines to rcs0 by default
On Tue, 2019-10-01 at 14:54 +0100, Chris Wilson wrote: > CI is still unstable whenever we enable more than one engine, and we > have not yet found a better hack than restricting it to using just > rcs0. > > However, to allow testing to continue on the other engines by > developers, we allow the available set of engines to be overridden on > the command line with just the default set limited to [rcs0]. > > Signed-off-by: Chris Wilson > Cc: Andi Shyti > Cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 690da64ec256..9c8c7c8af394 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -406,6 +406,10 @@ static bool engine_available(struct > drm_i915_private *i915, int id) > if (!HAS_ENGINE(i915, id)) > return false; > > + /* XXX reduced by default for CI stability XXX */ > + if (IS_TIGERLAKE(i915) && i915_modparams.engines == -1u) > + return id == RCS0; > + So I'm not completely against this, and I generally (from a debug perspective) like the idea of being able to tweak this kind of thing. But given our CI, is this really needed on top of just reducing the engines in i915_pci.c? Thanks, Stuart > if (!(i915_modparams.engines & param_bit[id])) > return false; > smime.p7s Description: S/MIME cryptographic signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
On Tue, 8 Oct 2019 at 15:50, Chris Wilson wrote: > > Couple up our mock_uncore to know about the fake global device and its > runtime powermanagement. > > Signed-off-by: Chris Wilson > Cc: Matthew Auld Thanks, Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/perf: drop list of streams
== Series Details ==
Series: drm/i915/perf: drop list of streams
URL : https://patchwork.freedesktop.org/series/67734/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7033 -> Patchwork_14702
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14702 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14702, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14702:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_workarounds:
- fi-skl-6260u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-skl-6260u/igt@i915_selftest@live_workarounds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/fi-skl-6260u/igt@i915_selftest@live_workarounds.html
Known issues
Here are the changes found in Patchwork_14702 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111045] / [fdo#111096])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- {fi-cml-s}: [INCOMPLETE][9] ([fdo#110566] / [fdo#111381]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-cml-s/igt@gem_ctx_swi...@legacy-render.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/fi-cml-s/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][11] ([fdo#109483]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7033/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7033 -> Patchwork_14702
CI-20190529: 20190529
CI_DRM_7033: 6bfe790ee0b4b350f112fb580bab4c05dcdffa16 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5217: b2e51cc6dfcf198afbd9c5e51fbb4b40d930627e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14702: b4cd330075a4a4d735306fa478669c86778c295e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b4cd330075a4 drm/i915/perf: drop list of streams
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14702/index.html
___
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush submission tasklet before waiting/retiring
On Tue, 2019-10-08 at 15:56 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-10-08 15:52:15)
> > On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> > > A common bane of ours is arbitrary delays in ksoftirqd processing
> > > our
> > > submission tasklet. Give the submission tasklet a kick before we
> > > wait
> > > to
> > > avoid those delays eating into a tight timeout.
> > >
> > > Signed-off-by: Chris Wilson
Reviewed-by: Stuart Summers
Ok, thanks for both of these responses. I agree with what you have here
in that case.
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_engine.h | 3 +-
> > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 +
> > >
> > >
> > > drivers/gpu/drm/i915/gt/intel_gt_requests.c | 12
> > > 3 files changed, 34 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> > > b/drivers/gpu/drm/i915/gt/intel_engine.h
> > > index c9e8c8ccbd47..d624752f2a92 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > > @@ -407,8 +407,9 @@ static inline void
> > > __intel_engine_reset(struct
> > > intel_engine_cs *engine,
> > > engine->serial++; /* contexts lost */
> > > }
> > >
> > > -bool intel_engine_is_idle(struct intel_engine_cs *engine);
> > > bool intel_engines_are_idle(struct intel_gt *gt);
> > > +bool intel_engine_is_idle(struct intel_engine_cs *engine);
> > > +void intel_engine_flush_submission(struct intel_engine_cs
> > > *engine);
> > >
> > > void intel_engines_reset_default_submission(struct intel_gt
> > > *gt);
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index 6220b7151bb9..7e2aa7a6bef0 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -1040,6 +1040,25 @@ static bool ring_is_idle(struct
> > > intel_engine_cs *engine)
> > > return idle;
> > > }
> > >
> > > +void intel_engine_flush_submission(struct intel_engine_cs
> > > *engine)
> > > +{
> > > + struct tasklet_struct *t = >execlists.tasklet;
> > > +
> > > + if (__tasklet_is_scheduled(t)) {
> > > + local_bh_disable();
> > > + if (tasklet_trylock(t)) {
> > > + /* Must wait for any GPU reset in progress.
> > > */
> > > + if (__tasklet_is_enabled(t))
> > > + t->func(t->data);
> > > + tasklet_unlock(t);
> > > + }
> > > + local_bh_enable();
> > > + }
> > > +
> > > + /* Otherwise flush the tasklet if it was running on another
> > > cpu
> > > */
> > > + tasklet_unlock_wait(t);
> > > +}
> > > +
> > > /**
> > > * intel_engine_is_idle() - Report if the engine has finished
> > > process all work
> > > * @engine: the intel_engine_cs
> > > @@ -1058,21 +1077,9 @@ bool intel_engine_is_idle(struct
> > > intel_engine_cs *engine)
> > >
> > > /* Waiting to drain ELSP? */
> > > if (execlists_active(>execlists)) {
> > > - struct tasklet_struct *t =
> > > >execlists.tasklet;
> > > -
> > > synchronize_hardirq(engine->i915->drm.pdev->irq);
> > >
> > > - local_bh_disable();
> > > - if (tasklet_trylock(t)) {
> > > - /* Must wait for any GPU reset in progress.
> > > */
> > > - if (__tasklet_is_enabled(t))
> > > - t->func(t->data);
> > > - tasklet_unlock(t);
> > > - }
> > > - local_bh_enable();
> > > -
> > > - /* Otherwise flush the tasklet if it was on another
> > > cpu
> > > */
> > > - tasklet_unlock_wait(t);
> > > + intel_engine_flush_submission(engine);
> > >
> > > if (execlists_active(>execlists))
> > > return false;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > > b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > > index ca606b79fd5e..cbb4069b11e1 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > > @@ -4,6 +4,7 @@
> > > * Copyright © 2019 Intel Corporation
> > > */
> > >
> > > +#include "i915_drv.h" /* for_each_engine() */
> > > #include "i915_request.h"
> > > #include "intel_gt.h"
> > > #include "intel_gt_pm.h"
> > > @@ -19,6 +20,15 @@ static void retire_requests(struct
> > > intel_timeline
> > > *tl)
> > > break;
> > > }
> > >
> > > +static void flush_submission(struct intel_gt *gt)
> > > +{
> > > + struct intel_engine_cs *engine;
> > > + enum intel_engine_id id;
> > > +
> > > + for_each_engine(engine, gt->i915, id)
> > > + intel_engine_flush_submission(engine);
> > > +}
> > > +
> > > long intel_gt_retire_requests_timeout(struct intel_gt *gt, long
> > > timeout)
> > > {
>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Describe structure member in documentation (rev2)
== Series Details == Series: drm/i915: Describe structure member in documentation (rev2) URL : https://patchwork.freedesktop.org/series/67102/ State : success == Summary == CI Bug Log - changes from CI_DRM_7032_full -> Patchwork_14700_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14700_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-skl4/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-skl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@reset-stress: - shard-snb: [PASS][5] -> [FAIL][6] ([fdo#109661]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-snb5/igt@gem_...@reset-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-snb4/igt@gem_...@reset-stress.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +22 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb1/igt@gem_exec_sched...@out-order-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-iclb3/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111764]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-iclb2/igt@i915_pm_...@system-suspend-execbuf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-iclb4/igt@i915_pm_...@system-suspend-execbuf.html * igt@i915_pm_rpm@system-suspend-modeset: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108] / [fdo#107807]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-skl8/igt@i915_pm_...@system-suspend-modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-skl3/igt@i915_pm_...@system-suspend-modeset.html * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-hsw6/igt@kms_b...@extended-modeset-hang-newfb-with-reset-render-b.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-hsw8/igt@kms_b...@extended-modeset-hang-newfb-with-reset-render-b.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-apl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][21] -> [FAIL][22] ([fdo#105363]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-glk9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-glk6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14700/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html *
Re: [Intel-gfx] [v8, 2/4] drm/panel: set display info in panel attach
/snip
> > > > > diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> > > > > index d16158deacdc..f3587a54b8ac 100644
> > > > > --- a/include/drm/drm_panel.h
> > > > > +++ b/include/drm/drm_panel.h
> > > > > @@ -141,6 +141,56 @@ struct drm_panel {
> > > > >*/
> > > > > const struct drm_panel_funcs *funcs;
> > > > >
> > > >
> > > > All these new added members seems dupliated with drm_display_info,
> > > > So I think, can we add a new drm_plane_funcs func:
> > > >
> > > > int (*set_display_info)(struct drm_panel *panel,
> > > > struct drm_display_info *info);
> > >
> > > I don't disagree personally, since I originally wrote it this way, but
> > > 2 maintainers, Daniel Vetter and Thierry Reding, requested that it be
> > > changed. Unless that decision is reversed, I won't be changing this.
> > >
> >
> > Reading back the feedback on v1, I don't think anyone said they were against
> > storing a drm_display_info struct in drm_panel (no one really weighed in on
> > it one way or another). IMO duplicating a bunch of fields feels pretty icky.
>
> Thanks for the review. Should we duplicate the entire struct, or just
> create a sub-struct, say, physical_properties that will be part of
> drm_display_info and drm_panel?
That's a good idea, but I think you can use the entire struct. Everything has
reasonable default values and I think it might be difficult to draw a line in
the sand as to which fields will or won't be useful for panels going forward.
Best for drivers to just treat the info in drm_display_info as best effort and
have good defaults IMO.
Sean
>
> >
> > I think most fields in drm_display_info have pretty reasonable defaults, so
> > I'd
> > recommend just storing a copy in drm_panel. As Thierry suggests, we can
> > populate the dt parts in probe (orientation) and then copy over all or a
> > subset
> > of the struct to connector on attach.
> >
> > Sean
> >
> > > >
> > > > Then in drm_panel_attach(), via this interface the specific panel
> > > > driver can directly set connector->display_info. like
> > > >
> > > >...
> > > >if (panel->funcs && panel->funcs->set_display_info)
> > > > panel->funcs->unprepare(panel, connector->display_info);
> > > >...
> > > >
> > > > Thanks
> > > > James
> > > >
> > > > > + /**
> > > > > + * @width_mm:
> > > > > + *
> > > > > + * Physical width in mm.
> > > > > + */
> > > > > + unsigned int width_mm;
> > > > > +
> > > > > + /**
> > > > > + * @height_mm:
> > > > > + *
> > > > > + * Physical height in mm.
> > > > > + */
> > > > > + unsigned int height_mm;
> > > > > +
> > > > > + /**
> > > > > + * @bpc:
> > > > > + *
> > > > > + * Maximum bits per color channel. Used by HDMI and DP outputs.
> > > > > + */
> > > > > + unsigned int bpc;
> > > > > +
> > > > > + /**
> > > > > + * @orientation
> > > > > + *
> > > > > + * Installation orientation of the panel with respect to the
> > > > > chassis.
> > > > > + */
> > > > > + int orientation;
> > > > > +
> > > > > + /**
> > > > > + * @bus_formats
> > > > > + *
> > > > > + * Pixel data format on the wire.
> > > > > + */
> > > > > + const u32 *bus_formats;
> > > > > +
> > > > > + /**
> > > > > + * @num_bus_formats:
> > > > > + *
> > > > > + * Number of elements pointed to by @bus_formats
> > > > > + */
> > > > > + unsigned int num_bus_formats;
> > > > > +
> > > > > + /**
> > > > > + * @bus_flags:
> > > > > + *
> > > > > + * Additional information (like pixel signal polarity) for the
> > > > > pixel
> > > > > + * data on the bus.
> > > > > + */
> > > > > + u32 bus_flags;
> > > > > +
> > > > > /**
> > > > >* @list:
> > > > >*
> > >
> > > Thanks for the review
> >
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush submission tasklet before waiting/retiring
Quoting Summers, Stuart (2019-10-08 15:52:15)
> On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> > A common bane of ours is arbitrary delays in ksoftirqd processing our
> > submission tasklet. Give the submission tasklet a kick before we wait
> > to
> > avoid those delays eating into a tight timeout.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine.h | 3 +-
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 +
> >
> > drivers/gpu/drm/i915/gt/intel_gt_requests.c | 12
> > 3 files changed, 34 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> > b/drivers/gpu/drm/i915/gt/intel_engine.h
> > index c9e8c8ccbd47..d624752f2a92 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > @@ -407,8 +407,9 @@ static inline void __intel_engine_reset(struct
> > intel_engine_cs *engine,
> > engine->serial++; /* contexts lost */
> > }
> >
> > -bool intel_engine_is_idle(struct intel_engine_cs *engine);
> > bool intel_engines_are_idle(struct intel_gt *gt);
> > +bool intel_engine_is_idle(struct intel_engine_cs *engine);
> > +void intel_engine_flush_submission(struct intel_engine_cs *engine);
> >
> > void intel_engines_reset_default_submission(struct intel_gt *gt);
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 6220b7151bb9..7e2aa7a6bef0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1040,6 +1040,25 @@ static bool ring_is_idle(struct
> > intel_engine_cs *engine)
> > return idle;
> > }
> >
> > +void intel_engine_flush_submission(struct intel_engine_cs *engine)
> > +{
> > + struct tasklet_struct *t = >execlists.tasklet;
> > +
> > + if (__tasklet_is_scheduled(t)) {
> > + local_bh_disable();
> > + if (tasklet_trylock(t)) {
> > + /* Must wait for any GPU reset in progress. */
> > + if (__tasklet_is_enabled(t))
> > + t->func(t->data);
> > + tasklet_unlock(t);
> > + }
> > + local_bh_enable();
> > + }
> > +
> > + /* Otherwise flush the tasklet if it was running on another cpu
> > */
> > + tasklet_unlock_wait(t);
> > +}
> > +
> > /**
> > * intel_engine_is_idle() - Report if the engine has finished
> > process all work
> > * @engine: the intel_engine_cs
> > @@ -1058,21 +1077,9 @@ bool intel_engine_is_idle(struct
> > intel_engine_cs *engine)
> >
> > /* Waiting to drain ELSP? */
> > if (execlists_active(>execlists)) {
> > - struct tasklet_struct *t = >execlists.tasklet;
> > -
> > synchronize_hardirq(engine->i915->drm.pdev->irq);
> >
> > - local_bh_disable();
> > - if (tasklet_trylock(t)) {
> > - /* Must wait for any GPU reset in progress. */
> > - if (__tasklet_is_enabled(t))
> > - t->func(t->data);
> > - tasklet_unlock(t);
> > - }
> > - local_bh_enable();
> > -
> > - /* Otherwise flush the tasklet if it was on another cpu
> > */
> > - tasklet_unlock_wait(t);
> > + intel_engine_flush_submission(engine);
> >
> > if (execlists_active(>execlists))
> > return false;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > index ca606b79fd5e..cbb4069b11e1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > @@ -4,6 +4,7 @@
> > * Copyright © 2019 Intel Corporation
> > */
> >
> > +#include "i915_drv.h" /* for_each_engine() */
> > #include "i915_request.h"
> > #include "intel_gt.h"
> > #include "intel_gt_pm.h"
> > @@ -19,6 +20,15 @@ static void retire_requests(struct intel_timeline
> > *tl)
> > break;
> > }
> >
> > +static void flush_submission(struct intel_gt *gt)
> > +{
> > + struct intel_engine_cs *engine;
> > + enum intel_engine_id id;
> > +
> > + for_each_engine(engine, gt->i915, id)
> > + intel_engine_flush_submission(engine);
> > +}
> > +
> > long intel_gt_retire_requests_timeout(struct intel_gt *gt, long
> > timeout)
> > {
> > struct intel_gt_timelines *timelines = >timelines;
> > @@ -32,6 +42,8 @@ long intel_gt_retire_requests_timeout(struct
> > intel_gt *gt, long timeout)
> > if (unlikely(timeout < 0))
> > timeout = -timeout, interruptible = false;
> >
> > + flush_submission(gt); /* kick the ksoftirqd tasklets */
>
> Won't this add a performance hit if we are doing this across all
> engines? Is there a way we can isolate this a bit more?
One of my earlier thoughts was to use
Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush submission tasklet before waiting/retiring
Quoting Summers, Stuart (2019-10-08 15:52:15)
> On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> > A common bane of ours is arbitrary delays in ksoftirqd processing our
> > submission tasklet. Give the submission tasklet a kick before we wait
> > to
> > avoid those delays eating into a tight timeout.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine.h | 3 +-
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 +
> >
> > drivers/gpu/drm/i915/gt/intel_gt_requests.c | 12
> > 3 files changed, 34 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> > b/drivers/gpu/drm/i915/gt/intel_engine.h
> > index c9e8c8ccbd47..d624752f2a92 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > @@ -407,8 +407,9 @@ static inline void __intel_engine_reset(struct
> > intel_engine_cs *engine,
> > engine->serial++; /* contexts lost */
> > }
> >
> > -bool intel_engine_is_idle(struct intel_engine_cs *engine);
> > bool intel_engines_are_idle(struct intel_gt *gt);
> > +bool intel_engine_is_idle(struct intel_engine_cs *engine);
> > +void intel_engine_flush_submission(struct intel_engine_cs *engine);
> >
> > void intel_engines_reset_default_submission(struct intel_gt *gt);
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 6220b7151bb9..7e2aa7a6bef0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1040,6 +1040,25 @@ static bool ring_is_idle(struct
> > intel_engine_cs *engine)
> > return idle;
> > }
> >
> > +void intel_engine_flush_submission(struct intel_engine_cs *engine)
> > +{
> > + struct tasklet_struct *t = >execlists.tasklet;
> > +
> > + if (__tasklet_is_scheduled(t)) {
> > + local_bh_disable();
> > + if (tasklet_trylock(t)) {
> > + /* Must wait for any GPU reset in progress. */
> > + if (__tasklet_is_enabled(t))
> > + t->func(t->data);
> > + tasklet_unlock(t);
> > + }
> > + local_bh_enable();
> > + }
> > +
> > + /* Otherwise flush the tasklet if it was running on another cpu
> > */
> > + tasklet_unlock_wait(t);
> > +}
> > +
> > /**
> > * intel_engine_is_idle() - Report if the engine has finished
> > process all work
> > * @engine: the intel_engine_cs
> > @@ -1058,21 +1077,9 @@ bool intel_engine_is_idle(struct
> > intel_engine_cs *engine)
> >
> > /* Waiting to drain ELSP? */
> > if (execlists_active(>execlists)) {
> > - struct tasklet_struct *t = >execlists.tasklet;
> > -
> > synchronize_hardirq(engine->i915->drm.pdev->irq);
> >
> > - local_bh_disable();
> > - if (tasklet_trylock(t)) {
> > - /* Must wait for any GPU reset in progress. */
> > - if (__tasklet_is_enabled(t))
> > - t->func(t->data);
> > - tasklet_unlock(t);
> > - }
> > - local_bh_enable();
> > -
> > - /* Otherwise flush the tasklet if it was on another cpu
> > */
> > - tasklet_unlock_wait(t);
> > + intel_engine_flush_submission(engine);
> >
> > if (execlists_active(>execlists))
> > return false;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > index ca606b79fd5e..cbb4069b11e1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > @@ -4,6 +4,7 @@
> > * Copyright © 2019 Intel Corporation
> > */
> >
> > +#include "i915_drv.h" /* for_each_engine() */
> > #include "i915_request.h"
> > #include "intel_gt.h"
> > #include "intel_gt_pm.h"
> > @@ -19,6 +20,15 @@ static void retire_requests(struct intel_timeline
> > *tl)
> > break;
> > }
> >
> > +static void flush_submission(struct intel_gt *gt)
> > +{
> > + struct intel_engine_cs *engine;
> > + enum intel_engine_id id;
> > +
> > + for_each_engine(engine, gt->i915, id)
> > + intel_engine_flush_submission(engine);
> > +}
> > +
> > long intel_gt_retire_requests_timeout(struct intel_gt *gt, long
> > timeout)
> > {
> > struct intel_gt_timelines *timelines = >timelines;
> > @@ -32,6 +42,8 @@ long intel_gt_retire_requests_timeout(struct
> > intel_gt *gt, long timeout)
> > if (unlikely(timeout < 0))
> > timeout = -timeout, interruptible = false;
> >
> > + flush_submission(gt); /* kick the ksoftirqd tasklets */
>
> Won't this add a performance hit if we are doing this across all
> engines? Is there a way we can isolate this a bit more?
It's a global wait, and it is just
Re: [Intel-gfx] [PATCH v8 1/4] drm/panel: Add helper for reading DT rotation
On Mon, Oct 07, 2019 at 03:12:00PM -0700, dbasehore . wrote:
> On Mon, Oct 7, 2019 at 9:38 AM Sean Paul wrote:
> >
> > On Wed, Sep 25, 2019 at 03:58:30PM -0700, Derek Basehore wrote:
> > > This adds a helper function for reading the rotation (panel
> > > orientation) from the device tree.
> > >
> > > Signed-off-by: Derek Basehore
> > > Reviewed-by: Sam Ravnborg
> >
> > The patch LGTM, but I don't see it used anywhere later in the patch? Is
> > there a
> > panel driver incoming?
>
> Yeah, the boe-tv101wum-nl6 panel will use it. It's not in the patch
> currently sent upstream since I don't want to step on their toes, but
> I plan on sending a patch to add it as soon as that is merged.
>
> I could hold back on this patch until that panel driver is merged too.
Yeah, I think it's probably best. I don't anticipate any changes will be
required, but it's always best to review the code end-to-end.
I haven't checked in on that review, but if it's close to landing, you can also
add a patch to this stack that is based on the in-flight patches. That way we
can
get all the review out of the way and then when the panel lands, we can apply
your add-on with the rest of the series.
Sean
> Another alternative is to throw this into the generic drm_panel code,
> but there's no obvious place to put it since DRM seems to leave
> reading the DTS up to the panel drivers themselves.
>
> >
> > Sean
> >
> > > ---
> > > drivers/gpu/drm/drm_panel.c | 43 +
> > > include/drm/drm_panel.h | 9
> > > 2 files changed, 52 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
> > > index 6b0bf42039cf..0909b53b74e6 100644
> > > --- a/drivers/gpu/drm/drm_panel.c
> > > +++ b/drivers/gpu/drm/drm_panel.c
> > > @@ -264,6 +264,49 @@ struct drm_panel *of_drm_find_panel(const struct
> > > device_node *np)
> > > return ERR_PTR(-EPROBE_DEFER);
> > > }
> > > EXPORT_SYMBOL(of_drm_find_panel);
> > > +
> > > +/**
> > > + * of_drm_get_panel_orientation - look up the orientation of the panel
> > > through
> > > + * the "rotation" binding from a device tree node
> > > + * @np: device tree node of the panel
> > > + * @orientation: orientation enum to be filled in
> > > + *
> > > + * Looks up the rotation of a panel in the device tree. The orientation
> > > of the
> > > + * panel is expressed as a property name "rotation" in the device tree.
> > > The
> > > + * rotation in the device tree is counter clockwise.
> > > + *
> > > + * Return: 0 when a valid rotation value (0, 90, 180, or 270) is read or
> > > the
> > > + * rotation property doesn't exist. -EERROR otherwise.
> > > + */
> > > +int of_drm_get_panel_orientation(const struct device_node *np,
> > > + enum drm_panel_orientation *orientation)
> > > +{
> > > + int rotation, ret;
> > > +
> > > + ret = of_property_read_u32(np, "rotation", );
> > > + if (ret == -EINVAL) {
> > > + /* Don't return an error if there's no rotation property. */
> > > + *orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
> > > + return 0;
> > > + }
> > > +
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + if (rotation == 0)
> > > + *orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
> > > + else if (rotation == 90)
> > > + *orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
> > > + else if (rotation == 180)
> > > + *orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
> > > + else if (rotation == 270)
> > > + *orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
> > > + else
> > > + return -EINVAL;
> > > +
> > > + return 0;
> > > +}
> > > +EXPORT_SYMBOL(of_drm_get_panel_orientation);
> > > #endif
> > >
> > > MODULE_AUTHOR("Thierry Reding ");
> > > diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> > > index 624bd15ecfab..d16158deacdc 100644
> > > --- a/include/drm/drm_panel.h
> > > +++ b/include/drm/drm_panel.h
> > > @@ -34,6 +34,8 @@ struct drm_device;
> > > struct drm_panel;
> > > struct display_timing;
> > >
> > > +enum drm_panel_orientation;
> > > +
> > > /**
> > > * struct drm_panel_funcs - perform operations on a given panel
> > > *
> > > @@ -165,11 +167,18 @@ int drm_panel_get_modes(struct drm_panel *panel);
> > >
> > > #if defined(CONFIG_OF) && defined(CONFIG_DRM_PANEL)
> > > struct drm_panel *of_drm_find_panel(const struct device_node *np);
> > > +int of_drm_get_panel_orientation(const struct device_node *np,
> > > + enum drm_panel_orientation *orientation);
> > > #else
> > > static inline struct drm_panel *of_drm_find_panel(const struct
> > > device_node *np)
> > > {
> > > return ERR_PTR(-ENODEV);
> > > }
> > > +static inline int of_drm_get_panel_orientation(const struct device_node
> > > *np,
> > > + enum drm_panel_orientation *orientation)
> > > +{
>
Re: [Intel-gfx] [PATCH] drm/i915/gt: Flush submission tasklet before waiting/retiring
On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> A common bane of ours is arbitrary delays in ksoftirqd processing our
> submission tasklet. Give the submission tasklet a kick before we wait
> to
> avoid those delays eating into a tight timeout.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 3 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 +
>
> drivers/gpu/drm/i915/gt/intel_gt_requests.c | 12
> 3 files changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index c9e8c8ccbd47..d624752f2a92 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -407,8 +407,9 @@ static inline void __intel_engine_reset(struct
> intel_engine_cs *engine,
> engine->serial++; /* contexts lost */
> }
>
> -bool intel_engine_is_idle(struct intel_engine_cs *engine);
> bool intel_engines_are_idle(struct intel_gt *gt);
> +bool intel_engine_is_idle(struct intel_engine_cs *engine);
> +void intel_engine_flush_submission(struct intel_engine_cs *engine);
>
> void intel_engines_reset_default_submission(struct intel_gt *gt);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 6220b7151bb9..7e2aa7a6bef0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1040,6 +1040,25 @@ static bool ring_is_idle(struct
> intel_engine_cs *engine)
> return idle;
> }
>
> +void intel_engine_flush_submission(struct intel_engine_cs *engine)
> +{
> + struct tasklet_struct *t = >execlists.tasklet;
> +
> + if (__tasklet_is_scheduled(t)) {
> + local_bh_disable();
> + if (tasklet_trylock(t)) {
> + /* Must wait for any GPU reset in progress. */
> + if (__tasklet_is_enabled(t))
> + t->func(t->data);
> + tasklet_unlock(t);
> + }
> + local_bh_enable();
> + }
> +
> + /* Otherwise flush the tasklet if it was running on another cpu
> */
> + tasklet_unlock_wait(t);
> +}
> +
> /**
> * intel_engine_is_idle() - Report if the engine has finished
> process all work
> * @engine: the intel_engine_cs
> @@ -1058,21 +1077,9 @@ bool intel_engine_is_idle(struct
> intel_engine_cs *engine)
>
> /* Waiting to drain ELSP? */
> if (execlists_active(>execlists)) {
> - struct tasklet_struct *t = >execlists.tasklet;
> -
> synchronize_hardirq(engine->i915->drm.pdev->irq);
>
> - local_bh_disable();
> - if (tasklet_trylock(t)) {
> - /* Must wait for any GPU reset in progress. */
> - if (__tasklet_is_enabled(t))
> - t->func(t->data);
> - tasklet_unlock(t);
> - }
> - local_bh_enable();
> -
> - /* Otherwise flush the tasklet if it was on another cpu
> */
> - tasklet_unlock_wait(t);
> + intel_engine_flush_submission(engine);
>
> if (execlists_active(>execlists))
> return false;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> index ca606b79fd5e..cbb4069b11e1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> @@ -4,6 +4,7 @@
> * Copyright © 2019 Intel Corporation
> */
>
> +#include "i915_drv.h" /* for_each_engine() */
> #include "i915_request.h"
> #include "intel_gt.h"
> #include "intel_gt_pm.h"
> @@ -19,6 +20,15 @@ static void retire_requests(struct intel_timeline
> *tl)
> break;
> }
>
> +static void flush_submission(struct intel_gt *gt)
> +{
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> +
> + for_each_engine(engine, gt->i915, id)
> + intel_engine_flush_submission(engine);
> +}
> +
> long intel_gt_retire_requests_timeout(struct intel_gt *gt, long
> timeout)
> {
> struct intel_gt_timelines *timelines = >timelines;
> @@ -32,6 +42,8 @@ long intel_gt_retire_requests_timeout(struct
> intel_gt *gt, long timeout)
> if (unlikely(timeout < 0))
> timeout = -timeout, interruptible = false;
>
> + flush_submission(gt); /* kick the ksoftirqd tasklets */
Won't this add a performance hit if we are doing this across all
engines? Is there a way we can isolate this a bit more?
Thanks,
Stuart
> +
> spin_lock_irqsave(>lock, flags);
> list_for_each_entry_safe(tl, tn, >active_list, link)
> {
> if (!mutex_trylock(>mutex)) {
smime.p7s
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[Intel-gfx] [PATCH] drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
Couple up our mock_uncore to know about the fake global device and its
runtime powermanagement.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/mock_engine.c| 1 +
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_uncore.c | 5 -
drivers/gpu/drm/i915/selftests/mock_uncore.h | 3 ++-
4 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index 3d88397c0dbb..747f7c7790eb 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -240,6 +240,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private
*i915,
struct mock_engine *engine;
GEM_BUG_ON(id >= I915_NUM_ENGINES);
+ GEM_BUG_ON(!i915->gt.uncore);
engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL);
if (!engine)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 70a7026db08d..d14c6d8735fe 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -162,7 +162,7 @@ struct drm_i915_private *mock_gem_device(void)
I915_GTT_PAGE_SIZE_64K |
I915_GTT_PAGE_SIZE_2M;
- mock_uncore_init(>uncore);
+ mock_uncore_init(>uncore, i915);
i915_gem_init__mm(i915);
intel_gt_init_early(>gt, i915);
atomic_inc(>gt.wakeref.count); /* disable; no hw support */
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c
b/drivers/gpu/drm/i915/selftests/mock_uncore.c
index 49585f16d4a2..ca57e4008701 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c
@@ -39,8 +39,11 @@ __nop_read(16)
__nop_read(32)
__nop_read(64)
-void mock_uncore_init(struct intel_uncore *uncore)
+void mock_uncore_init(struct intel_uncore *uncore,
+ struct drm_i915_private *i915)
{
+ intel_uncore_init_early(uncore, i915);
+
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop);
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop);
}
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.h
b/drivers/gpu/drm/i915/selftests/mock_uncore.h
index dacb36b5ffcd..8a2cc553f466 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.h
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.h
@@ -25,6 +25,7 @@
#ifndef __MOCK_UNCORE_H
#define __MOCK_UNCORE_H
-void mock_uncore_init(struct intel_uncore *uncore);
+void mock_uncore_init(struct intel_uncore *uncore,
+ struct drm_i915_private *i915);
#endif /* !__MOCK_UNCORE_H */
--
2.23.0
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/perf: drop list of streams
== Series Details == Series: drm/i915/perf: drop list of streams URL : https://patchwork.freedesktop.org/series/67734/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/perf: drop list of streams +drivers/gpu/drm/i915/i915_perf.c:1408:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1464:15: warning: memset with byte count of 16777216 -O:drivers/gpu/drm/i915/i915_perf.c:1408:15: warning: memset with byte count of 16777216 -O:drivers/gpu/drm/i915/i915_perf.c:1467:15: warning: memset with byte count of 16777216 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI] drm/i915/perf: drop list of streams
On 08/10/2019 17:01, Chris Wilson wrote:
From: Lionel Landwerlin
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Thanks, ship it! :)
-Lionel
---
drivers/gpu/drm/i915/i915_perf.c | 16 +---
drivers/gpu/drm/i915/i915_perf_types.h | 6 --
2 files changed, 1 insertion(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e5973809b69a..5a34cad7d824 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1407,9 +1407,6 @@ static void gen7_init_oa_buffer(struct i915_perf_stream
*stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /* Maybe make ->pollin per-stream state if we support multiple
-* concurrent streams in the future.
-*/
stream->pollin = false;
}
@@ -1466,10 +1463,6 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /*
-* Maybe make ->pollin per-stream state if we support multiple
-* concurrent streams in the future.
-*/
stream->pollin = false;
}
@@ -2585,8 +2578,6 @@ static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
if (stream->ops->destroy)
stream->ops->destroy(stream);
- list_del(>link);
-
if (stream->ctx)
i915_gem_context_put(stream->ctx);
@@ -2736,8 +2727,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
goto err_flags;
}
- list_add(>link, >streams);
-
if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
f_flags |= O_CLOEXEC;
if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
@@ -2746,7 +2735,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
stream_fd = anon_inode_getfd("[i915_perf]", , stream, f_flags);
if (stream_fd < 0) {
ret = stream_fd;
- goto err_open;
+ goto err_flags;
}
if (!(param->flags & I915_PERF_FLAG_DISABLED))
@@ -2759,8 +2748,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
return stream_fd;
-err_open:
- list_del(>link);
err_flags:
if (stream->ops->destroy)
stream->ops->destroy(stream);
@@ -3600,7 +3587,6 @@ void i915_perf_init(struct drm_i915_private *i915)
}
if (perf->ops.enable_metric_set) {
- INIT_LIST_HEAD(>streams);
mutex_init(>lock);
oa_sample_rate_hard_limit = 1000 *
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 3c6246064a0b..2d17059d32ee 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -134,11 +134,6 @@ struct i915_perf_stream {
*/
struct intel_gt *gt;
- /**
-* @link: Links the stream into ``_i915_private->streams``
-*/
- struct list_head link;
-
/**
* @wakeref: As we keep the device awake while the perf stream is
* active, we track our runtime pm reference for later release.
@@ -352,7 +347,6 @@ struct i915_perf {
* except exclusive_stream.
*/
struct mutex lock;
- struct list_head streams;
/*
* The stream currently using the OA unit. If accessed
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/perf: drop list of streams
From: Lionel Landwerlin
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 16 +---
drivers/gpu/drm/i915/i915_perf_types.h | 6 --
2 files changed, 1 insertion(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e5973809b69a..5a34cad7d824 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1407,9 +1407,6 @@ static void gen7_init_oa_buffer(struct i915_perf_stream
*stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /* Maybe make ->pollin per-stream state if we support multiple
-* concurrent streams in the future.
-*/
stream->pollin = false;
}
@@ -1466,10 +1463,6 @@ static void gen8_init_oa_buffer(struct i915_perf_stream
*stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /*
-* Maybe make ->pollin per-stream state if we support multiple
-* concurrent streams in the future.
-*/
stream->pollin = false;
}
@@ -2585,8 +2578,6 @@ static void i915_perf_destroy_locked(struct
i915_perf_stream *stream)
if (stream->ops->destroy)
stream->ops->destroy(stream);
- list_del(>link);
-
if (stream->ctx)
i915_gem_context_put(stream->ctx);
@@ -2736,8 +2727,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
goto err_flags;
}
- list_add(>link, >streams);
-
if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
f_flags |= O_CLOEXEC;
if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
@@ -2746,7 +2735,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
stream_fd = anon_inode_getfd("[i915_perf]", , stream, f_flags);
if (stream_fd < 0) {
ret = stream_fd;
- goto err_open;
+ goto err_flags;
}
if (!(param->flags & I915_PERF_FLAG_DISABLED))
@@ -2759,8 +2748,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
return stream_fd;
-err_open:
- list_del(>link);
err_flags:
if (stream->ops->destroy)
stream->ops->destroy(stream);
@@ -3600,7 +3587,6 @@ void i915_perf_init(struct drm_i915_private *i915)
}
if (perf->ops.enable_metric_set) {
- INIT_LIST_HEAD(>streams);
mutex_init(>lock);
oa_sample_rate_hard_limit = 1000 *
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 3c6246064a0b..2d17059d32ee 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -134,11 +134,6 @@ struct i915_perf_stream {
*/
struct intel_gt *gt;
- /**
-* @link: Links the stream into ``_i915_private->streams``
-*/
- struct list_head link;
-
/**
* @wakeref: As we keep the device awake while the perf stream is
* active, we track our runtime pm reference for later release.
@@ -352,7 +347,6 @@ struct i915_perf {
* except exclusive_stream.
*/
struct mutex lock;
- struct list_head streams;
/*
* The stream currently using the OA unit. If accessed
--
2.23.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Assign the engine->uncore shortcut
== Series Details ==
Series: drm/i915/selftests: Assign the engine->uncore shortcut
URL : https://patchwork.freedesktop.org/series/67720/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7030_full -> Patchwork_14699_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14699_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_render_copy@yf-tiled-ccs-to-x-tiled:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-tglb5/igt@gem_render_c...@yf-tiled-ccs-to-x-tiled.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- {shard-tglb}: [PASS][2] -> [INCOMPLETE][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-tglb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-tglb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
* igt@runner@aborted:
- {shard-tglb}: ([FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7],
[FAIL][8]) ([fdo#111851]) -> ([FAIL][9], [FAIL][10], [FAIL][11])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-tglb1/igt@run...@aborted.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-tglb6/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-tglb1/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-tglb3/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-tglb5/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-tglb5/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-tglb4/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-tglb4/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14699_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@busy:
- shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713]) +3
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-iclb6/igt@gem_exec_balan...@busy.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-iclb4/igt@gem_exec_balan...@busy.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) +5 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-iclb6/igt@gem_exec_sched...@in-order-bsd.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-iclb2/igt@gem_exec_sched...@in-order-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109276]) +16 similar
issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html
* igt@gem_exec_suspend@basic-s3:
- shard-skl: [PASS][18] -> [INCOMPLETE][19] ([fdo#104108])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-skl1/igt@gem_exec_susp...@basic-s3.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-skl3/igt@gem_exec_susp...@basic-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][20] -> [DMESG-FAIL][21] ([fdo#108686])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][22] -> [DMESG-WARN][23] ([fdo#111870])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-snb5/igt@gem_userptr_bl...@dmabuf-unsync.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-snb1/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][24] -> [DMESG-WARN][25] ([fdo#111870]) +1
similar issue
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7030/shard-hsw8/igt@gem_userptr_bl...@sync-unmap-after-close.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14699/shard-hsw7/igt@gem_userptr_bl...@sync-unmap-after-close.html
* igt@gem_wait@write-busy-bcs0:
- shard-skl: [PASS][26] -> [DMESG-WARN][27] ([fdo#106107])
[26]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Flush submission tasklet before waiting/retiring
== Series Details ==
Series: drm/i915/gt: Flush submission tasklet before waiting/retiring
URL : https://patchwork.freedesktop.org/series/67732/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7032 -> Patchwork_14701
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/index.html
Known issues
Here are the changes found in Patchwork_14701 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/fi-icl-u3/igt@gem_flink_ba...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/fi-icl-u3/igt@gem_flink_ba...@basic.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][3] -> [DMESG-FAIL][4] ([fdo#111678])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [INCOMPLETE][5] ([fdo#107713]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_render_tiled_blits@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/fi-icl-u3/igt@gem_render_tiled_bl...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/fi-icl-u3/igt@gem_render_tiled_bl...@basic.html
* igt@i915_selftest@live_execlists:
- fi-icl-u3: [DMESG-FAIL][11] ([fdo#111872]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/fi-icl-u3/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/fi-icl-u3/igt@i915_selftest@live_execlists.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) ->
[FAIL][14] ([fdo#111407])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#54]: https://bugs.freedesktop.org/show_bug.cgi?id=54
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
[fdo#111872]: https://bugs.freedesktop.org/show_bug.cgi?id=111872
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7032 -> Patchwork_14701
CI-20190529: 20190529
CI_DRM_7032: ec6a1544198d81f34a367bfb18173e402bbee0fa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5216: 0147a3777dc73ac2138905d0aef33c0fdb3dde5e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14701: 4f81b723a89b7567617a71e2d31a2ffd51edf77d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4f81b723a89b drm/i915/gt: Flush submission tasklet before waiting/retiring
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14701/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/11] drm/i915: keep power domains init/remove calls at the same level
On Mon, 07 Oct 2019, Jani Nikula wrote: > Move intel_power_domains_init_hw() call one level higher, to be on the > same level as all the other intel_power_domains_*() calls in the > probe/remove paths. > > This also moves the power domain hw init earlier in the sequence, along > with the dependent intel_update_rawclk() call. As far as I can tell > there should not be any other dependencies on the initalization that's > now done after these calls (vblank init, bios init, vga register). As Imre told me, the power domain code depends on both the vga and bios inits. Drawing board, here we go again. BR, Jani. > > Cc: Imre Deak > Cc: Ville Syrjala > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 0abfece20c57..16ac5e88e1ec 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -289,11 +289,6 @@ static int i915_driver_modeset_probe(struct > drm_i915_private *i915) > if (ret) > goto out; > > - /* must happen before intel_power_domains_init_hw() on VLV/CHV */ > - intel_update_rawclk(i915); > - > - intel_power_domains_init_hw(i915, false); > - > intel_csr_ucode_init(i915); > > ret = intel_irq_install(i915); > @@ -336,7 +331,6 @@ static int i915_driver_modeset_probe(struct > drm_i915_private *i915) > intel_irq_uninstall(i915); > cleanup_csr: > intel_csr_ucode_fini(i915); > - intel_power_domains_driver_remove(i915); > intel_vga_unregister(i915); > out: > return ret; > @@ -1493,6 +1487,11 @@ int i915_driver_probe(struct pci_dev *pdev, const > struct pci_device_id *ent) > if (ret < 0) > goto out_cleanup_mmio; > > + /* must happen before intel_power_domains_init_hw() on VLV/CHV */ > + intel_update_rawclk(i915); > + > + intel_power_domains_init_hw(i915, false); > + > ret = i915_driver_modeset_probe(i915); > if (ret < 0) > goto out_cleanup_hw; > @@ -1506,6 +1505,7 @@ int i915_driver_probe(struct pci_dev *pdev, const > struct pci_device_id *ent) > return 0; > > out_cleanup_hw: > + intel_power_domains_driver_remove(i915); > i915_driver_hw_remove(i915); > i915_ggtt_driver_release(i915); > out_cleanup_mmio: -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 02/21] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-10-08 12:57:50)
> On 08/10/2019 09:59, Chris Wilson wrote:
> > Quoting Matthew Auld (2019-10-04 18:04:33)
> >> +int
> >> +i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
> >> +{
> >> + struct intel_memory_region *mem = obj->mm.region;
> >> + struct list_head *blocks = >mm.blocks;
> >> + unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
> >> + resource_size_t size = obj->base.size;
> >> + resource_size_t prev_end;
> >> + struct i915_buddy_block *block;
> >> + struct sg_table *st;
> >> + struct scatterlist *sg;
> >> + unsigned int sg_page_sizes;
> >> + unsigned long i;
> >> + int ret;
> >> +
> >> + st = kmalloc(sizeof(*st), GFP_KERNEL);
> >> + if (!st)
> >> + return -ENOMEM;
> >> +
> >> + if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size),
> >> GFP_KERNEL)) {
> >> + kfree(st);
> >> + return -ENOMEM;
> >> + }
> >> +
> >> + ret = __intel_memory_region_get_pages_buddy(mem, size, flags,
> >> blocks);
> >> + if (ret)
> >> + goto err_free_sg;
> >> +
> >> + GEM_BUG_ON(list_empty(blocks));
> >> +
> >> + sg = st->sgl;
> >> + st->nents = 0;
> >> + sg_page_sizes = 0;
> >> + i = 0;
> >> +
> >> + list_for_each_entry(block, blocks, link) {
> >> + u64 block_size, offset;
> >> +
> >> + block_size = i915_buddy_block_size(>mm, block);
> >> + offset = i915_buddy_block_offset(block);
> >> +
> >> + GEM_BUG_ON(overflows_type(block_size, sg->length));
> >> +
> >> + if (!i || offset != prev_end ||
> >> + add_overflows_t(typeof(sg->length), sg->length,
> >> block_size)) {
> >> + if (i) {
> >
> > i is only being here to detect the start.
> > prev_end = (resource_size_t)-1;
> > Then I don't have to worry about i overflowing, although that seems
> > harmless, and as ridiculous as that may be.
> >
> >> + sg_page_sizes |= sg->length;
> >> + sg = __sg_next(sg);
> >> + }
> >> +
> >> + sg_dma_address(sg) = mem->region.start + offset;
> >> + sg_dma_len(sg) = block_size;
> >> +
> >> + sg->length = block_size;
> >> +
> >> + st->nents++;
> >> + } else {
> >> + sg->length += block_size;
> >> + sg_dma_len(sg) += block_size;
> >> + }
> >> +
> >> + prev_end = offset + block_size;
> >> + i++;
> >> + };
> >> +
> >> + sg_page_sizes |= sg->length;
> >> + sg_mark_end(sg);
> >> + i915_sg_trim(st);
> >> +
> >> + __i915_gem_object_set_pages(obj, st, sg_page_sizes);
> >> +
> >> + return 0;
> >> +
> >> +err_free_sg:
> >> + sg_free_table(st);
> >> + kfree(st);
> >> + return ret;
> >> +}
> >
> >> +struct drm_i915_gem_object *
> >> +i915_gem_object_create_region(struct intel_memory_region *mem,
> >> + resource_size_t size,
> >> + unsigned int flags)
> >> +{
> >> + struct drm_i915_gem_object *obj;
> >> +
> >> + if (!mem)
> >> + return ERR_PTR(-ENODEV);
> >> +
> >> + size = round_up(size, mem->min_page_size);
> >> +
> >> + GEM_BUG_ON(!size);
> >> + GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
> >> +
> >
> > Put the FIXME here from the start
> >
> >> + if (size >> PAGE_SHIFT > INT_MAX)
> >> + return ERR_PTR(-E2BIG);
> >> +
> >> + if (overflows_type(size, obj->base.size))
> >> + return ERR_PTR(-E2BIG);
> >> +
> >> + return mem->ops->create_object(mem, size, flags);
> >> +}
> >
> > I'm happy with this. But I would like a discussion on why
> > resource_size_t was chosen and for that rationale to be captured in the
> > code comments. At the end of the day, we need to bump obj->base.size to
> > suit.
>
> No good reason, I guess it just stems from using "struct resource
> region". Maybe for the object_create interface we should just use u64?
resource_size_t is definitely a better starting point than size_t, and
afaik is the preferred type for this physical usage, even when
dma_addr_t conflicts. But that just feels strange, and I couldn't find
any definitive guide. So writing down why we chose the type will help
the inevitable later discussions.
> On that topic should we also stop using "struct resource" here, since
> that's starting to get confusing, maybe use u64 there also?
Well, I'm still looking at struct resource and thinking/hoping it may
lead to us reusing more shared lib/ routines. So I'm ambivalent here. :)
My core objective here is supporting [in thought experiments at least]
4+GiB local memory on 32b platforms. To pull it off
Re: [Intel-gfx] [PATCH v3 02/21] drm/i915: introduce intel_memory_region
On 08/10/2019 09:59, Chris Wilson wrote:
Quoting Matthew Auld (2019-10-04 18:04:33)
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = >mm.blocks;
+ unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
+ resource_size_t size = obj->base.size;
+ resource_size_t prev_end;
+ struct i915_buddy_block *block;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_page_sizes;
+ unsigned long i;
+ int ret;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size), GFP_KERNEL)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
+ if (ret)
+ goto err_free_sg;
+
+ GEM_BUG_ON(list_empty(blocks));
+
+ sg = st->sgl;
+ st->nents = 0;
+ sg_page_sizes = 0;
+ i = 0;
+
+ list_for_each_entry(block, blocks, link) {
+ u64 block_size, offset;
+
+ block_size = i915_buddy_block_size(>mm, block);
+ offset = i915_buddy_block_offset(block);
+
+ GEM_BUG_ON(overflows_type(block_size, sg->length));
+
+ if (!i || offset != prev_end ||
+ add_overflows_t(typeof(sg->length), sg->length,
block_size)) {
+ if (i) {
i is only being here to detect the start.
prev_end = (resource_size_t)-1;
Then I don't have to worry about i overflowing, although that seems
harmless, and as ridiculous as that may be.
+ sg_page_sizes |= sg->length;
+ sg = __sg_next(sg);
+ }
+
+ sg_dma_address(sg) = mem->region.start + offset;
+ sg_dma_len(sg) = block_size;
+
+ sg->length = block_size;
+
+ st->nents++;
+ } else {
+ sg->length += block_size;
+ sg_dma_len(sg) += block_size;
+ }
+
+ prev_end = offset + block_size;
+ i++;
+ };
+
+ sg_page_sizes |= sg->length;
+ sg_mark_end(sg);
+ i915_sg_trim(st);
+
+ __i915_gem_object_set_pages(obj, st, sg_page_sizes);
+
+ return 0;
+
+err_free_sg:
+ sg_free_table(st);
+ kfree(st);
+ return ret;
+}
+struct drm_i915_gem_object *
+i915_gem_object_create_region(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
+{
+ struct drm_i915_gem_object *obj;
+
+ if (!mem)
+ return ERR_PTR(-ENODEV);
+
+ size = round_up(size, mem->min_page_size);
+
+ GEM_BUG_ON(!size);
+ GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
+
Put the FIXME here from the start
+ if (size >> PAGE_SHIFT > INT_MAX)
+ return ERR_PTR(-E2BIG);
+
+ if (overflows_type(size, obj->base.size))
+ return ERR_PTR(-E2BIG);
+
+ return mem->ops->create_object(mem, size, flags);
+}
I'm happy with this. But I would like a discussion on why
resource_size_t was chosen and for that rationale to be captured in the
code comments. At the end of the day, we need to bump obj->base.size to
suit.
No good reason, I guess it just stems from using "struct resource
region". Maybe for the object_create interface we should just use u64?
On that topic should we also stop using "struct resource" here, since
that's starting to get confusing, maybe use u64 there also?
-Chris
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Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Move SAGV block time to dev_priv
On Fri, Oct 04, 2019 at 03:14:48PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, move the variable to dev_priv, and extract the
> setting to an initial setup function. While we're at it, update the if
> ladder to follow the new gen -> old gen order preference, and warn on
> any non-specified gen.
>
> v2: Shorten the function name (Ville), return directly (Ville), move
> sagv_block_time_us value to dev_priv (Ville)
>
> v3: Change sagv_block_time_us to u32 (Lucas), Change fallback value to
> -1 (Lucas), use intel_has_sagv for setup check rather than hand-rolling
> (Lucas)
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Cc: Lucas De Marchi
> Signed-off-by: James Ausmus
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 33 -
> 2 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cde4c7fb5570..1d9a9e827261 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1560,6 +1560,8 @@ struct drm_i915_private {
> I915_SAGV_NOT_CONTROLLED
> } sagv_status;
>
> + u32 sagv_block_time_us;
> +
u32 seems a bit excessive. Although the pcode command doesn't document
any upper bound so maybe u32 is really the correct choice here. And we'd
need to put it somewhere else to avoid the hole anyway.
Series is
Reviewed-by: Ville Syrjälä
> struct {
> /*
>* Raw watermark latency values:
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bfcf03ab5245..0ffcafe97216 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> }
>
> +static void
> +skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> +{
> + if (IS_GEN(dev_priv, 11)) {
> + dev_priv->sagv_block_time_us = 10;
> + return;
> + } else if (IS_GEN(dev_priv, 10)) {
> + dev_priv->sagv_block_time_us = 20;
> + return;
> + } else if (IS_GEN(dev_priv, 9)) {
> + dev_priv->sagv_block_time_us = 30;
> + return;
> + } else {
> + MISSING_CASE(INTEL_GEN(dev_priv));
> + }
> +
> + /* Default to an unusable block time */
> + dev_priv->sagv_block_time_us = -1;
> +}
> +
> /*
> * SAGV dynamically adjusts the system agent voltage and clock frequencies
> * depending on power and performance requirements. The display engine access
> @@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> struct intel_crtc_state *crtc_state;
> enum pipe pipe;
> int level, latency;
> - int sagv_block_time_us;
>
> if (!intel_has_sagv(dev_priv))
> return false;
>
> - if (IS_GEN(dev_priv, 9))
> - sagv_block_time_us = 30;
> - else if (IS_GEN(dev_priv, 10))
> - sagv_block_time_us = 20;
> - else
> - sagv_block_time_us = 10;
> -
> /*
>* If there are no active CRTCs, no additional checks need be performed
>*/
> @@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
>* incur memory latencies higher than sagv_block_time_us we
>* can't enable SAGV.
>*/
> - if (latency < sagv_block_time_us)
> + if (latency < dev_priv->sagv_block_time_us)
> return false;
> }
>
> @@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> else if (IS_GEN(dev_priv, 5))
> i915_ironlake_get_mem_freq(dev_priv);
>
> + if (intel_has_sagv(dev_priv))
> + skl_setup_sagv_block_time(dev_priv);
> +
> /* For FIFO watermark updates */
> if (INTEL_GEN(dev_priv) >= 9) {
> skl_setup_wm_latency(dev_priv);
> --
> 2.22.1
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH i-g-t] i915/gem_eio: Reduce amount of incidental work after the delayed hang
Since we time how long it takes for the waiter to be woken upon
injecting the hang, we want to avoid as much distractions as possible
along the critical path.
Signed-off-by: Chris Wilson
---
tests/i915/gem_eio.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index 892f3657c..aa73b4deb 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -27,6 +27,7 @@
*
*/
+#include
#include
#include
#include
@@ -223,16 +224,20 @@ struct hang_ctx {
static void hang_handler(union sigval arg)
{
struct hang_ctx *ctx = arg.sival_ptr;
+ struct timespec *ts = ctx->ts;
+ int dir = ctx->debugfs;
igt_debug("hang delay = %.2fus\n",
igt_nsec_elapsed(>delay) / 1000.0);
-
- igt_nsec_elapsed(ctx->ts);
- igt_assert(igt_sysfs_set(ctx->debugfs, "i915_wedged", "-1"));
-
igt_assert_eq(timer_delete(ctx->timer), 0);
- close(ctx->debugfs);
free(ctx);
+
+ igt_nsec_elapsed(ts);
+ igt_assert(igt_sysfs_set(dir, "i915_wedged", "-1"));
+ /* -> wake up gem_sync() in check_wait() */
+
+ sched_yield();
+ close(dir);
}
static void hang_after(int fd, unsigned int us, struct timespec *ts)
--
2.23.0
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