[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add feature flag for platforms with DRAM info
== Series Details ==
Series: drm/i915: Add feature flag for platforms with DRAM info
URL : https://patchwork.freedesktop.org/series/67801/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7045_full -> Patchwork_14732_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14732_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@blocking-wf_vblank:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-tglb1/igt@kms_flip@blocking-wf_vblank.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-tglb2/igt@kms_flip@blocking-wf_vblank.html
Known issues
Here are the changes found in Patchwork_14732_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_blt@dumb-buf-max:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-apl2/igt@gem_exec_...@dumb-buf-max.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-apl4/igt@gem_exec_...@dumb-buf-max.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +12 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-iclb6/igt@gem_exec_sched...@independent-bsd2.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +2 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][9] -> [INCOMPLETE][10] ([fdo#103359] /
[fdo#108686] / [k.org#198133])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-glk8/igt@gem_tiled_swapp...@non-threaded.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-snb4/igt@gem_userptr_bl...@sync-unmap-cycles.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-snb1/igt@gem_userptr_bl...@sync-unmap-cycles.html
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-hsw4/igt@gem_userptr_bl...@sync-unmap-cycles.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-hsw1/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([fdo#105763] /
[fdo#106538])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-glk6/igt@i915_pm_...@modeset-stress-extra-wait.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-glk8/igt@i915_pm_...@modeset-stress-extra-wait.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +3
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-apl8/igt@i915_susp...@fence-restore-tiled2untiled.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#110741])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) +3 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/shard-snb2/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/shard-snb2/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#105363])
[23]:
Re: [Intel-gfx] [PATCH V2 6/8] mdev: introduce virtio device and its device ops
On 2019/10/1 上午5:36, Alex Williamson wrote:
On Fri, 27 Sep 2019 16:25:13 +
Parav Pandit wrote:
Hi Alex,
-Original Message-
From: Alex Williamson
Sent: Tuesday, September 24, 2019 6:07 PM
To: Jason Wang
Cc: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org;
kwankh...@nvidia.com; m...@redhat.com; tiwei@intel.com;
virtualizat...@lists.linux-foundation.org; net...@vger.kernel.org;
coh...@redhat.com; maxime.coque...@redhat.com;
cunming.li...@intel.com; zhihong.w...@intel.com;
rob.mil...@broadcom.com; xiao.w.w...@intel.com;
haotian.w...@sifive.com; zhen...@linux.intel.com; zhi.a.w...@intel.com;
jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com;
rodrigo.v...@intel.com; airl...@linux.ie; dan...@ffwll.ch;
far...@linux.ibm.com; pa...@linux.ibm.com; seb...@linux.ibm.com;
ober...@linux.ibm.com; heiko.carst...@de.ibm.com; g...@linux.ibm.com;
borntrae...@de.ibm.com; akrow...@linux.ibm.com; fre...@linux.ibm.com;
lingshan@intel.com; Ido Shamay ;
epere...@redhat.com; l...@redhat.com; Parav Pandit
; christophe.de.dinec...@gmail.com;
kevin.t...@intel.com
Subject: Re: [PATCH V2 6/8] mdev: introduce virtio device and its device ops
On Tue, 24 Sep 2019 21:53:30 +0800
Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
include/linux/mdev.h| 2 +
include/linux/virtio_mdev.h | 145
2 files changed, 147 insertions(+)
create mode 100644 include/linux/virtio_mdev.h
diff --git a/include/linux/mdev.h b/include/linux/mdev.h index
3414307311f1..73ac27b3b868 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -126,6 +126,8 @@ struct mdev_device *mdev_from_dev(struct device
*dev);
enum {
MDEV_ID_VFIO = 1,
+ MDEV_ID_VIRTIO = 2,
+ MDEV_ID_VHOST = 3,
MDEV_ID_VHOST isn't used yet here. Also, given the strong interdependence
between the class_id and the ops structure, we might wand to define them in
the same place. Thanks,
When mlx5_core creates mdevs (parent->ops->create() and it wants to
bind to mlx5 mdev driver (which does mdev_register_driver()), mlx5
core driver will publish MDEV_ID_MLX5_NET defined in central place as
include/linux/mdev.h without any ops structure. Because such ops are
not relevant. It uses usual, standard ops probe() remove() on the
mdev (similar to a regular PCI device). So for VHOST case ops may be
closely related to ID, but not for other type of ID.
Just want to make sure, that scope of ID covers this case.
AIUI, these device-ops are primarily meant to have 1:N multiplexing of
the mdev bus driver. One mdev bus driver supports N vendor drivers via
a common "protocol" defined by this structure. vfio-mdev supports
GVT-g, GRID, and several sample drivers. I think Jason and Tiwei are
attempting something similar if we have multiple vendors that may
provide virtio/vhost parent drivers.
Exactly.
If you have a 1:1 model with
mlx5 where you're not trying to abstract a common channel between the
mdev bus driver and the mdev vendor driver, then I suppose you might
not use the device-ops capabilities of the mdev-core.
Yes, current proposed API allows NULL to be passed as device ops.
Thanks
Did I interpret
the question correctly? I think that's probably fine, mdev-core
shouldn't have any dependencies on the device-ops and we shouldn't
really be dictating the bus/vendor link through mdev. Thanks,
Alex
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/execlists: Protect peeking at execlists->active (rev4)
== Series Details == Series: series starting with [1/2] drm/i915/execlists: Protect peeking at execlists->active (rev4) URL : https://patchwork.freedesktop.org/series/67782/ State : success == Summary == CI Bug Log - changes from CI_DRM_7044_full -> Patchwork_14731_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14731_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [fdo#108686] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-glk8/igt@gem_tiled_swapp...@non-threaded.html - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540] / [fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-hsw5/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-hsw5/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-snb5/igt@gem_userptr_bl...@dmabuf-sync.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-apl6/igt@gem_workarou...@suspend-resume-context.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-apl7/igt@gem_workarou...@suspend-resume-context.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#103232]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-256x256-offscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-256x256-offscreen.html * igt@kms_flip@2x-flip-vs-suspend: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-hsw7/igt@kms_f...@2x-flip-vs-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-apl: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-apl7/igt@kms_f...@flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-apl2/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/vbt: Handle generic DTD block
== Series Details ==
Series: drm/i915/vbt: Handle generic DTD block
URL : https://patchwork.freedesktop.org/series/67811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14741
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/index.html
Known issues
Here are the changes found in Patchwork_14741 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_m...@basic-small-bo.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-icl-u3/igt@gem_m...@basic-small-bo.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109483])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_exec_suspend@basic:
- {fi-tgl-u2}:[INCOMPLETE][5] ([fdo#111850]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-tgl-u2/igt@gem_exec_susp...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-tgl-u2/igt@gem_exec_susp...@basic.html
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713] / [fdo#108840]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-guc/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-icl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_hugepages:
- fi-elk-e7500: [INCOMPLETE][11] ([fdo#103989]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [INCOMPLETE][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) ->
[FAIL][16] ([fdo#111407])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
Participating hosts (53 -> 46)
--
Additional (1): fi-pnv-d510
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7046 -> Patchwork_14741
CI-20190529: 20190529
CI_DRM_7046: 136f98967ad06da28fd795aa83be314c7b641c49 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14741: 4081e8320e9caea4af807b3c0c904b8e175a1f4d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4081e8320e9c drm/i915/vbt: Handle generic DTD block
== Logs ==
For more details see:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/vbt: Handle generic DTD block
== Series Details ==
Series: drm/i915/vbt: Handle generic DTD block
URL : https://patchwork.freedesktop.org/series/67811/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4081e8320e9c drm/i915/vbt: Handle generic DTD block
-:46: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#46: FILE: drivers/gpu/drm/i915/display/intel_bios.c:229:
+ return NULL;
+ } else {
-:84: CHECK:LINE_SPACING: Please don't use multiple blank lines
#84: FILE: drivers/gpu/drm/i915/display/intel_bios.c:267:
+
+
-:183: CHECK:LINE_SPACING: Please don't use multiple blank lines
#183: FILE: drivers/gpu/drm/i915/display/intel_vbt_defs.h:842:
+
+
total: 0 errors, 1 warnings, 2 checks, 156 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Add microcontrollers documentation section
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Add microcontrollers
documentation section
URL : https://patchwork.freedesktop.org/series/67810/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14740
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/index.html
Known issues
Here are the changes found in Patchwork_14740 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_m...@basic-small-bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-icl-u3/igt@gem_m...@basic-small-bo.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109483])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_exec_suspend@basic:
- {fi-tgl-u2}:[INCOMPLETE][7] ([fdo#111850]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-tgl-u2/igt@gem_exec_susp...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-tgl-u2/igt@gem_exec_susp...@basic.html
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713] / [fdo#108840]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-guc/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-icl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_hugepages:
- fi-elk-e7500: [INCOMPLETE][13] ([fdo#103989]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [INCOMPLETE][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111045] / [fdo#111096]) ->
[FAIL][18] ([fdo#111407])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
Participating hosts (53 -> 46)
--
Additional (1): fi-pnv-d510
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7046 -> Patchwork_14740
CI-20190529: 20190529
CI_DRM_7046: 136f98967ad06da28fd795aa83be314c7b641c49 @
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: the BCS engine supports relative MMIO
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: the BCS engine supports
relative MMIO
URL : https://patchwork.freedesktop.org/series/67809/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14739
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/index.html
Known issues
Here are the changes found in Patchwork_14739 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_exec_suspend@basic:
- {fi-tgl-u2}:[INCOMPLETE][5] ([fdo#111850]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-tgl-u2/igt@gem_exec_susp...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-tgl-u2/igt@gem_exec_susp...@basic.html
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713] / [fdo#108840]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-guc/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-icl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_hugepages:
- fi-elk-e7500: [INCOMPLETE][11] ([fdo#103989]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [INCOMPLETE][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
Participating hosts (53 -> 47)
--
Additional (1): fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7046 -> Patchwork_14739
CI-20190529: 20190529
CI_DRM_7046: 136f98967ad06da28fd795aa83be314c7b641c49 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14739: 8c65f9a90680ed75a3a32a7d74b2118d22d06148 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8c65f9a90680 drm/i915/tgl: simplify the lrc register list for !RCS
f473ce3ccdf9 drm/i915/tgl: the BCS engine supports relative MMIO
== Logs ==
For more details see:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp-mst: Drop connection_mutex check
== Series Details ==
Series: drm/dp-mst: Drop connection_mutex check
URL : https://patchwork.freedesktop.org/series/67807/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14738
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/index.html
Known issues
Here are the changes found in Patchwork_14738 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([fdo#108511])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_coherency:
- fi-skl-lmem:[PASS][3] -> [TIMEOUT][4] ([fdo#111944])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-skl-lmem/igt@i915_selftest@live_coherency.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/fi-skl-lmem/igt@i915_selftest@live_coherency.html
Possible fixes
* igt@gem_exec_suspend@basic:
- {fi-tgl-u2}:[INCOMPLETE][5] ([fdo#111850]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-tgl-u2/igt@gem_exec_susp...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/fi-tgl-u2/igt@gem_exec_susp...@basic.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713] / [fdo#108840]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-guc/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/fi-icl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_hugepages:
- fi-elk-e7500: [INCOMPLETE][9] ([fdo#103989]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) ->
[FAIL][14] ([fdo#111407])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7046 -> Patchwork_14738
CI-20190529: 20190529
CI_DRM_7046: 136f98967ad06da28fd795aa83be314c7b641c49 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14738: 1d7c57f40bb1d99ebe33a1e8124cd857ca49e4b0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1d7c57f40bb1 drm/dp-mst: Drop connection_mutex check
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp-mst: Drop connection_mutex check
== Series Details == Series: drm/dp-mst: Drop connection_mutex check URL : https://patchwork.freedesktop.org/series/67807/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/dp-mst: Drop connection_mutex check - + ^~~ +drivers/gpu/drm/drm_dp_mst_topology.c:4187:21: warning: unused variable ‘dev’ [-Wunused-variable] +drivers/gpu/drm/drm_dp_mst_topology.c: In function ‘drm_atomic_get_mst_topology_state’: + struct drm_device *dev = mgr->dev; ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dp-mst: Drop connection_mutex check
== Series Details ==
Series: drm/dp-mst: Drop connection_mutex check
URL : https://patchwork.freedesktop.org/series/67807/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1d7c57f40bb1 drm/dp-mst: Drop connection_mutex check
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit b962a12050a3 ("drm/atomic:
integrate modeset lock with private objects")'
#8:
commit b962a12050a387e4bbf3a48745afe1d29d396b0d
-:33: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 1 errors, 1 warnings, 0 checks, 7 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/vbt: Handle generic DTD block
VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the
old LFP panel mode data in block 42. Let's start parsing this block to
fill in the panel fixed mode on devices with a >=229 VBT.
Bspec: 54751
Bspec: 20148
Signed-off-by: Matt Roper
---
I don't think we've encountered any devices that actually have a >=229
VBT yet, so this is just written to the spec and untested at the moment.
drivers/gpu/drm/i915/display/intel_bios.c | 84 ++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 32 +++
2 files changed, 113 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 9628b485b179..113911f050ee 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -202,6 +202,69 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
+static struct drm_display_mode *
+parse_generic_dtd(struct drm_i915_private *dev_priv,
+ const struct bdb_generic_dtd *generic_dtd)
+{
+ const struct bdb_generic_dtd_entry *dtd;
+ struct drm_display_mode *panel_fixed_mode;
+ int num_dtd;
+
+ if (generic_dtd->gdtd_size < sizeof(struct bdb_generic_dtd_entry)) {
+ DRM_ERROR("GDTD size %u is too small.\n",
+ generic_dtd->gdtd_size);
+ return NULL;
+ } else if (generic_dtd->gdtd_size !=
+ sizeof(struct bdb_generic_dtd_entry)) {
+ DRM_ERROR("Unexpected GDTD size %u\n", generic_dtd->gdtd_size);
+ /* DTD has unknown fields, but keep going */
+ }
+
+ num_dtd = (get_blocksize(generic_dtd) - sizeof(struct bdb_generic_dtd))
/
+ generic_dtd->gdtd_size;
+ if (dev_priv->vbt.panel_type > num_dtd) {
+ DRM_ERROR("Panel type %d not found in table of %d DTD's\n",
+ dev_priv->vbt.panel_type, num_dtd);
+ return NULL;
+ } else {
+ dtd = _dtd->dtd[dev_priv->vbt.panel_type];
+ }
+
+ panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
+ if (!panel_fixed_mode)
+ return NULL;
+
+ panel_fixed_mode->hdisplay = dtd->hactive;
+ panel_fixed_mode->hsync_start =
+ panel_fixed_mode->hdisplay + dtd->hfront_porch;
+ panel_fixed_mode->hsync_end =
+ panel_fixed_mode->hsync_start + dtd->hsync;
+ panel_fixed_mode->htotal = panel_fixed_mode->hsync_end;
+
+ panel_fixed_mode->vdisplay = dtd->vactive;
+ panel_fixed_mode->vsync_start =
+ panel_fixed_mode->vdisplay + dtd->vfront_porch;
+ panel_fixed_mode->vsync_end =
+ panel_fixed_mode->vsync_start + dtd->vsync;
+ panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end;
+
+ panel_fixed_mode->clock = dtd->pixel_clock;
+ panel_fixed_mode->width_mm = dtd->width_mm;
+ panel_fixed_mode->height_mm = dtd->height_mm;
+
+ panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
+ drm_mode_set_name(panel_fixed_mode);
+
+ /*
+* FIXME: We probably need to set FLAG_[P/N][H/V]SYNC according to the
+* value in dtd->[h/v]sync_polarity, but the bspec doesn't tell us how
+* to actually interpret those bits yet.
+*/
+
+ return panel_fixed_mode;
+}
+
+
/* Try to find integrated panel data */
static void
parse_lfp_panel_data(struct drm_i915_private *dev_priv,
@@ -210,6 +273,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
const struct bdb_lvds_options *lvds_options;
const struct bdb_lvds_lfp_data *lvds_lfp_data;
const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
+ const struct bdb_generic_dtd *generic_dtd;
const struct lvds_dvo_timing *panel_dvo_timing;
const struct lvds_fp_timing *fp_timing;
struct drm_display_mode *panel_fixed_mode;
@@ -262,6 +326,18 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
break;
}
+ if (bdb->version >= 229) {
+ generic_dtd = find_section(bdb, BDB_GENERIC_DTD);
+ if (!generic_dtd)
+ return;
+
+ panel_fixed_mode = parse_generic_dtd(dev_priv, generic_dtd);
+ if (!ret)
+ return;
+
+ goto skip_legacy_lfp;
+ }
+
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
return;
@@ -282,9 +358,6 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
- DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
- drm_mode_debug_printmodeline(panel_fixed_mode);
-
fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
lvds_lfp_data_ptrs,
[Intel-gfx] [PATCH v2 1/3] drm/i915: Add microcontrollers documentation section
To better organize the information, add a microcontrollers section and move/link the GuC, HuC and DMC documentation under it. Also add a small intro. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Acked-by: Anna Karas Reviewed-by: Martin Peres --- Documentation/gpu/i915.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 465779670fd4..f1bae7867045 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -415,6 +415,15 @@ Object Tiling IOCTLs .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c :doc: buffer object tiling +Microcontrollers + + +Starting from gen9, three microcontrollers are available on the HW: the +graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the +display microcontroller (DMC). The driver is responsible for loading the +firmwares on the microcontrollers; the GuC and HuC firmwares are transferred +to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. + WOPCM - @@ -454,6 +463,15 @@ GuC Address Space .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c :doc: GuC Address Space +HuC +--- +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c + :doc: HuC Firmware + +DMC +--- +See `CSR firmware support for DMC`_ + Tracing === -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/3] drm/i915/guc: improve documentation
Add a short description of what we expect from GuC and some minor
improvements to existing documentation. Also remove a comment about a
difference between GuC and HuC that is not true anymore.
v2: add that the GuC is not mandatory (Martin)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: Martin Peres
Acked-by: Anna Karas
---
Documentation/gpu/i915.rst| 22 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 30 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 3 --
4 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index f1bae7867045..357e9dfa7de1 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -436,12 +436,24 @@ WOPCM Layout
GuC
---
-Firmware Layout
-~~~
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+ :doc: GuC
+
+GuC Firmware Layout
+~~~
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
:doc: Firmware Layout
+GuC Memory Management
+~
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+ :doc: GuC Memory Management
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+ :functions: intel_guc_allocate_vma
+
+
GuC-specific firmware loader
@@ -457,12 +469,6 @@ GuC-based command submission
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
:internal:
-GuC Address Space
-~
-
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
- :doc: GuC Address Space
-
HuC
---
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 249c747e9756..ce97600790c2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -9,6 +9,26 @@
#include "intel_guc_submission.h"
#include "i915_drv.h"
+/**
+ * DOC: GuC
+ *
+ * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC
is
+ * designed to offload some of the functionality usually performed by the host
+ * driver; currently the main operations it can take care of are:
+ *
+ * - Authentication of the HuC, which is required to fully enable HuC usage.
+ * - Low latency graphics context scheduling (a.k.a. GuC submission).
+ * - GT Power management.
+ *
+ * The enable_guc module parameter can be used to select which of those
+ * operations to enable within GuC. Note that not all the operations are
+ * supported on all gen9+ platforms.
+ * Enabling the GuC is not mandatory and therefore the firmware is only loaded
+ * if at least one of the operations is selected. However, not loading the GuC
+ * might result in the loss of some features that do require the GuC (currently
+ * just the HuC, but more are expected to land in the future).
+ */
+
static void gen8_guc_raise_irq(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -548,9 +568,15 @@ int intel_guc_resume(struct intel_guc *guc)
}
/**
- * DOC: GuC Address Space
+ * DOC: GuC Memory Management
*
- * The layout of GuC address space is shown below:
+ * GuC can't allocate any memory for its own usage, so all the allocations must
+ * be handled by the host driver. GuC accesses the memory via the GGTT, with
the
+ * exception of the top and bottom parts of the 4GB address space, which are
+ * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
+ * or other parts of the HW. The driver must take care not to place objects
that
+ * the GuC is going to access in these reserved ranges. The layout of the GuC
+ * address space is shown below:
*
* ::
*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..849a44add424 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -29,6 +29,12 @@ enum {
/**
* DOC: GuC-based command submission
*
+ * IMPORTANT NOTE: GuC submission is currently not supported in i915. The GuC
+ * firmware is moving to an updated submission interface and we plan to
+ * turn submission back on when that lands. The below documentation (and
related
+ * code) matches the old submission model and will be updated as part of the
+ * upgrade to the new flow.
+ *
* GuC client:
* A intel_guc_client refers to a submission path through GuC. Currently, there
* is only one client, which is charged with all submissions to the GuC. This
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
index f8f6c91a0df6..029214cdedd5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -39,9 +39,6 @@
* 3. Length info of each component can be found
[Intel-gfx] [PATCH v2 3/3] drm/i915/huc: improve documentation
Better explain the usage of the microcontroller and what i915 is
responsible of. While at it, fix the documentation for the auth
function, which doesn't do any pinning anymore.
v2: add a comment on HuC being optional and descrive how HuC accesses
memory (Martin)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Martin Peres
Acked-by: Anna Karas
---
Documentation/gpu/i915.rst| 16 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 33 ---
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---
3 files changed, 43 insertions(+), 21 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 357e9dfa7de1..60bd6e6403da 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -471,8 +471,20 @@ GuC-based command submission
HuC
---
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
- :doc: HuC Firmware
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :doc: HuC
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :functions: intel_huc_auth
+
+HuC Memory Management
+~
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :doc: HuC Memory Management
+
+HuC Firmware Layout
+~~~
+The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
DMC
---
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 33608a114d4e..c802e5b68c05 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -9,6 +9,32 @@
#include "intel_huc.h"
#include "i915_drv.h"
+/**
+ * DOC: HuC
+ *
+ * The HuC is a dedicated microcontroller for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can directly use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ * The kernel driver is only responsible for loading the HuC firmware and
+ * triggering its security authentication, which is performed by the GuC. For
+ * The GuC to correctly perform the authentication, the HuC binary must be
+ * loaded before the GuC one. Loading the HuC is optional; however, not using
+ * the HuC might negatively impact power usage and/or performance of media
+ * workloads, depending on the use-cases.
+ * See https://github.com/intel/media-driver for the latest details on HuC
+ * functionality.
+ */
+
+/**
+ * DOC: HuC Memory Management
+ *
+ * Similarly to the GuC, the HuC can't do any memory allocations on its own,
+ * with the difference being that the allocations for HuC usage are handled by
+ * the userspace driver instead of the kernel one. The HuC accesses the memory
+ * via the PPGTT belonging to the context loaded on the VCS executing the
+ * HuC-specific commands.
+ */
+
void intel_huc_init_early(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
@@ -118,10 +144,9 @@ void intel_huc_fini(struct intel_huc *huc)
*
* Called after HuC and GuC firmware loading during intel_uc_init_hw().
*
- * This function pins HuC firmware image object into GGTT.
- * Then it invokes GuC action to authenticate passing the offset to RSA
- * signature through intel_guc_auth_huc(). It then waits for 50ms for
- * firmware verification ACK and unpins the object.
+ * This function invokes the GuC action to authenticate the HuC firmware,
+ * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
+ * waits for up to 50ms for firmware verification ACK.
*/
int intel_huc_auth(struct intel_huc *huc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 74602487ed67..d654340d4d03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -7,21 +7,6 @@
#include "intel_huc_fw.h"
#include "i915_drv.h"
-/**
- * DOC: HuC Firmware
- *
- * Motivation:
- * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
- * Efficiency Video Coding) operations. Userspace can use the firmware
- * capabilities by adding HuC specific commands to batch buffers.
- *
- * Implementation:
- * The same firmware loader is used as the GuC. However, the actual
- * loading to HW is deferred until GEM initialization is done.
- *
- * Note that HuC firmware loading must be done before GuC loading.
- */
-
/**
* intel_huc_fw_init_early() - initializes HuC firmware struct
* @huc: intel_huc struct
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v7,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
== Series Details ==
Series: series starting with [v7,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync
URL : https://patchwork.freedesktop.org/series/67806/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14737
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14737 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14737, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14737:
### IGT changes ###
Possible regressions
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-guc: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-guc/igt@kms_force_connector_ba...@force-connector-state.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-kbl-guc/igt@kms_force_connector_ba...@force-connector-state.html
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-ilk-650/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-pnv-d510/igt@run...@aborted.html
- fi-gdg-551: NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-gdg-551/igt@run...@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-snb-2520m/igt@run...@aborted.html
- fi-whl-u: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-whl-u/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-ivb-3770/igt@run...@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-bxt-dsi/igt@run...@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-bsw-n3050/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-blb-e6850/igt@run...@aborted.html
- fi-bsw-kefka: NOTRUN -> [FAIL][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-bsw-kefka/igt@run...@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][13]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-kbl-guc/igt@run...@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][14]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-elk-e7500/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14737 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] /
[fdo#109100])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
Possible fixes
* igt@gem_exec_suspend@basic:
- {fi-tgl-u2}:[INCOMPLETE][17] ([fdo#111850]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-tgl-u2/igt@gem_exec_susp...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-tgl-u2/igt@gem_exec_susp...@basic.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-guc}: [INCOMPLETE][19] ([fdo#107713] / [fdo#108840]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-guc/igt@i915_pm_...@module-reload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14737/fi-icl-guc/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (53 -> 45)
--
Additional (1): fi-pnv-d510
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915/perf: store the associated engine of a stream
== Series Details ==
Series: series starting with [1/9] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67804/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14736
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/index.html
New tests
-
New tests have been introduced between CI_DRM_7046 and Patchwork_14736:
### New IGT tests (1) ###
* igt@i915_selftest@live_perf:
- Statuses : 40 pass(s)
- Exec time: [0.42, 2.56] s
Known issues
Here are the changes found in Patchwork_14736 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
Possible fixes
* igt@gem_exec_suspend@basic:
- {fi-tgl-u2}:[INCOMPLETE][5] ([fdo#111850]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-tgl-u2/igt@gem_exec_susp...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/fi-tgl-u2/igt@gem_exec_susp...@basic.html
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
* igt@i915_selftest@live_hugepages:
- fi-elk-e7500: [INCOMPLETE][9] ([fdo#103989]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][13] ([fdo#102505] / [fdo#110390]) ->
[FAIL][14] ([fdo#109483])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
[fdo#111833]: https://bugs.freedesktop.org/show_bug.cgi?id=111833
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
Participating hosts (53 -> 45)
--
Missing(8): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7046 -> Patchwork_14736
CI-20190529: 20190529
CI_DRM_7046: 136f98967ad06da28fd795aa83be314c7b641c49 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14736: e3f2dcd269982b3af2bc0f8b3e5d1eab8c74d6e2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e3f2dcd26998 drm/i915/execlists: Prevent merging requests with conflicting flags
5d1246ef0b93 drm/i915/perf: allow holding preemption on filtered ctx
047ce24b0f91 drm/i915/perf: Allow dynamic reconfiguration of the OA stream
c8c01bdf5c02 drm/i915/perf: execute OA
[Intel-gfx] linux-next: build failure after merge of the drm tree
Hi all,
After merging the drm tree, today's linux-next build (x86_64 allmodconfig)
failed like this:
In file included from drivers/gpu/drm/i915/i915_vma.h:35,
from drivers/gpu/drm/i915/gt/uc/intel_guc.h:17,
from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
from drivers/gpu/drm/i915/i915_drv.h:81,
from drivers/gpu/drm/i915/i915_getparam.c:7:
drivers/gpu/drm/i915/gem/i915_gem_object.h:174:1: error: redefinition of
'i915_gem_object_never_bind_ggtt'
174 | i915_gem_object_never_bind_ggtt(const struct drm_i915_gem_object *obj)
| ^~~
drivers/gpu/drm/i915/gem/i915_gem_object.h:168:1: note: previous definition of
'i915_gem_object_never_bind_ggtt' was here
168 | i915_gem_object_never_bind_ggtt(const struct drm_i915_gem_object *obj)
| ^~~
Caused by the automatic merge of commit
3a1fea6d2353 ("drm/i915/userptr: Never allow userptr into the mappable GGTT")
from the drm-intel-fixes tree and commits
a4311745bba9 ("drm/i915/userptr: Never allow userptr into the mappable GGTT")
3cbad5d77749 ("drm/i915/gem: Refactor tests on obj->ops->flags")
from the drm tree.
I fixed it up by removing the extra definition. This sort of thing will
keep happening as longs as bugs are fixed in your development trees
and then cherry-picked back into your -fixes trees. This practise also
causes quite a few unnecessary conflicts that each have to be checked
and merged by hand.
--
Cheers,
Stephen Rothwell
pgp68lwBWwGza.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/perf: store the associated engine of a stream
== Series Details ==
Series: series starting with [1/9] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67804/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bf2b0e099619 drm/i915/perf: store the associated engine of a stream
4726bb22ec6f drm/i915/perf: introduce a versioning of the i915-perf uapi
635bb86b7638 drm/i915/perf: allow for CS OA configs to be created lazily
0c88bb75cd92 drm/i915: add support for perf configuration queries
37d537db43fb drm/i915/perf: implement active wait for noa configurations
-:45: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#45: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:228:
+#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
^
-:179: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#179: FILE: drivers/gpu/drm/i915/i915_perf.c:1567:
+ DIV64_U64_ROUND_UP(
-:213: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#213: FILE: drivers/gpu/drm/i915/i915_perf.c:1601:
+ batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
-:221: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#221: FILE: drivers/gpu/drm/i915/i915_perf.c:1609:
+ cs = save_restore_register(
-:224: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#224: FILE: drivers/gpu/drm/i915/i915_perf.c:1612:
+ cs = save_restore_register(
-:326: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#326: FILE: drivers/gpu/drm/i915/i915_perf.c:1714:
+ cs = save_restore_register(
-:329: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#329: FILE: drivers/gpu/drm/i915/i915_perf.c:1717:
+ cs = save_restore_register(
-:446: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#446:
new file mode 100644
-:451: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#451: FILE: drivers/gpu/drm/i915/selftests/i915_perf.c:1:
+/*
-:452: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#452: FILE: drivers/gpu/drm/i915/selftests/i915_perf.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 3 warnings, 7 checks, 590 lines checked
c8c01bdf5c02 drm/i915/perf: execute OA configuration from command stream
047ce24b0f91 drm/i915/perf: Allow dynamic reconfiguration of the OA stream
5d1246ef0b93 drm/i915/perf: allow holding preemption on filtered ctx
e3f2dcd26998 drm/i915/execlists: Prevent merging requests with conflicting flags
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#14:
References: 2a98f4e65bba ("drm/i915: add infrastructure to hold off preemption
on a request")
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2a98f4e65bba ("drm/i915: add
infrastructure to hold off preemption on a request")'
#14:
References: 2a98f4e65bba ("drm/i915: add infrastructure to hold off preemption
on a request")
total: 1 errors, 1 warnings, 0 checks, 9 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/i915/perf: Disable rc6 only while OA is enabled (rev2)
== Series Details ==
Series: series starting with [01/11] drm/i915/perf: Disable rc6 only while OA
is enabled (rev2)
URL : https://patchwork.freedesktop.org/series/67802/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14735
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14735 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14735, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14735:
### IGT changes ###
Possible regressions
* {igt@i915_selftest@live_perf} (NEW):
- fi-skl-6700k2: NOTRUN -> [DMESG-WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-skl-6700k2/igt@i915_selftest@live_perf.html
- fi-hsw-4770r: NOTRUN -> [DMESG-WARN][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-hsw-4770r/igt@i915_selftest@live_perf.html
- fi-skl-iommu: NOTRUN -> [DMESG-WARN][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-skl-iommu/igt@i915_selftest@live_perf.html
- fi-skl-6600u: NOTRUN -> [DMESG-WARN][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-skl-6600u/igt@i915_selftest@live_perf.html
- fi-whl-u: NOTRUN -> [DMESG-WARN][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-whl-u/igt@i915_selftest@live_perf.html
- {fi-icl-dsi}: NOTRUN -> [DMESG-WARN][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-icl-dsi/igt@i915_selftest@live_perf.html
- fi-apl-guc: NOTRUN -> [DMESG-WARN][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-apl-guc/igt@i915_selftest@live_perf.html
- fi-kbl-r: NOTRUN -> [DMESG-WARN][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-kbl-r/igt@i915_selftest@live_perf.html
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-kbl-8809g/igt@i915_selftest@live_perf.html
- fi-kbl-x1275: NOTRUN -> [DMESG-WARN][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-kbl-x1275/igt@i915_selftest@live_perf.html
- fi-icl-u3: NOTRUN -> [DMESG-WARN][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-icl-u3/igt@i915_selftest@live_perf.html
- fi-skl-6260u: NOTRUN -> [DMESG-WARN][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-skl-6260u/igt@i915_selftest@live_perf.html
- fi-hsw-peppy: NOTRUN -> [DMESG-WARN][13]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-hsw-peppy/igt@i915_selftest@live_perf.html
- fi-skl-lmem:NOTRUN -> [DMESG-WARN][14]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-skl-lmem/igt@i915_selftest@live_perf.html
- fi-skl-6770hq: NOTRUN -> [DMESG-WARN][15]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-skl-6770hq/igt@i915_selftest@live_perf.html
- fi-cfl-guc: NOTRUN -> [DMESG-WARN][16]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-cfl-guc/igt@i915_selftest@live_perf.html
- {fi-cml-s}: NOTRUN -> [DMESG-WARN][17]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-cml-s/igt@i915_selftest@live_perf.html
- {fi-kbl-soraka}:NOTRUN -> [DMESG-WARN][18]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-kbl-soraka/igt@i915_selftest@live_perf.html
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][19]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-hsw-4770/igt@i915_selftest@live_perf.html
- fi-bxt-dsi: NOTRUN -> [DMESG-WARN][20]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-bxt-dsi/igt@i915_selftest@live_perf.html
- fi-cfl-8700k: NOTRUN -> [DMESG-WARN][21]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-cfl-8700k/igt@i915_selftest@live_perf.html
- fi-cml-u2: NOTRUN -> [DMESG-WARN][22]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-cml-u2/igt@i915_selftest@live_perf.html
- fi-icl-u2: NOTRUN -> [DMESG-WARN][23]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-icl-u2/igt@i915_selftest@live_perf.html
- fi-kbl-7500u: NOTRUN -> [DMESG-WARN][24]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14735/fi-kbl-7500u/igt@i915_selftest@live_perf.html
- fi-cfl-8109u: NOTRUN -> [DMESG-WARN][25]
[25]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/print: cleanup and new drm_device based logging
== Series Details == Series: drm/print: cleanup and new drm_device based logging URL : https://patchwork.freedesktop.org/series/67795/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7043_full -> Patchwork_14728_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14728_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14728_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14728_full: ### IGT changes ### Possible regressions * igt@i915_suspend@forcewake: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-iclb4/igt@i915_susp...@forcewake.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-iclb7/igt@i915_susp...@forcewake.html Known issues Here are the changes found in Patchwork_14728_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_mmap_gtt@hang: - shard-snb: [PASS][7] -> [INCOMPLETE][8] ([fdo#105411]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-snb5/igt@gem_mmap_...@hang.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-snb7/igt@gem_mmap_...@hang.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-hsw6/igt@gem_userptr_bl...@dmabuf-unsync.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-hsw4/igt@gem_userptr_bl...@dmabuf-unsync.html * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([fdo#105763] / [fdo#106538]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-glk2/igt@i915_pm_...@modeset-stress-extra-wait.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-glk8/igt@i915_pm_...@modeset-stress-extra-wait.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-skl5/igt@i915_susp...@fence-restore-tiled2untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-skl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-apl7/igt@i915_susp...@sysfs-reader.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/11] drm/i915/perf: Disable rc6 only while OA is enabled (rev2)
== Series Details ==
Series: series starting with [01/11] drm/i915/perf: Disable rc6 only while OA
is enabled (rev2)
URL : https://patchwork.freedesktop.org/series/67802/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
abb0ff1fe0d5 drm/i915/perf: Disable rc6 only while OA is enabled
bb56bdb4350c drm/i915/perf: Tidy up unpinning the oa_context
549d5bcaa8ad drm/i915/perf: store the associated engine of a stream
51c8ed17baff drm/i915/perf: introduce a versioning of the i915-perf uapi
21ccc3e1c9fd drm/i915/perf: allow for CS OA configs to be created lazily
b823fc5fe42d drm/i915: add support for perf configuration queries
f32959e7af16 drm/i915/perf: implement active wait for noa configurations
-:45: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#45: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:228:
+#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
^
-:179: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#179: FILE: drivers/gpu/drm/i915/i915_perf.c:1562:
+ DIV64_U64_ROUND_UP(
-:213: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#213: FILE: drivers/gpu/drm/i915/i915_perf.c:1596:
+ batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
-:221: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#221: FILE: drivers/gpu/drm/i915/i915_perf.c:1604:
+ cs = save_restore_register(
-:224: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#224: FILE: drivers/gpu/drm/i915/i915_perf.c:1607:
+ cs = save_restore_register(
-:326: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#326: FILE: drivers/gpu/drm/i915/i915_perf.c:1709:
+ cs = save_restore_register(
-:329: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#329: FILE: drivers/gpu/drm/i915/i915_perf.c:1712:
+ cs = save_restore_register(
-:446: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#446:
new file mode 100644
-:451: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#451: FILE: drivers/gpu/drm/i915/selftests/i915_perf.c:1:
+/*
-:452: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#452: FILE: drivers/gpu/drm/i915/selftests/i915_perf.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 3 warnings, 7 checks, 590 lines checked
45cc47d7a24b drm/i915/perf: execute OA configuration from command stream
482e97d03cf8 drm/i915/perf: Allow dynamic reconfiguration of the OA stream
555eaf257a1d drm/i915/perf: allow holding preemption on filtered ctx
42ba0481cac2 drm/i915/execlists: Prevent merging requests with conflicting flags
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#14:
References: 2a98f4e65bba ("drm/i915: add infrastructure to hold off preemption
on a request")
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2a98f4e65bba ("drm/i915: add
infrastructure to hold off preemption on a request")'
#14:
References: 2a98f4e65bba ("drm/i915: add infrastructure to hold off preemption
on a request")
total: 1 errors, 1 warnings, 0 checks, 9 lines checked
___
Intel-gfx mailing list
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Leave tell-tales as to why pending[] is bad (rev2)
== Series Details ==
Series: drm/i915/execlists: Leave tell-tales as to why pending[] is bad (rev2)
URL : https://patchwork.freedesktop.org/series/67786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14734
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/index.html
Known issues
Here are the changes found in Patchwork_14734 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][1] ([fdo#107724]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_ctx_e...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/fi-icl-u3/igt@gem_ctx_e...@basic.html
* igt@gem_exec_suspend@basic:
- {fi-tgl-u2}:[INCOMPLETE][3] ([fdo#111850]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-tgl-u2/igt@gem_exec_susp...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/fi-tgl-u2/igt@gem_exec_susp...@basic.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-guc}: [INCOMPLETE][5] ([fdo#107713] / [fdo#108840]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-guc/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/fi-icl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_hugepages:
- fi-elk-e7500: [INCOMPLETE][7] ([fdo#103989]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111045] / [fdo#111096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (53 -> 47)
--
Additional (1): fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7046 -> Patchwork_14734
CI-20190529: 20190529
CI_DRM_7046: 136f98967ad06da28fd795aa83be314c7b641c49 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14734: 49c269f75e1857ac2990f2bbec06e3212d3de40b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
49c269f75e18 drm/i915/execlists: Leave tell-tales as to why pending[] is bad
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/huc: improve documentation
On 10/9/19 2:44 PM, Daniele Ceraolo Spurio wrote:
On 10/9/19 7:41 AM, Martin Peres wrote:
On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote:
Better explain the usage of the microcontroller and what i915 is
responsible of. While at it, fix the documentation for the auth
function, which doesn't do any pinning anymore.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
Documentation/gpu/i915.rst | 10 --
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 19 +++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---
3 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 357e9dfa7de1..bfb64337db66 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -471,8 +471,14 @@ GuC-based command submission
HuC
---
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
- :doc: HuC Firmware
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :doc: HuC
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :functions: intel_huc_auth
+
+HuC Firmware Layout
+~~~
+The HuC FW layout is the same as the GuC one, see `GuC Firmware
Layout`_
DMC
---
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d4625c97b4f9..6e10fe898c90 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -9,6 +9,18 @@
#include "intel_huc.h"
#include "i915_drv.h"
+/**
+ * DOC: HuC
+ *
+ * The HuC is a dedicated microcontroller for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can directly use
the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ * The kernel driver is only responsible for loading the HuC
firmware and
+ * triggering its security authentication, which is performed by the
GuC. For
+ * The GuC to correctly perform the authentication, the HuC binary
must be
+ * loaded before the GuC one.
+ */
+
void intel_huc_init_early(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
@@ -118,10 +130,9 @@ void intel_huc_fini(struct intel_huc *huc)
*
* Called after HuC and GuC firmware loading during
intel_uc_init_hw().
*
- * This function pins HuC firmware image object into GGTT.
- * Then it invokes GuC action to authenticate passing the offset to RSA
- * signature through intel_guc_auth_huc(). It then waits for 50ms for
- * firmware verification ACK and unpins the object.
+ * This function invokes the GuC action to authenticate the HuC
firmware,
+ * passing the offset of the RSA signature to intel_guc_auth_huc().
It then
+ * waits for up to 50ms for firmware verification ACK.
*/
int intel_huc_auth(struct intel_huc *huc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 74602487ed67..d654340d4d03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -7,21 +7,6 @@
#include "intel_huc_fw.h"
#include "i915_drv.h"
-/**
- * DOC: HuC Firmware
- *
- * Motivation:
- * GEN9 introduces a new dedicated firmware for usage in media HEVC
(High
- * Efficiency Video Coding) operations. Userspace can use the firmware
- * capabilities by adding HuC specific commands to batch buffers.
Having a link to the media driver here that would explain what the HuC
enables would be beneficial (we don't want to maintain that).
- *
- * Implementation:
- * The same firmware loader is used as the GuC. However, the actual
- * loading to HW is deferred until GEM initialization is done.
- *
- * Note that HuC firmware loading must be done before GuC loading.
- */
Could we add a section explaining the access the HuC has to memory, and
I'll have to follow up with the HuC team to understand how the memory
access works because I'm not too familiar with HuC. Are you ok if I
address all your other comments for GuC and HuC and add this as a follow
up later once I get the info?
Never mind, I found the info I needed (Bspec 48058), so I can do all
the changes in one go.
Daniele
Daniele
one stating that the firmware is optional?
Anyways, thanks! The series could be landed as-is already, but a few
more additions would be welcomed :)
Martin
-
/**
* intel_huc_fw_init_early() - initializes HuC firmware struct
* @huc: intel_huc struct
___
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___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv (rev2)
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to
dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/67799/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14733
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/index.html
Known issues
Here are the changes found in Patchwork_14733 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_ba...@create-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/fi-icl-u3/igt@gem_ba...@create-close.html
* igt@gem_close_race@basic-threads:
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-u3/igt@gem_close_r...@basic-threads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/fi-icl-u3/igt@gem_close_r...@basic-threads.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {fi-icl-guc}: [INCOMPLETE][5] ([fdo#107713] / [fdo#108840]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-icl-guc/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/fi-icl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_hugepages:
- fi-elk-e7500: [INCOMPLETE][7] ([fdo#103989]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/fi-elk-e7500/igt@i915_selftest@live_hugepages.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [INCOMPLETE][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111045] / [fdo#111096]) ->
[FAIL][12] ([fdo#111407])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (53 -> 44)
--
Additional (1): fi-pnv-d510
Missing(10): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-byt-clapper fi-gdg-551 fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7046 -> Patchwork_14733
CI-20190529: 20190529
CI_DRM_7046: 136f98967ad06da28fd795aa83be314c7b641c49 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14733: cc743a676c3acb583caf03127a69622eb28a6155 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cc743a676c3a drm/i915/tgl: Read SAGV block time from PCODE
7da5381e3ab8 drm/i915: Move SAGV block time to dev_priv
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/index.html
___
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[Intel-gfx] [PATCH 1/2] drm/i915/tgl: the BCS engine supports relative MMIO
The specs don't mention any specific HW limitation on the blitter and manual inspection shows that the HW does set the relative MMIO bit in the LRI of the blitter context image, so we can remove our limitations. Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: John Harrison Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6db762c509b8..78a136c12385 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3448,7 +3448,7 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine) engine->flags |= I915_ENGINE_HAS_PREEMPTION; } - if (engine->class != COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) >= 12) + if (INTEL_GEN(engine->i915) >= 12) engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; } -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/tgl: simplify the lrc register list for !RCS
There are small differences between the blitter and the video engines in
the xcs context image (e.g. registers 0x200 and 0x204 only exist on the
blitter). Since we never explicitly set a value for those register and
given that we don't need to update the offsets in the lrc image when we
change engine within the class for virtual engine because the HW can
handle that, instead of having a separate define for the BCS we can
just restrict the programming to the part we're interested in, which is
common across the engines.
Bspec: 45584
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 66 -
1 file changed, 8 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 78a136c12385..488a19ab908d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -669,64 +669,6 @@ static const u8 gen12_xcs_offsets[] = {
REG16(0x274),
REG16(0x270),
- NOP(13),
- LRI(2, POSTED),
- REG16(0x200),
- REG16(0x204),
-
- NOP(11),
- LRI(50, POSTED),
- REG16(0x588),
- REG16(0x588),
- REG16(0x588),
- REG16(0x588),
- REG16(0x588),
- REG16(0x588),
- REG(0x028),
- REG(0x09c),
- REG(0x0c0),
- REG(0x178),
- REG(0x17c),
- REG16(0x358),
- REG(0x170),
- REG(0x150),
- REG(0x154),
- REG(0x158),
- REG16(0x41c),
- REG16(0x600),
- REG16(0x604),
- REG16(0x608),
- REG16(0x60c),
- REG16(0x610),
- REG16(0x614),
- REG16(0x618),
- REG16(0x61c),
- REG16(0x620),
- REG16(0x624),
- REG16(0x628),
- REG16(0x62c),
- REG16(0x630),
- REG16(0x634),
- REG16(0x638),
- REG16(0x63c),
- REG16(0x640),
- REG16(0x644),
- REG16(0x648),
- REG16(0x64c),
- REG16(0x650),
- REG16(0x654),
- REG16(0x658),
- REG16(0x65c),
- REG16(0x660),
- REG16(0x664),
- REG16(0x668),
- REG16(0x66c),
- REG16(0x670),
- REG16(0x674),
- REG16(0x678),
- REG16(0x67c),
- REG(0x068),
-
END(),
};
@@ -857,6 +799,14 @@ static const u8 gen12_rcs_offsets[] = {
static const u8 *reg_offsets(const struct intel_engine_cs *engine)
{
+ /*
+* the gen12+ lists only have the register we program in the default
+* state because we don't need to update the offsets when using a
+* virtual engine.
+*/
+ GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
+ !intel_engine_has_relative_mmio(engine));
+
if (engine->class == RENDER_CLASS) {
if (INTEL_GEN(engine->i915) >= 12)
return gen12_rcs_offsets;
--
2.23.0
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Leave tell-tales as to why pending[] is bad
== Series Details ==
Series: drm/i915/execlists: Leave tell-tales as to why pending[] is bad
URL : https://patchwork.freedesktop.org/series/67786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7043_full -> Patchwork_14726_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14726_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-tglb6/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html
Known issues
Here are the changes found in Patchwork_14726_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@preempt-queue-bsd2:
- shard-iclb: [PASS][2] -> [SKIP][3] ([fdo#109276]) +8 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd2.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd2.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +7 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-hsw: [PASS][6] -> [DMESG-WARN][7] ([fdo#111870])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-hsw6/igt@gem_userptr_bl...@dmabuf-unsync.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-hsw6/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +4
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_atomic_interruptible@legacy-pageflip:
- shard-apl: [PASS][10] -> [INCOMPLETE][11] ([fdo#103927])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-apl3/igt@kms_atomic_interrupti...@legacy-pageflip.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-apl7/igt@kms_atomic_interrupti...@legacy-pageflip.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][12] -> [FAIL][13] ([fdo#105363]) +1 similar
issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-glk4/igt@kms_f...@flip-vs-expired-vblank.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][14] -> [FAIL][15] ([fdo#105363])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-skl9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][16] -> [FAIL][17] ([fdo#103167]) +6 similar
issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108145])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145] /
[fdo#110403]) +1 similar issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109642] / [fdo#111068])
Re: [Intel-gfx] [PATCH] drm/dp-mst: Drop connection_mutex check
oh, completely forgot about this one
Reviewed-by: Lyude Paul
On Thu, 2019-10-10 at 00:41 +0200, Daniel Vetter wrote:
> Private atomic objects have grown their own locking with
>
> commit b962a12050a387e4bbf3a48745afe1d29d396b0d
> Author: Rob Clark
> Date: Mon Oct 22 14:31:22 2018 +0200
>
> drm/atomic: integrate modeset lock with private objects
>
> which means we're no longer relying on connection_mutex for mst state
> locking needs.
>
> Cc: Lyude Paul
> Cc: Sean Paul
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 6b14b63b8d62..9364e4f42975 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -4186,7 +4186,6 @@ struct drm_dp_mst_topology_state
> *drm_atomic_get_mst_topology_state(struct drm_a
> {
> struct drm_device *dev = mgr->dev;
>
> - WARN_ON(!drm_modeset_is_locked(>mode_config.connection_mutex));
> return
> to_dp_mst_topology_state(drm_atomic_get_private_obj_state(state,
> >base));
> }
> EXPORT_SYMBOL(drm_atomic_get_mst_topology_state);
--
Cheers,
Lyude Paul
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[Intel-gfx] [PATCH] drm/dp-mst: Drop connection_mutex check
Private atomic objects have grown their own locking with
commit b962a12050a387e4bbf3a48745afe1d29d396b0d
Author: Rob Clark
Date: Mon Oct 22 14:31:22 2018 +0200
drm/atomic: integrate modeset lock with private objects
which means we're no longer relying on connection_mutex for mst state
locking needs.
Cc: Lyude Paul
Cc: Sean Paul
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_mst_topology.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 6b14b63b8d62..9364e4f42975 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4186,7 +4186,6 @@ struct drm_dp_mst_topology_state
*drm_atomic_get_mst_topology_state(struct drm_a
{
struct drm_device *dev = mgr->dev;
- WARN_ON(!drm_modeset_is_locked(>mode_config.connection_mutex));
return to_dp_mst_topology_state(drm_atomic_get_private_obj_state(state,
>base));
}
EXPORT_SYMBOL(drm_atomic_get_mst_topology_state);
--
2.23.0
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv (rev2)
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to
dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/67799/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7da5381e3ab8 drm/i915: Move SAGV block time to dev_priv
-:63: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#63: FILE: drivers/gpu/drm/i915/intel_pm.c:3657:
+ return;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 69 lines checked
cc743a676c3a drm/i915/tgl: Read SAGV block time from PCODE
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[Intel-gfx] [PATCH v7 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the transcoder port sync mode is configured and enabled
and the Vblanks of both ports are synchronized so then set DP_TP_CTL
for the slave and master to Normal and do post crtc enable updates.
v7:
* Use ffs(slaves) to get slave crtc (Ville)
v6:
* Modeset implies active_changed, remove one condition (Maarten)
v5:
* Fix checkpatch warning (Manasi)
v4:
* Reuse skl_commit_modeset_enables() hook (Maarten)
* Obtain slave crtc and states from master (Maarten)
v3:
* Rebase on drm-tip (Manasi)
v2:
* Create a icl_update_crtcs hook (Maarten, Danvet)
* This sequence only for CRTCs in trans port sync mode (Maarten)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 125 ++-
drivers/gpu/drm/i915/display/intel_display.h | 2 +
3 files changed, 126 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6c1315c7bcde..b96091800662 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3571,7 +3571,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder
*encoder,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
- if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+ if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
+ !is_trans_port_sync_mode(crtc_state))
intel_dp_stop_link_train(intel_dp);
intel_ddi_enable_fec(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d671cb0b50ef..fdb02f4b6eb8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13943,6 +13943,18 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_finish_crtc_commit(state, crtc);
}
+static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *dev_priv =
to_i915(new_crtc_state->base.crtc->dev);
+ enum transcoder slave_transcoder;
+
+ WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
+
+ slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
+ return intel_get_crtc_for_pipe(dev_priv,
+ (enum pipe)slave_transcoder);
+}
+
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state
*new_crtc_state,
@@ -14021,6 +14033,102 @@ static void intel_commit_modeset_enables(struct
intel_atomic_state *state)
}
}
+static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ update_scanline_offset(new_crtc_state);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
+ intel_crtc_enable_pipe_crc(crtc);
+}
+
+static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
+ struct intel_atomic_state *state)
+{
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_dp *intel_dp;
+ int i;
+
+ for_each_new_connector_in_state(>base, conn, conn_state, i) {
+ if (conn_state->crtc == >base)
+ break;
+ }
+ intel_dp = enc_to_intel_dp(_attached_encoder(conn)->base);
+ intel_dp_stop_link_train(intel_dp);
+}
+
+static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state
*old_crtc_state,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ struct intel_plane_state *new_plane_state =
+ intel_atomic_get_new_plane_state(state,
+
to_intel_plane(crtc->base.primary));
+
+ if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
+ intel_fbc_disable(crtc);
+ else if (new_plane_state)
+ intel_fbc_enable(crtc,
[Intel-gfx] [PATCH v7 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state mismatch.
v8:
* Use master_select -1, address TRANS_EDP case (Ville)
* Rename master_transcoder to _readout (Lucas)
v7:
* NDont read HW state for DSI
v6:
* Go through both parts of HW readout (Maarten)
* Add a WARN if the same trans configured as
master and slave (Ville, Maarten)
v5:
* Add return INVALID in defaut case (Maarten)
v4:
* Get power domains in master loop for get_config (Ville)
v3:
* Add TRANSCODER_D (Maarten)
* v3 Reviewed-by: Maarten Lankhorst
v2:
* Add Transcoder_D and MISSING_CASE (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 57
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f37b28da3768..d671cb0b50ef 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10481,6 +10481,59 @@ static void haswell_get_ddi_port_state(struct
intel_crtc *crtc,
}
}
+static enum transcoder transcoder_master_readout(struct drm_i915_private
*dev_priv,
+enum transcoder cpu_transcoder)
+{
+ u32 trans_port_sync, master_select;
+
+ trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
+
+ if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
+ return INVALID_TRANSCODER;
+
+ master_select = trans_port_sync &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK;
+ if (master_select == 0)
+ return TRANSCODER_EDP;
+ else
+ return master_select - 1;
+}
+
+static void icelake_get_trans_port_sync_config(struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ u32 transcoders;
+ enum transcoder cpu_transcoder;
+
+ crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
+
crtc_state->cpu_transcoder);
+
+ transcoders = BIT(TRANSCODER_A) |
+ BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) |
+ BIT(TRANSCODER_D);
+ for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+ enum intel_display_power_domain power_domain;
+ intel_wakeref_t trans_wakeref;
+
+ power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+ trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
+
power_domain);
+
+ if (!trans_wakeref)
+ continue;
+
+ if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
+ crtc_state->cpu_transcoder)
+ crtc_state->sync_mode_slaves_mask |=
BIT(cpu_transcoder);
+
+ intel_display_power_put(dev_priv, power_domain, trans_wakeref);
+ }
+
+ WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
+ crtc_state->sync_mode_slaves_mask);
+}
+
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -10600,6 +10653,10 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
pipe_config->pixel_multiplier = 1;
}
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ !transcoder_is_dsi(pipe_config->cpu_transcoder))
+ icelake_get_trans_port_sync_config(pipe_config);
+
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv,
--
2.19.1
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[Intel-gfx] [PATCH v7 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v5:
* Dont pass dev priv to get_slave_crtc (Ville)
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables() helper
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 58 ++--
1 file changed, 52 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index df5a3950bd84..2c1307ba1dcf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14012,6 +14012,37 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
new_crtc_state);
}
+static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state
*state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state
*old_crtc_state,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave_crtc);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+ WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+ !old_slave_crtc_state);
+
+ /* Disable Slave first */
+ intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+ if (old_slave_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_slave_crtc_state,
+ new_slave_crtc_state,
+ slave_crtc);
+
+ /* Disable Master */
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+}
+
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
{
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
@@ -14030,13 +14061,28 @@ static void intel_commit_modeset_disables(struct
intel_atomic_state *state)
if (!needs_modeset(new_crtc_state))
continue;
- intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ /* In case of Transcoder port Sync master slave CRTCs can be
+* assigned in any order and we need to make sure that
+* slave CRTCs are disabled first and then master CRTC since
+* Slave vblanks are masked till Master Vblanks.
+*/
+ if (is_trans_port_sync_mode(new_crtc_state)) {
+ if (is_trans_port_sync_master(new_crtc_state))
+ intel_trans_port_sync_modeset_disables(state,
+ crtc,
+
old_crtc_state,
+
new_crtc_state);
+ else
+ continue;
+ } else {
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (old_crtc_state->base.active)
- intel_old_crtc_state_disables(state,
- old_crtc_state,
- new_crtc_state,
- crtc);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+ }
}
}
--
2.19.1
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[Intel-gfx] [PATCH v7 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
v2:
* Directly write the trans_port_sync reg value (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 22
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fdb02f4b6eb8..df5a3950bd84 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4445,6 +4445,25 @@ static void icl_enable_trans_port_sync(const struct
intel_crtc_state *crtc_state
trans_ddi_func_ctl2_val);
}
+static void icl_disable_transcoder_port_sync(const struct intel_crtc_state
*old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ i915_reg_t reg;
+ u32 trans_ddi_func_ctl2_val;
+
+ if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
+ transcoder_name(old_crtc_state->cpu_transcoder));
+
+ reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
+ trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
+ PORT_SYNC_MODE_MASTER_SELECT_MASK);
+ I915_WRITE(reg, trans_ddi_func_ctl2_val);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
@@ -6689,6 +6708,9 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_disable_transcoder_port_sync(old_crtc_state);
+
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
--
2.19.1
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[Intel-gfx] [PATCH v7 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical tile that needs to be genlocked with
all other slave tiles.
This patch identifies saves the master transcoder in all the slave
CRTC states. This is needed to select the master CRTC/transcoder
while configuring transcoder port sync for the corresponding slaves.
v5:
* Address Ville's comments
* Just pass crtc_state, no need to check GEN (Ville)
v4:
* Rebase
v3:
* Use master_tramscoder instead of master_crtc for valid
HW state readouts (Ville)
v2:
* Move this to intel_mode_set_pipe_config(Jani N, Ville)
* Use slave_bitmask to save associated slaves in master crtc state (Ville)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 118 ++
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../drm/i915/display/intel_display_types.h| 6 +
3 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8d3247630c43..220a27f1e382 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -521,6 +521,20 @@ needs_modeset(const struct intel_crtc_state *state)
return drm_atomic_crtc_needs_modeset(>base);
}
+bool
+is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
+ crtc_state->sync_mode_slaves_mask);
+}
+
+static bool
+is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
+ crtc_state->sync_mode_slaves_mask);
+}
+
/*
* Platform specific helpers to calculate the port PLL loopback- (clock.m),
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -11816,6 +11830,91 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->base.state);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_connector *master_connector, *connector;
+ struct drm_connector_state *connector_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc *master_crtc = NULL;
+ struct drm_crtc_state *master_crtc_state;
+ struct intel_crtc_state *master_pipe_config;
+ int i, tile_group_id;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ /*
+* In case of tiled displays there could be one or more slaves but
there is
+* only one master. Lets make the CRTC used by the connector
corresponding
+* to the last horizonal and last vertical tile a master/genlock CRTC.
+* All the other CRTCs corresponding to other tiles of the same Tile
group
+* are the slave CRTCs and hold a pointer to their genlock CRTC.
+*/
+ for_each_new_connector_in_state(>base, connector,
connector_state, i) {
+ if (connector_state->crtc != crtc)
+ continue;
+ if (!connector->has_tile)
+ continue;
+ if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
+ crtc_state->base.mode.vdisplay != connector->tile_v_size)
+ return 0;
+ if (connector->tile_h_loc == connector->num_h_tile - 1 &&
+ connector->tile_v_loc == connector->num_v_tile - 1)
+ continue;
+ crtc_state->sync_mode_slaves_mask = 0;
+ tile_group_id = connector->tile_group->id;
+ drm_connector_list_iter_begin(_priv->drm, _iter);
+ drm_for_each_connector_iter(master_connector, _iter) {
+ struct drm_connector_state *master_conn_state = NULL;
+
+ if (!master_connector->has_tile)
+ continue;
+ if (master_connector->tile_h_loc !=
master_connector->num_h_tile - 1 ||
+ master_connector->tile_v_loc !=
master_connector->num_v_tile - 1)
+ continue;
+ if (master_connector->tile_group->id != tile_group_id)
+ continue;
+
+ master_conn_state =
[Intel-gfx] [PATCH v7 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave transcoder
and the master transcoder is unaware that it is operating
in this mode.
This has been tested with tiled display connected to ICL.
v6:
* Use master_trans +1 and address missing trans_edp case (Ville)
v5:
* Add TRANSCODER_D case and MISSING_CASE (Maarten)
v4:
Rebase
v3:
* Check of DP_MST moved to atomic_check (Maarten)
v2:
* Do not use RMW, just write to the register in commit (Jani N)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 33
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 220a27f1e382..f37b28da3768 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4415,6 +4415,36 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
+static void icl_enable_trans_port_sync(const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 trans_ddi_func_ctl2_val;
+ u8 master_select;
+
+ /*
+* Configure the master select and enable Transcoder Port Sync for
+* Slave CRTCs transcoder.
+*/
+ if (crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ if (crtc_state->master_transcoder == TRANSCODER_EDP)
+ master_select = 0;
+ else
+ master_select = crtc_state->master_transcoder + 1;
+
+ /* Set the master select bits for Tranascoder Port Sync */
+ trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
+ PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
+ /* Enable Transcoder Port Sync */
+ trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
+
+ I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
+ trans_ddi_func_ctl2_val);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
@@ -6478,6 +6508,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_set_pipe_timings(pipe_config);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_enable_trans_port_sync(pipe_config);
+
intel_set_pipe_src_size(pipe_config);
if (cpu_transcoder != TRANSCODER_EDP &&
--
2.19.1
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/huc: improve documentation
On 10/9/19 7:41 AM, Martin Peres wrote:
On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote:
Better explain the usage of the microcontroller and what i915 is
responsible of. While at it, fix the documentation for the auth
function, which doesn't do any pinning anymore.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
Documentation/gpu/i915.rst| 10 --
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 19 +++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---
3 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 357e9dfa7de1..bfb64337db66 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -471,8 +471,14 @@ GuC-based command submission
HuC
---
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
- :doc: HuC Firmware
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :doc: HuC
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :functions: intel_huc_auth
+
+HuC Firmware Layout
+~~~
+The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
DMC
---
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d4625c97b4f9..6e10fe898c90 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -9,6 +9,18 @@
#include "intel_huc.h"
#include "i915_drv.h"
+/**
+ * DOC: HuC
+ *
+ * The HuC is a dedicated microcontroller for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can directly use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ * The kernel driver is only responsible for loading the HuC firmware and
+ * triggering its security authentication, which is performed by the GuC. For
+ * The GuC to correctly perform the authentication, the HuC binary must be
+ * loaded before the GuC one.
+ */
+
void intel_huc_init_early(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
@@ -118,10 +130,9 @@ void intel_huc_fini(struct intel_huc *huc)
*
* Called after HuC and GuC firmware loading during intel_uc_init_hw().
*
- * This function pins HuC firmware image object into GGTT.
- * Then it invokes GuC action to authenticate passing the offset to RSA
- * signature through intel_guc_auth_huc(). It then waits for 50ms for
- * firmware verification ACK and unpins the object.
+ * This function invokes the GuC action to authenticate the HuC firmware,
+ * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
+ * waits for up to 50ms for firmware verification ACK.
*/
int intel_huc_auth(struct intel_huc *huc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 74602487ed67..d654340d4d03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -7,21 +7,6 @@
#include "intel_huc_fw.h"
#include "i915_drv.h"
-/**
- * DOC: HuC Firmware
- *
- * Motivation:
- * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
- * Efficiency Video Coding) operations. Userspace can use the firmware
- * capabilities by adding HuC specific commands to batch buffers.
Having a link to the media driver here that would explain what the HuC
enables would be beneficial (we don't want to maintain that).
- *
- * Implementation:
- * The same firmware loader is used as the GuC. However, the actual
- * loading to HW is deferred until GEM initialization is done.
- *
- * Note that HuC firmware loading must be done before GuC loading.
- */
Could we add a section explaining the access the HuC has to memory, and
I'll have to follow up with the HuC team to understand how the memory
access works because I'm not too familiar with HuC. Are you ok if I
address all your other comments for GuC and HuC and add this as a follow
up later once I get the info?
Daniele
one stating that the firmware is optional?
Anyways, thanks! The series could be landed as-is already, but a few
more additions would be welcomed :)
Martin
-
/**
* intel_huc_fw_init_early() - initializes HuC firmware struct
* @huc: intel_huc struct
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Re: [Intel-gfx] [PATCH v7 0/3] CRTC background color
On Wed, Oct 09, 2019 at 05:01:20PM -0400, Daniele Castagna wrote: > On Wed, Oct 9, 2019 at 1:34 PM Matt Roper wrote: > > > > The previous version of this series was posted in February here: > > > > https://lists.freedesktop.org/archives/dri-devel/2019-February/208068.html > > > > Right before we merged this in February Maarten noticed that we should > > be setting up the initial property state in a CRTC reset function (which > > didn't exist yet) instead of when the property was attached. Maarten > > landed the CRTC reset functionality a week or two later, but I was busy > > with travel and other work at the time, so revisiting and rebasing this > > background color series fell through the cracks and I'm just getting > > back to it now. > > > > Userspace consumer is chromeos; these are the links the ChromeOS folks > > gave me back in February: > > https://chromium-review.googlesource.com/c/chromium/src/+/1278858 > > > > https://chromium-review.googlesource.com/c/chromiumos/platform/drm-tests/+/1241436 > > Please note that the current state of the background color on Chrome > OS side is that while the property plumbing landed, the property is > currently not used by the compositor and no one is working on making > that happen. Hmm, in that case it sounds like we probably don't actually have enough userspace support yet to justify merging the kernel changes at this time. I'm not too familiar with Chrome OS' userspace stack; is the rest of the work to actually make use of ozone stuff in the links above a heavy lift? Is it something someone is likely to work on that once they're freed up from other tasks or is there just not enough benefit to justify the effort of utilizing it at the compositor level right now? Matt > The kernel patches have not landed on the ChromeOS kernel either. > > > > > > > > IGT is still the same as posted in February: > > https://lists.freedesktop.org/archives/igt-dev/2019-February/009637.html > > > > Cc: Maarten Lankhorst > > > > Matt Roper (3): > > drm: Add CRTC background color property > > drm/i915/gen9+: Add support for pipe background color > > drm/i915: Add background color hardware readout and state check > > > > drivers/gpu/drm/drm_atomic_state_helper.c| 4 +- > > drivers/gpu/drm/drm_atomic_uapi.c| 4 ++ > > drivers/gpu/drm/drm_blend.c | 35 +-- > > drivers/gpu/drm/drm_mode_config.c| 6 +++ > > drivers/gpu/drm/i915/display/intel_color.c | 11 +++-- > > drivers/gpu/drm/i915/display/intel_display.c | 45 > > drivers/gpu/drm/i915/i915_debugfs.c | 9 > > include/drm/drm_blend.h | 1 + > > include/drm/drm_crtc.h | 12 ++ > > include/drm/drm_mode_config.h| 5 +++ > > include/uapi/drm/drm_mode.h | 28 > > 11 files changed, 153 insertions(+), 7 deletions(-) > > > > -- > > 2.21.0 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/9] drm/i915/perf: Allow dynamic reconfiguration of the OA stream
From: Lionel Landwerlin
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the stream asynchronously on
the GPU in between and ordered with execbuffer calls.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 34 +++-
include/uapi/drm/i915_drm.h | 10 ++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 12cc47aece21..3b77db8995f3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2856,6 +2856,28 @@ static void i915_perf_disable_locked(struct
i915_perf_stream *stream)
stream->ops->disable(stream);
}
+static int i915_perf_config_locked(struct i915_perf_stream *stream,
+ unsigned long metrics_set)
+{
+ struct i915_oa_config *config;
+ int err = 0;
+
+ config = i915_perf_get_oa_config(stream->perf, metrics_set);
+ if (!config)
+ return -EINVAL;
+
+ if (config != stream->oa_config) {
+ if (stream->pinned_ctx)
+ err = emit_oa_config(stream, stream->pinned_ctx);
+ if (err == 0)
+ config = xchg(>oa_config, config);
+ }
+
+ i915_oa_config_put(config);
+
+ return err;
+}
+
/**
* i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
* @stream: An i915 perf stream
@@ -2879,6 +2901,8 @@ static long i915_perf_ioctl_locked(struct
i915_perf_stream *stream,
case I915_PERF_IOCTL_DISABLE:
i915_perf_disable_locked(stream);
return 0;
+ case I915_PERF_IOCTL_CONFIG:
+ return i915_perf_config_locked(stream, arg);
}
return -EINVAL;
@@ -4017,7 +4041,15 @@ void i915_perf_fini(struct drm_i915_private *i915)
*/
int i915_perf_ioctl_version(void)
{
- return 1;
+ /*
+* 1: Initial version
+* I915_PERF_IOCTL_ENABLE
+* I915_PERF_IOCTL_DISABLE
+*
+* 2: Added runtime modification of OA config.
+* I915_PERF_IOCTL_CONFIG
+*/
+ return 2;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0c7b2815fbf1..5e66f7c60261 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1932,6 +1932,16 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_DISABLE_IO('i', 0x1)
+/**
+ * Change metrics_set captured by a stream.
+ *
+ * Will not take effect until the stream is restart, or upon the next
+ * execbuf when attached to a specific context.
+ *
+ * This ioctl is available in perf revision 2.
+ */
+#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
+
/**
* Common to all i915 perf records
*/
--
2.23.0
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[Intel-gfx] [PATCH 8/9] drm/i915/perf: allow holding preemption on filtered ctx
From: Lionel Landwerlin
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of command buffer concept meant that
queries' duration could span multiple command buffers.
With that restriction gone in Vulkan, we would like to simplify
measuring performance just by measuring the deltas between the counter
snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
more complex scheme we currently have in the GL driver, using 2
MI_RECORD_PERF_COUNT commands and doing some post processing on the
stream of OA reports, coming from the global OA buffer, to remove any
unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
Disabling preemption only apply to a single context with which want to
query performance counters for and is considered a privileged
operation, by default protected by CAP_SYS_ADMIN. It is possible to
enable it for a normal user by disabling the paranoid stream setting.
v2: Store preemption setting in intel_context (Chris)
v3: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
v5: Add nopreempt flag on gem context and always flag requests
appropriately, regarless of OA reconfiguration.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 3 ++
drivers/gpu/drm/i915/i915_perf.c | 34 +--
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
include/uapi/drm/i915_drm.h | 11 ++
6 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 9234586830d1..cfe80590f0ed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -114,6 +114,24 @@ i915_gem_context_clear_user_engines(struct
i915_gem_context *ctx)
clear_bit(CONTEXT_USER_ENGINES, >flags);
}
+static inline bool
+i915_gem_context_nopreempt(const struct i915_gem_context *ctx)
+{
+ return test_bit(CONTEXT_NOPREEMPT, >flags);
+}
+
+static inline void
+i915_gem_context_set_nopreempt(struct i915_gem_context *ctx)
+{
+ set_bit(CONTEXT_NOPREEMPT, >flags);
+}
+
+static inline void
+i915_gem_context_clear_nopreempt(struct i915_gem_context *ctx)
+{
+ clear_bit(CONTEXT_NOPREEMPT, >flags);
+}
+
static inline bool i915_gem_context_is_kernel(struct i915_gem_context *ctx)
{
return !ctx->file_priv;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ab8e1367dfc8..fe97b8ba4fda 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -146,6 +146,7 @@ struct i915_gem_context {
#define CONTEXT_CLOSED 1
#define CONTEXT_FORCE_SINGLE_SUBMISSION2
#define CONTEXT_USER_ENGINES 3
+#define CONTEXT_NOPREEMPT 4
struct mutex mutex;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 98816c35ffc3..e96901888323 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2077,6 +2077,9 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
+ if (i915_gem_context_nopreempt(eb->gem_context))
+ eb->request->flags |= I915_REQUEST_NOPREEMPT;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 3b77db8995f3..136ea0980afa 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -344,6 +344,8 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* struct perf_open_properties - for validated properties given to open a
stream
* @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
* @single_context: Whether a single or all gpu contexts should be monitored
+ * @hold_preemption: Whether the preemption is disabled for the filtered
+ * context
* @ctx_handle: A gem ctx handle for use with @single_context
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
@@ -359,6 +361,7 @@ struct perf_open_properties {
u32 sample_flags;
u64 single_context:1;
+ u64 hold_preemption:1;
u64 ctx_handle;
/* OA sampling state */
@@ -2508,6 +2511,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
if
[Intel-gfx] [PATCH 3/9] drm/i915/perf: allow for CS OA configs to be created lazily
From: Lionel Landwerlin
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
v2: No need for locking on object OA config object creation (Chris)
Flush cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
v4: Fix oa config unref/put when not found (Lionel)
v5: Allocate BOs for configurations on the stream instead of globally
(Lionel)
v6: Fix 64bit division (Chris)
v7: Store allocated config BOs into the stream (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 107 +++
drivers/gpu/drm/i915/i915_perf.h | 24 +
drivers/gpu/drm/i915/i915_perf_types.h | 23 ++--
4 files changed, 102 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index b0227ab2fe1b..0987100c786b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -138,6 +138,7 @@
/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
#define MI_LRI_CS_MMIO (1<<19)
#define MI_LRI_FORCE_POSTED (1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT(1<<22)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 21e66c30c6cc..f087a81a6b30 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -369,52 +369,52 @@ struct perf_open_properties {
struct intel_engine_cs *engine;
};
+struct i915_oa_config_bo {
+ struct llist_node node;
+
+ struct i915_oa_config *oa_config;
+ struct i915_vma *vma;
+};
+
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
-static void free_oa_config(struct i915_oa_config *oa_config)
+void i915_oa_config_release(struct kref *ref)
{
+ struct i915_oa_config *oa_config =
+ container_of(ref, typeof(*oa_config), ref);
+
if (!PTR_ERR(oa_config->flex_regs))
kfree(oa_config->flex_regs);
if (!PTR_ERR(oa_config->b_counter_regs))
kfree(oa_config->b_counter_regs);
if (!PTR_ERR(oa_config->mux_regs))
kfree(oa_config->mux_regs);
- kfree(oa_config);
-}
-
-static void put_oa_config(struct i915_oa_config *oa_config)
-{
- if (!atomic_dec_and_test(_config->ref_count))
- return;
- free_oa_config(oa_config);
+ kfree_rcu(oa_config, rcu);
}
-static int get_oa_config(struct i915_perf *perf,
-int metrics_set,
-struct i915_oa_config **out_config)
+struct i915_oa_config *
+i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
{
- int ret;
-
- if (metrics_set == 1) {
- *out_config = >test_config;
- atomic_inc(>test_config.ref_count);
- return 0;
- }
-
- ret = mutex_lock_interruptible(>metrics_lock);
- if (ret)
- return ret;
+ struct i915_oa_config *oa_config;
- *out_config = idr_find(>metrics_idr, metrics_set);
- if (!*out_config)
- ret = -EINVAL;
+ rcu_read_lock();
+ if (metrics_set == 1)
+ oa_config = >test_config;
else
- atomic_inc(&(*out_config)->ref_count);
+ oa_config = idr_find(>metrics_idr, metrics_set);
+ if (oa_config)
+ oa_config = i915_oa_config_get(oa_config);
+ rcu_read_unlock();
- mutex_unlock(>metrics_lock);
+ return oa_config;
+}
- return ret;
+static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
+{
+ i915_oa_config_put(oa_bo->oa_config);
+ i915_vma_put(oa_bo->vma);
+ kfree(oa_bo);
}
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
@@ -1337,6 +1337,16 @@ free_oa_buffer(struct i915_perf_stream *stream)
stream->oa_buffer.vaddr = NULL;
}
+static void
+free_oa_configs(struct i915_perf_stream *stream)
+{
+ struct i915_oa_config_bo *oa_bo, *tmp;
+
+ i915_oa_config_put(stream->oa_config);
+ llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
+ free_oa_config_bo(oa_bo);
+}
+
static void
[Intel-gfx] [PATCH 9/9] drm/i915/execlists: Prevent merging requests with conflicting flags
We set out-of-bound parameters inside the i915_requests.flags field,
such as disabling preemption or marking the end-of-context. We should
not coalesce consecutive requests if they have differing instructions
as we only inspect the last active request in a context. Thus if we
allow a later request to be merged into the same execution context, it
will mask any of the earlier flags.
References: 2a98f4e65bba ("drm/i915: add infrastructure to hold off preemption
on a request")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7ea58335f04c..d0687a94c8d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1233,6 +1233,9 @@ static bool can_merge_rq(const struct i915_request *prev,
if (i915_request_completed(next))
return true;
+ if (unlikely(prev->flags ^ next->flags) & I915_REQUEST_NOPREEMPT)
+ return false;
+
if (!can_merge_ctx(prev->hw_context, next->hw_context))
return false;
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/9] drm/i915/perf: implement active wait for noa configurations
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
v4: Fix save/restore helpers (Umesh)
v5: Move noa_wait from drm_i915_private to i915_perf_stream (Lionel)
v6: Add missing struct declarations in i915_perf.h
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 32 +++
drivers/gpu/drm/i915/i915_perf.c | 223 ++
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
drivers/gpu/drm/i915/i915_reg.h | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_perf.c| 217 +
8 files changed, 492 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_perf.c
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 0987100c786b..8e63cffcabe0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -163,7 +163,8 @@
#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
-#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
+#define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -224,6 +225,7 @@
#define PIPE_CONTROL_CS_STALL(1<<20)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
+#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
#define PIPE_CONTROL_QW_WRITE(1<<14)
#define PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
#define PIPE_CONTROL_DEPTH_STALL (1<<13)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 802f516a3430..be4b263621c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -109,6 +109,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 277f31297f29..d463a28b7475 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3590,6 +3590,37 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+ const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
+
+ /*
+* This would lead to infinite waits as we're doing timestamp
+* difference on the CS with only 32bits.
+*/
+ if (val > mul_u32_u32(U32_MAX, clk))
+ return -EINVAL;
+
+ atomic64_set(>perf.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(>perf.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4340,6 +4371,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", _perf_noa_delay_fops},
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d79da167b6f0..6bc3fd37a2ec 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -198,6 +198,7 @@
[Intel-gfx] [PATCH 6/9] drm/i915/perf: execute OA configuration from command stream
From: Lionel Landwerlin
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke things from the CPU.
Since we have a command buffer prepared for the execbuffer side of
things, we can reuse that approach here too.
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
v3: Take global lock to pin global
v4: Create i915 request in emit_oa_config() to avoid deadlocks (Lionel)
v5: Move locking to the stream (Lionel)
v6: Move active reconfiguration request into i915_perf_stream (Lionel)
v7: Pin VMA outside request creation (Chris)
Lock VMA before move to active (Chris)
v8: Fix double free on stream->initial_oa_config_bo (Lionel)
Don't allow interruption when waiting on active config request
(Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 197 ---
1 file changed, 154 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 6bc3fd37a2ec..12cc47aece21 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1730,56 +1730,179 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
return 0;
err_unpin:
- __i915_vma_unpin(vma);
+ i915_vma_unpin_and_release(, 0);
err_unref:
i915_gem_object_put(bo);
return ret;
}
-static void config_oa_regs(struct intel_uncore *uncore,
- const struct i915_oa_reg *regs,
- u32 n_regs)
+static u32 *write_cs_mi_lri(u32 *cs,
+ const struct i915_oa_reg *reg_data,
+ u32 n_regs)
{
u32 i;
for (i = 0; i < n_regs; i++) {
- const struct i915_oa_reg *reg = regs + i;
+ if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
+ u32 n_lri = min_t(u32,
+ n_regs - i,
+ MI_LOAD_REGISTER_IMM_MAX_REGS);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
+ }
+ *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
+ *cs++ = reg_data[i].value;
+ }
+
+ return cs;
+}
+
+static int num_lri_dwords(int num_regs)
+{
+ int count = 0;
+
+ if (num_regs > 0) {
+ count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
+ count += num_regs * 2;
+ }
+
+ return count;
+}
+
+static struct i915_oa_config_bo *
+alloc_oa_config_buffer(struct i915_perf_stream *stream,
+ struct i915_oa_config *oa_config)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_oa_config_bo *oa_bo;
+ size_t config_length = 0;
+ u32 *cs;
+ int err;
+
+ oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
+ if (!oa_bo)
+ return ERR_PTR(-ENOMEM);
+
+ config_length += num_lri_dwords(oa_config->mux_regs_len);
+ config_length += num_lri_dwords(oa_config->b_counter_regs_len);
+ config_length += num_lri_dwords(oa_config->flex_regs_len);
+ config_length++; /* MI_BATCH_BUFFER_END */
+ config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
+
+ obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err_free;
+ }
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_oa_bo;
+ }
- intel_uncore_write(uncore, reg->addr, reg->value);
+ cs = write_cs_mi_lri(cs,
+oa_config->mux_regs,
+oa_config->mux_regs_len);
+ cs = write_cs_mi_lri(cs,
+oa_config->b_counter_regs,
+oa_config->b_counter_regs_len);
+ cs = write_cs_mi_lri(cs,
+oa_config->flex_regs,
+oa_config->flex_regs_len);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ oa_bo->vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
+ if (IS_ERR(oa_bo->vma)) {
+ err = PTR_ERR(oa_bo->vma);
+ goto err_oa_bo;
}
+
+ oa_bo->oa_config = i915_oa_config_get(oa_config);
+ llist_add(_bo->node, >oa_config_bos);
+
+ return oa_bo;
+
+err_oa_bo:
+ i915_gem_object_put(obj);
+err_free:
+ kfree(oa_bo);
+ return ERR_PTR(err);
}
-static void delay_after_mux(void)
+static struct
[Intel-gfx] [PATCH 4/9] drm/i915: add support for perf configuration queries
From: Lionel Landwerlin
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
v5: Drop lock when copying config content to userspace (Chris)
v6: Drop lock when copying config list to userspace (Chris)
Fix deadlock when calling i915_perf_get_oa_config() under
perf.metrics_lock (Lionel)
Add i915_oa_config_get() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 295 ++
include/uapi/drm/i915_drm.h | 62 ++-
3 files changed, 357 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f087a81a6b30..d79da167b6f0 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3473,8 +3473,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
GEM_BUG_ON(*arg != oa_config->id);
- sysfs_remove_group(perf->metrics_kobj,
- _config->sysfs_metric);
+ sysfs_remove_group(perf->metrics_kobj, _config->sysfs_metric);
idr_remove(>metrics_idr, *arg);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index abac5042da2b..6a68ecc7bb5f 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -7,6 +7,7 @@
#include
#include "i915_drv.h"
+#include "i915_perf.h"
#include "i915_query.h"
#include
@@ -140,10 +141,304 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+* We'll just put the number of registers, and won't copy the
+* register.
+*/
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg
*kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_perf_oa_config __user *user_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config));
+ struct drm_i915_perf_oa_config user_config;
+ struct i915_perf *perf = >perf;
+ struct i915_oa_config *oa_config;
+ char uuid[UUID_STRING_LEN + 1];
+ u64 config_id;
+ u32 flags, total_size;
+ int ret;
+
+ if (!perf->i915)
+ return -ENODEV;
+
+ total_size =
+ sizeof(struct drm_i915_query_perf_config) +
+ sizeof(struct drm_i915_perf_oa_config);
+
+ if (query_item->length == 0)
+ return total_size;
+
+ if (query_item->length < total_size) {
+
[Intel-gfx] [PATCH 2/9] drm/i915/perf: introduce a versioning of the i915-perf uapi
From: Lionel Landwerlin
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
drivers/gpu/drm/i915/i915_perf.c | 10 ++
drivers/gpu/drm/i915/i915_perf.h | 1 +
include/uapi/drm/i915_drm.h | 21 +
4 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index f4b3cbb1adce..ad33fbe90a28 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -5,6 +5,7 @@
#include "gt/intel_engine_user.h"
#include "i915_drv.h"
+#include "i915_perf.h"
int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
@@ -156,6 +157,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(i915)->has_coherent_ggtt;
break;
+ case I915_PARAM_PERF_REVISION:
+ value = i915_perf_ioctl_version();
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b28f2a269478..21e66c30c6cc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3665,3 +3665,13 @@ void i915_perf_fini(struct drm_i915_private *i915)
memset(>ops, 0, sizeof(perf->ops));
perf->i915 = NULL;
}
+
+/**
+ * i915_perf_ioctl_version - Version of the i915-perf subsystem
+ *
+ * This version number is used by userspace to detect available features.
+ */
+int i915_perf_ioctl_version(void)
+{
+ return 1;
+}
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index ff412fb0dbbf..295e33e8eef7 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -20,6 +20,7 @@ void i915_perf_init(struct drm_i915_private *i915);
void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
+int i915_perf_ioctl_version(void);
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 30c542144016..c50c712b3771 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -611,6 +611,13 @@ typedef struct drm_i915_irq_wait {
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
*/
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+
+/*
+ * Revision of the i915-perf uAPI. The value returned helps determine what
+ * i915-perf features are available. See drm_i915_perf_property_id.
+ */
+#define I915_PARAM_PERF_REVISION 54
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1844,23 +1851,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@@ -1870,6 +1885,8 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
@@ -1901,6 +1918,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@@ -1908,6 +1927,8 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
+ *
+ *
[Intel-gfx] [PATCH 1/9] drm/i915/perf: store the associated engine of a stream
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 28 +++---
drivers/gpu/drm/i915/i915_perf_types.h | 5 +
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..b28f2a269478 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -347,6 +348,7 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @engine: The engine (typically rcs0) being monitored by the OA unit
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +365,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -1205,7 +1209,7 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
int err;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- if (ce->engine->class != RENDER_CLASS)
+ if (ce->engine != stream->engine) /* first match! */
continue;
/*
@@ -2127,7 +2131,13 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
int format_size;
int ret;
- /* If the sysfs metrics/ directory wasn't registered for some
+ if (!props->engine) {
+ DRM_DEBUG("OA engine not specified\n");
+ return -EINVAL;
+ }
+
+ /*
+* If the sysfs metrics/ directory wasn't registered for some
* reason then don't let userspace try their luck with config
* IDs
*/
@@ -2146,7 +2156,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -ENODEV;
}
- /* To avoid the complexity of having to accurately filter
+ /*
+* To avoid the complexity of having to accurately filter
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
@@ -2164,6 +2175,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
format_size = perf->oa_formats[props->oa_format].size;
+ stream->engine = props->engine;
+
stream->sample_flags |= SAMPLE_OA_REPORT;
stream->sample_size += format_size;
@@ -2796,6 +2809,15 @@ static int read_properties_unlocked(struct i915_perf
*perf,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = intel_engine_lookup_user(perf->i915,
+I915_ENGINE_CLASS_RENDER,
+0);
+ if (!props->engine) {
+ DRM_DEBUG("No RENDER-capable engines\n");
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..82cd3b295037 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -140,6 +140,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+* @engine: Engine associated with this performance stream.
+*/
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on
SNB-BDW sprites (rev2)
URL : https://patchwork.freedesktop.org/series/67741/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14725_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14725_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14725_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@in-flight-1us:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_...@in-flight-1us.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_...@in-flight-1us.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_pl...@pixel-format-pipe-a-planes.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_pl...@pixel-format-pipe-a-planes.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@pixel-format-pipe-a-planes:
- {shard-tglb}: [PASS][5] -> [FAIL][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-tglb7/igt@kms_pl...@pixel-format-pipe-a-planes.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-tglb6/igt@kms_pl...@pixel-format-pipe-a-planes.html
* igt@kms_plane@pixel-format-pipe-c-planes:
- {shard-tglb}: NOTRUN -> [FAIL][7] +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-tglb1/igt@kms_pl...@pixel-format-pipe-c-planes.html
Known issues
Here are the changes found in Patchwork_14725_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [PASS][8] -> [FAIL][9] ([fdo#111925])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb1/igt@gem_...@in-flight-contexts-immediate.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb2/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +11 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#111325]) +1 similar
issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][14] -> [INCOMPLETE][15] ([fdo#103359] /
[fdo#108686] / [k.org#198133])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-glk8/igt@gem_tiled_swapp...@non-threaded.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-glk8/igt@gem_tiled_swapp...@non-threaded.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870]) +2
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-hsw8/igt@gem_userptr_bl...@sync-unmap-after-close.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-hsw2/igt@gem_userptr_bl...@sync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([fdo#108566]) +5
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-apl1/igt@gem_workarou...@suspend-resume-context.html
[21]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add feature flag for platforms with DRAM info
== Series Details ==
Series: drm/i915: Add feature flag for platforms with DRAM info
URL : https://patchwork.freedesktop.org/series/67801/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7045 -> Patchwork_14732
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/index.html
Known issues
Here are the changes found in Patchwork_14732 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@rcs0:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
* igt@i915_selftest@live_workarounds:
- fi-kbl-7500u: [PASS][5] -> [DMESG-FAIL][6] ([fdo#111926])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-kbl-7500u/igt@i915_selftest@live_workarounds.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-kbl-7500u/igt@i915_selftest@live_workarounds.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-hsw-4770r: [INCOMPLETE][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-hsw-4770r/igt@gem_close_r...@basic-threads.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-hsw-4770r/igt@gem_close_r...@basic-threads.html
* igt@gem_mmap@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-icl-u3/igt@gem_m...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-icl-u3/igt@gem_m...@basic.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-blb-e6850/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][13] ([fdo#109483]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) ->
[FAIL][16] ([fdo#111407])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7045/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111926]: https://bugs.freedesktop.org/show_bug.cgi?id=111926
Participating hosts (54 -> 44)
--
Missing(10): fi-ilk-m540 fi-bxt-dsi fi-tgl-u2 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7045 -> Patchwork_14732
CI-20190529: 20190529
CI_DRM_7045: 73de04406fdcb13a719003629b7e29ddf74a8036 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14732: ba252a7f82c76e4d42b678d8b81df483da3bde98 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ba252a7f82c7 drm/i915: Add feature flag for platforms with DRAM info
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14732/index.html
Re: [Intel-gfx] [PATCH 01/11] drm/i915/perf: Disable rc6 only while OA is enabled
On 09/10/2019 23:52, Chris Wilson wrote: Quoting Lionel Landwerlin (2019-10-09 21:46:56) Hmm... nope, sorry. We'll loose NOA configuration if you do that. And you'll have to rerun the oa config BO prior to enabling. Is that not worth it? Move the enable_metric_set/disable_metric_set to i915_perf_enable_locked as well? -Chris It takes some time to apply the configuration so not really worth it. Plus either you do perf queries and as soon as you're finished you shutdown OA, or you monitor the whole system and then you just can't have RC6 kick in. The only real use case of those enable/disable ioctl is to reset the head/tail register of the OA buffer because data head started overwriting the tail. -Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 0/3] CRTC background color
On Wed, Oct 9, 2019 at 1:34 PM Matt Roper wrote: > > The previous version of this series was posted in February here: > > https://lists.freedesktop.org/archives/dri-devel/2019-February/208068.html > > Right before we merged this in February Maarten noticed that we should > be setting up the initial property state in a CRTC reset function (which > didn't exist yet) instead of when the property was attached. Maarten > landed the CRTC reset functionality a week or two later, but I was busy > with travel and other work at the time, so revisiting and rebasing this > background color series fell through the cracks and I'm just getting > back to it now. > > Userspace consumer is chromeos; these are the links the ChromeOS folks > gave me back in February: > https://chromium-review.googlesource.com/c/chromium/src/+/1278858 > > https://chromium-review.googlesource.com/c/chromiumos/platform/drm-tests/+/1241436 Please note that the current state of the background color on Chrome OS side is that while the property plumbing landed, the property is currently not used by the compositor and no one is working on making that happen. The kernel patches have not landed on the ChromeOS kernel either. > > > IGT is still the same as posted in February: > https://lists.freedesktop.org/archives/igt-dev/2019-February/009637.html > > Cc: Maarten Lankhorst > > Matt Roper (3): > drm: Add CRTC background color property > drm/i915/gen9+: Add support for pipe background color > drm/i915: Add background color hardware readout and state check > > drivers/gpu/drm/drm_atomic_state_helper.c| 4 +- > drivers/gpu/drm/drm_atomic_uapi.c| 4 ++ > drivers/gpu/drm/drm_blend.c | 35 +-- > drivers/gpu/drm/drm_mode_config.c| 6 +++ > drivers/gpu/drm/i915/display/intel_color.c | 11 +++-- > drivers/gpu/drm/i915/display/intel_display.c | 45 > drivers/gpu/drm/i915/i915_debugfs.c | 9 > include/drm/drm_blend.h | 1 + > include/drm/drm_crtc.h | 12 ++ > include/drm/drm_mode_config.h| 5 +++ > include/uapi/drm/drm_mode.h | 28 > 11 files changed, 153 insertions(+), 7 deletions(-) > > -- > 2.21.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/11] drm/i915/perf: Disable rc6 only while OA is enabled
Quoting Lionel Landwerlin (2019-10-09 21:46:56) > Hmm... nope, sorry. > > We'll loose NOA configuration if you do that. > And you'll have to rerun the oa config BO prior to enabling. Is that not worth it? Move the enable_metric_set/disable_metric_set to i915_perf_enable_locked as well? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/perf: implement active wait for noa configurations
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
v4: Fix save/restore helpers (Umesh)
v5: Move noa_wait from drm_i915_private to i915_perf_stream (Lionel)
v6: Add missing struct declarations in i915_perf.h
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 32 +++
drivers/gpu/drm/i915/i915_perf.c | 223 ++
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
drivers/gpu/drm/i915/i915_reg.h | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_perf.c| 217 +
8 files changed, 492 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_perf.c
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 0987100c786b..8e63cffcabe0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -163,7 +163,8 @@
#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
-#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
+#define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -224,6 +225,7 @@
#define PIPE_CONTROL_CS_STALL(1<<20)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
+#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
#define PIPE_CONTROL_QW_WRITE(1<<14)
#define PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
#define PIPE_CONTROL_DEPTH_STALL (1<<13)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 802f516a3430..be4b263621c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -109,6 +109,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 277f31297f29..d463a28b7475 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3590,6 +3590,37 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+ const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
+
+ /*
+* This would lead to infinite waits as we're doing timestamp
+* difference on the CS with only 32bits.
+*/
+ if (val > mul_u32_u32(U32_MAX, clk))
+ return -EINVAL;
+
+ atomic64_set(>perf.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(>perf.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4340,6 +4371,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", _perf_noa_delay_fops},
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5e14dd6c4c78..6bf02e4c5f09 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -198,6 +198,7 @@
Re: [Intel-gfx] [PATCH 01/11] drm/i915/perf: Disable rc6 only while OA is enabled
Hmm... nope, sorry.
We'll loose NOA configuration if you do that.
And you'll have to rerun the oa config BO prior to enabling.
-Lionel
On 09/10/2019 23:36, Chris Wilson wrote:
Move rpm_get and forcewake_get into the perf enable (and corresponding
the puts into the disable) so that we only prevent powermaangement while
we OA is engaged.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 49 --
drivers/gpu/drm/i915/i915_perf_types.h | 12 +++
2 files changed, 26 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..6fa5c9dc38d3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1348,9 +1348,6 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
free_oa_buffer(stream);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
-
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -2192,21 +2189,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
goto err_config;
}
- /* PRM - observability performance counters:
-*
-* OACONTROL, performance counter enable, note:
-*
-* "When this bit is set, in order to have coherent counts,
-* RC6 power state and trunk clock gating must be disabled.
-* This can be achieved by programming MMIO registers as
-* 0xA094=0 and 0xA090[31]=1"
-*
-* In our case we are expecting that taking pm + FORCEWAKE
-* references will effectively disable RC6.
-*/
- stream->wakeref = intel_runtime_pm_get(stream->gt->uncore->rpm);
- intel_uncore_forcewake_get(stream->gt->uncore, FORCEWAKE_ALL);
-
ret = alloc_oa_buffer(stream);
if (ret)
goto err_oa_buf_alloc;
@@ -2237,9 +2219,6 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
err_oa_buf_alloc:
put_oa_config(stream->oa_config);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
-
err_config:
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -2473,8 +2452,21 @@ static void i915_perf_enable_locked(struct
i915_perf_stream *stream)
if (stream->enabled)
return;
- /* Allow stream->ops->enable() to refer to this */
- stream->enabled = true;
+ /*
+* PRM - observability performance counters:
+*
+* OACONTROL, performance counter enable, note:
+*
+* "When this bit is set, in order to have coherent counts,
+* RC6 power state and trunk clock gating must be disabled.
+* This can be achieved by programming MMIO registers as
+* 0xA094=0 and 0xA090[31]=1"
+*
+* In our case we are expecting that taking pm + FORCEWAKE
+* references will effectively disable RC6.
+*/
+ stream->enabled = intel_runtime_pm_get(stream->gt->uncore->rpm);
+ intel_uncore_forcewake_get(stream->gt->uncore, FORCEWAKE_ALL);
if (stream->ops->enable)
stream->ops->enable(stream);
@@ -2496,14 +2488,17 @@ static void i915_perf_enable_locked(struct
i915_perf_stream *stream)
*/
static void i915_perf_disable_locked(struct i915_perf_stream *stream)
{
- if (!stream->enabled)
- return;
+ intel_wakeref_t wakeref;
- /* Allow stream->ops->disable() to refer to this */
- stream->enabled = false;
+ wakeref = fetch_and_zero(>enabled);
+ if (!wakeref)
+ return;
if (stream->ops->disable)
stream->ops->disable(stream);
+
+ intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
+ intel_runtime_pm_put(stream->gt->uncore->rpm, wakeref);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..edfd64732704 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -137,8 +137,11 @@ struct i915_perf_stream {
/**
* @wakeref: As we keep the device awake while the perf stream is
* active, we track our runtime pm reference for later release.
+* Also indicates whether the stream is currently enabled, considering
+* whether the stream was opened in a disabled state and based
+* on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
*/
- intel_wakeref_t wakeref;
+ intel_wakeref_t enabled;
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
@@ -160,13 +163,6 @@ struct i915_perf_stream {
*/
struct i915_gem_context *ctx;
- /**
-* @enabled: Whether the
[Intel-gfx] [PATCH] drm/i915/execlists: Leave tell-tales as to why pending[] is bad
Before we BUG out with bad pending state, leave a telltale as to which
test failed.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 30 -
drivers/gpu/drm/i915/i915_gem.h | 8
2 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7ea58335f04c..da3d34b9d284 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1138,25 +1138,45 @@ assert_pending_valid(const struct
intel_engine_execlists *execlists,
trace_ports(execlists, msg, execlists->pending);
- if (!execlists->pending[0])
+ if (!execlists->pending[0]) {
+ GEM_TRACE_ERR("Nothing pending for promotion!\n");
return false;
+ }
- if (execlists->pending[execlists_num_ports(execlists)])
+ if (execlists->pending[execlists_num_ports(execlists)]) {
+ GEM_TRACE_ERR("Excess pending[%d] for promotion!\n",
+ execlists_num_ports(execlists));
return false;
+ }
for (port = execlists->pending; (rq = *port); port++) {
- if (ce == rq->hw_context)
+ if (ce == rq->hw_context) {
+ GEM_TRACE_ERR("Duplicate context in pending[%zd]\n",
+ port - execlists->pending);
return false;
+ }
ce = rq->hw_context;
if (i915_request_completed(rq))
continue;
- if (i915_active_is_idle(>active))
+ if (i915_active_is_idle(>active)) {
+ GEM_TRACE_ERR("Inactive context in pending[%zd]\n",
+ port - execlists->pending);
+ return false;
+ }
+
+ if (!i915_vma_is_pinned(ce->state)) {
+ GEM_TRACE_ERR("Unpinned context in pending[%zd]\n",
+ port - execlists->pending);
return false;
+ }
- if (!i915_vma_is_pinned(ce->state))
+ if (!i915_vma_is_pinned(ce->ring->vma)) {
+ GEM_TRACE_ERR("Unpinned ringbuffer in pending[%zd]\n",
+ port - execlists->pending);
return false;
+ }
}
return ce;
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 6795f1daa3d5..63dab3765106 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -37,10 +37,8 @@ struct drm_i915_private;
#define GEM_SHOW_DEBUG() (drm_debug & DRM_UT_DRIVER)
#define GEM_BUG_ON(condition) do { if (unlikely((condition))) {\
- pr_err("%s:%d GEM_BUG_ON(%s)\n", \
- __func__, __LINE__, __stringify(condition)); \
- GEM_TRACE("%s:%d GEM_BUG_ON(%s)\n", \
- __func__, __LINE__, __stringify(condition)); \
+ GEM_TRACE_ERR("%s:%d GEM_BUG_ON(%s)\n", \
+ __func__, __LINE__, __stringify(condition)); \
BUG(); \
} \
} while(0)
@@ -66,11 +64,13 @@ struct drm_i915_private;
#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
+#define GEM_TRACE_ERR(...) do { pr_err(__VA_ARGS__);
trace_printk(__VA_ARGS__); } while (0)
#define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
#define GEM_TRACE_DUMP_ON(expr) \
do { if (expr) ftrace_dump(DUMP_ALL); } while (0)
#else
#define GEM_TRACE(...) do { } while (0)
+#define GEM_TRACE_ERR(...) do { } while (0)
#define GEM_TRACE_DUMP() do { } while (0)
#define GEM_TRACE_DUMP_ON(expr) BUILD_BUG_ON_INVALID(expr)
#endif
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/11] drm/i915: add support for perf configuration queries
From: Lionel Landwerlin
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
v5: Drop lock when copying config content to userspace (Chris)
v6: Drop lock when copying config list to userspace (Chris)
Fix deadlock when calling i915_perf_get_oa_config() under
perf.metrics_lock (Lionel)
Add i915_oa_config_get() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 295 ++
include/uapi/drm/i915_drm.h | 62 ++-
3 files changed, 357 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 8c06f42720d6..5e14dd6c4c78 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3465,8 +3465,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
GEM_BUG_ON(*arg != oa_config->id);
- sysfs_remove_group(perf->metrics_kobj,
- _config->sysfs_metric);
+ sysfs_remove_group(perf->metrics_kobj, _config->sysfs_metric);
idr_remove(>metrics_idr, *arg);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index abac5042da2b..6a68ecc7bb5f 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -7,6 +7,7 @@
#include
#include "i915_drv.h"
+#include "i915_perf.h"
#include "i915_query.h"
#include
@@ -140,10 +141,304 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+* We'll just put the number of registers, and won't copy the
+* register.
+*/
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg
*kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_perf_oa_config __user *user_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config));
+ struct drm_i915_perf_oa_config user_config;
+ struct i915_perf *perf = >perf;
+ struct i915_oa_config *oa_config;
+ char uuid[UUID_STRING_LEN + 1];
+ u64 config_id;
+ u32 flags, total_size;
+ int ret;
+
+ if (!perf->i915)
+ return -ENODEV;
+
+ total_size =
+ sizeof(struct drm_i915_query_perf_config) +
+ sizeof(struct drm_i915_perf_oa_config);
+
+ if (query_item->length == 0)
+ return total_size;
+
+ if (query_item->length < total_size) {
+
[Intel-gfx] [PATCH 05/11] drm/i915/perf: allow for CS OA configs to be created lazily
From: Lionel Landwerlin
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
v2: No need for locking on object OA config object creation (Chris)
Flush cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
v4: Fix oa config unref/put when not found (Lionel)
v5: Allocate BOs for configurations on the stream instead of globally
(Lionel)
v6: Fix 64bit division (Chris)
v7: Store allocated config BOs into the stream (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 107 +++
drivers/gpu/drm/i915/i915_perf.h | 24 +
drivers/gpu/drm/i915/i915_perf_types.h | 23 ++--
4 files changed, 102 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index b0227ab2fe1b..0987100c786b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -138,6 +138,7 @@
/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
#define MI_LRI_CS_MMIO (1<<19)
#define MI_LRI_FORCE_POSTED (1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT(1<<22)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index bf99eaf2315f..8c06f42720d6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -369,52 +369,52 @@ struct perf_open_properties {
struct intel_engine_cs *engine;
};
+struct i915_oa_config_bo {
+ struct llist_node node;
+
+ struct i915_oa_config *oa_config;
+ struct i915_vma *vma;
+};
+
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
-static void free_oa_config(struct i915_oa_config *oa_config)
+void i915_oa_config_release(struct kref *ref)
{
+ struct i915_oa_config *oa_config =
+ container_of(ref, typeof(*oa_config), ref);
+
if (!PTR_ERR(oa_config->flex_regs))
kfree(oa_config->flex_regs);
if (!PTR_ERR(oa_config->b_counter_regs))
kfree(oa_config->b_counter_regs);
if (!PTR_ERR(oa_config->mux_regs))
kfree(oa_config->mux_regs);
- kfree(oa_config);
-}
-
-static void put_oa_config(struct i915_oa_config *oa_config)
-{
- if (!atomic_dec_and_test(_config->ref_count))
- return;
- free_oa_config(oa_config);
+ kfree_rcu(oa_config, rcu);
}
-static int get_oa_config(struct i915_perf *perf,
-int metrics_set,
-struct i915_oa_config **out_config)
+struct i915_oa_config *
+i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
{
- int ret;
-
- if (metrics_set == 1) {
- *out_config = >test_config;
- atomic_inc(>test_config.ref_count);
- return 0;
- }
-
- ret = mutex_lock_interruptible(>metrics_lock);
- if (ret)
- return ret;
+ struct i915_oa_config *oa_config;
- *out_config = idr_find(>metrics_idr, metrics_set);
- if (!*out_config)
- ret = -EINVAL;
+ rcu_read_lock();
+ if (metrics_set == 1)
+ oa_config = >test_config;
else
- atomic_inc(&(*out_config)->ref_count);
+ oa_config = idr_find(>metrics_idr, metrics_set);
+ if (oa_config)
+ oa_config = i915_oa_config_get(oa_config);
+ rcu_read_unlock();
- mutex_unlock(>metrics_lock);
+ return oa_config;
+}
- return ret;
+static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
+{
+ i915_oa_config_put(oa_bo->oa_config);
+ i915_vma_put(oa_bo->vma);
+ kfree(oa_bo);
}
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
@@ -1337,6 +1337,16 @@ free_oa_buffer(struct i915_perf_stream *stream)
stream->oa_buffer.vaddr = NULL;
}
+static void
+free_oa_configs(struct i915_perf_stream *stream)
+{
+ struct i915_oa_config_bo *oa_bo, *tmp;
+
+ i915_oa_config_put(stream->oa_config);
+ llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
+ free_oa_config_bo(oa_bo);
+}
+
static void
[Intel-gfx] [PATCH 10/11] drm/i915/perf: allow holding preemption on filtered ctx
From: Lionel Landwerlin
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of command buffer concept meant that
queries' duration could span multiple command buffers.
With that restriction gone in Vulkan, we would like to simplify
measuring performance just by measuring the deltas between the counter
snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
more complex scheme we currently have in the GL driver, using 2
MI_RECORD_PERF_COUNT commands and doing some post processing on the
stream of OA reports, coming from the global OA buffer, to remove any
unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
Disabling preemption only apply to a single context with which want to
query performance counters for and is considered a privileged
operation, by default protected by CAP_SYS_ADMIN. It is possible to
enable it for a normal user by disabling the paranoid stream setting.
v2: Store preemption setting in intel_context (Chris)
v3: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
v5: Add nopreempt flag on gem context and always flag requests
appropriately, regarless of OA reconfiguration.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 3 ++
drivers/gpu/drm/i915/i915_perf.c | 34 +--
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
include/uapi/drm/i915_drm.h | 11 ++
6 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 9234586830d1..cfe80590f0ed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -114,6 +114,24 @@ i915_gem_context_clear_user_engines(struct
i915_gem_context *ctx)
clear_bit(CONTEXT_USER_ENGINES, >flags);
}
+static inline bool
+i915_gem_context_nopreempt(const struct i915_gem_context *ctx)
+{
+ return test_bit(CONTEXT_NOPREEMPT, >flags);
+}
+
+static inline void
+i915_gem_context_set_nopreempt(struct i915_gem_context *ctx)
+{
+ set_bit(CONTEXT_NOPREEMPT, >flags);
+}
+
+static inline void
+i915_gem_context_clear_nopreempt(struct i915_gem_context *ctx)
+{
+ clear_bit(CONTEXT_NOPREEMPT, >flags);
+}
+
static inline bool i915_gem_context_is_kernel(struct i915_gem_context *ctx)
{
return !ctx->file_priv;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ab8e1367dfc8..fe97b8ba4fda 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -146,6 +146,7 @@ struct i915_gem_context {
#define CONTEXT_CLOSED 1
#define CONTEXT_FORCE_SINGLE_SUBMISSION2
#define CONTEXT_USER_ENGINES 3
+#define CONTEXT_NOPREEMPT 4
struct mutex mutex;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 98816c35ffc3..e96901888323 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2077,6 +2077,9 @@ static int eb_submit(struct i915_execbuffer *eb)
if (err)
return err;
+ if (i915_gem_context_nopreempt(eb->gem_context))
+ eb->request->flags |= I915_REQUEST_NOPREEMPT;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 93b7588e491c..d2f989ed1793 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -344,6 +344,8 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* struct perf_open_properties - for validated properties given to open a
stream
* @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
* @single_context: Whether a single or all gpu contexts should be monitored
+ * @hold_preemption: Whether the preemption is disabled for the filtered
+ * context
* @ctx_handle: A gem ctx handle for use with @single_context
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
@@ -359,6 +361,7 @@ struct perf_open_properties {
u32 sample_flags;
u64 single_context:1;
+ u64 hold_preemption:1;
u64 ctx_handle;
/* OA sampling state */
@@ -2503,6 +2506,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
if
[Intel-gfx] [PATCH 09/11] drm/i915/perf: Allow dynamic reconfiguration of the OA stream
From: Lionel Landwerlin
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the stream asynchronously on
the GPU in between and ordered with execbuffer calls.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 34 +++-
include/uapi/drm/i915_drm.h | 10 ++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9f2d92b9d22d..93b7588e491c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2846,6 +2846,28 @@ static void i915_perf_disable_locked(struct
i915_perf_stream *stream)
intel_runtime_pm_put(stream->gt->uncore->rpm, wakeref);
}
+static int i915_perf_config_locked(struct i915_perf_stream *stream,
+ unsigned long metrics_set)
+{
+ struct i915_oa_config *config;
+ int err = 0;
+
+ config = i915_perf_get_oa_config(stream->perf, metrics_set);
+ if (!config)
+ return -EINVAL;
+
+ if (config != stream->oa_config) {
+ if (stream->pinned_ctx)
+ err = emit_oa_config(stream, stream->pinned_ctx);
+ if (err == 0)
+ config = xchg(>oa_config, config);
+ }
+
+ i915_oa_config_put(config);
+
+ return err;
+}
+
/**
* i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
* @stream: An i915 perf stream
@@ -2869,6 +2891,8 @@ static long i915_perf_ioctl_locked(struct
i915_perf_stream *stream,
case I915_PERF_IOCTL_DISABLE:
i915_perf_disable_locked(stream);
return 0;
+ case I915_PERF_IOCTL_CONFIG:
+ return i915_perf_config_locked(stream, arg);
}
return -EINVAL;
@@ -4007,7 +4031,15 @@ void i915_perf_fini(struct drm_i915_private *i915)
*/
int i915_perf_ioctl_version(void)
{
- return 1;
+ /*
+* 1: Initial version
+* I915_PERF_IOCTL_ENABLE
+* I915_PERF_IOCTL_DISABLE
+*
+* 2: Added runtime modification of OA config.
+* I915_PERF_IOCTL_CONFIG
+*/
+ return 2;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0c7b2815fbf1..5e66f7c60261 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1932,6 +1932,16 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_DISABLE_IO('i', 0x1)
+/**
+ * Change metrics_set captured by a stream.
+ *
+ * Will not take effect until the stream is restart, or upon the next
+ * execbuf when attached to a specific context.
+ *
+ * This ioctl is available in perf revision 2.
+ */
+#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
+
/**
* Common to all i915 perf records
*/
--
2.23.0
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[Intel-gfx] [PATCH 03/11] drm/i915/perf: store the associated engine of a stream
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 28 +++---
drivers/gpu/drm/i915/i915_perf_types.h | 5 +
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 147d55e5fc8d..b628e4626e09 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -347,6 +348,7 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @engine: The engine (typically rcs0) being monitored by the OA unit
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +365,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -1205,7 +1209,7 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
int err;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- if (ce->engine->class != RENDER_CLASS)
+ if (ce->engine != stream->engine) /* first match! */
continue;
/*
@@ -2122,7 +2126,13 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
int format_size;
int ret;
- /* If the sysfs metrics/ directory wasn't registered for some
+ if (!props->engine) {
+ DRM_DEBUG("OA engine not specified\n");
+ return -EINVAL;
+ }
+
+ /*
+* If the sysfs metrics/ directory wasn't registered for some
* reason then don't let userspace try their luck with config
* IDs
*/
@@ -2141,7 +2151,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -ENODEV;
}
- /* To avoid the complexity of having to accurately filter
+ /*
+* To avoid the complexity of having to accurately filter
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
@@ -2159,6 +2170,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
format_size = perf->oa_formats[props->oa_format].size;
+ stream->engine = props->engine;
+
stream->sample_flags |= SAMPLE_OA_REPORT;
stream->sample_size += format_size;
@@ -2788,6 +2801,15 @@ static int read_properties_unlocked(struct i915_perf
*perf,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = intel_engine_lookup_user(perf->i915,
+I915_ENGINE_CLASS_RENDER,
+0);
+ if (!props->engine) {
+ DRM_DEBUG("No RENDER-capable engines\n");
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index edfd64732704..8cfe598352a8 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -143,6 +143,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t enabled;
+ /**
+* @engine: Engine associated with this performance stream.
+*/
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
--
2.23.0
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[Intel-gfx] [PATCH 02/11] drm/i915/perf: Tidy up unpinning the oa_context
Rename the function for consistency, and remove the redundant test.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 6fa5c9dc38d3..147d55e5fc8d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1304,13 +1304,13 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
}
/**
- * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
+ * put_oa_context - counterpart to oa_get_render_ctx_id releases hold
* @stream: An i915-perf stream opened for OA metrics
*
* In case anything needed doing to ensure the context HW ID would remain valid
* for the lifetime of the stream, then that can be undone here.
*/
-static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
+static void put_oa_context(struct i915_perf_stream *stream)
{
struct intel_context *ce;
@@ -1347,9 +1347,7 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
-
- if (stream->ctx)
- oa_put_render_ctx_id(stream);
+ put_oa_context(stream);
put_oa_config(stream->oa_config);
@@ -2220,8 +2218,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
put_oa_config(stream->oa_config);
err_config:
- if (stream->ctx)
- oa_put_render_ctx_id(stream);
+ put_oa_context(stream);
return ret;
}
--
2.23.0
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[Intel-gfx] [PATCH 11/11] drm/i915/execlists: Prevent merging requests with conflicting flags
We set out-of-bound parameters inside the i915_requests.flags field,
such as disabling preemption or marking the end-of-context. We should
not coalesce consecutive requests if they have differing instructions
as we only inspect the last active request in a context. Thus if we
allow a later request to be merged into the same execution context, it
will mask any of the earlier flags.
References: 2a98f4e65bba ("drm/i915: add infrastructure to hold off preemption
on a request")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7ea58335f04c..d0687a94c8d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1233,6 +1233,9 @@ static bool can_merge_rq(const struct i915_request *prev,
if (i915_request_completed(next))
return true;
+ if (unlikely(prev->flags ^ next->flags) & I915_REQUEST_NOPREEMPT)
+ return false;
+
if (!can_merge_ctx(prev->hw_context, next->hw_context))
return false;
--
2.23.0
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[Intel-gfx] [PATCH 01/11] drm/i915/perf: Disable rc6 only while OA is enabled
Move rpm_get and forcewake_get into the perf enable (and corresponding
the puts into the disable) so that we only prevent powermaangement while
we OA is engaged.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 49 --
drivers/gpu/drm/i915/i915_perf_types.h | 12 +++
2 files changed, 26 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..6fa5c9dc38d3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1348,9 +1348,6 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
free_oa_buffer(stream);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
-
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -2192,21 +2189,6 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
goto err_config;
}
- /* PRM - observability performance counters:
-*
-* OACONTROL, performance counter enable, note:
-*
-* "When this bit is set, in order to have coherent counts,
-* RC6 power state and trunk clock gating must be disabled.
-* This can be achieved by programming MMIO registers as
-* 0xA094=0 and 0xA090[31]=1"
-*
-* In our case we are expecting that taking pm + FORCEWAKE
-* references will effectively disable RC6.
-*/
- stream->wakeref = intel_runtime_pm_get(stream->gt->uncore->rpm);
- intel_uncore_forcewake_get(stream->gt->uncore, FORCEWAKE_ALL);
-
ret = alloc_oa_buffer(stream);
if (ret)
goto err_oa_buf_alloc;
@@ -2237,9 +2219,6 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
err_oa_buf_alloc:
put_oa_config(stream->oa_config);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
-
err_config:
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -2473,8 +2452,21 @@ static void i915_perf_enable_locked(struct
i915_perf_stream *stream)
if (stream->enabled)
return;
- /* Allow stream->ops->enable() to refer to this */
- stream->enabled = true;
+ /*
+* PRM - observability performance counters:
+*
+* OACONTROL, performance counter enable, note:
+*
+* "When this bit is set, in order to have coherent counts,
+* RC6 power state and trunk clock gating must be disabled.
+* This can be achieved by programming MMIO registers as
+* 0xA094=0 and 0xA090[31]=1"
+*
+* In our case we are expecting that taking pm + FORCEWAKE
+* references will effectively disable RC6.
+*/
+ stream->enabled = intel_runtime_pm_get(stream->gt->uncore->rpm);
+ intel_uncore_forcewake_get(stream->gt->uncore, FORCEWAKE_ALL);
if (stream->ops->enable)
stream->ops->enable(stream);
@@ -2496,14 +2488,17 @@ static void i915_perf_enable_locked(struct
i915_perf_stream *stream)
*/
static void i915_perf_disable_locked(struct i915_perf_stream *stream)
{
- if (!stream->enabled)
- return;
+ intel_wakeref_t wakeref;
- /* Allow stream->ops->disable() to refer to this */
- stream->enabled = false;
+ wakeref = fetch_and_zero(>enabled);
+ if (!wakeref)
+ return;
if (stream->ops->disable)
stream->ops->disable(stream);
+
+ intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
+ intel_runtime_pm_put(stream->gt->uncore->rpm, wakeref);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..edfd64732704 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -137,8 +137,11 @@ struct i915_perf_stream {
/**
* @wakeref: As we keep the device awake while the perf stream is
* active, we track our runtime pm reference for later release.
+* Also indicates whether the stream is currently enabled, considering
+* whether the stream was opened in a disabled state and based
+* on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
*/
- intel_wakeref_t wakeref;
+ intel_wakeref_t enabled;
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
@@ -160,13 +163,6 @@ struct i915_perf_stream {
*/
struct i915_gem_context *ctx;
- /**
-* @enabled: Whether the stream is currently enabled, considering
-* whether the stream was opened in a disabled state and based
-* on `I915_PERF_IOCTL_ENABLE` and
[Intel-gfx] [PATCH 07/11] drm/i915/perf: implement active wait for noa configurations
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
v4: Fix save/restore helpers (Umesh)
v5: Move noa_wait from drm_i915_private to i915_perf_stream (Lionel)
v6: Add missing struct declarations in i915_perf.h
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 32 +++
drivers/gpu/drm/i915/i915_perf.c | 223 ++
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
drivers/gpu/drm/i915/i915_reg.h | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 275 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 0987100c786b..8e63cffcabe0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -163,7 +163,8 @@
#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
-#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
+#define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -224,6 +225,7 @@
#define PIPE_CONTROL_CS_STALL(1<<20)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
+#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
#define PIPE_CONTROL_QW_WRITE(1<<14)
#define PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
#define PIPE_CONTROL_DEPTH_STALL (1<<13)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 802f516a3430..be4b263621c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -109,6 +109,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 277f31297f29..d463a28b7475 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3590,6 +3590,37 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+ const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
+
+ /*
+* This would lead to infinite waits as we're doing timestamp
+* difference on the CS with only 32bits.
+*/
+ if (val > mul_u32_u32(U32_MAX, clk))
+ return -EINVAL;
+
+ atomic64_set(>perf.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(>perf.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4340,6 +4371,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", _perf_noa_delay_fops},
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5e14dd6c4c78..6bf02e4c5f09 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -198,6 +198,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_gt.h"
#include
[Intel-gfx] [PATCH 08/11] drm/i915/perf: execute OA configuration from command stream
From: Lionel Landwerlin
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke things from the CPU.
Since we have a command buffer prepared for the execbuffer side of
things, we can reuse that approach here too.
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
v3: Take global lock to pin global
v4: Create i915 request in emit_oa_config() to avoid deadlocks (Lionel)
v5: Move locking to the stream (Lionel)
v6: Move active reconfiguration request into i915_perf_stream (Lionel)
v7: Pin VMA outside request creation (Chris)
Lock VMA before move to active (Chris)
v8: Fix double free on stream->initial_oa_config_bo (Lionel)
Don't allow interruption when waiting on active config request
(Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 201 ---
1 file changed, 155 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 6bf02e4c5f09..9f2d92b9d22d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1725,56 +1725,179 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
return 0;
err_unpin:
- __i915_vma_unpin(vma);
+ i915_vma_unpin_and_release(, 0);
err_unref:
i915_gem_object_put(bo);
return ret;
}
-static void config_oa_regs(struct intel_uncore *uncore,
- const struct i915_oa_reg *regs,
- u32 n_regs)
+static u32 *write_cs_mi_lri(u32 *cs,
+ const struct i915_oa_reg *reg_data,
+ u32 n_regs)
{
u32 i;
for (i = 0; i < n_regs; i++) {
- const struct i915_oa_reg *reg = regs + i;
+ if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
+ u32 n_lri = min_t(u32,
+ n_regs - i,
+ MI_LOAD_REGISTER_IMM_MAX_REGS);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
+ }
+ *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
+ *cs++ = reg_data[i].value;
+ }
+
+ return cs;
+}
+
+static int num_lri_dwords(int num_regs)
+{
+ int count = 0;
+
+ if (num_regs > 0) {
+ count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
+ count += num_regs * 2;
+ }
+
+ return count;
+}
+
+static struct i915_oa_config_bo *
+alloc_oa_config_buffer(struct i915_perf_stream *stream,
+ struct i915_oa_config *oa_config)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_oa_config_bo *oa_bo;
+ size_t config_length = 0;
+ u32 *cs;
+ int err;
- intel_uncore_write(uncore, reg->addr, reg->value);
+ oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
+ if (!oa_bo)
+ return ERR_PTR(-ENOMEM);
+
+ config_length += num_lri_dwords(oa_config->mux_regs_len);
+ config_length += num_lri_dwords(oa_config->b_counter_regs_len);
+ config_length += num_lri_dwords(oa_config->flex_regs_len);
+ config_length++; /* MI_BATCH_BUFFER_END */
+ config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
+
+ obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err_free;
+ }
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_oa_bo;
}
+
+ cs = write_cs_mi_lri(cs,
+oa_config->mux_regs,
+oa_config->mux_regs_len);
+ cs = write_cs_mi_lri(cs,
+oa_config->b_counter_regs,
+oa_config->b_counter_regs_len);
+ cs = write_cs_mi_lri(cs,
+oa_config->flex_regs,
+oa_config->flex_regs_len);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ oa_bo->vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
+ if (IS_ERR(oa_bo->vma)) {
+ err = PTR_ERR(oa_bo->vma);
+ goto err_oa_bo;
+ }
+
+ oa_bo->oa_config = i915_oa_config_get(oa_config);
+ llist_add(_bo->node, >oa_config_bos);
+
+ return oa_bo;
+
+err_oa_bo:
+ i915_gem_object_put(obj);
+err_free:
+ kfree(oa_bo);
+ return ERR_PTR(err);
}
-static void delay_after_mux(void)
+static struct
[Intel-gfx] [PATCH 04/11] drm/i915/perf: introduce a versioning of the i915-perf uapi
From: Lionel Landwerlin
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
drivers/gpu/drm/i915/i915_perf.c | 10 ++
drivers/gpu/drm/i915/i915_perf.h | 1 +
include/uapi/drm/i915_drm.h | 21 +
4 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index f4b3cbb1adce..ad33fbe90a28 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -5,6 +5,7 @@
#include "gt/intel_engine_user.h"
#include "i915_drv.h"
+#include "i915_perf.h"
int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
@@ -156,6 +157,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(i915)->has_coherent_ggtt;
break;
+ case I915_PARAM_PERF_REVISION:
+ value = i915_perf_ioctl_version();
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b628e4626e09..bf99eaf2315f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3657,3 +3657,13 @@ void i915_perf_fini(struct drm_i915_private *i915)
memset(>ops, 0, sizeof(perf->ops));
perf->i915 = NULL;
}
+
+/**
+ * i915_perf_ioctl_version - Version of the i915-perf subsystem
+ *
+ * This version number is used by userspace to detect available features.
+ */
+int i915_perf_ioctl_version(void)
+{
+ return 1;
+}
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index ff412fb0dbbf..295e33e8eef7 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -20,6 +20,7 @@ void i915_perf_init(struct drm_i915_private *i915);
void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
+int i915_perf_ioctl_version(void);
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 30c542144016..c50c712b3771 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -611,6 +611,13 @@ typedef struct drm_i915_irq_wait {
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
*/
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+
+/*
+ * Revision of the i915-perf uAPI. The value returned helps determine what
+ * i915-perf features are available. See drm_i915_perf_property_id.
+ */
+#define I915_PARAM_PERF_REVISION 54
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1844,23 +1851,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@@ -1870,6 +1885,8 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
@@ -1901,6 +1918,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@@ -1908,6 +1927,8 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
+ *
+ *
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Protect peeking at execlists->active (rev4)
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Protect peeking at
execlists->active (rev4)
URL : https://patchwork.freedesktop.org/series/67782/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7044 -> Patchwork_14731
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/index.html
Known issues
Here are the changes found in Patchwork_14731 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-cfl-8109u: [PASS][3] -> [INCOMPLETE][4] ([fdo#110977])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
Possible fixes
* igt@gem_ctx_param@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/fi-icl-u3/igt@gem_ctx_pa...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/fi-icl-u3/igt@gem_ctx_pa...@basic.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7044/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110977]: https://bugs.freedesktop.org/show_bug.cgi?id=110977
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111833]: https://bugs.freedesktop.org/show_bug.cgi?id=111833
Participating hosts (54 -> 46)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7044 -> Patchwork_14731
CI-20190529: 20190529
CI_DRM_7044: bb25359d0ab2e524333673e26a47fe392c831feb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14731: a6298b5c9029e8cbcc0be173a3b94f5c8fb99c02 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a6298b5c9029 drm/i915/gt: execlists->active is serialised by the tasklet
84b136f342ca drm/i915/execlists: Protect peeking at execlists->active
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14731/index.html
___
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Re: [Intel-gfx] [PATCH] drm/i915/cml: Add second PCH ID for CMP
On Wed, Oct 09, 2019 at 01:00:07PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 09, 2019 at 10:29:43AM -0700, Matt Roper wrote:
> > On Wed, Oct 09, 2019 at 10:03:31AM +0300, Timo Aaltonen wrote:
> > > On 17.9.2019 2.32, Matt Roper wrote:
> > > > The CMP PCH ID we have in the driver is correct for the CML-U machines
> > > > we have
> > > > in our CI system, but the CML-S and CML-H CI machines appear to use a
> > > > different PCH ID, leading our driver to detect no PCH for them.
> > > >
> > > > Cc: Rodrigo Vivi
> > > > Cc: Anusha Srivatsa
> > > > References: 729ae330a0f2e2 ("drm/i915/cml: Introduce Comet Lake PCH")
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111461
> > > > Signed-off-by: Matt Roper
> >
> > Cc: drm-intel-fi...@lists.freedesktop.org
>
> I don't believe this list even exist anymore.
>
> The right way would be:
>
> Fixes: 729ae330a0f2e2 ("drm/i915/cml: Introduce Comet Lake PCH")
Hmm - just curious on the semantics, as the "Fixes" tag implies that the
original patch was broken, but it wasn't - just new PCH IDs have been
added since.
-James
>
> instead of References
>
> >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_pch.c | 1 +
> > > > drivers/gpu/drm/i915/intel_pch.h | 1 +
> > > > 2 files changed, 2 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pch.c
> > > > b/drivers/gpu/drm/i915/intel_pch.c
> > > > index fa864d8f2b73..15f8bff141f9 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pch.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pch.c
> > > > @@ -69,6 +69,7 @@ intel_pch_type(const struct drm_i915_private
> > > > *dev_priv, unsigned short id)
> > > > WARN_ON(!IS_CANNONLAKE(dev_priv) &&
> > > > !IS_COFFEELAKE(dev_priv));
> > > > return PCH_CNP;
> > > > case INTEL_PCH_CMP_DEVICE_ID_TYPE:
> > > > + case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
> > > > DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
> > > > WARN_ON(!IS_COFFEELAKE(dev_priv));
> > > > /* CometPoint is CNP Compatible */
> > > > diff --git a/drivers/gpu/drm/i915/intel_pch.h
> > > > b/drivers/gpu/drm/i915/intel_pch.h
> > > > index e6a2d65f19c6..c29c81ec7971 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pch.h
> > > > +++ b/drivers/gpu/drm/i915/intel_pch.h
> > > > @@ -41,6 +41,7 @@ enum intel_pch {
> > > > #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
> > > > #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE0x9D80
> > > > #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
> > > > +#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
> > > > #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
> > > > #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
> > > > #define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
> > >
> > > Hi,
> > >
> > > Please add this in -fixes so 5.4 will get it, thanks.
> > >
> > >
> > > --
> > > t
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv
On Wed, Oct 09, 2019 at 06:15:26PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to
> dev_priv
> URL : https://patchwork.freedesktop.org/series/67799/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7043 -> Patchwork_14730
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14730 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14730, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14730:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live_coherency:
> - fi-glk-dsi: [PASS][1] -> [TIMEOUT][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-glk-dsi/igt@i915_selftest@live_coherency.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-glk-dsi/igt@i915_selftest@live_coherency.html
This isn't related - I'll hit the retest button...
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14730 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_close_race@basic-threads:
> - fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-bxt-dsi/igt@gem_close_r...@basic-threads.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-bxt-dsi/igt@gem_close_r...@basic-threads.html
>
> * igt@gem_ctx_switch@legacy-render:
> - fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
> [fdo#111381])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
>
> * igt@i915_selftest@live_hangcheck:
> - fi-bsw-kefka: [PASS][7] -> [INCOMPLETE][8] ([fdo#105876])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
>
> * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111045] /
> [fdo#111096])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>
>
> Possible fixes
>
> * igt@gem_sync@basic-many-each:
> - {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-tgl-u/igt@gem_s...@basic-many-each.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-tgl-u/igt@gem_s...@basic-many-each.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
> [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
> [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
> [fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
>
>
> Participating hosts (54 -> 45)
> --
>
> Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
> fi-byt-clapper fi-icl-u3 fi-icl-y fi-icl-dsi fi-bdw-samus
>
>
> Build changes
> -
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_7043 -> Patchwork_14730
>
> CI-20190529: 20190529
> CI_DRM_7043: ed6c47dff498138cd3494c95a107c5787094b0b9 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_14730: e95a4493c64678635694717b5bfb47c04faba383 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> e95a4493c646 drm/i915/tgl: Read SAGV block time from PCODE
> e6a4842921d1 drm/i915: Move SAGV block time to dev_priv
>
> == Logs ==
>
> For more details see:
>
Re: [Intel-gfx] [PATCH] drm/i915/cml: Add second PCH ID for CMP
On Wed, Oct 09, 2019 at 10:29:43AM -0700, Matt Roper wrote:
> On Wed, Oct 09, 2019 at 10:03:31AM +0300, Timo Aaltonen wrote:
> > On 17.9.2019 2.32, Matt Roper wrote:
> > > The CMP PCH ID we have in the driver is correct for the CML-U machines we
> > > have
> > > in our CI system, but the CML-S and CML-H CI machines appear to use a
> > > different PCH ID, leading our driver to detect no PCH for them.
> > >
> > > Cc: Rodrigo Vivi
> > > Cc: Anusha Srivatsa
> > > References: 729ae330a0f2e2 ("drm/i915/cml: Introduce Comet Lake PCH")
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111461
> > > Signed-off-by: Matt Roper
>
> Cc: drm-intel-fi...@lists.freedesktop.org
I don't believe this list even exist anymore.
The right way would be:
Fixes: 729ae330a0f2e2 ("drm/i915/cml: Introduce Comet Lake PCH")
instead of References
>
> > > ---
> > > drivers/gpu/drm/i915/intel_pch.c | 1 +
> > > drivers/gpu/drm/i915/intel_pch.h | 1 +
> > > 2 files changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pch.c
> > > b/drivers/gpu/drm/i915/intel_pch.c
> > > index fa864d8f2b73..15f8bff141f9 100644
> > > --- a/drivers/gpu/drm/i915/intel_pch.c
> > > +++ b/drivers/gpu/drm/i915/intel_pch.c
> > > @@ -69,6 +69,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
> > > unsigned short id)
> > > WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
> > > return PCH_CNP;
> > > case INTEL_PCH_CMP_DEVICE_ID_TYPE:
> > > + case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
> > > DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
> > > WARN_ON(!IS_COFFEELAKE(dev_priv));
> > > /* CometPoint is CNP Compatible */
> > > diff --git a/drivers/gpu/drm/i915/intel_pch.h
> > > b/drivers/gpu/drm/i915/intel_pch.h
> > > index e6a2d65f19c6..c29c81ec7971 100644
> > > --- a/drivers/gpu/drm/i915/intel_pch.h
> > > +++ b/drivers/gpu/drm/i915/intel_pch.h
> > > @@ -41,6 +41,7 @@ enum intel_pch {
> > > #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
> > > #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
> > > #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
> > > +#define INTEL_PCH_CMP2_DEVICE_ID_TYPE0x0680
> > > #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
> > > #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
> > > #define INTEL_PCH_MCC2_DEVICE_ID_TYPE0x3880
> >
> > Hi,
> >
> > Please add this in -fixes so 5.4 will get it, thanks.
> >
> >
> > --
> > t
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: remove redundant variable err
== Series Details == Series: drm/i915: remove redundant variable err URL : https://patchwork.freedesktop.org/series/6/ State : success == Summary == CI Bug Log - changes from CI_DRM_7041_full -> Patchwork_14722_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14722_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb7/igt@gem_exec_sched...@in-order-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-iclb2/igt@gem_exec_sched...@in-order-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][5] -> [DMESG-FAIL][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-apl4/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-apl3/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-glk7/igt@kms_f...@2x-flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-glk7/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-hsw8/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-hsw4/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#111609]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-glk9/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-glk5/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +7 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-apl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-apl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html * igt@perf@blocking: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#110728]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-skl5/igt@p...@blocking.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14722/shard-skl10/igt@p...@blocking.html * igt@perf_pmu@busy-no-semaphores-vcs0: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([fdo#111626]) [25]:
Re: [Intel-gfx] [PATCH v2 1/9] drm/i915/perf: store the associated engine of a stream
Quoting Lionel Landwerlin (2019-10-09 15:15:55) > On 09/10/2019 17:10, Chris Wilson wrote: > > Are you happy with associating the i915_perf_stream with the > > specific_ctx and controlling all the parameters via perf-ioctl? > > > > Yeah sounds like it should work, I would like to test the whole setup. > > If you can share the patches changing the config through a perf stream > ioctl, I'll update my driver and test. Ah, https://cgit.freedesktop.org/~ickle/linux-2.6/log/?h=wip-perf-context that turned out much simpler. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Kill the undead i915_gem_batch_pool.c
On Wed, Oct 09, 2019 at 07:57:33PM +0100, Chris Wilson wrote:
> Quoting Sean Paul (2019-10-09 19:53:31)
> > On Thu, Aug 22, 2019 at 7:17 AM Chris Wilson
> > wrote:
> > >
> > > Quoting Joonas Lahtinen (2019-08-22 12:12:03)
> > > > Quoting Chris Wilson (2019-08-22 09:59:17)
> > > > > You have to cut it off at the neck, otherwise it just reappears in the
> > > > > next merge, like commit 3f866026f0ce ("Merge drm/drm-next
> > > > > into drm-intel-next-queued")
> > > > >
> > > > > References: 3f866026f0ce ("Merge drm/drm-next into
> > > > > drm-intel-next-queued")
> > > > > Signed-off-by: Chris Wilson
> > > > > Cc: Rodrigo Vivi
> > > >
> > > > Acked-by: Joonas Lahtinen
> > >
> > > And once more the nails have been put back in the coffin.
> >
> > Months later, a hand reaches out from the grave and says:
> >
> > Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
> > Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
> > Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
>
> commit b047463c852272ef9956ad3a4c706f78f8b06c17
> Author: Joonas Lahtinen
> Date: Fri Aug 30 11:58:48 2019 +0300
>
> drm/i915: Remove link to missing "Batchbuffer Pools" documentation
>
Ah, that's so much less fun :-)
Thanks for the reference, I look forward to getting it in -misc on the next
backmerge.
Sean
> -Chris
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Re: [Intel-gfx] [PATCH v2 25/27] drm/dp_mst: Add basic topology reprobing when resuming
On Fri, 2019-09-27 at 09:52 -0400, Sean Paul wrote:
> On Tue, Sep 03, 2019 at 04:46:03PM -0400, Lyude Paul wrote:
> > Finally! For a very long time, our MST helpers have had one very
> > annoying issue: They don't know how to reprobe the topology state when
> > coming out of suspend. This means that if a user has a machine connected
> > to an MST topology and decides to suspend their machine, we lose all
> > topology changes that happened during that period. That can be a big
> > problem if the machine was connected to a different topology on the same
> > port before resuming, as we won't bother reprobing any of the ports and
> > likely cause the user's monitors not to come back up as expected.
> >
> > So, we start fixing this by teaching our MST helpers how to reprobe the
> > link addresses of each connected topology when resuming. As it turns
> > out, the behavior that we want here is identical to the behavior we want
> > when initially probing a newly connected MST topology, with a couple of
> > important differences:
> >
> > - We need to be more careful about handling the potential races between
> > events from the MST hub that could change the topology state as we're
> > performing the link address reprobe
> > - We need to be more careful about handling unlikely state changes on
> > ports - such as an input port turning into an output port, something
> > that would be far more likely to happen in situations like the MST hub
> > we're connected to being changed while we're suspend
> >
> > Both of which have been solved by previous commits. That leaves one
> > requirement:
> >
> > - We need to prune any MST ports in our in-memory topology state that
> > were present when suspending, but have not appeared in the post-resume
> > link address response from their parent branch device
> >
> > Which we can now handle in this commit by modifying
> > drm_dp_send_link_address(). We then introduce suspend/resume reprobing
> > by introducing drm_dp_mst_topology_mgr_invalidate_mstb(), which we call
> > in drm_dp_mst_topology_mgr_suspend() to traverse the in-memory topology
> > state to indicate that each mstb needs it's link address resent and PBN
> > resources reprobed.
> >
> > On resume, we start back up >work and have it reprobe the topology
> > in the same way we would on a hotplug, removing any leftover ports that
> > no longer appear in the topology state.
> >
> > Cc: Juston Li
> > Cc: Imre Deak
> > Cc: Ville Syrjälä
> > Cc: Harry Wentland
> > Cc: Daniel Vetter
> > Signed-off-by: Lyude Paul
> > ---
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> > drivers/gpu/drm/drm_dp_mst_topology.c | 138 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
> > drivers/gpu/drm/nouveau/dispnv50/disp.c | 6 +-
> > include/drm/drm_dp_mst_helper.h | 3 +-
> > 5 files changed, 112 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 4d3c8bff77da..27ee3e045b86 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -973,7 +973,7 @@ static void s3_handle_mst(struct drm_device *dev, bool
> > suspend)
> > if (suspend) {
> > drm_dp_mst_topology_mgr_suspend(mgr);
> > } else {
> > - ret = drm_dp_mst_topology_mgr_resume(mgr);
> > + ret = drm_dp_mst_topology_mgr_resume(mgr, true);
> > if (ret < 0) {
> > drm_dp_mst_topology_mgr_set_mst(mgr, false);
> > need_hotplug = true;
> > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > index e407aba1fbd2..2fe24e366925 100644
> > --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> > @@ -2020,6 +2020,14 @@ drm_dp_mst_handle_link_address_port(struct
> > drm_dp_mst_branch *mstb,
> > goto fail_unlock;
> > }
> >
> > + /*
> > +* If this port wasn't just created, then we're reprobing because
> > +* we're coming out of suspend. In this case, always resend the link
> > +* address if there's an MSTB on this port
> > +*/
> > + if (!created && port->pdt == DP_PEER_DEVICE_MST_BRANCHING)
> > + send_link_addr = true;
> > +
> > if (send_link_addr) {
> > mutex_lock(>lock);
> > if (port->mstb) {
> > @@ -2530,7 +2538,8 @@ static void drm_dp_send_link_address(struct
> > drm_dp_mst_topology_mgr *mgr,
> > {
> > struct drm_dp_sideband_msg_tx *txmsg;
> > struct drm_dp_link_address_ack_reply *reply;
> > - int i, len, ret;
> > + struct drm_dp_mst_port *port, *tmp;
> > + int i, len, ret, port_mask = 0;
> >
> > txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
> > if (!txmsg)
> > @@ -2560,9 +2569,28
[Intel-gfx] [PATCH] drm/i915: Add feature flag for platforms with DRAM info
Platforms prior to gen9 to not supply this info to software.
Instead of checking the platform directly, add a new feature
flag, HAS_DRAM_INFO, to allow us to quickly tell if the platform
supports this feature.
v2: Fix commit message and change feature flag name to HAS_DRAM_INFO
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f02a34722217..f5590559f828 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1053,7 +1053,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
*/
dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
- if (INTEL_GEN(dev_priv) < 9)
+ if (!HAS_DRAM_INFO(dev_priv))
return;
if (IS_GEN9_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d284b04c492b..f2e2d2a7b925 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1763,6 +1763,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
+#define HAS_DRAM_INFO(dev_priv)(INTEL_INFO(dev_priv)->has_dram_info)
+
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1cbf3998b361..9d7377f21926 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -601,7 +601,8 @@ static const struct intel_device_info intel_cherryview_info
= {
.display.has_csr = 1, \
.has_gt_uc = 1, \
.display.has_ipc = 1, \
- .ddb_size = 896
+ .ddb_size = 896, \
+ .has_dram_info = 1
#define SKL_PLATFORM \
GEN9_FEATURES, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0cdc2465534b..67a487d93ce4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -109,6 +109,7 @@ enum intel_ppgtt_type {
func(require_force_probe); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
+ func(has_dram_info); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_fpga_dbg); \
--
2.22.0
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Re: [Intel-gfx] [PATCH] drm/i915: Kill the undead i915_gem_batch_pool.c
Quoting Sean Paul (2019-10-09 19:53:31)
> On Thu, Aug 22, 2019 at 7:17 AM Chris Wilson wrote:
> >
> > Quoting Joonas Lahtinen (2019-08-22 12:12:03)
> > > Quoting Chris Wilson (2019-08-22 09:59:17)
> > > > You have to cut it off at the neck, otherwise it just reappears in the
> > > > next merge, like commit 3f866026f0ce ("Merge drm/drm-next
> > > > into drm-intel-next-queued")
> > > >
> > > > References: 3f866026f0ce ("Merge drm/drm-next into
> > > > drm-intel-next-queued")
> > > > Signed-off-by: Chris Wilson
> > > > Cc: Rodrigo Vivi
> > >
> > > Acked-by: Joonas Lahtinen
> >
> > And once more the nails have been put back in the coffin.
>
> Months later, a hand reaches out from the grave and says:
>
> Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
> Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
> Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
commit b047463c852272ef9956ad3a4c706f78f8b06c17
Author: Joonas Lahtinen
Date: Fri Aug 30 11:58:48 2019 +0300
drm/i915: Remove link to missing "Batchbuffer Pools" documentation
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Kill the undead i915_gem_batch_pool.c
On Thu, Aug 22, 2019 at 7:17 AM Chris Wilson wrote:
>
> Quoting Joonas Lahtinen (2019-08-22 12:12:03)
> > Quoting Chris Wilson (2019-08-22 09:59:17)
> > > You have to cut it off at the neck, otherwise it just reappears in the
> > > next merge, like commit 3f866026f0ce ("Merge drm/drm-next
> > > into drm-intel-next-queued")
> > >
> > > References: 3f866026f0ce ("Merge drm/drm-next into drm-intel-next-queued")
> > > Signed-off-by: Chris Wilson
> > > Cc: Rodrigo Vivi
> >
> > Acked-by: Joonas Lahtinen
>
> And once more the nails have been put back in the coffin.
Months later, a hand reaches out from the grave and says:
Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
Error: Cannot open file ../drivers/gpu/drm/i915/i915_gem_batch_pool.c
(warnings from i915.rst htmldocs build)
Sean
> -Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/execlists: Prevent merging requests with conflicting flags
== Series Details == Series: drm/i915/execlists: Prevent merging requests with conflicting flags URL : https://patchwork.freedesktop.org/series/67776/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7041_full -> Patchwork_14721_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14721_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14721_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14721_full: ### IGT changes ### Possible regressions * igt@i915_suspend@forcewake: - shard-iclb: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-iclb6/igt@i915_susp...@forcewake.html Known issues Here are the changes found in Patchwork_14721_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@q-smoketest-render: - shard-apl: [PASS][2] -> [INCOMPLETE][3] ([fdo#103927]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-apl2/igt@gem_ctx_sha...@q-smoketest-render.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-apl2/igt@gem_ctx_sha...@q-smoketest-render.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276]) +13 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#111325]) +7 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb3/igt@gem_exec_sched...@wide-bsd.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-iclb2/igt@gem_exec_sched...@wide-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-iclb: [PASS][8] -> [DMESG-FAIL][9] ([fdo#108686]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb4/igt@gem_tiled_swapp...@non-threaded.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-iclb1/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-hsw: [PASS][10] -> [DMESG-WARN][11] ([fdo#111870]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][12] -> [DMESG-WARN][13] ([fdo#108566]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-apl8/igt@gem_workarou...@suspend-resume-context.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-apl1/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][14] -> [INCOMPLETE][15] ([fdo#103540]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-hsw8/igt@kms_f...@flip-vs-suspend.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-hsw4/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][16] -> [FAIL][17] ([fdo#111609]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-glk9/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-glk8/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][18] -> [FAIL][19] ([fdo#103167]) +5 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109441]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7041/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14721/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv
URL : https://patchwork.freedesktop.org/series/67799/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7043 -> Patchwork_14730
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14730 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14730, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14730:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_coherency:
- fi-glk-dsi: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-glk-dsi/igt@i915_selftest@live_coherency.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-glk-dsi/igt@i915_selftest@live_coherency.html
Known issues
Here are the changes found in Patchwork_14730 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-bxt-dsi/igt@gem_close_r...@basic-threads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-bxt-dsi/igt@gem_close_r...@basic-threads.html
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
[fdo#111381])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_selftest@live_hangcheck:
- fi-bsw-kefka: [PASS][7] -> [INCOMPLETE][8] ([fdo#105876])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111045] / [fdo#111096])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-tgl-u/igt@gem_s...@basic-many-each.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-tgl-u/igt@gem_s...@basic-many-each.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (54 -> 45)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-icl-u3 fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7043 -> Patchwork_14730
CI-20190529: 20190529
CI_DRM_7043: ed6c47dff498138cd3494c95a107c5787094b0b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14730: e95a4493c64678635694717b5bfb47c04faba383 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e95a4493c646 drm/i915/tgl: Read SAGV block time from PCODE
e6a4842921d1 drm/i915: Move SAGV block time to dev_priv
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/index.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/print: introduce new struct drm_device based logging macros
>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Jani Nikula >Sent: Wednesday, October 9, 2019 11:38 AM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org >Cc: Nikula, Jani ; Sam Ravnborg >Subject: [Intel-gfx] [PATCH 8/8] drm/print: introduce new struct drm_device >based logging macros > >Add new struct drm_device based logging macros modeled after the core >kernel device based logging macros. These would be preferred over the >drm printk and struct device based macros in drm code, where possible. > >We have existing drm specific struct device based logging functions, but >they are too verbose to use for two main reasons: > > * The names are unnecessarily long, for example DRM_DEV_DEBUG_KMS(). > > * The use of struct device over struct drm_device is too generic for > most users, leading to an extra dereference. > >For example: > > DRM_DEV_DEBUG_KMS(drm->dev, "Hello, world\n"); > >vs. > > drm_dbg_kms(drm, "Hello, world\n"); > >It's a matter of taste, but the SHOUTING UPPERCASE has been argued to be >less readable than lowercase. > >Some names are changed from old DRM names to be based on the core >kernel >logging functions. For example, NOTE -> notice, ERROR -> err, DEBUG -> >dbg. > >Due to the conflation of DRM_DEBUG and DRM_DEBUG_DRIVER macro use >(DRM_DEBUG is used widely in drivers though it's supposed to be a core >debugging category), they are named as drm_dbg_core and drm_dbg, >respectively. > >The drm_err and _once/_ratelimited variants no longer include the >function name in order to be able to use the core device based logging >macros. Arguably this is not a significant change; error messages should >not be so common to be only distinguishable by the function name. > >Ratelimited debug logging macros are to be added later. > >Cc: Sam Ravnborg >Signed-off-by: Jani Nikula > >--- > >With something like this, I think i915 could start migrating to >drm_device based logging. I have a hard time convincing myself or anyone >about migrating to the DRM_DEV_* variants. >--- > include/drm/drm_print.h | 65 >+ > 1 file changed, 65 insertions(+) > >diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h >index 085a9685270c..e4040dea0d8c 100644 >--- a/include/drm/drm_print.h >+++ b/include/drm/drm_print.h >@@ -322,6 +322,8 @@ static inline bool drm_debug_enabled(enum >drm_debug_category category) > > /* > * struct device based logging >+ * >+ * Prefer drm_device based logging over device or prink based logging. > */ > > __printf(3, 4) >@@ -417,8 +419,71 @@ void drm_dev_dbg(const struct device *dev, enum >drm_debug_category category, > _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_PRIME, > \ > fmt, ##__VA_ARGS__) > >+/* >+ * struct drm_device based logging >+ * >+ * Prefer drm_device based logging over device or prink based logging. >+ */ >+ >+/* Helper for struct drm_device based logging. */ >+#define __drm_printk(drm, level, type, fmt, ...) \ >+ dev_##level##type(drm->dev, "[drm] " fmt, ##__VA_ARGS__) In the past, I have been able to do a: #undef pr_fmt #define pr_fmt(fmt) "[myinfo here] " fmt And have the "[myinfo here]" portion show up the output. Is it possible that you might be able to use this instead of "[drm] " fmt? I think that the this will be the same result, but might be more in line with the printk interface? Mike >+ >+ >+#define drm_info(drm, fmt, ...) \ >+ __drm_printk(drm, info,, fmt, ##__VA_ARGS__) >+ >+#define drm_notice(drm, fmt, ...) \ >+ __drm_printk(drm, notice,, fmt, ##__VA_ARGS__) >+ >+#define drm_warn(drm, fmt, ...) \ >+ __drm_printk(drm, warn,, fmt, ##__VA_ARGS__) >+ >+#define drm_err(drm, fmt, ...)\ >+ __drm_printk(drm, err,, "*ERROR* " fmt, ##__VA_ARGS__) >+ >+ >+#define drm_info_once(drm, fmt, ...) \ >+ __drm_printk(drm, info, _once, fmt, ##__VA_ARGS__) >+ >+#define drm_notice_once(drm, fmt, ...)\ >+ __drm_printk(drm, notice, _once, fmt, ##__VA_ARGS__) >+ >+#define drm_warn_once(drm, fmt, ...) \ >+ __drm_printk(drm, warn, _once, fmt, ##__VA_ARGS__) >+ >+#define drm_err_once(drm, fmt, ...) \ >+ __drm_printk(drm, err, _once, "*ERROR* " fmt, ##__VA_ARGS__) >+ >+ >+#define drm_err_ratelimited(drm, fmt, ...)\ >+ __drm_printk(drm, err, _ratelimited, "*ERROR* " fmt, >##__VA_ARGS__) >+ >+ >+#define drm_dbg_core(drm, fmt, ...) \ >+ drm_dev_dbg(drm->dev, DRM_UT_CORE, fmt, ##__VA_ARGS__) >+#define drm_dbg(drm, fmt, ...) > \ >+ drm_dev_dbg(drm->dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) >+#define
Re: [Intel-gfx] [PATCH v3 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
On Sun, Oct 06, 2019 at 08:43:31PM -0700, Manasi Navare wrote:
> On Mon, Sep 30, 2019 at 05:14:15PM +0300, Ville Syrjälä wrote:
> > On Sun, Sep 22, 2019 at 10:08:02AM -0700, Manasi Navare wrote:
> > > In case of tiled displays when the two tiles are sent across two CRTCs
> > > over two separate DP SST connectors, we need a mechanism to synchronize
> > > the two CRTCs and their corresponding transcoders.
> > > So use the master-slave mode where there is one master corresponding
> > > to last horizontal and vertical tile that needs to be genlocked with
> > > all other slave tiles.
> > > This patch identifies saves the master transcoder in all the slave
> > > CRTC states. This is needed to select the master CRTC/transcoder
> > > while configuring transcoder port sync for the corresponding slaves.
> > >
> > > v4:
> > > * Rebase
> > > v3:
> > > * Use master_tramscoder instead of master_crtc for valid
> > > HW state readouts (Ville)
> > > v2:
> > > * Move this to intel_mode_set_pipe_config(Jani N, Ville)
> > > * Use slave_bitmask to save associated slaves in master crtc state (Ville)
> > >
> > > Cc: Daniel Vetter
> > > Cc: Ville Syrjälä
> > > Cc: Maarten Lankhorst
> > > Cc: Matt Roper
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Maarten Lankhorst
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 123 ++
> > > drivers/gpu/drm/i915/display/intel_display.h | 3 +
> > > .../drm/i915/display/intel_display_types.h| 6 +
> > > 3 files changed, 132 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index c05ba6af6226..4ff375d5852d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -521,6 +521,24 @@ needs_modeset(const struct intel_crtc_state *state)
> > > return drm_atomic_crtc_needs_modeset(>base);
> > > }
> > >
> > > +bool
> > > +is_trans_port_sync_mode(struct drm_i915_private *dev_priv,
> >
> > Redundant function parameter. Can be derived if needed.
>
> Ok
>
> >
> > > + const struct intel_crtc_state *state)
> >
> > 'crtc_state'
>
> Ok
>
>
> >
> > > +{
> > > + return (INTEL_GEN(dev_priv) >= 11 &&
> >
> > I don't think we need a gen check at all. The state should not have
> > master/slaves set if the feature is not supported.
>
> Ok will remove this here and for master as well
>
> >
> > > + (state->master_transcoder != INVALID_TRANSCODER ||
> > > + state->sync_mode_slaves_mask));
> > > +}
> > > +
> > > +static bool
> > > +is_trans_port_sync_master(struct drm_i915_private *dev_priv,
> > > + const struct intel_crtc_state *state)
> > > +{
> > > + return (INTEL_GEN(dev_priv) >= 11 &&
> > > + (state->master_transcoder == INVALID_TRANSCODER &&
> > > + state->sync_mode_slaves_mask));
> > > +}
> > > +
> > > /*
> > > * Platform specific helpers to calculate the port PLL loopback-
> > > (clock.m),
> > > * and post-divider (clock.p) values, pre- (clock.vco) and post-divided
> > > fast
> > > @@ -11773,6 +11791,91 @@ static bool c8_planes_changed(const struct
> > > intel_crtc_state *new_crtc_state)
> > > return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
> > > }
> > >
> > > +static int icl_add_sync_mode_crtcs(struct drm_crtc *crtc,
> >
> > intel_ types all over please.
>
> Yes i think this patch was written we changed everything to intel_ states,
> will change it all
> to intel states
>
> But do we stll keep drm_atomic_state or change that to intel_atomic_state as
> well?
>
> >
> > Also don't need all three funciton arguments. Either just
> > crtc_state or state+crtc will do.
>
> Hmm, but I do need the atomic_state, crtc_state and also the crtc in the
> modeset
One can always derive the others.
Option 1:
foo(crtc_state)
{
crtc = crtc_state->crtc;
state = crtc_state->state;
...
}
Option 2:
foo(state, crtc)
{
crtc_state = get_crtc_state(state, crtc);
...
}
IMO life is more pleasant when you don't have to think about
every function needing to be passed a different set of redundant
information.
>
>
> >
> > > +struct intel_crtc_state *crtc_state,
> > > +struct drm_atomic_state *state)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > > + struct drm_connector *master_connector, *connector;
> > > + struct drm_connector_state *connector_state;
> > > + struct drm_connector_list_iter conn_iter;
> > > + struct drm_crtc *master_crtc = NULL;
> > > + struct drm_crtc_state *master_crtc_state;
> > > + struct intel_crtc_state *master_pipe_config;
> > > + int i, tile_group_id;
> > > +
> > > + if (INTEL_GEN(dev_priv) < 11)
> > > + return 0;
> > > +
> > > + /*
> > > + * In case of tiled displays there could be one or more slaves but
> > > there is
>
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv
URL : https://patchwork.freedesktop.org/series/67799/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e6a4842921d1 drm/i915: Move SAGV block time to dev_priv
-:63: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#63: FILE: drivers/gpu/drm/i915/intel_pm.c:3657:
+ return;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 69 lines checked
e95a4493c646 drm/i915/tgl: Read SAGV block time from PCODE
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/execlists: Protect peeking at execlists->active (rev3)
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Protect peeking at
execlists->active (rev3)
URL : https://patchwork.freedesktop.org/series/67782/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7043 -> Patchwork_14729
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14729 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14729, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14729:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_hangcheck:
- fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
* igt@i915_selftest@live_workarounds:
- fi-skl-6600u: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-skl-6600u/igt@i915_selftest@live_workarounds.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/fi-skl-6600u/igt@i915_selftest@live_workarounds.html
Known issues
Here are the changes found in Patchwork_14729 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@kms_busy@basic-flip-b:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#106107])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u3/igt@kms_b...@basic-flip-b.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/fi-icl-u3/igt@kms_b...@basic-flip-b.html
Possible fixes
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-tgl-u/igt@gem_s...@basic-many-each.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/fi-tgl-u/igt@gem_s...@basic-many-each.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (54 -> 46)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7043 -> Patchwork_14729
CI-20190529: 20190529
CI_DRM_7043: ed6c47dff498138cd3494c95a107c5787094b0b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14729: b21ed3cf220918131ef5e2092535758dd0441f3c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b21ed3cf2209 drm/i915/gt: execlists->active is serialised by the tasklet
108ed38692d3 drm/i915/execlists: Protect peeking at execlists->active
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14729/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cml: Add second PCH ID for CMP
On Wed, Oct 09, 2019 at 10:03:31AM +0300, Timo Aaltonen wrote:
> On 17.9.2019 2.32, Matt Roper wrote:
> > The CMP PCH ID we have in the driver is correct for the CML-U machines we
> > have
> > in our CI system, but the CML-S and CML-H CI machines appear to use a
> > different PCH ID, leading our driver to detect no PCH for them.
> >
> > Cc: Rodrigo Vivi
> > Cc: Anusha Srivatsa
> > References: 729ae330a0f2e2 ("drm/i915/cml: Introduce Comet Lake PCH")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111461
> > Signed-off-by: Matt Roper
Cc: drm-intel-fi...@lists.freedesktop.org
> > ---
> > drivers/gpu/drm/i915/intel_pch.c | 1 +
> > drivers/gpu/drm/i915/intel_pch.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pch.c
> > b/drivers/gpu/drm/i915/intel_pch.c
> > index fa864d8f2b73..15f8bff141f9 100644
> > --- a/drivers/gpu/drm/i915/intel_pch.c
> > +++ b/drivers/gpu/drm/i915/intel_pch.c
> > @@ -69,6 +69,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
> > unsigned short id)
> > WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
> > return PCH_CNP;
> > case INTEL_PCH_CMP_DEVICE_ID_TYPE:
> > + case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
> > DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
> > WARN_ON(!IS_COFFEELAKE(dev_priv));
> > /* CometPoint is CNP Compatible */
> > diff --git a/drivers/gpu/drm/i915/intel_pch.h
> > b/drivers/gpu/drm/i915/intel_pch.h
> > index e6a2d65f19c6..c29c81ec7971 100644
> > --- a/drivers/gpu/drm/i915/intel_pch.h
> > +++ b/drivers/gpu/drm/i915/intel_pch.h
> > @@ -41,6 +41,7 @@ enum intel_pch {
> > #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
> > #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE0x9D80
> > #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
> > +#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
> > #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
> > #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
> > #define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
>
> Hi,
>
> Please add this in -fixes so 5.4 will get it, thanks.
>
>
> --
> t
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
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Re: [Intel-gfx] [PATCH] drm/i915/execlists: Leave tell-tales as to why pending[] is bad
Hi Chris, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [cannot apply to v5.4-rc2 next-20191009] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-execlists-Leave-tell-tales-as-to-why-pending-is-bad/20191009-212112 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-randconfig-a001-201940 (attached as .config) compiler: gcc-4.9 (Debian 4.9.2-10+deb8u1) 4.9.2 reproduce: # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot All errors (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/i915_active.h:13:0, from drivers/gpu/drm/i915/display/intel_frontbuffer.h:30, from drivers/gpu/drm/i915/i915_drv.h:70, from drivers/gpu/drm/i915/display/intel_display_types.h:46, from drivers/gpu/drm/i915/i915_drv.c:54: drivers/gpu/drm/i915/i915_request.h: In function 'to_request': >> drivers/gpu/drm/i915/i915_request.h:261:2: error: implicit declaration of >> function 'GEM_TRACE_ERR' [-Werror=implicit-function-declaration] GEM_BUG_ON(fence && !dma_fence_is_i915(fence)); ^ Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_read Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_write Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:constant_test_bit Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:variable_test_bit Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls Cyclomatic Complexity 1 arch/x86/include/asm/arch_hweight.h:__arch_hweight32 Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32 Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR Cyclomatic Complexity 1 include/linux/err.h:PTR_ERR Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_read Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_add Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_sub Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_read Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_add Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_sub Cyclomatic Complexity 2 arch/x86/include/asm/jump_label.h:arch_static_branch Cyclomatic Complexity 1 include/linux/jump_label.h:static_key_false Cyclomatic Complexity 3 include/linux/string.h:memset Cyclomatic Complexity 4 include/linux/string.h:memcpy Cyclomatic Complexity 4 include/linux/string.h:memcmp Cyclomatic Complexity 1 include/linux/cpumask.h:cpu_max_bits_warn Cyclomatic Complexity 1 include/linux/cpumask.h:cpumask_check Cyclomatic Complexity 5 arch/x86/include/asm/preempt.h:__preempt_count_add Cyclomatic Complexity 5 arch/x86/include/asm/preempt.h:__preempt_count_sub Cyclomatic Complexity 1 include/linux/rcupdate.h:rcu_read_lock_sched_notrace Cyclomatic Complexity 1 include/linux/rcupdate.h:rcu_read_unlock_sched_notrace Cyclomatic Complexity 1 include/linux/spinlock.h:spinlock_check Cyclomatic Complexity 1 include/linux/spinlock.h:spin_lock_irq Cyclomatic Complexity 1 include/linux/spinlock.h:spin_unlock_irq Cyclomatic Complexity 3 include/linux/ktime.h:ktime_compare Cyclomatic Complexity 1 include/linux/ktime.h:ktime_after Cyclomatic Complexity 1 arch/x86/include/asm/io.h:readl Cyclomatic Complexity 1 include/linux/slab.h:kmalloc_large Cyclomatic Complexity 3 include/linux/slab.h:kmalloc Cyclomatic Complexity 1 include/linux/slab.h:kzalloc Cyclomatic Complexity 1 include/linux/device.h:dev_get_drvdata Cyclomatic Complexity 1 include/linux/device.h:dev_set_drvdata Cyclomatic Complexity 1 include/linux/pci.h:pci_disable_msi Cyclomatic Complexity 1 include/linux/pci.h:pci_enable_msi Cyclomatic Complexity 1 arch/x86/include/asm/pci.h:pci_domain_nr Cyclomatic Complexity 1 include/linux/pci.h:pci_get_drvdata Cyclomatic Complexity 1 include/linux/pci.h:pci_set_drvdata Cyclomatic Complexity 1 include/linux/vgaarb.h:vga_remove_vgacon Cyclomatic Complexity 1 include/linux/vgaarb.h:vga_client_register Cyclomatic Complexity 2 include/linux/fb.h:alloc_apertures Cyclomatic Complexity 1 include/linux/vga_switcheroo.h:vga_switcheroo_unregister_client Cyclomatic Complexity 1 include/linux/vga_switcheroo.h:vga_switcheroo_register_client Cyclomatic Complexity 1 include/linux/vga_switcheroo.h:vga_switcheroo_process_delayed_switch Cyclomati
[Intel-gfx] [CI 2/2] drm/i915/tgl: Read SAGV block time from PCODE
From: James Ausmus
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
Signed-off-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20191004221449.1317-2-james.aus...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc067fc57ab..0fb9030b89f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8878,6 +8878,7 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0ffcafe97216..e2aca3e81d28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
static void
skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ u32 val = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+ if (!ret) {
+ dev_priv->sagv_block_time_us = val;
+ return;
+ }
+
+ DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+ } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
--
2.23.0
___
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[Intel-gfx] [CI 1/2] drm/i915: Move SAGV block time to dev_priv
From: James Ausmus
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.
v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)
v3: Change sagv_block_time_us to u32 (Lucas), Change fallback value to
-1 (Lucas), use intel_has_sagv for setup check rather than hand-rolling
(Lucas)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
Signed-off-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20191004221449.1317-1-james.aus...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 33 -
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d284b04c492b..c46b339064c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1267,6 +1267,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
+ u32 sagv_block_time_us;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..0ffcafe97216 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+ if (IS_GEN(dev_priv, 11)) {
+ dev_priv->sagv_block_time_us = 10;
+ return;
+ } else if (IS_GEN(dev_priv, 10)) {
+ dev_priv->sagv_block_time_us = 20;
+ return;
+ } else if (IS_GEN(dev_priv, 9)) {
+ dev_priv->sagv_block_time_us = 30;
+ return;
+ } else {
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ }
+
+ /* Default to an unusable block time */
+ dev_priv->sagv_block_time_us = -1;
+}
+
/*
* SAGV dynamically adjusts the system agent voltage and clock frequencies
* depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9))
- sagv_block_time_us = 30;
- else if (IS_GEN(dev_priv, 10))
- sagv_block_time_us = 20;
- else
- sagv_block_time_us = 10;
-
/*
* If there are no active CRTCs, no additional checks need be performed
*/
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us)
return false;
}
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
+ if (intel_has_sagv(dev_priv))
+ skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
--
2.23.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/print: cleanup and new drm_device based logging
== Series Details ==
Series: drm/print: cleanup and new drm_device based logging
URL : https://patchwork.freedesktop.org/series/67795/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7043 -> Patchwork_14728
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/index.html
Known issues
Here are the changes found in Patchwork_14728 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111880]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-tgl-u/igt@gem_s...@basic-many-each.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/fi-tgl-u/igt@gem_s...@basic-many-each.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7043 -> Patchwork_14728
CI-20190529: 20190529
CI_DRM_7043: ed6c47dff498138cd3494c95a107c5787094b0b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14728: 48c9c02126116a746d016ad287f95e2b3d881a7d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
48c9c0212611 drm/print: introduce new struct drm_device based logging macros
5f8536cabd52 drm/print: group logging functions by prink or device based
c44938e9aa7c drm/print: convert debug category macros into an enum
2173f3c87495 drm/print: underscore prefix functions that should be private to
print
4169799b13df drm/print: rename drm_debug to __drm_debug to discourage use
f19cd5fa4e1d drm/amdgpu: use drm_debug_enabled() to check for debug categories
ad0afd4a8ac2 drm/nouveau: use drm_debug_enabled() to check for debug categories
89aa720fbb9a drm/i915: use drm_debug_enabled() to check for debug categories
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14728/index.html
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Re: [Intel-gfx] [PATCH] drm/i915/gt: execlists->active is serialised by the tasklet
Quoting Tvrtko Ursulin (2019-10-09 17:37:42)
>
> On 09/10/2019 16:59, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-09 16:53:53)
> >>
> >> On 09/10/2019 11:26, Chris Wilson wrote:
> >>> +static inline void
> >>> +execlists_active_lock(struct intel_engine_execlists *execlists)
> >>> +{
> >>> + tasklet_lock(>tasklet);
> >>> +}
> >>> +
> >>> +static inline void
> >>> +execlists_active_unlock(struct intel_engine_execlists *execlists)
> >>> +{
> >>> + tasklet_unlock(>tasklet);
> >>> +}
> >>
> >> After we stop preventing the tasklet from running should we maybe kick
> >> ksoftirqd? I am thinking if a tasklet gets scheduled and ran during us
> >> holding the lock here, it won't lose the "scheduled" status, but not
> >> sure at what next opportunity it would get re-run.
> >
> > If we call tasklet_schedule() while we hold tasklet_lock, ksoftirqd (on
> > another thread, hmm, we need local_bh_disable() to stop ourselves
> > entering the softirq processing), then that tasklet_action will spin on
> > tasklet_trylock.
>
> I don't see it spinning, I see it unlinking the tasklet is trylock fails
> and going onto the next one. So even what I implied before seems wrong -
> it doesn't look like it would get re-run on next tasklet processing run.
> Where do you see the retry?
It puts it back onto the list of taskets to run. Then sees it still has
tasklets to run and reschedules itself.
tasklet_action_common:
1. sets list of pending tasklets to NULL
2. iterates over current list
3. if not executed (trylock failed, or disabled) then appends
the tasklet to the list of pending for next time, and
re-raises the softirq, thereby rescheduling the
softirq/ksoftirqd.
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915/gt: execlists->active is serialised by the tasklet
On 09/10/2019 17:32, Chris Wilson wrote:
Quoting Chris Wilson (2019-10-09 17:09:06)
The active/pending execlists is no longer protected by the
engine->active.lock, but is serialised by the tasklet instead. Update
the locking around the debug and stats to follow suit.
v2: local_bh_disable() to prevent recursing into the tasklet in case we
trigger a softirq (Tvrtko)
Fixes: df403069029d ("drm/i915/execlists: Lift process_csb() out of the irq-off
spinlock")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h| 14 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +++-
drivers/gpu/drm/i915/i915_gem.h | 6 ++
3 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index d624752f2a92..fa770d3ca208 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -136,6 +136,20 @@ execlists_active(const struct intel_engine_execlists
*execlists)
return READ_ONCE(*execlists->active);
}
+static inline void
+execlists_active_lock(struct intel_engine_execlists *execlists)
execlists_active_bh_lock() to include the clue about bh_disable?
Makes sense. Or execlists_active_lock_bh to match the spin_lock_bh.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
+{
+ local_bh_disable(); /* prevent local softirq and lock recursion */
+ tasklet_lock(>tasklet);
+}
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/print: cleanup and new drm_device based logging
== Series Details == Series: drm/print: cleanup and new drm_device based logging URL : https://patchwork.freedesktop.org/series/67795/ State : warning == Summary == $ dim checkpatch origin/drm-tip 89aa720fbb9a drm/i915: use drm_debug_enabled() to check for debug categories ad0afd4a8ac2 drm/nouveau: use drm_debug_enabled() to check for debug categories f19cd5fa4e1d drm/amdgpu: use drm_debug_enabled() to check for debug categories 4169799b13df drm/print: rename drm_debug to __drm_debug to discourage use 2173f3c87495 drm/print: underscore prefix functions that should be private to print c44938e9aa7c drm/print: convert debug category macros into an enum 5f8536cabd52 drm/print: group logging functions by prink or device based -:202: CHECK:LINE_SPACING: Please don't use multiple blank lines #202: FILE: include/drm/drm_print.h:478: + + total: 0 errors, 0 warnings, 1 checks, 193 lines checked 48c9c0212611 drm/print: introduce new struct drm_device based logging macros -:73: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #73: FILE: include/drm/drm_print.h:429: +#define __drm_printk(drm, level, type, fmt, ...) \ + dev_##level##type(drm->dev, "[drm] " fmt, ##__VA_ARGS__) -:76: CHECK:LINE_SPACING: Please don't use multiple blank lines #76: FILE: include/drm/drm_print.h:432: + + -:78: ERROR:SPACING: space required after that ',' (ctx:VxO) #78: FILE: include/drm/drm_print.h:434: + __drm_printk(drm, info,, fmt, ##__VA_ARGS__) ^ -:81: ERROR:SPACING: space required after that ',' (ctx:VxO) #81: FILE: include/drm/drm_print.h:437: + __drm_printk(drm, notice,, fmt, ##__VA_ARGS__) ^ -:84: ERROR:SPACING: space required after that ',' (ctx:VxO) #84: FILE: include/drm/drm_print.h:440: + __drm_printk(drm, warn,, fmt, ##__VA_ARGS__) ^ -:87: ERROR:SPACING: space required after that ',' (ctx:VxO) #87: FILE: include/drm/drm_print.h:443: + __drm_printk(drm, err,, "*ERROR* " fmt, ##__VA_ARGS__) ^ -:89: CHECK:LINE_SPACING: Please don't use multiple blank lines #89: FILE: include/drm/drm_print.h:445: + + -:102: CHECK:LINE_SPACING: Please don't use multiple blank lines #102: FILE: include/drm/drm_print.h:458: + + -:106: CHECK:LINE_SPACING: Please don't use multiple blank lines #106: FILE: include/drm/drm_print.h:462: + + -:107: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #107: FILE: include/drm/drm_print.h:463: +#define drm_dbg_core(drm, fmt, ...)\ + drm_dev_dbg(drm->dev, DRM_UT_CORE, fmt, ##__VA_ARGS__) -:109: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #109: FILE: include/drm/drm_print.h:465: +#define drm_dbg(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) -:111: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #111: FILE: include/drm/drm_print.h:467: +#define drm_dbg_kms(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_KMS, fmt, ##__VA_ARGS__) -:113: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #113: FILE: include/drm/drm_print.h:469: +#define drm_dbg_prime(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_PRIME, fmt, ##__VA_ARGS__) -:115: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #115: FILE: include/drm/drm_print.h:471: +#define drm_dbg_atomic(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) -:117: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #117: FILE: include/drm/drm_print.h:473: +#define drm_dbg_vbl(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_VBL, fmt, ##__VA_ARGS__) -:119: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #119: FILE: include/drm/drm_print.h:475: +#define drm_dbg_state(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_STATE, fmt, ##__VA_ARGS__) -:121: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #121: FILE: include/drm/drm_print.h:477: +#define drm_dbg_lease(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_LEASE, fmt, ##__VA_ARGS__) -:123: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #123: FILE: include/drm/drm_print.h:479: +#define drm_dbg_dp(drm, fmt, ...)
[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/execlists: Leave tell-tales as to why pending[] is bad
== Series Details ==
Series: drm/i915/execlists: Leave tell-tales as to why pending[] is bad
URL : https://patchwork.freedesktop.org/series/67786/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
In file included from ./include/linux/printk.h:7:0,
from ./include/linux/kernel.h:15,
from ./include/linux/interrupt.h:6,
from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/intel_lrc.c: In function ‘assert_pending_valid’:
./include/linux/kern_levels.h:5:18: error: format ‘%ld’ expects argument of
type ‘long int’, but argument 2 has type ‘int’ [-Werror=format=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~
./drivers/gpu/drm/i915/i915_gem.h:67:33: note: in expansion of macro ‘pr_err’
#define GEM_TRACE_ERR(...) do { pr_err(__VA_ARGS__);
trace_printk(__VA_ARGS__); } while (0)
^~
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:4: note: in expansion of macro
‘GEM_TRACE_ERR’
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
^
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:50: note: format string is defined here
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
~~^
%d
In file included from ./include/linux/interrupt.h:6:0,
from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:18: error: format ‘%ld’ expects
argument of type ‘long int’, but argument 2 has type ‘int’ [-Werror=format=]
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
^
port - execlists->pending);
~~~
./include/linux/kernel.h:679:33: note: in definition of macro
‘__trace_printk_check_format’
trace_printk_check_format(fmt, ##args); \
^~~
./include/linux/kernel.h:716:3: note: in expansion of macro ‘do_trace_printk’
do_trace_printk(fmt, ##__VA_ARGS__); \
^~~
./drivers/gpu/drm/i915/i915_gem.h:67:54: note: in expansion of macro
‘trace_printk’
#define GEM_TRACE_ERR(...) do { pr_err(__VA_ARGS__);
trace_printk(__VA_ARGS__); } while (0)
^~~~
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:4: note: in expansion of macro
‘GEM_TRACE_ERR’
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
^
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:18: error: format ‘%ld’ expects
argument of type ‘long int’, but argument 3 has type ‘int’ [-Werror=format=]
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
^
port - execlists->pending);
~~~
./include/linux/kernel.h:732:29: note: in definition of macro ‘do_trace_printk’
__trace_printk(_THIS_IP_, fmt, ##args); \
^~~
./drivers/gpu/drm/i915/i915_gem.h:67:54: note: in expansion of macro
‘trace_printk’
#define GEM_TRACE_ERR(...) do { pr_err(__VA_ARGS__);
trace_printk(__VA_ARGS__); } while (0)
^~~~
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:4: note: in expansion of macro
‘GEM_TRACE_ERR’
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
^
In file included from ./include/linux/printk.h:7:0,
from ./include/linux/kernel.h:15,
from ./include/linux/interrupt.h:6,
from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
./include/linux/kern_levels.h:5:18: error: format ‘%ld’ expects argument of
type ‘long int’, but argument 2 has type ‘int’ [-Werror=format=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~
./drivers/gpu/drm/i915/i915_gem.h:67:33: note: in expansion of macro ‘pr_err’
#define GEM_TRACE_ERR(...) do { pr_err(__VA_ARGS__);
trace_printk(__VA_ARGS__); } while (0)
^~
drivers/gpu/drm/i915/gt/intel_lrc.c:1164:4: note: in expansion of macro
‘GEM_TRACE_ERR’
GEM_TRACE_ERR("Inactive context in pending[%ld]\n",
^
drivers/gpu/drm/i915/gt/intel_lrc.c:1164:49: note: format string is defined here
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Leave tell-tales as to why pending[] is bad
== Series Details ==
Series: drm/i915/execlists: Leave tell-tales as to why pending[] is bad
URL : https://patchwork.freedesktop.org/series/67786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7043 -> Patchwork_14726
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/index.html
Known issues
Here are the changes found in Patchwork_14726 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_linear_blits@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u3/igt@gem_linear_bl...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/fi-blb-e6850/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111880]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-tgl-u/igt@gem_s...@basic-many-each.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14726/fi-tgl-u/igt@gem_s...@basic-many-each.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (54 -> 45)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan
fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7043 -> Patchwork_14726
CI-20190529: 20190529
CI_DRM_7043: ed6c47dff498138cd3494c95a107c5787094b0b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14726: 4a8b6f2f5d98f942912702c1258883066e0d97e6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_14726/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
In file included from ./include/linux/printk.h:7:0,
from ./include/linux/kernel.h:15,
from ./include/linux/interrupt.h:6,
from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/intel_lrc.c: In function ‘assert_pending_valid’:
./include/linux/kern_levels.h:5:18: error: format ‘%ld’ expects argument of
type ‘long int’, but argument 2 has type ‘int’ [-Werror=format=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~
./drivers/gpu/drm/i915/i915_gem.h:67:33: note: in expansion of macro ‘pr_err’
#define GEM_TRACE_ERR(...) do { pr_err(__VA_ARGS__);
trace_printk(__VA_ARGS__); } while (0)
^~
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:4: note: in expansion of macro
‘GEM_TRACE_ERR’
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
^
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:50: note: format string is defined here
GEM_TRACE_ERR("Duplicate context in pending[%ld]\n",
~~^
%d
In file included from ./include/linux/interrupt.h:6:0,
from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/intel_lrc.c:1154:18: error: format ‘%ld’ expects
argument of type ‘long int’, but argument 2 has type ‘int’ [-Werror=format=]
[Intel-gfx] ✗ Fi.CI.BUILD: failure for treewide: remove unused argument in lock_release() (rev2)
== Series Details == Series: treewide: remove unused argument in lock_release() (rev2) URL : https://patchwork.freedesktop.org/series/67007/ State : failure == Summary == Applying: locking/lockdep: Remove unused @nested argument from lock_release() error: sha1 information is lacking or useless (mm/memcontrol.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 locking/lockdep: Remove unused @nested argument from lock_release() When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: execlists->active is serialised by the tasklet
On 09/10/2019 16:59, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-09 16:53:53)
On 09/10/2019 11:26, Chris Wilson wrote:
+static inline void
+execlists_active_lock(struct intel_engine_execlists *execlists)
+{
+ tasklet_lock(>tasklet);
+}
+
+static inline void
+execlists_active_unlock(struct intel_engine_execlists *execlists)
+{
+ tasklet_unlock(>tasklet);
+}
After we stop preventing the tasklet from running should we maybe kick
ksoftirqd? I am thinking if a tasklet gets scheduled and ran during us
holding the lock here, it won't lose the "scheduled" status, but not
sure at what next opportunity it would get re-run.
If we call tasklet_schedule() while we hold tasklet_lock, ksoftirqd (on
another thread, hmm, we need local_bh_disable() to stop ourselves
entering the softirq processing), then that tasklet_action will spin on
tasklet_trylock.
I don't see it spinning, I see it unlinking the tasklet is trylock fails
and going onto the next one. So even what I implied before seems wrong -
it doesn't look like it would get re-run on next tasklet processing run.
Where do you see the retry?
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v2] drm/i915/gt: execlists->active is serialised by the tasklet
Quoting Chris Wilson (2019-10-09 17:09:06)
> The active/pending execlists is no longer protected by the
> engine->active.lock, but is serialised by the tasklet instead. Update
> the locking around the debug and stats to follow suit.
>
> v2: local_bh_disable() to prevent recursing into the tasklet in case we
> trigger a softirq (Tvrtko)
>
> Fixes: df403069029d ("drm/i915/execlists: Lift process_csb() out of the
> irq-off spinlock")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h| 14 ++
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +++-
> drivers/gpu/drm/i915/i915_gem.h | 6 ++
> 3 files changed, 27 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index d624752f2a92..fa770d3ca208 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -136,6 +136,20 @@ execlists_active(const struct intel_engine_execlists
> *execlists)
> return READ_ONCE(*execlists->active);
> }
>
> +static inline void
> +execlists_active_lock(struct intel_engine_execlists *execlists)
execlists_active_bh_lock() to include the clue about bh_disable?
> +{
> + local_bh_disable(); /* prevent local softirq and lock recursion */
> + tasklet_lock(>tasklet);
> +}
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Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree
Applied. thanks!
Alex
On Tue, Oct 8, 2019 at 8:36 PM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.c:25:
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error:
> drm/drmP.h: No such file or directory
>40 | #include
> | ^~~~
> In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.c:38:
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error:
> drm/drmP.h: No such file or directory
>40 | #include
> | ^~~~
> In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.c:26:
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error:
> drm/drmP.h: No such file or directory
>40 | #include
> | ^~~~
> In file included from drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:34:
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_priv.h:40:10: fatal error:
> drm/drmP.h: No such file or directory
>40 | #include
> | ^~~~
>
>
> Caused by commit
>
> 4e98f871bcff ("drm: delete drmP.h + drm_os_linux.h")
>
> interacting with commit
>
> 6b855f7b83d2 ("drm/amdkfd: Check against device cgroup")
>
> from the amdgpu tree.
>
> I added the following merge fix patch for today:
>
> From: Stephen Rothwell
> Date: Wed, 9 Oct 2019 11:24:38 +1100
> Subject: [PATCH] drm/amdkfd: update for drmP.h removal
>
> Signed-off-by: Stephen Rothwell
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index b8b4485c8f74..41bc0428bfc0 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -37,7 +37,9 @@
> #include
> #include
> #include
> -#include
> +#include
> +#include
> +#include
> #include
>
> #include "amd_shared.h"
> @@ -49,8 +51,6 @@
> /* GPU ID hash width in bits */
> #define KFD_GPU_ID_HASH_WIDTH 16
>
> -struct drm_device;
> -
> /* Use upper bits of mmap offset to store KFD driver specific information.
> * BITS[63:62] - Encode MMAP type
> * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs
> to
> --
> 2.23.0
>
> --
> Cheers,
> Stephen Rothwell
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[Intel-gfx] [PATCH v2] drm/i915/gt: execlists->active is serialised by the tasklet
The active/pending execlists is no longer protected by the
engine->active.lock, but is serialised by the tasklet instead. Update
the locking around the debug and stats to follow suit.
v2: local_bh_disable() to prevent recursing into the tasklet in case we
trigger a softirq (Tvrtko)
Fixes: df403069029d ("drm/i915/execlists: Lift process_csb() out of the irq-off
spinlock")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h| 14 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +++-
drivers/gpu/drm/i915/i915_gem.h | 6 ++
3 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index d624752f2a92..fa770d3ca208 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -136,6 +136,20 @@ execlists_active(const struct intel_engine_execlists
*execlists)
return READ_ONCE(*execlists->active);
}
+static inline void
+execlists_active_lock(struct intel_engine_execlists *execlists)
+{
+ local_bh_disable(); /* prevent local softirq and lock recursion */
+ tasklet_lock(>tasklet);
+}
+
+static inline void
+execlists_active_unlock(struct intel_engine_execlists *execlists)
+{
+ tasklet_unlock(>tasklet);
+ local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
+}
+
struct i915_request *
execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5aa1371f6a0f..45b708fc4b52 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1245,9 +1245,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
struct drm_printer *m)
{
struct drm_i915_private *dev_priv = engine->i915;
- const struct intel_engine_execlists * const execlists =
- >execlists;
- unsigned long flags;
+ struct intel_engine_execlists * const execlists = >execlists;
u64 addr;
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
@@ -1329,7 +1327,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
idx, hws[idx * 2], hws[idx * 2 + 1]);
}
- spin_lock_irqsave(>active.lock, flags);
+ execlists_active_lock(execlists);
for (port = execlists->active; (rq = *port); port++) {
char hdr[80];
int len;
@@ -1367,7 +1365,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
if (tl)
intel_timeline_put(tl);
}
- spin_unlock_irqrestore(>active.lock, flags);
+ execlists_active_unlock(execlists);
} else if (INTEL_GEN(dev_priv) > 6) {
drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
ENGINE_READ(engine, RING_PP_DIR_BASE));
@@ -1509,8 +1507,8 @@ int intel_enable_engine_stats(struct intel_engine_cs
*engine)
if (!intel_engine_supports_stats(engine))
return -ENODEV;
- spin_lock_irqsave(>active.lock, flags);
- write_seqlock(>stats.lock);
+ execlists_active_lock(execlists);
+ write_seqlock_irqsave(>stats.lock, flags);
if (unlikely(engine->stats.enabled == ~0)) {
err = -EBUSY;
@@ -1538,8 +1536,8 @@ int intel_enable_engine_stats(struct intel_engine_cs
*engine)
}
unlock:
- write_sequnlock(>stats.lock);
- spin_unlock_irqrestore(>active.lock, flags);
+ write_sequnlock_irqrestore(>stats.lock, flags);
+ execlists_active_unlock(execlists);
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 167a7b56ed5b..6795f1daa3d5 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -77,6 +77,12 @@ struct drm_i915_private;
#define I915_GEM_IDLE_TIMEOUT (HZ / 5)
+static inline void tasklet_lock(struct tasklet_struct *t)
+{
+ while (!tasklet_trylock(t))
+ cpu_relax();
+}
+
static inline void __tasklet_disable_sync_once(struct tasklet_struct *t)
{
if (!atomic_fetch_inc(>count))
--
2.23.0
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Re: [Intel-gfx] [PATCH] drm/i915/gt: execlists->active is serialised by the tasklet
Quoting Tvrtko Ursulin (2019-10-09 16:53:53)
>
> On 09/10/2019 11:26, Chris Wilson wrote:
> > +static inline void
> > +execlists_active_lock(struct intel_engine_execlists *execlists)
> > +{
> > + tasklet_lock(>tasklet);
> > +}
> > +
> > +static inline void
> > +execlists_active_unlock(struct intel_engine_execlists *execlists)
> > +{
> > + tasklet_unlock(>tasklet);
> > +}
>
> After we stop preventing the tasklet from running should we maybe kick
> ksoftirqd? I am thinking if a tasklet gets scheduled and ran during us
> holding the lock here, it won't lose the "scheduled" status, but not
> sure at what next opportunity it would get re-run.
If we call tasklet_schedule() while we hold tasklet_lock, ksoftirqd (on
another thread, hmm, we need local_bh_disable() to stop ourselves
entering the softirq processing), then that tasklet_action will spin on
tasklet_trylock.
-Chris
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Re: [Intel-gfx] [PATCH 5/5] drm/mm: Use clear_bit_unlock() for releasing the drm_mm_node()
On Fri, Oct 04, 2019 at 01:01:36PM +0100, Tvrtko Ursulin wrote:
>
> On 04/10/2019 12:17, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-10-04 12:07:10)
> > > Quoting Tvrtko Ursulin (2019-10-04 10:15:20)
> > > >
> > > > On 03/10/2019 22:01, Chris Wilson wrote:
> > > > > A few callers need to serialise the destruction of their drm_mm_node
> > > > > and
> > > > > ensure it is removed from the drm_mm before freeing. However, to be
> > > > > completely sure that any access from another thread is complete before
> > > > > we free the struct, we require the RELEASE semantics of
> > > > > clear_bit_unlock().
> > > > >
> > > > > This allows the conditional locking such as
> > > > >
> > > > > Thread A Thread B
> > > > > mutex_lock(mm_lock);if
> > > > > (drm_mm_node_allocated(node)) {
> > > > > drm_mm_node_remove(node); mutex_lock(mm_lock);
> > > > > mutex_unlock(mm_lock);
> > > > > drm_mm_node_remove(node);
> > > > > mutex_unlock(mm_lock);
> > > > >}
> > > > >kfree(node);
> > > >
> > > > My understanding is that release semantics on node allocated mean 1 -> 0
> > > > transition is guaranteed to be seen only when thread A
> > > > drm_mm_node_remove is fully done with the removal. But if it is in the
> > > > middle of removal, node is still seen as allocated outside and thread B
> > > > can enter the if-body, wait for the lock, and then drm_mm_node_remove
> > > > will attempt a double removal. So I think another drm_mm_node_allocated
> > > > under the lock is needed.
> > >
> > > Yes. Check after the lock is indeed required in this scenario. And
> > > drm_mm_node_remove() insists the caller doesn't try a double remove.
> >
> > I had to go back and double check the vma code, and that's fine.
> > (We hit this case where one thread is evicting and another thread is
> > destroying the object. And for us we do the check under the lock inside
> > __i915_vma_unbind() on the destroy path.)
>
> So I think if you amend the commit message to contain the repeated check
> under the lock patch looks good to me. With that:
>
> Reviewed-by: Tvrtko Ursulin
I think a follow-up patch to update the kerneldoc to mention that we're
guaranteeing this now is missing here (best with the above fixed example).
Plus maybe a oneline code comment for the ALLOCATED_BIT.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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