[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/5] drm/i915: simplify setting of ddi_io_power_domain
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: simplify setting of
ddi_io_power_domain
URL : https://patchwork.freedesktop.org/series/68069/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7101 -> Patchwork_14826
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14826 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14826, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14826/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14826:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload-with-fault-injection:
- fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7101/fi-bdw-5557u/igt@i915_module_l...@reload-with-fault-injection.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14826/fi-bdw-5557u/igt@i915_module_l...@reload-with-fault-injection.html
Known issues
Here are the changes found in Patchwork_14826 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_gem_contexts:
- fi-kbl-r: [PASS][3] -> [INCOMPLETE][4] ([fdo#112002])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7101/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14826/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111407]) -> [FAIL][6] ([fdo#111045] /
[fdo#111096])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7101/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14826/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112002]: https://bugs.freedesktop.org/show_bug.cgi?id=112002
Participating hosts (53 -> 44)
--
Missing(9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7101 -> Patchwork_14826
CI-20190529: 20190529
CI_DRM_7101: 273c2e52226fe91c635f614ae1c1964769eed16b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14826: 11e662e6ea2a9d245b0df4e379f2ae382fb7960b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
11e662e6ea2a drm/i915: prettify MST debug message
61f60c77ebdd drm/i915: add pipe id/name to pipe mismatch logs
b7e27d51e20b drm/i915: remove extra new line on pipe_config mismatch
70b6d472cf6d drm/i915: fix port checks for MST support on gen >= 11
5fe78a5daa84 drm/i915: simplify setting of ddi_io_power_domain
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14826/index.html
___
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Re: [Intel-gfx] [PATCH V3 1/7] mdev: class id support
On 2019/10/16 上午12:38, Alex Williamson wrote:
On Fri, 11 Oct 2019 16:15:51 +0800
Jason Wang wrote:
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index b558d4cfd082..724e9b9841d8 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -45,6 +45,12 @@ void mdev_set_drvdata(struct mdev_device *mdev, void *data)
}
EXPORT_SYMBOL(mdev_set_drvdata);
+void mdev_set_class(struct mdev_device *mdev, u16 id)
+{
+ mdev->class_id = id;
+}
+EXPORT_SYMBOL(mdev_set_class);
+
struct device *mdev_dev(struct mdev_device *mdev)
{
return >dev;
@@ -135,6 +141,7 @@ static int mdev_device_remove_cb(struct device *dev, void
*data)
* mdev_register_device : Register a device
* @dev: device structure representing parent device.
* @ops: Parent device operation structure to be registered.
+ * @id: class id.
*
* Add device to list of registered parent devices.
* Returns a negative value on error, otherwise 0.
@@ -324,6 +331,9 @@ int mdev_device_create(struct kobject *kobj,
if (ret)
goto ops_create_fail;
+ if (!mdev->class_id)
This is a sanity test failure of the parent driver on a privileged
path, I think it's fair to print a warning when this occurs rather than
only return an errno to the user. In fact, ret is not set to an error
value here, so it looks like this fails to create the device but
returns success. Thanks,
Alex
Will fix.
Thanks
+ goto class_id_fail;
+
ret = device_add(>dev);
if (ret)
goto add_fail;
@@ -340,6 +350,7 @@ int mdev_device_create(struct kobject *kobj,
sysfs_fail:
device_del(>dev);
+class_id_fail:
add_fail:
parent->ops->remove(mdev);
ops_create_fail:
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: simplify setting of ddi_io_power_domain
== Series Details == Series: series starting with [CI,1/5] drm/i915: simplify setting of ddi_io_power_domain URL : https://patchwork.freedesktop.org/series/68069/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5fe78a5daa84 drm/i915: simplify setting of ddi_io_power_domain 70b6d472cf6d drm/i915: fix port checks for MST support on gen >= 11 b7e27d51e20b drm/i915: remove extra new line on pipe_config mismatch -:52: WARNING:LONG_LINE: line over 100 characters #52: FILE: drivers/gpu/drm/i915/display/intel_display.c:12607: +"unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ total: 0 errors, 1 warnings, 0 checks, 88 lines checked 61f60c77ebdd drm/i915: add pipe id/name to pipe mismatch logs 11e662e6ea2a drm/i915: prettify MST debug message ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move L3 MOCS to engine reset domain.
== Series Details ==
Series: drm/i915: Move L3 MOCS to engine reset domain.
URL : https://patchwork.freedesktop.org/series/68068/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7101 -> Patchwork_14825
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14825/index.html
Known issues
Here are the changes found in Patchwork_14825 that come from known issues:
### IGT changes ###
Issues hit
* igt@vgem_basic@sysfs:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7101/fi-icl-u3/igt@vgem_ba...@sysfs.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14825/fi-icl-u3/igt@vgem_ba...@sysfs.html
Possible fixes
* igt@gem_workarounds@basic-read:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7101/fi-icl-u3/igt@gem_workarou...@basic-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14825/fi-icl-u3/igt@gem_workarou...@basic-read.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#106107]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7101/fi-icl-u3/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14825/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7101/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14825/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (53 -> 45)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7101 -> Patchwork_14825
CI-20190529: 20190529
CI_DRM_7101: 273c2e52226fe91c635f614ae1c1964769eed16b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14825: 355e8f02f04d788c080a622923f7b7aab89dfba4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
355e8f02f04d drm/i915: Move L3 MOCS to engine reset domain.
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14825/index.html
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for Refactor Gen11+ SAGV support
== Series Details == Series: Refactor Gen11+ SAGV support URL : https://patchwork.freedesktop.org/series/68028/ State : success == Summary == CI Bug Log - changes from CI_DRM_7096_full -> Patchwork_14812_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14812_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@vcs0-heavy-queue: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-apl7/igt@gem_ctx_swi...@vcs0-heavy-queue.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-apl4/igt@gem_ctx_swi...@vcs0-heavy-queue.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-iclb7/igt@gem_exec_as...@concurrent-writes-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_tiled_blits@normal: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#111904]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-kbl4/igt@gem_tiled_bl...@normal.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-kbl3/igt@gem_tiled_bl...@normal.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108682]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-skl9/igt@kms_co...@pipe-a-ctm-0-75.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-skl10/igt@kms_co...@pipe-a-ctm-0-75.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding: - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#103232]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-apl7/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][17] -> [FAIL][18] ([fdo#105767]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#105363]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-skl3/igt@kms_f...@flip-vs-expired-vblank.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html - shard-glk: [PASS][21] -> [FAIL][22] ([fdo#105363]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-glk4/igt@kms_f...@flip-vs-expired-vblank.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb:
[Intel-gfx] [CI 1/5] drm/i915: simplify setting of ddi_io_power_domain
Instead of the ever growing switch, just compute the ddi io power domain
based on the port number.
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-2-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++--
1 file changed, 3 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 80f8e2698be0..cb26c487b68f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4754,46 +4754,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_encoder->update_complete = intel_ddi_update_complete;
}
- switch (port) {
- case PORT_A:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_A_IO;
- break;
- case PORT_B:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_B_IO;
- break;
- case PORT_C:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_C_IO;
- break;
- case PORT_D:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_D_IO;
- break;
- case PORT_E:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_E_IO;
- break;
- case PORT_F:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_F_IO;
- break;
- case PORT_G:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_G_IO;
- break;
- case PORT_H:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_H_IO;
- break;
- case PORT_I:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_I_IO;
- break;
- default:
- MISSING_CASE(port);
- }
+ WARN_ON(port > PORT_I);
+ intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
+ port - PORT_A;
if (init_dp) {
if (!intel_ddi_init_dp_connector(intel_dig_port))
--
2.23.0
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[Intel-gfx] [CI 5/5] drm/i915: prettify MST debug message
s/?/:/ so it gets correctly colored by dmesg.
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-7-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 61080aaebf5e..9c130e0f9472 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4451,7 +4451,7 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
_to_dig_port(intel_dp)->base;
bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
- DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support? port: %s, sink: %s,
modparam: %s\n",
+ DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s,
modparam: %s\n",
encoder->base.base.id, encoder->base.name,
yesno(intel_dp->can_mst), yesno(sink_can_mst),
yesno(i915_modparams.enable_dp_mst));
--
2.23.0
___
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[Intel-gfx] [CI 4/5] drm/i915: add pipe id/name to pipe mismatch logs
This way it's easier to figure out what didn't match when we have
multiple pipes enabled.
v2: pass drm_crtc and use the more common [CRTC:%d:%s] format
(Ville)
v3: use struct intel_crtc type to pass crtc around (Ville)
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015164029.18431-5-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +++-
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 796bf752f3dd..e054cfd47782 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12512,8 +12512,9 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
}
}
-static void __printf(3, 4)
-pipe_config_mismatch(bool fastset, const char *name, const char *format, ...)
+static void __printf(4, 5)
+pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
+const char *name, const char *format, ...)
{
struct va_format vaf;
va_list args;
@@ -12523,9 +12524,11 @@ pipe_config_mismatch(bool fastset, const char *name,
const char *format, ...)
vaf.va =
if (fastset)
- DRM_DEBUG_KMS("fastset mismatch in %s %pV\n", name, );
+ DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
+ crtc->base.base.id, crtc->base.name, name, );
else
- DRM_ERROR("mismatch in %s %pV\n", name, );
+ DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
+ crtc->base.base.id, crtc->base.name, name, );
va_end(args);
}
@@ -12553,6 +12556,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bool fastset)
{
struct drm_i915_private *dev_priv =
to_i915(current_config->base.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
bool ret = true;
u32 bp_gamma = 0;
bool fixup_inherited = fastset &&
@@ -12566,7 +12570,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_X(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected 0x%08x, found 0x%08x)", \
current_config->name, \
pipe_config->name); \
@@ -12576,7 +12580,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_I(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected %i, found %i)", \
current_config->name, \
pipe_config->name); \
@@ -12586,7 +12590,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
@@ -12603,7 +12607,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (!fixup_inherited || (!current_config->name && !pipe_config->name))
{ \
PIPE_CONF_CHECK_BOOL(name); \
} else { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"unable to verify whether state matches
exactly, forcing modeset (expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
@@ -12613,7 +12617,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_P(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected %p, found %p)", \
current_config->name, \
pipe_config->name); \
@@ -12625,7 +12629,7 @@
[Intel-gfx] [CI 3/5] drm/i915: remove extra new line on pipe_config mismatch
The new line is already added by pipe_config_mismatch(), so the callers
shouldn't add it.
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-5-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 22 ++--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7d7d1859775a..796bf752f3dd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12567,7 +12567,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_X(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected 0x%08x, found 0x%08x)\n", \
+"(expected 0x%08x, found 0x%08x)", \
current_config->name, \
pipe_config->name); \
ret = false; \
@@ -12577,7 +12577,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_I(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected %i, found %i)\n", \
+"(expected %i, found %i)", \
current_config->name, \
pipe_config->name); \
ret = false; \
@@ -12587,7 +12587,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected %s, found %s)\n", \
+"(expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
ret = false; \
@@ -12604,7 +12604,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_BOOL(name); \
} else { \
pipe_config_mismatch(fastset, __stringify(name), \
-"unable to verify whether state matches
exactly, forcing modeset (expected %s, found %s)\n", \
+"unable to verify whether state matches
exactly, forcing modeset (expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
ret = false; \
@@ -12614,7 +12614,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_P(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected %p, found %p)\n", \
+"(expected %p, found %p)", \
current_config->name, \
pipe_config->name); \
ret = false; \
@@ -12627,7 +12627,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
!fastset)) { \
pipe_config_mismatch(fastset, __stringify(name), \
"(expected tu %i gmch %i/%i link %i/%i, " \
-"found tu %i, gmch %i/%i link %i/%i)\n", \
+"found tu %i, gmch %i/%i link %i/%i)", \
current_config->name.tu, \
current_config->name.gmch_m, \
current_config->name.gmch_n, \
@@ -12655,7 +12655,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
pipe_config_mismatch(fastset, __stringify(name), \
"(expected tu %i gmch %i/%i link %i/%i, " \
"or tu %i gmch %i/%i link %i/%i, " \
-"found tu %i, gmch %i/%i link %i/%i)\n", \
+"found tu %i, gmch %i/%i link %i/%i)", \
current_config->name.tu, \
current_config->name.gmch_m, \
current_config->name.gmch_n, \
@@ -12678,7 +12678,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
[Intel-gfx] [CI 2/5] drm/i915: fix port checks for MST support on gen >= 11
Both Ice Lake and Elkhart Lake (gen 11) support MST on all external
connections except DDI A. Tiger Lake (gen 12) supports on all external
connections.
Move the check to happen inside intel_dp_mst_encoder_init() and add
specific platform checks.
v2: Replace != with == checks for ports on gen < 11 (Ville)
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015164029.18431-3-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++--
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index dd5dc1e38495..61080aaebf5e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7441,11 +7441,8 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
intel_connector->get_hw_state = intel_connector_get_hw_state;
/* init MST on ports that can support it */
- if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
- (port == PORT_B || port == PORT_C ||
-port == PORT_D || port == PORT_F))
- intel_dp_mst_encoder_init(intel_dig_port,
- intel_connector->base.base.id);
+ intel_dp_mst_encoder_init(intel_dig_port,
+ intel_connector->base.base.id);
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
intel_dp_aux_fini(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2203be28ea01..bbcab27644dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -655,21 +655,31 @@ intel_dp_mst_encoder_active_links(struct
intel_digital_port *intel_dig_port)
int
intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int
conn_base_id)
{
+ struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
struct intel_dp *intel_dp = _dig_port->dp;
- struct drm_device *dev = intel_dig_port->base.base.dev;
+ enum port port = intel_dig_port->base.port;
int ret;
- intel_dp->can_mst = true;
+ if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
+ return 0;
+
+ if (INTEL_GEN(i915) < 12 && port == PORT_A)
+ return 0;
+
+ if (INTEL_GEN(i915) < 11 && port == PORT_E)
+ return 0;
+
intel_dp->mst_mgr.cbs = _cbs;
/* create encoders */
intel_dp_create_fake_mst_encoders(intel_dig_port);
- ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, dev,
+ ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, >drm,
_dp->aux, 16, 3, conn_base_id);
- if (ret) {
- intel_dp->can_mst = false;
+ if (ret)
return ret;
- }
+
+ intel_dp->can_mst = true;
+
return 0;
}
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Move L3 MOCS to engine reset domain.
Gen12 has L3 MOCS in engine reset domain, having us to re-initialize on an engine reset. References: https://bugs.freedesktop.org/show_bug.cgi?id=111723 References: https://bugs.freedesktop.org/show_bug.cgi?id=111645 References: HSDES#1607983814 References: HSDES#14010115701 Signed-off-by: Prathap Kumar Valsan --- drivers/gpu/drm/i915/gt/intel_mocs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 728704bbbe18..774c5df0d0e9 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -365,6 +365,8 @@ static u32 get_entry_control(const struct drm_i915_mocs_table *table, return table->table[I915_MOCS_PTE].control_value; } +static void intel_mocs_init_l3cc_table(struct intel_gt *gt); + /** * intel_mocs_init_engine() - emit the mocs control table * @engine:The engine for whom to emit the registers. @@ -380,6 +382,9 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) unsigned int index; u32 unused_value; + if (IS_GEN(gt->i915, 12) && engine->class == RENDER_CLASS) + intel_mocs_init_l3cc_table(gt); + /* Platforms with global MOCS do not need per-engine initialization. */ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) return; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable Transcoder port sync for Tiled displays (rev2)
== Series Details ==
Series: Enable Transcoder port sync for Tiled displays (rev2)
URL : https://patchwork.freedesktop.org/series/68062/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7100 -> Patchwork_14824
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14824 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14824, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14824:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-ilk-650/igt@run...@aborted.html
- fi-gdg-551: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-gdg-551/igt@run...@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-snb-2520m/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-ivb-3770/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-blb-e6850/igt@run...@aborted.html
- fi-bsw-kefka: NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-bsw-kefka/igt@run...@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-elk-e7500/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14824 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][8] -> [INCOMPLETE][9] ([fdo#103927] /
[fdo#111381])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_wait@basic-await-all:
- fi-icl-u3: [PASS][10] -> [DMESG-WARN][11] ([fdo#107724]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-icl-u3/igt@gem_w...@basic-await-all.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-icl-u3/igt@gem_w...@basic-await-all.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-x1275: [INCOMPLETE][12] ([fdo#107139]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [DMESG-WARN][14] ([fdo#107724]) -> [PASS][15] +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [DMESG-FAIL][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][18] ([fdo#107713] / [fdo#108569]) ->
[PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14824/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
Participating hosts (52 -> 45)
Re: [Intel-gfx] [PATCH] kernel-doc: rename the kernel-doc directive 'functions' to 'specific'
On Wed, Oct 16, 2019 at 08:03:24AM +0800, Changbin Du wrote: > On Tue, Oct 15, 2019 at 04:54:39AM -0700, Matthew Wilcox wrote: > > On Tue, Oct 15, 2019 at 11:25:53AM +0200, Thomas Zimmermann wrote: > > > > My preference would be to use 'symbols'. I tried to come up with > > > > something > > > > but 'symbols' is better than anything I came up with. > > > > > > Maybe 'interfaces' or 'artifacts'. The term 'symbols' is just as > > > imprecise as 'functions'. > > > > I suggested 'identifier' because that's the term used in the C spec (6.2.1): > > > > : An identifier can denote an object; a function; a tag or a member > > : of a structure, union, or enumeration; a typedef name; a label name; > > : a macro name; or a macro parameter. > > I also prefer this one now. I was looking for something like this. My original > idea is 'prototype', but that is only for function. We could also go with 'declaration' or 'definition'. But I prefer 'identifier'. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] linux-next: build failure after merge of the drm-misc tree
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c:23:10: fatal error: drm/drmP.h: No such
file or directory
23 | #include
| ^~~~
Caused by commit
4e98f871bcff ("drm: delete drmP.h + drm_os_linux.h")
interacting with commit
8b8c294c5d37 ("drm/amdgpu: add function to check tmz capability (v4)")
from the amdgpu tree.
I applied the following merge fix patch for today (which should also
apply to the amdgpu tree).
From: Stephen Rothwell
Date: Wed, 16 Oct 2019 11:17:32 +1100
Subject: [PATCH] drm/amdgpu: fix up for amdgpu_tmz.c and removal of drm/drmP.h
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
index 14a55003dd81..823527a0fa47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
@@ -20,7 +20,10 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include
+#include
+
+#include
+
#include "amdgpu.h"
#include "amdgpu_tmz.h"
--
2.23.0
--
Cheers,
Stephen Rothwell
pgpILj2DiYPCk.pgp
Description: OpenPGP digital signature
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/12] drm/i915/icl: Wa_1607087056
== Series Details ==
Series: series starting with [CI,01/12] drm/i915/icl: Wa_1607087056
URL : https://patchwork.freedesktop.org/series/68057/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7100 -> Patchwork_14823
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/index.html
Known issues
Here are the changes found in Patchwork_14823 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([fdo#106107])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html
* igt@prime_vgem@basic-fence-read:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-icl-u3/igt@prime_v...@basic-fence-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/fi-icl-u3/igt@prime_v...@basic-fence-read.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-x1275: [INCOMPLETE][5] ([fdo#107139]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111045] / [fdo#111096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7100/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (52 -> 44)
--
Additional (1): fi-bsw-n3050
Missing(9): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-tgl-u2 fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7100 -> Patchwork_14823
CI-20190529: 20190529
CI_DRM_7100: 38af7ec455b5b57fb24e4451a968bf4e92749035 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14823: aa03bdf30e3e41ed8d2dd9729f85c56884c339ff @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
aa03bdf30e3e drm/i915/tgl: Wa_1607138340
956eeda18f87 drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627
54432ea9cba0 drm/i915/tgl: Wa_1607138336
4ee46276e132 drm/i915/tgl: Wa_1409600907
9c2c4b12f600 drm/i915/tgl: Wa_1409170338
62aae1629cad drm/i915/tgl: Wa_1409420604
5a81fe94b217 drm/i915/tgl: Keep FF dop clock enabled for A0
81e4c7f6e233 drm/i915/tgl: Add extra hdc flush workaround
a4408250eff6 drm/i915/tgl: Add HDC Pipeline Flush
0fb149808f79 drm/i915/tgl: Include ro parts of l3 to invalidate
67edc47b7159 drm/i915/tgl: Add IS_TGL_REVID
8f0f30a0bc83 drm/i915/icl: Wa_1607087056
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14823/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Expose engine properties via sysfs
== Series Details == Series: series starting with [1/7] drm/i915: Expose engine properties via sysfs URL : https://patchwork.freedesktop.org/series/68022/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7094_full -> Patchwork_14810_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14810_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14810_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14810_full: ### IGT changes ### Possible regressions * igt@gem_ctx_exec@basic-norecovery: - shard-apl: [PASS][1] -> [DMESG-WARN][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-apl2/igt@gem_ctx_e...@basic-norecovery.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-apl4/igt@gem_ctx_e...@basic-norecovery.html - shard-skl: [PASS][3] -> [DMESG-WARN][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-skl3/igt@gem_ctx_e...@basic-norecovery.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-skl3/igt@gem_ctx_e...@basic-norecovery.html - shard-glk: [PASS][5] -> [DMESG-WARN][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-glk6/igt@gem_ctx_e...@basic-norecovery.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-glk5/igt@gem_ctx_e...@basic-norecovery.html * igt@gem_eio@banned: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-kbl6/igt@gem_...@banned.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-kbl2/igt@gem_...@banned.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-iclb2/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-hsw: [PASS][11] -> [TIMEOUT][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-hsw8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-hsw6/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@i915_hangman@error-state-capture-bcs0: - shard-apl: [PASS][13] -> [FAIL][14] +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-apl6/igt@i915_hang...@error-state-capture-bcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-apl3/igt@i915_hang...@error-state-capture-bcs0.html - shard-iclb: [PASS][15] -> [FAIL][16] +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-iclb2/igt@i915_hang...@error-state-capture-bcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-iclb6/igt@i915_hang...@error-state-capture-bcs0.html * igt@i915_hangman@error-state-capture-rcs0: - shard-skl: [PASS][17] -> [FAIL][18] +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-skl3/igt@i915_hang...@error-state-capture-rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-skl9/igt@i915_hang...@error-state-capture-rcs0.html - shard-glk: [PASS][19] -> [FAIL][20] +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-glk7/igt@i915_hang...@error-state-capture-rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-glk1/igt@i915_hang...@error-state-capture-rcs0.html * igt@i915_hangman@error-state-capture-vcs0: - shard-kbl: [PASS][21] -> [FAIL][22] +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-kbl2/igt@i915_hang...@error-state-capture-vcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-kbl1/igt@i915_hang...@error-state-capture-vcs0.html Warnings * igt@gem_exec_schedule@preempt-queue-chain-bsd2: - shard-iclb: [SKIP][23] ([fdo#109276]) -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7094/shard-iclb8/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14810/shard-iclb1/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html Suppressed The following results come from
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/12] drm/i915/icl: Wa_1607087056
== Series Details == Series: series starting with [CI,01/12] drm/i915/icl: Wa_1607087056 URL : https://patchwork.freedesktop.org/series/68057/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8f0f30a0bc83 drm/i915/icl: Wa_1607087056 67edc47b7159 drm/i915/tgl: Add IS_TGL_REVID -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_drv.h:1691: +#define IS_TGL_REVID(p, since, until) \ + (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) total: 0 errors, 0 warnings, 1 checks, 11 lines checked 0fb149808f79 drm/i915/tgl: Include ro parts of l3 to invalidate a4408250eff6 drm/i915/tgl: Add HDC Pipeline Flush 81e4c7f6e233 drm/i915/tgl: Add extra hdc flush workaround 5a81fe94b217 drm/i915/tgl: Keep FF dop clock enabled for A0 62aae1629cad drm/i915/tgl: Wa_1409420604 9c2c4b12f600 drm/i915/tgl: Wa_1409170338 4ee46276e132 drm/i915/tgl: Wa_1409600907 54432ea9cba0 drm/i915/tgl: Wa_1607138336 956eeda18f87 drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627 aa03bdf30e3e drm/i915/tgl: Wa_1607138340 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical tile that needs to be genlocked with
all other slave tiles.
This patch identifies saves the master transcoder in all the slave
CRTC states. This is needed to select the master CRTC/transcoder
while configuring transcoder port sync for the corresponding slaves.
v6:
Rebase (manasi)
v5:
* Address Ville's comments
* Just pass crtc_state, no need to check GEN (Ville)
v4:
* Rebase
v3:
* Use master_tramscoder instead of master_crtc for valid
HW state readouts (Ville)
v2:
* Move this to intel_mode_set_pipe_config(Jani N, Ville)
* Use slave_bitmask to save associated slaves in master crtc state (Ville)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 118 ++
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../drm/i915/display/intel_display_types.h| 6 +
3 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index db9ff1bc1c64..0f4ab34d7281 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -519,6 +519,20 @@ needs_modeset(const struct intel_crtc_state *state)
return drm_atomic_crtc_needs_modeset(>base);
}
+bool
+is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
+ crtc_state->sync_mode_slaves_mask);
+}
+
+static bool
+is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
+ crtc_state->sync_mode_slaves_mask);
+}
+
/*
* Platform specific helpers to calculate the port PLL loopback- (clock.m),
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -11775,6 +11789,91 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->base.state);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_connector *master_connector, *connector;
+ struct drm_connector_state *connector_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc *master_crtc = NULL;
+ struct drm_crtc_state *master_crtc_state;
+ struct intel_crtc_state *master_pipe_config;
+ int i, tile_group_id;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ /*
+* In case of tiled displays there could be one or more slaves but
there is
+* only one master. Lets make the CRTC used by the connector
corresponding
+* to the last horizonal and last vertical tile a master/genlock CRTC.
+* All the other CRTCs corresponding to other tiles of the same Tile
group
+* are the slave CRTCs and hold a pointer to their genlock CRTC.
+*/
+ for_each_new_connector_in_state(>base, connector,
connector_state, i) {
+ if (connector_state->crtc != crtc)
+ continue;
+ if (!connector->has_tile)
+ continue;
+ if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
+ crtc_state->base.mode.vdisplay != connector->tile_v_size)
+ return 0;
+ if (connector->tile_h_loc == connector->num_h_tile - 1 &&
+ connector->tile_v_loc == connector->num_v_tile - 1)
+ continue;
+ crtc_state->sync_mode_slaves_mask = 0;
+ tile_group_id = connector->tile_group->id;
+ drm_connector_list_iter_begin(_priv->drm, _iter);
+ drm_for_each_connector_iter(master_connector, _iter) {
+ struct drm_connector_state *master_conn_state = NULL;
+
+ if (!master_connector->has_tile)
+ continue;
+ if (master_connector->tile_h_loc !=
master_connector->num_h_tile - 1 ||
+ master_connector->tile_v_loc !=
master_connector->num_v_tile - 1)
+ continue;
+ if (master_connector->tile_group->id != tile_group_id)
+ continue;
+
+ master_conn_state =
[Intel-gfx] [PATCH v9 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical tile that needs to be genlocked with
all other slave tiles.
This patch identifies saves the master transcoder in all the slave
CRTC states. This is needed to select the master CRTC/transcoder
while configuring transcoder port sync for the corresponding slaves.
v6:
Rebase (manasi)
v5:
* Address Ville's comments
* Just pass crtc_state, no need to check GEN (Ville)
v4:
* Rebase
v3:
* Use master_tramscoder instead of master_crtc for valid
HW state readouts (Ville)
v2:
* Move this to intel_mode_set_pipe_config(Jani N, Ville)
* Use slave_bitmask to save associated slaves in master crtc state (Ville)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 118 ++
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../drm/i915/display/intel_display_types.h| 6 +
3 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index db9ff1bc1c64..0f4ab34d7281 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -519,6 +519,20 @@ needs_modeset(const struct intel_crtc_state *state)
return drm_atomic_crtc_needs_modeset(>base);
}
+bool
+is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
+ crtc_state->sync_mode_slaves_mask);
+}
+
+static bool
+is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
+ crtc_state->sync_mode_slaves_mask);
+}
+
/*
* Platform specific helpers to calculate the port PLL loopback- (clock.m),
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -11775,6 +11789,91 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->base.state);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_connector *master_connector, *connector;
+ struct drm_connector_state *connector_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc *master_crtc = NULL;
+ struct drm_crtc_state *master_crtc_state;
+ struct intel_crtc_state *master_pipe_config;
+ int i, tile_group_id;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ /*
+* In case of tiled displays there could be one or more slaves but
there is
+* only one master. Lets make the CRTC used by the connector
corresponding
+* to the last horizonal and last vertical tile a master/genlock CRTC.
+* All the other CRTCs corresponding to other tiles of the same Tile
group
+* are the slave CRTCs and hold a pointer to their genlock CRTC.
+*/
+ for_each_new_connector_in_state(>base, connector,
connector_state, i) {
+ if (connector_state->crtc != crtc)
+ continue;
+ if (!connector->has_tile)
+ continue;
+ if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
+ crtc_state->base.mode.vdisplay != connector->tile_v_size)
+ return 0;
+ if (connector->tile_h_loc == connector->num_h_tile - 1 &&
+ connector->tile_v_loc == connector->num_v_tile - 1)
+ continue;
+ crtc_state->sync_mode_slaves_mask = 0;
+ tile_group_id = connector->tile_group->id;
+ drm_connector_list_iter_begin(_priv->drm, _iter);
+ drm_for_each_connector_iter(master_connector, _iter) {
+ struct drm_connector_state *master_conn_state = NULL;
+
+ if (!master_connector->has_tile)
+ continue;
+ if (master_connector->tile_h_loc !=
master_connector->num_h_tile - 1 ||
+ master_connector->tile_v_loc !=
master_connector->num_v_tile - 1)
+ continue;
+ if (master_connector->tile_group->id != tile_group_id)
+ continue;
+
+ master_conn_state =
[Intel-gfx] [PATCH v8 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
v3:
* Rebase on maarten's patches
v2:
* Directly write the trans_port_sync reg value (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 22
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bde142607dac..c7dbba237185 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4443,6 +4443,25 @@ static void icl_enable_trans_port_sync(const struct
intel_crtc_state *crtc_state
trans_ddi_func_ctl2_val);
}
+static void icl_disable_transcoder_port_sync(const struct intel_crtc_state
*old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ i915_reg_t reg;
+ u32 trans_ddi_func_ctl2_val;
+
+ if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
+ transcoder_name(old_crtc_state->cpu_transcoder));
+
+ reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
+ trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
+ PORT_SYNC_MODE_MASTER_SELECT_MASK);
+ I915_WRITE(reg, trans_ddi_func_ctl2_val);
+}
+
static void intel_fdi_normal_train(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -6648,6 +6667,9 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_disable_transcoder_port_sync(old_crtc_state);
+
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
--
2.19.1
___
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[Intel-gfx] [PATCH v8 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v5:
* Dont pass dev priv to get_slave_crtc (Ville)
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables() helper
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 58 ++--
1 file changed, 52 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c7dbba237185..cb3903d41113 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14077,6 +14077,37 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
new_crtc_state);
}
+static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state
*state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state
*old_crtc_state,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave_crtc);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+ WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+ !old_slave_crtc_state);
+
+ /* Disable Slave first */
+ intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+ if (old_slave_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_slave_crtc_state,
+ new_slave_crtc_state,
+ slave_crtc);
+
+ /* Disable Master */
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+}
+
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
{
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
@@ -14095,13 +14126,28 @@ static void intel_commit_modeset_disables(struct
intel_atomic_state *state)
if (!needs_modeset(new_crtc_state))
continue;
- intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ /* In case of Transcoder port Sync master slave CRTCs can be
+* assigned in any order and we need to make sure that
+* slave CRTCs are disabled first and then master CRTC since
+* Slave vblanks are masked till Master Vblanks.
+*/
+ if (is_trans_port_sync_mode(new_crtc_state)) {
+ if (is_trans_port_sync_master(new_crtc_state))
+ intel_trans_port_sync_modeset_disables(state,
+ crtc,
+
old_crtc_state,
+
new_crtc_state);
+ else
+ continue;
+ } else {
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (old_crtc_state->base.active)
- intel_old_crtc_state_disables(state,
- old_crtc_state,
- new_crtc_state,
- crtc);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+ }
}
}
--
2.19.1
___
Intel-gfx mailing list
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[Intel-gfx] [PATCH v8 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave transcoder
and the master transcoder is unaware that it is operating
in this mode.
This has been tested with tiled display connected to ICL.
v7:
* Rebase on Maarten's patches
v6:
* Use master_trans +1 and address missing trans_edp case (Ville)
v5:
* Add TRANSCODER_D case and MISSING_CASE (Maarten)
v4:
Rebase
v3:
* Check of DP_MST moved to atomic_check (Maarten)
v2:
* Do not use RMW, just write to the register in commit (Jani N)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 33
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ed6198fce537..b547f28e1971 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4413,6 +4413,36 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
+static void icl_enable_trans_port_sync(const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 trans_ddi_func_ctl2_val;
+ u8 master_select;
+
+ /*
+* Configure the master select and enable Transcoder Port Sync for
+* Slave CRTCs transcoder.
+*/
+ if (crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ if (crtc_state->master_transcoder == TRANSCODER_EDP)
+ master_select = 0;
+ else
+ master_select = crtc_state->master_transcoder + 1;
+
+ /* Set the master select bits for Tranascoder Port Sync */
+ trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
+ PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
+ /* Enable Transcoder Port Sync */
+ trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
+
+ I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
+ trans_ddi_func_ctl2_val);
+}
+
static void intel_fdi_normal_train(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -6437,6 +6467,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_set_pipe_timings(pipe_config);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_enable_trans_port_sync(pipe_config);
+
intel_set_pipe_src_size(pipe_config);
if (cpu_transcoder != TRANSCODER_EDP &&
--
2.19.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 0/6] Enable Transcoder port sync for Tiled displays
This set of patches enables transcoder port sync to synchronize tiled displays across multiple SST DP ports using the master-slave model. This has been tested with kms_dp_tiled_display.c IGT test which validates the page flip synchronization. This set of patches addresses the final set of comments from Ville and Maarten. Manasi Navare (6): drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports drm/i915/display/icl: HW state readout for transcoder port sync config drm/i915/display/icl: Enable master-slaves in trans port sync drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence drm/i915/display/icl: In port sync mode disable slaves first then master drivers/gpu/drm/i915/display/intel_ddi.c | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 428 +- drivers/gpu/drm/i915/display/intel_display.h | 4 + .../drm/i915/display/intel_display_types.h| 6 + 4 files changed, 431 insertions(+), 10 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state mismatch.
v9:
* Initialize master_transcoder = INVALID at get config (Ville)
v8:
* Use master_select -1, address TRANS_EDP case (Ville)
* Rename master_transcoder to _readout (Lucas)
v7:
* NDont read HW state for DSI
v6:
* Go through both parts of HW readout (Maarten)
* Add a WARN if the same trans configured as
master and slave (Ville, Maarten)
v5:
* Add return INVALID in defaut case (Maarten)
v4:
* Get power domains in master loop for get_config (Ville)
v3:
* Add TRANSCODER_D (Maarten)
* v3 Reviewed-by: Maarten Lankhorst
v2:
* Add Transcoder_D and MISSING_CASE (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 59
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b547f28e1971..3f40fa2d8278 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10440,6 +10440,59 @@ static void haswell_get_ddi_port_state(struct
intel_crtc *crtc,
}
}
+static enum transcoder transcoder_master_readout(struct drm_i915_private
*dev_priv,
+enum transcoder cpu_transcoder)
+{
+ u32 trans_port_sync, master_select;
+
+ trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
+
+ if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
+ return INVALID_TRANSCODER;
+
+ master_select = trans_port_sync &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK;
+ if (master_select == 0)
+ return TRANSCODER_EDP;
+ else
+ return master_select - 1;
+}
+
+static void icelake_get_trans_port_sync_config(struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ u32 transcoders;
+ enum transcoder cpu_transcoder;
+
+ crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
+
crtc_state->cpu_transcoder);
+
+ transcoders = BIT(TRANSCODER_A) |
+ BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) |
+ BIT(TRANSCODER_D);
+ for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+ enum intel_display_power_domain power_domain;
+ intel_wakeref_t trans_wakeref;
+
+ power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+ trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
+
power_domain);
+
+ if (!trans_wakeref)
+ continue;
+
+ if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
+ crtc_state->cpu_transcoder)
+ crtc_state->sync_mode_slaves_mask |=
BIT(cpu_transcoder);
+
+ intel_display_power_put(dev_priv, power_domain, trans_wakeref);
+ }
+
+ WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
+ crtc_state->sync_mode_slaves_mask);
+}
+
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -10449,6 +10502,8 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
u64 power_domain_mask;
bool active;
+ pipe_config->master_transcoder = INVALID_TRANSCODER;
+
intel_crtc_init_scalers(crtc, pipe_config);
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
@@ -10559,6 +10614,10 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
pipe_config->pixel_multiplier = 1;
}
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ !transcoder_is_dsi(pipe_config->cpu_transcoder))
+ icelake_get_trans_port_sync_config(pipe_config);
+
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv,
--
2.19.1
___
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[Intel-gfx] [PATCH v8 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the transcoder port sync mode is configured and enabled
and the Vblanks of both ports are synchronized so then set DP_TP_CTL
for the slave and master to Normal and do post crtc enable updates.
v8:
* Rebase on Maarten's patches (Manasi)
v7:
* Use ffs(slaves) to get slave crtc (Ville)
v6:
* Modeset implies active_changed, remove one condition (Maarten)
v5:
* Fix checkpatch warning (Manasi)
v4:
* Reuse skl_commit_modeset_enables() hook (Maarten)
* Obtain slave crtc and states from master (Maarten)
v3:
* Rebase on drm-tip (Manasi)
v2:
* Create a icl_update_crtcs hook (Maarten, Danvet)
* This sequence only for CRTCs in trans port sync mode (Maarten)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 136 ++-
drivers/gpu/drm/i915/display/intel_display.h | 2 +
3 files changed, 137 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6c1315c7bcde..b96091800662 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3571,7 +3571,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder
*encoder,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
- if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+ if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
+ !is_trans_port_sync_mode(crtc_state))
intel_dp_stop_link_train(intel_dp);
intel_ddi_enable_fec(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3f40fa2d8278..bde142607dac 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14008,6 +14008,18 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
}
+static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *dev_priv =
to_i915(new_crtc_state->base.crtc->dev);
+ enum transcoder slave_transcoder;
+
+ WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
+
+ slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
+ return intel_get_crtc_for_pipe(dev_priv,
+ (enum pipe)slave_transcoder);
+}
+
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state
*new_crtc_state,
@@ -14086,6 +14098,113 @@ static void intel_commit_modeset_enables(struct
intel_atomic_state *state)
}
}
+static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ update_scanline_offset(new_crtc_state);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
+ intel_crtc_enable_pipe_crc(crtc);
+}
+
+static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
+ struct intel_atomic_state *state)
+{
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_dp *intel_dp;
+ int i;
+
+ for_each_new_connector_in_state(>base, conn, conn_state, i) {
+ if (conn_state->crtc == >base)
+ break;
+ }
+ intel_dp = enc_to_intel_dp(_attached_encoder(conn)->base);
+ intel_dp_stop_link_train(intel_dp);
+}
+
+static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_plane_state *new_plane_state =
+ intel_atomic_get_new_plane_state(state,
+
to_intel_plane(crtc->base.primary));
+ bool modeset = needs_modeset(new_crtc_state);
+
+ if
[Intel-gfx] [PATCH v8 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical tile that needs to be genlocked with
all other slave tiles.
This patch identifies saves the master transcoder in all the slave
CRTC states. This is needed to select the master CRTC/transcoder
while configuring transcoder port sync for the corresponding slaves.
v5:
* Address Ville's comments
* Just pass crtc_state, no need to check GEN (Ville)
v4:
* Rebase
v3:
* Use master_tramscoder instead of master_crtc for valid
HW state readouts (Ville)
v2:
* Move this to intel_mode_set_pipe_config(Jani N, Ville)
* Use slave_bitmask to save associated slaves in master crtc state (Ville)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 118 ++
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../drm/i915/display/intel_display_types.h| 6 +
3 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d1b74e8a37fe..ed6198fce537 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -519,6 +519,20 @@ needs_modeset(const struct intel_crtc_state *state)
return drm_atomic_crtc_needs_modeset(>base);
}
+bool
+is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
+ crtc_state->sync_mode_slaves_mask);
+}
+
+static bool
+is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
+ crtc_state->sync_mode_slaves_mask);
+}
+
/*
* Platform specific helpers to calculate the port PLL loopback- (clock.m),
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -11784,6 +11798,91 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->base.state);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_connector *master_connector, *connector;
+ struct drm_connector_state *connector_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc *master_crtc = NULL;
+ struct drm_crtc_state *master_crtc_state;
+ struct intel_crtc_state *master_pipe_config;
+ int i, tile_group_id;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ /*
+* In case of tiled displays there could be one or more slaves but
there is
+* only one master. Lets make the CRTC used by the connector
corresponding
+* to the last horizonal and last vertical tile a master/genlock CRTC.
+* All the other CRTCs corresponding to other tiles of the same Tile
group
+* are the slave CRTCs and hold a pointer to their genlock CRTC.
+*/
+ for_each_new_connector_in_state(>base, connector,
connector_state, i) {
+ if (connector_state->crtc != crtc)
+ continue;
+ if (!connector->has_tile)
+ continue;
+ if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
+ crtc_state->base.mode.vdisplay != connector->tile_v_size)
+ return 0;
+ if (connector->tile_h_loc == connector->num_h_tile - 1 &&
+ connector->tile_v_loc == connector->num_v_tile - 1)
+ continue;
+ crtc_state->sync_mode_slaves_mask = 0;
+ tile_group_id = connector->tile_group->id;
+ drm_connector_list_iter_begin(_priv->drm, _iter);
+ drm_for_each_connector_iter(master_connector, _iter) {
+ struct drm_connector_state *master_conn_state = NULL;
+
+ if (!master_connector->has_tile)
+ continue;
+ if (master_connector->tile_h_loc !=
master_connector->num_h_tile - 1 ||
+ master_connector->tile_v_loc !=
master_connector->num_v_tile - 1)
+ continue;
+ if (master_connector->tile_group->id != tile_group_id)
+ continue;
+
+ master_conn_state =
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Introduce Jasper Lake PCH (rev4)
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev4)
URL : https://patchwork.freedesktop.org/series/67992/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14822
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/index.html
Known issues
Here are the changes found in Patchwork_14822 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_gem_contexts:
- fi-kbl-x1275: [PASS][3] -> [INCOMPLETE][4] ([fdo#112002])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u}: [INCOMPLETE][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u/igt@debugfs_test@read_all_entries.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-tgl-u/igt@debugfs_test@read_all_entries.html
* igt@gem_basic@bad-close:
- fi-skl-6770hq: [DMESG-WARN][9] ([fdo#105541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-skl-6770hq/igt@gem_ba...@bad-close.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-skl-6770hq/igt@gem_ba...@bad-close.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927] / [fdo#111381]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ringfill@basic-default-fd:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
* igt@gem_wait@basic-busy-all:
- {fi-tgl-u2}:[INCOMPLETE][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
* igt@i915_selftest@live_gem_contexts:
- {fi-icl-dsi}: [DMESG-FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-a:
- fi-icl-u2: [TIMEOUT][19] ([fdo#111800]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u2/igt@kms_b...@basic-flip-a.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-icl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_self_import@basic-llseek-bad:
- {fi-icl-dsi}: [DMESG-WARN][21] ([fdo#106107]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14822/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
[fdo#112002]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane cdclk requirements and fp16 for gen4+ (rev2)
== Series Details ==
Series: drm/i915: Plane cdclk requirements and fp16 for gen4+ (rev2)
URL : https://patchwork.freedesktop.org/series/63373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14821
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/index.html
Known issues
Here are the changes found in Patchwork_14821 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +3
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u}: [INCOMPLETE][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-tgl-u/igt@debugfs_test@read_all_entries.html
* igt@gem_basic@bad-close:
- fi-skl-6770hq: [DMESG-WARN][7] ([fdo#105541]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-skl-6770hq/igt@gem_ba...@bad-close.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-skl-6770hq/igt@gem_ba...@bad-close.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][9] ([fdo#103927] / [fdo#111381]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ringfill@basic-default-fd:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
* igt@gem_wait@basic-busy-all:
- {fi-tgl-u2}:[INCOMPLETE][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
* igt@i915_selftest@live_gem_contexts:
- {fi-icl-dsi}: [DMESG-FAIL][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-a:
- fi-icl-u2: [TIMEOUT][17] ([fdo#111800]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u2/igt@kms_b...@basic-flip-a.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-icl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_self_import@basic-llseek-bad:
- {fi-icl-dsi}: [DMESG-WARN][19] ([fdo#106107]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14821/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
Participating hosts (52 -> 46)
--
Additional (1): fi-hsw-peppy
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
[Intel-gfx] [PATCH i-g-t 1/2 v3] NOMERGE: Import drm.h up to 54ecb8f7028c
Depends on ummerged kernel code for getfb2
Rest of drm.h taken from:
commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c
Author: Linus Torvalds
Date: Mon Sep 30 10:35:40 2019 -0700
Linux 5.4-rc1
Signed-off-by: Juston Li
---
include/drm-uapi/drm.h | 39 +++
1 file changed, 39 insertions(+)
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
index 85c685a2075e..0b02f4c92d1e 100644
--- a/include/drm-uapi/drm.h
+++ b/include/drm-uapi/drm.h
@@ -643,6 +643,7 @@ struct drm_gem_open {
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
#define DRM_CAP_SYNCOBJ0x13
+#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
@@ -729,8 +730,18 @@ struct drm_syncobj_handle {
__u32 pad;
};
+struct drm_syncobj_transfer {
+ __u32 src_handle;
+ __u32 dst_handle;
+ __u64 src_point;
+ __u64 dst_point;
+ __u32 flags;
+ __u32 pad;
+};
+
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point
to become available */
struct drm_syncobj_wait {
__u64 handles;
/* absolute timeout */
@@ -741,12 +752,33 @@ struct drm_syncobj_wait {
__u32 pad;
};
+struct drm_syncobj_timeline_wait {
+ __u64 handles;
+ /* wait on specific timeline point for every handles*/
+ __u64 points;
+ /* absolute timeout */
+ __s64 timeout_nsec;
+ __u32 count_handles;
+ __u32 flags;
+ __u32 first_signaled; /* only valid when not waiting all */
+ __u32 pad;
+};
+
+
struct drm_syncobj_array {
__u64 handles;
__u32 count_handles;
__u32 pad;
};
+struct drm_syncobj_timeline_array {
+ __u64 handles;
+ __u64 points;
+ __u32 count_handles;
+ __u32 pad;
+};
+
+
/* Query current scanout sequence number */
struct drm_crtc_get_sequence {
__u32 crtc_id; /* requested crtc_id */
@@ -903,6 +935,13 @@ extern "C" {
#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct
drm_mode_get_lease)
#define DRM_IOCTL_MODE_REVOKE_LEASEDRM_IOWR(0xC9, struct
drm_mode_revoke_lease)
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAITDRM_IOWR(0xCA, struct
drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERYDRM_IOWR(0xCB, struct
drm_syncobj_timeline_array)
+#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct
drm_syncobj_transfer)
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct
drm_syncobj_timeline_array)
+
+#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
+
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/2 v3] tests/kms_getfb: Add getfb2 tests
From: Daniel Stone
Mirroring addfb2, add tests for the new ioctl which will return us
information about framebuffers containing multiple buffers, as well as
modifiers.
Changes since v1:
- Add test that uses getfb2 output to call addfb2 as suggested by Ville
Signed-off-by: Daniel Stone
Signed-off-by: Juston Li
---
tests/kms_getfb.c | 103 ++
1 file changed, 103 insertions(+)
diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
index ca0b01c05e5c..848b896b7556 100644
--- a/tests/kms_getfb.c
+++ b/tests/kms_getfb.c
@@ -228,6 +228,106 @@ static void test_duplicate_handles(int fd)
}
}
+static void test_getfb2(int fd)
+{
+ struct drm_mode_fb_cmd2 add_basic = {};
+
+ igt_fixture {
+ struct drm_mode_fb_cmd2 get = {};
+
+ add_basic.width = 1024;
+ add_basic.height = 1024;
+ add_basic.pixel_format = DRM_FORMAT_XRGB;
+ add_basic.pitches[0] = 1024*4;
+ add_basic.handles[0] = igt_create_bo_with_dimensions(fd, 1024,
1024,
+ DRM_FORMAT_XRGB, 0, 0, NULL, NULL, NULL);
+ igt_assert(add_basic.handles[0]);
+ do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, _basic);
+
+ get.fb_id = add_basic.fb_id;
+ do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
+ igt_assert_neq_u32(get.handles[0], 0);
+ gem_close(fd, get.handles[0]);
+ }
+
+ igt_subtest("getfb2-handle-zero") {
+ struct drm_mode_fb_cmd2 get = {};
+ do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB2, , ENOENT);
+ }
+
+ igt_subtest("getfb2-handle-closed") {
+ struct drm_mode_fb_cmd2 add = add_basic;
+ struct drm_mode_fb_cmd2 get = { };
+
+ add.handles[0] = igt_create_bo_with_dimensions(fd, 1024, 1024,
+ DRM_FORMAT_XRGB, 0, 0, NULL, NULL, NULL);
+ igt_assert(add.handles[0]);
+ do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, );
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
+
+ get.fb_id = add.fb_id;
+ do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB2, , ENOENT);
+ gem_close(fd, add.handles[0]);
+ }
+
+ igt_subtest("getfb2-handle-not-fb") {
+ struct drm_mode_fb_cmd get = { .fb_id = get_any_prop_id(fd) };
+ igt_require(get.fb_id > 0);
+ do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB, , ENOENT);
+ }
+
+ igt_subtest("getfb2-accept-ccs") {
+ struct drm_mode_fb_cmd2 add_ccs = { };
+ struct drm_mode_fb_cmd2 get = { };
+ int i;
+
+ get_ccs_fb(fd, _ccs);
+ igt_require(add_ccs.fb_id != 0);
+ get.fb_id = add_ccs.fb_id;
+ do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
+
+ igt_assert_eq_u32(get.width, add_ccs.width);
+ igt_assert_eq_u32(get.height, add_ccs.height);
+ igt_assert(get.flags & DRM_MODE_FB_MODIFIERS);
+
+ for (i = 0; i < ARRAY_SIZE(get.handles); i++) {
+ igt_assert_eq_u32(get.pitches[i], add_ccs.pitches[i]);
+ igt_assert_eq_u32(get.offsets[i], add_ccs.offsets[i]);
+ if (add_ccs.handles[i] != 0) {
+ igt_assert_neq_u32(get.handles[i], 0);
+ igt_assert_neq_u32(get.handles[i],
+ add_ccs.handles[i]);
+ igt_assert_eq_u64(get.modifier[i],
+ add_ccs.modifier[i]);
+ } else {
+ igt_assert_eq_u32(get.handles[i], 0);
+ igt_assert_eq_u64(get.modifier[i], 0);
+ }
+ }
+ igt_assert_eq_u32(get.handles[0], get.handles[1]);
+
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
+ gem_close(fd, add_ccs.handles[0]);
+ gem_close(fd, get.handles[0]);
+ }
+
+ igt_subtest("getfb2-into-addfb2") {
+ struct drm_mode_fb_cmd2 cmd = { };
+
+ cmd.fb_id = add_basic.fb_id;
+ do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
+ do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, );
+
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
+ gem_close(fd, cmd.handles[0]);
+ }
+
+ igt_fixture {
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _basic.fb_id);
+ gem_close(fd, add_basic.handles[0]);
+ }
+}
+
igt_main
{
int fd;
@@ -243,6 +343,9 @@ igt_main
igt_subtest_group
test_duplicate_handles(fd);
+ igt_subtest_group
+ test_getfb2(fd);
+
igt_fixture
close(fd);
}
--
2.21.0
___
Intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Jasper Lake PCH (rev4)
== Series Details == Series: drm/i915: Introduce Jasper Lake PCH (rev4) URL : https://patchwork.freedesktop.org/series/67992/ State : warning == Summary == $ dim checkpatch origin/drm-tip af8d69d10bd5 drm/i915: Introduce Jasper Lake PCH -:30: WARNING:BAD_SIGN_OFF: Duplicate signature #30: Reviewed-by: Vivek Kasireddy total: 0 errors, 1 warnings, 0 checks, 89 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cdclk requirements and fp16 for gen4+ (rev2)
== Series Details == Series: drm/i915: Plane cdclk requirements and fp16 for gen4+ (rev2) URL : https://patchwork.freedesktop.org/series/63373/ State : warning == Summary == $ dim checkpatch origin/drm-tip d780d2521e9c drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll update 8f6777bc8259 drm/i915: Rework global state locking 592968317718 drm/i915: Move check_digital_port_conflicts() earier 3ce3e1bdf217 drm/i915: Allow planes to declare their minimum acceptable cdclk -:316: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV) #316: FILE: drivers/gpu/drm/i915/display/intel_display.c:13668: + *need_modeset |= intel_plane_calc_min_cdclk(state, plane); ^ total: 0 errors, 0 warnings, 1 checks, 770 lines checked b21fdbb98b1d drm/i915: Eliminate skl_check_pipe_max_pixel_rate() 17fd610dc415 drm/i915: Simplify skl_max_scale() 58c4817d7539 drm/i915: Add support for half float framebuffers for skl+ 2689307aa01f drm/i915: Add support for half float framebuffers for gen4+ primary planes 10d0783bf6fc drm/i915: Add support for half float framebuffers for ivb+ sprites 7fb22d625662 drm/i915: Add support for half float framebuffers on snb sprites 5ba5da60c0ef drm/i915: Move more cdclk state handling into intel_modeset_calc_cdclk() 45ef641ea5c7 drm/i915: Consolidate more cdclk state handling 667e88eaa390 drm/i915: Collect more cdclk state under the same roof ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Don't forget to set TC long detect function (rev2)
== Series Details ==
Series: drm/i915/ehl: Don't forget to set TC long detect function (rev2)
URL : https://patchwork.freedesktop.org/series/68038/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14820
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/index.html
Known issues
Here are the changes found in Patchwork_14820 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u}: [INCOMPLETE][3] -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u/igt@debugfs_test@read_all_entries.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-tgl-u/igt@debugfs_test@read_all_entries.html
* igt@gem_basic@bad-close:
- fi-skl-6770hq: [DMESG-WARN][5] ([fdo#105541]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-skl-6770hq/igt@gem_ba...@bad-close.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-skl-6770hq/igt@gem_ba...@bad-close.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927] / [fdo#111381]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ringfill@basic-default-fd:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
* igt@gem_wait@basic-busy-all:
- {fi-tgl-u2}:[INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
* igt@i915_selftest@live_gem_contexts:
- {fi-icl-dsi}: [DMESG-FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-a:
- fi-icl-u2: [TIMEOUT][15] ([fdo#111800]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u2/igt@kms_b...@basic-flip-a.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-icl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_self_import@basic-llseek-bad:
- {fi-icl-dsi}: [DMESG-WARN][17] ([fdo#106107]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14820/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
Participating hosts (52 -> 46)
--
Additional (1): fi-hsw-peppy
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7099 -> Patchwork_14820
CI-20190529: 20190529
CI_DRM_7099: fccd0abc9c05536751c60aabe5710c173fb8ffa6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14820: 00b771c3855cd257caa714b4884f02b5b35714d8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
00b771c3855c drm/i915/ehl: Don't forget to set TC long detect function
== Logs ==
For more details see:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix MST oops due to MSA changes
== Series Details ==
Series: drm/i915: Fix MST oops due to MSA changes
URL : https://patchwork.freedesktop.org/series/68053/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14819
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14819 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14819, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14819:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14819 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@bad-close:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_ba...@bad-close.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-u3/igt@gem_ba...@bad-close.html
* igt@i915_selftest@live_coherency:
- fi-glk-dsi: [PASS][5] -> [TIMEOUT][6] ([fdo#111944])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-glk-dsi/igt@i915_selftest@live_coherency.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-glk-dsi/igt@i915_selftest@live_coherency.html
* igt@i915_selftest@live_gem_contexts:
- fi-kbl-x1275: [PASS][7] -> [INCOMPLETE][8] ([fdo#112002])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u}: [INCOMPLETE][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u/igt@debugfs_test@read_all_entries.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-tgl-u/igt@debugfs_test@read_all_entries.html
* igt@gem_basic@bad-close:
- fi-skl-6770hq: [DMESG-WARN][11] ([fdo#105541]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-skl-6770hq/igt@gem_ba...@bad-close.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-skl-6770hq/igt@gem_ba...@bad-close.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][13] ([fdo#103927] / [fdo#111381]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ringfill@basic-default-fd:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
* igt@gem_wait@basic-busy-all:
- {fi-tgl-u2}:[INCOMPLETE][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
* igt@i915_selftest@live_gem_contexts:
- {fi-icl-dsi}: [DMESG-FAIL][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-a:
- fi-icl-u2: [TIMEOUT][21] ([fdo#111800]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u2/igt@kms_b...@basic-flip-a.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14819/fi-icl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_self_import@basic-llseek-bad:
- {fi-icl-dsi}: [DMESG-WARN][23] ([fdo#106107]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
[24]:
[Intel-gfx] [CI 07/12] drm/i915/tgl: Wa_1409420604
From: Mika Kuoppala
Avoid possible hang in CPSS unit.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-6-mika.kuopp...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bc5fdb4e47b1..7fea61b00b99 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -902,6 +902,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
+ /* Wa_1409420604:tgl */
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b58861b5114..449648a28a67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4056,6 +4056,9 @@ enum {
#define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
#define GWUNIT_CLKGATE_DIS(1 << 16)
+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
+#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
+
#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
#define VFUNIT_CLKGATE_DIS(1 << 20)
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 09/12] drm/i915/tgl: Wa_1409600907
From: Mika Kuoppala To avoid possible hang, we need to add depth stall if we flush the depth cache. Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-8-mika.kuopp...@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 03b961c62b97..96e28a07bc48 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3204,6 +3204,8 @@ static int gen12_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; + /* Wa_1409600907:tgl */ + flags |= PIPE_CONTROL_DEPTH_STALL; flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; flags |= PIPE_CONTROL_FLUSH_ENABLE; flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; @@ -3436,6 +3438,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) PIPE_CONTROL_TILE_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | + /* Wa_1409600907:tgl */ + PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_DC_FLUSH_ENABLE | PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_HDC_PIPELINE_FLUSH); -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 02/12] drm/i915/tgl: Add IS_TGL_REVID
From: Mika Kuoppala We are going to need this macro on limiting the workaround scope. Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-1-mika.kuopp...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c46b339064c0..f6aee1e01a7f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1686,6 +1686,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ICL_REVID(p, since, until) \ (IS_ICELAKE(p) && IS_REVID(p, since, until)) +#define TGL_REVID_A0 0x0 + +#define IS_TGL_REVID(p, since, until) \ + (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) + #define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp) #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 04/12] drm/i915/tgl: Add HDC Pipeline Flush
From: Mika Kuoppala Add hdc pipeline flush to ensure memory state is coherent in L3 when we are done. v2: Flush also in breadcrumbs (Chris) Cc: Chris Wilson Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-3-mika.kuopp...@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index afc869dc785f..4294f146f13c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -235,6 +235,7 @@ #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE(1<<10) /* GM45+ only */ #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE REG_BIT(10) /* gen12 */ #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) +#define PIPE_CONTROL_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */ #define PIPE_CONTROL_NOTIFY (1<<8) #define PIPE_CONTROL_FLUSH_ENABLE(1<<7) /* gen7+ */ #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 2fe339228b82..d03258ce8291 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3206,6 +3206,7 @@ static int gen12_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; flags |= PIPE_CONTROL_FLUSH_ENABLE; + flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; flags |= PIPE_CONTROL_STORE_DATA_INDEX; flags |= PIPE_CONTROL_QW_WRITE; @@ -3416,7 +3417,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DC_FLUSH_ENABLE | - PIPE_CONTROL_FLUSH_ENABLE); + PIPE_CONTROL_FLUSH_ENABLE | + PIPE_CONTROL_HDC_PIPELINE_FLUSH); return gen12_emit_fini_breadcrumb_footer(request, cs); } -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 10/12] drm/i915/tgl: Wa_1607138336
From: Mika Kuoppala
Avoid possible deadlock on context switch.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-9-mika.kuopp...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4f9be2eee132..483725137291 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1281,6 +1281,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_masked_en(wal,
GEN9_CS_DEBUG_MODE1,
FF_DOP_CLOCK_GATE_DISABLE);
+
+ /* Wa_1607138336:tgl */
+ wa_write_or(wal,
+ GEN9_CTX_PREEMPT_REG,
+ GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
}
if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 449648a28a67..baf5939df1ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7678,6 +7678,8 @@ enum {
#define GEN9_CS_DEBUG_MODE1_MMIO(0x20ec)
#define FF_DOP_CLOCK_GATE_DISABLEREG_BIT(1)
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
+#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
+
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
--
2.23.0
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[Intel-gfx] [CI 03/12] drm/i915/tgl: Include ro parts of l3 to invalidate
From: Mika Kuoppala Aim for completeness and invalidate also the ro parts in l3 cache. This might allow to get rid of the preparser disable/enable workaround on invalidation path. Cc: Chris Wilson Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-2-mika.kuopp...@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 8e63cffcabe0..afc869dc785f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -233,6 +233,7 @@ #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE(1<<11) /* MBZ on ILK */ #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE(1<<10) /* GM45+ only */ +#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE REG_BIT(10) /* gen12 */ #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) #define PIPE_CONTROL_NOTIFY (1<<8) #define PIPE_CONTROL_FLUSH_ENABLE(1<<7) /* gen7+ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 21635db8d76c..2fe339228b82 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3231,6 +3231,7 @@ static int gen12_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STORE_DATA_INDEX; flags |= PIPE_CONTROL_QW_WRITE; -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 12/12] drm/i915/tgl: Wa_1607138340
From: Mika Kuoppala Avoid possible cs hang with semaphores by disabling lite restore. Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-11-mika.kuopp...@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 96e28a07bc48..e55124e49f29 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1048,6 +1048,10 @@ static u64 execlists_update_context(const struct i915_request *rq) desc = ce->lrc_desc; ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE; + /* Wa_1607138340:tgl */ + if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_A0)) + desc |= CTX_DESC_FORCE_RESTORE; + return desc; } -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 08/12] drm/i915/tgl: Wa_1409170338
From: Mika Kuoppala Avoid possible hang in tsg,vfe units by keeping l3 clocks runnings. Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-7-mika.kuopp...@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 7fea61b00b99..4f9be2eee132 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -907,6 +907,12 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS); + + /* Wa_1409180338:tgl */ + if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) + wa_write_or(wal, + SLICE_UNIT_LEVEL_CLKGATE, + L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); } static void -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 06/12] drm/i915/tgl: Keep FF dop clock enabled for A0
From: Mika Kuoppala
To ensure correct state data for compute workloads, we
need to keep the ff dop clock enabled.
References: HSDES#1606700617
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-5-mika.kuopp...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 81d299b27fbc..bc5fdb4e47b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -567,7 +567,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs
*engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- /* Wa_1409142259 */
+ /* Wa_1409142259:tgl */
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
@@ -1265,6 +1265,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ /* Wa_1606700617:tgl */
+ wa_masked_en(wal,
+GEN9_CS_DEBUG_MODE1,
+FF_DOP_CLOCK_GATE_DISABLE);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 821159c4cd32..4b58861b5114 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7673,6 +7673,7 @@ enum {
#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
#define GEN9_CS_DEBUG_MODE1_MMIO(0x20ec)
+#define FF_DOP_CLOCK_GATE_DISABLEREG_BIT(1)
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
--
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[Intel-gfx] [CI 05/12] drm/i915/tgl: Add extra hdc flush workaround
From: Mika Kuoppala
In order to ensure constant caches are invalidated
properly with a0, we need extra hdc flush after invalidation.
v2: use IS_TGL_REVID (Chris)
References: HSDES#1604544889
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-4-mika.kuopp...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d03258ce8291..03b961c62b97 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3254,6 +3254,26 @@ static int gen12_emit_flush_render(struct i915_request
*request,
*cs++ = preparser_disable(false);
intel_ring_advance(request, cs);
+
+ /*
+* Wa_1604544889:tgl
+*/
+ if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ flags = 0;
+ flags |= PIPE_CONTROL_CS_STALL;
+ flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
+
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ flags |= PIPE_CONTROL_QW_WRITE;
+
+ cs = intel_ring_begin(request, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cs = gen8_emit_pipe_control(cs, flags,
+ LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(request, cs);
+ }
}
return 0;
--
2.23.0
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[Intel-gfx] [CI 01/12] drm/i915/icl: Wa_1607087056
From: Mika Kuoppala
Avoid possible hang in tsg,vfe units by keeping
l3 clocks runnings.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154411.9984-1-mika.kuopp...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ba65e5018978..81d299b27fbc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -892,6 +892,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
wa_write_or(wal,
GAMT_CHKN_BIT_REG,
GAMT_CHKN_DISABLE_L3_COH_PIPE);
+
+ /* Wa_1607087056:icl */
+ wa_write_or(wal,
+ SLICE_UNIT_LEVEL_CLKGATE,
+ L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dd126cc3ac3..821159c4cd32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4050,6 +4050,8 @@ enum {
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
#define MSCUNIT_CLKGATE_DIS (1 << 10)
+#define L3_CLKGATE_DISREG_BIT(16)
+#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
#define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
#define GWUNIT_CLKGATE_DIS(1 << 16)
--
2.23.0
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[Intel-gfx] [CI 11/12] drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627
From: Mika Kuoppala
Disable semaphore idle messages and wait for event
power downs.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-10-mika.kuopp...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 483725137291..af8a8183154a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1286,6 +1286,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+
+ /* Wa_1607030317:tgl */
+ /* Wa_1607186500:tgl */
+ /* Wa_1607297627:tgl */
+ wa_masked_en(wal,
+GEN6_RC_SLEEP_PSMI_CONTROL,
+GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index baf5939df1ec..855db888516c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2885,6 +2885,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE(1 << 12)
#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
--
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Small fixes before fixing MST (rev2)
== Series Details ==
Series: Small fixes before fixing MST (rev2)
URL : https://patchwork.freedesktop.org/series/67883/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7099 -> Patchwork_14818
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14818 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14818, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14818:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload-no-display:
- fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-bwr-2160/igt@i915_module_l...@reload-no-display.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-bwr-2160/igt@i915_module_l...@reload-no-display.html
Known issues
Here are the changes found in Patchwork_14818 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-gtt-noreloc:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_exec_re...@basic-gtt-noreloc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-icl-u3/igt@gem_exec_re...@basic-gtt-noreloc.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u}: [INCOMPLETE][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u/igt@debugfs_test@read_all_entries.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-tgl-u/igt@debugfs_test@read_all_entries.html
* igt@gem_basic@bad-close:
- fi-skl-6770hq: [DMESG-WARN][9] ([fdo#105541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-skl-6770hq/igt@gem_ba...@bad-close.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-skl-6770hq/igt@gem_ba...@bad-close.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927] / [fdo#111381]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ringfill@basic-default-fd:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
* igt@gem_wait@basic-busy-all:
- {fi-tgl-u2}:[INCOMPLETE][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-tgl-u2/igt@gem_w...@basic-busy-all.html
* igt@i915_selftest@live_gem_contexts:
- {fi-icl-dsi}: [DMESG-FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-a:
- fi-icl-u2: [TIMEOUT][19] ([fdo#111800]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-u2/igt@kms_b...@basic-flip-a.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-icl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_self_import@basic-llseek-bad:
- {fi-icl-dsi}: [DMESG-WARN][21] ([fdo#106107]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7099/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14818/fi-icl-dsi/igt@prime_self_imp...@basic-llseek-bad.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105541]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Clear semaphore immediately upon ELSP promotion (rev2)
== Series Details ==
Series: drm/i915/execlists: Clear semaphore immediately upon ELSP promotion
(rev2)
URL : https://patchwork.freedesktop.org/series/67955/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7093_full -> Patchwork_14807_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14807_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@extended-pageflip-hang-oldfb-render-f:
- {shard-tglb}: NOTRUN -> [SKIP][1] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-tglb4/igt@kms_b...@extended-pageflip-hang-oldfb-render-f.html
New tests
-
New tests have been introduced between CI_DRM_7093_full and
Patchwork_14807_full:
### New Piglit tests (2) ###
* spec@ext_texture_snorm@multisample-formats 4 gl_ext_texture_snorm:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@ext_texture_srgb@multisample-formats 2 gl_ext_texture_srgb:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_14807_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][2] -> [SKIP][3] ([fdo#110841])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +2 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-iclb6/igt@gem_exec_as...@concurrent-writes-bsd.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-apl: [PASS][6] -> [INCOMPLETE][7] ([fdo#103927]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-apl4/igt@gem_set_tiling_vs_...@tiled-to-tiled.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-apl5/igt@gem_set_tiling_vs_...@tiled-to-tiled.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-hsw: [PASS][8] -> [DMESG-WARN][9] ([fdo#111870])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-hsw5/igt@gem_userptr_bl...@dmabuf-unsync.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-hsw4/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][10] -> [DMESG-WARN][11] ([fdo#111870])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-snb6/igt@gem_userptr_bl...@sync-unmap.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-snb7/igt@gem_userptr_bl...@sync-unmap.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][12] -> [INCOMPLETE][13] ([fdo#103665])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-kbl2/igt@gem_workarou...@suspend-resume-fd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][14] -> [DMESG-FAIL][15] ([fdo#111991])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-hsw6/igt@i915_selftest@live_hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-hsw4/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [PASS][16] -> [DMESG-WARN][17] ([fdo#106107])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-skl10/igt@kms_co...@pipe-a-ctm-0-5.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-skl7/igt@kms_co...@pipe-a-ctm-0-5.html
* igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-xtiled:
- shard-skl: [PASS][18] -> [FAIL][19] ([fdo#103184] / [fdo#103232])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-skl5/igt@kms_draw_...@draw-method-xrgb2101010-pwrite-xtiled.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14807/shard-skl9/igt@kms_draw_...@draw-method-xrgb2101010-pwrite-xtiled.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html
[21]:
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Introduce Jasper Lake PCH (rev3)
On Tue, Oct 15, 2019 at 07:42:03PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Introduce Jasper Lake PCH (rev3)
> URL : https://patchwork.freedesktop.org/series/67992/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14817
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14817 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14817, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14817:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live_gem_contexts:
> - fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Selftest timeout failure; not related to PCH changes here. Will request
a re-test.
(i915_selftest:4885) igt_kmod-WARNING: i915: probe of :00:02.0 failed with
error -62
(i915_selftest:4885) igt_kmod-CRITICAL: Test assertion failure function
igt_kselftest_execute, file ../lib/igt_kmod.c:548:
(i915_selftest:4885) igt_kmod-CRITICAL: Failed assertion: err == 0
(i915_selftest:4885) igt_kmod-CRITICAL: kselftest "i915
igt__31__live_gem_contexts=1 live_selftests=-1 disable_display=1 st_filter="
failed: Timer expired [62]
Subtest live_gem_contexts failed.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@i915_selftest@live_hangcheck:
> - {fi-cml-s}: [PASS][3] -> [DMESG-FAIL][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-cml-s/igt@i915_selftest@live_hangcheck.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-cml-s/igt@i915_selftest@live_hangcheck.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14817 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_basic@create-close:
> - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ba...@create-close.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-icl-u3/igt@gem_ba...@create-close.html
>
>
> Possible fixes
>
> * igt@gem_ctx_create@basic-files:
> - fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8]
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
> - fi-icl-u3: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
> [PASS][10]
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
>
> * igt@i915_selftest@live_execlists:
> - fi-apl-guc: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-apl-guc/igt@i915_selftest@live_execlists.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-apl-guc/igt@i915_selftest@live_execlists.html
>
> * igt@i915_selftest@live_hangcheck:
> - {fi-icl-u4}:[INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) ->
> [PASS][14]
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>
>
> Warnings
>
> * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16]
> ([fdo#111045] / [fdo#111096])
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Small fixes before fixing MST (rev2)
== Series Details == Series: Small fixes before fixing MST (rev2) URL : https://patchwork.freedesktop.org/series/67883/ State : warning == Summary == $ dim checkpatch origin/drm-tip dd2c2adfc049 drm/i915: simplify setting of ddi_io_power_domain 7d4e878c74b2 drm/i915: fix port checks for MST support on gen >= 11 851e808be6ce drm/i915: remove extra new line on pipe_config mismatch -:52: WARNING:LONG_LINE: line over 100 characters #52: FILE: drivers/gpu/drm/i915/display/intel_display.c:12607: +"unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ total: 0 errors, 1 warnings, 0 checks, 88 lines checked 28fedf7760f7 drm/i915: add pipe id/name to pipe mismatch logs 3b66197dbde8 drm/i915: prettify MST debug message ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Introduce Jasper Lake PCH (rev3)
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev3)
URL : https://patchwork.freedesktop.org/series/67992/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14817
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14817 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14817, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14817:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_hangcheck:
- {fi-cml-s}: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-cml-s/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-cml-s/igt@i915_selftest@live_hangcheck.html
Known issues
Here are the changes found in Patchwork_14817 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-close:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ba...@create-close.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-icl-u3/igt@gem_ba...@create-close.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
- fi-icl-u3: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-apl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-apl-guc/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}:[INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111045]
/ [fdo#111096])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14817/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 44)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan
fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7098 -> Patchwork_14817
CI-20190529: 20190529
CI_DRM_7098: 4e4fe1f2e2ff11f066e3ea4706dec0dded6925e5 @
[Intel-gfx] [PATCH v2 13/13] drm/i915: Collect more cdclk state under the same roof
From: Ville Syrjälä
Move the min_cdclk[] and min_voltage_level[] arrays under the
rest of the cdclk state. And while at it provide a simple
helper (intel_cdclk_clear_state()) to clear the state during
the ww_mutex backoff dance.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 ++---
drivers/gpu/drm/i915/display/intel_cdclk.c| 40 ---
drivers/gpu/drm/i915/display/intel_cdclk.h| 1 +
drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
.../drm/i915/display/intel_display_types.h| 10 +++--
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
6 files changed, 46 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 9cd6d2348a1e..6b2cddb3c867 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -35,6 +35,7 @@
#include
#include "intel_atomic.h"
+#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
#include "intel_sprite.h"
@@ -427,15 +428,13 @@ intel_atomic_state_alloc(struct drm_device *dev)
void intel_atomic_state_clear(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
+
drm_atomic_state_default_clear(>base);
+
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
state->active_pipes = 0;
- memset(>min_cdclk, 0, sizeof(state->min_cdclk));
- memset(>min_voltage_level, 0, sizeof(state->min_voltage_level));
- memset(>cdclk.logical, 0, sizeof(state->cdclk.logical));
- memset(>cdclk.actual, 0, sizeof(state->cdclk.actual));
- state->cdclk.pipe = INVALID_PIPE;
+ intel_cdclk_clear_state(state);
}
struct intel_crtc_state *
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f6e2048dd2b8..41e2f0298d41 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1801,6 +1801,18 @@ static bool intel_cdclk_changed(const struct
intel_cdclk_state *a,
a->voltage_level != b->voltage_level;
}
+/**
+ * intel_cdclk_clear_state - clear the cdclk state
+ * @state: atomic state
+ *
+ * Clear the cdclk state for ww_mutex backoff.
+ */
+void intel_cdclk_clear_state(struct intel_atomic_state *state)
+{
+ memset(>cdclk, 0, sizeof(state->cdclk));
+ state->cdclk.pipe = INVALID_PIPE;
+}
+
/**
* intel_cdclk_swap_state - make atomic CDCLK configuration effective
* @state: atomic state
@@ -1818,10 +1830,10 @@ void intel_cdclk_swap_state(struct intel_atomic_state
*state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
/* FIXME maybe swap() these too */
- memcpy(dev_priv->min_cdclk, state->min_cdclk,
- sizeof(state->min_cdclk));
- memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
- sizeof(state->min_voltage_level));
+ memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk,
+ sizeof(state->cdclk.min_cdclk));
+ memcpy(dev_priv->cdclk.min_voltage_level,
state->cdclk.min_voltage_level,
+ sizeof(state->cdclk.min_voltage_level));
dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
@@ -2034,10 +2046,10 @@ static int intel_compute_min_cdclk(struct
intel_atomic_state *state)
if (min_cdclk < 0)
return min_cdclk;
- if (state->min_cdclk[i] == min_cdclk)
+ if (state->cdclk.min_cdclk[i] == min_cdclk)
continue;
- state->min_cdclk[i] = min_cdclk;
+ state->cdclk.min_cdclk[i] = min_cdclk;
ret = intel_atomic_lock_global_state(state);
if (ret)
@@ -2046,7 +2058,7 @@ static int intel_compute_min_cdclk(struct
intel_atomic_state *state)
min_cdclk = state->cdclk.force_min_cdclk;
for_each_pipe(dev_priv, pipe)
- min_cdclk = max(state->min_cdclk[pipe], min_cdclk);
+ min_cdclk = max(state->cdclk.min_cdclk[pipe], min_cdclk);
return min_cdclk;
}
@@ -2081,10 +2093,10 @@ static int bxt_compute_min_voltage_level(struct
intel_atomic_state *state)
else
min_voltage_level = 0;
- if (state->min_voltage_level[i] == min_voltage_level)
+ if (state->cdclk.min_voltage_level[i] == min_voltage_level)
continue;
- state->min_voltage_level[i] = min_voltage_level;
+ state->cdclk.min_voltage_level[i] = min_voltage_level;
ret = intel_atomic_lock_global_state(state);
if (ret)
@@ -2093,7 +2105,7 @@ static int bxt_compute_min_voltage_level(struct
intel_atomic_state *state)
min_voltage_level = 0;
for_each_pipe(dev_priv, pipe)
[Intel-gfx] [PATCH v2 12/13] drm/i915: Consolidate more cdclk state handling
From: Ville Syrjälä
Move the initial setup of state->min_cdclk[]/min_voltage_level[]
into intel_modeset_calc_cdclk() alongside the rest of the global
cdclk state. And the counterparts we move into
intel_cdclk_swap_state().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +--
drivers/gpu/drm/i915/display/intel_display.c | 5 -
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 27addbd35d9c..f6e2048dd2b8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1817,6 +1817,14 @@ void intel_cdclk_swap_state(struct intel_atomic_state
*state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ /* FIXME maybe swap() these too */
+ memcpy(dev_priv->min_cdclk, state->min_cdclk,
+ sizeof(state->min_cdclk));
+ memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
+ sizeof(state->min_voltage_level));
+
+ dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
+
swap(state->cdclk.logical, dev_priv->cdclk.logical);
swap(state->cdclk.actual, dev_priv->cdclk.actual);
}
@@ -2019,9 +2027,6 @@ static int intel_compute_min_cdclk(struct
intel_atomic_state *state)
int min_cdclk, i;
enum pipe pipe;
- memcpy(state->min_cdclk, dev_priv->min_cdclk,
- sizeof(state->min_cdclk));
-
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2068,9 +2073,6 @@ static int bxt_compute_min_voltage_level(struct
intel_atomic_state *state)
int i;
enum pipe pipe;
- memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
- sizeof(state->min_voltage_level));
-
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2325,6 +2327,11 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
enum pipe pipe;
int ret;
+ memcpy(state->min_cdclk, dev_priv->min_cdclk,
+ sizeof(state->min_cdclk));
+ memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
+ sizeof(state->min_voltage_level));
+
/* keep the current setting */
if (!state->cdclk.force_min_cdclk_changed)
state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 94fec0958f39..8e607dad87d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14453,12 +14453,7 @@ static int intel_atomic_commit(struct drm_device *dev,
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
- memcpy(dev_priv->min_cdclk, state->min_cdclk,
- sizeof(state->min_cdclk));
- memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
- sizeof(state->min_voltage_level));
dev_priv->active_pipes = state->active_pipes;
- dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
intel_cdclk_swap_state(state);
}
--
2.21.0
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[Intel-gfx] [PATCH v2 11/13] drm/i915: Move more cdclk state handling into intel_modeset_calc_cdclk()
From: Ville Syrjälä
Encapsulate the cdclk state handling a bit better by performing
the copy from dev_priv->cdclk into the current intel_atomic_state
within the cdclk code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++
drivers/gpu/drm/i915/display/intel_display.c | 6 --
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0caef2592a7e..27addbd35d9c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2325,6 +2325,13 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
enum pipe pipe;
int ret;
+ /* keep the current setting */
+ if (!state->cdclk.force_min_cdclk_changed)
+ state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
+
+ state->cdclk.logical = dev_priv->cdclk.logical;
+ state->cdclk.actual = dev_priv->cdclk.actual;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2a77d5d5051a..94fec0958f39 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13525,14 +13525,8 @@ static int intel_modeset_checks(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
- /* keep the current setting */
- if (!state->cdclk.force_min_cdclk_changed)
- state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
-
state->modeset = true;
state->active_pipes = dev_priv->active_pipes;
- state->cdclk.logical = dev_priv->cdclk.logical;
- state->cdclk.actual = dev_priv->cdclk.actual;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
--
2.21.0
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[Intel-gfx] [PATCH v2 10/13] drm/i915: Add support for half float framebuffers on snb sprites
From: Ville Syrjälä
snb supports fp16 pixel formats on the sprite planes. Expose that
capability. Nothing special needs to be done, it just works.
v2: Rebase on top of icl fp16
Split snb+ sprite bits into a separate patch
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index db1e2dce6636..edc41fc40726 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1653,6 +1653,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
dvscntr |= DVS_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR16161616F:
+ dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR;
+ break;
+ case DRM_FORMAT_XRGB16161616F:
+ dvscntr |= DVS_FORMAT_RGBX161616;
+ break;
case DRM_FORMAT_YUYV:
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
break;
@@ -2367,8 +2373,10 @@ static const u64 i9xx_plane_format_modifiers[] = {
};
static const u32 snb_plane_formats[] = {
- DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
--
2.21.0
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[Intel-gfx] [PATCH v2 09/13] drm/i915: Add support for half float framebuffers for ivb+ sprites
From: Ville Syrjälä
ivb+ supports fp16 pixel formats on the sprite planes planes. Expose
that capability.
On ivb/hsw fp16 scanout is slightly busted. The output from the plane
will have 1/4 the expected value. For the sprite plane we can fix that
up with the plane gamma unit. This was fixed on bdw.
v2: Rebase on top of icl fp16
Split the ivb+ sprite birs into a separate patch
v3: Move ivb_need_sprite_gamma() check one level up so that
we don't waste time programming garbage into he gamma registers
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 48 ++---
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index e8442299989b..db1e2dce6636 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1316,6 +1316,16 @@ static u32 ivb_sprite_ctl_crtc(const struct
intel_crtc_state *crtc_state)
return sprctl;
}
+static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+
+ return fb->format->cpp[0] == 8 &&
+ (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv));
+}
+
static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -1338,6 +1348,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
sprctl |= SPRITE_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR16161616F:
+ sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX;
+ break;
+ case DRM_FORMAT_XRGB16161616F:
+ sprctl |= SPRITE_FORMAT_RGBX161616;
+ break;
case DRM_FORMAT_YUYV:
sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
break;
@@ -1355,7 +1371,8 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
return 0;
}
- sprctl |= SPRITE_INT_GAMMA_DISABLE;
+ if (!ivb_need_sprite_gamma(plane_state))
+ sprctl |= SPRITE_INT_GAMMA_DISABLE;
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
@@ -1377,12 +1394,26 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
return sprctl;
}
-static void ivb_sprite_linear_gamma(u16 gamma[18])
+static void ivb_sprite_linear_gamma(const struct intel_plane_state
*plane_state,
+ u16 gamma[18])
{
- int i;
+ int scale, i;
- for (i = 0; i < 17; i++)
- gamma[i] = (i << 10) / 16;
+ /*
+* WaFP16GammaEnabling:ivb,hsw
+* "Workaround : When using the 64-bit format, the sprite output
+* on each color channel has one quarter amplitude. It can be
+* brought up to full amplitude by using sprite internal gamma
+* correction, pipe gamma correction, or pipe color space
+* conversion to multiply the sprite output by four."
+*/
+ scale = 4;
+
+ for (i = 0; i < 16; i++)
+ gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1);
+
+ gamma[i] = min((scale * i << 10) / 16, 1 << 10);
+ i++;
gamma[i] = 3 << 10;
i++;
@@ -1396,7 +1427,10 @@ static void ivb_update_gamma(const struct
intel_plane_state *plane_state)
u16 gamma[18];
int i;
- ivb_sprite_linear_gamma(gamma);
+ if (!ivb_need_sprite_gamma(plane_state))
+ return;
+
+ ivb_sprite_linear_gamma(plane_state, gamma);
/* FIXME these register are single buffered :( */
for (i = 0; i < 16; i++)
@@ -2551,6 +2585,8 @@ static bool snb_sprite_format_mod_supported(struct
drm_plane *_plane,
switch (format) {
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
--
2.21.0
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[Intel-gfx] [PATCH v2 08/13] drm/i915: Add support for half float framebuffers for gen4+ primary planes
From: Ville Syrjälä
gen4+ supports fp16 pixel formats on the primary planes. Add the
relevant code.
On ivb fp16 scanout is slightly busted. The output from the plane will
have 1/4 the expected value. For the primary plane we would have to
use the pipe gamma or pipe csc to correct that which would affect all
the other planes as well, hence we simply choose not to expose fp16
on the ivb primary plane. On hsw the primary plane got fixed.
On gmch platforms I observed that the plane width must be below 2k
pixels with fp16 or else we get a corrupted image. This limitation
does not seem to be documented in bspec. I verified the exact limit
using the chv pipe B primary plane since it has windowing capability.
The stride limits are unaffected by fp16.
v2: Rebase on top of icl fp16
Split thea gen4+ primary plane bits into a separate patch
Deal with HAS_GMCH()
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 49 ++--
1 file changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 64e1e5e933e0..2a77d5d5051a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -88,7 +88,17 @@ static const u32 i8xx_primary_formats[] = {
DRM_FORMAT_XRGB,
};
-/* Primary plane formats for gen >= 4 */
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
static const u32 i965_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -96,6 +106,7 @@ static const u32 i965_primary_formats[] = {
DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
};
static const u64 i9xx_format_modifiers[] = {
@@ -2957,6 +2968,8 @@ static int i9xx_format_to_fourcc(int format)
return DRM_FORMAT_XRGB2101010;
case DISPPLANE_RGBX101010:
return DRM_FORMAT_XBGR2101010;
+ case DISPPLANE_RGBX161616:
+ return DRM_FORMAT_XBGR16161616F;
}
}
@@ -3693,6 +3706,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XBGR2101010:
dspcntr |= DISPPLANE_RGBX101010;
break;
+ case DRM_FORMAT_XBGR16161616F:
+ dspcntr |= DISPPLANE_RGBX161616;
+ break;
default:
MISSING_CASE(fb->format->format);
return 0;
@@ -3715,7 +3731,8 @@ int i9xx_check_plane_surface(struct intel_plane_state
*plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- int src_x, src_y;
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ int src_x, src_y, src_w;
u32 offset;
int ret;
@@ -3726,9 +3743,14 @@ int i9xx_check_plane_surface(struct intel_plane_state
*plane_state)
if (!plane_state->base.visible)
return 0;
+ src_w = drm_rect_width(_state->base.src) >> 16;
src_x = plane_state->base.src.x1 >> 16;
src_y = plane_state->base.src.y1 >> 16;
+ /* Undocumented hardware limit on i965/g4x/vlv/chv */
+ if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
+ return -EINVAL;
+
intel_add_fb_offsets(_x, _y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
@@ -14764,6 +14786,7 @@ static bool i965_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_XBGR:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
return modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED;
default:
@@ -14984,8 +15007,26 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
}
if (INTEL_GEN(dev_priv) >= 4) {
- formats = i965_primary_formats;
- num_formats = ARRAY_SIZE(i965_primary_formats);
+ /*
+* WaFP16GammaEnabling:ivb
+* "Workaround : When using the 64-bit format, the plane
+* output on each color channel has one quarter amplitude.
+* It can be brought up to full amplitude by using pipe
+* gamma correction or pipe color space conversion to
+* multiply the plane output by four."
+*
+* There is no dedicated plane gamma for the primary plane,
+* and using the pipe gamma/csc could conflict with other
+
[Intel-gfx] [PATCH v2 05/13] drm/i915: Eliminate skl_check_pipe_max_pixel_rate()
From: Ville Syrjälä
The normal cdclk handling now takes care of making sure the
plane's pixel rate doesn't exceed the spec appointed percentage
of the cdclk frequency. Thus we can nuke
skl_check_pipe_max_pixel_rate().
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 -
drivers/gpu/drm/i915/intel_pm.c | 87
drivers/gpu/drm/i915/intel_pm.h | 2 -
3 files changed, 91 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 67bb5fa03b2b..cbc807ea08c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11887,8 +11887,6 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 9) {
if (mode_changed || crtc_state->update_pipe)
ret = skl_update_scaler_crtc(crtc_state);
- if (!ret)
- ret = skl_check_pipe_max_pixel_rate(crtc, crtc_state);
if (!ret)
ret = intel_atomic_setup_scalers(dev_priv, crtc,
crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b306e2338f5a..643b6b65fba8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4096,93 +4096,6 @@ skl_plane_downscale_amount(const struct intel_crtc_state
*crtc_state,
return mul_fixed16(downscale_w, downscale_h);
}
-static uint_fixed_16_16_t
-skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
-{
- uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
-
- if (!crtc_state->base.enable)
- return pipe_downscale;
-
- if (crtc_state->pch_pfit.enabled) {
- u32 src_w, src_h, dst_w, dst_h;
- u32 pfit_size = crtc_state->pch_pfit.size;
- uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
- uint_fixed_16_16_t downscale_h, downscale_w;
-
- src_w = crtc_state->pipe_src_w;
- src_h = crtc_state->pipe_src_h;
- dst_w = pfit_size >> 16;
- dst_h = pfit_size & 0x;
-
- if (!dst_w || !dst_h)
- return pipe_downscale;
-
- fp_w_ratio = div_fixed16(src_w, dst_w);
- fp_h_ratio = div_fixed16(src_h, dst_h);
- downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
- downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
-
- pipe_downscale = mul_fixed16(downscale_w, downscale_h);
- }
-
- return pipe_downscale;
-}
-
-int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- struct drm_atomic_state *state = crtc_state->base.state;
- const struct intel_plane_state *plane_state;
- struct intel_plane *plane;
- int crtc_clock, dotclk;
- u32 pipe_max_pixel_rate;
- uint_fixed_16_16_t pipe_downscale;
- uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
-
- if (!crtc_state->base.enable)
- return 0;
-
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
crtc_state) {
- uint_fixed_16_16_t plane_downscale;
- uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
- int bpp;
-
- if (!intel_wm_plane_visible(crtc_state, plane_state))
- continue;
-
- if (WARN_ON(!plane_state->base.fb))
- return -EINVAL;
-
- plane_downscale = skl_plane_downscale_amount(crtc_state,
plane_state);
- bpp = plane_state->base.fb->format->cpp[0] * 8;
- if (bpp == 64)
- plane_downscale = mul_fixed16(plane_downscale,
- fp_9_div_8);
-
- max_downscale = max_fixed16(plane_downscale, max_downscale);
- }
- pipe_downscale = skl_pipe_downscale_amount(crtc_state);
-
- pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
-
- crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
- dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
-
- if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
- dotclk *= 2;
-
- pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
-
- if (pipe_max_pixel_rate < crtc_clock) {
- DRM_DEBUG_KMS("Max supported pixel clock with scaling
exceeded\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
[Intel-gfx] [PATCH v2 01/13] drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll update
From: Ville Syrjälä
To make the logs a bit less confusing let's toss in some
debug prints to indicate whether the cdclk reprogramming
is going to happen with a single pipe active or whether we
need to turn all pipes off for the duration.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3d867963a6d1..6eaebc38ee01 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2343,6 +2343,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
return ret;
state->cdclk.pipe = pipe;
+
+ DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n",
+ pipe_name(pipe));
} else if (intel_cdclk_needs_modeset(_priv->cdclk.actual,
>cdclk.actual)) {
ret = intel_modeset_all_pipes(state);
@@ -2350,6 +2353,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
return ret;
state->cdclk.pipe = INVALID_PIPE;
+
+ DRM_DEBUG_KMS("Modeset required for cdclk change\n");
}
DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u
kHz\n",
--
2.21.0
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[Intel-gfx] [PATCH v2 00/13] drm/i915: Plane cdclk requirements and fp16 for gen4+
From: Ville Syrjälä Several patches have been pushed, new patches have appeared at the end. I wonder if I've invented a perpetual motion patch series... The new stuff is mostly just cleaning up the cdclk state (mis)management we have going on. I also modifier the global state locking stuff a bit to make sure we correctly serialize the hardware stuff when cdclk actually changes (and we need it for the QGV stuff as well). I also tweaked the debug messages to trigger only when a plane actually needs to bump the cdclk. Previously it would print that stuff all the time. Ville Syrjälä (13): drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll update drm/i915: Rework global state locking drm/i915: Move check_digital_port_conflicts() earier drm/i915: Allow planes to declare their minimum acceptable cdclk drm/i915: Eliminate skl_check_pipe_max_pixel_rate() drm/i915: Simplify skl_max_scale() drm/i915: Add support for half float framebuffers for skl+ drm/i915: Add support for half float framebuffers for gen4+ primary planes drm/i915: Add support for half float framebuffers for ivb+ sprites drm/i915: Add support for half float framebuffers on snb sprites drm/i915: Move more cdclk state handling into intel_modeset_calc_cdclk() drm/i915: Consolidate more cdclk state handling drm/i915: Collect more cdclk state under the same roof drivers/gpu/drm/i915/display/intel_atomic.c | 43 ++ drivers/gpu/drm/i915/display/intel_atomic.h | 5 + .../gpu/drm/i915/display/intel_atomic_plane.c | 39 ++ .../gpu/drm/i915/display/intel_atomic_plane.h | 2 + drivers/gpu/drm/i915/display/intel_audio.c| 10 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 167 --- drivers/gpu/drm/i915/display/intel_cdclk.h| 1 + drivers/gpu/drm/i915/display/intel_display.c | 339 ++ drivers/gpu/drm/i915/display/intel_display.h | 2 - .../drm/i915/display/intel_display_types.h| 22 +- drivers/gpu/drm/i915/display/intel_sprite.c | 428 +- drivers/gpu/drm/i915/display/intel_sprite.h | 7 + drivers/gpu/drm/i915/i915_drv.h | 20 +- drivers/gpu/drm/i915/intel_pm.c | 87 drivers/gpu/drm/i915/intel_pm.h | 2 - 15 files changed, 914 insertions(+), 260 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 07/13] drm/i915: Add support for half float framebuffers for skl+
From: Ville Syrjälä
skl+ supports fp16 pixel formats on all universal planes. Add the
necessary bits to expose that capability. The main different to
icl is that we can't scale fp16, so need to add the relevant
checks.
v2: Rebase on top of icl fp16
Split skl+ bits into a separate patch
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e31a8af808f5..64e1e5e933e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5577,10 +5577,6 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_ARGB:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ABGR16161616F:
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -5596,6 +5592,13 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
break;
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ if (INTEL_GEN(dev_priv) >= 11)
+ break;
+ /* fall through */
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
intel_plane->base.base.id, intel_plane->base.name,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 6b2eaf26700c..e8442299989b 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1832,6 +1832,11 @@ static bool intel_fb_scalable(const struct
drm_framebuffer *fb)
switch (fb->format->format) {
case DRM_FORMAT_C8:
return false;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return INTEL_GEN(to_i915(fb->dev)) >= 11;
default:
return true;
}
@@ -2359,6 +2364,8 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2374,6 +2381,8 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2390,6 +2399,8 @@ static const u32 glk_planar_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
--
2.21.0
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[Intel-gfx] [PATCH v2 02/13] drm/i915: Rework global state locking
From: Ville Syrjälä
So far we've sort of protected the global state under dev_priv with
the connection_mutex. I wan to change that so that we can change the
cdclk even for pure plane updates. To that end let's formalize the
protection of the global state to follow what I started with the cdclk
code already (though not entirely properly) such that any crtc mutex
will suffice as a read lock, and all crtcs mutexes act as the write
lock.
We'll also pimp intel_atomic_state_clear() to clear the entire global
state, so that we don't accidentally leak stale information between
the locking retries.
As a slight optimization we'll only lock the crtc mutexes to protect
the global state, however if and when we actually have to poke the
hw (eg. if the actual cdclk changes) we must serialize commits
across all crtcs so that a parallel nonblocking commit can't get
ahead of the cdclk reprogamming. We do that by adding all crtcs to
the state.
TODO: the old global state examined during commit may still
be a problem since it always looks at the _latest_ swapped state
in dev_priv. Need to add proper old/new state for that too I think.
v2: Remeber to serialize the commits if necessary
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 44
drivers/gpu/drm/i915/display/intel_atomic.h | 5 +
drivers/gpu/drm/i915/display/intel_audio.c| 10 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 102 ++
drivers/gpu/drm/i915/display/intel_display.c | 29 -
.../drm/i915/display/intel_display_types.h| 8 ++
drivers/gpu/drm/i915/i915_drv.h | 11 +-
7 files changed, 153 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index c5a552a69752..9cd6d2348a1e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -429,6 +429,13 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
struct intel_atomic_state *state = to_intel_atomic_state(s);
drm_atomic_state_default_clear(>base);
state->dpll_set = state->modeset = false;
+ state->global_state_changed = false;
+ state->active_pipes = 0;
+ memset(>min_cdclk, 0, sizeof(state->min_cdclk));
+ memset(>min_voltage_level, 0, sizeof(state->min_voltage_level));
+ memset(>cdclk.logical, 0, sizeof(state->cdclk.logical));
+ memset(>cdclk.actual, 0, sizeof(state->cdclk.actual));
+ state->cdclk.pipe = INVALID_PIPE;
}
struct intel_crtc_state *
@@ -442,3 +449,40 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
return to_intel_crtc_state(crtc_state);
}
+
+int intel_atomic_lock_global_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ state->global_state_changed = true;
+
+ for_each_intel_crtc(_priv->drm, crtc) {
+ int ret;
+
+ ret = drm_modeset_lock(>base.mutex,
+ state->base.acquire_ctx);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ state->global_state_changed = true;
+
+ for_each_intel_crtc(_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ crtc_state = intel_atomic_get_crtc_state(>base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..49d5cb1b9e0a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -16,6 +16,7 @@ struct drm_crtc_state;
struct drm_device;
struct drm_i915_private;
struct drm_property;
+struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
@@ -46,4 +47,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state);
+int intel_atomic_lock_global_state(struct intel_atomic_state *state);
+
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
#endif /* __INTEL_ATOMIC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index ed18511befa3..85e6b2bbb34f 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -28,6 +28,7 @@
#include
#include "i915_drv.h"
+#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_display_types.h"
#include
[Intel-gfx] [PATCH v2 04/13] drm/i915: Allow planes to declare their minimum acceptable cdclk
From: Ville Syrjälä
Various pixel formats and plane scaling impose additional constraints
on the cdclk frequency. Provide a new plane->min_cdclk() hook that
will be used to compute the minimum acceptable cdclk frequency for
each plane.
Annoyingly on some platforms the numer of active planes affects
this calculation so we must also toss in more planes into the
state when the number of active planes changes.
The sequence of state computation must also be changed:
1. check_plane() (updates plane's visibility etc.)
2. figure out if more planes now require update min_cdclk
computaion
3. calculate the new min cdclk for each plane in the state
4. if the minimum of any plane now exceeds the current
logical cdclk we recompute the cdclk
4. during cdclk computation take the planes' min_cdclk into
accoutn
5. follow the normal cdclk programming to change the
cdclk frequency. This may now require a modeset (except
on bxt/glk in some cases), which either succeeds or
fails depending on whether userspace has given
us permission to perform a modeset or not.
v2: Fix plane id check in intel_crtc_add_planes_to_state()
Only print the debug message when cdclk needs bumping
Use dev_priv->cdclk... as the old state explicitly
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 39 ++
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_cdclk.c| 16 +
drivers/gpu/drm/i915/display/intel_display.c | 184 --
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_sprite.c | 341 ++
drivers/gpu/drm/i915/display/intel_sprite.h | 7 +
7 files changed, 571 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index a6cff5a160fb..98f557a9f8ee 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -138,6 +138,44 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
return cpp * crtc_state->pixel_rate;
}
+bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct intel_plane_state *plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
+ struct intel_crtc_state *crtc_state;
+
+ if (!plane_state->base.visible || !plane->min_cdclk)
+ return false;
+
+ crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ crtc_state->min_cdclk[plane->id] =
+ plane->min_cdclk(crtc_state, plane_state);
+
+ /*
+* Does the cdclk need to be bumbed up?
+*
+* Note: we obviously need to be called before the new
+* cdclk frequency is calculated so state->cdclk.logical
+* hasn't been populated yet. Hence we look at the old
+* cdclk state under dev_priv->cdclk.logical. This is
+* safe as long we hold at least one crtc mutex (which
+* must be true since we have crtc_state).
+*/
+ if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) {
+ DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk
(%d kHz)\n",
+ plane->base.base.id, plane->base.name,
+ crtc_state->min_cdclk[plane->id],
+ dev_priv->cdclk.logical.cdclk);
+ return true;
+ }
+
+ return false;
+}
+
int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
@@ -151,6 +189,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
+ new_crtc_state->min_cdclk[plane->id] = 0;
new_plane_state->base.visible = false;
if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index dc85af02e9b7..e61e9a82aadf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -47,5 +47,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
struct intel_crtc_state *crtc_state,
const struct intel_plane_state
[Intel-gfx] [PATCH v2 06/13] drm/i915: Simplify skl_max_scale()
From: Ville Syrjälä
Now that the planes declare their minimum cdclk requirements properly
we don't need to check the cdclk in skl_max_scale() anymore. Just check
against the maximum downscale ratio, and move the code next to it's
only caller.
v2: Add a comment explaining the HQ vs. not thing
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 38
drivers/gpu/drm/i915/display/intel_display.h | 2 --
drivers/gpu/drm/i915/display/intel_sprite.c | 18 +-
3 files changed, 17 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cbc807ea08c5..e31a8af808f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14707,44 +14707,6 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
intel_plane_unpin_fb(old_plane_state);
}
-int
-skl_max_scale(const struct intel_crtc_state *crtc_state,
- const struct drm_format_info *format)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int max_scale;
- int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
-
- if (!crtc_state->base.enable)
- return DRM_PLANE_HELPER_NO_SCALING;
-
- crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
- max_dotclk =
to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
-
- if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
- max_dotclk *= 2;
-
- if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
- return DRM_PLANE_HELPER_NO_SCALING;
-
- /*
-* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
-*or
-*cdclk/crtc_clock
-*/
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
- !drm_format_info_is_yuv_semiplanar(format))
- tmpclk1 = 0x3 - 1;
- else
- tmpclk1 = 0x2 - 1;
- tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
- max_scale = min(tmpclk1, tmpclk2);
-
- return max_scale;
-}
-
/**
* intel_plane_destroy - destroy a plane
* @plane: plane to destroy
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index bed203ec1df8..c7ec8984f007 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -558,8 +558,6 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(const struct intel_crtc_state *crtc_state,
- const struct drm_format_info *format);
u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 469f79b01114..6b2eaf26700c 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2120,6 +2120,22 @@ static int skl_plane_check_nv12_rotation(const struct
intel_plane_state *plane_s
return 0;
}
+static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
+ const struct drm_framebuffer *fb)
+{
+ /*
+* We don't yet know the final source width nor
+* whether we can use the HQ scaler mode. Assume
+* the best case.
+* FIXME need to properly check this later.
+*/
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
+ !drm_format_info_is_yuv_semiplanar(fb->format))
+ return 0x3 - 1;
+ else
+ return 0x2 - 1;
+}
+
static int skl_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
@@ -2137,7 +2153,7 @@ static int skl_plane_check(struct intel_crtc_state
*crtc_state,
/* use scaler when colorkey is not required */
if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
min_scale = 1;
- max_scale = skl_max_scale(crtc_state, fb->format);
+ max_scale = skl_plane_max_scale(dev_priv, fb);
}
ret = drm_atomic_helper_check_plane_state(_state->base,
--
2.21.0
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[Intel-gfx] [PATCH v2 03/13] drm/i915: Move check_digital_port_conflicts() earier
From: Ville Syrjälä
check_digital_port_conflicts() is done needlessly late. Move it earlier.
This will be needed as later on we want to set any_ms=true a bit later
for non-modesets too and we can't call this guy without the
connection_mutex held.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a8444d9841c1..44bd4d15019b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13456,11 +13456,6 @@ static int intel_modeset_checks(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
- if (!check_digital_port_conflicts(state)) {
- DRM_DEBUG_KMS("rejecting conflicting digital port
configuration\n");
- return -EINVAL;
- }
-
/* keep the current setting */
if (!state->cdclk.force_min_cdclk_changed)
state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
@@ -13622,6 +13617,12 @@ static int intel_atomic_check(struct drm_device *dev,
any_ms = true;
}
+ if (any_ms && !check_digital_port_conflicts(state)) {
+ DRM_DEBUG_KMS("rejecting conflicting digital port
configuration\n");
+ ret = EINVAL;
+ goto fail;
+ }
+
ret = drm_dp_mst_atomic_check(>base);
if (ret)
goto fail;
--
2.21.0
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Re: [Intel-gfx] [RESEND PATCH v2] drm: Add getfb2 ioctl
On Mon, Oct 14, 2019 at 1:51 PM Daniel Vetter wrote:
>
> On Mon, Oct 14, 2019 at 6:21 PM Li, Juston wrote:
> >
> > On Wed, 2019-10-09 at 17:50 +0200, Daniel Vetter wrote:
> > > On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > > > From: Daniel Stone
> > > >
> > > > getfb2 allows us to pass multiple planes and modifiers, just like
> > > > addfb2
> > > > over addfb.
> > > >
> > > > Changes since v1:
> > > > - unused modifiers set to 0 instead of DRM_FORMAT_MOD_INVALID
> > > > - update ioctl number
> > > >
> > > > Signed-off-by: Daniel Stone
> > > > Signed-off-by: Juston Li
> > >
> > > Looks all good from a very quick glance (kernel, libdrm, igt), but
> > > where's
> > > the userspace? Link to weston/drm_hwc/whatever MR good enough.
> > > -Daniel
> >
> > My use case is a screenshot utility in chromiuomos that breaks with y-
> > tiled ccs enabled.
> > Review linked is just WIP hack for now since it depends on this
> > merging:
> > https://chromium-review.googlesource.com/c/chromiumos/platform2/+/1815146
>
> Adding Sean & Daniele to confirm this is real cros.
> -Daniel
Yes, this is useful for cros and not only for the screenshot utility.
It is also useful for the transition from the splash screen to Chrome
login without flashing the screen black.
Thank you!
>
> >
> > Thanks
> > Juston
> >
> > > > ---
> > > > drivers/gpu/drm/drm_crtc_internal.h | 2 +
> > > > drivers/gpu/drm/drm_framebuffer.c | 110
> > > >
> > > > drivers/gpu/drm/drm_ioctl.c | 1 +
> > > > include/uapi/drm/drm.h | 2 +
> > > > 4 files changed, 115 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> > > > b/drivers/gpu/drm/drm_crtc_internal.h
> > > > index c7d5e4c21423..16f2413403aa 100644
> > > > --- a/drivers/gpu/drm/drm_crtc_internal.h
> > > > +++ b/drivers/gpu/drm/drm_crtc_internal.h
> > > > @@ -216,6 +216,8 @@ int drm_mode_rmfb_ioctl(struct drm_device *dev,
> > > > void *data, struct drm_file *file_priv);
> > > > int drm_mode_getfb(struct drm_device *dev,
> > > >void *data, struct drm_file *file_priv);
> > > > +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> > > > + void *data, struct drm_file *file_priv);
> > > > int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
> > > >void *data, struct drm_file *file_priv);
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_framebuffer.c
> > > > b/drivers/gpu/drm/drm_framebuffer.c
> > > > index 57564318ceea..6db54f177443 100644
> > > > --- a/drivers/gpu/drm/drm_framebuffer.c
> > > > +++ b/drivers/gpu/drm/drm_framebuffer.c
> > > > @@ -31,6 +31,7 @@
> > > > #include
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > @@ -548,7 +549,116 @@ int drm_mode_getfb(struct drm_device *dev,
> > > >
> > > > out:
> > > > drm_framebuffer_put(fb);
> > > > + return ret;
> > > > +}
> > > > +
> > > > +/**
> > > > + * drm_mode_getfb2 - get extended FB info
> > > > + * @dev: drm device for the ioctl
> > > > + * @data: data pointer for the ioctl
> > > > + * @file_priv: drm file for the ioctl call
> > > > + *
> > > > + * Lookup the FB given its ID and return info about it.
> > > > + *
> > > > + * Called by the user via ioctl.
> > > > + *
> > > > + * Returns:
> > > > + * Zero on success, negative errno on failure.
> > > > + */
> > > > +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> > > > + void *data, struct drm_file *file_priv)
> > > > +{
> > > > + struct drm_mode_fb_cmd2 *r = data;
> > > > + struct drm_framebuffer *fb;
> > > > + unsigned int i;
> > > > + int ret;
> > > > +
> > > > + if (!drm_core_check_feature(dev, DRIVER_MODESET))
> > > > + return -EINVAL;
> > > > +
> > > > + fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
> > > > + if (!fb)
> > > > + return -ENOENT;
> > > > +
> > > > + /* For multi-plane framebuffers, we require the driver to place
> > > > the
> > > > +* GEM objects directly in the drm_framebuffer. For single-
> > > > plane
> > > > +* framebuffers, we can fall back to create_handle.
> > > > +*/
> > > > + if (!fb->obj[0] &&
> > > > + (fb->format->num_planes > 1 || !fb->funcs->create_handle))
> > > > {
> > > > + ret = -ENODEV;
> > > > + goto out;
> > > > + }
> > > > +
> > > > + r->height = fb->height;
> > > > + r->width = fb->width;
> > > > + r->pixel_format = fb->format->format;
> > > > +
> > > > + r->flags = 0;
> > > > + if (dev->mode_config.allow_fb_modifiers)
> > > > + r->flags |= DRM_MODE_FB_MODIFIERS;
> > > > +
> > > > + for (i = 0; i < ARRAY_SIZE(r->handles); i++) {
> > > > + r->handles[i] = 0;
> > > > + r->pitches[i] = 0;
> > > > + r->offsets[i] = 0;
> > > > + r->modifier[i] = 0;
> > > > + }
> > > >
> > > > + for (i = 0; i < fb->format->num_planes; i++) {
> > > > +
Re: [Intel-gfx] [PATCH V3 0/7] mdev based hardware virtio offloading support
On Tue, Oct 15, 2019 at 11:37:17AM +0800, Jason Wang wrote: > > On 2019/10/15 上午1:49, Stefan Hajnoczi wrote: > > On Fri, Oct 11, 2019 at 04:15:50PM +0800, Jason Wang wrote: > > > There are hardware that can do virtio datapath offloading while having > > > its own control path. This path tries to implement a mdev based > > > unified API to support using kernel virtio driver to drive those > > > devices. This is done by introducing a new mdev transport for virtio > > > (virtio_mdev) and register itself as a new kind of mdev driver. Then > > > it provides a unified way for kernel virtio driver to talk with mdev > > > device implementation. > > > > > > Though the series only contains kernel driver support, the goal is to > > > make the transport generic enough to support userspace drivers. This > > > means vhost-mdev[1] could be built on top as well by resuing the > > > transport. > > > > > > A sample driver is also implemented which simulate a virito-net > > > loopback ethernet device on top of vringh + workqueue. This could be > > > used as a reference implementation for real hardware driver. > > > > > > Consider mdev framework only support VFIO device and driver right now, > > > this series also extend it to support other types. This is done > > > through introducing class id to the device and pairing it with > > > id_talbe claimed by the driver. On top, this seris also decouple > > > device specific parents ops out of the common ones. > > I was curious so I took a quick look and posted comments. > > > > I guess this driver runs inside the guest since it registers virtio > > devices? > > > It could run in either guest or host. But the main focus is to run in the > host then we can use virtio drivers in containers. > > > > > > If this is used with physical PCI devices that support datapath > > offloading then how are physical devices presented to the guest without > > SR-IOV? > > > We will do control path meditation through vhost-mdev[1] and vhost-vfio[2]. > Then we will present a full virtio compatible ethernet device for guest. > > SR-IOV is not a must, any mdev device that implements the API defined in > patch 5 can be used by this framework. What I'm trying to understand is: if you want to present a virtio-pci device to the guest (e.g. using vhost-mdev or vhost-vfio), then how is that related to this patch series? Does this mean this patch series is useful mostly for presenting virtio devices to containers or the host? Stefan signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 4/7] drm/i915/dsi: Helper to find dsi encoder in cmd mode
On Mon, 14 Oct 2019, Vandita Kulkarni wrote:
> From: Madhav Chauhan
>
> This patch adds a helper function to find encoder
> if DSI is operating in command mode. This function
> will be used while enabling/disabling TE interrupts
> for DSI.
>
> Signed-off-by: Madhav Chauhan
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 17 +
> drivers/gpu/drm/i915/display/intel_dsi.h | 3 +++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 5dd9eebab6b1..877746416e52 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -73,6 +73,23 @@ static enum transcoder dsi_port_to_transcoder(enum port
> port)
> return TRANSCODER_DSI_1;
> }
>
> +struct intel_encoder *gen11_dsi_find_cmd_mode_encoder(struct intel_crtc
> *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct intel_encoder *encoder;
> + struct intel_dsi *intel_dsi;
> +
> + for_each_encoder_on_crtc(dev, >base, encoder) {
> + if (encoder->type != INTEL_OUTPUT_DSI)
> + continue;
> + intel_dsi = enc_to_intel_dsi(>base);
> + if (intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE)
> + return encoder;
> + }
> +
> + return NULL;
> +}
This may be a bit harsh, but everything that feels wrong about the
following patches pretty much boils down to this function. It may get
the job done, and I don't have a better suggestion on how to accomplish
this right now. But it seems like we shouldn't have to do anything like
this, and makes you feel like there's something wrong with the design.
It would be great to be able to handle this using crtc state, but alas
the vblank enable hook only gets passed a struct drm_crtc *. (Patch 7
could easily switch to using crtc state, but need to also solve patch
5.)
I'll get back to you on this later, but in the mean time - Ville, do you
have any ideas?
BR,
Jani.
> +
> static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h
> b/drivers/gpu/drm/i915/display/intel_dsi.h
> index b15be5814599..071dad7ee04a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.h
> @@ -201,6 +201,9 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
>struct intel_crtc_state *config);
> void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
>
> +/* icl_dsi.c */
> +struct intel_encoder *gen11_dsi_find_cmd_mode_encoder(struct intel_crtc
> *crtc);
> +
> /* intel_dsi_vbt.c */
> bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
> void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/ehl: Don't forget to set TC long detect function
On Tue, Oct 15, 2019 at 06:54:02PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Don't forget to set TC long detect function
> URL : https://patchwork.freedesktop.org/series/68038/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14816
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14816 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14816, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14816:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_module_load@reload-with-fault-injection:
> - fi-skl-6260u: [PASS][1] -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-skl-6260u/igt@i915_module_l...@reload-with-fault-injection.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-skl-6260u/igt@i915_module_l...@reload-with-fault-injection.html
>
> * igt@i915_selftest@live_gem_contexts:
> - fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
>
Neither of these are related to the MCC PCH changes in this patch; will
request a re-test.
Matt
>
> Known issues
>
>
> Here are the changes found in Patchwork_14816 that come from known issues:
>
> ### IGT changes ###
>
> Possible fixes
>
> * igt@gem_ctx_create@basic-files:
> - fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
> - fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
> [PASS][8]
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
>
> * igt@i915_selftest@live_execlists:
> - fi-apl-guc: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-apl-guc/igt@i915_selftest@live_execlists.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-apl-guc/igt@i915_selftest@live_execlists.html
>
> * igt@i915_selftest@live_hangcheck:
> - {fi-icl-guc}: [DMESG-FAIL][11] ([fdo#111678]) -> [PASS][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
> - {fi-icl-u4}:[INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) ->
> [PASS][14]
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>
> * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-icl-u2: [DMESG-WARN][15] ([fdo#102505] / [fdo#110390]) ->
> [PASS][16]
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
> [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
> [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
> [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
> [fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
> [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
>
>
> Participating hosts (53 -> 46)
>
[Intel-gfx] [PATCH] drm/i915: Fix MST oops due to MSA changes
From: Ville Syrjälä
The MSA MISC computation now depends on the connector state, and
we do it from the DDI .pre_enable() hook. All that is fine for
DP SST but with MST we don't actually pass the connector state
to the dig port's .pre_enable() hook which leads to an oops.
Need to think more how to solve this in a cleaner fashion, but
for now let's just add a NULL check to stop the oopsing.
Cc: Gwan-gyeong Mun
Cc: Uma Shankar
Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP
MSA")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 80f8e2698be0..4c81449ec144 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state
*crtc_state,
* of Color Encoding Format and Content Color Gamut] while sending
* YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
* which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+*
+* FIXME MST doesn't pass in the conn_state
*/
- if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+ if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
temp |= DP_MSA_MISC_COLOR_VSC_SDP;
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
--
2.21.0
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Jasper Lake PCH (rev3)
== Series Details == Series: drm/i915: Introduce Jasper Lake PCH (rev3) URL : https://patchwork.freedesktop.org/series/67992/ State : warning == Summary == $ dim checkpatch origin/drm-tip 47be6f8097ac drm/i915: Introduce Jasper Lake PCH -:30: WARNING:BAD_SIGN_OFF: Duplicate signature #30: Reviewed-by: Vivek Kasireddy total: 0 errors, 1 warnings, 0 checks, 89 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/ehl: Don't forget to set TC long detect function
== Series Details ==
Series: drm/i915/ehl: Don't forget to set TC long detect function
URL : https://patchwork.freedesktop.org/series/68038/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14816
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14816 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14816, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14816:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload-with-fault-injection:
- fi-skl-6260u: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-skl-6260u/igt@i915_module_l...@reload-with-fault-injection.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-skl-6260u/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14816 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
- fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-apl-guc/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-apl-guc/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [DMESG-FAIL][11] ([fdo#111678]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
- {fi-icl-u4}:[INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][15] ([fdo#102505] / [fdo#110390]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14816/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7098 -> Patchwork_14816
CI-20190529: 20190529
CI_DRM_7098: 4e4fe1f2e2ff11f066e3ea4706dec0dded6925e5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @
Re: [Intel-gfx] [RFC 3/7] drm/i915/dsi: Add vblank calculation for command mode
On Mon, 14 Oct 2019, Vandita Kulkarni wrote:
> Transcoder timing calculation differ for command mode.
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 56 +-
> 1 file changed, 37 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 8e6c09a1db78..5dd9eebab6b1 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -780,6 +780,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
> *encoder,
> u16 hback_porch;
> /* vertical timings */
> u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
> + int bpp, line_time_us, byte_clk_period_ns;
>
> hactive = adjusted_mode->crtc_hdisplay;
> htotal = adjusted_mode->crtc_htotal;
> @@ -841,40 +842,57 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
> *encoder,
> }
>
> /* program TRANS_VTOTAL register */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - dsi_trans = dsi_port_to_transcoder(port);
> - /*
> - * FIXME: Programing this by assuming progressive mode, since
> - * non-interlaced info from VBT is not saved inside
> - * struct drm_display_mode.
> - * For interlace mode: program required pixel minus 2
> - */
> - I915_WRITE(VTOTAL(dsi_trans),
> -(vactive - 1) | ((vtotal - 1) << 16));
> + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
There's is_vid_mode() and is_cmd_mode(). Use them throughout the series
instead of the above.
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + /*
> + * FIXME: Programing this by assuming progressive mode,
> + * since non-interlaced info from VBT is not saved
> + * inside struct drm_display_mode.
> + * For interlace mode: program required pixel minus 2
> + */
> + I915_WRITE(VTOTAL(dsi_trans),
> +(vactive - 1) | ((vtotal - 1) << 16));
> + }
> + } else {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + bpp =
> mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> + byte_clk_period_ns = 8 * 100 / intel_dsi->pclk;
> + htotal = hactive + 160;
> + line_time_us = (htotal * (bpp / 8) *
> byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
> + vtotal = vactive + DIV_ROUND_UP(460, line_time_us);
This is a bit hand-wavy, but some of these seem suspicious. Someone(tm)
needs to go through these in detail.
> + I915_WRITE(VTOTAL(dsi_trans),
> +(vactive - 1) | ((vtotal - 1) << 16));
> + }
> }
As the I915_WRITE() is the same for both, albeit with changed values for
cmd mode, I think it would be better to have the mode check within the
for_each_dsi_port() block.
>
> +
> if (vsync_end < vsync_start || vsync_end > vtotal)
> DRM_ERROR("Invalid vsync_end value\n");
>
> if (vsync_start < vactive)
> DRM_ERROR("vsync_start less than vactive\n");
>
> - /* program TRANS_VSYNC register */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - dsi_trans = dsi_port_to_transcoder(port);
> - I915_WRITE(VSYNC(dsi_trans),
> -(vsync_start - 1) | ((vsync_end - 1) << 16));
> + /* program TRANS_VSYNC register for video mode only */
> + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + I915_WRITE(VSYNC(dsi_trans),
> +(vsync_start - 1) | ((vsync_end - 1) << 16));
> + }
> }
>
> /*
> - * FIXME: It has to be programmed only for interlaced
> + * FIXME: It has to be programmed only for video modes and interlaced
>* modes. Put the check condition here once interlaced
>* info available as described above.
>* program TRANS_VSYNCSHIFT register
>*/
> - for_each_dsi_port(port, intel_dsi->ports) {
> - dsi_trans = dsi_port_to_transcoder(port);
> - I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
> + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
> + }
> }
>
> /* program TRANS_VBLANK register, should be
Re: [Intel-gfx] [RFC 2/7] drm/i915/dsi: Configure transcoder operation for command mode.
On Mon, 14 Oct 2019, Vandita Kulkarni wrote:
> Configure the transcoder to operate in TE GATE command mode
> and take TE events from GPIO.
> Also disable the periodic command mode, that GOP would have
> programmed.
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 32 ++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6e398c33a524..8e6c09a1db78 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder
> *encoder,
> tmp |= VIDEO_MODE_SYNC_PULSE;
> break;
> }
> + } else {
> + tmp &= ~OP_MODE_MASK;
> + tmp |= CMD_MODE_TE_GATE;
> + tmp |= TE_SOURCE_GPIO;
> }
>
> I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> @@ -953,6 +957,22 @@ static void gen11_dsi_setup_timeouts(struct
> intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_config_util_pin(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + u32 tmp;
> +
> + /* used only as TE i/p for DSI0 for dual link TE is from slave DSI1 */
> + if (is_vid_mode(intel_dsi) || (intel_dsi->dual_link))
> + return;
Full disclosure: I didn't check the spec on this.
But... where does the TE come for the slave DSI1 then? The comment seems
confusing.
Nitpick, intel_dsi->dual_link does not need parenthesis.
> +
> + tmp = I915_READ(UTIL_PIN_CTL);
> + tmp |= ICL_UTIL_PIN_DIRECTION;
If the macro had INPUT in the name, this would be self-explanatory.
> + tmp |= UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, tmp);
> +}
> +
> static void
> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> @@ -974,6 +994,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
> *encoder,
> /* setup D-PHY timings */
> gen11_dsi_setup_dphy_timings(encoder);
>
> + /* Since transcoder is configured to take events from GPIO */
> + gen11_dsi_config_util_pin(encoder);
> +
> /* step 4h: setup DSI protocol timeouts */
> gen11_dsi_setup_timeouts(encoder);
>
> @@ -1104,6 +1127,15 @@ static void gen11_dsi_deconfigure_trancoder(struct
> intel_encoder *encoder)
> enum transcoder dsi_trans;
> u32 tmp;
>
> + /* disable periodic update mode */
> + if (is_cmd_mode(intel_dsi)) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_DSI_CMD_FRMCTL(port));
> + tmp &= ~ICL_PERIODIC_FRAME_UPDATE_ENABLE;
> + I915_WRITE(ICL_DSI_CMD_FRMCTL(port), tmp);
> + }
> + }
> +
> /* put dsi link in ULPS */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Drop stale struct_mutex
== Series Details ==
Series: drm/i915/selftests: Drop stale struct_mutex
URL : https://patchwork.freedesktop.org/series/68011/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7093_full -> Patchwork_14806_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14806_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14806_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14806_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@in-flight-contexts-10ms:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-snb7/igt@gem_...@in-flight-contexts-10ms.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-snb1/igt@gem_...@in-flight-contexts-10ms.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@extended-pageflip-hang-oldfb-render-f:
- {shard-tglb}: NOTRUN -> [SKIP][3] +11 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-tglb1/igt@kms_b...@extended-pageflip-hang-oldfb-render-f.html
Known issues
Here are the changes found in Patchwork_14806_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-nonpriv:
- shard-apl: [PASS][4] -> [INCOMPLETE][5] ([fdo#103927])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-apl3/igt@gem_ctx_isolat...@rcs0-nonpriv.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-apl2/igt@gem_ctx_isolat...@rcs0-nonpriv.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#110841])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +8 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_wait@write-wait-bcs0:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([fdo#106107])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-skl10/igt@gem_w...@write-wait-bcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-skl2/igt@gem_w...@write-wait-bcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [PASS][12] -> [INCOMPLETE][13] ([fdo#104108])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-skl3/igt@gem_workarou...@suspend-resume-context.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-skl7/igt@gem_workarou...@suspend-resume-context.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][14] -> [DMESG-WARN][15] ([fdo#108566]) +5
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: [PASS][16] -> [FAIL][17] ([fdo#103355])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-hsw1/igt@kms_cursor_leg...@cursor-vs-flip-atomic.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-hsw1/igt@kms_cursor_leg...@cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][18] -> [FAIL][19] ([fdo#102887])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-glk3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14806/shard-glk8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +4 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7093/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html
[21]:
Re: [Intel-gfx] [PATCH] kernel-doc: rename the kernel-doc directive 'functions' to 'specific'
On Sun, 13 Oct 2019 13:53:59 +0800 Changbin Du wrote: > The 'functions' directive is not only for functions, but also works for > structs/unions. So the name is misleading. This patch renames it to > 'specific', so now we have export/internal/specific directives to limit > the functions/types to be included in documentation. Meanwhile we improved > the warning message. I agree with the others that "specific" doesn't really make things better. "Interfaces" maybe; otherwise we could go for something like "filter" or "select". Paint mine green :) Whatever we end up with, I think it should be added as a synonym for "functions". Then the various selectors that are actually pulling out docs for functions could be changed at leisure - or not at all. I'd rather not see a big patch changing everything at once. Thanks, jon ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 v2 4/5] drm/i915: add pipe id/name to pipe mismatch logs
On Tue, Oct 15, 2019 at 09:40:28AM -0700, Lucas De Marchi wrote:
> This way it's easier to figure out what didn't match when we have
> multiple pipes enabled.
>
> v2: pass drm_crtc and use the more common [CRTC:%d:%s] format
> (Ville)
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 34 +++-
> 1 file changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e71ec9d96c75..cd0f600e0205 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12526,8 +12526,9 @@ pipe_config_infoframe_mismatch(struct
> drm_i915_private *dev_priv,
> }
> }
>
> -static void __printf(3, 4)
> -pipe_config_mismatch(bool fastset, const char *name, const char *format, ...)
> +static void __printf(4, 5)
> +pipe_config_mismatch(bool fastset, const struct drm_crtc *crtc,
> + const char *name, const char *format, ...)
> {
> struct va_format vaf;
> va_list args;
> @@ -12537,9 +12538,11 @@ pipe_config_mismatch(bool fastset, const char *name,
> const char *format, ...)
> vaf.va =
>
> if (fastset)
> - DRM_DEBUG_KMS("fastset mismatch in %s %pV\n", name, );
> + DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
> + crtc->base.id, crtc->name, name, );
> else
> - DRM_ERROR("mismatch in %s %pV\n", name, );
> + DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
> + crtc->base.id, crtc->name, name, );
>
> va_end(args);
> }
> @@ -12567,6 +12570,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> bool fastset)
> {
> struct drm_i915_private *dev_priv =
> to_i915(current_config->base.crtc->dev);
> + const struct drm_crtc *crtc = pipe_config->base.crtc;
The only thing we really const these days is the states. So I'd drop the
const here.
Also pls make it struct intel_crtc since we're trying to get rid of
this mess with both drm_ and intel_ types getting mixed around randomly.
with that
Reviewed-by: Ville Syrjälä
> bool ret = true;
> u32 bp_gamma = 0;
> bool fixup_inherited = fastset &&
> @@ -12580,7 +12584,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> #define PIPE_CONF_CHECK_X(name) do { \
> if (current_config->name != pipe_config->name) { \
> - pipe_config_mismatch(fastset, __stringify(name), \
> + pipe_config_mismatch(fastset, crtc, __stringify(name), \
>"(expected 0x%08x, found 0x%08x)", \
>current_config->name, \
>pipe_config->name); \
> @@ -12590,7 +12594,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> #define PIPE_CONF_CHECK_I(name) do { \
> if (current_config->name != pipe_config->name) { \
> - pipe_config_mismatch(fastset, __stringify(name), \
> + pipe_config_mismatch(fastset, crtc, __stringify(name), \
>"(expected %i, found %i)", \
>current_config->name, \
>pipe_config->name); \
> @@ -12600,7 +12604,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> #define PIPE_CONF_CHECK_BOOL(name) do { \
> if (current_config->name != pipe_config->name) { \
> - pipe_config_mismatch(fastset, __stringify(name), \
> + pipe_config_mismatch(fastset, crtc, __stringify(name), \
>"(expected %s, found %s)", \
>yesno(current_config->name), \
>yesno(pipe_config->name)); \
> @@ -12617,7 +12621,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> if (!fixup_inherited || (!current_config->name && !pipe_config->name))
> { \
> PIPE_CONF_CHECK_BOOL(name); \
> } else { \
> - pipe_config_mismatch(fastset, __stringify(name), \
> + pipe_config_mismatch(fastset, crtc, __stringify(name), \
>"unable to verify whether state matches
> exactly, forcing modeset (expected %s, found %s)", \
>yesno(current_config->name), \
>yesno(pipe_config->name)); \
> @@ -12627,7 +12631,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> #define PIPE_CONF_CHECK_P(name) do { \
> if (current_config->name != pipe_config->name) { \
> - pipe_config_mismatch(fastset, __stringify(name), \
> + pipe_config_mismatch(fastset, crtc, __stringify(name), \
>
Re: [Intel-gfx] [PATCH v3 v2 2/5] drm/i915: fix port checks for MST support on gen >= 11
On Tue, Oct 15, 2019 at 09:40:26AM -0700, Lucas De Marchi wrote:
> Both Ice Lake and Elkhart Lake (gen 11) support MST on all external
> connections except DDI A. Tiger Lake (gen 12) supports on all external
> connections.
>
> Move the check to happen inside intel_dp_mst_encoder_init() and add
> specific platform checks.
>
> v2: Replace != with == checks for ports on gen < 11 (Ville)
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++--
> 2 files changed, 18 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6594f2af1257..415d0f2c2751 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7271,11 +7271,8 @@ intel_dp_init_connector(struct intel_digital_port
> *intel_dig_port,
> intel_connector->get_hw_state = intel_connector_get_hw_state;
>
> /* init MST on ports that can support it */
> - if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
> - (port == PORT_B || port == PORT_C ||
> - port == PORT_D || port == PORT_F))
> - intel_dp_mst_encoder_init(intel_dig_port,
> - intel_connector->base.base.id);
> + intel_dp_mst_encoder_init(intel_dig_port,
> + intel_connector->base.base.id);
>
> if (!intel_edp_init_connector(intel_dp, intel_connector)) {
> intel_dp_aux_fini(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2203be28ea01..ea062fea8a44 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -655,21 +655,31 @@ intel_dp_mst_encoder_active_links(struct
> intel_digital_port *intel_dig_port)
> int
> intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int
> conn_base_id)
> {
> + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
> struct intel_dp *intel_dp = _dig_port->dp;
> - struct drm_device *dev = intel_dig_port->base.base.dev;
> + enum port port = intel_dig_port->base.port;
> int ret;
>
> - intel_dp->can_mst = true;
> + if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
> + return 0;
> +
> + if (INTEL_GEN(i915) <= 11 && port == PORT_A)
> + return 0;
gen<12
with that
Reviewed-by: Ville Syrjälä
> +
> + if (INTEL_GEN(i915) < 11 && port == PORT_E)
> + return 0;
> +
> intel_dp->mst_mgr.cbs = _cbs;
>
> /* create encoders */
> intel_dp_create_fake_mst_encoders(intel_dig_port);
> - ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, dev,
> + ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, >drm,
> _dp->aux, 16, 3, conn_base_id);
> - if (ret) {
> - intel_dp->can_mst = false;
> + if (ret)
> return ret;
> - }
> +
> + intel_dp->can_mst = true;
> +
> return 0;
> }
>
> --
> 2.23.0
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/11] drm/i915/tgl: Add IS_TGL_REVID
== Series Details == Series: series starting with [01/11] drm/i915/tgl: Add IS_TGL_REVID URL : https://patchwork.freedesktop.org/series/68037/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o drivers/gpu/drm/i915/gt/intel_workarounds.c: In function ‘tgl_gt_workarounds_init’: drivers/gpu/drm/i915/gt/intel_workarounds.c:910:8: error: ‘L3_CLKGATE_DIS’ undeclared (first use in this function); did you mean ‘CGPSF_CLKGATE_DIS’? L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); ^~ CGPSF_CLKGATE_DIS drivers/gpu/drm/i915/gt/intel_workarounds.c:910:8: note: each undeclared identifier is reported only once for each function it appears in drivers/gpu/drm/i915/gt/intel_workarounds.c:910:25: error: ‘L3_CR2X_CLKGATE_DIS’ undeclared (first use in this function); did you mean ‘L3_CLKGATE_DIS’? L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); ^~~ L3_CLKGATE_DIS scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/gt/intel_workarounds.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_workarounds.o] Error 1 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1650: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Wa_1607087056
== Series Details ==
Series: drm/i915/icl: Wa_1607087056
URL : https://patchwork.freedesktop.org/series/68036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14814
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14814:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gem_contexts:
- {fi-icl-guc}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14814 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#106766])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
- fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-apl-guc/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/fi-apl-guc/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [DMESG-FAIL][11] ([fdo#111678]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
- {fi-icl-u4}:[INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106766]: https://bugs.freedesktop.org/show_bug.cgi?id=106766
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7098 -> Patchwork_14814
CI-20190529: 20190529
CI_DRM_7098: 4e4fe1f2e2ff11f066e3ea4706dec0dded6925e5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14814: efddc844861e8f68f47c61f702cd200c8b1d2913 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
efddc844861e drm/i915/icl: Wa_1607087056
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14814/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move the cursor rotation handling into intel_cursor_check_surface()
== Series Details ==
Series: drm/i915: Move the cursor rotation handling into
intel_cursor_check_surface()
URL : https://patchwork.freedesktop.org/series/68035/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7098 -> Patchwork_14813
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14813:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gem_contexts:
- {fi-icl-dsi}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14813 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#106070] /
[fdo#111700])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-skl-iommu: [PASS][5] -> [INCOMPLETE][6] ([fdo#111700])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-skl-iommu/igt@i915_selftest@live_gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-skl-iommu/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
- fi-icl-u3: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-apl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-apl-guc/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [DMESG-FAIL][13] ([fdo#111678]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
- {fi-icl-u4}:[INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [FAIL][18] ([fdo#111045]
/ [fdo#111096])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7098/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14813/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
[fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700
Participating hosts (53 -> 45)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y
Re: [Intel-gfx] [PATCH v3] drm/i915: Introduce Jasper Lake PCH
On Tue, 15 Oct 2019 09:28:54 -0700
Matt Roper wrote:
> The Jasper Lake PCH follows ICP/TGP's south display behavior and is
> identical to MCC graphics-wise except that it does not use the unusual
> (port C -> TC1) pin mapping that MCC does.
>
> Also, it turns out the extra PCH ID that we had previously thought
> was a form of MCC is actually a second ID for JSP (i.e., port C uses
> the port C pins instead of the TC1 pins).
>
> v2:
> - Also update the port masks (not just the pin table) in
>mcc_hpd_irq_setup. (Vivek)
>
> v3:
> - Break jsp_hpd_irq_setup out into its own function for clarity.
>(Vivek)
>
> Cc: José Roberto de Souza
> Cc: James Ausmus
> Cc: Vivek Kasireddy
> Signed-off-by: Matt Roper
> Reviewed-by: Vivek Kasireddy
> ---
> drivers/gpu/drm/i915/i915_irq.c | 24 +++-
> drivers/gpu/drm/i915/intel_pch.c | 6 +-
> drivers/gpu/drm/i915/intel_pch.h | 5 -
> 3 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index d20ca02d3166..448390ad2128
> 100644 --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2248,11 +2248,18 @@ static void icp_irq_handler(struct
> drm_i915_private *dev_priv, u32 pch_iir) tc_hotplug_trigger = pch_iir
> & SDE_TC_MASK_TGP; tc_port_hotplug_long_detect =
> tgp_tc_port_hotplug_long_detect; pins = hpd_tgp;
> + } else if (HAS_PCH_JSP(dev_priv)) {
> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> + tc_hotplug_trigger = 0;
> + pins = hpd_tgp;
> } else if (HAS_PCH_MCC(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> tc_hotplug_trigger = pch_iir &
> SDE_TC_HOTPLUG_ICP(PORT_TC1); pins = hpd_icp;
> } else {
> + WARN(!HAS_PCH_ICP(dev_priv),
> + "Unrecognized PCH type 0x%x\n",
> INTEL_PCH_TYPE(dev_priv)); +
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> tc_port_hotplug_long_detect =
> icp_tc_port_hotplug_long_detect; @@ -3384,6 +3391,19 @@ static void
> mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) hpd_icp);
> }
>
> +/*
> + * JSP behaves exactly the same as MCC above except that port C is
> mapped to
> + * the DDI-C pins instead of the TC1 pins. This means we should
> follow TGP's
> + * masks & tables rather than ICP's masks & tables.
> + */
> +static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +{
> + icp_hpd_irq_setup(dev_priv,
> + SDE_DDI_MASK_TGP, 0,
> + TGP_DDI_HPD_ENABLE_MASK, 0,
> + hpd_tgp);
> +}
> +
Looks good.
Reviewed-by: Vivek Kasireddy
> static void gen11_hpd_detection_setup(struct drm_i915_private
> *dev_priv) {
> u32 hotplug;
> @@ -4315,7 +4335,9 @@ void intel_irq_init(struct drm_i915_private
> *dev_priv) if (I915_HAS_HOTPLUG(dev_priv))
> dev_priv->display.hpd_irq_setup =
> i915_hpd_irq_setup; } else {
> - if (HAS_PCH_MCC(dev_priv))
> + if (HAS_PCH_JSP(dev_priv))
> + dev_priv->display.hpd_irq_setup =
> jsp_hpd_irq_setup;
> + else if (HAS_PCH_MCC(dev_priv))
> dev_priv->display.hpd_irq_setup =
> mcc_hpd_irq_setup; else if (INTEL_GEN(dev_priv) >= 11)
> dev_priv->display.hpd_irq_setup =
> gen11_hpd_irq_setup; diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c index 15f8bff141f9..1035d3d46fd8
> 100644 --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -79,7 +79,6 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id) WARN_ON(!IS_ICELAKE(dev_priv));
> return PCH_ICP;
> case INTEL_PCH_MCC_DEVICE_ID_TYPE:
> - case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
> DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
> WARN_ON(!IS_ELKHARTLAKE(dev_priv));
> return PCH_MCC;
> @@ -87,6 +86,11 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id) DRM_DEBUG_KMS("Found Tiger Lake LP
> PCH\n"); WARN_ON(!IS_TIGERLAKE(dev_priv));
> return PCH_TGP;
> + case INTEL_PCH_JSP_DEVICE_ID_TYPE:
> + case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
> + DRM_DEBUG_KMS("Found Jasper Lake PCH\n");
> + WARN_ON(!IS_ELKHARTLAKE(dev_priv));
> + return PCH_JSP;
> default:
> return PCH_NONE;
> }
> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> b/drivers/gpu/drm/i915/intel_pch.h index c29c81ec7971..f4dc18c34291
> 100644 --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -23,6 +23,7 @@ enum intel_pch {
> PCH_SPT,/* Sunrisepoint/Kaby Lake PCH */
> PCH_CNP,/* Cannon/Comet Lake PCH */
> PCH_ICP,/* Ice
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Don't forget to set TC long detect function
On Tue, 15 Oct 2019 09:11:31 -0700
Matt Roper wrote:
> Since EHL's MCC PCH reuses one of the TC pins we need to supply a TC
> long detect function when handling the interrupts.
>
> Fixes: 53448aed7b80 ("drm/i915/ehl: Port C's hotplug interrupt is
> associated with TC1 bits") Reported-by: kbuild test robot
> Reported-by: Dan Carpenter
> Cc: Vivek Kasireddy
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index a7c968b01af3..af7426cd8de9
> 100644 --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2251,6 +2251,7 @@ static void icp_irq_handler(struct
> drm_i915_private *dev_priv, u32 pch_iir) } else if
> (HAS_PCH_MCC(dev_priv)) { ddi_hotplug_trigger = pch_iir &
> SDE_DDI_MASK_ICP; tc_hotplug_trigger = pch_iir &
> SDE_TC_HOTPLUG_ICP(PORT_TC1);
> + tc_port_hotplug_long_detect =
> icp_tc_port_hotplug_long_detect; pins = hpd_icp;
Reviewed-by: Vivek Kasireddy
> } else {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
___
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Re: [Intel-gfx] [PATCH V3 4/7] mdev: introduce device specific ops
On Tue, 15 Oct 2019 20:17:01 +0800 Jason Wang wrote: > On 2019/10/15 下午6:41, Cornelia Huck wrote: > > On Fri, 11 Oct 2019 16:15:54 +0800 > > Jason Wang wrote: > > > >> Currently, except for the create and remove, the rest of > >> mdev_parent_ops is designed for vfio-mdev driver only and may not help > >> for kernel mdev driver. With the help of class id, this patch > >> introduces device specific callbacks inside mdev_device > >> structure. This allows different set of callback to be used by > >> vfio-mdev and virtio-mdev. > >> > >> Signed-off-by: Jason Wang > >> --- > >> .../driver-api/vfio-mediated-device.rst | 22 +--- > >> MAINTAINERS | 1 + > >> drivers/gpu/drm/i915/gvt/kvmgt.c | 18 --- > >> drivers/s390/cio/vfio_ccw_ops.c | 18 --- > >> drivers/s390/crypto/vfio_ap_ops.c | 14 +++-- > >> drivers/vfio/mdev/mdev_core.c | 9 +++- > >> drivers/vfio/mdev/mdev_private.h | 1 + > >> drivers/vfio/mdev/vfio_mdev.c | 37 ++--- > >> include/linux/mdev.h | 42 +++ > >> include/linux/vfio_mdev.h | 52 +++ > >> samples/vfio-mdev/mbochs.c| 20 --- > >> samples/vfio-mdev/mdpy.c | 21 +--- > >> samples/vfio-mdev/mtty.c | 18 --- > >> 13 files changed, 177 insertions(+), 96 deletions(-) > >> create mode 100644 include/linux/vfio_mdev.h > >> > >> diff --git a/Documentation/driver-api/vfio-mediated-device.rst > >> b/Documentation/driver-api/vfio-mediated-device.rst > >> index 2035e48da7b2..553574ebba73 100644 > >> --- a/Documentation/driver-api/vfio-mediated-device.rst > >> +++ b/Documentation/driver-api/vfio-mediated-device.rst > >> @@ -152,11 +152,20 @@ callbacks per mdev parent device, per mdev type, or > >> any other categorization. > >> Vendor drivers are expected to be fully asynchronous in this respect or > >> provide their own internal resource protection.) > >> > >> -The callbacks in the mdev_parent_ops structure are as follows: > >> +In order to support multiple types of device/driver, device needs to > >> +provide both class_id and device_ops through: > > "As multiple types of mediated devices may be supported, the device > > needs to set up the class id and the device specific callbacks via:" > > > > ? > > > >> > >> -* open: open callback of mediated device > >> -* close: close callback of mediated device > >> -* ioctl: ioctl callback of mediated device > >> +void mdev_set_class(struct mdev_device *mdev, u16 id, const void > >> *ops); > >> + > >> +The class_id is used to be paired with ids in id_table in mdev_driver > >> +structure for probing the correct driver. > > "The class id (specified in id) is used to match a device with an mdev > > driver via its id table." > > > > ? > > > >> The device_ops is device > >> +specific callbacks which can be get through mdev_get_dev_ops() > >> +function by mdev bus driver. > > "The device specific callbacks (specified in *ops) are obtainable via > > mdev_get_dev_ops() (for use by the mdev bus driver.)" > > > > ? > > > >> For vfio-mdev device, its device specific > >> +ops are as follows: > > "A vfio-mdev device (class id MDEV_ID_VFIO) uses the following > > device-specific ops:" > > > > ? > > > All you propose is better than what I wrote, will change the docs. > > > > > >> + > >> +* open: open callback of vfio mediated device > >> +* close: close callback of vfio mediated device > >> +* ioctl: ioctl callback of vfio mediated device > >> * read : read emulation callback > >> * write: write emulation callback > >> * mmap: mmap emulation callback > >> @@ -167,9 +176,10 @@ register itself with the mdev core driver:: > >>extern int mdev_register_device(struct device *dev, > >> const struct mdev_parent_ops *ops); > >> > >> -It is also required to specify the class_id through:: > >> +It is also required to specify the class_id and device specific ops > >> through:: > >> > >> - extern int mdev_set_class(struct device *dev, u16 id); > >> + extern int mdev_set_class(struct device *dev, u16 id, > >> +const void *ops); > > Apologies if that has already been discussed, but do we want a 1:1 > > relationship between id and ops, or can different devices with the same > > id register different ops? > > > I think we have a N:1 mapping between id and ops, e.g we want both > virtio-mdev and vhost-mdev use a single set of device ops. The contents of the ops structure is essentially defined by the id, which is why I was leaning towards them being defined together. They are effectively interlocked, the id defines which mdev "endpoint" driver is loaded and that driver requires mdev_get_dev_ops() to return the structure required by the driver. I wish
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/5] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core
== Series Details ==
Series: series starting with [v3,1/5] drm/i915: Allow i915 to manage the vma
offset nodes instead of drm core
URL : https://patchwork.freedesktop.org/series/68010/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7092_full -> Patchwork_14805_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14805_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_atomic_transition@5x-modeset-transitions-nonblocking-fencing:
- {shard-tglb}: NOTRUN -> [SKIP][1] +6 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-tglb7/igt@kms_atomic_transit...@5x-modeset-transitions-nonblocking-fencing.html
Known issues
Here are the changes found in Patchwork_14805_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-iclb: [PASS][2] -> [DMESG-WARN][3] ([fdo#111764])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-iclb1/igt@gem_...@in-flight-suspend.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-iclb3/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#110854])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-iclb4/igt@gem_exec_balan...@smoke.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-iclb3/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#111325]) +2 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-iclb5/igt@gem_exec_sched...@wide-bsd.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html
* igt@gem_linear_blits@interruptible:
- shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([fdo#107713] /
[fdo#109100])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-iclb2/igt@gem_linear_bl...@interruptible.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-iclb7/igt@gem_linear_bl...@interruptible.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][10] -> [DMESG-FAIL][11] ([fdo#108686])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-glk3/igt@gem_tiled_swapp...@non-threaded.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-glk9/igt@gem_tiled_swapp...@non-threaded.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][12] -> [DMESG-WARN][13] ([fdo#111870]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [PASS][14] -> [DMESG-WARN][15] ([fdo#105763] /
[fdo#106538])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-glk5/igt@i915_pm_...@modeset-stress-extra-wait.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-glk8/igt@i915_pm_...@modeset-stress-extra-wait.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][16] -> [DMESG-WARN][17] ([fdo#108566]) +3
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-apl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-apl8/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-random:
- shard-apl: [PASS][18] -> [INCOMPLETE][19] ([fdo#103927]) +4
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-64x64-random.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-apl7/igt@kms_cursor_...@pipe-c-cursor-64x64-random.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +3 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7092/shard-iclb3/igt@kms_frontbuffer_track...@fbc-badstride.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14805/shard-iclb6/igt@kms_frontbuffer_track...@fbc-badstride.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][22] -> [FAIL][23] ([fdo#108145] / [fdo#110403])
[22]:
[Intel-gfx] [PATCH v3 v2 5/5] drm/i915: prettify MST debug message
s/?/:/ so it gets correctly colored by dmesg.
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-7-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 415d0f2c2751..abcaffd75182 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4450,7 +4450,7 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
_to_dig_port(intel_dp)->base;
bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
- DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support? port: %s, sink: %s,
modparam: %s\n",
+ DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s,
modparam: %s\n",
encoder->base.base.id, encoder->base.name,
yesno(intel_dp->can_mst), yesno(sink_can_mst),
yesno(i915_modparams.enable_dp_mst));
--
2.23.0
___
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[Intel-gfx] [PATCH v3 v2 2/5] drm/i915: fix port checks for MST support on gen >= 11
Both Ice Lake and Elkhart Lake (gen 11) support MST on all external
connections except DDI A. Tiger Lake (gen 12) supports on all external
connections.
Move the check to happen inside intel_dp_mst_encoder_init() and add
specific platform checks.
v2: Replace != with == checks for ports on gen < 11 (Ville)
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++--
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6594f2af1257..415d0f2c2751 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7271,11 +7271,8 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
intel_connector->get_hw_state = intel_connector_get_hw_state;
/* init MST on ports that can support it */
- if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
- (port == PORT_B || port == PORT_C ||
-port == PORT_D || port == PORT_F))
- intel_dp_mst_encoder_init(intel_dig_port,
- intel_connector->base.base.id);
+ intel_dp_mst_encoder_init(intel_dig_port,
+ intel_connector->base.base.id);
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
intel_dp_aux_fini(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2203be28ea01..ea062fea8a44 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -655,21 +655,31 @@ intel_dp_mst_encoder_active_links(struct
intel_digital_port *intel_dig_port)
int
intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int
conn_base_id)
{
+ struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
struct intel_dp *intel_dp = _dig_port->dp;
- struct drm_device *dev = intel_dig_port->base.base.dev;
+ enum port port = intel_dig_port->base.port;
int ret;
- intel_dp->can_mst = true;
+ if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
+ return 0;
+
+ if (INTEL_GEN(i915) <= 11 && port == PORT_A)
+ return 0;
+
+ if (INTEL_GEN(i915) < 11 && port == PORT_E)
+ return 0;
+
intel_dp->mst_mgr.cbs = _cbs;
/* create encoders */
intel_dp_create_fake_mst_encoders(intel_dig_port);
- ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, dev,
+ ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, >drm,
_dp->aux, 16, 3, conn_base_id);
- if (ret) {
- intel_dp->can_mst = false;
+ if (ret)
return ret;
- }
+
+ intel_dp->can_mst = true;
+
return 0;
}
--
2.23.0
___
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[Intel-gfx] [PATCH v3 v2 4/5] drm/i915: add pipe id/name to pipe mismatch logs
This way it's easier to figure out what didn't match when we have
multiple pipes enabled.
v2: pass drm_crtc and use the more common [CRTC:%d:%s] format
(Ville)
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +++-
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e71ec9d96c75..cd0f600e0205 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12526,8 +12526,9 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
}
}
-static void __printf(3, 4)
-pipe_config_mismatch(bool fastset, const char *name, const char *format, ...)
+static void __printf(4, 5)
+pipe_config_mismatch(bool fastset, const struct drm_crtc *crtc,
+const char *name, const char *format, ...)
{
struct va_format vaf;
va_list args;
@@ -12537,9 +12538,11 @@ pipe_config_mismatch(bool fastset, const char *name,
const char *format, ...)
vaf.va =
if (fastset)
- DRM_DEBUG_KMS("fastset mismatch in %s %pV\n", name, );
+ DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
+ crtc->base.id, crtc->name, name, );
else
- DRM_ERROR("mismatch in %s %pV\n", name, );
+ DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
+ crtc->base.id, crtc->name, name, );
va_end(args);
}
@@ -12567,6 +12570,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bool fastset)
{
struct drm_i915_private *dev_priv =
to_i915(current_config->base.crtc->dev);
+ const struct drm_crtc *crtc = pipe_config->base.crtc;
bool ret = true;
u32 bp_gamma = 0;
bool fixup_inherited = fastset &&
@@ -12580,7 +12584,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_X(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected 0x%08x, found 0x%08x)", \
current_config->name, \
pipe_config->name); \
@@ -12590,7 +12594,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_I(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected %i, found %i)", \
current_config->name, \
pipe_config->name); \
@@ -12600,7 +12604,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
@@ -12617,7 +12621,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (!fixup_inherited || (!current_config->name && !pipe_config->name))
{ \
PIPE_CONF_CHECK_BOOL(name); \
} else { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"unable to verify whether state matches
exactly, forcing modeset (expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
@@ -12627,7 +12631,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_P(name) do { \
if (current_config->name != pipe_config->name) { \
- pipe_config_mismatch(fastset, __stringify(name), \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
"(expected %p, found %p)", \
current_config->name, \
pipe_config->name); \
@@ -12639,7 +12643,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (!intel_compare_link_m_n(_config->name, \
_config->name,\
!fastset)) { \
-
[Intel-gfx] [PATCH v3 v2 3/5] drm/i915: remove extra new line on pipe_config mismatch
The new line is already added by pipe_config_mismatch(), so the callers
shouldn't add it.
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-5-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 22 ++--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3cf39fc153b3..e71ec9d96c75 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12581,7 +12581,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_X(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected 0x%08x, found 0x%08x)\n", \
+"(expected 0x%08x, found 0x%08x)", \
current_config->name, \
pipe_config->name); \
ret = false; \
@@ -12591,7 +12591,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_I(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected %i, found %i)\n", \
+"(expected %i, found %i)", \
current_config->name, \
pipe_config->name); \
ret = false; \
@@ -12601,7 +12601,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected %s, found %s)\n", \
+"(expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
ret = false; \
@@ -12618,7 +12618,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_BOOL(name); \
} else { \
pipe_config_mismatch(fastset, __stringify(name), \
-"unable to verify whether state matches
exactly, forcing modeset (expected %s, found %s)\n", \
+"unable to verify whether state matches
exactly, forcing modeset (expected %s, found %s)", \
yesno(current_config->name), \
yesno(pipe_config->name)); \
ret = false; \
@@ -12628,7 +12628,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_P(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, __stringify(name), \
-"(expected %p, found %p)\n", \
+"(expected %p, found %p)", \
current_config->name, \
pipe_config->name); \
ret = false; \
@@ -12641,7 +12641,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
!fastset)) { \
pipe_config_mismatch(fastset, __stringify(name), \
"(expected tu %i gmch %i/%i link %i/%i, " \
-"found tu %i, gmch %i/%i link %i/%i)\n", \
+"found tu %i, gmch %i/%i link %i/%i)", \
current_config->name.tu, \
current_config->name.gmch_m, \
current_config->name.gmch_n, \
@@ -12669,7 +12669,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
pipe_config_mismatch(fastset, __stringify(name), \
"(expected tu %i gmch %i/%i link %i/%i, " \
"or tu %i gmch %i/%i link %i/%i, " \
-"found tu %i, gmch %i/%i link %i/%i)\n", \
+"found tu %i, gmch %i/%i link %i/%i)", \
current_config->name.tu, \
current_config->name.gmch_m, \
current_config->name.gmch_n, \
@@ -12692,7 +12692,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
[Intel-gfx] [PATCH v3 v2 1/5] drm/i915: simplify setting of ddi_io_power_domain
Instead of the ever growing switch, just compute the ddi io power domain
based on the port number.
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20191011010907.103309-2-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++--
1 file changed, 3 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6c1315c7bcde..b2776f6044ae 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4750,46 +4750,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_encoder->update_complete = intel_ddi_update_complete;
}
- switch (port) {
- case PORT_A:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_A_IO;
- break;
- case PORT_B:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_B_IO;
- break;
- case PORT_C:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_C_IO;
- break;
- case PORT_D:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_D_IO;
- break;
- case PORT_E:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_E_IO;
- break;
- case PORT_F:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_F_IO;
- break;
- case PORT_G:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_G_IO;
- break;
- case PORT_H:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_H_IO;
- break;
- case PORT_I:
- intel_dig_port->ddi_io_power_domain =
- POWER_DOMAIN_PORT_DDI_I_IO;
- break;
- default:
- MISSING_CASE(port);
- }
+ WARN_ON(port > PORT_I);
+ intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
+ port - PORT_A;
if (init_dp) {
if (!intel_ddi_init_dp_connector(intel_dig_port))
--
2.23.0
___
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[Intel-gfx] [PATCH v3 v2 0/5] Small fixes before fixing MST
https://patchwork.freedesktop.org/series/67883/ v2: - remove "drm/i915: cleanup unused returns on DP-MST": we should actually care more about the error handling here - left for later - handle other comments on the series Lucas De Marchi (5): drm/i915: simplify setting of ddi_io_power_domain drm/i915: fix port checks for MST support on gen >= 11 drm/i915: remove extra new line on pipe_config mismatch drm/i915: add pipe id/name to pipe mismatch logs drm/i915: prettify MST debug message drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++- drivers/gpu/drm/i915/display/intel_display.c | 56 +++- drivers/gpu/drm/i915/display/intel_dp.c | 9 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +--- 4 files changed, 52 insertions(+), 78 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V3 1/7] mdev: class id support
On Fri, 11 Oct 2019 16:15:51 +0800
Jason Wang wrote:
> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> index b558d4cfd082..724e9b9841d8 100644
> --- a/drivers/vfio/mdev/mdev_core.c
> +++ b/drivers/vfio/mdev/mdev_core.c
> @@ -45,6 +45,12 @@ void mdev_set_drvdata(struct mdev_device *mdev, void *data)
> }
> EXPORT_SYMBOL(mdev_set_drvdata);
>
> +void mdev_set_class(struct mdev_device *mdev, u16 id)
> +{
> + mdev->class_id = id;
> +}
> +EXPORT_SYMBOL(mdev_set_class);
> +
> struct device *mdev_dev(struct mdev_device *mdev)
> {
> return >dev;
> @@ -135,6 +141,7 @@ static int mdev_device_remove_cb(struct device *dev, void
> *data)
> * mdev_register_device : Register a device
> * @dev: device structure representing parent device.
> * @ops: Parent device operation structure to be registered.
> + * @id: class id.
> *
> * Add device to list of registered parent devices.
> * Returns a negative value on error, otherwise 0.
> @@ -324,6 +331,9 @@ int mdev_device_create(struct kobject *kobj,
> if (ret)
> goto ops_create_fail;
>
> + if (!mdev->class_id)
This is a sanity test failure of the parent driver on a privileged
path, I think it's fair to print a warning when this occurs rather than
only return an errno to the user. In fact, ret is not set to an error
value here, so it looks like this fails to create the device but
returns success. Thanks,
Alex
> + goto class_id_fail;
> +
> ret = device_add(>dev);
> if (ret)
> goto add_fail;
> @@ -340,6 +350,7 @@ int mdev_device_create(struct kobject *kobj,
>
> sysfs_fail:
> device_del(>dev);
> +class_id_fail:
> add_fail:
> parent->ops->remove(mdev);
> ops_create_fail:
___
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[Intel-gfx] [PATCH v3] drm/i915: Introduce Jasper Lake PCH
The Jasper Lake PCH follows ICP/TGP's south display behavior and is
identical to MCC graphics-wise except that it does not use the unusual
(port C -> TC1) pin mapping that MCC does.
Also, it turns out the extra PCH ID that we had previously thought was a
form of MCC is actually a second ID for JSP (i.e., port C uses the port
C pins instead of the TC1 pins).
v2:
- Also update the port masks (not just the pin table) in
mcc_hpd_irq_setup. (Vivek)
v3:
- Break jsp_hpd_irq_setup out into its own function for clarity.
(Vivek)
Cc: José Roberto de Souza
Cc: James Ausmus
Cc: Vivek Kasireddy
Signed-off-by: Matt Roper
Reviewed-by: Vivek Kasireddy
---
drivers/gpu/drm/i915/i915_irq.c | 24 +++-
drivers/gpu/drm/i915/intel_pch.c | 6 +-
drivers/gpu/drm/i915/intel_pch.h | 5 -
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d20ca02d3166..448390ad2128 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2248,11 +2248,18 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
pins = hpd_tgp;
+ } else if (HAS_PCH_JSP(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ tc_hotplug_trigger = 0;
+ pins = hpd_tgp;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
pins = hpd_icp;
} else {
+ WARN(!HAS_PCH_ICP(dev_priv),
+"Unrecognized PCH type 0x%x\n", INTEL_PCH_TYPE(dev_priv));
+
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
@@ -3384,6 +3391,19 @@ static void mcc_hpd_irq_setup(struct drm_i915_private
*dev_priv)
hpd_icp);
}
+/*
+ * JSP behaves exactly the same as MCC above except that port C is mapped to
+ * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
+ * masks & tables rather than ICP's masks & tables.
+ */
+static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ icp_hpd_irq_setup(dev_priv,
+ SDE_DDI_MASK_TGP, 0,
+ TGP_DDI_HPD_ENABLE_MASK, 0,
+ hpd_tgp);
+}
+
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -4315,7 +4335,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_JSP(dev_priv))
+ dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
+ else if (HAS_PCH_MCC(dev_priv))
dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
else if (INTEL_GEN(dev_priv) >= 11)
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 15f8bff141f9..1035d3d46fd8 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -79,7 +79,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
WARN_ON(!IS_ICELAKE(dev_priv));
return PCH_ICP;
case INTEL_PCH_MCC_DEVICE_ID_TYPE:
- case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
WARN_ON(!IS_ELKHARTLAKE(dev_priv));
return PCH_MCC;
@@ -87,6 +86,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
WARN_ON(!IS_TIGERLAKE(dev_priv));
return PCH_TGP;
+ case INTEL_PCH_JSP_DEVICE_ID_TYPE:
+ case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
+ DRM_DEBUG_KMS("Found Jasper Lake PCH\n");
+ WARN_ON(!IS_ELKHARTLAKE(dev_priv));
+ return PCH_JSP;
default:
return PCH_NONE;
}
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index c29c81ec7971..f4dc18c34291 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -23,6 +23,7 @@ enum intel_pch {
PCH_SPT,/* Sunrisepoint/Kaby Lake PCH */
PCH_CNP,/* Cannon/Comet Lake PCH */
PCH_ICP,/* Ice Lake PCH */
+ PCH_JSP,/* Jasper Lake PCH */
[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support
== Series Details ==
Series: Refactor Gen11+ SAGV support
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7096 -> Patchwork_14812
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/index.html
Known issues
Here are the changes found in Patchwork_14812 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_getparams_basic@basic-eu-total:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-u3/igt@i915_getparams_ba...@basic-eu-total.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/fi-icl-u3/igt@i915_getparams_ba...@basic-eu-total.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [DMESG-FAIL][7] ([fdo#44] / [fdo#111678]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-crc-fast:
- {fi-icl-u4}:[FAIL][9] ([fdo#111045]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-snb-2520m: [FAIL][11] ([fdo#100368]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-snb-2520m/igt@kms_flip@basic-flip-vs-wf_vblank.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/fi-snb-2520m/igt@kms_flip@basic-flip-vs-wf_vblank.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#44]: https://bugs.freedesktop.org/show_bug.cgi?id=44
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7096 -> Patchwork_14812
CI-20190529: 20190529
CI_DRM_7096: 2ed00991bec362d1e5fce84b6f0863ba44b79eee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14812: 4b87f530f10818b31e1969b4357ca2ad369f8ba8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4b87f530f108 drm/i915: Restrict qgv points which don't have enough bandwidth.
248cbaf741d0 drm/i915: Refactor intel_can_enable_sagv
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14812/index.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Flush tasklet submission before sleeping on i915_request_wait
== Series Details ==
Series: drm/i915: Flush tasklet submission before sleeping on i915_request_wait
URL : https://patchwork.freedesktop.org/series/68024/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7096 -> Patchwork_14811
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14811 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14811, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14811:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14811 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_gem_contexts:
- fi-kbl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#112002])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109483])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html
Possible fixes
* igt@i915_getparams_basic@basic-eu-total:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-u3/igt@i915_getparams_ba...@basic-eu-total.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-icl-u3/igt@i915_getparams_ba...@basic-eu-total.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [DMESG-FAIL][11] ([fdo#44] / [fdo#111678]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][13] ([fdo#111600]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-snb-2520m: [FAIL][15] ([fdo#100368]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-snb-2520m/igt@kms_flip@basic-flip-vs-wf_vblank.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-snb-2520m/igt@kms_flip@basic-flip-vs-wf_vblank.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111045] / [fdo#111096]) ->
[FAIL][18] ([fdo#111407])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7096/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14811/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#44]: https://bugs.freedesktop.org/show_bug.cgi?id=44
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111678]:
[Intel-gfx] [PATCH] drm/i915/ehl: Don't forget to set TC long detect function
Since EHL's MCC PCH reuses one of the TC pins we need to supply a TC
long detect function when handling the interrupts.
Fixes: 53448aed7b80 ("drm/i915/ehl: Port C's hotplug interrupt is associated
with TC1 bits")
Reported-by: kbuild test robot
Reported-by: Dan Carpenter
Cc: Vivek Kasireddy
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a7c968b01af3..af7426cd8de9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2251,6 +2251,7 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
+ tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
pins = hpd_icp;
} else {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
--
2.21.0
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Re: [Intel-gfx] [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID
Quoting Mika Kuoppala (2019-10-15 16:44:39) > We are going to need this macro on limiting > the workaround scope. > > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_drv.h | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index c46b339064c0..f6aee1e01a7f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1686,6 +1686,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_ICL_REVID(p, since, until) \ > (IS_ICELAKE(p) && IS_REVID(p, since, until)) > > +#define TGL_REVID_A0 0x0 > + > +#define IS_TGL_REVID(p, since, until) \ > + (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/11] drm/i915/tgl: Wa_1607138340
Quoting Mika Kuoppala (2019-10-15 16:44:49) > Avoid possible cs hang with semaphores by disabling > lite restore. > > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 1ef23735c1f6..580d99d18e71 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1048,6 +1048,10 @@ static u64 execlists_update_context(const struct > i915_request *rq) > desc = ce->lrc_desc; > ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE; > > + /* Wa_1607138340:tgl */ > + if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_A0)) > + desc |= CTX_DESC_FORCE_RESTORE; This looks much more heavy handed than suggested, but for a0, I'm not fused. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/11] drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627
Quoting Mika Kuoppala (2019-10-15 16:44:48)
> Disable semaphore idle messages and wait for event
> power downs.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3bacf3d9684e..73fc168d7f60 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1281,6 +1281,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_write_or(wal,
> GEN9_CTX_PREEMPT_REG,
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> +
> + /* Wa_1607030317:tgl */
> + /* Wa_1607186500:tgl */
> + /* Wa_1607297627:tgl */
> + wa_masked_en(wal,
> +GEN6_RC_SLEEP_PSMI_CONTROL,
> +GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> +GEN8_RC_SEMA_IDLE_MSG_DISABLE);
rcs only, ack.
> }
>
> if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 19ac01057528..b50ec878a0b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2885,6 +2885,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>
> #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
> #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
> +#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE (1 << 7)
REG_BIT(7)
> #define GEN8_RC_SEMA_IDLE_MSG_DISABLE(1 << 12)
> #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH 09/11] drm/i915/tgl: Wa_1607138336
Quoting Mika Kuoppala (2019-10-15 16:44:47)
> Avoid possible deadlock on context switch.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4b7740aaf3bf..3bacf3d9684e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1276,6 +1276,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_masked_en(wal,
> GEN9_CS_DEBUG_MODE1,
> FF_DOP_CLOCK_GATE_DISABLE);
> +
> + /* Wa_1607138336:tgl */
> + wa_write_or(wal,
> + GEN9_CTX_PREEMPT_REG,
> + GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> }
>
> if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 51c3e7975d6b..19ac01057528 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7676,6 +7676,8 @@ enum {
> #define GEN9_CS_DEBUG_MODE1_MMIO(0x20ec)
>#define FF_DOP_CLOCK_GATE_DISABLEBIT(1)
> #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
> + #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG (1 << 11)
REG_BIT(11)
Reviewed-by: Chris Wilson
-Chris
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